1b2441318SGreg Kroah-Hartman/* SPDX-License-Identifier: GPL-2.0 */ 2250c2277SThomas Gleixner/* 35b171e82SAlexander Kuleshov * linux/arch/x86/kernel/head_64.S -- start in 32bit and switch to 64bit 4250c2277SThomas Gleixner * 5250c2277SThomas Gleixner * Copyright (C) 2000 Andrea Arcangeli <andrea@suse.de> SuSE 6250c2277SThomas Gleixner * Copyright (C) 2000 Pavel Machek <pavel@suse.cz> 7250c2277SThomas Gleixner * Copyright (C) 2000 Karsten Keil <kkeil@suse.de> 8250c2277SThomas Gleixner * Copyright (C) 2001,2002 Andi Kleen <ak@suse.de> 9250c2277SThomas Gleixner * Copyright (C) 2005 Eric Biederman <ebiederm@xmission.com> 10250c2277SThomas Gleixner */ 11250c2277SThomas Gleixner 12250c2277SThomas Gleixner 13250c2277SThomas Gleixner#include <linux/linkage.h> 14250c2277SThomas Gleixner#include <linux/threads.h> 15250c2277SThomas Gleixner#include <linux/init.h> 16ca5999fdSMike Rapoport#include <linux/pgtable.h> 1765fddcfcSMike Rapoport#include <asm/segment.h> 18250c2277SThomas Gleixner#include <asm/page.h> 19250c2277SThomas Gleixner#include <asm/msr.h> 20250c2277SThomas Gleixner#include <asm/cache.h> 21369101daSCyrill Gorcunov#include <asm/processor-flags.h> 22b12d8db8STejun Heo#include <asm/percpu.h> 239900aa2fSH. Peter Anvin#include <asm/nops.h> 247bbcdb1cSAndy Lutomirski#include "../entry/calling.h" 25784d5699SAl Viro#include <asm/export.h> 26bd89004fSPeter Zijlstra#include <asm/nospec-branch.h> 277e75178aSDavid Woodhouse#include <asm/apicdef.h> 2805ab1d8aSFeng Tang#include <asm/fixmap.h> 297e75178aSDavid Woodhouse#include <asm/smp.h> 30250c2277SThomas Gleixner 3175da04f7SThomas Gleixner/* 3275da04f7SThomas Gleixner * We are not able to switch in one step to the final KERNEL ADDRESS SPACE 33250c2277SThomas Gleixner * because we need identity-mapped pages. 34250c2277SThomas Gleixner */ 35b9952ec7SKirill A. Shutemov#define l4_index(x) (((x) >> 39) & 511) 36a6523748SEduardo Habkost#define pud_index(x) (((x) >> PUD_SHIFT) & (PTRS_PER_PUD-1)) 37a6523748SEduardo Habkost 38b9952ec7SKirill A. ShutemovL4_PAGE_OFFSET = l4_index(__PAGE_OFFSET_BASE_L4) 39b9952ec7SKirill A. ShutemovL4_START_KERNEL = l4_index(__START_KERNEL_map) 40b9952ec7SKirill A. Shutemov 41a6523748SEduardo HabkostL3_START_KERNEL = pud_index(__START_KERNEL_map) 42a6523748SEduardo Habkost 43250c2277SThomas Gleixner .text 444ae59b91STim Abbott __HEAD 45250c2277SThomas Gleixner .code64 4637818afdSJiri SlabySYM_CODE_START_NOALIGN(startup_64) 47fb799447SJosh Poimboeuf UNWIND_HINT_END_OF_STACK 48250c2277SThomas Gleixner /* 491256276cSKonrad Rzeszutek Wilk * At this point the CPU runs in 64bit mode CS.L = 1 CS.D = 0, 50250c2277SThomas Gleixner * and someone has loaded an identity mapped page table 51250c2277SThomas Gleixner * for us. These identity mapped page tables map all of the 52250c2277SThomas Gleixner * kernel pages and possibly all of memory. 53250c2277SThomas Gleixner * 542f69a81aSArd Biesheuvel * %RSI holds the physical address of the boot_params structure 552f69a81aSArd Biesheuvel * provided by the bootloader. Preserve it in %R15 so C function calls 562f69a81aSArd Biesheuvel * will not clobber it. 57250c2277SThomas Gleixner * 58250c2277SThomas Gleixner * We come here either directly from a 64bit bootloader, or from 595b171e82SAlexander Kuleshov * arch/x86/boot/compressed/head_64.S. 60250c2277SThomas Gleixner * 61250c2277SThomas Gleixner * We only come here initially at boot nothing else comes here. 62250c2277SThomas Gleixner * 63250c2277SThomas Gleixner * Since we may be loaded at an address different from what we were 64250c2277SThomas Gleixner * compiled to run at we first fixup the physical addresses in our page 65250c2277SThomas Gleixner * tables and then reload them. 66250c2277SThomas Gleixner */ 672f69a81aSArd Biesheuvel mov %rsi, %r15 68250c2277SThomas Gleixner 693adee777SBrian Gerst /* Set up the stack for verify_cpu() */ 703adee777SBrian Gerst leaq (__end_init_task - PTREGS_SIZE)(%rip), %rsp 7191ed140dSBorislav Petkov 72866b556eSJoerg Roedel leaq _text(%rip), %rdi 73469693d8SMichael Roth 748f6be6d8SBrian Gerst /* Setup GSBASE to allow stack canary access for C code */ 75469693d8SMichael Roth movl $MSR_GS_BASE, %ecx 768f6be6d8SBrian Gerst leaq INIT_PER_CPU_VAR(fixed_percpu_data)(%rip), %rdx 778f6be6d8SBrian Gerst movl %edx, %eax 78469693d8SMichael Roth shrq $32, %rdx 79469693d8SMichael Roth wrmsr 80469693d8SMichael Roth 81866b556eSJoerg Roedel call startup_64_setup_env 82866b556eSJoerg Roedel 83a37f2699STom Lendacky /* Now switch to __KERNEL_CS so IRET works reliably */ 84a37f2699STom Lendacky pushq $__KERNEL_CS 85a37f2699STom Lendacky leaq .Lon_kernel_cs(%rip), %rax 86a37f2699STom Lendacky pushq %rax 87a37f2699STom Lendacky lretq 88a37f2699STom Lendacky 89a37f2699STom Lendacky.Lon_kernel_cs: 90a37f2699STom Lendacky UNWIND_HINT_END_OF_STACK 91a37f2699STom Lendacky 92bcce8290SMichael Roth#ifdef CONFIG_AMD_MEM_ENCRYPT 93bcce8290SMichael Roth /* 94bcce8290SMichael Roth * Activate SEV/SME memory encryption if supported/enabled. This needs to 95bcce8290SMichael Roth * be done now, since this also includes setup of the SEV-SNP CPUID table, 96bcce8290SMichael Roth * which needs to be done before any CPUID instructions are executed in 972f69a81aSArd Biesheuvel * subsequent code. Pass the boot_params pointer as the first argument. 98bcce8290SMichael Roth */ 992f69a81aSArd Biesheuvel movq %r15, %rdi 100bcce8290SMichael Roth call sme_enable 101bcce8290SMichael Roth#endif 102bcce8290SMichael Roth 10304633df0SBorislav Petkov /* Sanitize CPU configuration */ 10404633df0SBorislav Petkov call verify_cpu 10504633df0SBorislav Petkov 1065868f365STom Lendacky /* 1075868f365STom Lendacky * Perform pagetable fixups. Additionally, if SME is active, encrypt 1085868f365STom Lendacky * the kernel and retrieve the modifier (SME encryption mask if SME 1095868f365STom Lendacky * is active) to be added to the initial pgdir entry that will be 1105868f365STom Lendacky * programmed into CR3. 1115868f365STom Lendacky */ 112250c2277SThomas Gleixner leaq _text(%rip), %rdi 1132f69a81aSArd Biesheuvel movq %r15, %rsi 114c88d7150SKirill A. Shutemov call __startup_64 115250c2277SThomas Gleixner 1165868f365STom Lendacky /* Form the CR3 value being sure to include the CR3 modifier */ 1175868f365STom Lendacky addq $(early_top_pgt - __START_KERNEL_map), %rax 1188170e6beSH. Peter Anvin jmp 1f 11937818afdSJiri SlabySYM_CODE_END(startup_64) 12037818afdSJiri Slaby 121bc7b11c0SJiri SlabySYM_CODE_START(secondary_startup_64) 122fb799447SJosh Poimboeuf UNWIND_HINT_END_OF_STACK 1233e3f0695SPeter Zijlstra ANNOTATE_NOENDBR 124250c2277SThomas Gleixner /* 1251256276cSKonrad Rzeszutek Wilk * At this point the CPU runs in 64bit mode CS.L = 1 CS.D = 0, 126250c2277SThomas Gleixner * and someone has loaded a mapped page table. 127250c2277SThomas Gleixner * 128250c2277SThomas Gleixner * We come here either from startup_64 (using physical addresses) 129250c2277SThomas Gleixner * or from trampoline.S (using virtual addresses). 130250c2277SThomas Gleixner * 131250c2277SThomas Gleixner * Using virtual addresses from trampoline.S removes the need 132250c2277SThomas Gleixner * to have any identity mapped pages in the kernel page table 133250c2277SThomas Gleixner * after the boot processor executes this code. 134250c2277SThomas Gleixner */ 135250c2277SThomas Gleixner 13604633df0SBorislav Petkov /* Sanitize CPU configuration */ 13704633df0SBorislav Petkov call verify_cpu 13804633df0SBorislav Petkov 1395868f365STom Lendacky /* 1403ecacdbdSJoerg Roedel * The secondary_startup_64_no_verify entry point is only used by 1413ecacdbdSJoerg Roedel * SEV-ES guests. In those guests the call to verify_cpu() would cause 1423ecacdbdSJoerg Roedel * #VC exceptions which can not be handled at this stage of secondary 1433ecacdbdSJoerg Roedel * CPU bringup. 1443ecacdbdSJoerg Roedel * 1453ecacdbdSJoerg Roedel * All non SEV-ES systems, especially Intel systems, need to execute 1463ecacdbdSJoerg Roedel * verify_cpu() above to make sure NX is enabled. 1473ecacdbdSJoerg Roedel */ 1483ecacdbdSJoerg RoedelSYM_INNER_LABEL(secondary_startup_64_no_verify, SYM_L_GLOBAL) 149fb799447SJosh Poimboeuf UNWIND_HINT_END_OF_STACK 1503e3f0695SPeter Zijlstra ANNOTATE_NOENDBR 1513ecacdbdSJoerg Roedel 1522f69a81aSArd Biesheuvel /* Clear %R15 which holds the boot_params pointer on the boot CPU */ 1532f69a81aSArd Biesheuvel xorq %r15, %r15 1542f69a81aSArd Biesheuvel 1553ecacdbdSJoerg Roedel /* 1565868f365STom Lendacky * Retrieve the modifier (SME encryption mask if SME is active) to be 1575868f365STom Lendacky * added to the initial pgdir entry that will be programmed into CR3. 1585868f365STom Lendacky */ 159469693d8SMichael Roth#ifdef CONFIG_AMD_MEM_ENCRYPT 160469693d8SMichael Roth movq sme_me_mask, %rax 161469693d8SMichael Roth#else 162469693d8SMichael Roth xorq %rax, %rax 163469693d8SMichael Roth#endif 1645868f365STom Lendacky 1655868f365STom Lendacky /* Form the CR3 value being sure to include the CR3 modifier */ 1665868f365STom Lendacky addq $(init_top_pgt - __START_KERNEL_map), %rax 1678170e6beSH. Peter Anvin1: 1688170e6beSH. Peter Anvin 16977a512e3SSean Christopherson#ifdef CONFIG_X86_MCE 17077a512e3SSean Christopherson /* 17177a512e3SSean Christopherson * Preserve CR4.MCE if the kernel will enable #MC support. 17277a512e3SSean Christopherson * Clearing MCE may fault in some environments (that also force #MC 17377a512e3SSean Christopherson * support). Any machine check that occurs before #MC support is fully 17477a512e3SSean Christopherson * configured will crash the system regardless of the CR4.MCE value set 17577a512e3SSean Christopherson * here. 17677a512e3SSean Christopherson */ 17777a512e3SSean Christopherson movq %cr4, %rcx 17877a512e3SSean Christopherson andl $X86_CR4_MCE, %ecx 17977a512e3SSean Christopherson#else 18077a512e3SSean Christopherson movl $0, %ecx 18177a512e3SSean Christopherson#endif 18277a512e3SSean Christopherson 183032370b9SKirill A. Shutemov /* Enable PAE mode, PGE and LA57 */ 18477a512e3SSean Christopherson orl $(X86_CR4_PAE | X86_CR4_PGE), %ecx 185032370b9SKirill A. Shutemov#ifdef CONFIG_X86_5LEVEL 18639b95522SKirill A. Shutemov testl $1, __pgtable_l5_enabled(%rip) 1876f9dd329SKirill A. Shutemov jz 1f 188032370b9SKirill A. Shutemov orl $X86_CR4_LA57, %ecx 1896f9dd329SKirill A. Shutemov1: 190032370b9SKirill A. Shutemov#endif 1918170e6beSH. Peter Anvin movq %rcx, %cr4 192250c2277SThomas Gleixner 193032370b9SKirill A. Shutemov /* Setup early boot stage 4-/5-level pagetables. */ 194250c2277SThomas Gleixner addq phys_base(%rip), %rax 195c9f09539SJoerg Roedel 196c9f09539SJoerg Roedel /* 197c9f09539SJoerg Roedel * For SEV guests: Verify that the C-bit is correct. A malicious 198c9f09539SJoerg Roedel * hypervisor could lie about the C-bit position to perform a ROP 199c9f09539SJoerg Roedel * attack on the guest by writing to the unencrypted stack and wait for 200c9f09539SJoerg Roedel * the next RET instruction. 201c9f09539SJoerg Roedel */ 202c9f09539SJoerg Roedel movq %rax, %rdi 203c9f09539SJoerg Roedel call sev_verify_cbit 204c9f09539SJoerg Roedel 205f154f290SJoerg Roedel /* 206f154f290SJoerg Roedel * Switch to new page-table 207f154f290SJoerg Roedel * 208f154f290SJoerg Roedel * For the boot CPU this switches to early_top_pgt which still has the 209f154f290SJoerg Roedel * indentity mappings present. The secondary CPUs will switch to the 210f154f290SJoerg Roedel * init_top_pgt here, away from the trampoline_pgd and unmap the 211f154f290SJoerg Roedel * indentity mapped ranges. 212f154f290SJoerg Roedel */ 213250c2277SThomas Gleixner movq %rax, %cr3 214250c2277SThomas Gleixner 215f154f290SJoerg Roedel /* 216f154f290SJoerg Roedel * Do a global TLB flush after the CR3 switch to make sure the TLB 217f154f290SJoerg Roedel * entries from the identity mapping are flushed. 218f154f290SJoerg Roedel */ 219f154f290SJoerg Roedel movq %cr4, %rcx 220f154f290SJoerg Roedel movq %rcx, %rax 221f154f290SJoerg Roedel xorq $X86_CR4_PGE, %rcx 222f154f290SJoerg Roedel movq %rcx, %cr4 223f154f290SJoerg Roedel movq %rax, %cr4 224f154f290SJoerg Roedel 225250c2277SThomas Gleixner /* Ensure I am executing from virtual addresses */ 226250c2277SThomas Gleixner movq $1f, %rax 227bd89004fSPeter Zijlstra ANNOTATE_RETPOLINE_SAFE 228250c2277SThomas Gleixner jmp *%rax 229250c2277SThomas Gleixner1: 230fb799447SJosh Poimboeuf UNWIND_HINT_END_OF_STACK 2313e3f0695SPeter Zijlstra ANNOTATE_NOENDBR // above 232250c2277SThomas Gleixner 2333adee777SBrian Gerst#ifdef CONFIG_SMP 2347e75178aSDavid Woodhouse /* 2357e75178aSDavid Woodhouse * For parallel boot, the APIC ID is read from the APIC, and then 2367e75178aSDavid Woodhouse * used to look up the CPU number. For booting a single CPU, the 2377e75178aSDavid Woodhouse * CPU number is encoded in smpboot_control. 2387e75178aSDavid Woodhouse * 2397e75178aSDavid Woodhouse * Bit 31 STARTUP_READ_APICID (Read APICID from APIC) 2407e75178aSDavid Woodhouse * Bit 0-23 CPU# if STARTUP_xx flags are not set 2417e75178aSDavid Woodhouse */ 2423adee777SBrian Gerst movl smpboot_control(%rip), %ecx 2437e75178aSDavid Woodhouse testl $STARTUP_READ_APICID, %ecx 2447e75178aSDavid Woodhouse jnz .Lread_apicid 2457e75178aSDavid Woodhouse /* 2467e75178aSDavid Woodhouse * No control bit set, single CPU bringup. CPU number is provided 2477e75178aSDavid Woodhouse * in bit 0-23. This is also the boot CPU case (CPU number 0). 2487e75178aSDavid Woodhouse */ 2497e75178aSDavid Woodhouse andl $(~STARTUP_PARALLEL_MASK), %ecx 2507e75178aSDavid Woodhouse jmp .Lsetup_cpu 2513adee777SBrian Gerst 2527e75178aSDavid Woodhouse.Lread_apicid: 2537e75178aSDavid Woodhouse /* Check whether X2APIC mode is already enabled */ 2547e75178aSDavid Woodhouse mov $MSR_IA32_APICBASE, %ecx 2557e75178aSDavid Woodhouse rdmsr 2567e75178aSDavid Woodhouse testl $X2APIC_ENABLE, %eax 2577e75178aSDavid Woodhouse jnz .Lread_apicid_msr 2587e75178aSDavid Woodhouse 259*ddc4ad52SThomas Gleixner#ifdef CONFIG_X86_X2APIC 260*ddc4ad52SThomas Gleixner /* 261*ddc4ad52SThomas Gleixner * If system is in X2APIC mode then MMIO base might not be 262*ddc4ad52SThomas Gleixner * mapped causing the MMIO read below to fault. Faults can't 263*ddc4ad52SThomas Gleixner * be handled at that point. 264*ddc4ad52SThomas Gleixner */ 265*ddc4ad52SThomas Gleixner cmpl $0, x2apic_mode(%rip) 266*ddc4ad52SThomas Gleixner jz .Lread_apicid_mmio 267*ddc4ad52SThomas Gleixner 268*ddc4ad52SThomas Gleixner /* Force the AP into X2APIC mode. */ 269*ddc4ad52SThomas Gleixner orl $X2APIC_ENABLE, %eax 270*ddc4ad52SThomas Gleixner wrmsr 271*ddc4ad52SThomas Gleixner jmp .Lread_apicid_msr 272*ddc4ad52SThomas Gleixner#endif 273*ddc4ad52SThomas Gleixner 274*ddc4ad52SThomas Gleixner.Lread_apicid_mmio: 2757e75178aSDavid Woodhouse /* Read the APIC ID from the fix-mapped MMIO space. */ 2767e75178aSDavid Woodhouse movq apic_mmio_base(%rip), %rcx 2777e75178aSDavid Woodhouse addq $APIC_ID, %rcx 2787e75178aSDavid Woodhouse movl (%rcx), %eax 2797e75178aSDavid Woodhouse shr $24, %eax 2807e75178aSDavid Woodhouse jmp .Llookup_AP 2817e75178aSDavid Woodhouse 2827e75178aSDavid Woodhouse.Lread_apicid_msr: 2837e75178aSDavid Woodhouse mov $APIC_X2APIC_ID_MSR, %ecx 2847e75178aSDavid Woodhouse rdmsr 2857e75178aSDavid Woodhouse 2867e75178aSDavid Woodhouse.Llookup_AP: 2877e75178aSDavid Woodhouse /* EAX contains the APIC ID of the current CPU */ 2887e75178aSDavid Woodhouse xorq %rcx, %rcx 2897e75178aSDavid Woodhouse leaq cpuid_to_apicid(%rip), %rbx 2907e75178aSDavid Woodhouse 2917e75178aSDavid Woodhouse.Lfind_cpunr: 2927e75178aSDavid Woodhouse cmpl (%rbx,%rcx,4), %eax 2937e75178aSDavid Woodhouse jz .Lsetup_cpu 2947e75178aSDavid Woodhouse inc %ecx 2957e75178aSDavid Woodhouse#ifdef CONFIG_FORCE_NR_CPUS 2967e75178aSDavid Woodhouse cmpl $NR_CPUS, %ecx 2977e75178aSDavid Woodhouse#else 2987e75178aSDavid Woodhouse cmpl nr_cpu_ids(%rip), %ecx 2997e75178aSDavid Woodhouse#endif 3007e75178aSDavid Woodhouse jb .Lfind_cpunr 3017e75178aSDavid Woodhouse 3027e75178aSDavid Woodhouse /* APIC ID not found in the table. Drop the trampoline lock and bail. */ 3037e75178aSDavid Woodhouse movq trampoline_lock(%rip), %rax 3047e75178aSDavid Woodhouse movl $0, (%rax) 3057e75178aSDavid Woodhouse 3067e75178aSDavid Woodhouse1: cli 3077e75178aSDavid Woodhouse hlt 3087e75178aSDavid Woodhouse jmp 1b 3097e75178aSDavid Woodhouse 3107e75178aSDavid Woodhouse.Lsetup_cpu: 3113adee777SBrian Gerst /* Get the per cpu offset for the given CPU# which is in ECX */ 3123adee777SBrian Gerst movq __per_cpu_offset(,%rcx,8), %rdx 3133adee777SBrian Gerst#else 3143adee777SBrian Gerst xorl %edx, %edx /* zero-extended to clear all of RDX */ 3153adee777SBrian Gerst#endif /* CONFIG_SMP */ 3163adee777SBrian Gerst 3173adee777SBrian Gerst /* 3183adee777SBrian Gerst * Setup a boot time stack - Any secondary CPU will have lost its stack 3193adee777SBrian Gerst * by now because the cr3-switch above unmaps the real-mode stack. 3203adee777SBrian Gerst * 3213adee777SBrian Gerst * RDX contains the per-cpu offset 3223adee777SBrian Gerst */ 3233adee777SBrian Gerst movq pcpu_hot + X86_current_task(%rdx), %rax 3243adee777SBrian Gerst movq TASK_threadsp(%rax), %rsp 3253adee777SBrian Gerst 326e04b8833SJoerg Roedel /* 327f6f1ae91SThomas Gleixner * Now that this CPU is running on its own stack, drop the realmode 328f6f1ae91SThomas Gleixner * protection. For the boot CPU the pointer is NULL! 329f6f1ae91SThomas Gleixner */ 330f6f1ae91SThomas Gleixner movq trampoline_lock(%rip), %rax 331f6f1ae91SThomas Gleixner testq %rax, %rax 332f6f1ae91SThomas Gleixner jz .Lsetup_gdt 333f6f1ae91SThomas Gleixner movl $0, (%rax) 334f6f1ae91SThomas Gleixner 335f6f1ae91SThomas Gleixner.Lsetup_gdt: 336f6f1ae91SThomas Gleixner /* 337e04b8833SJoerg Roedel * We must switch to a new descriptor in kernel space for the GDT 338e04b8833SJoerg Roedel * because soon the kernel won't have access anymore to the userspace 339e04b8833SJoerg Roedel * addresses where we're currently running on. We have to do that here 340e04b8833SJoerg Roedel * because in 32bit we couldn't load a 64bit linear address. 341e04b8833SJoerg Roedel */ 342c253b640SBrian Gerst subq $16, %rsp 343c253b640SBrian Gerst movw $(GDT_SIZE-1), (%rsp) 344c253b640SBrian Gerst leaq gdt_page(%rdx), %rax 345c253b640SBrian Gerst movq %rax, 2(%rsp) 346c253b640SBrian Gerst lgdt (%rsp) 347c253b640SBrian Gerst addq $16, %rsp 348e04b8833SJoerg Roedel 3497b99819dSJoerg Roedel /* set up data segments */ 3507b99819dSJoerg Roedel xorl %eax,%eax 3517b99819dSJoerg Roedel movl %eax,%ds 3527b99819dSJoerg Roedel movl %eax,%ss 3537b99819dSJoerg Roedel movl %eax,%es 3547b99819dSJoerg Roedel 3557b99819dSJoerg Roedel /* 3567b99819dSJoerg Roedel * We don't really need to load %fs or %gs, but load them anyway 3577b99819dSJoerg Roedel * to kill any stale realmode selectors. This allows execution 3587b99819dSJoerg Roedel * under VT hardware. 3597b99819dSJoerg Roedel */ 3607b99819dSJoerg Roedel movl %eax,%fs 3617b99819dSJoerg Roedel movl %eax,%gs 3627b99819dSJoerg Roedel 3637b99819dSJoerg Roedel /* Set up %gs. 3647b99819dSJoerg Roedel * 3657b99819dSJoerg Roedel * The base of %gs always points to fixed_percpu_data. If the 3667b99819dSJoerg Roedel * stack protector canary is enabled, it is located at %gs:40. 3677b99819dSJoerg Roedel * Note that, on SMP, the boot cpu uses init data section until 3687b99819dSJoerg Roedel * the per cpu areas are set up. 3697b99819dSJoerg Roedel */ 3707b99819dSJoerg Roedel movl $MSR_GS_BASE,%ecx 3718f6be6d8SBrian Gerst#ifndef CONFIG_SMP 3728f6be6d8SBrian Gerst leaq INIT_PER_CPU_VAR(fixed_percpu_data)(%rip), %rdx 3738f6be6d8SBrian Gerst#endif 3748f6be6d8SBrian Gerst movl %edx, %eax 3758f6be6d8SBrian Gerst shrq $32, %rdx 3767b99819dSJoerg Roedel wrmsr 3777b99819dSJoerg Roedel 378f5963ba7SJoerg Roedel /* Setup and Load IDT */ 379f5963ba7SJoerg Roedel call early_setup_idt 380f5963ba7SJoerg Roedel 381250c2277SThomas Gleixner /* Check if nx is implemented */ 382250c2277SThomas Gleixner movl $0x80000001, %eax 383250c2277SThomas Gleixner cpuid 384250c2277SThomas Gleixner movl %edx,%edi 385250c2277SThomas Gleixner 386250c2277SThomas Gleixner /* Setup EFER (Extended Feature Enable Register) */ 387250c2277SThomas Gleixner movl $MSR_EFER, %ecx 388250c2277SThomas Gleixner rdmsr 38977a512e3SSean Christopherson /* 39077a512e3SSean Christopherson * Preserve current value of EFER for comparison and to skip 39177a512e3SSean Christopherson * EFER writes if no change was made (for TDX guest) 39277a512e3SSean Christopherson */ 39377a512e3SSean Christopherson movl %eax, %edx 394250c2277SThomas Gleixner btsl $_EFER_SCE, %eax /* Enable System Call */ 395250c2277SThomas Gleixner btl $20,%edi /* No Execute supported? */ 396250c2277SThomas Gleixner jnc 1f 397250c2277SThomas Gleixner btsl $_EFER_NX, %eax 39878d77df7SH. Peter Anvin btsq $_PAGE_BIT_NX,early_pmd_flags(%rip) 399250c2277SThomas Gleixner 40077a512e3SSean Christopherson /* Avoid writing EFER if no change was made (for TDX guest) */ 40177a512e3SSean Christopherson1: cmpl %edx, %eax 40277a512e3SSean Christopherson je 1f 40377a512e3SSean Christopherson xor %edx, %edx 40477a512e3SSean Christopherson wrmsr /* Make changes effective */ 40577a512e3SSean Christopherson1: 406250c2277SThomas Gleixner /* Setup cr0 */ 407369101daSCyrill Gorcunov movl $CR0_STATE, %eax 408250c2277SThomas Gleixner /* Make changes effective */ 409250c2277SThomas Gleixner movq %rax, %cr0 410250c2277SThomas Gleixner 411250c2277SThomas Gleixner /* zero EFLAGS after setting rsp */ 412250c2277SThomas Gleixner pushq $0 413250c2277SThomas Gleixner popfq 414250c2277SThomas Gleixner 4152f69a81aSArd Biesheuvel /* Pass the boot_params pointer as first argument */ 4162f69a81aSArd Biesheuvel movq %r15, %rdi 417250c2277SThomas Gleixner 41879d243a0SBorislav Petkov.Ljump_to_C_code: 419a9468df5SJosh Poimboeuf /* 420a9468df5SJosh Poimboeuf * Jump to run C code and to be on a real kernel address. 421250c2277SThomas Gleixner * Since we are running on identity-mapped space we have to jump 422250c2277SThomas Gleixner * to the full 64bit address, this is only possible as indirect 423250c2277SThomas Gleixner * jump. In addition we need to ensure %cs is set so we make this 424250c2277SThomas Gleixner * a far return. 4258170e6beSH. Peter Anvin * 4268170e6beSH. Peter Anvin * Note: do not change to far jump indirect with 64bit offset. 4278170e6beSH. Peter Anvin * 4288170e6beSH. Peter Anvin * AMD does not support far jump indirect with 64bit offset. 4298170e6beSH. Peter Anvin * AMD64 Architecture Programmer's Manual, Volume 3: states only 4308170e6beSH. Peter Anvin * JMP FAR mem16:16 FF /5 Far jump indirect, 4318170e6beSH. Peter Anvin * with the target specified by a far pointer in memory. 4328170e6beSH. Peter Anvin * JMP FAR mem16:32 FF /5 Far jump indirect, 4338170e6beSH. Peter Anvin * with the target specified by a far pointer in memory. 4348170e6beSH. Peter Anvin * 4358170e6beSH. Peter Anvin * Intel64 does support 64bit offset. 4368170e6beSH. Peter Anvin * Software Developer Manual Vol 2: states: 4378170e6beSH. Peter Anvin * FF /5 JMP m16:16 Jump far, absolute indirect, 4388170e6beSH. Peter Anvin * address given in m16:16 4398170e6beSH. Peter Anvin * FF /5 JMP m16:32 Jump far, absolute indirect, 4408170e6beSH. Peter Anvin * address given in m16:32. 4418170e6beSH. Peter Anvin * REX.W + FF /5 JMP m16:64 Jump far, absolute indirect, 4428170e6beSH. Peter Anvin * address given in m16:64. 443250c2277SThomas Gleixner */ 44431dcfec1SJosh Poimboeuf pushq $.Lafter_lret # put return address on stack for unwinder 445a7bea830SJan Beulich xorl %ebp, %ebp # clear frame pointer 446250c2277SThomas Gleixner movq initial_code(%rip), %rax 447250c2277SThomas Gleixner pushq $__KERNEL_CS # set correct cs 448250c2277SThomas Gleixner pushq %rax # target address in negative space 449250c2277SThomas Gleixner lretq 45031dcfec1SJosh Poimboeuf.Lafter_lret: 4513e3f0695SPeter Zijlstra ANNOTATE_NOENDBR 452bc7b11c0SJiri SlabySYM_CODE_END(secondary_startup_64) 453250c2277SThomas Gleixner 45404633df0SBorislav Petkov#include "verify_cpu.S" 455c9f09539SJoerg Roedel#include "sev_verify_cbit.S" 45604633df0SBorislav Petkov 457cded3679SThomas Gleixner#if defined(CONFIG_HOTPLUG_CPU) && defined(CONFIG_AMD_MEM_ENCRYPT) 45842e78e97SFenghua Yu/* 459666e1156SThomas Gleixner * Entry point for soft restart of a CPU. Invoked from xxx_play_dead() for 460666e1156SThomas Gleixner * restarting the boot CPU or for restarting SEV guest CPUs after CPU hot 461666e1156SThomas Gleixner * unplug. Everything is set up already except the stack. 46242e78e97SFenghua Yu */ 463666e1156SThomas GleixnerSYM_CODE_START(soft_restart_cpu) 464e81dc127SThomas Gleixner ANNOTATE_NOENDBR 465fb799447SJosh Poimboeuf UNWIND_HINT_END_OF_STACK 4663adee777SBrian Gerst 4673adee777SBrian Gerst /* Find the idle task stack */ 4683adee777SBrian Gerst movq PER_CPU_VAR(pcpu_hot) + X86_current_task, %rcx 4693adee777SBrian Gerst movq TASK_threadsp(%rcx), %rsp 4703adee777SBrian Gerst 47179d243a0SBorislav Petkov jmp .Ljump_to_C_code 472666e1156SThomas GleixnerSYM_CODE_END(soft_restart_cpu) 47342e78e97SFenghua Yu#endif 47442e78e97SFenghua Yu 4751aa9aa8eSJoerg Roedel#ifdef CONFIG_AMD_MEM_ENCRYPT 4761aa9aa8eSJoerg Roedel/* 4771aa9aa8eSJoerg Roedel * VC Exception handler used during early boot when running on kernel 4781aa9aa8eSJoerg Roedel * addresses, but before the switch to the idt_table can be made. 4791aa9aa8eSJoerg Roedel * The early_idt_handler_array can't be used here because it calls into a lot 4801aa9aa8eSJoerg Roedel * of __init code and this handler is also used during CPU offlining/onlining. 4811aa9aa8eSJoerg Roedel * Therefore this handler ends up in the .text section so that it stays around 4821aa9aa8eSJoerg Roedel * when .init.text is freed. 4831aa9aa8eSJoerg Roedel */ 4841aa9aa8eSJoerg RoedelSYM_CODE_START_NOALIGN(vc_boot_ghcb) 4851aa9aa8eSJoerg Roedel UNWIND_HINT_IRET_REGS offset=8 486e8d61bdfSPeter Zijlstra ENDBR 4871aa9aa8eSJoerg Roedel 4881aa9aa8eSJoerg Roedel /* Build pt_regs */ 4891aa9aa8eSJoerg Roedel PUSH_AND_CLEAR_REGS 4901aa9aa8eSJoerg Roedel 4911aa9aa8eSJoerg Roedel /* Call C handler */ 4921aa9aa8eSJoerg Roedel movq %rsp, %rdi 4931aa9aa8eSJoerg Roedel movq ORIG_RAX(%rsp), %rsi 4941aa9aa8eSJoerg Roedel movq initial_vc_handler(%rip), %rax 4951aa9aa8eSJoerg Roedel ANNOTATE_RETPOLINE_SAFE 4961aa9aa8eSJoerg Roedel call *%rax 4971aa9aa8eSJoerg Roedel 4981aa9aa8eSJoerg Roedel /* Unwind pt_regs */ 4991aa9aa8eSJoerg Roedel POP_REGS 5001aa9aa8eSJoerg Roedel 5011aa9aa8eSJoerg Roedel /* Remove Error Code */ 5021aa9aa8eSJoerg Roedel addq $8, %rsp 5031aa9aa8eSJoerg Roedel 5041aa9aa8eSJoerg Roedel iretq 5051aa9aa8eSJoerg RoedelSYM_CODE_END(vc_boot_ghcb) 5061aa9aa8eSJoerg Roedel#endif 5071aa9aa8eSJoerg Roedel 508b32f96c7SJosh Poimboeuf /* Both SMP bootup and ACPI suspend change these variables */ 509da5968aeSSam Ravnborg __REFDATA 5108170e6beSH. Peter Anvin .balign 8 511b1bd27b9SJiri SlabySYM_DATA(initial_code, .quad x86_64_start_kernel) 5121aa9aa8eSJoerg Roedel#ifdef CONFIG_AMD_MEM_ENCRYPT 5131aa9aa8eSJoerg RoedelSYM_DATA(initial_vc_handler, .quad handle_vc_boot_ghcb) 5141aa9aa8eSJoerg Roedel#endif 515f6f1ae91SThomas Gleixner 516f6f1ae91SThomas GleixnerSYM_DATA(trampoline_lock, .quad 0); 517b9af7c0dSSuresh Siddha __FINITDATA 518250c2277SThomas Gleixner 5198170e6beSH. Peter Anvin __INIT 520bc7b11c0SJiri SlabySYM_CODE_START(early_idt_handler_array) 521749c970aSAndi Kleen i = 0 522749c970aSAndi Kleen .rept NUM_EXCEPTION_VECTORS 52382c62fa0SJosh Poimboeuf .if ((EXCEPTION_ERRCODE_MASK >> i) & 1) == 0 5242704fbb6SJosh Poimboeuf UNWIND_HINT_IRET_REGS 5258f93402bSPeter Zijlstra ENDBR 5269900aa2fSH. Peter Anvin pushq $0 # Dummy error code, to make stack frame uniform 5272704fbb6SJosh Poimboeuf .else 5282704fbb6SJosh Poimboeuf UNWIND_HINT_IRET_REGS offset=8 5298f93402bSPeter Zijlstra ENDBR 5309900aa2fSH. Peter Anvin .endif 5319900aa2fSH. Peter Anvin pushq $i # 72(%rsp) Vector number 532cdeb6048SAndy Lutomirski jmp early_idt_handler_common 5332704fbb6SJosh Poimboeuf UNWIND_HINT_IRET_REGS 534749c970aSAndi Kleen i = i + 1 535cdeb6048SAndy Lutomirski .fill early_idt_handler_array + i*EARLY_IDT_HANDLER_SIZE - ., 1, 0xcc 536749c970aSAndi Kleen .endr 537bc7b11c0SJiri SlabySYM_CODE_END(early_idt_handler_array) 5385b2fc515SPeter Zijlstra ANNOTATE_NOENDBR // early_idt_handler_array[NUM_EXCEPTION_VECTORS] 5398866cd9dSRoland McGrath 540ef77e688SJiri SlabySYM_CODE_START_LOCAL(early_idt_handler_common) 5418f93402bSPeter Zijlstra UNWIND_HINT_IRET_REGS offset=16 542cdeb6048SAndy Lutomirski /* 543cdeb6048SAndy Lutomirski * The stack is the hardware frame, an error code or zero, and the 544cdeb6048SAndy Lutomirski * vector number. 545cdeb6048SAndy Lutomirski */ 5469900aa2fSH. Peter Anvin cld 5479900aa2fSH. Peter Anvin 548250c2277SThomas Gleixner incl early_recursion_flag(%rip) 5499900aa2fSH. Peter Anvin 5507bbcdb1cSAndy Lutomirski /* The vector number is currently in the pt_regs->di slot. */ 5517bbcdb1cSAndy Lutomirski pushq %rsi /* pt_regs->si */ 5527bbcdb1cSAndy Lutomirski movq 8(%rsp), %rsi /* RSI = vector number */ 5537bbcdb1cSAndy Lutomirski movq %rdi, 8(%rsp) /* pt_regs->di = RDI */ 5547bbcdb1cSAndy Lutomirski pushq %rdx /* pt_regs->dx */ 5557bbcdb1cSAndy Lutomirski pushq %rcx /* pt_regs->cx */ 5567bbcdb1cSAndy Lutomirski pushq %rax /* pt_regs->ax */ 5577bbcdb1cSAndy Lutomirski pushq %r8 /* pt_regs->r8 */ 5587bbcdb1cSAndy Lutomirski pushq %r9 /* pt_regs->r9 */ 5597bbcdb1cSAndy Lutomirski pushq %r10 /* pt_regs->r10 */ 5607bbcdb1cSAndy Lutomirski pushq %r11 /* pt_regs->r11 */ 5617bbcdb1cSAndy Lutomirski pushq %rbx /* pt_regs->bx */ 5627bbcdb1cSAndy Lutomirski pushq %rbp /* pt_regs->bp */ 5637bbcdb1cSAndy Lutomirski pushq %r12 /* pt_regs->r12 */ 5647bbcdb1cSAndy Lutomirski pushq %r13 /* pt_regs->r13 */ 5657bbcdb1cSAndy Lutomirski pushq %r14 /* pt_regs->r14 */ 5667bbcdb1cSAndy Lutomirski pushq %r15 /* pt_regs->r15 */ 5672704fbb6SJosh Poimboeuf UNWIND_HINT_REGS 5689900aa2fSH. Peter Anvin 5697bbcdb1cSAndy Lutomirski movq %rsp,%rdi /* RDI = pt_regs; RSI is already trapnr */ 5704b47cdbdSJoerg Roedel call do_early_exception 5719900aa2fSH. Peter Anvin 5729900aa2fSH. Peter Anvin decl early_recursion_flag(%rip) 57326c4ef9cSAndy Lutomirski jmp restore_regs_and_return_to_kernel 574ef77e688SJiri SlabySYM_CODE_END(early_idt_handler_common) 5759900aa2fSH. Peter Anvin 57674d8d9d5SJoerg Roedel#ifdef CONFIG_AMD_MEM_ENCRYPT 57774d8d9d5SJoerg Roedel/* 57874d8d9d5SJoerg Roedel * VC Exception handler used during very early boot. The 57974d8d9d5SJoerg Roedel * early_idt_handler_array can't be used because it returns via the 58074d8d9d5SJoerg Roedel * paravirtualized INTERRUPT_RETURN and pv-ops don't work that early. 58174d8d9d5SJoerg Roedel * 5828b87d8ceSPeter Zijlstra * XXX it does, fix this. 5838b87d8ceSPeter Zijlstra * 58474d8d9d5SJoerg Roedel * This handler will end up in the .init.text section and not be 58574d8d9d5SJoerg Roedel * available to boot secondary CPUs. 58674d8d9d5SJoerg Roedel */ 58774d8d9d5SJoerg RoedelSYM_CODE_START_NOALIGN(vc_no_ghcb) 58874d8d9d5SJoerg Roedel UNWIND_HINT_IRET_REGS offset=8 589e8d61bdfSPeter Zijlstra ENDBR 59074d8d9d5SJoerg Roedel 59174d8d9d5SJoerg Roedel /* Build pt_regs */ 59274d8d9d5SJoerg Roedel PUSH_AND_CLEAR_REGS 59374d8d9d5SJoerg Roedel 59474d8d9d5SJoerg Roedel /* Call C handler */ 59574d8d9d5SJoerg Roedel movq %rsp, %rdi 59674d8d9d5SJoerg Roedel movq ORIG_RAX(%rsp), %rsi 59774d8d9d5SJoerg Roedel call do_vc_no_ghcb 59874d8d9d5SJoerg Roedel 59974d8d9d5SJoerg Roedel /* Unwind pt_regs */ 60074d8d9d5SJoerg Roedel POP_REGS 60174d8d9d5SJoerg Roedel 60274d8d9d5SJoerg Roedel /* Remove Error Code */ 60374d8d9d5SJoerg Roedel addq $8, %rsp 60474d8d9d5SJoerg Roedel 60574d8d9d5SJoerg Roedel /* Pure iret required here - don't use INTERRUPT_RETURN */ 60674d8d9d5SJoerg Roedel iretq 60774d8d9d5SJoerg RoedelSYM_CODE_END(vc_no_ghcb) 60874d8d9d5SJoerg Roedel#endif 609b1bd27b9SJiri Slaby 610b1bd27b9SJiri Slaby#define SYM_DATA_START_PAGE_ALIGNED(name) \ 611b1bd27b9SJiri Slaby SYM_START(name, SYM_L_GLOBAL, .balign PAGE_SIZE) 612250c2277SThomas Gleixner 613d9e9a641SDave Hansen#ifdef CONFIG_PAGE_TABLE_ISOLATION 614d9e9a641SDave Hansen/* 615d9e9a641SDave Hansen * Each PGD needs to be 8k long and 8k aligned. We do not 616d9e9a641SDave Hansen * ever go out to userspace with these, so we do not 617d9e9a641SDave Hansen * strictly *need* the second page, but this allows us to 618d9e9a641SDave Hansen * have a single set_pgd() implementation that does not 619d9e9a641SDave Hansen * need to worry about whether it has 4k or 8k to work 620d9e9a641SDave Hansen * with. 621d9e9a641SDave Hansen * 622d9e9a641SDave Hansen * This ensures PGDs are 8k long: 623d9e9a641SDave Hansen */ 624d9e9a641SDave Hansen#define PTI_USER_PGD_FILL 512 625d9e9a641SDave Hansen/* This ensures they are 8k-aligned: */ 626b1bd27b9SJiri Slaby#define SYM_DATA_START_PTI_ALIGNED(name) \ 627b1bd27b9SJiri Slaby SYM_START(name, SYM_L_GLOBAL, .balign 2 * PAGE_SIZE) 628d9e9a641SDave Hansen#else 629b1bd27b9SJiri Slaby#define SYM_DATA_START_PTI_ALIGNED(name) \ 630b1bd27b9SJiri Slaby SYM_DATA_START_PAGE_ALIGNED(name) 631d9e9a641SDave Hansen#define PTI_USER_PGD_FILL 0 632d9e9a641SDave Hansen#endif 633d9e9a641SDave Hansen 634250c2277SThomas Gleixner/* Automate the creation of 1 to 1 mapping pmd entries */ 635250c2277SThomas Gleixner#define PMDS(START, PERM, COUNT) \ 636250c2277SThomas Gleixner i = 0 ; \ 637250c2277SThomas Gleixner .rept (COUNT) ; \ 6380e192b99SCyrill Gorcunov .quad (START) + (i << PMD_SHIFT) + (PERM) ; \ 639250c2277SThomas Gleixner i = i + 1 ; \ 640250c2277SThomas Gleixner .endr 641250c2277SThomas Gleixner 6428170e6beSH. Peter Anvin __INITDATA 6431a8770b7SJiri Slaby .balign 4 6441a8770b7SJiri Slaby 645b1bd27b9SJiri SlabySYM_DATA_START_PTI_ALIGNED(early_top_pgt) 6466f9dd329SKirill A. Shutemov .fill 512,8,0 647d9e9a641SDave Hansen .fill PTI_USER_PGD_FILL,8,0 648b1bd27b9SJiri SlabySYM_DATA_END(early_top_pgt) 6498170e6beSH. Peter Anvin 650b1bd27b9SJiri SlabySYM_DATA_START_PAGE_ALIGNED(early_dynamic_pgts) 6518170e6beSH. Peter Anvin .fill 512*EARLY_DYNAMIC_PAGE_TABLES,8,0 652b1bd27b9SJiri SlabySYM_DATA_END(early_dynamic_pgts) 6538170e6beSH. Peter Anvin 654b1bd27b9SJiri SlabySYM_DATA(early_recursion_flag, .long 0) 6551a8770b7SJiri Slaby 656b9af7c0dSSuresh Siddha .data 6578170e6beSH. Peter Anvin 6587733607fSMaran Wilson#if defined(CONFIG_XEN_PV) || defined(CONFIG_PVH) 659b1bd27b9SJiri SlabySYM_DATA_START_PTI_ALIGNED(init_top_pgt) 66021729f81STom Lendacky .quad level3_ident_pgt - __START_KERNEL_map + _KERNPG_TABLE_NOENC 661b9952ec7SKirill A. Shutemov .org init_top_pgt + L4_PAGE_OFFSET*8, 0 66221729f81STom Lendacky .quad level3_ident_pgt - __START_KERNEL_map + _KERNPG_TABLE_NOENC 663b9952ec7SKirill A. Shutemov .org init_top_pgt + L4_START_KERNEL*8, 0 664250c2277SThomas Gleixner /* (2^48-(2*1024*1024*1024))/(2^39) = 511 */ 66521729f81STom Lendacky .quad level3_kernel_pgt - __START_KERNEL_map + _PAGE_TABLE_NOENC 666d9e9a641SDave Hansen .fill PTI_USER_PGD_FILL,8,0 667b1bd27b9SJiri SlabySYM_DATA_END(init_top_pgt) 668250c2277SThomas Gleixner 669b1bd27b9SJiri SlabySYM_DATA_START_PAGE_ALIGNED(level3_ident_pgt) 67021729f81STom Lendacky .quad level2_ident_pgt - __START_KERNEL_map + _KERNPG_TABLE_NOENC 671250c2277SThomas Gleixner .fill 511, 8, 0 672b1bd27b9SJiri SlabySYM_DATA_END(level3_ident_pgt) 673b1bd27b9SJiri SlabySYM_DATA_START_PAGE_ALIGNED(level2_ident_pgt) 674430d4005SDave Hansen /* 675430d4005SDave Hansen * Since I easily can, map the first 1G. 6768170e6beSH. Peter Anvin * Don't set NX because code runs from these pages. 677430d4005SDave Hansen * 678430d4005SDave Hansen * Note: This sets _PAGE_GLOBAL despite whether 679430d4005SDave Hansen * the CPU supports it or it is enabled. But, 680430d4005SDave Hansen * the CPU should ignore the bit. 6818170e6beSH. Peter Anvin */ 6828170e6beSH. Peter Anvin PMDS(0, __PAGE_KERNEL_IDENT_LARGE_EXEC, PTRS_PER_PMD) 683b1bd27b9SJiri SlabySYM_DATA_END(level2_ident_pgt) 6844375c299SKirill A. Shutemov#else 685b1bd27b9SJiri SlabySYM_DATA_START_PTI_ALIGNED(init_top_pgt) 6864375c299SKirill A. Shutemov .fill 512,8,0 687d9e9a641SDave Hansen .fill PTI_USER_PGD_FILL,8,0 688b1bd27b9SJiri SlabySYM_DATA_END(init_top_pgt) 6898170e6beSH. Peter Anvin#endif 690250c2277SThomas Gleixner 691032370b9SKirill A. Shutemov#ifdef CONFIG_X86_5LEVEL 692b1bd27b9SJiri SlabySYM_DATA_START_PAGE_ALIGNED(level4_kernel_pgt) 693032370b9SKirill A. Shutemov .fill 511,8,0 69421729f81STom Lendacky .quad level3_kernel_pgt - __START_KERNEL_map + _PAGE_TABLE_NOENC 695b1bd27b9SJiri SlabySYM_DATA_END(level4_kernel_pgt) 696032370b9SKirill A. Shutemov#endif 697032370b9SKirill A. Shutemov 698b1bd27b9SJiri SlabySYM_DATA_START_PAGE_ALIGNED(level3_kernel_pgt) 699a6523748SEduardo Habkost .fill L3_START_KERNEL,8,0 700250c2277SThomas Gleixner /* (2^48-(2*1024*1024*1024)-((2^39)*511))/(2^30) = 510 */ 70121729f81STom Lendacky .quad level2_kernel_pgt - __START_KERNEL_map + _KERNPG_TABLE_NOENC 70221729f81STom Lendacky .quad level2_fixmap_pgt - __START_KERNEL_map + _PAGE_TABLE_NOENC 703b1bd27b9SJiri SlabySYM_DATA_END(level3_kernel_pgt) 704250c2277SThomas Gleixner 705b1bd27b9SJiri SlabySYM_DATA_START_PAGE_ALIGNED(level2_kernel_pgt) 70688f3aec7SIngo Molnar /* 707ea3186b9SArvind Sankar * Kernel high mapping. 70888f3aec7SIngo Molnar * 709ea3186b9SArvind Sankar * The kernel code+data+bss must be located below KERNEL_IMAGE_SIZE in 710ea3186b9SArvind Sankar * virtual address space, which is 1 GiB if RANDOMIZE_BASE is enabled, 711ea3186b9SArvind Sankar * 512 MiB otherwise. 71288f3aec7SIngo Molnar * 713ea3186b9SArvind Sankar * (NOTE: after that starts the module area, see MODULES_VADDR.) 714430d4005SDave Hansen * 715ea3186b9SArvind Sankar * This table is eventually used by the kernel during normal runtime. 716ea3186b9SArvind Sankar * Care must be taken to clear out undesired bits later, like _PAGE_RW 717ea3186b9SArvind Sankar * or _PAGE_GLOBAL in some cases. 71888f3aec7SIngo Molnar */ 719ea3186b9SArvind Sankar PMDS(0, __PAGE_KERNEL_LARGE_EXEC, KERNEL_IMAGE_SIZE/PMD_SIZE) 720b1bd27b9SJiri SlabySYM_DATA_END(level2_kernel_pgt) 721250c2277SThomas Gleixner 722b1bd27b9SJiri SlabySYM_DATA_START_PAGE_ALIGNED(level2_fixmap_pgt) 72305ab1d8aSFeng Tang .fill (512 - 4 - FIXMAP_PMD_NUM),8,0 72405ab1d8aSFeng Tang pgtno = 0 72505ab1d8aSFeng Tang .rept (FIXMAP_PMD_NUM) 72605ab1d8aSFeng Tang .quad level1_fixmap_pgt + (pgtno << PAGE_SHIFT) - __START_KERNEL_map \ 72705ab1d8aSFeng Tang + _PAGE_TABLE_NOENC; 72805ab1d8aSFeng Tang pgtno = pgtno + 1 72905ab1d8aSFeng Tang .endr 73005ab1d8aSFeng Tang /* 6 MB reserved space + a 2MB hole */ 73105ab1d8aSFeng Tang .fill 4,8,0 732b1bd27b9SJiri SlabySYM_DATA_END(level2_fixmap_pgt) 7338170e6beSH. Peter Anvin 734b1bd27b9SJiri SlabySYM_DATA_START_PAGE_ALIGNED(level1_fixmap_pgt) 73505ab1d8aSFeng Tang .rept (FIXMAP_PMD_NUM) 736250c2277SThomas Gleixner .fill 512,8,0 73705ab1d8aSFeng Tang .endr 738b1bd27b9SJiri SlabySYM_DATA_END(level1_fixmap_pgt) 739250c2277SThomas Gleixner 740250c2277SThomas Gleixner#undef PMDS 741250c2277SThomas Gleixner 742250c2277SThomas Gleixner .data 743250c2277SThomas Gleixner .align 16 744250c2277SThomas Gleixner 7453adee777SBrian GerstSYM_DATA(smpboot_control, .long 0) 7463adee777SBrian Gerst 7473adee777SBrian Gerst .align 16 748250c2277SThomas Gleixner/* This must match the first entry in level2_kernel_pgt */ 749b1bd27b9SJiri SlabySYM_DATA(phys_base, .quad 0x0) 750784d5699SAl ViroEXPORT_SYMBOL(phys_base) 751250c2277SThomas Gleixner 7528c5e5ac3SJeremy Fitzhardinge#include "../../x86/xen/xen-head.S" 753250c2277SThomas Gleixner 75402b7da37STim Abbott __PAGE_ALIGNED_BSS 755b1bd27b9SJiri SlabySYM_DATA_START_PAGE_ALIGNED(empty_zero_page) 756250c2277SThomas Gleixner .skip PAGE_SIZE 757b1bd27b9SJiri SlabySYM_DATA_END(empty_zero_page) 758784d5699SAl ViroEXPORT_SYMBOL(empty_zero_page) 759ef7f0d6aSAndrey Ryabinin 760