1b2441318SGreg Kroah-Hartman/* SPDX-License-Identifier: GPL-2.0 */ 2250c2277SThomas Gleixner/* 35b171e82SAlexander Kuleshov * linux/arch/x86/kernel/head_64.S -- start in 32bit and switch to 64bit 4250c2277SThomas Gleixner * 5250c2277SThomas Gleixner * Copyright (C) 2000 Andrea Arcangeli <andrea@suse.de> SuSE 6250c2277SThomas Gleixner * Copyright (C) 2000 Pavel Machek <pavel@suse.cz> 7250c2277SThomas Gleixner * Copyright (C) 2000 Karsten Keil <kkeil@suse.de> 8250c2277SThomas Gleixner * Copyright (C) 2001,2002 Andi Kleen <ak@suse.de> 9250c2277SThomas Gleixner * Copyright (C) 2005 Eric Biederman <ebiederm@xmission.com> 10250c2277SThomas Gleixner */ 11250c2277SThomas Gleixner 12250c2277SThomas Gleixner 13250c2277SThomas Gleixner#include <linux/linkage.h> 14250c2277SThomas Gleixner#include <linux/threads.h> 15250c2277SThomas Gleixner#include <linux/init.h> 16ca5999fdSMike Rapoport#include <linux/pgtable.h> 1765fddcfcSMike Rapoport#include <asm/segment.h> 18250c2277SThomas Gleixner#include <asm/page.h> 19250c2277SThomas Gleixner#include <asm/msr.h> 20250c2277SThomas Gleixner#include <asm/cache.h> 21369101daSCyrill Gorcunov#include <asm/processor-flags.h> 22b12d8db8STejun Heo#include <asm/percpu.h> 239900aa2fSH. Peter Anvin#include <asm/nops.h> 247bbcdb1cSAndy Lutomirski#include "../entry/calling.h" 25784d5699SAl Viro#include <asm/export.h> 26bd89004fSPeter Zijlstra#include <asm/nospec-branch.h> 2705ab1d8aSFeng Tang#include <asm/fixmap.h> 28250c2277SThomas Gleixner 2975da04f7SThomas Gleixner/* 3075da04f7SThomas Gleixner * We are not able to switch in one step to the final KERNEL ADDRESS SPACE 31250c2277SThomas Gleixner * because we need identity-mapped pages. 32250c2277SThomas Gleixner */ 33b9952ec7SKirill A. Shutemov#define l4_index(x) (((x) >> 39) & 511) 34a6523748SEduardo Habkost#define pud_index(x) (((x) >> PUD_SHIFT) & (PTRS_PER_PUD-1)) 35a6523748SEduardo Habkost 36b9952ec7SKirill A. ShutemovL4_PAGE_OFFSET = l4_index(__PAGE_OFFSET_BASE_L4) 37b9952ec7SKirill A. ShutemovL4_START_KERNEL = l4_index(__START_KERNEL_map) 38b9952ec7SKirill A. Shutemov 39a6523748SEduardo HabkostL3_START_KERNEL = pud_index(__START_KERNEL_map) 40a6523748SEduardo Habkost 41250c2277SThomas Gleixner .text 424ae59b91STim Abbott __HEAD 43250c2277SThomas Gleixner .code64 4437818afdSJiri SlabySYM_CODE_START_NOALIGN(startup_64) 452704fbb6SJosh Poimboeuf UNWIND_HINT_EMPTY 46250c2277SThomas Gleixner /* 471256276cSKonrad Rzeszutek Wilk * At this point the CPU runs in 64bit mode CS.L = 1 CS.D = 0, 48250c2277SThomas Gleixner * and someone has loaded an identity mapped page table 49250c2277SThomas Gleixner * for us. These identity mapped page tables map all of the 50250c2277SThomas Gleixner * kernel pages and possibly all of memory. 51250c2277SThomas Gleixner * 528170e6beSH. Peter Anvin * %rsi holds a physical pointer to real_mode_data. 53250c2277SThomas Gleixner * 54250c2277SThomas Gleixner * We come here either directly from a 64bit bootloader, or from 555b171e82SAlexander Kuleshov * arch/x86/boot/compressed/head_64.S. 56250c2277SThomas Gleixner * 57250c2277SThomas Gleixner * We only come here initially at boot nothing else comes here. 58250c2277SThomas Gleixner * 59250c2277SThomas Gleixner * Since we may be loaded at an address different from what we were 60250c2277SThomas Gleixner * compiled to run at we first fixup the physical addresses in our page 61250c2277SThomas Gleixner * tables and then reload them. 62250c2277SThomas Gleixner */ 63250c2277SThomas Gleixner 6422dc3918SJosh Poimboeuf /* Set up the stack for verify_cpu(), similar to initial_stack below */ 656627eb25SH. Peter Anvin (Intel) leaq (__end_init_task - FRAME_SIZE)(%rip), %rsp 6691ed140dSBorislav Petkov 67866b556eSJoerg Roedel leaq _text(%rip), %rdi 68866b556eSJoerg Roedel pushq %rsi 69866b556eSJoerg Roedel call startup_64_setup_env 70866b556eSJoerg Roedel popq %rsi 71866b556eSJoerg Roedel 72*bcce8290SMichael Roth#ifdef CONFIG_AMD_MEM_ENCRYPT 73*bcce8290SMichael Roth /* 74*bcce8290SMichael Roth * Activate SEV/SME memory encryption if supported/enabled. This needs to 75*bcce8290SMichael Roth * be done now, since this also includes setup of the SEV-SNP CPUID table, 76*bcce8290SMichael Roth * which needs to be done before any CPUID instructions are executed in 77*bcce8290SMichael Roth * subsequent code. 78*bcce8290SMichael Roth */ 79*bcce8290SMichael Roth movq %rsi, %rdi 80*bcce8290SMichael Roth pushq %rsi 81*bcce8290SMichael Roth call sme_enable 82*bcce8290SMichael Roth popq %rsi 83*bcce8290SMichael Roth#endif 84*bcce8290SMichael Roth 85866b556eSJoerg Roedel /* Now switch to __KERNEL_CS so IRET works reliably */ 86866b556eSJoerg Roedel pushq $__KERNEL_CS 87866b556eSJoerg Roedel leaq .Lon_kernel_cs(%rip), %rax 88866b556eSJoerg Roedel pushq %rax 89866b556eSJoerg Roedel lretq 90866b556eSJoerg Roedel 91866b556eSJoerg Roedel.Lon_kernel_cs: 92866b556eSJoerg Roedel UNWIND_HINT_EMPTY 93866b556eSJoerg Roedel 9404633df0SBorislav Petkov /* Sanitize CPU configuration */ 9504633df0SBorislav Petkov call verify_cpu 9604633df0SBorislav Petkov 975868f365STom Lendacky /* 985868f365STom Lendacky * Perform pagetable fixups. Additionally, if SME is active, encrypt 995868f365STom Lendacky * the kernel and retrieve the modifier (SME encryption mask if SME 1005868f365STom Lendacky * is active) to be added to the initial pgdir entry that will be 1015868f365STom Lendacky * programmed into CR3. 1025868f365STom Lendacky */ 103250c2277SThomas Gleixner leaq _text(%rip), %rdi 104c88d7150SKirill A. Shutemov pushq %rsi 105c88d7150SKirill A. Shutemov call __startup_64 106c88d7150SKirill A. Shutemov popq %rsi 107250c2277SThomas Gleixner 1085868f365STom Lendacky /* Form the CR3 value being sure to include the CR3 modifier */ 1095868f365STom Lendacky addq $(early_top_pgt - __START_KERNEL_map), %rax 1108170e6beSH. Peter Anvin jmp 1f 11137818afdSJiri SlabySYM_CODE_END(startup_64) 11237818afdSJiri Slaby 113bc7b11c0SJiri SlabySYM_CODE_START(secondary_startup_64) 1142704fbb6SJosh Poimboeuf UNWIND_HINT_EMPTY 1153e3f0695SPeter Zijlstra ANNOTATE_NOENDBR 116250c2277SThomas Gleixner /* 1171256276cSKonrad Rzeszutek Wilk * At this point the CPU runs in 64bit mode CS.L = 1 CS.D = 0, 118250c2277SThomas Gleixner * and someone has loaded a mapped page table. 119250c2277SThomas Gleixner * 1208170e6beSH. Peter Anvin * %rsi holds a physical pointer to real_mode_data. 121250c2277SThomas Gleixner * 122250c2277SThomas Gleixner * We come here either from startup_64 (using physical addresses) 123250c2277SThomas Gleixner * or from trampoline.S (using virtual addresses). 124250c2277SThomas Gleixner * 125250c2277SThomas Gleixner * Using virtual addresses from trampoline.S removes the need 126250c2277SThomas Gleixner * to have any identity mapped pages in the kernel page table 127250c2277SThomas Gleixner * after the boot processor executes this code. 128250c2277SThomas Gleixner */ 129250c2277SThomas Gleixner 13004633df0SBorislav Petkov /* Sanitize CPU configuration */ 13104633df0SBorislav Petkov call verify_cpu 13204633df0SBorislav Petkov 1335868f365STom Lendacky /* 1343ecacdbdSJoerg Roedel * The secondary_startup_64_no_verify entry point is only used by 1353ecacdbdSJoerg Roedel * SEV-ES guests. In those guests the call to verify_cpu() would cause 1363ecacdbdSJoerg Roedel * #VC exceptions which can not be handled at this stage of secondary 1373ecacdbdSJoerg Roedel * CPU bringup. 1383ecacdbdSJoerg Roedel * 1393ecacdbdSJoerg Roedel * All non SEV-ES systems, especially Intel systems, need to execute 1403ecacdbdSJoerg Roedel * verify_cpu() above to make sure NX is enabled. 1413ecacdbdSJoerg Roedel */ 1423ecacdbdSJoerg RoedelSYM_INNER_LABEL(secondary_startup_64_no_verify, SYM_L_GLOBAL) 1433ecacdbdSJoerg Roedel UNWIND_HINT_EMPTY 1443e3f0695SPeter Zijlstra ANNOTATE_NOENDBR 1453ecacdbdSJoerg Roedel 1463ecacdbdSJoerg Roedel /* 1475868f365STom Lendacky * Retrieve the modifier (SME encryption mask if SME is active) to be 1485868f365STom Lendacky * added to the initial pgdir entry that will be programmed into CR3. 1495868f365STom Lendacky */ 1505868f365STom Lendacky pushq %rsi 1515868f365STom Lendacky call __startup_secondary_64 1525868f365STom Lendacky popq %rsi 1535868f365STom Lendacky 1545868f365STom Lendacky /* Form the CR3 value being sure to include the CR3 modifier */ 1555868f365STom Lendacky addq $(init_top_pgt - __START_KERNEL_map), %rax 1568170e6beSH. Peter Anvin1: 1578170e6beSH. Peter Anvin 158032370b9SKirill A. Shutemov /* Enable PAE mode, PGE and LA57 */ 1598170e6beSH. Peter Anvin movl $(X86_CR4_PAE | X86_CR4_PGE), %ecx 160032370b9SKirill A. Shutemov#ifdef CONFIG_X86_5LEVEL 16139b95522SKirill A. Shutemov testl $1, __pgtable_l5_enabled(%rip) 1626f9dd329SKirill A. Shutemov jz 1f 163032370b9SKirill A. Shutemov orl $X86_CR4_LA57, %ecx 1646f9dd329SKirill A. Shutemov1: 165032370b9SKirill A. Shutemov#endif 1668170e6beSH. Peter Anvin movq %rcx, %cr4 167250c2277SThomas Gleixner 168032370b9SKirill A. Shutemov /* Setup early boot stage 4-/5-level pagetables. */ 169250c2277SThomas Gleixner addq phys_base(%rip), %rax 170c9f09539SJoerg Roedel 171c9f09539SJoerg Roedel /* 172c9f09539SJoerg Roedel * For SEV guests: Verify that the C-bit is correct. A malicious 173c9f09539SJoerg Roedel * hypervisor could lie about the C-bit position to perform a ROP 174c9f09539SJoerg Roedel * attack on the guest by writing to the unencrypted stack and wait for 175c9f09539SJoerg Roedel * the next RET instruction. 176c9f09539SJoerg Roedel * %rsi carries pointer to realmode data and is callee-clobbered. Save 177c9f09539SJoerg Roedel * and restore it. 178c9f09539SJoerg Roedel */ 179c9f09539SJoerg Roedel pushq %rsi 180c9f09539SJoerg Roedel movq %rax, %rdi 181c9f09539SJoerg Roedel call sev_verify_cbit 182c9f09539SJoerg Roedel popq %rsi 183c9f09539SJoerg Roedel 184f154f290SJoerg Roedel /* 185f154f290SJoerg Roedel * Switch to new page-table 186f154f290SJoerg Roedel * 187f154f290SJoerg Roedel * For the boot CPU this switches to early_top_pgt which still has the 188f154f290SJoerg Roedel * indentity mappings present. The secondary CPUs will switch to the 189f154f290SJoerg Roedel * init_top_pgt here, away from the trampoline_pgd and unmap the 190f154f290SJoerg Roedel * indentity mapped ranges. 191f154f290SJoerg Roedel */ 192250c2277SThomas Gleixner movq %rax, %cr3 193250c2277SThomas Gleixner 194f154f290SJoerg Roedel /* 195f154f290SJoerg Roedel * Do a global TLB flush after the CR3 switch to make sure the TLB 196f154f290SJoerg Roedel * entries from the identity mapping are flushed. 197f154f290SJoerg Roedel */ 198f154f290SJoerg Roedel movq %cr4, %rcx 199f154f290SJoerg Roedel movq %rcx, %rax 200f154f290SJoerg Roedel xorq $X86_CR4_PGE, %rcx 201f154f290SJoerg Roedel movq %rcx, %cr4 202f154f290SJoerg Roedel movq %rax, %cr4 203f154f290SJoerg Roedel 204250c2277SThomas Gleixner /* Ensure I am executing from virtual addresses */ 205250c2277SThomas Gleixner movq $1f, %rax 206bd89004fSPeter Zijlstra ANNOTATE_RETPOLINE_SAFE 207250c2277SThomas Gleixner jmp *%rax 208250c2277SThomas Gleixner1: 2092704fbb6SJosh Poimboeuf UNWIND_HINT_EMPTY 2103e3f0695SPeter Zijlstra ANNOTATE_NOENDBR // above 211250c2277SThomas Gleixner 212e04b8833SJoerg Roedel /* 213e04b8833SJoerg Roedel * We must switch to a new descriptor in kernel space for the GDT 214e04b8833SJoerg Roedel * because soon the kernel won't have access anymore to the userspace 215e04b8833SJoerg Roedel * addresses where we're currently running on. We have to do that here 216e04b8833SJoerg Roedel * because in 32bit we couldn't load a 64bit linear address. 217e04b8833SJoerg Roedel */ 218e04b8833SJoerg Roedel lgdt early_gdt_descr(%rip) 219e04b8833SJoerg Roedel 2207b99819dSJoerg Roedel /* set up data segments */ 2217b99819dSJoerg Roedel xorl %eax,%eax 2227b99819dSJoerg Roedel movl %eax,%ds 2237b99819dSJoerg Roedel movl %eax,%ss 2247b99819dSJoerg Roedel movl %eax,%es 2257b99819dSJoerg Roedel 2267b99819dSJoerg Roedel /* 2277b99819dSJoerg Roedel * We don't really need to load %fs or %gs, but load them anyway 2287b99819dSJoerg Roedel * to kill any stale realmode selectors. This allows execution 2297b99819dSJoerg Roedel * under VT hardware. 2307b99819dSJoerg Roedel */ 2317b99819dSJoerg Roedel movl %eax,%fs 2327b99819dSJoerg Roedel movl %eax,%gs 2337b99819dSJoerg Roedel 2347b99819dSJoerg Roedel /* Set up %gs. 2357b99819dSJoerg Roedel * 2367b99819dSJoerg Roedel * The base of %gs always points to fixed_percpu_data. If the 2377b99819dSJoerg Roedel * stack protector canary is enabled, it is located at %gs:40. 2387b99819dSJoerg Roedel * Note that, on SMP, the boot cpu uses init data section until 2397b99819dSJoerg Roedel * the per cpu areas are set up. 2407b99819dSJoerg Roedel */ 2417b99819dSJoerg Roedel movl $MSR_GS_BASE,%ecx 2427b99819dSJoerg Roedel movl initial_gs(%rip),%eax 2437b99819dSJoerg Roedel movl initial_gs+4(%rip),%edx 2447b99819dSJoerg Roedel wrmsr 2457b99819dSJoerg Roedel 2463add38cbSJoerg Roedel /* 2473add38cbSJoerg Roedel * Setup a boot time stack - Any secondary CPU will have lost its stack 2483add38cbSJoerg Roedel * by now because the cr3-switch above unmaps the real-mode stack 2493add38cbSJoerg Roedel */ 2503add38cbSJoerg Roedel movq initial_stack(%rip), %rsp 2513add38cbSJoerg Roedel 252f5963ba7SJoerg Roedel /* Setup and Load IDT */ 253f5963ba7SJoerg Roedel pushq %rsi 254f5963ba7SJoerg Roedel call early_setup_idt 255f5963ba7SJoerg Roedel popq %rsi 256f5963ba7SJoerg Roedel 257250c2277SThomas Gleixner /* Check if nx is implemented */ 258250c2277SThomas Gleixner movl $0x80000001, %eax 259250c2277SThomas Gleixner cpuid 260250c2277SThomas Gleixner movl %edx,%edi 261250c2277SThomas Gleixner 262250c2277SThomas Gleixner /* Setup EFER (Extended Feature Enable Register) */ 263250c2277SThomas Gleixner movl $MSR_EFER, %ecx 264250c2277SThomas Gleixner rdmsr 265250c2277SThomas Gleixner btsl $_EFER_SCE, %eax /* Enable System Call */ 266250c2277SThomas Gleixner btl $20,%edi /* No Execute supported? */ 267250c2277SThomas Gleixner jnc 1f 268250c2277SThomas Gleixner btsl $_EFER_NX, %eax 26978d77df7SH. Peter Anvin btsq $_PAGE_BIT_NX,early_pmd_flags(%rip) 270250c2277SThomas Gleixner1: wrmsr /* Make changes effective */ 271250c2277SThomas Gleixner 272250c2277SThomas Gleixner /* Setup cr0 */ 273369101daSCyrill Gorcunov movl $CR0_STATE, %eax 274250c2277SThomas Gleixner /* Make changes effective */ 275250c2277SThomas Gleixner movq %rax, %cr0 276250c2277SThomas Gleixner 277250c2277SThomas Gleixner /* zero EFLAGS after setting rsp */ 278250c2277SThomas Gleixner pushq $0 279250c2277SThomas Gleixner popfq 280250c2277SThomas Gleixner 2818170e6beSH. Peter Anvin /* rsi is pointer to real mode structure with interesting info. 282250c2277SThomas Gleixner pass it to C */ 2838170e6beSH. Peter Anvin movq %rsi, %rdi 284250c2277SThomas Gleixner 28579d243a0SBorislav Petkov.Ljump_to_C_code: 286a9468df5SJosh Poimboeuf /* 287a9468df5SJosh Poimboeuf * Jump to run C code and to be on a real kernel address. 288250c2277SThomas Gleixner * Since we are running on identity-mapped space we have to jump 289250c2277SThomas Gleixner * to the full 64bit address, this is only possible as indirect 290250c2277SThomas Gleixner * jump. In addition we need to ensure %cs is set so we make this 291250c2277SThomas Gleixner * a far return. 2928170e6beSH. Peter Anvin * 2938170e6beSH. Peter Anvin * Note: do not change to far jump indirect with 64bit offset. 2948170e6beSH. Peter Anvin * 2958170e6beSH. Peter Anvin * AMD does not support far jump indirect with 64bit offset. 2968170e6beSH. Peter Anvin * AMD64 Architecture Programmer's Manual, Volume 3: states only 2978170e6beSH. Peter Anvin * JMP FAR mem16:16 FF /5 Far jump indirect, 2988170e6beSH. Peter Anvin * with the target specified by a far pointer in memory. 2998170e6beSH. Peter Anvin * JMP FAR mem16:32 FF /5 Far jump indirect, 3008170e6beSH. Peter Anvin * with the target specified by a far pointer in memory. 3018170e6beSH. Peter Anvin * 3028170e6beSH. Peter Anvin * Intel64 does support 64bit offset. 3038170e6beSH. Peter Anvin * Software Developer Manual Vol 2: states: 3048170e6beSH. Peter Anvin * FF /5 JMP m16:16 Jump far, absolute indirect, 3058170e6beSH. Peter Anvin * address given in m16:16 3068170e6beSH. Peter Anvin * FF /5 JMP m16:32 Jump far, absolute indirect, 3078170e6beSH. Peter Anvin * address given in m16:32. 3088170e6beSH. Peter Anvin * REX.W + FF /5 JMP m16:64 Jump far, absolute indirect, 3098170e6beSH. Peter Anvin * address given in m16:64. 310250c2277SThomas Gleixner */ 31131dcfec1SJosh Poimboeuf pushq $.Lafter_lret # put return address on stack for unwinder 312a7bea830SJan Beulich xorl %ebp, %ebp # clear frame pointer 313250c2277SThomas Gleixner movq initial_code(%rip), %rax 314250c2277SThomas Gleixner pushq $__KERNEL_CS # set correct cs 315250c2277SThomas Gleixner pushq %rax # target address in negative space 316250c2277SThomas Gleixner lretq 31731dcfec1SJosh Poimboeuf.Lafter_lret: 3183e3f0695SPeter Zijlstra ANNOTATE_NOENDBR 319bc7b11c0SJiri SlabySYM_CODE_END(secondary_startup_64) 320250c2277SThomas Gleixner 32104633df0SBorislav Petkov#include "verify_cpu.S" 322c9f09539SJoerg Roedel#include "sev_verify_cbit.S" 32304633df0SBorislav Petkov 32442e78e97SFenghua Yu#ifdef CONFIG_HOTPLUG_CPU 32542e78e97SFenghua Yu/* 32642e78e97SFenghua Yu * Boot CPU0 entry point. It's called from play_dead(). Everything has been set 32742e78e97SFenghua Yu * up already except stack. We just set up stack here. Then call 32879d243a0SBorislav Petkov * start_secondary() via .Ljump_to_C_code. 32942e78e97SFenghua Yu */ 330bc7b11c0SJiri SlabySYM_CODE_START(start_cpu0) 3312704fbb6SJosh Poimboeuf UNWIND_HINT_EMPTY 33261a73f5cSJosh Poimboeuf movq initial_stack(%rip), %rsp 33379d243a0SBorislav Petkov jmp .Ljump_to_C_code 334bc7b11c0SJiri SlabySYM_CODE_END(start_cpu0) 33542e78e97SFenghua Yu#endif 33642e78e97SFenghua Yu 3371aa9aa8eSJoerg Roedel#ifdef CONFIG_AMD_MEM_ENCRYPT 3381aa9aa8eSJoerg Roedel/* 3391aa9aa8eSJoerg Roedel * VC Exception handler used during early boot when running on kernel 3401aa9aa8eSJoerg Roedel * addresses, but before the switch to the idt_table can be made. 3411aa9aa8eSJoerg Roedel * The early_idt_handler_array can't be used here because it calls into a lot 3421aa9aa8eSJoerg Roedel * of __init code and this handler is also used during CPU offlining/onlining. 3431aa9aa8eSJoerg Roedel * Therefore this handler ends up in the .text section so that it stays around 3441aa9aa8eSJoerg Roedel * when .init.text is freed. 3451aa9aa8eSJoerg Roedel */ 3461aa9aa8eSJoerg RoedelSYM_CODE_START_NOALIGN(vc_boot_ghcb) 3471aa9aa8eSJoerg Roedel UNWIND_HINT_IRET_REGS offset=8 348e8d61bdfSPeter Zijlstra ENDBR 3491aa9aa8eSJoerg Roedel 3501aa9aa8eSJoerg Roedel /* Build pt_regs */ 3511aa9aa8eSJoerg Roedel PUSH_AND_CLEAR_REGS 3521aa9aa8eSJoerg Roedel 3531aa9aa8eSJoerg Roedel /* Call C handler */ 3541aa9aa8eSJoerg Roedel movq %rsp, %rdi 3551aa9aa8eSJoerg Roedel movq ORIG_RAX(%rsp), %rsi 3561aa9aa8eSJoerg Roedel movq initial_vc_handler(%rip), %rax 3571aa9aa8eSJoerg Roedel ANNOTATE_RETPOLINE_SAFE 3581aa9aa8eSJoerg Roedel call *%rax 3591aa9aa8eSJoerg Roedel 3601aa9aa8eSJoerg Roedel /* Unwind pt_regs */ 3611aa9aa8eSJoerg Roedel POP_REGS 3621aa9aa8eSJoerg Roedel 3631aa9aa8eSJoerg Roedel /* Remove Error Code */ 3641aa9aa8eSJoerg Roedel addq $8, %rsp 3651aa9aa8eSJoerg Roedel 3661aa9aa8eSJoerg Roedel iretq 3671aa9aa8eSJoerg RoedelSYM_CODE_END(vc_boot_ghcb) 3681aa9aa8eSJoerg Roedel#endif 3691aa9aa8eSJoerg Roedel 370b32f96c7SJosh Poimboeuf /* Both SMP bootup and ACPI suspend change these variables */ 371da5968aeSSam Ravnborg __REFDATA 3728170e6beSH. Peter Anvin .balign 8 373b1bd27b9SJiri SlabySYM_DATA(initial_code, .quad x86_64_start_kernel) 374b1bd27b9SJiri SlabySYM_DATA(initial_gs, .quad INIT_PER_CPU_VAR(fixed_percpu_data)) 3751aa9aa8eSJoerg Roedel#ifdef CONFIG_AMD_MEM_ENCRYPT 3761aa9aa8eSJoerg RoedelSYM_DATA(initial_vc_handler, .quad handle_vc_boot_ghcb) 3771aa9aa8eSJoerg Roedel#endif 378b1bd27b9SJiri Slaby 37922dc3918SJosh Poimboeuf/* 3806627eb25SH. Peter Anvin (Intel) * The FRAME_SIZE gap is a convention which helps the in-kernel unwinder 381b1bd27b9SJiri Slaby * reliably detect the end of the stack. 38222dc3918SJosh Poimboeuf */ 3836627eb25SH. Peter Anvin (Intel)SYM_DATA(initial_stack, .quad init_thread_union + THREAD_SIZE - FRAME_SIZE) 384b9af7c0dSSuresh Siddha __FINITDATA 385250c2277SThomas Gleixner 3868170e6beSH. Peter Anvin __INIT 387bc7b11c0SJiri SlabySYM_CODE_START(early_idt_handler_array) 388749c970aSAndi Kleen i = 0 389749c970aSAndi Kleen .rept NUM_EXCEPTION_VECTORS 39082c62fa0SJosh Poimboeuf .if ((EXCEPTION_ERRCODE_MASK >> i) & 1) == 0 3912704fbb6SJosh Poimboeuf UNWIND_HINT_IRET_REGS 3928f93402bSPeter Zijlstra ENDBR 3939900aa2fSH. Peter Anvin pushq $0 # Dummy error code, to make stack frame uniform 3942704fbb6SJosh Poimboeuf .else 3952704fbb6SJosh Poimboeuf UNWIND_HINT_IRET_REGS offset=8 3968f93402bSPeter Zijlstra ENDBR 3979900aa2fSH. Peter Anvin .endif 3989900aa2fSH. Peter Anvin pushq $i # 72(%rsp) Vector number 399cdeb6048SAndy Lutomirski jmp early_idt_handler_common 4002704fbb6SJosh Poimboeuf UNWIND_HINT_IRET_REGS 401749c970aSAndi Kleen i = i + 1 402cdeb6048SAndy Lutomirski .fill early_idt_handler_array + i*EARLY_IDT_HANDLER_SIZE - ., 1, 0xcc 403749c970aSAndi Kleen .endr 404bc7b11c0SJiri SlabySYM_CODE_END(early_idt_handler_array) 4055b2fc515SPeter Zijlstra ANNOTATE_NOENDBR // early_idt_handler_array[NUM_EXCEPTION_VECTORS] 4068866cd9dSRoland McGrath 407ef77e688SJiri SlabySYM_CODE_START_LOCAL(early_idt_handler_common) 4088f93402bSPeter Zijlstra UNWIND_HINT_IRET_REGS offset=16 409cdeb6048SAndy Lutomirski /* 410cdeb6048SAndy Lutomirski * The stack is the hardware frame, an error code or zero, and the 411cdeb6048SAndy Lutomirski * vector number. 412cdeb6048SAndy Lutomirski */ 4139900aa2fSH. Peter Anvin cld 4149900aa2fSH. Peter Anvin 415250c2277SThomas Gleixner incl early_recursion_flag(%rip) 4169900aa2fSH. Peter Anvin 4177bbcdb1cSAndy Lutomirski /* The vector number is currently in the pt_regs->di slot. */ 4187bbcdb1cSAndy Lutomirski pushq %rsi /* pt_regs->si */ 4197bbcdb1cSAndy Lutomirski movq 8(%rsp), %rsi /* RSI = vector number */ 4207bbcdb1cSAndy Lutomirski movq %rdi, 8(%rsp) /* pt_regs->di = RDI */ 4217bbcdb1cSAndy Lutomirski pushq %rdx /* pt_regs->dx */ 4227bbcdb1cSAndy Lutomirski pushq %rcx /* pt_regs->cx */ 4237bbcdb1cSAndy Lutomirski pushq %rax /* pt_regs->ax */ 4247bbcdb1cSAndy Lutomirski pushq %r8 /* pt_regs->r8 */ 4257bbcdb1cSAndy Lutomirski pushq %r9 /* pt_regs->r9 */ 4267bbcdb1cSAndy Lutomirski pushq %r10 /* pt_regs->r10 */ 4277bbcdb1cSAndy Lutomirski pushq %r11 /* pt_regs->r11 */ 4287bbcdb1cSAndy Lutomirski pushq %rbx /* pt_regs->bx */ 4297bbcdb1cSAndy Lutomirski pushq %rbp /* pt_regs->bp */ 4307bbcdb1cSAndy Lutomirski pushq %r12 /* pt_regs->r12 */ 4317bbcdb1cSAndy Lutomirski pushq %r13 /* pt_regs->r13 */ 4327bbcdb1cSAndy Lutomirski pushq %r14 /* pt_regs->r14 */ 4337bbcdb1cSAndy Lutomirski pushq %r15 /* pt_regs->r15 */ 4342704fbb6SJosh Poimboeuf UNWIND_HINT_REGS 4359900aa2fSH. Peter Anvin 4367bbcdb1cSAndy Lutomirski movq %rsp,%rdi /* RDI = pt_regs; RSI is already trapnr */ 4374b47cdbdSJoerg Roedel call do_early_exception 4389900aa2fSH. Peter Anvin 4399900aa2fSH. Peter Anvin decl early_recursion_flag(%rip) 44026c4ef9cSAndy Lutomirski jmp restore_regs_and_return_to_kernel 441ef77e688SJiri SlabySYM_CODE_END(early_idt_handler_common) 4429900aa2fSH. Peter Anvin 44374d8d9d5SJoerg Roedel#ifdef CONFIG_AMD_MEM_ENCRYPT 44474d8d9d5SJoerg Roedel/* 44574d8d9d5SJoerg Roedel * VC Exception handler used during very early boot. The 44674d8d9d5SJoerg Roedel * early_idt_handler_array can't be used because it returns via the 44774d8d9d5SJoerg Roedel * paravirtualized INTERRUPT_RETURN and pv-ops don't work that early. 44874d8d9d5SJoerg Roedel * 4498b87d8ceSPeter Zijlstra * XXX it does, fix this. 4508b87d8ceSPeter Zijlstra * 45174d8d9d5SJoerg Roedel * This handler will end up in the .init.text section and not be 45274d8d9d5SJoerg Roedel * available to boot secondary CPUs. 45374d8d9d5SJoerg Roedel */ 45474d8d9d5SJoerg RoedelSYM_CODE_START_NOALIGN(vc_no_ghcb) 45574d8d9d5SJoerg Roedel UNWIND_HINT_IRET_REGS offset=8 456e8d61bdfSPeter Zijlstra ENDBR 45774d8d9d5SJoerg Roedel 45874d8d9d5SJoerg Roedel /* Build pt_regs */ 45974d8d9d5SJoerg Roedel PUSH_AND_CLEAR_REGS 46074d8d9d5SJoerg Roedel 46174d8d9d5SJoerg Roedel /* Call C handler */ 46274d8d9d5SJoerg Roedel movq %rsp, %rdi 46374d8d9d5SJoerg Roedel movq ORIG_RAX(%rsp), %rsi 46474d8d9d5SJoerg Roedel call do_vc_no_ghcb 46574d8d9d5SJoerg Roedel 46674d8d9d5SJoerg Roedel /* Unwind pt_regs */ 46774d8d9d5SJoerg Roedel POP_REGS 46874d8d9d5SJoerg Roedel 46974d8d9d5SJoerg Roedel /* Remove Error Code */ 47074d8d9d5SJoerg Roedel addq $8, %rsp 47174d8d9d5SJoerg Roedel 47274d8d9d5SJoerg Roedel /* Pure iret required here - don't use INTERRUPT_RETURN */ 47374d8d9d5SJoerg Roedel iretq 47474d8d9d5SJoerg RoedelSYM_CODE_END(vc_no_ghcb) 47574d8d9d5SJoerg Roedel#endif 476b1bd27b9SJiri Slaby 477b1bd27b9SJiri Slaby#define SYM_DATA_START_PAGE_ALIGNED(name) \ 478b1bd27b9SJiri Slaby SYM_START(name, SYM_L_GLOBAL, .balign PAGE_SIZE) 479250c2277SThomas Gleixner 480d9e9a641SDave Hansen#ifdef CONFIG_PAGE_TABLE_ISOLATION 481d9e9a641SDave Hansen/* 482d9e9a641SDave Hansen * Each PGD needs to be 8k long and 8k aligned. We do not 483d9e9a641SDave Hansen * ever go out to userspace with these, so we do not 484d9e9a641SDave Hansen * strictly *need* the second page, but this allows us to 485d9e9a641SDave Hansen * have a single set_pgd() implementation that does not 486d9e9a641SDave Hansen * need to worry about whether it has 4k or 8k to work 487d9e9a641SDave Hansen * with. 488d9e9a641SDave Hansen * 489d9e9a641SDave Hansen * This ensures PGDs are 8k long: 490d9e9a641SDave Hansen */ 491d9e9a641SDave Hansen#define PTI_USER_PGD_FILL 512 492d9e9a641SDave Hansen/* This ensures they are 8k-aligned: */ 493b1bd27b9SJiri Slaby#define SYM_DATA_START_PTI_ALIGNED(name) \ 494b1bd27b9SJiri Slaby SYM_START(name, SYM_L_GLOBAL, .balign 2 * PAGE_SIZE) 495d9e9a641SDave Hansen#else 496b1bd27b9SJiri Slaby#define SYM_DATA_START_PTI_ALIGNED(name) \ 497b1bd27b9SJiri Slaby SYM_DATA_START_PAGE_ALIGNED(name) 498d9e9a641SDave Hansen#define PTI_USER_PGD_FILL 0 499d9e9a641SDave Hansen#endif 500d9e9a641SDave Hansen 501250c2277SThomas Gleixner/* Automate the creation of 1 to 1 mapping pmd entries */ 502250c2277SThomas Gleixner#define PMDS(START, PERM, COUNT) \ 503250c2277SThomas Gleixner i = 0 ; \ 504250c2277SThomas Gleixner .rept (COUNT) ; \ 5050e192b99SCyrill Gorcunov .quad (START) + (i << PMD_SHIFT) + (PERM) ; \ 506250c2277SThomas Gleixner i = i + 1 ; \ 507250c2277SThomas Gleixner .endr 508250c2277SThomas Gleixner 5098170e6beSH. Peter Anvin __INITDATA 5101a8770b7SJiri Slaby .balign 4 5111a8770b7SJiri Slaby 512b1bd27b9SJiri SlabySYM_DATA_START_PTI_ALIGNED(early_top_pgt) 5136f9dd329SKirill A. Shutemov .fill 512,8,0 514d9e9a641SDave Hansen .fill PTI_USER_PGD_FILL,8,0 515b1bd27b9SJiri SlabySYM_DATA_END(early_top_pgt) 5168170e6beSH. Peter Anvin 517b1bd27b9SJiri SlabySYM_DATA_START_PAGE_ALIGNED(early_dynamic_pgts) 5188170e6beSH. Peter Anvin .fill 512*EARLY_DYNAMIC_PAGE_TABLES,8,0 519b1bd27b9SJiri SlabySYM_DATA_END(early_dynamic_pgts) 5208170e6beSH. Peter Anvin 521b1bd27b9SJiri SlabySYM_DATA(early_recursion_flag, .long 0) 5221a8770b7SJiri Slaby 523b9af7c0dSSuresh Siddha .data 5248170e6beSH. Peter Anvin 5257733607fSMaran Wilson#if defined(CONFIG_XEN_PV) || defined(CONFIG_PVH) 526b1bd27b9SJiri SlabySYM_DATA_START_PTI_ALIGNED(init_top_pgt) 52721729f81STom Lendacky .quad level3_ident_pgt - __START_KERNEL_map + _KERNPG_TABLE_NOENC 528b9952ec7SKirill A. Shutemov .org init_top_pgt + L4_PAGE_OFFSET*8, 0 52921729f81STom Lendacky .quad level3_ident_pgt - __START_KERNEL_map + _KERNPG_TABLE_NOENC 530b9952ec7SKirill A. Shutemov .org init_top_pgt + L4_START_KERNEL*8, 0 531250c2277SThomas Gleixner /* (2^48-(2*1024*1024*1024))/(2^39) = 511 */ 53221729f81STom Lendacky .quad level3_kernel_pgt - __START_KERNEL_map + _PAGE_TABLE_NOENC 533d9e9a641SDave Hansen .fill PTI_USER_PGD_FILL,8,0 534b1bd27b9SJiri SlabySYM_DATA_END(init_top_pgt) 535250c2277SThomas Gleixner 536b1bd27b9SJiri SlabySYM_DATA_START_PAGE_ALIGNED(level3_ident_pgt) 53721729f81STom Lendacky .quad level2_ident_pgt - __START_KERNEL_map + _KERNPG_TABLE_NOENC 538250c2277SThomas Gleixner .fill 511, 8, 0 539b1bd27b9SJiri SlabySYM_DATA_END(level3_ident_pgt) 540b1bd27b9SJiri SlabySYM_DATA_START_PAGE_ALIGNED(level2_ident_pgt) 541430d4005SDave Hansen /* 542430d4005SDave Hansen * Since I easily can, map the first 1G. 5438170e6beSH. Peter Anvin * Don't set NX because code runs from these pages. 544430d4005SDave Hansen * 545430d4005SDave Hansen * Note: This sets _PAGE_GLOBAL despite whether 546430d4005SDave Hansen * the CPU supports it or it is enabled. But, 547430d4005SDave Hansen * the CPU should ignore the bit. 5488170e6beSH. Peter Anvin */ 5498170e6beSH. Peter Anvin PMDS(0, __PAGE_KERNEL_IDENT_LARGE_EXEC, PTRS_PER_PMD) 550b1bd27b9SJiri SlabySYM_DATA_END(level2_ident_pgt) 5514375c299SKirill A. Shutemov#else 552b1bd27b9SJiri SlabySYM_DATA_START_PTI_ALIGNED(init_top_pgt) 5534375c299SKirill A. Shutemov .fill 512,8,0 554d9e9a641SDave Hansen .fill PTI_USER_PGD_FILL,8,0 555b1bd27b9SJiri SlabySYM_DATA_END(init_top_pgt) 5568170e6beSH. Peter Anvin#endif 557250c2277SThomas Gleixner 558032370b9SKirill A. Shutemov#ifdef CONFIG_X86_5LEVEL 559b1bd27b9SJiri SlabySYM_DATA_START_PAGE_ALIGNED(level4_kernel_pgt) 560032370b9SKirill A. Shutemov .fill 511,8,0 56121729f81STom Lendacky .quad level3_kernel_pgt - __START_KERNEL_map + _PAGE_TABLE_NOENC 562b1bd27b9SJiri SlabySYM_DATA_END(level4_kernel_pgt) 563032370b9SKirill A. Shutemov#endif 564032370b9SKirill A. Shutemov 565b1bd27b9SJiri SlabySYM_DATA_START_PAGE_ALIGNED(level3_kernel_pgt) 566a6523748SEduardo Habkost .fill L3_START_KERNEL,8,0 567250c2277SThomas Gleixner /* (2^48-(2*1024*1024*1024)-((2^39)*511))/(2^30) = 510 */ 56821729f81STom Lendacky .quad level2_kernel_pgt - __START_KERNEL_map + _KERNPG_TABLE_NOENC 56921729f81STom Lendacky .quad level2_fixmap_pgt - __START_KERNEL_map + _PAGE_TABLE_NOENC 570b1bd27b9SJiri SlabySYM_DATA_END(level3_kernel_pgt) 571250c2277SThomas Gleixner 572b1bd27b9SJiri SlabySYM_DATA_START_PAGE_ALIGNED(level2_kernel_pgt) 57388f3aec7SIngo Molnar /* 574ea3186b9SArvind Sankar * Kernel high mapping. 57588f3aec7SIngo Molnar * 576ea3186b9SArvind Sankar * The kernel code+data+bss must be located below KERNEL_IMAGE_SIZE in 577ea3186b9SArvind Sankar * virtual address space, which is 1 GiB if RANDOMIZE_BASE is enabled, 578ea3186b9SArvind Sankar * 512 MiB otherwise. 57988f3aec7SIngo Molnar * 580ea3186b9SArvind Sankar * (NOTE: after that starts the module area, see MODULES_VADDR.) 581430d4005SDave Hansen * 582ea3186b9SArvind Sankar * This table is eventually used by the kernel during normal runtime. 583ea3186b9SArvind Sankar * Care must be taken to clear out undesired bits later, like _PAGE_RW 584ea3186b9SArvind Sankar * or _PAGE_GLOBAL in some cases. 58588f3aec7SIngo Molnar */ 586ea3186b9SArvind Sankar PMDS(0, __PAGE_KERNEL_LARGE_EXEC, KERNEL_IMAGE_SIZE/PMD_SIZE) 587b1bd27b9SJiri SlabySYM_DATA_END(level2_kernel_pgt) 588250c2277SThomas Gleixner 589b1bd27b9SJiri SlabySYM_DATA_START_PAGE_ALIGNED(level2_fixmap_pgt) 59005ab1d8aSFeng Tang .fill (512 - 4 - FIXMAP_PMD_NUM),8,0 59105ab1d8aSFeng Tang pgtno = 0 59205ab1d8aSFeng Tang .rept (FIXMAP_PMD_NUM) 59305ab1d8aSFeng Tang .quad level1_fixmap_pgt + (pgtno << PAGE_SHIFT) - __START_KERNEL_map \ 59405ab1d8aSFeng Tang + _PAGE_TABLE_NOENC; 59505ab1d8aSFeng Tang pgtno = pgtno + 1 59605ab1d8aSFeng Tang .endr 59705ab1d8aSFeng Tang /* 6 MB reserved space + a 2MB hole */ 59805ab1d8aSFeng Tang .fill 4,8,0 599b1bd27b9SJiri SlabySYM_DATA_END(level2_fixmap_pgt) 6008170e6beSH. Peter Anvin 601b1bd27b9SJiri SlabySYM_DATA_START_PAGE_ALIGNED(level1_fixmap_pgt) 60205ab1d8aSFeng Tang .rept (FIXMAP_PMD_NUM) 603250c2277SThomas Gleixner .fill 512,8,0 60405ab1d8aSFeng Tang .endr 605b1bd27b9SJiri SlabySYM_DATA_END(level1_fixmap_pgt) 606250c2277SThomas Gleixner 607250c2277SThomas Gleixner#undef PMDS 608250c2277SThomas Gleixner 609250c2277SThomas Gleixner .data 610250c2277SThomas Gleixner .align 16 611250c2277SThomas Gleixner 612b1bd27b9SJiri SlabySYM_DATA(early_gdt_descr, .word GDT_ENTRIES*8-1) 613b1bd27b9SJiri SlabySYM_DATA_LOCAL(early_gdt_descr_base, .quad INIT_PER_CPU_VAR(gdt_page)) 614b1bd27b9SJiri Slaby 615b1bd27b9SJiri Slaby .align 16 616250c2277SThomas Gleixner/* This must match the first entry in level2_kernel_pgt */ 617b1bd27b9SJiri SlabySYM_DATA(phys_base, .quad 0x0) 618784d5699SAl ViroEXPORT_SYMBOL(phys_base) 619250c2277SThomas Gleixner 6208c5e5ac3SJeremy Fitzhardinge#include "../../x86/xen/xen-head.S" 621250c2277SThomas Gleixner 62202b7da37STim Abbott __PAGE_ALIGNED_BSS 623b1bd27b9SJiri SlabySYM_DATA_START_PAGE_ALIGNED(empty_zero_page) 624250c2277SThomas Gleixner .skip PAGE_SIZE 625b1bd27b9SJiri SlabySYM_DATA_END(empty_zero_page) 626784d5699SAl ViroEXPORT_SYMBOL(empty_zero_page) 627ef7f0d6aSAndrey Ryabinin 628