1b2441318SGreg Kroah-Hartman/* SPDX-License-Identifier: GPL-2.0 */ 2250c2277SThomas Gleixner/* 35b171e82SAlexander Kuleshov * linux/arch/x86/kernel/head_64.S -- start in 32bit and switch to 64bit 4250c2277SThomas Gleixner * 5250c2277SThomas Gleixner * Copyright (C) 2000 Andrea Arcangeli <andrea@suse.de> SuSE 6250c2277SThomas Gleixner * Copyright (C) 2000 Pavel Machek <pavel@suse.cz> 7250c2277SThomas Gleixner * Copyright (C) 2000 Karsten Keil <kkeil@suse.de> 8250c2277SThomas Gleixner * Copyright (C) 2001,2002 Andi Kleen <ak@suse.de> 9250c2277SThomas Gleixner * Copyright (C) 2005 Eric Biederman <ebiederm@xmission.com> 10250c2277SThomas Gleixner */ 11250c2277SThomas Gleixner 12250c2277SThomas Gleixner 13250c2277SThomas Gleixner#include <linux/linkage.h> 14250c2277SThomas Gleixner#include <linux/threads.h> 15250c2277SThomas Gleixner#include <linux/init.h> 16250c2277SThomas Gleixner#include <asm/segment.h> 17250c2277SThomas Gleixner#include <asm/pgtable.h> 18250c2277SThomas Gleixner#include <asm/page.h> 19250c2277SThomas Gleixner#include <asm/msr.h> 20250c2277SThomas Gleixner#include <asm/cache.h> 21369101daSCyrill Gorcunov#include <asm/processor-flags.h> 22b12d8db8STejun Heo#include <asm/percpu.h> 239900aa2fSH. Peter Anvin#include <asm/nops.h> 247bbcdb1cSAndy Lutomirski#include "../entry/calling.h" 25784d5699SAl Viro#include <asm/export.h> 26bd89004fSPeter Zijlstra#include <asm/nospec-branch.h> 27250c2277SThomas Gleixner 2849a69787SGlauber de Oliveira Costa#ifdef CONFIG_PARAVIRT 2949a69787SGlauber de Oliveira Costa#include <asm/asm-offsets.h> 3049a69787SGlauber de Oliveira Costa#include <asm/paravirt.h> 31ffc4bc9cSH. Peter Anvin#define GET_CR2_INTO(reg) GET_CR2_INTO_RAX ; movq %rax, reg 3249a69787SGlauber de Oliveira Costa#else 33ffc4bc9cSH. Peter Anvin#define GET_CR2_INTO(reg) movq %cr2, reg 349900aa2fSH. Peter Anvin#define INTERRUPT_RETURN iretq 3549a69787SGlauber de Oliveira Costa#endif 3649a69787SGlauber de Oliveira Costa 373ad2f3fbSDaniel Mack/* we are not able to switch in one step to the final KERNEL ADDRESS SPACE 38250c2277SThomas Gleixner * because we need identity-mapped pages. 39250c2277SThomas Gleixner * 40250c2277SThomas Gleixner */ 41250c2277SThomas Gleixner 42b9952ec7SKirill A. Shutemov#define l4_index(x) (((x) >> 39) & 511) 43a6523748SEduardo Habkost#define pud_index(x) (((x) >> PUD_SHIFT) & (PTRS_PER_PUD-1)) 44a6523748SEduardo Habkost 45b9952ec7SKirill A. ShutemovL4_PAGE_OFFSET = l4_index(__PAGE_OFFSET_BASE_L4) 46b9952ec7SKirill A. ShutemovL4_START_KERNEL = l4_index(__START_KERNEL_map) 47b9952ec7SKirill A. Shutemov 48a6523748SEduardo HabkostL3_START_KERNEL = pud_index(__START_KERNEL_map) 49a6523748SEduardo Habkost 50250c2277SThomas Gleixner .text 514ae59b91STim Abbott __HEAD 52250c2277SThomas Gleixner .code64 53250c2277SThomas Gleixner .globl startup_64 54250c2277SThomas Gleixnerstartup_64: 552704fbb6SJosh Poimboeuf UNWIND_HINT_EMPTY 56250c2277SThomas Gleixner /* 571256276cSKonrad Rzeszutek Wilk * At this point the CPU runs in 64bit mode CS.L = 1 CS.D = 0, 58250c2277SThomas Gleixner * and someone has loaded an identity mapped page table 59250c2277SThomas Gleixner * for us. These identity mapped page tables map all of the 60250c2277SThomas Gleixner * kernel pages and possibly all of memory. 61250c2277SThomas Gleixner * 628170e6beSH. Peter Anvin * %rsi holds a physical pointer to real_mode_data. 63250c2277SThomas Gleixner * 64250c2277SThomas Gleixner * We come here either directly from a 64bit bootloader, or from 655b171e82SAlexander Kuleshov * arch/x86/boot/compressed/head_64.S. 66250c2277SThomas Gleixner * 67250c2277SThomas Gleixner * We only come here initially at boot nothing else comes here. 68250c2277SThomas Gleixner * 69250c2277SThomas Gleixner * Since we may be loaded at an address different from what we were 70250c2277SThomas Gleixner * compiled to run at we first fixup the physical addresses in our page 71250c2277SThomas Gleixner * tables and then reload them. 72250c2277SThomas Gleixner */ 73250c2277SThomas Gleixner 7422dc3918SJosh Poimboeuf /* Set up the stack for verify_cpu(), similar to initial_stack below */ 7522dc3918SJosh Poimboeuf leaq (__end_init_task - SIZEOF_PTREGS)(%rip), %rsp 7691ed140dSBorislav Petkov 7704633df0SBorislav Petkov /* Sanitize CPU configuration */ 7804633df0SBorislav Petkov call verify_cpu 7904633df0SBorislav Petkov 805868f365STom Lendacky /* 815868f365STom Lendacky * Perform pagetable fixups. Additionally, if SME is active, encrypt 825868f365STom Lendacky * the kernel and retrieve the modifier (SME encryption mask if SME 835868f365STom Lendacky * is active) to be added to the initial pgdir entry that will be 845868f365STom Lendacky * programmed into CR3. 855868f365STom Lendacky */ 86250c2277SThomas Gleixner leaq _text(%rip), %rdi 87c88d7150SKirill A. Shutemov pushq %rsi 88c88d7150SKirill A. Shutemov call __startup_64 89c88d7150SKirill A. Shutemov popq %rsi 90250c2277SThomas Gleixner 915868f365STom Lendacky /* Form the CR3 value being sure to include the CR3 modifier */ 925868f365STom Lendacky addq $(early_top_pgt - __START_KERNEL_map), %rax 938170e6beSH. Peter Anvin jmp 1f 94250c2277SThomas GleixnerENTRY(secondary_startup_64) 952704fbb6SJosh Poimboeuf UNWIND_HINT_EMPTY 96250c2277SThomas Gleixner /* 971256276cSKonrad Rzeszutek Wilk * At this point the CPU runs in 64bit mode CS.L = 1 CS.D = 0, 98250c2277SThomas Gleixner * and someone has loaded a mapped page table. 99250c2277SThomas Gleixner * 1008170e6beSH. Peter Anvin * %rsi holds a physical pointer to real_mode_data. 101250c2277SThomas Gleixner * 102250c2277SThomas Gleixner * We come here either from startup_64 (using physical addresses) 103250c2277SThomas Gleixner * or from trampoline.S (using virtual addresses). 104250c2277SThomas Gleixner * 105250c2277SThomas Gleixner * Using virtual addresses from trampoline.S removes the need 106250c2277SThomas Gleixner * to have any identity mapped pages in the kernel page table 107250c2277SThomas Gleixner * after the boot processor executes this code. 108250c2277SThomas Gleixner */ 109250c2277SThomas Gleixner 11004633df0SBorislav Petkov /* Sanitize CPU configuration */ 11104633df0SBorislav Petkov call verify_cpu 11204633df0SBorislav Petkov 1135868f365STom Lendacky /* 1145868f365STom Lendacky * Retrieve the modifier (SME encryption mask if SME is active) to be 1155868f365STom Lendacky * added to the initial pgdir entry that will be programmed into CR3. 1165868f365STom Lendacky */ 1175868f365STom Lendacky pushq %rsi 1185868f365STom Lendacky call __startup_secondary_64 1195868f365STom Lendacky popq %rsi 1205868f365STom Lendacky 1215868f365STom Lendacky /* Form the CR3 value being sure to include the CR3 modifier */ 1225868f365STom Lendacky addq $(init_top_pgt - __START_KERNEL_map), %rax 1238170e6beSH. Peter Anvin1: 1248170e6beSH. Peter Anvin 125032370b9SKirill A. Shutemov /* Enable PAE mode, PGE and LA57 */ 1268170e6beSH. Peter Anvin movl $(X86_CR4_PAE | X86_CR4_PGE), %ecx 127032370b9SKirill A. Shutemov#ifdef CONFIG_X86_5LEVEL 12839b95522SKirill A. Shutemov testl $1, __pgtable_l5_enabled(%rip) 1296f9dd329SKirill A. Shutemov jz 1f 130032370b9SKirill A. Shutemov orl $X86_CR4_LA57, %ecx 1316f9dd329SKirill A. Shutemov1: 132032370b9SKirill A. Shutemov#endif 1338170e6beSH. Peter Anvin movq %rcx, %cr4 134250c2277SThomas Gleixner 135032370b9SKirill A. Shutemov /* Setup early boot stage 4-/5-level pagetables. */ 136250c2277SThomas Gleixner addq phys_base(%rip), %rax 137250c2277SThomas Gleixner movq %rax, %cr3 138250c2277SThomas Gleixner 139250c2277SThomas Gleixner /* Ensure I am executing from virtual addresses */ 140250c2277SThomas Gleixner movq $1f, %rax 141bd89004fSPeter Zijlstra ANNOTATE_RETPOLINE_SAFE 142250c2277SThomas Gleixner jmp *%rax 143250c2277SThomas Gleixner1: 1442704fbb6SJosh Poimboeuf UNWIND_HINT_EMPTY 145250c2277SThomas Gleixner 146250c2277SThomas Gleixner /* Check if nx is implemented */ 147250c2277SThomas Gleixner movl $0x80000001, %eax 148250c2277SThomas Gleixner cpuid 149250c2277SThomas Gleixner movl %edx,%edi 150250c2277SThomas Gleixner 151250c2277SThomas Gleixner /* Setup EFER (Extended Feature Enable Register) */ 152250c2277SThomas Gleixner movl $MSR_EFER, %ecx 153250c2277SThomas Gleixner rdmsr 154250c2277SThomas Gleixner btsl $_EFER_SCE, %eax /* Enable System Call */ 155250c2277SThomas Gleixner btl $20,%edi /* No Execute supported? */ 156250c2277SThomas Gleixner jnc 1f 157250c2277SThomas Gleixner btsl $_EFER_NX, %eax 15878d77df7SH. Peter Anvin btsq $_PAGE_BIT_NX,early_pmd_flags(%rip) 159250c2277SThomas Gleixner1: wrmsr /* Make changes effective */ 160250c2277SThomas Gleixner 161250c2277SThomas Gleixner /* Setup cr0 */ 162369101daSCyrill Gorcunov movl $CR0_STATE, %eax 163250c2277SThomas Gleixner /* Make changes effective */ 164250c2277SThomas Gleixner movq %rax, %cr0 165250c2277SThomas Gleixner 166250c2277SThomas Gleixner /* Setup a boot time stack */ 167b32f96c7SJosh Poimboeuf movq initial_stack(%rip), %rsp 168250c2277SThomas Gleixner 169250c2277SThomas Gleixner /* zero EFLAGS after setting rsp */ 170250c2277SThomas Gleixner pushq $0 171250c2277SThomas Gleixner popfq 172250c2277SThomas Gleixner 173250c2277SThomas Gleixner /* 174250c2277SThomas Gleixner * We must switch to a new descriptor in kernel space for the GDT 175250c2277SThomas Gleixner * because soon the kernel won't have access anymore to the userspace 176250c2277SThomas Gleixner * addresses where we're currently running on. We have to do that here 177250c2277SThomas Gleixner * because in 32bit we couldn't load a 64bit linear address. 178250c2277SThomas Gleixner */ 179a939098aSGlauber Costa lgdt early_gdt_descr(%rip) 180250c2277SThomas Gleixner 1818ec6993dSBrian Gerst /* set up data segments */ 1828ec6993dSBrian Gerst xorl %eax,%eax 183250c2277SThomas Gleixner movl %eax,%ds 184250c2277SThomas Gleixner movl %eax,%ss 185250c2277SThomas Gleixner movl %eax,%es 186250c2277SThomas Gleixner 187250c2277SThomas Gleixner /* 188250c2277SThomas Gleixner * We don't really need to load %fs or %gs, but load them anyway 189250c2277SThomas Gleixner * to kill any stale realmode selectors. This allows execution 190250c2277SThomas Gleixner * under VT hardware. 191250c2277SThomas Gleixner */ 192250c2277SThomas Gleixner movl %eax,%fs 193250c2277SThomas Gleixner movl %eax,%gs 194250c2277SThomas Gleixner 195f32ff538STejun Heo /* Set up %gs. 196f32ff538STejun Heo * 197947e76cdSBrian Gerst * The base of %gs always points to the bottom of the irqstack 198947e76cdSBrian Gerst * union. If the stack protector canary is enabled, it is 199947e76cdSBrian Gerst * located at %gs:40. Note that, on SMP, the boot cpu uses 200947e76cdSBrian Gerst * init data section till per cpu areas are set up. 201250c2277SThomas Gleixner */ 202250c2277SThomas Gleixner movl $MSR_GS_BASE,%ecx 203650fb439SBrian Gerst movl initial_gs(%rip),%eax 204650fb439SBrian Gerst movl initial_gs+4(%rip),%edx 205250c2277SThomas Gleixner wrmsr 206250c2277SThomas Gleixner 2078170e6beSH. Peter Anvin /* rsi is pointer to real mode structure with interesting info. 208250c2277SThomas Gleixner pass it to C */ 2098170e6beSH. Peter Anvin movq %rsi, %rdi 210250c2277SThomas Gleixner 21179d243a0SBorislav Petkov.Ljump_to_C_code: 212a9468df5SJosh Poimboeuf /* 213a9468df5SJosh Poimboeuf * Jump to run C code and to be on a real kernel address. 214250c2277SThomas Gleixner * Since we are running on identity-mapped space we have to jump 215250c2277SThomas Gleixner * to the full 64bit address, this is only possible as indirect 216250c2277SThomas Gleixner * jump. In addition we need to ensure %cs is set so we make this 217250c2277SThomas Gleixner * a far return. 2188170e6beSH. Peter Anvin * 2198170e6beSH. Peter Anvin * Note: do not change to far jump indirect with 64bit offset. 2208170e6beSH. Peter Anvin * 2218170e6beSH. Peter Anvin * AMD does not support far jump indirect with 64bit offset. 2228170e6beSH. Peter Anvin * AMD64 Architecture Programmer's Manual, Volume 3: states only 2238170e6beSH. Peter Anvin * JMP FAR mem16:16 FF /5 Far jump indirect, 2248170e6beSH. Peter Anvin * with the target specified by a far pointer in memory. 2258170e6beSH. Peter Anvin * JMP FAR mem16:32 FF /5 Far jump indirect, 2268170e6beSH. Peter Anvin * with the target specified by a far pointer in memory. 2278170e6beSH. Peter Anvin * 2288170e6beSH. Peter Anvin * Intel64 does support 64bit offset. 2298170e6beSH. Peter Anvin * Software Developer Manual Vol 2: states: 2308170e6beSH. Peter Anvin * FF /5 JMP m16:16 Jump far, absolute indirect, 2318170e6beSH. Peter Anvin * address given in m16:16 2328170e6beSH. Peter Anvin * FF /5 JMP m16:32 Jump far, absolute indirect, 2338170e6beSH. Peter Anvin * address given in m16:32. 2348170e6beSH. Peter Anvin * REX.W + FF /5 JMP m16:64 Jump far, absolute indirect, 2358170e6beSH. Peter Anvin * address given in m16:64. 236250c2277SThomas Gleixner */ 23731dcfec1SJosh Poimboeuf pushq $.Lafter_lret # put return address on stack for unwinder 238a7bea830SJan Beulich xorl %ebp, %ebp # clear frame pointer 239250c2277SThomas Gleixner movq initial_code(%rip), %rax 240250c2277SThomas Gleixner pushq $__KERNEL_CS # set correct cs 241250c2277SThomas Gleixner pushq %rax # target address in negative space 242250c2277SThomas Gleixner lretq 24331dcfec1SJosh Poimboeuf.Lafter_lret: 244015a2ea5SJosh PoimboeufEND(secondary_startup_64) 245250c2277SThomas Gleixner 24604633df0SBorislav Petkov#include "verify_cpu.S" 24704633df0SBorislav Petkov 24842e78e97SFenghua Yu#ifdef CONFIG_HOTPLUG_CPU 24942e78e97SFenghua Yu/* 25042e78e97SFenghua Yu * Boot CPU0 entry point. It's called from play_dead(). Everything has been set 25142e78e97SFenghua Yu * up already except stack. We just set up stack here. Then call 25279d243a0SBorislav Petkov * start_secondary() via .Ljump_to_C_code. 25342e78e97SFenghua Yu */ 25442e78e97SFenghua YuENTRY(start_cpu0) 255b32f96c7SJosh Poimboeuf movq initial_stack(%rip), %rsp 2562704fbb6SJosh Poimboeuf UNWIND_HINT_EMPTY 25779d243a0SBorislav Petkov jmp .Ljump_to_C_code 25842e78e97SFenghua YuENDPROC(start_cpu0) 25942e78e97SFenghua Yu#endif 26042e78e97SFenghua Yu 261b32f96c7SJosh Poimboeuf /* Both SMP bootup and ACPI suspend change these variables */ 262da5968aeSSam Ravnborg __REFDATA 2638170e6beSH. Peter Anvin .balign 8 2648170e6beSH. Peter Anvin GLOBAL(initial_code) 265250c2277SThomas Gleixner .quad x86_64_start_kernel 2668170e6beSH. Peter Anvin GLOBAL(initial_gs) 2672add8e23SBrian Gerst .quad INIT_PER_CPU_VAR(irq_stack_union) 268b32f96c7SJosh Poimboeuf GLOBAL(initial_stack) 26922dc3918SJosh Poimboeuf /* 27022dc3918SJosh Poimboeuf * The SIZEOF_PTREGS gap is a convention which helps the in-kernel 27122dc3918SJosh Poimboeuf * unwinder reliably detect the end of the stack. 27222dc3918SJosh Poimboeuf */ 27322dc3918SJosh Poimboeuf .quad init_thread_union + THREAD_SIZE - SIZEOF_PTREGS 274b9af7c0dSSuresh Siddha __FINITDATA 275250c2277SThomas Gleixner 2768170e6beSH. Peter Anvin __INIT 277cdeb6048SAndy LutomirskiENTRY(early_idt_handler_array) 278749c970aSAndi Kleen i = 0 279749c970aSAndi Kleen .rept NUM_EXCEPTION_VECTORS 28082c62fa0SJosh Poimboeuf .if ((EXCEPTION_ERRCODE_MASK >> i) & 1) == 0 2812704fbb6SJosh Poimboeuf UNWIND_HINT_IRET_REGS 2829900aa2fSH. Peter Anvin pushq $0 # Dummy error code, to make stack frame uniform 2832704fbb6SJosh Poimboeuf .else 2842704fbb6SJosh Poimboeuf UNWIND_HINT_IRET_REGS offset=8 2859900aa2fSH. Peter Anvin .endif 2869900aa2fSH. Peter Anvin pushq $i # 72(%rsp) Vector number 287cdeb6048SAndy Lutomirski jmp early_idt_handler_common 2882704fbb6SJosh Poimboeuf UNWIND_HINT_IRET_REGS 289749c970aSAndi Kleen i = i + 1 290cdeb6048SAndy Lutomirski .fill early_idt_handler_array + i*EARLY_IDT_HANDLER_SIZE - ., 1, 0xcc 291749c970aSAndi Kleen .endr 2922704fbb6SJosh Poimboeuf UNWIND_HINT_IRET_REGS offset=16 293015a2ea5SJosh PoimboeufEND(early_idt_handler_array) 2948866cd9dSRoland McGrath 295cdeb6048SAndy Lutomirskiearly_idt_handler_common: 296cdeb6048SAndy Lutomirski /* 297cdeb6048SAndy Lutomirski * The stack is the hardware frame, an error code or zero, and the 298cdeb6048SAndy Lutomirski * vector number. 299cdeb6048SAndy Lutomirski */ 3009900aa2fSH. Peter Anvin cld 3019900aa2fSH. Peter Anvin 302250c2277SThomas Gleixner incl early_recursion_flag(%rip) 3039900aa2fSH. Peter Anvin 3047bbcdb1cSAndy Lutomirski /* The vector number is currently in the pt_regs->di slot. */ 3057bbcdb1cSAndy Lutomirski pushq %rsi /* pt_regs->si */ 3067bbcdb1cSAndy Lutomirski movq 8(%rsp), %rsi /* RSI = vector number */ 3077bbcdb1cSAndy Lutomirski movq %rdi, 8(%rsp) /* pt_regs->di = RDI */ 3087bbcdb1cSAndy Lutomirski pushq %rdx /* pt_regs->dx */ 3097bbcdb1cSAndy Lutomirski pushq %rcx /* pt_regs->cx */ 3107bbcdb1cSAndy Lutomirski pushq %rax /* pt_regs->ax */ 3117bbcdb1cSAndy Lutomirski pushq %r8 /* pt_regs->r8 */ 3127bbcdb1cSAndy Lutomirski pushq %r9 /* pt_regs->r9 */ 3137bbcdb1cSAndy Lutomirski pushq %r10 /* pt_regs->r10 */ 3147bbcdb1cSAndy Lutomirski pushq %r11 /* pt_regs->r11 */ 3157bbcdb1cSAndy Lutomirski pushq %rbx /* pt_regs->bx */ 3167bbcdb1cSAndy Lutomirski pushq %rbp /* pt_regs->bp */ 3177bbcdb1cSAndy Lutomirski pushq %r12 /* pt_regs->r12 */ 3187bbcdb1cSAndy Lutomirski pushq %r13 /* pt_regs->r13 */ 3197bbcdb1cSAndy Lutomirski pushq %r14 /* pt_regs->r14 */ 3207bbcdb1cSAndy Lutomirski pushq %r15 /* pt_regs->r15 */ 3212704fbb6SJosh Poimboeuf UNWIND_HINT_REGS 3229900aa2fSH. Peter Anvin 3237bbcdb1cSAndy Lutomirski cmpq $14,%rsi /* Page fault? */ 3248170e6beSH. Peter Anvin jnz 10f 3257bbcdb1cSAndy Lutomirski GET_CR2_INTO(%rdi) /* Can clobber any volatile register if pv */ 3268170e6beSH. Peter Anvin call early_make_pgtable 3278170e6beSH. Peter Anvin andl %eax,%eax 3287bbcdb1cSAndy Lutomirski jz 20f /* All good */ 3298170e6beSH. Peter Anvin 3308170e6beSH. Peter Anvin10: 3317bbcdb1cSAndy Lutomirski movq %rsp,%rdi /* RDI = pt_regs; RSI is already trapnr */ 3329900aa2fSH. Peter Anvin call early_fixup_exception 3339900aa2fSH. Peter Anvin 3340e861fbbSAndy Lutomirski20: 3359900aa2fSH. Peter Anvin decl early_recursion_flag(%rip) 33626c4ef9cSAndy Lutomirski jmp restore_regs_and_return_to_kernel 337015a2ea5SJosh PoimboeufEND(early_idt_handler_common) 3389900aa2fSH. Peter Anvin 3398170e6beSH. Peter Anvin __INITDATA 3408170e6beSH. Peter Anvin 3419900aa2fSH. Peter Anvin .balign 4 3420e861fbbSAndy LutomirskiGLOBAL(early_recursion_flag) 343250c2277SThomas Gleixner .long 0 344250c2277SThomas Gleixner 345250c2277SThomas Gleixner#define NEXT_PAGE(name) \ 346250c2277SThomas Gleixner .balign PAGE_SIZE; \ 3478170e6beSH. Peter AnvinGLOBAL(name) 348250c2277SThomas Gleixner 349d9e9a641SDave Hansen#ifdef CONFIG_PAGE_TABLE_ISOLATION 350d9e9a641SDave Hansen/* 351d9e9a641SDave Hansen * Each PGD needs to be 8k long and 8k aligned. We do not 352d9e9a641SDave Hansen * ever go out to userspace with these, so we do not 353d9e9a641SDave Hansen * strictly *need* the second page, but this allows us to 354d9e9a641SDave Hansen * have a single set_pgd() implementation that does not 355d9e9a641SDave Hansen * need to worry about whether it has 4k or 8k to work 356d9e9a641SDave Hansen * with. 357d9e9a641SDave Hansen * 358d9e9a641SDave Hansen * This ensures PGDs are 8k long: 359d9e9a641SDave Hansen */ 360d9e9a641SDave Hansen#define PTI_USER_PGD_FILL 512 361d9e9a641SDave Hansen/* This ensures they are 8k-aligned: */ 362d9e9a641SDave Hansen#define NEXT_PGD_PAGE(name) \ 363d9e9a641SDave Hansen .balign 2 * PAGE_SIZE; \ 364d9e9a641SDave HansenGLOBAL(name) 365d9e9a641SDave Hansen#else 366d9e9a641SDave Hansen#define NEXT_PGD_PAGE(name) NEXT_PAGE(name) 367d9e9a641SDave Hansen#define PTI_USER_PGD_FILL 0 368d9e9a641SDave Hansen#endif 369d9e9a641SDave Hansen 370250c2277SThomas Gleixner/* Automate the creation of 1 to 1 mapping pmd entries */ 371250c2277SThomas Gleixner#define PMDS(START, PERM, COUNT) \ 372250c2277SThomas Gleixner i = 0 ; \ 373250c2277SThomas Gleixner .rept (COUNT) ; \ 3740e192b99SCyrill Gorcunov .quad (START) + (i << PMD_SHIFT) + (PERM) ; \ 375250c2277SThomas Gleixner i = i + 1 ; \ 376250c2277SThomas Gleixner .endr 377250c2277SThomas Gleixner 3788170e6beSH. Peter Anvin __INITDATA 379d9e9a641SDave HansenNEXT_PGD_PAGE(early_top_pgt) 3806f9dd329SKirill A. Shutemov .fill 512,8,0 381d9e9a641SDave Hansen .fill PTI_USER_PGD_FILL,8,0 3828170e6beSH. Peter Anvin 3838170e6beSH. Peter AnvinNEXT_PAGE(early_dynamic_pgts) 3848170e6beSH. Peter Anvin .fill 512*EARLY_DYNAMIC_PAGE_TABLES,8,0 3858170e6beSH. Peter Anvin 386b9af7c0dSSuresh Siddha .data 3878170e6beSH. Peter Anvin 3884375c299SKirill A. Shutemov#if defined(CONFIG_XEN_PV) || defined(CONFIG_XEN_PVH) 389d9e9a641SDave HansenNEXT_PGD_PAGE(init_top_pgt) 39021729f81STom Lendacky .quad level3_ident_pgt - __START_KERNEL_map + _KERNPG_TABLE_NOENC 391b9952ec7SKirill A. Shutemov .org init_top_pgt + L4_PAGE_OFFSET*8, 0 39221729f81STom Lendacky .quad level3_ident_pgt - __START_KERNEL_map + _KERNPG_TABLE_NOENC 393b9952ec7SKirill A. Shutemov .org init_top_pgt + L4_START_KERNEL*8, 0 394250c2277SThomas Gleixner /* (2^48-(2*1024*1024*1024))/(2^39) = 511 */ 39521729f81STom Lendacky .quad level3_kernel_pgt - __START_KERNEL_map + _PAGE_TABLE_NOENC 396d9e9a641SDave Hansen .fill PTI_USER_PGD_FILL,8,0 397250c2277SThomas Gleixner 398250c2277SThomas GleixnerNEXT_PAGE(level3_ident_pgt) 39921729f81STom Lendacky .quad level2_ident_pgt - __START_KERNEL_map + _KERNPG_TABLE_NOENC 400250c2277SThomas Gleixner .fill 511, 8, 0 4018170e6beSH. Peter AnvinNEXT_PAGE(level2_ident_pgt) 402430d4005SDave Hansen /* 403430d4005SDave Hansen * Since I easily can, map the first 1G. 4048170e6beSH. Peter Anvin * Don't set NX because code runs from these pages. 405430d4005SDave Hansen * 406430d4005SDave Hansen * Note: This sets _PAGE_GLOBAL despite whether 407430d4005SDave Hansen * the CPU supports it or it is enabled. But, 408430d4005SDave Hansen * the CPU should ignore the bit. 4098170e6beSH. Peter Anvin */ 4108170e6beSH. Peter Anvin PMDS(0, __PAGE_KERNEL_IDENT_LARGE_EXEC, PTRS_PER_PMD) 4114375c299SKirill A. Shutemov#else 412d9e9a641SDave HansenNEXT_PGD_PAGE(init_top_pgt) 4134375c299SKirill A. Shutemov .fill 512,8,0 414d9e9a641SDave Hansen .fill PTI_USER_PGD_FILL,8,0 4158170e6beSH. Peter Anvin#endif 416250c2277SThomas Gleixner 417032370b9SKirill A. Shutemov#ifdef CONFIG_X86_5LEVEL 418032370b9SKirill A. ShutemovNEXT_PAGE(level4_kernel_pgt) 419032370b9SKirill A. Shutemov .fill 511,8,0 42021729f81STom Lendacky .quad level3_kernel_pgt - __START_KERNEL_map + _PAGE_TABLE_NOENC 421032370b9SKirill A. Shutemov#endif 422032370b9SKirill A. Shutemov 423250c2277SThomas GleixnerNEXT_PAGE(level3_kernel_pgt) 424a6523748SEduardo Habkost .fill L3_START_KERNEL,8,0 425250c2277SThomas Gleixner /* (2^48-(2*1024*1024*1024)-((2^39)*511))/(2^30) = 510 */ 42621729f81STom Lendacky .quad level2_kernel_pgt - __START_KERNEL_map + _KERNPG_TABLE_NOENC 42721729f81STom Lendacky .quad level2_fixmap_pgt - __START_KERNEL_map + _PAGE_TABLE_NOENC 428250c2277SThomas Gleixner 429250c2277SThomas GleixnerNEXT_PAGE(level2_kernel_pgt) 43088f3aec7SIngo Molnar /* 43185eb69a1SIngo Molnar * 512 MB kernel mapping. We spend a full page on this pagetable 43288f3aec7SIngo Molnar * anyway. 43388f3aec7SIngo Molnar * 43488f3aec7SIngo Molnar * The kernel code+data+bss must not be bigger than that. 43588f3aec7SIngo Molnar * 43685eb69a1SIngo Molnar * (NOTE: at +512MB starts the module area, see MODULES_VADDR. 43788f3aec7SIngo Molnar * If you want to increase this then increase MODULES_VADDR 43888f3aec7SIngo Molnar * too.) 439430d4005SDave Hansen * 440430d4005SDave Hansen * This table is eventually used by the kernel during normal 441430d4005SDave Hansen * runtime. Care must be taken to clear out undesired bits 442430d4005SDave Hansen * later, like _PAGE_RW or _PAGE_GLOBAL in some cases. 44388f3aec7SIngo Molnar */ 4448490638cSJeremy Fitzhardinge PMDS(0, __PAGE_KERNEL_LARGE_EXEC, 445d4afe414SIngo Molnar KERNEL_IMAGE_SIZE/PMD_SIZE) 446250c2277SThomas Gleixner 4478170e6beSH. Peter AnvinNEXT_PAGE(level2_fixmap_pgt) 4488170e6beSH. Peter Anvin .fill 506,8,0 44921729f81STom Lendacky .quad level1_fixmap_pgt - __START_KERNEL_map + _PAGE_TABLE_NOENC 4508170e6beSH. Peter Anvin /* 8MB reserved for vsyscalls + a 2MB hole = 4 + 1 entries */ 4518170e6beSH. Peter Anvin .fill 5,8,0 4528170e6beSH. Peter Anvin 4538170e6beSH. Peter AnvinNEXT_PAGE(level1_fixmap_pgt) 454250c2277SThomas Gleixner .fill 512,8,0 455250c2277SThomas Gleixner 456250c2277SThomas Gleixner#undef PMDS 457250c2277SThomas Gleixner 458250c2277SThomas Gleixner .data 459250c2277SThomas Gleixner .align 16 460a939098aSGlauber Costa .globl early_gdt_descr 461a939098aSGlauber Costaearly_gdt_descr: 462a939098aSGlauber Costa .word GDT_ENTRIES*8-1 4633e5d8f97STejun Heoearly_gdt_descr_base: 4642add8e23SBrian Gerst .quad INIT_PER_CPU_VAR(gdt_page) 465250c2277SThomas Gleixner 466250c2277SThomas GleixnerENTRY(phys_base) 467250c2277SThomas Gleixner /* This must match the first entry in level2_kernel_pgt */ 468250c2277SThomas Gleixner .quad 0x0000000000000000 469784d5699SAl ViroEXPORT_SYMBOL(phys_base) 470250c2277SThomas Gleixner 4718c5e5ac3SJeremy Fitzhardinge#include "../../x86/xen/xen-head.S" 472250c2277SThomas Gleixner 47302b7da37STim Abbott __PAGE_ALIGNED_BSS 4748170e6beSH. Peter AnvinNEXT_PAGE(empty_zero_page) 475250c2277SThomas Gleixner .skip PAGE_SIZE 476784d5699SAl ViroEXPORT_SYMBOL(empty_zero_page) 477ef7f0d6aSAndrey Ryabinin 478