1250c2277SThomas Gleixner/* 2250c2277SThomas Gleixner * linux/arch/x86_64/kernel/head.S -- start in 32bit and switch to 64bit 3250c2277SThomas Gleixner * 4250c2277SThomas Gleixner * Copyright (C) 2000 Andrea Arcangeli <andrea@suse.de> SuSE 5250c2277SThomas Gleixner * Copyright (C) 2000 Pavel Machek <pavel@suse.cz> 6250c2277SThomas Gleixner * Copyright (C) 2000 Karsten Keil <kkeil@suse.de> 7250c2277SThomas Gleixner * Copyright (C) 2001,2002 Andi Kleen <ak@suse.de> 8250c2277SThomas Gleixner * Copyright (C) 2005 Eric Biederman <ebiederm@xmission.com> 9250c2277SThomas Gleixner */ 10250c2277SThomas Gleixner 11250c2277SThomas Gleixner 12250c2277SThomas Gleixner#include <linux/linkage.h> 13250c2277SThomas Gleixner#include <linux/threads.h> 14250c2277SThomas Gleixner#include <linux/init.h> 15250c2277SThomas Gleixner#include <asm/segment.h> 16250c2277SThomas Gleixner#include <asm/pgtable.h> 17250c2277SThomas Gleixner#include <asm/page.h> 18250c2277SThomas Gleixner#include <asm/msr.h> 19250c2277SThomas Gleixner#include <asm/cache.h> 20369101daSCyrill Gorcunov#include <asm/processor-flags.h> 21b12d8db8STejun Heo#include <asm/percpu.h> 229900aa2fSH. Peter Anvin#include <asm/nops.h> 23250c2277SThomas Gleixner 2449a69787SGlauber de Oliveira Costa#ifdef CONFIG_PARAVIRT 2549a69787SGlauber de Oliveira Costa#include <asm/asm-offsets.h> 2649a69787SGlauber de Oliveira Costa#include <asm/paravirt.h> 27ffc4bc9cSH. Peter Anvin#define GET_CR2_INTO(reg) GET_CR2_INTO_RAX ; movq %rax, reg 2849a69787SGlauber de Oliveira Costa#else 29ffc4bc9cSH. Peter Anvin#define GET_CR2_INTO(reg) movq %cr2, reg 309900aa2fSH. Peter Anvin#define INTERRUPT_RETURN iretq 3149a69787SGlauber de Oliveira Costa#endif 3249a69787SGlauber de Oliveira Costa 333ad2f3fbSDaniel Mack/* we are not able to switch in one step to the final KERNEL ADDRESS SPACE 34250c2277SThomas Gleixner * because we need identity-mapped pages. 35250c2277SThomas Gleixner * 36250c2277SThomas Gleixner */ 37250c2277SThomas Gleixner 38a6523748SEduardo Habkost#define pud_index(x) (((x) >> PUD_SHIFT) & (PTRS_PER_PUD-1)) 39a6523748SEduardo Habkost 40a6523748SEduardo HabkostL4_PAGE_OFFSET = pgd_index(__PAGE_OFFSET) 41a6523748SEduardo HabkostL3_PAGE_OFFSET = pud_index(__PAGE_OFFSET) 42a6523748SEduardo HabkostL4_START_KERNEL = pgd_index(__START_KERNEL_map) 43a6523748SEduardo HabkostL3_START_KERNEL = pud_index(__START_KERNEL_map) 44a6523748SEduardo Habkost 45250c2277SThomas Gleixner .text 464ae59b91STim Abbott __HEAD 47250c2277SThomas Gleixner .code64 48250c2277SThomas Gleixner .globl startup_64 49250c2277SThomas Gleixnerstartup_64: 50250c2277SThomas Gleixner 51250c2277SThomas Gleixner /* 52250c2277SThomas Gleixner * At this point the CPU runs in 64bit mode CS.L = 1 CS.D = 1, 53250c2277SThomas Gleixner * and someone has loaded an identity mapped page table 54250c2277SThomas Gleixner * for us. These identity mapped page tables map all of the 55250c2277SThomas Gleixner * kernel pages and possibly all of memory. 56250c2277SThomas Gleixner * 57250c2277SThomas Gleixner * %esi holds a physical pointer to real_mode_data. 58250c2277SThomas Gleixner * 59250c2277SThomas Gleixner * We come here either directly from a 64bit bootloader, or from 60250c2277SThomas Gleixner * arch/x86_64/boot/compressed/head.S. 61250c2277SThomas Gleixner * 62250c2277SThomas Gleixner * We only come here initially at boot nothing else comes here. 63250c2277SThomas Gleixner * 64250c2277SThomas Gleixner * Since we may be loaded at an address different from what we were 65250c2277SThomas Gleixner * compiled to run at we first fixup the physical addresses in our page 66250c2277SThomas Gleixner * tables and then reload them. 67250c2277SThomas Gleixner */ 68250c2277SThomas Gleixner 69250c2277SThomas Gleixner /* Compute the delta between the address I am compiled to run at and the 70250c2277SThomas Gleixner * address I am actually running at. 71250c2277SThomas Gleixner */ 72250c2277SThomas Gleixner leaq _text(%rip), %rbp 73250c2277SThomas Gleixner subq $_text - __START_KERNEL_map, %rbp 74250c2277SThomas Gleixner 75250c2277SThomas Gleixner /* Is the address not 2M aligned? */ 76250c2277SThomas Gleixner movq %rbp, %rax 7731422c51SAndi Kleen andl $~PMD_PAGE_MASK, %eax 78250c2277SThomas Gleixner testl %eax, %eax 79250c2277SThomas Gleixner jnz bad_address 80250c2277SThomas Gleixner 81250c2277SThomas Gleixner /* Is the address too large? */ 82250c2277SThomas Gleixner leaq _text(%rip), %rdx 83250c2277SThomas Gleixner movq $PGDIR_SIZE, %rax 84250c2277SThomas Gleixner cmpq %rax, %rdx 85250c2277SThomas Gleixner jae bad_address 86250c2277SThomas Gleixner 87250c2277SThomas Gleixner /* Fixup the physical addresses in the page table 88250c2277SThomas Gleixner */ 89250c2277SThomas Gleixner addq %rbp, init_level4_pgt + 0(%rip) 90a6523748SEduardo Habkost addq %rbp, init_level4_pgt + (L4_PAGE_OFFSET*8)(%rip) 91a6523748SEduardo Habkost addq %rbp, init_level4_pgt + (L4_START_KERNEL*8)(%rip) 92250c2277SThomas Gleixner 93250c2277SThomas Gleixner addq %rbp, level3_ident_pgt + 0(%rip) 94250c2277SThomas Gleixner 95250c2277SThomas Gleixner addq %rbp, level3_kernel_pgt + (510*8)(%rip) 96250c2277SThomas Gleixner addq %rbp, level3_kernel_pgt + (511*8)(%rip) 97250c2277SThomas Gleixner 98250c2277SThomas Gleixner addq %rbp, level2_fixmap_pgt + (506*8)(%rip) 99250c2277SThomas Gleixner 100250c2277SThomas Gleixner /* Add an Identity mapping if I am above 1G */ 101250c2277SThomas Gleixner leaq _text(%rip), %rdi 10231422c51SAndi Kleen andq $PMD_PAGE_MASK, %rdi 103250c2277SThomas Gleixner 104250c2277SThomas Gleixner movq %rdi, %rax 105250c2277SThomas Gleixner shrq $PUD_SHIFT, %rax 106250c2277SThomas Gleixner andq $(PTRS_PER_PUD - 1), %rax 107250c2277SThomas Gleixner jz ident_complete 108250c2277SThomas Gleixner 109250c2277SThomas Gleixner leaq (level2_spare_pgt - __START_KERNEL_map + _KERNPG_TABLE)(%rbp), %rdx 110250c2277SThomas Gleixner leaq level3_ident_pgt(%rip), %rbx 111250c2277SThomas Gleixner movq %rdx, 0(%rbx, %rax, 8) 112250c2277SThomas Gleixner 113250c2277SThomas Gleixner movq %rdi, %rax 114250c2277SThomas Gleixner shrq $PMD_SHIFT, %rax 115250c2277SThomas Gleixner andq $(PTRS_PER_PMD - 1), %rax 116b2bc2731SSuresh Siddha leaq __PAGE_KERNEL_IDENT_LARGE_EXEC(%rdi), %rdx 117250c2277SThomas Gleixner leaq level2_spare_pgt(%rip), %rbx 118250c2277SThomas Gleixner movq %rdx, 0(%rbx, %rax, 8) 119250c2277SThomas Gleixnerident_complete: 120250c2277SThomas Gleixner 12131eedd82SThomas Gleixner /* 12231eedd82SThomas Gleixner * Fixup the kernel text+data virtual addresses. Note that 12331eedd82SThomas Gleixner * we might write invalid pmds, when the kernel is relocated 12431eedd82SThomas Gleixner * cleanup_highmap() fixes this up along with the mappings 12531eedd82SThomas Gleixner * beyond _end. 126250c2277SThomas Gleixner */ 12731eedd82SThomas Gleixner 128250c2277SThomas Gleixner leaq level2_kernel_pgt(%rip), %rdi 129250c2277SThomas Gleixner leaq 4096(%rdi), %r8 130250c2277SThomas Gleixner /* See if it is a valid page table entry */ 131250c2277SThomas Gleixner1: testq $1, 0(%rdi) 132250c2277SThomas Gleixner jz 2f 133250c2277SThomas Gleixner addq %rbp, 0(%rdi) 134250c2277SThomas Gleixner /* Go to the next page */ 135250c2277SThomas Gleixner2: addq $8, %rdi 136250c2277SThomas Gleixner cmp %r8, %rdi 137250c2277SThomas Gleixner jne 1b 138250c2277SThomas Gleixner 139250c2277SThomas Gleixner /* Fixup phys_base */ 140250c2277SThomas Gleixner addq %rbp, phys_base(%rip) 141250c2277SThomas Gleixner 1424822b7fcSH. Peter Anvin /* Fixup trampoline */ 143250c2277SThomas Gleixner addq %rbp, trampoline_level4_pgt + 0(%rip) 144250c2277SThomas Gleixner addq %rbp, trampoline_level4_pgt + (511*8)(%rip) 145250c2277SThomas Gleixner 146250c2277SThomas Gleixner /* Due to ENTRY(), sometimes the empty space gets filled with 147250c2277SThomas Gleixner * zeros. Better take a jmp than relying on empty space being 148250c2277SThomas Gleixner * filled with 0x90 (nop) 149250c2277SThomas Gleixner */ 150250c2277SThomas Gleixner jmp secondary_startup_64 151250c2277SThomas GleixnerENTRY(secondary_startup_64) 152250c2277SThomas Gleixner /* 153250c2277SThomas Gleixner * At this point the CPU runs in 64bit mode CS.L = 1 CS.D = 1, 154250c2277SThomas Gleixner * and someone has loaded a mapped page table. 155250c2277SThomas Gleixner * 156250c2277SThomas Gleixner * %esi holds a physical pointer to real_mode_data. 157250c2277SThomas Gleixner * 158250c2277SThomas Gleixner * We come here either from startup_64 (using physical addresses) 159250c2277SThomas Gleixner * or from trampoline.S (using virtual addresses). 160250c2277SThomas Gleixner * 161250c2277SThomas Gleixner * Using virtual addresses from trampoline.S removes the need 162250c2277SThomas Gleixner * to have any identity mapped pages in the kernel page table 163250c2277SThomas Gleixner * after the boot processor executes this code. 164250c2277SThomas Gleixner */ 165250c2277SThomas Gleixner 166250c2277SThomas Gleixner /* Enable PAE mode and PGE */ 16705139d8fSCyrill Gorcunov movl $(X86_CR4_PAE | X86_CR4_PGE), %eax 168250c2277SThomas Gleixner movq %rax, %cr4 169250c2277SThomas Gleixner 170250c2277SThomas Gleixner /* Setup early boot stage 4 level pagetables. */ 171250c2277SThomas Gleixner movq $(init_level4_pgt - __START_KERNEL_map), %rax 172250c2277SThomas Gleixner addq phys_base(%rip), %rax 173250c2277SThomas Gleixner movq %rax, %cr3 174250c2277SThomas Gleixner 175250c2277SThomas Gleixner /* Ensure I am executing from virtual addresses */ 176250c2277SThomas Gleixner movq $1f, %rax 177250c2277SThomas Gleixner jmp *%rax 178250c2277SThomas Gleixner1: 179250c2277SThomas Gleixner 180250c2277SThomas Gleixner /* Check if nx is implemented */ 181250c2277SThomas Gleixner movl $0x80000001, %eax 182250c2277SThomas Gleixner cpuid 183250c2277SThomas Gleixner movl %edx,%edi 184250c2277SThomas Gleixner 185250c2277SThomas Gleixner /* Setup EFER (Extended Feature Enable Register) */ 186250c2277SThomas Gleixner movl $MSR_EFER, %ecx 187250c2277SThomas Gleixner rdmsr 188250c2277SThomas Gleixner btsl $_EFER_SCE, %eax /* Enable System Call */ 189250c2277SThomas Gleixner btl $20,%edi /* No Execute supported? */ 190250c2277SThomas Gleixner jnc 1f 191250c2277SThomas Gleixner btsl $_EFER_NX, %eax 192250c2277SThomas Gleixner1: wrmsr /* Make changes effective */ 193250c2277SThomas Gleixner 194250c2277SThomas Gleixner /* Setup cr0 */ 195369101daSCyrill Gorcunov#define CR0_STATE (X86_CR0_PE | X86_CR0_MP | X86_CR0_ET | \ 196369101daSCyrill Gorcunov X86_CR0_NE | X86_CR0_WP | X86_CR0_AM | \ 197369101daSCyrill Gorcunov X86_CR0_PG) 198369101daSCyrill Gorcunov movl $CR0_STATE, %eax 199250c2277SThomas Gleixner /* Make changes effective */ 200250c2277SThomas Gleixner movq %rax, %cr0 201250c2277SThomas Gleixner 202250c2277SThomas Gleixner /* Setup a boot time stack */ 2039cf4f298SGlauber Costa movq stack_start(%rip),%rsp 204250c2277SThomas Gleixner 205250c2277SThomas Gleixner /* zero EFLAGS after setting rsp */ 206250c2277SThomas Gleixner pushq $0 207250c2277SThomas Gleixner popfq 208250c2277SThomas Gleixner 209250c2277SThomas Gleixner /* 210250c2277SThomas Gleixner * We must switch to a new descriptor in kernel space for the GDT 211250c2277SThomas Gleixner * because soon the kernel won't have access anymore to the userspace 212250c2277SThomas Gleixner * addresses where we're currently running on. We have to do that here 213250c2277SThomas Gleixner * because in 32bit we couldn't load a 64bit linear address. 214250c2277SThomas Gleixner */ 215a939098aSGlauber Costa lgdt early_gdt_descr(%rip) 216250c2277SThomas Gleixner 2178ec6993dSBrian Gerst /* set up data segments */ 2188ec6993dSBrian Gerst xorl %eax,%eax 219250c2277SThomas Gleixner movl %eax,%ds 220250c2277SThomas Gleixner movl %eax,%ss 221250c2277SThomas Gleixner movl %eax,%es 222250c2277SThomas Gleixner 223250c2277SThomas Gleixner /* 224250c2277SThomas Gleixner * We don't really need to load %fs or %gs, but load them anyway 225250c2277SThomas Gleixner * to kill any stale realmode selectors. This allows execution 226250c2277SThomas Gleixner * under VT hardware. 227250c2277SThomas Gleixner */ 228250c2277SThomas Gleixner movl %eax,%fs 229250c2277SThomas Gleixner movl %eax,%gs 230250c2277SThomas Gleixner 231f32ff538STejun Heo /* Set up %gs. 232f32ff538STejun Heo * 233947e76cdSBrian Gerst * The base of %gs always points to the bottom of the irqstack 234947e76cdSBrian Gerst * union. If the stack protector canary is enabled, it is 235947e76cdSBrian Gerst * located at %gs:40. Note that, on SMP, the boot cpu uses 236947e76cdSBrian Gerst * init data section till per cpu areas are set up. 237250c2277SThomas Gleixner */ 238250c2277SThomas Gleixner movl $MSR_GS_BASE,%ecx 239650fb439SBrian Gerst movl initial_gs(%rip),%eax 240650fb439SBrian Gerst movl initial_gs+4(%rip),%edx 241250c2277SThomas Gleixner wrmsr 242250c2277SThomas Gleixner 243250c2277SThomas Gleixner /* esi is pointer to real mode structure with interesting info. 244250c2277SThomas Gleixner pass it to C */ 245250c2277SThomas Gleixner movl %esi, %edi 246250c2277SThomas Gleixner 247250c2277SThomas Gleixner /* Finally jump to run C code and to be on real kernel address 248250c2277SThomas Gleixner * Since we are running on identity-mapped space we have to jump 249250c2277SThomas Gleixner * to the full 64bit address, this is only possible as indirect 250250c2277SThomas Gleixner * jump. In addition we need to ensure %cs is set so we make this 251250c2277SThomas Gleixner * a far return. 252250c2277SThomas Gleixner */ 253250c2277SThomas Gleixner movq initial_code(%rip),%rax 254250c2277SThomas Gleixner pushq $0 # fake return address to stop unwinder 255250c2277SThomas Gleixner pushq $__KERNEL_CS # set correct cs 256250c2277SThomas Gleixner pushq %rax # target address in negative space 257250c2277SThomas Gleixner lretq 258250c2277SThomas Gleixner 259250c2277SThomas Gleixner /* SMP bootup changes these two */ 260da5968aeSSam Ravnborg __REFDATA 261250c2277SThomas Gleixner .align 8 262f1fbabb3SSam Ravnborg ENTRY(initial_code) 263250c2277SThomas Gleixner .quad x86_64_start_kernel 264f32ff538STejun Heo ENTRY(initial_gs) 2652add8e23SBrian Gerst .quad INIT_PER_CPU_VAR(irq_stack_union) 266f1fbabb3SSam Ravnborg 2679cf4f298SGlauber Costa ENTRY(stack_start) 268250c2277SThomas Gleixner .quad init_thread_union+THREAD_SIZE-8 2699cf4f298SGlauber Costa .word 0 270b9af7c0dSSuresh Siddha __FINITDATA 271250c2277SThomas Gleixner 272250c2277SThomas Gleixnerbad_address: 273250c2277SThomas Gleixner jmp bad_address 274250c2277SThomas Gleixner 27541bd4eacSAndi Kleen .section ".init.text","ax" 2768866cd9dSRoland McGrath .globl early_idt_handlers 2778866cd9dSRoland McGrathearly_idt_handlers: 2789900aa2fSH. Peter Anvin # 104(%rsp) %rflags 2799900aa2fSH. Peter Anvin # 96(%rsp) %cs 2809900aa2fSH. Peter Anvin # 88(%rsp) %rip 2819900aa2fSH. Peter Anvin # 80(%rsp) error code 282749c970aSAndi Kleen i = 0 283749c970aSAndi Kleen .rept NUM_EXCEPTION_VECTORS 2849900aa2fSH. Peter Anvin .if (EXCEPTION_ERRCODE_MASK >> i) & 1 2859900aa2fSH. Peter Anvin ASM_NOP2 2869900aa2fSH. Peter Anvin .else 2879900aa2fSH. Peter Anvin pushq $0 # Dummy error code, to make stack frame uniform 2889900aa2fSH. Peter Anvin .endif 2899900aa2fSH. Peter Anvin pushq $i # 72(%rsp) Vector number 290749c970aSAndi Kleen jmp early_idt_handler 291749c970aSAndi Kleen i = i + 1 292749c970aSAndi Kleen .endr 2938866cd9dSRoland McGrath 294250c2277SThomas GleixnerENTRY(early_idt_handler) 2959900aa2fSH. Peter Anvin cld 2969900aa2fSH. Peter Anvin 297250c2277SThomas Gleixner cmpl $2,early_recursion_flag(%rip) 298250c2277SThomas Gleixner jz 1f 299250c2277SThomas Gleixner incl early_recursion_flag(%rip) 3009900aa2fSH. Peter Anvin 3019900aa2fSH. Peter Anvin pushq %rax # 64(%rsp) 3029900aa2fSH. Peter Anvin pushq %rcx # 56(%rsp) 3039900aa2fSH. Peter Anvin pushq %rdx # 48(%rsp) 3049900aa2fSH. Peter Anvin pushq %rsi # 40(%rsp) 3059900aa2fSH. Peter Anvin pushq %rdi # 32(%rsp) 3069900aa2fSH. Peter Anvin pushq %r8 # 24(%rsp) 3079900aa2fSH. Peter Anvin pushq %r9 # 16(%rsp) 3089900aa2fSH. Peter Anvin pushq %r10 # 8(%rsp) 3099900aa2fSH. Peter Anvin pushq %r11 # 0(%rsp) 3109900aa2fSH. Peter Anvin 3119900aa2fSH. Peter Anvin cmpl $__KERNEL_CS,96(%rsp) 3129900aa2fSH. Peter Anvin jne 10f 3139900aa2fSH. Peter Anvin 3149900aa2fSH. Peter Anvin leaq 88(%rsp),%rdi # Pointer to %rip 3159900aa2fSH. Peter Anvin call early_fixup_exception 3169900aa2fSH. Peter Anvin andl %eax,%eax 3179900aa2fSH. Peter Anvin jnz 20f # Found an exception entry 3189900aa2fSH. Peter Anvin 3199900aa2fSH. Peter Anvin10: 3209900aa2fSH. Peter Anvin#ifdef CONFIG_EARLY_PRINTK 3219900aa2fSH. Peter Anvin GET_CR2_INTO(%r9) # can clobber any volatile register if pv 3229900aa2fSH. Peter Anvin movl 80(%rsp),%r8d # error code 3239900aa2fSH. Peter Anvin movl 72(%rsp),%esi # vector number 3249900aa2fSH. Peter Anvin movl 96(%rsp),%edx # %cs 3259900aa2fSH. Peter Anvin movq 88(%rsp),%rcx # %rip 3268866cd9dSRoland McGrath xorl %eax,%eax 327250c2277SThomas Gleixner leaq early_idt_msg(%rip),%rdi 328250c2277SThomas Gleixner call early_printk 329250c2277SThomas Gleixner cmpl $2,early_recursion_flag(%rip) 330250c2277SThomas Gleixner jz 1f 331250c2277SThomas Gleixner call dump_stack 332250c2277SThomas Gleixner#ifdef CONFIG_KALLSYMS 333250c2277SThomas Gleixner leaq early_idt_ripmsg(%rip),%rdi 3349900aa2fSH. Peter Anvin movq 40(%rsp),%rsi # %rip again 335250c2277SThomas Gleixner call __print_symbol 336250c2277SThomas Gleixner#endif 337076f9776SIngo Molnar#endif /* EARLY_PRINTK */ 338250c2277SThomas Gleixner1: hlt 339250c2277SThomas Gleixner jmp 1b 340076f9776SIngo Molnar 3419900aa2fSH. Peter Anvin20: # Exception table entry found 3429900aa2fSH. Peter Anvin popq %r11 3439900aa2fSH. Peter Anvin popq %r10 3449900aa2fSH. Peter Anvin popq %r9 3459900aa2fSH. Peter Anvin popq %r8 3469900aa2fSH. Peter Anvin popq %rdi 3479900aa2fSH. Peter Anvin popq %rsi 3489900aa2fSH. Peter Anvin popq %rdx 3499900aa2fSH. Peter Anvin popq %rcx 3509900aa2fSH. Peter Anvin popq %rax 3519900aa2fSH. Peter Anvin addq $16,%rsp # drop vector number and error code 3529900aa2fSH. Peter Anvin decl early_recursion_flag(%rip) 3539900aa2fSH. Peter Anvin INTERRUPT_RETURN 3549900aa2fSH. Peter Anvin 3559900aa2fSH. Peter Anvin .balign 4 356250c2277SThomas Gleixnerearly_recursion_flag: 357250c2277SThomas Gleixner .long 0 358250c2277SThomas Gleixner 3599900aa2fSH. Peter Anvin#ifdef CONFIG_EARLY_PRINTK 360250c2277SThomas Gleixnerearly_idt_msg: 3618866cd9dSRoland McGrath .asciz "PANIC: early exception %02lx rip %lx:%lx error %lx cr2 %lx\n" 362250c2277SThomas Gleixnerearly_idt_ripmsg: 363250c2277SThomas Gleixner .asciz "RIP %s\n" 364076f9776SIngo Molnar#endif /* CONFIG_EARLY_PRINTK */ 36541bd4eacSAndi Kleen .previous 366250c2277SThomas Gleixner 367250c2277SThomas Gleixner#define NEXT_PAGE(name) \ 368250c2277SThomas Gleixner .balign PAGE_SIZE; \ 369250c2277SThomas GleixnerENTRY(name) 370250c2277SThomas Gleixner 371250c2277SThomas Gleixner/* Automate the creation of 1 to 1 mapping pmd entries */ 372250c2277SThomas Gleixner#define PMDS(START, PERM, COUNT) \ 373250c2277SThomas Gleixner i = 0 ; \ 374250c2277SThomas Gleixner .rept (COUNT) ; \ 3750e192b99SCyrill Gorcunov .quad (START) + (i << PMD_SHIFT) + (PERM) ; \ 376250c2277SThomas Gleixner i = i + 1 ; \ 377250c2277SThomas Gleixner .endr 378250c2277SThomas Gleixner 379b9af7c0dSSuresh Siddha .data 380250c2277SThomas Gleixner /* 381250c2277SThomas Gleixner * This default setting generates an ident mapping at address 0x100000 382250c2277SThomas Gleixner * and a mapping for the kernel that precisely maps virtual address 383250c2277SThomas Gleixner * 0xffffffff80000000 to physical address 0x000000. (always using 384250c2277SThomas Gleixner * 2Mbyte large pages provided by PAE mode) 385250c2277SThomas Gleixner */ 386250c2277SThomas GleixnerNEXT_PAGE(init_level4_pgt) 387250c2277SThomas Gleixner .quad level3_ident_pgt - __START_KERNEL_map + _KERNPG_TABLE 388a6523748SEduardo Habkost .org init_level4_pgt + L4_PAGE_OFFSET*8, 0 389250c2277SThomas Gleixner .quad level3_ident_pgt - __START_KERNEL_map + _KERNPG_TABLE 390a6523748SEduardo Habkost .org init_level4_pgt + L4_START_KERNEL*8, 0 391250c2277SThomas Gleixner /* (2^48-(2*1024*1024*1024))/(2^39) = 511 */ 392250c2277SThomas Gleixner .quad level3_kernel_pgt - __START_KERNEL_map + _PAGE_TABLE 393250c2277SThomas Gleixner 394250c2277SThomas GleixnerNEXT_PAGE(level3_ident_pgt) 395250c2277SThomas Gleixner .quad level2_ident_pgt - __START_KERNEL_map + _KERNPG_TABLE 396250c2277SThomas Gleixner .fill 511,8,0 397250c2277SThomas Gleixner 398250c2277SThomas GleixnerNEXT_PAGE(level3_kernel_pgt) 399a6523748SEduardo Habkost .fill L3_START_KERNEL,8,0 400250c2277SThomas Gleixner /* (2^48-(2*1024*1024*1024)-((2^39)*511))/(2^30) = 510 */ 401250c2277SThomas Gleixner .quad level2_kernel_pgt - __START_KERNEL_map + _KERNPG_TABLE 402250c2277SThomas Gleixner .quad level2_fixmap_pgt - __START_KERNEL_map + _PAGE_TABLE 403250c2277SThomas Gleixner 404250c2277SThomas GleixnerNEXT_PAGE(level2_fixmap_pgt) 4056596f242SIngo Molnar .fill 506,8,0 4066596f242SIngo Molnar .quad level1_fixmap_pgt - __START_KERNEL_map + _PAGE_TABLE 4076596f242SIngo Molnar /* 8MB reserved for vsyscalls + a 2MB hole = 4 + 1 entries */ 4086596f242SIngo Molnar .fill 5,8,0 4096596f242SIngo Molnar 4106596f242SIngo MolnarNEXT_PAGE(level1_fixmap_pgt) 411250c2277SThomas Gleixner .fill 512,8,0 412250c2277SThomas Gleixner 413250c2277SThomas GleixnerNEXT_PAGE(level2_ident_pgt) 414250c2277SThomas Gleixner /* Since I easily can, map the first 1G. 415250c2277SThomas Gleixner * Don't set NX because code runs from these pages. 416250c2277SThomas Gleixner */ 417b2bc2731SSuresh Siddha PMDS(0, __PAGE_KERNEL_IDENT_LARGE_EXEC, PTRS_PER_PMD) 418250c2277SThomas Gleixner 419250c2277SThomas GleixnerNEXT_PAGE(level2_kernel_pgt) 42088f3aec7SIngo Molnar /* 42185eb69a1SIngo Molnar * 512 MB kernel mapping. We spend a full page on this pagetable 42288f3aec7SIngo Molnar * anyway. 42388f3aec7SIngo Molnar * 42488f3aec7SIngo Molnar * The kernel code+data+bss must not be bigger than that. 42588f3aec7SIngo Molnar * 42685eb69a1SIngo Molnar * (NOTE: at +512MB starts the module area, see MODULES_VADDR. 42788f3aec7SIngo Molnar * If you want to increase this then increase MODULES_VADDR 42888f3aec7SIngo Molnar * too.) 42988f3aec7SIngo Molnar */ 4308490638cSJeremy Fitzhardinge PMDS(0, __PAGE_KERNEL_LARGE_EXEC, 431d4afe414SIngo Molnar KERNEL_IMAGE_SIZE/PMD_SIZE) 432250c2277SThomas Gleixner 433250c2277SThomas GleixnerNEXT_PAGE(level2_spare_pgt) 434250c2277SThomas Gleixner .fill 512, 8, 0 435250c2277SThomas Gleixner 436250c2277SThomas Gleixner#undef PMDS 437250c2277SThomas Gleixner#undef NEXT_PAGE 438250c2277SThomas Gleixner 439250c2277SThomas Gleixner .data 440250c2277SThomas Gleixner .align 16 441a939098aSGlauber Costa .globl early_gdt_descr 442a939098aSGlauber Costaearly_gdt_descr: 443a939098aSGlauber Costa .word GDT_ENTRIES*8-1 4443e5d8f97STejun Heoearly_gdt_descr_base: 4452add8e23SBrian Gerst .quad INIT_PER_CPU_VAR(gdt_page) 446250c2277SThomas Gleixner 447250c2277SThomas GleixnerENTRY(phys_base) 448250c2277SThomas Gleixner /* This must match the first entry in level2_kernel_pgt */ 449250c2277SThomas Gleixner .quad 0x0000000000000000 450250c2277SThomas Gleixner 4518c5e5ac3SJeremy Fitzhardinge#include "../../x86/xen/xen-head.S" 452250c2277SThomas Gleixner 453250c2277SThomas Gleixner .section .bss, "aw", @nobits 454250c2277SThomas Gleixner .align L1_CACHE_BYTES 455250c2277SThomas GleixnerENTRY(idt_table) 4565e112ae2SCyrill Gorcunov .skip IDT_ENTRIES * 16 457250c2277SThomas Gleixner 458228bdaa9SSteven Rostedt .align L1_CACHE_BYTES 459228bdaa9SSteven RostedtENTRY(nmi_idt_table) 460228bdaa9SSteven Rostedt .skip IDT_ENTRIES * 16 461228bdaa9SSteven Rostedt 46202b7da37STim Abbott __PAGE_ALIGNED_BSS 463250c2277SThomas Gleixner .align PAGE_SIZE 464250c2277SThomas GleixnerENTRY(empty_zero_page) 465250c2277SThomas Gleixner .skip PAGE_SIZE 466