1250c2277SThomas Gleixner/* 2250c2277SThomas Gleixner * linux/arch/x86_64/kernel/head.S -- start in 32bit and switch to 64bit 3250c2277SThomas Gleixner * 4250c2277SThomas Gleixner * Copyright (C) 2000 Andrea Arcangeli <andrea@suse.de> SuSE 5250c2277SThomas Gleixner * Copyright (C) 2000 Pavel Machek <pavel@suse.cz> 6250c2277SThomas Gleixner * Copyright (C) 2000 Karsten Keil <kkeil@suse.de> 7250c2277SThomas Gleixner * Copyright (C) 2001,2002 Andi Kleen <ak@suse.de> 8250c2277SThomas Gleixner * Copyright (C) 2005 Eric Biederman <ebiederm@xmission.com> 9250c2277SThomas Gleixner */ 10250c2277SThomas Gleixner 11250c2277SThomas Gleixner 12250c2277SThomas Gleixner#include <linux/linkage.h> 13250c2277SThomas Gleixner#include <linux/threads.h> 14250c2277SThomas Gleixner#include <linux/init.h> 15250c2277SThomas Gleixner#include <asm/desc.h> 16250c2277SThomas Gleixner#include <asm/segment.h> 17250c2277SThomas Gleixner#include <asm/pgtable.h> 18250c2277SThomas Gleixner#include <asm/page.h> 19250c2277SThomas Gleixner#include <asm/msr.h> 20250c2277SThomas Gleixner#include <asm/cache.h> 21369101daSCyrill Gorcunov#include <asm/processor-flags.h> 22b12d8db8STejun Heo#include <asm/percpu.h> 23250c2277SThomas Gleixner 2449a69787SGlauber de Oliveira Costa#ifdef CONFIG_PARAVIRT 2549a69787SGlauber de Oliveira Costa#include <asm/asm-offsets.h> 2649a69787SGlauber de Oliveira Costa#include <asm/paravirt.h> 2749a69787SGlauber de Oliveira Costa#else 2849a69787SGlauber de Oliveira Costa#define GET_CR2_INTO_RCX movq %cr2, %rcx 2949a69787SGlauber de Oliveira Costa#endif 3049a69787SGlauber de Oliveira Costa 31250c2277SThomas Gleixner/* we are not able to switch in one step to the final KERNEL ADRESS SPACE 32250c2277SThomas Gleixner * because we need identity-mapped pages. 33250c2277SThomas Gleixner * 34250c2277SThomas Gleixner */ 35250c2277SThomas Gleixner 36a6523748SEduardo Habkost#define pud_index(x) (((x) >> PUD_SHIFT) & (PTRS_PER_PUD-1)) 37a6523748SEduardo Habkost 38a6523748SEduardo HabkostL4_PAGE_OFFSET = pgd_index(__PAGE_OFFSET) 39a6523748SEduardo HabkostL3_PAGE_OFFSET = pud_index(__PAGE_OFFSET) 40a6523748SEduardo HabkostL4_START_KERNEL = pgd_index(__START_KERNEL_map) 41a6523748SEduardo HabkostL3_START_KERNEL = pud_index(__START_KERNEL_map) 42a6523748SEduardo Habkost 43250c2277SThomas Gleixner .text 44250c2277SThomas Gleixner .section .text.head 45250c2277SThomas Gleixner .code64 46250c2277SThomas Gleixner .globl startup_64 47250c2277SThomas Gleixnerstartup_64: 48250c2277SThomas Gleixner 49250c2277SThomas Gleixner /* 50250c2277SThomas Gleixner * At this point the CPU runs in 64bit mode CS.L = 1 CS.D = 1, 51250c2277SThomas Gleixner * and someone has loaded an identity mapped page table 52250c2277SThomas Gleixner * for us. These identity mapped page tables map all of the 53250c2277SThomas Gleixner * kernel pages and possibly all of memory. 54250c2277SThomas Gleixner * 55250c2277SThomas Gleixner * %esi holds a physical pointer to real_mode_data. 56250c2277SThomas Gleixner * 57250c2277SThomas Gleixner * We come here either directly from a 64bit bootloader, or from 58250c2277SThomas Gleixner * arch/x86_64/boot/compressed/head.S. 59250c2277SThomas Gleixner * 60250c2277SThomas Gleixner * We only come here initially at boot nothing else comes here. 61250c2277SThomas Gleixner * 62250c2277SThomas Gleixner * Since we may be loaded at an address different from what we were 63250c2277SThomas Gleixner * compiled to run at we first fixup the physical addresses in our page 64250c2277SThomas Gleixner * tables and then reload them. 65250c2277SThomas Gleixner */ 66250c2277SThomas Gleixner 67250c2277SThomas Gleixner /* Compute the delta between the address I am compiled to run at and the 68250c2277SThomas Gleixner * address I am actually running at. 69250c2277SThomas Gleixner */ 70250c2277SThomas Gleixner leaq _text(%rip), %rbp 71250c2277SThomas Gleixner subq $_text - __START_KERNEL_map, %rbp 72250c2277SThomas Gleixner 73250c2277SThomas Gleixner /* Is the address not 2M aligned? */ 74250c2277SThomas Gleixner movq %rbp, %rax 7531422c51SAndi Kleen andl $~PMD_PAGE_MASK, %eax 76250c2277SThomas Gleixner testl %eax, %eax 77250c2277SThomas Gleixner jnz bad_address 78250c2277SThomas Gleixner 79250c2277SThomas Gleixner /* Is the address too large? */ 80250c2277SThomas Gleixner leaq _text(%rip), %rdx 81250c2277SThomas Gleixner movq $PGDIR_SIZE, %rax 82250c2277SThomas Gleixner cmpq %rax, %rdx 83250c2277SThomas Gleixner jae bad_address 84250c2277SThomas Gleixner 85250c2277SThomas Gleixner /* Fixup the physical addresses in the page table 86250c2277SThomas Gleixner */ 87250c2277SThomas Gleixner addq %rbp, init_level4_pgt + 0(%rip) 88a6523748SEduardo Habkost addq %rbp, init_level4_pgt + (L4_PAGE_OFFSET*8)(%rip) 89a6523748SEduardo Habkost addq %rbp, init_level4_pgt + (L4_START_KERNEL*8)(%rip) 90250c2277SThomas Gleixner 91250c2277SThomas Gleixner addq %rbp, level3_ident_pgt + 0(%rip) 92250c2277SThomas Gleixner 93250c2277SThomas Gleixner addq %rbp, level3_kernel_pgt + (510*8)(%rip) 94250c2277SThomas Gleixner addq %rbp, level3_kernel_pgt + (511*8)(%rip) 95250c2277SThomas Gleixner 96250c2277SThomas Gleixner addq %rbp, level2_fixmap_pgt + (506*8)(%rip) 97250c2277SThomas Gleixner 98250c2277SThomas Gleixner /* Add an Identity mapping if I am above 1G */ 99250c2277SThomas Gleixner leaq _text(%rip), %rdi 10031422c51SAndi Kleen andq $PMD_PAGE_MASK, %rdi 101250c2277SThomas Gleixner 102250c2277SThomas Gleixner movq %rdi, %rax 103250c2277SThomas Gleixner shrq $PUD_SHIFT, %rax 104250c2277SThomas Gleixner andq $(PTRS_PER_PUD - 1), %rax 105250c2277SThomas Gleixner jz ident_complete 106250c2277SThomas Gleixner 107250c2277SThomas Gleixner leaq (level2_spare_pgt - __START_KERNEL_map + _KERNPG_TABLE)(%rbp), %rdx 108250c2277SThomas Gleixner leaq level3_ident_pgt(%rip), %rbx 109250c2277SThomas Gleixner movq %rdx, 0(%rbx, %rax, 8) 110250c2277SThomas Gleixner 111250c2277SThomas Gleixner movq %rdi, %rax 112250c2277SThomas Gleixner shrq $PMD_SHIFT, %rax 113250c2277SThomas Gleixner andq $(PTRS_PER_PMD - 1), %rax 114b2bc2731SSuresh Siddha leaq __PAGE_KERNEL_IDENT_LARGE_EXEC(%rdi), %rdx 115250c2277SThomas Gleixner leaq level2_spare_pgt(%rip), %rbx 116250c2277SThomas Gleixner movq %rdx, 0(%rbx, %rax, 8) 117250c2277SThomas Gleixnerident_complete: 118250c2277SThomas Gleixner 11931eedd82SThomas Gleixner /* 12031eedd82SThomas Gleixner * Fixup the kernel text+data virtual addresses. Note that 12131eedd82SThomas Gleixner * we might write invalid pmds, when the kernel is relocated 12231eedd82SThomas Gleixner * cleanup_highmap() fixes this up along with the mappings 12331eedd82SThomas Gleixner * beyond _end. 124250c2277SThomas Gleixner */ 12531eedd82SThomas Gleixner 126250c2277SThomas Gleixner leaq level2_kernel_pgt(%rip), %rdi 127250c2277SThomas Gleixner leaq 4096(%rdi), %r8 128250c2277SThomas Gleixner /* See if it is a valid page table entry */ 129250c2277SThomas Gleixner1: testq $1, 0(%rdi) 130250c2277SThomas Gleixner jz 2f 131250c2277SThomas Gleixner addq %rbp, 0(%rdi) 132250c2277SThomas Gleixner /* Go to the next page */ 133250c2277SThomas Gleixner2: addq $8, %rdi 134250c2277SThomas Gleixner cmp %r8, %rdi 135250c2277SThomas Gleixner jne 1b 136250c2277SThomas Gleixner 137250c2277SThomas Gleixner /* Fixup phys_base */ 138250c2277SThomas Gleixner addq %rbp, phys_base(%rip) 139250c2277SThomas Gleixner 14064e83b5aSRafael J. Wysocki#ifdef CONFIG_X86_TRAMPOLINE 141250c2277SThomas Gleixner addq %rbp, trampoline_level4_pgt + 0(%rip) 142250c2277SThomas Gleixner addq %rbp, trampoline_level4_pgt + (511*8)(%rip) 143250c2277SThomas Gleixner#endif 144250c2277SThomas Gleixner 145250c2277SThomas Gleixner /* Due to ENTRY(), sometimes the empty space gets filled with 146250c2277SThomas Gleixner * zeros. Better take a jmp than relying on empty space being 147250c2277SThomas Gleixner * filled with 0x90 (nop) 148250c2277SThomas Gleixner */ 149250c2277SThomas Gleixner jmp secondary_startup_64 150250c2277SThomas GleixnerENTRY(secondary_startup_64) 151250c2277SThomas Gleixner /* 152250c2277SThomas Gleixner * At this point the CPU runs in 64bit mode CS.L = 1 CS.D = 1, 153250c2277SThomas Gleixner * and someone has loaded a mapped page table. 154250c2277SThomas Gleixner * 155250c2277SThomas Gleixner * %esi holds a physical pointer to real_mode_data. 156250c2277SThomas Gleixner * 157250c2277SThomas Gleixner * We come here either from startup_64 (using physical addresses) 158250c2277SThomas Gleixner * or from trampoline.S (using virtual addresses). 159250c2277SThomas Gleixner * 160250c2277SThomas Gleixner * Using virtual addresses from trampoline.S removes the need 161250c2277SThomas Gleixner * to have any identity mapped pages in the kernel page table 162250c2277SThomas Gleixner * after the boot processor executes this code. 163250c2277SThomas Gleixner */ 164250c2277SThomas Gleixner 165250c2277SThomas Gleixner /* Enable PAE mode and PGE */ 16605139d8fSCyrill Gorcunov movl $(X86_CR4_PAE | X86_CR4_PGE), %eax 167250c2277SThomas Gleixner movq %rax, %cr4 168250c2277SThomas Gleixner 169250c2277SThomas Gleixner /* Setup early boot stage 4 level pagetables. */ 170250c2277SThomas Gleixner movq $(init_level4_pgt - __START_KERNEL_map), %rax 171250c2277SThomas Gleixner addq phys_base(%rip), %rax 172250c2277SThomas Gleixner movq %rax, %cr3 173250c2277SThomas Gleixner 174250c2277SThomas Gleixner /* Ensure I am executing from virtual addresses */ 175250c2277SThomas Gleixner movq $1f, %rax 176250c2277SThomas Gleixner jmp *%rax 177250c2277SThomas Gleixner1: 178250c2277SThomas Gleixner 179250c2277SThomas Gleixner /* Check if nx is implemented */ 180250c2277SThomas Gleixner movl $0x80000001, %eax 181250c2277SThomas Gleixner cpuid 182250c2277SThomas Gleixner movl %edx,%edi 183250c2277SThomas Gleixner 184250c2277SThomas Gleixner /* Setup EFER (Extended Feature Enable Register) */ 185250c2277SThomas Gleixner movl $MSR_EFER, %ecx 186250c2277SThomas Gleixner rdmsr 187250c2277SThomas Gleixner btsl $_EFER_SCE, %eax /* Enable System Call */ 188250c2277SThomas Gleixner btl $20,%edi /* No Execute supported? */ 189250c2277SThomas Gleixner jnc 1f 190250c2277SThomas Gleixner btsl $_EFER_NX, %eax 191250c2277SThomas Gleixner1: wrmsr /* Make changes effective */ 192250c2277SThomas Gleixner 193250c2277SThomas Gleixner /* Setup cr0 */ 194369101daSCyrill Gorcunov#define CR0_STATE (X86_CR0_PE | X86_CR0_MP | X86_CR0_ET | \ 195369101daSCyrill Gorcunov X86_CR0_NE | X86_CR0_WP | X86_CR0_AM | \ 196369101daSCyrill Gorcunov X86_CR0_PG) 197369101daSCyrill Gorcunov movl $CR0_STATE, %eax 198250c2277SThomas Gleixner /* Make changes effective */ 199250c2277SThomas Gleixner movq %rax, %cr0 200250c2277SThomas Gleixner 201250c2277SThomas Gleixner /* Setup a boot time stack */ 2029cf4f298SGlauber Costa movq stack_start(%rip),%rsp 203250c2277SThomas Gleixner 204250c2277SThomas Gleixner /* zero EFLAGS after setting rsp */ 205250c2277SThomas Gleixner pushq $0 206250c2277SThomas Gleixner popfq 207250c2277SThomas Gleixner 2083e5d8f97STejun Heo#ifdef CONFIG_SMP 2093e5d8f97STejun Heo /* 2108c7e58e6SBrian Gerst * Fix up static pointers that need __per_cpu_load added. The assembler 2118c7e58e6SBrian Gerst * is unable to do this directly. This is only needed for the boot cpu. 2128c7e58e6SBrian Gerst * These values are set up with the correct base addresses by C code for 2138c7e58e6SBrian Gerst * secondary cpus. 2143e5d8f97STejun Heo */ 2158c7e58e6SBrian Gerst movq initial_gs(%rip), %rax 2168c7e58e6SBrian Gerst cmpl $0, per_cpu__cpu_number(%rax) 2178c7e58e6SBrian Gerst jne 1f 2188c7e58e6SBrian Gerst addq %rax, early_gdt_descr_base(%rip) 2193e5d8f97STejun Heo1: 2203e5d8f97STejun Heo#endif 221250c2277SThomas Gleixner /* 222250c2277SThomas Gleixner * We must switch to a new descriptor in kernel space for the GDT 223250c2277SThomas Gleixner * because soon the kernel won't have access anymore to the userspace 224250c2277SThomas Gleixner * addresses where we're currently running on. We have to do that here 225250c2277SThomas Gleixner * because in 32bit we couldn't load a 64bit linear address. 226250c2277SThomas Gleixner */ 227a939098aSGlauber Costa lgdt early_gdt_descr(%rip) 228250c2277SThomas Gleixner 229250c2277SThomas Gleixner /* set up data segments. actually 0 would do too */ 230250c2277SThomas Gleixner movl $__KERNEL_DS,%eax 231250c2277SThomas Gleixner movl %eax,%ds 232250c2277SThomas Gleixner movl %eax,%ss 233250c2277SThomas Gleixner movl %eax,%es 234250c2277SThomas Gleixner 235250c2277SThomas Gleixner /* 236250c2277SThomas Gleixner * We don't really need to load %fs or %gs, but load them anyway 237250c2277SThomas Gleixner * to kill any stale realmode selectors. This allows execution 238250c2277SThomas Gleixner * under VT hardware. 239250c2277SThomas Gleixner */ 240250c2277SThomas Gleixner movl %eax,%fs 241250c2277SThomas Gleixner movl %eax,%gs 242250c2277SThomas Gleixner 243f32ff538STejun Heo /* Set up %gs. 244f32ff538STejun Heo * 245947e76cdSBrian Gerst * The base of %gs always points to the bottom of the irqstack 246947e76cdSBrian Gerst * union. If the stack protector canary is enabled, it is 247947e76cdSBrian Gerst * located at %gs:40. Note that, on SMP, the boot cpu uses 248947e76cdSBrian Gerst * init data section till per cpu areas are set up. 249250c2277SThomas Gleixner */ 250250c2277SThomas Gleixner movl $MSR_GS_BASE,%ecx 251f32ff538STejun Heo movq initial_gs(%rip),%rax 252250c2277SThomas Gleixner movq %rax,%rdx 253250c2277SThomas Gleixner shrq $32,%rdx 254250c2277SThomas Gleixner wrmsr 255250c2277SThomas Gleixner 256250c2277SThomas Gleixner /* esi is pointer to real mode structure with interesting info. 257250c2277SThomas Gleixner pass it to C */ 258250c2277SThomas Gleixner movl %esi, %edi 259250c2277SThomas Gleixner 260250c2277SThomas Gleixner /* Finally jump to run C code and to be on real kernel address 261250c2277SThomas Gleixner * Since we are running on identity-mapped space we have to jump 262250c2277SThomas Gleixner * to the full 64bit address, this is only possible as indirect 263250c2277SThomas Gleixner * jump. In addition we need to ensure %cs is set so we make this 264250c2277SThomas Gleixner * a far return. 265250c2277SThomas Gleixner */ 266250c2277SThomas Gleixner movq initial_code(%rip),%rax 267250c2277SThomas Gleixner pushq $0 # fake return address to stop unwinder 268250c2277SThomas Gleixner pushq $__KERNEL_CS # set correct cs 269250c2277SThomas Gleixner pushq %rax # target address in negative space 270250c2277SThomas Gleixner lretq 271250c2277SThomas Gleixner 272250c2277SThomas Gleixner /* SMP bootup changes these two */ 273da5968aeSSam Ravnborg __REFDATA 274250c2277SThomas Gleixner .align 8 275f1fbabb3SSam Ravnborg ENTRY(initial_code) 276250c2277SThomas Gleixner .quad x86_64_start_kernel 277f32ff538STejun Heo ENTRY(initial_gs) 2781a51e3a0STejun Heo#ifdef CONFIG_SMP 2791a51e3a0STejun Heo .quad __per_cpu_load 2801a51e3a0STejun Heo#else 281947e76cdSBrian Gerst .quad PER_CPU_VAR(irq_stack_union) 2821a51e3a0STejun Heo#endif 283f1fbabb3SSam Ravnborg __FINITDATA 284f1fbabb3SSam Ravnborg 2859cf4f298SGlauber Costa ENTRY(stack_start) 286250c2277SThomas Gleixner .quad init_thread_union+THREAD_SIZE-8 2879cf4f298SGlauber Costa .word 0 288250c2277SThomas Gleixner 289250c2277SThomas Gleixnerbad_address: 290250c2277SThomas Gleixner jmp bad_address 291250c2277SThomas Gleixner 29241bd4eacSAndi Kleen .section ".init.text","ax" 293076f9776SIngo Molnar#ifdef CONFIG_EARLY_PRINTK 2948866cd9dSRoland McGrath .globl early_idt_handlers 2958866cd9dSRoland McGrathearly_idt_handlers: 296749c970aSAndi Kleen i = 0 297749c970aSAndi Kleen .rept NUM_EXCEPTION_VECTORS 298749c970aSAndi Kleen movl $i, %esi 299749c970aSAndi Kleen jmp early_idt_handler 300749c970aSAndi Kleen i = i + 1 301749c970aSAndi Kleen .endr 302076f9776SIngo Molnar#endif 3038866cd9dSRoland McGrath 304250c2277SThomas GleixnerENTRY(early_idt_handler) 305076f9776SIngo Molnar#ifdef CONFIG_EARLY_PRINTK 306250c2277SThomas Gleixner cmpl $2,early_recursion_flag(%rip) 307250c2277SThomas Gleixner jz 1f 308250c2277SThomas Gleixner incl early_recursion_flag(%rip) 30949a69787SGlauber de Oliveira Costa GET_CR2_INTO_RCX 3108866cd9dSRoland McGrath movq %rcx,%r9 3118866cd9dSRoland McGrath xorl %r8d,%r8d # zero for error code 3128866cd9dSRoland McGrath movl %esi,%ecx # get vector number 3138866cd9dSRoland McGrath # Test %ecx against mask of vectors that push error code. 3148866cd9dSRoland McGrath cmpl $31,%ecx 3158866cd9dSRoland McGrath ja 0f 3168866cd9dSRoland McGrath movl $1,%eax 3178866cd9dSRoland McGrath salq %cl,%rax 3188866cd9dSRoland McGrath testl $0x27d00,%eax 3198866cd9dSRoland McGrath je 0f 3208866cd9dSRoland McGrath popq %r8 # get error code 3218866cd9dSRoland McGrath0: movq 0(%rsp),%rcx # get ip 3228866cd9dSRoland McGrath movq 8(%rsp),%rdx # get cs 3238866cd9dSRoland McGrath xorl %eax,%eax 324250c2277SThomas Gleixner leaq early_idt_msg(%rip),%rdi 325250c2277SThomas Gleixner call early_printk 326250c2277SThomas Gleixner cmpl $2,early_recursion_flag(%rip) 327250c2277SThomas Gleixner jz 1f 328250c2277SThomas Gleixner call dump_stack 329250c2277SThomas Gleixner#ifdef CONFIG_KALLSYMS 330250c2277SThomas Gleixner leaq early_idt_ripmsg(%rip),%rdi 3317aed55d1SJiri Slaby movq 0(%rsp),%rsi # get rip again 332250c2277SThomas Gleixner call __print_symbol 333250c2277SThomas Gleixner#endif 334076f9776SIngo Molnar#endif /* EARLY_PRINTK */ 335250c2277SThomas Gleixner1: hlt 336250c2277SThomas Gleixner jmp 1b 337076f9776SIngo Molnar 338076f9776SIngo Molnar#ifdef CONFIG_EARLY_PRINTK 339250c2277SThomas Gleixnerearly_recursion_flag: 340250c2277SThomas Gleixner .long 0 341250c2277SThomas Gleixner 342250c2277SThomas Gleixnerearly_idt_msg: 3438866cd9dSRoland McGrath .asciz "PANIC: early exception %02lx rip %lx:%lx error %lx cr2 %lx\n" 344250c2277SThomas Gleixnerearly_idt_ripmsg: 345250c2277SThomas Gleixner .asciz "RIP %s\n" 346076f9776SIngo Molnar#endif /* CONFIG_EARLY_PRINTK */ 34741bd4eacSAndi Kleen .previous 348250c2277SThomas Gleixner 349250c2277SThomas Gleixner.balign PAGE_SIZE 350250c2277SThomas Gleixner 351250c2277SThomas Gleixner#define NEXT_PAGE(name) \ 352250c2277SThomas Gleixner .balign PAGE_SIZE; \ 353250c2277SThomas GleixnerENTRY(name) 354250c2277SThomas Gleixner 355250c2277SThomas Gleixner/* Automate the creation of 1 to 1 mapping pmd entries */ 356250c2277SThomas Gleixner#define PMDS(START, PERM, COUNT) \ 357250c2277SThomas Gleixner i = 0 ; \ 358250c2277SThomas Gleixner .rept (COUNT) ; \ 3590e192b99SCyrill Gorcunov .quad (START) + (i << PMD_SHIFT) + (PERM) ; \ 360250c2277SThomas Gleixner i = i + 1 ; \ 361250c2277SThomas Gleixner .endr 362250c2277SThomas Gleixner 363250c2277SThomas Gleixner /* 364250c2277SThomas Gleixner * This default setting generates an ident mapping at address 0x100000 365250c2277SThomas Gleixner * and a mapping for the kernel that precisely maps virtual address 366250c2277SThomas Gleixner * 0xffffffff80000000 to physical address 0x000000. (always using 367250c2277SThomas Gleixner * 2Mbyte large pages provided by PAE mode) 368250c2277SThomas Gleixner */ 369250c2277SThomas GleixnerNEXT_PAGE(init_level4_pgt) 370250c2277SThomas Gleixner .quad level3_ident_pgt - __START_KERNEL_map + _KERNPG_TABLE 371a6523748SEduardo Habkost .org init_level4_pgt + L4_PAGE_OFFSET*8, 0 372250c2277SThomas Gleixner .quad level3_ident_pgt - __START_KERNEL_map + _KERNPG_TABLE 373a6523748SEduardo Habkost .org init_level4_pgt + L4_START_KERNEL*8, 0 374250c2277SThomas Gleixner /* (2^48-(2*1024*1024*1024))/(2^39) = 511 */ 375250c2277SThomas Gleixner .quad level3_kernel_pgt - __START_KERNEL_map + _PAGE_TABLE 376250c2277SThomas Gleixner 377250c2277SThomas GleixnerNEXT_PAGE(level3_ident_pgt) 378250c2277SThomas Gleixner .quad level2_ident_pgt - __START_KERNEL_map + _KERNPG_TABLE 379250c2277SThomas Gleixner .fill 511,8,0 380250c2277SThomas Gleixner 381250c2277SThomas GleixnerNEXT_PAGE(level3_kernel_pgt) 382a6523748SEduardo Habkost .fill L3_START_KERNEL,8,0 383250c2277SThomas Gleixner /* (2^48-(2*1024*1024*1024)-((2^39)*511))/(2^30) = 510 */ 384250c2277SThomas Gleixner .quad level2_kernel_pgt - __START_KERNEL_map + _KERNPG_TABLE 385250c2277SThomas Gleixner .quad level2_fixmap_pgt - __START_KERNEL_map + _PAGE_TABLE 386250c2277SThomas Gleixner 387250c2277SThomas GleixnerNEXT_PAGE(level2_fixmap_pgt) 3886596f242SIngo Molnar .fill 506,8,0 3896596f242SIngo Molnar .quad level1_fixmap_pgt - __START_KERNEL_map + _PAGE_TABLE 3906596f242SIngo Molnar /* 8MB reserved for vsyscalls + a 2MB hole = 4 + 1 entries */ 3916596f242SIngo Molnar .fill 5,8,0 3926596f242SIngo Molnar 3936596f242SIngo MolnarNEXT_PAGE(level1_fixmap_pgt) 394250c2277SThomas Gleixner .fill 512,8,0 395250c2277SThomas Gleixner 396250c2277SThomas GleixnerNEXT_PAGE(level2_ident_pgt) 397250c2277SThomas Gleixner /* Since I easily can, map the first 1G. 398250c2277SThomas Gleixner * Don't set NX because code runs from these pages. 399250c2277SThomas Gleixner */ 400b2bc2731SSuresh Siddha PMDS(0, __PAGE_KERNEL_IDENT_LARGE_EXEC, PTRS_PER_PMD) 401250c2277SThomas Gleixner 402250c2277SThomas GleixnerNEXT_PAGE(level2_kernel_pgt) 40388f3aec7SIngo Molnar /* 40485eb69a1SIngo Molnar * 512 MB kernel mapping. We spend a full page on this pagetable 40588f3aec7SIngo Molnar * anyway. 40688f3aec7SIngo Molnar * 40788f3aec7SIngo Molnar * The kernel code+data+bss must not be bigger than that. 40888f3aec7SIngo Molnar * 40985eb69a1SIngo Molnar * (NOTE: at +512MB starts the module area, see MODULES_VADDR. 41088f3aec7SIngo Molnar * If you want to increase this then increase MODULES_VADDR 41188f3aec7SIngo Molnar * too.) 41288f3aec7SIngo Molnar */ 4138490638cSJeremy Fitzhardinge PMDS(0, __PAGE_KERNEL_LARGE_EXEC, 414d4afe414SIngo Molnar KERNEL_IMAGE_SIZE/PMD_SIZE) 415250c2277SThomas Gleixner 416250c2277SThomas GleixnerNEXT_PAGE(level2_spare_pgt) 417250c2277SThomas Gleixner .fill 512, 8, 0 418250c2277SThomas Gleixner 419250c2277SThomas Gleixner#undef PMDS 420250c2277SThomas Gleixner#undef NEXT_PAGE 421250c2277SThomas Gleixner 422250c2277SThomas Gleixner .data 423250c2277SThomas Gleixner .align 16 424a939098aSGlauber Costa .globl early_gdt_descr 425a939098aSGlauber Costaearly_gdt_descr: 426a939098aSGlauber Costa .word GDT_ENTRIES*8-1 4273e5d8f97STejun Heoearly_gdt_descr_base: 428a939098aSGlauber Costa .quad per_cpu__gdt_page 429250c2277SThomas Gleixner 430250c2277SThomas GleixnerENTRY(phys_base) 431250c2277SThomas Gleixner /* This must match the first entry in level2_kernel_pgt */ 432250c2277SThomas Gleixner .quad 0x0000000000000000 433250c2277SThomas Gleixner 4348c5e5ac3SJeremy Fitzhardinge#include "../../x86/xen/xen-head.S" 435250c2277SThomas Gleixner 436250c2277SThomas Gleixner .section .bss, "aw", @nobits 437250c2277SThomas Gleixner .align L1_CACHE_BYTES 438250c2277SThomas GleixnerENTRY(idt_table) 439250c2277SThomas Gleixner .skip 256 * 16 440250c2277SThomas Gleixner 441250c2277SThomas Gleixner .section .bss.page_aligned, "aw", @nobits 442250c2277SThomas Gleixner .align PAGE_SIZE 443250c2277SThomas GleixnerENTRY(empty_zero_page) 444250c2277SThomas Gleixner .skip PAGE_SIZE 445