1250c2277SThomas Gleixner/* 2250c2277SThomas Gleixner * linux/arch/x86_64/kernel/head.S -- start in 32bit and switch to 64bit 3250c2277SThomas Gleixner * 4250c2277SThomas Gleixner * Copyright (C) 2000 Andrea Arcangeli <andrea@suse.de> SuSE 5250c2277SThomas Gleixner * Copyright (C) 2000 Pavel Machek <pavel@suse.cz> 6250c2277SThomas Gleixner * Copyright (C) 2000 Karsten Keil <kkeil@suse.de> 7250c2277SThomas Gleixner * Copyright (C) 2001,2002 Andi Kleen <ak@suse.de> 8250c2277SThomas Gleixner * Copyright (C) 2005 Eric Biederman <ebiederm@xmission.com> 9250c2277SThomas Gleixner */ 10250c2277SThomas Gleixner 11250c2277SThomas Gleixner 12250c2277SThomas Gleixner#include <linux/linkage.h> 13250c2277SThomas Gleixner#include <linux/threads.h> 14250c2277SThomas Gleixner#include <linux/init.h> 15250c2277SThomas Gleixner#include <asm/desc.h> 16250c2277SThomas Gleixner#include <asm/segment.h> 17250c2277SThomas Gleixner#include <asm/pgtable.h> 18250c2277SThomas Gleixner#include <asm/page.h> 19250c2277SThomas Gleixner#include <asm/msr.h> 20250c2277SThomas Gleixner#include <asm/cache.h> 21250c2277SThomas Gleixner 2249a69787SGlauber de Oliveira Costa#ifdef CONFIG_PARAVIRT 2349a69787SGlauber de Oliveira Costa#include <asm/asm-offsets.h> 2449a69787SGlauber de Oliveira Costa#include <asm/paravirt.h> 2549a69787SGlauber de Oliveira Costa#else 2649a69787SGlauber de Oliveira Costa#define GET_CR2_INTO_RCX movq %cr2, %rcx 2749a69787SGlauber de Oliveira Costa#endif 2849a69787SGlauber de Oliveira Costa 29250c2277SThomas Gleixner/* we are not able to switch in one step to the final KERNEL ADRESS SPACE 30250c2277SThomas Gleixner * because we need identity-mapped pages. 31250c2277SThomas Gleixner * 32250c2277SThomas Gleixner */ 33250c2277SThomas Gleixner 34250c2277SThomas Gleixner .text 35250c2277SThomas Gleixner .section .text.head 36250c2277SThomas Gleixner .code64 37250c2277SThomas Gleixner .globl startup_64 38250c2277SThomas Gleixnerstartup_64: 39250c2277SThomas Gleixner 40250c2277SThomas Gleixner /* 41250c2277SThomas Gleixner * At this point the CPU runs in 64bit mode CS.L = 1 CS.D = 1, 42250c2277SThomas Gleixner * and someone has loaded an identity mapped page table 43250c2277SThomas Gleixner * for us. These identity mapped page tables map all of the 44250c2277SThomas Gleixner * kernel pages and possibly all of memory. 45250c2277SThomas Gleixner * 46250c2277SThomas Gleixner * %esi holds a physical pointer to real_mode_data. 47250c2277SThomas Gleixner * 48250c2277SThomas Gleixner * We come here either directly from a 64bit bootloader, or from 49250c2277SThomas Gleixner * arch/x86_64/boot/compressed/head.S. 50250c2277SThomas Gleixner * 51250c2277SThomas Gleixner * We only come here initially at boot nothing else comes here. 52250c2277SThomas Gleixner * 53250c2277SThomas Gleixner * Since we may be loaded at an address different from what we were 54250c2277SThomas Gleixner * compiled to run at we first fixup the physical addresses in our page 55250c2277SThomas Gleixner * tables and then reload them. 56250c2277SThomas Gleixner */ 57250c2277SThomas Gleixner 58250c2277SThomas Gleixner /* Compute the delta between the address I am compiled to run at and the 59250c2277SThomas Gleixner * address I am actually running at. 60250c2277SThomas Gleixner */ 61250c2277SThomas Gleixner leaq _text(%rip), %rbp 62250c2277SThomas Gleixner subq $_text - __START_KERNEL_map, %rbp 63250c2277SThomas Gleixner 64250c2277SThomas Gleixner /* Is the address not 2M aligned? */ 65250c2277SThomas Gleixner movq %rbp, %rax 66250c2277SThomas Gleixner andl $~LARGE_PAGE_MASK, %eax 67250c2277SThomas Gleixner testl %eax, %eax 68250c2277SThomas Gleixner jnz bad_address 69250c2277SThomas Gleixner 70250c2277SThomas Gleixner /* Is the address too large? */ 71250c2277SThomas Gleixner leaq _text(%rip), %rdx 72250c2277SThomas Gleixner movq $PGDIR_SIZE, %rax 73250c2277SThomas Gleixner cmpq %rax, %rdx 74250c2277SThomas Gleixner jae bad_address 75250c2277SThomas Gleixner 76250c2277SThomas Gleixner /* Fixup the physical addresses in the page table 77250c2277SThomas Gleixner */ 78250c2277SThomas Gleixner addq %rbp, init_level4_pgt + 0(%rip) 79250c2277SThomas Gleixner addq %rbp, init_level4_pgt + (258*8)(%rip) 80250c2277SThomas Gleixner addq %rbp, init_level4_pgt + (511*8)(%rip) 81250c2277SThomas Gleixner 82250c2277SThomas Gleixner addq %rbp, level3_ident_pgt + 0(%rip) 83250c2277SThomas Gleixner 84250c2277SThomas Gleixner addq %rbp, level3_kernel_pgt + (510*8)(%rip) 85250c2277SThomas Gleixner addq %rbp, level3_kernel_pgt + (511*8)(%rip) 86250c2277SThomas Gleixner 87250c2277SThomas Gleixner addq %rbp, level2_fixmap_pgt + (506*8)(%rip) 88250c2277SThomas Gleixner 89250c2277SThomas Gleixner /* Add an Identity mapping if I am above 1G */ 90250c2277SThomas Gleixner leaq _text(%rip), %rdi 91250c2277SThomas Gleixner andq $LARGE_PAGE_MASK, %rdi 92250c2277SThomas Gleixner 93250c2277SThomas Gleixner movq %rdi, %rax 94250c2277SThomas Gleixner shrq $PUD_SHIFT, %rax 95250c2277SThomas Gleixner andq $(PTRS_PER_PUD - 1), %rax 96250c2277SThomas Gleixner jz ident_complete 97250c2277SThomas Gleixner 98250c2277SThomas Gleixner leaq (level2_spare_pgt - __START_KERNEL_map + _KERNPG_TABLE)(%rbp), %rdx 99250c2277SThomas Gleixner leaq level3_ident_pgt(%rip), %rbx 100250c2277SThomas Gleixner movq %rdx, 0(%rbx, %rax, 8) 101250c2277SThomas Gleixner 102250c2277SThomas Gleixner movq %rdi, %rax 103250c2277SThomas Gleixner shrq $PMD_SHIFT, %rax 104250c2277SThomas Gleixner andq $(PTRS_PER_PMD - 1), %rax 105250c2277SThomas Gleixner leaq __PAGE_KERNEL_LARGE_EXEC(%rdi), %rdx 106250c2277SThomas Gleixner leaq level2_spare_pgt(%rip), %rbx 107250c2277SThomas Gleixner movq %rdx, 0(%rbx, %rax, 8) 108250c2277SThomas Gleixnerident_complete: 109250c2277SThomas Gleixner 110250c2277SThomas Gleixner /* Fixup the kernel text+data virtual addresses 111250c2277SThomas Gleixner */ 112250c2277SThomas Gleixner leaq level2_kernel_pgt(%rip), %rdi 113250c2277SThomas Gleixner leaq 4096(%rdi), %r8 114250c2277SThomas Gleixner /* See if it is a valid page table entry */ 115250c2277SThomas Gleixner1: testq $1, 0(%rdi) 116250c2277SThomas Gleixner jz 2f 117250c2277SThomas Gleixner addq %rbp, 0(%rdi) 118250c2277SThomas Gleixner /* Go to the next page */ 119250c2277SThomas Gleixner2: addq $8, %rdi 120250c2277SThomas Gleixner cmp %r8, %rdi 121250c2277SThomas Gleixner jne 1b 122250c2277SThomas Gleixner 123250c2277SThomas Gleixner /* Fixup phys_base */ 124250c2277SThomas Gleixner addq %rbp, phys_base(%rip) 125250c2277SThomas Gleixner 126250c2277SThomas Gleixner#ifdef CONFIG_SMP 127250c2277SThomas Gleixner addq %rbp, trampoline_level4_pgt + 0(%rip) 128250c2277SThomas Gleixner addq %rbp, trampoline_level4_pgt + (511*8)(%rip) 129250c2277SThomas Gleixner#endif 130250c2277SThomas Gleixner#ifdef CONFIG_ACPI_SLEEP 131250c2277SThomas Gleixner addq %rbp, wakeup_level4_pgt + 0(%rip) 132250c2277SThomas Gleixner addq %rbp, wakeup_level4_pgt + (511*8)(%rip) 133250c2277SThomas Gleixner#endif 134250c2277SThomas Gleixner 135250c2277SThomas Gleixner /* Due to ENTRY(), sometimes the empty space gets filled with 136250c2277SThomas Gleixner * zeros. Better take a jmp than relying on empty space being 137250c2277SThomas Gleixner * filled with 0x90 (nop) 138250c2277SThomas Gleixner */ 139250c2277SThomas Gleixner jmp secondary_startup_64 140250c2277SThomas GleixnerENTRY(secondary_startup_64) 141250c2277SThomas Gleixner /* 142250c2277SThomas Gleixner * At this point the CPU runs in 64bit mode CS.L = 1 CS.D = 1, 143250c2277SThomas Gleixner * and someone has loaded a mapped page table. 144250c2277SThomas Gleixner * 145250c2277SThomas Gleixner * %esi holds a physical pointer to real_mode_data. 146250c2277SThomas Gleixner * 147250c2277SThomas Gleixner * We come here either from startup_64 (using physical addresses) 148250c2277SThomas Gleixner * or from trampoline.S (using virtual addresses). 149250c2277SThomas Gleixner * 150250c2277SThomas Gleixner * Using virtual addresses from trampoline.S removes the need 151250c2277SThomas Gleixner * to have any identity mapped pages in the kernel page table 152250c2277SThomas Gleixner * after the boot processor executes this code. 153250c2277SThomas Gleixner */ 154250c2277SThomas Gleixner 155250c2277SThomas Gleixner /* Enable PAE mode and PGE */ 156250c2277SThomas Gleixner xorq %rax, %rax 157250c2277SThomas Gleixner btsq $5, %rax 158250c2277SThomas Gleixner btsq $7, %rax 159250c2277SThomas Gleixner movq %rax, %cr4 160250c2277SThomas Gleixner 161250c2277SThomas Gleixner /* Setup early boot stage 4 level pagetables. */ 162250c2277SThomas Gleixner movq $(init_level4_pgt - __START_KERNEL_map), %rax 163250c2277SThomas Gleixner addq phys_base(%rip), %rax 164250c2277SThomas Gleixner movq %rax, %cr3 165250c2277SThomas Gleixner 166250c2277SThomas Gleixner /* Ensure I am executing from virtual addresses */ 167250c2277SThomas Gleixner movq $1f, %rax 168250c2277SThomas Gleixner jmp *%rax 169250c2277SThomas Gleixner1: 170250c2277SThomas Gleixner 171250c2277SThomas Gleixner /* Check if nx is implemented */ 172250c2277SThomas Gleixner movl $0x80000001, %eax 173250c2277SThomas Gleixner cpuid 174250c2277SThomas Gleixner movl %edx,%edi 175250c2277SThomas Gleixner 176250c2277SThomas Gleixner /* Setup EFER (Extended Feature Enable Register) */ 177250c2277SThomas Gleixner movl $MSR_EFER, %ecx 178250c2277SThomas Gleixner rdmsr 179250c2277SThomas Gleixner btsl $_EFER_SCE, %eax /* Enable System Call */ 180250c2277SThomas Gleixner btl $20,%edi /* No Execute supported? */ 181250c2277SThomas Gleixner jnc 1f 182250c2277SThomas Gleixner btsl $_EFER_NX, %eax 183250c2277SThomas Gleixner1: wrmsr /* Make changes effective */ 184250c2277SThomas Gleixner 185250c2277SThomas Gleixner /* Setup cr0 */ 186250c2277SThomas Gleixner#define CR0_PM 1 /* protected mode */ 187250c2277SThomas Gleixner#define CR0_MP (1<<1) 188250c2277SThomas Gleixner#define CR0_ET (1<<4) 189250c2277SThomas Gleixner#define CR0_NE (1<<5) 190250c2277SThomas Gleixner#define CR0_WP (1<<16) 191250c2277SThomas Gleixner#define CR0_AM (1<<18) 192250c2277SThomas Gleixner#define CR0_PAGING (1<<31) 193250c2277SThomas Gleixner movl $CR0_PM|CR0_MP|CR0_ET|CR0_NE|CR0_WP|CR0_AM|CR0_PAGING,%eax 194250c2277SThomas Gleixner /* Make changes effective */ 195250c2277SThomas Gleixner movq %rax, %cr0 196250c2277SThomas Gleixner 197250c2277SThomas Gleixner /* Setup a boot time stack */ 198250c2277SThomas Gleixner movq init_rsp(%rip),%rsp 199250c2277SThomas Gleixner 200250c2277SThomas Gleixner /* zero EFLAGS after setting rsp */ 201250c2277SThomas Gleixner pushq $0 202250c2277SThomas Gleixner popfq 203250c2277SThomas Gleixner 204250c2277SThomas Gleixner /* 205250c2277SThomas Gleixner * We must switch to a new descriptor in kernel space for the GDT 206250c2277SThomas Gleixner * because soon the kernel won't have access anymore to the userspace 207250c2277SThomas Gleixner * addresses where we're currently running on. We have to do that here 208250c2277SThomas Gleixner * because in 32bit we couldn't load a 64bit linear address. 209250c2277SThomas Gleixner */ 210250c2277SThomas Gleixner lgdt cpu_gdt_descr(%rip) 211250c2277SThomas Gleixner 212250c2277SThomas Gleixner /* set up data segments. actually 0 would do too */ 213250c2277SThomas Gleixner movl $__KERNEL_DS,%eax 214250c2277SThomas Gleixner movl %eax,%ds 215250c2277SThomas Gleixner movl %eax,%ss 216250c2277SThomas Gleixner movl %eax,%es 217250c2277SThomas Gleixner 218250c2277SThomas Gleixner /* 219250c2277SThomas Gleixner * We don't really need to load %fs or %gs, but load them anyway 220250c2277SThomas Gleixner * to kill any stale realmode selectors. This allows execution 221250c2277SThomas Gleixner * under VT hardware. 222250c2277SThomas Gleixner */ 223250c2277SThomas Gleixner movl %eax,%fs 224250c2277SThomas Gleixner movl %eax,%gs 225250c2277SThomas Gleixner 226250c2277SThomas Gleixner /* 227250c2277SThomas Gleixner * Setup up a dummy PDA. this is just for some early bootup code 228250c2277SThomas Gleixner * that does in_interrupt() 229250c2277SThomas Gleixner */ 230250c2277SThomas Gleixner movl $MSR_GS_BASE,%ecx 231250c2277SThomas Gleixner movq $empty_zero_page,%rax 232250c2277SThomas Gleixner movq %rax,%rdx 233250c2277SThomas Gleixner shrq $32,%rdx 234250c2277SThomas Gleixner wrmsr 235250c2277SThomas Gleixner 236250c2277SThomas Gleixner /* esi is pointer to real mode structure with interesting info. 237250c2277SThomas Gleixner pass it to C */ 238250c2277SThomas Gleixner movl %esi, %edi 239250c2277SThomas Gleixner 240250c2277SThomas Gleixner /* Finally jump to run C code and to be on real kernel address 241250c2277SThomas Gleixner * Since we are running on identity-mapped space we have to jump 242250c2277SThomas Gleixner * to the full 64bit address, this is only possible as indirect 243250c2277SThomas Gleixner * jump. In addition we need to ensure %cs is set so we make this 244250c2277SThomas Gleixner * a far return. 245250c2277SThomas Gleixner */ 246250c2277SThomas Gleixner movq initial_code(%rip),%rax 247250c2277SThomas Gleixner pushq $0 # fake return address to stop unwinder 248250c2277SThomas Gleixner pushq $__KERNEL_CS # set correct cs 249250c2277SThomas Gleixner pushq %rax # target address in negative space 250250c2277SThomas Gleixner lretq 251250c2277SThomas Gleixner 252250c2277SThomas Gleixner /* SMP bootup changes these two */ 253250c2277SThomas Gleixner#ifndef CONFIG_HOTPLUG_CPU 254250c2277SThomas Gleixner .pushsection .init.data 255250c2277SThomas Gleixner#endif 256250c2277SThomas Gleixner .align 8 257250c2277SThomas Gleixner .globl initial_code 258250c2277SThomas Gleixnerinitial_code: 259250c2277SThomas Gleixner .quad x86_64_start_kernel 260250c2277SThomas Gleixner#ifndef CONFIG_HOTPLUG_CPU 261250c2277SThomas Gleixner .popsection 262250c2277SThomas Gleixner#endif 263250c2277SThomas Gleixner .globl init_rsp 264250c2277SThomas Gleixnerinit_rsp: 265250c2277SThomas Gleixner .quad init_thread_union+THREAD_SIZE-8 266250c2277SThomas Gleixner 267250c2277SThomas Gleixnerbad_address: 268250c2277SThomas Gleixner jmp bad_address 269250c2277SThomas Gleixner 2708866cd9dSRoland McGrath.macro early_idt_tramp first, last 2718866cd9dSRoland McGrath .ifgt \last-\first 2728866cd9dSRoland McGrath early_idt_tramp \first, \last-1 2738866cd9dSRoland McGrath .endif 2748866cd9dSRoland McGrath movl $\last,%esi 2758866cd9dSRoland McGrath jmp early_idt_handler 2768866cd9dSRoland McGrath.endm 2778866cd9dSRoland McGrath 2788866cd9dSRoland McGrath .globl early_idt_handlers 2798866cd9dSRoland McGrathearly_idt_handlers: 2808866cd9dSRoland McGrath early_idt_tramp 0, 63 2818866cd9dSRoland McGrath early_idt_tramp 64, 127 2828866cd9dSRoland McGrath early_idt_tramp 128, 191 2838866cd9dSRoland McGrath early_idt_tramp 192, 255 2848866cd9dSRoland McGrath 285250c2277SThomas GleixnerENTRY(early_idt_handler) 286250c2277SThomas Gleixner cmpl $2,early_recursion_flag(%rip) 287250c2277SThomas Gleixner jz 1f 288250c2277SThomas Gleixner incl early_recursion_flag(%rip) 28949a69787SGlauber de Oliveira Costa GET_CR2_INTO_RCX 2908866cd9dSRoland McGrath movq %rcx,%r9 2918866cd9dSRoland McGrath xorl %r8d,%r8d # zero for error code 2928866cd9dSRoland McGrath movl %esi,%ecx # get vector number 2938866cd9dSRoland McGrath # Test %ecx against mask of vectors that push error code. 2948866cd9dSRoland McGrath cmpl $31,%ecx 2958866cd9dSRoland McGrath ja 0f 2968866cd9dSRoland McGrath movl $1,%eax 2978866cd9dSRoland McGrath salq %cl,%rax 2988866cd9dSRoland McGrath testl $0x27d00,%eax 2998866cd9dSRoland McGrath je 0f 3008866cd9dSRoland McGrath popq %r8 # get error code 3018866cd9dSRoland McGrath0: movq 0(%rsp),%rcx # get ip 3028866cd9dSRoland McGrath movq 8(%rsp),%rdx # get cs 3038866cd9dSRoland McGrath xorl %eax,%eax 304250c2277SThomas Gleixner leaq early_idt_msg(%rip),%rdi 305250c2277SThomas Gleixner call early_printk 306250c2277SThomas Gleixner cmpl $2,early_recursion_flag(%rip) 307250c2277SThomas Gleixner jz 1f 308250c2277SThomas Gleixner call dump_stack 309250c2277SThomas Gleixner#ifdef CONFIG_KALLSYMS 310250c2277SThomas Gleixner leaq early_idt_ripmsg(%rip),%rdi 311250c2277SThomas Gleixner movq 8(%rsp),%rsi # get rip again 312250c2277SThomas Gleixner call __print_symbol 313250c2277SThomas Gleixner#endif 314250c2277SThomas Gleixner1: hlt 315250c2277SThomas Gleixner jmp 1b 316250c2277SThomas Gleixnerearly_recursion_flag: 317250c2277SThomas Gleixner .long 0 318250c2277SThomas Gleixner 319250c2277SThomas Gleixnerearly_idt_msg: 3208866cd9dSRoland McGrath .asciz "PANIC: early exception %02lx rip %lx:%lx error %lx cr2 %lx\n" 321250c2277SThomas Gleixnerearly_idt_ripmsg: 322250c2277SThomas Gleixner .asciz "RIP %s\n" 323250c2277SThomas Gleixner 324250c2277SThomas Gleixner.balign PAGE_SIZE 325250c2277SThomas Gleixner 326250c2277SThomas Gleixner#define NEXT_PAGE(name) \ 327250c2277SThomas Gleixner .balign PAGE_SIZE; \ 328250c2277SThomas GleixnerENTRY(name) 329250c2277SThomas Gleixner 330250c2277SThomas Gleixner/* Automate the creation of 1 to 1 mapping pmd entries */ 331250c2277SThomas Gleixner#define PMDS(START, PERM, COUNT) \ 332250c2277SThomas Gleixner i = 0 ; \ 333250c2277SThomas Gleixner .rept (COUNT) ; \ 334250c2277SThomas Gleixner .quad (START) + (i << 21) + (PERM) ; \ 335250c2277SThomas Gleixner i = i + 1 ; \ 336250c2277SThomas Gleixner .endr 337250c2277SThomas Gleixner 338250c2277SThomas Gleixner /* 339250c2277SThomas Gleixner * This default setting generates an ident mapping at address 0x100000 340250c2277SThomas Gleixner * and a mapping for the kernel that precisely maps virtual address 341250c2277SThomas Gleixner * 0xffffffff80000000 to physical address 0x000000. (always using 342250c2277SThomas Gleixner * 2Mbyte large pages provided by PAE mode) 343250c2277SThomas Gleixner */ 344250c2277SThomas GleixnerNEXT_PAGE(init_level4_pgt) 345250c2277SThomas Gleixner .quad level3_ident_pgt - __START_KERNEL_map + _KERNPG_TABLE 346250c2277SThomas Gleixner .fill 257,8,0 347250c2277SThomas Gleixner .quad level3_ident_pgt - __START_KERNEL_map + _KERNPG_TABLE 348250c2277SThomas Gleixner .fill 252,8,0 349250c2277SThomas Gleixner /* (2^48-(2*1024*1024*1024))/(2^39) = 511 */ 350250c2277SThomas Gleixner .quad level3_kernel_pgt - __START_KERNEL_map + _PAGE_TABLE 351250c2277SThomas Gleixner 352250c2277SThomas GleixnerNEXT_PAGE(level3_ident_pgt) 353250c2277SThomas Gleixner .quad level2_ident_pgt - __START_KERNEL_map + _KERNPG_TABLE 354250c2277SThomas Gleixner .fill 511,8,0 355250c2277SThomas Gleixner 356250c2277SThomas GleixnerNEXT_PAGE(level3_kernel_pgt) 357250c2277SThomas Gleixner .fill 510,8,0 358250c2277SThomas Gleixner /* (2^48-(2*1024*1024*1024)-((2^39)*511))/(2^30) = 510 */ 359250c2277SThomas Gleixner .quad level2_kernel_pgt - __START_KERNEL_map + _KERNPG_TABLE 360250c2277SThomas Gleixner .quad level2_fixmap_pgt - __START_KERNEL_map + _PAGE_TABLE 361250c2277SThomas Gleixner 362250c2277SThomas GleixnerNEXT_PAGE(level2_fixmap_pgt) 363250c2277SThomas Gleixner .fill 506,8,0 364250c2277SThomas Gleixner .quad level1_fixmap_pgt - __START_KERNEL_map + _PAGE_TABLE 365250c2277SThomas Gleixner /* 8MB reserved for vsyscalls + a 2MB hole = 4 + 1 entries */ 366250c2277SThomas Gleixner .fill 5,8,0 367250c2277SThomas Gleixner 368250c2277SThomas GleixnerNEXT_PAGE(level1_fixmap_pgt) 369250c2277SThomas Gleixner .fill 512,8,0 370250c2277SThomas Gleixner 371250c2277SThomas GleixnerNEXT_PAGE(level2_ident_pgt) 372250c2277SThomas Gleixner /* Since I easily can, map the first 1G. 373250c2277SThomas Gleixner * Don't set NX because code runs from these pages. 374250c2277SThomas Gleixner */ 375250c2277SThomas Gleixner PMDS(0x0000000000000000, __PAGE_KERNEL_LARGE_EXEC, PTRS_PER_PMD) 376250c2277SThomas Gleixner 377250c2277SThomas GleixnerNEXT_PAGE(level2_kernel_pgt) 378250c2277SThomas Gleixner /* 40MB kernel mapping. The kernel code cannot be bigger than that. 379250c2277SThomas Gleixner When you change this change KERNEL_TEXT_SIZE in page.h too. */ 380250c2277SThomas Gleixner /* (2^48-(2*1024*1024*1024)-((2^39)*511)-((2^30)*510)) = 0 */ 381250c2277SThomas Gleixner PMDS(0x0000000000000000, __PAGE_KERNEL_LARGE_EXEC|_PAGE_GLOBAL, KERNEL_TEXT_SIZE/PMD_SIZE) 382250c2277SThomas Gleixner /* Module mapping starts here */ 383250c2277SThomas Gleixner .fill (PTRS_PER_PMD - (KERNEL_TEXT_SIZE/PMD_SIZE)),8,0 384250c2277SThomas Gleixner 385250c2277SThomas GleixnerNEXT_PAGE(level2_spare_pgt) 386250c2277SThomas Gleixner .fill 512,8,0 387250c2277SThomas Gleixner 388250c2277SThomas Gleixner#undef PMDS 389250c2277SThomas Gleixner#undef NEXT_PAGE 390250c2277SThomas Gleixner 391250c2277SThomas Gleixner .data 392250c2277SThomas Gleixner .align 16 393250c2277SThomas Gleixner .globl cpu_gdt_descr 394250c2277SThomas Gleixnercpu_gdt_descr: 395250c2277SThomas Gleixner .word gdt_end-cpu_gdt_table-1 396250c2277SThomas Gleixnergdt: 397250c2277SThomas Gleixner .quad cpu_gdt_table 398250c2277SThomas Gleixner#ifdef CONFIG_SMP 399250c2277SThomas Gleixner .rept NR_CPUS-1 400250c2277SThomas Gleixner .word 0 401250c2277SThomas Gleixner .quad 0 402250c2277SThomas Gleixner .endr 403250c2277SThomas Gleixner#endif 404250c2277SThomas Gleixner 405250c2277SThomas GleixnerENTRY(phys_base) 406250c2277SThomas Gleixner /* This must match the first entry in level2_kernel_pgt */ 407250c2277SThomas Gleixner .quad 0x0000000000000000 408250c2277SThomas Gleixner 409250c2277SThomas Gleixner/* We need valid kernel segments for data and code in long mode too 410250c2277SThomas Gleixner * IRET will check the segment types kkeil 2000/10/28 411250c2277SThomas Gleixner * Also sysret mandates a special GDT layout 412250c2277SThomas Gleixner */ 413250c2277SThomas Gleixner 414250c2277SThomas Gleixner .section .data.page_aligned, "aw" 415250c2277SThomas Gleixner .align PAGE_SIZE 416250c2277SThomas Gleixner 417250c2277SThomas Gleixner/* The TLS descriptors are currently at a different place compared to i386. 418250c2277SThomas Gleixner Hopefully nobody expects them at a fixed place (Wine?) */ 419250c2277SThomas Gleixner 420250c2277SThomas GleixnerENTRY(cpu_gdt_table) 421250c2277SThomas Gleixner .quad 0x0000000000000000 /* NULL descriptor */ 422250c2277SThomas Gleixner .quad 0x00cf9b000000ffff /* __KERNEL32_CS */ 423250c2277SThomas Gleixner .quad 0x00af9b000000ffff /* __KERNEL_CS */ 424250c2277SThomas Gleixner .quad 0x00cf93000000ffff /* __KERNEL_DS */ 425250c2277SThomas Gleixner .quad 0x00cffb000000ffff /* __USER32_CS */ 426250c2277SThomas Gleixner .quad 0x00cff3000000ffff /* __USER_DS, __USER32_DS */ 427250c2277SThomas Gleixner .quad 0x00affb000000ffff /* __USER_CS */ 428250c2277SThomas Gleixner .quad 0x0 /* unused */ 429250c2277SThomas Gleixner .quad 0,0 /* TSS */ 430250c2277SThomas Gleixner .quad 0,0 /* LDT */ 431250c2277SThomas Gleixner .quad 0,0,0 /* three TLS descriptors */ 432250c2277SThomas Gleixner .quad 0x0000f40000000000 /* node/CPU stored in limit */ 433250c2277SThomas Gleixnergdt_end: 434250c2277SThomas Gleixner /* asm/segment.h:GDT_ENTRIES must match this */ 435250c2277SThomas Gleixner /* This should be a multiple of the cache line size */ 436250c2277SThomas Gleixner /* GDTs of other CPUs are now dynamically allocated */ 437250c2277SThomas Gleixner 438250c2277SThomas Gleixner /* zero the remaining page */ 439250c2277SThomas Gleixner .fill PAGE_SIZE / 8 - GDT_ENTRIES,8,0 440250c2277SThomas Gleixner 441250c2277SThomas Gleixner .section .bss, "aw", @nobits 442250c2277SThomas Gleixner .align L1_CACHE_BYTES 443250c2277SThomas GleixnerENTRY(idt_table) 444250c2277SThomas Gleixner .skip 256 * 16 445250c2277SThomas Gleixner 446250c2277SThomas Gleixner .section .bss.page_aligned, "aw", @nobits 447250c2277SThomas Gleixner .align PAGE_SIZE 448250c2277SThomas GleixnerENTRY(empty_zero_page) 449250c2277SThomas Gleixner .skip PAGE_SIZE 450