1250c2277SThomas Gleixner/* 2250c2277SThomas Gleixner * linux/arch/x86_64/kernel/head.S -- start in 32bit and switch to 64bit 3250c2277SThomas Gleixner * 4250c2277SThomas Gleixner * Copyright (C) 2000 Andrea Arcangeli <andrea@suse.de> SuSE 5250c2277SThomas Gleixner * Copyright (C) 2000 Pavel Machek <pavel@suse.cz> 6250c2277SThomas Gleixner * Copyright (C) 2000 Karsten Keil <kkeil@suse.de> 7250c2277SThomas Gleixner * Copyright (C) 2001,2002 Andi Kleen <ak@suse.de> 8250c2277SThomas Gleixner * Copyright (C) 2005 Eric Biederman <ebiederm@xmission.com> 9250c2277SThomas Gleixner */ 10250c2277SThomas Gleixner 11250c2277SThomas Gleixner 12250c2277SThomas Gleixner#include <linux/linkage.h> 13250c2277SThomas Gleixner#include <linux/threads.h> 14250c2277SThomas Gleixner#include <linux/init.h> 15250c2277SThomas Gleixner#include <asm/segment.h> 16250c2277SThomas Gleixner#include <asm/pgtable.h> 17250c2277SThomas Gleixner#include <asm/page.h> 18250c2277SThomas Gleixner#include <asm/msr.h> 19250c2277SThomas Gleixner#include <asm/cache.h> 20369101daSCyrill Gorcunov#include <asm/processor-flags.h> 21b12d8db8STejun Heo#include <asm/percpu.h> 229900aa2fSH. Peter Anvin#include <asm/nops.h> 23250c2277SThomas Gleixner 2449a69787SGlauber de Oliveira Costa#ifdef CONFIG_PARAVIRT 2549a69787SGlauber de Oliveira Costa#include <asm/asm-offsets.h> 2649a69787SGlauber de Oliveira Costa#include <asm/paravirt.h> 27ffc4bc9cSH. Peter Anvin#define GET_CR2_INTO(reg) GET_CR2_INTO_RAX ; movq %rax, reg 2849a69787SGlauber de Oliveira Costa#else 29ffc4bc9cSH. Peter Anvin#define GET_CR2_INTO(reg) movq %cr2, reg 309900aa2fSH. Peter Anvin#define INTERRUPT_RETURN iretq 3149a69787SGlauber de Oliveira Costa#endif 3249a69787SGlauber de Oliveira Costa 333ad2f3fbSDaniel Mack/* we are not able to switch in one step to the final KERNEL ADDRESS SPACE 34250c2277SThomas Gleixner * because we need identity-mapped pages. 35250c2277SThomas Gleixner * 36250c2277SThomas Gleixner */ 37250c2277SThomas Gleixner 38a6523748SEduardo Habkost#define pud_index(x) (((x) >> PUD_SHIFT) & (PTRS_PER_PUD-1)) 39a6523748SEduardo Habkost 40a6523748SEduardo HabkostL4_PAGE_OFFSET = pgd_index(__PAGE_OFFSET) 41a6523748SEduardo HabkostL3_PAGE_OFFSET = pud_index(__PAGE_OFFSET) 42a6523748SEduardo HabkostL4_START_KERNEL = pgd_index(__START_KERNEL_map) 43a6523748SEduardo HabkostL3_START_KERNEL = pud_index(__START_KERNEL_map) 44a6523748SEduardo Habkost 45250c2277SThomas Gleixner .text 464ae59b91STim Abbott __HEAD 47250c2277SThomas Gleixner .code64 48250c2277SThomas Gleixner .globl startup_64 49250c2277SThomas Gleixnerstartup_64: 50250c2277SThomas Gleixner /* 511256276cSKonrad Rzeszutek Wilk * At this point the CPU runs in 64bit mode CS.L = 1 CS.D = 0, 52250c2277SThomas Gleixner * and someone has loaded an identity mapped page table 53250c2277SThomas Gleixner * for us. These identity mapped page tables map all of the 54250c2277SThomas Gleixner * kernel pages and possibly all of memory. 55250c2277SThomas Gleixner * 568170e6beSH. Peter Anvin * %rsi holds a physical pointer to real_mode_data. 57250c2277SThomas Gleixner * 58250c2277SThomas Gleixner * We come here either directly from a 64bit bootloader, or from 59250c2277SThomas Gleixner * arch/x86_64/boot/compressed/head.S. 60250c2277SThomas Gleixner * 61250c2277SThomas Gleixner * We only come here initially at boot nothing else comes here. 62250c2277SThomas Gleixner * 63250c2277SThomas Gleixner * Since we may be loaded at an address different from what we were 64250c2277SThomas Gleixner * compiled to run at we first fixup the physical addresses in our page 65250c2277SThomas Gleixner * tables and then reload them. 66250c2277SThomas Gleixner */ 67250c2277SThomas Gleixner 688170e6beSH. Peter Anvin /* 698170e6beSH. Peter Anvin * Compute the delta between the address I am compiled to run at and the 70250c2277SThomas Gleixner * address I am actually running at. 71250c2277SThomas Gleixner */ 72250c2277SThomas Gleixner leaq _text(%rip), %rbp 73250c2277SThomas Gleixner subq $_text - __START_KERNEL_map, %rbp 74250c2277SThomas Gleixner 75250c2277SThomas Gleixner /* Is the address not 2M aligned? */ 76250c2277SThomas Gleixner movq %rbp, %rax 7731422c51SAndi Kleen andl $~PMD_PAGE_MASK, %eax 78250c2277SThomas Gleixner testl %eax, %eax 79250c2277SThomas Gleixner jnz bad_address 80250c2277SThomas Gleixner 818170e6beSH. Peter Anvin /* 828170e6beSH. Peter Anvin * Is the address too large? 83250c2277SThomas Gleixner */ 848170e6beSH. Peter Anvin leaq _text(%rip), %rax 858170e6beSH. Peter Anvin shrq $MAX_PHYSMEM_BITS, %rax 868170e6beSH. Peter Anvin jnz bad_address 87250c2277SThomas Gleixner 888170e6beSH. Peter Anvin /* 898170e6beSH. Peter Anvin * Fixup the physical addresses in the page table 908170e6beSH. Peter Anvin */ 918170e6beSH. Peter Anvin addq %rbp, early_level4_pgt + (L4_START_KERNEL*8)(%rip) 92250c2277SThomas Gleixner 93250c2277SThomas Gleixner addq %rbp, level3_kernel_pgt + (510*8)(%rip) 94250c2277SThomas Gleixner addq %rbp, level3_kernel_pgt + (511*8)(%rip) 95250c2277SThomas Gleixner 96250c2277SThomas Gleixner addq %rbp, level2_fixmap_pgt + (506*8)(%rip) 97250c2277SThomas Gleixner 988170e6beSH. Peter Anvin /* 998170e6beSH. Peter Anvin * Set up the identity mapping for the switchover. These 1008170e6beSH. Peter Anvin * entries should *NOT* have the global bit set! This also 1018170e6beSH. Peter Anvin * creates a bunch of nonsense entries but that is fine -- 1028170e6beSH. Peter Anvin * it avoids problems around wraparound. 1038170e6beSH. Peter Anvin */ 104250c2277SThomas Gleixner leaq _text(%rip), %rdi 1058170e6beSH. Peter Anvin leaq early_level4_pgt(%rip), %rbx 106250c2277SThomas Gleixner 107250c2277SThomas Gleixner movq %rdi, %rax 1088170e6beSH. Peter Anvin shrq $PGDIR_SHIFT, %rax 1098170e6beSH. Peter Anvin 1108170e6beSH. Peter Anvin leaq (4096 + _KERNPG_TABLE)(%rbx), %rdx 1118170e6beSH. Peter Anvin movq %rdx, 0(%rbx,%rax,8) 1128170e6beSH. Peter Anvin movq %rdx, 8(%rbx,%rax,8) 1138170e6beSH. Peter Anvin 1148170e6beSH. Peter Anvin addq $4096, %rdx 1158170e6beSH. Peter Anvin movq %rdi, %rax 116250c2277SThomas Gleixner shrq $PUD_SHIFT, %rax 1178170e6beSH. Peter Anvin andl $(PTRS_PER_PUD-1), %eax 1188170e6beSH. Peter Anvin movq %rdx, (4096+0)(%rbx,%rax,8) 1198170e6beSH. Peter Anvin movq %rdx, (4096+8)(%rbx,%rax,8) 120250c2277SThomas Gleixner 1218170e6beSH. Peter Anvin addq $8192, %rbx 122250c2277SThomas Gleixner movq %rdi, %rax 1238170e6beSH. Peter Anvin shrq $PMD_SHIFT, %rdi 1248170e6beSH. Peter Anvin addq $(__PAGE_KERNEL_LARGE_EXEC & ~_PAGE_GLOBAL), %rax 1258170e6beSH. Peter Anvin leaq (_end - 1)(%rip), %rcx 1268170e6beSH. Peter Anvin shrq $PMD_SHIFT, %rcx 1278170e6beSH. Peter Anvin subq %rdi, %rcx 1288170e6beSH. Peter Anvin incl %ecx 1298170e6beSH. Peter Anvin 1308170e6beSH. Peter Anvin1: 1318170e6beSH. Peter Anvin andq $(PTRS_PER_PMD - 1), %rdi 1328170e6beSH. Peter Anvin movq %rax, (%rbx,%rdi,8) 1338170e6beSH. Peter Anvin incq %rdi 1348170e6beSH. Peter Anvin addq $PMD_SIZE, %rax 1358170e6beSH. Peter Anvin decl %ecx 1368170e6beSH. Peter Anvin jnz 1b 137250c2277SThomas Gleixner 13831eedd82SThomas Gleixner /* 13931eedd82SThomas Gleixner * Fixup the kernel text+data virtual addresses. Note that 14031eedd82SThomas Gleixner * we might write invalid pmds, when the kernel is relocated 14131eedd82SThomas Gleixner * cleanup_highmap() fixes this up along with the mappings 14231eedd82SThomas Gleixner * beyond _end. 143250c2277SThomas Gleixner */ 144250c2277SThomas Gleixner leaq level2_kernel_pgt(%rip), %rdi 145250c2277SThomas Gleixner leaq 4096(%rdi), %r8 146250c2277SThomas Gleixner /* See if it is a valid page table entry */ 147250c2277SThomas Gleixner1: testq $1, 0(%rdi) 148250c2277SThomas Gleixner jz 2f 149250c2277SThomas Gleixner addq %rbp, 0(%rdi) 150250c2277SThomas Gleixner /* Go to the next page */ 151250c2277SThomas Gleixner2: addq $8, %rdi 152250c2277SThomas Gleixner cmp %r8, %rdi 153250c2277SThomas Gleixner jne 1b 154250c2277SThomas Gleixner 155250c2277SThomas Gleixner /* Fixup phys_base */ 156250c2277SThomas Gleixner addq %rbp, phys_base(%rip) 157250c2277SThomas Gleixner 1588170e6beSH. Peter Anvin movq $(early_level4_pgt - __START_KERNEL_map), %rax 1598170e6beSH. Peter Anvin jmp 1f 160250c2277SThomas GleixnerENTRY(secondary_startup_64) 161250c2277SThomas Gleixner /* 1621256276cSKonrad Rzeszutek Wilk * At this point the CPU runs in 64bit mode CS.L = 1 CS.D = 0, 163250c2277SThomas Gleixner * and someone has loaded a mapped page table. 164250c2277SThomas Gleixner * 1658170e6beSH. Peter Anvin * %rsi holds a physical pointer to real_mode_data. 166250c2277SThomas Gleixner * 167250c2277SThomas Gleixner * We come here either from startup_64 (using physical addresses) 168250c2277SThomas Gleixner * or from trampoline.S (using virtual addresses). 169250c2277SThomas Gleixner * 170250c2277SThomas Gleixner * Using virtual addresses from trampoline.S removes the need 171250c2277SThomas Gleixner * to have any identity mapped pages in the kernel page table 172250c2277SThomas Gleixner * after the boot processor executes this code. 173250c2277SThomas Gleixner */ 174250c2277SThomas Gleixner 1758170e6beSH. Peter Anvin movq $(init_level4_pgt - __START_KERNEL_map), %rax 1768170e6beSH. Peter Anvin1: 1778170e6beSH. Peter Anvin 178250c2277SThomas Gleixner /* Enable PAE mode and PGE */ 1798170e6beSH. Peter Anvin movl $(X86_CR4_PAE | X86_CR4_PGE), %ecx 1808170e6beSH. Peter Anvin movq %rcx, %cr4 181250c2277SThomas Gleixner 182250c2277SThomas Gleixner /* Setup early boot stage 4 level pagetables. */ 183250c2277SThomas Gleixner addq phys_base(%rip), %rax 184250c2277SThomas Gleixner movq %rax, %cr3 185250c2277SThomas Gleixner 186250c2277SThomas Gleixner /* Ensure I am executing from virtual addresses */ 187250c2277SThomas Gleixner movq $1f, %rax 188250c2277SThomas Gleixner jmp *%rax 189250c2277SThomas Gleixner1: 190250c2277SThomas Gleixner 191250c2277SThomas Gleixner /* Check if nx is implemented */ 192250c2277SThomas Gleixner movl $0x80000001, %eax 193250c2277SThomas Gleixner cpuid 194250c2277SThomas Gleixner movl %edx,%edi 195250c2277SThomas Gleixner 196250c2277SThomas Gleixner /* Setup EFER (Extended Feature Enable Register) */ 197250c2277SThomas Gleixner movl $MSR_EFER, %ecx 198250c2277SThomas Gleixner rdmsr 199250c2277SThomas Gleixner btsl $_EFER_SCE, %eax /* Enable System Call */ 200250c2277SThomas Gleixner btl $20,%edi /* No Execute supported? */ 201250c2277SThomas Gleixner jnc 1f 202250c2277SThomas Gleixner btsl $_EFER_NX, %eax 20378d77df7SH. Peter Anvin btsq $_PAGE_BIT_NX,early_pmd_flags(%rip) 204250c2277SThomas Gleixner1: wrmsr /* Make changes effective */ 205250c2277SThomas Gleixner 206250c2277SThomas Gleixner /* Setup cr0 */ 207369101daSCyrill Gorcunov#define CR0_STATE (X86_CR0_PE | X86_CR0_MP | X86_CR0_ET | \ 208369101daSCyrill Gorcunov X86_CR0_NE | X86_CR0_WP | X86_CR0_AM | \ 209369101daSCyrill Gorcunov X86_CR0_PG) 210369101daSCyrill Gorcunov movl $CR0_STATE, %eax 211250c2277SThomas Gleixner /* Make changes effective */ 212250c2277SThomas Gleixner movq %rax, %cr0 213250c2277SThomas Gleixner 214250c2277SThomas Gleixner /* Setup a boot time stack */ 2159cf4f298SGlauber Costa movq stack_start(%rip), %rsp 216250c2277SThomas Gleixner 217250c2277SThomas Gleixner /* zero EFLAGS after setting rsp */ 218250c2277SThomas Gleixner pushq $0 219250c2277SThomas Gleixner popfq 220250c2277SThomas Gleixner 221250c2277SThomas Gleixner /* 222250c2277SThomas Gleixner * We must switch to a new descriptor in kernel space for the GDT 223250c2277SThomas Gleixner * because soon the kernel won't have access anymore to the userspace 224250c2277SThomas Gleixner * addresses where we're currently running on. We have to do that here 225250c2277SThomas Gleixner * because in 32bit we couldn't load a 64bit linear address. 226250c2277SThomas Gleixner */ 227a939098aSGlauber Costa lgdt early_gdt_descr(%rip) 228250c2277SThomas Gleixner 2298ec6993dSBrian Gerst /* set up data segments */ 2308ec6993dSBrian Gerst xorl %eax,%eax 231250c2277SThomas Gleixner movl %eax,%ds 232250c2277SThomas Gleixner movl %eax,%ss 233250c2277SThomas Gleixner movl %eax,%es 234250c2277SThomas Gleixner 235250c2277SThomas Gleixner /* 236250c2277SThomas Gleixner * We don't really need to load %fs or %gs, but load them anyway 237250c2277SThomas Gleixner * to kill any stale realmode selectors. This allows execution 238250c2277SThomas Gleixner * under VT hardware. 239250c2277SThomas Gleixner */ 240250c2277SThomas Gleixner movl %eax,%fs 241250c2277SThomas Gleixner movl %eax,%gs 242250c2277SThomas Gleixner 243f32ff538STejun Heo /* Set up %gs. 244f32ff538STejun Heo * 245947e76cdSBrian Gerst * The base of %gs always points to the bottom of the irqstack 246947e76cdSBrian Gerst * union. If the stack protector canary is enabled, it is 247947e76cdSBrian Gerst * located at %gs:40. Note that, on SMP, the boot cpu uses 248947e76cdSBrian Gerst * init data section till per cpu areas are set up. 249250c2277SThomas Gleixner */ 250250c2277SThomas Gleixner movl $MSR_GS_BASE,%ecx 251650fb439SBrian Gerst movl initial_gs(%rip),%eax 252650fb439SBrian Gerst movl initial_gs+4(%rip),%edx 253250c2277SThomas Gleixner wrmsr 254250c2277SThomas Gleixner 2558170e6beSH. Peter Anvin /* rsi is pointer to real mode structure with interesting info. 256250c2277SThomas Gleixner pass it to C */ 2578170e6beSH. Peter Anvin movq %rsi, %rdi 258250c2277SThomas Gleixner 259250c2277SThomas Gleixner /* Finally jump to run C code and to be on real kernel address 260250c2277SThomas Gleixner * Since we are running on identity-mapped space we have to jump 261250c2277SThomas Gleixner * to the full 64bit address, this is only possible as indirect 262250c2277SThomas Gleixner * jump. In addition we need to ensure %cs is set so we make this 263250c2277SThomas Gleixner * a far return. 2648170e6beSH. Peter Anvin * 2658170e6beSH. Peter Anvin * Note: do not change to far jump indirect with 64bit offset. 2668170e6beSH. Peter Anvin * 2678170e6beSH. Peter Anvin * AMD does not support far jump indirect with 64bit offset. 2688170e6beSH. Peter Anvin * AMD64 Architecture Programmer's Manual, Volume 3: states only 2698170e6beSH. Peter Anvin * JMP FAR mem16:16 FF /5 Far jump indirect, 2708170e6beSH. Peter Anvin * with the target specified by a far pointer in memory. 2718170e6beSH. Peter Anvin * JMP FAR mem16:32 FF /5 Far jump indirect, 2728170e6beSH. Peter Anvin * with the target specified by a far pointer in memory. 2738170e6beSH. Peter Anvin * 2748170e6beSH. Peter Anvin * Intel64 does support 64bit offset. 2758170e6beSH. Peter Anvin * Software Developer Manual Vol 2: states: 2768170e6beSH. Peter Anvin * FF /5 JMP m16:16 Jump far, absolute indirect, 2778170e6beSH. Peter Anvin * address given in m16:16 2788170e6beSH. Peter Anvin * FF /5 JMP m16:32 Jump far, absolute indirect, 2798170e6beSH. Peter Anvin * address given in m16:32. 2808170e6beSH. Peter Anvin * REX.W + FF /5 JMP m16:64 Jump far, absolute indirect, 2818170e6beSH. Peter Anvin * address given in m16:64. 282250c2277SThomas Gleixner */ 283250c2277SThomas Gleixner movq initial_code(%rip),%rax 284250c2277SThomas Gleixner pushq $0 # fake return address to stop unwinder 285250c2277SThomas Gleixner pushq $__KERNEL_CS # set correct cs 286250c2277SThomas Gleixner pushq %rax # target address in negative space 287250c2277SThomas Gleixner lretq 288250c2277SThomas Gleixner 28942e78e97SFenghua Yu#ifdef CONFIG_HOTPLUG_CPU 29042e78e97SFenghua Yu/* 29142e78e97SFenghua Yu * Boot CPU0 entry point. It's called from play_dead(). Everything has been set 29242e78e97SFenghua Yu * up already except stack. We just set up stack here. Then call 29342e78e97SFenghua Yu * start_secondary(). 29442e78e97SFenghua Yu */ 29542e78e97SFenghua YuENTRY(start_cpu0) 29642e78e97SFenghua Yu movq stack_start(%rip),%rsp 29742e78e97SFenghua Yu movq initial_code(%rip),%rax 29842e78e97SFenghua Yu pushq $0 # fake return address to stop unwinder 29942e78e97SFenghua Yu pushq $__KERNEL_CS # set correct cs 30042e78e97SFenghua Yu pushq %rax # target address in negative space 30142e78e97SFenghua Yu lretq 30242e78e97SFenghua YuENDPROC(start_cpu0) 30342e78e97SFenghua Yu#endif 30442e78e97SFenghua Yu 305250c2277SThomas Gleixner /* SMP bootup changes these two */ 306da5968aeSSam Ravnborg __REFDATA 3078170e6beSH. Peter Anvin .balign 8 3088170e6beSH. Peter Anvin GLOBAL(initial_code) 309250c2277SThomas Gleixner .quad x86_64_start_kernel 3108170e6beSH. Peter Anvin GLOBAL(initial_gs) 3112add8e23SBrian Gerst .quad INIT_PER_CPU_VAR(irq_stack_union) 312f1fbabb3SSam Ravnborg 3138170e6beSH. Peter Anvin GLOBAL(stack_start) 314250c2277SThomas Gleixner .quad init_thread_union+THREAD_SIZE-8 3159cf4f298SGlauber Costa .word 0 316b9af7c0dSSuresh Siddha __FINITDATA 317250c2277SThomas Gleixner 318250c2277SThomas Gleixnerbad_address: 319250c2277SThomas Gleixner jmp bad_address 320250c2277SThomas Gleixner 3218170e6beSH. Peter Anvin __INIT 3228866cd9dSRoland McGrath .globl early_idt_handlers 3238866cd9dSRoland McGrathearly_idt_handlers: 3249900aa2fSH. Peter Anvin # 104(%rsp) %rflags 3259900aa2fSH. Peter Anvin # 96(%rsp) %cs 3269900aa2fSH. Peter Anvin # 88(%rsp) %rip 3279900aa2fSH. Peter Anvin # 80(%rsp) error code 328749c970aSAndi Kleen i = 0 329749c970aSAndi Kleen .rept NUM_EXCEPTION_VECTORS 3309900aa2fSH. Peter Anvin .if (EXCEPTION_ERRCODE_MASK >> i) & 1 3319900aa2fSH. Peter Anvin ASM_NOP2 3329900aa2fSH. Peter Anvin .else 3339900aa2fSH. Peter Anvin pushq $0 # Dummy error code, to make stack frame uniform 3349900aa2fSH. Peter Anvin .endif 3359900aa2fSH. Peter Anvin pushq $i # 72(%rsp) Vector number 336749c970aSAndi Kleen jmp early_idt_handler 337749c970aSAndi Kleen i = i + 1 338749c970aSAndi Kleen .endr 3398866cd9dSRoland McGrath 340ac630dd9SLinus Torvalds/* This is global to keep gas from relaxing the jumps */ 341250c2277SThomas GleixnerENTRY(early_idt_handler) 3429900aa2fSH. Peter Anvin cld 3439900aa2fSH. Peter Anvin 344250c2277SThomas Gleixner cmpl $2,early_recursion_flag(%rip) 345250c2277SThomas Gleixner jz 1f 346250c2277SThomas Gleixner incl early_recursion_flag(%rip) 3479900aa2fSH. Peter Anvin 3489900aa2fSH. Peter Anvin pushq %rax # 64(%rsp) 3499900aa2fSH. Peter Anvin pushq %rcx # 56(%rsp) 3509900aa2fSH. Peter Anvin pushq %rdx # 48(%rsp) 3519900aa2fSH. Peter Anvin pushq %rsi # 40(%rsp) 3529900aa2fSH. Peter Anvin pushq %rdi # 32(%rsp) 3539900aa2fSH. Peter Anvin pushq %r8 # 24(%rsp) 3549900aa2fSH. Peter Anvin pushq %r9 # 16(%rsp) 3559900aa2fSH. Peter Anvin pushq %r10 # 8(%rsp) 3569900aa2fSH. Peter Anvin pushq %r11 # 0(%rsp) 3579900aa2fSH. Peter Anvin 3589900aa2fSH. Peter Anvin cmpl $__KERNEL_CS,96(%rsp) 3598170e6beSH. Peter Anvin jne 11f 3609900aa2fSH. Peter Anvin 3618170e6beSH. Peter Anvin cmpl $14,72(%rsp) # Page fault? 3628170e6beSH. Peter Anvin jnz 10f 3638170e6beSH. Peter Anvin GET_CR2_INTO(%rdi) # can clobber any volatile register if pv 3648170e6beSH. Peter Anvin call early_make_pgtable 3658170e6beSH. Peter Anvin andl %eax,%eax 3668170e6beSH. Peter Anvin jz 20f # All good 3678170e6beSH. Peter Anvin 3688170e6beSH. Peter Anvin10: 3699900aa2fSH. Peter Anvin leaq 88(%rsp),%rdi # Pointer to %rip 3709900aa2fSH. Peter Anvin call early_fixup_exception 3719900aa2fSH. Peter Anvin andl %eax,%eax 3729900aa2fSH. Peter Anvin jnz 20f # Found an exception entry 3739900aa2fSH. Peter Anvin 3748170e6beSH. Peter Anvin11: 3759900aa2fSH. Peter Anvin#ifdef CONFIG_EARLY_PRINTK 3769900aa2fSH. Peter Anvin GET_CR2_INTO(%r9) # can clobber any volatile register if pv 3779900aa2fSH. Peter Anvin movl 80(%rsp),%r8d # error code 3789900aa2fSH. Peter Anvin movl 72(%rsp),%esi # vector number 3799900aa2fSH. Peter Anvin movl 96(%rsp),%edx # %cs 3809900aa2fSH. Peter Anvin movq 88(%rsp),%rcx # %rip 3818866cd9dSRoland McGrath xorl %eax,%eax 382250c2277SThomas Gleixner leaq early_idt_msg(%rip),%rdi 383250c2277SThomas Gleixner call early_printk 384250c2277SThomas Gleixner cmpl $2,early_recursion_flag(%rip) 385250c2277SThomas Gleixner jz 1f 386250c2277SThomas Gleixner call dump_stack 387250c2277SThomas Gleixner#ifdef CONFIG_KALLSYMS 388250c2277SThomas Gleixner leaq early_idt_ripmsg(%rip),%rdi 3899900aa2fSH. Peter Anvin movq 40(%rsp),%rsi # %rip again 390250c2277SThomas Gleixner call __print_symbol 391250c2277SThomas Gleixner#endif 392076f9776SIngo Molnar#endif /* EARLY_PRINTK */ 393250c2277SThomas Gleixner1: hlt 394250c2277SThomas Gleixner jmp 1b 395076f9776SIngo Molnar 3968170e6beSH. Peter Anvin20: # Exception table entry found or page table generated 3979900aa2fSH. Peter Anvin popq %r11 3989900aa2fSH. Peter Anvin popq %r10 3999900aa2fSH. Peter Anvin popq %r9 4009900aa2fSH. Peter Anvin popq %r8 4019900aa2fSH. Peter Anvin popq %rdi 4029900aa2fSH. Peter Anvin popq %rsi 4039900aa2fSH. Peter Anvin popq %rdx 4049900aa2fSH. Peter Anvin popq %rcx 4059900aa2fSH. Peter Anvin popq %rax 4069900aa2fSH. Peter Anvin addq $16,%rsp # drop vector number and error code 4079900aa2fSH. Peter Anvin decl early_recursion_flag(%rip) 4089900aa2fSH. Peter Anvin INTERRUPT_RETURN 409ac630dd9SLinus TorvaldsENDPROC(early_idt_handler) 4109900aa2fSH. Peter Anvin 4118170e6beSH. Peter Anvin __INITDATA 4128170e6beSH. Peter Anvin 4139900aa2fSH. Peter Anvin .balign 4 414250c2277SThomas Gleixnerearly_recursion_flag: 415250c2277SThomas Gleixner .long 0 416250c2277SThomas Gleixner 4179900aa2fSH. Peter Anvin#ifdef CONFIG_EARLY_PRINTK 418250c2277SThomas Gleixnerearly_idt_msg: 4198866cd9dSRoland McGrath .asciz "PANIC: early exception %02lx rip %lx:%lx error %lx cr2 %lx\n" 420250c2277SThomas Gleixnerearly_idt_ripmsg: 421250c2277SThomas Gleixner .asciz "RIP %s\n" 422076f9776SIngo Molnar#endif /* CONFIG_EARLY_PRINTK */ 423250c2277SThomas Gleixner 424250c2277SThomas Gleixner#define NEXT_PAGE(name) \ 425250c2277SThomas Gleixner .balign PAGE_SIZE; \ 4268170e6beSH. Peter AnvinGLOBAL(name) 427250c2277SThomas Gleixner 428250c2277SThomas Gleixner/* Automate the creation of 1 to 1 mapping pmd entries */ 429250c2277SThomas Gleixner#define PMDS(START, PERM, COUNT) \ 430250c2277SThomas Gleixner i = 0 ; \ 431250c2277SThomas Gleixner .rept (COUNT) ; \ 4320e192b99SCyrill Gorcunov .quad (START) + (i << PMD_SHIFT) + (PERM) ; \ 433250c2277SThomas Gleixner i = i + 1 ; \ 434250c2277SThomas Gleixner .endr 435250c2277SThomas Gleixner 4368170e6beSH. Peter Anvin __INITDATA 4378170e6beSH. Peter AnvinNEXT_PAGE(early_level4_pgt) 4388170e6beSH. Peter Anvin .fill 511,8,0 4398170e6beSH. Peter Anvin .quad level3_kernel_pgt - __START_KERNEL_map + _PAGE_TABLE 4408170e6beSH. Peter Anvin 4418170e6beSH. Peter AnvinNEXT_PAGE(early_dynamic_pgts) 4428170e6beSH. Peter Anvin .fill 512*EARLY_DYNAMIC_PAGE_TABLES,8,0 4438170e6beSH. Peter Anvin 444b9af7c0dSSuresh Siddha .data 4458170e6beSH. Peter Anvin 4468170e6beSH. Peter Anvin#ifndef CONFIG_XEN 4478170e6beSH. Peter AnvinNEXT_PAGE(init_level4_pgt) 4488170e6beSH. Peter Anvin .fill 512,8,0 4498170e6beSH. Peter Anvin#else 450250c2277SThomas GleixnerNEXT_PAGE(init_level4_pgt) 451250c2277SThomas Gleixner .quad level3_ident_pgt - __START_KERNEL_map + _KERNPG_TABLE 452a6523748SEduardo Habkost .org init_level4_pgt + L4_PAGE_OFFSET*8, 0 453250c2277SThomas Gleixner .quad level3_ident_pgt - __START_KERNEL_map + _KERNPG_TABLE 454a6523748SEduardo Habkost .org init_level4_pgt + L4_START_KERNEL*8, 0 455250c2277SThomas Gleixner /* (2^48-(2*1024*1024*1024))/(2^39) = 511 */ 456250c2277SThomas Gleixner .quad level3_kernel_pgt - __START_KERNEL_map + _PAGE_TABLE 457250c2277SThomas Gleixner 458250c2277SThomas GleixnerNEXT_PAGE(level3_ident_pgt) 459250c2277SThomas Gleixner .quad level2_ident_pgt - __START_KERNEL_map + _KERNPG_TABLE 460250c2277SThomas Gleixner .fill 511, 8, 0 4618170e6beSH. Peter AnvinNEXT_PAGE(level2_ident_pgt) 4628170e6beSH. Peter Anvin /* Since I easily can, map the first 1G. 4638170e6beSH. Peter Anvin * Don't set NX because code runs from these pages. 4648170e6beSH. Peter Anvin */ 4658170e6beSH. Peter Anvin PMDS(0, __PAGE_KERNEL_IDENT_LARGE_EXEC, PTRS_PER_PMD) 4668170e6beSH. Peter Anvin#endif 467250c2277SThomas Gleixner 468250c2277SThomas GleixnerNEXT_PAGE(level3_kernel_pgt) 469a6523748SEduardo Habkost .fill L3_START_KERNEL,8,0 470250c2277SThomas Gleixner /* (2^48-(2*1024*1024*1024)-((2^39)*511))/(2^30) = 510 */ 471250c2277SThomas Gleixner .quad level2_kernel_pgt - __START_KERNEL_map + _KERNPG_TABLE 472250c2277SThomas Gleixner .quad level2_fixmap_pgt - __START_KERNEL_map + _PAGE_TABLE 473250c2277SThomas Gleixner 474250c2277SThomas GleixnerNEXT_PAGE(level2_kernel_pgt) 47588f3aec7SIngo Molnar /* 47685eb69a1SIngo Molnar * 512 MB kernel mapping. We spend a full page on this pagetable 47788f3aec7SIngo Molnar * anyway. 47888f3aec7SIngo Molnar * 47988f3aec7SIngo Molnar * The kernel code+data+bss must not be bigger than that. 48088f3aec7SIngo Molnar * 48185eb69a1SIngo Molnar * (NOTE: at +512MB starts the module area, see MODULES_VADDR. 48288f3aec7SIngo Molnar * If you want to increase this then increase MODULES_VADDR 48388f3aec7SIngo Molnar * too.) 48488f3aec7SIngo Molnar */ 4858490638cSJeremy Fitzhardinge PMDS(0, __PAGE_KERNEL_LARGE_EXEC, 486d4afe414SIngo Molnar KERNEL_IMAGE_SIZE/PMD_SIZE) 487250c2277SThomas Gleixner 4888170e6beSH. Peter AnvinNEXT_PAGE(level2_fixmap_pgt) 4898170e6beSH. Peter Anvin .fill 506,8,0 4908170e6beSH. Peter Anvin .quad level1_fixmap_pgt - __START_KERNEL_map + _PAGE_TABLE 4918170e6beSH. Peter Anvin /* 8MB reserved for vsyscalls + a 2MB hole = 4 + 1 entries */ 4928170e6beSH. Peter Anvin .fill 5,8,0 4938170e6beSH. Peter Anvin 4948170e6beSH. Peter AnvinNEXT_PAGE(level1_fixmap_pgt) 495250c2277SThomas Gleixner .fill 512,8,0 496250c2277SThomas Gleixner 497250c2277SThomas Gleixner#undef PMDS 498250c2277SThomas Gleixner 499250c2277SThomas Gleixner .data 500250c2277SThomas Gleixner .align 16 501a939098aSGlauber Costa .globl early_gdt_descr 502a939098aSGlauber Costaearly_gdt_descr: 503a939098aSGlauber Costa .word GDT_ENTRIES*8-1 5043e5d8f97STejun Heoearly_gdt_descr_base: 5052add8e23SBrian Gerst .quad INIT_PER_CPU_VAR(gdt_page) 506250c2277SThomas Gleixner 507250c2277SThomas GleixnerENTRY(phys_base) 508250c2277SThomas Gleixner /* This must match the first entry in level2_kernel_pgt */ 509250c2277SThomas Gleixner .quad 0x0000000000000000 510250c2277SThomas Gleixner 5118c5e5ac3SJeremy Fitzhardinge#include "../../x86/xen/xen-head.S" 512250c2277SThomas Gleixner 513250c2277SThomas Gleixner .section .bss, "aw", @nobits 514250c2277SThomas Gleixner .align L1_CACHE_BYTES 515250c2277SThomas GleixnerENTRY(idt_table) 5165e112ae2SCyrill Gorcunov .skip IDT_ENTRIES * 16 517250c2277SThomas Gleixner 518228bdaa9SSteven Rostedt .align L1_CACHE_BYTES 519228bdaa9SSteven RostedtENTRY(nmi_idt_table) 520228bdaa9SSteven Rostedt .skip IDT_ENTRIES * 16 521228bdaa9SSteven Rostedt 52202b7da37STim Abbott __PAGE_ALIGNED_BSS 5238170e6beSH. Peter AnvinNEXT_PAGE(empty_zero_page) 524250c2277SThomas Gleixner .skip PAGE_SIZE 525