1250c2277SThomas Gleixner/* 2250c2277SThomas Gleixner * linux/arch/x86_64/kernel/head.S -- start in 32bit and switch to 64bit 3250c2277SThomas Gleixner * 4250c2277SThomas Gleixner * Copyright (C) 2000 Andrea Arcangeli <andrea@suse.de> SuSE 5250c2277SThomas Gleixner * Copyright (C) 2000 Pavel Machek <pavel@suse.cz> 6250c2277SThomas Gleixner * Copyright (C) 2000 Karsten Keil <kkeil@suse.de> 7250c2277SThomas Gleixner * Copyright (C) 2001,2002 Andi Kleen <ak@suse.de> 8250c2277SThomas Gleixner * Copyright (C) 2005 Eric Biederman <ebiederm@xmission.com> 9250c2277SThomas Gleixner */ 10250c2277SThomas Gleixner 11250c2277SThomas Gleixner 12250c2277SThomas Gleixner#include <linux/linkage.h> 13250c2277SThomas Gleixner#include <linux/threads.h> 14250c2277SThomas Gleixner#include <linux/init.h> 15250c2277SThomas Gleixner#include <asm/desc.h> 16250c2277SThomas Gleixner#include <asm/segment.h> 17250c2277SThomas Gleixner#include <asm/pgtable.h> 18250c2277SThomas Gleixner#include <asm/page.h> 19250c2277SThomas Gleixner#include <asm/msr.h> 20250c2277SThomas Gleixner#include <asm/cache.h> 21250c2277SThomas Gleixner 22250c2277SThomas Gleixner/* we are not able to switch in one step to the final KERNEL ADRESS SPACE 23250c2277SThomas Gleixner * because we need identity-mapped pages. 24250c2277SThomas Gleixner * 25250c2277SThomas Gleixner */ 26250c2277SThomas Gleixner 27250c2277SThomas Gleixner .text 28250c2277SThomas Gleixner .section .text.head 29250c2277SThomas Gleixner .code64 30250c2277SThomas Gleixner .globl startup_64 31250c2277SThomas Gleixnerstartup_64: 32250c2277SThomas Gleixner 33250c2277SThomas Gleixner /* 34250c2277SThomas Gleixner * At this point the CPU runs in 64bit mode CS.L = 1 CS.D = 1, 35250c2277SThomas Gleixner * and someone has loaded an identity mapped page table 36250c2277SThomas Gleixner * for us. These identity mapped page tables map all of the 37250c2277SThomas Gleixner * kernel pages and possibly all of memory. 38250c2277SThomas Gleixner * 39250c2277SThomas Gleixner * %esi holds a physical pointer to real_mode_data. 40250c2277SThomas Gleixner * 41250c2277SThomas Gleixner * We come here either directly from a 64bit bootloader, or from 42250c2277SThomas Gleixner * arch/x86_64/boot/compressed/head.S. 43250c2277SThomas Gleixner * 44250c2277SThomas Gleixner * We only come here initially at boot nothing else comes here. 45250c2277SThomas Gleixner * 46250c2277SThomas Gleixner * Since we may be loaded at an address different from what we were 47250c2277SThomas Gleixner * compiled to run at we first fixup the physical addresses in our page 48250c2277SThomas Gleixner * tables and then reload them. 49250c2277SThomas Gleixner */ 50250c2277SThomas Gleixner 51250c2277SThomas Gleixner /* Compute the delta between the address I am compiled to run at and the 52250c2277SThomas Gleixner * address I am actually running at. 53250c2277SThomas Gleixner */ 54250c2277SThomas Gleixner leaq _text(%rip), %rbp 55250c2277SThomas Gleixner subq $_text - __START_KERNEL_map, %rbp 56250c2277SThomas Gleixner 57250c2277SThomas Gleixner /* Is the address not 2M aligned? */ 58250c2277SThomas Gleixner movq %rbp, %rax 59250c2277SThomas Gleixner andl $~LARGE_PAGE_MASK, %eax 60250c2277SThomas Gleixner testl %eax, %eax 61250c2277SThomas Gleixner jnz bad_address 62250c2277SThomas Gleixner 63250c2277SThomas Gleixner /* Is the address too large? */ 64250c2277SThomas Gleixner leaq _text(%rip), %rdx 65250c2277SThomas Gleixner movq $PGDIR_SIZE, %rax 66250c2277SThomas Gleixner cmpq %rax, %rdx 67250c2277SThomas Gleixner jae bad_address 68250c2277SThomas Gleixner 69250c2277SThomas Gleixner /* Fixup the physical addresses in the page table 70250c2277SThomas Gleixner */ 71250c2277SThomas Gleixner addq %rbp, init_level4_pgt + 0(%rip) 72250c2277SThomas Gleixner addq %rbp, init_level4_pgt + (258*8)(%rip) 73250c2277SThomas Gleixner addq %rbp, init_level4_pgt + (511*8)(%rip) 74250c2277SThomas Gleixner 75250c2277SThomas Gleixner addq %rbp, level3_ident_pgt + 0(%rip) 76250c2277SThomas Gleixner 77250c2277SThomas Gleixner addq %rbp, level3_kernel_pgt + (510*8)(%rip) 78250c2277SThomas Gleixner addq %rbp, level3_kernel_pgt + (511*8)(%rip) 79250c2277SThomas Gleixner 80250c2277SThomas Gleixner addq %rbp, level2_fixmap_pgt + (506*8)(%rip) 81250c2277SThomas Gleixner 82250c2277SThomas Gleixner /* Add an Identity mapping if I am above 1G */ 83250c2277SThomas Gleixner leaq _text(%rip), %rdi 84250c2277SThomas Gleixner andq $LARGE_PAGE_MASK, %rdi 85250c2277SThomas Gleixner 86250c2277SThomas Gleixner movq %rdi, %rax 87250c2277SThomas Gleixner shrq $PUD_SHIFT, %rax 88250c2277SThomas Gleixner andq $(PTRS_PER_PUD - 1), %rax 89250c2277SThomas Gleixner jz ident_complete 90250c2277SThomas Gleixner 91250c2277SThomas Gleixner leaq (level2_spare_pgt - __START_KERNEL_map + _KERNPG_TABLE)(%rbp), %rdx 92250c2277SThomas Gleixner leaq level3_ident_pgt(%rip), %rbx 93250c2277SThomas Gleixner movq %rdx, 0(%rbx, %rax, 8) 94250c2277SThomas Gleixner 95250c2277SThomas Gleixner movq %rdi, %rax 96250c2277SThomas Gleixner shrq $PMD_SHIFT, %rax 97250c2277SThomas Gleixner andq $(PTRS_PER_PMD - 1), %rax 98250c2277SThomas Gleixner leaq __PAGE_KERNEL_LARGE_EXEC(%rdi), %rdx 99250c2277SThomas Gleixner leaq level2_spare_pgt(%rip), %rbx 100250c2277SThomas Gleixner movq %rdx, 0(%rbx, %rax, 8) 101250c2277SThomas Gleixnerident_complete: 102250c2277SThomas Gleixner 103250c2277SThomas Gleixner /* Fixup the kernel text+data virtual addresses 104250c2277SThomas Gleixner */ 105250c2277SThomas Gleixner leaq level2_kernel_pgt(%rip), %rdi 106250c2277SThomas Gleixner leaq 4096(%rdi), %r8 107250c2277SThomas Gleixner /* See if it is a valid page table entry */ 108250c2277SThomas Gleixner1: testq $1, 0(%rdi) 109250c2277SThomas Gleixner jz 2f 110250c2277SThomas Gleixner addq %rbp, 0(%rdi) 111250c2277SThomas Gleixner /* Go to the next page */ 112250c2277SThomas Gleixner2: addq $8, %rdi 113250c2277SThomas Gleixner cmp %r8, %rdi 114250c2277SThomas Gleixner jne 1b 115250c2277SThomas Gleixner 116250c2277SThomas Gleixner /* Fixup phys_base */ 117250c2277SThomas Gleixner addq %rbp, phys_base(%rip) 118250c2277SThomas Gleixner 119250c2277SThomas Gleixner#ifdef CONFIG_SMP 120250c2277SThomas Gleixner addq %rbp, trampoline_level4_pgt + 0(%rip) 121250c2277SThomas Gleixner addq %rbp, trampoline_level4_pgt + (511*8)(%rip) 122250c2277SThomas Gleixner#endif 123250c2277SThomas Gleixner#ifdef CONFIG_ACPI_SLEEP 124250c2277SThomas Gleixner addq %rbp, wakeup_level4_pgt + 0(%rip) 125250c2277SThomas Gleixner addq %rbp, wakeup_level4_pgt + (511*8)(%rip) 126250c2277SThomas Gleixner#endif 127250c2277SThomas Gleixner 128250c2277SThomas Gleixner /* Due to ENTRY(), sometimes the empty space gets filled with 129250c2277SThomas Gleixner * zeros. Better take a jmp than relying on empty space being 130250c2277SThomas Gleixner * filled with 0x90 (nop) 131250c2277SThomas Gleixner */ 132250c2277SThomas Gleixner jmp secondary_startup_64 133250c2277SThomas GleixnerENTRY(secondary_startup_64) 134250c2277SThomas Gleixner /* 135250c2277SThomas Gleixner * At this point the CPU runs in 64bit mode CS.L = 1 CS.D = 1, 136250c2277SThomas Gleixner * and someone has loaded a mapped page table. 137250c2277SThomas Gleixner * 138250c2277SThomas Gleixner * %esi holds a physical pointer to real_mode_data. 139250c2277SThomas Gleixner * 140250c2277SThomas Gleixner * We come here either from startup_64 (using physical addresses) 141250c2277SThomas Gleixner * or from trampoline.S (using virtual addresses). 142250c2277SThomas Gleixner * 143250c2277SThomas Gleixner * Using virtual addresses from trampoline.S removes the need 144250c2277SThomas Gleixner * to have any identity mapped pages in the kernel page table 145250c2277SThomas Gleixner * after the boot processor executes this code. 146250c2277SThomas Gleixner */ 147250c2277SThomas Gleixner 148250c2277SThomas Gleixner /* Enable PAE mode and PGE */ 149250c2277SThomas Gleixner xorq %rax, %rax 150250c2277SThomas Gleixner btsq $5, %rax 151250c2277SThomas Gleixner btsq $7, %rax 152250c2277SThomas Gleixner movq %rax, %cr4 153250c2277SThomas Gleixner 154250c2277SThomas Gleixner /* Setup early boot stage 4 level pagetables. */ 155250c2277SThomas Gleixner movq $(init_level4_pgt - __START_KERNEL_map), %rax 156250c2277SThomas Gleixner addq phys_base(%rip), %rax 157250c2277SThomas Gleixner movq %rax, %cr3 158250c2277SThomas Gleixner 159250c2277SThomas Gleixner /* Ensure I am executing from virtual addresses */ 160250c2277SThomas Gleixner movq $1f, %rax 161250c2277SThomas Gleixner jmp *%rax 162250c2277SThomas Gleixner1: 163250c2277SThomas Gleixner 164250c2277SThomas Gleixner /* Check if nx is implemented */ 165250c2277SThomas Gleixner movl $0x80000001, %eax 166250c2277SThomas Gleixner cpuid 167250c2277SThomas Gleixner movl %edx,%edi 168250c2277SThomas Gleixner 169250c2277SThomas Gleixner /* Setup EFER (Extended Feature Enable Register) */ 170250c2277SThomas Gleixner movl $MSR_EFER, %ecx 171250c2277SThomas Gleixner rdmsr 172250c2277SThomas Gleixner btsl $_EFER_SCE, %eax /* Enable System Call */ 173250c2277SThomas Gleixner btl $20,%edi /* No Execute supported? */ 174250c2277SThomas Gleixner jnc 1f 175250c2277SThomas Gleixner btsl $_EFER_NX, %eax 176250c2277SThomas Gleixner1: wrmsr /* Make changes effective */ 177250c2277SThomas Gleixner 178250c2277SThomas Gleixner /* Setup cr0 */ 179250c2277SThomas Gleixner#define CR0_PM 1 /* protected mode */ 180250c2277SThomas Gleixner#define CR0_MP (1<<1) 181250c2277SThomas Gleixner#define CR0_ET (1<<4) 182250c2277SThomas Gleixner#define CR0_NE (1<<5) 183250c2277SThomas Gleixner#define CR0_WP (1<<16) 184250c2277SThomas Gleixner#define CR0_AM (1<<18) 185250c2277SThomas Gleixner#define CR0_PAGING (1<<31) 186250c2277SThomas Gleixner movl $CR0_PM|CR0_MP|CR0_ET|CR0_NE|CR0_WP|CR0_AM|CR0_PAGING,%eax 187250c2277SThomas Gleixner /* Make changes effective */ 188250c2277SThomas Gleixner movq %rax, %cr0 189250c2277SThomas Gleixner 190250c2277SThomas Gleixner /* Setup a boot time stack */ 191250c2277SThomas Gleixner movq init_rsp(%rip),%rsp 192250c2277SThomas Gleixner 193250c2277SThomas Gleixner /* zero EFLAGS after setting rsp */ 194250c2277SThomas Gleixner pushq $0 195250c2277SThomas Gleixner popfq 196250c2277SThomas Gleixner 197250c2277SThomas Gleixner /* 198250c2277SThomas Gleixner * We must switch to a new descriptor in kernel space for the GDT 199250c2277SThomas Gleixner * because soon the kernel won't have access anymore to the userspace 200250c2277SThomas Gleixner * addresses where we're currently running on. We have to do that here 201250c2277SThomas Gleixner * because in 32bit we couldn't load a 64bit linear address. 202250c2277SThomas Gleixner */ 203250c2277SThomas Gleixner lgdt cpu_gdt_descr(%rip) 204250c2277SThomas Gleixner 205250c2277SThomas Gleixner /* set up data segments. actually 0 would do too */ 206250c2277SThomas Gleixner movl $__KERNEL_DS,%eax 207250c2277SThomas Gleixner movl %eax,%ds 208250c2277SThomas Gleixner movl %eax,%ss 209250c2277SThomas Gleixner movl %eax,%es 210250c2277SThomas Gleixner 211250c2277SThomas Gleixner /* 212250c2277SThomas Gleixner * We don't really need to load %fs or %gs, but load them anyway 213250c2277SThomas Gleixner * to kill any stale realmode selectors. This allows execution 214250c2277SThomas Gleixner * under VT hardware. 215250c2277SThomas Gleixner */ 216250c2277SThomas Gleixner movl %eax,%fs 217250c2277SThomas Gleixner movl %eax,%gs 218250c2277SThomas Gleixner 219250c2277SThomas Gleixner /* 220250c2277SThomas Gleixner * Setup up a dummy PDA. this is just for some early bootup code 221250c2277SThomas Gleixner * that does in_interrupt() 222250c2277SThomas Gleixner */ 223250c2277SThomas Gleixner movl $MSR_GS_BASE,%ecx 224250c2277SThomas Gleixner movq $empty_zero_page,%rax 225250c2277SThomas Gleixner movq %rax,%rdx 226250c2277SThomas Gleixner shrq $32,%rdx 227250c2277SThomas Gleixner wrmsr 228250c2277SThomas Gleixner 229250c2277SThomas Gleixner /* esi is pointer to real mode structure with interesting info. 230250c2277SThomas Gleixner pass it to C */ 231250c2277SThomas Gleixner movl %esi, %edi 232250c2277SThomas Gleixner 233250c2277SThomas Gleixner /* Finally jump to run C code and to be on real kernel address 234250c2277SThomas Gleixner * Since we are running on identity-mapped space we have to jump 235250c2277SThomas Gleixner * to the full 64bit address, this is only possible as indirect 236250c2277SThomas Gleixner * jump. In addition we need to ensure %cs is set so we make this 237250c2277SThomas Gleixner * a far return. 238250c2277SThomas Gleixner */ 239250c2277SThomas Gleixner movq initial_code(%rip),%rax 240250c2277SThomas Gleixner pushq $0 # fake return address to stop unwinder 241250c2277SThomas Gleixner pushq $__KERNEL_CS # set correct cs 242250c2277SThomas Gleixner pushq %rax # target address in negative space 243250c2277SThomas Gleixner lretq 244250c2277SThomas Gleixner 245250c2277SThomas Gleixner /* SMP bootup changes these two */ 246250c2277SThomas Gleixner#ifndef CONFIG_HOTPLUG_CPU 247250c2277SThomas Gleixner .pushsection .init.data 248250c2277SThomas Gleixner#endif 249250c2277SThomas Gleixner .align 8 250250c2277SThomas Gleixner .globl initial_code 251250c2277SThomas Gleixnerinitial_code: 252250c2277SThomas Gleixner .quad x86_64_start_kernel 253250c2277SThomas Gleixner#ifndef CONFIG_HOTPLUG_CPU 254250c2277SThomas Gleixner .popsection 255250c2277SThomas Gleixner#endif 256250c2277SThomas Gleixner .globl init_rsp 257250c2277SThomas Gleixnerinit_rsp: 258250c2277SThomas Gleixner .quad init_thread_union+THREAD_SIZE-8 259250c2277SThomas Gleixner 260250c2277SThomas Gleixnerbad_address: 261250c2277SThomas Gleixner jmp bad_address 262250c2277SThomas Gleixner 263250c2277SThomas GleixnerENTRY(early_idt_handler) 264250c2277SThomas Gleixner cmpl $2,early_recursion_flag(%rip) 265250c2277SThomas Gleixner jz 1f 266250c2277SThomas Gleixner incl early_recursion_flag(%rip) 267250c2277SThomas Gleixner xorl %eax,%eax 268250c2277SThomas Gleixner movq 8(%rsp),%rsi # get rip 269250c2277SThomas Gleixner movq (%rsp),%rdx 270250c2277SThomas Gleixner movq %cr2,%rcx 271250c2277SThomas Gleixner leaq early_idt_msg(%rip),%rdi 272250c2277SThomas Gleixner call early_printk 273250c2277SThomas Gleixner cmpl $2,early_recursion_flag(%rip) 274250c2277SThomas Gleixner jz 1f 275250c2277SThomas Gleixner call dump_stack 276250c2277SThomas Gleixner#ifdef CONFIG_KALLSYMS 277250c2277SThomas Gleixner leaq early_idt_ripmsg(%rip),%rdi 278250c2277SThomas Gleixner movq 8(%rsp),%rsi # get rip again 279250c2277SThomas Gleixner call __print_symbol 280250c2277SThomas Gleixner#endif 281250c2277SThomas Gleixner1: hlt 282250c2277SThomas Gleixner jmp 1b 283250c2277SThomas Gleixnerearly_recursion_flag: 284250c2277SThomas Gleixner .long 0 285250c2277SThomas Gleixner 286250c2277SThomas Gleixnerearly_idt_msg: 287250c2277SThomas Gleixner .asciz "PANIC: early exception rip %lx error %lx cr2 %lx\n" 288250c2277SThomas Gleixnerearly_idt_ripmsg: 289250c2277SThomas Gleixner .asciz "RIP %s\n" 290250c2277SThomas Gleixner 291250c2277SThomas Gleixner.balign PAGE_SIZE 292250c2277SThomas Gleixner 293250c2277SThomas Gleixner#define NEXT_PAGE(name) \ 294250c2277SThomas Gleixner .balign PAGE_SIZE; \ 295250c2277SThomas GleixnerENTRY(name) 296250c2277SThomas Gleixner 297250c2277SThomas Gleixner/* Automate the creation of 1 to 1 mapping pmd entries */ 298250c2277SThomas Gleixner#define PMDS(START, PERM, COUNT) \ 299250c2277SThomas Gleixner i = 0 ; \ 300250c2277SThomas Gleixner .rept (COUNT) ; \ 301250c2277SThomas Gleixner .quad (START) + (i << 21) + (PERM) ; \ 302250c2277SThomas Gleixner i = i + 1 ; \ 303250c2277SThomas Gleixner .endr 304250c2277SThomas Gleixner 305250c2277SThomas Gleixner /* 306250c2277SThomas Gleixner * This default setting generates an ident mapping at address 0x100000 307250c2277SThomas Gleixner * and a mapping for the kernel that precisely maps virtual address 308250c2277SThomas Gleixner * 0xffffffff80000000 to physical address 0x000000. (always using 309250c2277SThomas Gleixner * 2Mbyte large pages provided by PAE mode) 310250c2277SThomas Gleixner */ 311250c2277SThomas GleixnerNEXT_PAGE(init_level4_pgt) 312250c2277SThomas Gleixner .quad level3_ident_pgt - __START_KERNEL_map + _KERNPG_TABLE 313250c2277SThomas Gleixner .fill 257,8,0 314250c2277SThomas Gleixner .quad level3_ident_pgt - __START_KERNEL_map + _KERNPG_TABLE 315250c2277SThomas Gleixner .fill 252,8,0 316250c2277SThomas Gleixner /* (2^48-(2*1024*1024*1024))/(2^39) = 511 */ 317250c2277SThomas Gleixner .quad level3_kernel_pgt - __START_KERNEL_map + _PAGE_TABLE 318250c2277SThomas Gleixner 319250c2277SThomas GleixnerNEXT_PAGE(level3_ident_pgt) 320250c2277SThomas Gleixner .quad level2_ident_pgt - __START_KERNEL_map + _KERNPG_TABLE 321250c2277SThomas Gleixner .fill 511,8,0 322250c2277SThomas Gleixner 323250c2277SThomas GleixnerNEXT_PAGE(level3_kernel_pgt) 324250c2277SThomas Gleixner .fill 510,8,0 325250c2277SThomas Gleixner /* (2^48-(2*1024*1024*1024)-((2^39)*511))/(2^30) = 510 */ 326250c2277SThomas Gleixner .quad level2_kernel_pgt - __START_KERNEL_map + _KERNPG_TABLE 327250c2277SThomas Gleixner .quad level2_fixmap_pgt - __START_KERNEL_map + _PAGE_TABLE 328250c2277SThomas Gleixner 329250c2277SThomas GleixnerNEXT_PAGE(level2_fixmap_pgt) 330250c2277SThomas Gleixner .fill 506,8,0 331250c2277SThomas Gleixner .quad level1_fixmap_pgt - __START_KERNEL_map + _PAGE_TABLE 332250c2277SThomas Gleixner /* 8MB reserved for vsyscalls + a 2MB hole = 4 + 1 entries */ 333250c2277SThomas Gleixner .fill 5,8,0 334250c2277SThomas Gleixner 335250c2277SThomas GleixnerNEXT_PAGE(level1_fixmap_pgt) 336250c2277SThomas Gleixner .fill 512,8,0 337250c2277SThomas Gleixner 338250c2277SThomas GleixnerNEXT_PAGE(level2_ident_pgt) 339250c2277SThomas Gleixner /* Since I easily can, map the first 1G. 340250c2277SThomas Gleixner * Don't set NX because code runs from these pages. 341250c2277SThomas Gleixner */ 342250c2277SThomas Gleixner PMDS(0x0000000000000000, __PAGE_KERNEL_LARGE_EXEC, PTRS_PER_PMD) 343250c2277SThomas Gleixner 344250c2277SThomas GleixnerNEXT_PAGE(level2_kernel_pgt) 345250c2277SThomas Gleixner /* 40MB kernel mapping. The kernel code cannot be bigger than that. 346250c2277SThomas Gleixner When you change this change KERNEL_TEXT_SIZE in page.h too. */ 347250c2277SThomas Gleixner /* (2^48-(2*1024*1024*1024)-((2^39)*511)-((2^30)*510)) = 0 */ 348250c2277SThomas Gleixner PMDS(0x0000000000000000, __PAGE_KERNEL_LARGE_EXEC|_PAGE_GLOBAL, KERNEL_TEXT_SIZE/PMD_SIZE) 349250c2277SThomas Gleixner /* Module mapping starts here */ 350250c2277SThomas Gleixner .fill (PTRS_PER_PMD - (KERNEL_TEXT_SIZE/PMD_SIZE)),8,0 351250c2277SThomas Gleixner 352250c2277SThomas GleixnerNEXT_PAGE(level2_spare_pgt) 353250c2277SThomas Gleixner .fill 512,8,0 354250c2277SThomas Gleixner 355250c2277SThomas Gleixner#undef PMDS 356250c2277SThomas Gleixner#undef NEXT_PAGE 357250c2277SThomas Gleixner 358250c2277SThomas Gleixner .data 359250c2277SThomas Gleixner .align 16 360250c2277SThomas Gleixner .globl cpu_gdt_descr 361250c2277SThomas Gleixnercpu_gdt_descr: 362250c2277SThomas Gleixner .word gdt_end-cpu_gdt_table-1 363250c2277SThomas Gleixnergdt: 364250c2277SThomas Gleixner .quad cpu_gdt_table 365250c2277SThomas Gleixner#ifdef CONFIG_SMP 366250c2277SThomas Gleixner .rept NR_CPUS-1 367250c2277SThomas Gleixner .word 0 368250c2277SThomas Gleixner .quad 0 369250c2277SThomas Gleixner .endr 370250c2277SThomas Gleixner#endif 371250c2277SThomas Gleixner 372250c2277SThomas GleixnerENTRY(phys_base) 373250c2277SThomas Gleixner /* This must match the first entry in level2_kernel_pgt */ 374250c2277SThomas Gleixner .quad 0x0000000000000000 375250c2277SThomas Gleixner 376250c2277SThomas Gleixner/* We need valid kernel segments for data and code in long mode too 377250c2277SThomas Gleixner * IRET will check the segment types kkeil 2000/10/28 378250c2277SThomas Gleixner * Also sysret mandates a special GDT layout 379250c2277SThomas Gleixner */ 380250c2277SThomas Gleixner 381250c2277SThomas Gleixner .section .data.page_aligned, "aw" 382250c2277SThomas Gleixner .align PAGE_SIZE 383250c2277SThomas Gleixner 384250c2277SThomas Gleixner/* The TLS descriptors are currently at a different place compared to i386. 385250c2277SThomas Gleixner Hopefully nobody expects them at a fixed place (Wine?) */ 386250c2277SThomas Gleixner 387250c2277SThomas GleixnerENTRY(cpu_gdt_table) 388250c2277SThomas Gleixner .quad 0x0000000000000000 /* NULL descriptor */ 389250c2277SThomas Gleixner .quad 0x00cf9b000000ffff /* __KERNEL32_CS */ 390250c2277SThomas Gleixner .quad 0x00af9b000000ffff /* __KERNEL_CS */ 391250c2277SThomas Gleixner .quad 0x00cf93000000ffff /* __KERNEL_DS */ 392250c2277SThomas Gleixner .quad 0x00cffb000000ffff /* __USER32_CS */ 393250c2277SThomas Gleixner .quad 0x00cff3000000ffff /* __USER_DS, __USER32_DS */ 394250c2277SThomas Gleixner .quad 0x00affb000000ffff /* __USER_CS */ 395250c2277SThomas Gleixner .quad 0x0 /* unused */ 396250c2277SThomas Gleixner .quad 0,0 /* TSS */ 397250c2277SThomas Gleixner .quad 0,0 /* LDT */ 398250c2277SThomas Gleixner .quad 0,0,0 /* three TLS descriptors */ 399250c2277SThomas Gleixner .quad 0x0000f40000000000 /* node/CPU stored in limit */ 400250c2277SThomas Gleixnergdt_end: 401250c2277SThomas Gleixner /* asm/segment.h:GDT_ENTRIES must match this */ 402250c2277SThomas Gleixner /* This should be a multiple of the cache line size */ 403250c2277SThomas Gleixner /* GDTs of other CPUs are now dynamically allocated */ 404250c2277SThomas Gleixner 405250c2277SThomas Gleixner /* zero the remaining page */ 406250c2277SThomas Gleixner .fill PAGE_SIZE / 8 - GDT_ENTRIES,8,0 407250c2277SThomas Gleixner 408250c2277SThomas Gleixner .section .bss, "aw", @nobits 409250c2277SThomas Gleixner .align L1_CACHE_BYTES 410250c2277SThomas GleixnerENTRY(idt_table) 411250c2277SThomas Gleixner .skip 256 * 16 412250c2277SThomas Gleixner 413250c2277SThomas Gleixner .section .bss.page_aligned, "aw", @nobits 414250c2277SThomas Gleixner .align PAGE_SIZE 415250c2277SThomas GleixnerENTRY(empty_zero_page) 416250c2277SThomas Gleixner .skip PAGE_SIZE 417