1 /* SPDX-License-Identifier: GPL-2.0 */ 2 /* 3 * pgtable.h: SpitFire page table operations. 4 * 5 * Copyright 1996,1997 David S. Miller (davem@caip.rutgers.edu) 6 * Copyright 1997,1998 Jakub Jelinek (jj@sunsite.mff.cuni.cz) 7 */ 8 9 #ifndef _SPARC64_PGTABLE_H 10 #define _SPARC64_PGTABLE_H 11 12 /* This file contains the functions and defines necessary to modify and use 13 * the SpitFire page tables. 14 */ 15 16 #include <asm-generic/5level-fixup.h> 17 #include <linux/compiler.h> 18 #include <linux/const.h> 19 #include <asm/types.h> 20 #include <asm/spitfire.h> 21 #include <asm/asi.h> 22 #include <asm/adi.h> 23 #include <asm/page.h> 24 #include <asm/processor.h> 25 26 /* The kernel image occupies 0x4000000 to 0x6000000 (4MB --> 96MB). 27 * The page copy blockops can use 0x6000000 to 0x8000000. 28 * The 8K TSB is mapped in the 0x8000000 to 0x8400000 range. 29 * The 4M TSB is mapped in the 0x8400000 to 0x8800000 range. 30 * The PROM resides in an area spanning 0xf0000000 to 0x100000000. 31 * The vmalloc area spans 0x100000000 to 0x200000000. 32 * Since modules need to be in the lowest 32-bits of the address space, 33 * we place them right before the OBP area from 0x10000000 to 0xf0000000. 34 * There is a single static kernel PMD which maps from 0x0 to address 35 * 0x400000000. 36 */ 37 #define TLBTEMP_BASE _AC(0x0000000006000000,UL) 38 #define TSBMAP_8K_BASE _AC(0x0000000008000000,UL) 39 #define TSBMAP_4M_BASE _AC(0x0000000008400000,UL) 40 #define MODULES_VADDR _AC(0x0000000010000000,UL) 41 #define MODULES_LEN _AC(0x00000000e0000000,UL) 42 #define MODULES_END _AC(0x00000000f0000000,UL) 43 #define LOW_OBP_ADDRESS _AC(0x00000000f0000000,UL) 44 #define HI_OBP_ADDRESS _AC(0x0000000100000000,UL) 45 #define VMALLOC_START _AC(0x0000000100000000,UL) 46 #define VMEMMAP_BASE VMALLOC_END 47 48 /* PMD_SHIFT determines the size of the area a second-level page 49 * table can map 50 */ 51 #define PMD_SHIFT (PAGE_SHIFT + (PAGE_SHIFT-3)) 52 #define PMD_SIZE (_AC(1,UL) << PMD_SHIFT) 53 #define PMD_MASK (~(PMD_SIZE-1)) 54 #define PMD_BITS (PAGE_SHIFT - 3) 55 56 /* PUD_SHIFT determines the size of the area a third-level page 57 * table can map 58 */ 59 #define PUD_SHIFT (PMD_SHIFT + PMD_BITS) 60 #define PUD_SIZE (_AC(1,UL) << PUD_SHIFT) 61 #define PUD_MASK (~(PUD_SIZE-1)) 62 #define PUD_BITS (PAGE_SHIFT - 3) 63 64 /* PGDIR_SHIFT determines what a fourth-level page table entry can map */ 65 #define PGDIR_SHIFT (PUD_SHIFT + PUD_BITS) 66 #define PGDIR_SIZE (_AC(1,UL) << PGDIR_SHIFT) 67 #define PGDIR_MASK (~(PGDIR_SIZE-1)) 68 #define PGDIR_BITS (PAGE_SHIFT - 3) 69 70 #if (MAX_PHYS_ADDRESS_BITS > PGDIR_SHIFT + PGDIR_BITS) 71 #error MAX_PHYS_ADDRESS_BITS exceeds what kernel page tables can support 72 #endif 73 74 #if (PGDIR_SHIFT + PGDIR_BITS) != 53 75 #error Page table parameters do not cover virtual address space properly. 76 #endif 77 78 #if (PMD_SHIFT != HPAGE_SHIFT) 79 #error PMD_SHIFT must equal HPAGE_SHIFT for transparent huge pages. 80 #endif 81 82 #ifndef __ASSEMBLY__ 83 84 extern unsigned long VMALLOC_END; 85 86 #define vmemmap ((struct page *)VMEMMAP_BASE) 87 88 #include <linux/sched.h> 89 90 bool kern_addr_valid(unsigned long addr); 91 92 /* Entries per page directory level. */ 93 #define PTRS_PER_PTE (1UL << (PAGE_SHIFT-3)) 94 #define PTRS_PER_PMD (1UL << PMD_BITS) 95 #define PTRS_PER_PUD (1UL << PUD_BITS) 96 #define PTRS_PER_PGD (1UL << PGDIR_BITS) 97 98 /* Kernel has a separate 44bit address space. */ 99 #define FIRST_USER_ADDRESS 0UL 100 101 #define pmd_ERROR(e) \ 102 pr_err("%s:%d: bad pmd %p(%016lx) seen at (%pS)\n", \ 103 __FILE__, __LINE__, &(e), pmd_val(e), __builtin_return_address(0)) 104 #define pud_ERROR(e) \ 105 pr_err("%s:%d: bad pud %p(%016lx) seen at (%pS)\n", \ 106 __FILE__, __LINE__, &(e), pud_val(e), __builtin_return_address(0)) 107 #define pgd_ERROR(e) \ 108 pr_err("%s:%d: bad pgd %p(%016lx) seen at (%pS)\n", \ 109 __FILE__, __LINE__, &(e), pgd_val(e), __builtin_return_address(0)) 110 111 #endif /* !(__ASSEMBLY__) */ 112 113 /* PTE bits which are the same in SUN4U and SUN4V format. */ 114 #define _PAGE_VALID _AC(0x8000000000000000,UL) /* Valid TTE */ 115 #define _PAGE_R _AC(0x8000000000000000,UL) /* Keep ref bit uptodate*/ 116 #define _PAGE_SPECIAL _AC(0x0200000000000000,UL) /* Special page */ 117 #define _PAGE_PMD_HUGE _AC(0x0100000000000000,UL) /* Huge page */ 118 #define _PAGE_PUD_HUGE _PAGE_PMD_HUGE 119 120 /* Advertise support for _PAGE_SPECIAL */ 121 #define __HAVE_ARCH_PTE_SPECIAL 122 123 /* SUN4U pte bits... */ 124 #define _PAGE_SZ4MB_4U _AC(0x6000000000000000,UL) /* 4MB Page */ 125 #define _PAGE_SZ512K_4U _AC(0x4000000000000000,UL) /* 512K Page */ 126 #define _PAGE_SZ64K_4U _AC(0x2000000000000000,UL) /* 64K Page */ 127 #define _PAGE_SZ8K_4U _AC(0x0000000000000000,UL) /* 8K Page */ 128 #define _PAGE_NFO_4U _AC(0x1000000000000000,UL) /* No Fault Only */ 129 #define _PAGE_IE_4U _AC(0x0800000000000000,UL) /* Invert Endianness */ 130 #define _PAGE_SOFT2_4U _AC(0x07FC000000000000,UL) /* Software bits, set 2 */ 131 #define _PAGE_SPECIAL_4U _AC(0x0200000000000000,UL) /* Special page */ 132 #define _PAGE_PMD_HUGE_4U _AC(0x0100000000000000,UL) /* Huge page */ 133 #define _PAGE_RES1_4U _AC(0x0002000000000000,UL) /* Reserved */ 134 #define _PAGE_SZ32MB_4U _AC(0x0001000000000000,UL) /* (Panther) 32MB page */ 135 #define _PAGE_SZ256MB_4U _AC(0x2001000000000000,UL) /* (Panther) 256MB page */ 136 #define _PAGE_SZALL_4U _AC(0x6001000000000000,UL) /* All pgsz bits */ 137 #define _PAGE_SN_4U _AC(0x0000800000000000,UL) /* (Cheetah) Snoop */ 138 #define _PAGE_RES2_4U _AC(0x0000780000000000,UL) /* Reserved */ 139 #define _PAGE_PADDR_4U _AC(0x000007FFFFFFE000,UL) /* (Cheetah) pa[42:13] */ 140 #define _PAGE_SOFT_4U _AC(0x0000000000001F80,UL) /* Software bits: */ 141 #define _PAGE_EXEC_4U _AC(0x0000000000001000,UL) /* Executable SW bit */ 142 #define _PAGE_MODIFIED_4U _AC(0x0000000000000800,UL) /* Modified (dirty) */ 143 #define _PAGE_ACCESSED_4U _AC(0x0000000000000400,UL) /* Accessed (ref'd) */ 144 #define _PAGE_READ_4U _AC(0x0000000000000200,UL) /* Readable SW Bit */ 145 #define _PAGE_WRITE_4U _AC(0x0000000000000100,UL) /* Writable SW Bit */ 146 #define _PAGE_PRESENT_4U _AC(0x0000000000000080,UL) /* Present */ 147 #define _PAGE_L_4U _AC(0x0000000000000040,UL) /* Locked TTE */ 148 #define _PAGE_CP_4U _AC(0x0000000000000020,UL) /* Cacheable in P-Cache */ 149 #define _PAGE_CV_4U _AC(0x0000000000000010,UL) /* Cacheable in V-Cache */ 150 #define _PAGE_E_4U _AC(0x0000000000000008,UL) /* side-Effect */ 151 #define _PAGE_P_4U _AC(0x0000000000000004,UL) /* Privileged Page */ 152 #define _PAGE_W_4U _AC(0x0000000000000002,UL) /* Writable */ 153 154 /* SUN4V pte bits... */ 155 #define _PAGE_NFO_4V _AC(0x4000000000000000,UL) /* No Fault Only */ 156 #define _PAGE_SOFT2_4V _AC(0x3F00000000000000,UL) /* Software bits, set 2 */ 157 #define _PAGE_MODIFIED_4V _AC(0x2000000000000000,UL) /* Modified (dirty) */ 158 #define _PAGE_ACCESSED_4V _AC(0x1000000000000000,UL) /* Accessed (ref'd) */ 159 #define _PAGE_READ_4V _AC(0x0800000000000000,UL) /* Readable SW Bit */ 160 #define _PAGE_WRITE_4V _AC(0x0400000000000000,UL) /* Writable SW Bit */ 161 #define _PAGE_SPECIAL_4V _AC(0x0200000000000000,UL) /* Special page */ 162 #define _PAGE_PMD_HUGE_4V _AC(0x0100000000000000,UL) /* Huge page */ 163 #define _PAGE_PADDR_4V _AC(0x00FFFFFFFFFFE000,UL) /* paddr[55:13] */ 164 #define _PAGE_IE_4V _AC(0x0000000000001000,UL) /* Invert Endianness */ 165 #define _PAGE_E_4V _AC(0x0000000000000800,UL) /* side-Effect */ 166 #define _PAGE_CP_4V _AC(0x0000000000000400,UL) /* Cacheable in P-Cache */ 167 #define _PAGE_CV_4V _AC(0x0000000000000200,UL) /* Cacheable in V-Cache */ 168 /* Bit 9 is used to enable MCD corruption detection instead on M7 */ 169 #define _PAGE_MCD_4V _AC(0x0000000000000200,UL) /* Memory Corruption */ 170 #define _PAGE_P_4V _AC(0x0000000000000100,UL) /* Privileged Page */ 171 #define _PAGE_EXEC_4V _AC(0x0000000000000080,UL) /* Executable Page */ 172 #define _PAGE_W_4V _AC(0x0000000000000040,UL) /* Writable */ 173 #define _PAGE_SOFT_4V _AC(0x0000000000000030,UL) /* Software bits */ 174 #define _PAGE_PRESENT_4V _AC(0x0000000000000010,UL) /* Present */ 175 #define _PAGE_RESV_4V _AC(0x0000000000000008,UL) /* Reserved */ 176 #define _PAGE_SZ16GB_4V _AC(0x0000000000000007,UL) /* 16GB Page */ 177 #define _PAGE_SZ2GB_4V _AC(0x0000000000000006,UL) /* 2GB Page */ 178 #define _PAGE_SZ256MB_4V _AC(0x0000000000000005,UL) /* 256MB Page */ 179 #define _PAGE_SZ32MB_4V _AC(0x0000000000000004,UL) /* 32MB Page */ 180 #define _PAGE_SZ4MB_4V _AC(0x0000000000000003,UL) /* 4MB Page */ 181 #define _PAGE_SZ512K_4V _AC(0x0000000000000002,UL) /* 512K Page */ 182 #define _PAGE_SZ64K_4V _AC(0x0000000000000001,UL) /* 64K Page */ 183 #define _PAGE_SZ8K_4V _AC(0x0000000000000000,UL) /* 8K Page */ 184 #define _PAGE_SZALL_4V _AC(0x0000000000000007,UL) /* All pgsz bits */ 185 186 #define _PAGE_SZBITS_4U _PAGE_SZ8K_4U 187 #define _PAGE_SZBITS_4V _PAGE_SZ8K_4V 188 189 #if REAL_HPAGE_SHIFT != 22 190 #error REAL_HPAGE_SHIFT and _PAGE_SZHUGE_foo must match up 191 #endif 192 193 #define _PAGE_SZHUGE_4U _PAGE_SZ4MB_4U 194 #define _PAGE_SZHUGE_4V _PAGE_SZ4MB_4V 195 196 /* These are actually filled in at boot time by sun4{u,v}_pgprot_init() */ 197 #define __P000 __pgprot(0) 198 #define __P001 __pgprot(0) 199 #define __P010 __pgprot(0) 200 #define __P011 __pgprot(0) 201 #define __P100 __pgprot(0) 202 #define __P101 __pgprot(0) 203 #define __P110 __pgprot(0) 204 #define __P111 __pgprot(0) 205 206 #define __S000 __pgprot(0) 207 #define __S001 __pgprot(0) 208 #define __S010 __pgprot(0) 209 #define __S011 __pgprot(0) 210 #define __S100 __pgprot(0) 211 #define __S101 __pgprot(0) 212 #define __S110 __pgprot(0) 213 #define __S111 __pgprot(0) 214 215 #ifndef __ASSEMBLY__ 216 217 pte_t mk_pte_io(unsigned long, pgprot_t, int, unsigned long); 218 219 unsigned long pte_sz_bits(unsigned long size); 220 221 extern pgprot_t PAGE_KERNEL; 222 extern pgprot_t PAGE_KERNEL_LOCKED; 223 extern pgprot_t PAGE_COPY; 224 extern pgprot_t PAGE_SHARED; 225 226 /* XXX This ugliness is for the atyfb driver's sparc mmap() support. XXX */ 227 extern unsigned long _PAGE_IE; 228 extern unsigned long _PAGE_E; 229 extern unsigned long _PAGE_CACHE; 230 231 extern unsigned long pg_iobits; 232 extern unsigned long _PAGE_ALL_SZ_BITS; 233 234 extern struct page *mem_map_zero; 235 #define ZERO_PAGE(vaddr) (mem_map_zero) 236 237 /* This macro must be updated when the size of struct page grows above 80 238 * or reduces below 64. 239 * The idea that compiler optimizes out switch() statement, and only 240 * leaves clrx instructions 241 */ 242 #define mm_zero_struct_page(pp) do { \ 243 unsigned long *_pp = (void *)(pp); \ 244 \ 245 /* Check that struct page is either 64, 72, or 80 bytes */ \ 246 BUILD_BUG_ON(sizeof(struct page) & 7); \ 247 BUILD_BUG_ON(sizeof(struct page) < 64); \ 248 BUILD_BUG_ON(sizeof(struct page) > 80); \ 249 \ 250 switch (sizeof(struct page)) { \ 251 case 80: \ 252 _pp[9] = 0; /* fallthrough */ \ 253 case 72: \ 254 _pp[8] = 0; /* fallthrough */ \ 255 default: \ 256 _pp[7] = 0; \ 257 _pp[6] = 0; \ 258 _pp[5] = 0; \ 259 _pp[4] = 0; \ 260 _pp[3] = 0; \ 261 _pp[2] = 0; \ 262 _pp[1] = 0; \ 263 _pp[0] = 0; \ 264 } \ 265 } while (0) 266 267 /* PFNs are real physical page numbers. However, mem_map only begins to record 268 * per-page information starting at pfn_base. This is to handle systems where 269 * the first physical page in the machine is at some huge physical address, 270 * such as 4GB. This is common on a partitioned E10000, for example. 271 */ 272 static inline pte_t pfn_pte(unsigned long pfn, pgprot_t prot) 273 { 274 unsigned long paddr = pfn << PAGE_SHIFT; 275 276 BUILD_BUG_ON(_PAGE_SZBITS_4U != 0UL || _PAGE_SZBITS_4V != 0UL); 277 return __pte(paddr | pgprot_val(prot)); 278 } 279 #define mk_pte(page, pgprot) pfn_pte(page_to_pfn(page), (pgprot)) 280 281 #ifdef CONFIG_TRANSPARENT_HUGEPAGE 282 static inline pmd_t pfn_pmd(unsigned long page_nr, pgprot_t pgprot) 283 { 284 pte_t pte = pfn_pte(page_nr, pgprot); 285 286 return __pmd(pte_val(pte)); 287 } 288 #define mk_pmd(page, pgprot) pfn_pmd(page_to_pfn(page), (pgprot)) 289 #endif 290 291 /* This one can be done with two shifts. */ 292 static inline unsigned long pte_pfn(pte_t pte) 293 { 294 unsigned long ret; 295 296 __asm__ __volatile__( 297 "\n661: sllx %1, %2, %0\n" 298 " srlx %0, %3, %0\n" 299 " .section .sun4v_2insn_patch, \"ax\"\n" 300 " .word 661b\n" 301 " sllx %1, %4, %0\n" 302 " srlx %0, %5, %0\n" 303 " .previous\n" 304 : "=r" (ret) 305 : "r" (pte_val(pte)), 306 "i" (21), "i" (21 + PAGE_SHIFT), 307 "i" (8), "i" (8 + PAGE_SHIFT)); 308 309 return ret; 310 } 311 #define pte_page(x) pfn_to_page(pte_pfn(x)) 312 313 static inline pte_t pte_modify(pte_t pte, pgprot_t prot) 314 { 315 unsigned long mask, tmp; 316 317 /* SUN4U: 0x630107ffffffec38 (negated == 0x9cfef800000013c7) 318 * SUN4V: 0x33ffffffffffee07 (negated == 0xcc000000000011f8) 319 * 320 * Even if we use negation tricks the result is still a 6 321 * instruction sequence, so don't try to play fancy and just 322 * do the most straightforward implementation. 323 * 324 * Note: We encode this into 3 sun4v 2-insn patch sequences. 325 */ 326 327 BUILD_BUG_ON(_PAGE_SZBITS_4U != 0UL || _PAGE_SZBITS_4V != 0UL); 328 __asm__ __volatile__( 329 "\n661: sethi %%uhi(%2), %1\n" 330 " sethi %%hi(%2), %0\n" 331 "\n662: or %1, %%ulo(%2), %1\n" 332 " or %0, %%lo(%2), %0\n" 333 "\n663: sllx %1, 32, %1\n" 334 " or %0, %1, %0\n" 335 " .section .sun4v_2insn_patch, \"ax\"\n" 336 " .word 661b\n" 337 " sethi %%uhi(%3), %1\n" 338 " sethi %%hi(%3), %0\n" 339 " .word 662b\n" 340 " or %1, %%ulo(%3), %1\n" 341 " or %0, %%lo(%3), %0\n" 342 " .word 663b\n" 343 " sllx %1, 32, %1\n" 344 " or %0, %1, %0\n" 345 " .previous\n" 346 " .section .sun_m7_2insn_patch, \"ax\"\n" 347 " .word 661b\n" 348 " sethi %%uhi(%4), %1\n" 349 " sethi %%hi(%4), %0\n" 350 " .word 662b\n" 351 " or %1, %%ulo(%4), %1\n" 352 " or %0, %%lo(%4), %0\n" 353 " .word 663b\n" 354 " sllx %1, 32, %1\n" 355 " or %0, %1, %0\n" 356 " .previous\n" 357 : "=r" (mask), "=r" (tmp) 358 : "i" (_PAGE_PADDR_4U | _PAGE_MODIFIED_4U | _PAGE_ACCESSED_4U | 359 _PAGE_CP_4U | _PAGE_CV_4U | _PAGE_E_4U | 360 _PAGE_SPECIAL | _PAGE_PMD_HUGE | _PAGE_SZALL_4U), 361 "i" (_PAGE_PADDR_4V | _PAGE_MODIFIED_4V | _PAGE_ACCESSED_4V | 362 _PAGE_CP_4V | _PAGE_CV_4V | _PAGE_E_4V | 363 _PAGE_SPECIAL | _PAGE_PMD_HUGE | _PAGE_SZALL_4V), 364 "i" (_PAGE_PADDR_4V | _PAGE_MODIFIED_4V | _PAGE_ACCESSED_4V | 365 _PAGE_CP_4V | _PAGE_E_4V | 366 _PAGE_SPECIAL | _PAGE_PMD_HUGE | _PAGE_SZALL_4V)); 367 368 return __pte((pte_val(pte) & mask) | (pgprot_val(prot) & ~mask)); 369 } 370 371 #ifdef CONFIG_TRANSPARENT_HUGEPAGE 372 static inline pmd_t pmd_modify(pmd_t pmd, pgprot_t newprot) 373 { 374 pte_t pte = __pte(pmd_val(pmd)); 375 376 pte = pte_modify(pte, newprot); 377 378 return __pmd(pte_val(pte)); 379 } 380 #endif 381 382 static inline pgprot_t pgprot_noncached(pgprot_t prot) 383 { 384 unsigned long val = pgprot_val(prot); 385 386 __asm__ __volatile__( 387 "\n661: andn %0, %2, %0\n" 388 " or %0, %3, %0\n" 389 " .section .sun4v_2insn_patch, \"ax\"\n" 390 " .word 661b\n" 391 " andn %0, %4, %0\n" 392 " or %0, %5, %0\n" 393 " .previous\n" 394 " .section .sun_m7_2insn_patch, \"ax\"\n" 395 " .word 661b\n" 396 " andn %0, %6, %0\n" 397 " or %0, %5, %0\n" 398 " .previous\n" 399 : "=r" (val) 400 : "0" (val), "i" (_PAGE_CP_4U | _PAGE_CV_4U), "i" (_PAGE_E_4U), 401 "i" (_PAGE_CP_4V | _PAGE_CV_4V), "i" (_PAGE_E_4V), 402 "i" (_PAGE_CP_4V)); 403 404 return __pgprot(val); 405 } 406 /* Various pieces of code check for platform support by ifdef testing 407 * on "pgprot_noncached". That's broken and should be fixed, but for 408 * now... 409 */ 410 #define pgprot_noncached pgprot_noncached 411 412 #if defined(CONFIG_HUGETLB_PAGE) || defined(CONFIG_TRANSPARENT_HUGEPAGE) 413 extern pte_t arch_make_huge_pte(pte_t entry, struct vm_area_struct *vma, 414 struct page *page, int writable); 415 #define arch_make_huge_pte arch_make_huge_pte 416 static inline unsigned long __pte_default_huge_mask(void) 417 { 418 unsigned long mask; 419 420 __asm__ __volatile__( 421 "\n661: sethi %%uhi(%1), %0\n" 422 " sllx %0, 32, %0\n" 423 " .section .sun4v_2insn_patch, \"ax\"\n" 424 " .word 661b\n" 425 " mov %2, %0\n" 426 " nop\n" 427 " .previous\n" 428 : "=r" (mask) 429 : "i" (_PAGE_SZHUGE_4U), "i" (_PAGE_SZHUGE_4V)); 430 431 return mask; 432 } 433 434 static inline pte_t pte_mkhuge(pte_t pte) 435 { 436 return __pte(pte_val(pte) | __pte_default_huge_mask()); 437 } 438 439 static inline bool is_default_hugetlb_pte(pte_t pte) 440 { 441 unsigned long mask = __pte_default_huge_mask(); 442 443 return (pte_val(pte) & mask) == mask; 444 } 445 446 static inline bool is_hugetlb_pmd(pmd_t pmd) 447 { 448 return !!(pmd_val(pmd) & _PAGE_PMD_HUGE); 449 } 450 451 static inline bool is_hugetlb_pud(pud_t pud) 452 { 453 return !!(pud_val(pud) & _PAGE_PUD_HUGE); 454 } 455 456 #ifdef CONFIG_TRANSPARENT_HUGEPAGE 457 static inline pmd_t pmd_mkhuge(pmd_t pmd) 458 { 459 pte_t pte = __pte(pmd_val(pmd)); 460 461 pte = pte_mkhuge(pte); 462 pte_val(pte) |= _PAGE_PMD_HUGE; 463 464 return __pmd(pte_val(pte)); 465 } 466 #endif 467 #else 468 static inline bool is_hugetlb_pte(pte_t pte) 469 { 470 return false; 471 } 472 #endif 473 474 static inline pte_t pte_mkdirty(pte_t pte) 475 { 476 unsigned long val = pte_val(pte), tmp; 477 478 __asm__ __volatile__( 479 "\n661: or %0, %3, %0\n" 480 " nop\n" 481 "\n662: nop\n" 482 " nop\n" 483 " .section .sun4v_2insn_patch, \"ax\"\n" 484 " .word 661b\n" 485 " sethi %%uhi(%4), %1\n" 486 " sllx %1, 32, %1\n" 487 " .word 662b\n" 488 " or %1, %%lo(%4), %1\n" 489 " or %0, %1, %0\n" 490 " .previous\n" 491 : "=r" (val), "=r" (tmp) 492 : "0" (val), "i" (_PAGE_MODIFIED_4U | _PAGE_W_4U), 493 "i" (_PAGE_MODIFIED_4V | _PAGE_W_4V)); 494 495 return __pte(val); 496 } 497 498 static inline pte_t pte_mkclean(pte_t pte) 499 { 500 unsigned long val = pte_val(pte), tmp; 501 502 __asm__ __volatile__( 503 "\n661: andn %0, %3, %0\n" 504 " nop\n" 505 "\n662: nop\n" 506 " nop\n" 507 " .section .sun4v_2insn_patch, \"ax\"\n" 508 " .word 661b\n" 509 " sethi %%uhi(%4), %1\n" 510 " sllx %1, 32, %1\n" 511 " .word 662b\n" 512 " or %1, %%lo(%4), %1\n" 513 " andn %0, %1, %0\n" 514 " .previous\n" 515 : "=r" (val), "=r" (tmp) 516 : "0" (val), "i" (_PAGE_MODIFIED_4U | _PAGE_W_4U), 517 "i" (_PAGE_MODIFIED_4V | _PAGE_W_4V)); 518 519 return __pte(val); 520 } 521 522 static inline pte_t pte_mkwrite(pte_t pte) 523 { 524 unsigned long val = pte_val(pte), mask; 525 526 __asm__ __volatile__( 527 "\n661: mov %1, %0\n" 528 " nop\n" 529 " .section .sun4v_2insn_patch, \"ax\"\n" 530 " .word 661b\n" 531 " sethi %%uhi(%2), %0\n" 532 " sllx %0, 32, %0\n" 533 " .previous\n" 534 : "=r" (mask) 535 : "i" (_PAGE_WRITE_4U), "i" (_PAGE_WRITE_4V)); 536 537 return __pte(val | mask); 538 } 539 540 static inline pte_t pte_wrprotect(pte_t pte) 541 { 542 unsigned long val = pte_val(pte), tmp; 543 544 __asm__ __volatile__( 545 "\n661: andn %0, %3, %0\n" 546 " nop\n" 547 "\n662: nop\n" 548 " nop\n" 549 " .section .sun4v_2insn_patch, \"ax\"\n" 550 " .word 661b\n" 551 " sethi %%uhi(%4), %1\n" 552 " sllx %1, 32, %1\n" 553 " .word 662b\n" 554 " or %1, %%lo(%4), %1\n" 555 " andn %0, %1, %0\n" 556 " .previous\n" 557 : "=r" (val), "=r" (tmp) 558 : "0" (val), "i" (_PAGE_WRITE_4U | _PAGE_W_4U), 559 "i" (_PAGE_WRITE_4V | _PAGE_W_4V)); 560 561 return __pte(val); 562 } 563 564 static inline pte_t pte_mkold(pte_t pte) 565 { 566 unsigned long mask; 567 568 __asm__ __volatile__( 569 "\n661: mov %1, %0\n" 570 " nop\n" 571 " .section .sun4v_2insn_patch, \"ax\"\n" 572 " .word 661b\n" 573 " sethi %%uhi(%2), %0\n" 574 " sllx %0, 32, %0\n" 575 " .previous\n" 576 : "=r" (mask) 577 : "i" (_PAGE_ACCESSED_4U), "i" (_PAGE_ACCESSED_4V)); 578 579 mask |= _PAGE_R; 580 581 return __pte(pte_val(pte) & ~mask); 582 } 583 584 static inline pte_t pte_mkyoung(pte_t pte) 585 { 586 unsigned long mask; 587 588 __asm__ __volatile__( 589 "\n661: mov %1, %0\n" 590 " nop\n" 591 " .section .sun4v_2insn_patch, \"ax\"\n" 592 " .word 661b\n" 593 " sethi %%uhi(%2), %0\n" 594 " sllx %0, 32, %0\n" 595 " .previous\n" 596 : "=r" (mask) 597 : "i" (_PAGE_ACCESSED_4U), "i" (_PAGE_ACCESSED_4V)); 598 599 mask |= _PAGE_R; 600 601 return __pte(pte_val(pte) | mask); 602 } 603 604 static inline pte_t pte_mkspecial(pte_t pte) 605 { 606 pte_val(pte) |= _PAGE_SPECIAL; 607 return pte; 608 } 609 610 static inline pte_t pte_mkmcd(pte_t pte) 611 { 612 pte_val(pte) |= _PAGE_MCD_4V; 613 return pte; 614 } 615 616 static inline pte_t pte_mknotmcd(pte_t pte) 617 { 618 pte_val(pte) &= ~_PAGE_MCD_4V; 619 return pte; 620 } 621 622 static inline unsigned long pte_young(pte_t pte) 623 { 624 unsigned long mask; 625 626 __asm__ __volatile__( 627 "\n661: mov %1, %0\n" 628 " nop\n" 629 " .section .sun4v_2insn_patch, \"ax\"\n" 630 " .word 661b\n" 631 " sethi %%uhi(%2), %0\n" 632 " sllx %0, 32, %0\n" 633 " .previous\n" 634 : "=r" (mask) 635 : "i" (_PAGE_ACCESSED_4U), "i" (_PAGE_ACCESSED_4V)); 636 637 return (pte_val(pte) & mask); 638 } 639 640 static inline unsigned long pte_dirty(pte_t pte) 641 { 642 unsigned long mask; 643 644 __asm__ __volatile__( 645 "\n661: mov %1, %0\n" 646 " nop\n" 647 " .section .sun4v_2insn_patch, \"ax\"\n" 648 " .word 661b\n" 649 " sethi %%uhi(%2), %0\n" 650 " sllx %0, 32, %0\n" 651 " .previous\n" 652 : "=r" (mask) 653 : "i" (_PAGE_MODIFIED_4U), "i" (_PAGE_MODIFIED_4V)); 654 655 return (pte_val(pte) & mask); 656 } 657 658 static inline unsigned long pte_write(pte_t pte) 659 { 660 unsigned long mask; 661 662 __asm__ __volatile__( 663 "\n661: mov %1, %0\n" 664 " nop\n" 665 " .section .sun4v_2insn_patch, \"ax\"\n" 666 " .word 661b\n" 667 " sethi %%uhi(%2), %0\n" 668 " sllx %0, 32, %0\n" 669 " .previous\n" 670 : "=r" (mask) 671 : "i" (_PAGE_WRITE_4U), "i" (_PAGE_WRITE_4V)); 672 673 return (pte_val(pte) & mask); 674 } 675 676 static inline unsigned long pte_exec(pte_t pte) 677 { 678 unsigned long mask; 679 680 __asm__ __volatile__( 681 "\n661: sethi %%hi(%1), %0\n" 682 " .section .sun4v_1insn_patch, \"ax\"\n" 683 " .word 661b\n" 684 " mov %2, %0\n" 685 " .previous\n" 686 : "=r" (mask) 687 : "i" (_PAGE_EXEC_4U), "i" (_PAGE_EXEC_4V)); 688 689 return (pte_val(pte) & mask); 690 } 691 692 static inline unsigned long pte_present(pte_t pte) 693 { 694 unsigned long val = pte_val(pte); 695 696 __asm__ __volatile__( 697 "\n661: and %0, %2, %0\n" 698 " .section .sun4v_1insn_patch, \"ax\"\n" 699 " .word 661b\n" 700 " and %0, %3, %0\n" 701 " .previous\n" 702 : "=r" (val) 703 : "0" (val), "i" (_PAGE_PRESENT_4U), "i" (_PAGE_PRESENT_4V)); 704 705 return val; 706 } 707 708 #define pte_accessible pte_accessible 709 static inline unsigned long pte_accessible(struct mm_struct *mm, pte_t a) 710 { 711 return pte_val(a) & _PAGE_VALID; 712 } 713 714 static inline unsigned long pte_special(pte_t pte) 715 { 716 return pte_val(pte) & _PAGE_SPECIAL; 717 } 718 719 static inline unsigned long pmd_large(pmd_t pmd) 720 { 721 pte_t pte = __pte(pmd_val(pmd)); 722 723 return pte_val(pte) & _PAGE_PMD_HUGE; 724 } 725 726 static inline unsigned long pmd_pfn(pmd_t pmd) 727 { 728 pte_t pte = __pte(pmd_val(pmd)); 729 730 return pte_pfn(pte); 731 } 732 733 #define pmd_write pmd_write 734 static inline unsigned long pmd_write(pmd_t pmd) 735 { 736 pte_t pte = __pte(pmd_val(pmd)); 737 738 return pte_write(pte); 739 } 740 741 #define pud_write(pud) pte_write(__pte(pud_val(pud))) 742 743 #ifdef CONFIG_TRANSPARENT_HUGEPAGE 744 static inline unsigned long pmd_dirty(pmd_t pmd) 745 { 746 pte_t pte = __pte(pmd_val(pmd)); 747 748 return pte_dirty(pte); 749 } 750 751 static inline unsigned long pmd_young(pmd_t pmd) 752 { 753 pte_t pte = __pte(pmd_val(pmd)); 754 755 return pte_young(pte); 756 } 757 758 static inline unsigned long pmd_trans_huge(pmd_t pmd) 759 { 760 pte_t pte = __pte(pmd_val(pmd)); 761 762 return pte_val(pte) & _PAGE_PMD_HUGE; 763 } 764 765 static inline pmd_t pmd_mkold(pmd_t pmd) 766 { 767 pte_t pte = __pte(pmd_val(pmd)); 768 769 pte = pte_mkold(pte); 770 771 return __pmd(pte_val(pte)); 772 } 773 774 static inline pmd_t pmd_wrprotect(pmd_t pmd) 775 { 776 pte_t pte = __pte(pmd_val(pmd)); 777 778 pte = pte_wrprotect(pte); 779 780 return __pmd(pte_val(pte)); 781 } 782 783 static inline pmd_t pmd_mkdirty(pmd_t pmd) 784 { 785 pte_t pte = __pte(pmd_val(pmd)); 786 787 pte = pte_mkdirty(pte); 788 789 return __pmd(pte_val(pte)); 790 } 791 792 static inline pmd_t pmd_mkclean(pmd_t pmd) 793 { 794 pte_t pte = __pte(pmd_val(pmd)); 795 796 pte = pte_mkclean(pte); 797 798 return __pmd(pte_val(pte)); 799 } 800 801 static inline pmd_t pmd_mkyoung(pmd_t pmd) 802 { 803 pte_t pte = __pte(pmd_val(pmd)); 804 805 pte = pte_mkyoung(pte); 806 807 return __pmd(pte_val(pte)); 808 } 809 810 static inline pmd_t pmd_mkwrite(pmd_t pmd) 811 { 812 pte_t pte = __pte(pmd_val(pmd)); 813 814 pte = pte_mkwrite(pte); 815 816 return __pmd(pte_val(pte)); 817 } 818 819 static inline pgprot_t pmd_pgprot(pmd_t entry) 820 { 821 unsigned long val = pmd_val(entry); 822 823 return __pgprot(val); 824 } 825 #endif 826 827 static inline int pmd_present(pmd_t pmd) 828 { 829 return pmd_val(pmd) != 0UL; 830 } 831 832 #define pmd_none(pmd) (!pmd_val(pmd)) 833 834 /* pmd_bad() is only called on non-trans-huge PMDs. Our encoding is 835 * very simple, it's just the physical address. PTE tables are of 836 * size PAGE_SIZE so make sure the sub-PAGE_SIZE bits are clear and 837 * the top bits outside of the range of any physical address size we 838 * support are clear as well. We also validate the physical itself. 839 */ 840 #define pmd_bad(pmd) (pmd_val(pmd) & ~PAGE_MASK) 841 842 #define pud_none(pud) (!pud_val(pud)) 843 844 #define pud_bad(pud) (pud_val(pud) & ~PAGE_MASK) 845 846 #define pgd_none(pgd) (!pgd_val(pgd)) 847 848 #define pgd_bad(pgd) (pgd_val(pgd) & ~PAGE_MASK) 849 850 #ifdef CONFIG_TRANSPARENT_HUGEPAGE 851 void set_pmd_at(struct mm_struct *mm, unsigned long addr, 852 pmd_t *pmdp, pmd_t pmd); 853 #else 854 static inline void set_pmd_at(struct mm_struct *mm, unsigned long addr, 855 pmd_t *pmdp, pmd_t pmd) 856 { 857 *pmdp = pmd; 858 } 859 #endif 860 861 static inline void pmd_set(struct mm_struct *mm, pmd_t *pmdp, pte_t *ptep) 862 { 863 unsigned long val = __pa((unsigned long) (ptep)); 864 865 pmd_val(*pmdp) = val; 866 } 867 868 #define pud_set(pudp, pmdp) \ 869 (pud_val(*(pudp)) = (__pa((unsigned long) (pmdp)))) 870 static inline unsigned long __pmd_page(pmd_t pmd) 871 { 872 pte_t pte = __pte(pmd_val(pmd)); 873 unsigned long pfn; 874 875 pfn = pte_pfn(pte); 876 877 return ((unsigned long) __va(pfn << PAGE_SHIFT)); 878 } 879 880 static inline unsigned long pud_page_vaddr(pud_t pud) 881 { 882 pte_t pte = __pte(pud_val(pud)); 883 unsigned long pfn; 884 885 pfn = pte_pfn(pte); 886 887 return ((unsigned long) __va(pfn << PAGE_SHIFT)); 888 } 889 890 #define pmd_page(pmd) virt_to_page((void *)__pmd_page(pmd)) 891 #define pud_page(pud) virt_to_page((void *)pud_page_vaddr(pud)) 892 #define pmd_clear(pmdp) (pmd_val(*(pmdp)) = 0UL) 893 #define pud_present(pud) (pud_val(pud) != 0U) 894 #define pud_clear(pudp) (pud_val(*(pudp)) = 0UL) 895 #define pgd_page_vaddr(pgd) \ 896 ((unsigned long) __va(pgd_val(pgd))) 897 #define pgd_present(pgd) (pgd_val(pgd) != 0U) 898 #define pgd_clear(pgdp) (pgd_val(*(pgdp)) = 0UL) 899 900 static inline unsigned long pud_large(pud_t pud) 901 { 902 pte_t pte = __pte(pud_val(pud)); 903 904 return pte_val(pte) & _PAGE_PMD_HUGE; 905 } 906 907 static inline unsigned long pud_pfn(pud_t pud) 908 { 909 pte_t pte = __pte(pud_val(pud)); 910 911 return pte_pfn(pte); 912 } 913 914 /* Same in both SUN4V and SUN4U. */ 915 #define pte_none(pte) (!pte_val(pte)) 916 917 #define pgd_set(pgdp, pudp) \ 918 (pgd_val(*(pgdp)) = (__pa((unsigned long) (pudp)))) 919 920 /* to find an entry in a page-table-directory. */ 921 #define pgd_index(address) (((address) >> PGDIR_SHIFT) & (PTRS_PER_PGD - 1)) 922 #define pgd_offset(mm, address) ((mm)->pgd + pgd_index(address)) 923 924 /* to find an entry in a kernel page-table-directory */ 925 #define pgd_offset_k(address) pgd_offset(&init_mm, address) 926 927 /* Find an entry in the third-level page table.. */ 928 #define pud_index(address) (((address) >> PUD_SHIFT) & (PTRS_PER_PUD - 1)) 929 #define pud_offset(pgdp, address) \ 930 ((pud_t *) pgd_page_vaddr(*(pgdp)) + pud_index(address)) 931 932 /* Find an entry in the second-level page table.. */ 933 #define pmd_offset(pudp, address) \ 934 ((pmd_t *) pud_page_vaddr(*(pudp)) + \ 935 (((address) >> PMD_SHIFT) & (PTRS_PER_PMD-1))) 936 937 /* Find an entry in the third-level page table.. */ 938 #define pte_index(dir, address) \ 939 ((pte_t *) __pmd_page(*(dir)) + \ 940 ((address >> PAGE_SHIFT) & (PTRS_PER_PTE - 1))) 941 #define pte_offset_kernel pte_index 942 #define pte_offset_map pte_index 943 #define pte_unmap(pte) do { } while (0) 944 945 /* We cannot include <linux/mm_types.h> at this point yet: */ 946 extern struct mm_struct init_mm; 947 948 /* Actual page table PTE updates. */ 949 void tlb_batch_add(struct mm_struct *mm, unsigned long vaddr, 950 pte_t *ptep, pte_t orig, int fullmm, 951 unsigned int hugepage_shift); 952 953 static void maybe_tlb_batch_add(struct mm_struct *mm, unsigned long vaddr, 954 pte_t *ptep, pte_t orig, int fullmm, 955 unsigned int hugepage_shift) 956 { 957 /* It is more efficient to let flush_tlb_kernel_range() 958 * handle init_mm tlb flushes. 959 * 960 * SUN4V NOTE: _PAGE_VALID is the same value in both the SUN4U 961 * and SUN4V pte layout, so this inline test is fine. 962 */ 963 if (likely(mm != &init_mm) && pte_accessible(mm, orig)) 964 tlb_batch_add(mm, vaddr, ptep, orig, fullmm, hugepage_shift); 965 } 966 967 #define __HAVE_ARCH_PMDP_HUGE_GET_AND_CLEAR 968 static inline pmd_t pmdp_huge_get_and_clear(struct mm_struct *mm, 969 unsigned long addr, 970 pmd_t *pmdp) 971 { 972 pmd_t pmd = *pmdp; 973 set_pmd_at(mm, addr, pmdp, __pmd(0UL)); 974 return pmd; 975 } 976 977 static inline void __set_pte_at(struct mm_struct *mm, unsigned long addr, 978 pte_t *ptep, pte_t pte, int fullmm) 979 { 980 pte_t orig = *ptep; 981 982 *ptep = pte; 983 maybe_tlb_batch_add(mm, addr, ptep, orig, fullmm, PAGE_SHIFT); 984 } 985 986 #define set_pte_at(mm,addr,ptep,pte) \ 987 __set_pte_at((mm), (addr), (ptep), (pte), 0) 988 989 #define pte_clear(mm,addr,ptep) \ 990 set_pte_at((mm), (addr), (ptep), __pte(0UL)) 991 992 #define __HAVE_ARCH_PTE_CLEAR_NOT_PRESENT_FULL 993 #define pte_clear_not_present_full(mm,addr,ptep,fullmm) \ 994 __set_pte_at((mm), (addr), (ptep), __pte(0UL), (fullmm)) 995 996 #ifdef DCACHE_ALIASING_POSSIBLE 997 #define __HAVE_ARCH_MOVE_PTE 998 #define move_pte(pte, prot, old_addr, new_addr) \ 999 ({ \ 1000 pte_t newpte = (pte); \ 1001 if (tlb_type != hypervisor && pte_present(pte)) { \ 1002 unsigned long this_pfn = pte_pfn(pte); \ 1003 \ 1004 if (pfn_valid(this_pfn) && \ 1005 (((old_addr) ^ (new_addr)) & (1 << 13))) \ 1006 flush_dcache_page_all(current->mm, \ 1007 pfn_to_page(this_pfn)); \ 1008 } \ 1009 newpte; \ 1010 }) 1011 #endif 1012 1013 extern pgd_t swapper_pg_dir[PTRS_PER_PGD]; 1014 1015 void paging_init(void); 1016 unsigned long find_ecache_flush_span(unsigned long size); 1017 1018 struct seq_file; 1019 void mmu_info(struct seq_file *); 1020 1021 struct vm_area_struct; 1022 void update_mmu_cache(struct vm_area_struct *, unsigned long, pte_t *); 1023 #ifdef CONFIG_TRANSPARENT_HUGEPAGE 1024 void update_mmu_cache_pmd(struct vm_area_struct *vma, unsigned long addr, 1025 pmd_t *pmd); 1026 1027 #define __HAVE_ARCH_PMDP_INVALIDATE 1028 extern pmd_t pmdp_invalidate(struct vm_area_struct *vma, unsigned long address, 1029 pmd_t *pmdp); 1030 1031 #define __HAVE_ARCH_PGTABLE_DEPOSIT 1032 void pgtable_trans_huge_deposit(struct mm_struct *mm, pmd_t *pmdp, 1033 pgtable_t pgtable); 1034 1035 #define __HAVE_ARCH_PGTABLE_WITHDRAW 1036 pgtable_t pgtable_trans_huge_withdraw(struct mm_struct *mm, pmd_t *pmdp); 1037 #endif 1038 1039 /* Encode and de-code a swap entry */ 1040 #define __swp_type(entry) (((entry).val >> PAGE_SHIFT) & 0xffUL) 1041 #define __swp_offset(entry) ((entry).val >> (PAGE_SHIFT + 8UL)) 1042 #define __swp_entry(type, offset) \ 1043 ( (swp_entry_t) \ 1044 { \ 1045 (((long)(type) << PAGE_SHIFT) | \ 1046 ((long)(offset) << (PAGE_SHIFT + 8UL))) \ 1047 } ) 1048 #define __pte_to_swp_entry(pte) ((swp_entry_t) { pte_val(pte) }) 1049 #define __swp_entry_to_pte(x) ((pte_t) { (x).val }) 1050 1051 int page_in_phys_avail(unsigned long paddr); 1052 1053 /* 1054 * For sparc32&64, the pfn in io_remap_pfn_range() carries <iospace> in 1055 * its high 4 bits. These macros/functions put it there or get it from there. 1056 */ 1057 #define MK_IOSPACE_PFN(space, pfn) (pfn | (space << (BITS_PER_LONG - 4))) 1058 #define GET_IOSPACE(pfn) (pfn >> (BITS_PER_LONG - 4)) 1059 #define GET_PFN(pfn) (pfn & 0x0fffffffffffffffUL) 1060 1061 int remap_pfn_range(struct vm_area_struct *, unsigned long, unsigned long, 1062 unsigned long, pgprot_t); 1063 1064 void adi_restore_tags(struct mm_struct *mm, struct vm_area_struct *vma, 1065 unsigned long addr, pte_t pte); 1066 1067 int adi_save_tags(struct mm_struct *mm, struct vm_area_struct *vma, 1068 unsigned long addr, pte_t oldpte); 1069 1070 #define __HAVE_ARCH_DO_SWAP_PAGE 1071 static inline void arch_do_swap_page(struct mm_struct *mm, 1072 struct vm_area_struct *vma, 1073 unsigned long addr, 1074 pte_t pte, pte_t oldpte) 1075 { 1076 /* If this is a new page being mapped in, there can be no 1077 * ADI tags stored away for this page. Skip looking for 1078 * stored tags 1079 */ 1080 if (pte_none(oldpte)) 1081 return; 1082 1083 if (adi_state.enabled && (pte_val(pte) & _PAGE_MCD_4V)) 1084 adi_restore_tags(mm, vma, addr, pte); 1085 } 1086 1087 #define __HAVE_ARCH_UNMAP_ONE 1088 static inline int arch_unmap_one(struct mm_struct *mm, 1089 struct vm_area_struct *vma, 1090 unsigned long addr, pte_t oldpte) 1091 { 1092 if (adi_state.enabled && (pte_val(oldpte) & _PAGE_MCD_4V)) 1093 return adi_save_tags(mm, vma, addr, oldpte); 1094 return 0; 1095 } 1096 1097 static inline int io_remap_pfn_range(struct vm_area_struct *vma, 1098 unsigned long from, unsigned long pfn, 1099 unsigned long size, pgprot_t prot) 1100 { 1101 unsigned long offset = GET_PFN(pfn) << PAGE_SHIFT; 1102 int space = GET_IOSPACE(pfn); 1103 unsigned long phys_base; 1104 1105 phys_base = offset | (((unsigned long) space) << 32UL); 1106 1107 return remap_pfn_range(vma, from, phys_base >> PAGE_SHIFT, size, prot); 1108 } 1109 #define io_remap_pfn_range io_remap_pfn_range 1110 1111 #include <asm/tlbflush.h> 1112 #include <asm-generic/pgtable.h> 1113 1114 /* We provide our own get_unmapped_area to cope with VA holes and 1115 * SHM area cache aliasing for userland. 1116 */ 1117 #define HAVE_ARCH_UNMAPPED_AREA 1118 #define HAVE_ARCH_UNMAPPED_AREA_TOPDOWN 1119 1120 /* We provide a special get_unmapped_area for framebuffer mmaps to try and use 1121 * the largest alignment possible such that larget PTEs can be used. 1122 */ 1123 unsigned long get_fb_unmapped_area(struct file *filp, unsigned long, 1124 unsigned long, unsigned long, 1125 unsigned long); 1126 #define HAVE_ARCH_FB_UNMAPPED_AREA 1127 1128 void pgtable_cache_init(void); 1129 void sun4v_register_fault_status(void); 1130 void sun4v_ktsb_register(void); 1131 void __init cheetah_ecache_flush_init(void); 1132 void sun4v_patch_tlb_handlers(void); 1133 1134 extern unsigned long cmdline_memory_size; 1135 1136 asmlinkage void do_sparc64_fault(struct pt_regs *regs); 1137 1138 #endif /* !(__ASSEMBLY__) */ 1139 1140 #endif /* !(_SPARC64_PGTABLE_H) */ 1141