xref: /openbmc/linux/arch/sparc/include/asm/chmctrl.h (revision b2441318)
1 /* SPDX-License-Identifier: GPL-2.0 */
2 #ifndef _SPARC64_CHMCTRL_H
3 #define _SPARC64_CHMCTRL_H
4 
5 /* Cheetah memory controller programmable registers. */
6 #define CHMCTRL_TCTRL1		0x00 /* Memory Timing Control I		*/
7 #define CHMCTRL_TCTRL2		0x08 /* Memory Timing Control II	*/
8 #define CHMCTRL_TCTRL3		0x38 /* Memory Timing Control III	*/
9 #define CHMCTRL_TCTRL4		0x40 /* Memory Timing Control IV	*/
10 #define CHMCTRL_DECODE1		0x10 /* Memory Address Decode I		*/
11 #define CHMCTRL_DECODE2		0x18 /* Memory Address Decode II	*/
12 #define CHMCTRL_DECODE3		0x20 /* Memory Address Decode III	*/
13 #define CHMCTRL_DECODE4		0x28 /* Memory Address Decode IV	*/
14 #define CHMCTRL_MACTRL		0x30 /* Memory Address Control		*/
15 
16 /* Memory Timing Control I */
17 #define TCTRL1_SDRAMCTL_DLY	0xf000000000000000UL
18 #define TCTRL1_SDRAMCTL_DLY_SHIFT     60
19 #define TCTRL1_SDRAMCLK_DLY	0x0e00000000000000UL
20 #define TCTRL1_SDRAMCLK_DLY_SHIFT     57
21 #define TCTRL1_R		0x0100000000000000UL
22 #define TCTRL1_R_SHIFT 		      56
23 #define TCTRL1_AUTORFR_CYCLE	0x00fe000000000000UL
24 #define TCTRL1_AUTORFR_CYCLE_SHIFT    49
25 #define TCTRL1_RD_WAIT		0x0001f00000000000UL
26 #define TCTRL1_RD_WAIT_SHIFT	      44
27 #define TCTRL1_PC_CYCLE		0x00000fc000000000UL
28 #define TCTRL1_PC_CYCLE_SHIFT	      38
29 #define TCTRL1_WR_MORE_RAS_PW	0x0000003f00000000UL
30 #define TCTRL1_WR_MORE_RAS_PW_SHIFT   32
31 #define TCTRL1_RD_MORE_RAW_PW	0x00000000fc000000UL
32 #define TCTRL1_RD_MORE_RAS_PW_SHIFT   26
33 #define TCTRL1_ACT_WR_DLY	0x0000000003f00000UL
34 #define TCTRL1_ACT_WR_DLY_SHIFT	      20
35 #define TCTRL1_ACT_RD_DLY	0x00000000000fc000UL
36 #define TCTRL1_ACT_RD_DLY_SHIFT	      14
37 #define TCTRL1_BANK_PRESENT	0x0000000000003000UL
38 #define TCTRL1_BANK_PRESENT_SHIFT     12
39 #define TCTRL1_RFR_INT		0x0000000000000ff8UL
40 #define TCTRL1_RFR_INT_SHIFT	      3
41 #define TCTRL1_SET_MODE_REG	0x0000000000000004UL
42 #define TCTRL1_SET_MODE_REG_SHIFT     2
43 #define TCTRL1_RFR_ENABLE	0x0000000000000002UL
44 #define TCTRL1_RFR_ENABLE_SHIFT	      1
45 #define TCTRL1_PRECHG_ALL	0x0000000000000001UL
46 #define TCTRL1_PRECHG_ALL_SHIFT	      0
47 
48 /* Memory Timing Control II */
49 #define TCTRL2_WR_MSEL_DLY	0xfc00000000000000UL
50 #define TCTRL2_WR_MSEL_DLY_SHIFT      58
51 #define TCTRL2_RD_MSEL_DLY	0x03f0000000000000UL
52 #define TCTRL2_RD_MSEL_DLY_SHIFT      52
53 #define TCTRL2_WRDATA_THLD	0x000c000000000000UL
54 #define TCTRL2_WRDATA_THLD_SHIFT      50
55 #define TCTRL2_RDWR_RD_TI_DLY	0x0003f00000000000UL
56 #define TCTRL2_RDWR_RD_TI_DLY_SHIFT   44
57 #define TCTRL2_AUTOPRECHG_ENBL	0x0000080000000000UL
58 #define TCTRL2_AUTOPRECHG_ENBL_SHIFT  43
59 #define TCTRL2_RDWR_PI_MORE_DLY	0x000007c000000000UL
60 #define TCTRL2_RDWR_PI_MORE_DLY_SHIFT 38
61 #define TCTRL2_RDWR_1_DLY	0x0000003f00000000UL
62 #define TCTRL2_RDWR_1_DLY_SHIFT       32
63 #define TCTRL2_WRWR_PI_MORE_DLY	0x00000000f8000000UL
64 #define TCTRL2_WRWR_PI_MORE_DLY_SHIFT 27
65 #define TCTRL2_WRWR_1_DLY	0x0000000007e00000UL
66 #define TCTRL2_WRWR_1_DLY_SHIFT       21
67 #define TCTRL2_RDWR_RD_PI_MORE_DLY 0x00000000001f0000UL
68 #define TCTRL2_RDWR_RD_PI_MORE_DLY_SHIFT 16
69 #define TCTRL2_R		0x0000000000008000UL
70 #define TCTRL2_R_SHIFT		      15
71 #define TCTRL2_SDRAM_MODE_REG_DATA 0x0000000000007fffUL
72 #define TCTRL2_SDRAM_MODE_REG_DATA_SHIFT 0
73 
74 /* Memory Timing Control III */
75 #define TCTRL3_SDRAM_CTL_DLY	0xf000000000000000UL
76 #define TCTRL3_SDRAM_CTL_DLY_SHIFT    60
77 #define TCTRL3_SDRAM_CLK_DLY	0x0e00000000000000UL
78 #define TCTRL3_SDRAM_CLK_DLY_SHIFT    57
79 #define TCTRL3_R		0x0100000000000000UL
80 #define TCTRL3_R_SHIFT		      56
81 #define TCTRL3_AUTO_RFR_CYCLE	0x00fe000000000000UL
82 #define TCTRL3_AUTO_RFR_CYCLE_SHIFT   49
83 #define TCTRL3_RD_WAIT		0x0001f00000000000UL
84 #define TCTRL3_RD_WAIT_SHIFT	      44
85 #define TCTRL3_PC_CYCLE		0x00000fc000000000UL
86 #define TCTRL3_PC_CYCLE_SHIFT	      38
87 #define TCTRL3_WR_MORE_RAW_PW	0x0000003f00000000UL
88 #define TCTRL3_WR_MORE_RAW_PW_SHIFT   32
89 #define TCTRL3_RD_MORE_RAW_PW	0x00000000fc000000UL
90 #define TCTRL3_RD_MORE_RAW_PW_SHIFT   26
91 #define TCTRL3_ACT_WR_DLY	0x0000000003f00000UL
92 #define TCTRL3_ACT_WR_DLY_SHIFT       20
93 #define TCTRL3_ACT_RD_DLY	0x00000000000fc000UL
94 #define TCTRL3_ACT_RD_DLY_SHIFT       14
95 #define TCTRL3_BANK_PRESENT	0x0000000000003000UL
96 #define TCTRL3_BANK_PRESENT_SHIFT     12
97 #define TCTRL3_RFR_INT		0x0000000000000ff8UL
98 #define TCTRL3_RFR_INT_SHIFT	      3
99 #define TCTRL3_SET_MODE_REG	0x0000000000000004UL
100 #define TCTRL3_SET_MODE_REG_SHIFT     2
101 #define TCTRL3_RFR_ENABLE	0x0000000000000002UL
102 #define TCTRL3_RFR_ENABLE_SHIFT       1
103 #define TCTRL3_PRECHG_ALL	0x0000000000000001UL
104 #define TCTRL3_PRECHG_ALL_SHIFT	      0
105 
106 /* Memory Timing Control IV */
107 #define TCTRL4_WR_MSEL_DLY	0xfc00000000000000UL
108 #define TCTRL4_WR_MSEL_DLY_SHIFT      58
109 #define TCTRL4_RD_MSEL_DLY	0x03f0000000000000UL
110 #define TCTRL4_RD_MSEL_DLY_SHIFT      52
111 #define TCTRL4_WRDATA_THLD	0x000c000000000000UL
112 #define TCTRL4_WRDATA_THLD_SHIFT      50
113 #define TCTRL4_RDWR_RD_RI_DLY	0x0003f00000000000UL
114 #define TCTRL4_RDWR_RD_RI_DLY_SHIFT   44
115 #define TCTRL4_AUTO_PRECHG_ENBL	0x0000080000000000UL
116 #define TCTRL4_AUTO_PRECHG_ENBL_SHIFT 43
117 #define TCTRL4_RD_WR_PI_MORE_DLY 0x000007c000000000UL
118 #define TCTRL4_RD_WR_PI_MORE_DLY_SHIFT 38
119 #define TCTRL4_RD_WR_TI_DLY	0x0000003f00000000UL
120 #define TCTRL4_RD_WR_TI_DLY_SHIFT     32
121 #define TCTRL4_WR_WR_PI_MORE_DLY 0x00000000f8000000UL
122 #define TCTRL4_WR_WR_PI_MORE_DLY_SHIFT 27
123 #define TCTRL4_WR_WR_TI_DLY	0x0000000007e00000UL
124 #define TCTRL4_WR_WR_TI_DLY_SHIFT     21
125 #define TCTRL4_RDWR_RD_PI_MORE_DLY 0x00000000001f000UL0
126 #define TCTRL4_RDWR_RD_PI_MORE_DLY_SHIFT 16
127 #define TCTRL4_R		0x0000000000008000UL
128 #define TCTRL4_R_SHIFT		      15
129 #define TCTRL4_SDRAM_MODE_REG_DATA 0x0000000000007fffUL
130 #define TCTRL4_SDRAM_MODE_REG_DATA_SHIFT 0
131 
132 /* All 4 memory address decoding registers have the
133  * same layout.
134  */
135 #define MEM_DECODE_VALID	0x8000000000000000UL /* Valid */
136 #define MEM_DECODE_VALID_SHIFT	      63
137 #define MEM_DECODE_UK		0x001ffe0000000000UL /* Upper mask */
138 #define MEM_DECODE_UK_SHIFT	      41
139 #define MEM_DECODE_UM		0x0000001ffff00000UL /* Upper match */
140 #define MEM_DECODE_UM_SHIFT	      20
141 #define MEM_DECODE_LK		0x000000000003c000UL /* Lower mask */
142 #define MEM_DECODE_LK_SHIFT	      14
143 #define MEM_DECODE_LM		0x0000000000000f00UL /* Lower match */
144 #define MEM_DECODE_LM_SHIFT           8
145 
146 #define PA_UPPER_BITS		0x000007fffc000000UL
147 #define PA_UPPER_BITS_SHIFT	26
148 #define PA_LOWER_BITS		0x00000000000003c0UL
149 #define PA_LOWER_BITS_SHIFT	6
150 
151 #define MACTRL_R0		         0x8000000000000000UL
152 #define MACTRL_R0_SHIFT		         63
153 #define MACTRL_ADDR_LE_PW                0x7000000000000000UL
154 #define MACTRL_ADDR_LE_PW_SHIFT		 60
155 #define MACTRL_CMD_PW                    0x0f00000000000000UL
156 #define MACTRL_CMD_PW_SHIFT		 56
157 #define MACTRL_HALF_MODE_WR_MSEL_DLY     0x00fc000000000000UL
158 #define MACTRL_HALF_MODE_WR_MSEL_DLY_SHIFT 50
159 #define MACTRL_HALF_MODE_RD_MSEL_DLY     0x0003f00000000000UL
160 #define MACTRL_HALF_MODE_RD_MSEL_DLY_SHIFT 44
161 #define MACTRL_HALF_MODE_SDRAM_CTL_DLY   0x00000f0000000000UL
162 #define MACTRL_HALF_MODE_SDRAM_CTL_DLY_SHIFT 40
163 #define MACTRL_HALF_MODE_SDRAM_CLK_DLY   0x000000e000000000UL
164 #define MACTRL_HALF_MODE_SDRAM_CLK_DLY_SHIFT 37
165 #define MACTRL_R1                        0x0000001000000000UL
166 #define MACTRL_R1_SHIFT                      36
167 #define MACTRL_BANKSEL_N_ROWADDR_SIZE_B3 0x0000000f00000000UL
168 #define MACTRL_BANKSEL_N_ROWADDR_SIZE_B3_SHIFT 32
169 #define MACTRL_ENC_INTLV_B3              0x00000000f8000000UL
170 #define MACTRL_ENC_INTLV_B3_SHIFT              27
171 #define MACTRL_BANKSEL_N_ROWADDR_SIZE_B2 0x0000000007800000UL
172 #define MACTRL_BANKSEL_N_ROWADDR_SIZE_B2_SHIFT 23
173 #define MACTRL_ENC_INTLV_B2              0x00000000007c0000UL
174 #define MACTRL_ENC_INTLV_B2_SHIFT              18
175 #define MACTRL_BANKSEL_N_ROWADDR_SIZE_B1 0x000000000003c000UL
176 #define MACTRL_BANKSEL_N_ROWADDR_SIZE_B1_SHIFT 14
177 #define MACTRL_ENC_INTLV_B1              0x0000000000003e00UL
178 #define MACTRL_ENC_INTLV_B1_SHIFT               9
179 #define MACTRL_BANKSEL_N_ROWADDR_SIZE_B0 0x00000000000001e0UL
180 #define MACTRL_BANKSEL_N_ROWADDR_SIZE_B0_SHIFT  5
181 #define MACTRL_ENC_INTLV_B0              0x000000000000001fUL
182 #define MACTRL_ENC_INTLV_B0_SHIFT               0
183 
184 #endif /* _SPARC64_CHMCTRL_H */
185