1 // SPDX-License-Identifier: GPL-2.0
2 /*
3 * arch/sh/kernel/cpu/sh2a/clock-sh7201.c
4 *
5 * SH7201 support for the clock framework
6 *
7 * Copyright (C) 2008 Peter Griffin <pgriffin@mpc-data.co.uk>
8 *
9 * Based on clock-sh4.c
10 * Copyright (C) 2005 Paul Mundt
11 */
12 #include <linux/init.h>
13 #include <linux/kernel.h>
14 #include <asm/clock.h>
15 #include <asm/freq.h>
16 #include <asm/io.h>
17
18 static const int pll1rate[]={1,2,3,4,6,8};
19 static const int pfc_divisors[]={1,2,3,4,6,8,12};
20 #define ifc_divisors pfc_divisors
21
22 static unsigned int pll2_mult;
23
master_clk_init(struct clk * clk)24 static void master_clk_init(struct clk *clk)
25 {
26 clk->rate = 10000000 * pll2_mult *
27 pll1rate[(__raw_readw(FREQCR) >> 8) & 0x0007];
28 }
29
30 static struct sh_clk_ops sh7201_master_clk_ops = {
31 .init = master_clk_init,
32 };
33
module_clk_recalc(struct clk * clk)34 static unsigned long module_clk_recalc(struct clk *clk)
35 {
36 int idx = (__raw_readw(FREQCR) & 0x0007);
37 return clk->parent->rate / pfc_divisors[idx];
38 }
39
40 static struct sh_clk_ops sh7201_module_clk_ops = {
41 .recalc = module_clk_recalc,
42 };
43
bus_clk_recalc(struct clk * clk)44 static unsigned long bus_clk_recalc(struct clk *clk)
45 {
46 int idx = (__raw_readw(FREQCR) & 0x0007);
47 return clk->parent->rate / pfc_divisors[idx];
48 }
49
50 static struct sh_clk_ops sh7201_bus_clk_ops = {
51 .recalc = bus_clk_recalc,
52 };
53
cpu_clk_recalc(struct clk * clk)54 static unsigned long cpu_clk_recalc(struct clk *clk)
55 {
56 int idx = ((__raw_readw(FREQCR) >> 4) & 0x0007);
57 return clk->parent->rate / ifc_divisors[idx];
58 }
59
60 static struct sh_clk_ops sh7201_cpu_clk_ops = {
61 .recalc = cpu_clk_recalc,
62 };
63
64 static struct sh_clk_ops *sh7201_clk_ops[] = {
65 &sh7201_master_clk_ops,
66 &sh7201_module_clk_ops,
67 &sh7201_bus_clk_ops,
68 &sh7201_cpu_clk_ops,
69 };
70
arch_init_clk_ops(struct sh_clk_ops ** ops,int idx)71 void __init arch_init_clk_ops(struct sh_clk_ops **ops, int idx)
72 {
73 if (test_mode_pin(MODE_PIN1 | MODE_PIN0))
74 pll2_mult = 1;
75 else if (test_mode_pin(MODE_PIN1))
76 pll2_mult = 2;
77 else
78 pll2_mult = 4;
79
80 if (idx < ARRAY_SIZE(sh7201_clk_ops))
81 *ops = sh7201_clk_ops[idx];
82 }
83