1 // SPDX-License-Identifier: GPL-2.0 2 /* BPF JIT compiler for RV64G 3 * 4 * Copyright(c) 2019 Björn Töpel <bjorn.topel@gmail.com> 5 * 6 */ 7 8 #include <linux/bitfield.h> 9 #include <linux/bpf.h> 10 #include <linux/filter.h> 11 #include <linux/memory.h> 12 #include <linux/stop_machine.h> 13 #include <asm/patch.h> 14 #include "bpf_jit.h" 15 16 #define RV_FENTRY_NINSNS 2 17 18 #define RV_REG_TCC RV_REG_A6 19 #define RV_REG_TCC_SAVED RV_REG_S6 /* Store A6 in S6 if program do calls */ 20 21 static const int regmap[] = { 22 [BPF_REG_0] = RV_REG_A5, 23 [BPF_REG_1] = RV_REG_A0, 24 [BPF_REG_2] = RV_REG_A1, 25 [BPF_REG_3] = RV_REG_A2, 26 [BPF_REG_4] = RV_REG_A3, 27 [BPF_REG_5] = RV_REG_A4, 28 [BPF_REG_6] = RV_REG_S1, 29 [BPF_REG_7] = RV_REG_S2, 30 [BPF_REG_8] = RV_REG_S3, 31 [BPF_REG_9] = RV_REG_S4, 32 [BPF_REG_FP] = RV_REG_S5, 33 [BPF_REG_AX] = RV_REG_T0, 34 }; 35 36 static const int pt_regmap[] = { 37 [RV_REG_A0] = offsetof(struct pt_regs, a0), 38 [RV_REG_A1] = offsetof(struct pt_regs, a1), 39 [RV_REG_A2] = offsetof(struct pt_regs, a2), 40 [RV_REG_A3] = offsetof(struct pt_regs, a3), 41 [RV_REG_A4] = offsetof(struct pt_regs, a4), 42 [RV_REG_A5] = offsetof(struct pt_regs, a5), 43 [RV_REG_S1] = offsetof(struct pt_regs, s1), 44 [RV_REG_S2] = offsetof(struct pt_regs, s2), 45 [RV_REG_S3] = offsetof(struct pt_regs, s3), 46 [RV_REG_S4] = offsetof(struct pt_regs, s4), 47 [RV_REG_S5] = offsetof(struct pt_regs, s5), 48 [RV_REG_T0] = offsetof(struct pt_regs, t0), 49 }; 50 51 enum { 52 RV_CTX_F_SEEN_TAIL_CALL = 0, 53 RV_CTX_F_SEEN_CALL = RV_REG_RA, 54 RV_CTX_F_SEEN_S1 = RV_REG_S1, 55 RV_CTX_F_SEEN_S2 = RV_REG_S2, 56 RV_CTX_F_SEEN_S3 = RV_REG_S3, 57 RV_CTX_F_SEEN_S4 = RV_REG_S4, 58 RV_CTX_F_SEEN_S5 = RV_REG_S5, 59 RV_CTX_F_SEEN_S6 = RV_REG_S6, 60 }; 61 62 static u8 bpf_to_rv_reg(int bpf_reg, struct rv_jit_context *ctx) 63 { 64 u8 reg = regmap[bpf_reg]; 65 66 switch (reg) { 67 case RV_CTX_F_SEEN_S1: 68 case RV_CTX_F_SEEN_S2: 69 case RV_CTX_F_SEEN_S3: 70 case RV_CTX_F_SEEN_S4: 71 case RV_CTX_F_SEEN_S5: 72 case RV_CTX_F_SEEN_S6: 73 __set_bit(reg, &ctx->flags); 74 } 75 return reg; 76 }; 77 78 static bool seen_reg(int reg, struct rv_jit_context *ctx) 79 { 80 switch (reg) { 81 case RV_CTX_F_SEEN_CALL: 82 case RV_CTX_F_SEEN_S1: 83 case RV_CTX_F_SEEN_S2: 84 case RV_CTX_F_SEEN_S3: 85 case RV_CTX_F_SEEN_S4: 86 case RV_CTX_F_SEEN_S5: 87 case RV_CTX_F_SEEN_S6: 88 return test_bit(reg, &ctx->flags); 89 } 90 return false; 91 } 92 93 static void mark_fp(struct rv_jit_context *ctx) 94 { 95 __set_bit(RV_CTX_F_SEEN_S5, &ctx->flags); 96 } 97 98 static void mark_call(struct rv_jit_context *ctx) 99 { 100 __set_bit(RV_CTX_F_SEEN_CALL, &ctx->flags); 101 } 102 103 static bool seen_call(struct rv_jit_context *ctx) 104 { 105 return test_bit(RV_CTX_F_SEEN_CALL, &ctx->flags); 106 } 107 108 static void mark_tail_call(struct rv_jit_context *ctx) 109 { 110 __set_bit(RV_CTX_F_SEEN_TAIL_CALL, &ctx->flags); 111 } 112 113 static bool seen_tail_call(struct rv_jit_context *ctx) 114 { 115 return test_bit(RV_CTX_F_SEEN_TAIL_CALL, &ctx->flags); 116 } 117 118 static u8 rv_tail_call_reg(struct rv_jit_context *ctx) 119 { 120 mark_tail_call(ctx); 121 122 if (seen_call(ctx)) { 123 __set_bit(RV_CTX_F_SEEN_S6, &ctx->flags); 124 return RV_REG_S6; 125 } 126 return RV_REG_A6; 127 } 128 129 static bool is_32b_int(s64 val) 130 { 131 return -(1L << 31) <= val && val < (1L << 31); 132 } 133 134 static bool in_auipc_jalr_range(s64 val) 135 { 136 /* 137 * auipc+jalr can reach any signed PC-relative offset in the range 138 * [-2^31 - 2^11, 2^31 - 2^11). 139 */ 140 return (-(1L << 31) - (1L << 11)) <= val && 141 val < ((1L << 31) - (1L << 11)); 142 } 143 144 /* Emit fixed-length instructions for address */ 145 static int emit_addr(u8 rd, u64 addr, bool extra_pass, struct rv_jit_context *ctx) 146 { 147 u64 ip = (u64)(ctx->insns + ctx->ninsns); 148 s64 off = addr - ip; 149 s64 upper = (off + (1 << 11)) >> 12; 150 s64 lower = off & 0xfff; 151 152 if (extra_pass && !in_auipc_jalr_range(off)) { 153 pr_err("bpf-jit: target offset 0x%llx is out of range\n", off); 154 return -ERANGE; 155 } 156 157 emit(rv_auipc(rd, upper), ctx); 158 emit(rv_addi(rd, rd, lower), ctx); 159 return 0; 160 } 161 162 /* Emit variable-length instructions for 32-bit and 64-bit imm */ 163 static void emit_imm(u8 rd, s64 val, struct rv_jit_context *ctx) 164 { 165 /* Note that the immediate from the add is sign-extended, 166 * which means that we need to compensate this by adding 2^12, 167 * when the 12th bit is set. A simpler way of doing this, and 168 * getting rid of the check, is to just add 2**11 before the 169 * shift. The "Loading a 32-Bit constant" example from the 170 * "Computer Organization and Design, RISC-V edition" book by 171 * Patterson/Hennessy highlights this fact. 172 * 173 * This also means that we need to process LSB to MSB. 174 */ 175 s64 upper = (val + (1 << 11)) >> 12; 176 /* Sign-extend lower 12 bits to 64 bits since immediates for li, addiw, 177 * and addi are signed and RVC checks will perform signed comparisons. 178 */ 179 s64 lower = ((val & 0xfff) << 52) >> 52; 180 int shift; 181 182 if (is_32b_int(val)) { 183 if (upper) 184 emit_lui(rd, upper, ctx); 185 186 if (!upper) { 187 emit_li(rd, lower, ctx); 188 return; 189 } 190 191 emit_addiw(rd, rd, lower, ctx); 192 return; 193 } 194 195 shift = __ffs(upper); 196 upper >>= shift; 197 shift += 12; 198 199 emit_imm(rd, upper, ctx); 200 201 emit_slli(rd, rd, shift, ctx); 202 if (lower) 203 emit_addi(rd, rd, lower, ctx); 204 } 205 206 static void __build_epilogue(bool is_tail_call, struct rv_jit_context *ctx) 207 { 208 int stack_adjust = ctx->stack_size, store_offset = stack_adjust - 8; 209 210 if (seen_reg(RV_REG_RA, ctx)) { 211 emit_ld(RV_REG_RA, store_offset, RV_REG_SP, ctx); 212 store_offset -= 8; 213 } 214 emit_ld(RV_REG_FP, store_offset, RV_REG_SP, ctx); 215 store_offset -= 8; 216 if (seen_reg(RV_REG_S1, ctx)) { 217 emit_ld(RV_REG_S1, store_offset, RV_REG_SP, ctx); 218 store_offset -= 8; 219 } 220 if (seen_reg(RV_REG_S2, ctx)) { 221 emit_ld(RV_REG_S2, store_offset, RV_REG_SP, ctx); 222 store_offset -= 8; 223 } 224 if (seen_reg(RV_REG_S3, ctx)) { 225 emit_ld(RV_REG_S3, store_offset, RV_REG_SP, ctx); 226 store_offset -= 8; 227 } 228 if (seen_reg(RV_REG_S4, ctx)) { 229 emit_ld(RV_REG_S4, store_offset, RV_REG_SP, ctx); 230 store_offset -= 8; 231 } 232 if (seen_reg(RV_REG_S5, ctx)) { 233 emit_ld(RV_REG_S5, store_offset, RV_REG_SP, ctx); 234 store_offset -= 8; 235 } 236 if (seen_reg(RV_REG_S6, ctx)) { 237 emit_ld(RV_REG_S6, store_offset, RV_REG_SP, ctx); 238 store_offset -= 8; 239 } 240 241 emit_addi(RV_REG_SP, RV_REG_SP, stack_adjust, ctx); 242 /* Set return value. */ 243 if (!is_tail_call) 244 emit_mv(RV_REG_A0, RV_REG_A5, ctx); 245 emit_jalr(RV_REG_ZERO, is_tail_call ? RV_REG_T3 : RV_REG_RA, 246 is_tail_call ? (RV_FENTRY_NINSNS + 1) * 4 : 0, /* skip reserved nops and TCC init */ 247 ctx); 248 } 249 250 static void emit_bcc(u8 cond, u8 rd, u8 rs, int rvoff, 251 struct rv_jit_context *ctx) 252 { 253 switch (cond) { 254 case BPF_JEQ: 255 emit(rv_beq(rd, rs, rvoff >> 1), ctx); 256 return; 257 case BPF_JGT: 258 emit(rv_bltu(rs, rd, rvoff >> 1), ctx); 259 return; 260 case BPF_JLT: 261 emit(rv_bltu(rd, rs, rvoff >> 1), ctx); 262 return; 263 case BPF_JGE: 264 emit(rv_bgeu(rd, rs, rvoff >> 1), ctx); 265 return; 266 case BPF_JLE: 267 emit(rv_bgeu(rs, rd, rvoff >> 1), ctx); 268 return; 269 case BPF_JNE: 270 emit(rv_bne(rd, rs, rvoff >> 1), ctx); 271 return; 272 case BPF_JSGT: 273 emit(rv_blt(rs, rd, rvoff >> 1), ctx); 274 return; 275 case BPF_JSLT: 276 emit(rv_blt(rd, rs, rvoff >> 1), ctx); 277 return; 278 case BPF_JSGE: 279 emit(rv_bge(rd, rs, rvoff >> 1), ctx); 280 return; 281 case BPF_JSLE: 282 emit(rv_bge(rs, rd, rvoff >> 1), ctx); 283 } 284 } 285 286 static void emit_branch(u8 cond, u8 rd, u8 rs, int rvoff, 287 struct rv_jit_context *ctx) 288 { 289 s64 upper, lower; 290 291 if (is_13b_int(rvoff)) { 292 emit_bcc(cond, rd, rs, rvoff, ctx); 293 return; 294 } 295 296 /* Adjust for jal */ 297 rvoff -= 4; 298 299 /* Transform, e.g.: 300 * bne rd,rs,foo 301 * to 302 * beq rd,rs,<.L1> 303 * (auipc foo) 304 * jal(r) foo 305 * .L1 306 */ 307 cond = invert_bpf_cond(cond); 308 if (is_21b_int(rvoff)) { 309 emit_bcc(cond, rd, rs, 8, ctx); 310 emit(rv_jal(RV_REG_ZERO, rvoff >> 1), ctx); 311 return; 312 } 313 314 /* 32b No need for an additional rvoff adjustment, since we 315 * get that from the auipc at PC', where PC = PC' + 4. 316 */ 317 upper = (rvoff + (1 << 11)) >> 12; 318 lower = rvoff & 0xfff; 319 320 emit_bcc(cond, rd, rs, 12, ctx); 321 emit(rv_auipc(RV_REG_T1, upper), ctx); 322 emit(rv_jalr(RV_REG_ZERO, RV_REG_T1, lower), ctx); 323 } 324 325 static void emit_zext_32(u8 reg, struct rv_jit_context *ctx) 326 { 327 emit_slli(reg, reg, 32, ctx); 328 emit_srli(reg, reg, 32, ctx); 329 } 330 331 static int emit_bpf_tail_call(int insn, struct rv_jit_context *ctx) 332 { 333 int tc_ninsn, off, start_insn = ctx->ninsns; 334 u8 tcc = rv_tail_call_reg(ctx); 335 336 /* a0: &ctx 337 * a1: &array 338 * a2: index 339 * 340 * if (index >= array->map.max_entries) 341 * goto out; 342 */ 343 tc_ninsn = insn ? ctx->offset[insn] - ctx->offset[insn - 1] : 344 ctx->offset[0]; 345 emit_zext_32(RV_REG_A2, ctx); 346 347 off = offsetof(struct bpf_array, map.max_entries); 348 if (is_12b_check(off, insn)) 349 return -1; 350 emit(rv_lwu(RV_REG_T1, off, RV_REG_A1), ctx); 351 off = ninsns_rvoff(tc_ninsn - (ctx->ninsns - start_insn)); 352 emit_branch(BPF_JGE, RV_REG_A2, RV_REG_T1, off, ctx); 353 354 /* if (--TCC < 0) 355 * goto out; 356 */ 357 emit_addi(RV_REG_TCC, tcc, -1, ctx); 358 off = ninsns_rvoff(tc_ninsn - (ctx->ninsns - start_insn)); 359 emit_branch(BPF_JSLT, RV_REG_TCC, RV_REG_ZERO, off, ctx); 360 361 /* prog = array->ptrs[index]; 362 * if (!prog) 363 * goto out; 364 */ 365 emit_slli(RV_REG_T2, RV_REG_A2, 3, ctx); 366 emit_add(RV_REG_T2, RV_REG_T2, RV_REG_A1, ctx); 367 off = offsetof(struct bpf_array, ptrs); 368 if (is_12b_check(off, insn)) 369 return -1; 370 emit_ld(RV_REG_T2, off, RV_REG_T2, ctx); 371 off = ninsns_rvoff(tc_ninsn - (ctx->ninsns - start_insn)); 372 emit_branch(BPF_JEQ, RV_REG_T2, RV_REG_ZERO, off, ctx); 373 374 /* goto *(prog->bpf_func + 4); */ 375 off = offsetof(struct bpf_prog, bpf_func); 376 if (is_12b_check(off, insn)) 377 return -1; 378 emit_ld(RV_REG_T3, off, RV_REG_T2, ctx); 379 __build_epilogue(true, ctx); 380 return 0; 381 } 382 383 static void init_regs(u8 *rd, u8 *rs, const struct bpf_insn *insn, 384 struct rv_jit_context *ctx) 385 { 386 u8 code = insn->code; 387 388 switch (code) { 389 case BPF_JMP | BPF_JA: 390 case BPF_JMP | BPF_CALL: 391 case BPF_JMP | BPF_EXIT: 392 case BPF_JMP | BPF_TAIL_CALL: 393 break; 394 default: 395 *rd = bpf_to_rv_reg(insn->dst_reg, ctx); 396 } 397 398 if (code & (BPF_ALU | BPF_X) || code & (BPF_ALU64 | BPF_X) || 399 code & (BPF_JMP | BPF_X) || code & (BPF_JMP32 | BPF_X) || 400 code & BPF_LDX || code & BPF_STX) 401 *rs = bpf_to_rv_reg(insn->src_reg, ctx); 402 } 403 404 static void emit_zext_32_rd_rs(u8 *rd, u8 *rs, struct rv_jit_context *ctx) 405 { 406 emit_mv(RV_REG_T2, *rd, ctx); 407 emit_zext_32(RV_REG_T2, ctx); 408 emit_mv(RV_REG_T1, *rs, ctx); 409 emit_zext_32(RV_REG_T1, ctx); 410 *rd = RV_REG_T2; 411 *rs = RV_REG_T1; 412 } 413 414 static void emit_sext_32_rd_rs(u8 *rd, u8 *rs, struct rv_jit_context *ctx) 415 { 416 emit_addiw(RV_REG_T2, *rd, 0, ctx); 417 emit_addiw(RV_REG_T1, *rs, 0, ctx); 418 *rd = RV_REG_T2; 419 *rs = RV_REG_T1; 420 } 421 422 static void emit_zext_32_rd_t1(u8 *rd, struct rv_jit_context *ctx) 423 { 424 emit_mv(RV_REG_T2, *rd, ctx); 425 emit_zext_32(RV_REG_T2, ctx); 426 emit_zext_32(RV_REG_T1, ctx); 427 *rd = RV_REG_T2; 428 } 429 430 static void emit_sext_32_rd(u8 *rd, struct rv_jit_context *ctx) 431 { 432 emit_addiw(RV_REG_T2, *rd, 0, ctx); 433 *rd = RV_REG_T2; 434 } 435 436 static int emit_jump_and_link(u8 rd, s64 rvoff, bool fixed_addr, 437 struct rv_jit_context *ctx) 438 { 439 s64 upper, lower; 440 441 if (rvoff && fixed_addr && is_21b_int(rvoff)) { 442 emit(rv_jal(rd, rvoff >> 1), ctx); 443 return 0; 444 } else if (in_auipc_jalr_range(rvoff)) { 445 upper = (rvoff + (1 << 11)) >> 12; 446 lower = rvoff & 0xfff; 447 emit(rv_auipc(RV_REG_T1, upper), ctx); 448 emit(rv_jalr(rd, RV_REG_T1, lower), ctx); 449 return 0; 450 } 451 452 pr_err("bpf-jit: target offset 0x%llx is out of range\n", rvoff); 453 return -ERANGE; 454 } 455 456 static bool is_signed_bpf_cond(u8 cond) 457 { 458 return cond == BPF_JSGT || cond == BPF_JSLT || 459 cond == BPF_JSGE || cond == BPF_JSLE; 460 } 461 462 static int emit_call(u64 addr, bool fixed_addr, struct rv_jit_context *ctx) 463 { 464 s64 off = 0; 465 u64 ip; 466 467 if (addr && ctx->insns) { 468 ip = (u64)(long)(ctx->insns + ctx->ninsns); 469 off = addr - ip; 470 } 471 472 return emit_jump_and_link(RV_REG_RA, off, fixed_addr, ctx); 473 } 474 475 static void emit_atomic(u8 rd, u8 rs, s16 off, s32 imm, bool is64, 476 struct rv_jit_context *ctx) 477 { 478 u8 r0; 479 int jmp_offset; 480 481 if (off) { 482 if (is_12b_int(off)) { 483 emit_addi(RV_REG_T1, rd, off, ctx); 484 } else { 485 emit_imm(RV_REG_T1, off, ctx); 486 emit_add(RV_REG_T1, RV_REG_T1, rd, ctx); 487 } 488 rd = RV_REG_T1; 489 } 490 491 switch (imm) { 492 /* lock *(u32/u64 *)(dst_reg + off16) <op>= src_reg */ 493 case BPF_ADD: 494 emit(is64 ? rv_amoadd_d(RV_REG_ZERO, rs, rd, 0, 0) : 495 rv_amoadd_w(RV_REG_ZERO, rs, rd, 0, 0), ctx); 496 break; 497 case BPF_AND: 498 emit(is64 ? rv_amoand_d(RV_REG_ZERO, rs, rd, 0, 0) : 499 rv_amoand_w(RV_REG_ZERO, rs, rd, 0, 0), ctx); 500 break; 501 case BPF_OR: 502 emit(is64 ? rv_amoor_d(RV_REG_ZERO, rs, rd, 0, 0) : 503 rv_amoor_w(RV_REG_ZERO, rs, rd, 0, 0), ctx); 504 break; 505 case BPF_XOR: 506 emit(is64 ? rv_amoxor_d(RV_REG_ZERO, rs, rd, 0, 0) : 507 rv_amoxor_w(RV_REG_ZERO, rs, rd, 0, 0), ctx); 508 break; 509 /* src_reg = atomic_fetch_<op>(dst_reg + off16, src_reg) */ 510 case BPF_ADD | BPF_FETCH: 511 emit(is64 ? rv_amoadd_d(rs, rs, rd, 0, 0) : 512 rv_amoadd_w(rs, rs, rd, 0, 0), ctx); 513 if (!is64) 514 emit_zext_32(rs, ctx); 515 break; 516 case BPF_AND | BPF_FETCH: 517 emit(is64 ? rv_amoand_d(rs, rs, rd, 0, 0) : 518 rv_amoand_w(rs, rs, rd, 0, 0), ctx); 519 if (!is64) 520 emit_zext_32(rs, ctx); 521 break; 522 case BPF_OR | BPF_FETCH: 523 emit(is64 ? rv_amoor_d(rs, rs, rd, 0, 0) : 524 rv_amoor_w(rs, rs, rd, 0, 0), ctx); 525 if (!is64) 526 emit_zext_32(rs, ctx); 527 break; 528 case BPF_XOR | BPF_FETCH: 529 emit(is64 ? rv_amoxor_d(rs, rs, rd, 0, 0) : 530 rv_amoxor_w(rs, rs, rd, 0, 0), ctx); 531 if (!is64) 532 emit_zext_32(rs, ctx); 533 break; 534 /* src_reg = atomic_xchg(dst_reg + off16, src_reg); */ 535 case BPF_XCHG: 536 emit(is64 ? rv_amoswap_d(rs, rs, rd, 0, 0) : 537 rv_amoswap_w(rs, rs, rd, 0, 0), ctx); 538 if (!is64) 539 emit_zext_32(rs, ctx); 540 break; 541 /* r0 = atomic_cmpxchg(dst_reg + off16, r0, src_reg); */ 542 case BPF_CMPXCHG: 543 r0 = bpf_to_rv_reg(BPF_REG_0, ctx); 544 emit(is64 ? rv_addi(RV_REG_T2, r0, 0) : 545 rv_addiw(RV_REG_T2, r0, 0), ctx); 546 emit(is64 ? rv_lr_d(r0, 0, rd, 0, 0) : 547 rv_lr_w(r0, 0, rd, 0, 0), ctx); 548 jmp_offset = ninsns_rvoff(8); 549 emit(rv_bne(RV_REG_T2, r0, jmp_offset >> 1), ctx); 550 emit(is64 ? rv_sc_d(RV_REG_T3, rs, rd, 0, 0) : 551 rv_sc_w(RV_REG_T3, rs, rd, 0, 0), ctx); 552 jmp_offset = ninsns_rvoff(-6); 553 emit(rv_bne(RV_REG_T3, 0, jmp_offset >> 1), ctx); 554 emit(rv_fence(0x3, 0x3), ctx); 555 break; 556 } 557 } 558 559 #define BPF_FIXUP_OFFSET_MASK GENMASK(26, 0) 560 #define BPF_FIXUP_REG_MASK GENMASK(31, 27) 561 562 bool ex_handler_bpf(const struct exception_table_entry *ex, 563 struct pt_regs *regs) 564 { 565 off_t offset = FIELD_GET(BPF_FIXUP_OFFSET_MASK, ex->fixup); 566 int regs_offset = FIELD_GET(BPF_FIXUP_REG_MASK, ex->fixup); 567 568 *(unsigned long *)((void *)regs + pt_regmap[regs_offset]) = 0; 569 regs->epc = (unsigned long)&ex->fixup - offset; 570 571 return true; 572 } 573 574 /* For accesses to BTF pointers, add an entry to the exception table */ 575 static int add_exception_handler(const struct bpf_insn *insn, 576 struct rv_jit_context *ctx, 577 int dst_reg, int insn_len) 578 { 579 struct exception_table_entry *ex; 580 unsigned long pc; 581 off_t offset; 582 583 if (!ctx->insns || !ctx->prog->aux->extable || 584 (BPF_MODE(insn->code) != BPF_PROBE_MEM && BPF_MODE(insn->code) != BPF_PROBE_MEMSX)) 585 return 0; 586 587 if (WARN_ON_ONCE(ctx->nexentries >= ctx->prog->aux->num_exentries)) 588 return -EINVAL; 589 590 if (WARN_ON_ONCE(insn_len > ctx->ninsns)) 591 return -EINVAL; 592 593 if (WARN_ON_ONCE(!rvc_enabled() && insn_len == 1)) 594 return -EINVAL; 595 596 ex = &ctx->prog->aux->extable[ctx->nexentries]; 597 pc = (unsigned long)&ctx->insns[ctx->ninsns - insn_len]; 598 599 offset = pc - (long)&ex->insn; 600 if (WARN_ON_ONCE(offset >= 0 || offset < INT_MIN)) 601 return -ERANGE; 602 ex->insn = offset; 603 604 /* 605 * Since the extable follows the program, the fixup offset is always 606 * negative and limited to BPF_JIT_REGION_SIZE. Store a positive value 607 * to keep things simple, and put the destination register in the upper 608 * bits. We don't need to worry about buildtime or runtime sort 609 * modifying the upper bits because the table is already sorted, and 610 * isn't part of the main exception table. 611 */ 612 offset = (long)&ex->fixup - (pc + insn_len * sizeof(u16)); 613 if (!FIELD_FIT(BPF_FIXUP_OFFSET_MASK, offset)) 614 return -ERANGE; 615 616 ex->fixup = FIELD_PREP(BPF_FIXUP_OFFSET_MASK, offset) | 617 FIELD_PREP(BPF_FIXUP_REG_MASK, dst_reg); 618 ex->type = EX_TYPE_BPF; 619 620 ctx->nexentries++; 621 return 0; 622 } 623 624 static int gen_jump_or_nops(void *target, void *ip, u32 *insns, bool is_call) 625 { 626 s64 rvoff; 627 struct rv_jit_context ctx; 628 629 ctx.ninsns = 0; 630 ctx.insns = (u16 *)insns; 631 632 if (!target) { 633 emit(rv_nop(), &ctx); 634 emit(rv_nop(), &ctx); 635 return 0; 636 } 637 638 rvoff = (s64)(target - ip); 639 return emit_jump_and_link(is_call ? RV_REG_T0 : RV_REG_ZERO, rvoff, false, &ctx); 640 } 641 642 int bpf_arch_text_poke(void *ip, enum bpf_text_poke_type poke_type, 643 void *old_addr, void *new_addr) 644 { 645 u32 old_insns[RV_FENTRY_NINSNS], new_insns[RV_FENTRY_NINSNS]; 646 bool is_call = poke_type == BPF_MOD_CALL; 647 int ret; 648 649 if (!is_kernel_text((unsigned long)ip) && 650 !is_bpf_text_address((unsigned long)ip)) 651 return -ENOTSUPP; 652 653 ret = gen_jump_or_nops(old_addr, ip, old_insns, is_call); 654 if (ret) 655 return ret; 656 657 if (memcmp(ip, old_insns, RV_FENTRY_NINSNS * 4)) 658 return -EFAULT; 659 660 ret = gen_jump_or_nops(new_addr, ip, new_insns, is_call); 661 if (ret) 662 return ret; 663 664 cpus_read_lock(); 665 mutex_lock(&text_mutex); 666 if (memcmp(ip, new_insns, RV_FENTRY_NINSNS * 4)) 667 ret = patch_text(ip, new_insns, RV_FENTRY_NINSNS); 668 mutex_unlock(&text_mutex); 669 cpus_read_unlock(); 670 671 return ret; 672 } 673 674 static void store_args(int nregs, int args_off, struct rv_jit_context *ctx) 675 { 676 int i; 677 678 for (i = 0; i < nregs; i++) { 679 emit_sd(RV_REG_FP, -args_off, RV_REG_A0 + i, ctx); 680 args_off -= 8; 681 } 682 } 683 684 static void restore_args(int nregs, int args_off, struct rv_jit_context *ctx) 685 { 686 int i; 687 688 for (i = 0; i < nregs; i++) { 689 emit_ld(RV_REG_A0 + i, -args_off, RV_REG_FP, ctx); 690 args_off -= 8; 691 } 692 } 693 694 static int invoke_bpf_prog(struct bpf_tramp_link *l, int args_off, int retval_off, 695 int run_ctx_off, bool save_ret, struct rv_jit_context *ctx) 696 { 697 int ret, branch_off; 698 struct bpf_prog *p = l->link.prog; 699 int cookie_off = offsetof(struct bpf_tramp_run_ctx, bpf_cookie); 700 701 if (l->cookie) { 702 emit_imm(RV_REG_T1, l->cookie, ctx); 703 emit_sd(RV_REG_FP, -run_ctx_off + cookie_off, RV_REG_T1, ctx); 704 } else { 705 emit_sd(RV_REG_FP, -run_ctx_off + cookie_off, RV_REG_ZERO, ctx); 706 } 707 708 /* arg1: prog */ 709 emit_imm(RV_REG_A0, (const s64)p, ctx); 710 /* arg2: &run_ctx */ 711 emit_addi(RV_REG_A1, RV_REG_FP, -run_ctx_off, ctx); 712 ret = emit_call((const u64)bpf_trampoline_enter(p), true, ctx); 713 if (ret) 714 return ret; 715 716 /* if (__bpf_prog_enter(prog) == 0) 717 * goto skip_exec_of_prog; 718 */ 719 branch_off = ctx->ninsns; 720 /* nop reserved for conditional jump */ 721 emit(rv_nop(), ctx); 722 723 /* store prog start time */ 724 emit_mv(RV_REG_S1, RV_REG_A0, ctx); 725 726 /* arg1: &args_off */ 727 emit_addi(RV_REG_A0, RV_REG_FP, -args_off, ctx); 728 if (!p->jited) 729 /* arg2: progs[i]->insnsi for interpreter */ 730 emit_imm(RV_REG_A1, (const s64)p->insnsi, ctx); 731 ret = emit_call((const u64)p->bpf_func, true, ctx); 732 if (ret) 733 return ret; 734 735 if (save_ret) 736 emit_sd(RV_REG_FP, -retval_off, regmap[BPF_REG_0], ctx); 737 738 /* update branch with beqz */ 739 if (ctx->insns) { 740 int offset = ninsns_rvoff(ctx->ninsns - branch_off); 741 u32 insn = rv_beq(RV_REG_A0, RV_REG_ZERO, offset >> 1); 742 *(u32 *)(ctx->insns + branch_off) = insn; 743 } 744 745 /* arg1: prog */ 746 emit_imm(RV_REG_A0, (const s64)p, ctx); 747 /* arg2: prog start time */ 748 emit_mv(RV_REG_A1, RV_REG_S1, ctx); 749 /* arg3: &run_ctx */ 750 emit_addi(RV_REG_A2, RV_REG_FP, -run_ctx_off, ctx); 751 ret = emit_call((const u64)bpf_trampoline_exit(p), true, ctx); 752 753 return ret; 754 } 755 756 static int __arch_prepare_bpf_trampoline(struct bpf_tramp_image *im, 757 const struct btf_func_model *m, 758 struct bpf_tramp_links *tlinks, 759 void *func_addr, u32 flags, 760 struct rv_jit_context *ctx) 761 { 762 int i, ret, offset; 763 int *branches_off = NULL; 764 int stack_size = 0, nregs = m->nr_args; 765 int retval_off, args_off, nregs_off, ip_off, run_ctx_off, sreg_off; 766 struct bpf_tramp_links *fentry = &tlinks[BPF_TRAMP_FENTRY]; 767 struct bpf_tramp_links *fexit = &tlinks[BPF_TRAMP_FEXIT]; 768 struct bpf_tramp_links *fmod_ret = &tlinks[BPF_TRAMP_MODIFY_RETURN]; 769 void *orig_call = func_addr; 770 bool save_ret; 771 u32 insn; 772 773 /* Two types of generated trampoline stack layout: 774 * 775 * 1. trampoline called from function entry 776 * -------------------------------------- 777 * FP + 8 [ RA to parent func ] return address to parent 778 * function 779 * FP + 0 [ FP of parent func ] frame pointer of parent 780 * function 781 * FP - 8 [ T0 to traced func ] return address of traced 782 * function 783 * FP - 16 [ FP of traced func ] frame pointer of traced 784 * function 785 * -------------------------------------- 786 * 787 * 2. trampoline called directly 788 * -------------------------------------- 789 * FP - 8 [ RA to caller func ] return address to caller 790 * function 791 * FP - 16 [ FP of caller func ] frame pointer of caller 792 * function 793 * -------------------------------------- 794 * 795 * FP - retval_off [ return value ] BPF_TRAMP_F_CALL_ORIG or 796 * BPF_TRAMP_F_RET_FENTRY_RET 797 * [ argN ] 798 * [ ... ] 799 * FP - args_off [ arg1 ] 800 * 801 * FP - nregs_off [ regs count ] 802 * 803 * FP - ip_off [ traced func ] BPF_TRAMP_F_IP_ARG 804 * 805 * FP - run_ctx_off [ bpf_tramp_run_ctx ] 806 * 807 * FP - sreg_off [ callee saved reg ] 808 * 809 * [ pads ] pads for 16 bytes alignment 810 */ 811 812 if (flags & (BPF_TRAMP_F_ORIG_STACK | BPF_TRAMP_F_SHARE_IPMODIFY)) 813 return -ENOTSUPP; 814 815 /* extra regiters for struct arguments */ 816 for (i = 0; i < m->nr_args; i++) 817 if (m->arg_flags[i] & BTF_FMODEL_STRUCT_ARG) 818 nregs += round_up(m->arg_size[i], 8) / 8 - 1; 819 820 /* 8 arguments passed by registers */ 821 if (nregs > 8) 822 return -ENOTSUPP; 823 824 /* room of trampoline frame to store return address and frame pointer */ 825 stack_size += 16; 826 827 save_ret = flags & (BPF_TRAMP_F_CALL_ORIG | BPF_TRAMP_F_RET_FENTRY_RET); 828 if (save_ret) { 829 stack_size += 8; 830 retval_off = stack_size; 831 } 832 833 stack_size += nregs * 8; 834 args_off = stack_size; 835 836 stack_size += 8; 837 nregs_off = stack_size; 838 839 if (flags & BPF_TRAMP_F_IP_ARG) { 840 stack_size += 8; 841 ip_off = stack_size; 842 } 843 844 stack_size += round_up(sizeof(struct bpf_tramp_run_ctx), 8); 845 run_ctx_off = stack_size; 846 847 stack_size += 8; 848 sreg_off = stack_size; 849 850 stack_size = round_up(stack_size, 16); 851 852 if (func_addr) { 853 /* For the trampoline called from function entry, 854 * the frame of traced function and the frame of 855 * trampoline need to be considered. 856 */ 857 emit_addi(RV_REG_SP, RV_REG_SP, -16, ctx); 858 emit_sd(RV_REG_SP, 8, RV_REG_RA, ctx); 859 emit_sd(RV_REG_SP, 0, RV_REG_FP, ctx); 860 emit_addi(RV_REG_FP, RV_REG_SP, 16, ctx); 861 862 emit_addi(RV_REG_SP, RV_REG_SP, -stack_size, ctx); 863 emit_sd(RV_REG_SP, stack_size - 8, RV_REG_T0, ctx); 864 emit_sd(RV_REG_SP, stack_size - 16, RV_REG_FP, ctx); 865 emit_addi(RV_REG_FP, RV_REG_SP, stack_size, ctx); 866 } else { 867 /* For the trampoline called directly, just handle 868 * the frame of trampoline. 869 */ 870 emit_addi(RV_REG_SP, RV_REG_SP, -stack_size, ctx); 871 emit_sd(RV_REG_SP, stack_size - 8, RV_REG_RA, ctx); 872 emit_sd(RV_REG_SP, stack_size - 16, RV_REG_FP, ctx); 873 emit_addi(RV_REG_FP, RV_REG_SP, stack_size, ctx); 874 } 875 876 /* callee saved register S1 to pass start time */ 877 emit_sd(RV_REG_FP, -sreg_off, RV_REG_S1, ctx); 878 879 /* store ip address of the traced function */ 880 if (flags & BPF_TRAMP_F_IP_ARG) { 881 emit_imm(RV_REG_T1, (const s64)func_addr, ctx); 882 emit_sd(RV_REG_FP, -ip_off, RV_REG_T1, ctx); 883 } 884 885 emit_li(RV_REG_T1, nregs, ctx); 886 emit_sd(RV_REG_FP, -nregs_off, RV_REG_T1, ctx); 887 888 store_args(nregs, args_off, ctx); 889 890 /* skip to actual body of traced function */ 891 if (flags & BPF_TRAMP_F_SKIP_FRAME) 892 orig_call += RV_FENTRY_NINSNS * 4; 893 894 if (flags & BPF_TRAMP_F_CALL_ORIG) { 895 emit_imm(RV_REG_A0, (const s64)im, ctx); 896 ret = emit_call((const u64)__bpf_tramp_enter, true, ctx); 897 if (ret) 898 return ret; 899 } 900 901 for (i = 0; i < fentry->nr_links; i++) { 902 ret = invoke_bpf_prog(fentry->links[i], args_off, retval_off, run_ctx_off, 903 flags & BPF_TRAMP_F_RET_FENTRY_RET, ctx); 904 if (ret) 905 return ret; 906 } 907 908 if (fmod_ret->nr_links) { 909 branches_off = kcalloc(fmod_ret->nr_links, sizeof(int), GFP_KERNEL); 910 if (!branches_off) 911 return -ENOMEM; 912 913 /* cleanup to avoid garbage return value confusion */ 914 emit_sd(RV_REG_FP, -retval_off, RV_REG_ZERO, ctx); 915 for (i = 0; i < fmod_ret->nr_links; i++) { 916 ret = invoke_bpf_prog(fmod_ret->links[i], args_off, retval_off, 917 run_ctx_off, true, ctx); 918 if (ret) 919 goto out; 920 emit_ld(RV_REG_T1, -retval_off, RV_REG_FP, ctx); 921 branches_off[i] = ctx->ninsns; 922 /* nop reserved for conditional jump */ 923 emit(rv_nop(), ctx); 924 } 925 } 926 927 if (flags & BPF_TRAMP_F_CALL_ORIG) { 928 restore_args(nregs, args_off, ctx); 929 ret = emit_call((const u64)orig_call, true, ctx); 930 if (ret) 931 goto out; 932 emit_sd(RV_REG_FP, -retval_off, RV_REG_A0, ctx); 933 im->ip_after_call = ctx->insns + ctx->ninsns; 934 /* 2 nops reserved for auipc+jalr pair */ 935 emit(rv_nop(), ctx); 936 emit(rv_nop(), ctx); 937 } 938 939 /* update branches saved in invoke_bpf_mod_ret with bnez */ 940 for (i = 0; ctx->insns && i < fmod_ret->nr_links; i++) { 941 offset = ninsns_rvoff(ctx->ninsns - branches_off[i]); 942 insn = rv_bne(RV_REG_T1, RV_REG_ZERO, offset >> 1); 943 *(u32 *)(ctx->insns + branches_off[i]) = insn; 944 } 945 946 for (i = 0; i < fexit->nr_links; i++) { 947 ret = invoke_bpf_prog(fexit->links[i], args_off, retval_off, 948 run_ctx_off, false, ctx); 949 if (ret) 950 goto out; 951 } 952 953 if (flags & BPF_TRAMP_F_CALL_ORIG) { 954 im->ip_epilogue = ctx->insns + ctx->ninsns; 955 emit_imm(RV_REG_A0, (const s64)im, ctx); 956 ret = emit_call((const u64)__bpf_tramp_exit, true, ctx); 957 if (ret) 958 goto out; 959 } 960 961 if (flags & BPF_TRAMP_F_RESTORE_REGS) 962 restore_args(nregs, args_off, ctx); 963 964 if (save_ret) 965 emit_ld(RV_REG_A0, -retval_off, RV_REG_FP, ctx); 966 967 emit_ld(RV_REG_S1, -sreg_off, RV_REG_FP, ctx); 968 969 if (func_addr) { 970 /* trampoline called from function entry */ 971 emit_ld(RV_REG_T0, stack_size - 8, RV_REG_SP, ctx); 972 emit_ld(RV_REG_FP, stack_size - 16, RV_REG_SP, ctx); 973 emit_addi(RV_REG_SP, RV_REG_SP, stack_size, ctx); 974 975 emit_ld(RV_REG_RA, 8, RV_REG_SP, ctx); 976 emit_ld(RV_REG_FP, 0, RV_REG_SP, ctx); 977 emit_addi(RV_REG_SP, RV_REG_SP, 16, ctx); 978 979 if (flags & BPF_TRAMP_F_SKIP_FRAME) 980 /* return to parent function */ 981 emit_jalr(RV_REG_ZERO, RV_REG_RA, 0, ctx); 982 else 983 /* return to traced function */ 984 emit_jalr(RV_REG_ZERO, RV_REG_T0, 0, ctx); 985 } else { 986 /* trampoline called directly */ 987 emit_ld(RV_REG_RA, stack_size - 8, RV_REG_SP, ctx); 988 emit_ld(RV_REG_FP, stack_size - 16, RV_REG_SP, ctx); 989 emit_addi(RV_REG_SP, RV_REG_SP, stack_size, ctx); 990 991 emit_jalr(RV_REG_ZERO, RV_REG_RA, 0, ctx); 992 } 993 994 ret = ctx->ninsns; 995 out: 996 kfree(branches_off); 997 return ret; 998 } 999 1000 int arch_prepare_bpf_trampoline(struct bpf_tramp_image *im, void *image, 1001 void *image_end, const struct btf_func_model *m, 1002 u32 flags, struct bpf_tramp_links *tlinks, 1003 void *func_addr) 1004 { 1005 int ret; 1006 struct rv_jit_context ctx; 1007 1008 ctx.ninsns = 0; 1009 ctx.insns = NULL; 1010 ret = __arch_prepare_bpf_trampoline(im, m, tlinks, func_addr, flags, &ctx); 1011 if (ret < 0) 1012 return ret; 1013 1014 if (ninsns_rvoff(ret) > (long)image_end - (long)image) 1015 return -EFBIG; 1016 1017 ctx.ninsns = 0; 1018 ctx.insns = image; 1019 ret = __arch_prepare_bpf_trampoline(im, m, tlinks, func_addr, flags, &ctx); 1020 if (ret < 0) 1021 return ret; 1022 1023 bpf_flush_icache(ctx.insns, ctx.insns + ctx.ninsns); 1024 1025 return ninsns_rvoff(ret); 1026 } 1027 1028 int bpf_jit_emit_insn(const struct bpf_insn *insn, struct rv_jit_context *ctx, 1029 bool extra_pass) 1030 { 1031 bool is64 = BPF_CLASS(insn->code) == BPF_ALU64 || 1032 BPF_CLASS(insn->code) == BPF_JMP; 1033 int s, e, rvoff, ret, i = insn - ctx->prog->insnsi; 1034 struct bpf_prog_aux *aux = ctx->prog->aux; 1035 u8 rd = -1, rs = -1, code = insn->code; 1036 s16 off = insn->off; 1037 s32 imm = insn->imm; 1038 1039 init_regs(&rd, &rs, insn, ctx); 1040 1041 switch (code) { 1042 /* dst = src */ 1043 case BPF_ALU | BPF_MOV | BPF_X: 1044 case BPF_ALU64 | BPF_MOV | BPF_X: 1045 if (imm == 1) { 1046 /* Special mov32 for zext */ 1047 emit_zext_32(rd, ctx); 1048 break; 1049 } 1050 switch (insn->off) { 1051 case 0: 1052 emit_mv(rd, rs, ctx); 1053 break; 1054 case 8: 1055 case 16: 1056 emit_slli(RV_REG_T1, rs, 64 - insn->off, ctx); 1057 emit_srai(rd, RV_REG_T1, 64 - insn->off, ctx); 1058 break; 1059 case 32: 1060 emit_addiw(rd, rs, 0, ctx); 1061 break; 1062 } 1063 if (!is64 && !aux->verifier_zext) 1064 emit_zext_32(rd, ctx); 1065 break; 1066 1067 /* dst = dst OP src */ 1068 case BPF_ALU | BPF_ADD | BPF_X: 1069 case BPF_ALU64 | BPF_ADD | BPF_X: 1070 emit_add(rd, rd, rs, ctx); 1071 if (!is64 && !aux->verifier_zext) 1072 emit_zext_32(rd, ctx); 1073 break; 1074 case BPF_ALU | BPF_SUB | BPF_X: 1075 case BPF_ALU64 | BPF_SUB | BPF_X: 1076 if (is64) 1077 emit_sub(rd, rd, rs, ctx); 1078 else 1079 emit_subw(rd, rd, rs, ctx); 1080 1081 if (!is64 && !aux->verifier_zext) 1082 emit_zext_32(rd, ctx); 1083 break; 1084 case BPF_ALU | BPF_AND | BPF_X: 1085 case BPF_ALU64 | BPF_AND | BPF_X: 1086 emit_and(rd, rd, rs, ctx); 1087 if (!is64 && !aux->verifier_zext) 1088 emit_zext_32(rd, ctx); 1089 break; 1090 case BPF_ALU | BPF_OR | BPF_X: 1091 case BPF_ALU64 | BPF_OR | BPF_X: 1092 emit_or(rd, rd, rs, ctx); 1093 if (!is64 && !aux->verifier_zext) 1094 emit_zext_32(rd, ctx); 1095 break; 1096 case BPF_ALU | BPF_XOR | BPF_X: 1097 case BPF_ALU64 | BPF_XOR | BPF_X: 1098 emit_xor(rd, rd, rs, ctx); 1099 if (!is64 && !aux->verifier_zext) 1100 emit_zext_32(rd, ctx); 1101 break; 1102 case BPF_ALU | BPF_MUL | BPF_X: 1103 case BPF_ALU64 | BPF_MUL | BPF_X: 1104 emit(is64 ? rv_mul(rd, rd, rs) : rv_mulw(rd, rd, rs), ctx); 1105 if (!is64 && !aux->verifier_zext) 1106 emit_zext_32(rd, ctx); 1107 break; 1108 case BPF_ALU | BPF_DIV | BPF_X: 1109 case BPF_ALU64 | BPF_DIV | BPF_X: 1110 emit(is64 ? rv_divu(rd, rd, rs) : rv_divuw(rd, rd, rs), ctx); 1111 if (!is64 && !aux->verifier_zext) 1112 emit_zext_32(rd, ctx); 1113 break; 1114 case BPF_ALU | BPF_MOD | BPF_X: 1115 case BPF_ALU64 | BPF_MOD | BPF_X: 1116 emit(is64 ? rv_remu(rd, rd, rs) : rv_remuw(rd, rd, rs), ctx); 1117 if (!is64 && !aux->verifier_zext) 1118 emit_zext_32(rd, ctx); 1119 break; 1120 case BPF_ALU | BPF_LSH | BPF_X: 1121 case BPF_ALU64 | BPF_LSH | BPF_X: 1122 emit(is64 ? rv_sll(rd, rd, rs) : rv_sllw(rd, rd, rs), ctx); 1123 if (!is64 && !aux->verifier_zext) 1124 emit_zext_32(rd, ctx); 1125 break; 1126 case BPF_ALU | BPF_RSH | BPF_X: 1127 case BPF_ALU64 | BPF_RSH | BPF_X: 1128 emit(is64 ? rv_srl(rd, rd, rs) : rv_srlw(rd, rd, rs), ctx); 1129 if (!is64 && !aux->verifier_zext) 1130 emit_zext_32(rd, ctx); 1131 break; 1132 case BPF_ALU | BPF_ARSH | BPF_X: 1133 case BPF_ALU64 | BPF_ARSH | BPF_X: 1134 emit(is64 ? rv_sra(rd, rd, rs) : rv_sraw(rd, rd, rs), ctx); 1135 if (!is64 && !aux->verifier_zext) 1136 emit_zext_32(rd, ctx); 1137 break; 1138 1139 /* dst = -dst */ 1140 case BPF_ALU | BPF_NEG: 1141 case BPF_ALU64 | BPF_NEG: 1142 emit_sub(rd, RV_REG_ZERO, rd, ctx); 1143 if (!is64 && !aux->verifier_zext) 1144 emit_zext_32(rd, ctx); 1145 break; 1146 1147 /* dst = BSWAP##imm(dst) */ 1148 case BPF_ALU | BPF_END | BPF_FROM_LE: 1149 switch (imm) { 1150 case 16: 1151 emit_slli(rd, rd, 48, ctx); 1152 emit_srli(rd, rd, 48, ctx); 1153 break; 1154 case 32: 1155 if (!aux->verifier_zext) 1156 emit_zext_32(rd, ctx); 1157 break; 1158 case 64: 1159 /* Do nothing */ 1160 break; 1161 } 1162 break; 1163 1164 case BPF_ALU | BPF_END | BPF_FROM_BE: 1165 emit_li(RV_REG_T2, 0, ctx); 1166 1167 emit_andi(RV_REG_T1, rd, 0xff, ctx); 1168 emit_add(RV_REG_T2, RV_REG_T2, RV_REG_T1, ctx); 1169 emit_slli(RV_REG_T2, RV_REG_T2, 8, ctx); 1170 emit_srli(rd, rd, 8, ctx); 1171 if (imm == 16) 1172 goto out_be; 1173 1174 emit_andi(RV_REG_T1, rd, 0xff, ctx); 1175 emit_add(RV_REG_T2, RV_REG_T2, RV_REG_T1, ctx); 1176 emit_slli(RV_REG_T2, RV_REG_T2, 8, ctx); 1177 emit_srli(rd, rd, 8, ctx); 1178 1179 emit_andi(RV_REG_T1, rd, 0xff, ctx); 1180 emit_add(RV_REG_T2, RV_REG_T2, RV_REG_T1, ctx); 1181 emit_slli(RV_REG_T2, RV_REG_T2, 8, ctx); 1182 emit_srli(rd, rd, 8, ctx); 1183 if (imm == 32) 1184 goto out_be; 1185 1186 emit_andi(RV_REG_T1, rd, 0xff, ctx); 1187 emit_add(RV_REG_T2, RV_REG_T2, RV_REG_T1, ctx); 1188 emit_slli(RV_REG_T2, RV_REG_T2, 8, ctx); 1189 emit_srli(rd, rd, 8, ctx); 1190 1191 emit_andi(RV_REG_T1, rd, 0xff, ctx); 1192 emit_add(RV_REG_T2, RV_REG_T2, RV_REG_T1, ctx); 1193 emit_slli(RV_REG_T2, RV_REG_T2, 8, ctx); 1194 emit_srli(rd, rd, 8, ctx); 1195 1196 emit_andi(RV_REG_T1, rd, 0xff, ctx); 1197 emit_add(RV_REG_T2, RV_REG_T2, RV_REG_T1, ctx); 1198 emit_slli(RV_REG_T2, RV_REG_T2, 8, ctx); 1199 emit_srli(rd, rd, 8, ctx); 1200 1201 emit_andi(RV_REG_T1, rd, 0xff, ctx); 1202 emit_add(RV_REG_T2, RV_REG_T2, RV_REG_T1, ctx); 1203 emit_slli(RV_REG_T2, RV_REG_T2, 8, ctx); 1204 emit_srli(rd, rd, 8, ctx); 1205 out_be: 1206 emit_andi(RV_REG_T1, rd, 0xff, ctx); 1207 emit_add(RV_REG_T2, RV_REG_T2, RV_REG_T1, ctx); 1208 1209 emit_mv(rd, RV_REG_T2, ctx); 1210 break; 1211 1212 /* dst = imm */ 1213 case BPF_ALU | BPF_MOV | BPF_K: 1214 case BPF_ALU64 | BPF_MOV | BPF_K: 1215 emit_imm(rd, imm, ctx); 1216 if (!is64 && !aux->verifier_zext) 1217 emit_zext_32(rd, ctx); 1218 break; 1219 1220 /* dst = dst OP imm */ 1221 case BPF_ALU | BPF_ADD | BPF_K: 1222 case BPF_ALU64 | BPF_ADD | BPF_K: 1223 if (is_12b_int(imm)) { 1224 emit_addi(rd, rd, imm, ctx); 1225 } else { 1226 emit_imm(RV_REG_T1, imm, ctx); 1227 emit_add(rd, rd, RV_REG_T1, ctx); 1228 } 1229 if (!is64 && !aux->verifier_zext) 1230 emit_zext_32(rd, ctx); 1231 break; 1232 case BPF_ALU | BPF_SUB | BPF_K: 1233 case BPF_ALU64 | BPF_SUB | BPF_K: 1234 if (is_12b_int(-imm)) { 1235 emit_addi(rd, rd, -imm, ctx); 1236 } else { 1237 emit_imm(RV_REG_T1, imm, ctx); 1238 emit_sub(rd, rd, RV_REG_T1, ctx); 1239 } 1240 if (!is64 && !aux->verifier_zext) 1241 emit_zext_32(rd, ctx); 1242 break; 1243 case BPF_ALU | BPF_AND | BPF_K: 1244 case BPF_ALU64 | BPF_AND | BPF_K: 1245 if (is_12b_int(imm)) { 1246 emit_andi(rd, rd, imm, ctx); 1247 } else { 1248 emit_imm(RV_REG_T1, imm, ctx); 1249 emit_and(rd, rd, RV_REG_T1, ctx); 1250 } 1251 if (!is64 && !aux->verifier_zext) 1252 emit_zext_32(rd, ctx); 1253 break; 1254 case BPF_ALU | BPF_OR | BPF_K: 1255 case BPF_ALU64 | BPF_OR | BPF_K: 1256 if (is_12b_int(imm)) { 1257 emit(rv_ori(rd, rd, imm), ctx); 1258 } else { 1259 emit_imm(RV_REG_T1, imm, ctx); 1260 emit_or(rd, rd, RV_REG_T1, ctx); 1261 } 1262 if (!is64 && !aux->verifier_zext) 1263 emit_zext_32(rd, ctx); 1264 break; 1265 case BPF_ALU | BPF_XOR | BPF_K: 1266 case BPF_ALU64 | BPF_XOR | BPF_K: 1267 if (is_12b_int(imm)) { 1268 emit(rv_xori(rd, rd, imm), ctx); 1269 } else { 1270 emit_imm(RV_REG_T1, imm, ctx); 1271 emit_xor(rd, rd, RV_REG_T1, ctx); 1272 } 1273 if (!is64 && !aux->verifier_zext) 1274 emit_zext_32(rd, ctx); 1275 break; 1276 case BPF_ALU | BPF_MUL | BPF_K: 1277 case BPF_ALU64 | BPF_MUL | BPF_K: 1278 emit_imm(RV_REG_T1, imm, ctx); 1279 emit(is64 ? rv_mul(rd, rd, RV_REG_T1) : 1280 rv_mulw(rd, rd, RV_REG_T1), ctx); 1281 if (!is64 && !aux->verifier_zext) 1282 emit_zext_32(rd, ctx); 1283 break; 1284 case BPF_ALU | BPF_DIV | BPF_K: 1285 case BPF_ALU64 | BPF_DIV | BPF_K: 1286 emit_imm(RV_REG_T1, imm, ctx); 1287 emit(is64 ? rv_divu(rd, rd, RV_REG_T1) : 1288 rv_divuw(rd, rd, RV_REG_T1), ctx); 1289 if (!is64 && !aux->verifier_zext) 1290 emit_zext_32(rd, ctx); 1291 break; 1292 case BPF_ALU | BPF_MOD | BPF_K: 1293 case BPF_ALU64 | BPF_MOD | BPF_K: 1294 emit_imm(RV_REG_T1, imm, ctx); 1295 emit(is64 ? rv_remu(rd, rd, RV_REG_T1) : 1296 rv_remuw(rd, rd, RV_REG_T1), ctx); 1297 if (!is64 && !aux->verifier_zext) 1298 emit_zext_32(rd, ctx); 1299 break; 1300 case BPF_ALU | BPF_LSH | BPF_K: 1301 case BPF_ALU64 | BPF_LSH | BPF_K: 1302 emit_slli(rd, rd, imm, ctx); 1303 1304 if (!is64 && !aux->verifier_zext) 1305 emit_zext_32(rd, ctx); 1306 break; 1307 case BPF_ALU | BPF_RSH | BPF_K: 1308 case BPF_ALU64 | BPF_RSH | BPF_K: 1309 if (is64) 1310 emit_srli(rd, rd, imm, ctx); 1311 else 1312 emit(rv_srliw(rd, rd, imm), ctx); 1313 1314 if (!is64 && !aux->verifier_zext) 1315 emit_zext_32(rd, ctx); 1316 break; 1317 case BPF_ALU | BPF_ARSH | BPF_K: 1318 case BPF_ALU64 | BPF_ARSH | BPF_K: 1319 if (is64) 1320 emit_srai(rd, rd, imm, ctx); 1321 else 1322 emit(rv_sraiw(rd, rd, imm), ctx); 1323 1324 if (!is64 && !aux->verifier_zext) 1325 emit_zext_32(rd, ctx); 1326 break; 1327 1328 /* JUMP off */ 1329 case BPF_JMP | BPF_JA: 1330 case BPF_JMP32 | BPF_JA: 1331 if (BPF_CLASS(code) == BPF_JMP) 1332 rvoff = rv_offset(i, off, ctx); 1333 else 1334 rvoff = rv_offset(i, imm, ctx); 1335 ret = emit_jump_and_link(RV_REG_ZERO, rvoff, true, ctx); 1336 if (ret) 1337 return ret; 1338 break; 1339 1340 /* IF (dst COND src) JUMP off */ 1341 case BPF_JMP | BPF_JEQ | BPF_X: 1342 case BPF_JMP32 | BPF_JEQ | BPF_X: 1343 case BPF_JMP | BPF_JGT | BPF_X: 1344 case BPF_JMP32 | BPF_JGT | BPF_X: 1345 case BPF_JMP | BPF_JLT | BPF_X: 1346 case BPF_JMP32 | BPF_JLT | BPF_X: 1347 case BPF_JMP | BPF_JGE | BPF_X: 1348 case BPF_JMP32 | BPF_JGE | BPF_X: 1349 case BPF_JMP | BPF_JLE | BPF_X: 1350 case BPF_JMP32 | BPF_JLE | BPF_X: 1351 case BPF_JMP | BPF_JNE | BPF_X: 1352 case BPF_JMP32 | BPF_JNE | BPF_X: 1353 case BPF_JMP | BPF_JSGT | BPF_X: 1354 case BPF_JMP32 | BPF_JSGT | BPF_X: 1355 case BPF_JMP | BPF_JSLT | BPF_X: 1356 case BPF_JMP32 | BPF_JSLT | BPF_X: 1357 case BPF_JMP | BPF_JSGE | BPF_X: 1358 case BPF_JMP32 | BPF_JSGE | BPF_X: 1359 case BPF_JMP | BPF_JSLE | BPF_X: 1360 case BPF_JMP32 | BPF_JSLE | BPF_X: 1361 case BPF_JMP | BPF_JSET | BPF_X: 1362 case BPF_JMP32 | BPF_JSET | BPF_X: 1363 rvoff = rv_offset(i, off, ctx); 1364 if (!is64) { 1365 s = ctx->ninsns; 1366 if (is_signed_bpf_cond(BPF_OP(code))) 1367 emit_sext_32_rd_rs(&rd, &rs, ctx); 1368 else 1369 emit_zext_32_rd_rs(&rd, &rs, ctx); 1370 e = ctx->ninsns; 1371 1372 /* Adjust for extra insns */ 1373 rvoff -= ninsns_rvoff(e - s); 1374 } 1375 1376 if (BPF_OP(code) == BPF_JSET) { 1377 /* Adjust for and */ 1378 rvoff -= 4; 1379 emit_and(RV_REG_T1, rd, rs, ctx); 1380 emit_branch(BPF_JNE, RV_REG_T1, RV_REG_ZERO, rvoff, 1381 ctx); 1382 } else { 1383 emit_branch(BPF_OP(code), rd, rs, rvoff, ctx); 1384 } 1385 break; 1386 1387 /* IF (dst COND imm) JUMP off */ 1388 case BPF_JMP | BPF_JEQ | BPF_K: 1389 case BPF_JMP32 | BPF_JEQ | BPF_K: 1390 case BPF_JMP | BPF_JGT | BPF_K: 1391 case BPF_JMP32 | BPF_JGT | BPF_K: 1392 case BPF_JMP | BPF_JLT | BPF_K: 1393 case BPF_JMP32 | BPF_JLT | BPF_K: 1394 case BPF_JMP | BPF_JGE | BPF_K: 1395 case BPF_JMP32 | BPF_JGE | BPF_K: 1396 case BPF_JMP | BPF_JLE | BPF_K: 1397 case BPF_JMP32 | BPF_JLE | BPF_K: 1398 case BPF_JMP | BPF_JNE | BPF_K: 1399 case BPF_JMP32 | BPF_JNE | BPF_K: 1400 case BPF_JMP | BPF_JSGT | BPF_K: 1401 case BPF_JMP32 | BPF_JSGT | BPF_K: 1402 case BPF_JMP | BPF_JSLT | BPF_K: 1403 case BPF_JMP32 | BPF_JSLT | BPF_K: 1404 case BPF_JMP | BPF_JSGE | BPF_K: 1405 case BPF_JMP32 | BPF_JSGE | BPF_K: 1406 case BPF_JMP | BPF_JSLE | BPF_K: 1407 case BPF_JMP32 | BPF_JSLE | BPF_K: 1408 rvoff = rv_offset(i, off, ctx); 1409 s = ctx->ninsns; 1410 if (imm) { 1411 emit_imm(RV_REG_T1, imm, ctx); 1412 rs = RV_REG_T1; 1413 } else { 1414 /* If imm is 0, simply use zero register. */ 1415 rs = RV_REG_ZERO; 1416 } 1417 if (!is64) { 1418 if (is_signed_bpf_cond(BPF_OP(code))) 1419 emit_sext_32_rd(&rd, ctx); 1420 else 1421 emit_zext_32_rd_t1(&rd, ctx); 1422 } 1423 e = ctx->ninsns; 1424 1425 /* Adjust for extra insns */ 1426 rvoff -= ninsns_rvoff(e - s); 1427 emit_branch(BPF_OP(code), rd, rs, rvoff, ctx); 1428 break; 1429 1430 case BPF_JMP | BPF_JSET | BPF_K: 1431 case BPF_JMP32 | BPF_JSET | BPF_K: 1432 rvoff = rv_offset(i, off, ctx); 1433 s = ctx->ninsns; 1434 if (is_12b_int(imm)) { 1435 emit_andi(RV_REG_T1, rd, imm, ctx); 1436 } else { 1437 emit_imm(RV_REG_T1, imm, ctx); 1438 emit_and(RV_REG_T1, rd, RV_REG_T1, ctx); 1439 } 1440 /* For jset32, we should clear the upper 32 bits of t1, but 1441 * sign-extension is sufficient here and saves one instruction, 1442 * as t1 is used only in comparison against zero. 1443 */ 1444 if (!is64 && imm < 0) 1445 emit_addiw(RV_REG_T1, RV_REG_T1, 0, ctx); 1446 e = ctx->ninsns; 1447 rvoff -= ninsns_rvoff(e - s); 1448 emit_branch(BPF_JNE, RV_REG_T1, RV_REG_ZERO, rvoff, ctx); 1449 break; 1450 1451 /* function call */ 1452 case BPF_JMP | BPF_CALL: 1453 { 1454 bool fixed_addr; 1455 u64 addr; 1456 1457 mark_call(ctx); 1458 ret = bpf_jit_get_func_addr(ctx->prog, insn, extra_pass, 1459 &addr, &fixed_addr); 1460 if (ret < 0) 1461 return ret; 1462 1463 ret = emit_call(addr, fixed_addr, ctx); 1464 if (ret) 1465 return ret; 1466 1467 emit_mv(bpf_to_rv_reg(BPF_REG_0, ctx), RV_REG_A0, ctx); 1468 break; 1469 } 1470 /* tail call */ 1471 case BPF_JMP | BPF_TAIL_CALL: 1472 if (emit_bpf_tail_call(i, ctx)) 1473 return -1; 1474 break; 1475 1476 /* function return */ 1477 case BPF_JMP | BPF_EXIT: 1478 if (i == ctx->prog->len - 1) 1479 break; 1480 1481 rvoff = epilogue_offset(ctx); 1482 ret = emit_jump_and_link(RV_REG_ZERO, rvoff, true, ctx); 1483 if (ret) 1484 return ret; 1485 break; 1486 1487 /* dst = imm64 */ 1488 case BPF_LD | BPF_IMM | BPF_DW: 1489 { 1490 struct bpf_insn insn1 = insn[1]; 1491 u64 imm64; 1492 1493 imm64 = (u64)insn1.imm << 32 | (u32)imm; 1494 if (bpf_pseudo_func(insn)) { 1495 /* fixed-length insns for extra jit pass */ 1496 ret = emit_addr(rd, imm64, extra_pass, ctx); 1497 if (ret) 1498 return ret; 1499 } else { 1500 emit_imm(rd, imm64, ctx); 1501 } 1502 1503 return 1; 1504 } 1505 1506 /* LDX: dst = *(unsigned size *)(src + off) */ 1507 case BPF_LDX | BPF_MEM | BPF_B: 1508 case BPF_LDX | BPF_MEM | BPF_H: 1509 case BPF_LDX | BPF_MEM | BPF_W: 1510 case BPF_LDX | BPF_MEM | BPF_DW: 1511 case BPF_LDX | BPF_PROBE_MEM | BPF_B: 1512 case BPF_LDX | BPF_PROBE_MEM | BPF_H: 1513 case BPF_LDX | BPF_PROBE_MEM | BPF_W: 1514 case BPF_LDX | BPF_PROBE_MEM | BPF_DW: 1515 /* LDSX: dst = *(signed size *)(src + off) */ 1516 case BPF_LDX | BPF_MEMSX | BPF_B: 1517 case BPF_LDX | BPF_MEMSX | BPF_H: 1518 case BPF_LDX | BPF_MEMSX | BPF_W: 1519 case BPF_LDX | BPF_PROBE_MEMSX | BPF_B: 1520 case BPF_LDX | BPF_PROBE_MEMSX | BPF_H: 1521 case BPF_LDX | BPF_PROBE_MEMSX | BPF_W: 1522 { 1523 int insn_len, insns_start; 1524 bool sign_ext; 1525 1526 sign_ext = BPF_MODE(insn->code) == BPF_MEMSX || 1527 BPF_MODE(insn->code) == BPF_PROBE_MEMSX; 1528 1529 switch (BPF_SIZE(code)) { 1530 case BPF_B: 1531 if (is_12b_int(off)) { 1532 insns_start = ctx->ninsns; 1533 if (sign_ext) 1534 emit(rv_lb(rd, off, rs), ctx); 1535 else 1536 emit(rv_lbu(rd, off, rs), ctx); 1537 insn_len = ctx->ninsns - insns_start; 1538 break; 1539 } 1540 1541 emit_imm(RV_REG_T1, off, ctx); 1542 emit_add(RV_REG_T1, RV_REG_T1, rs, ctx); 1543 insns_start = ctx->ninsns; 1544 if (sign_ext) 1545 emit(rv_lb(rd, 0, RV_REG_T1), ctx); 1546 else 1547 emit(rv_lbu(rd, 0, RV_REG_T1), ctx); 1548 insn_len = ctx->ninsns - insns_start; 1549 break; 1550 case BPF_H: 1551 if (is_12b_int(off)) { 1552 insns_start = ctx->ninsns; 1553 if (sign_ext) 1554 emit(rv_lh(rd, off, rs), ctx); 1555 else 1556 emit(rv_lhu(rd, off, rs), ctx); 1557 insn_len = ctx->ninsns - insns_start; 1558 break; 1559 } 1560 1561 emit_imm(RV_REG_T1, off, ctx); 1562 emit_add(RV_REG_T1, RV_REG_T1, rs, ctx); 1563 insns_start = ctx->ninsns; 1564 if (sign_ext) 1565 emit(rv_lh(rd, 0, RV_REG_T1), ctx); 1566 else 1567 emit(rv_lhu(rd, 0, RV_REG_T1), ctx); 1568 insn_len = ctx->ninsns - insns_start; 1569 break; 1570 case BPF_W: 1571 if (is_12b_int(off)) { 1572 insns_start = ctx->ninsns; 1573 if (sign_ext) 1574 emit(rv_lw(rd, off, rs), ctx); 1575 else 1576 emit(rv_lwu(rd, off, rs), ctx); 1577 insn_len = ctx->ninsns - insns_start; 1578 break; 1579 } 1580 1581 emit_imm(RV_REG_T1, off, ctx); 1582 emit_add(RV_REG_T1, RV_REG_T1, rs, ctx); 1583 insns_start = ctx->ninsns; 1584 if (sign_ext) 1585 emit(rv_lw(rd, 0, RV_REG_T1), ctx); 1586 else 1587 emit(rv_lwu(rd, 0, RV_REG_T1), ctx); 1588 insn_len = ctx->ninsns - insns_start; 1589 break; 1590 case BPF_DW: 1591 if (is_12b_int(off)) { 1592 insns_start = ctx->ninsns; 1593 emit_ld(rd, off, rs, ctx); 1594 insn_len = ctx->ninsns - insns_start; 1595 break; 1596 } 1597 1598 emit_imm(RV_REG_T1, off, ctx); 1599 emit_add(RV_REG_T1, RV_REG_T1, rs, ctx); 1600 insns_start = ctx->ninsns; 1601 emit_ld(rd, 0, RV_REG_T1, ctx); 1602 insn_len = ctx->ninsns - insns_start; 1603 break; 1604 } 1605 1606 ret = add_exception_handler(insn, ctx, rd, insn_len); 1607 if (ret) 1608 return ret; 1609 1610 if (BPF_SIZE(code) != BPF_DW && insn_is_zext(&insn[1])) 1611 return 1; 1612 break; 1613 } 1614 /* speculation barrier */ 1615 case BPF_ST | BPF_NOSPEC: 1616 break; 1617 1618 /* ST: *(size *)(dst + off) = imm */ 1619 case BPF_ST | BPF_MEM | BPF_B: 1620 emit_imm(RV_REG_T1, imm, ctx); 1621 if (is_12b_int(off)) { 1622 emit(rv_sb(rd, off, RV_REG_T1), ctx); 1623 break; 1624 } 1625 1626 emit_imm(RV_REG_T2, off, ctx); 1627 emit_add(RV_REG_T2, RV_REG_T2, rd, ctx); 1628 emit(rv_sb(RV_REG_T2, 0, RV_REG_T1), ctx); 1629 break; 1630 1631 case BPF_ST | BPF_MEM | BPF_H: 1632 emit_imm(RV_REG_T1, imm, ctx); 1633 if (is_12b_int(off)) { 1634 emit(rv_sh(rd, off, RV_REG_T1), ctx); 1635 break; 1636 } 1637 1638 emit_imm(RV_REG_T2, off, ctx); 1639 emit_add(RV_REG_T2, RV_REG_T2, rd, ctx); 1640 emit(rv_sh(RV_REG_T2, 0, RV_REG_T1), ctx); 1641 break; 1642 case BPF_ST | BPF_MEM | BPF_W: 1643 emit_imm(RV_REG_T1, imm, ctx); 1644 if (is_12b_int(off)) { 1645 emit_sw(rd, off, RV_REG_T1, ctx); 1646 break; 1647 } 1648 1649 emit_imm(RV_REG_T2, off, ctx); 1650 emit_add(RV_REG_T2, RV_REG_T2, rd, ctx); 1651 emit_sw(RV_REG_T2, 0, RV_REG_T1, ctx); 1652 break; 1653 case BPF_ST | BPF_MEM | BPF_DW: 1654 emit_imm(RV_REG_T1, imm, ctx); 1655 if (is_12b_int(off)) { 1656 emit_sd(rd, off, RV_REG_T1, ctx); 1657 break; 1658 } 1659 1660 emit_imm(RV_REG_T2, off, ctx); 1661 emit_add(RV_REG_T2, RV_REG_T2, rd, ctx); 1662 emit_sd(RV_REG_T2, 0, RV_REG_T1, ctx); 1663 break; 1664 1665 /* STX: *(size *)(dst + off) = src */ 1666 case BPF_STX | BPF_MEM | BPF_B: 1667 if (is_12b_int(off)) { 1668 emit(rv_sb(rd, off, rs), ctx); 1669 break; 1670 } 1671 1672 emit_imm(RV_REG_T1, off, ctx); 1673 emit_add(RV_REG_T1, RV_REG_T1, rd, ctx); 1674 emit(rv_sb(RV_REG_T1, 0, rs), ctx); 1675 break; 1676 case BPF_STX | BPF_MEM | BPF_H: 1677 if (is_12b_int(off)) { 1678 emit(rv_sh(rd, off, rs), ctx); 1679 break; 1680 } 1681 1682 emit_imm(RV_REG_T1, off, ctx); 1683 emit_add(RV_REG_T1, RV_REG_T1, rd, ctx); 1684 emit(rv_sh(RV_REG_T1, 0, rs), ctx); 1685 break; 1686 case BPF_STX | BPF_MEM | BPF_W: 1687 if (is_12b_int(off)) { 1688 emit_sw(rd, off, rs, ctx); 1689 break; 1690 } 1691 1692 emit_imm(RV_REG_T1, off, ctx); 1693 emit_add(RV_REG_T1, RV_REG_T1, rd, ctx); 1694 emit_sw(RV_REG_T1, 0, rs, ctx); 1695 break; 1696 case BPF_STX | BPF_MEM | BPF_DW: 1697 if (is_12b_int(off)) { 1698 emit_sd(rd, off, rs, ctx); 1699 break; 1700 } 1701 1702 emit_imm(RV_REG_T1, off, ctx); 1703 emit_add(RV_REG_T1, RV_REG_T1, rd, ctx); 1704 emit_sd(RV_REG_T1, 0, rs, ctx); 1705 break; 1706 case BPF_STX | BPF_ATOMIC | BPF_W: 1707 case BPF_STX | BPF_ATOMIC | BPF_DW: 1708 emit_atomic(rd, rs, off, imm, 1709 BPF_SIZE(code) == BPF_DW, ctx); 1710 break; 1711 default: 1712 pr_err("bpf-jit: unknown opcode %02x\n", code); 1713 return -EINVAL; 1714 } 1715 1716 return 0; 1717 } 1718 1719 void bpf_jit_build_prologue(struct rv_jit_context *ctx) 1720 { 1721 int i, stack_adjust = 0, store_offset, bpf_stack_adjust; 1722 1723 bpf_stack_adjust = round_up(ctx->prog->aux->stack_depth, 16); 1724 if (bpf_stack_adjust) 1725 mark_fp(ctx); 1726 1727 if (seen_reg(RV_REG_RA, ctx)) 1728 stack_adjust += 8; 1729 stack_adjust += 8; /* RV_REG_FP */ 1730 if (seen_reg(RV_REG_S1, ctx)) 1731 stack_adjust += 8; 1732 if (seen_reg(RV_REG_S2, ctx)) 1733 stack_adjust += 8; 1734 if (seen_reg(RV_REG_S3, ctx)) 1735 stack_adjust += 8; 1736 if (seen_reg(RV_REG_S4, ctx)) 1737 stack_adjust += 8; 1738 if (seen_reg(RV_REG_S5, ctx)) 1739 stack_adjust += 8; 1740 if (seen_reg(RV_REG_S6, ctx)) 1741 stack_adjust += 8; 1742 1743 stack_adjust = round_up(stack_adjust, 16); 1744 stack_adjust += bpf_stack_adjust; 1745 1746 store_offset = stack_adjust - 8; 1747 1748 /* nops reserved for auipc+jalr pair */ 1749 for (i = 0; i < RV_FENTRY_NINSNS; i++) 1750 emit(rv_nop(), ctx); 1751 1752 /* First instruction is always setting the tail-call-counter 1753 * (TCC) register. This instruction is skipped for tail calls. 1754 * Force using a 4-byte (non-compressed) instruction. 1755 */ 1756 emit(rv_addi(RV_REG_TCC, RV_REG_ZERO, MAX_TAIL_CALL_CNT), ctx); 1757 1758 emit_addi(RV_REG_SP, RV_REG_SP, -stack_adjust, ctx); 1759 1760 if (seen_reg(RV_REG_RA, ctx)) { 1761 emit_sd(RV_REG_SP, store_offset, RV_REG_RA, ctx); 1762 store_offset -= 8; 1763 } 1764 emit_sd(RV_REG_SP, store_offset, RV_REG_FP, ctx); 1765 store_offset -= 8; 1766 if (seen_reg(RV_REG_S1, ctx)) { 1767 emit_sd(RV_REG_SP, store_offset, RV_REG_S1, ctx); 1768 store_offset -= 8; 1769 } 1770 if (seen_reg(RV_REG_S2, ctx)) { 1771 emit_sd(RV_REG_SP, store_offset, RV_REG_S2, ctx); 1772 store_offset -= 8; 1773 } 1774 if (seen_reg(RV_REG_S3, ctx)) { 1775 emit_sd(RV_REG_SP, store_offset, RV_REG_S3, ctx); 1776 store_offset -= 8; 1777 } 1778 if (seen_reg(RV_REG_S4, ctx)) { 1779 emit_sd(RV_REG_SP, store_offset, RV_REG_S4, ctx); 1780 store_offset -= 8; 1781 } 1782 if (seen_reg(RV_REG_S5, ctx)) { 1783 emit_sd(RV_REG_SP, store_offset, RV_REG_S5, ctx); 1784 store_offset -= 8; 1785 } 1786 if (seen_reg(RV_REG_S6, ctx)) { 1787 emit_sd(RV_REG_SP, store_offset, RV_REG_S6, ctx); 1788 store_offset -= 8; 1789 } 1790 1791 emit_addi(RV_REG_FP, RV_REG_SP, stack_adjust, ctx); 1792 1793 if (bpf_stack_adjust) 1794 emit_addi(RV_REG_S5, RV_REG_SP, bpf_stack_adjust, ctx); 1795 1796 /* Program contains calls and tail calls, so RV_REG_TCC need 1797 * to be saved across calls. 1798 */ 1799 if (seen_tail_call(ctx) && seen_call(ctx)) 1800 emit_mv(RV_REG_TCC_SAVED, RV_REG_TCC, ctx); 1801 1802 ctx->stack_size = stack_adjust; 1803 } 1804 1805 void bpf_jit_build_epilogue(struct rv_jit_context *ctx) 1806 { 1807 __build_epilogue(false, ctx); 1808 } 1809 1810 bool bpf_jit_supports_kfunc_call(void) 1811 { 1812 return true; 1813 } 1814