1 // SPDX-License-Identifier: GPL-2.0 2 /* BPF JIT compiler for RV64G 3 * 4 * Copyright(c) 2019 Björn Töpel <bjorn.topel@gmail.com> 5 * 6 */ 7 8 #include <linux/bitfield.h> 9 #include <linux/bpf.h> 10 #include <linux/filter.h> 11 #include <linux/memory.h> 12 #include <linux/stop_machine.h> 13 #include <asm/patch.h> 14 #include "bpf_jit.h" 15 16 #define RV_FENTRY_NINSNS 2 17 18 #define RV_REG_TCC RV_REG_A6 19 #define RV_REG_TCC_SAVED RV_REG_S6 /* Store A6 in S6 if program do calls */ 20 21 static const int regmap[] = { 22 [BPF_REG_0] = RV_REG_A5, 23 [BPF_REG_1] = RV_REG_A0, 24 [BPF_REG_2] = RV_REG_A1, 25 [BPF_REG_3] = RV_REG_A2, 26 [BPF_REG_4] = RV_REG_A3, 27 [BPF_REG_5] = RV_REG_A4, 28 [BPF_REG_6] = RV_REG_S1, 29 [BPF_REG_7] = RV_REG_S2, 30 [BPF_REG_8] = RV_REG_S3, 31 [BPF_REG_9] = RV_REG_S4, 32 [BPF_REG_FP] = RV_REG_S5, 33 [BPF_REG_AX] = RV_REG_T0, 34 }; 35 36 static const int pt_regmap[] = { 37 [RV_REG_A0] = offsetof(struct pt_regs, a0), 38 [RV_REG_A1] = offsetof(struct pt_regs, a1), 39 [RV_REG_A2] = offsetof(struct pt_regs, a2), 40 [RV_REG_A3] = offsetof(struct pt_regs, a3), 41 [RV_REG_A4] = offsetof(struct pt_regs, a4), 42 [RV_REG_A5] = offsetof(struct pt_regs, a5), 43 [RV_REG_S1] = offsetof(struct pt_regs, s1), 44 [RV_REG_S2] = offsetof(struct pt_regs, s2), 45 [RV_REG_S3] = offsetof(struct pt_regs, s3), 46 [RV_REG_S4] = offsetof(struct pt_regs, s4), 47 [RV_REG_S5] = offsetof(struct pt_regs, s5), 48 [RV_REG_T0] = offsetof(struct pt_regs, t0), 49 }; 50 51 enum { 52 RV_CTX_F_SEEN_TAIL_CALL = 0, 53 RV_CTX_F_SEEN_CALL = RV_REG_RA, 54 RV_CTX_F_SEEN_S1 = RV_REG_S1, 55 RV_CTX_F_SEEN_S2 = RV_REG_S2, 56 RV_CTX_F_SEEN_S3 = RV_REG_S3, 57 RV_CTX_F_SEEN_S4 = RV_REG_S4, 58 RV_CTX_F_SEEN_S5 = RV_REG_S5, 59 RV_CTX_F_SEEN_S6 = RV_REG_S6, 60 }; 61 62 static u8 bpf_to_rv_reg(int bpf_reg, struct rv_jit_context *ctx) 63 { 64 u8 reg = regmap[bpf_reg]; 65 66 switch (reg) { 67 case RV_CTX_F_SEEN_S1: 68 case RV_CTX_F_SEEN_S2: 69 case RV_CTX_F_SEEN_S3: 70 case RV_CTX_F_SEEN_S4: 71 case RV_CTX_F_SEEN_S5: 72 case RV_CTX_F_SEEN_S6: 73 __set_bit(reg, &ctx->flags); 74 } 75 return reg; 76 }; 77 78 static bool seen_reg(int reg, struct rv_jit_context *ctx) 79 { 80 switch (reg) { 81 case RV_CTX_F_SEEN_CALL: 82 case RV_CTX_F_SEEN_S1: 83 case RV_CTX_F_SEEN_S2: 84 case RV_CTX_F_SEEN_S3: 85 case RV_CTX_F_SEEN_S4: 86 case RV_CTX_F_SEEN_S5: 87 case RV_CTX_F_SEEN_S6: 88 return test_bit(reg, &ctx->flags); 89 } 90 return false; 91 } 92 93 static void mark_fp(struct rv_jit_context *ctx) 94 { 95 __set_bit(RV_CTX_F_SEEN_S5, &ctx->flags); 96 } 97 98 static void mark_call(struct rv_jit_context *ctx) 99 { 100 __set_bit(RV_CTX_F_SEEN_CALL, &ctx->flags); 101 } 102 103 static bool seen_call(struct rv_jit_context *ctx) 104 { 105 return test_bit(RV_CTX_F_SEEN_CALL, &ctx->flags); 106 } 107 108 static void mark_tail_call(struct rv_jit_context *ctx) 109 { 110 __set_bit(RV_CTX_F_SEEN_TAIL_CALL, &ctx->flags); 111 } 112 113 static bool seen_tail_call(struct rv_jit_context *ctx) 114 { 115 return test_bit(RV_CTX_F_SEEN_TAIL_CALL, &ctx->flags); 116 } 117 118 static u8 rv_tail_call_reg(struct rv_jit_context *ctx) 119 { 120 mark_tail_call(ctx); 121 122 if (seen_call(ctx)) { 123 __set_bit(RV_CTX_F_SEEN_S6, &ctx->flags); 124 return RV_REG_S6; 125 } 126 return RV_REG_A6; 127 } 128 129 static bool is_32b_int(s64 val) 130 { 131 return -(1L << 31) <= val && val < (1L << 31); 132 } 133 134 static bool in_auipc_jalr_range(s64 val) 135 { 136 /* 137 * auipc+jalr can reach any signed PC-relative offset in the range 138 * [-2^31 - 2^11, 2^31 - 2^11). 139 */ 140 return (-(1L << 31) - (1L << 11)) <= val && 141 val < ((1L << 31) - (1L << 11)); 142 } 143 144 /* Emit fixed-length instructions for address */ 145 static int emit_addr(u8 rd, u64 addr, bool extra_pass, struct rv_jit_context *ctx) 146 { 147 /* 148 * Use the ro_insns(RX) to calculate the offset as the BPF program will 149 * finally run from this memory region. 150 */ 151 u64 ip = (u64)(ctx->ro_insns + ctx->ninsns); 152 s64 off = addr - ip; 153 s64 upper = (off + (1 << 11)) >> 12; 154 s64 lower = off & 0xfff; 155 156 if (extra_pass && !in_auipc_jalr_range(off)) { 157 pr_err("bpf-jit: target offset 0x%llx is out of range\n", off); 158 return -ERANGE; 159 } 160 161 emit(rv_auipc(rd, upper), ctx); 162 emit(rv_addi(rd, rd, lower), ctx); 163 return 0; 164 } 165 166 /* Emit variable-length instructions for 32-bit and 64-bit imm */ 167 static void emit_imm(u8 rd, s64 val, struct rv_jit_context *ctx) 168 { 169 /* Note that the immediate from the add is sign-extended, 170 * which means that we need to compensate this by adding 2^12, 171 * when the 12th bit is set. A simpler way of doing this, and 172 * getting rid of the check, is to just add 2**11 before the 173 * shift. The "Loading a 32-Bit constant" example from the 174 * "Computer Organization and Design, RISC-V edition" book by 175 * Patterson/Hennessy highlights this fact. 176 * 177 * This also means that we need to process LSB to MSB. 178 */ 179 s64 upper = (val + (1 << 11)) >> 12; 180 /* Sign-extend lower 12 bits to 64 bits since immediates for li, addiw, 181 * and addi are signed and RVC checks will perform signed comparisons. 182 */ 183 s64 lower = ((val & 0xfff) << 52) >> 52; 184 int shift; 185 186 if (is_32b_int(val)) { 187 if (upper) 188 emit_lui(rd, upper, ctx); 189 190 if (!upper) { 191 emit_li(rd, lower, ctx); 192 return; 193 } 194 195 emit_addiw(rd, rd, lower, ctx); 196 return; 197 } 198 199 shift = __ffs(upper); 200 upper >>= shift; 201 shift += 12; 202 203 emit_imm(rd, upper, ctx); 204 205 emit_slli(rd, rd, shift, ctx); 206 if (lower) 207 emit_addi(rd, rd, lower, ctx); 208 } 209 210 static void __build_epilogue(bool is_tail_call, struct rv_jit_context *ctx) 211 { 212 int stack_adjust = ctx->stack_size, store_offset = stack_adjust - 8; 213 214 if (seen_reg(RV_REG_RA, ctx)) { 215 emit_ld(RV_REG_RA, store_offset, RV_REG_SP, ctx); 216 store_offset -= 8; 217 } 218 emit_ld(RV_REG_FP, store_offset, RV_REG_SP, ctx); 219 store_offset -= 8; 220 if (seen_reg(RV_REG_S1, ctx)) { 221 emit_ld(RV_REG_S1, store_offset, RV_REG_SP, ctx); 222 store_offset -= 8; 223 } 224 if (seen_reg(RV_REG_S2, ctx)) { 225 emit_ld(RV_REG_S2, store_offset, RV_REG_SP, ctx); 226 store_offset -= 8; 227 } 228 if (seen_reg(RV_REG_S3, ctx)) { 229 emit_ld(RV_REG_S3, store_offset, RV_REG_SP, ctx); 230 store_offset -= 8; 231 } 232 if (seen_reg(RV_REG_S4, ctx)) { 233 emit_ld(RV_REG_S4, store_offset, RV_REG_SP, ctx); 234 store_offset -= 8; 235 } 236 if (seen_reg(RV_REG_S5, ctx)) { 237 emit_ld(RV_REG_S5, store_offset, RV_REG_SP, ctx); 238 store_offset -= 8; 239 } 240 if (seen_reg(RV_REG_S6, ctx)) { 241 emit_ld(RV_REG_S6, store_offset, RV_REG_SP, ctx); 242 store_offset -= 8; 243 } 244 245 emit_addi(RV_REG_SP, RV_REG_SP, stack_adjust, ctx); 246 /* Set return value. */ 247 if (!is_tail_call) 248 emit_mv(RV_REG_A0, RV_REG_A5, ctx); 249 emit_jalr(RV_REG_ZERO, is_tail_call ? RV_REG_T3 : RV_REG_RA, 250 is_tail_call ? (RV_FENTRY_NINSNS + 1) * 4 : 0, /* skip reserved nops and TCC init */ 251 ctx); 252 } 253 254 static void emit_bcc(u8 cond, u8 rd, u8 rs, int rvoff, 255 struct rv_jit_context *ctx) 256 { 257 switch (cond) { 258 case BPF_JEQ: 259 emit(rv_beq(rd, rs, rvoff >> 1), ctx); 260 return; 261 case BPF_JGT: 262 emit(rv_bltu(rs, rd, rvoff >> 1), ctx); 263 return; 264 case BPF_JLT: 265 emit(rv_bltu(rd, rs, rvoff >> 1), ctx); 266 return; 267 case BPF_JGE: 268 emit(rv_bgeu(rd, rs, rvoff >> 1), ctx); 269 return; 270 case BPF_JLE: 271 emit(rv_bgeu(rs, rd, rvoff >> 1), ctx); 272 return; 273 case BPF_JNE: 274 emit(rv_bne(rd, rs, rvoff >> 1), ctx); 275 return; 276 case BPF_JSGT: 277 emit(rv_blt(rs, rd, rvoff >> 1), ctx); 278 return; 279 case BPF_JSLT: 280 emit(rv_blt(rd, rs, rvoff >> 1), ctx); 281 return; 282 case BPF_JSGE: 283 emit(rv_bge(rd, rs, rvoff >> 1), ctx); 284 return; 285 case BPF_JSLE: 286 emit(rv_bge(rs, rd, rvoff >> 1), ctx); 287 } 288 } 289 290 static void emit_branch(u8 cond, u8 rd, u8 rs, int rvoff, 291 struct rv_jit_context *ctx) 292 { 293 s64 upper, lower; 294 295 if (is_13b_int(rvoff)) { 296 emit_bcc(cond, rd, rs, rvoff, ctx); 297 return; 298 } 299 300 /* Adjust for jal */ 301 rvoff -= 4; 302 303 /* Transform, e.g.: 304 * bne rd,rs,foo 305 * to 306 * beq rd,rs,<.L1> 307 * (auipc foo) 308 * jal(r) foo 309 * .L1 310 */ 311 cond = invert_bpf_cond(cond); 312 if (is_21b_int(rvoff)) { 313 emit_bcc(cond, rd, rs, 8, ctx); 314 emit(rv_jal(RV_REG_ZERO, rvoff >> 1), ctx); 315 return; 316 } 317 318 /* 32b No need for an additional rvoff adjustment, since we 319 * get that from the auipc at PC', where PC = PC' + 4. 320 */ 321 upper = (rvoff + (1 << 11)) >> 12; 322 lower = rvoff & 0xfff; 323 324 emit_bcc(cond, rd, rs, 12, ctx); 325 emit(rv_auipc(RV_REG_T1, upper), ctx); 326 emit(rv_jalr(RV_REG_ZERO, RV_REG_T1, lower), ctx); 327 } 328 329 static void emit_zext_32(u8 reg, struct rv_jit_context *ctx) 330 { 331 emit_slli(reg, reg, 32, ctx); 332 emit_srli(reg, reg, 32, ctx); 333 } 334 335 static int emit_bpf_tail_call(int insn, struct rv_jit_context *ctx) 336 { 337 int tc_ninsn, off, start_insn = ctx->ninsns; 338 u8 tcc = rv_tail_call_reg(ctx); 339 340 /* a0: &ctx 341 * a1: &array 342 * a2: index 343 * 344 * if (index >= array->map.max_entries) 345 * goto out; 346 */ 347 tc_ninsn = insn ? ctx->offset[insn] - ctx->offset[insn - 1] : 348 ctx->offset[0]; 349 emit_zext_32(RV_REG_A2, ctx); 350 351 off = offsetof(struct bpf_array, map.max_entries); 352 if (is_12b_check(off, insn)) 353 return -1; 354 emit(rv_lwu(RV_REG_T1, off, RV_REG_A1), ctx); 355 off = ninsns_rvoff(tc_ninsn - (ctx->ninsns - start_insn)); 356 emit_branch(BPF_JGE, RV_REG_A2, RV_REG_T1, off, ctx); 357 358 /* if (--TCC < 0) 359 * goto out; 360 */ 361 emit_addi(RV_REG_TCC, tcc, -1, ctx); 362 off = ninsns_rvoff(tc_ninsn - (ctx->ninsns - start_insn)); 363 emit_branch(BPF_JSLT, RV_REG_TCC, RV_REG_ZERO, off, ctx); 364 365 /* prog = array->ptrs[index]; 366 * if (!prog) 367 * goto out; 368 */ 369 emit_slli(RV_REG_T2, RV_REG_A2, 3, ctx); 370 emit_add(RV_REG_T2, RV_REG_T2, RV_REG_A1, ctx); 371 off = offsetof(struct bpf_array, ptrs); 372 if (is_12b_check(off, insn)) 373 return -1; 374 emit_ld(RV_REG_T2, off, RV_REG_T2, ctx); 375 off = ninsns_rvoff(tc_ninsn - (ctx->ninsns - start_insn)); 376 emit_branch(BPF_JEQ, RV_REG_T2, RV_REG_ZERO, off, ctx); 377 378 /* goto *(prog->bpf_func + 4); */ 379 off = offsetof(struct bpf_prog, bpf_func); 380 if (is_12b_check(off, insn)) 381 return -1; 382 emit_ld(RV_REG_T3, off, RV_REG_T2, ctx); 383 __build_epilogue(true, ctx); 384 return 0; 385 } 386 387 static void init_regs(u8 *rd, u8 *rs, const struct bpf_insn *insn, 388 struct rv_jit_context *ctx) 389 { 390 u8 code = insn->code; 391 392 switch (code) { 393 case BPF_JMP | BPF_JA: 394 case BPF_JMP | BPF_CALL: 395 case BPF_JMP | BPF_EXIT: 396 case BPF_JMP | BPF_TAIL_CALL: 397 break; 398 default: 399 *rd = bpf_to_rv_reg(insn->dst_reg, ctx); 400 } 401 402 if (code & (BPF_ALU | BPF_X) || code & (BPF_ALU64 | BPF_X) || 403 code & (BPF_JMP | BPF_X) || code & (BPF_JMP32 | BPF_X) || 404 code & BPF_LDX || code & BPF_STX) 405 *rs = bpf_to_rv_reg(insn->src_reg, ctx); 406 } 407 408 static void emit_zext_32_rd_rs(u8 *rd, u8 *rs, struct rv_jit_context *ctx) 409 { 410 emit_mv(RV_REG_T2, *rd, ctx); 411 emit_zext_32(RV_REG_T2, ctx); 412 emit_mv(RV_REG_T1, *rs, ctx); 413 emit_zext_32(RV_REG_T1, ctx); 414 *rd = RV_REG_T2; 415 *rs = RV_REG_T1; 416 } 417 418 static void emit_sext_32_rd_rs(u8 *rd, u8 *rs, struct rv_jit_context *ctx) 419 { 420 emit_addiw(RV_REG_T2, *rd, 0, ctx); 421 emit_addiw(RV_REG_T1, *rs, 0, ctx); 422 *rd = RV_REG_T2; 423 *rs = RV_REG_T1; 424 } 425 426 static void emit_zext_32_rd_t1(u8 *rd, struct rv_jit_context *ctx) 427 { 428 emit_mv(RV_REG_T2, *rd, ctx); 429 emit_zext_32(RV_REG_T2, ctx); 430 emit_zext_32(RV_REG_T1, ctx); 431 *rd = RV_REG_T2; 432 } 433 434 static void emit_sext_32_rd(u8 *rd, struct rv_jit_context *ctx) 435 { 436 emit_addiw(RV_REG_T2, *rd, 0, ctx); 437 *rd = RV_REG_T2; 438 } 439 440 static int emit_jump_and_link(u8 rd, s64 rvoff, bool fixed_addr, 441 struct rv_jit_context *ctx) 442 { 443 s64 upper, lower; 444 445 if (rvoff && fixed_addr && is_21b_int(rvoff)) { 446 emit(rv_jal(rd, rvoff >> 1), ctx); 447 return 0; 448 } else if (in_auipc_jalr_range(rvoff)) { 449 upper = (rvoff + (1 << 11)) >> 12; 450 lower = rvoff & 0xfff; 451 emit(rv_auipc(RV_REG_T1, upper), ctx); 452 emit(rv_jalr(rd, RV_REG_T1, lower), ctx); 453 return 0; 454 } 455 456 pr_err("bpf-jit: target offset 0x%llx is out of range\n", rvoff); 457 return -ERANGE; 458 } 459 460 static bool is_signed_bpf_cond(u8 cond) 461 { 462 return cond == BPF_JSGT || cond == BPF_JSLT || 463 cond == BPF_JSGE || cond == BPF_JSLE; 464 } 465 466 static int emit_call(u64 addr, bool fixed_addr, struct rv_jit_context *ctx) 467 { 468 s64 off = 0; 469 u64 ip; 470 471 if (addr && ctx->insns && ctx->ro_insns) { 472 /* 473 * Use the ro_insns(RX) to calculate the offset as the BPF 474 * program will finally run from this memory region. 475 */ 476 ip = (u64)(long)(ctx->ro_insns + ctx->ninsns); 477 off = addr - ip; 478 } 479 480 return emit_jump_and_link(RV_REG_RA, off, fixed_addr, ctx); 481 } 482 483 static void emit_atomic(u8 rd, u8 rs, s16 off, s32 imm, bool is64, 484 struct rv_jit_context *ctx) 485 { 486 u8 r0; 487 int jmp_offset; 488 489 if (off) { 490 if (is_12b_int(off)) { 491 emit_addi(RV_REG_T1, rd, off, ctx); 492 } else { 493 emit_imm(RV_REG_T1, off, ctx); 494 emit_add(RV_REG_T1, RV_REG_T1, rd, ctx); 495 } 496 rd = RV_REG_T1; 497 } 498 499 switch (imm) { 500 /* lock *(u32/u64 *)(dst_reg + off16) <op>= src_reg */ 501 case BPF_ADD: 502 emit(is64 ? rv_amoadd_d(RV_REG_ZERO, rs, rd, 0, 0) : 503 rv_amoadd_w(RV_REG_ZERO, rs, rd, 0, 0), ctx); 504 break; 505 case BPF_AND: 506 emit(is64 ? rv_amoand_d(RV_REG_ZERO, rs, rd, 0, 0) : 507 rv_amoand_w(RV_REG_ZERO, rs, rd, 0, 0), ctx); 508 break; 509 case BPF_OR: 510 emit(is64 ? rv_amoor_d(RV_REG_ZERO, rs, rd, 0, 0) : 511 rv_amoor_w(RV_REG_ZERO, rs, rd, 0, 0), ctx); 512 break; 513 case BPF_XOR: 514 emit(is64 ? rv_amoxor_d(RV_REG_ZERO, rs, rd, 0, 0) : 515 rv_amoxor_w(RV_REG_ZERO, rs, rd, 0, 0), ctx); 516 break; 517 /* src_reg = atomic_fetch_<op>(dst_reg + off16, src_reg) */ 518 case BPF_ADD | BPF_FETCH: 519 emit(is64 ? rv_amoadd_d(rs, rs, rd, 0, 0) : 520 rv_amoadd_w(rs, rs, rd, 0, 0), ctx); 521 if (!is64) 522 emit_zext_32(rs, ctx); 523 break; 524 case BPF_AND | BPF_FETCH: 525 emit(is64 ? rv_amoand_d(rs, rs, rd, 0, 0) : 526 rv_amoand_w(rs, rs, rd, 0, 0), ctx); 527 if (!is64) 528 emit_zext_32(rs, ctx); 529 break; 530 case BPF_OR | BPF_FETCH: 531 emit(is64 ? rv_amoor_d(rs, rs, rd, 0, 0) : 532 rv_amoor_w(rs, rs, rd, 0, 0), ctx); 533 if (!is64) 534 emit_zext_32(rs, ctx); 535 break; 536 case BPF_XOR | BPF_FETCH: 537 emit(is64 ? rv_amoxor_d(rs, rs, rd, 0, 0) : 538 rv_amoxor_w(rs, rs, rd, 0, 0), ctx); 539 if (!is64) 540 emit_zext_32(rs, ctx); 541 break; 542 /* src_reg = atomic_xchg(dst_reg + off16, src_reg); */ 543 case BPF_XCHG: 544 emit(is64 ? rv_amoswap_d(rs, rs, rd, 0, 0) : 545 rv_amoswap_w(rs, rs, rd, 0, 0), ctx); 546 if (!is64) 547 emit_zext_32(rs, ctx); 548 break; 549 /* r0 = atomic_cmpxchg(dst_reg + off16, r0, src_reg); */ 550 case BPF_CMPXCHG: 551 r0 = bpf_to_rv_reg(BPF_REG_0, ctx); 552 emit(is64 ? rv_addi(RV_REG_T2, r0, 0) : 553 rv_addiw(RV_REG_T2, r0, 0), ctx); 554 emit(is64 ? rv_lr_d(r0, 0, rd, 0, 0) : 555 rv_lr_w(r0, 0, rd, 0, 0), ctx); 556 jmp_offset = ninsns_rvoff(8); 557 emit(rv_bne(RV_REG_T2, r0, jmp_offset >> 1), ctx); 558 emit(is64 ? rv_sc_d(RV_REG_T3, rs, rd, 0, 0) : 559 rv_sc_w(RV_REG_T3, rs, rd, 0, 0), ctx); 560 jmp_offset = ninsns_rvoff(-6); 561 emit(rv_bne(RV_REG_T3, 0, jmp_offset >> 1), ctx); 562 emit(rv_fence(0x3, 0x3), ctx); 563 break; 564 } 565 } 566 567 #define BPF_FIXUP_OFFSET_MASK GENMASK(26, 0) 568 #define BPF_FIXUP_REG_MASK GENMASK(31, 27) 569 570 bool ex_handler_bpf(const struct exception_table_entry *ex, 571 struct pt_regs *regs) 572 { 573 off_t offset = FIELD_GET(BPF_FIXUP_OFFSET_MASK, ex->fixup); 574 int regs_offset = FIELD_GET(BPF_FIXUP_REG_MASK, ex->fixup); 575 576 *(unsigned long *)((void *)regs + pt_regmap[regs_offset]) = 0; 577 regs->epc = (unsigned long)&ex->fixup - offset; 578 579 return true; 580 } 581 582 /* For accesses to BTF pointers, add an entry to the exception table */ 583 static int add_exception_handler(const struct bpf_insn *insn, 584 struct rv_jit_context *ctx, 585 int dst_reg, int insn_len) 586 { 587 struct exception_table_entry *ex; 588 unsigned long pc; 589 off_t ins_offset; 590 off_t fixup_offset; 591 592 if (!ctx->insns || !ctx->ro_insns || !ctx->prog->aux->extable || 593 (BPF_MODE(insn->code) != BPF_PROBE_MEM && BPF_MODE(insn->code) != BPF_PROBE_MEMSX)) 594 return 0; 595 596 if (WARN_ON_ONCE(ctx->nexentries >= ctx->prog->aux->num_exentries)) 597 return -EINVAL; 598 599 if (WARN_ON_ONCE(insn_len > ctx->ninsns)) 600 return -EINVAL; 601 602 if (WARN_ON_ONCE(!rvc_enabled() && insn_len == 1)) 603 return -EINVAL; 604 605 ex = &ctx->prog->aux->extable[ctx->nexentries]; 606 pc = (unsigned long)&ctx->ro_insns[ctx->ninsns - insn_len]; 607 608 /* 609 * This is the relative offset of the instruction that may fault from 610 * the exception table itself. This will be written to the exception 611 * table and if this instruction faults, the destination register will 612 * be set to '0' and the execution will jump to the next instruction. 613 */ 614 ins_offset = pc - (long)&ex->insn; 615 if (WARN_ON_ONCE(ins_offset >= 0 || ins_offset < INT_MIN)) 616 return -ERANGE; 617 618 /* 619 * Since the extable follows the program, the fixup offset is always 620 * negative and limited to BPF_JIT_REGION_SIZE. Store a positive value 621 * to keep things simple, and put the destination register in the upper 622 * bits. We don't need to worry about buildtime or runtime sort 623 * modifying the upper bits because the table is already sorted, and 624 * isn't part of the main exception table. 625 * 626 * The fixup_offset is set to the next instruction from the instruction 627 * that may fault. The execution will jump to this after handling the 628 * fault. 629 */ 630 fixup_offset = (long)&ex->fixup - (pc + insn_len * sizeof(u16)); 631 if (!FIELD_FIT(BPF_FIXUP_OFFSET_MASK, fixup_offset)) 632 return -ERANGE; 633 634 /* 635 * The offsets above have been calculated using the RO buffer but we 636 * need to use the R/W buffer for writes. 637 * switch ex to rw buffer for writing. 638 */ 639 ex = (void *)ctx->insns + ((void *)ex - (void *)ctx->ro_insns); 640 641 ex->insn = ins_offset; 642 643 ex->fixup = FIELD_PREP(BPF_FIXUP_OFFSET_MASK, fixup_offset) | 644 FIELD_PREP(BPF_FIXUP_REG_MASK, dst_reg); 645 ex->type = EX_TYPE_BPF; 646 647 ctx->nexentries++; 648 return 0; 649 } 650 651 static int gen_jump_or_nops(void *target, void *ip, u32 *insns, bool is_call) 652 { 653 s64 rvoff; 654 struct rv_jit_context ctx; 655 656 ctx.ninsns = 0; 657 ctx.insns = (u16 *)insns; 658 659 if (!target) { 660 emit(rv_nop(), &ctx); 661 emit(rv_nop(), &ctx); 662 return 0; 663 } 664 665 rvoff = (s64)(target - ip); 666 return emit_jump_and_link(is_call ? RV_REG_T0 : RV_REG_ZERO, rvoff, false, &ctx); 667 } 668 669 int bpf_arch_text_poke(void *ip, enum bpf_text_poke_type poke_type, 670 void *old_addr, void *new_addr) 671 { 672 u32 old_insns[RV_FENTRY_NINSNS], new_insns[RV_FENTRY_NINSNS]; 673 bool is_call = poke_type == BPF_MOD_CALL; 674 int ret; 675 676 if (!is_kernel_text((unsigned long)ip) && 677 !is_bpf_text_address((unsigned long)ip)) 678 return -ENOTSUPP; 679 680 ret = gen_jump_or_nops(old_addr, ip, old_insns, is_call); 681 if (ret) 682 return ret; 683 684 if (memcmp(ip, old_insns, RV_FENTRY_NINSNS * 4)) 685 return -EFAULT; 686 687 ret = gen_jump_or_nops(new_addr, ip, new_insns, is_call); 688 if (ret) 689 return ret; 690 691 cpus_read_lock(); 692 mutex_lock(&text_mutex); 693 if (memcmp(ip, new_insns, RV_FENTRY_NINSNS * 4)) 694 ret = patch_text(ip, new_insns, RV_FENTRY_NINSNS); 695 mutex_unlock(&text_mutex); 696 cpus_read_unlock(); 697 698 return ret; 699 } 700 701 static void store_args(int nregs, int args_off, struct rv_jit_context *ctx) 702 { 703 int i; 704 705 for (i = 0; i < nregs; i++) { 706 emit_sd(RV_REG_FP, -args_off, RV_REG_A0 + i, ctx); 707 args_off -= 8; 708 } 709 } 710 711 static void restore_args(int nregs, int args_off, struct rv_jit_context *ctx) 712 { 713 int i; 714 715 for (i = 0; i < nregs; i++) { 716 emit_ld(RV_REG_A0 + i, -args_off, RV_REG_FP, ctx); 717 args_off -= 8; 718 } 719 } 720 721 static int invoke_bpf_prog(struct bpf_tramp_link *l, int args_off, int retval_off, 722 int run_ctx_off, bool save_ret, struct rv_jit_context *ctx) 723 { 724 int ret, branch_off; 725 struct bpf_prog *p = l->link.prog; 726 int cookie_off = offsetof(struct bpf_tramp_run_ctx, bpf_cookie); 727 728 if (l->cookie) { 729 emit_imm(RV_REG_T1, l->cookie, ctx); 730 emit_sd(RV_REG_FP, -run_ctx_off + cookie_off, RV_REG_T1, ctx); 731 } else { 732 emit_sd(RV_REG_FP, -run_ctx_off + cookie_off, RV_REG_ZERO, ctx); 733 } 734 735 /* arg1: prog */ 736 emit_imm(RV_REG_A0, (const s64)p, ctx); 737 /* arg2: &run_ctx */ 738 emit_addi(RV_REG_A1, RV_REG_FP, -run_ctx_off, ctx); 739 ret = emit_call((const u64)bpf_trampoline_enter(p), true, ctx); 740 if (ret) 741 return ret; 742 743 /* if (__bpf_prog_enter(prog) == 0) 744 * goto skip_exec_of_prog; 745 */ 746 branch_off = ctx->ninsns; 747 /* nop reserved for conditional jump */ 748 emit(rv_nop(), ctx); 749 750 /* store prog start time */ 751 emit_mv(RV_REG_S1, RV_REG_A0, ctx); 752 753 /* arg1: &args_off */ 754 emit_addi(RV_REG_A0, RV_REG_FP, -args_off, ctx); 755 if (!p->jited) 756 /* arg2: progs[i]->insnsi for interpreter */ 757 emit_imm(RV_REG_A1, (const s64)p->insnsi, ctx); 758 ret = emit_call((const u64)p->bpf_func, true, ctx); 759 if (ret) 760 return ret; 761 762 if (save_ret) 763 emit_sd(RV_REG_FP, -retval_off, regmap[BPF_REG_0], ctx); 764 765 /* update branch with beqz */ 766 if (ctx->insns) { 767 int offset = ninsns_rvoff(ctx->ninsns - branch_off); 768 u32 insn = rv_beq(RV_REG_A0, RV_REG_ZERO, offset >> 1); 769 *(u32 *)(ctx->insns + branch_off) = insn; 770 } 771 772 /* arg1: prog */ 773 emit_imm(RV_REG_A0, (const s64)p, ctx); 774 /* arg2: prog start time */ 775 emit_mv(RV_REG_A1, RV_REG_S1, ctx); 776 /* arg3: &run_ctx */ 777 emit_addi(RV_REG_A2, RV_REG_FP, -run_ctx_off, ctx); 778 ret = emit_call((const u64)bpf_trampoline_exit(p), true, ctx); 779 780 return ret; 781 } 782 783 static int __arch_prepare_bpf_trampoline(struct bpf_tramp_image *im, 784 const struct btf_func_model *m, 785 struct bpf_tramp_links *tlinks, 786 void *func_addr, u32 flags, 787 struct rv_jit_context *ctx) 788 { 789 int i, ret, offset; 790 int *branches_off = NULL; 791 int stack_size = 0, nregs = m->nr_args; 792 int retval_off, args_off, nregs_off, ip_off, run_ctx_off, sreg_off; 793 struct bpf_tramp_links *fentry = &tlinks[BPF_TRAMP_FENTRY]; 794 struct bpf_tramp_links *fexit = &tlinks[BPF_TRAMP_FEXIT]; 795 struct bpf_tramp_links *fmod_ret = &tlinks[BPF_TRAMP_MODIFY_RETURN]; 796 void *orig_call = func_addr; 797 bool save_ret; 798 u32 insn; 799 800 /* Two types of generated trampoline stack layout: 801 * 802 * 1. trampoline called from function entry 803 * -------------------------------------- 804 * FP + 8 [ RA to parent func ] return address to parent 805 * function 806 * FP + 0 [ FP of parent func ] frame pointer of parent 807 * function 808 * FP - 8 [ T0 to traced func ] return address of traced 809 * function 810 * FP - 16 [ FP of traced func ] frame pointer of traced 811 * function 812 * -------------------------------------- 813 * 814 * 2. trampoline called directly 815 * -------------------------------------- 816 * FP - 8 [ RA to caller func ] return address to caller 817 * function 818 * FP - 16 [ FP of caller func ] frame pointer of caller 819 * function 820 * -------------------------------------- 821 * 822 * FP - retval_off [ return value ] BPF_TRAMP_F_CALL_ORIG or 823 * BPF_TRAMP_F_RET_FENTRY_RET 824 * [ argN ] 825 * [ ... ] 826 * FP - args_off [ arg1 ] 827 * 828 * FP - nregs_off [ regs count ] 829 * 830 * FP - ip_off [ traced func ] BPF_TRAMP_F_IP_ARG 831 * 832 * FP - run_ctx_off [ bpf_tramp_run_ctx ] 833 * 834 * FP - sreg_off [ callee saved reg ] 835 * 836 * [ pads ] pads for 16 bytes alignment 837 */ 838 839 if (flags & (BPF_TRAMP_F_ORIG_STACK | BPF_TRAMP_F_SHARE_IPMODIFY)) 840 return -ENOTSUPP; 841 842 /* extra regiters for struct arguments */ 843 for (i = 0; i < m->nr_args; i++) 844 if (m->arg_flags[i] & BTF_FMODEL_STRUCT_ARG) 845 nregs += round_up(m->arg_size[i], 8) / 8 - 1; 846 847 /* 8 arguments passed by registers */ 848 if (nregs > 8) 849 return -ENOTSUPP; 850 851 /* room of trampoline frame to store return address and frame pointer */ 852 stack_size += 16; 853 854 save_ret = flags & (BPF_TRAMP_F_CALL_ORIG | BPF_TRAMP_F_RET_FENTRY_RET); 855 if (save_ret) { 856 stack_size += 8; 857 retval_off = stack_size; 858 } 859 860 stack_size += nregs * 8; 861 args_off = stack_size; 862 863 stack_size += 8; 864 nregs_off = stack_size; 865 866 if (flags & BPF_TRAMP_F_IP_ARG) { 867 stack_size += 8; 868 ip_off = stack_size; 869 } 870 871 stack_size += round_up(sizeof(struct bpf_tramp_run_ctx), 8); 872 run_ctx_off = stack_size; 873 874 stack_size += 8; 875 sreg_off = stack_size; 876 877 stack_size = round_up(stack_size, 16); 878 879 if (func_addr) { 880 /* For the trampoline called from function entry, 881 * the frame of traced function and the frame of 882 * trampoline need to be considered. 883 */ 884 emit_addi(RV_REG_SP, RV_REG_SP, -16, ctx); 885 emit_sd(RV_REG_SP, 8, RV_REG_RA, ctx); 886 emit_sd(RV_REG_SP, 0, RV_REG_FP, ctx); 887 emit_addi(RV_REG_FP, RV_REG_SP, 16, ctx); 888 889 emit_addi(RV_REG_SP, RV_REG_SP, -stack_size, ctx); 890 emit_sd(RV_REG_SP, stack_size - 8, RV_REG_T0, ctx); 891 emit_sd(RV_REG_SP, stack_size - 16, RV_REG_FP, ctx); 892 emit_addi(RV_REG_FP, RV_REG_SP, stack_size, ctx); 893 } else { 894 /* For the trampoline called directly, just handle 895 * the frame of trampoline. 896 */ 897 emit_addi(RV_REG_SP, RV_REG_SP, -stack_size, ctx); 898 emit_sd(RV_REG_SP, stack_size - 8, RV_REG_RA, ctx); 899 emit_sd(RV_REG_SP, stack_size - 16, RV_REG_FP, ctx); 900 emit_addi(RV_REG_FP, RV_REG_SP, stack_size, ctx); 901 } 902 903 /* callee saved register S1 to pass start time */ 904 emit_sd(RV_REG_FP, -sreg_off, RV_REG_S1, ctx); 905 906 /* store ip address of the traced function */ 907 if (flags & BPF_TRAMP_F_IP_ARG) { 908 emit_imm(RV_REG_T1, (const s64)func_addr, ctx); 909 emit_sd(RV_REG_FP, -ip_off, RV_REG_T1, ctx); 910 } 911 912 emit_li(RV_REG_T1, nregs, ctx); 913 emit_sd(RV_REG_FP, -nregs_off, RV_REG_T1, ctx); 914 915 store_args(nregs, args_off, ctx); 916 917 /* skip to actual body of traced function */ 918 if (flags & BPF_TRAMP_F_SKIP_FRAME) 919 orig_call += RV_FENTRY_NINSNS * 4; 920 921 if (flags & BPF_TRAMP_F_CALL_ORIG) { 922 emit_imm(RV_REG_A0, (const s64)im, ctx); 923 ret = emit_call((const u64)__bpf_tramp_enter, true, ctx); 924 if (ret) 925 return ret; 926 } 927 928 for (i = 0; i < fentry->nr_links; i++) { 929 ret = invoke_bpf_prog(fentry->links[i], args_off, retval_off, run_ctx_off, 930 flags & BPF_TRAMP_F_RET_FENTRY_RET, ctx); 931 if (ret) 932 return ret; 933 } 934 935 if (fmod_ret->nr_links) { 936 branches_off = kcalloc(fmod_ret->nr_links, sizeof(int), GFP_KERNEL); 937 if (!branches_off) 938 return -ENOMEM; 939 940 /* cleanup to avoid garbage return value confusion */ 941 emit_sd(RV_REG_FP, -retval_off, RV_REG_ZERO, ctx); 942 for (i = 0; i < fmod_ret->nr_links; i++) { 943 ret = invoke_bpf_prog(fmod_ret->links[i], args_off, retval_off, 944 run_ctx_off, true, ctx); 945 if (ret) 946 goto out; 947 emit_ld(RV_REG_T1, -retval_off, RV_REG_FP, ctx); 948 branches_off[i] = ctx->ninsns; 949 /* nop reserved for conditional jump */ 950 emit(rv_nop(), ctx); 951 } 952 } 953 954 if (flags & BPF_TRAMP_F_CALL_ORIG) { 955 restore_args(nregs, args_off, ctx); 956 ret = emit_call((const u64)orig_call, true, ctx); 957 if (ret) 958 goto out; 959 emit_sd(RV_REG_FP, -retval_off, RV_REG_A0, ctx); 960 im->ip_after_call = ctx->insns + ctx->ninsns; 961 /* 2 nops reserved for auipc+jalr pair */ 962 emit(rv_nop(), ctx); 963 emit(rv_nop(), ctx); 964 } 965 966 /* update branches saved in invoke_bpf_mod_ret with bnez */ 967 for (i = 0; ctx->insns && i < fmod_ret->nr_links; i++) { 968 offset = ninsns_rvoff(ctx->ninsns - branches_off[i]); 969 insn = rv_bne(RV_REG_T1, RV_REG_ZERO, offset >> 1); 970 *(u32 *)(ctx->insns + branches_off[i]) = insn; 971 } 972 973 for (i = 0; i < fexit->nr_links; i++) { 974 ret = invoke_bpf_prog(fexit->links[i], args_off, retval_off, 975 run_ctx_off, false, ctx); 976 if (ret) 977 goto out; 978 } 979 980 if (flags & BPF_TRAMP_F_CALL_ORIG) { 981 im->ip_epilogue = ctx->insns + ctx->ninsns; 982 emit_imm(RV_REG_A0, (const s64)im, ctx); 983 ret = emit_call((const u64)__bpf_tramp_exit, true, ctx); 984 if (ret) 985 goto out; 986 } 987 988 if (flags & BPF_TRAMP_F_RESTORE_REGS) 989 restore_args(nregs, args_off, ctx); 990 991 if (save_ret) 992 emit_ld(RV_REG_A0, -retval_off, RV_REG_FP, ctx); 993 994 emit_ld(RV_REG_S1, -sreg_off, RV_REG_FP, ctx); 995 996 if (func_addr) { 997 /* trampoline called from function entry */ 998 emit_ld(RV_REG_T0, stack_size - 8, RV_REG_SP, ctx); 999 emit_ld(RV_REG_FP, stack_size - 16, RV_REG_SP, ctx); 1000 emit_addi(RV_REG_SP, RV_REG_SP, stack_size, ctx); 1001 1002 emit_ld(RV_REG_RA, 8, RV_REG_SP, ctx); 1003 emit_ld(RV_REG_FP, 0, RV_REG_SP, ctx); 1004 emit_addi(RV_REG_SP, RV_REG_SP, 16, ctx); 1005 1006 if (flags & BPF_TRAMP_F_SKIP_FRAME) 1007 /* return to parent function */ 1008 emit_jalr(RV_REG_ZERO, RV_REG_RA, 0, ctx); 1009 else 1010 /* return to traced function */ 1011 emit_jalr(RV_REG_ZERO, RV_REG_T0, 0, ctx); 1012 } else { 1013 /* trampoline called directly */ 1014 emit_ld(RV_REG_RA, stack_size - 8, RV_REG_SP, ctx); 1015 emit_ld(RV_REG_FP, stack_size - 16, RV_REG_SP, ctx); 1016 emit_addi(RV_REG_SP, RV_REG_SP, stack_size, ctx); 1017 1018 emit_jalr(RV_REG_ZERO, RV_REG_RA, 0, ctx); 1019 } 1020 1021 ret = ctx->ninsns; 1022 out: 1023 kfree(branches_off); 1024 return ret; 1025 } 1026 1027 int arch_prepare_bpf_trampoline(struct bpf_tramp_image *im, void *image, 1028 void *image_end, const struct btf_func_model *m, 1029 u32 flags, struct bpf_tramp_links *tlinks, 1030 void *func_addr) 1031 { 1032 int ret; 1033 struct rv_jit_context ctx; 1034 1035 ctx.ninsns = 0; 1036 ctx.insns = NULL; 1037 ctx.ro_insns = NULL; 1038 ret = __arch_prepare_bpf_trampoline(im, m, tlinks, func_addr, flags, &ctx); 1039 if (ret < 0) 1040 return ret; 1041 1042 if (ninsns_rvoff(ret) > (long)image_end - (long)image) 1043 return -EFBIG; 1044 1045 ctx.ninsns = 0; 1046 /* 1047 * The bpf_int_jit_compile() uses a RW buffer (ctx.insns) to write the 1048 * JITed instructions and later copies it to a RX region (ctx.ro_insns). 1049 * It also uses ctx.ro_insns to calculate offsets for jumps etc. As the 1050 * trampoline image uses the same memory area for writing and execution, 1051 * both ctx.insns and ctx.ro_insns can be set to image. 1052 */ 1053 ctx.insns = image; 1054 ctx.ro_insns = image; 1055 ret = __arch_prepare_bpf_trampoline(im, m, tlinks, func_addr, flags, &ctx); 1056 if (ret < 0) 1057 return ret; 1058 1059 bpf_flush_icache(ctx.insns, ctx.insns + ctx.ninsns); 1060 1061 return ninsns_rvoff(ret); 1062 } 1063 1064 int bpf_jit_emit_insn(const struct bpf_insn *insn, struct rv_jit_context *ctx, 1065 bool extra_pass) 1066 { 1067 bool is64 = BPF_CLASS(insn->code) == BPF_ALU64 || 1068 BPF_CLASS(insn->code) == BPF_JMP; 1069 int s, e, rvoff, ret, i = insn - ctx->prog->insnsi; 1070 struct bpf_prog_aux *aux = ctx->prog->aux; 1071 u8 rd = -1, rs = -1, code = insn->code; 1072 s16 off = insn->off; 1073 s32 imm = insn->imm; 1074 1075 init_regs(&rd, &rs, insn, ctx); 1076 1077 switch (code) { 1078 /* dst = src */ 1079 case BPF_ALU | BPF_MOV | BPF_X: 1080 case BPF_ALU64 | BPF_MOV | BPF_X: 1081 if (imm == 1) { 1082 /* Special mov32 for zext */ 1083 emit_zext_32(rd, ctx); 1084 break; 1085 } 1086 switch (insn->off) { 1087 case 0: 1088 emit_mv(rd, rs, ctx); 1089 break; 1090 case 8: 1091 case 16: 1092 emit_slli(RV_REG_T1, rs, 64 - insn->off, ctx); 1093 emit_srai(rd, RV_REG_T1, 64 - insn->off, ctx); 1094 break; 1095 case 32: 1096 emit_addiw(rd, rs, 0, ctx); 1097 break; 1098 } 1099 if (!is64 && !aux->verifier_zext) 1100 emit_zext_32(rd, ctx); 1101 break; 1102 1103 /* dst = dst OP src */ 1104 case BPF_ALU | BPF_ADD | BPF_X: 1105 case BPF_ALU64 | BPF_ADD | BPF_X: 1106 emit_add(rd, rd, rs, ctx); 1107 if (!is64 && !aux->verifier_zext) 1108 emit_zext_32(rd, ctx); 1109 break; 1110 case BPF_ALU | BPF_SUB | BPF_X: 1111 case BPF_ALU64 | BPF_SUB | BPF_X: 1112 if (is64) 1113 emit_sub(rd, rd, rs, ctx); 1114 else 1115 emit_subw(rd, rd, rs, ctx); 1116 1117 if (!is64 && !aux->verifier_zext) 1118 emit_zext_32(rd, ctx); 1119 break; 1120 case BPF_ALU | BPF_AND | BPF_X: 1121 case BPF_ALU64 | BPF_AND | BPF_X: 1122 emit_and(rd, rd, rs, ctx); 1123 if (!is64 && !aux->verifier_zext) 1124 emit_zext_32(rd, ctx); 1125 break; 1126 case BPF_ALU | BPF_OR | BPF_X: 1127 case BPF_ALU64 | BPF_OR | BPF_X: 1128 emit_or(rd, rd, rs, ctx); 1129 if (!is64 && !aux->verifier_zext) 1130 emit_zext_32(rd, ctx); 1131 break; 1132 case BPF_ALU | BPF_XOR | BPF_X: 1133 case BPF_ALU64 | BPF_XOR | BPF_X: 1134 emit_xor(rd, rd, rs, ctx); 1135 if (!is64 && !aux->verifier_zext) 1136 emit_zext_32(rd, ctx); 1137 break; 1138 case BPF_ALU | BPF_MUL | BPF_X: 1139 case BPF_ALU64 | BPF_MUL | BPF_X: 1140 emit(is64 ? rv_mul(rd, rd, rs) : rv_mulw(rd, rd, rs), ctx); 1141 if (!is64 && !aux->verifier_zext) 1142 emit_zext_32(rd, ctx); 1143 break; 1144 case BPF_ALU | BPF_DIV | BPF_X: 1145 case BPF_ALU64 | BPF_DIV | BPF_X: 1146 if (off) 1147 emit(is64 ? rv_div(rd, rd, rs) : rv_divw(rd, rd, rs), ctx); 1148 else 1149 emit(is64 ? rv_divu(rd, rd, rs) : rv_divuw(rd, rd, rs), ctx); 1150 if (!is64 && !aux->verifier_zext) 1151 emit_zext_32(rd, ctx); 1152 break; 1153 case BPF_ALU | BPF_MOD | BPF_X: 1154 case BPF_ALU64 | BPF_MOD | BPF_X: 1155 if (off) 1156 emit(is64 ? rv_rem(rd, rd, rs) : rv_remw(rd, rd, rs), ctx); 1157 else 1158 emit(is64 ? rv_remu(rd, rd, rs) : rv_remuw(rd, rd, rs), ctx); 1159 if (!is64 && !aux->verifier_zext) 1160 emit_zext_32(rd, ctx); 1161 break; 1162 case BPF_ALU | BPF_LSH | BPF_X: 1163 case BPF_ALU64 | BPF_LSH | BPF_X: 1164 emit(is64 ? rv_sll(rd, rd, rs) : rv_sllw(rd, rd, rs), ctx); 1165 if (!is64 && !aux->verifier_zext) 1166 emit_zext_32(rd, ctx); 1167 break; 1168 case BPF_ALU | BPF_RSH | BPF_X: 1169 case BPF_ALU64 | BPF_RSH | BPF_X: 1170 emit(is64 ? rv_srl(rd, rd, rs) : rv_srlw(rd, rd, rs), ctx); 1171 if (!is64 && !aux->verifier_zext) 1172 emit_zext_32(rd, ctx); 1173 break; 1174 case BPF_ALU | BPF_ARSH | BPF_X: 1175 case BPF_ALU64 | BPF_ARSH | BPF_X: 1176 emit(is64 ? rv_sra(rd, rd, rs) : rv_sraw(rd, rd, rs), ctx); 1177 if (!is64 && !aux->verifier_zext) 1178 emit_zext_32(rd, ctx); 1179 break; 1180 1181 /* dst = -dst */ 1182 case BPF_ALU | BPF_NEG: 1183 case BPF_ALU64 | BPF_NEG: 1184 emit_sub(rd, RV_REG_ZERO, rd, ctx); 1185 if (!is64 && !aux->verifier_zext) 1186 emit_zext_32(rd, ctx); 1187 break; 1188 1189 /* dst = BSWAP##imm(dst) */ 1190 case BPF_ALU | BPF_END | BPF_FROM_LE: 1191 switch (imm) { 1192 case 16: 1193 emit_slli(rd, rd, 48, ctx); 1194 emit_srli(rd, rd, 48, ctx); 1195 break; 1196 case 32: 1197 if (!aux->verifier_zext) 1198 emit_zext_32(rd, ctx); 1199 break; 1200 case 64: 1201 /* Do nothing */ 1202 break; 1203 } 1204 break; 1205 1206 case BPF_ALU | BPF_END | BPF_FROM_BE: 1207 case BPF_ALU64 | BPF_END | BPF_FROM_LE: 1208 emit_li(RV_REG_T2, 0, ctx); 1209 1210 emit_andi(RV_REG_T1, rd, 0xff, ctx); 1211 emit_add(RV_REG_T2, RV_REG_T2, RV_REG_T1, ctx); 1212 emit_slli(RV_REG_T2, RV_REG_T2, 8, ctx); 1213 emit_srli(rd, rd, 8, ctx); 1214 if (imm == 16) 1215 goto out_be; 1216 1217 emit_andi(RV_REG_T1, rd, 0xff, ctx); 1218 emit_add(RV_REG_T2, RV_REG_T2, RV_REG_T1, ctx); 1219 emit_slli(RV_REG_T2, RV_REG_T2, 8, ctx); 1220 emit_srli(rd, rd, 8, ctx); 1221 1222 emit_andi(RV_REG_T1, rd, 0xff, ctx); 1223 emit_add(RV_REG_T2, RV_REG_T2, RV_REG_T1, ctx); 1224 emit_slli(RV_REG_T2, RV_REG_T2, 8, ctx); 1225 emit_srli(rd, rd, 8, ctx); 1226 if (imm == 32) 1227 goto out_be; 1228 1229 emit_andi(RV_REG_T1, rd, 0xff, ctx); 1230 emit_add(RV_REG_T2, RV_REG_T2, RV_REG_T1, ctx); 1231 emit_slli(RV_REG_T2, RV_REG_T2, 8, ctx); 1232 emit_srli(rd, rd, 8, ctx); 1233 1234 emit_andi(RV_REG_T1, rd, 0xff, ctx); 1235 emit_add(RV_REG_T2, RV_REG_T2, RV_REG_T1, ctx); 1236 emit_slli(RV_REG_T2, RV_REG_T2, 8, ctx); 1237 emit_srli(rd, rd, 8, ctx); 1238 1239 emit_andi(RV_REG_T1, rd, 0xff, ctx); 1240 emit_add(RV_REG_T2, RV_REG_T2, RV_REG_T1, ctx); 1241 emit_slli(RV_REG_T2, RV_REG_T2, 8, ctx); 1242 emit_srli(rd, rd, 8, ctx); 1243 1244 emit_andi(RV_REG_T1, rd, 0xff, ctx); 1245 emit_add(RV_REG_T2, RV_REG_T2, RV_REG_T1, ctx); 1246 emit_slli(RV_REG_T2, RV_REG_T2, 8, ctx); 1247 emit_srli(rd, rd, 8, ctx); 1248 out_be: 1249 emit_andi(RV_REG_T1, rd, 0xff, ctx); 1250 emit_add(RV_REG_T2, RV_REG_T2, RV_REG_T1, ctx); 1251 1252 emit_mv(rd, RV_REG_T2, ctx); 1253 break; 1254 1255 /* dst = imm */ 1256 case BPF_ALU | BPF_MOV | BPF_K: 1257 case BPF_ALU64 | BPF_MOV | BPF_K: 1258 emit_imm(rd, imm, ctx); 1259 if (!is64 && !aux->verifier_zext) 1260 emit_zext_32(rd, ctx); 1261 break; 1262 1263 /* dst = dst OP imm */ 1264 case BPF_ALU | BPF_ADD | BPF_K: 1265 case BPF_ALU64 | BPF_ADD | BPF_K: 1266 if (is_12b_int(imm)) { 1267 emit_addi(rd, rd, imm, ctx); 1268 } else { 1269 emit_imm(RV_REG_T1, imm, ctx); 1270 emit_add(rd, rd, RV_REG_T1, ctx); 1271 } 1272 if (!is64 && !aux->verifier_zext) 1273 emit_zext_32(rd, ctx); 1274 break; 1275 case BPF_ALU | BPF_SUB | BPF_K: 1276 case BPF_ALU64 | BPF_SUB | BPF_K: 1277 if (is_12b_int(-imm)) { 1278 emit_addi(rd, rd, -imm, ctx); 1279 } else { 1280 emit_imm(RV_REG_T1, imm, ctx); 1281 emit_sub(rd, rd, RV_REG_T1, ctx); 1282 } 1283 if (!is64 && !aux->verifier_zext) 1284 emit_zext_32(rd, ctx); 1285 break; 1286 case BPF_ALU | BPF_AND | BPF_K: 1287 case BPF_ALU64 | BPF_AND | BPF_K: 1288 if (is_12b_int(imm)) { 1289 emit_andi(rd, rd, imm, ctx); 1290 } else { 1291 emit_imm(RV_REG_T1, imm, ctx); 1292 emit_and(rd, rd, RV_REG_T1, ctx); 1293 } 1294 if (!is64 && !aux->verifier_zext) 1295 emit_zext_32(rd, ctx); 1296 break; 1297 case BPF_ALU | BPF_OR | BPF_K: 1298 case BPF_ALU64 | BPF_OR | BPF_K: 1299 if (is_12b_int(imm)) { 1300 emit(rv_ori(rd, rd, imm), ctx); 1301 } else { 1302 emit_imm(RV_REG_T1, imm, ctx); 1303 emit_or(rd, rd, RV_REG_T1, ctx); 1304 } 1305 if (!is64 && !aux->verifier_zext) 1306 emit_zext_32(rd, ctx); 1307 break; 1308 case BPF_ALU | BPF_XOR | BPF_K: 1309 case BPF_ALU64 | BPF_XOR | BPF_K: 1310 if (is_12b_int(imm)) { 1311 emit(rv_xori(rd, rd, imm), ctx); 1312 } else { 1313 emit_imm(RV_REG_T1, imm, ctx); 1314 emit_xor(rd, rd, RV_REG_T1, ctx); 1315 } 1316 if (!is64 && !aux->verifier_zext) 1317 emit_zext_32(rd, ctx); 1318 break; 1319 case BPF_ALU | BPF_MUL | BPF_K: 1320 case BPF_ALU64 | BPF_MUL | BPF_K: 1321 emit_imm(RV_REG_T1, imm, ctx); 1322 emit(is64 ? rv_mul(rd, rd, RV_REG_T1) : 1323 rv_mulw(rd, rd, RV_REG_T1), ctx); 1324 if (!is64 && !aux->verifier_zext) 1325 emit_zext_32(rd, ctx); 1326 break; 1327 case BPF_ALU | BPF_DIV | BPF_K: 1328 case BPF_ALU64 | BPF_DIV | BPF_K: 1329 emit_imm(RV_REG_T1, imm, ctx); 1330 if (off) 1331 emit(is64 ? rv_div(rd, rd, RV_REG_T1) : 1332 rv_divw(rd, rd, RV_REG_T1), ctx); 1333 else 1334 emit(is64 ? rv_divu(rd, rd, RV_REG_T1) : 1335 rv_divuw(rd, rd, RV_REG_T1), ctx); 1336 if (!is64 && !aux->verifier_zext) 1337 emit_zext_32(rd, ctx); 1338 break; 1339 case BPF_ALU | BPF_MOD | BPF_K: 1340 case BPF_ALU64 | BPF_MOD | BPF_K: 1341 emit_imm(RV_REG_T1, imm, ctx); 1342 if (off) 1343 emit(is64 ? rv_rem(rd, rd, RV_REG_T1) : 1344 rv_remw(rd, rd, RV_REG_T1), ctx); 1345 else 1346 emit(is64 ? rv_remu(rd, rd, RV_REG_T1) : 1347 rv_remuw(rd, rd, RV_REG_T1), ctx); 1348 if (!is64 && !aux->verifier_zext) 1349 emit_zext_32(rd, ctx); 1350 break; 1351 case BPF_ALU | BPF_LSH | BPF_K: 1352 case BPF_ALU64 | BPF_LSH | BPF_K: 1353 emit_slli(rd, rd, imm, ctx); 1354 1355 if (!is64 && !aux->verifier_zext) 1356 emit_zext_32(rd, ctx); 1357 break; 1358 case BPF_ALU | BPF_RSH | BPF_K: 1359 case BPF_ALU64 | BPF_RSH | BPF_K: 1360 if (is64) 1361 emit_srli(rd, rd, imm, ctx); 1362 else 1363 emit(rv_srliw(rd, rd, imm), ctx); 1364 1365 if (!is64 && !aux->verifier_zext) 1366 emit_zext_32(rd, ctx); 1367 break; 1368 case BPF_ALU | BPF_ARSH | BPF_K: 1369 case BPF_ALU64 | BPF_ARSH | BPF_K: 1370 if (is64) 1371 emit_srai(rd, rd, imm, ctx); 1372 else 1373 emit(rv_sraiw(rd, rd, imm), ctx); 1374 1375 if (!is64 && !aux->verifier_zext) 1376 emit_zext_32(rd, ctx); 1377 break; 1378 1379 /* JUMP off */ 1380 case BPF_JMP | BPF_JA: 1381 case BPF_JMP32 | BPF_JA: 1382 if (BPF_CLASS(code) == BPF_JMP) 1383 rvoff = rv_offset(i, off, ctx); 1384 else 1385 rvoff = rv_offset(i, imm, ctx); 1386 ret = emit_jump_and_link(RV_REG_ZERO, rvoff, true, ctx); 1387 if (ret) 1388 return ret; 1389 break; 1390 1391 /* IF (dst COND src) JUMP off */ 1392 case BPF_JMP | BPF_JEQ | BPF_X: 1393 case BPF_JMP32 | BPF_JEQ | BPF_X: 1394 case BPF_JMP | BPF_JGT | BPF_X: 1395 case BPF_JMP32 | BPF_JGT | BPF_X: 1396 case BPF_JMP | BPF_JLT | BPF_X: 1397 case BPF_JMP32 | BPF_JLT | BPF_X: 1398 case BPF_JMP | BPF_JGE | BPF_X: 1399 case BPF_JMP32 | BPF_JGE | BPF_X: 1400 case BPF_JMP | BPF_JLE | BPF_X: 1401 case BPF_JMP32 | BPF_JLE | BPF_X: 1402 case BPF_JMP | BPF_JNE | BPF_X: 1403 case BPF_JMP32 | BPF_JNE | BPF_X: 1404 case BPF_JMP | BPF_JSGT | BPF_X: 1405 case BPF_JMP32 | BPF_JSGT | BPF_X: 1406 case BPF_JMP | BPF_JSLT | BPF_X: 1407 case BPF_JMP32 | BPF_JSLT | BPF_X: 1408 case BPF_JMP | BPF_JSGE | BPF_X: 1409 case BPF_JMP32 | BPF_JSGE | BPF_X: 1410 case BPF_JMP | BPF_JSLE | BPF_X: 1411 case BPF_JMP32 | BPF_JSLE | BPF_X: 1412 case BPF_JMP | BPF_JSET | BPF_X: 1413 case BPF_JMP32 | BPF_JSET | BPF_X: 1414 rvoff = rv_offset(i, off, ctx); 1415 if (!is64) { 1416 s = ctx->ninsns; 1417 if (is_signed_bpf_cond(BPF_OP(code))) 1418 emit_sext_32_rd_rs(&rd, &rs, ctx); 1419 else 1420 emit_zext_32_rd_rs(&rd, &rs, ctx); 1421 e = ctx->ninsns; 1422 1423 /* Adjust for extra insns */ 1424 rvoff -= ninsns_rvoff(e - s); 1425 } 1426 1427 if (BPF_OP(code) == BPF_JSET) { 1428 /* Adjust for and */ 1429 rvoff -= 4; 1430 emit_and(RV_REG_T1, rd, rs, ctx); 1431 emit_branch(BPF_JNE, RV_REG_T1, RV_REG_ZERO, rvoff, 1432 ctx); 1433 } else { 1434 emit_branch(BPF_OP(code), rd, rs, rvoff, ctx); 1435 } 1436 break; 1437 1438 /* IF (dst COND imm) JUMP off */ 1439 case BPF_JMP | BPF_JEQ | BPF_K: 1440 case BPF_JMP32 | BPF_JEQ | BPF_K: 1441 case BPF_JMP | BPF_JGT | BPF_K: 1442 case BPF_JMP32 | BPF_JGT | BPF_K: 1443 case BPF_JMP | BPF_JLT | BPF_K: 1444 case BPF_JMP32 | BPF_JLT | BPF_K: 1445 case BPF_JMP | BPF_JGE | BPF_K: 1446 case BPF_JMP32 | BPF_JGE | BPF_K: 1447 case BPF_JMP | BPF_JLE | BPF_K: 1448 case BPF_JMP32 | BPF_JLE | BPF_K: 1449 case BPF_JMP | BPF_JNE | BPF_K: 1450 case BPF_JMP32 | BPF_JNE | BPF_K: 1451 case BPF_JMP | BPF_JSGT | BPF_K: 1452 case BPF_JMP32 | BPF_JSGT | BPF_K: 1453 case BPF_JMP | BPF_JSLT | BPF_K: 1454 case BPF_JMP32 | BPF_JSLT | BPF_K: 1455 case BPF_JMP | BPF_JSGE | BPF_K: 1456 case BPF_JMP32 | BPF_JSGE | BPF_K: 1457 case BPF_JMP | BPF_JSLE | BPF_K: 1458 case BPF_JMP32 | BPF_JSLE | BPF_K: 1459 rvoff = rv_offset(i, off, ctx); 1460 s = ctx->ninsns; 1461 if (imm) { 1462 emit_imm(RV_REG_T1, imm, ctx); 1463 rs = RV_REG_T1; 1464 } else { 1465 /* If imm is 0, simply use zero register. */ 1466 rs = RV_REG_ZERO; 1467 } 1468 if (!is64) { 1469 if (is_signed_bpf_cond(BPF_OP(code))) 1470 emit_sext_32_rd(&rd, ctx); 1471 else 1472 emit_zext_32_rd_t1(&rd, ctx); 1473 } 1474 e = ctx->ninsns; 1475 1476 /* Adjust for extra insns */ 1477 rvoff -= ninsns_rvoff(e - s); 1478 emit_branch(BPF_OP(code), rd, rs, rvoff, ctx); 1479 break; 1480 1481 case BPF_JMP | BPF_JSET | BPF_K: 1482 case BPF_JMP32 | BPF_JSET | BPF_K: 1483 rvoff = rv_offset(i, off, ctx); 1484 s = ctx->ninsns; 1485 if (is_12b_int(imm)) { 1486 emit_andi(RV_REG_T1, rd, imm, ctx); 1487 } else { 1488 emit_imm(RV_REG_T1, imm, ctx); 1489 emit_and(RV_REG_T1, rd, RV_REG_T1, ctx); 1490 } 1491 /* For jset32, we should clear the upper 32 bits of t1, but 1492 * sign-extension is sufficient here and saves one instruction, 1493 * as t1 is used only in comparison against zero. 1494 */ 1495 if (!is64 && imm < 0) 1496 emit_addiw(RV_REG_T1, RV_REG_T1, 0, ctx); 1497 e = ctx->ninsns; 1498 rvoff -= ninsns_rvoff(e - s); 1499 emit_branch(BPF_JNE, RV_REG_T1, RV_REG_ZERO, rvoff, ctx); 1500 break; 1501 1502 /* function call */ 1503 case BPF_JMP | BPF_CALL: 1504 { 1505 bool fixed_addr; 1506 u64 addr; 1507 1508 mark_call(ctx); 1509 ret = bpf_jit_get_func_addr(ctx->prog, insn, extra_pass, 1510 &addr, &fixed_addr); 1511 if (ret < 0) 1512 return ret; 1513 1514 ret = emit_call(addr, fixed_addr, ctx); 1515 if (ret) 1516 return ret; 1517 1518 emit_mv(bpf_to_rv_reg(BPF_REG_0, ctx), RV_REG_A0, ctx); 1519 break; 1520 } 1521 /* tail call */ 1522 case BPF_JMP | BPF_TAIL_CALL: 1523 if (emit_bpf_tail_call(i, ctx)) 1524 return -1; 1525 break; 1526 1527 /* function return */ 1528 case BPF_JMP | BPF_EXIT: 1529 if (i == ctx->prog->len - 1) 1530 break; 1531 1532 rvoff = epilogue_offset(ctx); 1533 ret = emit_jump_and_link(RV_REG_ZERO, rvoff, true, ctx); 1534 if (ret) 1535 return ret; 1536 break; 1537 1538 /* dst = imm64 */ 1539 case BPF_LD | BPF_IMM | BPF_DW: 1540 { 1541 struct bpf_insn insn1 = insn[1]; 1542 u64 imm64; 1543 1544 imm64 = (u64)insn1.imm << 32 | (u32)imm; 1545 if (bpf_pseudo_func(insn)) { 1546 /* fixed-length insns for extra jit pass */ 1547 ret = emit_addr(rd, imm64, extra_pass, ctx); 1548 if (ret) 1549 return ret; 1550 } else { 1551 emit_imm(rd, imm64, ctx); 1552 } 1553 1554 return 1; 1555 } 1556 1557 /* LDX: dst = *(unsigned size *)(src + off) */ 1558 case BPF_LDX | BPF_MEM | BPF_B: 1559 case BPF_LDX | BPF_MEM | BPF_H: 1560 case BPF_LDX | BPF_MEM | BPF_W: 1561 case BPF_LDX | BPF_MEM | BPF_DW: 1562 case BPF_LDX | BPF_PROBE_MEM | BPF_B: 1563 case BPF_LDX | BPF_PROBE_MEM | BPF_H: 1564 case BPF_LDX | BPF_PROBE_MEM | BPF_W: 1565 case BPF_LDX | BPF_PROBE_MEM | BPF_DW: 1566 /* LDSX: dst = *(signed size *)(src + off) */ 1567 case BPF_LDX | BPF_MEMSX | BPF_B: 1568 case BPF_LDX | BPF_MEMSX | BPF_H: 1569 case BPF_LDX | BPF_MEMSX | BPF_W: 1570 case BPF_LDX | BPF_PROBE_MEMSX | BPF_B: 1571 case BPF_LDX | BPF_PROBE_MEMSX | BPF_H: 1572 case BPF_LDX | BPF_PROBE_MEMSX | BPF_W: 1573 { 1574 int insn_len, insns_start; 1575 bool sign_ext; 1576 1577 sign_ext = BPF_MODE(insn->code) == BPF_MEMSX || 1578 BPF_MODE(insn->code) == BPF_PROBE_MEMSX; 1579 1580 switch (BPF_SIZE(code)) { 1581 case BPF_B: 1582 if (is_12b_int(off)) { 1583 insns_start = ctx->ninsns; 1584 if (sign_ext) 1585 emit(rv_lb(rd, off, rs), ctx); 1586 else 1587 emit(rv_lbu(rd, off, rs), ctx); 1588 insn_len = ctx->ninsns - insns_start; 1589 break; 1590 } 1591 1592 emit_imm(RV_REG_T1, off, ctx); 1593 emit_add(RV_REG_T1, RV_REG_T1, rs, ctx); 1594 insns_start = ctx->ninsns; 1595 if (sign_ext) 1596 emit(rv_lb(rd, 0, RV_REG_T1), ctx); 1597 else 1598 emit(rv_lbu(rd, 0, RV_REG_T1), ctx); 1599 insn_len = ctx->ninsns - insns_start; 1600 break; 1601 case BPF_H: 1602 if (is_12b_int(off)) { 1603 insns_start = ctx->ninsns; 1604 if (sign_ext) 1605 emit(rv_lh(rd, off, rs), ctx); 1606 else 1607 emit(rv_lhu(rd, off, rs), ctx); 1608 insn_len = ctx->ninsns - insns_start; 1609 break; 1610 } 1611 1612 emit_imm(RV_REG_T1, off, ctx); 1613 emit_add(RV_REG_T1, RV_REG_T1, rs, ctx); 1614 insns_start = ctx->ninsns; 1615 if (sign_ext) 1616 emit(rv_lh(rd, 0, RV_REG_T1), ctx); 1617 else 1618 emit(rv_lhu(rd, 0, RV_REG_T1), ctx); 1619 insn_len = ctx->ninsns - insns_start; 1620 break; 1621 case BPF_W: 1622 if (is_12b_int(off)) { 1623 insns_start = ctx->ninsns; 1624 if (sign_ext) 1625 emit(rv_lw(rd, off, rs), ctx); 1626 else 1627 emit(rv_lwu(rd, off, rs), ctx); 1628 insn_len = ctx->ninsns - insns_start; 1629 break; 1630 } 1631 1632 emit_imm(RV_REG_T1, off, ctx); 1633 emit_add(RV_REG_T1, RV_REG_T1, rs, ctx); 1634 insns_start = ctx->ninsns; 1635 if (sign_ext) 1636 emit(rv_lw(rd, 0, RV_REG_T1), ctx); 1637 else 1638 emit(rv_lwu(rd, 0, RV_REG_T1), ctx); 1639 insn_len = ctx->ninsns - insns_start; 1640 break; 1641 case BPF_DW: 1642 if (is_12b_int(off)) { 1643 insns_start = ctx->ninsns; 1644 emit_ld(rd, off, rs, ctx); 1645 insn_len = ctx->ninsns - insns_start; 1646 break; 1647 } 1648 1649 emit_imm(RV_REG_T1, off, ctx); 1650 emit_add(RV_REG_T1, RV_REG_T1, rs, ctx); 1651 insns_start = ctx->ninsns; 1652 emit_ld(rd, 0, RV_REG_T1, ctx); 1653 insn_len = ctx->ninsns - insns_start; 1654 break; 1655 } 1656 1657 ret = add_exception_handler(insn, ctx, rd, insn_len); 1658 if (ret) 1659 return ret; 1660 1661 if (BPF_SIZE(code) != BPF_DW && insn_is_zext(&insn[1])) 1662 return 1; 1663 break; 1664 } 1665 /* speculation barrier */ 1666 case BPF_ST | BPF_NOSPEC: 1667 break; 1668 1669 /* ST: *(size *)(dst + off) = imm */ 1670 case BPF_ST | BPF_MEM | BPF_B: 1671 emit_imm(RV_REG_T1, imm, ctx); 1672 if (is_12b_int(off)) { 1673 emit(rv_sb(rd, off, RV_REG_T1), ctx); 1674 break; 1675 } 1676 1677 emit_imm(RV_REG_T2, off, ctx); 1678 emit_add(RV_REG_T2, RV_REG_T2, rd, ctx); 1679 emit(rv_sb(RV_REG_T2, 0, RV_REG_T1), ctx); 1680 break; 1681 1682 case BPF_ST | BPF_MEM | BPF_H: 1683 emit_imm(RV_REG_T1, imm, ctx); 1684 if (is_12b_int(off)) { 1685 emit(rv_sh(rd, off, RV_REG_T1), ctx); 1686 break; 1687 } 1688 1689 emit_imm(RV_REG_T2, off, ctx); 1690 emit_add(RV_REG_T2, RV_REG_T2, rd, ctx); 1691 emit(rv_sh(RV_REG_T2, 0, RV_REG_T1), ctx); 1692 break; 1693 case BPF_ST | BPF_MEM | BPF_W: 1694 emit_imm(RV_REG_T1, imm, ctx); 1695 if (is_12b_int(off)) { 1696 emit_sw(rd, off, RV_REG_T1, ctx); 1697 break; 1698 } 1699 1700 emit_imm(RV_REG_T2, off, ctx); 1701 emit_add(RV_REG_T2, RV_REG_T2, rd, ctx); 1702 emit_sw(RV_REG_T2, 0, RV_REG_T1, ctx); 1703 break; 1704 case BPF_ST | BPF_MEM | BPF_DW: 1705 emit_imm(RV_REG_T1, imm, ctx); 1706 if (is_12b_int(off)) { 1707 emit_sd(rd, off, RV_REG_T1, ctx); 1708 break; 1709 } 1710 1711 emit_imm(RV_REG_T2, off, ctx); 1712 emit_add(RV_REG_T2, RV_REG_T2, rd, ctx); 1713 emit_sd(RV_REG_T2, 0, RV_REG_T1, ctx); 1714 break; 1715 1716 /* STX: *(size *)(dst + off) = src */ 1717 case BPF_STX | BPF_MEM | BPF_B: 1718 if (is_12b_int(off)) { 1719 emit(rv_sb(rd, off, rs), ctx); 1720 break; 1721 } 1722 1723 emit_imm(RV_REG_T1, off, ctx); 1724 emit_add(RV_REG_T1, RV_REG_T1, rd, ctx); 1725 emit(rv_sb(RV_REG_T1, 0, rs), ctx); 1726 break; 1727 case BPF_STX | BPF_MEM | BPF_H: 1728 if (is_12b_int(off)) { 1729 emit(rv_sh(rd, off, rs), ctx); 1730 break; 1731 } 1732 1733 emit_imm(RV_REG_T1, off, ctx); 1734 emit_add(RV_REG_T1, RV_REG_T1, rd, ctx); 1735 emit(rv_sh(RV_REG_T1, 0, rs), ctx); 1736 break; 1737 case BPF_STX | BPF_MEM | BPF_W: 1738 if (is_12b_int(off)) { 1739 emit_sw(rd, off, rs, ctx); 1740 break; 1741 } 1742 1743 emit_imm(RV_REG_T1, off, ctx); 1744 emit_add(RV_REG_T1, RV_REG_T1, rd, ctx); 1745 emit_sw(RV_REG_T1, 0, rs, ctx); 1746 break; 1747 case BPF_STX | BPF_MEM | BPF_DW: 1748 if (is_12b_int(off)) { 1749 emit_sd(rd, off, rs, ctx); 1750 break; 1751 } 1752 1753 emit_imm(RV_REG_T1, off, ctx); 1754 emit_add(RV_REG_T1, RV_REG_T1, rd, ctx); 1755 emit_sd(RV_REG_T1, 0, rs, ctx); 1756 break; 1757 case BPF_STX | BPF_ATOMIC | BPF_W: 1758 case BPF_STX | BPF_ATOMIC | BPF_DW: 1759 emit_atomic(rd, rs, off, imm, 1760 BPF_SIZE(code) == BPF_DW, ctx); 1761 break; 1762 default: 1763 pr_err("bpf-jit: unknown opcode %02x\n", code); 1764 return -EINVAL; 1765 } 1766 1767 return 0; 1768 } 1769 1770 void bpf_jit_build_prologue(struct rv_jit_context *ctx) 1771 { 1772 int i, stack_adjust = 0, store_offset, bpf_stack_adjust; 1773 1774 bpf_stack_adjust = round_up(ctx->prog->aux->stack_depth, 16); 1775 if (bpf_stack_adjust) 1776 mark_fp(ctx); 1777 1778 if (seen_reg(RV_REG_RA, ctx)) 1779 stack_adjust += 8; 1780 stack_adjust += 8; /* RV_REG_FP */ 1781 if (seen_reg(RV_REG_S1, ctx)) 1782 stack_adjust += 8; 1783 if (seen_reg(RV_REG_S2, ctx)) 1784 stack_adjust += 8; 1785 if (seen_reg(RV_REG_S3, ctx)) 1786 stack_adjust += 8; 1787 if (seen_reg(RV_REG_S4, ctx)) 1788 stack_adjust += 8; 1789 if (seen_reg(RV_REG_S5, ctx)) 1790 stack_adjust += 8; 1791 if (seen_reg(RV_REG_S6, ctx)) 1792 stack_adjust += 8; 1793 1794 stack_adjust = round_up(stack_adjust, 16); 1795 stack_adjust += bpf_stack_adjust; 1796 1797 store_offset = stack_adjust - 8; 1798 1799 /* nops reserved for auipc+jalr pair */ 1800 for (i = 0; i < RV_FENTRY_NINSNS; i++) 1801 emit(rv_nop(), ctx); 1802 1803 /* First instruction is always setting the tail-call-counter 1804 * (TCC) register. This instruction is skipped for tail calls. 1805 * Force using a 4-byte (non-compressed) instruction. 1806 */ 1807 emit(rv_addi(RV_REG_TCC, RV_REG_ZERO, MAX_TAIL_CALL_CNT), ctx); 1808 1809 emit_addi(RV_REG_SP, RV_REG_SP, -stack_adjust, ctx); 1810 1811 if (seen_reg(RV_REG_RA, ctx)) { 1812 emit_sd(RV_REG_SP, store_offset, RV_REG_RA, ctx); 1813 store_offset -= 8; 1814 } 1815 emit_sd(RV_REG_SP, store_offset, RV_REG_FP, ctx); 1816 store_offset -= 8; 1817 if (seen_reg(RV_REG_S1, ctx)) { 1818 emit_sd(RV_REG_SP, store_offset, RV_REG_S1, ctx); 1819 store_offset -= 8; 1820 } 1821 if (seen_reg(RV_REG_S2, ctx)) { 1822 emit_sd(RV_REG_SP, store_offset, RV_REG_S2, ctx); 1823 store_offset -= 8; 1824 } 1825 if (seen_reg(RV_REG_S3, ctx)) { 1826 emit_sd(RV_REG_SP, store_offset, RV_REG_S3, ctx); 1827 store_offset -= 8; 1828 } 1829 if (seen_reg(RV_REG_S4, ctx)) { 1830 emit_sd(RV_REG_SP, store_offset, RV_REG_S4, ctx); 1831 store_offset -= 8; 1832 } 1833 if (seen_reg(RV_REG_S5, ctx)) { 1834 emit_sd(RV_REG_SP, store_offset, RV_REG_S5, ctx); 1835 store_offset -= 8; 1836 } 1837 if (seen_reg(RV_REG_S6, ctx)) { 1838 emit_sd(RV_REG_SP, store_offset, RV_REG_S6, ctx); 1839 store_offset -= 8; 1840 } 1841 1842 emit_addi(RV_REG_FP, RV_REG_SP, stack_adjust, ctx); 1843 1844 if (bpf_stack_adjust) 1845 emit_addi(RV_REG_S5, RV_REG_SP, bpf_stack_adjust, ctx); 1846 1847 /* Program contains calls and tail calls, so RV_REG_TCC need 1848 * to be saved across calls. 1849 */ 1850 if (seen_tail_call(ctx) && seen_call(ctx)) 1851 emit_mv(RV_REG_TCC_SAVED, RV_REG_TCC, ctx); 1852 1853 ctx->stack_size = stack_adjust; 1854 } 1855 1856 void bpf_jit_build_epilogue(struct rv_jit_context *ctx) 1857 { 1858 __build_epilogue(false, ctx); 1859 } 1860 1861 bool bpf_jit_supports_kfunc_call(void) 1862 { 1863 return true; 1864 } 1865