1 /* 2 * Support PCI/PCIe on PowerNV platforms 3 * 4 * Copyright 2011 Benjamin Herrenschmidt, IBM Corp. 5 * 6 * This program is free software; you can redistribute it and/or 7 * modify it under the terms of the GNU General Public License 8 * as published by the Free Software Foundation; either version 9 * 2 of the License, or (at your option) any later version. 10 */ 11 12 #undef DEBUG 13 14 #include <linux/kernel.h> 15 #include <linux/pci.h> 16 #include <linux/crash_dump.h> 17 #include <linux/debugfs.h> 18 #include <linux/delay.h> 19 #include <linux/string.h> 20 #include <linux/init.h> 21 #include <linux/bootmem.h> 22 #include <linux/irq.h> 23 #include <linux/io.h> 24 #include <linux/msi.h> 25 #include <linux/memblock.h> 26 #include <linux/iommu.h> 27 #include <linux/rculist.h> 28 #include <linux/sizes.h> 29 30 #include <asm/sections.h> 31 #include <asm/io.h> 32 #include <asm/prom.h> 33 #include <asm/pci-bridge.h> 34 #include <asm/machdep.h> 35 #include <asm/msi_bitmap.h> 36 #include <asm/ppc-pci.h> 37 #include <asm/opal.h> 38 #include <asm/iommu.h> 39 #include <asm/tce.h> 40 #include <asm/xics.h> 41 #include <asm/debug.h> 42 #include <asm/firmware.h> 43 #include <asm/pnv-pci.h> 44 #include <asm/mmzone.h> 45 46 #include <misc/cxl-base.h> 47 48 #include "powernv.h" 49 #include "pci.h" 50 51 #define PNV_IODA1_M64_NUM 16 /* Number of M64 BARs */ 52 #define PNV_IODA1_M64_SEGS 8 /* Segments per M64 BAR */ 53 #define PNV_IODA1_DMA32_SEGSIZE 0x10000000 54 55 #define POWERNV_IOMMU_DEFAULT_LEVELS 1 56 #define POWERNV_IOMMU_MAX_LEVELS 5 57 58 static void pnv_pci_ioda2_table_free_pages(struct iommu_table *tbl); 59 60 static void pe_level_printk(const struct pnv_ioda_pe *pe, const char *level, 61 const char *fmt, ...) 62 { 63 struct va_format vaf; 64 va_list args; 65 char pfix[32]; 66 67 va_start(args, fmt); 68 69 vaf.fmt = fmt; 70 vaf.va = &args; 71 72 if (pe->flags & PNV_IODA_PE_DEV) 73 strlcpy(pfix, dev_name(&pe->pdev->dev), sizeof(pfix)); 74 else if (pe->flags & (PNV_IODA_PE_BUS | PNV_IODA_PE_BUS_ALL)) 75 sprintf(pfix, "%04x:%02x ", 76 pci_domain_nr(pe->pbus), pe->pbus->number); 77 #ifdef CONFIG_PCI_IOV 78 else if (pe->flags & PNV_IODA_PE_VF) 79 sprintf(pfix, "%04x:%02x:%2x.%d", 80 pci_domain_nr(pe->parent_dev->bus), 81 (pe->rid & 0xff00) >> 8, 82 PCI_SLOT(pe->rid), PCI_FUNC(pe->rid)); 83 #endif /* CONFIG_PCI_IOV*/ 84 85 printk("%spci %s: [PE# %.3d] %pV", 86 level, pfix, pe->pe_number, &vaf); 87 88 va_end(args); 89 } 90 91 #define pe_err(pe, fmt, ...) \ 92 pe_level_printk(pe, KERN_ERR, fmt, ##__VA_ARGS__) 93 #define pe_warn(pe, fmt, ...) \ 94 pe_level_printk(pe, KERN_WARNING, fmt, ##__VA_ARGS__) 95 #define pe_info(pe, fmt, ...) \ 96 pe_level_printk(pe, KERN_INFO, fmt, ##__VA_ARGS__) 97 98 static bool pnv_iommu_bypass_disabled __read_mostly; 99 100 static int __init iommu_setup(char *str) 101 { 102 if (!str) 103 return -EINVAL; 104 105 while (*str) { 106 if (!strncmp(str, "nobypass", 8)) { 107 pnv_iommu_bypass_disabled = true; 108 pr_info("PowerNV: IOMMU bypass window disabled.\n"); 109 break; 110 } 111 str += strcspn(str, ","); 112 if (*str == ',') 113 str++; 114 } 115 116 return 0; 117 } 118 early_param("iommu", iommu_setup); 119 120 static inline bool pnv_pci_is_mem_pref_64(unsigned long flags) 121 { 122 return ((flags & (IORESOURCE_MEM_64 | IORESOURCE_PREFETCH)) == 123 (IORESOURCE_MEM_64 | IORESOURCE_PREFETCH)); 124 } 125 126 static struct pnv_ioda_pe *pnv_ioda_init_pe(struct pnv_phb *phb, int pe_no) 127 { 128 phb->ioda.pe_array[pe_no].phb = phb; 129 phb->ioda.pe_array[pe_no].pe_number = pe_no; 130 131 return &phb->ioda.pe_array[pe_no]; 132 } 133 134 static void pnv_ioda_reserve_pe(struct pnv_phb *phb, int pe_no) 135 { 136 if (!(pe_no >= 0 && pe_no < phb->ioda.total_pe_num)) { 137 pr_warn("%s: Invalid PE %d on PHB#%x\n", 138 __func__, pe_no, phb->hose->global_number); 139 return; 140 } 141 142 if (test_and_set_bit(pe_no, phb->ioda.pe_alloc)) 143 pr_debug("%s: PE %d was reserved on PHB#%x\n", 144 __func__, pe_no, phb->hose->global_number); 145 146 pnv_ioda_init_pe(phb, pe_no); 147 } 148 149 static struct pnv_ioda_pe *pnv_ioda_alloc_pe(struct pnv_phb *phb) 150 { 151 unsigned long pe; 152 153 do { 154 pe = find_next_zero_bit(phb->ioda.pe_alloc, 155 phb->ioda.total_pe_num, 0); 156 if (pe >= phb->ioda.total_pe_num) 157 return NULL; 158 } while(test_and_set_bit(pe, phb->ioda.pe_alloc)); 159 160 return pnv_ioda_init_pe(phb, pe); 161 } 162 163 static void pnv_ioda_free_pe(struct pnv_ioda_pe *pe) 164 { 165 struct pnv_phb *phb = pe->phb; 166 167 WARN_ON(pe->pdev); 168 169 memset(pe, 0, sizeof(struct pnv_ioda_pe)); 170 clear_bit(pe->pe_number, phb->ioda.pe_alloc); 171 } 172 173 /* The default M64 BAR is shared by all PEs */ 174 static int pnv_ioda2_init_m64(struct pnv_phb *phb) 175 { 176 const char *desc; 177 struct resource *r; 178 s64 rc; 179 180 /* Configure the default M64 BAR */ 181 rc = opal_pci_set_phb_mem_window(phb->opal_id, 182 OPAL_M64_WINDOW_TYPE, 183 phb->ioda.m64_bar_idx, 184 phb->ioda.m64_base, 185 0, /* unused */ 186 phb->ioda.m64_size); 187 if (rc != OPAL_SUCCESS) { 188 desc = "configuring"; 189 goto fail; 190 } 191 192 /* Enable the default M64 BAR */ 193 rc = opal_pci_phb_mmio_enable(phb->opal_id, 194 OPAL_M64_WINDOW_TYPE, 195 phb->ioda.m64_bar_idx, 196 OPAL_ENABLE_M64_SPLIT); 197 if (rc != OPAL_SUCCESS) { 198 desc = "enabling"; 199 goto fail; 200 } 201 202 /* Mark the M64 BAR assigned */ 203 set_bit(phb->ioda.m64_bar_idx, &phb->ioda.m64_bar_alloc); 204 205 /* 206 * Strip off the segment used by the reserved PE, which is 207 * expected to be 0 or last one of PE capabicity. 208 */ 209 r = &phb->hose->mem_resources[1]; 210 if (phb->ioda.reserved_pe_idx == 0) 211 r->start += phb->ioda.m64_segsize; 212 else if (phb->ioda.reserved_pe_idx == (phb->ioda.total_pe_num - 1)) 213 r->end -= phb->ioda.m64_segsize; 214 else 215 pr_warn(" Cannot strip M64 segment for reserved PE#%d\n", 216 phb->ioda.reserved_pe_idx); 217 218 return 0; 219 220 fail: 221 pr_warn(" Failure %lld %s M64 BAR#%d\n", 222 rc, desc, phb->ioda.m64_bar_idx); 223 opal_pci_phb_mmio_enable(phb->opal_id, 224 OPAL_M64_WINDOW_TYPE, 225 phb->ioda.m64_bar_idx, 226 OPAL_DISABLE_M64); 227 return -EIO; 228 } 229 230 static void pnv_ioda_reserve_dev_m64_pe(struct pci_dev *pdev, 231 unsigned long *pe_bitmap) 232 { 233 struct pci_controller *hose = pci_bus_to_host(pdev->bus); 234 struct pnv_phb *phb = hose->private_data; 235 struct resource *r; 236 resource_size_t base, sgsz, start, end; 237 int segno, i; 238 239 base = phb->ioda.m64_base; 240 sgsz = phb->ioda.m64_segsize; 241 for (i = 0; i <= PCI_ROM_RESOURCE; i++) { 242 r = &pdev->resource[i]; 243 if (!r->parent || !pnv_pci_is_mem_pref_64(r->flags)) 244 continue; 245 246 start = _ALIGN_DOWN(r->start - base, sgsz); 247 end = _ALIGN_UP(r->end - base, sgsz); 248 for (segno = start / sgsz; segno < end / sgsz; segno++) { 249 if (pe_bitmap) 250 set_bit(segno, pe_bitmap); 251 else 252 pnv_ioda_reserve_pe(phb, segno); 253 } 254 } 255 } 256 257 static int pnv_ioda1_init_m64(struct pnv_phb *phb) 258 { 259 struct resource *r; 260 int index; 261 262 /* 263 * There are 16 M64 BARs, each of which has 8 segments. So 264 * there are as many M64 segments as the maximum number of 265 * PEs, which is 128. 266 */ 267 for (index = 0; index < PNV_IODA1_M64_NUM; index++) { 268 unsigned long base, segsz = phb->ioda.m64_segsize; 269 int64_t rc; 270 271 base = phb->ioda.m64_base + 272 index * PNV_IODA1_M64_SEGS * segsz; 273 rc = opal_pci_set_phb_mem_window(phb->opal_id, 274 OPAL_M64_WINDOW_TYPE, index, base, 0, 275 PNV_IODA1_M64_SEGS * segsz); 276 if (rc != OPAL_SUCCESS) { 277 pr_warn(" Error %lld setting M64 PHB#%d-BAR#%d\n", 278 rc, phb->hose->global_number, index); 279 goto fail; 280 } 281 282 rc = opal_pci_phb_mmio_enable(phb->opal_id, 283 OPAL_M64_WINDOW_TYPE, index, 284 OPAL_ENABLE_M64_SPLIT); 285 if (rc != OPAL_SUCCESS) { 286 pr_warn(" Error %lld enabling M64 PHB#%d-BAR#%d\n", 287 rc, phb->hose->global_number, index); 288 goto fail; 289 } 290 } 291 292 /* 293 * Exclude the segment used by the reserved PE, which 294 * is expected to be 0 or last supported PE#. 295 */ 296 r = &phb->hose->mem_resources[1]; 297 if (phb->ioda.reserved_pe_idx == 0) 298 r->start += phb->ioda.m64_segsize; 299 else if (phb->ioda.reserved_pe_idx == (phb->ioda.total_pe_num - 1)) 300 r->end -= phb->ioda.m64_segsize; 301 else 302 WARN(1, "Wrong reserved PE#%d on PHB#%d\n", 303 phb->ioda.reserved_pe_idx, phb->hose->global_number); 304 305 return 0; 306 307 fail: 308 for ( ; index >= 0; index--) 309 opal_pci_phb_mmio_enable(phb->opal_id, 310 OPAL_M64_WINDOW_TYPE, index, OPAL_DISABLE_M64); 311 312 return -EIO; 313 } 314 315 static void pnv_ioda_reserve_m64_pe(struct pci_bus *bus, 316 unsigned long *pe_bitmap, 317 bool all) 318 { 319 struct pci_dev *pdev; 320 321 list_for_each_entry(pdev, &bus->devices, bus_list) { 322 pnv_ioda_reserve_dev_m64_pe(pdev, pe_bitmap); 323 324 if (all && pdev->subordinate) 325 pnv_ioda_reserve_m64_pe(pdev->subordinate, 326 pe_bitmap, all); 327 } 328 } 329 330 static struct pnv_ioda_pe *pnv_ioda_pick_m64_pe(struct pci_bus *bus, bool all) 331 { 332 struct pci_controller *hose = pci_bus_to_host(bus); 333 struct pnv_phb *phb = hose->private_data; 334 struct pnv_ioda_pe *master_pe, *pe; 335 unsigned long size, *pe_alloc; 336 int i; 337 338 /* Root bus shouldn't use M64 */ 339 if (pci_is_root_bus(bus)) 340 return NULL; 341 342 /* Allocate bitmap */ 343 size = _ALIGN_UP(phb->ioda.total_pe_num / 8, sizeof(unsigned long)); 344 pe_alloc = kzalloc(size, GFP_KERNEL); 345 if (!pe_alloc) { 346 pr_warn("%s: Out of memory !\n", 347 __func__); 348 return NULL; 349 } 350 351 /* Figure out reserved PE numbers by the PE */ 352 pnv_ioda_reserve_m64_pe(bus, pe_alloc, all); 353 354 /* 355 * the current bus might not own M64 window and that's all 356 * contributed by its child buses. For the case, we needn't 357 * pick M64 dependent PE#. 358 */ 359 if (bitmap_empty(pe_alloc, phb->ioda.total_pe_num)) { 360 kfree(pe_alloc); 361 return NULL; 362 } 363 364 /* 365 * Figure out the master PE and put all slave PEs to master 366 * PE's list to form compound PE. 367 */ 368 master_pe = NULL; 369 i = -1; 370 while ((i = find_next_bit(pe_alloc, phb->ioda.total_pe_num, i + 1)) < 371 phb->ioda.total_pe_num) { 372 pe = &phb->ioda.pe_array[i]; 373 374 phb->ioda.m64_segmap[pe->pe_number] = pe->pe_number; 375 if (!master_pe) { 376 pe->flags |= PNV_IODA_PE_MASTER; 377 INIT_LIST_HEAD(&pe->slaves); 378 master_pe = pe; 379 } else { 380 pe->flags |= PNV_IODA_PE_SLAVE; 381 pe->master = master_pe; 382 list_add_tail(&pe->list, &master_pe->slaves); 383 } 384 385 /* 386 * P7IOC supports M64DT, which helps mapping M64 segment 387 * to one particular PE#. However, PHB3 has fixed mapping 388 * between M64 segment and PE#. In order to have same logic 389 * for P7IOC and PHB3, we enforce fixed mapping between M64 390 * segment and PE# on P7IOC. 391 */ 392 if (phb->type == PNV_PHB_IODA1) { 393 int64_t rc; 394 395 rc = opal_pci_map_pe_mmio_window(phb->opal_id, 396 pe->pe_number, OPAL_M64_WINDOW_TYPE, 397 pe->pe_number / PNV_IODA1_M64_SEGS, 398 pe->pe_number % PNV_IODA1_M64_SEGS); 399 if (rc != OPAL_SUCCESS) 400 pr_warn("%s: Error %lld mapping M64 for PHB#%d-PE#%d\n", 401 __func__, rc, phb->hose->global_number, 402 pe->pe_number); 403 } 404 } 405 406 kfree(pe_alloc); 407 return master_pe; 408 } 409 410 static void __init pnv_ioda_parse_m64_window(struct pnv_phb *phb) 411 { 412 struct pci_controller *hose = phb->hose; 413 struct device_node *dn = hose->dn; 414 struct resource *res; 415 const u32 *r; 416 u64 pci_addr; 417 418 if (phb->type != PNV_PHB_IODA1 && phb->type != PNV_PHB_IODA2) { 419 pr_info(" Not support M64 window\n"); 420 return; 421 } 422 423 if (!firmware_has_feature(FW_FEATURE_OPAL)) { 424 pr_info(" Firmware too old to support M64 window\n"); 425 return; 426 } 427 428 r = of_get_property(dn, "ibm,opal-m64-window", NULL); 429 if (!r) { 430 pr_info(" No <ibm,opal-m64-window> on %s\n", 431 dn->full_name); 432 return; 433 } 434 435 res = &hose->mem_resources[1]; 436 res->name = dn->full_name; 437 res->start = of_translate_address(dn, r + 2); 438 res->end = res->start + of_read_number(r + 4, 2) - 1; 439 res->flags = (IORESOURCE_MEM | IORESOURCE_MEM_64 | IORESOURCE_PREFETCH); 440 pci_addr = of_read_number(r, 2); 441 hose->mem_offset[1] = res->start - pci_addr; 442 443 phb->ioda.m64_size = resource_size(res); 444 phb->ioda.m64_segsize = phb->ioda.m64_size / phb->ioda.total_pe_num; 445 phb->ioda.m64_base = pci_addr; 446 447 pr_info(" MEM64 0x%016llx..0x%016llx -> 0x%016llx\n", 448 res->start, res->end, pci_addr); 449 450 /* Use last M64 BAR to cover M64 window */ 451 phb->ioda.m64_bar_idx = 15; 452 if (phb->type == PNV_PHB_IODA1) 453 phb->init_m64 = pnv_ioda1_init_m64; 454 else 455 phb->init_m64 = pnv_ioda2_init_m64; 456 phb->reserve_m64_pe = pnv_ioda_reserve_m64_pe; 457 phb->pick_m64_pe = pnv_ioda_pick_m64_pe; 458 } 459 460 static void pnv_ioda_freeze_pe(struct pnv_phb *phb, int pe_no) 461 { 462 struct pnv_ioda_pe *pe = &phb->ioda.pe_array[pe_no]; 463 struct pnv_ioda_pe *slave; 464 s64 rc; 465 466 /* Fetch master PE */ 467 if (pe->flags & PNV_IODA_PE_SLAVE) { 468 pe = pe->master; 469 if (WARN_ON(!pe || !(pe->flags & PNV_IODA_PE_MASTER))) 470 return; 471 472 pe_no = pe->pe_number; 473 } 474 475 /* Freeze master PE */ 476 rc = opal_pci_eeh_freeze_set(phb->opal_id, 477 pe_no, 478 OPAL_EEH_ACTION_SET_FREEZE_ALL); 479 if (rc != OPAL_SUCCESS) { 480 pr_warn("%s: Failure %lld freezing PHB#%x-PE#%x\n", 481 __func__, rc, phb->hose->global_number, pe_no); 482 return; 483 } 484 485 /* Freeze slave PEs */ 486 if (!(pe->flags & PNV_IODA_PE_MASTER)) 487 return; 488 489 list_for_each_entry(slave, &pe->slaves, list) { 490 rc = opal_pci_eeh_freeze_set(phb->opal_id, 491 slave->pe_number, 492 OPAL_EEH_ACTION_SET_FREEZE_ALL); 493 if (rc != OPAL_SUCCESS) 494 pr_warn("%s: Failure %lld freezing PHB#%x-PE#%x\n", 495 __func__, rc, phb->hose->global_number, 496 slave->pe_number); 497 } 498 } 499 500 static int pnv_ioda_unfreeze_pe(struct pnv_phb *phb, int pe_no, int opt) 501 { 502 struct pnv_ioda_pe *pe, *slave; 503 s64 rc; 504 505 /* Find master PE */ 506 pe = &phb->ioda.pe_array[pe_no]; 507 if (pe->flags & PNV_IODA_PE_SLAVE) { 508 pe = pe->master; 509 WARN_ON(!pe || !(pe->flags & PNV_IODA_PE_MASTER)); 510 pe_no = pe->pe_number; 511 } 512 513 /* Clear frozen state for master PE */ 514 rc = opal_pci_eeh_freeze_clear(phb->opal_id, pe_no, opt); 515 if (rc != OPAL_SUCCESS) { 516 pr_warn("%s: Failure %lld clear %d on PHB#%x-PE#%x\n", 517 __func__, rc, opt, phb->hose->global_number, pe_no); 518 return -EIO; 519 } 520 521 if (!(pe->flags & PNV_IODA_PE_MASTER)) 522 return 0; 523 524 /* Clear frozen state for slave PEs */ 525 list_for_each_entry(slave, &pe->slaves, list) { 526 rc = opal_pci_eeh_freeze_clear(phb->opal_id, 527 slave->pe_number, 528 opt); 529 if (rc != OPAL_SUCCESS) { 530 pr_warn("%s: Failure %lld clear %d on PHB#%x-PE#%x\n", 531 __func__, rc, opt, phb->hose->global_number, 532 slave->pe_number); 533 return -EIO; 534 } 535 } 536 537 return 0; 538 } 539 540 static int pnv_ioda_get_pe_state(struct pnv_phb *phb, int pe_no) 541 { 542 struct pnv_ioda_pe *slave, *pe; 543 u8 fstate, state; 544 __be16 pcierr; 545 s64 rc; 546 547 /* Sanity check on PE number */ 548 if (pe_no < 0 || pe_no >= phb->ioda.total_pe_num) 549 return OPAL_EEH_STOPPED_PERM_UNAVAIL; 550 551 /* 552 * Fetch the master PE and the PE instance might be 553 * not initialized yet. 554 */ 555 pe = &phb->ioda.pe_array[pe_no]; 556 if (pe->flags & PNV_IODA_PE_SLAVE) { 557 pe = pe->master; 558 WARN_ON(!pe || !(pe->flags & PNV_IODA_PE_MASTER)); 559 pe_no = pe->pe_number; 560 } 561 562 /* Check the master PE */ 563 rc = opal_pci_eeh_freeze_status(phb->opal_id, pe_no, 564 &state, &pcierr, NULL); 565 if (rc != OPAL_SUCCESS) { 566 pr_warn("%s: Failure %lld getting " 567 "PHB#%x-PE#%x state\n", 568 __func__, rc, 569 phb->hose->global_number, pe_no); 570 return OPAL_EEH_STOPPED_TEMP_UNAVAIL; 571 } 572 573 /* Check the slave PE */ 574 if (!(pe->flags & PNV_IODA_PE_MASTER)) 575 return state; 576 577 list_for_each_entry(slave, &pe->slaves, list) { 578 rc = opal_pci_eeh_freeze_status(phb->opal_id, 579 slave->pe_number, 580 &fstate, 581 &pcierr, 582 NULL); 583 if (rc != OPAL_SUCCESS) { 584 pr_warn("%s: Failure %lld getting " 585 "PHB#%x-PE#%x state\n", 586 __func__, rc, 587 phb->hose->global_number, slave->pe_number); 588 return OPAL_EEH_STOPPED_TEMP_UNAVAIL; 589 } 590 591 /* 592 * Override the result based on the ascending 593 * priority. 594 */ 595 if (fstate > state) 596 state = fstate; 597 } 598 599 return state; 600 } 601 602 /* Currently those 2 are only used when MSIs are enabled, this will change 603 * but in the meantime, we need to protect them to avoid warnings 604 */ 605 #ifdef CONFIG_PCI_MSI 606 static struct pnv_ioda_pe *pnv_ioda_get_pe(struct pci_dev *dev) 607 { 608 struct pci_controller *hose = pci_bus_to_host(dev->bus); 609 struct pnv_phb *phb = hose->private_data; 610 struct pci_dn *pdn = pci_get_pdn(dev); 611 612 if (!pdn) 613 return NULL; 614 if (pdn->pe_number == IODA_INVALID_PE) 615 return NULL; 616 return &phb->ioda.pe_array[pdn->pe_number]; 617 } 618 #endif /* CONFIG_PCI_MSI */ 619 620 static int pnv_ioda_set_one_peltv(struct pnv_phb *phb, 621 struct pnv_ioda_pe *parent, 622 struct pnv_ioda_pe *child, 623 bool is_add) 624 { 625 const char *desc = is_add ? "adding" : "removing"; 626 uint8_t op = is_add ? OPAL_ADD_PE_TO_DOMAIN : 627 OPAL_REMOVE_PE_FROM_DOMAIN; 628 struct pnv_ioda_pe *slave; 629 long rc; 630 631 /* Parent PE affects child PE */ 632 rc = opal_pci_set_peltv(phb->opal_id, parent->pe_number, 633 child->pe_number, op); 634 if (rc != OPAL_SUCCESS) { 635 pe_warn(child, "OPAL error %ld %s to parent PELTV\n", 636 rc, desc); 637 return -ENXIO; 638 } 639 640 if (!(child->flags & PNV_IODA_PE_MASTER)) 641 return 0; 642 643 /* Compound case: parent PE affects slave PEs */ 644 list_for_each_entry(slave, &child->slaves, list) { 645 rc = opal_pci_set_peltv(phb->opal_id, parent->pe_number, 646 slave->pe_number, op); 647 if (rc != OPAL_SUCCESS) { 648 pe_warn(slave, "OPAL error %ld %s to parent PELTV\n", 649 rc, desc); 650 return -ENXIO; 651 } 652 } 653 654 return 0; 655 } 656 657 static int pnv_ioda_set_peltv(struct pnv_phb *phb, 658 struct pnv_ioda_pe *pe, 659 bool is_add) 660 { 661 struct pnv_ioda_pe *slave; 662 struct pci_dev *pdev = NULL; 663 int ret; 664 665 /* 666 * Clear PE frozen state. If it's master PE, we need 667 * clear slave PE frozen state as well. 668 */ 669 if (is_add) { 670 opal_pci_eeh_freeze_clear(phb->opal_id, pe->pe_number, 671 OPAL_EEH_ACTION_CLEAR_FREEZE_ALL); 672 if (pe->flags & PNV_IODA_PE_MASTER) { 673 list_for_each_entry(slave, &pe->slaves, list) 674 opal_pci_eeh_freeze_clear(phb->opal_id, 675 slave->pe_number, 676 OPAL_EEH_ACTION_CLEAR_FREEZE_ALL); 677 } 678 } 679 680 /* 681 * Associate PE in PELT. We need add the PE into the 682 * corresponding PELT-V as well. Otherwise, the error 683 * originated from the PE might contribute to other 684 * PEs. 685 */ 686 ret = pnv_ioda_set_one_peltv(phb, pe, pe, is_add); 687 if (ret) 688 return ret; 689 690 /* For compound PEs, any one affects all of them */ 691 if (pe->flags & PNV_IODA_PE_MASTER) { 692 list_for_each_entry(slave, &pe->slaves, list) { 693 ret = pnv_ioda_set_one_peltv(phb, slave, pe, is_add); 694 if (ret) 695 return ret; 696 } 697 } 698 699 if (pe->flags & (PNV_IODA_PE_BUS_ALL | PNV_IODA_PE_BUS)) 700 pdev = pe->pbus->self; 701 else if (pe->flags & PNV_IODA_PE_DEV) 702 pdev = pe->pdev->bus->self; 703 #ifdef CONFIG_PCI_IOV 704 else if (pe->flags & PNV_IODA_PE_VF) 705 pdev = pe->parent_dev; 706 #endif /* CONFIG_PCI_IOV */ 707 while (pdev) { 708 struct pci_dn *pdn = pci_get_pdn(pdev); 709 struct pnv_ioda_pe *parent; 710 711 if (pdn && pdn->pe_number != IODA_INVALID_PE) { 712 parent = &phb->ioda.pe_array[pdn->pe_number]; 713 ret = pnv_ioda_set_one_peltv(phb, parent, pe, is_add); 714 if (ret) 715 return ret; 716 } 717 718 pdev = pdev->bus->self; 719 } 720 721 return 0; 722 } 723 724 #ifdef CONFIG_PCI_IOV 725 static int pnv_ioda_deconfigure_pe(struct pnv_phb *phb, struct pnv_ioda_pe *pe) 726 { 727 struct pci_dev *parent; 728 uint8_t bcomp, dcomp, fcomp; 729 int64_t rc; 730 long rid_end, rid; 731 732 /* Currently, we just deconfigure VF PE. Bus PE will always there.*/ 733 if (pe->pbus) { 734 int count; 735 736 dcomp = OPAL_IGNORE_RID_DEVICE_NUMBER; 737 fcomp = OPAL_IGNORE_RID_FUNCTION_NUMBER; 738 parent = pe->pbus->self; 739 if (pe->flags & PNV_IODA_PE_BUS_ALL) 740 count = pe->pbus->busn_res.end - pe->pbus->busn_res.start + 1; 741 else 742 count = 1; 743 744 switch(count) { 745 case 1: bcomp = OpalPciBusAll; break; 746 case 2: bcomp = OpalPciBus7Bits; break; 747 case 4: bcomp = OpalPciBus6Bits; break; 748 case 8: bcomp = OpalPciBus5Bits; break; 749 case 16: bcomp = OpalPciBus4Bits; break; 750 case 32: bcomp = OpalPciBus3Bits; break; 751 default: 752 dev_err(&pe->pbus->dev, "Number of subordinate buses %d unsupported\n", 753 count); 754 /* Do an exact match only */ 755 bcomp = OpalPciBusAll; 756 } 757 rid_end = pe->rid + (count << 8); 758 } else { 759 if (pe->flags & PNV_IODA_PE_VF) 760 parent = pe->parent_dev; 761 else 762 parent = pe->pdev->bus->self; 763 bcomp = OpalPciBusAll; 764 dcomp = OPAL_COMPARE_RID_DEVICE_NUMBER; 765 fcomp = OPAL_COMPARE_RID_FUNCTION_NUMBER; 766 rid_end = pe->rid + 1; 767 } 768 769 /* Clear the reverse map */ 770 for (rid = pe->rid; rid < rid_end; rid++) 771 phb->ioda.pe_rmap[rid] = 0; 772 773 /* Release from all parents PELT-V */ 774 while (parent) { 775 struct pci_dn *pdn = pci_get_pdn(parent); 776 if (pdn && pdn->pe_number != IODA_INVALID_PE) { 777 rc = opal_pci_set_peltv(phb->opal_id, pdn->pe_number, 778 pe->pe_number, OPAL_REMOVE_PE_FROM_DOMAIN); 779 /* XXX What to do in case of error ? */ 780 } 781 parent = parent->bus->self; 782 } 783 784 opal_pci_eeh_freeze_clear(phb->opal_id, pe->pe_number, 785 OPAL_EEH_ACTION_CLEAR_FREEZE_ALL); 786 787 /* Disassociate PE in PELT */ 788 rc = opal_pci_set_peltv(phb->opal_id, pe->pe_number, 789 pe->pe_number, OPAL_REMOVE_PE_FROM_DOMAIN); 790 if (rc) 791 pe_warn(pe, "OPAL error %ld remove self from PELTV\n", rc); 792 rc = opal_pci_set_pe(phb->opal_id, pe->pe_number, pe->rid, 793 bcomp, dcomp, fcomp, OPAL_UNMAP_PE); 794 if (rc) 795 pe_err(pe, "OPAL error %ld trying to setup PELT table\n", rc); 796 797 pe->pbus = NULL; 798 pe->pdev = NULL; 799 pe->parent_dev = NULL; 800 801 return 0; 802 } 803 #endif /* CONFIG_PCI_IOV */ 804 805 static int pnv_ioda_configure_pe(struct pnv_phb *phb, struct pnv_ioda_pe *pe) 806 { 807 struct pci_dev *parent; 808 uint8_t bcomp, dcomp, fcomp; 809 long rc, rid_end, rid; 810 811 /* Bus validation ? */ 812 if (pe->pbus) { 813 int count; 814 815 dcomp = OPAL_IGNORE_RID_DEVICE_NUMBER; 816 fcomp = OPAL_IGNORE_RID_FUNCTION_NUMBER; 817 parent = pe->pbus->self; 818 if (pe->flags & PNV_IODA_PE_BUS_ALL) 819 count = pe->pbus->busn_res.end - pe->pbus->busn_res.start + 1; 820 else 821 count = 1; 822 823 switch(count) { 824 case 1: bcomp = OpalPciBusAll; break; 825 case 2: bcomp = OpalPciBus7Bits; break; 826 case 4: bcomp = OpalPciBus6Bits; break; 827 case 8: bcomp = OpalPciBus5Bits; break; 828 case 16: bcomp = OpalPciBus4Bits; break; 829 case 32: bcomp = OpalPciBus3Bits; break; 830 default: 831 dev_err(&pe->pbus->dev, "Number of subordinate buses %d unsupported\n", 832 count); 833 /* Do an exact match only */ 834 bcomp = OpalPciBusAll; 835 } 836 rid_end = pe->rid + (count << 8); 837 } else { 838 #ifdef CONFIG_PCI_IOV 839 if (pe->flags & PNV_IODA_PE_VF) 840 parent = pe->parent_dev; 841 else 842 #endif /* CONFIG_PCI_IOV */ 843 parent = pe->pdev->bus->self; 844 bcomp = OpalPciBusAll; 845 dcomp = OPAL_COMPARE_RID_DEVICE_NUMBER; 846 fcomp = OPAL_COMPARE_RID_FUNCTION_NUMBER; 847 rid_end = pe->rid + 1; 848 } 849 850 /* 851 * Associate PE in PELT. We need add the PE into the 852 * corresponding PELT-V as well. Otherwise, the error 853 * originated from the PE might contribute to other 854 * PEs. 855 */ 856 rc = opal_pci_set_pe(phb->opal_id, pe->pe_number, pe->rid, 857 bcomp, dcomp, fcomp, OPAL_MAP_PE); 858 if (rc) { 859 pe_err(pe, "OPAL error %ld trying to setup PELT table\n", rc); 860 return -ENXIO; 861 } 862 863 /* 864 * Configure PELTV. NPUs don't have a PELTV table so skip 865 * configuration on them. 866 */ 867 if (phb->type != PNV_PHB_NPU) 868 pnv_ioda_set_peltv(phb, pe, true); 869 870 /* Setup reverse map */ 871 for (rid = pe->rid; rid < rid_end; rid++) 872 phb->ioda.pe_rmap[rid] = pe->pe_number; 873 874 /* Setup one MVTs on IODA1 */ 875 if (phb->type != PNV_PHB_IODA1) { 876 pe->mve_number = 0; 877 goto out; 878 } 879 880 pe->mve_number = pe->pe_number; 881 rc = opal_pci_set_mve(phb->opal_id, pe->mve_number, pe->pe_number); 882 if (rc != OPAL_SUCCESS) { 883 pe_err(pe, "OPAL error %ld setting up MVE %d\n", 884 rc, pe->mve_number); 885 pe->mve_number = -1; 886 } else { 887 rc = opal_pci_set_mve_enable(phb->opal_id, 888 pe->mve_number, OPAL_ENABLE_MVE); 889 if (rc) { 890 pe_err(pe, "OPAL error %ld enabling MVE %d\n", 891 rc, pe->mve_number); 892 pe->mve_number = -1; 893 } 894 } 895 896 out: 897 return 0; 898 } 899 900 #ifdef CONFIG_PCI_IOV 901 static int pnv_pci_vf_resource_shift(struct pci_dev *dev, int offset) 902 { 903 struct pci_dn *pdn = pci_get_pdn(dev); 904 int i; 905 struct resource *res, res2; 906 resource_size_t size; 907 u16 num_vfs; 908 909 if (!dev->is_physfn) 910 return -EINVAL; 911 912 /* 913 * "offset" is in VFs. The M64 windows are sized so that when they 914 * are segmented, each segment is the same size as the IOV BAR. 915 * Each segment is in a separate PE, and the high order bits of the 916 * address are the PE number. Therefore, each VF's BAR is in a 917 * separate PE, and changing the IOV BAR start address changes the 918 * range of PEs the VFs are in. 919 */ 920 num_vfs = pdn->num_vfs; 921 for (i = 0; i < PCI_SRIOV_NUM_BARS; i++) { 922 res = &dev->resource[i + PCI_IOV_RESOURCES]; 923 if (!res->flags || !res->parent) 924 continue; 925 926 /* 927 * The actual IOV BAR range is determined by the start address 928 * and the actual size for num_vfs VFs BAR. This check is to 929 * make sure that after shifting, the range will not overlap 930 * with another device. 931 */ 932 size = pci_iov_resource_size(dev, i + PCI_IOV_RESOURCES); 933 res2.flags = res->flags; 934 res2.start = res->start + (size * offset); 935 res2.end = res2.start + (size * num_vfs) - 1; 936 937 if (res2.end > res->end) { 938 dev_err(&dev->dev, "VF BAR%d: %pR would extend past %pR (trying to enable %d VFs shifted by %d)\n", 939 i, &res2, res, num_vfs, offset); 940 return -EBUSY; 941 } 942 } 943 944 /* 945 * After doing so, there would be a "hole" in the /proc/iomem when 946 * offset is a positive value. It looks like the device return some 947 * mmio back to the system, which actually no one could use it. 948 */ 949 for (i = 0; i < PCI_SRIOV_NUM_BARS; i++) { 950 res = &dev->resource[i + PCI_IOV_RESOURCES]; 951 if (!res->flags || !res->parent) 952 continue; 953 954 size = pci_iov_resource_size(dev, i + PCI_IOV_RESOURCES); 955 res2 = *res; 956 res->start += size * offset; 957 958 dev_info(&dev->dev, "VF BAR%d: %pR shifted to %pR (%sabling %d VFs shifted by %d)\n", 959 i, &res2, res, (offset > 0) ? "En" : "Dis", 960 num_vfs, offset); 961 pci_update_resource(dev, i + PCI_IOV_RESOURCES); 962 } 963 return 0; 964 } 965 #endif /* CONFIG_PCI_IOV */ 966 967 static struct pnv_ioda_pe *pnv_ioda_setup_dev_PE(struct pci_dev *dev) 968 { 969 struct pci_controller *hose = pci_bus_to_host(dev->bus); 970 struct pnv_phb *phb = hose->private_data; 971 struct pci_dn *pdn = pci_get_pdn(dev); 972 struct pnv_ioda_pe *pe; 973 974 if (!pdn) { 975 pr_err("%s: Device tree node not associated properly\n", 976 pci_name(dev)); 977 return NULL; 978 } 979 if (pdn->pe_number != IODA_INVALID_PE) 980 return NULL; 981 982 pe = pnv_ioda_alloc_pe(phb); 983 if (!pe) { 984 pr_warning("%s: Not enough PE# available, disabling device\n", 985 pci_name(dev)); 986 return NULL; 987 } 988 989 /* NOTE: We get only one ref to the pci_dev for the pdn, not for the 990 * pointer in the PE data structure, both should be destroyed at the 991 * same time. However, this needs to be looked at more closely again 992 * once we actually start removing things (Hotplug, SR-IOV, ...) 993 * 994 * At some point we want to remove the PDN completely anyways 995 */ 996 pci_dev_get(dev); 997 pdn->pcidev = dev; 998 pdn->pe_number = pe->pe_number; 999 pe->flags = PNV_IODA_PE_DEV; 1000 pe->pdev = dev; 1001 pe->pbus = NULL; 1002 pe->mve_number = -1; 1003 pe->rid = dev->bus->number << 8 | pdn->devfn; 1004 1005 pe_info(pe, "Associated device to PE\n"); 1006 1007 if (pnv_ioda_configure_pe(phb, pe)) { 1008 /* XXX What do we do here ? */ 1009 pnv_ioda_free_pe(pe); 1010 pdn->pe_number = IODA_INVALID_PE; 1011 pe->pdev = NULL; 1012 pci_dev_put(dev); 1013 return NULL; 1014 } 1015 1016 return pe; 1017 } 1018 1019 static void pnv_ioda_setup_same_PE(struct pci_bus *bus, struct pnv_ioda_pe *pe) 1020 { 1021 struct pci_dev *dev; 1022 1023 list_for_each_entry(dev, &bus->devices, bus_list) { 1024 struct pci_dn *pdn = pci_get_pdn(dev); 1025 1026 if (pdn == NULL) { 1027 pr_warn("%s: No device node associated with device !\n", 1028 pci_name(dev)); 1029 continue; 1030 } 1031 pdn->pcidev = dev; 1032 pdn->pe_number = pe->pe_number; 1033 if ((pe->flags & PNV_IODA_PE_BUS_ALL) && dev->subordinate) 1034 pnv_ioda_setup_same_PE(dev->subordinate, pe); 1035 } 1036 } 1037 1038 /* 1039 * There're 2 types of PCI bus sensitive PEs: One that is compromised of 1040 * single PCI bus. Another one that contains the primary PCI bus and its 1041 * subordinate PCI devices and buses. The second type of PE is normally 1042 * orgiriated by PCIe-to-PCI bridge or PLX switch downstream ports. 1043 */ 1044 static struct pnv_ioda_pe *pnv_ioda_setup_bus_PE(struct pci_bus *bus, bool all) 1045 { 1046 struct pci_controller *hose = pci_bus_to_host(bus); 1047 struct pnv_phb *phb = hose->private_data; 1048 struct pnv_ioda_pe *pe = NULL; 1049 1050 /* Check if PE is determined by M64 */ 1051 if (phb->pick_m64_pe) 1052 pe = phb->pick_m64_pe(bus, all); 1053 1054 /* The PE number isn't pinned by M64 */ 1055 if (!pe) 1056 pe = pnv_ioda_alloc_pe(phb); 1057 1058 if (!pe) { 1059 pr_warning("%s: Not enough PE# available for PCI bus %04x:%02x\n", 1060 __func__, pci_domain_nr(bus), bus->number); 1061 return NULL; 1062 } 1063 1064 pe->flags |= (all ? PNV_IODA_PE_BUS_ALL : PNV_IODA_PE_BUS); 1065 pe->pbus = bus; 1066 pe->pdev = NULL; 1067 pe->mve_number = -1; 1068 pe->rid = bus->busn_res.start << 8; 1069 1070 if (all) 1071 pe_info(pe, "Secondary bus %d..%d associated with PE#%d\n", 1072 bus->busn_res.start, bus->busn_res.end, pe->pe_number); 1073 else 1074 pe_info(pe, "Secondary bus %d associated with PE#%d\n", 1075 bus->busn_res.start, pe->pe_number); 1076 1077 if (pnv_ioda_configure_pe(phb, pe)) { 1078 /* XXX What do we do here ? */ 1079 pnv_ioda_free_pe(pe); 1080 pe->pbus = NULL; 1081 return NULL; 1082 } 1083 1084 /* Associate it with all child devices */ 1085 pnv_ioda_setup_same_PE(bus, pe); 1086 1087 /* Put PE to the list */ 1088 list_add_tail(&pe->list, &phb->ioda.pe_list); 1089 1090 return pe; 1091 } 1092 1093 static struct pnv_ioda_pe *pnv_ioda_setup_npu_PE(struct pci_dev *npu_pdev) 1094 { 1095 int pe_num, found_pe = false, rc; 1096 long rid; 1097 struct pnv_ioda_pe *pe; 1098 struct pci_dev *gpu_pdev; 1099 struct pci_dn *npu_pdn; 1100 struct pci_controller *hose = pci_bus_to_host(npu_pdev->bus); 1101 struct pnv_phb *phb = hose->private_data; 1102 1103 /* 1104 * Due to a hardware errata PE#0 on the NPU is reserved for 1105 * error handling. This means we only have three PEs remaining 1106 * which need to be assigned to four links, implying some 1107 * links must share PEs. 1108 * 1109 * To achieve this we assign PEs such that NPUs linking the 1110 * same GPU get assigned the same PE. 1111 */ 1112 gpu_pdev = pnv_pci_get_gpu_dev(npu_pdev); 1113 for (pe_num = 0; pe_num < phb->ioda.total_pe_num; pe_num++) { 1114 pe = &phb->ioda.pe_array[pe_num]; 1115 if (!pe->pdev) 1116 continue; 1117 1118 if (pnv_pci_get_gpu_dev(pe->pdev) == gpu_pdev) { 1119 /* 1120 * This device has the same peer GPU so should 1121 * be assigned the same PE as the existing 1122 * peer NPU. 1123 */ 1124 dev_info(&npu_pdev->dev, 1125 "Associating to existing PE %d\n", pe_num); 1126 pci_dev_get(npu_pdev); 1127 npu_pdn = pci_get_pdn(npu_pdev); 1128 rid = npu_pdev->bus->number << 8 | npu_pdn->devfn; 1129 npu_pdn->pcidev = npu_pdev; 1130 npu_pdn->pe_number = pe_num; 1131 phb->ioda.pe_rmap[rid] = pe->pe_number; 1132 1133 /* Map the PE to this link */ 1134 rc = opal_pci_set_pe(phb->opal_id, pe_num, rid, 1135 OpalPciBusAll, 1136 OPAL_COMPARE_RID_DEVICE_NUMBER, 1137 OPAL_COMPARE_RID_FUNCTION_NUMBER, 1138 OPAL_MAP_PE); 1139 WARN_ON(rc != OPAL_SUCCESS); 1140 found_pe = true; 1141 break; 1142 } 1143 } 1144 1145 if (!found_pe) 1146 /* 1147 * Could not find an existing PE so allocate a new 1148 * one. 1149 */ 1150 return pnv_ioda_setup_dev_PE(npu_pdev); 1151 else 1152 return pe; 1153 } 1154 1155 static void pnv_ioda_setup_npu_PEs(struct pci_bus *bus) 1156 { 1157 struct pci_dev *pdev; 1158 1159 list_for_each_entry(pdev, &bus->devices, bus_list) 1160 pnv_ioda_setup_npu_PE(pdev); 1161 } 1162 1163 static void pnv_ioda_setup_PEs(struct pci_bus *bus) 1164 { 1165 struct pci_dev *dev; 1166 1167 pnv_ioda_setup_bus_PE(bus, false); 1168 1169 list_for_each_entry(dev, &bus->devices, bus_list) { 1170 if (dev->subordinate) { 1171 if (pci_pcie_type(dev) == PCI_EXP_TYPE_PCI_BRIDGE) 1172 pnv_ioda_setup_bus_PE(dev->subordinate, true); 1173 else 1174 pnv_ioda_setup_PEs(dev->subordinate); 1175 } 1176 } 1177 } 1178 1179 /* 1180 * Configure PEs so that the downstream PCI buses and devices 1181 * could have their associated PE#. Unfortunately, we didn't 1182 * figure out the way to identify the PLX bridge yet. So we 1183 * simply put the PCI bus and the subordinate behind the root 1184 * port to PE# here. The game rule here is expected to be changed 1185 * as soon as we can detected PLX bridge correctly. 1186 */ 1187 static void pnv_pci_ioda_setup_PEs(void) 1188 { 1189 struct pci_controller *hose, *tmp; 1190 struct pnv_phb *phb; 1191 1192 list_for_each_entry_safe(hose, tmp, &hose_list, list_node) { 1193 phb = hose->private_data; 1194 1195 /* M64 layout might affect PE allocation */ 1196 if (phb->reserve_m64_pe) 1197 phb->reserve_m64_pe(hose->bus, NULL, true); 1198 1199 /* 1200 * On NPU PHB, we expect separate PEs for individual PCI 1201 * functions. PCI bus dependent PEs are required for the 1202 * remaining types of PHBs. 1203 */ 1204 if (phb->type == PNV_PHB_NPU) { 1205 /* PE#0 is needed for error reporting */ 1206 pnv_ioda_reserve_pe(phb, 0); 1207 pnv_ioda_setup_npu_PEs(hose->bus); 1208 } else 1209 pnv_ioda_setup_PEs(hose->bus); 1210 } 1211 } 1212 1213 #ifdef CONFIG_PCI_IOV 1214 static int pnv_pci_vf_release_m64(struct pci_dev *pdev, u16 num_vfs) 1215 { 1216 struct pci_bus *bus; 1217 struct pci_controller *hose; 1218 struct pnv_phb *phb; 1219 struct pci_dn *pdn; 1220 int i, j; 1221 int m64_bars; 1222 1223 bus = pdev->bus; 1224 hose = pci_bus_to_host(bus); 1225 phb = hose->private_data; 1226 pdn = pci_get_pdn(pdev); 1227 1228 if (pdn->m64_single_mode) 1229 m64_bars = num_vfs; 1230 else 1231 m64_bars = 1; 1232 1233 for (i = 0; i < PCI_SRIOV_NUM_BARS; i++) 1234 for (j = 0; j < m64_bars; j++) { 1235 if (pdn->m64_map[j][i] == IODA_INVALID_M64) 1236 continue; 1237 opal_pci_phb_mmio_enable(phb->opal_id, 1238 OPAL_M64_WINDOW_TYPE, pdn->m64_map[j][i], 0); 1239 clear_bit(pdn->m64_map[j][i], &phb->ioda.m64_bar_alloc); 1240 pdn->m64_map[j][i] = IODA_INVALID_M64; 1241 } 1242 1243 kfree(pdn->m64_map); 1244 return 0; 1245 } 1246 1247 static int pnv_pci_vf_assign_m64(struct pci_dev *pdev, u16 num_vfs) 1248 { 1249 struct pci_bus *bus; 1250 struct pci_controller *hose; 1251 struct pnv_phb *phb; 1252 struct pci_dn *pdn; 1253 unsigned int win; 1254 struct resource *res; 1255 int i, j; 1256 int64_t rc; 1257 int total_vfs; 1258 resource_size_t size, start; 1259 int pe_num; 1260 int m64_bars; 1261 1262 bus = pdev->bus; 1263 hose = pci_bus_to_host(bus); 1264 phb = hose->private_data; 1265 pdn = pci_get_pdn(pdev); 1266 total_vfs = pci_sriov_get_totalvfs(pdev); 1267 1268 if (pdn->m64_single_mode) 1269 m64_bars = num_vfs; 1270 else 1271 m64_bars = 1; 1272 1273 pdn->m64_map = kmalloc(sizeof(*pdn->m64_map) * m64_bars, GFP_KERNEL); 1274 if (!pdn->m64_map) 1275 return -ENOMEM; 1276 /* Initialize the m64_map to IODA_INVALID_M64 */ 1277 for (i = 0; i < m64_bars ; i++) 1278 for (j = 0; j < PCI_SRIOV_NUM_BARS; j++) 1279 pdn->m64_map[i][j] = IODA_INVALID_M64; 1280 1281 1282 for (i = 0; i < PCI_SRIOV_NUM_BARS; i++) { 1283 res = &pdev->resource[i + PCI_IOV_RESOURCES]; 1284 if (!res->flags || !res->parent) 1285 continue; 1286 1287 for (j = 0; j < m64_bars; j++) { 1288 do { 1289 win = find_next_zero_bit(&phb->ioda.m64_bar_alloc, 1290 phb->ioda.m64_bar_idx + 1, 0); 1291 1292 if (win >= phb->ioda.m64_bar_idx + 1) 1293 goto m64_failed; 1294 } while (test_and_set_bit(win, &phb->ioda.m64_bar_alloc)); 1295 1296 pdn->m64_map[j][i] = win; 1297 1298 if (pdn->m64_single_mode) { 1299 size = pci_iov_resource_size(pdev, 1300 PCI_IOV_RESOURCES + i); 1301 start = res->start + size * j; 1302 } else { 1303 size = resource_size(res); 1304 start = res->start; 1305 } 1306 1307 /* Map the M64 here */ 1308 if (pdn->m64_single_mode) { 1309 pe_num = pdn->pe_num_map[j]; 1310 rc = opal_pci_map_pe_mmio_window(phb->opal_id, 1311 pe_num, OPAL_M64_WINDOW_TYPE, 1312 pdn->m64_map[j][i], 0); 1313 } 1314 1315 rc = opal_pci_set_phb_mem_window(phb->opal_id, 1316 OPAL_M64_WINDOW_TYPE, 1317 pdn->m64_map[j][i], 1318 start, 1319 0, /* unused */ 1320 size); 1321 1322 1323 if (rc != OPAL_SUCCESS) { 1324 dev_err(&pdev->dev, "Failed to map M64 window #%d: %lld\n", 1325 win, rc); 1326 goto m64_failed; 1327 } 1328 1329 if (pdn->m64_single_mode) 1330 rc = opal_pci_phb_mmio_enable(phb->opal_id, 1331 OPAL_M64_WINDOW_TYPE, pdn->m64_map[j][i], 2); 1332 else 1333 rc = opal_pci_phb_mmio_enable(phb->opal_id, 1334 OPAL_M64_WINDOW_TYPE, pdn->m64_map[j][i], 1); 1335 1336 if (rc != OPAL_SUCCESS) { 1337 dev_err(&pdev->dev, "Failed to enable M64 window #%d: %llx\n", 1338 win, rc); 1339 goto m64_failed; 1340 } 1341 } 1342 } 1343 return 0; 1344 1345 m64_failed: 1346 pnv_pci_vf_release_m64(pdev, num_vfs); 1347 return -EBUSY; 1348 } 1349 1350 static long pnv_pci_ioda2_unset_window(struct iommu_table_group *table_group, 1351 int num); 1352 static void pnv_pci_ioda2_set_bypass(struct pnv_ioda_pe *pe, bool enable); 1353 1354 static void pnv_pci_ioda2_release_dma_pe(struct pci_dev *dev, struct pnv_ioda_pe *pe) 1355 { 1356 struct iommu_table *tbl; 1357 int64_t rc; 1358 1359 tbl = pe->table_group.tables[0]; 1360 rc = pnv_pci_ioda2_unset_window(&pe->table_group, 0); 1361 if (rc) 1362 pe_warn(pe, "OPAL error %ld release DMA window\n", rc); 1363 1364 pnv_pci_ioda2_set_bypass(pe, false); 1365 if (pe->table_group.group) { 1366 iommu_group_put(pe->table_group.group); 1367 BUG_ON(pe->table_group.group); 1368 } 1369 pnv_pci_ioda2_table_free_pages(tbl); 1370 iommu_free_table(tbl, of_node_full_name(dev->dev.of_node)); 1371 } 1372 1373 static void pnv_ioda_release_vf_PE(struct pci_dev *pdev) 1374 { 1375 struct pci_bus *bus; 1376 struct pci_controller *hose; 1377 struct pnv_phb *phb; 1378 struct pnv_ioda_pe *pe, *pe_n; 1379 struct pci_dn *pdn; 1380 1381 bus = pdev->bus; 1382 hose = pci_bus_to_host(bus); 1383 phb = hose->private_data; 1384 pdn = pci_get_pdn(pdev); 1385 1386 if (!pdev->is_physfn) 1387 return; 1388 1389 list_for_each_entry_safe(pe, pe_n, &phb->ioda.pe_list, list) { 1390 if (pe->parent_dev != pdev) 1391 continue; 1392 1393 pnv_pci_ioda2_release_dma_pe(pdev, pe); 1394 1395 /* Remove from list */ 1396 mutex_lock(&phb->ioda.pe_list_mutex); 1397 list_del(&pe->list); 1398 mutex_unlock(&phb->ioda.pe_list_mutex); 1399 1400 pnv_ioda_deconfigure_pe(phb, pe); 1401 1402 pnv_ioda_free_pe(pe); 1403 } 1404 } 1405 1406 void pnv_pci_sriov_disable(struct pci_dev *pdev) 1407 { 1408 struct pci_bus *bus; 1409 struct pci_controller *hose; 1410 struct pnv_phb *phb; 1411 struct pnv_ioda_pe *pe; 1412 struct pci_dn *pdn; 1413 struct pci_sriov *iov; 1414 u16 num_vfs, i; 1415 1416 bus = pdev->bus; 1417 hose = pci_bus_to_host(bus); 1418 phb = hose->private_data; 1419 pdn = pci_get_pdn(pdev); 1420 iov = pdev->sriov; 1421 num_vfs = pdn->num_vfs; 1422 1423 /* Release VF PEs */ 1424 pnv_ioda_release_vf_PE(pdev); 1425 1426 if (phb->type == PNV_PHB_IODA2) { 1427 if (!pdn->m64_single_mode) 1428 pnv_pci_vf_resource_shift(pdev, -*pdn->pe_num_map); 1429 1430 /* Release M64 windows */ 1431 pnv_pci_vf_release_m64(pdev, num_vfs); 1432 1433 /* Release PE numbers */ 1434 if (pdn->m64_single_mode) { 1435 for (i = 0; i < num_vfs; i++) { 1436 if (pdn->pe_num_map[i] == IODA_INVALID_PE) 1437 continue; 1438 1439 pe = &phb->ioda.pe_array[pdn->pe_num_map[i]]; 1440 pnv_ioda_free_pe(pe); 1441 } 1442 } else 1443 bitmap_clear(phb->ioda.pe_alloc, *pdn->pe_num_map, num_vfs); 1444 /* Releasing pe_num_map */ 1445 kfree(pdn->pe_num_map); 1446 } 1447 } 1448 1449 static void pnv_pci_ioda2_setup_dma_pe(struct pnv_phb *phb, 1450 struct pnv_ioda_pe *pe); 1451 static void pnv_ioda_setup_vf_PE(struct pci_dev *pdev, u16 num_vfs) 1452 { 1453 struct pci_bus *bus; 1454 struct pci_controller *hose; 1455 struct pnv_phb *phb; 1456 struct pnv_ioda_pe *pe; 1457 int pe_num; 1458 u16 vf_index; 1459 struct pci_dn *pdn; 1460 1461 bus = pdev->bus; 1462 hose = pci_bus_to_host(bus); 1463 phb = hose->private_data; 1464 pdn = pci_get_pdn(pdev); 1465 1466 if (!pdev->is_physfn) 1467 return; 1468 1469 /* Reserve PE for each VF */ 1470 for (vf_index = 0; vf_index < num_vfs; vf_index++) { 1471 if (pdn->m64_single_mode) 1472 pe_num = pdn->pe_num_map[vf_index]; 1473 else 1474 pe_num = *pdn->pe_num_map + vf_index; 1475 1476 pe = &phb->ioda.pe_array[pe_num]; 1477 pe->pe_number = pe_num; 1478 pe->phb = phb; 1479 pe->flags = PNV_IODA_PE_VF; 1480 pe->pbus = NULL; 1481 pe->parent_dev = pdev; 1482 pe->mve_number = -1; 1483 pe->rid = (pci_iov_virtfn_bus(pdev, vf_index) << 8) | 1484 pci_iov_virtfn_devfn(pdev, vf_index); 1485 1486 pe_info(pe, "VF %04d:%02d:%02d.%d associated with PE#%d\n", 1487 hose->global_number, pdev->bus->number, 1488 PCI_SLOT(pci_iov_virtfn_devfn(pdev, vf_index)), 1489 PCI_FUNC(pci_iov_virtfn_devfn(pdev, vf_index)), pe_num); 1490 1491 if (pnv_ioda_configure_pe(phb, pe)) { 1492 /* XXX What do we do here ? */ 1493 pnv_ioda_free_pe(pe); 1494 pe->pdev = NULL; 1495 continue; 1496 } 1497 1498 /* Put PE to the list */ 1499 mutex_lock(&phb->ioda.pe_list_mutex); 1500 list_add_tail(&pe->list, &phb->ioda.pe_list); 1501 mutex_unlock(&phb->ioda.pe_list_mutex); 1502 1503 pnv_pci_ioda2_setup_dma_pe(phb, pe); 1504 } 1505 } 1506 1507 int pnv_pci_sriov_enable(struct pci_dev *pdev, u16 num_vfs) 1508 { 1509 struct pci_bus *bus; 1510 struct pci_controller *hose; 1511 struct pnv_phb *phb; 1512 struct pnv_ioda_pe *pe; 1513 struct pci_dn *pdn; 1514 int ret; 1515 u16 i; 1516 1517 bus = pdev->bus; 1518 hose = pci_bus_to_host(bus); 1519 phb = hose->private_data; 1520 pdn = pci_get_pdn(pdev); 1521 1522 if (phb->type == PNV_PHB_IODA2) { 1523 if (!pdn->vfs_expanded) { 1524 dev_info(&pdev->dev, "don't support this SRIOV device" 1525 " with non 64bit-prefetchable IOV BAR\n"); 1526 return -ENOSPC; 1527 } 1528 1529 /* 1530 * When M64 BARs functions in Single PE mode, the number of VFs 1531 * could be enabled must be less than the number of M64 BARs. 1532 */ 1533 if (pdn->m64_single_mode && num_vfs > phb->ioda.m64_bar_idx) { 1534 dev_info(&pdev->dev, "Not enough M64 BAR for VFs\n"); 1535 return -EBUSY; 1536 } 1537 1538 /* Allocating pe_num_map */ 1539 if (pdn->m64_single_mode) 1540 pdn->pe_num_map = kmalloc(sizeof(*pdn->pe_num_map) * num_vfs, 1541 GFP_KERNEL); 1542 else 1543 pdn->pe_num_map = kmalloc(sizeof(*pdn->pe_num_map), GFP_KERNEL); 1544 1545 if (!pdn->pe_num_map) 1546 return -ENOMEM; 1547 1548 if (pdn->m64_single_mode) 1549 for (i = 0; i < num_vfs; i++) 1550 pdn->pe_num_map[i] = IODA_INVALID_PE; 1551 1552 /* Calculate available PE for required VFs */ 1553 if (pdn->m64_single_mode) { 1554 for (i = 0; i < num_vfs; i++) { 1555 pe = pnv_ioda_alloc_pe(phb); 1556 if (!pe) { 1557 ret = -EBUSY; 1558 goto m64_failed; 1559 } 1560 1561 pdn->pe_num_map[i] = pe->pe_number; 1562 } 1563 } else { 1564 mutex_lock(&phb->ioda.pe_alloc_mutex); 1565 *pdn->pe_num_map = bitmap_find_next_zero_area( 1566 phb->ioda.pe_alloc, phb->ioda.total_pe_num, 1567 0, num_vfs, 0); 1568 if (*pdn->pe_num_map >= phb->ioda.total_pe_num) { 1569 mutex_unlock(&phb->ioda.pe_alloc_mutex); 1570 dev_info(&pdev->dev, "Failed to enable VF%d\n", num_vfs); 1571 kfree(pdn->pe_num_map); 1572 return -EBUSY; 1573 } 1574 bitmap_set(phb->ioda.pe_alloc, *pdn->pe_num_map, num_vfs); 1575 mutex_unlock(&phb->ioda.pe_alloc_mutex); 1576 } 1577 pdn->num_vfs = num_vfs; 1578 1579 /* Assign M64 window accordingly */ 1580 ret = pnv_pci_vf_assign_m64(pdev, num_vfs); 1581 if (ret) { 1582 dev_info(&pdev->dev, "Not enough M64 window resources\n"); 1583 goto m64_failed; 1584 } 1585 1586 /* 1587 * When using one M64 BAR to map one IOV BAR, we need to shift 1588 * the IOV BAR according to the PE# allocated to the VFs. 1589 * Otherwise, the PE# for the VF will conflict with others. 1590 */ 1591 if (!pdn->m64_single_mode) { 1592 ret = pnv_pci_vf_resource_shift(pdev, *pdn->pe_num_map); 1593 if (ret) 1594 goto m64_failed; 1595 } 1596 } 1597 1598 /* Setup VF PEs */ 1599 pnv_ioda_setup_vf_PE(pdev, num_vfs); 1600 1601 return 0; 1602 1603 m64_failed: 1604 if (pdn->m64_single_mode) { 1605 for (i = 0; i < num_vfs; i++) { 1606 if (pdn->pe_num_map[i] == IODA_INVALID_PE) 1607 continue; 1608 1609 pe = &phb->ioda.pe_array[pdn->pe_num_map[i]]; 1610 pnv_ioda_free_pe(pe); 1611 } 1612 } else 1613 bitmap_clear(phb->ioda.pe_alloc, *pdn->pe_num_map, num_vfs); 1614 1615 /* Releasing pe_num_map */ 1616 kfree(pdn->pe_num_map); 1617 1618 return ret; 1619 } 1620 1621 int pcibios_sriov_disable(struct pci_dev *pdev) 1622 { 1623 pnv_pci_sriov_disable(pdev); 1624 1625 /* Release PCI data */ 1626 remove_dev_pci_data(pdev); 1627 return 0; 1628 } 1629 1630 int pcibios_sriov_enable(struct pci_dev *pdev, u16 num_vfs) 1631 { 1632 /* Allocate PCI data */ 1633 add_dev_pci_data(pdev); 1634 1635 return pnv_pci_sriov_enable(pdev, num_vfs); 1636 } 1637 #endif /* CONFIG_PCI_IOV */ 1638 1639 static void pnv_pci_ioda_dma_dev_setup(struct pnv_phb *phb, struct pci_dev *pdev) 1640 { 1641 struct pci_dn *pdn = pci_get_pdn(pdev); 1642 struct pnv_ioda_pe *pe; 1643 1644 /* 1645 * The function can be called while the PE# 1646 * hasn't been assigned. Do nothing for the 1647 * case. 1648 */ 1649 if (!pdn || pdn->pe_number == IODA_INVALID_PE) 1650 return; 1651 1652 pe = &phb->ioda.pe_array[pdn->pe_number]; 1653 WARN_ON(get_dma_ops(&pdev->dev) != &dma_iommu_ops); 1654 set_dma_offset(&pdev->dev, pe->tce_bypass_base); 1655 set_iommu_table_base(&pdev->dev, pe->table_group.tables[0]); 1656 /* 1657 * Note: iommu_add_device() will fail here as 1658 * for physical PE: the device is already added by now; 1659 * for virtual PE: sysfs entries are not ready yet and 1660 * tce_iommu_bus_notifier will add the device to a group later. 1661 */ 1662 } 1663 1664 static int pnv_pci_ioda_dma_set_mask(struct pci_dev *pdev, u64 dma_mask) 1665 { 1666 struct pci_controller *hose = pci_bus_to_host(pdev->bus); 1667 struct pnv_phb *phb = hose->private_data; 1668 struct pci_dn *pdn = pci_get_pdn(pdev); 1669 struct pnv_ioda_pe *pe; 1670 uint64_t top; 1671 bool bypass = false; 1672 1673 if (WARN_ON(!pdn || pdn->pe_number == IODA_INVALID_PE)) 1674 return -ENODEV;; 1675 1676 pe = &phb->ioda.pe_array[pdn->pe_number]; 1677 if (pe->tce_bypass_enabled) { 1678 top = pe->tce_bypass_base + memblock_end_of_DRAM() - 1; 1679 bypass = (dma_mask >= top); 1680 } 1681 1682 if (bypass) { 1683 dev_info(&pdev->dev, "Using 64-bit DMA iommu bypass\n"); 1684 set_dma_ops(&pdev->dev, &dma_direct_ops); 1685 } else { 1686 dev_info(&pdev->dev, "Using 32-bit DMA via iommu\n"); 1687 set_dma_ops(&pdev->dev, &dma_iommu_ops); 1688 } 1689 *pdev->dev.dma_mask = dma_mask; 1690 1691 /* Update peer npu devices */ 1692 pnv_npu_try_dma_set_bypass(pdev, bypass); 1693 1694 return 0; 1695 } 1696 1697 static u64 pnv_pci_ioda_dma_get_required_mask(struct pci_dev *pdev) 1698 { 1699 struct pci_controller *hose = pci_bus_to_host(pdev->bus); 1700 struct pnv_phb *phb = hose->private_data; 1701 struct pci_dn *pdn = pci_get_pdn(pdev); 1702 struct pnv_ioda_pe *pe; 1703 u64 end, mask; 1704 1705 if (WARN_ON(!pdn || pdn->pe_number == IODA_INVALID_PE)) 1706 return 0; 1707 1708 pe = &phb->ioda.pe_array[pdn->pe_number]; 1709 if (!pe->tce_bypass_enabled) 1710 return __dma_get_required_mask(&pdev->dev); 1711 1712 1713 end = pe->tce_bypass_base + memblock_end_of_DRAM(); 1714 mask = 1ULL << (fls64(end) - 1); 1715 mask += mask - 1; 1716 1717 return mask; 1718 } 1719 1720 static void pnv_ioda_setup_bus_dma(struct pnv_ioda_pe *pe, 1721 struct pci_bus *bus) 1722 { 1723 struct pci_dev *dev; 1724 1725 list_for_each_entry(dev, &bus->devices, bus_list) { 1726 set_iommu_table_base(&dev->dev, pe->table_group.tables[0]); 1727 set_dma_offset(&dev->dev, pe->tce_bypass_base); 1728 iommu_add_device(&dev->dev); 1729 1730 if ((pe->flags & PNV_IODA_PE_BUS_ALL) && dev->subordinate) 1731 pnv_ioda_setup_bus_dma(pe, dev->subordinate); 1732 } 1733 } 1734 1735 static void pnv_pci_ioda1_tce_invalidate(struct iommu_table *tbl, 1736 unsigned long index, unsigned long npages, bool rm) 1737 { 1738 struct iommu_table_group_link *tgl = list_first_entry_or_null( 1739 &tbl->it_group_list, struct iommu_table_group_link, 1740 next); 1741 struct pnv_ioda_pe *pe = container_of(tgl->table_group, 1742 struct pnv_ioda_pe, table_group); 1743 __be64 __iomem *invalidate = rm ? 1744 (__be64 __iomem *)pe->phb->ioda.tce_inval_reg_phys : 1745 pe->phb->ioda.tce_inval_reg; 1746 unsigned long start, end, inc; 1747 const unsigned shift = tbl->it_page_shift; 1748 1749 start = __pa(((__be64 *)tbl->it_base) + index - tbl->it_offset); 1750 end = __pa(((__be64 *)tbl->it_base) + index - tbl->it_offset + 1751 npages - 1); 1752 1753 /* BML uses this case for p6/p7/galaxy2: Shift addr and put in node */ 1754 if (tbl->it_busno) { 1755 start <<= shift; 1756 end <<= shift; 1757 inc = 128ull << shift; 1758 start |= tbl->it_busno; 1759 end |= tbl->it_busno; 1760 } else if (tbl->it_type & TCE_PCI_SWINV_PAIR) { 1761 /* p7ioc-style invalidation, 2 TCEs per write */ 1762 start |= (1ull << 63); 1763 end |= (1ull << 63); 1764 inc = 16; 1765 } else { 1766 /* Default (older HW) */ 1767 inc = 128; 1768 } 1769 1770 end |= inc - 1; /* round up end to be different than start */ 1771 1772 mb(); /* Ensure above stores are visible */ 1773 while (start <= end) { 1774 if (rm) 1775 __raw_rm_writeq(cpu_to_be64(start), invalidate); 1776 else 1777 __raw_writeq(cpu_to_be64(start), invalidate); 1778 start += inc; 1779 } 1780 1781 /* 1782 * The iommu layer will do another mb() for us on build() 1783 * and we don't care on free() 1784 */ 1785 } 1786 1787 static int pnv_ioda1_tce_build(struct iommu_table *tbl, long index, 1788 long npages, unsigned long uaddr, 1789 enum dma_data_direction direction, 1790 struct dma_attrs *attrs) 1791 { 1792 int ret = pnv_tce_build(tbl, index, npages, uaddr, direction, 1793 attrs); 1794 1795 if (!ret && (tbl->it_type & TCE_PCI_SWINV_CREATE)) 1796 pnv_pci_ioda1_tce_invalidate(tbl, index, npages, false); 1797 1798 return ret; 1799 } 1800 1801 #ifdef CONFIG_IOMMU_API 1802 static int pnv_ioda1_tce_xchg(struct iommu_table *tbl, long index, 1803 unsigned long *hpa, enum dma_data_direction *direction) 1804 { 1805 long ret = pnv_tce_xchg(tbl, index, hpa, direction); 1806 1807 if (!ret && (tbl->it_type & 1808 (TCE_PCI_SWINV_CREATE | TCE_PCI_SWINV_FREE))) 1809 pnv_pci_ioda1_tce_invalidate(tbl, index, 1, false); 1810 1811 return ret; 1812 } 1813 #endif 1814 1815 static void pnv_ioda1_tce_free(struct iommu_table *tbl, long index, 1816 long npages) 1817 { 1818 pnv_tce_free(tbl, index, npages); 1819 1820 if (tbl->it_type & TCE_PCI_SWINV_FREE) 1821 pnv_pci_ioda1_tce_invalidate(tbl, index, npages, false); 1822 } 1823 1824 static struct iommu_table_ops pnv_ioda1_iommu_ops = { 1825 .set = pnv_ioda1_tce_build, 1826 #ifdef CONFIG_IOMMU_API 1827 .exchange = pnv_ioda1_tce_xchg, 1828 #endif 1829 .clear = pnv_ioda1_tce_free, 1830 .get = pnv_tce_get, 1831 }; 1832 1833 #define TCE_KILL_INVAL_ALL PPC_BIT(0) 1834 #define TCE_KILL_INVAL_PE PPC_BIT(1) 1835 #define TCE_KILL_INVAL_TCE PPC_BIT(2) 1836 1837 void pnv_pci_ioda2_tce_invalidate_entire(struct pnv_phb *phb, bool rm) 1838 { 1839 const unsigned long val = TCE_KILL_INVAL_ALL; 1840 1841 mb(); /* Ensure previous TCE table stores are visible */ 1842 if (rm) 1843 __raw_rm_writeq(cpu_to_be64(val), 1844 (__be64 __iomem *) 1845 phb->ioda.tce_inval_reg_phys); 1846 else 1847 __raw_writeq(cpu_to_be64(val), phb->ioda.tce_inval_reg); 1848 } 1849 1850 static inline void pnv_pci_ioda2_tce_invalidate_pe(struct pnv_ioda_pe *pe) 1851 { 1852 /* 01xb - invalidate TCEs that match the specified PE# */ 1853 unsigned long val = TCE_KILL_INVAL_PE | (pe->pe_number & 0xFF); 1854 struct pnv_phb *phb = pe->phb; 1855 struct pnv_ioda_pe *npe; 1856 int i; 1857 1858 if (!phb->ioda.tce_inval_reg) 1859 return; 1860 1861 mb(); /* Ensure above stores are visible */ 1862 __raw_writeq(cpu_to_be64(val), phb->ioda.tce_inval_reg); 1863 1864 if (pe->flags & PNV_IODA_PE_PEER) 1865 for (i = 0; i < PNV_IODA_MAX_PEER_PES; i++) { 1866 npe = pe->peers[i]; 1867 if (!npe || npe->phb->type != PNV_PHB_NPU) 1868 continue; 1869 1870 pnv_pci_ioda2_tce_invalidate_entire(npe->phb, false); 1871 } 1872 } 1873 1874 static void pnv_pci_ioda2_do_tce_invalidate(unsigned pe_number, bool rm, 1875 __be64 __iomem *invalidate, unsigned shift, 1876 unsigned long index, unsigned long npages) 1877 { 1878 unsigned long start, end, inc; 1879 1880 /* We'll invalidate DMA address in PE scope */ 1881 start = TCE_KILL_INVAL_TCE; 1882 start |= (pe_number & 0xFF); 1883 end = start; 1884 1885 /* Figure out the start, end and step */ 1886 start |= (index << shift); 1887 end |= ((index + npages - 1) << shift); 1888 inc = (0x1ull << shift); 1889 mb(); 1890 1891 while (start <= end) { 1892 if (rm) 1893 __raw_rm_writeq(cpu_to_be64(start), invalidate); 1894 else 1895 __raw_writeq(cpu_to_be64(start), invalidate); 1896 start += inc; 1897 } 1898 } 1899 1900 static void pnv_pci_ioda2_tce_invalidate(struct iommu_table *tbl, 1901 unsigned long index, unsigned long npages, bool rm) 1902 { 1903 struct iommu_table_group_link *tgl; 1904 1905 list_for_each_entry_rcu(tgl, &tbl->it_group_list, next) { 1906 struct pnv_ioda_pe *npe; 1907 struct pnv_ioda_pe *pe = container_of(tgl->table_group, 1908 struct pnv_ioda_pe, table_group); 1909 __be64 __iomem *invalidate = rm ? 1910 (__be64 __iomem *)pe->phb->ioda.tce_inval_reg_phys : 1911 pe->phb->ioda.tce_inval_reg; 1912 int i; 1913 1914 pnv_pci_ioda2_do_tce_invalidate(pe->pe_number, rm, 1915 invalidate, tbl->it_page_shift, 1916 index, npages); 1917 1918 if (pe->flags & PNV_IODA_PE_PEER) 1919 /* 1920 * The NVLink hardware does not support TCE kill 1921 * per TCE entry so we have to invalidate 1922 * the entire cache for it. 1923 */ 1924 for (i = 0; i < PNV_IODA_MAX_PEER_PES; i++) { 1925 npe = pe->peers[i]; 1926 if (!npe || npe->phb->type != PNV_PHB_NPU || 1927 !npe->phb->ioda.tce_inval_reg) 1928 continue; 1929 1930 pnv_pci_ioda2_tce_invalidate_entire(npe->phb, 1931 rm); 1932 } 1933 } 1934 } 1935 1936 static int pnv_ioda2_tce_build(struct iommu_table *tbl, long index, 1937 long npages, unsigned long uaddr, 1938 enum dma_data_direction direction, 1939 struct dma_attrs *attrs) 1940 { 1941 int ret = pnv_tce_build(tbl, index, npages, uaddr, direction, 1942 attrs); 1943 1944 if (!ret && (tbl->it_type & TCE_PCI_SWINV_CREATE)) 1945 pnv_pci_ioda2_tce_invalidate(tbl, index, npages, false); 1946 1947 return ret; 1948 } 1949 1950 #ifdef CONFIG_IOMMU_API 1951 static int pnv_ioda2_tce_xchg(struct iommu_table *tbl, long index, 1952 unsigned long *hpa, enum dma_data_direction *direction) 1953 { 1954 long ret = pnv_tce_xchg(tbl, index, hpa, direction); 1955 1956 if (!ret && (tbl->it_type & 1957 (TCE_PCI_SWINV_CREATE | TCE_PCI_SWINV_FREE))) 1958 pnv_pci_ioda2_tce_invalidate(tbl, index, 1, false); 1959 1960 return ret; 1961 } 1962 #endif 1963 1964 static void pnv_ioda2_tce_free(struct iommu_table *tbl, long index, 1965 long npages) 1966 { 1967 pnv_tce_free(tbl, index, npages); 1968 1969 if (tbl->it_type & TCE_PCI_SWINV_FREE) 1970 pnv_pci_ioda2_tce_invalidate(tbl, index, npages, false); 1971 } 1972 1973 static void pnv_ioda2_table_free(struct iommu_table *tbl) 1974 { 1975 pnv_pci_ioda2_table_free_pages(tbl); 1976 iommu_free_table(tbl, "pnv"); 1977 } 1978 1979 static struct iommu_table_ops pnv_ioda2_iommu_ops = { 1980 .set = pnv_ioda2_tce_build, 1981 #ifdef CONFIG_IOMMU_API 1982 .exchange = pnv_ioda2_tce_xchg, 1983 #endif 1984 .clear = pnv_ioda2_tce_free, 1985 .get = pnv_tce_get, 1986 .free = pnv_ioda2_table_free, 1987 }; 1988 1989 static int pnv_pci_ioda_dev_dma_weight(struct pci_dev *dev, void *data) 1990 { 1991 unsigned int *weight = (unsigned int *)data; 1992 1993 /* This is quite simplistic. The "base" weight of a device 1994 * is 10. 0 means no DMA is to be accounted for it. 1995 */ 1996 if (dev->hdr_type != PCI_HEADER_TYPE_NORMAL) 1997 return 0; 1998 1999 if (dev->class == PCI_CLASS_SERIAL_USB_UHCI || 2000 dev->class == PCI_CLASS_SERIAL_USB_OHCI || 2001 dev->class == PCI_CLASS_SERIAL_USB_EHCI) 2002 *weight += 3; 2003 else if ((dev->class >> 8) == PCI_CLASS_STORAGE_RAID) 2004 *weight += 15; 2005 else 2006 *weight += 10; 2007 2008 return 0; 2009 } 2010 2011 static unsigned int pnv_pci_ioda_pe_dma_weight(struct pnv_ioda_pe *pe) 2012 { 2013 unsigned int weight = 0; 2014 2015 /* SRIOV VF has same DMA32 weight as its PF */ 2016 #ifdef CONFIG_PCI_IOV 2017 if ((pe->flags & PNV_IODA_PE_VF) && pe->parent_dev) { 2018 pnv_pci_ioda_dev_dma_weight(pe->parent_dev, &weight); 2019 return weight; 2020 } 2021 #endif 2022 2023 if ((pe->flags & PNV_IODA_PE_DEV) && pe->pdev) { 2024 pnv_pci_ioda_dev_dma_weight(pe->pdev, &weight); 2025 } else if ((pe->flags & PNV_IODA_PE_BUS) && pe->pbus) { 2026 struct pci_dev *pdev; 2027 2028 list_for_each_entry(pdev, &pe->pbus->devices, bus_list) 2029 pnv_pci_ioda_dev_dma_weight(pdev, &weight); 2030 } else if ((pe->flags & PNV_IODA_PE_BUS_ALL) && pe->pbus) { 2031 pci_walk_bus(pe->pbus, pnv_pci_ioda_dev_dma_weight, &weight); 2032 } 2033 2034 return weight; 2035 } 2036 2037 static void pnv_pci_ioda1_setup_dma_pe(struct pnv_phb *phb, 2038 struct pnv_ioda_pe *pe) 2039 { 2040 2041 struct page *tce_mem = NULL; 2042 struct iommu_table *tbl; 2043 unsigned int weight, total_weight = 0; 2044 unsigned int tce32_segsz, base, segs, avail, i; 2045 int64_t rc; 2046 void *addr; 2047 2048 /* XXX FIXME: Handle 64-bit only DMA devices */ 2049 /* XXX FIXME: Provide 64-bit DMA facilities & non-4K TCE tables etc.. */ 2050 /* XXX FIXME: Allocate multi-level tables on PHB3 */ 2051 weight = pnv_pci_ioda_pe_dma_weight(pe); 2052 if (!weight) 2053 return; 2054 2055 pci_walk_bus(phb->hose->bus, pnv_pci_ioda_dev_dma_weight, 2056 &total_weight); 2057 segs = (weight * phb->ioda.dma32_count) / total_weight; 2058 if (!segs) 2059 segs = 1; 2060 2061 /* 2062 * Allocate contiguous DMA32 segments. We begin with the expected 2063 * number of segments. With one more attempt, the number of DMA32 2064 * segments to be allocated is decreased by one until one segment 2065 * is allocated successfully. 2066 */ 2067 do { 2068 for (base = 0; base <= phb->ioda.dma32_count - segs; base++) { 2069 for (avail = 0, i = base; i < base + segs; i++) { 2070 if (phb->ioda.dma32_segmap[i] == 2071 IODA_INVALID_PE) 2072 avail++; 2073 } 2074 2075 if (avail == segs) 2076 goto found; 2077 } 2078 } while (--segs); 2079 2080 if (!segs) { 2081 pe_warn(pe, "No available DMA32 segments\n"); 2082 return; 2083 } 2084 2085 found: 2086 tbl = pnv_pci_table_alloc(phb->hose->node); 2087 iommu_register_group(&pe->table_group, phb->hose->global_number, 2088 pe->pe_number); 2089 pnv_pci_link_table_and_group(phb->hose->node, 0, tbl, &pe->table_group); 2090 2091 /* Grab a 32-bit TCE table */ 2092 pe_info(pe, "DMA weight %d (%d), assigned (%d) %d DMA32 segments\n", 2093 weight, total_weight, base, segs); 2094 pe_info(pe, " Setting up 32-bit TCE table at %08x..%08x\n", 2095 base * PNV_IODA1_DMA32_SEGSIZE, 2096 (base + segs) * PNV_IODA1_DMA32_SEGSIZE - 1); 2097 2098 /* XXX Currently, we allocate one big contiguous table for the 2099 * TCEs. We only really need one chunk per 256M of TCE space 2100 * (ie per segment) but that's an optimization for later, it 2101 * requires some added smarts with our get/put_tce implementation 2102 * 2103 * Each TCE page is 4KB in size and each TCE entry occupies 8 2104 * bytes 2105 */ 2106 tce32_segsz = PNV_IODA1_DMA32_SEGSIZE >> (IOMMU_PAGE_SHIFT_4K - 3); 2107 tce_mem = alloc_pages_node(phb->hose->node, GFP_KERNEL, 2108 get_order(tce32_segsz * segs)); 2109 if (!tce_mem) { 2110 pe_err(pe, " Failed to allocate a 32-bit TCE memory\n"); 2111 goto fail; 2112 } 2113 addr = page_address(tce_mem); 2114 memset(addr, 0, tce32_segsz * segs); 2115 2116 /* Configure HW */ 2117 for (i = 0; i < segs; i++) { 2118 rc = opal_pci_map_pe_dma_window(phb->opal_id, 2119 pe->pe_number, 2120 base + i, 1, 2121 __pa(addr) + tce32_segsz * i, 2122 tce32_segsz, IOMMU_PAGE_SIZE_4K); 2123 if (rc) { 2124 pe_err(pe, " Failed to configure 32-bit TCE table," 2125 " err %ld\n", rc); 2126 goto fail; 2127 } 2128 } 2129 2130 /* Setup DMA32 segment mapping */ 2131 for (i = base; i < base + segs; i++) 2132 phb->ioda.dma32_segmap[i] = pe->pe_number; 2133 2134 /* Setup linux iommu table */ 2135 pnv_pci_setup_iommu_table(tbl, addr, tce32_segsz * segs, 2136 base * PNV_IODA1_DMA32_SEGSIZE, 2137 IOMMU_PAGE_SHIFT_4K); 2138 2139 /* OPAL variant of P7IOC SW invalidated TCEs */ 2140 if (phb->ioda.tce_inval_reg) 2141 tbl->it_type |= (TCE_PCI_SWINV_CREATE | 2142 TCE_PCI_SWINV_FREE | 2143 TCE_PCI_SWINV_PAIR); 2144 2145 tbl->it_ops = &pnv_ioda1_iommu_ops; 2146 pe->table_group.tce32_start = tbl->it_offset << tbl->it_page_shift; 2147 pe->table_group.tce32_size = tbl->it_size << tbl->it_page_shift; 2148 iommu_init_table(tbl, phb->hose->node); 2149 2150 if (pe->flags & PNV_IODA_PE_DEV) { 2151 /* 2152 * Setting table base here only for carrying iommu_group 2153 * further down to let iommu_add_device() do the job. 2154 * pnv_pci_ioda_dma_dev_setup will override it later anyway. 2155 */ 2156 set_iommu_table_base(&pe->pdev->dev, tbl); 2157 iommu_add_device(&pe->pdev->dev); 2158 } else if (pe->flags & (PNV_IODA_PE_BUS | PNV_IODA_PE_BUS_ALL)) 2159 pnv_ioda_setup_bus_dma(pe, pe->pbus); 2160 2161 return; 2162 fail: 2163 /* XXX Failure: Try to fallback to 64-bit only ? */ 2164 if (tce_mem) 2165 __free_pages(tce_mem, get_order(tce32_segsz * segs)); 2166 if (tbl) { 2167 pnv_pci_unlink_table_and_group(tbl, &pe->table_group); 2168 iommu_free_table(tbl, "pnv"); 2169 } 2170 } 2171 2172 static long pnv_pci_ioda2_set_window(struct iommu_table_group *table_group, 2173 int num, struct iommu_table *tbl) 2174 { 2175 struct pnv_ioda_pe *pe = container_of(table_group, struct pnv_ioda_pe, 2176 table_group); 2177 struct pnv_phb *phb = pe->phb; 2178 int64_t rc; 2179 const unsigned long size = tbl->it_indirect_levels ? 2180 tbl->it_level_size : tbl->it_size; 2181 const __u64 start_addr = tbl->it_offset << tbl->it_page_shift; 2182 const __u64 win_size = tbl->it_size << tbl->it_page_shift; 2183 2184 pe_info(pe, "Setting up window#%d %llx..%llx pg=%x\n", num, 2185 start_addr, start_addr + win_size - 1, 2186 IOMMU_PAGE_SIZE(tbl)); 2187 2188 /* 2189 * Map TCE table through TVT. The TVE index is the PE number 2190 * shifted by 1 bit for 32-bits DMA space. 2191 */ 2192 rc = opal_pci_map_pe_dma_window(phb->opal_id, 2193 pe->pe_number, 2194 (pe->pe_number << 1) + num, 2195 tbl->it_indirect_levels + 1, 2196 __pa(tbl->it_base), 2197 size << 3, 2198 IOMMU_PAGE_SIZE(tbl)); 2199 if (rc) { 2200 pe_err(pe, "Failed to configure TCE table, err %ld\n", rc); 2201 return rc; 2202 } 2203 2204 pnv_pci_link_table_and_group(phb->hose->node, num, 2205 tbl, &pe->table_group); 2206 pnv_pci_ioda2_tce_invalidate_pe(pe); 2207 2208 return 0; 2209 } 2210 2211 static void pnv_pci_ioda2_set_bypass(struct pnv_ioda_pe *pe, bool enable) 2212 { 2213 uint16_t window_id = (pe->pe_number << 1 ) + 1; 2214 int64_t rc; 2215 2216 pe_info(pe, "%sabling 64-bit DMA bypass\n", enable ? "En" : "Dis"); 2217 if (enable) { 2218 phys_addr_t top = memblock_end_of_DRAM(); 2219 2220 top = roundup_pow_of_two(top); 2221 rc = opal_pci_map_pe_dma_window_real(pe->phb->opal_id, 2222 pe->pe_number, 2223 window_id, 2224 pe->tce_bypass_base, 2225 top); 2226 } else { 2227 rc = opal_pci_map_pe_dma_window_real(pe->phb->opal_id, 2228 pe->pe_number, 2229 window_id, 2230 pe->tce_bypass_base, 2231 0); 2232 } 2233 if (rc) 2234 pe_err(pe, "OPAL error %lld configuring bypass window\n", rc); 2235 else 2236 pe->tce_bypass_enabled = enable; 2237 } 2238 2239 static long pnv_pci_ioda2_table_alloc_pages(int nid, __u64 bus_offset, 2240 __u32 page_shift, __u64 window_size, __u32 levels, 2241 struct iommu_table *tbl); 2242 2243 static long pnv_pci_ioda2_create_table(struct iommu_table_group *table_group, 2244 int num, __u32 page_shift, __u64 window_size, __u32 levels, 2245 struct iommu_table **ptbl) 2246 { 2247 struct pnv_ioda_pe *pe = container_of(table_group, struct pnv_ioda_pe, 2248 table_group); 2249 int nid = pe->phb->hose->node; 2250 __u64 bus_offset = num ? pe->tce_bypass_base : table_group->tce32_start; 2251 long ret; 2252 struct iommu_table *tbl; 2253 2254 tbl = pnv_pci_table_alloc(nid); 2255 if (!tbl) 2256 return -ENOMEM; 2257 2258 ret = pnv_pci_ioda2_table_alloc_pages(nid, 2259 bus_offset, page_shift, window_size, 2260 levels, tbl); 2261 if (ret) { 2262 iommu_free_table(tbl, "pnv"); 2263 return ret; 2264 } 2265 2266 tbl->it_ops = &pnv_ioda2_iommu_ops; 2267 if (pe->phb->ioda.tce_inval_reg) 2268 tbl->it_type |= (TCE_PCI_SWINV_CREATE | TCE_PCI_SWINV_FREE); 2269 2270 *ptbl = tbl; 2271 2272 return 0; 2273 } 2274 2275 static long pnv_pci_ioda2_setup_default_config(struct pnv_ioda_pe *pe) 2276 { 2277 struct iommu_table *tbl = NULL; 2278 long rc; 2279 2280 /* 2281 * crashkernel= specifies the kdump kernel's maximum memory at 2282 * some offset and there is no guaranteed the result is a power 2283 * of 2, which will cause errors later. 2284 */ 2285 const u64 max_memory = __rounddown_pow_of_two(memory_hotplug_max()); 2286 2287 /* 2288 * In memory constrained environments, e.g. kdump kernel, the 2289 * DMA window can be larger than available memory, which will 2290 * cause errors later. 2291 */ 2292 const u64 window_size = min((u64)pe->table_group.tce32_size, max_memory); 2293 2294 rc = pnv_pci_ioda2_create_table(&pe->table_group, 0, 2295 IOMMU_PAGE_SHIFT_4K, 2296 window_size, 2297 POWERNV_IOMMU_DEFAULT_LEVELS, &tbl); 2298 if (rc) { 2299 pe_err(pe, "Failed to create 32-bit TCE table, err %ld", 2300 rc); 2301 return rc; 2302 } 2303 2304 iommu_init_table(tbl, pe->phb->hose->node); 2305 2306 rc = pnv_pci_ioda2_set_window(&pe->table_group, 0, tbl); 2307 if (rc) { 2308 pe_err(pe, "Failed to configure 32-bit TCE table, err %ld\n", 2309 rc); 2310 pnv_ioda2_table_free(tbl); 2311 return rc; 2312 } 2313 2314 if (!pnv_iommu_bypass_disabled) 2315 pnv_pci_ioda2_set_bypass(pe, true); 2316 2317 /* OPAL variant of PHB3 invalidated TCEs */ 2318 if (pe->phb->ioda.tce_inval_reg) 2319 tbl->it_type |= (TCE_PCI_SWINV_CREATE | TCE_PCI_SWINV_FREE); 2320 2321 /* 2322 * Setting table base here only for carrying iommu_group 2323 * further down to let iommu_add_device() do the job. 2324 * pnv_pci_ioda_dma_dev_setup will override it later anyway. 2325 */ 2326 if (pe->flags & PNV_IODA_PE_DEV) 2327 set_iommu_table_base(&pe->pdev->dev, tbl); 2328 2329 return 0; 2330 } 2331 2332 #if defined(CONFIG_IOMMU_API) || defined(CONFIG_PCI_IOV) 2333 static long pnv_pci_ioda2_unset_window(struct iommu_table_group *table_group, 2334 int num) 2335 { 2336 struct pnv_ioda_pe *pe = container_of(table_group, struct pnv_ioda_pe, 2337 table_group); 2338 struct pnv_phb *phb = pe->phb; 2339 long ret; 2340 2341 pe_info(pe, "Removing DMA window #%d\n", num); 2342 2343 ret = opal_pci_map_pe_dma_window(phb->opal_id, pe->pe_number, 2344 (pe->pe_number << 1) + num, 2345 0/* levels */, 0/* table address */, 2346 0/* table size */, 0/* page size */); 2347 if (ret) 2348 pe_warn(pe, "Unmapping failed, ret = %ld\n", ret); 2349 else 2350 pnv_pci_ioda2_tce_invalidate_pe(pe); 2351 2352 pnv_pci_unlink_table_and_group(table_group->tables[num], table_group); 2353 2354 return ret; 2355 } 2356 #endif 2357 2358 #ifdef CONFIG_IOMMU_API 2359 static unsigned long pnv_pci_ioda2_get_table_size(__u32 page_shift, 2360 __u64 window_size, __u32 levels) 2361 { 2362 unsigned long bytes = 0; 2363 const unsigned window_shift = ilog2(window_size); 2364 unsigned entries_shift = window_shift - page_shift; 2365 unsigned table_shift = entries_shift + 3; 2366 unsigned long tce_table_size = max(0x1000UL, 1UL << table_shift); 2367 unsigned long direct_table_size; 2368 2369 if (!levels || (levels > POWERNV_IOMMU_MAX_LEVELS) || 2370 (window_size > memory_hotplug_max()) || 2371 !is_power_of_2(window_size)) 2372 return 0; 2373 2374 /* Calculate a direct table size from window_size and levels */ 2375 entries_shift = (entries_shift + levels - 1) / levels; 2376 table_shift = entries_shift + 3; 2377 table_shift = max_t(unsigned, table_shift, PAGE_SHIFT); 2378 direct_table_size = 1UL << table_shift; 2379 2380 for ( ; levels; --levels) { 2381 bytes += _ALIGN_UP(tce_table_size, direct_table_size); 2382 2383 tce_table_size /= direct_table_size; 2384 tce_table_size <<= 3; 2385 tce_table_size = _ALIGN_UP(tce_table_size, direct_table_size); 2386 } 2387 2388 return bytes; 2389 } 2390 2391 static void pnv_ioda2_take_ownership(struct iommu_table_group *table_group) 2392 { 2393 struct pnv_ioda_pe *pe = container_of(table_group, struct pnv_ioda_pe, 2394 table_group); 2395 /* Store @tbl as pnv_pci_ioda2_unset_window() resets it */ 2396 struct iommu_table *tbl = pe->table_group.tables[0]; 2397 2398 pnv_pci_ioda2_set_bypass(pe, false); 2399 pnv_pci_ioda2_unset_window(&pe->table_group, 0); 2400 pnv_ioda2_table_free(tbl); 2401 } 2402 2403 static void pnv_ioda2_release_ownership(struct iommu_table_group *table_group) 2404 { 2405 struct pnv_ioda_pe *pe = container_of(table_group, struct pnv_ioda_pe, 2406 table_group); 2407 2408 pnv_pci_ioda2_setup_default_config(pe); 2409 } 2410 2411 static struct iommu_table_group_ops pnv_pci_ioda2_ops = { 2412 .get_table_size = pnv_pci_ioda2_get_table_size, 2413 .create_table = pnv_pci_ioda2_create_table, 2414 .set_window = pnv_pci_ioda2_set_window, 2415 .unset_window = pnv_pci_ioda2_unset_window, 2416 .take_ownership = pnv_ioda2_take_ownership, 2417 .release_ownership = pnv_ioda2_release_ownership, 2418 }; 2419 #endif 2420 2421 static void pnv_pci_ioda_setup_opal_tce_kill(struct pnv_phb *phb) 2422 { 2423 const __be64 *swinvp; 2424 2425 /* OPAL variant of PHB3 invalidated TCEs */ 2426 swinvp = of_get_property(phb->hose->dn, "ibm,opal-tce-kill", NULL); 2427 if (!swinvp) 2428 return; 2429 2430 phb->ioda.tce_inval_reg_phys = be64_to_cpup(swinvp); 2431 phb->ioda.tce_inval_reg = ioremap(phb->ioda.tce_inval_reg_phys, 8); 2432 } 2433 2434 static __be64 *pnv_pci_ioda2_table_do_alloc_pages(int nid, unsigned shift, 2435 unsigned levels, unsigned long limit, 2436 unsigned long *current_offset, unsigned long *total_allocated) 2437 { 2438 struct page *tce_mem = NULL; 2439 __be64 *addr, *tmp; 2440 unsigned order = max_t(unsigned, shift, PAGE_SHIFT) - PAGE_SHIFT; 2441 unsigned long allocated = 1UL << (order + PAGE_SHIFT); 2442 unsigned entries = 1UL << (shift - 3); 2443 long i; 2444 2445 tce_mem = alloc_pages_node(nid, GFP_KERNEL, order); 2446 if (!tce_mem) { 2447 pr_err("Failed to allocate a TCE memory, order=%d\n", order); 2448 return NULL; 2449 } 2450 addr = page_address(tce_mem); 2451 memset(addr, 0, allocated); 2452 *total_allocated += allocated; 2453 2454 --levels; 2455 if (!levels) { 2456 *current_offset += allocated; 2457 return addr; 2458 } 2459 2460 for (i = 0; i < entries; ++i) { 2461 tmp = pnv_pci_ioda2_table_do_alloc_pages(nid, shift, 2462 levels, limit, current_offset, total_allocated); 2463 if (!tmp) 2464 break; 2465 2466 addr[i] = cpu_to_be64(__pa(tmp) | 2467 TCE_PCI_READ | TCE_PCI_WRITE); 2468 2469 if (*current_offset >= limit) 2470 break; 2471 } 2472 2473 return addr; 2474 } 2475 2476 static void pnv_pci_ioda2_table_do_free_pages(__be64 *addr, 2477 unsigned long size, unsigned level); 2478 2479 static long pnv_pci_ioda2_table_alloc_pages(int nid, __u64 bus_offset, 2480 __u32 page_shift, __u64 window_size, __u32 levels, 2481 struct iommu_table *tbl) 2482 { 2483 void *addr; 2484 unsigned long offset = 0, level_shift, total_allocated = 0; 2485 const unsigned window_shift = ilog2(window_size); 2486 unsigned entries_shift = window_shift - page_shift; 2487 unsigned table_shift = max_t(unsigned, entries_shift + 3, PAGE_SHIFT); 2488 const unsigned long tce_table_size = 1UL << table_shift; 2489 2490 if (!levels || (levels > POWERNV_IOMMU_MAX_LEVELS)) 2491 return -EINVAL; 2492 2493 if ((window_size > memory_hotplug_max()) || !is_power_of_2(window_size)) 2494 return -EINVAL; 2495 2496 /* Adjust direct table size from window_size and levels */ 2497 entries_shift = (entries_shift + levels - 1) / levels; 2498 level_shift = entries_shift + 3; 2499 level_shift = max_t(unsigned, level_shift, PAGE_SHIFT); 2500 2501 /* Allocate TCE table */ 2502 addr = pnv_pci_ioda2_table_do_alloc_pages(nid, level_shift, 2503 levels, tce_table_size, &offset, &total_allocated); 2504 2505 /* addr==NULL means that the first level allocation failed */ 2506 if (!addr) 2507 return -ENOMEM; 2508 2509 /* 2510 * First level was allocated but some lower level failed as 2511 * we did not allocate as much as we wanted, 2512 * release partially allocated table. 2513 */ 2514 if (offset < tce_table_size) { 2515 pnv_pci_ioda2_table_do_free_pages(addr, 2516 1ULL << (level_shift - 3), levels - 1); 2517 return -ENOMEM; 2518 } 2519 2520 /* Setup linux iommu table */ 2521 pnv_pci_setup_iommu_table(tbl, addr, tce_table_size, bus_offset, 2522 page_shift); 2523 tbl->it_level_size = 1ULL << (level_shift - 3); 2524 tbl->it_indirect_levels = levels - 1; 2525 tbl->it_allocated_size = total_allocated; 2526 2527 pr_devel("Created TCE table: ws=%08llx ts=%lx @%08llx\n", 2528 window_size, tce_table_size, bus_offset); 2529 2530 return 0; 2531 } 2532 2533 static void pnv_pci_ioda2_table_do_free_pages(__be64 *addr, 2534 unsigned long size, unsigned level) 2535 { 2536 const unsigned long addr_ul = (unsigned long) addr & 2537 ~(TCE_PCI_READ | TCE_PCI_WRITE); 2538 2539 if (level) { 2540 long i; 2541 u64 *tmp = (u64 *) addr_ul; 2542 2543 for (i = 0; i < size; ++i) { 2544 unsigned long hpa = be64_to_cpu(tmp[i]); 2545 2546 if (!(hpa & (TCE_PCI_READ | TCE_PCI_WRITE))) 2547 continue; 2548 2549 pnv_pci_ioda2_table_do_free_pages(__va(hpa), size, 2550 level - 1); 2551 } 2552 } 2553 2554 free_pages(addr_ul, get_order(size << 3)); 2555 } 2556 2557 static void pnv_pci_ioda2_table_free_pages(struct iommu_table *tbl) 2558 { 2559 const unsigned long size = tbl->it_indirect_levels ? 2560 tbl->it_level_size : tbl->it_size; 2561 2562 if (!tbl->it_size) 2563 return; 2564 2565 pnv_pci_ioda2_table_do_free_pages((__be64 *)tbl->it_base, size, 2566 tbl->it_indirect_levels); 2567 } 2568 2569 static void pnv_pci_ioda2_setup_dma_pe(struct pnv_phb *phb, 2570 struct pnv_ioda_pe *pe) 2571 { 2572 int64_t rc; 2573 2574 /* TVE #1 is selected by PCI address bit 59 */ 2575 pe->tce_bypass_base = 1ull << 59; 2576 2577 iommu_register_group(&pe->table_group, phb->hose->global_number, 2578 pe->pe_number); 2579 2580 /* The PE will reserve all possible 32-bits space */ 2581 pe_info(pe, "Setting up 32-bit TCE table at 0..%08x\n", 2582 phb->ioda.m32_pci_base); 2583 2584 /* Setup linux iommu table */ 2585 pe->table_group.tce32_start = 0; 2586 pe->table_group.tce32_size = phb->ioda.m32_pci_base; 2587 pe->table_group.max_dynamic_windows_supported = 2588 IOMMU_TABLE_GROUP_MAX_TABLES; 2589 pe->table_group.max_levels = POWERNV_IOMMU_MAX_LEVELS; 2590 pe->table_group.pgsizes = SZ_4K | SZ_64K | SZ_16M; 2591 #ifdef CONFIG_IOMMU_API 2592 pe->table_group.ops = &pnv_pci_ioda2_ops; 2593 #endif 2594 2595 rc = pnv_pci_ioda2_setup_default_config(pe); 2596 if (rc) 2597 return; 2598 2599 if (pe->flags & PNV_IODA_PE_DEV) 2600 iommu_add_device(&pe->pdev->dev); 2601 else if (pe->flags & (PNV_IODA_PE_BUS | PNV_IODA_PE_BUS_ALL)) 2602 pnv_ioda_setup_bus_dma(pe, pe->pbus); 2603 } 2604 2605 static void pnv_ioda_setup_dma(struct pnv_phb *phb) 2606 { 2607 struct pci_controller *hose = phb->hose; 2608 struct pnv_ioda_pe *pe; 2609 unsigned int weight; 2610 2611 /* If we have more PE# than segments available, hand out one 2612 * per PE until we run out and let the rest fail. If not, 2613 * then we assign at least one segment per PE, plus more based 2614 * on the amount of devices under that PE 2615 */ 2616 pr_info("PCI: Domain %04x has %d available 32-bit DMA segments\n", 2617 hose->global_number, phb->ioda.dma32_count); 2618 2619 pnv_pci_ioda_setup_opal_tce_kill(phb); 2620 2621 /* Walk our PE list and configure their DMA segments */ 2622 list_for_each_entry(pe, &phb->ioda.pe_list, list) { 2623 weight = pnv_pci_ioda_pe_dma_weight(pe); 2624 if (!weight) 2625 continue; 2626 2627 /* 2628 * For IODA2 compliant PHB3, we needn't care about the weight. 2629 * The all available 32-bits DMA space will be assigned to 2630 * the specific PE. 2631 */ 2632 if (phb->type == PNV_PHB_IODA1) { 2633 pnv_pci_ioda1_setup_dma_pe(phb, pe); 2634 } else if (phb->type == PNV_PHB_IODA2) { 2635 pe_info(pe, "Assign DMA32 space\n"); 2636 pnv_pci_ioda2_setup_dma_pe(phb, pe); 2637 } else if (phb->type == PNV_PHB_NPU) { 2638 /* 2639 * We initialise the DMA space for an NPU PHB 2640 * after setup of the PHB is complete as we 2641 * point the NPU TVT to the the same location 2642 * as the PHB3 TVT. 2643 */ 2644 } 2645 } 2646 } 2647 2648 #ifdef CONFIG_PCI_MSI 2649 static void pnv_ioda2_msi_eoi(struct irq_data *d) 2650 { 2651 unsigned int hw_irq = (unsigned int)irqd_to_hwirq(d); 2652 struct irq_chip *chip = irq_data_get_irq_chip(d); 2653 struct pnv_phb *phb = container_of(chip, struct pnv_phb, 2654 ioda.irq_chip); 2655 int64_t rc; 2656 2657 rc = opal_pci_msi_eoi(phb->opal_id, hw_irq); 2658 WARN_ON_ONCE(rc); 2659 2660 icp_native_eoi(d); 2661 } 2662 2663 2664 static void set_msi_irq_chip(struct pnv_phb *phb, unsigned int virq) 2665 { 2666 struct irq_data *idata; 2667 struct irq_chip *ichip; 2668 2669 if (phb->type != PNV_PHB_IODA2) 2670 return; 2671 2672 if (!phb->ioda.irq_chip_init) { 2673 /* 2674 * First time we setup an MSI IRQ, we need to setup the 2675 * corresponding IRQ chip to route correctly. 2676 */ 2677 idata = irq_get_irq_data(virq); 2678 ichip = irq_data_get_irq_chip(idata); 2679 phb->ioda.irq_chip_init = 1; 2680 phb->ioda.irq_chip = *ichip; 2681 phb->ioda.irq_chip.irq_eoi = pnv_ioda2_msi_eoi; 2682 } 2683 irq_set_chip(virq, &phb->ioda.irq_chip); 2684 } 2685 2686 #ifdef CONFIG_CXL_BASE 2687 2688 struct device_node *pnv_pci_get_phb_node(struct pci_dev *dev) 2689 { 2690 struct pci_controller *hose = pci_bus_to_host(dev->bus); 2691 2692 return of_node_get(hose->dn); 2693 } 2694 EXPORT_SYMBOL(pnv_pci_get_phb_node); 2695 2696 int pnv_phb_to_cxl_mode(struct pci_dev *dev, uint64_t mode) 2697 { 2698 struct pci_controller *hose = pci_bus_to_host(dev->bus); 2699 struct pnv_phb *phb = hose->private_data; 2700 struct pnv_ioda_pe *pe; 2701 int rc; 2702 2703 pe = pnv_ioda_get_pe(dev); 2704 if (!pe) 2705 return -ENODEV; 2706 2707 pe_info(pe, "Switching PHB to CXL\n"); 2708 2709 rc = opal_pci_set_phb_cxl_mode(phb->opal_id, mode, pe->pe_number); 2710 if (rc) 2711 dev_err(&dev->dev, "opal_pci_set_phb_cxl_mode failed: %i\n", rc); 2712 2713 return rc; 2714 } 2715 EXPORT_SYMBOL(pnv_phb_to_cxl_mode); 2716 2717 /* Find PHB for cxl dev and allocate MSI hwirqs? 2718 * Returns the absolute hardware IRQ number 2719 */ 2720 int pnv_cxl_alloc_hwirqs(struct pci_dev *dev, int num) 2721 { 2722 struct pci_controller *hose = pci_bus_to_host(dev->bus); 2723 struct pnv_phb *phb = hose->private_data; 2724 int hwirq = msi_bitmap_alloc_hwirqs(&phb->msi_bmp, num); 2725 2726 if (hwirq < 0) { 2727 dev_warn(&dev->dev, "Failed to find a free MSI\n"); 2728 return -ENOSPC; 2729 } 2730 2731 return phb->msi_base + hwirq; 2732 } 2733 EXPORT_SYMBOL(pnv_cxl_alloc_hwirqs); 2734 2735 void pnv_cxl_release_hwirqs(struct pci_dev *dev, int hwirq, int num) 2736 { 2737 struct pci_controller *hose = pci_bus_to_host(dev->bus); 2738 struct pnv_phb *phb = hose->private_data; 2739 2740 msi_bitmap_free_hwirqs(&phb->msi_bmp, hwirq - phb->msi_base, num); 2741 } 2742 EXPORT_SYMBOL(pnv_cxl_release_hwirqs); 2743 2744 void pnv_cxl_release_hwirq_ranges(struct cxl_irq_ranges *irqs, 2745 struct pci_dev *dev) 2746 { 2747 struct pci_controller *hose = pci_bus_to_host(dev->bus); 2748 struct pnv_phb *phb = hose->private_data; 2749 int i, hwirq; 2750 2751 for (i = 1; i < CXL_IRQ_RANGES; i++) { 2752 if (!irqs->range[i]) 2753 continue; 2754 pr_devel("cxl release irq range 0x%x: offset: 0x%lx limit: %ld\n", 2755 i, irqs->offset[i], 2756 irqs->range[i]); 2757 hwirq = irqs->offset[i] - phb->msi_base; 2758 msi_bitmap_free_hwirqs(&phb->msi_bmp, hwirq, 2759 irqs->range[i]); 2760 } 2761 } 2762 EXPORT_SYMBOL(pnv_cxl_release_hwirq_ranges); 2763 2764 int pnv_cxl_alloc_hwirq_ranges(struct cxl_irq_ranges *irqs, 2765 struct pci_dev *dev, int num) 2766 { 2767 struct pci_controller *hose = pci_bus_to_host(dev->bus); 2768 struct pnv_phb *phb = hose->private_data; 2769 int i, hwirq, try; 2770 2771 memset(irqs, 0, sizeof(struct cxl_irq_ranges)); 2772 2773 /* 0 is reserved for the multiplexed PSL DSI interrupt */ 2774 for (i = 1; i < CXL_IRQ_RANGES && num; i++) { 2775 try = num; 2776 while (try) { 2777 hwirq = msi_bitmap_alloc_hwirqs(&phb->msi_bmp, try); 2778 if (hwirq >= 0) 2779 break; 2780 try /= 2; 2781 } 2782 if (!try) 2783 goto fail; 2784 2785 irqs->offset[i] = phb->msi_base + hwirq; 2786 irqs->range[i] = try; 2787 pr_devel("cxl alloc irq range 0x%x: offset: 0x%lx limit: %li\n", 2788 i, irqs->offset[i], irqs->range[i]); 2789 num -= try; 2790 } 2791 if (num) 2792 goto fail; 2793 2794 return 0; 2795 fail: 2796 pnv_cxl_release_hwirq_ranges(irqs, dev); 2797 return -ENOSPC; 2798 } 2799 EXPORT_SYMBOL(pnv_cxl_alloc_hwirq_ranges); 2800 2801 int pnv_cxl_get_irq_count(struct pci_dev *dev) 2802 { 2803 struct pci_controller *hose = pci_bus_to_host(dev->bus); 2804 struct pnv_phb *phb = hose->private_data; 2805 2806 return phb->msi_bmp.irq_count; 2807 } 2808 EXPORT_SYMBOL(pnv_cxl_get_irq_count); 2809 2810 int pnv_cxl_ioda_msi_setup(struct pci_dev *dev, unsigned int hwirq, 2811 unsigned int virq) 2812 { 2813 struct pci_controller *hose = pci_bus_to_host(dev->bus); 2814 struct pnv_phb *phb = hose->private_data; 2815 unsigned int xive_num = hwirq - phb->msi_base; 2816 struct pnv_ioda_pe *pe; 2817 int rc; 2818 2819 if (!(pe = pnv_ioda_get_pe(dev))) 2820 return -ENODEV; 2821 2822 /* Assign XIVE to PE */ 2823 rc = opal_pci_set_xive_pe(phb->opal_id, pe->pe_number, xive_num); 2824 if (rc) { 2825 pe_warn(pe, "%s: OPAL error %d setting msi_base 0x%x " 2826 "hwirq 0x%x XIVE 0x%x PE\n", 2827 pci_name(dev), rc, phb->msi_base, hwirq, xive_num); 2828 return -EIO; 2829 } 2830 set_msi_irq_chip(phb, virq); 2831 2832 return 0; 2833 } 2834 EXPORT_SYMBOL(pnv_cxl_ioda_msi_setup); 2835 #endif 2836 2837 static int pnv_pci_ioda_msi_setup(struct pnv_phb *phb, struct pci_dev *dev, 2838 unsigned int hwirq, unsigned int virq, 2839 unsigned int is_64, struct msi_msg *msg) 2840 { 2841 struct pnv_ioda_pe *pe = pnv_ioda_get_pe(dev); 2842 unsigned int xive_num = hwirq - phb->msi_base; 2843 __be32 data; 2844 int rc; 2845 2846 /* No PE assigned ? bail out ... no MSI for you ! */ 2847 if (pe == NULL) 2848 return -ENXIO; 2849 2850 /* Check if we have an MVE */ 2851 if (pe->mve_number < 0) 2852 return -ENXIO; 2853 2854 /* Force 32-bit MSI on some broken devices */ 2855 if (dev->no_64bit_msi) 2856 is_64 = 0; 2857 2858 /* Assign XIVE to PE */ 2859 rc = opal_pci_set_xive_pe(phb->opal_id, pe->pe_number, xive_num); 2860 if (rc) { 2861 pr_warn("%s: OPAL error %d setting XIVE %d PE\n", 2862 pci_name(dev), rc, xive_num); 2863 return -EIO; 2864 } 2865 2866 if (is_64) { 2867 __be64 addr64; 2868 2869 rc = opal_get_msi_64(phb->opal_id, pe->mve_number, xive_num, 1, 2870 &addr64, &data); 2871 if (rc) { 2872 pr_warn("%s: OPAL error %d getting 64-bit MSI data\n", 2873 pci_name(dev), rc); 2874 return -EIO; 2875 } 2876 msg->address_hi = be64_to_cpu(addr64) >> 32; 2877 msg->address_lo = be64_to_cpu(addr64) & 0xfffffffful; 2878 } else { 2879 __be32 addr32; 2880 2881 rc = opal_get_msi_32(phb->opal_id, pe->mve_number, xive_num, 1, 2882 &addr32, &data); 2883 if (rc) { 2884 pr_warn("%s: OPAL error %d getting 32-bit MSI data\n", 2885 pci_name(dev), rc); 2886 return -EIO; 2887 } 2888 msg->address_hi = 0; 2889 msg->address_lo = be32_to_cpu(addr32); 2890 } 2891 msg->data = be32_to_cpu(data); 2892 2893 set_msi_irq_chip(phb, virq); 2894 2895 pr_devel("%s: %s-bit MSI on hwirq %x (xive #%d)," 2896 " address=%x_%08x data=%x PE# %d\n", 2897 pci_name(dev), is_64 ? "64" : "32", hwirq, xive_num, 2898 msg->address_hi, msg->address_lo, data, pe->pe_number); 2899 2900 return 0; 2901 } 2902 2903 static void pnv_pci_init_ioda_msis(struct pnv_phb *phb) 2904 { 2905 unsigned int count; 2906 const __be32 *prop = of_get_property(phb->hose->dn, 2907 "ibm,opal-msi-ranges", NULL); 2908 if (!prop) { 2909 /* BML Fallback */ 2910 prop = of_get_property(phb->hose->dn, "msi-ranges", NULL); 2911 } 2912 if (!prop) 2913 return; 2914 2915 phb->msi_base = be32_to_cpup(prop); 2916 count = be32_to_cpup(prop + 1); 2917 if (msi_bitmap_alloc(&phb->msi_bmp, count, phb->hose->dn)) { 2918 pr_err("PCI %d: Failed to allocate MSI bitmap !\n", 2919 phb->hose->global_number); 2920 return; 2921 } 2922 2923 phb->msi_setup = pnv_pci_ioda_msi_setup; 2924 phb->msi32_support = 1; 2925 pr_info(" Allocated bitmap for %d MSIs (base IRQ 0x%x)\n", 2926 count, phb->msi_base); 2927 } 2928 #else 2929 static void pnv_pci_init_ioda_msis(struct pnv_phb *phb) { } 2930 #endif /* CONFIG_PCI_MSI */ 2931 2932 #ifdef CONFIG_PCI_IOV 2933 static void pnv_pci_ioda_fixup_iov_resources(struct pci_dev *pdev) 2934 { 2935 struct pci_controller *hose = pci_bus_to_host(pdev->bus); 2936 struct pnv_phb *phb = hose->private_data; 2937 const resource_size_t gate = phb->ioda.m64_segsize >> 2; 2938 struct resource *res; 2939 int i; 2940 resource_size_t size, total_vf_bar_sz; 2941 struct pci_dn *pdn; 2942 int mul, total_vfs; 2943 2944 if (!pdev->is_physfn || pdev->is_added) 2945 return; 2946 2947 pdn = pci_get_pdn(pdev); 2948 pdn->vfs_expanded = 0; 2949 pdn->m64_single_mode = false; 2950 2951 total_vfs = pci_sriov_get_totalvfs(pdev); 2952 mul = phb->ioda.total_pe_num; 2953 total_vf_bar_sz = 0; 2954 2955 for (i = 0; i < PCI_SRIOV_NUM_BARS; i++) { 2956 res = &pdev->resource[i + PCI_IOV_RESOURCES]; 2957 if (!res->flags || res->parent) 2958 continue; 2959 if (!pnv_pci_is_mem_pref_64(res->flags)) { 2960 dev_warn(&pdev->dev, "Don't support SR-IOV with" 2961 " non M64 VF BAR%d: %pR. \n", 2962 i, res); 2963 goto truncate_iov; 2964 } 2965 2966 total_vf_bar_sz += pci_iov_resource_size(pdev, 2967 i + PCI_IOV_RESOURCES); 2968 2969 /* 2970 * If bigger than quarter of M64 segment size, just round up 2971 * power of two. 2972 * 2973 * Generally, one M64 BAR maps one IOV BAR. To avoid conflict 2974 * with other devices, IOV BAR size is expanded to be 2975 * (total_pe * VF_BAR_size). When VF_BAR_size is half of M64 2976 * segment size , the expanded size would equal to half of the 2977 * whole M64 space size, which will exhaust the M64 Space and 2978 * limit the system flexibility. This is a design decision to 2979 * set the boundary to quarter of the M64 segment size. 2980 */ 2981 if (total_vf_bar_sz > gate) { 2982 mul = roundup_pow_of_two(total_vfs); 2983 dev_info(&pdev->dev, 2984 "VF BAR Total IOV size %llx > %llx, roundup to %d VFs\n", 2985 total_vf_bar_sz, gate, mul); 2986 pdn->m64_single_mode = true; 2987 break; 2988 } 2989 } 2990 2991 for (i = 0; i < PCI_SRIOV_NUM_BARS; i++) { 2992 res = &pdev->resource[i + PCI_IOV_RESOURCES]; 2993 if (!res->flags || res->parent) 2994 continue; 2995 2996 size = pci_iov_resource_size(pdev, i + PCI_IOV_RESOURCES); 2997 /* 2998 * On PHB3, the minimum size alignment of M64 BAR in single 2999 * mode is 32MB. 3000 */ 3001 if (pdn->m64_single_mode && (size < SZ_32M)) 3002 goto truncate_iov; 3003 dev_dbg(&pdev->dev, " Fixing VF BAR%d: %pR to\n", i, res); 3004 res->end = res->start + size * mul - 1; 3005 dev_dbg(&pdev->dev, " %pR\n", res); 3006 dev_info(&pdev->dev, "VF BAR%d: %pR (expanded to %d VFs for PE alignment)", 3007 i, res, mul); 3008 } 3009 pdn->vfs_expanded = mul; 3010 3011 return; 3012 3013 truncate_iov: 3014 /* To save MMIO space, IOV BAR is truncated. */ 3015 for (i = 0; i < PCI_SRIOV_NUM_BARS; i++) { 3016 res = &pdev->resource[i + PCI_IOV_RESOURCES]; 3017 res->flags = 0; 3018 res->end = res->start - 1; 3019 } 3020 } 3021 #endif /* CONFIG_PCI_IOV */ 3022 3023 static void pnv_ioda_setup_pe_res(struct pnv_ioda_pe *pe, 3024 struct resource *res) 3025 { 3026 struct pnv_phb *phb = pe->phb; 3027 struct pci_bus_region region; 3028 int index; 3029 int64_t rc; 3030 3031 if (!res || !res->flags || res->start > res->end) 3032 return; 3033 3034 if (res->flags & IORESOURCE_IO) { 3035 region.start = res->start - phb->ioda.io_pci_base; 3036 region.end = res->end - phb->ioda.io_pci_base; 3037 index = region.start / phb->ioda.io_segsize; 3038 3039 while (index < phb->ioda.total_pe_num && 3040 region.start <= region.end) { 3041 phb->ioda.io_segmap[index] = pe->pe_number; 3042 rc = opal_pci_map_pe_mmio_window(phb->opal_id, 3043 pe->pe_number, OPAL_IO_WINDOW_TYPE, 0, index); 3044 if (rc != OPAL_SUCCESS) { 3045 pr_err("%s: Error %lld mapping IO segment#%d to PE#%d\n", 3046 __func__, rc, index, pe->pe_number); 3047 break; 3048 } 3049 3050 region.start += phb->ioda.io_segsize; 3051 index++; 3052 } 3053 } else if ((res->flags & IORESOURCE_MEM) && 3054 !pnv_pci_is_mem_pref_64(res->flags)) { 3055 region.start = res->start - 3056 phb->hose->mem_offset[0] - 3057 phb->ioda.m32_pci_base; 3058 region.end = res->end - 3059 phb->hose->mem_offset[0] - 3060 phb->ioda.m32_pci_base; 3061 index = region.start / phb->ioda.m32_segsize; 3062 3063 while (index < phb->ioda.total_pe_num && 3064 region.start <= region.end) { 3065 phb->ioda.m32_segmap[index] = pe->pe_number; 3066 rc = opal_pci_map_pe_mmio_window(phb->opal_id, 3067 pe->pe_number, OPAL_M32_WINDOW_TYPE, 0, index); 3068 if (rc != OPAL_SUCCESS) { 3069 pr_err("%s: Error %lld mapping M32 segment#%d to PE#%d", 3070 __func__, rc, index, pe->pe_number); 3071 break; 3072 } 3073 3074 region.start += phb->ioda.m32_segsize; 3075 index++; 3076 } 3077 } 3078 } 3079 3080 /* 3081 * This function is supposed to be called on basis of PE from top 3082 * to bottom style. So the the I/O or MMIO segment assigned to 3083 * parent PE could be overrided by its child PEs if necessary. 3084 */ 3085 static void pnv_ioda_setup_pe_seg(struct pnv_ioda_pe *pe) 3086 { 3087 struct pci_dev *pdev; 3088 int i; 3089 3090 /* 3091 * NOTE: We only care PCI bus based PE for now. For PCI 3092 * device based PE, for example SRIOV sensitive VF should 3093 * be figured out later. 3094 */ 3095 BUG_ON(!(pe->flags & (PNV_IODA_PE_BUS | PNV_IODA_PE_BUS_ALL))); 3096 3097 list_for_each_entry(pdev, &pe->pbus->devices, bus_list) { 3098 for (i = 0; i <= PCI_ROM_RESOURCE; i++) 3099 pnv_ioda_setup_pe_res(pe, &pdev->resource[i]); 3100 3101 /* 3102 * If the PE contains all subordinate PCI buses, the 3103 * windows of the child bridges should be mapped to 3104 * the PE as well. 3105 */ 3106 if (!(pe->flags & PNV_IODA_PE_BUS_ALL) || !pci_is_bridge(pdev)) 3107 continue; 3108 for (i = 0; i < PCI_BRIDGE_RESOURCE_NUM; i++) 3109 pnv_ioda_setup_pe_res(pe, 3110 &pdev->resource[PCI_BRIDGE_RESOURCES + i]); 3111 } 3112 } 3113 3114 static void pnv_pci_ioda_setup_seg(void) 3115 { 3116 struct pci_controller *tmp, *hose; 3117 struct pnv_phb *phb; 3118 struct pnv_ioda_pe *pe; 3119 3120 list_for_each_entry_safe(hose, tmp, &hose_list, list_node) { 3121 phb = hose->private_data; 3122 3123 /* NPU PHB does not support IO or MMIO segmentation */ 3124 if (phb->type == PNV_PHB_NPU) 3125 continue; 3126 3127 list_for_each_entry(pe, &phb->ioda.pe_list, list) { 3128 pnv_ioda_setup_pe_seg(pe); 3129 } 3130 } 3131 } 3132 3133 static void pnv_pci_ioda_setup_DMA(void) 3134 { 3135 struct pci_controller *hose, *tmp; 3136 struct pnv_phb *phb; 3137 3138 list_for_each_entry_safe(hose, tmp, &hose_list, list_node) { 3139 pnv_ioda_setup_dma(hose->private_data); 3140 3141 /* Mark the PHB initialization done */ 3142 phb = hose->private_data; 3143 phb->initialized = 1; 3144 } 3145 } 3146 3147 static void pnv_pci_ioda_create_dbgfs(void) 3148 { 3149 #ifdef CONFIG_DEBUG_FS 3150 struct pci_controller *hose, *tmp; 3151 struct pnv_phb *phb; 3152 char name[16]; 3153 3154 list_for_each_entry_safe(hose, tmp, &hose_list, list_node) { 3155 phb = hose->private_data; 3156 3157 sprintf(name, "PCI%04x", hose->global_number); 3158 phb->dbgfs = debugfs_create_dir(name, powerpc_debugfs_root); 3159 if (!phb->dbgfs) 3160 pr_warning("%s: Error on creating debugfs on PHB#%x\n", 3161 __func__, hose->global_number); 3162 } 3163 #endif /* CONFIG_DEBUG_FS */ 3164 } 3165 3166 static void pnv_npu_ioda_fixup(void) 3167 { 3168 bool enable_bypass; 3169 struct pci_controller *hose, *tmp; 3170 struct pnv_phb *phb; 3171 struct pnv_ioda_pe *pe; 3172 unsigned int weight; 3173 3174 list_for_each_entry_safe(hose, tmp, &hose_list, list_node) { 3175 phb = hose->private_data; 3176 if (phb->type != PNV_PHB_NPU) 3177 continue; 3178 3179 list_for_each_entry(pe, &phb->ioda.pe_list, list) { 3180 weight = pnv_pci_ioda_pe_dma_weight(pe); 3181 if (WARN_ON(!weight)) 3182 continue; 3183 3184 enable_bypass = dma_get_mask(&pe->pdev->dev) == 3185 DMA_BIT_MASK(64); 3186 pnv_npu_init_dma_pe(pe); 3187 } 3188 } 3189 } 3190 3191 static void pnv_pci_ioda_fixup(void) 3192 { 3193 pnv_pci_ioda_setup_PEs(); 3194 pnv_pci_ioda_setup_seg(); 3195 pnv_pci_ioda_setup_DMA(); 3196 3197 pnv_pci_ioda_create_dbgfs(); 3198 3199 #ifdef CONFIG_EEH 3200 eeh_init(); 3201 eeh_addr_cache_build(); 3202 #endif 3203 3204 /* Link NPU IODA tables to their PCI devices. */ 3205 pnv_npu_ioda_fixup(); 3206 } 3207 3208 /* 3209 * Returns the alignment for I/O or memory windows for P2P 3210 * bridges. That actually depends on how PEs are segmented. 3211 * For now, we return I/O or M32 segment size for PE sensitive 3212 * P2P bridges. Otherwise, the default values (4KiB for I/O, 3213 * 1MiB for memory) will be returned. 3214 * 3215 * The current PCI bus might be put into one PE, which was 3216 * create against the parent PCI bridge. For that case, we 3217 * needn't enlarge the alignment so that we can save some 3218 * resources. 3219 */ 3220 static resource_size_t pnv_pci_window_alignment(struct pci_bus *bus, 3221 unsigned long type) 3222 { 3223 struct pci_dev *bridge; 3224 struct pci_controller *hose = pci_bus_to_host(bus); 3225 struct pnv_phb *phb = hose->private_data; 3226 int num_pci_bridges = 0; 3227 3228 bridge = bus->self; 3229 while (bridge) { 3230 if (pci_pcie_type(bridge) == PCI_EXP_TYPE_PCI_BRIDGE) { 3231 num_pci_bridges++; 3232 if (num_pci_bridges >= 2) 3233 return 1; 3234 } 3235 3236 bridge = bridge->bus->self; 3237 } 3238 3239 /* We fail back to M32 if M64 isn't supported */ 3240 if (phb->ioda.m64_segsize && 3241 pnv_pci_is_mem_pref_64(type)) 3242 return phb->ioda.m64_segsize; 3243 if (type & IORESOURCE_MEM) 3244 return phb->ioda.m32_segsize; 3245 3246 return phb->ioda.io_segsize; 3247 } 3248 3249 #ifdef CONFIG_PCI_IOV 3250 static resource_size_t pnv_pci_iov_resource_alignment(struct pci_dev *pdev, 3251 int resno) 3252 { 3253 struct pci_controller *hose = pci_bus_to_host(pdev->bus); 3254 struct pnv_phb *phb = hose->private_data; 3255 struct pci_dn *pdn = pci_get_pdn(pdev); 3256 resource_size_t align; 3257 3258 /* 3259 * On PowerNV platform, IOV BAR is mapped by M64 BAR to enable the 3260 * SR-IOV. While from hardware perspective, the range mapped by M64 3261 * BAR should be size aligned. 3262 * 3263 * When IOV BAR is mapped with M64 BAR in Single PE mode, the extra 3264 * powernv-specific hardware restriction is gone. But if just use the 3265 * VF BAR size as the alignment, PF BAR / VF BAR may be allocated with 3266 * in one segment of M64 #15, which introduces the PE conflict between 3267 * PF and VF. Based on this, the minimum alignment of an IOV BAR is 3268 * m64_segsize. 3269 * 3270 * This function returns the total IOV BAR size if M64 BAR is in 3271 * Shared PE mode or just VF BAR size if not. 3272 * If the M64 BAR is in Single PE mode, return the VF BAR size or 3273 * M64 segment size if IOV BAR size is less. 3274 */ 3275 align = pci_iov_resource_size(pdev, resno); 3276 if (!pdn->vfs_expanded) 3277 return align; 3278 if (pdn->m64_single_mode) 3279 return max(align, (resource_size_t)phb->ioda.m64_segsize); 3280 3281 return pdn->vfs_expanded * align; 3282 } 3283 #endif /* CONFIG_PCI_IOV */ 3284 3285 /* Prevent enabling devices for which we couldn't properly 3286 * assign a PE 3287 */ 3288 static bool pnv_pci_enable_device_hook(struct pci_dev *dev) 3289 { 3290 struct pci_controller *hose = pci_bus_to_host(dev->bus); 3291 struct pnv_phb *phb = hose->private_data; 3292 struct pci_dn *pdn; 3293 3294 /* The function is probably called while the PEs have 3295 * not be created yet. For example, resource reassignment 3296 * during PCI probe period. We just skip the check if 3297 * PEs isn't ready. 3298 */ 3299 if (!phb->initialized) 3300 return true; 3301 3302 pdn = pci_get_pdn(dev); 3303 if (!pdn || pdn->pe_number == IODA_INVALID_PE) 3304 return false; 3305 3306 return true; 3307 } 3308 3309 static void pnv_pci_ioda_shutdown(struct pci_controller *hose) 3310 { 3311 struct pnv_phb *phb = hose->private_data; 3312 3313 opal_pci_reset(phb->opal_id, OPAL_RESET_PCI_IODA_TABLE, 3314 OPAL_ASSERT_RESET); 3315 } 3316 3317 static const struct pci_controller_ops pnv_pci_ioda_controller_ops = { 3318 .dma_dev_setup = pnv_pci_dma_dev_setup, 3319 .dma_bus_setup = pnv_pci_dma_bus_setup, 3320 #ifdef CONFIG_PCI_MSI 3321 .setup_msi_irqs = pnv_setup_msi_irqs, 3322 .teardown_msi_irqs = pnv_teardown_msi_irqs, 3323 #endif 3324 .enable_device_hook = pnv_pci_enable_device_hook, 3325 .window_alignment = pnv_pci_window_alignment, 3326 .reset_secondary_bus = pnv_pci_reset_secondary_bus, 3327 .dma_set_mask = pnv_pci_ioda_dma_set_mask, 3328 .dma_get_required_mask = pnv_pci_ioda_dma_get_required_mask, 3329 .shutdown = pnv_pci_ioda_shutdown, 3330 }; 3331 3332 static int pnv_npu_dma_set_mask(struct pci_dev *npdev, u64 dma_mask) 3333 { 3334 dev_err_once(&npdev->dev, 3335 "%s operation unsupported for NVLink devices\n", 3336 __func__); 3337 return -EPERM; 3338 } 3339 3340 static const struct pci_controller_ops pnv_npu_ioda_controller_ops = { 3341 .dma_dev_setup = pnv_pci_dma_dev_setup, 3342 #ifdef CONFIG_PCI_MSI 3343 .setup_msi_irqs = pnv_setup_msi_irqs, 3344 .teardown_msi_irqs = pnv_teardown_msi_irqs, 3345 #endif 3346 .enable_device_hook = pnv_pci_enable_device_hook, 3347 .window_alignment = pnv_pci_window_alignment, 3348 .reset_secondary_bus = pnv_pci_reset_secondary_bus, 3349 .dma_set_mask = pnv_npu_dma_set_mask, 3350 .shutdown = pnv_pci_ioda_shutdown, 3351 }; 3352 3353 static void __init pnv_pci_init_ioda_phb(struct device_node *np, 3354 u64 hub_id, int ioda_type) 3355 { 3356 struct pci_controller *hose; 3357 struct pnv_phb *phb; 3358 unsigned long size, m64map_off, m32map_off, pemap_off; 3359 unsigned long iomap_off = 0, dma32map_off = 0; 3360 const __be64 *prop64; 3361 const __be32 *prop32; 3362 int len; 3363 unsigned int segno; 3364 u64 phb_id; 3365 void *aux; 3366 long rc; 3367 3368 pr_info("Initializing IODA%d OPAL PHB %s\n", ioda_type, np->full_name); 3369 3370 prop64 = of_get_property(np, "ibm,opal-phbid", NULL); 3371 if (!prop64) { 3372 pr_err(" Missing \"ibm,opal-phbid\" property !\n"); 3373 return; 3374 } 3375 phb_id = be64_to_cpup(prop64); 3376 pr_debug(" PHB-ID : 0x%016llx\n", phb_id); 3377 3378 phb = memblock_virt_alloc(sizeof(struct pnv_phb), 0); 3379 3380 /* Allocate PCI controller */ 3381 phb->hose = hose = pcibios_alloc_controller(np); 3382 if (!phb->hose) { 3383 pr_err(" Can't allocate PCI controller for %s\n", 3384 np->full_name); 3385 memblock_free(__pa(phb), sizeof(struct pnv_phb)); 3386 return; 3387 } 3388 3389 spin_lock_init(&phb->lock); 3390 prop32 = of_get_property(np, "bus-range", &len); 3391 if (prop32 && len == 8) { 3392 hose->first_busno = be32_to_cpu(prop32[0]); 3393 hose->last_busno = be32_to_cpu(prop32[1]); 3394 } else { 3395 pr_warn(" Broken <bus-range> on %s\n", np->full_name); 3396 hose->first_busno = 0; 3397 hose->last_busno = 0xff; 3398 } 3399 hose->private_data = phb; 3400 phb->hub_id = hub_id; 3401 phb->opal_id = phb_id; 3402 phb->type = ioda_type; 3403 mutex_init(&phb->ioda.pe_alloc_mutex); 3404 3405 /* Detect specific models for error handling */ 3406 if (of_device_is_compatible(np, "ibm,p7ioc-pciex")) 3407 phb->model = PNV_PHB_MODEL_P7IOC; 3408 else if (of_device_is_compatible(np, "ibm,power8-pciex")) 3409 phb->model = PNV_PHB_MODEL_PHB3; 3410 else if (of_device_is_compatible(np, "ibm,power8-npu-pciex")) 3411 phb->model = PNV_PHB_MODEL_NPU; 3412 else 3413 phb->model = PNV_PHB_MODEL_UNKNOWN; 3414 3415 /* Parse 32-bit and IO ranges (if any) */ 3416 pci_process_bridge_OF_ranges(hose, np, !hose->global_number); 3417 3418 /* Get registers */ 3419 phb->regs = of_iomap(np, 0); 3420 if (phb->regs == NULL) 3421 pr_err(" Failed to map registers !\n"); 3422 3423 /* Initialize more IODA stuff */ 3424 phb->ioda.total_pe_num = 1; 3425 prop32 = of_get_property(np, "ibm,opal-num-pes", NULL); 3426 if (prop32) 3427 phb->ioda.total_pe_num = be32_to_cpup(prop32); 3428 prop32 = of_get_property(np, "ibm,opal-reserved-pe", NULL); 3429 if (prop32) 3430 phb->ioda.reserved_pe_idx = be32_to_cpup(prop32); 3431 3432 /* Parse 64-bit MMIO range */ 3433 pnv_ioda_parse_m64_window(phb); 3434 3435 phb->ioda.m32_size = resource_size(&hose->mem_resources[0]); 3436 /* FW Has already off top 64k of M32 space (MSI space) */ 3437 phb->ioda.m32_size += 0x10000; 3438 3439 phb->ioda.m32_segsize = phb->ioda.m32_size / phb->ioda.total_pe_num; 3440 phb->ioda.m32_pci_base = hose->mem_resources[0].start - hose->mem_offset[0]; 3441 phb->ioda.io_size = hose->pci_io_size; 3442 phb->ioda.io_segsize = phb->ioda.io_size / phb->ioda.total_pe_num; 3443 phb->ioda.io_pci_base = 0; /* XXX calculate this ? */ 3444 3445 /* Calculate how many 32-bit TCE segments we have */ 3446 phb->ioda.dma32_count = phb->ioda.m32_pci_base / 3447 PNV_IODA1_DMA32_SEGSIZE; 3448 3449 /* Allocate aux data & arrays. We don't have IO ports on PHB3 */ 3450 size = _ALIGN_UP(phb->ioda.total_pe_num / 8, sizeof(unsigned long)); 3451 m64map_off = size; 3452 size += phb->ioda.total_pe_num * sizeof(phb->ioda.m64_segmap[0]); 3453 m32map_off = size; 3454 size += phb->ioda.total_pe_num * sizeof(phb->ioda.m32_segmap[0]); 3455 if (phb->type == PNV_PHB_IODA1) { 3456 iomap_off = size; 3457 size += phb->ioda.total_pe_num * sizeof(phb->ioda.io_segmap[0]); 3458 dma32map_off = size; 3459 size += phb->ioda.dma32_count * 3460 sizeof(phb->ioda.dma32_segmap[0]); 3461 } 3462 pemap_off = size; 3463 size += phb->ioda.total_pe_num * sizeof(struct pnv_ioda_pe); 3464 aux = memblock_virt_alloc(size, 0); 3465 phb->ioda.pe_alloc = aux; 3466 phb->ioda.m64_segmap = aux + m64map_off; 3467 phb->ioda.m32_segmap = aux + m32map_off; 3468 for (segno = 0; segno < phb->ioda.total_pe_num; segno++) { 3469 phb->ioda.m64_segmap[segno] = IODA_INVALID_PE; 3470 phb->ioda.m32_segmap[segno] = IODA_INVALID_PE; 3471 } 3472 if (phb->type == PNV_PHB_IODA1) { 3473 phb->ioda.io_segmap = aux + iomap_off; 3474 for (segno = 0; segno < phb->ioda.total_pe_num; segno++) 3475 phb->ioda.io_segmap[segno] = IODA_INVALID_PE; 3476 3477 phb->ioda.dma32_segmap = aux + dma32map_off; 3478 for (segno = 0; segno < phb->ioda.dma32_count; segno++) 3479 phb->ioda.dma32_segmap[segno] = IODA_INVALID_PE; 3480 } 3481 phb->ioda.pe_array = aux + pemap_off; 3482 set_bit(phb->ioda.reserved_pe_idx, phb->ioda.pe_alloc); 3483 3484 INIT_LIST_HEAD(&phb->ioda.pe_list); 3485 mutex_init(&phb->ioda.pe_list_mutex); 3486 3487 /* Calculate how many 32-bit TCE segments we have */ 3488 phb->ioda.dma32_count = phb->ioda.m32_pci_base / 3489 PNV_IODA1_DMA32_SEGSIZE; 3490 3491 #if 0 /* We should really do that ... */ 3492 rc = opal_pci_set_phb_mem_window(opal->phb_id, 3493 window_type, 3494 window_num, 3495 starting_real_address, 3496 starting_pci_address, 3497 segment_size); 3498 #endif 3499 3500 pr_info(" %03d (%03d) PE's M32: 0x%x [segment=0x%x]\n", 3501 phb->ioda.total_pe_num, phb->ioda.reserved_pe_idx, 3502 phb->ioda.m32_size, phb->ioda.m32_segsize); 3503 if (phb->ioda.m64_size) 3504 pr_info(" M64: 0x%lx [segment=0x%lx]\n", 3505 phb->ioda.m64_size, phb->ioda.m64_segsize); 3506 if (phb->ioda.io_size) 3507 pr_info(" IO: 0x%x [segment=0x%x]\n", 3508 phb->ioda.io_size, phb->ioda.io_segsize); 3509 3510 3511 phb->hose->ops = &pnv_pci_ops; 3512 phb->get_pe_state = pnv_ioda_get_pe_state; 3513 phb->freeze_pe = pnv_ioda_freeze_pe; 3514 phb->unfreeze_pe = pnv_ioda_unfreeze_pe; 3515 3516 /* Setup MSI support */ 3517 pnv_pci_init_ioda_msis(phb); 3518 3519 /* 3520 * We pass the PCI probe flag PCI_REASSIGN_ALL_RSRC here 3521 * to let the PCI core do resource assignment. It's supposed 3522 * that the PCI core will do correct I/O and MMIO alignment 3523 * for the P2P bridge bars so that each PCI bus (excluding 3524 * the child P2P bridges) can form individual PE. 3525 */ 3526 ppc_md.pcibios_fixup = pnv_pci_ioda_fixup; 3527 3528 if (phb->type == PNV_PHB_NPU) { 3529 hose->controller_ops = pnv_npu_ioda_controller_ops; 3530 } else { 3531 phb->dma_dev_setup = pnv_pci_ioda_dma_dev_setup; 3532 hose->controller_ops = pnv_pci_ioda_controller_ops; 3533 } 3534 3535 #ifdef CONFIG_PCI_IOV 3536 ppc_md.pcibios_fixup_sriov = pnv_pci_ioda_fixup_iov_resources; 3537 ppc_md.pcibios_iov_resource_alignment = pnv_pci_iov_resource_alignment; 3538 #endif 3539 3540 pci_add_flags(PCI_REASSIGN_ALL_RSRC); 3541 3542 /* Reset IODA tables to a clean state */ 3543 rc = opal_pci_reset(phb_id, OPAL_RESET_PCI_IODA_TABLE, OPAL_ASSERT_RESET); 3544 if (rc) 3545 pr_warning(" OPAL Error %ld performing IODA table reset !\n", rc); 3546 3547 /* If we're running in kdump kerenl, the previous kerenl never 3548 * shutdown PCI devices correctly. We already got IODA table 3549 * cleaned out. So we have to issue PHB reset to stop all PCI 3550 * transactions from previous kerenl. 3551 */ 3552 if (is_kdump_kernel()) { 3553 pr_info(" Issue PHB reset ...\n"); 3554 pnv_eeh_phb_reset(hose, EEH_RESET_FUNDAMENTAL); 3555 pnv_eeh_phb_reset(hose, EEH_RESET_DEACTIVATE); 3556 } 3557 3558 /* Remove M64 resource if we can't configure it successfully */ 3559 if (!phb->init_m64 || phb->init_m64(phb)) 3560 hose->mem_resources[1].flags = 0; 3561 } 3562 3563 void __init pnv_pci_init_ioda2_phb(struct device_node *np) 3564 { 3565 pnv_pci_init_ioda_phb(np, 0, PNV_PHB_IODA2); 3566 } 3567 3568 void __init pnv_pci_init_npu_phb(struct device_node *np) 3569 { 3570 pnv_pci_init_ioda_phb(np, 0, PNV_PHB_NPU); 3571 } 3572 3573 void __init pnv_pci_init_ioda_hub(struct device_node *np) 3574 { 3575 struct device_node *phbn; 3576 const __be64 *prop64; 3577 u64 hub_id; 3578 3579 pr_info("Probing IODA IO-Hub %s\n", np->full_name); 3580 3581 prop64 = of_get_property(np, "ibm,opal-hubid", NULL); 3582 if (!prop64) { 3583 pr_err(" Missing \"ibm,opal-hubid\" property !\n"); 3584 return; 3585 } 3586 hub_id = be64_to_cpup(prop64); 3587 pr_devel(" HUB-ID : 0x%016llx\n", hub_id); 3588 3589 /* Count child PHBs */ 3590 for_each_child_of_node(np, phbn) { 3591 /* Look for IODA1 PHBs */ 3592 if (of_device_is_compatible(phbn, "ibm,ioda-phb")) 3593 pnv_pci_init_ioda_phb(phbn, hub_id, PNV_PHB_IODA1); 3594 } 3595 } 3596