1 /* 2 * Support PCI/PCIe on PowerNV platforms 3 * 4 * Copyright 2011 Benjamin Herrenschmidt, IBM Corp. 5 * 6 * This program is free software; you can redistribute it and/or 7 * modify it under the terms of the GNU General Public License 8 * as published by the Free Software Foundation; either version 9 * 2 of the License, or (at your option) any later version. 10 */ 11 12 #undef DEBUG 13 14 #include <linux/kernel.h> 15 #include <linux/pci.h> 16 #include <linux/crash_dump.h> 17 #include <linux/delay.h> 18 #include <linux/string.h> 19 #include <linux/init.h> 20 #include <linux/bootmem.h> 21 #include <linux/irq.h> 22 #include <linux/io.h> 23 #include <linux/msi.h> 24 #include <linux/memblock.h> 25 #include <linux/iommu.h> 26 #include <linux/rculist.h> 27 #include <linux/sizes.h> 28 29 #include <asm/sections.h> 30 #include <asm/io.h> 31 #include <asm/prom.h> 32 #include <asm/pci-bridge.h> 33 #include <asm/machdep.h> 34 #include <asm/msi_bitmap.h> 35 #include <asm/ppc-pci.h> 36 #include <asm/opal.h> 37 #include <asm/iommu.h> 38 #include <asm/tce.h> 39 #include <asm/xics.h> 40 #include <asm/debugfs.h> 41 #include <asm/firmware.h> 42 #include <asm/pnv-pci.h> 43 #include <asm/mmzone.h> 44 45 #include <misc/cxl-base.h> 46 47 #include "powernv.h" 48 #include "pci.h" 49 #include "../../../../drivers/pci/pci.h" 50 51 #define PNV_IODA1_M64_NUM 16 /* Number of M64 BARs */ 52 #define PNV_IODA1_M64_SEGS 8 /* Segments per M64 BAR */ 53 #define PNV_IODA1_DMA32_SEGSIZE 0x10000000 54 55 #define POWERNV_IOMMU_DEFAULT_LEVELS 1 56 #define POWERNV_IOMMU_MAX_LEVELS 5 57 58 static const char * const pnv_phb_names[] = { "IODA1", "IODA2", "NPU_NVLINK", 59 "NPU_OCAPI" }; 60 static void pnv_pci_ioda2_table_free_pages(struct iommu_table *tbl); 61 62 void pe_level_printk(const struct pnv_ioda_pe *pe, const char *level, 63 const char *fmt, ...) 64 { 65 struct va_format vaf; 66 va_list args; 67 char pfix[32]; 68 69 va_start(args, fmt); 70 71 vaf.fmt = fmt; 72 vaf.va = &args; 73 74 if (pe->flags & PNV_IODA_PE_DEV) 75 strlcpy(pfix, dev_name(&pe->pdev->dev), sizeof(pfix)); 76 else if (pe->flags & (PNV_IODA_PE_BUS | PNV_IODA_PE_BUS_ALL)) 77 sprintf(pfix, "%04x:%02x ", 78 pci_domain_nr(pe->pbus), pe->pbus->number); 79 #ifdef CONFIG_PCI_IOV 80 else if (pe->flags & PNV_IODA_PE_VF) 81 sprintf(pfix, "%04x:%02x:%2x.%d", 82 pci_domain_nr(pe->parent_dev->bus), 83 (pe->rid & 0xff00) >> 8, 84 PCI_SLOT(pe->rid), PCI_FUNC(pe->rid)); 85 #endif /* CONFIG_PCI_IOV*/ 86 87 printk("%spci %s: [PE# %.2x] %pV", 88 level, pfix, pe->pe_number, &vaf); 89 90 va_end(args); 91 } 92 93 static bool pnv_iommu_bypass_disabled __read_mostly; 94 static bool pci_reset_phbs __read_mostly; 95 96 static int __init iommu_setup(char *str) 97 { 98 if (!str) 99 return -EINVAL; 100 101 while (*str) { 102 if (!strncmp(str, "nobypass", 8)) { 103 pnv_iommu_bypass_disabled = true; 104 pr_info("PowerNV: IOMMU bypass window disabled.\n"); 105 break; 106 } 107 str += strcspn(str, ","); 108 if (*str == ',') 109 str++; 110 } 111 112 return 0; 113 } 114 early_param("iommu", iommu_setup); 115 116 static int __init pci_reset_phbs_setup(char *str) 117 { 118 pci_reset_phbs = true; 119 return 0; 120 } 121 122 early_param("ppc_pci_reset_phbs", pci_reset_phbs_setup); 123 124 static inline bool pnv_pci_is_m64(struct pnv_phb *phb, struct resource *r) 125 { 126 /* 127 * WARNING: We cannot rely on the resource flags. The Linux PCI 128 * allocation code sometimes decides to put a 64-bit prefetchable 129 * BAR in the 32-bit window, so we have to compare the addresses. 130 * 131 * For simplicity we only test resource start. 132 */ 133 return (r->start >= phb->ioda.m64_base && 134 r->start < (phb->ioda.m64_base + phb->ioda.m64_size)); 135 } 136 137 static inline bool pnv_pci_is_m64_flags(unsigned long resource_flags) 138 { 139 unsigned long flags = (IORESOURCE_MEM_64 | IORESOURCE_PREFETCH); 140 141 return (resource_flags & flags) == flags; 142 } 143 144 static struct pnv_ioda_pe *pnv_ioda_init_pe(struct pnv_phb *phb, int pe_no) 145 { 146 s64 rc; 147 148 phb->ioda.pe_array[pe_no].phb = phb; 149 phb->ioda.pe_array[pe_no].pe_number = pe_no; 150 151 /* 152 * Clear the PE frozen state as it might be put into frozen state 153 * in the last PCI remove path. It's not harmful to do so when the 154 * PE is already in unfrozen state. 155 */ 156 rc = opal_pci_eeh_freeze_clear(phb->opal_id, pe_no, 157 OPAL_EEH_ACTION_CLEAR_FREEZE_ALL); 158 if (rc != OPAL_SUCCESS && rc != OPAL_UNSUPPORTED) 159 pr_warn("%s: Error %lld unfreezing PHB#%x-PE#%x\n", 160 __func__, rc, phb->hose->global_number, pe_no); 161 162 return &phb->ioda.pe_array[pe_no]; 163 } 164 165 static void pnv_ioda_reserve_pe(struct pnv_phb *phb, int pe_no) 166 { 167 if (!(pe_no >= 0 && pe_no < phb->ioda.total_pe_num)) { 168 pr_warn("%s: Invalid PE %x on PHB#%x\n", 169 __func__, pe_no, phb->hose->global_number); 170 return; 171 } 172 173 if (test_and_set_bit(pe_no, phb->ioda.pe_alloc)) 174 pr_debug("%s: PE %x was reserved on PHB#%x\n", 175 __func__, pe_no, phb->hose->global_number); 176 177 pnv_ioda_init_pe(phb, pe_no); 178 } 179 180 static struct pnv_ioda_pe *pnv_ioda_alloc_pe(struct pnv_phb *phb) 181 { 182 long pe; 183 184 for (pe = phb->ioda.total_pe_num - 1; pe >= 0; pe--) { 185 if (!test_and_set_bit(pe, phb->ioda.pe_alloc)) 186 return pnv_ioda_init_pe(phb, pe); 187 } 188 189 return NULL; 190 } 191 192 static void pnv_ioda_free_pe(struct pnv_ioda_pe *pe) 193 { 194 struct pnv_phb *phb = pe->phb; 195 unsigned int pe_num = pe->pe_number; 196 197 WARN_ON(pe->pdev); 198 199 memset(pe, 0, sizeof(struct pnv_ioda_pe)); 200 clear_bit(pe_num, phb->ioda.pe_alloc); 201 } 202 203 /* The default M64 BAR is shared by all PEs */ 204 static int pnv_ioda2_init_m64(struct pnv_phb *phb) 205 { 206 const char *desc; 207 struct resource *r; 208 s64 rc; 209 210 /* Configure the default M64 BAR */ 211 rc = opal_pci_set_phb_mem_window(phb->opal_id, 212 OPAL_M64_WINDOW_TYPE, 213 phb->ioda.m64_bar_idx, 214 phb->ioda.m64_base, 215 0, /* unused */ 216 phb->ioda.m64_size); 217 if (rc != OPAL_SUCCESS) { 218 desc = "configuring"; 219 goto fail; 220 } 221 222 /* Enable the default M64 BAR */ 223 rc = opal_pci_phb_mmio_enable(phb->opal_id, 224 OPAL_M64_WINDOW_TYPE, 225 phb->ioda.m64_bar_idx, 226 OPAL_ENABLE_M64_SPLIT); 227 if (rc != OPAL_SUCCESS) { 228 desc = "enabling"; 229 goto fail; 230 } 231 232 /* 233 * Exclude the segments for reserved and root bus PE, which 234 * are first or last two PEs. 235 */ 236 r = &phb->hose->mem_resources[1]; 237 if (phb->ioda.reserved_pe_idx == 0) 238 r->start += (2 * phb->ioda.m64_segsize); 239 else if (phb->ioda.reserved_pe_idx == (phb->ioda.total_pe_num - 1)) 240 r->end -= (2 * phb->ioda.m64_segsize); 241 else 242 pr_warn(" Cannot strip M64 segment for reserved PE#%x\n", 243 phb->ioda.reserved_pe_idx); 244 245 return 0; 246 247 fail: 248 pr_warn(" Failure %lld %s M64 BAR#%d\n", 249 rc, desc, phb->ioda.m64_bar_idx); 250 opal_pci_phb_mmio_enable(phb->opal_id, 251 OPAL_M64_WINDOW_TYPE, 252 phb->ioda.m64_bar_idx, 253 OPAL_DISABLE_M64); 254 return -EIO; 255 } 256 257 static void pnv_ioda_reserve_dev_m64_pe(struct pci_dev *pdev, 258 unsigned long *pe_bitmap) 259 { 260 struct pci_controller *hose = pci_bus_to_host(pdev->bus); 261 struct pnv_phb *phb = hose->private_data; 262 struct resource *r; 263 resource_size_t base, sgsz, start, end; 264 int segno, i; 265 266 base = phb->ioda.m64_base; 267 sgsz = phb->ioda.m64_segsize; 268 for (i = 0; i <= PCI_ROM_RESOURCE; i++) { 269 r = &pdev->resource[i]; 270 if (!r->parent || !pnv_pci_is_m64(phb, r)) 271 continue; 272 273 start = _ALIGN_DOWN(r->start - base, sgsz); 274 end = _ALIGN_UP(r->end - base, sgsz); 275 for (segno = start / sgsz; segno < end / sgsz; segno++) { 276 if (pe_bitmap) 277 set_bit(segno, pe_bitmap); 278 else 279 pnv_ioda_reserve_pe(phb, segno); 280 } 281 } 282 } 283 284 static int pnv_ioda1_init_m64(struct pnv_phb *phb) 285 { 286 struct resource *r; 287 int index; 288 289 /* 290 * There are 16 M64 BARs, each of which has 8 segments. So 291 * there are as many M64 segments as the maximum number of 292 * PEs, which is 128. 293 */ 294 for (index = 0; index < PNV_IODA1_M64_NUM; index++) { 295 unsigned long base, segsz = phb->ioda.m64_segsize; 296 int64_t rc; 297 298 base = phb->ioda.m64_base + 299 index * PNV_IODA1_M64_SEGS * segsz; 300 rc = opal_pci_set_phb_mem_window(phb->opal_id, 301 OPAL_M64_WINDOW_TYPE, index, base, 0, 302 PNV_IODA1_M64_SEGS * segsz); 303 if (rc != OPAL_SUCCESS) { 304 pr_warn(" Error %lld setting M64 PHB#%x-BAR#%d\n", 305 rc, phb->hose->global_number, index); 306 goto fail; 307 } 308 309 rc = opal_pci_phb_mmio_enable(phb->opal_id, 310 OPAL_M64_WINDOW_TYPE, index, 311 OPAL_ENABLE_M64_SPLIT); 312 if (rc != OPAL_SUCCESS) { 313 pr_warn(" Error %lld enabling M64 PHB#%x-BAR#%d\n", 314 rc, phb->hose->global_number, index); 315 goto fail; 316 } 317 } 318 319 /* 320 * Exclude the segments for reserved and root bus PE, which 321 * are first or last two PEs. 322 */ 323 r = &phb->hose->mem_resources[1]; 324 if (phb->ioda.reserved_pe_idx == 0) 325 r->start += (2 * phb->ioda.m64_segsize); 326 else if (phb->ioda.reserved_pe_idx == (phb->ioda.total_pe_num - 1)) 327 r->end -= (2 * phb->ioda.m64_segsize); 328 else 329 WARN(1, "Wrong reserved PE#%x on PHB#%x\n", 330 phb->ioda.reserved_pe_idx, phb->hose->global_number); 331 332 return 0; 333 334 fail: 335 for ( ; index >= 0; index--) 336 opal_pci_phb_mmio_enable(phb->opal_id, 337 OPAL_M64_WINDOW_TYPE, index, OPAL_DISABLE_M64); 338 339 return -EIO; 340 } 341 342 static void pnv_ioda_reserve_m64_pe(struct pci_bus *bus, 343 unsigned long *pe_bitmap, 344 bool all) 345 { 346 struct pci_dev *pdev; 347 348 list_for_each_entry(pdev, &bus->devices, bus_list) { 349 pnv_ioda_reserve_dev_m64_pe(pdev, pe_bitmap); 350 351 if (all && pdev->subordinate) 352 pnv_ioda_reserve_m64_pe(pdev->subordinate, 353 pe_bitmap, all); 354 } 355 } 356 357 static struct pnv_ioda_pe *pnv_ioda_pick_m64_pe(struct pci_bus *bus, bool all) 358 { 359 struct pci_controller *hose = pci_bus_to_host(bus); 360 struct pnv_phb *phb = hose->private_data; 361 struct pnv_ioda_pe *master_pe, *pe; 362 unsigned long size, *pe_alloc; 363 int i; 364 365 /* Root bus shouldn't use M64 */ 366 if (pci_is_root_bus(bus)) 367 return NULL; 368 369 /* Allocate bitmap */ 370 size = _ALIGN_UP(phb->ioda.total_pe_num / 8, sizeof(unsigned long)); 371 pe_alloc = kzalloc(size, GFP_KERNEL); 372 if (!pe_alloc) { 373 pr_warn("%s: Out of memory !\n", 374 __func__); 375 return NULL; 376 } 377 378 /* Figure out reserved PE numbers by the PE */ 379 pnv_ioda_reserve_m64_pe(bus, pe_alloc, all); 380 381 /* 382 * the current bus might not own M64 window and that's all 383 * contributed by its child buses. For the case, we needn't 384 * pick M64 dependent PE#. 385 */ 386 if (bitmap_empty(pe_alloc, phb->ioda.total_pe_num)) { 387 kfree(pe_alloc); 388 return NULL; 389 } 390 391 /* 392 * Figure out the master PE and put all slave PEs to master 393 * PE's list to form compound PE. 394 */ 395 master_pe = NULL; 396 i = -1; 397 while ((i = find_next_bit(pe_alloc, phb->ioda.total_pe_num, i + 1)) < 398 phb->ioda.total_pe_num) { 399 pe = &phb->ioda.pe_array[i]; 400 401 phb->ioda.m64_segmap[pe->pe_number] = pe->pe_number; 402 if (!master_pe) { 403 pe->flags |= PNV_IODA_PE_MASTER; 404 INIT_LIST_HEAD(&pe->slaves); 405 master_pe = pe; 406 } else { 407 pe->flags |= PNV_IODA_PE_SLAVE; 408 pe->master = master_pe; 409 list_add_tail(&pe->list, &master_pe->slaves); 410 } 411 412 /* 413 * P7IOC supports M64DT, which helps mapping M64 segment 414 * to one particular PE#. However, PHB3 has fixed mapping 415 * between M64 segment and PE#. In order to have same logic 416 * for P7IOC and PHB3, we enforce fixed mapping between M64 417 * segment and PE# on P7IOC. 418 */ 419 if (phb->type == PNV_PHB_IODA1) { 420 int64_t rc; 421 422 rc = opal_pci_map_pe_mmio_window(phb->opal_id, 423 pe->pe_number, OPAL_M64_WINDOW_TYPE, 424 pe->pe_number / PNV_IODA1_M64_SEGS, 425 pe->pe_number % PNV_IODA1_M64_SEGS); 426 if (rc != OPAL_SUCCESS) 427 pr_warn("%s: Error %lld mapping M64 for PHB#%x-PE#%x\n", 428 __func__, rc, phb->hose->global_number, 429 pe->pe_number); 430 } 431 } 432 433 kfree(pe_alloc); 434 return master_pe; 435 } 436 437 static void __init pnv_ioda_parse_m64_window(struct pnv_phb *phb) 438 { 439 struct pci_controller *hose = phb->hose; 440 struct device_node *dn = hose->dn; 441 struct resource *res; 442 u32 m64_range[2], i; 443 const __be32 *r; 444 u64 pci_addr; 445 446 if (phb->type != PNV_PHB_IODA1 && phb->type != PNV_PHB_IODA2) { 447 pr_info(" Not support M64 window\n"); 448 return; 449 } 450 451 if (!firmware_has_feature(FW_FEATURE_OPAL)) { 452 pr_info(" Firmware too old to support M64 window\n"); 453 return; 454 } 455 456 r = of_get_property(dn, "ibm,opal-m64-window", NULL); 457 if (!r) { 458 pr_info(" No <ibm,opal-m64-window> on %pOF\n", 459 dn); 460 return; 461 } 462 463 /* 464 * Find the available M64 BAR range and pickup the last one for 465 * covering the whole 64-bits space. We support only one range. 466 */ 467 if (of_property_read_u32_array(dn, "ibm,opal-available-m64-ranges", 468 m64_range, 2)) { 469 /* In absence of the property, assume 0..15 */ 470 m64_range[0] = 0; 471 m64_range[1] = 16; 472 } 473 /* We only support 64 bits in our allocator */ 474 if (m64_range[1] > 63) { 475 pr_warn("%s: Limiting M64 range to 63 (from %d) on PHB#%x\n", 476 __func__, m64_range[1], phb->hose->global_number); 477 m64_range[1] = 63; 478 } 479 /* Empty range, no m64 */ 480 if (m64_range[1] <= m64_range[0]) { 481 pr_warn("%s: M64 empty, disabling M64 usage on PHB#%x\n", 482 __func__, phb->hose->global_number); 483 return; 484 } 485 486 /* Configure M64 informations */ 487 res = &hose->mem_resources[1]; 488 res->name = dn->full_name; 489 res->start = of_translate_address(dn, r + 2); 490 res->end = res->start + of_read_number(r + 4, 2) - 1; 491 res->flags = (IORESOURCE_MEM | IORESOURCE_MEM_64 | IORESOURCE_PREFETCH); 492 pci_addr = of_read_number(r, 2); 493 hose->mem_offset[1] = res->start - pci_addr; 494 495 phb->ioda.m64_size = resource_size(res); 496 phb->ioda.m64_segsize = phb->ioda.m64_size / phb->ioda.total_pe_num; 497 phb->ioda.m64_base = pci_addr; 498 499 /* This lines up nicely with the display from processing OF ranges */ 500 pr_info(" MEM 0x%016llx..0x%016llx -> 0x%016llx (M64 #%d..%d)\n", 501 res->start, res->end, pci_addr, m64_range[0], 502 m64_range[0] + m64_range[1] - 1); 503 504 /* Mark all M64 used up by default */ 505 phb->ioda.m64_bar_alloc = (unsigned long)-1; 506 507 /* Use last M64 BAR to cover M64 window */ 508 m64_range[1]--; 509 phb->ioda.m64_bar_idx = m64_range[0] + m64_range[1]; 510 511 pr_info(" Using M64 #%d as default window\n", phb->ioda.m64_bar_idx); 512 513 /* Mark remaining ones free */ 514 for (i = m64_range[0]; i < m64_range[1]; i++) 515 clear_bit(i, &phb->ioda.m64_bar_alloc); 516 517 /* 518 * Setup init functions for M64 based on IODA version, IODA3 uses 519 * the IODA2 code. 520 */ 521 if (phb->type == PNV_PHB_IODA1) 522 phb->init_m64 = pnv_ioda1_init_m64; 523 else 524 phb->init_m64 = pnv_ioda2_init_m64; 525 phb->reserve_m64_pe = pnv_ioda_reserve_m64_pe; 526 phb->pick_m64_pe = pnv_ioda_pick_m64_pe; 527 } 528 529 static void pnv_ioda_freeze_pe(struct pnv_phb *phb, int pe_no) 530 { 531 struct pnv_ioda_pe *pe = &phb->ioda.pe_array[pe_no]; 532 struct pnv_ioda_pe *slave; 533 s64 rc; 534 535 /* Fetch master PE */ 536 if (pe->flags & PNV_IODA_PE_SLAVE) { 537 pe = pe->master; 538 if (WARN_ON(!pe || !(pe->flags & PNV_IODA_PE_MASTER))) 539 return; 540 541 pe_no = pe->pe_number; 542 } 543 544 /* Freeze master PE */ 545 rc = opal_pci_eeh_freeze_set(phb->opal_id, 546 pe_no, 547 OPAL_EEH_ACTION_SET_FREEZE_ALL); 548 if (rc != OPAL_SUCCESS) { 549 pr_warn("%s: Failure %lld freezing PHB#%x-PE#%x\n", 550 __func__, rc, phb->hose->global_number, pe_no); 551 return; 552 } 553 554 /* Freeze slave PEs */ 555 if (!(pe->flags & PNV_IODA_PE_MASTER)) 556 return; 557 558 list_for_each_entry(slave, &pe->slaves, list) { 559 rc = opal_pci_eeh_freeze_set(phb->opal_id, 560 slave->pe_number, 561 OPAL_EEH_ACTION_SET_FREEZE_ALL); 562 if (rc != OPAL_SUCCESS) 563 pr_warn("%s: Failure %lld freezing PHB#%x-PE#%x\n", 564 __func__, rc, phb->hose->global_number, 565 slave->pe_number); 566 } 567 } 568 569 static int pnv_ioda_unfreeze_pe(struct pnv_phb *phb, int pe_no, int opt) 570 { 571 struct pnv_ioda_pe *pe, *slave; 572 s64 rc; 573 574 /* Find master PE */ 575 pe = &phb->ioda.pe_array[pe_no]; 576 if (pe->flags & PNV_IODA_PE_SLAVE) { 577 pe = pe->master; 578 WARN_ON(!pe || !(pe->flags & PNV_IODA_PE_MASTER)); 579 pe_no = pe->pe_number; 580 } 581 582 /* Clear frozen state for master PE */ 583 rc = opal_pci_eeh_freeze_clear(phb->opal_id, pe_no, opt); 584 if (rc != OPAL_SUCCESS) { 585 pr_warn("%s: Failure %lld clear %d on PHB#%x-PE#%x\n", 586 __func__, rc, opt, phb->hose->global_number, pe_no); 587 return -EIO; 588 } 589 590 if (!(pe->flags & PNV_IODA_PE_MASTER)) 591 return 0; 592 593 /* Clear frozen state for slave PEs */ 594 list_for_each_entry(slave, &pe->slaves, list) { 595 rc = opal_pci_eeh_freeze_clear(phb->opal_id, 596 slave->pe_number, 597 opt); 598 if (rc != OPAL_SUCCESS) { 599 pr_warn("%s: Failure %lld clear %d on PHB#%x-PE#%x\n", 600 __func__, rc, opt, phb->hose->global_number, 601 slave->pe_number); 602 return -EIO; 603 } 604 } 605 606 return 0; 607 } 608 609 static int pnv_ioda_get_pe_state(struct pnv_phb *phb, int pe_no) 610 { 611 struct pnv_ioda_pe *slave, *pe; 612 u8 fstate, state; 613 __be16 pcierr; 614 s64 rc; 615 616 /* Sanity check on PE number */ 617 if (pe_no < 0 || pe_no >= phb->ioda.total_pe_num) 618 return OPAL_EEH_STOPPED_PERM_UNAVAIL; 619 620 /* 621 * Fetch the master PE and the PE instance might be 622 * not initialized yet. 623 */ 624 pe = &phb->ioda.pe_array[pe_no]; 625 if (pe->flags & PNV_IODA_PE_SLAVE) { 626 pe = pe->master; 627 WARN_ON(!pe || !(pe->flags & PNV_IODA_PE_MASTER)); 628 pe_no = pe->pe_number; 629 } 630 631 /* Check the master PE */ 632 rc = opal_pci_eeh_freeze_status(phb->opal_id, pe_no, 633 &state, &pcierr, NULL); 634 if (rc != OPAL_SUCCESS) { 635 pr_warn("%s: Failure %lld getting " 636 "PHB#%x-PE#%x state\n", 637 __func__, rc, 638 phb->hose->global_number, pe_no); 639 return OPAL_EEH_STOPPED_TEMP_UNAVAIL; 640 } 641 642 /* Check the slave PE */ 643 if (!(pe->flags & PNV_IODA_PE_MASTER)) 644 return state; 645 646 list_for_each_entry(slave, &pe->slaves, list) { 647 rc = opal_pci_eeh_freeze_status(phb->opal_id, 648 slave->pe_number, 649 &fstate, 650 &pcierr, 651 NULL); 652 if (rc != OPAL_SUCCESS) { 653 pr_warn("%s: Failure %lld getting " 654 "PHB#%x-PE#%x state\n", 655 __func__, rc, 656 phb->hose->global_number, slave->pe_number); 657 return OPAL_EEH_STOPPED_TEMP_UNAVAIL; 658 } 659 660 /* 661 * Override the result based on the ascending 662 * priority. 663 */ 664 if (fstate > state) 665 state = fstate; 666 } 667 668 return state; 669 } 670 671 /* Currently those 2 are only used when MSIs are enabled, this will change 672 * but in the meantime, we need to protect them to avoid warnings 673 */ 674 #ifdef CONFIG_PCI_MSI 675 struct pnv_ioda_pe *pnv_ioda_get_pe(struct pci_dev *dev) 676 { 677 struct pci_controller *hose = pci_bus_to_host(dev->bus); 678 struct pnv_phb *phb = hose->private_data; 679 struct pci_dn *pdn = pci_get_pdn(dev); 680 681 if (!pdn) 682 return NULL; 683 if (pdn->pe_number == IODA_INVALID_PE) 684 return NULL; 685 return &phb->ioda.pe_array[pdn->pe_number]; 686 } 687 #endif /* CONFIG_PCI_MSI */ 688 689 static int pnv_ioda_set_one_peltv(struct pnv_phb *phb, 690 struct pnv_ioda_pe *parent, 691 struct pnv_ioda_pe *child, 692 bool is_add) 693 { 694 const char *desc = is_add ? "adding" : "removing"; 695 uint8_t op = is_add ? OPAL_ADD_PE_TO_DOMAIN : 696 OPAL_REMOVE_PE_FROM_DOMAIN; 697 struct pnv_ioda_pe *slave; 698 long rc; 699 700 /* Parent PE affects child PE */ 701 rc = opal_pci_set_peltv(phb->opal_id, parent->pe_number, 702 child->pe_number, op); 703 if (rc != OPAL_SUCCESS) { 704 pe_warn(child, "OPAL error %ld %s to parent PELTV\n", 705 rc, desc); 706 return -ENXIO; 707 } 708 709 if (!(child->flags & PNV_IODA_PE_MASTER)) 710 return 0; 711 712 /* Compound case: parent PE affects slave PEs */ 713 list_for_each_entry(slave, &child->slaves, list) { 714 rc = opal_pci_set_peltv(phb->opal_id, parent->pe_number, 715 slave->pe_number, op); 716 if (rc != OPAL_SUCCESS) { 717 pe_warn(slave, "OPAL error %ld %s to parent PELTV\n", 718 rc, desc); 719 return -ENXIO; 720 } 721 } 722 723 return 0; 724 } 725 726 static int pnv_ioda_set_peltv(struct pnv_phb *phb, 727 struct pnv_ioda_pe *pe, 728 bool is_add) 729 { 730 struct pnv_ioda_pe *slave; 731 struct pci_dev *pdev = NULL; 732 int ret; 733 734 /* 735 * Clear PE frozen state. If it's master PE, we need 736 * clear slave PE frozen state as well. 737 */ 738 if (is_add) { 739 opal_pci_eeh_freeze_clear(phb->opal_id, pe->pe_number, 740 OPAL_EEH_ACTION_CLEAR_FREEZE_ALL); 741 if (pe->flags & PNV_IODA_PE_MASTER) { 742 list_for_each_entry(slave, &pe->slaves, list) 743 opal_pci_eeh_freeze_clear(phb->opal_id, 744 slave->pe_number, 745 OPAL_EEH_ACTION_CLEAR_FREEZE_ALL); 746 } 747 } 748 749 /* 750 * Associate PE in PELT. We need add the PE into the 751 * corresponding PELT-V as well. Otherwise, the error 752 * originated from the PE might contribute to other 753 * PEs. 754 */ 755 ret = pnv_ioda_set_one_peltv(phb, pe, pe, is_add); 756 if (ret) 757 return ret; 758 759 /* For compound PEs, any one affects all of them */ 760 if (pe->flags & PNV_IODA_PE_MASTER) { 761 list_for_each_entry(slave, &pe->slaves, list) { 762 ret = pnv_ioda_set_one_peltv(phb, slave, pe, is_add); 763 if (ret) 764 return ret; 765 } 766 } 767 768 if (pe->flags & (PNV_IODA_PE_BUS_ALL | PNV_IODA_PE_BUS)) 769 pdev = pe->pbus->self; 770 else if (pe->flags & PNV_IODA_PE_DEV) 771 pdev = pe->pdev->bus->self; 772 #ifdef CONFIG_PCI_IOV 773 else if (pe->flags & PNV_IODA_PE_VF) 774 pdev = pe->parent_dev; 775 #endif /* CONFIG_PCI_IOV */ 776 while (pdev) { 777 struct pci_dn *pdn = pci_get_pdn(pdev); 778 struct pnv_ioda_pe *parent; 779 780 if (pdn && pdn->pe_number != IODA_INVALID_PE) { 781 parent = &phb->ioda.pe_array[pdn->pe_number]; 782 ret = pnv_ioda_set_one_peltv(phb, parent, pe, is_add); 783 if (ret) 784 return ret; 785 } 786 787 pdev = pdev->bus->self; 788 } 789 790 return 0; 791 } 792 793 static int pnv_ioda_deconfigure_pe(struct pnv_phb *phb, struct pnv_ioda_pe *pe) 794 { 795 struct pci_dev *parent; 796 uint8_t bcomp, dcomp, fcomp; 797 int64_t rc; 798 long rid_end, rid; 799 800 /* Currently, we just deconfigure VF PE. Bus PE will always there.*/ 801 if (pe->pbus) { 802 int count; 803 804 dcomp = OPAL_IGNORE_RID_DEVICE_NUMBER; 805 fcomp = OPAL_IGNORE_RID_FUNCTION_NUMBER; 806 parent = pe->pbus->self; 807 if (pe->flags & PNV_IODA_PE_BUS_ALL) 808 count = pe->pbus->busn_res.end - pe->pbus->busn_res.start + 1; 809 else 810 count = 1; 811 812 switch(count) { 813 case 1: bcomp = OpalPciBusAll; break; 814 case 2: bcomp = OpalPciBus7Bits; break; 815 case 4: bcomp = OpalPciBus6Bits; break; 816 case 8: bcomp = OpalPciBus5Bits; break; 817 case 16: bcomp = OpalPciBus4Bits; break; 818 case 32: bcomp = OpalPciBus3Bits; break; 819 default: 820 dev_err(&pe->pbus->dev, "Number of subordinate buses %d unsupported\n", 821 count); 822 /* Do an exact match only */ 823 bcomp = OpalPciBusAll; 824 } 825 rid_end = pe->rid + (count << 8); 826 } else { 827 #ifdef CONFIG_PCI_IOV 828 if (pe->flags & PNV_IODA_PE_VF) 829 parent = pe->parent_dev; 830 else 831 #endif 832 parent = pe->pdev->bus->self; 833 bcomp = OpalPciBusAll; 834 dcomp = OPAL_COMPARE_RID_DEVICE_NUMBER; 835 fcomp = OPAL_COMPARE_RID_FUNCTION_NUMBER; 836 rid_end = pe->rid + 1; 837 } 838 839 /* Clear the reverse map */ 840 for (rid = pe->rid; rid < rid_end; rid++) 841 phb->ioda.pe_rmap[rid] = IODA_INVALID_PE; 842 843 /* Release from all parents PELT-V */ 844 while (parent) { 845 struct pci_dn *pdn = pci_get_pdn(parent); 846 if (pdn && pdn->pe_number != IODA_INVALID_PE) { 847 rc = opal_pci_set_peltv(phb->opal_id, pdn->pe_number, 848 pe->pe_number, OPAL_REMOVE_PE_FROM_DOMAIN); 849 /* XXX What to do in case of error ? */ 850 } 851 parent = parent->bus->self; 852 } 853 854 opal_pci_eeh_freeze_clear(phb->opal_id, pe->pe_number, 855 OPAL_EEH_ACTION_CLEAR_FREEZE_ALL); 856 857 /* Disassociate PE in PELT */ 858 rc = opal_pci_set_peltv(phb->opal_id, pe->pe_number, 859 pe->pe_number, OPAL_REMOVE_PE_FROM_DOMAIN); 860 if (rc) 861 pe_warn(pe, "OPAL error %ld remove self from PELTV\n", rc); 862 rc = opal_pci_set_pe(phb->opal_id, pe->pe_number, pe->rid, 863 bcomp, dcomp, fcomp, OPAL_UNMAP_PE); 864 if (rc) 865 pe_err(pe, "OPAL error %ld trying to setup PELT table\n", rc); 866 867 pe->pbus = NULL; 868 pe->pdev = NULL; 869 #ifdef CONFIG_PCI_IOV 870 pe->parent_dev = NULL; 871 #endif 872 873 return 0; 874 } 875 876 static int pnv_ioda_configure_pe(struct pnv_phb *phb, struct pnv_ioda_pe *pe) 877 { 878 struct pci_dev *parent; 879 uint8_t bcomp, dcomp, fcomp; 880 long rc, rid_end, rid; 881 882 /* Bus validation ? */ 883 if (pe->pbus) { 884 int count; 885 886 dcomp = OPAL_IGNORE_RID_DEVICE_NUMBER; 887 fcomp = OPAL_IGNORE_RID_FUNCTION_NUMBER; 888 parent = pe->pbus->self; 889 if (pe->flags & PNV_IODA_PE_BUS_ALL) 890 count = pe->pbus->busn_res.end - pe->pbus->busn_res.start + 1; 891 else 892 count = 1; 893 894 switch(count) { 895 case 1: bcomp = OpalPciBusAll; break; 896 case 2: bcomp = OpalPciBus7Bits; break; 897 case 4: bcomp = OpalPciBus6Bits; break; 898 case 8: bcomp = OpalPciBus5Bits; break; 899 case 16: bcomp = OpalPciBus4Bits; break; 900 case 32: bcomp = OpalPciBus3Bits; break; 901 default: 902 dev_err(&pe->pbus->dev, "Number of subordinate buses %d unsupported\n", 903 count); 904 /* Do an exact match only */ 905 bcomp = OpalPciBusAll; 906 } 907 rid_end = pe->rid + (count << 8); 908 } else { 909 #ifdef CONFIG_PCI_IOV 910 if (pe->flags & PNV_IODA_PE_VF) 911 parent = pe->parent_dev; 912 else 913 #endif /* CONFIG_PCI_IOV */ 914 parent = pe->pdev->bus->self; 915 bcomp = OpalPciBusAll; 916 dcomp = OPAL_COMPARE_RID_DEVICE_NUMBER; 917 fcomp = OPAL_COMPARE_RID_FUNCTION_NUMBER; 918 rid_end = pe->rid + 1; 919 } 920 921 /* 922 * Associate PE in PELT. We need add the PE into the 923 * corresponding PELT-V as well. Otherwise, the error 924 * originated from the PE might contribute to other 925 * PEs. 926 */ 927 rc = opal_pci_set_pe(phb->opal_id, pe->pe_number, pe->rid, 928 bcomp, dcomp, fcomp, OPAL_MAP_PE); 929 if (rc) { 930 pe_err(pe, "OPAL error %ld trying to setup PELT table\n", rc); 931 return -ENXIO; 932 } 933 934 /* 935 * Configure PELTV. NPUs don't have a PELTV table so skip 936 * configuration on them. 937 */ 938 if (phb->type != PNV_PHB_NPU_NVLINK && phb->type != PNV_PHB_NPU_OCAPI) 939 pnv_ioda_set_peltv(phb, pe, true); 940 941 /* Setup reverse map */ 942 for (rid = pe->rid; rid < rid_end; rid++) 943 phb->ioda.pe_rmap[rid] = pe->pe_number; 944 945 /* Setup one MVTs on IODA1 */ 946 if (phb->type != PNV_PHB_IODA1) { 947 pe->mve_number = 0; 948 goto out; 949 } 950 951 pe->mve_number = pe->pe_number; 952 rc = opal_pci_set_mve(phb->opal_id, pe->mve_number, pe->pe_number); 953 if (rc != OPAL_SUCCESS) { 954 pe_err(pe, "OPAL error %ld setting up MVE %x\n", 955 rc, pe->mve_number); 956 pe->mve_number = -1; 957 } else { 958 rc = opal_pci_set_mve_enable(phb->opal_id, 959 pe->mve_number, OPAL_ENABLE_MVE); 960 if (rc) { 961 pe_err(pe, "OPAL error %ld enabling MVE %x\n", 962 rc, pe->mve_number); 963 pe->mve_number = -1; 964 } 965 } 966 967 out: 968 return 0; 969 } 970 971 #ifdef CONFIG_PCI_IOV 972 static int pnv_pci_vf_resource_shift(struct pci_dev *dev, int offset) 973 { 974 struct pci_dn *pdn = pci_get_pdn(dev); 975 int i; 976 struct resource *res, res2; 977 resource_size_t size; 978 u16 num_vfs; 979 980 if (!dev->is_physfn) 981 return -EINVAL; 982 983 /* 984 * "offset" is in VFs. The M64 windows are sized so that when they 985 * are segmented, each segment is the same size as the IOV BAR. 986 * Each segment is in a separate PE, and the high order bits of the 987 * address are the PE number. Therefore, each VF's BAR is in a 988 * separate PE, and changing the IOV BAR start address changes the 989 * range of PEs the VFs are in. 990 */ 991 num_vfs = pdn->num_vfs; 992 for (i = 0; i < PCI_SRIOV_NUM_BARS; i++) { 993 res = &dev->resource[i + PCI_IOV_RESOURCES]; 994 if (!res->flags || !res->parent) 995 continue; 996 997 /* 998 * The actual IOV BAR range is determined by the start address 999 * and the actual size for num_vfs VFs BAR. This check is to 1000 * make sure that after shifting, the range will not overlap 1001 * with another device. 1002 */ 1003 size = pci_iov_resource_size(dev, i + PCI_IOV_RESOURCES); 1004 res2.flags = res->flags; 1005 res2.start = res->start + (size * offset); 1006 res2.end = res2.start + (size * num_vfs) - 1; 1007 1008 if (res2.end > res->end) { 1009 dev_err(&dev->dev, "VF BAR%d: %pR would extend past %pR (trying to enable %d VFs shifted by %d)\n", 1010 i, &res2, res, num_vfs, offset); 1011 return -EBUSY; 1012 } 1013 } 1014 1015 /* 1016 * Since M64 BAR shares segments among all possible 256 PEs, 1017 * we have to shift the beginning of PF IOV BAR to make it start from 1018 * the segment which belongs to the PE number assigned to the first VF. 1019 * This creates a "hole" in the /proc/iomem which could be used for 1020 * allocating other resources so we reserve this area below and 1021 * release when IOV is released. 1022 */ 1023 for (i = 0; i < PCI_SRIOV_NUM_BARS; i++) { 1024 res = &dev->resource[i + PCI_IOV_RESOURCES]; 1025 if (!res->flags || !res->parent) 1026 continue; 1027 1028 size = pci_iov_resource_size(dev, i + PCI_IOV_RESOURCES); 1029 res2 = *res; 1030 res->start += size * offset; 1031 1032 dev_info(&dev->dev, "VF BAR%d: %pR shifted to %pR (%sabling %d VFs shifted by %d)\n", 1033 i, &res2, res, (offset > 0) ? "En" : "Dis", 1034 num_vfs, offset); 1035 1036 if (offset < 0) { 1037 devm_release_resource(&dev->dev, &pdn->holes[i]); 1038 memset(&pdn->holes[i], 0, sizeof(pdn->holes[i])); 1039 } 1040 1041 pci_update_resource(dev, i + PCI_IOV_RESOURCES); 1042 1043 if (offset > 0) { 1044 pdn->holes[i].start = res2.start; 1045 pdn->holes[i].end = res2.start + size * offset - 1; 1046 pdn->holes[i].flags = IORESOURCE_BUS; 1047 pdn->holes[i].name = "pnv_iov_reserved"; 1048 devm_request_resource(&dev->dev, res->parent, 1049 &pdn->holes[i]); 1050 } 1051 } 1052 return 0; 1053 } 1054 #endif /* CONFIG_PCI_IOV */ 1055 1056 static struct pnv_ioda_pe *pnv_ioda_setup_dev_PE(struct pci_dev *dev) 1057 { 1058 struct pci_controller *hose = pci_bus_to_host(dev->bus); 1059 struct pnv_phb *phb = hose->private_data; 1060 struct pci_dn *pdn = pci_get_pdn(dev); 1061 struct pnv_ioda_pe *pe; 1062 1063 if (!pdn) { 1064 pr_err("%s: Device tree node not associated properly\n", 1065 pci_name(dev)); 1066 return NULL; 1067 } 1068 if (pdn->pe_number != IODA_INVALID_PE) 1069 return NULL; 1070 1071 pe = pnv_ioda_alloc_pe(phb); 1072 if (!pe) { 1073 pr_warn("%s: Not enough PE# available, disabling device\n", 1074 pci_name(dev)); 1075 return NULL; 1076 } 1077 1078 /* NOTE: We get only one ref to the pci_dev for the pdn, not for the 1079 * pointer in the PE data structure, both should be destroyed at the 1080 * same time. However, this needs to be looked at more closely again 1081 * once we actually start removing things (Hotplug, SR-IOV, ...) 1082 * 1083 * At some point we want to remove the PDN completely anyways 1084 */ 1085 pci_dev_get(dev); 1086 pdn->pe_number = pe->pe_number; 1087 pe->flags = PNV_IODA_PE_DEV; 1088 pe->pdev = dev; 1089 pe->pbus = NULL; 1090 pe->mve_number = -1; 1091 pe->rid = dev->bus->number << 8 | pdn->devfn; 1092 1093 pe_info(pe, "Associated device to PE\n"); 1094 1095 if (pnv_ioda_configure_pe(phb, pe)) { 1096 /* XXX What do we do here ? */ 1097 pnv_ioda_free_pe(pe); 1098 pdn->pe_number = IODA_INVALID_PE; 1099 pe->pdev = NULL; 1100 pci_dev_put(dev); 1101 return NULL; 1102 } 1103 1104 /* Put PE to the list */ 1105 list_add_tail(&pe->list, &phb->ioda.pe_list); 1106 1107 return pe; 1108 } 1109 1110 static void pnv_ioda_setup_same_PE(struct pci_bus *bus, struct pnv_ioda_pe *pe) 1111 { 1112 struct pci_dev *dev; 1113 1114 list_for_each_entry(dev, &bus->devices, bus_list) { 1115 struct pci_dn *pdn = pci_get_pdn(dev); 1116 1117 if (pdn == NULL) { 1118 pr_warn("%s: No device node associated with device !\n", 1119 pci_name(dev)); 1120 continue; 1121 } 1122 1123 /* 1124 * In partial hotplug case, the PCI device might be still 1125 * associated with the PE and needn't attach it to the PE 1126 * again. 1127 */ 1128 if (pdn->pe_number != IODA_INVALID_PE) 1129 continue; 1130 1131 pe->device_count++; 1132 pdn->pe_number = pe->pe_number; 1133 if ((pe->flags & PNV_IODA_PE_BUS_ALL) && dev->subordinate) 1134 pnv_ioda_setup_same_PE(dev->subordinate, pe); 1135 } 1136 } 1137 1138 /* 1139 * There're 2 types of PCI bus sensitive PEs: One that is compromised of 1140 * single PCI bus. Another one that contains the primary PCI bus and its 1141 * subordinate PCI devices and buses. The second type of PE is normally 1142 * orgiriated by PCIe-to-PCI bridge or PLX switch downstream ports. 1143 */ 1144 static struct pnv_ioda_pe *pnv_ioda_setup_bus_PE(struct pci_bus *bus, bool all) 1145 { 1146 struct pci_controller *hose = pci_bus_to_host(bus); 1147 struct pnv_phb *phb = hose->private_data; 1148 struct pnv_ioda_pe *pe = NULL; 1149 unsigned int pe_num; 1150 1151 /* 1152 * In partial hotplug case, the PE instance might be still alive. 1153 * We should reuse it instead of allocating a new one. 1154 */ 1155 pe_num = phb->ioda.pe_rmap[bus->number << 8]; 1156 if (pe_num != IODA_INVALID_PE) { 1157 pe = &phb->ioda.pe_array[pe_num]; 1158 pnv_ioda_setup_same_PE(bus, pe); 1159 return NULL; 1160 } 1161 1162 /* PE number for root bus should have been reserved */ 1163 if (pci_is_root_bus(bus) && 1164 phb->ioda.root_pe_idx != IODA_INVALID_PE) 1165 pe = &phb->ioda.pe_array[phb->ioda.root_pe_idx]; 1166 1167 /* Check if PE is determined by M64 */ 1168 if (!pe && phb->pick_m64_pe) 1169 pe = phb->pick_m64_pe(bus, all); 1170 1171 /* The PE number isn't pinned by M64 */ 1172 if (!pe) 1173 pe = pnv_ioda_alloc_pe(phb); 1174 1175 if (!pe) { 1176 pr_warn("%s: Not enough PE# available for PCI bus %04x:%02x\n", 1177 __func__, pci_domain_nr(bus), bus->number); 1178 return NULL; 1179 } 1180 1181 pe->flags |= (all ? PNV_IODA_PE_BUS_ALL : PNV_IODA_PE_BUS); 1182 pe->pbus = bus; 1183 pe->pdev = NULL; 1184 pe->mve_number = -1; 1185 pe->rid = bus->busn_res.start << 8; 1186 1187 if (all) 1188 pe_info(pe, "Secondary bus %d..%d associated with PE#%x\n", 1189 bus->busn_res.start, bus->busn_res.end, pe->pe_number); 1190 else 1191 pe_info(pe, "Secondary bus %d associated with PE#%x\n", 1192 bus->busn_res.start, pe->pe_number); 1193 1194 if (pnv_ioda_configure_pe(phb, pe)) { 1195 /* XXX What do we do here ? */ 1196 pnv_ioda_free_pe(pe); 1197 pe->pbus = NULL; 1198 return NULL; 1199 } 1200 1201 /* Associate it with all child devices */ 1202 pnv_ioda_setup_same_PE(bus, pe); 1203 1204 /* Put PE to the list */ 1205 list_add_tail(&pe->list, &phb->ioda.pe_list); 1206 1207 return pe; 1208 } 1209 1210 static struct pnv_ioda_pe *pnv_ioda_setup_npu_PE(struct pci_dev *npu_pdev) 1211 { 1212 int pe_num, found_pe = false, rc; 1213 long rid; 1214 struct pnv_ioda_pe *pe; 1215 struct pci_dev *gpu_pdev; 1216 struct pci_dn *npu_pdn; 1217 struct pci_controller *hose = pci_bus_to_host(npu_pdev->bus); 1218 struct pnv_phb *phb = hose->private_data; 1219 1220 /* 1221 * Due to a hardware errata PE#0 on the NPU is reserved for 1222 * error handling. This means we only have three PEs remaining 1223 * which need to be assigned to four links, implying some 1224 * links must share PEs. 1225 * 1226 * To achieve this we assign PEs such that NPUs linking the 1227 * same GPU get assigned the same PE. 1228 */ 1229 gpu_pdev = pnv_pci_get_gpu_dev(npu_pdev); 1230 for (pe_num = 0; pe_num < phb->ioda.total_pe_num; pe_num++) { 1231 pe = &phb->ioda.pe_array[pe_num]; 1232 if (!pe->pdev) 1233 continue; 1234 1235 if (pnv_pci_get_gpu_dev(pe->pdev) == gpu_pdev) { 1236 /* 1237 * This device has the same peer GPU so should 1238 * be assigned the same PE as the existing 1239 * peer NPU. 1240 */ 1241 dev_info(&npu_pdev->dev, 1242 "Associating to existing PE %x\n", pe_num); 1243 pci_dev_get(npu_pdev); 1244 npu_pdn = pci_get_pdn(npu_pdev); 1245 rid = npu_pdev->bus->number << 8 | npu_pdn->devfn; 1246 npu_pdn->pe_number = pe_num; 1247 phb->ioda.pe_rmap[rid] = pe->pe_number; 1248 1249 /* Map the PE to this link */ 1250 rc = opal_pci_set_pe(phb->opal_id, pe_num, rid, 1251 OpalPciBusAll, 1252 OPAL_COMPARE_RID_DEVICE_NUMBER, 1253 OPAL_COMPARE_RID_FUNCTION_NUMBER, 1254 OPAL_MAP_PE); 1255 WARN_ON(rc != OPAL_SUCCESS); 1256 found_pe = true; 1257 break; 1258 } 1259 } 1260 1261 if (!found_pe) 1262 /* 1263 * Could not find an existing PE so allocate a new 1264 * one. 1265 */ 1266 return pnv_ioda_setup_dev_PE(npu_pdev); 1267 else 1268 return pe; 1269 } 1270 1271 static void pnv_ioda_setup_npu_PEs(struct pci_bus *bus) 1272 { 1273 struct pci_dev *pdev; 1274 1275 list_for_each_entry(pdev, &bus->devices, bus_list) 1276 pnv_ioda_setup_npu_PE(pdev); 1277 } 1278 1279 static void pnv_pci_ioda_setup_PEs(void) 1280 { 1281 struct pci_controller *hose, *tmp; 1282 struct pnv_phb *phb; 1283 struct pci_bus *bus; 1284 struct pci_dev *pdev; 1285 1286 list_for_each_entry_safe(hose, tmp, &hose_list, list_node) { 1287 phb = hose->private_data; 1288 if (phb->type == PNV_PHB_NPU_NVLINK) { 1289 /* PE#0 is needed for error reporting */ 1290 pnv_ioda_reserve_pe(phb, 0); 1291 pnv_ioda_setup_npu_PEs(hose->bus); 1292 if (phb->model == PNV_PHB_MODEL_NPU2) 1293 pnv_npu2_init(phb); 1294 } 1295 if (phb->type == PNV_PHB_NPU_OCAPI) { 1296 bus = hose->bus; 1297 list_for_each_entry(pdev, &bus->devices, bus_list) 1298 pnv_ioda_setup_dev_PE(pdev); 1299 } 1300 } 1301 } 1302 1303 #ifdef CONFIG_PCI_IOV 1304 static int pnv_pci_vf_release_m64(struct pci_dev *pdev, u16 num_vfs) 1305 { 1306 struct pci_bus *bus; 1307 struct pci_controller *hose; 1308 struct pnv_phb *phb; 1309 struct pci_dn *pdn; 1310 int i, j; 1311 int m64_bars; 1312 1313 bus = pdev->bus; 1314 hose = pci_bus_to_host(bus); 1315 phb = hose->private_data; 1316 pdn = pci_get_pdn(pdev); 1317 1318 if (pdn->m64_single_mode) 1319 m64_bars = num_vfs; 1320 else 1321 m64_bars = 1; 1322 1323 for (i = 0; i < PCI_SRIOV_NUM_BARS; i++) 1324 for (j = 0; j < m64_bars; j++) { 1325 if (pdn->m64_map[j][i] == IODA_INVALID_M64) 1326 continue; 1327 opal_pci_phb_mmio_enable(phb->opal_id, 1328 OPAL_M64_WINDOW_TYPE, pdn->m64_map[j][i], 0); 1329 clear_bit(pdn->m64_map[j][i], &phb->ioda.m64_bar_alloc); 1330 pdn->m64_map[j][i] = IODA_INVALID_M64; 1331 } 1332 1333 kfree(pdn->m64_map); 1334 return 0; 1335 } 1336 1337 static int pnv_pci_vf_assign_m64(struct pci_dev *pdev, u16 num_vfs) 1338 { 1339 struct pci_bus *bus; 1340 struct pci_controller *hose; 1341 struct pnv_phb *phb; 1342 struct pci_dn *pdn; 1343 unsigned int win; 1344 struct resource *res; 1345 int i, j; 1346 int64_t rc; 1347 int total_vfs; 1348 resource_size_t size, start; 1349 int pe_num; 1350 int m64_bars; 1351 1352 bus = pdev->bus; 1353 hose = pci_bus_to_host(bus); 1354 phb = hose->private_data; 1355 pdn = pci_get_pdn(pdev); 1356 total_vfs = pci_sriov_get_totalvfs(pdev); 1357 1358 if (pdn->m64_single_mode) 1359 m64_bars = num_vfs; 1360 else 1361 m64_bars = 1; 1362 1363 pdn->m64_map = kmalloc_array(m64_bars, 1364 sizeof(*pdn->m64_map), 1365 GFP_KERNEL); 1366 if (!pdn->m64_map) 1367 return -ENOMEM; 1368 /* Initialize the m64_map to IODA_INVALID_M64 */ 1369 for (i = 0; i < m64_bars ; i++) 1370 for (j = 0; j < PCI_SRIOV_NUM_BARS; j++) 1371 pdn->m64_map[i][j] = IODA_INVALID_M64; 1372 1373 1374 for (i = 0; i < PCI_SRIOV_NUM_BARS; i++) { 1375 res = &pdev->resource[i + PCI_IOV_RESOURCES]; 1376 if (!res->flags || !res->parent) 1377 continue; 1378 1379 for (j = 0; j < m64_bars; j++) { 1380 do { 1381 win = find_next_zero_bit(&phb->ioda.m64_bar_alloc, 1382 phb->ioda.m64_bar_idx + 1, 0); 1383 1384 if (win >= phb->ioda.m64_bar_idx + 1) 1385 goto m64_failed; 1386 } while (test_and_set_bit(win, &phb->ioda.m64_bar_alloc)); 1387 1388 pdn->m64_map[j][i] = win; 1389 1390 if (pdn->m64_single_mode) { 1391 size = pci_iov_resource_size(pdev, 1392 PCI_IOV_RESOURCES + i); 1393 start = res->start + size * j; 1394 } else { 1395 size = resource_size(res); 1396 start = res->start; 1397 } 1398 1399 /* Map the M64 here */ 1400 if (pdn->m64_single_mode) { 1401 pe_num = pdn->pe_num_map[j]; 1402 rc = opal_pci_map_pe_mmio_window(phb->opal_id, 1403 pe_num, OPAL_M64_WINDOW_TYPE, 1404 pdn->m64_map[j][i], 0); 1405 } 1406 1407 rc = opal_pci_set_phb_mem_window(phb->opal_id, 1408 OPAL_M64_WINDOW_TYPE, 1409 pdn->m64_map[j][i], 1410 start, 1411 0, /* unused */ 1412 size); 1413 1414 1415 if (rc != OPAL_SUCCESS) { 1416 dev_err(&pdev->dev, "Failed to map M64 window #%d: %lld\n", 1417 win, rc); 1418 goto m64_failed; 1419 } 1420 1421 if (pdn->m64_single_mode) 1422 rc = opal_pci_phb_mmio_enable(phb->opal_id, 1423 OPAL_M64_WINDOW_TYPE, pdn->m64_map[j][i], 2); 1424 else 1425 rc = opal_pci_phb_mmio_enable(phb->opal_id, 1426 OPAL_M64_WINDOW_TYPE, pdn->m64_map[j][i], 1); 1427 1428 if (rc != OPAL_SUCCESS) { 1429 dev_err(&pdev->dev, "Failed to enable M64 window #%d: %llx\n", 1430 win, rc); 1431 goto m64_failed; 1432 } 1433 } 1434 } 1435 return 0; 1436 1437 m64_failed: 1438 pnv_pci_vf_release_m64(pdev, num_vfs); 1439 return -EBUSY; 1440 } 1441 1442 static long pnv_pci_ioda2_unset_window(struct iommu_table_group *table_group, 1443 int num); 1444 1445 static void pnv_pci_ioda2_release_dma_pe(struct pci_dev *dev, struct pnv_ioda_pe *pe) 1446 { 1447 struct iommu_table *tbl; 1448 int64_t rc; 1449 1450 tbl = pe->table_group.tables[0]; 1451 rc = pnv_pci_ioda2_unset_window(&pe->table_group, 0); 1452 if (rc) 1453 pe_warn(pe, "OPAL error %ld release DMA window\n", rc); 1454 1455 pnv_pci_ioda2_set_bypass(pe, false); 1456 if (pe->table_group.group) { 1457 iommu_group_put(pe->table_group.group); 1458 BUG_ON(pe->table_group.group); 1459 } 1460 iommu_tce_table_put(tbl); 1461 } 1462 1463 static void pnv_ioda_release_vf_PE(struct pci_dev *pdev) 1464 { 1465 struct pci_bus *bus; 1466 struct pci_controller *hose; 1467 struct pnv_phb *phb; 1468 struct pnv_ioda_pe *pe, *pe_n; 1469 struct pci_dn *pdn; 1470 1471 bus = pdev->bus; 1472 hose = pci_bus_to_host(bus); 1473 phb = hose->private_data; 1474 pdn = pci_get_pdn(pdev); 1475 1476 if (!pdev->is_physfn) 1477 return; 1478 1479 list_for_each_entry_safe(pe, pe_n, &phb->ioda.pe_list, list) { 1480 if (pe->parent_dev != pdev) 1481 continue; 1482 1483 pnv_pci_ioda2_release_dma_pe(pdev, pe); 1484 1485 /* Remove from list */ 1486 mutex_lock(&phb->ioda.pe_list_mutex); 1487 list_del(&pe->list); 1488 mutex_unlock(&phb->ioda.pe_list_mutex); 1489 1490 pnv_ioda_deconfigure_pe(phb, pe); 1491 1492 pnv_ioda_free_pe(pe); 1493 } 1494 } 1495 1496 void pnv_pci_sriov_disable(struct pci_dev *pdev) 1497 { 1498 struct pci_bus *bus; 1499 struct pci_controller *hose; 1500 struct pnv_phb *phb; 1501 struct pnv_ioda_pe *pe; 1502 struct pci_dn *pdn; 1503 u16 num_vfs, i; 1504 1505 bus = pdev->bus; 1506 hose = pci_bus_to_host(bus); 1507 phb = hose->private_data; 1508 pdn = pci_get_pdn(pdev); 1509 num_vfs = pdn->num_vfs; 1510 1511 /* Release VF PEs */ 1512 pnv_ioda_release_vf_PE(pdev); 1513 1514 if (phb->type == PNV_PHB_IODA2) { 1515 if (!pdn->m64_single_mode) 1516 pnv_pci_vf_resource_shift(pdev, -*pdn->pe_num_map); 1517 1518 /* Release M64 windows */ 1519 pnv_pci_vf_release_m64(pdev, num_vfs); 1520 1521 /* Release PE numbers */ 1522 if (pdn->m64_single_mode) { 1523 for (i = 0; i < num_vfs; i++) { 1524 if (pdn->pe_num_map[i] == IODA_INVALID_PE) 1525 continue; 1526 1527 pe = &phb->ioda.pe_array[pdn->pe_num_map[i]]; 1528 pnv_ioda_free_pe(pe); 1529 } 1530 } else 1531 bitmap_clear(phb->ioda.pe_alloc, *pdn->pe_num_map, num_vfs); 1532 /* Releasing pe_num_map */ 1533 kfree(pdn->pe_num_map); 1534 } 1535 } 1536 1537 static void pnv_pci_ioda2_setup_dma_pe(struct pnv_phb *phb, 1538 struct pnv_ioda_pe *pe); 1539 static void pnv_ioda_setup_vf_PE(struct pci_dev *pdev, u16 num_vfs) 1540 { 1541 struct pci_bus *bus; 1542 struct pci_controller *hose; 1543 struct pnv_phb *phb; 1544 struct pnv_ioda_pe *pe; 1545 int pe_num; 1546 u16 vf_index; 1547 struct pci_dn *pdn; 1548 1549 bus = pdev->bus; 1550 hose = pci_bus_to_host(bus); 1551 phb = hose->private_data; 1552 pdn = pci_get_pdn(pdev); 1553 1554 if (!pdev->is_physfn) 1555 return; 1556 1557 /* Reserve PE for each VF */ 1558 for (vf_index = 0; vf_index < num_vfs; vf_index++) { 1559 if (pdn->m64_single_mode) 1560 pe_num = pdn->pe_num_map[vf_index]; 1561 else 1562 pe_num = *pdn->pe_num_map + vf_index; 1563 1564 pe = &phb->ioda.pe_array[pe_num]; 1565 pe->pe_number = pe_num; 1566 pe->phb = phb; 1567 pe->flags = PNV_IODA_PE_VF; 1568 pe->pbus = NULL; 1569 pe->parent_dev = pdev; 1570 pe->mve_number = -1; 1571 pe->rid = (pci_iov_virtfn_bus(pdev, vf_index) << 8) | 1572 pci_iov_virtfn_devfn(pdev, vf_index); 1573 1574 pe_info(pe, "VF %04d:%02d:%02d.%d associated with PE#%x\n", 1575 hose->global_number, pdev->bus->number, 1576 PCI_SLOT(pci_iov_virtfn_devfn(pdev, vf_index)), 1577 PCI_FUNC(pci_iov_virtfn_devfn(pdev, vf_index)), pe_num); 1578 1579 if (pnv_ioda_configure_pe(phb, pe)) { 1580 /* XXX What do we do here ? */ 1581 pnv_ioda_free_pe(pe); 1582 pe->pdev = NULL; 1583 continue; 1584 } 1585 1586 /* Put PE to the list */ 1587 mutex_lock(&phb->ioda.pe_list_mutex); 1588 list_add_tail(&pe->list, &phb->ioda.pe_list); 1589 mutex_unlock(&phb->ioda.pe_list_mutex); 1590 1591 pnv_pci_ioda2_setup_dma_pe(phb, pe); 1592 } 1593 } 1594 1595 int pnv_pci_sriov_enable(struct pci_dev *pdev, u16 num_vfs) 1596 { 1597 struct pci_bus *bus; 1598 struct pci_controller *hose; 1599 struct pnv_phb *phb; 1600 struct pnv_ioda_pe *pe; 1601 struct pci_dn *pdn; 1602 int ret; 1603 u16 i; 1604 1605 bus = pdev->bus; 1606 hose = pci_bus_to_host(bus); 1607 phb = hose->private_data; 1608 pdn = pci_get_pdn(pdev); 1609 1610 if (phb->type == PNV_PHB_IODA2) { 1611 if (!pdn->vfs_expanded) { 1612 dev_info(&pdev->dev, "don't support this SRIOV device" 1613 " with non 64bit-prefetchable IOV BAR\n"); 1614 return -ENOSPC; 1615 } 1616 1617 /* 1618 * When M64 BARs functions in Single PE mode, the number of VFs 1619 * could be enabled must be less than the number of M64 BARs. 1620 */ 1621 if (pdn->m64_single_mode && num_vfs > phb->ioda.m64_bar_idx) { 1622 dev_info(&pdev->dev, "Not enough M64 BAR for VFs\n"); 1623 return -EBUSY; 1624 } 1625 1626 /* Allocating pe_num_map */ 1627 if (pdn->m64_single_mode) 1628 pdn->pe_num_map = kmalloc_array(num_vfs, 1629 sizeof(*pdn->pe_num_map), 1630 GFP_KERNEL); 1631 else 1632 pdn->pe_num_map = kmalloc(sizeof(*pdn->pe_num_map), GFP_KERNEL); 1633 1634 if (!pdn->pe_num_map) 1635 return -ENOMEM; 1636 1637 if (pdn->m64_single_mode) 1638 for (i = 0; i < num_vfs; i++) 1639 pdn->pe_num_map[i] = IODA_INVALID_PE; 1640 1641 /* Calculate available PE for required VFs */ 1642 if (pdn->m64_single_mode) { 1643 for (i = 0; i < num_vfs; i++) { 1644 pe = pnv_ioda_alloc_pe(phb); 1645 if (!pe) { 1646 ret = -EBUSY; 1647 goto m64_failed; 1648 } 1649 1650 pdn->pe_num_map[i] = pe->pe_number; 1651 } 1652 } else { 1653 mutex_lock(&phb->ioda.pe_alloc_mutex); 1654 *pdn->pe_num_map = bitmap_find_next_zero_area( 1655 phb->ioda.pe_alloc, phb->ioda.total_pe_num, 1656 0, num_vfs, 0); 1657 if (*pdn->pe_num_map >= phb->ioda.total_pe_num) { 1658 mutex_unlock(&phb->ioda.pe_alloc_mutex); 1659 dev_info(&pdev->dev, "Failed to enable VF%d\n", num_vfs); 1660 kfree(pdn->pe_num_map); 1661 return -EBUSY; 1662 } 1663 bitmap_set(phb->ioda.pe_alloc, *pdn->pe_num_map, num_vfs); 1664 mutex_unlock(&phb->ioda.pe_alloc_mutex); 1665 } 1666 pdn->num_vfs = num_vfs; 1667 1668 /* Assign M64 window accordingly */ 1669 ret = pnv_pci_vf_assign_m64(pdev, num_vfs); 1670 if (ret) { 1671 dev_info(&pdev->dev, "Not enough M64 window resources\n"); 1672 goto m64_failed; 1673 } 1674 1675 /* 1676 * When using one M64 BAR to map one IOV BAR, we need to shift 1677 * the IOV BAR according to the PE# allocated to the VFs. 1678 * Otherwise, the PE# for the VF will conflict with others. 1679 */ 1680 if (!pdn->m64_single_mode) { 1681 ret = pnv_pci_vf_resource_shift(pdev, *pdn->pe_num_map); 1682 if (ret) 1683 goto m64_failed; 1684 } 1685 } 1686 1687 /* Setup VF PEs */ 1688 pnv_ioda_setup_vf_PE(pdev, num_vfs); 1689 1690 return 0; 1691 1692 m64_failed: 1693 if (pdn->m64_single_mode) { 1694 for (i = 0; i < num_vfs; i++) { 1695 if (pdn->pe_num_map[i] == IODA_INVALID_PE) 1696 continue; 1697 1698 pe = &phb->ioda.pe_array[pdn->pe_num_map[i]]; 1699 pnv_ioda_free_pe(pe); 1700 } 1701 } else 1702 bitmap_clear(phb->ioda.pe_alloc, *pdn->pe_num_map, num_vfs); 1703 1704 /* Releasing pe_num_map */ 1705 kfree(pdn->pe_num_map); 1706 1707 return ret; 1708 } 1709 1710 int pnv_pcibios_sriov_disable(struct pci_dev *pdev) 1711 { 1712 pnv_pci_sriov_disable(pdev); 1713 1714 /* Release PCI data */ 1715 remove_dev_pci_data(pdev); 1716 return 0; 1717 } 1718 1719 int pnv_pcibios_sriov_enable(struct pci_dev *pdev, u16 num_vfs) 1720 { 1721 /* Allocate PCI data */ 1722 add_dev_pci_data(pdev); 1723 1724 return pnv_pci_sriov_enable(pdev, num_vfs); 1725 } 1726 #endif /* CONFIG_PCI_IOV */ 1727 1728 static void pnv_pci_ioda_dma_dev_setup(struct pnv_phb *phb, struct pci_dev *pdev) 1729 { 1730 struct pci_dn *pdn = pci_get_pdn(pdev); 1731 struct pnv_ioda_pe *pe; 1732 1733 /* 1734 * The function can be called while the PE# 1735 * hasn't been assigned. Do nothing for the 1736 * case. 1737 */ 1738 if (!pdn || pdn->pe_number == IODA_INVALID_PE) 1739 return; 1740 1741 pe = &phb->ioda.pe_array[pdn->pe_number]; 1742 WARN_ON(get_dma_ops(&pdev->dev) != &dma_iommu_ops); 1743 set_dma_offset(&pdev->dev, pe->tce_bypass_base); 1744 set_iommu_table_base(&pdev->dev, pe->table_group.tables[0]); 1745 /* 1746 * Note: iommu_add_device() will fail here as 1747 * for physical PE: the device is already added by now; 1748 * for virtual PE: sysfs entries are not ready yet and 1749 * tce_iommu_bus_notifier will add the device to a group later. 1750 */ 1751 } 1752 1753 static bool pnv_pci_ioda_pe_single_vendor(struct pnv_ioda_pe *pe) 1754 { 1755 unsigned short vendor = 0; 1756 struct pci_dev *pdev; 1757 1758 if (pe->device_count == 1) 1759 return true; 1760 1761 /* pe->pdev should be set if it's a single device, pe->pbus if not */ 1762 if (!pe->pbus) 1763 return true; 1764 1765 list_for_each_entry(pdev, &pe->pbus->devices, bus_list) { 1766 if (!vendor) { 1767 vendor = pdev->vendor; 1768 continue; 1769 } 1770 1771 if (pdev->vendor != vendor) 1772 return false; 1773 } 1774 1775 return true; 1776 } 1777 1778 /* 1779 * Reconfigure TVE#0 to be usable as 64-bit DMA space. 1780 * 1781 * The first 4GB of virtual memory for a PE is reserved for 32-bit accesses. 1782 * Devices can only access more than that if bit 59 of the PCI address is set 1783 * by hardware, which indicates TVE#1 should be used instead of TVE#0. 1784 * Many PCI devices are not capable of addressing that many bits, and as a 1785 * result are limited to the 4GB of virtual memory made available to 32-bit 1786 * devices in TVE#0. 1787 * 1788 * In order to work around this, reconfigure TVE#0 to be suitable for 64-bit 1789 * devices by configuring the virtual memory past the first 4GB inaccessible 1790 * by 64-bit DMAs. This should only be used by devices that want more than 1791 * 4GB, and only on PEs that have no 32-bit devices. 1792 * 1793 * Currently this will only work on PHB3 (POWER8). 1794 */ 1795 static int pnv_pci_ioda_dma_64bit_bypass(struct pnv_ioda_pe *pe) 1796 { 1797 u64 window_size, table_size, tce_count, addr; 1798 struct page *table_pages; 1799 u64 tce_order = 28; /* 256MB TCEs */ 1800 __be64 *tces; 1801 s64 rc; 1802 1803 /* 1804 * Window size needs to be a power of two, but needs to account for 1805 * shifting memory by the 4GB offset required to skip 32bit space. 1806 */ 1807 window_size = roundup_pow_of_two(memory_hotplug_max() + (1ULL << 32)); 1808 tce_count = window_size >> tce_order; 1809 table_size = tce_count << 3; 1810 1811 if (table_size < PAGE_SIZE) 1812 table_size = PAGE_SIZE; 1813 1814 table_pages = alloc_pages_node(pe->phb->hose->node, GFP_KERNEL, 1815 get_order(table_size)); 1816 if (!table_pages) 1817 goto err; 1818 1819 tces = page_address(table_pages); 1820 if (!tces) 1821 goto err; 1822 1823 memset(tces, 0, table_size); 1824 1825 for (addr = 0; addr < memory_hotplug_max(); addr += (1 << tce_order)) { 1826 tces[(addr + (1ULL << 32)) >> tce_order] = 1827 cpu_to_be64(addr | TCE_PCI_READ | TCE_PCI_WRITE); 1828 } 1829 1830 rc = opal_pci_map_pe_dma_window(pe->phb->opal_id, 1831 pe->pe_number, 1832 /* reconfigure window 0 */ 1833 (pe->pe_number << 1) + 0, 1834 1, 1835 __pa(tces), 1836 table_size, 1837 1 << tce_order); 1838 if (rc == OPAL_SUCCESS) { 1839 pe_info(pe, "Using 64-bit DMA iommu bypass (through TVE#0)\n"); 1840 return 0; 1841 } 1842 err: 1843 pe_err(pe, "Error configuring 64-bit DMA bypass\n"); 1844 return -EIO; 1845 } 1846 1847 static int pnv_pci_ioda_dma_set_mask(struct pci_dev *pdev, u64 dma_mask) 1848 { 1849 struct pci_controller *hose = pci_bus_to_host(pdev->bus); 1850 struct pnv_phb *phb = hose->private_data; 1851 struct pci_dn *pdn = pci_get_pdn(pdev); 1852 struct pnv_ioda_pe *pe; 1853 uint64_t top; 1854 bool bypass = false; 1855 s64 rc; 1856 1857 if (WARN_ON(!pdn || pdn->pe_number == IODA_INVALID_PE)) 1858 return -ENODEV; 1859 1860 pe = &phb->ioda.pe_array[pdn->pe_number]; 1861 if (pe->tce_bypass_enabled) { 1862 top = pe->tce_bypass_base + memblock_end_of_DRAM() - 1; 1863 bypass = (dma_mask >= top); 1864 } 1865 1866 if (bypass) { 1867 dev_info(&pdev->dev, "Using 64-bit DMA iommu bypass\n"); 1868 set_dma_ops(&pdev->dev, &dma_nommu_ops); 1869 } else { 1870 /* 1871 * If the device can't set the TCE bypass bit but still wants 1872 * to access 4GB or more, on PHB3 we can reconfigure TVE#0 to 1873 * bypass the 32-bit region and be usable for 64-bit DMAs. 1874 * The device needs to be able to address all of this space. 1875 */ 1876 if (dma_mask >> 32 && 1877 dma_mask > (memory_hotplug_max() + (1ULL << 32)) && 1878 pnv_pci_ioda_pe_single_vendor(pe) && 1879 phb->model == PNV_PHB_MODEL_PHB3) { 1880 /* Configure the bypass mode */ 1881 rc = pnv_pci_ioda_dma_64bit_bypass(pe); 1882 if (rc) 1883 return rc; 1884 /* 4GB offset bypasses 32-bit space */ 1885 set_dma_offset(&pdev->dev, (1ULL << 32)); 1886 set_dma_ops(&pdev->dev, &dma_nommu_ops); 1887 } else if (dma_mask >> 32 && dma_mask != DMA_BIT_MASK(64)) { 1888 /* 1889 * Fail the request if a DMA mask between 32 and 64 bits 1890 * was requested but couldn't be fulfilled. Ideally we 1891 * would do this for 64-bits but historically we have 1892 * always fallen back to 32-bits. 1893 */ 1894 return -ENOMEM; 1895 } else { 1896 dev_info(&pdev->dev, "Using 32-bit DMA via iommu\n"); 1897 set_dma_ops(&pdev->dev, &dma_iommu_ops); 1898 } 1899 } 1900 *pdev->dev.dma_mask = dma_mask; 1901 1902 /* Update peer npu devices */ 1903 pnv_npu_try_dma_set_bypass(pdev, bypass); 1904 1905 return 0; 1906 } 1907 1908 static u64 pnv_pci_ioda_dma_get_required_mask(struct pci_dev *pdev) 1909 { 1910 struct pci_controller *hose = pci_bus_to_host(pdev->bus); 1911 struct pnv_phb *phb = hose->private_data; 1912 struct pci_dn *pdn = pci_get_pdn(pdev); 1913 struct pnv_ioda_pe *pe; 1914 u64 end, mask; 1915 1916 if (WARN_ON(!pdn || pdn->pe_number == IODA_INVALID_PE)) 1917 return 0; 1918 1919 pe = &phb->ioda.pe_array[pdn->pe_number]; 1920 if (!pe->tce_bypass_enabled) 1921 return __dma_get_required_mask(&pdev->dev); 1922 1923 1924 end = pe->tce_bypass_base + memblock_end_of_DRAM(); 1925 mask = 1ULL << (fls64(end) - 1); 1926 mask += mask - 1; 1927 1928 return mask; 1929 } 1930 1931 static void pnv_ioda_setup_bus_dma(struct pnv_ioda_pe *pe, 1932 struct pci_bus *bus, 1933 bool add_to_group) 1934 { 1935 struct pci_dev *dev; 1936 1937 list_for_each_entry(dev, &bus->devices, bus_list) { 1938 set_iommu_table_base(&dev->dev, pe->table_group.tables[0]); 1939 set_dma_offset(&dev->dev, pe->tce_bypass_base); 1940 if (add_to_group) 1941 iommu_add_device(&dev->dev); 1942 1943 if ((pe->flags & PNV_IODA_PE_BUS_ALL) && dev->subordinate) 1944 pnv_ioda_setup_bus_dma(pe, dev->subordinate, 1945 add_to_group); 1946 } 1947 } 1948 1949 static inline __be64 __iomem *pnv_ioda_get_inval_reg(struct pnv_phb *phb, 1950 bool real_mode) 1951 { 1952 return real_mode ? (__be64 __iomem *)(phb->regs_phys + 0x210) : 1953 (phb->regs + 0x210); 1954 } 1955 1956 static void pnv_pci_p7ioc_tce_invalidate(struct iommu_table *tbl, 1957 unsigned long index, unsigned long npages, bool rm) 1958 { 1959 struct iommu_table_group_link *tgl = list_first_entry_or_null( 1960 &tbl->it_group_list, struct iommu_table_group_link, 1961 next); 1962 struct pnv_ioda_pe *pe = container_of(tgl->table_group, 1963 struct pnv_ioda_pe, table_group); 1964 __be64 __iomem *invalidate = pnv_ioda_get_inval_reg(pe->phb, rm); 1965 unsigned long start, end, inc; 1966 1967 start = __pa(((__be64 *)tbl->it_base) + index - tbl->it_offset); 1968 end = __pa(((__be64 *)tbl->it_base) + index - tbl->it_offset + 1969 npages - 1); 1970 1971 /* p7ioc-style invalidation, 2 TCEs per write */ 1972 start |= (1ull << 63); 1973 end |= (1ull << 63); 1974 inc = 16; 1975 end |= inc - 1; /* round up end to be different than start */ 1976 1977 mb(); /* Ensure above stores are visible */ 1978 while (start <= end) { 1979 if (rm) 1980 __raw_rm_writeq_be(start, invalidate); 1981 else 1982 __raw_writeq_be(start, invalidate); 1983 1984 start += inc; 1985 } 1986 1987 /* 1988 * The iommu layer will do another mb() for us on build() 1989 * and we don't care on free() 1990 */ 1991 } 1992 1993 static int pnv_ioda1_tce_build(struct iommu_table *tbl, long index, 1994 long npages, unsigned long uaddr, 1995 enum dma_data_direction direction, 1996 unsigned long attrs) 1997 { 1998 int ret = pnv_tce_build(tbl, index, npages, uaddr, direction, 1999 attrs); 2000 2001 if (!ret) 2002 pnv_pci_p7ioc_tce_invalidate(tbl, index, npages, false); 2003 2004 return ret; 2005 } 2006 2007 #ifdef CONFIG_IOMMU_API 2008 static int pnv_ioda1_tce_xchg(struct iommu_table *tbl, long index, 2009 unsigned long *hpa, enum dma_data_direction *direction) 2010 { 2011 long ret = pnv_tce_xchg(tbl, index, hpa, direction); 2012 2013 if (!ret) 2014 pnv_pci_p7ioc_tce_invalidate(tbl, index, 1, false); 2015 2016 return ret; 2017 } 2018 2019 static int pnv_ioda1_tce_xchg_rm(struct iommu_table *tbl, long index, 2020 unsigned long *hpa, enum dma_data_direction *direction) 2021 { 2022 long ret = pnv_tce_xchg(tbl, index, hpa, direction); 2023 2024 if (!ret) 2025 pnv_pci_p7ioc_tce_invalidate(tbl, index, 1, true); 2026 2027 return ret; 2028 } 2029 #endif 2030 2031 static void pnv_ioda1_tce_free(struct iommu_table *tbl, long index, 2032 long npages) 2033 { 2034 pnv_tce_free(tbl, index, npages); 2035 2036 pnv_pci_p7ioc_tce_invalidate(tbl, index, npages, false); 2037 } 2038 2039 static struct iommu_table_ops pnv_ioda1_iommu_ops = { 2040 .set = pnv_ioda1_tce_build, 2041 #ifdef CONFIG_IOMMU_API 2042 .exchange = pnv_ioda1_tce_xchg, 2043 .exchange_rm = pnv_ioda1_tce_xchg_rm, 2044 #endif 2045 .clear = pnv_ioda1_tce_free, 2046 .get = pnv_tce_get, 2047 }; 2048 2049 #define PHB3_TCE_KILL_INVAL_ALL PPC_BIT(0) 2050 #define PHB3_TCE_KILL_INVAL_PE PPC_BIT(1) 2051 #define PHB3_TCE_KILL_INVAL_ONE PPC_BIT(2) 2052 2053 static void pnv_pci_phb3_tce_invalidate_entire(struct pnv_phb *phb, bool rm) 2054 { 2055 __be64 __iomem *invalidate = pnv_ioda_get_inval_reg(phb, rm); 2056 const unsigned long val = PHB3_TCE_KILL_INVAL_ALL; 2057 2058 mb(); /* Ensure previous TCE table stores are visible */ 2059 if (rm) 2060 __raw_rm_writeq_be(val, invalidate); 2061 else 2062 __raw_writeq_be(val, invalidate); 2063 } 2064 2065 static inline void pnv_pci_phb3_tce_invalidate_pe(struct pnv_ioda_pe *pe) 2066 { 2067 /* 01xb - invalidate TCEs that match the specified PE# */ 2068 __be64 __iomem *invalidate = pnv_ioda_get_inval_reg(pe->phb, false); 2069 unsigned long val = PHB3_TCE_KILL_INVAL_PE | (pe->pe_number & 0xFF); 2070 2071 mb(); /* Ensure above stores are visible */ 2072 __raw_writeq_be(val, invalidate); 2073 } 2074 2075 static void pnv_pci_phb3_tce_invalidate(struct pnv_ioda_pe *pe, bool rm, 2076 unsigned shift, unsigned long index, 2077 unsigned long npages) 2078 { 2079 __be64 __iomem *invalidate = pnv_ioda_get_inval_reg(pe->phb, rm); 2080 unsigned long start, end, inc; 2081 2082 /* We'll invalidate DMA address in PE scope */ 2083 start = PHB3_TCE_KILL_INVAL_ONE; 2084 start |= (pe->pe_number & 0xFF); 2085 end = start; 2086 2087 /* Figure out the start, end and step */ 2088 start |= (index << shift); 2089 end |= ((index + npages - 1) << shift); 2090 inc = (0x1ull << shift); 2091 mb(); 2092 2093 while (start <= end) { 2094 if (rm) 2095 __raw_rm_writeq_be(start, invalidate); 2096 else 2097 __raw_writeq_be(start, invalidate); 2098 start += inc; 2099 } 2100 } 2101 2102 static inline void pnv_pci_ioda2_tce_invalidate_pe(struct pnv_ioda_pe *pe) 2103 { 2104 struct pnv_phb *phb = pe->phb; 2105 2106 if (phb->model == PNV_PHB_MODEL_PHB3 && phb->regs) 2107 pnv_pci_phb3_tce_invalidate_pe(pe); 2108 else 2109 opal_pci_tce_kill(phb->opal_id, OPAL_PCI_TCE_KILL_PE, 2110 pe->pe_number, 0, 0, 0); 2111 } 2112 2113 static void pnv_pci_ioda2_tce_invalidate(struct iommu_table *tbl, 2114 unsigned long index, unsigned long npages, bool rm) 2115 { 2116 struct iommu_table_group_link *tgl; 2117 2118 list_for_each_entry_lockless(tgl, &tbl->it_group_list, next) { 2119 struct pnv_ioda_pe *pe = container_of(tgl->table_group, 2120 struct pnv_ioda_pe, table_group); 2121 struct pnv_phb *phb = pe->phb; 2122 unsigned int shift = tbl->it_page_shift; 2123 2124 /* 2125 * NVLink1 can use the TCE kill register directly as 2126 * it's the same as PHB3. NVLink2 is different and 2127 * should go via the OPAL call. 2128 */ 2129 if (phb->model == PNV_PHB_MODEL_NPU) { 2130 /* 2131 * The NVLink hardware does not support TCE kill 2132 * per TCE entry so we have to invalidate 2133 * the entire cache for it. 2134 */ 2135 pnv_pci_phb3_tce_invalidate_entire(phb, rm); 2136 continue; 2137 } 2138 if (phb->model == PNV_PHB_MODEL_PHB3 && phb->regs) 2139 pnv_pci_phb3_tce_invalidate(pe, rm, shift, 2140 index, npages); 2141 else 2142 opal_pci_tce_kill(phb->opal_id, 2143 OPAL_PCI_TCE_KILL_PAGES, 2144 pe->pe_number, 1u << shift, 2145 index << shift, npages); 2146 } 2147 } 2148 2149 void pnv_pci_ioda2_tce_invalidate_entire(struct pnv_phb *phb, bool rm) 2150 { 2151 if (phb->model == PNV_PHB_MODEL_NPU || phb->model == PNV_PHB_MODEL_PHB3) 2152 pnv_pci_phb3_tce_invalidate_entire(phb, rm); 2153 else 2154 opal_pci_tce_kill(phb->opal_id, OPAL_PCI_TCE_KILL, 0, 0, 0, 0); 2155 } 2156 2157 static int pnv_ioda2_tce_build(struct iommu_table *tbl, long index, 2158 long npages, unsigned long uaddr, 2159 enum dma_data_direction direction, 2160 unsigned long attrs) 2161 { 2162 int ret = pnv_tce_build(tbl, index, npages, uaddr, direction, 2163 attrs); 2164 2165 if (!ret) 2166 pnv_pci_ioda2_tce_invalidate(tbl, index, npages, false); 2167 2168 return ret; 2169 } 2170 2171 #ifdef CONFIG_IOMMU_API 2172 static int pnv_ioda2_tce_xchg(struct iommu_table *tbl, long index, 2173 unsigned long *hpa, enum dma_data_direction *direction) 2174 { 2175 long ret = pnv_tce_xchg(tbl, index, hpa, direction); 2176 2177 if (!ret) 2178 pnv_pci_ioda2_tce_invalidate(tbl, index, 1, false); 2179 2180 return ret; 2181 } 2182 2183 static int pnv_ioda2_tce_xchg_rm(struct iommu_table *tbl, long index, 2184 unsigned long *hpa, enum dma_data_direction *direction) 2185 { 2186 long ret = pnv_tce_xchg(tbl, index, hpa, direction); 2187 2188 if (!ret) 2189 pnv_pci_ioda2_tce_invalidate(tbl, index, 1, true); 2190 2191 return ret; 2192 } 2193 #endif 2194 2195 static void pnv_ioda2_tce_free(struct iommu_table *tbl, long index, 2196 long npages) 2197 { 2198 pnv_tce_free(tbl, index, npages); 2199 2200 pnv_pci_ioda2_tce_invalidate(tbl, index, npages, false); 2201 } 2202 2203 static void pnv_ioda2_table_free(struct iommu_table *tbl) 2204 { 2205 pnv_pci_ioda2_table_free_pages(tbl); 2206 } 2207 2208 static struct iommu_table_ops pnv_ioda2_iommu_ops = { 2209 .set = pnv_ioda2_tce_build, 2210 #ifdef CONFIG_IOMMU_API 2211 .exchange = pnv_ioda2_tce_xchg, 2212 .exchange_rm = pnv_ioda2_tce_xchg_rm, 2213 #endif 2214 .clear = pnv_ioda2_tce_free, 2215 .get = pnv_tce_get, 2216 .free = pnv_ioda2_table_free, 2217 }; 2218 2219 static int pnv_pci_ioda_dev_dma_weight(struct pci_dev *dev, void *data) 2220 { 2221 unsigned int *weight = (unsigned int *)data; 2222 2223 /* This is quite simplistic. The "base" weight of a device 2224 * is 10. 0 means no DMA is to be accounted for it. 2225 */ 2226 if (dev->hdr_type != PCI_HEADER_TYPE_NORMAL) 2227 return 0; 2228 2229 if (dev->class == PCI_CLASS_SERIAL_USB_UHCI || 2230 dev->class == PCI_CLASS_SERIAL_USB_OHCI || 2231 dev->class == PCI_CLASS_SERIAL_USB_EHCI) 2232 *weight += 3; 2233 else if ((dev->class >> 8) == PCI_CLASS_STORAGE_RAID) 2234 *weight += 15; 2235 else 2236 *weight += 10; 2237 2238 return 0; 2239 } 2240 2241 static unsigned int pnv_pci_ioda_pe_dma_weight(struct pnv_ioda_pe *pe) 2242 { 2243 unsigned int weight = 0; 2244 2245 /* SRIOV VF has same DMA32 weight as its PF */ 2246 #ifdef CONFIG_PCI_IOV 2247 if ((pe->flags & PNV_IODA_PE_VF) && pe->parent_dev) { 2248 pnv_pci_ioda_dev_dma_weight(pe->parent_dev, &weight); 2249 return weight; 2250 } 2251 #endif 2252 2253 if ((pe->flags & PNV_IODA_PE_DEV) && pe->pdev) { 2254 pnv_pci_ioda_dev_dma_weight(pe->pdev, &weight); 2255 } else if ((pe->flags & PNV_IODA_PE_BUS) && pe->pbus) { 2256 struct pci_dev *pdev; 2257 2258 list_for_each_entry(pdev, &pe->pbus->devices, bus_list) 2259 pnv_pci_ioda_dev_dma_weight(pdev, &weight); 2260 } else if ((pe->flags & PNV_IODA_PE_BUS_ALL) && pe->pbus) { 2261 pci_walk_bus(pe->pbus, pnv_pci_ioda_dev_dma_weight, &weight); 2262 } 2263 2264 return weight; 2265 } 2266 2267 static void pnv_pci_ioda1_setup_dma_pe(struct pnv_phb *phb, 2268 struct pnv_ioda_pe *pe) 2269 { 2270 2271 struct page *tce_mem = NULL; 2272 struct iommu_table *tbl; 2273 unsigned int weight, total_weight = 0; 2274 unsigned int tce32_segsz, base, segs, avail, i; 2275 int64_t rc; 2276 void *addr; 2277 2278 /* XXX FIXME: Handle 64-bit only DMA devices */ 2279 /* XXX FIXME: Provide 64-bit DMA facilities & non-4K TCE tables etc.. */ 2280 /* XXX FIXME: Allocate multi-level tables on PHB3 */ 2281 weight = pnv_pci_ioda_pe_dma_weight(pe); 2282 if (!weight) 2283 return; 2284 2285 pci_walk_bus(phb->hose->bus, pnv_pci_ioda_dev_dma_weight, 2286 &total_weight); 2287 segs = (weight * phb->ioda.dma32_count) / total_weight; 2288 if (!segs) 2289 segs = 1; 2290 2291 /* 2292 * Allocate contiguous DMA32 segments. We begin with the expected 2293 * number of segments. With one more attempt, the number of DMA32 2294 * segments to be allocated is decreased by one until one segment 2295 * is allocated successfully. 2296 */ 2297 do { 2298 for (base = 0; base <= phb->ioda.dma32_count - segs; base++) { 2299 for (avail = 0, i = base; i < base + segs; i++) { 2300 if (phb->ioda.dma32_segmap[i] == 2301 IODA_INVALID_PE) 2302 avail++; 2303 } 2304 2305 if (avail == segs) 2306 goto found; 2307 } 2308 } while (--segs); 2309 2310 if (!segs) { 2311 pe_warn(pe, "No available DMA32 segments\n"); 2312 return; 2313 } 2314 2315 found: 2316 tbl = pnv_pci_table_alloc(phb->hose->node); 2317 if (WARN_ON(!tbl)) 2318 return; 2319 2320 iommu_register_group(&pe->table_group, phb->hose->global_number, 2321 pe->pe_number); 2322 pnv_pci_link_table_and_group(phb->hose->node, 0, tbl, &pe->table_group); 2323 2324 /* Grab a 32-bit TCE table */ 2325 pe_info(pe, "DMA weight %d (%d), assigned (%d) %d DMA32 segments\n", 2326 weight, total_weight, base, segs); 2327 pe_info(pe, " Setting up 32-bit TCE table at %08x..%08x\n", 2328 base * PNV_IODA1_DMA32_SEGSIZE, 2329 (base + segs) * PNV_IODA1_DMA32_SEGSIZE - 1); 2330 2331 /* XXX Currently, we allocate one big contiguous table for the 2332 * TCEs. We only really need one chunk per 256M of TCE space 2333 * (ie per segment) but that's an optimization for later, it 2334 * requires some added smarts with our get/put_tce implementation 2335 * 2336 * Each TCE page is 4KB in size and each TCE entry occupies 8 2337 * bytes 2338 */ 2339 tce32_segsz = PNV_IODA1_DMA32_SEGSIZE >> (IOMMU_PAGE_SHIFT_4K - 3); 2340 tce_mem = alloc_pages_node(phb->hose->node, GFP_KERNEL, 2341 get_order(tce32_segsz * segs)); 2342 if (!tce_mem) { 2343 pe_err(pe, " Failed to allocate a 32-bit TCE memory\n"); 2344 goto fail; 2345 } 2346 addr = page_address(tce_mem); 2347 memset(addr, 0, tce32_segsz * segs); 2348 2349 /* Configure HW */ 2350 for (i = 0; i < segs; i++) { 2351 rc = opal_pci_map_pe_dma_window(phb->opal_id, 2352 pe->pe_number, 2353 base + i, 1, 2354 __pa(addr) + tce32_segsz * i, 2355 tce32_segsz, IOMMU_PAGE_SIZE_4K); 2356 if (rc) { 2357 pe_err(pe, " Failed to configure 32-bit TCE table," 2358 " err %ld\n", rc); 2359 goto fail; 2360 } 2361 } 2362 2363 /* Setup DMA32 segment mapping */ 2364 for (i = base; i < base + segs; i++) 2365 phb->ioda.dma32_segmap[i] = pe->pe_number; 2366 2367 /* Setup linux iommu table */ 2368 pnv_pci_setup_iommu_table(tbl, addr, tce32_segsz * segs, 2369 base * PNV_IODA1_DMA32_SEGSIZE, 2370 IOMMU_PAGE_SHIFT_4K); 2371 2372 tbl->it_ops = &pnv_ioda1_iommu_ops; 2373 pe->table_group.tce32_start = tbl->it_offset << tbl->it_page_shift; 2374 pe->table_group.tce32_size = tbl->it_size << tbl->it_page_shift; 2375 iommu_init_table(tbl, phb->hose->node); 2376 2377 if (pe->flags & PNV_IODA_PE_DEV) { 2378 /* 2379 * Setting table base here only for carrying iommu_group 2380 * further down to let iommu_add_device() do the job. 2381 * pnv_pci_ioda_dma_dev_setup will override it later anyway. 2382 */ 2383 set_iommu_table_base(&pe->pdev->dev, tbl); 2384 iommu_add_device(&pe->pdev->dev); 2385 } else if (pe->flags & (PNV_IODA_PE_BUS | PNV_IODA_PE_BUS_ALL)) 2386 pnv_ioda_setup_bus_dma(pe, pe->pbus, true); 2387 2388 return; 2389 fail: 2390 /* XXX Failure: Try to fallback to 64-bit only ? */ 2391 if (tce_mem) 2392 __free_pages(tce_mem, get_order(tce32_segsz * segs)); 2393 if (tbl) { 2394 pnv_pci_unlink_table_and_group(tbl, &pe->table_group); 2395 iommu_tce_table_put(tbl); 2396 } 2397 } 2398 2399 static long pnv_pci_ioda2_set_window(struct iommu_table_group *table_group, 2400 int num, struct iommu_table *tbl) 2401 { 2402 struct pnv_ioda_pe *pe = container_of(table_group, struct pnv_ioda_pe, 2403 table_group); 2404 struct pnv_phb *phb = pe->phb; 2405 int64_t rc; 2406 const unsigned long size = tbl->it_indirect_levels ? 2407 tbl->it_level_size : tbl->it_size; 2408 const __u64 start_addr = tbl->it_offset << tbl->it_page_shift; 2409 const __u64 win_size = tbl->it_size << tbl->it_page_shift; 2410 2411 pe_info(pe, "Setting up window#%d %llx..%llx pg=%x\n", num, 2412 start_addr, start_addr + win_size - 1, 2413 IOMMU_PAGE_SIZE(tbl)); 2414 2415 /* 2416 * Map TCE table through TVT. The TVE index is the PE number 2417 * shifted by 1 bit for 32-bits DMA space. 2418 */ 2419 rc = opal_pci_map_pe_dma_window(phb->opal_id, 2420 pe->pe_number, 2421 (pe->pe_number << 1) + num, 2422 tbl->it_indirect_levels + 1, 2423 __pa(tbl->it_base), 2424 size << 3, 2425 IOMMU_PAGE_SIZE(tbl)); 2426 if (rc) { 2427 pe_err(pe, "Failed to configure TCE table, err %ld\n", rc); 2428 return rc; 2429 } 2430 2431 pnv_pci_link_table_and_group(phb->hose->node, num, 2432 tbl, &pe->table_group); 2433 pnv_pci_ioda2_tce_invalidate_pe(pe); 2434 2435 return 0; 2436 } 2437 2438 void pnv_pci_ioda2_set_bypass(struct pnv_ioda_pe *pe, bool enable) 2439 { 2440 uint16_t window_id = (pe->pe_number << 1 ) + 1; 2441 int64_t rc; 2442 2443 pe_info(pe, "%sabling 64-bit DMA bypass\n", enable ? "En" : "Dis"); 2444 if (enable) { 2445 phys_addr_t top = memblock_end_of_DRAM(); 2446 2447 top = roundup_pow_of_two(top); 2448 rc = opal_pci_map_pe_dma_window_real(pe->phb->opal_id, 2449 pe->pe_number, 2450 window_id, 2451 pe->tce_bypass_base, 2452 top); 2453 } else { 2454 rc = opal_pci_map_pe_dma_window_real(pe->phb->opal_id, 2455 pe->pe_number, 2456 window_id, 2457 pe->tce_bypass_base, 2458 0); 2459 } 2460 if (rc) 2461 pe_err(pe, "OPAL error %lld configuring bypass window\n", rc); 2462 else 2463 pe->tce_bypass_enabled = enable; 2464 } 2465 2466 static long pnv_pci_ioda2_table_alloc_pages(int nid, __u64 bus_offset, 2467 __u32 page_shift, __u64 window_size, __u32 levels, 2468 struct iommu_table *tbl); 2469 2470 static long pnv_pci_ioda2_create_table(struct iommu_table_group *table_group, 2471 int num, __u32 page_shift, __u64 window_size, __u32 levels, 2472 struct iommu_table **ptbl) 2473 { 2474 struct pnv_ioda_pe *pe = container_of(table_group, struct pnv_ioda_pe, 2475 table_group); 2476 int nid = pe->phb->hose->node; 2477 __u64 bus_offset = num ? pe->tce_bypass_base : table_group->tce32_start; 2478 long ret; 2479 struct iommu_table *tbl; 2480 2481 tbl = pnv_pci_table_alloc(nid); 2482 if (!tbl) 2483 return -ENOMEM; 2484 2485 tbl->it_ops = &pnv_ioda2_iommu_ops; 2486 2487 ret = pnv_pci_ioda2_table_alloc_pages(nid, 2488 bus_offset, page_shift, window_size, 2489 levels, tbl); 2490 if (ret) { 2491 iommu_tce_table_put(tbl); 2492 return ret; 2493 } 2494 2495 *ptbl = tbl; 2496 2497 return 0; 2498 } 2499 2500 static long pnv_pci_ioda2_setup_default_config(struct pnv_ioda_pe *pe) 2501 { 2502 struct iommu_table *tbl = NULL; 2503 long rc; 2504 2505 /* 2506 * crashkernel= specifies the kdump kernel's maximum memory at 2507 * some offset and there is no guaranteed the result is a power 2508 * of 2, which will cause errors later. 2509 */ 2510 const u64 max_memory = __rounddown_pow_of_two(memory_hotplug_max()); 2511 2512 /* 2513 * In memory constrained environments, e.g. kdump kernel, the 2514 * DMA window can be larger than available memory, which will 2515 * cause errors later. 2516 */ 2517 const u64 window_size = min((u64)pe->table_group.tce32_size, max_memory); 2518 2519 rc = pnv_pci_ioda2_create_table(&pe->table_group, 0, 2520 IOMMU_PAGE_SHIFT_4K, 2521 window_size, 2522 POWERNV_IOMMU_DEFAULT_LEVELS, &tbl); 2523 if (rc) { 2524 pe_err(pe, "Failed to create 32-bit TCE table, err %ld", 2525 rc); 2526 return rc; 2527 } 2528 2529 iommu_init_table(tbl, pe->phb->hose->node); 2530 2531 rc = pnv_pci_ioda2_set_window(&pe->table_group, 0, tbl); 2532 if (rc) { 2533 pe_err(pe, "Failed to configure 32-bit TCE table, err %ld\n", 2534 rc); 2535 iommu_tce_table_put(tbl); 2536 return rc; 2537 } 2538 2539 if (!pnv_iommu_bypass_disabled) 2540 pnv_pci_ioda2_set_bypass(pe, true); 2541 2542 /* 2543 * Setting table base here only for carrying iommu_group 2544 * further down to let iommu_add_device() do the job. 2545 * pnv_pci_ioda_dma_dev_setup will override it later anyway. 2546 */ 2547 if (pe->flags & PNV_IODA_PE_DEV) 2548 set_iommu_table_base(&pe->pdev->dev, tbl); 2549 2550 return 0; 2551 } 2552 2553 #if defined(CONFIG_IOMMU_API) || defined(CONFIG_PCI_IOV) 2554 static long pnv_pci_ioda2_unset_window(struct iommu_table_group *table_group, 2555 int num) 2556 { 2557 struct pnv_ioda_pe *pe = container_of(table_group, struct pnv_ioda_pe, 2558 table_group); 2559 struct pnv_phb *phb = pe->phb; 2560 long ret; 2561 2562 pe_info(pe, "Removing DMA window #%d\n", num); 2563 2564 ret = opal_pci_map_pe_dma_window(phb->opal_id, pe->pe_number, 2565 (pe->pe_number << 1) + num, 2566 0/* levels */, 0/* table address */, 2567 0/* table size */, 0/* page size */); 2568 if (ret) 2569 pe_warn(pe, "Unmapping failed, ret = %ld\n", ret); 2570 else 2571 pnv_pci_ioda2_tce_invalidate_pe(pe); 2572 2573 pnv_pci_unlink_table_and_group(table_group->tables[num], table_group); 2574 2575 return ret; 2576 } 2577 #endif 2578 2579 #ifdef CONFIG_IOMMU_API 2580 static unsigned long pnv_pci_ioda2_get_table_size(__u32 page_shift, 2581 __u64 window_size, __u32 levels) 2582 { 2583 unsigned long bytes = 0; 2584 const unsigned window_shift = ilog2(window_size); 2585 unsigned entries_shift = window_shift - page_shift; 2586 unsigned table_shift = entries_shift + 3; 2587 unsigned long tce_table_size = max(0x1000UL, 1UL << table_shift); 2588 unsigned long direct_table_size; 2589 2590 if (!levels || (levels > POWERNV_IOMMU_MAX_LEVELS) || 2591 !is_power_of_2(window_size)) 2592 return 0; 2593 2594 /* Calculate a direct table size from window_size and levels */ 2595 entries_shift = (entries_shift + levels - 1) / levels; 2596 table_shift = entries_shift + 3; 2597 table_shift = max_t(unsigned, table_shift, PAGE_SHIFT); 2598 direct_table_size = 1UL << table_shift; 2599 2600 for ( ; levels; --levels) { 2601 bytes += _ALIGN_UP(tce_table_size, direct_table_size); 2602 2603 tce_table_size /= direct_table_size; 2604 tce_table_size <<= 3; 2605 tce_table_size = max_t(unsigned long, 2606 tce_table_size, direct_table_size); 2607 } 2608 2609 return bytes; 2610 } 2611 2612 static void pnv_ioda2_take_ownership(struct iommu_table_group *table_group) 2613 { 2614 struct pnv_ioda_pe *pe = container_of(table_group, struct pnv_ioda_pe, 2615 table_group); 2616 /* Store @tbl as pnv_pci_ioda2_unset_window() resets it */ 2617 struct iommu_table *tbl = pe->table_group.tables[0]; 2618 2619 pnv_pci_ioda2_set_bypass(pe, false); 2620 pnv_pci_ioda2_unset_window(&pe->table_group, 0); 2621 if (pe->pbus) 2622 pnv_ioda_setup_bus_dma(pe, pe->pbus, false); 2623 iommu_tce_table_put(tbl); 2624 } 2625 2626 static void pnv_ioda2_release_ownership(struct iommu_table_group *table_group) 2627 { 2628 struct pnv_ioda_pe *pe = container_of(table_group, struct pnv_ioda_pe, 2629 table_group); 2630 2631 pnv_pci_ioda2_setup_default_config(pe); 2632 if (pe->pbus) 2633 pnv_ioda_setup_bus_dma(pe, pe->pbus, false); 2634 } 2635 2636 static struct iommu_table_group_ops pnv_pci_ioda2_ops = { 2637 .get_table_size = pnv_pci_ioda2_get_table_size, 2638 .create_table = pnv_pci_ioda2_create_table, 2639 .set_window = pnv_pci_ioda2_set_window, 2640 .unset_window = pnv_pci_ioda2_unset_window, 2641 .take_ownership = pnv_ioda2_take_ownership, 2642 .release_ownership = pnv_ioda2_release_ownership, 2643 }; 2644 2645 static int gpe_table_group_to_npe_cb(struct device *dev, void *opaque) 2646 { 2647 struct pci_controller *hose; 2648 struct pnv_phb *phb; 2649 struct pnv_ioda_pe **ptmppe = opaque; 2650 struct pci_dev *pdev = container_of(dev, struct pci_dev, dev); 2651 struct pci_dn *pdn = pci_get_pdn(pdev); 2652 2653 if (!pdn || pdn->pe_number == IODA_INVALID_PE) 2654 return 0; 2655 2656 hose = pci_bus_to_host(pdev->bus); 2657 phb = hose->private_data; 2658 if (phb->type != PNV_PHB_NPU_NVLINK) 2659 return 0; 2660 2661 *ptmppe = &phb->ioda.pe_array[pdn->pe_number]; 2662 2663 return 1; 2664 } 2665 2666 /* 2667 * This returns PE of associated NPU. 2668 * This assumes that NPU is in the same IOMMU group with GPU and there is 2669 * no other PEs. 2670 */ 2671 static struct pnv_ioda_pe *gpe_table_group_to_npe( 2672 struct iommu_table_group *table_group) 2673 { 2674 struct pnv_ioda_pe *npe = NULL; 2675 int ret = iommu_group_for_each_dev(table_group->group, &npe, 2676 gpe_table_group_to_npe_cb); 2677 2678 BUG_ON(!ret || !npe); 2679 2680 return npe; 2681 } 2682 2683 static long pnv_pci_ioda2_npu_set_window(struct iommu_table_group *table_group, 2684 int num, struct iommu_table *tbl) 2685 { 2686 struct pnv_ioda_pe *npe = gpe_table_group_to_npe(table_group); 2687 int num2 = (num == 0) ? 1 : 0; 2688 long ret = pnv_pci_ioda2_set_window(table_group, num, tbl); 2689 2690 if (ret) 2691 return ret; 2692 2693 if (table_group->tables[num2]) 2694 pnv_npu_unset_window(npe, num2); 2695 2696 ret = pnv_npu_set_window(npe, num, tbl); 2697 if (ret) { 2698 pnv_pci_ioda2_unset_window(table_group, num); 2699 if (table_group->tables[num2]) 2700 pnv_npu_set_window(npe, num2, 2701 table_group->tables[num2]); 2702 } 2703 2704 return ret; 2705 } 2706 2707 static long pnv_pci_ioda2_npu_unset_window( 2708 struct iommu_table_group *table_group, 2709 int num) 2710 { 2711 struct pnv_ioda_pe *npe = gpe_table_group_to_npe(table_group); 2712 int num2 = (num == 0) ? 1 : 0; 2713 long ret = pnv_pci_ioda2_unset_window(table_group, num); 2714 2715 if (ret) 2716 return ret; 2717 2718 if (!npe->table_group.tables[num]) 2719 return 0; 2720 2721 ret = pnv_npu_unset_window(npe, num); 2722 if (ret) 2723 return ret; 2724 2725 if (table_group->tables[num2]) 2726 ret = pnv_npu_set_window(npe, num2, table_group->tables[num2]); 2727 2728 return ret; 2729 } 2730 2731 static void pnv_ioda2_npu_take_ownership(struct iommu_table_group *table_group) 2732 { 2733 /* 2734 * Detach NPU first as pnv_ioda2_take_ownership() will destroy 2735 * the iommu_table if 32bit DMA is enabled. 2736 */ 2737 pnv_npu_take_ownership(gpe_table_group_to_npe(table_group)); 2738 pnv_ioda2_take_ownership(table_group); 2739 } 2740 2741 static struct iommu_table_group_ops pnv_pci_ioda2_npu_ops = { 2742 .get_table_size = pnv_pci_ioda2_get_table_size, 2743 .create_table = pnv_pci_ioda2_create_table, 2744 .set_window = pnv_pci_ioda2_npu_set_window, 2745 .unset_window = pnv_pci_ioda2_npu_unset_window, 2746 .take_ownership = pnv_ioda2_npu_take_ownership, 2747 .release_ownership = pnv_ioda2_release_ownership, 2748 }; 2749 2750 static void pnv_pci_ioda_setup_iommu_api(void) 2751 { 2752 struct pci_controller *hose, *tmp; 2753 struct pnv_phb *phb; 2754 struct pnv_ioda_pe *pe, *gpe; 2755 2756 /* 2757 * Now we have all PHBs discovered, time to add NPU devices to 2758 * the corresponding IOMMU groups. 2759 */ 2760 list_for_each_entry_safe(hose, tmp, &hose_list, list_node) { 2761 phb = hose->private_data; 2762 2763 if (phb->type != PNV_PHB_NPU_NVLINK) 2764 continue; 2765 2766 list_for_each_entry(pe, &phb->ioda.pe_list, list) { 2767 gpe = pnv_pci_npu_setup_iommu(pe); 2768 if (gpe) 2769 gpe->table_group.ops = &pnv_pci_ioda2_npu_ops; 2770 } 2771 } 2772 } 2773 #else /* !CONFIG_IOMMU_API */ 2774 static void pnv_pci_ioda_setup_iommu_api(void) { }; 2775 #endif 2776 2777 static __be64 *pnv_pci_ioda2_table_do_alloc_pages(int nid, unsigned shift, 2778 unsigned levels, unsigned long limit, 2779 unsigned long *current_offset, unsigned long *total_allocated) 2780 { 2781 struct page *tce_mem = NULL; 2782 __be64 *addr, *tmp; 2783 unsigned order = max_t(unsigned, shift, PAGE_SHIFT) - PAGE_SHIFT; 2784 unsigned long allocated = 1UL << (order + PAGE_SHIFT); 2785 unsigned entries = 1UL << (shift - 3); 2786 long i; 2787 2788 tce_mem = alloc_pages_node(nid, GFP_KERNEL, order); 2789 if (!tce_mem) { 2790 pr_err("Failed to allocate a TCE memory, order=%d\n", order); 2791 return NULL; 2792 } 2793 addr = page_address(tce_mem); 2794 memset(addr, 0, allocated); 2795 *total_allocated += allocated; 2796 2797 --levels; 2798 if (!levels) { 2799 *current_offset += allocated; 2800 return addr; 2801 } 2802 2803 for (i = 0; i < entries; ++i) { 2804 tmp = pnv_pci_ioda2_table_do_alloc_pages(nid, shift, 2805 levels, limit, current_offset, total_allocated); 2806 if (!tmp) 2807 break; 2808 2809 addr[i] = cpu_to_be64(__pa(tmp) | 2810 TCE_PCI_READ | TCE_PCI_WRITE); 2811 2812 if (*current_offset >= limit) 2813 break; 2814 } 2815 2816 return addr; 2817 } 2818 2819 static void pnv_pci_ioda2_table_do_free_pages(__be64 *addr, 2820 unsigned long size, unsigned level); 2821 2822 static long pnv_pci_ioda2_table_alloc_pages(int nid, __u64 bus_offset, 2823 __u32 page_shift, __u64 window_size, __u32 levels, 2824 struct iommu_table *tbl) 2825 { 2826 void *addr; 2827 unsigned long offset = 0, level_shift, total_allocated = 0; 2828 const unsigned window_shift = ilog2(window_size); 2829 unsigned entries_shift = window_shift - page_shift; 2830 unsigned table_shift = max_t(unsigned, entries_shift + 3, PAGE_SHIFT); 2831 const unsigned long tce_table_size = 1UL << table_shift; 2832 2833 if (!levels || (levels > POWERNV_IOMMU_MAX_LEVELS)) 2834 return -EINVAL; 2835 2836 if (!is_power_of_2(window_size)) 2837 return -EINVAL; 2838 2839 /* Adjust direct table size from window_size and levels */ 2840 entries_shift = (entries_shift + levels - 1) / levels; 2841 level_shift = entries_shift + 3; 2842 level_shift = max_t(unsigned, level_shift, PAGE_SHIFT); 2843 2844 if ((level_shift - 3) * levels + page_shift >= 60) 2845 return -EINVAL; 2846 2847 /* Allocate TCE table */ 2848 addr = pnv_pci_ioda2_table_do_alloc_pages(nid, level_shift, 2849 levels, tce_table_size, &offset, &total_allocated); 2850 2851 /* addr==NULL means that the first level allocation failed */ 2852 if (!addr) 2853 return -ENOMEM; 2854 2855 /* 2856 * First level was allocated but some lower level failed as 2857 * we did not allocate as much as we wanted, 2858 * release partially allocated table. 2859 */ 2860 if (offset < tce_table_size) { 2861 pnv_pci_ioda2_table_do_free_pages(addr, 2862 1ULL << (level_shift - 3), levels - 1); 2863 return -ENOMEM; 2864 } 2865 2866 /* Setup linux iommu table */ 2867 pnv_pci_setup_iommu_table(tbl, addr, tce_table_size, bus_offset, 2868 page_shift); 2869 tbl->it_level_size = 1ULL << (level_shift - 3); 2870 tbl->it_indirect_levels = levels - 1; 2871 tbl->it_allocated_size = total_allocated; 2872 2873 pr_devel("Created TCE table: ws=%08llx ts=%lx @%08llx\n", 2874 window_size, tce_table_size, bus_offset); 2875 2876 return 0; 2877 } 2878 2879 static void pnv_pci_ioda2_table_do_free_pages(__be64 *addr, 2880 unsigned long size, unsigned level) 2881 { 2882 const unsigned long addr_ul = (unsigned long) addr & 2883 ~(TCE_PCI_READ | TCE_PCI_WRITE); 2884 2885 if (level) { 2886 long i; 2887 u64 *tmp = (u64 *) addr_ul; 2888 2889 for (i = 0; i < size; ++i) { 2890 unsigned long hpa = be64_to_cpu(tmp[i]); 2891 2892 if (!(hpa & (TCE_PCI_READ | TCE_PCI_WRITE))) 2893 continue; 2894 2895 pnv_pci_ioda2_table_do_free_pages(__va(hpa), size, 2896 level - 1); 2897 } 2898 } 2899 2900 free_pages(addr_ul, get_order(size << 3)); 2901 } 2902 2903 static void pnv_pci_ioda2_table_free_pages(struct iommu_table *tbl) 2904 { 2905 const unsigned long size = tbl->it_indirect_levels ? 2906 tbl->it_level_size : tbl->it_size; 2907 2908 if (!tbl->it_size) 2909 return; 2910 2911 pnv_pci_ioda2_table_do_free_pages((__be64 *)tbl->it_base, size, 2912 tbl->it_indirect_levels); 2913 } 2914 2915 static unsigned long pnv_ioda_parse_tce_sizes(struct pnv_phb *phb) 2916 { 2917 struct pci_controller *hose = phb->hose; 2918 struct device_node *dn = hose->dn; 2919 unsigned long mask = 0; 2920 int i, rc, count; 2921 u32 val; 2922 2923 count = of_property_count_u32_elems(dn, "ibm,supported-tce-sizes"); 2924 if (count <= 0) { 2925 mask = SZ_4K | SZ_64K; 2926 /* Add 16M for POWER8 by default */ 2927 if (cpu_has_feature(CPU_FTR_ARCH_207S) && 2928 !cpu_has_feature(CPU_FTR_ARCH_300)) 2929 mask |= SZ_16M; 2930 return mask; 2931 } 2932 2933 for (i = 0; i < count; i++) { 2934 rc = of_property_read_u32_index(dn, "ibm,supported-tce-sizes", 2935 i, &val); 2936 if (rc == 0) 2937 mask |= 1ULL << val; 2938 } 2939 2940 return mask; 2941 } 2942 2943 static void pnv_pci_ioda2_setup_dma_pe(struct pnv_phb *phb, 2944 struct pnv_ioda_pe *pe) 2945 { 2946 int64_t rc; 2947 2948 if (!pnv_pci_ioda_pe_dma_weight(pe)) 2949 return; 2950 2951 /* TVE #1 is selected by PCI address bit 59 */ 2952 pe->tce_bypass_base = 1ull << 59; 2953 2954 iommu_register_group(&pe->table_group, phb->hose->global_number, 2955 pe->pe_number); 2956 2957 /* The PE will reserve all possible 32-bits space */ 2958 pe_info(pe, "Setting up 32-bit TCE table at 0..%08x\n", 2959 phb->ioda.m32_pci_base); 2960 2961 /* Setup linux iommu table */ 2962 pe->table_group.tce32_start = 0; 2963 pe->table_group.tce32_size = phb->ioda.m32_pci_base; 2964 pe->table_group.max_dynamic_windows_supported = 2965 IOMMU_TABLE_GROUP_MAX_TABLES; 2966 pe->table_group.max_levels = POWERNV_IOMMU_MAX_LEVELS; 2967 pe->table_group.pgsizes = pnv_ioda_parse_tce_sizes(phb); 2968 #ifdef CONFIG_IOMMU_API 2969 pe->table_group.ops = &pnv_pci_ioda2_ops; 2970 #endif 2971 2972 rc = pnv_pci_ioda2_setup_default_config(pe); 2973 if (rc) 2974 return; 2975 2976 if (pe->flags & (PNV_IODA_PE_BUS | PNV_IODA_PE_BUS_ALL)) 2977 pnv_ioda_setup_bus_dma(pe, pe->pbus, true); 2978 } 2979 2980 #ifdef CONFIG_PCI_MSI 2981 int64_t pnv_opal_pci_msi_eoi(struct irq_chip *chip, unsigned int hw_irq) 2982 { 2983 struct pnv_phb *phb = container_of(chip, struct pnv_phb, 2984 ioda.irq_chip); 2985 2986 return opal_pci_msi_eoi(phb->opal_id, hw_irq); 2987 } 2988 2989 static void pnv_ioda2_msi_eoi(struct irq_data *d) 2990 { 2991 int64_t rc; 2992 unsigned int hw_irq = (unsigned int)irqd_to_hwirq(d); 2993 struct irq_chip *chip = irq_data_get_irq_chip(d); 2994 2995 rc = pnv_opal_pci_msi_eoi(chip, hw_irq); 2996 WARN_ON_ONCE(rc); 2997 2998 icp_native_eoi(d); 2999 } 3000 3001 3002 void pnv_set_msi_irq_chip(struct pnv_phb *phb, unsigned int virq) 3003 { 3004 struct irq_data *idata; 3005 struct irq_chip *ichip; 3006 3007 /* The MSI EOI OPAL call is only needed on PHB3 */ 3008 if (phb->model != PNV_PHB_MODEL_PHB3) 3009 return; 3010 3011 if (!phb->ioda.irq_chip_init) { 3012 /* 3013 * First time we setup an MSI IRQ, we need to setup the 3014 * corresponding IRQ chip to route correctly. 3015 */ 3016 idata = irq_get_irq_data(virq); 3017 ichip = irq_data_get_irq_chip(idata); 3018 phb->ioda.irq_chip_init = 1; 3019 phb->ioda.irq_chip = *ichip; 3020 phb->ioda.irq_chip.irq_eoi = pnv_ioda2_msi_eoi; 3021 } 3022 irq_set_chip(virq, &phb->ioda.irq_chip); 3023 } 3024 3025 /* 3026 * Returns true iff chip is something that we could call 3027 * pnv_opal_pci_msi_eoi for. 3028 */ 3029 bool is_pnv_opal_msi(struct irq_chip *chip) 3030 { 3031 return chip->irq_eoi == pnv_ioda2_msi_eoi; 3032 } 3033 EXPORT_SYMBOL_GPL(is_pnv_opal_msi); 3034 3035 static int pnv_pci_ioda_msi_setup(struct pnv_phb *phb, struct pci_dev *dev, 3036 unsigned int hwirq, unsigned int virq, 3037 unsigned int is_64, struct msi_msg *msg) 3038 { 3039 struct pnv_ioda_pe *pe = pnv_ioda_get_pe(dev); 3040 unsigned int xive_num = hwirq - phb->msi_base; 3041 __be32 data; 3042 int rc; 3043 3044 /* No PE assigned ? bail out ... no MSI for you ! */ 3045 if (pe == NULL) 3046 return -ENXIO; 3047 3048 /* Check if we have an MVE */ 3049 if (pe->mve_number < 0) 3050 return -ENXIO; 3051 3052 /* Force 32-bit MSI on some broken devices */ 3053 if (dev->no_64bit_msi) 3054 is_64 = 0; 3055 3056 /* Assign XIVE to PE */ 3057 rc = opal_pci_set_xive_pe(phb->opal_id, pe->pe_number, xive_num); 3058 if (rc) { 3059 pr_warn("%s: OPAL error %d setting XIVE %d PE\n", 3060 pci_name(dev), rc, xive_num); 3061 return -EIO; 3062 } 3063 3064 if (is_64) { 3065 __be64 addr64; 3066 3067 rc = opal_get_msi_64(phb->opal_id, pe->mve_number, xive_num, 1, 3068 &addr64, &data); 3069 if (rc) { 3070 pr_warn("%s: OPAL error %d getting 64-bit MSI data\n", 3071 pci_name(dev), rc); 3072 return -EIO; 3073 } 3074 msg->address_hi = be64_to_cpu(addr64) >> 32; 3075 msg->address_lo = be64_to_cpu(addr64) & 0xfffffffful; 3076 } else { 3077 __be32 addr32; 3078 3079 rc = opal_get_msi_32(phb->opal_id, pe->mve_number, xive_num, 1, 3080 &addr32, &data); 3081 if (rc) { 3082 pr_warn("%s: OPAL error %d getting 32-bit MSI data\n", 3083 pci_name(dev), rc); 3084 return -EIO; 3085 } 3086 msg->address_hi = 0; 3087 msg->address_lo = be32_to_cpu(addr32); 3088 } 3089 msg->data = be32_to_cpu(data); 3090 3091 pnv_set_msi_irq_chip(phb, virq); 3092 3093 pr_devel("%s: %s-bit MSI on hwirq %x (xive #%d)," 3094 " address=%x_%08x data=%x PE# %x\n", 3095 pci_name(dev), is_64 ? "64" : "32", hwirq, xive_num, 3096 msg->address_hi, msg->address_lo, data, pe->pe_number); 3097 3098 return 0; 3099 } 3100 3101 static void pnv_pci_init_ioda_msis(struct pnv_phb *phb) 3102 { 3103 unsigned int count; 3104 const __be32 *prop = of_get_property(phb->hose->dn, 3105 "ibm,opal-msi-ranges", NULL); 3106 if (!prop) { 3107 /* BML Fallback */ 3108 prop = of_get_property(phb->hose->dn, "msi-ranges", NULL); 3109 } 3110 if (!prop) 3111 return; 3112 3113 phb->msi_base = be32_to_cpup(prop); 3114 count = be32_to_cpup(prop + 1); 3115 if (msi_bitmap_alloc(&phb->msi_bmp, count, phb->hose->dn)) { 3116 pr_err("PCI %d: Failed to allocate MSI bitmap !\n", 3117 phb->hose->global_number); 3118 return; 3119 } 3120 3121 phb->msi_setup = pnv_pci_ioda_msi_setup; 3122 phb->msi32_support = 1; 3123 pr_info(" Allocated bitmap for %d MSIs (base IRQ 0x%x)\n", 3124 count, phb->msi_base); 3125 } 3126 #else 3127 static void pnv_pci_init_ioda_msis(struct pnv_phb *phb) { } 3128 #endif /* CONFIG_PCI_MSI */ 3129 3130 #ifdef CONFIG_PCI_IOV 3131 static void pnv_pci_ioda_fixup_iov_resources(struct pci_dev *pdev) 3132 { 3133 struct pci_controller *hose = pci_bus_to_host(pdev->bus); 3134 struct pnv_phb *phb = hose->private_data; 3135 const resource_size_t gate = phb->ioda.m64_segsize >> 2; 3136 struct resource *res; 3137 int i; 3138 resource_size_t size, total_vf_bar_sz; 3139 struct pci_dn *pdn; 3140 int mul, total_vfs; 3141 3142 if (!pdev->is_physfn || pci_dev_is_added(pdev)) 3143 return; 3144 3145 pdn = pci_get_pdn(pdev); 3146 pdn->vfs_expanded = 0; 3147 pdn->m64_single_mode = false; 3148 3149 total_vfs = pci_sriov_get_totalvfs(pdev); 3150 mul = phb->ioda.total_pe_num; 3151 total_vf_bar_sz = 0; 3152 3153 for (i = 0; i < PCI_SRIOV_NUM_BARS; i++) { 3154 res = &pdev->resource[i + PCI_IOV_RESOURCES]; 3155 if (!res->flags || res->parent) 3156 continue; 3157 if (!pnv_pci_is_m64_flags(res->flags)) { 3158 dev_warn(&pdev->dev, "Don't support SR-IOV with" 3159 " non M64 VF BAR%d: %pR. \n", 3160 i, res); 3161 goto truncate_iov; 3162 } 3163 3164 total_vf_bar_sz += pci_iov_resource_size(pdev, 3165 i + PCI_IOV_RESOURCES); 3166 3167 /* 3168 * If bigger than quarter of M64 segment size, just round up 3169 * power of two. 3170 * 3171 * Generally, one M64 BAR maps one IOV BAR. To avoid conflict 3172 * with other devices, IOV BAR size is expanded to be 3173 * (total_pe * VF_BAR_size). When VF_BAR_size is half of M64 3174 * segment size , the expanded size would equal to half of the 3175 * whole M64 space size, which will exhaust the M64 Space and 3176 * limit the system flexibility. This is a design decision to 3177 * set the boundary to quarter of the M64 segment size. 3178 */ 3179 if (total_vf_bar_sz > gate) { 3180 mul = roundup_pow_of_two(total_vfs); 3181 dev_info(&pdev->dev, 3182 "VF BAR Total IOV size %llx > %llx, roundup to %d VFs\n", 3183 total_vf_bar_sz, gate, mul); 3184 pdn->m64_single_mode = true; 3185 break; 3186 } 3187 } 3188 3189 for (i = 0; i < PCI_SRIOV_NUM_BARS; i++) { 3190 res = &pdev->resource[i + PCI_IOV_RESOURCES]; 3191 if (!res->flags || res->parent) 3192 continue; 3193 3194 size = pci_iov_resource_size(pdev, i + PCI_IOV_RESOURCES); 3195 /* 3196 * On PHB3, the minimum size alignment of M64 BAR in single 3197 * mode is 32MB. 3198 */ 3199 if (pdn->m64_single_mode && (size < SZ_32M)) 3200 goto truncate_iov; 3201 dev_dbg(&pdev->dev, " Fixing VF BAR%d: %pR to\n", i, res); 3202 res->end = res->start + size * mul - 1; 3203 dev_dbg(&pdev->dev, " %pR\n", res); 3204 dev_info(&pdev->dev, "VF BAR%d: %pR (expanded to %d VFs for PE alignment)", 3205 i, res, mul); 3206 } 3207 pdn->vfs_expanded = mul; 3208 3209 return; 3210 3211 truncate_iov: 3212 /* To save MMIO space, IOV BAR is truncated. */ 3213 for (i = 0; i < PCI_SRIOV_NUM_BARS; i++) { 3214 res = &pdev->resource[i + PCI_IOV_RESOURCES]; 3215 res->flags = 0; 3216 res->end = res->start - 1; 3217 } 3218 } 3219 #endif /* CONFIG_PCI_IOV */ 3220 3221 static void pnv_ioda_setup_pe_res(struct pnv_ioda_pe *pe, 3222 struct resource *res) 3223 { 3224 struct pnv_phb *phb = pe->phb; 3225 struct pci_bus_region region; 3226 int index; 3227 int64_t rc; 3228 3229 if (!res || !res->flags || res->start > res->end) 3230 return; 3231 3232 if (res->flags & IORESOURCE_IO) { 3233 region.start = res->start - phb->ioda.io_pci_base; 3234 region.end = res->end - phb->ioda.io_pci_base; 3235 index = region.start / phb->ioda.io_segsize; 3236 3237 while (index < phb->ioda.total_pe_num && 3238 region.start <= region.end) { 3239 phb->ioda.io_segmap[index] = pe->pe_number; 3240 rc = opal_pci_map_pe_mmio_window(phb->opal_id, 3241 pe->pe_number, OPAL_IO_WINDOW_TYPE, 0, index); 3242 if (rc != OPAL_SUCCESS) { 3243 pr_err("%s: Error %lld mapping IO segment#%d to PE#%x\n", 3244 __func__, rc, index, pe->pe_number); 3245 break; 3246 } 3247 3248 region.start += phb->ioda.io_segsize; 3249 index++; 3250 } 3251 } else if ((res->flags & IORESOURCE_MEM) && 3252 !pnv_pci_is_m64(phb, res)) { 3253 region.start = res->start - 3254 phb->hose->mem_offset[0] - 3255 phb->ioda.m32_pci_base; 3256 region.end = res->end - 3257 phb->hose->mem_offset[0] - 3258 phb->ioda.m32_pci_base; 3259 index = region.start / phb->ioda.m32_segsize; 3260 3261 while (index < phb->ioda.total_pe_num && 3262 region.start <= region.end) { 3263 phb->ioda.m32_segmap[index] = pe->pe_number; 3264 rc = opal_pci_map_pe_mmio_window(phb->opal_id, 3265 pe->pe_number, OPAL_M32_WINDOW_TYPE, 0, index); 3266 if (rc != OPAL_SUCCESS) { 3267 pr_err("%s: Error %lld mapping M32 segment#%d to PE#%x", 3268 __func__, rc, index, pe->pe_number); 3269 break; 3270 } 3271 3272 region.start += phb->ioda.m32_segsize; 3273 index++; 3274 } 3275 } 3276 } 3277 3278 /* 3279 * This function is supposed to be called on basis of PE from top 3280 * to bottom style. So the the I/O or MMIO segment assigned to 3281 * parent PE could be overridden by its child PEs if necessary. 3282 */ 3283 static void pnv_ioda_setup_pe_seg(struct pnv_ioda_pe *pe) 3284 { 3285 struct pci_dev *pdev; 3286 int i; 3287 3288 /* 3289 * NOTE: We only care PCI bus based PE for now. For PCI 3290 * device based PE, for example SRIOV sensitive VF should 3291 * be figured out later. 3292 */ 3293 BUG_ON(!(pe->flags & (PNV_IODA_PE_BUS | PNV_IODA_PE_BUS_ALL))); 3294 3295 list_for_each_entry(pdev, &pe->pbus->devices, bus_list) { 3296 for (i = 0; i <= PCI_ROM_RESOURCE; i++) 3297 pnv_ioda_setup_pe_res(pe, &pdev->resource[i]); 3298 3299 /* 3300 * If the PE contains all subordinate PCI buses, the 3301 * windows of the child bridges should be mapped to 3302 * the PE as well. 3303 */ 3304 if (!(pe->flags & PNV_IODA_PE_BUS_ALL) || !pci_is_bridge(pdev)) 3305 continue; 3306 for (i = 0; i < PCI_BRIDGE_RESOURCE_NUM; i++) 3307 pnv_ioda_setup_pe_res(pe, 3308 &pdev->resource[PCI_BRIDGE_RESOURCES + i]); 3309 } 3310 } 3311 3312 #ifdef CONFIG_DEBUG_FS 3313 static int pnv_pci_diag_data_set(void *data, u64 val) 3314 { 3315 struct pci_controller *hose; 3316 struct pnv_phb *phb; 3317 s64 ret; 3318 3319 if (val != 1ULL) 3320 return -EINVAL; 3321 3322 hose = (struct pci_controller *)data; 3323 if (!hose || !hose->private_data) 3324 return -ENODEV; 3325 3326 phb = hose->private_data; 3327 3328 /* Retrieve the diag data from firmware */ 3329 ret = opal_pci_get_phb_diag_data2(phb->opal_id, phb->diag_data, 3330 phb->diag_data_size); 3331 if (ret != OPAL_SUCCESS) 3332 return -EIO; 3333 3334 /* Print the diag data to the kernel log */ 3335 pnv_pci_dump_phb_diag_data(phb->hose, phb->diag_data); 3336 return 0; 3337 } 3338 3339 DEFINE_SIMPLE_ATTRIBUTE(pnv_pci_diag_data_fops, NULL, 3340 pnv_pci_diag_data_set, "%llu\n"); 3341 3342 #endif /* CONFIG_DEBUG_FS */ 3343 3344 static void pnv_pci_ioda_create_dbgfs(void) 3345 { 3346 #ifdef CONFIG_DEBUG_FS 3347 struct pci_controller *hose, *tmp; 3348 struct pnv_phb *phb; 3349 char name[16]; 3350 3351 list_for_each_entry_safe(hose, tmp, &hose_list, list_node) { 3352 phb = hose->private_data; 3353 3354 /* Notify initialization of PHB done */ 3355 phb->initialized = 1; 3356 3357 sprintf(name, "PCI%04x", hose->global_number); 3358 phb->dbgfs = debugfs_create_dir(name, powerpc_debugfs_root); 3359 if (!phb->dbgfs) { 3360 pr_warn("%s: Error on creating debugfs on PHB#%x\n", 3361 __func__, hose->global_number); 3362 continue; 3363 } 3364 3365 debugfs_create_file("dump_diag_regs", 0200, phb->dbgfs, hose, 3366 &pnv_pci_diag_data_fops); 3367 } 3368 #endif /* CONFIG_DEBUG_FS */ 3369 } 3370 3371 static void pnv_pci_ioda_fixup(void) 3372 { 3373 pnv_pci_ioda_setup_PEs(); 3374 pnv_pci_ioda_setup_iommu_api(); 3375 pnv_pci_ioda_create_dbgfs(); 3376 3377 #ifdef CONFIG_EEH 3378 pnv_eeh_post_init(); 3379 #endif 3380 } 3381 3382 /* 3383 * Returns the alignment for I/O or memory windows for P2P 3384 * bridges. That actually depends on how PEs are segmented. 3385 * For now, we return I/O or M32 segment size for PE sensitive 3386 * P2P bridges. Otherwise, the default values (4KiB for I/O, 3387 * 1MiB for memory) will be returned. 3388 * 3389 * The current PCI bus might be put into one PE, which was 3390 * create against the parent PCI bridge. For that case, we 3391 * needn't enlarge the alignment so that we can save some 3392 * resources. 3393 */ 3394 static resource_size_t pnv_pci_window_alignment(struct pci_bus *bus, 3395 unsigned long type) 3396 { 3397 struct pci_dev *bridge; 3398 struct pci_controller *hose = pci_bus_to_host(bus); 3399 struct pnv_phb *phb = hose->private_data; 3400 int num_pci_bridges = 0; 3401 3402 bridge = bus->self; 3403 while (bridge) { 3404 if (pci_pcie_type(bridge) == PCI_EXP_TYPE_PCI_BRIDGE) { 3405 num_pci_bridges++; 3406 if (num_pci_bridges >= 2) 3407 return 1; 3408 } 3409 3410 bridge = bridge->bus->self; 3411 } 3412 3413 /* 3414 * We fall back to M32 if M64 isn't supported. We enforce the M64 3415 * alignment for any 64-bit resource, PCIe doesn't care and 3416 * bridges only do 64-bit prefetchable anyway. 3417 */ 3418 if (phb->ioda.m64_segsize && pnv_pci_is_m64_flags(type)) 3419 return phb->ioda.m64_segsize; 3420 if (type & IORESOURCE_MEM) 3421 return phb->ioda.m32_segsize; 3422 3423 return phb->ioda.io_segsize; 3424 } 3425 3426 /* 3427 * We are updating root port or the upstream port of the 3428 * bridge behind the root port with PHB's windows in order 3429 * to accommodate the changes on required resources during 3430 * PCI (slot) hotplug, which is connected to either root 3431 * port or the downstream ports of PCIe switch behind the 3432 * root port. 3433 */ 3434 static void pnv_pci_fixup_bridge_resources(struct pci_bus *bus, 3435 unsigned long type) 3436 { 3437 struct pci_controller *hose = pci_bus_to_host(bus); 3438 struct pnv_phb *phb = hose->private_data; 3439 struct pci_dev *bridge = bus->self; 3440 struct resource *r, *w; 3441 bool msi_region = false; 3442 int i; 3443 3444 /* Check if we need apply fixup to the bridge's windows */ 3445 if (!pci_is_root_bus(bridge->bus) && 3446 !pci_is_root_bus(bridge->bus->self->bus)) 3447 return; 3448 3449 /* Fixup the resources */ 3450 for (i = 0; i < PCI_BRIDGE_RESOURCE_NUM; i++) { 3451 r = &bridge->resource[PCI_BRIDGE_RESOURCES + i]; 3452 if (!r->flags || !r->parent) 3453 continue; 3454 3455 w = NULL; 3456 if (r->flags & type & IORESOURCE_IO) 3457 w = &hose->io_resource; 3458 else if (pnv_pci_is_m64(phb, r) && 3459 (type & IORESOURCE_PREFETCH) && 3460 phb->ioda.m64_segsize) 3461 w = &hose->mem_resources[1]; 3462 else if (r->flags & type & IORESOURCE_MEM) { 3463 w = &hose->mem_resources[0]; 3464 msi_region = true; 3465 } 3466 3467 r->start = w->start; 3468 r->end = w->end; 3469 3470 /* The 64KB 32-bits MSI region shouldn't be included in 3471 * the 32-bits bridge window. Otherwise, we can see strange 3472 * issues. One of them is EEH error observed on Garrison. 3473 * 3474 * Exclude top 1MB region which is the minimal alignment of 3475 * 32-bits bridge window. 3476 */ 3477 if (msi_region) { 3478 r->end += 0x10000; 3479 r->end -= 0x100000; 3480 } 3481 } 3482 } 3483 3484 static void pnv_pci_setup_bridge(struct pci_bus *bus, unsigned long type) 3485 { 3486 struct pci_controller *hose = pci_bus_to_host(bus); 3487 struct pnv_phb *phb = hose->private_data; 3488 struct pci_dev *bridge = bus->self; 3489 struct pnv_ioda_pe *pe; 3490 bool all = (pci_pcie_type(bridge) == PCI_EXP_TYPE_PCI_BRIDGE); 3491 3492 /* Extend bridge's windows if necessary */ 3493 pnv_pci_fixup_bridge_resources(bus, type); 3494 3495 /* The PE for root bus should be realized before any one else */ 3496 if (!phb->ioda.root_pe_populated) { 3497 pe = pnv_ioda_setup_bus_PE(phb->hose->bus, false); 3498 if (pe) { 3499 phb->ioda.root_pe_idx = pe->pe_number; 3500 phb->ioda.root_pe_populated = true; 3501 } 3502 } 3503 3504 /* Don't assign PE to PCI bus, which doesn't have subordinate devices */ 3505 if (list_empty(&bus->devices)) 3506 return; 3507 3508 /* Reserve PEs according to used M64 resources */ 3509 if (phb->reserve_m64_pe) 3510 phb->reserve_m64_pe(bus, NULL, all); 3511 3512 /* 3513 * Assign PE. We might run here because of partial hotplug. 3514 * For the case, we just pick up the existing PE and should 3515 * not allocate resources again. 3516 */ 3517 pe = pnv_ioda_setup_bus_PE(bus, all); 3518 if (!pe) 3519 return; 3520 3521 pnv_ioda_setup_pe_seg(pe); 3522 switch (phb->type) { 3523 case PNV_PHB_IODA1: 3524 pnv_pci_ioda1_setup_dma_pe(phb, pe); 3525 break; 3526 case PNV_PHB_IODA2: 3527 pnv_pci_ioda2_setup_dma_pe(phb, pe); 3528 break; 3529 default: 3530 pr_warn("%s: No DMA for PHB#%x (type %d)\n", 3531 __func__, phb->hose->global_number, phb->type); 3532 } 3533 } 3534 3535 static resource_size_t pnv_pci_default_alignment(void) 3536 { 3537 return PAGE_SIZE; 3538 } 3539 3540 #ifdef CONFIG_PCI_IOV 3541 static resource_size_t pnv_pci_iov_resource_alignment(struct pci_dev *pdev, 3542 int resno) 3543 { 3544 struct pci_controller *hose = pci_bus_to_host(pdev->bus); 3545 struct pnv_phb *phb = hose->private_data; 3546 struct pci_dn *pdn = pci_get_pdn(pdev); 3547 resource_size_t align; 3548 3549 /* 3550 * On PowerNV platform, IOV BAR is mapped by M64 BAR to enable the 3551 * SR-IOV. While from hardware perspective, the range mapped by M64 3552 * BAR should be size aligned. 3553 * 3554 * When IOV BAR is mapped with M64 BAR in Single PE mode, the extra 3555 * powernv-specific hardware restriction is gone. But if just use the 3556 * VF BAR size as the alignment, PF BAR / VF BAR may be allocated with 3557 * in one segment of M64 #15, which introduces the PE conflict between 3558 * PF and VF. Based on this, the minimum alignment of an IOV BAR is 3559 * m64_segsize. 3560 * 3561 * This function returns the total IOV BAR size if M64 BAR is in 3562 * Shared PE mode or just VF BAR size if not. 3563 * If the M64 BAR is in Single PE mode, return the VF BAR size or 3564 * M64 segment size if IOV BAR size is less. 3565 */ 3566 align = pci_iov_resource_size(pdev, resno); 3567 if (!pdn->vfs_expanded) 3568 return align; 3569 if (pdn->m64_single_mode) 3570 return max(align, (resource_size_t)phb->ioda.m64_segsize); 3571 3572 return pdn->vfs_expanded * align; 3573 } 3574 #endif /* CONFIG_PCI_IOV */ 3575 3576 /* Prevent enabling devices for which we couldn't properly 3577 * assign a PE 3578 */ 3579 bool pnv_pci_enable_device_hook(struct pci_dev *dev) 3580 { 3581 struct pci_controller *hose = pci_bus_to_host(dev->bus); 3582 struct pnv_phb *phb = hose->private_data; 3583 struct pci_dn *pdn; 3584 3585 /* The function is probably called while the PEs have 3586 * not be created yet. For example, resource reassignment 3587 * during PCI probe period. We just skip the check if 3588 * PEs isn't ready. 3589 */ 3590 if (!phb->initialized) 3591 return true; 3592 3593 pdn = pci_get_pdn(dev); 3594 if (!pdn || pdn->pe_number == IODA_INVALID_PE) 3595 return false; 3596 3597 return true; 3598 } 3599 3600 static long pnv_pci_ioda1_unset_window(struct iommu_table_group *table_group, 3601 int num) 3602 { 3603 struct pnv_ioda_pe *pe = container_of(table_group, 3604 struct pnv_ioda_pe, table_group); 3605 struct pnv_phb *phb = pe->phb; 3606 unsigned int idx; 3607 long rc; 3608 3609 pe_info(pe, "Removing DMA window #%d\n", num); 3610 for (idx = 0; idx < phb->ioda.dma32_count; idx++) { 3611 if (phb->ioda.dma32_segmap[idx] != pe->pe_number) 3612 continue; 3613 3614 rc = opal_pci_map_pe_dma_window(phb->opal_id, pe->pe_number, 3615 idx, 0, 0ul, 0ul, 0ul); 3616 if (rc != OPAL_SUCCESS) { 3617 pe_warn(pe, "Failure %ld unmapping DMA32 segment#%d\n", 3618 rc, idx); 3619 return rc; 3620 } 3621 3622 phb->ioda.dma32_segmap[idx] = IODA_INVALID_PE; 3623 } 3624 3625 pnv_pci_unlink_table_and_group(table_group->tables[num], table_group); 3626 return OPAL_SUCCESS; 3627 } 3628 3629 static void pnv_pci_ioda1_release_pe_dma(struct pnv_ioda_pe *pe) 3630 { 3631 unsigned int weight = pnv_pci_ioda_pe_dma_weight(pe); 3632 struct iommu_table *tbl = pe->table_group.tables[0]; 3633 int64_t rc; 3634 3635 if (!weight) 3636 return; 3637 3638 rc = pnv_pci_ioda1_unset_window(&pe->table_group, 0); 3639 if (rc != OPAL_SUCCESS) 3640 return; 3641 3642 pnv_pci_p7ioc_tce_invalidate(tbl, tbl->it_offset, tbl->it_size, false); 3643 if (pe->table_group.group) { 3644 iommu_group_put(pe->table_group.group); 3645 WARN_ON(pe->table_group.group); 3646 } 3647 3648 free_pages(tbl->it_base, get_order(tbl->it_size << 3)); 3649 iommu_tce_table_put(tbl); 3650 } 3651 3652 static void pnv_pci_ioda2_release_pe_dma(struct pnv_ioda_pe *pe) 3653 { 3654 struct iommu_table *tbl = pe->table_group.tables[0]; 3655 unsigned int weight = pnv_pci_ioda_pe_dma_weight(pe); 3656 #ifdef CONFIG_IOMMU_API 3657 int64_t rc; 3658 #endif 3659 3660 if (!weight) 3661 return; 3662 3663 #ifdef CONFIG_IOMMU_API 3664 rc = pnv_pci_ioda2_unset_window(&pe->table_group, 0); 3665 if (rc) 3666 pe_warn(pe, "OPAL error %ld release DMA window\n", rc); 3667 #endif 3668 3669 pnv_pci_ioda2_set_bypass(pe, false); 3670 if (pe->table_group.group) { 3671 iommu_group_put(pe->table_group.group); 3672 WARN_ON(pe->table_group.group); 3673 } 3674 3675 iommu_tce_table_put(tbl); 3676 } 3677 3678 static void pnv_ioda_free_pe_seg(struct pnv_ioda_pe *pe, 3679 unsigned short win, 3680 unsigned int *map) 3681 { 3682 struct pnv_phb *phb = pe->phb; 3683 int idx; 3684 int64_t rc; 3685 3686 for (idx = 0; idx < phb->ioda.total_pe_num; idx++) { 3687 if (map[idx] != pe->pe_number) 3688 continue; 3689 3690 if (win == OPAL_M64_WINDOW_TYPE) 3691 rc = opal_pci_map_pe_mmio_window(phb->opal_id, 3692 phb->ioda.reserved_pe_idx, win, 3693 idx / PNV_IODA1_M64_SEGS, 3694 idx % PNV_IODA1_M64_SEGS); 3695 else 3696 rc = opal_pci_map_pe_mmio_window(phb->opal_id, 3697 phb->ioda.reserved_pe_idx, win, 0, idx); 3698 3699 if (rc != OPAL_SUCCESS) 3700 pe_warn(pe, "Error %ld unmapping (%d) segment#%d\n", 3701 rc, win, idx); 3702 3703 map[idx] = IODA_INVALID_PE; 3704 } 3705 } 3706 3707 static void pnv_ioda_release_pe_seg(struct pnv_ioda_pe *pe) 3708 { 3709 struct pnv_phb *phb = pe->phb; 3710 3711 if (phb->type == PNV_PHB_IODA1) { 3712 pnv_ioda_free_pe_seg(pe, OPAL_IO_WINDOW_TYPE, 3713 phb->ioda.io_segmap); 3714 pnv_ioda_free_pe_seg(pe, OPAL_M32_WINDOW_TYPE, 3715 phb->ioda.m32_segmap); 3716 pnv_ioda_free_pe_seg(pe, OPAL_M64_WINDOW_TYPE, 3717 phb->ioda.m64_segmap); 3718 } else if (phb->type == PNV_PHB_IODA2) { 3719 pnv_ioda_free_pe_seg(pe, OPAL_M32_WINDOW_TYPE, 3720 phb->ioda.m32_segmap); 3721 } 3722 } 3723 3724 static void pnv_ioda_release_pe(struct pnv_ioda_pe *pe) 3725 { 3726 struct pnv_phb *phb = pe->phb; 3727 struct pnv_ioda_pe *slave, *tmp; 3728 3729 list_del(&pe->list); 3730 switch (phb->type) { 3731 case PNV_PHB_IODA1: 3732 pnv_pci_ioda1_release_pe_dma(pe); 3733 break; 3734 case PNV_PHB_IODA2: 3735 pnv_pci_ioda2_release_pe_dma(pe); 3736 break; 3737 default: 3738 WARN_ON(1); 3739 } 3740 3741 pnv_ioda_release_pe_seg(pe); 3742 pnv_ioda_deconfigure_pe(pe->phb, pe); 3743 3744 /* Release slave PEs in the compound PE */ 3745 if (pe->flags & PNV_IODA_PE_MASTER) { 3746 list_for_each_entry_safe(slave, tmp, &pe->slaves, list) { 3747 list_del(&slave->list); 3748 pnv_ioda_free_pe(slave); 3749 } 3750 } 3751 3752 /* 3753 * The PE for root bus can be removed because of hotplug in EEH 3754 * recovery for fenced PHB error. We need to mark the PE dead so 3755 * that it can be populated again in PCI hot add path. The PE 3756 * shouldn't be destroyed as it's the global reserved resource. 3757 */ 3758 if (phb->ioda.root_pe_populated && 3759 phb->ioda.root_pe_idx == pe->pe_number) 3760 phb->ioda.root_pe_populated = false; 3761 else 3762 pnv_ioda_free_pe(pe); 3763 } 3764 3765 static void pnv_pci_release_device(struct pci_dev *pdev) 3766 { 3767 struct pci_controller *hose = pci_bus_to_host(pdev->bus); 3768 struct pnv_phb *phb = hose->private_data; 3769 struct pci_dn *pdn = pci_get_pdn(pdev); 3770 struct pnv_ioda_pe *pe; 3771 3772 if (pdev->is_virtfn) 3773 return; 3774 3775 if (!pdn || pdn->pe_number == IODA_INVALID_PE) 3776 return; 3777 3778 /* 3779 * PCI hotplug can happen as part of EEH error recovery. The @pdn 3780 * isn't removed and added afterwards in this scenario. We should 3781 * set the PE number in @pdn to an invalid one. Otherwise, the PE's 3782 * device count is decreased on removing devices while failing to 3783 * be increased on adding devices. It leads to unbalanced PE's device 3784 * count and eventually make normal PCI hotplug path broken. 3785 */ 3786 pe = &phb->ioda.pe_array[pdn->pe_number]; 3787 pdn->pe_number = IODA_INVALID_PE; 3788 3789 WARN_ON(--pe->device_count < 0); 3790 if (pe->device_count == 0) 3791 pnv_ioda_release_pe(pe); 3792 } 3793 3794 static void pnv_pci_ioda_shutdown(struct pci_controller *hose) 3795 { 3796 struct pnv_phb *phb = hose->private_data; 3797 3798 opal_pci_reset(phb->opal_id, OPAL_RESET_PCI_IODA_TABLE, 3799 OPAL_ASSERT_RESET); 3800 } 3801 3802 static const struct pci_controller_ops pnv_pci_ioda_controller_ops = { 3803 .dma_dev_setup = pnv_pci_dma_dev_setup, 3804 .dma_bus_setup = pnv_pci_dma_bus_setup, 3805 #ifdef CONFIG_PCI_MSI 3806 .setup_msi_irqs = pnv_setup_msi_irqs, 3807 .teardown_msi_irqs = pnv_teardown_msi_irqs, 3808 #endif 3809 .enable_device_hook = pnv_pci_enable_device_hook, 3810 .release_device = pnv_pci_release_device, 3811 .window_alignment = pnv_pci_window_alignment, 3812 .setup_bridge = pnv_pci_setup_bridge, 3813 .reset_secondary_bus = pnv_pci_reset_secondary_bus, 3814 .dma_set_mask = pnv_pci_ioda_dma_set_mask, 3815 .dma_get_required_mask = pnv_pci_ioda_dma_get_required_mask, 3816 .shutdown = pnv_pci_ioda_shutdown, 3817 }; 3818 3819 static int pnv_npu_dma_set_mask(struct pci_dev *npdev, u64 dma_mask) 3820 { 3821 dev_err_once(&npdev->dev, 3822 "%s operation unsupported for NVLink devices\n", 3823 __func__); 3824 return -EPERM; 3825 } 3826 3827 static const struct pci_controller_ops pnv_npu_ioda_controller_ops = { 3828 .dma_dev_setup = pnv_pci_dma_dev_setup, 3829 #ifdef CONFIG_PCI_MSI 3830 .setup_msi_irqs = pnv_setup_msi_irqs, 3831 .teardown_msi_irqs = pnv_teardown_msi_irqs, 3832 #endif 3833 .enable_device_hook = pnv_pci_enable_device_hook, 3834 .window_alignment = pnv_pci_window_alignment, 3835 .reset_secondary_bus = pnv_pci_reset_secondary_bus, 3836 .dma_set_mask = pnv_npu_dma_set_mask, 3837 .shutdown = pnv_pci_ioda_shutdown, 3838 }; 3839 3840 static const struct pci_controller_ops pnv_npu_ocapi_ioda_controller_ops = { 3841 .enable_device_hook = pnv_pci_enable_device_hook, 3842 .window_alignment = pnv_pci_window_alignment, 3843 .reset_secondary_bus = pnv_pci_reset_secondary_bus, 3844 .shutdown = pnv_pci_ioda_shutdown, 3845 }; 3846 3847 #ifdef CONFIG_CXL_BASE 3848 const struct pci_controller_ops pnv_cxl_cx4_ioda_controller_ops = { 3849 .dma_dev_setup = pnv_pci_dma_dev_setup, 3850 .dma_bus_setup = pnv_pci_dma_bus_setup, 3851 #ifdef CONFIG_PCI_MSI 3852 .setup_msi_irqs = pnv_cxl_cx4_setup_msi_irqs, 3853 .teardown_msi_irqs = pnv_cxl_cx4_teardown_msi_irqs, 3854 #endif 3855 .enable_device_hook = pnv_cxl_enable_device_hook, 3856 .disable_device = pnv_cxl_disable_device, 3857 .release_device = pnv_pci_release_device, 3858 .window_alignment = pnv_pci_window_alignment, 3859 .setup_bridge = pnv_pci_setup_bridge, 3860 .reset_secondary_bus = pnv_pci_reset_secondary_bus, 3861 .dma_set_mask = pnv_pci_ioda_dma_set_mask, 3862 .dma_get_required_mask = pnv_pci_ioda_dma_get_required_mask, 3863 .shutdown = pnv_pci_ioda_shutdown, 3864 }; 3865 #endif 3866 3867 static void __init pnv_pci_init_ioda_phb(struct device_node *np, 3868 u64 hub_id, int ioda_type) 3869 { 3870 struct pci_controller *hose; 3871 struct pnv_phb *phb; 3872 unsigned long size, m64map_off, m32map_off, pemap_off; 3873 unsigned long iomap_off = 0, dma32map_off = 0; 3874 struct resource r; 3875 const __be64 *prop64; 3876 const __be32 *prop32; 3877 int len; 3878 unsigned int segno; 3879 u64 phb_id; 3880 void *aux; 3881 long rc; 3882 3883 if (!of_device_is_available(np)) 3884 return; 3885 3886 pr_info("Initializing %s PHB (%pOF)\n", pnv_phb_names[ioda_type], np); 3887 3888 prop64 = of_get_property(np, "ibm,opal-phbid", NULL); 3889 if (!prop64) { 3890 pr_err(" Missing \"ibm,opal-phbid\" property !\n"); 3891 return; 3892 } 3893 phb_id = be64_to_cpup(prop64); 3894 pr_debug(" PHB-ID : 0x%016llx\n", phb_id); 3895 3896 phb = memblock_virt_alloc(sizeof(*phb), 0); 3897 3898 /* Allocate PCI controller */ 3899 phb->hose = hose = pcibios_alloc_controller(np); 3900 if (!phb->hose) { 3901 pr_err(" Can't allocate PCI controller for %pOF\n", 3902 np); 3903 memblock_free(__pa(phb), sizeof(struct pnv_phb)); 3904 return; 3905 } 3906 3907 spin_lock_init(&phb->lock); 3908 prop32 = of_get_property(np, "bus-range", &len); 3909 if (prop32 && len == 8) { 3910 hose->first_busno = be32_to_cpu(prop32[0]); 3911 hose->last_busno = be32_to_cpu(prop32[1]); 3912 } else { 3913 pr_warn(" Broken <bus-range> on %pOF\n", np); 3914 hose->first_busno = 0; 3915 hose->last_busno = 0xff; 3916 } 3917 hose->private_data = phb; 3918 phb->hub_id = hub_id; 3919 phb->opal_id = phb_id; 3920 phb->type = ioda_type; 3921 mutex_init(&phb->ioda.pe_alloc_mutex); 3922 3923 /* Detect specific models for error handling */ 3924 if (of_device_is_compatible(np, "ibm,p7ioc-pciex")) 3925 phb->model = PNV_PHB_MODEL_P7IOC; 3926 else if (of_device_is_compatible(np, "ibm,power8-pciex")) 3927 phb->model = PNV_PHB_MODEL_PHB3; 3928 else if (of_device_is_compatible(np, "ibm,power8-npu-pciex")) 3929 phb->model = PNV_PHB_MODEL_NPU; 3930 else if (of_device_is_compatible(np, "ibm,power9-npu-pciex")) 3931 phb->model = PNV_PHB_MODEL_NPU2; 3932 else 3933 phb->model = PNV_PHB_MODEL_UNKNOWN; 3934 3935 /* Initialize diagnostic data buffer */ 3936 prop32 = of_get_property(np, "ibm,phb-diag-data-size", NULL); 3937 if (prop32) 3938 phb->diag_data_size = be32_to_cpup(prop32); 3939 else 3940 phb->diag_data_size = PNV_PCI_DIAG_BUF_SIZE; 3941 3942 phb->diag_data = memblock_virt_alloc(phb->diag_data_size, 0); 3943 3944 /* Parse 32-bit and IO ranges (if any) */ 3945 pci_process_bridge_OF_ranges(hose, np, !hose->global_number); 3946 3947 /* Get registers */ 3948 if (!of_address_to_resource(np, 0, &r)) { 3949 phb->regs_phys = r.start; 3950 phb->regs = ioremap(r.start, resource_size(&r)); 3951 if (phb->regs == NULL) 3952 pr_err(" Failed to map registers !\n"); 3953 } 3954 3955 /* Initialize more IODA stuff */ 3956 phb->ioda.total_pe_num = 1; 3957 prop32 = of_get_property(np, "ibm,opal-num-pes", NULL); 3958 if (prop32) 3959 phb->ioda.total_pe_num = be32_to_cpup(prop32); 3960 prop32 = of_get_property(np, "ibm,opal-reserved-pe", NULL); 3961 if (prop32) 3962 phb->ioda.reserved_pe_idx = be32_to_cpup(prop32); 3963 3964 /* Invalidate RID to PE# mapping */ 3965 for (segno = 0; segno < ARRAY_SIZE(phb->ioda.pe_rmap); segno++) 3966 phb->ioda.pe_rmap[segno] = IODA_INVALID_PE; 3967 3968 /* Parse 64-bit MMIO range */ 3969 pnv_ioda_parse_m64_window(phb); 3970 3971 phb->ioda.m32_size = resource_size(&hose->mem_resources[0]); 3972 /* FW Has already off top 64k of M32 space (MSI space) */ 3973 phb->ioda.m32_size += 0x10000; 3974 3975 phb->ioda.m32_segsize = phb->ioda.m32_size / phb->ioda.total_pe_num; 3976 phb->ioda.m32_pci_base = hose->mem_resources[0].start - hose->mem_offset[0]; 3977 phb->ioda.io_size = hose->pci_io_size; 3978 phb->ioda.io_segsize = phb->ioda.io_size / phb->ioda.total_pe_num; 3979 phb->ioda.io_pci_base = 0; /* XXX calculate this ? */ 3980 3981 /* Calculate how many 32-bit TCE segments we have */ 3982 phb->ioda.dma32_count = phb->ioda.m32_pci_base / 3983 PNV_IODA1_DMA32_SEGSIZE; 3984 3985 /* Allocate aux data & arrays. We don't have IO ports on PHB3 */ 3986 size = _ALIGN_UP(max_t(unsigned, phb->ioda.total_pe_num, 8) / 8, 3987 sizeof(unsigned long)); 3988 m64map_off = size; 3989 size += phb->ioda.total_pe_num * sizeof(phb->ioda.m64_segmap[0]); 3990 m32map_off = size; 3991 size += phb->ioda.total_pe_num * sizeof(phb->ioda.m32_segmap[0]); 3992 if (phb->type == PNV_PHB_IODA1) { 3993 iomap_off = size; 3994 size += phb->ioda.total_pe_num * sizeof(phb->ioda.io_segmap[0]); 3995 dma32map_off = size; 3996 size += phb->ioda.dma32_count * 3997 sizeof(phb->ioda.dma32_segmap[0]); 3998 } 3999 pemap_off = size; 4000 size += phb->ioda.total_pe_num * sizeof(struct pnv_ioda_pe); 4001 aux = memblock_virt_alloc(size, 0); 4002 phb->ioda.pe_alloc = aux; 4003 phb->ioda.m64_segmap = aux + m64map_off; 4004 phb->ioda.m32_segmap = aux + m32map_off; 4005 for (segno = 0; segno < phb->ioda.total_pe_num; segno++) { 4006 phb->ioda.m64_segmap[segno] = IODA_INVALID_PE; 4007 phb->ioda.m32_segmap[segno] = IODA_INVALID_PE; 4008 } 4009 if (phb->type == PNV_PHB_IODA1) { 4010 phb->ioda.io_segmap = aux + iomap_off; 4011 for (segno = 0; segno < phb->ioda.total_pe_num; segno++) 4012 phb->ioda.io_segmap[segno] = IODA_INVALID_PE; 4013 4014 phb->ioda.dma32_segmap = aux + dma32map_off; 4015 for (segno = 0; segno < phb->ioda.dma32_count; segno++) 4016 phb->ioda.dma32_segmap[segno] = IODA_INVALID_PE; 4017 } 4018 phb->ioda.pe_array = aux + pemap_off; 4019 4020 /* 4021 * Choose PE number for root bus, which shouldn't have 4022 * M64 resources consumed by its child devices. To pick 4023 * the PE number adjacent to the reserved one if possible. 4024 */ 4025 pnv_ioda_reserve_pe(phb, phb->ioda.reserved_pe_idx); 4026 if (phb->ioda.reserved_pe_idx == 0) { 4027 phb->ioda.root_pe_idx = 1; 4028 pnv_ioda_reserve_pe(phb, phb->ioda.root_pe_idx); 4029 } else if (phb->ioda.reserved_pe_idx == (phb->ioda.total_pe_num - 1)) { 4030 phb->ioda.root_pe_idx = phb->ioda.reserved_pe_idx - 1; 4031 pnv_ioda_reserve_pe(phb, phb->ioda.root_pe_idx); 4032 } else { 4033 phb->ioda.root_pe_idx = IODA_INVALID_PE; 4034 } 4035 4036 INIT_LIST_HEAD(&phb->ioda.pe_list); 4037 mutex_init(&phb->ioda.pe_list_mutex); 4038 4039 /* Calculate how many 32-bit TCE segments we have */ 4040 phb->ioda.dma32_count = phb->ioda.m32_pci_base / 4041 PNV_IODA1_DMA32_SEGSIZE; 4042 4043 #if 0 /* We should really do that ... */ 4044 rc = opal_pci_set_phb_mem_window(opal->phb_id, 4045 window_type, 4046 window_num, 4047 starting_real_address, 4048 starting_pci_address, 4049 segment_size); 4050 #endif 4051 4052 pr_info(" %03d (%03d) PE's M32: 0x%x [segment=0x%x]\n", 4053 phb->ioda.total_pe_num, phb->ioda.reserved_pe_idx, 4054 phb->ioda.m32_size, phb->ioda.m32_segsize); 4055 if (phb->ioda.m64_size) 4056 pr_info(" M64: 0x%lx [segment=0x%lx]\n", 4057 phb->ioda.m64_size, phb->ioda.m64_segsize); 4058 if (phb->ioda.io_size) 4059 pr_info(" IO: 0x%x [segment=0x%x]\n", 4060 phb->ioda.io_size, phb->ioda.io_segsize); 4061 4062 4063 phb->hose->ops = &pnv_pci_ops; 4064 phb->get_pe_state = pnv_ioda_get_pe_state; 4065 phb->freeze_pe = pnv_ioda_freeze_pe; 4066 phb->unfreeze_pe = pnv_ioda_unfreeze_pe; 4067 4068 /* Setup MSI support */ 4069 pnv_pci_init_ioda_msis(phb); 4070 4071 /* 4072 * We pass the PCI probe flag PCI_REASSIGN_ALL_RSRC here 4073 * to let the PCI core do resource assignment. It's supposed 4074 * that the PCI core will do correct I/O and MMIO alignment 4075 * for the P2P bridge bars so that each PCI bus (excluding 4076 * the child P2P bridges) can form individual PE. 4077 */ 4078 ppc_md.pcibios_fixup = pnv_pci_ioda_fixup; 4079 4080 switch (phb->type) { 4081 case PNV_PHB_NPU_NVLINK: 4082 hose->controller_ops = pnv_npu_ioda_controller_ops; 4083 break; 4084 case PNV_PHB_NPU_OCAPI: 4085 hose->controller_ops = pnv_npu_ocapi_ioda_controller_ops; 4086 break; 4087 default: 4088 phb->dma_dev_setup = pnv_pci_ioda_dma_dev_setup; 4089 hose->controller_ops = pnv_pci_ioda_controller_ops; 4090 } 4091 4092 ppc_md.pcibios_default_alignment = pnv_pci_default_alignment; 4093 4094 #ifdef CONFIG_PCI_IOV 4095 ppc_md.pcibios_fixup_sriov = pnv_pci_ioda_fixup_iov_resources; 4096 ppc_md.pcibios_iov_resource_alignment = pnv_pci_iov_resource_alignment; 4097 ppc_md.pcibios_sriov_enable = pnv_pcibios_sriov_enable; 4098 ppc_md.pcibios_sriov_disable = pnv_pcibios_sriov_disable; 4099 #endif 4100 4101 pci_add_flags(PCI_REASSIGN_ALL_RSRC); 4102 4103 /* Reset IODA tables to a clean state */ 4104 rc = opal_pci_reset(phb_id, OPAL_RESET_PCI_IODA_TABLE, OPAL_ASSERT_RESET); 4105 if (rc) 4106 pr_warn(" OPAL Error %ld performing IODA table reset !\n", rc); 4107 4108 /* 4109 * If we're running in kdump kernel, the previous kernel never 4110 * shutdown PCI devices correctly. We already got IODA table 4111 * cleaned out. So we have to issue PHB reset to stop all PCI 4112 * transactions from previous kernel. The ppc_pci_reset_phbs 4113 * kernel parameter will force this reset too. 4114 */ 4115 if (is_kdump_kernel() || pci_reset_phbs) { 4116 pr_info(" Issue PHB reset ...\n"); 4117 pnv_eeh_phb_reset(hose, EEH_RESET_FUNDAMENTAL); 4118 pnv_eeh_phb_reset(hose, EEH_RESET_DEACTIVATE); 4119 } 4120 4121 /* Remove M64 resource if we can't configure it successfully */ 4122 if (!phb->init_m64 || phb->init_m64(phb)) 4123 hose->mem_resources[1].flags = 0; 4124 } 4125 4126 void __init pnv_pci_init_ioda2_phb(struct device_node *np) 4127 { 4128 pnv_pci_init_ioda_phb(np, 0, PNV_PHB_IODA2); 4129 } 4130 4131 void __init pnv_pci_init_npu_phb(struct device_node *np) 4132 { 4133 pnv_pci_init_ioda_phb(np, 0, PNV_PHB_NPU_NVLINK); 4134 } 4135 4136 void __init pnv_pci_init_npu2_opencapi_phb(struct device_node *np) 4137 { 4138 pnv_pci_init_ioda_phb(np, 0, PNV_PHB_NPU_OCAPI); 4139 } 4140 4141 static void pnv_npu2_opencapi_cfg_size_fixup(struct pci_dev *dev) 4142 { 4143 struct pci_controller *hose = pci_bus_to_host(dev->bus); 4144 struct pnv_phb *phb = hose->private_data; 4145 4146 if (!machine_is(powernv)) 4147 return; 4148 4149 if (phb->type == PNV_PHB_NPU_OCAPI) 4150 dev->cfg_size = PCI_CFG_SPACE_EXP_SIZE; 4151 } 4152 DECLARE_PCI_FIXUP_EARLY(PCI_ANY_ID, PCI_ANY_ID, pnv_npu2_opencapi_cfg_size_fixup); 4153 4154 void __init pnv_pci_init_ioda_hub(struct device_node *np) 4155 { 4156 struct device_node *phbn; 4157 const __be64 *prop64; 4158 u64 hub_id; 4159 4160 pr_info("Probing IODA IO-Hub %pOF\n", np); 4161 4162 prop64 = of_get_property(np, "ibm,opal-hubid", NULL); 4163 if (!prop64) { 4164 pr_err(" Missing \"ibm,opal-hubid\" property !\n"); 4165 return; 4166 } 4167 hub_id = be64_to_cpup(prop64); 4168 pr_devel(" HUB-ID : 0x%016llx\n", hub_id); 4169 4170 /* Count child PHBs */ 4171 for_each_child_of_node(np, phbn) { 4172 /* Look for IODA1 PHBs */ 4173 if (of_device_is_compatible(phbn, "ibm,ioda-phb")) 4174 pnv_pci_init_ioda_phb(phbn, hub_id, PNV_PHB_IODA1); 4175 } 4176 } 4177