1 // SPDX-License-Identifier: GPL-2.0-or-later 2 /* 3 * Support PCI/PCIe on PowerNV platforms 4 * 5 * Copyright 2011 Benjamin Herrenschmidt, IBM Corp. 6 */ 7 8 #undef DEBUG 9 10 #include <linux/kernel.h> 11 #include <linux/pci.h> 12 #include <linux/crash_dump.h> 13 #include <linux/delay.h> 14 #include <linux/string.h> 15 #include <linux/init.h> 16 #include <linux/memblock.h> 17 #include <linux/irq.h> 18 #include <linux/io.h> 19 #include <linux/msi.h> 20 #include <linux/iommu.h> 21 #include <linux/rculist.h> 22 #include <linux/sizes.h> 23 #include <linux/debugfs.h> 24 #include <linux/of_address.h> 25 #include <linux/of_irq.h> 26 27 #include <asm/sections.h> 28 #include <asm/io.h> 29 #include <asm/pci-bridge.h> 30 #include <asm/machdep.h> 31 #include <asm/msi_bitmap.h> 32 #include <asm/ppc-pci.h> 33 #include <asm/opal.h> 34 #include <asm/iommu.h> 35 #include <asm/tce.h> 36 #include <asm/xics.h> 37 #include <asm/firmware.h> 38 #include <asm/pnv-pci.h> 39 #include <asm/mmzone.h> 40 #include <asm/xive.h> 41 42 #include <misc/cxl-base.h> 43 44 #include "powernv.h" 45 #include "pci.h" 46 #include "../../../../drivers/pci/pci.h" 47 48 #define PNV_IODA1_M64_NUM 16 /* Number of M64 BARs */ 49 #define PNV_IODA1_M64_SEGS 8 /* Segments per M64 BAR */ 50 #define PNV_IODA1_DMA32_SEGSIZE 0x10000000 51 52 static const char * const pnv_phb_names[] = { "IODA1", "IODA2", "NPU_OCAPI" }; 53 54 static void pnv_pci_ioda2_set_bypass(struct pnv_ioda_pe *pe, bool enable); 55 static void pnv_pci_configure_bus(struct pci_bus *bus); 56 57 void pe_level_printk(const struct pnv_ioda_pe *pe, const char *level, 58 const char *fmt, ...) 59 { 60 struct va_format vaf; 61 va_list args; 62 char pfix[32]; 63 64 va_start(args, fmt); 65 66 vaf.fmt = fmt; 67 vaf.va = &args; 68 69 if (pe->flags & PNV_IODA_PE_DEV) 70 strlcpy(pfix, dev_name(&pe->pdev->dev), sizeof(pfix)); 71 else if (pe->flags & (PNV_IODA_PE_BUS | PNV_IODA_PE_BUS_ALL)) 72 sprintf(pfix, "%04x:%02x ", 73 pci_domain_nr(pe->pbus), pe->pbus->number); 74 #ifdef CONFIG_PCI_IOV 75 else if (pe->flags & PNV_IODA_PE_VF) 76 sprintf(pfix, "%04x:%02x:%2x.%d", 77 pci_domain_nr(pe->parent_dev->bus), 78 (pe->rid & 0xff00) >> 8, 79 PCI_SLOT(pe->rid), PCI_FUNC(pe->rid)); 80 #endif /* CONFIG_PCI_IOV*/ 81 82 printk("%spci %s: [PE# %.2x] %pV", 83 level, pfix, pe->pe_number, &vaf); 84 85 va_end(args); 86 } 87 88 static bool pnv_iommu_bypass_disabled __read_mostly; 89 static bool pci_reset_phbs __read_mostly; 90 91 static int __init iommu_setup(char *str) 92 { 93 if (!str) 94 return -EINVAL; 95 96 while (*str) { 97 if (!strncmp(str, "nobypass", 8)) { 98 pnv_iommu_bypass_disabled = true; 99 pr_info("PowerNV: IOMMU bypass window disabled.\n"); 100 break; 101 } 102 str += strcspn(str, ","); 103 if (*str == ',') 104 str++; 105 } 106 107 return 0; 108 } 109 early_param("iommu", iommu_setup); 110 111 static int __init pci_reset_phbs_setup(char *str) 112 { 113 pci_reset_phbs = true; 114 return 0; 115 } 116 117 early_param("ppc_pci_reset_phbs", pci_reset_phbs_setup); 118 119 static struct pnv_ioda_pe *pnv_ioda_init_pe(struct pnv_phb *phb, int pe_no) 120 { 121 s64 rc; 122 123 phb->ioda.pe_array[pe_no].phb = phb; 124 phb->ioda.pe_array[pe_no].pe_number = pe_no; 125 phb->ioda.pe_array[pe_no].dma_setup_done = false; 126 127 /* 128 * Clear the PE frozen state as it might be put into frozen state 129 * in the last PCI remove path. It's not harmful to do so when the 130 * PE is already in unfrozen state. 131 */ 132 rc = opal_pci_eeh_freeze_clear(phb->opal_id, pe_no, 133 OPAL_EEH_ACTION_CLEAR_FREEZE_ALL); 134 if (rc != OPAL_SUCCESS && rc != OPAL_UNSUPPORTED) 135 pr_warn("%s: Error %lld unfreezing PHB#%x-PE#%x\n", 136 __func__, rc, phb->hose->global_number, pe_no); 137 138 return &phb->ioda.pe_array[pe_no]; 139 } 140 141 static void pnv_ioda_reserve_pe(struct pnv_phb *phb, int pe_no) 142 { 143 if (!(pe_no >= 0 && pe_no < phb->ioda.total_pe_num)) { 144 pr_warn("%s: Invalid PE %x on PHB#%x\n", 145 __func__, pe_no, phb->hose->global_number); 146 return; 147 } 148 149 mutex_lock(&phb->ioda.pe_alloc_mutex); 150 if (test_and_set_bit(pe_no, phb->ioda.pe_alloc)) 151 pr_debug("%s: PE %x was reserved on PHB#%x\n", 152 __func__, pe_no, phb->hose->global_number); 153 mutex_unlock(&phb->ioda.pe_alloc_mutex); 154 155 pnv_ioda_init_pe(phb, pe_no); 156 } 157 158 struct pnv_ioda_pe *pnv_ioda_alloc_pe(struct pnv_phb *phb, int count) 159 { 160 struct pnv_ioda_pe *ret = NULL; 161 int run = 0, pe, i; 162 163 mutex_lock(&phb->ioda.pe_alloc_mutex); 164 165 /* scan backwards for a run of @count cleared bits */ 166 for (pe = phb->ioda.total_pe_num - 1; pe >= 0; pe--) { 167 if (test_bit(pe, phb->ioda.pe_alloc)) { 168 run = 0; 169 continue; 170 } 171 172 run++; 173 if (run == count) 174 break; 175 } 176 if (run != count) 177 goto out; 178 179 for (i = pe; i < pe + count; i++) { 180 set_bit(i, phb->ioda.pe_alloc); 181 pnv_ioda_init_pe(phb, i); 182 } 183 ret = &phb->ioda.pe_array[pe]; 184 185 out: 186 mutex_unlock(&phb->ioda.pe_alloc_mutex); 187 return ret; 188 } 189 190 void pnv_ioda_free_pe(struct pnv_ioda_pe *pe) 191 { 192 struct pnv_phb *phb = pe->phb; 193 unsigned int pe_num = pe->pe_number; 194 195 WARN_ON(pe->pdev); 196 memset(pe, 0, sizeof(struct pnv_ioda_pe)); 197 198 mutex_lock(&phb->ioda.pe_alloc_mutex); 199 clear_bit(pe_num, phb->ioda.pe_alloc); 200 mutex_unlock(&phb->ioda.pe_alloc_mutex); 201 } 202 203 /* The default M64 BAR is shared by all PEs */ 204 static int pnv_ioda2_init_m64(struct pnv_phb *phb) 205 { 206 const char *desc; 207 struct resource *r; 208 s64 rc; 209 210 /* Configure the default M64 BAR */ 211 rc = opal_pci_set_phb_mem_window(phb->opal_id, 212 OPAL_M64_WINDOW_TYPE, 213 phb->ioda.m64_bar_idx, 214 phb->ioda.m64_base, 215 0, /* unused */ 216 phb->ioda.m64_size); 217 if (rc != OPAL_SUCCESS) { 218 desc = "configuring"; 219 goto fail; 220 } 221 222 /* Enable the default M64 BAR */ 223 rc = opal_pci_phb_mmio_enable(phb->opal_id, 224 OPAL_M64_WINDOW_TYPE, 225 phb->ioda.m64_bar_idx, 226 OPAL_ENABLE_M64_SPLIT); 227 if (rc != OPAL_SUCCESS) { 228 desc = "enabling"; 229 goto fail; 230 } 231 232 /* 233 * Exclude the segments for reserved and root bus PE, which 234 * are first or last two PEs. 235 */ 236 r = &phb->hose->mem_resources[1]; 237 if (phb->ioda.reserved_pe_idx == 0) 238 r->start += (2 * phb->ioda.m64_segsize); 239 else if (phb->ioda.reserved_pe_idx == (phb->ioda.total_pe_num - 1)) 240 r->end -= (2 * phb->ioda.m64_segsize); 241 else 242 pr_warn(" Cannot strip M64 segment for reserved PE#%x\n", 243 phb->ioda.reserved_pe_idx); 244 245 return 0; 246 247 fail: 248 pr_warn(" Failure %lld %s M64 BAR#%d\n", 249 rc, desc, phb->ioda.m64_bar_idx); 250 opal_pci_phb_mmio_enable(phb->opal_id, 251 OPAL_M64_WINDOW_TYPE, 252 phb->ioda.m64_bar_idx, 253 OPAL_DISABLE_M64); 254 return -EIO; 255 } 256 257 static void pnv_ioda_reserve_dev_m64_pe(struct pci_dev *pdev, 258 unsigned long *pe_bitmap) 259 { 260 struct pnv_phb *phb = pci_bus_to_pnvhb(pdev->bus); 261 struct resource *r; 262 resource_size_t base, sgsz, start, end; 263 int segno, i; 264 265 base = phb->ioda.m64_base; 266 sgsz = phb->ioda.m64_segsize; 267 for (i = 0; i <= PCI_ROM_RESOURCE; i++) { 268 r = &pdev->resource[i]; 269 if (!r->parent || !pnv_pci_is_m64(phb, r)) 270 continue; 271 272 start = ALIGN_DOWN(r->start - base, sgsz); 273 end = ALIGN(r->end - base, sgsz); 274 for (segno = start / sgsz; segno < end / sgsz; segno++) { 275 if (pe_bitmap) 276 set_bit(segno, pe_bitmap); 277 else 278 pnv_ioda_reserve_pe(phb, segno); 279 } 280 } 281 } 282 283 static int pnv_ioda1_init_m64(struct pnv_phb *phb) 284 { 285 struct resource *r; 286 int index; 287 288 /* 289 * There are 16 M64 BARs, each of which has 8 segments. So 290 * there are as many M64 segments as the maximum number of 291 * PEs, which is 128. 292 */ 293 for (index = 0; index < PNV_IODA1_M64_NUM; index++) { 294 unsigned long base, segsz = phb->ioda.m64_segsize; 295 int64_t rc; 296 297 base = phb->ioda.m64_base + 298 index * PNV_IODA1_M64_SEGS * segsz; 299 rc = opal_pci_set_phb_mem_window(phb->opal_id, 300 OPAL_M64_WINDOW_TYPE, index, base, 0, 301 PNV_IODA1_M64_SEGS * segsz); 302 if (rc != OPAL_SUCCESS) { 303 pr_warn(" Error %lld setting M64 PHB#%x-BAR#%d\n", 304 rc, phb->hose->global_number, index); 305 goto fail; 306 } 307 308 rc = opal_pci_phb_mmio_enable(phb->opal_id, 309 OPAL_M64_WINDOW_TYPE, index, 310 OPAL_ENABLE_M64_SPLIT); 311 if (rc != OPAL_SUCCESS) { 312 pr_warn(" Error %lld enabling M64 PHB#%x-BAR#%d\n", 313 rc, phb->hose->global_number, index); 314 goto fail; 315 } 316 } 317 318 for (index = 0; index < phb->ioda.total_pe_num; index++) { 319 int64_t rc; 320 321 /* 322 * P7IOC supports M64DT, which helps mapping M64 segment 323 * to one particular PE#. However, PHB3 has fixed mapping 324 * between M64 segment and PE#. In order to have same logic 325 * for P7IOC and PHB3, we enforce fixed mapping between M64 326 * segment and PE# on P7IOC. 327 */ 328 rc = opal_pci_map_pe_mmio_window(phb->opal_id, 329 index, OPAL_M64_WINDOW_TYPE, 330 index / PNV_IODA1_M64_SEGS, 331 index % PNV_IODA1_M64_SEGS); 332 if (rc != OPAL_SUCCESS) { 333 pr_warn("%s: Error %lld mapping M64 for PHB#%x-PE#%x\n", 334 __func__, rc, phb->hose->global_number, 335 index); 336 goto fail; 337 } 338 } 339 340 /* 341 * Exclude the segments for reserved and root bus PE, which 342 * are first or last two PEs. 343 */ 344 r = &phb->hose->mem_resources[1]; 345 if (phb->ioda.reserved_pe_idx == 0) 346 r->start += (2 * phb->ioda.m64_segsize); 347 else if (phb->ioda.reserved_pe_idx == (phb->ioda.total_pe_num - 1)) 348 r->end -= (2 * phb->ioda.m64_segsize); 349 else 350 WARN(1, "Wrong reserved PE#%x on PHB#%x\n", 351 phb->ioda.reserved_pe_idx, phb->hose->global_number); 352 353 return 0; 354 355 fail: 356 for ( ; index >= 0; index--) 357 opal_pci_phb_mmio_enable(phb->opal_id, 358 OPAL_M64_WINDOW_TYPE, index, OPAL_DISABLE_M64); 359 360 return -EIO; 361 } 362 363 static void pnv_ioda_reserve_m64_pe(struct pci_bus *bus, 364 unsigned long *pe_bitmap, 365 bool all) 366 { 367 struct pci_dev *pdev; 368 369 list_for_each_entry(pdev, &bus->devices, bus_list) { 370 pnv_ioda_reserve_dev_m64_pe(pdev, pe_bitmap); 371 372 if (all && pdev->subordinate) 373 pnv_ioda_reserve_m64_pe(pdev->subordinate, 374 pe_bitmap, all); 375 } 376 } 377 378 static struct pnv_ioda_pe *pnv_ioda_pick_m64_pe(struct pci_bus *bus, bool all) 379 { 380 struct pnv_phb *phb = pci_bus_to_pnvhb(bus); 381 struct pnv_ioda_pe *master_pe, *pe; 382 unsigned long size, *pe_alloc; 383 int i; 384 385 /* Root bus shouldn't use M64 */ 386 if (pci_is_root_bus(bus)) 387 return NULL; 388 389 /* Allocate bitmap */ 390 size = ALIGN(phb->ioda.total_pe_num / 8, sizeof(unsigned long)); 391 pe_alloc = kzalloc(size, GFP_KERNEL); 392 if (!pe_alloc) { 393 pr_warn("%s: Out of memory !\n", 394 __func__); 395 return NULL; 396 } 397 398 /* Figure out reserved PE numbers by the PE */ 399 pnv_ioda_reserve_m64_pe(bus, pe_alloc, all); 400 401 /* 402 * the current bus might not own M64 window and that's all 403 * contributed by its child buses. For the case, we needn't 404 * pick M64 dependent PE#. 405 */ 406 if (bitmap_empty(pe_alloc, phb->ioda.total_pe_num)) { 407 kfree(pe_alloc); 408 return NULL; 409 } 410 411 /* 412 * Figure out the master PE and put all slave PEs to master 413 * PE's list to form compound PE. 414 */ 415 master_pe = NULL; 416 i = -1; 417 while ((i = find_next_bit(pe_alloc, phb->ioda.total_pe_num, i + 1)) < 418 phb->ioda.total_pe_num) { 419 pe = &phb->ioda.pe_array[i]; 420 421 phb->ioda.m64_segmap[pe->pe_number] = pe->pe_number; 422 if (!master_pe) { 423 pe->flags |= PNV_IODA_PE_MASTER; 424 INIT_LIST_HEAD(&pe->slaves); 425 master_pe = pe; 426 } else { 427 pe->flags |= PNV_IODA_PE_SLAVE; 428 pe->master = master_pe; 429 list_add_tail(&pe->list, &master_pe->slaves); 430 } 431 } 432 433 kfree(pe_alloc); 434 return master_pe; 435 } 436 437 static void __init pnv_ioda_parse_m64_window(struct pnv_phb *phb) 438 { 439 struct pci_controller *hose = phb->hose; 440 struct device_node *dn = hose->dn; 441 struct resource *res; 442 u32 m64_range[2], i; 443 const __be32 *r; 444 u64 pci_addr; 445 446 if (phb->type != PNV_PHB_IODA1 && phb->type != PNV_PHB_IODA2) { 447 pr_info(" Not support M64 window\n"); 448 return; 449 } 450 451 if (!firmware_has_feature(FW_FEATURE_OPAL)) { 452 pr_info(" Firmware too old to support M64 window\n"); 453 return; 454 } 455 456 r = of_get_property(dn, "ibm,opal-m64-window", NULL); 457 if (!r) { 458 pr_info(" No <ibm,opal-m64-window> on %pOF\n", 459 dn); 460 return; 461 } 462 463 /* 464 * Find the available M64 BAR range and pickup the last one for 465 * covering the whole 64-bits space. We support only one range. 466 */ 467 if (of_property_read_u32_array(dn, "ibm,opal-available-m64-ranges", 468 m64_range, 2)) { 469 /* In absence of the property, assume 0..15 */ 470 m64_range[0] = 0; 471 m64_range[1] = 16; 472 } 473 /* We only support 64 bits in our allocator */ 474 if (m64_range[1] > 63) { 475 pr_warn("%s: Limiting M64 range to 63 (from %d) on PHB#%x\n", 476 __func__, m64_range[1], phb->hose->global_number); 477 m64_range[1] = 63; 478 } 479 /* Empty range, no m64 */ 480 if (m64_range[1] <= m64_range[0]) { 481 pr_warn("%s: M64 empty, disabling M64 usage on PHB#%x\n", 482 __func__, phb->hose->global_number); 483 return; 484 } 485 486 /* Configure M64 informations */ 487 res = &hose->mem_resources[1]; 488 res->name = dn->full_name; 489 res->start = of_translate_address(dn, r + 2); 490 res->end = res->start + of_read_number(r + 4, 2) - 1; 491 res->flags = (IORESOURCE_MEM | IORESOURCE_MEM_64 | IORESOURCE_PREFETCH); 492 pci_addr = of_read_number(r, 2); 493 hose->mem_offset[1] = res->start - pci_addr; 494 495 phb->ioda.m64_size = resource_size(res); 496 phb->ioda.m64_segsize = phb->ioda.m64_size / phb->ioda.total_pe_num; 497 phb->ioda.m64_base = pci_addr; 498 499 /* This lines up nicely with the display from processing OF ranges */ 500 pr_info(" MEM 0x%016llx..0x%016llx -> 0x%016llx (M64 #%d..%d)\n", 501 res->start, res->end, pci_addr, m64_range[0], 502 m64_range[0] + m64_range[1] - 1); 503 504 /* Mark all M64 used up by default */ 505 phb->ioda.m64_bar_alloc = (unsigned long)-1; 506 507 /* Use last M64 BAR to cover M64 window */ 508 m64_range[1]--; 509 phb->ioda.m64_bar_idx = m64_range[0] + m64_range[1]; 510 511 pr_info(" Using M64 #%d as default window\n", phb->ioda.m64_bar_idx); 512 513 /* Mark remaining ones free */ 514 for (i = m64_range[0]; i < m64_range[1]; i++) 515 clear_bit(i, &phb->ioda.m64_bar_alloc); 516 517 /* 518 * Setup init functions for M64 based on IODA version, IODA3 uses 519 * the IODA2 code. 520 */ 521 if (phb->type == PNV_PHB_IODA1) 522 phb->init_m64 = pnv_ioda1_init_m64; 523 else 524 phb->init_m64 = pnv_ioda2_init_m64; 525 } 526 527 static void pnv_ioda_freeze_pe(struct pnv_phb *phb, int pe_no) 528 { 529 struct pnv_ioda_pe *pe = &phb->ioda.pe_array[pe_no]; 530 struct pnv_ioda_pe *slave; 531 s64 rc; 532 533 /* Fetch master PE */ 534 if (pe->flags & PNV_IODA_PE_SLAVE) { 535 pe = pe->master; 536 if (WARN_ON(!pe || !(pe->flags & PNV_IODA_PE_MASTER))) 537 return; 538 539 pe_no = pe->pe_number; 540 } 541 542 /* Freeze master PE */ 543 rc = opal_pci_eeh_freeze_set(phb->opal_id, 544 pe_no, 545 OPAL_EEH_ACTION_SET_FREEZE_ALL); 546 if (rc != OPAL_SUCCESS) { 547 pr_warn("%s: Failure %lld freezing PHB#%x-PE#%x\n", 548 __func__, rc, phb->hose->global_number, pe_no); 549 return; 550 } 551 552 /* Freeze slave PEs */ 553 if (!(pe->flags & PNV_IODA_PE_MASTER)) 554 return; 555 556 list_for_each_entry(slave, &pe->slaves, list) { 557 rc = opal_pci_eeh_freeze_set(phb->opal_id, 558 slave->pe_number, 559 OPAL_EEH_ACTION_SET_FREEZE_ALL); 560 if (rc != OPAL_SUCCESS) 561 pr_warn("%s: Failure %lld freezing PHB#%x-PE#%x\n", 562 __func__, rc, phb->hose->global_number, 563 slave->pe_number); 564 } 565 } 566 567 static int pnv_ioda_unfreeze_pe(struct pnv_phb *phb, int pe_no, int opt) 568 { 569 struct pnv_ioda_pe *pe, *slave; 570 s64 rc; 571 572 /* Find master PE */ 573 pe = &phb->ioda.pe_array[pe_no]; 574 if (pe->flags & PNV_IODA_PE_SLAVE) { 575 pe = pe->master; 576 WARN_ON(!pe || !(pe->flags & PNV_IODA_PE_MASTER)); 577 pe_no = pe->pe_number; 578 } 579 580 /* Clear frozen state for master PE */ 581 rc = opal_pci_eeh_freeze_clear(phb->opal_id, pe_no, opt); 582 if (rc != OPAL_SUCCESS) { 583 pr_warn("%s: Failure %lld clear %d on PHB#%x-PE#%x\n", 584 __func__, rc, opt, phb->hose->global_number, pe_no); 585 return -EIO; 586 } 587 588 if (!(pe->flags & PNV_IODA_PE_MASTER)) 589 return 0; 590 591 /* Clear frozen state for slave PEs */ 592 list_for_each_entry(slave, &pe->slaves, list) { 593 rc = opal_pci_eeh_freeze_clear(phb->opal_id, 594 slave->pe_number, 595 opt); 596 if (rc != OPAL_SUCCESS) { 597 pr_warn("%s: Failure %lld clear %d on PHB#%x-PE#%x\n", 598 __func__, rc, opt, phb->hose->global_number, 599 slave->pe_number); 600 return -EIO; 601 } 602 } 603 604 return 0; 605 } 606 607 static int pnv_ioda_get_pe_state(struct pnv_phb *phb, int pe_no) 608 { 609 struct pnv_ioda_pe *slave, *pe; 610 u8 fstate = 0, state; 611 __be16 pcierr = 0; 612 s64 rc; 613 614 /* Sanity check on PE number */ 615 if (pe_no < 0 || pe_no >= phb->ioda.total_pe_num) 616 return OPAL_EEH_STOPPED_PERM_UNAVAIL; 617 618 /* 619 * Fetch the master PE and the PE instance might be 620 * not initialized yet. 621 */ 622 pe = &phb->ioda.pe_array[pe_no]; 623 if (pe->flags & PNV_IODA_PE_SLAVE) { 624 pe = pe->master; 625 WARN_ON(!pe || !(pe->flags & PNV_IODA_PE_MASTER)); 626 pe_no = pe->pe_number; 627 } 628 629 /* Check the master PE */ 630 rc = opal_pci_eeh_freeze_status(phb->opal_id, pe_no, 631 &state, &pcierr, NULL); 632 if (rc != OPAL_SUCCESS) { 633 pr_warn("%s: Failure %lld getting " 634 "PHB#%x-PE#%x state\n", 635 __func__, rc, 636 phb->hose->global_number, pe_no); 637 return OPAL_EEH_STOPPED_TEMP_UNAVAIL; 638 } 639 640 /* Check the slave PE */ 641 if (!(pe->flags & PNV_IODA_PE_MASTER)) 642 return state; 643 644 list_for_each_entry(slave, &pe->slaves, list) { 645 rc = opal_pci_eeh_freeze_status(phb->opal_id, 646 slave->pe_number, 647 &fstate, 648 &pcierr, 649 NULL); 650 if (rc != OPAL_SUCCESS) { 651 pr_warn("%s: Failure %lld getting " 652 "PHB#%x-PE#%x state\n", 653 __func__, rc, 654 phb->hose->global_number, slave->pe_number); 655 return OPAL_EEH_STOPPED_TEMP_UNAVAIL; 656 } 657 658 /* 659 * Override the result based on the ascending 660 * priority. 661 */ 662 if (fstate > state) 663 state = fstate; 664 } 665 666 return state; 667 } 668 669 struct pnv_ioda_pe *pnv_pci_bdfn_to_pe(struct pnv_phb *phb, u16 bdfn) 670 { 671 int pe_number = phb->ioda.pe_rmap[bdfn]; 672 673 if (pe_number == IODA_INVALID_PE) 674 return NULL; 675 676 return &phb->ioda.pe_array[pe_number]; 677 } 678 679 struct pnv_ioda_pe *pnv_ioda_get_pe(struct pci_dev *dev) 680 { 681 struct pnv_phb *phb = pci_bus_to_pnvhb(dev->bus); 682 struct pci_dn *pdn = pci_get_pdn(dev); 683 684 if (!pdn) 685 return NULL; 686 if (pdn->pe_number == IODA_INVALID_PE) 687 return NULL; 688 return &phb->ioda.pe_array[pdn->pe_number]; 689 } 690 691 static int pnv_ioda_set_one_peltv(struct pnv_phb *phb, 692 struct pnv_ioda_pe *parent, 693 struct pnv_ioda_pe *child, 694 bool is_add) 695 { 696 const char *desc = is_add ? "adding" : "removing"; 697 uint8_t op = is_add ? OPAL_ADD_PE_TO_DOMAIN : 698 OPAL_REMOVE_PE_FROM_DOMAIN; 699 struct pnv_ioda_pe *slave; 700 long rc; 701 702 /* Parent PE affects child PE */ 703 rc = opal_pci_set_peltv(phb->opal_id, parent->pe_number, 704 child->pe_number, op); 705 if (rc != OPAL_SUCCESS) { 706 pe_warn(child, "OPAL error %ld %s to parent PELTV\n", 707 rc, desc); 708 return -ENXIO; 709 } 710 711 if (!(child->flags & PNV_IODA_PE_MASTER)) 712 return 0; 713 714 /* Compound case: parent PE affects slave PEs */ 715 list_for_each_entry(slave, &child->slaves, list) { 716 rc = opal_pci_set_peltv(phb->opal_id, parent->pe_number, 717 slave->pe_number, op); 718 if (rc != OPAL_SUCCESS) { 719 pe_warn(slave, "OPAL error %ld %s to parent PELTV\n", 720 rc, desc); 721 return -ENXIO; 722 } 723 } 724 725 return 0; 726 } 727 728 static int pnv_ioda_set_peltv(struct pnv_phb *phb, 729 struct pnv_ioda_pe *pe, 730 bool is_add) 731 { 732 struct pnv_ioda_pe *slave; 733 struct pci_dev *pdev = NULL; 734 int ret; 735 736 /* 737 * Clear PE frozen state. If it's master PE, we need 738 * clear slave PE frozen state as well. 739 */ 740 if (is_add) { 741 opal_pci_eeh_freeze_clear(phb->opal_id, pe->pe_number, 742 OPAL_EEH_ACTION_CLEAR_FREEZE_ALL); 743 if (pe->flags & PNV_IODA_PE_MASTER) { 744 list_for_each_entry(slave, &pe->slaves, list) 745 opal_pci_eeh_freeze_clear(phb->opal_id, 746 slave->pe_number, 747 OPAL_EEH_ACTION_CLEAR_FREEZE_ALL); 748 } 749 } 750 751 /* 752 * Associate PE in PELT. We need add the PE into the 753 * corresponding PELT-V as well. Otherwise, the error 754 * originated from the PE might contribute to other 755 * PEs. 756 */ 757 ret = pnv_ioda_set_one_peltv(phb, pe, pe, is_add); 758 if (ret) 759 return ret; 760 761 /* For compound PEs, any one affects all of them */ 762 if (pe->flags & PNV_IODA_PE_MASTER) { 763 list_for_each_entry(slave, &pe->slaves, list) { 764 ret = pnv_ioda_set_one_peltv(phb, slave, pe, is_add); 765 if (ret) 766 return ret; 767 } 768 } 769 770 if (pe->flags & (PNV_IODA_PE_BUS_ALL | PNV_IODA_PE_BUS)) 771 pdev = pe->pbus->self; 772 else if (pe->flags & PNV_IODA_PE_DEV) 773 pdev = pe->pdev->bus->self; 774 #ifdef CONFIG_PCI_IOV 775 else if (pe->flags & PNV_IODA_PE_VF) 776 pdev = pe->parent_dev; 777 #endif /* CONFIG_PCI_IOV */ 778 while (pdev) { 779 struct pci_dn *pdn = pci_get_pdn(pdev); 780 struct pnv_ioda_pe *parent; 781 782 if (pdn && pdn->pe_number != IODA_INVALID_PE) { 783 parent = &phb->ioda.pe_array[pdn->pe_number]; 784 ret = pnv_ioda_set_one_peltv(phb, parent, pe, is_add); 785 if (ret) 786 return ret; 787 } 788 789 pdev = pdev->bus->self; 790 } 791 792 return 0; 793 } 794 795 static void pnv_ioda_unset_peltv(struct pnv_phb *phb, 796 struct pnv_ioda_pe *pe, 797 struct pci_dev *parent) 798 { 799 int64_t rc; 800 801 while (parent) { 802 struct pci_dn *pdn = pci_get_pdn(parent); 803 804 if (pdn && pdn->pe_number != IODA_INVALID_PE) { 805 rc = opal_pci_set_peltv(phb->opal_id, pdn->pe_number, 806 pe->pe_number, 807 OPAL_REMOVE_PE_FROM_DOMAIN); 808 /* XXX What to do in case of error ? */ 809 } 810 parent = parent->bus->self; 811 } 812 813 opal_pci_eeh_freeze_clear(phb->opal_id, pe->pe_number, 814 OPAL_EEH_ACTION_CLEAR_FREEZE_ALL); 815 816 /* Disassociate PE in PELT */ 817 rc = opal_pci_set_peltv(phb->opal_id, pe->pe_number, 818 pe->pe_number, OPAL_REMOVE_PE_FROM_DOMAIN); 819 if (rc) 820 pe_warn(pe, "OPAL error %lld remove self from PELTV\n", rc); 821 } 822 823 int pnv_ioda_deconfigure_pe(struct pnv_phb *phb, struct pnv_ioda_pe *pe) 824 { 825 struct pci_dev *parent; 826 uint8_t bcomp, dcomp, fcomp; 827 int64_t rc; 828 long rid_end, rid; 829 830 /* Currently, we just deconfigure VF PE. Bus PE will always there.*/ 831 if (pe->pbus) { 832 int count; 833 834 dcomp = OPAL_IGNORE_RID_DEVICE_NUMBER; 835 fcomp = OPAL_IGNORE_RID_FUNCTION_NUMBER; 836 parent = pe->pbus->self; 837 if (pe->flags & PNV_IODA_PE_BUS_ALL) 838 count = resource_size(&pe->pbus->busn_res); 839 else 840 count = 1; 841 842 switch(count) { 843 case 1: bcomp = OpalPciBusAll; break; 844 case 2: bcomp = OpalPciBus7Bits; break; 845 case 4: bcomp = OpalPciBus6Bits; break; 846 case 8: bcomp = OpalPciBus5Bits; break; 847 case 16: bcomp = OpalPciBus4Bits; break; 848 case 32: bcomp = OpalPciBus3Bits; break; 849 default: 850 dev_err(&pe->pbus->dev, "Number of subordinate buses %d unsupported\n", 851 count); 852 /* Do an exact match only */ 853 bcomp = OpalPciBusAll; 854 } 855 rid_end = pe->rid + (count << 8); 856 } else { 857 #ifdef CONFIG_PCI_IOV 858 if (pe->flags & PNV_IODA_PE_VF) 859 parent = pe->parent_dev; 860 else 861 #endif 862 parent = pe->pdev->bus->self; 863 bcomp = OpalPciBusAll; 864 dcomp = OPAL_COMPARE_RID_DEVICE_NUMBER; 865 fcomp = OPAL_COMPARE_RID_FUNCTION_NUMBER; 866 rid_end = pe->rid + 1; 867 } 868 869 /* Clear the reverse map */ 870 for (rid = pe->rid; rid < rid_end; rid++) 871 phb->ioda.pe_rmap[rid] = IODA_INVALID_PE; 872 873 /* 874 * Release from all parents PELT-V. NPUs don't have a PELTV 875 * table 876 */ 877 if (phb->type != PNV_PHB_NPU_OCAPI) 878 pnv_ioda_unset_peltv(phb, pe, parent); 879 880 rc = opal_pci_set_pe(phb->opal_id, pe->pe_number, pe->rid, 881 bcomp, dcomp, fcomp, OPAL_UNMAP_PE); 882 if (rc) 883 pe_err(pe, "OPAL error %lld trying to setup PELT table\n", rc); 884 885 pe->pbus = NULL; 886 pe->pdev = NULL; 887 #ifdef CONFIG_PCI_IOV 888 pe->parent_dev = NULL; 889 #endif 890 891 return 0; 892 } 893 894 int pnv_ioda_configure_pe(struct pnv_phb *phb, struct pnv_ioda_pe *pe) 895 { 896 uint8_t bcomp, dcomp, fcomp; 897 long rc, rid_end, rid; 898 899 /* Bus validation ? */ 900 if (pe->pbus) { 901 int count; 902 903 dcomp = OPAL_IGNORE_RID_DEVICE_NUMBER; 904 fcomp = OPAL_IGNORE_RID_FUNCTION_NUMBER; 905 if (pe->flags & PNV_IODA_PE_BUS_ALL) 906 count = resource_size(&pe->pbus->busn_res); 907 else 908 count = 1; 909 910 switch(count) { 911 case 1: bcomp = OpalPciBusAll; break; 912 case 2: bcomp = OpalPciBus7Bits; break; 913 case 4: bcomp = OpalPciBus6Bits; break; 914 case 8: bcomp = OpalPciBus5Bits; break; 915 case 16: bcomp = OpalPciBus4Bits; break; 916 case 32: bcomp = OpalPciBus3Bits; break; 917 default: 918 dev_err(&pe->pbus->dev, "Number of subordinate buses %d unsupported\n", 919 count); 920 /* Do an exact match only */ 921 bcomp = OpalPciBusAll; 922 } 923 rid_end = pe->rid + (count << 8); 924 } else { 925 bcomp = OpalPciBusAll; 926 dcomp = OPAL_COMPARE_RID_DEVICE_NUMBER; 927 fcomp = OPAL_COMPARE_RID_FUNCTION_NUMBER; 928 rid_end = pe->rid + 1; 929 } 930 931 /* 932 * Associate PE in PELT. We need add the PE into the 933 * corresponding PELT-V as well. Otherwise, the error 934 * originated from the PE might contribute to other 935 * PEs. 936 */ 937 rc = opal_pci_set_pe(phb->opal_id, pe->pe_number, pe->rid, 938 bcomp, dcomp, fcomp, OPAL_MAP_PE); 939 if (rc) { 940 pe_err(pe, "OPAL error %ld trying to setup PELT table\n", rc); 941 return -ENXIO; 942 } 943 944 /* 945 * Configure PELTV. NPUs don't have a PELTV table so skip 946 * configuration on them. 947 */ 948 if (phb->type != PNV_PHB_NPU_OCAPI) 949 pnv_ioda_set_peltv(phb, pe, true); 950 951 /* Setup reverse map */ 952 for (rid = pe->rid; rid < rid_end; rid++) 953 phb->ioda.pe_rmap[rid] = pe->pe_number; 954 955 /* Setup one MVTs on IODA1 */ 956 if (phb->type != PNV_PHB_IODA1) { 957 pe->mve_number = 0; 958 goto out; 959 } 960 961 pe->mve_number = pe->pe_number; 962 rc = opal_pci_set_mve(phb->opal_id, pe->mve_number, pe->pe_number); 963 if (rc != OPAL_SUCCESS) { 964 pe_err(pe, "OPAL error %ld setting up MVE %x\n", 965 rc, pe->mve_number); 966 pe->mve_number = -1; 967 } else { 968 rc = opal_pci_set_mve_enable(phb->opal_id, 969 pe->mve_number, OPAL_ENABLE_MVE); 970 if (rc) { 971 pe_err(pe, "OPAL error %ld enabling MVE %x\n", 972 rc, pe->mve_number); 973 pe->mve_number = -1; 974 } 975 } 976 977 out: 978 return 0; 979 } 980 981 static struct pnv_ioda_pe *pnv_ioda_setup_dev_PE(struct pci_dev *dev) 982 { 983 struct pnv_phb *phb = pci_bus_to_pnvhb(dev->bus); 984 struct pci_dn *pdn = pci_get_pdn(dev); 985 struct pnv_ioda_pe *pe; 986 987 if (!pdn) { 988 pr_err("%s: Device tree node not associated properly\n", 989 pci_name(dev)); 990 return NULL; 991 } 992 if (pdn->pe_number != IODA_INVALID_PE) 993 return NULL; 994 995 pe = pnv_ioda_alloc_pe(phb, 1); 996 if (!pe) { 997 pr_warn("%s: Not enough PE# available, disabling device\n", 998 pci_name(dev)); 999 return NULL; 1000 } 1001 1002 /* NOTE: We don't get a reference for the pointer in the PE 1003 * data structure, both the device and PE structures should be 1004 * destroyed at the same time. 1005 * 1006 * At some point we want to remove the PDN completely anyways 1007 */ 1008 pdn->pe_number = pe->pe_number; 1009 pe->flags = PNV_IODA_PE_DEV; 1010 pe->pdev = dev; 1011 pe->pbus = NULL; 1012 pe->mve_number = -1; 1013 pe->rid = dev->bus->number << 8 | pdn->devfn; 1014 pe->device_count++; 1015 1016 pe_info(pe, "Associated device to PE\n"); 1017 1018 if (pnv_ioda_configure_pe(phb, pe)) { 1019 /* XXX What do we do here ? */ 1020 pnv_ioda_free_pe(pe); 1021 pdn->pe_number = IODA_INVALID_PE; 1022 pe->pdev = NULL; 1023 return NULL; 1024 } 1025 1026 /* Put PE to the list */ 1027 mutex_lock(&phb->ioda.pe_list_mutex); 1028 list_add_tail(&pe->list, &phb->ioda.pe_list); 1029 mutex_unlock(&phb->ioda.pe_list_mutex); 1030 return pe; 1031 } 1032 1033 /* 1034 * There're 2 types of PCI bus sensitive PEs: One that is compromised of 1035 * single PCI bus. Another one that contains the primary PCI bus and its 1036 * subordinate PCI devices and buses. The second type of PE is normally 1037 * orgiriated by PCIe-to-PCI bridge or PLX switch downstream ports. 1038 */ 1039 static struct pnv_ioda_pe *pnv_ioda_setup_bus_PE(struct pci_bus *bus, bool all) 1040 { 1041 struct pnv_phb *phb = pci_bus_to_pnvhb(bus); 1042 struct pnv_ioda_pe *pe = NULL; 1043 unsigned int pe_num; 1044 1045 /* 1046 * In partial hotplug case, the PE instance might be still alive. 1047 * We should reuse it instead of allocating a new one. 1048 */ 1049 pe_num = phb->ioda.pe_rmap[bus->number << 8]; 1050 if (WARN_ON(pe_num != IODA_INVALID_PE)) { 1051 pe = &phb->ioda.pe_array[pe_num]; 1052 return NULL; 1053 } 1054 1055 /* PE number for root bus should have been reserved */ 1056 if (pci_is_root_bus(bus)) 1057 pe = &phb->ioda.pe_array[phb->ioda.root_pe_idx]; 1058 1059 /* Check if PE is determined by M64 */ 1060 if (!pe) 1061 pe = pnv_ioda_pick_m64_pe(bus, all); 1062 1063 /* The PE number isn't pinned by M64 */ 1064 if (!pe) 1065 pe = pnv_ioda_alloc_pe(phb, 1); 1066 1067 if (!pe) { 1068 pr_warn("%s: Not enough PE# available for PCI bus %04x:%02x\n", 1069 __func__, pci_domain_nr(bus), bus->number); 1070 return NULL; 1071 } 1072 1073 pe->flags |= (all ? PNV_IODA_PE_BUS_ALL : PNV_IODA_PE_BUS); 1074 pe->pbus = bus; 1075 pe->pdev = NULL; 1076 pe->mve_number = -1; 1077 pe->rid = bus->busn_res.start << 8; 1078 1079 if (all) 1080 pe_info(pe, "Secondary bus %pad..%pad associated with PE#%x\n", 1081 &bus->busn_res.start, &bus->busn_res.end, 1082 pe->pe_number); 1083 else 1084 pe_info(pe, "Secondary bus %pad associated with PE#%x\n", 1085 &bus->busn_res.start, pe->pe_number); 1086 1087 if (pnv_ioda_configure_pe(phb, pe)) { 1088 /* XXX What do we do here ? */ 1089 pnv_ioda_free_pe(pe); 1090 pe->pbus = NULL; 1091 return NULL; 1092 } 1093 1094 /* Put PE to the list */ 1095 list_add_tail(&pe->list, &phb->ioda.pe_list); 1096 1097 return pe; 1098 } 1099 1100 static void pnv_pci_ioda1_setup_dma_pe(struct pnv_phb *phb, 1101 struct pnv_ioda_pe *pe); 1102 1103 static void pnv_pci_ioda_dma_dev_setup(struct pci_dev *pdev) 1104 { 1105 struct pnv_phb *phb = pci_bus_to_pnvhb(pdev->bus); 1106 struct pci_dn *pdn = pci_get_pdn(pdev); 1107 struct pnv_ioda_pe *pe; 1108 1109 /* Check if the BDFN for this device is associated with a PE yet */ 1110 pe = pnv_pci_bdfn_to_pe(phb, pdev->devfn | (pdev->bus->number << 8)); 1111 if (!pe) { 1112 /* VF PEs should be pre-configured in pnv_pci_sriov_enable() */ 1113 if (WARN_ON(pdev->is_virtfn)) 1114 return; 1115 1116 pnv_pci_configure_bus(pdev->bus); 1117 pe = pnv_pci_bdfn_to_pe(phb, pdev->devfn | (pdev->bus->number << 8)); 1118 pci_info(pdev, "Configured PE#%x\n", pe ? pe->pe_number : 0xfffff); 1119 1120 1121 /* 1122 * If we can't setup the IODA PE something has gone horribly 1123 * wrong and we can't enable DMA for the device. 1124 */ 1125 if (WARN_ON(!pe)) 1126 return; 1127 } else { 1128 pci_info(pdev, "Added to existing PE#%x\n", pe->pe_number); 1129 } 1130 1131 /* 1132 * We assume that bridges *probably* don't need to do any DMA so we can 1133 * skip allocating a TCE table, etc unless we get a non-bridge device. 1134 */ 1135 if (!pe->dma_setup_done && !pci_is_bridge(pdev)) { 1136 switch (phb->type) { 1137 case PNV_PHB_IODA1: 1138 pnv_pci_ioda1_setup_dma_pe(phb, pe); 1139 break; 1140 case PNV_PHB_IODA2: 1141 pnv_pci_ioda2_setup_dma_pe(phb, pe); 1142 break; 1143 default: 1144 pr_warn("%s: No DMA for PHB#%x (type %d)\n", 1145 __func__, phb->hose->global_number, phb->type); 1146 } 1147 } 1148 1149 if (pdn) 1150 pdn->pe_number = pe->pe_number; 1151 pe->device_count++; 1152 1153 WARN_ON(get_dma_ops(&pdev->dev) != &dma_iommu_ops); 1154 pdev->dev.archdata.dma_offset = pe->tce_bypass_base; 1155 set_iommu_table_base(&pdev->dev, pe->table_group.tables[0]); 1156 1157 /* PEs with a DMA weight of zero won't have a group */ 1158 if (pe->table_group.group) 1159 iommu_add_device(&pe->table_group, &pdev->dev); 1160 } 1161 1162 /* 1163 * Reconfigure TVE#0 to be usable as 64-bit DMA space. 1164 * 1165 * The first 4GB of virtual memory for a PE is reserved for 32-bit accesses. 1166 * Devices can only access more than that if bit 59 of the PCI address is set 1167 * by hardware, which indicates TVE#1 should be used instead of TVE#0. 1168 * Many PCI devices are not capable of addressing that many bits, and as a 1169 * result are limited to the 4GB of virtual memory made available to 32-bit 1170 * devices in TVE#0. 1171 * 1172 * In order to work around this, reconfigure TVE#0 to be suitable for 64-bit 1173 * devices by configuring the virtual memory past the first 4GB inaccessible 1174 * by 64-bit DMAs. This should only be used by devices that want more than 1175 * 4GB, and only on PEs that have no 32-bit devices. 1176 * 1177 * Currently this will only work on PHB3 (POWER8). 1178 */ 1179 static int pnv_pci_ioda_dma_64bit_bypass(struct pnv_ioda_pe *pe) 1180 { 1181 u64 window_size, table_size, tce_count, addr; 1182 struct page *table_pages; 1183 u64 tce_order = 28; /* 256MB TCEs */ 1184 __be64 *tces; 1185 s64 rc; 1186 1187 /* 1188 * Window size needs to be a power of two, but needs to account for 1189 * shifting memory by the 4GB offset required to skip 32bit space. 1190 */ 1191 window_size = roundup_pow_of_two(memory_hotplug_max() + (1ULL << 32)); 1192 tce_count = window_size >> tce_order; 1193 table_size = tce_count << 3; 1194 1195 if (table_size < PAGE_SIZE) 1196 table_size = PAGE_SIZE; 1197 1198 table_pages = alloc_pages_node(pe->phb->hose->node, GFP_KERNEL, 1199 get_order(table_size)); 1200 if (!table_pages) 1201 goto err; 1202 1203 tces = page_address(table_pages); 1204 if (!tces) 1205 goto err; 1206 1207 memset(tces, 0, table_size); 1208 1209 for (addr = 0; addr < memory_hotplug_max(); addr += (1 << tce_order)) { 1210 tces[(addr + (1ULL << 32)) >> tce_order] = 1211 cpu_to_be64(addr | TCE_PCI_READ | TCE_PCI_WRITE); 1212 } 1213 1214 rc = opal_pci_map_pe_dma_window(pe->phb->opal_id, 1215 pe->pe_number, 1216 /* reconfigure window 0 */ 1217 (pe->pe_number << 1) + 0, 1218 1, 1219 __pa(tces), 1220 table_size, 1221 1 << tce_order); 1222 if (rc == OPAL_SUCCESS) { 1223 pe_info(pe, "Using 64-bit DMA iommu bypass (through TVE#0)\n"); 1224 return 0; 1225 } 1226 err: 1227 pe_err(pe, "Error configuring 64-bit DMA bypass\n"); 1228 return -EIO; 1229 } 1230 1231 static bool pnv_pci_ioda_iommu_bypass_supported(struct pci_dev *pdev, 1232 u64 dma_mask) 1233 { 1234 struct pnv_phb *phb = pci_bus_to_pnvhb(pdev->bus); 1235 struct pci_dn *pdn = pci_get_pdn(pdev); 1236 struct pnv_ioda_pe *pe; 1237 1238 if (WARN_ON(!pdn || pdn->pe_number == IODA_INVALID_PE)) 1239 return false; 1240 1241 pe = &phb->ioda.pe_array[pdn->pe_number]; 1242 if (pe->tce_bypass_enabled) { 1243 u64 top = pe->tce_bypass_base + memblock_end_of_DRAM() - 1; 1244 if (dma_mask >= top) 1245 return true; 1246 } 1247 1248 /* 1249 * If the device can't set the TCE bypass bit but still wants 1250 * to access 4GB or more, on PHB3 we can reconfigure TVE#0 to 1251 * bypass the 32-bit region and be usable for 64-bit DMAs. 1252 * The device needs to be able to address all of this space. 1253 */ 1254 if (dma_mask >> 32 && 1255 dma_mask > (memory_hotplug_max() + (1ULL << 32)) && 1256 /* pe->pdev should be set if it's a single device, pe->pbus if not */ 1257 (pe->device_count == 1 || !pe->pbus) && 1258 phb->model == PNV_PHB_MODEL_PHB3) { 1259 /* Configure the bypass mode */ 1260 s64 rc = pnv_pci_ioda_dma_64bit_bypass(pe); 1261 if (rc) 1262 return false; 1263 /* 4GB offset bypasses 32-bit space */ 1264 pdev->dev.archdata.dma_offset = (1ULL << 32); 1265 return true; 1266 } 1267 1268 return false; 1269 } 1270 1271 static inline __be64 __iomem *pnv_ioda_get_inval_reg(struct pnv_phb *phb, 1272 bool real_mode) 1273 { 1274 return real_mode ? (__be64 __iomem *)(phb->regs_phys + 0x210) : 1275 (phb->regs + 0x210); 1276 } 1277 1278 static void pnv_pci_p7ioc_tce_invalidate(struct iommu_table *tbl, 1279 unsigned long index, unsigned long npages, bool rm) 1280 { 1281 struct iommu_table_group_link *tgl = list_first_entry_or_null( 1282 &tbl->it_group_list, struct iommu_table_group_link, 1283 next); 1284 struct pnv_ioda_pe *pe = container_of(tgl->table_group, 1285 struct pnv_ioda_pe, table_group); 1286 __be64 __iomem *invalidate = pnv_ioda_get_inval_reg(pe->phb, rm); 1287 unsigned long start, end, inc; 1288 1289 start = __pa(((__be64 *)tbl->it_base) + index - tbl->it_offset); 1290 end = __pa(((__be64 *)tbl->it_base) + index - tbl->it_offset + 1291 npages - 1); 1292 1293 /* p7ioc-style invalidation, 2 TCEs per write */ 1294 start |= (1ull << 63); 1295 end |= (1ull << 63); 1296 inc = 16; 1297 end |= inc - 1; /* round up end to be different than start */ 1298 1299 mb(); /* Ensure above stores are visible */ 1300 while (start <= end) { 1301 if (rm) 1302 __raw_rm_writeq_be(start, invalidate); 1303 else 1304 __raw_writeq_be(start, invalidate); 1305 1306 start += inc; 1307 } 1308 1309 /* 1310 * The iommu layer will do another mb() for us on build() 1311 * and we don't care on free() 1312 */ 1313 } 1314 1315 static int pnv_ioda1_tce_build(struct iommu_table *tbl, long index, 1316 long npages, unsigned long uaddr, 1317 enum dma_data_direction direction, 1318 unsigned long attrs) 1319 { 1320 int ret = pnv_tce_build(tbl, index, npages, uaddr, direction, 1321 attrs); 1322 1323 if (!ret) 1324 pnv_pci_p7ioc_tce_invalidate(tbl, index, npages, false); 1325 1326 return ret; 1327 } 1328 1329 #ifdef CONFIG_IOMMU_API 1330 /* Common for IODA1 and IODA2 */ 1331 static int pnv_ioda_tce_xchg_no_kill(struct iommu_table *tbl, long index, 1332 unsigned long *hpa, enum dma_data_direction *direction, 1333 bool realmode) 1334 { 1335 return pnv_tce_xchg(tbl, index, hpa, direction, !realmode); 1336 } 1337 #endif 1338 1339 static void pnv_ioda1_tce_free(struct iommu_table *tbl, long index, 1340 long npages) 1341 { 1342 pnv_tce_free(tbl, index, npages); 1343 1344 pnv_pci_p7ioc_tce_invalidate(tbl, index, npages, false); 1345 } 1346 1347 static struct iommu_table_ops pnv_ioda1_iommu_ops = { 1348 .set = pnv_ioda1_tce_build, 1349 #ifdef CONFIG_IOMMU_API 1350 .xchg_no_kill = pnv_ioda_tce_xchg_no_kill, 1351 .tce_kill = pnv_pci_p7ioc_tce_invalidate, 1352 .useraddrptr = pnv_tce_useraddrptr, 1353 #endif 1354 .clear = pnv_ioda1_tce_free, 1355 .get = pnv_tce_get, 1356 }; 1357 1358 #define PHB3_TCE_KILL_INVAL_ALL PPC_BIT(0) 1359 #define PHB3_TCE_KILL_INVAL_PE PPC_BIT(1) 1360 #define PHB3_TCE_KILL_INVAL_ONE PPC_BIT(2) 1361 1362 static inline void pnv_pci_phb3_tce_invalidate_pe(struct pnv_ioda_pe *pe) 1363 { 1364 /* 01xb - invalidate TCEs that match the specified PE# */ 1365 __be64 __iomem *invalidate = pnv_ioda_get_inval_reg(pe->phb, false); 1366 unsigned long val = PHB3_TCE_KILL_INVAL_PE | (pe->pe_number & 0xFF); 1367 1368 mb(); /* Ensure above stores are visible */ 1369 __raw_writeq_be(val, invalidate); 1370 } 1371 1372 static void pnv_pci_phb3_tce_invalidate(struct pnv_ioda_pe *pe, bool rm, 1373 unsigned shift, unsigned long index, 1374 unsigned long npages) 1375 { 1376 __be64 __iomem *invalidate = pnv_ioda_get_inval_reg(pe->phb, rm); 1377 unsigned long start, end, inc; 1378 1379 /* We'll invalidate DMA address in PE scope */ 1380 start = PHB3_TCE_KILL_INVAL_ONE; 1381 start |= (pe->pe_number & 0xFF); 1382 end = start; 1383 1384 /* Figure out the start, end and step */ 1385 start |= (index << shift); 1386 end |= ((index + npages - 1) << shift); 1387 inc = (0x1ull << shift); 1388 mb(); 1389 1390 while (start <= end) { 1391 if (rm) 1392 __raw_rm_writeq_be(start, invalidate); 1393 else 1394 __raw_writeq_be(start, invalidate); 1395 start += inc; 1396 } 1397 } 1398 1399 static inline void pnv_pci_ioda2_tce_invalidate_pe(struct pnv_ioda_pe *pe) 1400 { 1401 struct pnv_phb *phb = pe->phb; 1402 1403 if (phb->model == PNV_PHB_MODEL_PHB3 && phb->regs) 1404 pnv_pci_phb3_tce_invalidate_pe(pe); 1405 else 1406 opal_pci_tce_kill(phb->opal_id, OPAL_PCI_TCE_KILL_PE, 1407 pe->pe_number, 0, 0, 0); 1408 } 1409 1410 static void pnv_pci_ioda2_tce_invalidate(struct iommu_table *tbl, 1411 unsigned long index, unsigned long npages, bool rm) 1412 { 1413 struct iommu_table_group_link *tgl; 1414 1415 list_for_each_entry_lockless(tgl, &tbl->it_group_list, next) { 1416 struct pnv_ioda_pe *pe = container_of(tgl->table_group, 1417 struct pnv_ioda_pe, table_group); 1418 struct pnv_phb *phb = pe->phb; 1419 unsigned int shift = tbl->it_page_shift; 1420 1421 if (phb->model == PNV_PHB_MODEL_PHB3 && phb->regs) 1422 pnv_pci_phb3_tce_invalidate(pe, rm, shift, 1423 index, npages); 1424 else 1425 opal_pci_tce_kill(phb->opal_id, 1426 OPAL_PCI_TCE_KILL_PAGES, 1427 pe->pe_number, 1u << shift, 1428 index << shift, npages); 1429 } 1430 } 1431 1432 static int pnv_ioda2_tce_build(struct iommu_table *tbl, long index, 1433 long npages, unsigned long uaddr, 1434 enum dma_data_direction direction, 1435 unsigned long attrs) 1436 { 1437 int ret = pnv_tce_build(tbl, index, npages, uaddr, direction, 1438 attrs); 1439 1440 if (!ret) 1441 pnv_pci_ioda2_tce_invalidate(tbl, index, npages, false); 1442 1443 return ret; 1444 } 1445 1446 static void pnv_ioda2_tce_free(struct iommu_table *tbl, long index, 1447 long npages) 1448 { 1449 pnv_tce_free(tbl, index, npages); 1450 1451 pnv_pci_ioda2_tce_invalidate(tbl, index, npages, false); 1452 } 1453 1454 static struct iommu_table_ops pnv_ioda2_iommu_ops = { 1455 .set = pnv_ioda2_tce_build, 1456 #ifdef CONFIG_IOMMU_API 1457 .xchg_no_kill = pnv_ioda_tce_xchg_no_kill, 1458 .tce_kill = pnv_pci_ioda2_tce_invalidate, 1459 .useraddrptr = pnv_tce_useraddrptr, 1460 #endif 1461 .clear = pnv_ioda2_tce_free, 1462 .get = pnv_tce_get, 1463 .free = pnv_pci_ioda2_table_free_pages, 1464 }; 1465 1466 static int pnv_pci_ioda_dev_dma_weight(struct pci_dev *dev, void *data) 1467 { 1468 unsigned int *weight = (unsigned int *)data; 1469 1470 /* This is quite simplistic. The "base" weight of a device 1471 * is 10. 0 means no DMA is to be accounted for it. 1472 */ 1473 if (dev->hdr_type != PCI_HEADER_TYPE_NORMAL) 1474 return 0; 1475 1476 if (dev->class == PCI_CLASS_SERIAL_USB_UHCI || 1477 dev->class == PCI_CLASS_SERIAL_USB_OHCI || 1478 dev->class == PCI_CLASS_SERIAL_USB_EHCI) 1479 *weight += 3; 1480 else if ((dev->class >> 8) == PCI_CLASS_STORAGE_RAID) 1481 *weight += 15; 1482 else 1483 *weight += 10; 1484 1485 return 0; 1486 } 1487 1488 static unsigned int pnv_pci_ioda_pe_dma_weight(struct pnv_ioda_pe *pe) 1489 { 1490 unsigned int weight = 0; 1491 1492 /* SRIOV VF has same DMA32 weight as its PF */ 1493 #ifdef CONFIG_PCI_IOV 1494 if ((pe->flags & PNV_IODA_PE_VF) && pe->parent_dev) { 1495 pnv_pci_ioda_dev_dma_weight(pe->parent_dev, &weight); 1496 return weight; 1497 } 1498 #endif 1499 1500 if ((pe->flags & PNV_IODA_PE_DEV) && pe->pdev) { 1501 pnv_pci_ioda_dev_dma_weight(pe->pdev, &weight); 1502 } else if ((pe->flags & PNV_IODA_PE_BUS) && pe->pbus) { 1503 struct pci_dev *pdev; 1504 1505 list_for_each_entry(pdev, &pe->pbus->devices, bus_list) 1506 pnv_pci_ioda_dev_dma_weight(pdev, &weight); 1507 } else if ((pe->flags & PNV_IODA_PE_BUS_ALL) && pe->pbus) { 1508 pci_walk_bus(pe->pbus, pnv_pci_ioda_dev_dma_weight, &weight); 1509 } 1510 1511 return weight; 1512 } 1513 1514 static void pnv_pci_ioda1_setup_dma_pe(struct pnv_phb *phb, 1515 struct pnv_ioda_pe *pe) 1516 { 1517 1518 struct page *tce_mem = NULL; 1519 struct iommu_table *tbl; 1520 unsigned int weight, total_weight = 0; 1521 unsigned int tce32_segsz, base, segs, avail, i; 1522 int64_t rc; 1523 void *addr; 1524 1525 /* XXX FIXME: Handle 64-bit only DMA devices */ 1526 /* XXX FIXME: Provide 64-bit DMA facilities & non-4K TCE tables etc.. */ 1527 /* XXX FIXME: Allocate multi-level tables on PHB3 */ 1528 weight = pnv_pci_ioda_pe_dma_weight(pe); 1529 if (!weight) 1530 return; 1531 1532 pci_walk_bus(phb->hose->bus, pnv_pci_ioda_dev_dma_weight, 1533 &total_weight); 1534 segs = (weight * phb->ioda.dma32_count) / total_weight; 1535 if (!segs) 1536 segs = 1; 1537 1538 /* 1539 * Allocate contiguous DMA32 segments. We begin with the expected 1540 * number of segments. With one more attempt, the number of DMA32 1541 * segments to be allocated is decreased by one until one segment 1542 * is allocated successfully. 1543 */ 1544 do { 1545 for (base = 0; base <= phb->ioda.dma32_count - segs; base++) { 1546 for (avail = 0, i = base; i < base + segs; i++) { 1547 if (phb->ioda.dma32_segmap[i] == 1548 IODA_INVALID_PE) 1549 avail++; 1550 } 1551 1552 if (avail == segs) 1553 goto found; 1554 } 1555 } while (--segs); 1556 1557 if (!segs) { 1558 pe_warn(pe, "No available DMA32 segments\n"); 1559 return; 1560 } 1561 1562 found: 1563 tbl = pnv_pci_table_alloc(phb->hose->node); 1564 if (WARN_ON(!tbl)) 1565 return; 1566 1567 iommu_register_group(&pe->table_group, phb->hose->global_number, 1568 pe->pe_number); 1569 pnv_pci_link_table_and_group(phb->hose->node, 0, tbl, &pe->table_group); 1570 1571 /* Grab a 32-bit TCE table */ 1572 pe_info(pe, "DMA weight %d (%d), assigned (%d) %d DMA32 segments\n", 1573 weight, total_weight, base, segs); 1574 pe_info(pe, " Setting up 32-bit TCE table at %08x..%08x\n", 1575 base * PNV_IODA1_DMA32_SEGSIZE, 1576 (base + segs) * PNV_IODA1_DMA32_SEGSIZE - 1); 1577 1578 /* XXX Currently, we allocate one big contiguous table for the 1579 * TCEs. We only really need one chunk per 256M of TCE space 1580 * (ie per segment) but that's an optimization for later, it 1581 * requires some added smarts with our get/put_tce implementation 1582 * 1583 * Each TCE page is 4KB in size and each TCE entry occupies 8 1584 * bytes 1585 */ 1586 tce32_segsz = PNV_IODA1_DMA32_SEGSIZE >> (IOMMU_PAGE_SHIFT_4K - 3); 1587 tce_mem = alloc_pages_node(phb->hose->node, GFP_KERNEL, 1588 get_order(tce32_segsz * segs)); 1589 if (!tce_mem) { 1590 pe_err(pe, " Failed to allocate a 32-bit TCE memory\n"); 1591 goto fail; 1592 } 1593 addr = page_address(tce_mem); 1594 memset(addr, 0, tce32_segsz * segs); 1595 1596 /* Configure HW */ 1597 for (i = 0; i < segs; i++) { 1598 rc = opal_pci_map_pe_dma_window(phb->opal_id, 1599 pe->pe_number, 1600 base + i, 1, 1601 __pa(addr) + tce32_segsz * i, 1602 tce32_segsz, IOMMU_PAGE_SIZE_4K); 1603 if (rc) { 1604 pe_err(pe, " Failed to configure 32-bit TCE table, err %lld\n", 1605 rc); 1606 goto fail; 1607 } 1608 } 1609 1610 /* Setup DMA32 segment mapping */ 1611 for (i = base; i < base + segs; i++) 1612 phb->ioda.dma32_segmap[i] = pe->pe_number; 1613 1614 /* Setup linux iommu table */ 1615 pnv_pci_setup_iommu_table(tbl, addr, tce32_segsz * segs, 1616 base * PNV_IODA1_DMA32_SEGSIZE, 1617 IOMMU_PAGE_SHIFT_4K); 1618 1619 tbl->it_ops = &pnv_ioda1_iommu_ops; 1620 pe->table_group.tce32_start = tbl->it_offset << tbl->it_page_shift; 1621 pe->table_group.tce32_size = tbl->it_size << tbl->it_page_shift; 1622 if (!iommu_init_table(tbl, phb->hose->node, 0, 0)) 1623 panic("Failed to initialize iommu table"); 1624 1625 pe->dma_setup_done = true; 1626 return; 1627 fail: 1628 /* XXX Failure: Try to fallback to 64-bit only ? */ 1629 if (tce_mem) 1630 __free_pages(tce_mem, get_order(tce32_segsz * segs)); 1631 if (tbl) { 1632 pnv_pci_unlink_table_and_group(tbl, &pe->table_group); 1633 iommu_tce_table_put(tbl); 1634 } 1635 } 1636 1637 static long pnv_pci_ioda2_set_window(struct iommu_table_group *table_group, 1638 int num, struct iommu_table *tbl) 1639 { 1640 struct pnv_ioda_pe *pe = container_of(table_group, struct pnv_ioda_pe, 1641 table_group); 1642 struct pnv_phb *phb = pe->phb; 1643 int64_t rc; 1644 const unsigned long size = tbl->it_indirect_levels ? 1645 tbl->it_level_size : tbl->it_size; 1646 const __u64 start_addr = tbl->it_offset << tbl->it_page_shift; 1647 const __u64 win_size = tbl->it_size << tbl->it_page_shift; 1648 1649 pe_info(pe, "Setting up window#%d %llx..%llx pg=%lx\n", 1650 num, start_addr, start_addr + win_size - 1, 1651 IOMMU_PAGE_SIZE(tbl)); 1652 1653 /* 1654 * Map TCE table through TVT. The TVE index is the PE number 1655 * shifted by 1 bit for 32-bits DMA space. 1656 */ 1657 rc = opal_pci_map_pe_dma_window(phb->opal_id, 1658 pe->pe_number, 1659 (pe->pe_number << 1) + num, 1660 tbl->it_indirect_levels + 1, 1661 __pa(tbl->it_base), 1662 size << 3, 1663 IOMMU_PAGE_SIZE(tbl)); 1664 if (rc) { 1665 pe_err(pe, "Failed to configure TCE table, err %lld\n", rc); 1666 return rc; 1667 } 1668 1669 pnv_pci_link_table_and_group(phb->hose->node, num, 1670 tbl, &pe->table_group); 1671 pnv_pci_ioda2_tce_invalidate_pe(pe); 1672 1673 return 0; 1674 } 1675 1676 static void pnv_pci_ioda2_set_bypass(struct pnv_ioda_pe *pe, bool enable) 1677 { 1678 uint16_t window_id = (pe->pe_number << 1 ) + 1; 1679 int64_t rc; 1680 1681 pe_info(pe, "%sabling 64-bit DMA bypass\n", enable ? "En" : "Dis"); 1682 if (enable) { 1683 phys_addr_t top = memblock_end_of_DRAM(); 1684 1685 top = roundup_pow_of_two(top); 1686 rc = opal_pci_map_pe_dma_window_real(pe->phb->opal_id, 1687 pe->pe_number, 1688 window_id, 1689 pe->tce_bypass_base, 1690 top); 1691 } else { 1692 rc = opal_pci_map_pe_dma_window_real(pe->phb->opal_id, 1693 pe->pe_number, 1694 window_id, 1695 pe->tce_bypass_base, 1696 0); 1697 } 1698 if (rc) 1699 pe_err(pe, "OPAL error %lld configuring bypass window\n", rc); 1700 else 1701 pe->tce_bypass_enabled = enable; 1702 } 1703 1704 static long pnv_pci_ioda2_create_table(struct iommu_table_group *table_group, 1705 int num, __u32 page_shift, __u64 window_size, __u32 levels, 1706 bool alloc_userspace_copy, struct iommu_table **ptbl) 1707 { 1708 struct pnv_ioda_pe *pe = container_of(table_group, struct pnv_ioda_pe, 1709 table_group); 1710 int nid = pe->phb->hose->node; 1711 __u64 bus_offset = num ? pe->tce_bypass_base : table_group->tce32_start; 1712 long ret; 1713 struct iommu_table *tbl; 1714 1715 tbl = pnv_pci_table_alloc(nid); 1716 if (!tbl) 1717 return -ENOMEM; 1718 1719 tbl->it_ops = &pnv_ioda2_iommu_ops; 1720 1721 ret = pnv_pci_ioda2_table_alloc_pages(nid, 1722 bus_offset, page_shift, window_size, 1723 levels, alloc_userspace_copy, tbl); 1724 if (ret) { 1725 iommu_tce_table_put(tbl); 1726 return ret; 1727 } 1728 1729 *ptbl = tbl; 1730 1731 return 0; 1732 } 1733 1734 static long pnv_pci_ioda2_setup_default_config(struct pnv_ioda_pe *pe) 1735 { 1736 struct iommu_table *tbl = NULL; 1737 long rc; 1738 unsigned long res_start, res_end; 1739 1740 /* 1741 * crashkernel= specifies the kdump kernel's maximum memory at 1742 * some offset and there is no guaranteed the result is a power 1743 * of 2, which will cause errors later. 1744 */ 1745 const u64 max_memory = __rounddown_pow_of_two(memory_hotplug_max()); 1746 1747 /* 1748 * In memory constrained environments, e.g. kdump kernel, the 1749 * DMA window can be larger than available memory, which will 1750 * cause errors later. 1751 */ 1752 const u64 maxblock = 1UL << (PAGE_SHIFT + MAX_ORDER - 1); 1753 1754 /* 1755 * We create the default window as big as we can. The constraint is 1756 * the max order of allocation possible. The TCE table is likely to 1757 * end up being multilevel and with on-demand allocation in place, 1758 * the initial use is not going to be huge as the default window aims 1759 * to support crippled devices (i.e. not fully 64bit DMAble) only. 1760 */ 1761 /* iommu_table::it_map uses 1 bit per IOMMU page, hence 8 */ 1762 const u64 window_size = min((maxblock * 8) << PAGE_SHIFT, max_memory); 1763 /* Each TCE level cannot exceed maxblock so go multilevel if needed */ 1764 unsigned long tces_order = ilog2(window_size >> PAGE_SHIFT); 1765 unsigned long tcelevel_order = ilog2(maxblock >> 3); 1766 unsigned int levels = tces_order / tcelevel_order; 1767 1768 if (tces_order % tcelevel_order) 1769 levels += 1; 1770 /* 1771 * We try to stick to default levels (which is >1 at the moment) in 1772 * order to save memory by relying on on-demain TCE level allocation. 1773 */ 1774 levels = max_t(unsigned int, levels, POWERNV_IOMMU_DEFAULT_LEVELS); 1775 1776 rc = pnv_pci_ioda2_create_table(&pe->table_group, 0, PAGE_SHIFT, 1777 window_size, levels, false, &tbl); 1778 if (rc) { 1779 pe_err(pe, "Failed to create 32-bit TCE table, err %ld", 1780 rc); 1781 return rc; 1782 } 1783 1784 /* We use top part of 32bit space for MMIO so exclude it from DMA */ 1785 res_start = 0; 1786 res_end = 0; 1787 if (window_size > pe->phb->ioda.m32_pci_base) { 1788 res_start = pe->phb->ioda.m32_pci_base >> tbl->it_page_shift; 1789 res_end = min(window_size, SZ_4G) >> tbl->it_page_shift; 1790 } 1791 1792 if (iommu_init_table(tbl, pe->phb->hose->node, res_start, res_end)) 1793 rc = pnv_pci_ioda2_set_window(&pe->table_group, 0, tbl); 1794 else 1795 rc = -ENOMEM; 1796 if (rc) { 1797 pe_err(pe, "Failed to configure 32-bit TCE table, err %ld\n", rc); 1798 iommu_tce_table_put(tbl); 1799 tbl = NULL; /* This clears iommu_table_base below */ 1800 } 1801 if (!pnv_iommu_bypass_disabled) 1802 pnv_pci_ioda2_set_bypass(pe, true); 1803 1804 /* 1805 * Set table base for the case of IOMMU DMA use. Usually this is done 1806 * from dma_dev_setup() which is not called when a device is returned 1807 * from VFIO so do it here. 1808 */ 1809 if (pe->pdev) 1810 set_iommu_table_base(&pe->pdev->dev, tbl); 1811 1812 return 0; 1813 } 1814 1815 static long pnv_pci_ioda2_unset_window(struct iommu_table_group *table_group, 1816 int num) 1817 { 1818 struct pnv_ioda_pe *pe = container_of(table_group, struct pnv_ioda_pe, 1819 table_group); 1820 struct pnv_phb *phb = pe->phb; 1821 long ret; 1822 1823 pe_info(pe, "Removing DMA window #%d\n", num); 1824 1825 ret = opal_pci_map_pe_dma_window(phb->opal_id, pe->pe_number, 1826 (pe->pe_number << 1) + num, 1827 0/* levels */, 0/* table address */, 1828 0/* table size */, 0/* page size */); 1829 if (ret) 1830 pe_warn(pe, "Unmapping failed, ret = %ld\n", ret); 1831 else 1832 pnv_pci_ioda2_tce_invalidate_pe(pe); 1833 1834 pnv_pci_unlink_table_and_group(table_group->tables[num], table_group); 1835 1836 return ret; 1837 } 1838 1839 #ifdef CONFIG_IOMMU_API 1840 unsigned long pnv_pci_ioda2_get_table_size(__u32 page_shift, 1841 __u64 window_size, __u32 levels) 1842 { 1843 unsigned long bytes = 0; 1844 const unsigned window_shift = ilog2(window_size); 1845 unsigned entries_shift = window_shift - page_shift; 1846 unsigned table_shift = entries_shift + 3; 1847 unsigned long tce_table_size = max(0x1000UL, 1UL << table_shift); 1848 unsigned long direct_table_size; 1849 1850 if (!levels || (levels > POWERNV_IOMMU_MAX_LEVELS) || 1851 !is_power_of_2(window_size)) 1852 return 0; 1853 1854 /* Calculate a direct table size from window_size and levels */ 1855 entries_shift = (entries_shift + levels - 1) / levels; 1856 table_shift = entries_shift + 3; 1857 table_shift = max_t(unsigned, table_shift, PAGE_SHIFT); 1858 direct_table_size = 1UL << table_shift; 1859 1860 for ( ; levels; --levels) { 1861 bytes += ALIGN(tce_table_size, direct_table_size); 1862 1863 tce_table_size /= direct_table_size; 1864 tce_table_size <<= 3; 1865 tce_table_size = max_t(unsigned long, 1866 tce_table_size, direct_table_size); 1867 } 1868 1869 return bytes + bytes; /* one for HW table, one for userspace copy */ 1870 } 1871 1872 static long pnv_pci_ioda2_create_table_userspace( 1873 struct iommu_table_group *table_group, 1874 int num, __u32 page_shift, __u64 window_size, __u32 levels, 1875 struct iommu_table **ptbl) 1876 { 1877 long ret = pnv_pci_ioda2_create_table(table_group, 1878 num, page_shift, window_size, levels, true, ptbl); 1879 1880 if (!ret) 1881 (*ptbl)->it_allocated_size = pnv_pci_ioda2_get_table_size( 1882 page_shift, window_size, levels); 1883 return ret; 1884 } 1885 1886 static void pnv_ioda_setup_bus_dma(struct pnv_ioda_pe *pe, struct pci_bus *bus) 1887 { 1888 struct pci_dev *dev; 1889 1890 list_for_each_entry(dev, &bus->devices, bus_list) { 1891 set_iommu_table_base(&dev->dev, pe->table_group.tables[0]); 1892 dev->dev.archdata.dma_offset = pe->tce_bypass_base; 1893 1894 if ((pe->flags & PNV_IODA_PE_BUS_ALL) && dev->subordinate) 1895 pnv_ioda_setup_bus_dma(pe, dev->subordinate); 1896 } 1897 } 1898 1899 static void pnv_ioda2_take_ownership(struct iommu_table_group *table_group) 1900 { 1901 struct pnv_ioda_pe *pe = container_of(table_group, struct pnv_ioda_pe, 1902 table_group); 1903 /* Store @tbl as pnv_pci_ioda2_unset_window() resets it */ 1904 struct iommu_table *tbl = pe->table_group.tables[0]; 1905 1906 pnv_pci_ioda2_set_bypass(pe, false); 1907 pnv_pci_ioda2_unset_window(&pe->table_group, 0); 1908 if (pe->pbus) 1909 pnv_ioda_setup_bus_dma(pe, pe->pbus); 1910 else if (pe->pdev) 1911 set_iommu_table_base(&pe->pdev->dev, NULL); 1912 iommu_tce_table_put(tbl); 1913 } 1914 1915 static void pnv_ioda2_release_ownership(struct iommu_table_group *table_group) 1916 { 1917 struct pnv_ioda_pe *pe = container_of(table_group, struct pnv_ioda_pe, 1918 table_group); 1919 1920 pnv_pci_ioda2_setup_default_config(pe); 1921 if (pe->pbus) 1922 pnv_ioda_setup_bus_dma(pe, pe->pbus); 1923 } 1924 1925 static struct iommu_table_group_ops pnv_pci_ioda2_ops = { 1926 .get_table_size = pnv_pci_ioda2_get_table_size, 1927 .create_table = pnv_pci_ioda2_create_table_userspace, 1928 .set_window = pnv_pci_ioda2_set_window, 1929 .unset_window = pnv_pci_ioda2_unset_window, 1930 .take_ownership = pnv_ioda2_take_ownership, 1931 .release_ownership = pnv_ioda2_release_ownership, 1932 }; 1933 #endif 1934 1935 void pnv_pci_ioda2_setup_dma_pe(struct pnv_phb *phb, 1936 struct pnv_ioda_pe *pe) 1937 { 1938 int64_t rc; 1939 1940 /* TVE #1 is selected by PCI address bit 59 */ 1941 pe->tce_bypass_base = 1ull << 59; 1942 1943 /* The PE will reserve all possible 32-bits space */ 1944 pe_info(pe, "Setting up 32-bit TCE table at 0..%08x\n", 1945 phb->ioda.m32_pci_base); 1946 1947 /* Setup linux iommu table */ 1948 pe->table_group.tce32_start = 0; 1949 pe->table_group.tce32_size = phb->ioda.m32_pci_base; 1950 pe->table_group.max_dynamic_windows_supported = 1951 IOMMU_TABLE_GROUP_MAX_TABLES; 1952 pe->table_group.max_levels = POWERNV_IOMMU_MAX_LEVELS; 1953 pe->table_group.pgsizes = pnv_ioda_parse_tce_sizes(phb); 1954 1955 rc = pnv_pci_ioda2_setup_default_config(pe); 1956 if (rc) 1957 return; 1958 1959 #ifdef CONFIG_IOMMU_API 1960 pe->table_group.ops = &pnv_pci_ioda2_ops; 1961 iommu_register_group(&pe->table_group, phb->hose->global_number, 1962 pe->pe_number); 1963 #endif 1964 pe->dma_setup_done = true; 1965 } 1966 1967 /* 1968 * Called from KVM in real mode to EOI passthru interrupts. The ICP 1969 * EOI is handled directly in KVM in kvmppc_deliver_irq_passthru(). 1970 * 1971 * The IRQ data is mapped in the PCI-MSI domain and the EOI OPAL call 1972 * needs an HW IRQ number mapped in the XICS IRQ domain. The HW IRQ 1973 * numbers of the in-the-middle MSI domain are vector numbers and it's 1974 * good enough for OPAL. Use that. 1975 */ 1976 int64_t pnv_opal_pci_msi_eoi(struct irq_data *d) 1977 { 1978 struct pci_controller *hose = irq_data_get_irq_chip_data(d->parent_data); 1979 struct pnv_phb *phb = hose->private_data; 1980 1981 return opal_pci_msi_eoi(phb->opal_id, d->parent_data->hwirq); 1982 } 1983 1984 /* 1985 * The IRQ data is mapped in the XICS domain, with OPAL HW IRQ numbers 1986 */ 1987 static void pnv_ioda2_msi_eoi(struct irq_data *d) 1988 { 1989 int64_t rc; 1990 unsigned int hw_irq = (unsigned int)irqd_to_hwirq(d); 1991 struct pci_controller *hose = irq_data_get_irq_chip_data(d); 1992 struct pnv_phb *phb = hose->private_data; 1993 1994 rc = opal_pci_msi_eoi(phb->opal_id, hw_irq); 1995 WARN_ON_ONCE(rc); 1996 1997 icp_native_eoi(d); 1998 } 1999 2000 /* P8/CXL only */ 2001 void pnv_set_msi_irq_chip(struct pnv_phb *phb, unsigned int virq) 2002 { 2003 struct irq_data *idata; 2004 struct irq_chip *ichip; 2005 2006 /* The MSI EOI OPAL call is only needed on PHB3 */ 2007 if (phb->model != PNV_PHB_MODEL_PHB3) 2008 return; 2009 2010 if (!phb->ioda.irq_chip_init) { 2011 /* 2012 * First time we setup an MSI IRQ, we need to setup the 2013 * corresponding IRQ chip to route correctly. 2014 */ 2015 idata = irq_get_irq_data(virq); 2016 ichip = irq_data_get_irq_chip(idata); 2017 phb->ioda.irq_chip_init = 1; 2018 phb->ioda.irq_chip = *ichip; 2019 phb->ioda.irq_chip.irq_eoi = pnv_ioda2_msi_eoi; 2020 } 2021 irq_set_chip(virq, &phb->ioda.irq_chip); 2022 irq_set_chip_data(virq, phb->hose); 2023 } 2024 2025 static struct irq_chip pnv_pci_msi_irq_chip; 2026 2027 /* 2028 * Returns true iff chip is something that we could call 2029 * pnv_opal_pci_msi_eoi for. 2030 */ 2031 bool is_pnv_opal_msi(struct irq_chip *chip) 2032 { 2033 return chip == &pnv_pci_msi_irq_chip; 2034 } 2035 EXPORT_SYMBOL_GPL(is_pnv_opal_msi); 2036 2037 static int __pnv_pci_ioda_msi_setup(struct pnv_phb *phb, struct pci_dev *dev, 2038 unsigned int xive_num, 2039 unsigned int is_64, struct msi_msg *msg) 2040 { 2041 struct pnv_ioda_pe *pe = pnv_ioda_get_pe(dev); 2042 __be32 data; 2043 int rc; 2044 2045 dev_dbg(&dev->dev, "%s: setup %s-bit MSI for vector #%d\n", __func__, 2046 is_64 ? "64" : "32", xive_num); 2047 2048 /* No PE assigned ? bail out ... no MSI for you ! */ 2049 if (pe == NULL) 2050 return -ENXIO; 2051 2052 /* Check if we have an MVE */ 2053 if (pe->mve_number < 0) 2054 return -ENXIO; 2055 2056 /* Force 32-bit MSI on some broken devices */ 2057 if (dev->no_64bit_msi) 2058 is_64 = 0; 2059 2060 /* Assign XIVE to PE */ 2061 rc = opal_pci_set_xive_pe(phb->opal_id, pe->pe_number, xive_num); 2062 if (rc) { 2063 pr_warn("%s: OPAL error %d setting XIVE %d PE\n", 2064 pci_name(dev), rc, xive_num); 2065 return -EIO; 2066 } 2067 2068 if (is_64) { 2069 __be64 addr64; 2070 2071 rc = opal_get_msi_64(phb->opal_id, pe->mve_number, xive_num, 1, 2072 &addr64, &data); 2073 if (rc) { 2074 pr_warn("%s: OPAL error %d getting 64-bit MSI data\n", 2075 pci_name(dev), rc); 2076 return -EIO; 2077 } 2078 msg->address_hi = be64_to_cpu(addr64) >> 32; 2079 msg->address_lo = be64_to_cpu(addr64) & 0xfffffffful; 2080 } else { 2081 __be32 addr32; 2082 2083 rc = opal_get_msi_32(phb->opal_id, pe->mve_number, xive_num, 1, 2084 &addr32, &data); 2085 if (rc) { 2086 pr_warn("%s: OPAL error %d getting 32-bit MSI data\n", 2087 pci_name(dev), rc); 2088 return -EIO; 2089 } 2090 msg->address_hi = 0; 2091 msg->address_lo = be32_to_cpu(addr32); 2092 } 2093 msg->data = be32_to_cpu(data); 2094 2095 return 0; 2096 } 2097 2098 /* 2099 * The msi_free() op is called before irq_domain_free_irqs_top() when 2100 * the handler data is still available. Use that to clear the XIVE 2101 * controller. 2102 */ 2103 static void pnv_msi_ops_msi_free(struct irq_domain *domain, 2104 struct msi_domain_info *info, 2105 unsigned int irq) 2106 { 2107 if (xive_enabled()) 2108 xive_irq_free_data(irq); 2109 } 2110 2111 static struct msi_domain_ops pnv_pci_msi_domain_ops = { 2112 .msi_free = pnv_msi_ops_msi_free, 2113 }; 2114 2115 static void pnv_msi_shutdown(struct irq_data *d) 2116 { 2117 d = d->parent_data; 2118 if (d->chip->irq_shutdown) 2119 d->chip->irq_shutdown(d); 2120 } 2121 2122 static void pnv_msi_mask(struct irq_data *d) 2123 { 2124 pci_msi_mask_irq(d); 2125 irq_chip_mask_parent(d); 2126 } 2127 2128 static void pnv_msi_unmask(struct irq_data *d) 2129 { 2130 pci_msi_unmask_irq(d); 2131 irq_chip_unmask_parent(d); 2132 } 2133 2134 static struct irq_chip pnv_pci_msi_irq_chip = { 2135 .name = "PNV-PCI-MSI", 2136 .irq_shutdown = pnv_msi_shutdown, 2137 .irq_mask = pnv_msi_mask, 2138 .irq_unmask = pnv_msi_unmask, 2139 .irq_eoi = irq_chip_eoi_parent, 2140 }; 2141 2142 static struct msi_domain_info pnv_msi_domain_info = { 2143 .flags = (MSI_FLAG_USE_DEF_DOM_OPS | MSI_FLAG_USE_DEF_CHIP_OPS | 2144 MSI_FLAG_MULTI_PCI_MSI | MSI_FLAG_PCI_MSIX), 2145 .ops = &pnv_pci_msi_domain_ops, 2146 .chip = &pnv_pci_msi_irq_chip, 2147 }; 2148 2149 static void pnv_msi_compose_msg(struct irq_data *d, struct msi_msg *msg) 2150 { 2151 struct msi_desc *entry = irq_data_get_msi_desc(d); 2152 struct pci_dev *pdev = msi_desc_to_pci_dev(entry); 2153 struct pci_controller *hose = irq_data_get_irq_chip_data(d); 2154 struct pnv_phb *phb = hose->private_data; 2155 int rc; 2156 2157 rc = __pnv_pci_ioda_msi_setup(phb, pdev, d->hwirq, 2158 entry->pci.msi_attrib.is_64, msg); 2159 if (rc) 2160 dev_err(&pdev->dev, "Failed to setup %s-bit MSI #%ld : %d\n", 2161 entry->pci.msi_attrib.is_64 ? "64" : "32", d->hwirq, rc); 2162 } 2163 2164 /* 2165 * The IRQ data is mapped in the MSI domain in which HW IRQ numbers 2166 * correspond to vector numbers. 2167 */ 2168 static void pnv_msi_eoi(struct irq_data *d) 2169 { 2170 struct pci_controller *hose = irq_data_get_irq_chip_data(d); 2171 struct pnv_phb *phb = hose->private_data; 2172 2173 if (phb->model == PNV_PHB_MODEL_PHB3) { 2174 /* 2175 * The EOI OPAL call takes an OPAL HW IRQ number but 2176 * since it is translated into a vector number in 2177 * OPAL, use that directly. 2178 */ 2179 WARN_ON_ONCE(opal_pci_msi_eoi(phb->opal_id, d->hwirq)); 2180 } 2181 2182 irq_chip_eoi_parent(d); 2183 } 2184 2185 static struct irq_chip pnv_msi_irq_chip = { 2186 .name = "PNV-MSI", 2187 .irq_shutdown = pnv_msi_shutdown, 2188 .irq_mask = irq_chip_mask_parent, 2189 .irq_unmask = irq_chip_unmask_parent, 2190 .irq_eoi = pnv_msi_eoi, 2191 .irq_set_affinity = irq_chip_set_affinity_parent, 2192 .irq_compose_msi_msg = pnv_msi_compose_msg, 2193 }; 2194 2195 static int pnv_irq_parent_domain_alloc(struct irq_domain *domain, 2196 unsigned int virq, int hwirq) 2197 { 2198 struct irq_fwspec parent_fwspec; 2199 int ret; 2200 2201 parent_fwspec.fwnode = domain->parent->fwnode; 2202 parent_fwspec.param_count = 2; 2203 parent_fwspec.param[0] = hwirq; 2204 parent_fwspec.param[1] = IRQ_TYPE_EDGE_RISING; 2205 2206 ret = irq_domain_alloc_irqs_parent(domain, virq, 1, &parent_fwspec); 2207 if (ret) 2208 return ret; 2209 2210 return 0; 2211 } 2212 2213 static int pnv_irq_domain_alloc(struct irq_domain *domain, unsigned int virq, 2214 unsigned int nr_irqs, void *arg) 2215 { 2216 struct pci_controller *hose = domain->host_data; 2217 struct pnv_phb *phb = hose->private_data; 2218 msi_alloc_info_t *info = arg; 2219 struct pci_dev *pdev = msi_desc_to_pci_dev(info->desc); 2220 int hwirq; 2221 int i, ret; 2222 2223 hwirq = msi_bitmap_alloc_hwirqs(&phb->msi_bmp, nr_irqs); 2224 if (hwirq < 0) { 2225 dev_warn(&pdev->dev, "failed to find a free MSI\n"); 2226 return -ENOSPC; 2227 } 2228 2229 dev_dbg(&pdev->dev, "%s bridge %pOF %d/%x #%d\n", __func__, 2230 hose->dn, virq, hwirq, nr_irqs); 2231 2232 for (i = 0; i < nr_irqs; i++) { 2233 ret = pnv_irq_parent_domain_alloc(domain, virq + i, 2234 phb->msi_base + hwirq + i); 2235 if (ret) 2236 goto out; 2237 2238 irq_domain_set_hwirq_and_chip(domain, virq + i, hwirq + i, 2239 &pnv_msi_irq_chip, hose); 2240 } 2241 2242 return 0; 2243 2244 out: 2245 irq_domain_free_irqs_parent(domain, virq, i - 1); 2246 msi_bitmap_free_hwirqs(&phb->msi_bmp, hwirq, nr_irqs); 2247 return ret; 2248 } 2249 2250 static void pnv_irq_domain_free(struct irq_domain *domain, unsigned int virq, 2251 unsigned int nr_irqs) 2252 { 2253 struct irq_data *d = irq_domain_get_irq_data(domain, virq); 2254 struct pci_controller *hose = irq_data_get_irq_chip_data(d); 2255 struct pnv_phb *phb = hose->private_data; 2256 2257 pr_debug("%s bridge %pOF %d/%lx #%d\n", __func__, hose->dn, 2258 virq, d->hwirq, nr_irqs); 2259 2260 msi_bitmap_free_hwirqs(&phb->msi_bmp, d->hwirq, nr_irqs); 2261 /* XIVE domain is cleared through ->msi_free() */ 2262 } 2263 2264 static const struct irq_domain_ops pnv_irq_domain_ops = { 2265 .alloc = pnv_irq_domain_alloc, 2266 .free = pnv_irq_domain_free, 2267 }; 2268 2269 static int __init pnv_msi_allocate_domains(struct pci_controller *hose, unsigned int count) 2270 { 2271 struct pnv_phb *phb = hose->private_data; 2272 struct irq_domain *parent = irq_get_default_host(); 2273 2274 hose->fwnode = irq_domain_alloc_named_id_fwnode("PNV-MSI", phb->opal_id); 2275 if (!hose->fwnode) 2276 return -ENOMEM; 2277 2278 hose->dev_domain = irq_domain_create_hierarchy(parent, 0, count, 2279 hose->fwnode, 2280 &pnv_irq_domain_ops, hose); 2281 if (!hose->dev_domain) { 2282 pr_err("PCI: failed to create IRQ domain bridge %pOF (domain %d)\n", 2283 hose->dn, hose->global_number); 2284 irq_domain_free_fwnode(hose->fwnode); 2285 return -ENOMEM; 2286 } 2287 2288 hose->msi_domain = pci_msi_create_irq_domain(of_node_to_fwnode(hose->dn), 2289 &pnv_msi_domain_info, 2290 hose->dev_domain); 2291 if (!hose->msi_domain) { 2292 pr_err("PCI: failed to create MSI IRQ domain bridge %pOF (domain %d)\n", 2293 hose->dn, hose->global_number); 2294 irq_domain_free_fwnode(hose->fwnode); 2295 irq_domain_remove(hose->dev_domain); 2296 return -ENOMEM; 2297 } 2298 2299 return 0; 2300 } 2301 2302 static void __init pnv_pci_init_ioda_msis(struct pnv_phb *phb) 2303 { 2304 unsigned int count; 2305 const __be32 *prop = of_get_property(phb->hose->dn, 2306 "ibm,opal-msi-ranges", NULL); 2307 if (!prop) { 2308 /* BML Fallback */ 2309 prop = of_get_property(phb->hose->dn, "msi-ranges", NULL); 2310 } 2311 if (!prop) 2312 return; 2313 2314 phb->msi_base = be32_to_cpup(prop); 2315 count = be32_to_cpup(prop + 1); 2316 if (msi_bitmap_alloc(&phb->msi_bmp, count, phb->hose->dn)) { 2317 pr_err("PCI %d: Failed to allocate MSI bitmap !\n", 2318 phb->hose->global_number); 2319 return; 2320 } 2321 2322 pr_info(" Allocated bitmap for %d MSIs (base IRQ 0x%x)\n", 2323 count, phb->msi_base); 2324 2325 pnv_msi_allocate_domains(phb->hose, count); 2326 } 2327 2328 static void pnv_ioda_setup_pe_res(struct pnv_ioda_pe *pe, 2329 struct resource *res) 2330 { 2331 struct pnv_phb *phb = pe->phb; 2332 struct pci_bus_region region; 2333 int index; 2334 int64_t rc; 2335 2336 if (!res || !res->flags || res->start > res->end) 2337 return; 2338 2339 if (res->flags & IORESOURCE_IO) { 2340 region.start = res->start - phb->ioda.io_pci_base; 2341 region.end = res->end - phb->ioda.io_pci_base; 2342 index = region.start / phb->ioda.io_segsize; 2343 2344 while (index < phb->ioda.total_pe_num && 2345 region.start <= region.end) { 2346 phb->ioda.io_segmap[index] = pe->pe_number; 2347 rc = opal_pci_map_pe_mmio_window(phb->opal_id, 2348 pe->pe_number, OPAL_IO_WINDOW_TYPE, 0, index); 2349 if (rc != OPAL_SUCCESS) { 2350 pr_err("%s: Error %lld mapping IO segment#%d to PE#%x\n", 2351 __func__, rc, index, pe->pe_number); 2352 break; 2353 } 2354 2355 region.start += phb->ioda.io_segsize; 2356 index++; 2357 } 2358 } else if ((res->flags & IORESOURCE_MEM) && 2359 !pnv_pci_is_m64(phb, res)) { 2360 region.start = res->start - 2361 phb->hose->mem_offset[0] - 2362 phb->ioda.m32_pci_base; 2363 region.end = res->end - 2364 phb->hose->mem_offset[0] - 2365 phb->ioda.m32_pci_base; 2366 index = region.start / phb->ioda.m32_segsize; 2367 2368 while (index < phb->ioda.total_pe_num && 2369 region.start <= region.end) { 2370 phb->ioda.m32_segmap[index] = pe->pe_number; 2371 rc = opal_pci_map_pe_mmio_window(phb->opal_id, 2372 pe->pe_number, OPAL_M32_WINDOW_TYPE, 0, index); 2373 if (rc != OPAL_SUCCESS) { 2374 pr_err("%s: Error %lld mapping M32 segment#%d to PE#%x", 2375 __func__, rc, index, pe->pe_number); 2376 break; 2377 } 2378 2379 region.start += phb->ioda.m32_segsize; 2380 index++; 2381 } 2382 } 2383 } 2384 2385 /* 2386 * This function is supposed to be called on basis of PE from top 2387 * to bottom style. So the the I/O or MMIO segment assigned to 2388 * parent PE could be overridden by its child PEs if necessary. 2389 */ 2390 static void pnv_ioda_setup_pe_seg(struct pnv_ioda_pe *pe) 2391 { 2392 struct pci_dev *pdev; 2393 int i; 2394 2395 /* 2396 * NOTE: We only care PCI bus based PE for now. For PCI 2397 * device based PE, for example SRIOV sensitive VF should 2398 * be figured out later. 2399 */ 2400 BUG_ON(!(pe->flags & (PNV_IODA_PE_BUS | PNV_IODA_PE_BUS_ALL))); 2401 2402 list_for_each_entry(pdev, &pe->pbus->devices, bus_list) { 2403 for (i = 0; i <= PCI_ROM_RESOURCE; i++) 2404 pnv_ioda_setup_pe_res(pe, &pdev->resource[i]); 2405 2406 /* 2407 * If the PE contains all subordinate PCI buses, the 2408 * windows of the child bridges should be mapped to 2409 * the PE as well. 2410 */ 2411 if (!(pe->flags & PNV_IODA_PE_BUS_ALL) || !pci_is_bridge(pdev)) 2412 continue; 2413 for (i = 0; i < PCI_BRIDGE_RESOURCE_NUM; i++) 2414 pnv_ioda_setup_pe_res(pe, 2415 &pdev->resource[PCI_BRIDGE_RESOURCES + i]); 2416 } 2417 } 2418 2419 #ifdef CONFIG_DEBUG_FS 2420 static int pnv_pci_diag_data_set(void *data, u64 val) 2421 { 2422 struct pnv_phb *phb = data; 2423 s64 ret; 2424 2425 /* Retrieve the diag data from firmware */ 2426 ret = opal_pci_get_phb_diag_data2(phb->opal_id, phb->diag_data, 2427 phb->diag_data_size); 2428 if (ret != OPAL_SUCCESS) 2429 return -EIO; 2430 2431 /* Print the diag data to the kernel log */ 2432 pnv_pci_dump_phb_diag_data(phb->hose, phb->diag_data); 2433 return 0; 2434 } 2435 2436 DEFINE_DEBUGFS_ATTRIBUTE(pnv_pci_diag_data_fops, NULL, pnv_pci_diag_data_set, 2437 "%llu\n"); 2438 2439 static int pnv_pci_ioda_pe_dump(void *data, u64 val) 2440 { 2441 struct pnv_phb *phb = data; 2442 int pe_num; 2443 2444 for (pe_num = 0; pe_num < phb->ioda.total_pe_num; pe_num++) { 2445 struct pnv_ioda_pe *pe = &phb->ioda.pe_array[pe_num]; 2446 2447 if (!test_bit(pe_num, phb->ioda.pe_alloc)) 2448 continue; 2449 2450 pe_warn(pe, "rid: %04x dev count: %2d flags: %s%s%s%s%s%s\n", 2451 pe->rid, pe->device_count, 2452 (pe->flags & PNV_IODA_PE_DEV) ? "dev " : "", 2453 (pe->flags & PNV_IODA_PE_BUS) ? "bus " : "", 2454 (pe->flags & PNV_IODA_PE_BUS_ALL) ? "all " : "", 2455 (pe->flags & PNV_IODA_PE_MASTER) ? "master " : "", 2456 (pe->flags & PNV_IODA_PE_SLAVE) ? "slave " : "", 2457 (pe->flags & PNV_IODA_PE_VF) ? "vf " : ""); 2458 } 2459 2460 return 0; 2461 } 2462 2463 DEFINE_DEBUGFS_ATTRIBUTE(pnv_pci_ioda_pe_dump_fops, NULL, 2464 pnv_pci_ioda_pe_dump, "%llu\n"); 2465 2466 #endif /* CONFIG_DEBUG_FS */ 2467 2468 static void pnv_pci_ioda_create_dbgfs(void) 2469 { 2470 #ifdef CONFIG_DEBUG_FS 2471 struct pci_controller *hose, *tmp; 2472 struct pnv_phb *phb; 2473 char name[16]; 2474 2475 list_for_each_entry_safe(hose, tmp, &hose_list, list_node) { 2476 phb = hose->private_data; 2477 2478 sprintf(name, "PCI%04x", hose->global_number); 2479 phb->dbgfs = debugfs_create_dir(name, arch_debugfs_dir); 2480 2481 debugfs_create_file_unsafe("dump_diag_regs", 0200, phb->dbgfs, 2482 phb, &pnv_pci_diag_data_fops); 2483 debugfs_create_file_unsafe("dump_ioda_pe_state", 0200, phb->dbgfs, 2484 phb, &pnv_pci_ioda_pe_dump_fops); 2485 } 2486 #endif /* CONFIG_DEBUG_FS */ 2487 } 2488 2489 static void pnv_pci_enable_bridge(struct pci_bus *bus) 2490 { 2491 struct pci_dev *dev = bus->self; 2492 struct pci_bus *child; 2493 2494 /* Empty bus ? bail */ 2495 if (list_empty(&bus->devices)) 2496 return; 2497 2498 /* 2499 * If there's a bridge associated with that bus enable it. This works 2500 * around races in the generic code if the enabling is done during 2501 * parallel probing. This can be removed once those races have been 2502 * fixed. 2503 */ 2504 if (dev) { 2505 int rc = pci_enable_device(dev); 2506 if (rc) 2507 pci_err(dev, "Error enabling bridge (%d)\n", rc); 2508 pci_set_master(dev); 2509 } 2510 2511 /* Perform the same to child busses */ 2512 list_for_each_entry(child, &bus->children, node) 2513 pnv_pci_enable_bridge(child); 2514 } 2515 2516 static void pnv_pci_enable_bridges(void) 2517 { 2518 struct pci_controller *hose; 2519 2520 list_for_each_entry(hose, &hose_list, list_node) 2521 pnv_pci_enable_bridge(hose->bus); 2522 } 2523 2524 static void pnv_pci_ioda_fixup(void) 2525 { 2526 pnv_pci_ioda_create_dbgfs(); 2527 2528 pnv_pci_enable_bridges(); 2529 2530 #ifdef CONFIG_EEH 2531 pnv_eeh_post_init(); 2532 #endif 2533 } 2534 2535 /* 2536 * Returns the alignment for I/O or memory windows for P2P 2537 * bridges. That actually depends on how PEs are segmented. 2538 * For now, we return I/O or M32 segment size for PE sensitive 2539 * P2P bridges. Otherwise, the default values (4KiB for I/O, 2540 * 1MiB for memory) will be returned. 2541 * 2542 * The current PCI bus might be put into one PE, which was 2543 * create against the parent PCI bridge. For that case, we 2544 * needn't enlarge the alignment so that we can save some 2545 * resources. 2546 */ 2547 static resource_size_t pnv_pci_window_alignment(struct pci_bus *bus, 2548 unsigned long type) 2549 { 2550 struct pnv_phb *phb = pci_bus_to_pnvhb(bus); 2551 int num_pci_bridges = 0; 2552 struct pci_dev *bridge; 2553 2554 bridge = bus->self; 2555 while (bridge) { 2556 if (pci_pcie_type(bridge) == PCI_EXP_TYPE_PCI_BRIDGE) { 2557 num_pci_bridges++; 2558 if (num_pci_bridges >= 2) 2559 return 1; 2560 } 2561 2562 bridge = bridge->bus->self; 2563 } 2564 2565 /* 2566 * We fall back to M32 if M64 isn't supported. We enforce the M64 2567 * alignment for any 64-bit resource, PCIe doesn't care and 2568 * bridges only do 64-bit prefetchable anyway. 2569 */ 2570 if (phb->ioda.m64_segsize && pnv_pci_is_m64_flags(type)) 2571 return phb->ioda.m64_segsize; 2572 if (type & IORESOURCE_MEM) 2573 return phb->ioda.m32_segsize; 2574 2575 return phb->ioda.io_segsize; 2576 } 2577 2578 /* 2579 * We are updating root port or the upstream port of the 2580 * bridge behind the root port with PHB's windows in order 2581 * to accommodate the changes on required resources during 2582 * PCI (slot) hotplug, which is connected to either root 2583 * port or the downstream ports of PCIe switch behind the 2584 * root port. 2585 */ 2586 static void pnv_pci_fixup_bridge_resources(struct pci_bus *bus, 2587 unsigned long type) 2588 { 2589 struct pci_controller *hose = pci_bus_to_host(bus); 2590 struct pnv_phb *phb = hose->private_data; 2591 struct pci_dev *bridge = bus->self; 2592 struct resource *r, *w; 2593 bool msi_region = false; 2594 int i; 2595 2596 /* Check if we need apply fixup to the bridge's windows */ 2597 if (!pci_is_root_bus(bridge->bus) && 2598 !pci_is_root_bus(bridge->bus->self->bus)) 2599 return; 2600 2601 /* Fixup the resources */ 2602 for (i = 0; i < PCI_BRIDGE_RESOURCE_NUM; i++) { 2603 r = &bridge->resource[PCI_BRIDGE_RESOURCES + i]; 2604 if (!r->flags || !r->parent) 2605 continue; 2606 2607 w = NULL; 2608 if (r->flags & type & IORESOURCE_IO) 2609 w = &hose->io_resource; 2610 else if (pnv_pci_is_m64(phb, r) && 2611 (type & IORESOURCE_PREFETCH) && 2612 phb->ioda.m64_segsize) 2613 w = &hose->mem_resources[1]; 2614 else if (r->flags & type & IORESOURCE_MEM) { 2615 w = &hose->mem_resources[0]; 2616 msi_region = true; 2617 } 2618 2619 r->start = w->start; 2620 r->end = w->end; 2621 2622 /* The 64KB 32-bits MSI region shouldn't be included in 2623 * the 32-bits bridge window. Otherwise, we can see strange 2624 * issues. One of them is EEH error observed on Garrison. 2625 * 2626 * Exclude top 1MB region which is the minimal alignment of 2627 * 32-bits bridge window. 2628 */ 2629 if (msi_region) { 2630 r->end += 0x10000; 2631 r->end -= 0x100000; 2632 } 2633 } 2634 } 2635 2636 static void pnv_pci_configure_bus(struct pci_bus *bus) 2637 { 2638 struct pci_dev *bridge = bus->self; 2639 struct pnv_ioda_pe *pe; 2640 bool all = (bridge && pci_pcie_type(bridge) == PCI_EXP_TYPE_PCI_BRIDGE); 2641 2642 dev_info(&bus->dev, "Configuring PE for bus\n"); 2643 2644 /* Don't assign PE to PCI bus, which doesn't have subordinate devices */ 2645 if (WARN_ON(list_empty(&bus->devices))) 2646 return; 2647 2648 /* Reserve PEs according to used M64 resources */ 2649 pnv_ioda_reserve_m64_pe(bus, NULL, all); 2650 2651 /* 2652 * Assign PE. We might run here because of partial hotplug. 2653 * For the case, we just pick up the existing PE and should 2654 * not allocate resources again. 2655 */ 2656 pe = pnv_ioda_setup_bus_PE(bus, all); 2657 if (!pe) 2658 return; 2659 2660 pnv_ioda_setup_pe_seg(pe); 2661 } 2662 2663 static resource_size_t pnv_pci_default_alignment(void) 2664 { 2665 return PAGE_SIZE; 2666 } 2667 2668 /* Prevent enabling devices for which we couldn't properly 2669 * assign a PE 2670 */ 2671 static bool pnv_pci_enable_device_hook(struct pci_dev *dev) 2672 { 2673 struct pci_dn *pdn; 2674 2675 pdn = pci_get_pdn(dev); 2676 if (!pdn || pdn->pe_number == IODA_INVALID_PE) { 2677 pci_err(dev, "pci_enable_device() blocked, no PE assigned.\n"); 2678 return false; 2679 } 2680 2681 return true; 2682 } 2683 2684 static bool pnv_ocapi_enable_device_hook(struct pci_dev *dev) 2685 { 2686 struct pci_dn *pdn; 2687 struct pnv_ioda_pe *pe; 2688 2689 pdn = pci_get_pdn(dev); 2690 if (!pdn) 2691 return false; 2692 2693 if (pdn->pe_number == IODA_INVALID_PE) { 2694 pe = pnv_ioda_setup_dev_PE(dev); 2695 if (!pe) 2696 return false; 2697 } 2698 return true; 2699 } 2700 2701 static long pnv_pci_ioda1_unset_window(struct iommu_table_group *table_group, 2702 int num) 2703 { 2704 struct pnv_ioda_pe *pe = container_of(table_group, 2705 struct pnv_ioda_pe, table_group); 2706 struct pnv_phb *phb = pe->phb; 2707 unsigned int idx; 2708 long rc; 2709 2710 pe_info(pe, "Removing DMA window #%d\n", num); 2711 for (idx = 0; idx < phb->ioda.dma32_count; idx++) { 2712 if (phb->ioda.dma32_segmap[idx] != pe->pe_number) 2713 continue; 2714 2715 rc = opal_pci_map_pe_dma_window(phb->opal_id, pe->pe_number, 2716 idx, 0, 0ul, 0ul, 0ul); 2717 if (rc != OPAL_SUCCESS) { 2718 pe_warn(pe, "Failure %ld unmapping DMA32 segment#%d\n", 2719 rc, idx); 2720 return rc; 2721 } 2722 2723 phb->ioda.dma32_segmap[idx] = IODA_INVALID_PE; 2724 } 2725 2726 pnv_pci_unlink_table_and_group(table_group->tables[num], table_group); 2727 return OPAL_SUCCESS; 2728 } 2729 2730 static void pnv_pci_ioda1_release_pe_dma(struct pnv_ioda_pe *pe) 2731 { 2732 struct iommu_table *tbl = pe->table_group.tables[0]; 2733 int64_t rc; 2734 2735 if (!pe->dma_setup_done) 2736 return; 2737 2738 rc = pnv_pci_ioda1_unset_window(&pe->table_group, 0); 2739 if (rc != OPAL_SUCCESS) 2740 return; 2741 2742 pnv_pci_p7ioc_tce_invalidate(tbl, tbl->it_offset, tbl->it_size, false); 2743 if (pe->table_group.group) { 2744 iommu_group_put(pe->table_group.group); 2745 WARN_ON(pe->table_group.group); 2746 } 2747 2748 free_pages(tbl->it_base, get_order(tbl->it_size << 3)); 2749 iommu_tce_table_put(tbl); 2750 } 2751 2752 void pnv_pci_ioda2_release_pe_dma(struct pnv_ioda_pe *pe) 2753 { 2754 struct iommu_table *tbl = pe->table_group.tables[0]; 2755 int64_t rc; 2756 2757 if (!pe->dma_setup_done) 2758 return; 2759 2760 rc = pnv_pci_ioda2_unset_window(&pe->table_group, 0); 2761 if (rc) 2762 pe_warn(pe, "OPAL error %lld release DMA window\n", rc); 2763 2764 pnv_pci_ioda2_set_bypass(pe, false); 2765 if (pe->table_group.group) { 2766 iommu_group_put(pe->table_group.group); 2767 WARN_ON(pe->table_group.group); 2768 } 2769 2770 iommu_tce_table_put(tbl); 2771 } 2772 2773 static void pnv_ioda_free_pe_seg(struct pnv_ioda_pe *pe, 2774 unsigned short win, 2775 unsigned int *map) 2776 { 2777 struct pnv_phb *phb = pe->phb; 2778 int idx; 2779 int64_t rc; 2780 2781 for (idx = 0; idx < phb->ioda.total_pe_num; idx++) { 2782 if (map[idx] != pe->pe_number) 2783 continue; 2784 2785 rc = opal_pci_map_pe_mmio_window(phb->opal_id, 2786 phb->ioda.reserved_pe_idx, win, 0, idx); 2787 2788 if (rc != OPAL_SUCCESS) 2789 pe_warn(pe, "Error %lld unmapping (%d) segment#%d\n", 2790 rc, win, idx); 2791 2792 map[idx] = IODA_INVALID_PE; 2793 } 2794 } 2795 2796 static void pnv_ioda_release_pe_seg(struct pnv_ioda_pe *pe) 2797 { 2798 struct pnv_phb *phb = pe->phb; 2799 2800 if (phb->type == PNV_PHB_IODA1) { 2801 pnv_ioda_free_pe_seg(pe, OPAL_IO_WINDOW_TYPE, 2802 phb->ioda.io_segmap); 2803 pnv_ioda_free_pe_seg(pe, OPAL_M32_WINDOW_TYPE, 2804 phb->ioda.m32_segmap); 2805 /* M64 is pre-configured by pnv_ioda1_init_m64() */ 2806 } else if (phb->type == PNV_PHB_IODA2) { 2807 pnv_ioda_free_pe_seg(pe, OPAL_M32_WINDOW_TYPE, 2808 phb->ioda.m32_segmap); 2809 } 2810 } 2811 2812 static void pnv_ioda_release_pe(struct pnv_ioda_pe *pe) 2813 { 2814 struct pnv_phb *phb = pe->phb; 2815 struct pnv_ioda_pe *slave, *tmp; 2816 2817 pe_info(pe, "Releasing PE\n"); 2818 2819 mutex_lock(&phb->ioda.pe_list_mutex); 2820 list_del(&pe->list); 2821 mutex_unlock(&phb->ioda.pe_list_mutex); 2822 2823 switch (phb->type) { 2824 case PNV_PHB_IODA1: 2825 pnv_pci_ioda1_release_pe_dma(pe); 2826 break; 2827 case PNV_PHB_IODA2: 2828 pnv_pci_ioda2_release_pe_dma(pe); 2829 break; 2830 case PNV_PHB_NPU_OCAPI: 2831 break; 2832 default: 2833 WARN_ON(1); 2834 } 2835 2836 pnv_ioda_release_pe_seg(pe); 2837 pnv_ioda_deconfigure_pe(pe->phb, pe); 2838 2839 /* Release slave PEs in the compound PE */ 2840 if (pe->flags & PNV_IODA_PE_MASTER) { 2841 list_for_each_entry_safe(slave, tmp, &pe->slaves, list) { 2842 list_del(&slave->list); 2843 pnv_ioda_free_pe(slave); 2844 } 2845 } 2846 2847 /* 2848 * The PE for root bus can be removed because of hotplug in EEH 2849 * recovery for fenced PHB error. We need to mark the PE dead so 2850 * that it can be populated again in PCI hot add path. The PE 2851 * shouldn't be destroyed as it's the global reserved resource. 2852 */ 2853 if (phb->ioda.root_pe_idx == pe->pe_number) 2854 return; 2855 2856 pnv_ioda_free_pe(pe); 2857 } 2858 2859 static void pnv_pci_release_device(struct pci_dev *pdev) 2860 { 2861 struct pnv_phb *phb = pci_bus_to_pnvhb(pdev->bus); 2862 struct pci_dn *pdn = pci_get_pdn(pdev); 2863 struct pnv_ioda_pe *pe; 2864 2865 /* The VF PE state is torn down when sriov_disable() is called */ 2866 if (pdev->is_virtfn) 2867 return; 2868 2869 if (!pdn || pdn->pe_number == IODA_INVALID_PE) 2870 return; 2871 2872 #ifdef CONFIG_PCI_IOV 2873 /* 2874 * FIXME: Try move this to sriov_disable(). It's here since we allocate 2875 * the iov state at probe time since we need to fiddle with the IOV 2876 * resources. 2877 */ 2878 if (pdev->is_physfn) 2879 kfree(pdev->dev.archdata.iov_data); 2880 #endif 2881 2882 /* 2883 * PCI hotplug can happen as part of EEH error recovery. The @pdn 2884 * isn't removed and added afterwards in this scenario. We should 2885 * set the PE number in @pdn to an invalid one. Otherwise, the PE's 2886 * device count is decreased on removing devices while failing to 2887 * be increased on adding devices. It leads to unbalanced PE's device 2888 * count and eventually make normal PCI hotplug path broken. 2889 */ 2890 pe = &phb->ioda.pe_array[pdn->pe_number]; 2891 pdn->pe_number = IODA_INVALID_PE; 2892 2893 WARN_ON(--pe->device_count < 0); 2894 if (pe->device_count == 0) 2895 pnv_ioda_release_pe(pe); 2896 } 2897 2898 static void pnv_pci_ioda_shutdown(struct pci_controller *hose) 2899 { 2900 struct pnv_phb *phb = hose->private_data; 2901 2902 opal_pci_reset(phb->opal_id, OPAL_RESET_PCI_IODA_TABLE, 2903 OPAL_ASSERT_RESET); 2904 } 2905 2906 static void pnv_pci_ioda_dma_bus_setup(struct pci_bus *bus) 2907 { 2908 struct pnv_phb *phb = pci_bus_to_pnvhb(bus); 2909 struct pnv_ioda_pe *pe; 2910 2911 list_for_each_entry(pe, &phb->ioda.pe_list, list) { 2912 if (!(pe->flags & (PNV_IODA_PE_BUS | PNV_IODA_PE_BUS_ALL))) 2913 continue; 2914 2915 if (!pe->pbus) 2916 continue; 2917 2918 if (bus->number == ((pe->rid >> 8) & 0xFF)) { 2919 pe->pbus = bus; 2920 break; 2921 } 2922 } 2923 } 2924 2925 static const struct pci_controller_ops pnv_pci_ioda_controller_ops = { 2926 .dma_dev_setup = pnv_pci_ioda_dma_dev_setup, 2927 .dma_bus_setup = pnv_pci_ioda_dma_bus_setup, 2928 .iommu_bypass_supported = pnv_pci_ioda_iommu_bypass_supported, 2929 .enable_device_hook = pnv_pci_enable_device_hook, 2930 .release_device = pnv_pci_release_device, 2931 .window_alignment = pnv_pci_window_alignment, 2932 .setup_bridge = pnv_pci_fixup_bridge_resources, 2933 .reset_secondary_bus = pnv_pci_reset_secondary_bus, 2934 .shutdown = pnv_pci_ioda_shutdown, 2935 }; 2936 2937 static const struct pci_controller_ops pnv_npu_ocapi_ioda_controller_ops = { 2938 .enable_device_hook = pnv_ocapi_enable_device_hook, 2939 .release_device = pnv_pci_release_device, 2940 .window_alignment = pnv_pci_window_alignment, 2941 .reset_secondary_bus = pnv_pci_reset_secondary_bus, 2942 .shutdown = pnv_pci_ioda_shutdown, 2943 }; 2944 2945 static void __init pnv_pci_init_ioda_phb(struct device_node *np, 2946 u64 hub_id, int ioda_type) 2947 { 2948 struct pci_controller *hose; 2949 struct pnv_phb *phb; 2950 unsigned long size, m64map_off, m32map_off, pemap_off; 2951 unsigned long iomap_off = 0, dma32map_off = 0; 2952 struct pnv_ioda_pe *root_pe; 2953 struct resource r; 2954 const __be64 *prop64; 2955 const __be32 *prop32; 2956 int len; 2957 unsigned int segno; 2958 u64 phb_id; 2959 void *aux; 2960 long rc; 2961 2962 if (!of_device_is_available(np)) 2963 return; 2964 2965 pr_info("Initializing %s PHB (%pOF)\n", pnv_phb_names[ioda_type], np); 2966 2967 prop64 = of_get_property(np, "ibm,opal-phbid", NULL); 2968 if (!prop64) { 2969 pr_err(" Missing \"ibm,opal-phbid\" property !\n"); 2970 return; 2971 } 2972 phb_id = be64_to_cpup(prop64); 2973 pr_debug(" PHB-ID : 0x%016llx\n", phb_id); 2974 2975 phb = kzalloc(sizeof(*phb), GFP_KERNEL); 2976 if (!phb) 2977 panic("%s: Failed to allocate %zu bytes\n", __func__, 2978 sizeof(*phb)); 2979 2980 /* Allocate PCI controller */ 2981 phb->hose = hose = pcibios_alloc_controller(np); 2982 if (!phb->hose) { 2983 pr_err(" Can't allocate PCI controller for %pOF\n", 2984 np); 2985 memblock_free(phb, sizeof(struct pnv_phb)); 2986 return; 2987 } 2988 2989 spin_lock_init(&phb->lock); 2990 prop32 = of_get_property(np, "bus-range", &len); 2991 if (prop32 && len == 8) { 2992 hose->first_busno = be32_to_cpu(prop32[0]); 2993 hose->last_busno = be32_to_cpu(prop32[1]); 2994 } else { 2995 pr_warn(" Broken <bus-range> on %pOF\n", np); 2996 hose->first_busno = 0; 2997 hose->last_busno = 0xff; 2998 } 2999 hose->private_data = phb; 3000 phb->hub_id = hub_id; 3001 phb->opal_id = phb_id; 3002 phb->type = ioda_type; 3003 mutex_init(&phb->ioda.pe_alloc_mutex); 3004 3005 /* Detect specific models for error handling */ 3006 if (of_device_is_compatible(np, "ibm,p7ioc-pciex")) 3007 phb->model = PNV_PHB_MODEL_P7IOC; 3008 else if (of_device_is_compatible(np, "ibm,power8-pciex")) 3009 phb->model = PNV_PHB_MODEL_PHB3; 3010 else 3011 phb->model = PNV_PHB_MODEL_UNKNOWN; 3012 3013 /* Initialize diagnostic data buffer */ 3014 prop32 = of_get_property(np, "ibm,phb-diag-data-size", NULL); 3015 if (prop32) 3016 phb->diag_data_size = be32_to_cpup(prop32); 3017 else 3018 phb->diag_data_size = PNV_PCI_DIAG_BUF_SIZE; 3019 3020 phb->diag_data = kzalloc(phb->diag_data_size, GFP_KERNEL); 3021 if (!phb->diag_data) 3022 panic("%s: Failed to allocate %u bytes\n", __func__, 3023 phb->diag_data_size); 3024 3025 /* Parse 32-bit and IO ranges (if any) */ 3026 pci_process_bridge_OF_ranges(hose, np, !hose->global_number); 3027 3028 /* Get registers */ 3029 if (!of_address_to_resource(np, 0, &r)) { 3030 phb->regs_phys = r.start; 3031 phb->regs = ioremap(r.start, resource_size(&r)); 3032 if (phb->regs == NULL) 3033 pr_err(" Failed to map registers !\n"); 3034 } 3035 3036 /* Initialize more IODA stuff */ 3037 phb->ioda.total_pe_num = 1; 3038 prop32 = of_get_property(np, "ibm,opal-num-pes", NULL); 3039 if (prop32) 3040 phb->ioda.total_pe_num = be32_to_cpup(prop32); 3041 prop32 = of_get_property(np, "ibm,opal-reserved-pe", NULL); 3042 if (prop32) 3043 phb->ioda.reserved_pe_idx = be32_to_cpup(prop32); 3044 3045 /* Invalidate RID to PE# mapping */ 3046 for (segno = 0; segno < ARRAY_SIZE(phb->ioda.pe_rmap); segno++) 3047 phb->ioda.pe_rmap[segno] = IODA_INVALID_PE; 3048 3049 /* Parse 64-bit MMIO range */ 3050 pnv_ioda_parse_m64_window(phb); 3051 3052 phb->ioda.m32_size = resource_size(&hose->mem_resources[0]); 3053 /* FW Has already off top 64k of M32 space (MSI space) */ 3054 phb->ioda.m32_size += 0x10000; 3055 3056 phb->ioda.m32_segsize = phb->ioda.m32_size / phb->ioda.total_pe_num; 3057 phb->ioda.m32_pci_base = hose->mem_resources[0].start - hose->mem_offset[0]; 3058 phb->ioda.io_size = hose->pci_io_size; 3059 phb->ioda.io_segsize = phb->ioda.io_size / phb->ioda.total_pe_num; 3060 phb->ioda.io_pci_base = 0; /* XXX calculate this ? */ 3061 3062 /* Calculate how many 32-bit TCE segments we have */ 3063 phb->ioda.dma32_count = phb->ioda.m32_pci_base / 3064 PNV_IODA1_DMA32_SEGSIZE; 3065 3066 /* Allocate aux data & arrays. We don't have IO ports on PHB3 */ 3067 size = ALIGN(max_t(unsigned, phb->ioda.total_pe_num, 8) / 8, 3068 sizeof(unsigned long)); 3069 m64map_off = size; 3070 size += phb->ioda.total_pe_num * sizeof(phb->ioda.m64_segmap[0]); 3071 m32map_off = size; 3072 size += phb->ioda.total_pe_num * sizeof(phb->ioda.m32_segmap[0]); 3073 if (phb->type == PNV_PHB_IODA1) { 3074 iomap_off = size; 3075 size += phb->ioda.total_pe_num * sizeof(phb->ioda.io_segmap[0]); 3076 dma32map_off = size; 3077 size += phb->ioda.dma32_count * 3078 sizeof(phb->ioda.dma32_segmap[0]); 3079 } 3080 pemap_off = size; 3081 size += phb->ioda.total_pe_num * sizeof(struct pnv_ioda_pe); 3082 aux = kzalloc(size, GFP_KERNEL); 3083 if (!aux) 3084 panic("%s: Failed to allocate %lu bytes\n", __func__, size); 3085 3086 phb->ioda.pe_alloc = aux; 3087 phb->ioda.m64_segmap = aux + m64map_off; 3088 phb->ioda.m32_segmap = aux + m32map_off; 3089 for (segno = 0; segno < phb->ioda.total_pe_num; segno++) { 3090 phb->ioda.m64_segmap[segno] = IODA_INVALID_PE; 3091 phb->ioda.m32_segmap[segno] = IODA_INVALID_PE; 3092 } 3093 if (phb->type == PNV_PHB_IODA1) { 3094 phb->ioda.io_segmap = aux + iomap_off; 3095 for (segno = 0; segno < phb->ioda.total_pe_num; segno++) 3096 phb->ioda.io_segmap[segno] = IODA_INVALID_PE; 3097 3098 phb->ioda.dma32_segmap = aux + dma32map_off; 3099 for (segno = 0; segno < phb->ioda.dma32_count; segno++) 3100 phb->ioda.dma32_segmap[segno] = IODA_INVALID_PE; 3101 } 3102 phb->ioda.pe_array = aux + pemap_off; 3103 3104 /* 3105 * Choose PE number for root bus, which shouldn't have 3106 * M64 resources consumed by its child devices. To pick 3107 * the PE number adjacent to the reserved one if possible. 3108 */ 3109 pnv_ioda_reserve_pe(phb, phb->ioda.reserved_pe_idx); 3110 if (phb->ioda.reserved_pe_idx == 0) { 3111 phb->ioda.root_pe_idx = 1; 3112 pnv_ioda_reserve_pe(phb, phb->ioda.root_pe_idx); 3113 } else if (phb->ioda.reserved_pe_idx == (phb->ioda.total_pe_num - 1)) { 3114 phb->ioda.root_pe_idx = phb->ioda.reserved_pe_idx - 1; 3115 pnv_ioda_reserve_pe(phb, phb->ioda.root_pe_idx); 3116 } else { 3117 /* otherwise just allocate one */ 3118 root_pe = pnv_ioda_alloc_pe(phb, 1); 3119 phb->ioda.root_pe_idx = root_pe->pe_number; 3120 } 3121 3122 INIT_LIST_HEAD(&phb->ioda.pe_list); 3123 mutex_init(&phb->ioda.pe_list_mutex); 3124 3125 /* Calculate how many 32-bit TCE segments we have */ 3126 phb->ioda.dma32_count = phb->ioda.m32_pci_base / 3127 PNV_IODA1_DMA32_SEGSIZE; 3128 3129 #if 0 /* We should really do that ... */ 3130 rc = opal_pci_set_phb_mem_window(opal->phb_id, 3131 window_type, 3132 window_num, 3133 starting_real_address, 3134 starting_pci_address, 3135 segment_size); 3136 #endif 3137 3138 pr_info(" %03d (%03d) PE's M32: 0x%x [segment=0x%x]\n", 3139 phb->ioda.total_pe_num, phb->ioda.reserved_pe_idx, 3140 phb->ioda.m32_size, phb->ioda.m32_segsize); 3141 if (phb->ioda.m64_size) 3142 pr_info(" M64: 0x%lx [segment=0x%lx]\n", 3143 phb->ioda.m64_size, phb->ioda.m64_segsize); 3144 if (phb->ioda.io_size) 3145 pr_info(" IO: 0x%x [segment=0x%x]\n", 3146 phb->ioda.io_size, phb->ioda.io_segsize); 3147 3148 3149 phb->hose->ops = &pnv_pci_ops; 3150 phb->get_pe_state = pnv_ioda_get_pe_state; 3151 phb->freeze_pe = pnv_ioda_freeze_pe; 3152 phb->unfreeze_pe = pnv_ioda_unfreeze_pe; 3153 3154 /* Setup MSI support */ 3155 pnv_pci_init_ioda_msis(phb); 3156 3157 /* 3158 * We pass the PCI probe flag PCI_REASSIGN_ALL_RSRC here 3159 * to let the PCI core do resource assignment. It's supposed 3160 * that the PCI core will do correct I/O and MMIO alignment 3161 * for the P2P bridge bars so that each PCI bus (excluding 3162 * the child P2P bridges) can form individual PE. 3163 */ 3164 ppc_md.pcibios_fixup = pnv_pci_ioda_fixup; 3165 3166 switch (phb->type) { 3167 case PNV_PHB_NPU_OCAPI: 3168 hose->controller_ops = pnv_npu_ocapi_ioda_controller_ops; 3169 break; 3170 default: 3171 hose->controller_ops = pnv_pci_ioda_controller_ops; 3172 } 3173 3174 ppc_md.pcibios_default_alignment = pnv_pci_default_alignment; 3175 3176 #ifdef CONFIG_PCI_IOV 3177 ppc_md.pcibios_fixup_sriov = pnv_pci_ioda_fixup_iov; 3178 ppc_md.pcibios_iov_resource_alignment = pnv_pci_iov_resource_alignment; 3179 ppc_md.pcibios_sriov_enable = pnv_pcibios_sriov_enable; 3180 ppc_md.pcibios_sriov_disable = pnv_pcibios_sriov_disable; 3181 #endif 3182 3183 pci_add_flags(PCI_REASSIGN_ALL_RSRC); 3184 3185 /* Reset IODA tables to a clean state */ 3186 rc = opal_pci_reset(phb_id, OPAL_RESET_PCI_IODA_TABLE, OPAL_ASSERT_RESET); 3187 if (rc) 3188 pr_warn(" OPAL Error %ld performing IODA table reset !\n", rc); 3189 3190 /* 3191 * If we're running in kdump kernel, the previous kernel never 3192 * shutdown PCI devices correctly. We already got IODA table 3193 * cleaned out. So we have to issue PHB reset to stop all PCI 3194 * transactions from previous kernel. The ppc_pci_reset_phbs 3195 * kernel parameter will force this reset too. Additionally, 3196 * if the IODA reset above failed then use a bigger hammer. 3197 * This can happen if we get a PHB fatal error in very early 3198 * boot. 3199 */ 3200 if (is_kdump_kernel() || pci_reset_phbs || rc) { 3201 pr_info(" Issue PHB reset ...\n"); 3202 pnv_eeh_phb_reset(hose, EEH_RESET_FUNDAMENTAL); 3203 pnv_eeh_phb_reset(hose, EEH_RESET_DEACTIVATE); 3204 } 3205 3206 /* Remove M64 resource if we can't configure it successfully */ 3207 if (!phb->init_m64 || phb->init_m64(phb)) 3208 hose->mem_resources[1].flags = 0; 3209 3210 /* create pci_dn's for DT nodes under this PHB */ 3211 pci_devs_phb_init_dynamic(hose); 3212 } 3213 3214 void __init pnv_pci_init_ioda2_phb(struct device_node *np) 3215 { 3216 pnv_pci_init_ioda_phb(np, 0, PNV_PHB_IODA2); 3217 } 3218 3219 void __init pnv_pci_init_npu2_opencapi_phb(struct device_node *np) 3220 { 3221 pnv_pci_init_ioda_phb(np, 0, PNV_PHB_NPU_OCAPI); 3222 } 3223 3224 static void pnv_npu2_opencapi_cfg_size_fixup(struct pci_dev *dev) 3225 { 3226 struct pnv_phb *phb = pci_bus_to_pnvhb(dev->bus); 3227 3228 if (!machine_is(powernv)) 3229 return; 3230 3231 if (phb->type == PNV_PHB_NPU_OCAPI) 3232 dev->cfg_size = PCI_CFG_SPACE_EXP_SIZE; 3233 } 3234 DECLARE_PCI_FIXUP_EARLY(PCI_ANY_ID, PCI_ANY_ID, pnv_npu2_opencapi_cfg_size_fixup); 3235 3236 void __init pnv_pci_init_ioda_hub(struct device_node *np) 3237 { 3238 struct device_node *phbn; 3239 const __be64 *prop64; 3240 u64 hub_id; 3241 3242 pr_info("Probing IODA IO-Hub %pOF\n", np); 3243 3244 prop64 = of_get_property(np, "ibm,opal-hubid", NULL); 3245 if (!prop64) { 3246 pr_err(" Missing \"ibm,opal-hubid\" property !\n"); 3247 return; 3248 } 3249 hub_id = be64_to_cpup(prop64); 3250 pr_devel(" HUB-ID : 0x%016llx\n", hub_id); 3251 3252 /* Count child PHBs */ 3253 for_each_child_of_node(np, phbn) { 3254 /* Look for IODA1 PHBs */ 3255 if (of_device_is_compatible(phbn, "ibm,ioda-phb")) 3256 pnv_pci_init_ioda_phb(phbn, hub_id, PNV_PHB_IODA1); 3257 } 3258 } 3259