1 // SPDX-License-Identifier: GPL-2.0-or-later 2 /* 3 * Support PCI/PCIe on PowerNV platforms 4 * 5 * Copyright 2011 Benjamin Herrenschmidt, IBM Corp. 6 */ 7 8 #undef DEBUG 9 10 #include <linux/kernel.h> 11 #include <linux/pci.h> 12 #include <linux/crash_dump.h> 13 #include <linux/delay.h> 14 #include <linux/string.h> 15 #include <linux/init.h> 16 #include <linux/memblock.h> 17 #include <linux/irq.h> 18 #include <linux/io.h> 19 #include <linux/msi.h> 20 #include <linux/iommu.h> 21 #include <linux/rculist.h> 22 #include <linux/sizes.h> 23 #include <linux/debugfs.h> 24 25 #include <asm/sections.h> 26 #include <asm/io.h> 27 #include <asm/prom.h> 28 #include <asm/pci-bridge.h> 29 #include <asm/machdep.h> 30 #include <asm/msi_bitmap.h> 31 #include <asm/ppc-pci.h> 32 #include <asm/opal.h> 33 #include <asm/iommu.h> 34 #include <asm/tce.h> 35 #include <asm/xics.h> 36 #include <asm/firmware.h> 37 #include <asm/pnv-pci.h> 38 #include <asm/mmzone.h> 39 #include <asm/xive.h> 40 41 #include <misc/cxl-base.h> 42 43 #include "powernv.h" 44 #include "pci.h" 45 #include "../../../../drivers/pci/pci.h" 46 47 #define PNV_IODA1_M64_NUM 16 /* Number of M64 BARs */ 48 #define PNV_IODA1_M64_SEGS 8 /* Segments per M64 BAR */ 49 #define PNV_IODA1_DMA32_SEGSIZE 0x10000000 50 51 static const char * const pnv_phb_names[] = { "IODA1", "IODA2", "NPU_OCAPI" }; 52 53 static void pnv_pci_ioda2_set_bypass(struct pnv_ioda_pe *pe, bool enable); 54 static void pnv_pci_configure_bus(struct pci_bus *bus); 55 56 void pe_level_printk(const struct pnv_ioda_pe *pe, const char *level, 57 const char *fmt, ...) 58 { 59 struct va_format vaf; 60 va_list args; 61 char pfix[32]; 62 63 va_start(args, fmt); 64 65 vaf.fmt = fmt; 66 vaf.va = &args; 67 68 if (pe->flags & PNV_IODA_PE_DEV) 69 strlcpy(pfix, dev_name(&pe->pdev->dev), sizeof(pfix)); 70 else if (pe->flags & (PNV_IODA_PE_BUS | PNV_IODA_PE_BUS_ALL)) 71 sprintf(pfix, "%04x:%02x ", 72 pci_domain_nr(pe->pbus), pe->pbus->number); 73 #ifdef CONFIG_PCI_IOV 74 else if (pe->flags & PNV_IODA_PE_VF) 75 sprintf(pfix, "%04x:%02x:%2x.%d", 76 pci_domain_nr(pe->parent_dev->bus), 77 (pe->rid & 0xff00) >> 8, 78 PCI_SLOT(pe->rid), PCI_FUNC(pe->rid)); 79 #endif /* CONFIG_PCI_IOV*/ 80 81 printk("%spci %s: [PE# %.2x] %pV", 82 level, pfix, pe->pe_number, &vaf); 83 84 va_end(args); 85 } 86 87 static bool pnv_iommu_bypass_disabled __read_mostly; 88 static bool pci_reset_phbs __read_mostly; 89 90 static int __init iommu_setup(char *str) 91 { 92 if (!str) 93 return -EINVAL; 94 95 while (*str) { 96 if (!strncmp(str, "nobypass", 8)) { 97 pnv_iommu_bypass_disabled = true; 98 pr_info("PowerNV: IOMMU bypass window disabled.\n"); 99 break; 100 } 101 str += strcspn(str, ","); 102 if (*str == ',') 103 str++; 104 } 105 106 return 0; 107 } 108 early_param("iommu", iommu_setup); 109 110 static int __init pci_reset_phbs_setup(char *str) 111 { 112 pci_reset_phbs = true; 113 return 0; 114 } 115 116 early_param("ppc_pci_reset_phbs", pci_reset_phbs_setup); 117 118 static struct pnv_ioda_pe *pnv_ioda_init_pe(struct pnv_phb *phb, int pe_no) 119 { 120 s64 rc; 121 122 phb->ioda.pe_array[pe_no].phb = phb; 123 phb->ioda.pe_array[pe_no].pe_number = pe_no; 124 phb->ioda.pe_array[pe_no].dma_setup_done = false; 125 126 /* 127 * Clear the PE frozen state as it might be put into frozen state 128 * in the last PCI remove path. It's not harmful to do so when the 129 * PE is already in unfrozen state. 130 */ 131 rc = opal_pci_eeh_freeze_clear(phb->opal_id, pe_no, 132 OPAL_EEH_ACTION_CLEAR_FREEZE_ALL); 133 if (rc != OPAL_SUCCESS && rc != OPAL_UNSUPPORTED) 134 pr_warn("%s: Error %lld unfreezing PHB#%x-PE#%x\n", 135 __func__, rc, phb->hose->global_number, pe_no); 136 137 return &phb->ioda.pe_array[pe_no]; 138 } 139 140 static void pnv_ioda_reserve_pe(struct pnv_phb *phb, int pe_no) 141 { 142 if (!(pe_no >= 0 && pe_no < phb->ioda.total_pe_num)) { 143 pr_warn("%s: Invalid PE %x on PHB#%x\n", 144 __func__, pe_no, phb->hose->global_number); 145 return; 146 } 147 148 mutex_lock(&phb->ioda.pe_alloc_mutex); 149 if (test_and_set_bit(pe_no, phb->ioda.pe_alloc)) 150 pr_debug("%s: PE %x was reserved on PHB#%x\n", 151 __func__, pe_no, phb->hose->global_number); 152 mutex_unlock(&phb->ioda.pe_alloc_mutex); 153 154 pnv_ioda_init_pe(phb, pe_no); 155 } 156 157 struct pnv_ioda_pe *pnv_ioda_alloc_pe(struct pnv_phb *phb, int count) 158 { 159 struct pnv_ioda_pe *ret = NULL; 160 int run = 0, pe, i; 161 162 mutex_lock(&phb->ioda.pe_alloc_mutex); 163 164 /* scan backwards for a run of @count cleared bits */ 165 for (pe = phb->ioda.total_pe_num - 1; pe >= 0; pe--) { 166 if (test_bit(pe, phb->ioda.pe_alloc)) { 167 run = 0; 168 continue; 169 } 170 171 run++; 172 if (run == count) 173 break; 174 } 175 if (run != count) 176 goto out; 177 178 for (i = pe; i < pe + count; i++) { 179 set_bit(i, phb->ioda.pe_alloc); 180 pnv_ioda_init_pe(phb, i); 181 } 182 ret = &phb->ioda.pe_array[pe]; 183 184 out: 185 mutex_unlock(&phb->ioda.pe_alloc_mutex); 186 return ret; 187 } 188 189 void pnv_ioda_free_pe(struct pnv_ioda_pe *pe) 190 { 191 struct pnv_phb *phb = pe->phb; 192 unsigned int pe_num = pe->pe_number; 193 194 WARN_ON(pe->pdev); 195 memset(pe, 0, sizeof(struct pnv_ioda_pe)); 196 197 mutex_lock(&phb->ioda.pe_alloc_mutex); 198 clear_bit(pe_num, phb->ioda.pe_alloc); 199 mutex_unlock(&phb->ioda.pe_alloc_mutex); 200 } 201 202 /* The default M64 BAR is shared by all PEs */ 203 static int pnv_ioda2_init_m64(struct pnv_phb *phb) 204 { 205 const char *desc; 206 struct resource *r; 207 s64 rc; 208 209 /* Configure the default M64 BAR */ 210 rc = opal_pci_set_phb_mem_window(phb->opal_id, 211 OPAL_M64_WINDOW_TYPE, 212 phb->ioda.m64_bar_idx, 213 phb->ioda.m64_base, 214 0, /* unused */ 215 phb->ioda.m64_size); 216 if (rc != OPAL_SUCCESS) { 217 desc = "configuring"; 218 goto fail; 219 } 220 221 /* Enable the default M64 BAR */ 222 rc = opal_pci_phb_mmio_enable(phb->opal_id, 223 OPAL_M64_WINDOW_TYPE, 224 phb->ioda.m64_bar_idx, 225 OPAL_ENABLE_M64_SPLIT); 226 if (rc != OPAL_SUCCESS) { 227 desc = "enabling"; 228 goto fail; 229 } 230 231 /* 232 * Exclude the segments for reserved and root bus PE, which 233 * are first or last two PEs. 234 */ 235 r = &phb->hose->mem_resources[1]; 236 if (phb->ioda.reserved_pe_idx == 0) 237 r->start += (2 * phb->ioda.m64_segsize); 238 else if (phb->ioda.reserved_pe_idx == (phb->ioda.total_pe_num - 1)) 239 r->end -= (2 * phb->ioda.m64_segsize); 240 else 241 pr_warn(" Cannot strip M64 segment for reserved PE#%x\n", 242 phb->ioda.reserved_pe_idx); 243 244 return 0; 245 246 fail: 247 pr_warn(" Failure %lld %s M64 BAR#%d\n", 248 rc, desc, phb->ioda.m64_bar_idx); 249 opal_pci_phb_mmio_enable(phb->opal_id, 250 OPAL_M64_WINDOW_TYPE, 251 phb->ioda.m64_bar_idx, 252 OPAL_DISABLE_M64); 253 return -EIO; 254 } 255 256 static void pnv_ioda_reserve_dev_m64_pe(struct pci_dev *pdev, 257 unsigned long *pe_bitmap) 258 { 259 struct pnv_phb *phb = pci_bus_to_pnvhb(pdev->bus); 260 struct resource *r; 261 resource_size_t base, sgsz, start, end; 262 int segno, i; 263 264 base = phb->ioda.m64_base; 265 sgsz = phb->ioda.m64_segsize; 266 for (i = 0; i <= PCI_ROM_RESOURCE; i++) { 267 r = &pdev->resource[i]; 268 if (!r->parent || !pnv_pci_is_m64(phb, r)) 269 continue; 270 271 start = ALIGN_DOWN(r->start - base, sgsz); 272 end = ALIGN(r->end - base, sgsz); 273 for (segno = start / sgsz; segno < end / sgsz; segno++) { 274 if (pe_bitmap) 275 set_bit(segno, pe_bitmap); 276 else 277 pnv_ioda_reserve_pe(phb, segno); 278 } 279 } 280 } 281 282 static int pnv_ioda1_init_m64(struct pnv_phb *phb) 283 { 284 struct resource *r; 285 int index; 286 287 /* 288 * There are 16 M64 BARs, each of which has 8 segments. So 289 * there are as many M64 segments as the maximum number of 290 * PEs, which is 128. 291 */ 292 for (index = 0; index < PNV_IODA1_M64_NUM; index++) { 293 unsigned long base, segsz = phb->ioda.m64_segsize; 294 int64_t rc; 295 296 base = phb->ioda.m64_base + 297 index * PNV_IODA1_M64_SEGS * segsz; 298 rc = opal_pci_set_phb_mem_window(phb->opal_id, 299 OPAL_M64_WINDOW_TYPE, index, base, 0, 300 PNV_IODA1_M64_SEGS * segsz); 301 if (rc != OPAL_SUCCESS) { 302 pr_warn(" Error %lld setting M64 PHB#%x-BAR#%d\n", 303 rc, phb->hose->global_number, index); 304 goto fail; 305 } 306 307 rc = opal_pci_phb_mmio_enable(phb->opal_id, 308 OPAL_M64_WINDOW_TYPE, index, 309 OPAL_ENABLE_M64_SPLIT); 310 if (rc != OPAL_SUCCESS) { 311 pr_warn(" Error %lld enabling M64 PHB#%x-BAR#%d\n", 312 rc, phb->hose->global_number, index); 313 goto fail; 314 } 315 } 316 317 for (index = 0; index < phb->ioda.total_pe_num; index++) { 318 int64_t rc; 319 320 /* 321 * P7IOC supports M64DT, which helps mapping M64 segment 322 * to one particular PE#. However, PHB3 has fixed mapping 323 * between M64 segment and PE#. In order to have same logic 324 * for P7IOC and PHB3, we enforce fixed mapping between M64 325 * segment and PE# on P7IOC. 326 */ 327 rc = opal_pci_map_pe_mmio_window(phb->opal_id, 328 index, OPAL_M64_WINDOW_TYPE, 329 index / PNV_IODA1_M64_SEGS, 330 index % PNV_IODA1_M64_SEGS); 331 if (rc != OPAL_SUCCESS) { 332 pr_warn("%s: Error %lld mapping M64 for PHB#%x-PE#%x\n", 333 __func__, rc, phb->hose->global_number, 334 index); 335 goto fail; 336 } 337 } 338 339 /* 340 * Exclude the segments for reserved and root bus PE, which 341 * are first or last two PEs. 342 */ 343 r = &phb->hose->mem_resources[1]; 344 if (phb->ioda.reserved_pe_idx == 0) 345 r->start += (2 * phb->ioda.m64_segsize); 346 else if (phb->ioda.reserved_pe_idx == (phb->ioda.total_pe_num - 1)) 347 r->end -= (2 * phb->ioda.m64_segsize); 348 else 349 WARN(1, "Wrong reserved PE#%x on PHB#%x\n", 350 phb->ioda.reserved_pe_idx, phb->hose->global_number); 351 352 return 0; 353 354 fail: 355 for ( ; index >= 0; index--) 356 opal_pci_phb_mmio_enable(phb->opal_id, 357 OPAL_M64_WINDOW_TYPE, index, OPAL_DISABLE_M64); 358 359 return -EIO; 360 } 361 362 static void pnv_ioda_reserve_m64_pe(struct pci_bus *bus, 363 unsigned long *pe_bitmap, 364 bool all) 365 { 366 struct pci_dev *pdev; 367 368 list_for_each_entry(pdev, &bus->devices, bus_list) { 369 pnv_ioda_reserve_dev_m64_pe(pdev, pe_bitmap); 370 371 if (all && pdev->subordinate) 372 pnv_ioda_reserve_m64_pe(pdev->subordinate, 373 pe_bitmap, all); 374 } 375 } 376 377 static struct pnv_ioda_pe *pnv_ioda_pick_m64_pe(struct pci_bus *bus, bool all) 378 { 379 struct pnv_phb *phb = pci_bus_to_pnvhb(bus); 380 struct pnv_ioda_pe *master_pe, *pe; 381 unsigned long size, *pe_alloc; 382 int i; 383 384 /* Root bus shouldn't use M64 */ 385 if (pci_is_root_bus(bus)) 386 return NULL; 387 388 /* Allocate bitmap */ 389 size = ALIGN(phb->ioda.total_pe_num / 8, sizeof(unsigned long)); 390 pe_alloc = kzalloc(size, GFP_KERNEL); 391 if (!pe_alloc) { 392 pr_warn("%s: Out of memory !\n", 393 __func__); 394 return NULL; 395 } 396 397 /* Figure out reserved PE numbers by the PE */ 398 pnv_ioda_reserve_m64_pe(bus, pe_alloc, all); 399 400 /* 401 * the current bus might not own M64 window and that's all 402 * contributed by its child buses. For the case, we needn't 403 * pick M64 dependent PE#. 404 */ 405 if (bitmap_empty(pe_alloc, phb->ioda.total_pe_num)) { 406 kfree(pe_alloc); 407 return NULL; 408 } 409 410 /* 411 * Figure out the master PE and put all slave PEs to master 412 * PE's list to form compound PE. 413 */ 414 master_pe = NULL; 415 i = -1; 416 while ((i = find_next_bit(pe_alloc, phb->ioda.total_pe_num, i + 1)) < 417 phb->ioda.total_pe_num) { 418 pe = &phb->ioda.pe_array[i]; 419 420 phb->ioda.m64_segmap[pe->pe_number] = pe->pe_number; 421 if (!master_pe) { 422 pe->flags |= PNV_IODA_PE_MASTER; 423 INIT_LIST_HEAD(&pe->slaves); 424 master_pe = pe; 425 } else { 426 pe->flags |= PNV_IODA_PE_SLAVE; 427 pe->master = master_pe; 428 list_add_tail(&pe->list, &master_pe->slaves); 429 } 430 } 431 432 kfree(pe_alloc); 433 return master_pe; 434 } 435 436 static void __init pnv_ioda_parse_m64_window(struct pnv_phb *phb) 437 { 438 struct pci_controller *hose = phb->hose; 439 struct device_node *dn = hose->dn; 440 struct resource *res; 441 u32 m64_range[2], i; 442 const __be32 *r; 443 u64 pci_addr; 444 445 if (phb->type != PNV_PHB_IODA1 && phb->type != PNV_PHB_IODA2) { 446 pr_info(" Not support M64 window\n"); 447 return; 448 } 449 450 if (!firmware_has_feature(FW_FEATURE_OPAL)) { 451 pr_info(" Firmware too old to support M64 window\n"); 452 return; 453 } 454 455 r = of_get_property(dn, "ibm,opal-m64-window", NULL); 456 if (!r) { 457 pr_info(" No <ibm,opal-m64-window> on %pOF\n", 458 dn); 459 return; 460 } 461 462 /* 463 * Find the available M64 BAR range and pickup the last one for 464 * covering the whole 64-bits space. We support only one range. 465 */ 466 if (of_property_read_u32_array(dn, "ibm,opal-available-m64-ranges", 467 m64_range, 2)) { 468 /* In absence of the property, assume 0..15 */ 469 m64_range[0] = 0; 470 m64_range[1] = 16; 471 } 472 /* We only support 64 bits in our allocator */ 473 if (m64_range[1] > 63) { 474 pr_warn("%s: Limiting M64 range to 63 (from %d) on PHB#%x\n", 475 __func__, m64_range[1], phb->hose->global_number); 476 m64_range[1] = 63; 477 } 478 /* Empty range, no m64 */ 479 if (m64_range[1] <= m64_range[0]) { 480 pr_warn("%s: M64 empty, disabling M64 usage on PHB#%x\n", 481 __func__, phb->hose->global_number); 482 return; 483 } 484 485 /* Configure M64 informations */ 486 res = &hose->mem_resources[1]; 487 res->name = dn->full_name; 488 res->start = of_translate_address(dn, r + 2); 489 res->end = res->start + of_read_number(r + 4, 2) - 1; 490 res->flags = (IORESOURCE_MEM | IORESOURCE_MEM_64 | IORESOURCE_PREFETCH); 491 pci_addr = of_read_number(r, 2); 492 hose->mem_offset[1] = res->start - pci_addr; 493 494 phb->ioda.m64_size = resource_size(res); 495 phb->ioda.m64_segsize = phb->ioda.m64_size / phb->ioda.total_pe_num; 496 phb->ioda.m64_base = pci_addr; 497 498 /* This lines up nicely with the display from processing OF ranges */ 499 pr_info(" MEM 0x%016llx..0x%016llx -> 0x%016llx (M64 #%d..%d)\n", 500 res->start, res->end, pci_addr, m64_range[0], 501 m64_range[0] + m64_range[1] - 1); 502 503 /* Mark all M64 used up by default */ 504 phb->ioda.m64_bar_alloc = (unsigned long)-1; 505 506 /* Use last M64 BAR to cover M64 window */ 507 m64_range[1]--; 508 phb->ioda.m64_bar_idx = m64_range[0] + m64_range[1]; 509 510 pr_info(" Using M64 #%d as default window\n", phb->ioda.m64_bar_idx); 511 512 /* Mark remaining ones free */ 513 for (i = m64_range[0]; i < m64_range[1]; i++) 514 clear_bit(i, &phb->ioda.m64_bar_alloc); 515 516 /* 517 * Setup init functions for M64 based on IODA version, IODA3 uses 518 * the IODA2 code. 519 */ 520 if (phb->type == PNV_PHB_IODA1) 521 phb->init_m64 = pnv_ioda1_init_m64; 522 else 523 phb->init_m64 = pnv_ioda2_init_m64; 524 } 525 526 static void pnv_ioda_freeze_pe(struct pnv_phb *phb, int pe_no) 527 { 528 struct pnv_ioda_pe *pe = &phb->ioda.pe_array[pe_no]; 529 struct pnv_ioda_pe *slave; 530 s64 rc; 531 532 /* Fetch master PE */ 533 if (pe->flags & PNV_IODA_PE_SLAVE) { 534 pe = pe->master; 535 if (WARN_ON(!pe || !(pe->flags & PNV_IODA_PE_MASTER))) 536 return; 537 538 pe_no = pe->pe_number; 539 } 540 541 /* Freeze master PE */ 542 rc = opal_pci_eeh_freeze_set(phb->opal_id, 543 pe_no, 544 OPAL_EEH_ACTION_SET_FREEZE_ALL); 545 if (rc != OPAL_SUCCESS) { 546 pr_warn("%s: Failure %lld freezing PHB#%x-PE#%x\n", 547 __func__, rc, phb->hose->global_number, pe_no); 548 return; 549 } 550 551 /* Freeze slave PEs */ 552 if (!(pe->flags & PNV_IODA_PE_MASTER)) 553 return; 554 555 list_for_each_entry(slave, &pe->slaves, list) { 556 rc = opal_pci_eeh_freeze_set(phb->opal_id, 557 slave->pe_number, 558 OPAL_EEH_ACTION_SET_FREEZE_ALL); 559 if (rc != OPAL_SUCCESS) 560 pr_warn("%s: Failure %lld freezing PHB#%x-PE#%x\n", 561 __func__, rc, phb->hose->global_number, 562 slave->pe_number); 563 } 564 } 565 566 static int pnv_ioda_unfreeze_pe(struct pnv_phb *phb, int pe_no, int opt) 567 { 568 struct pnv_ioda_pe *pe, *slave; 569 s64 rc; 570 571 /* Find master PE */ 572 pe = &phb->ioda.pe_array[pe_no]; 573 if (pe->flags & PNV_IODA_PE_SLAVE) { 574 pe = pe->master; 575 WARN_ON(!pe || !(pe->flags & PNV_IODA_PE_MASTER)); 576 pe_no = pe->pe_number; 577 } 578 579 /* Clear frozen state for master PE */ 580 rc = opal_pci_eeh_freeze_clear(phb->opal_id, pe_no, opt); 581 if (rc != OPAL_SUCCESS) { 582 pr_warn("%s: Failure %lld clear %d on PHB#%x-PE#%x\n", 583 __func__, rc, opt, phb->hose->global_number, pe_no); 584 return -EIO; 585 } 586 587 if (!(pe->flags & PNV_IODA_PE_MASTER)) 588 return 0; 589 590 /* Clear frozen state for slave PEs */ 591 list_for_each_entry(slave, &pe->slaves, list) { 592 rc = opal_pci_eeh_freeze_clear(phb->opal_id, 593 slave->pe_number, 594 opt); 595 if (rc != OPAL_SUCCESS) { 596 pr_warn("%s: Failure %lld clear %d on PHB#%x-PE#%x\n", 597 __func__, rc, opt, phb->hose->global_number, 598 slave->pe_number); 599 return -EIO; 600 } 601 } 602 603 return 0; 604 } 605 606 static int pnv_ioda_get_pe_state(struct pnv_phb *phb, int pe_no) 607 { 608 struct pnv_ioda_pe *slave, *pe; 609 u8 fstate = 0, state; 610 __be16 pcierr = 0; 611 s64 rc; 612 613 /* Sanity check on PE number */ 614 if (pe_no < 0 || pe_no >= phb->ioda.total_pe_num) 615 return OPAL_EEH_STOPPED_PERM_UNAVAIL; 616 617 /* 618 * Fetch the master PE and the PE instance might be 619 * not initialized yet. 620 */ 621 pe = &phb->ioda.pe_array[pe_no]; 622 if (pe->flags & PNV_IODA_PE_SLAVE) { 623 pe = pe->master; 624 WARN_ON(!pe || !(pe->flags & PNV_IODA_PE_MASTER)); 625 pe_no = pe->pe_number; 626 } 627 628 /* Check the master PE */ 629 rc = opal_pci_eeh_freeze_status(phb->opal_id, pe_no, 630 &state, &pcierr, NULL); 631 if (rc != OPAL_SUCCESS) { 632 pr_warn("%s: Failure %lld getting " 633 "PHB#%x-PE#%x state\n", 634 __func__, rc, 635 phb->hose->global_number, pe_no); 636 return OPAL_EEH_STOPPED_TEMP_UNAVAIL; 637 } 638 639 /* Check the slave PE */ 640 if (!(pe->flags & PNV_IODA_PE_MASTER)) 641 return state; 642 643 list_for_each_entry(slave, &pe->slaves, list) { 644 rc = opal_pci_eeh_freeze_status(phb->opal_id, 645 slave->pe_number, 646 &fstate, 647 &pcierr, 648 NULL); 649 if (rc != OPAL_SUCCESS) { 650 pr_warn("%s: Failure %lld getting " 651 "PHB#%x-PE#%x state\n", 652 __func__, rc, 653 phb->hose->global_number, slave->pe_number); 654 return OPAL_EEH_STOPPED_TEMP_UNAVAIL; 655 } 656 657 /* 658 * Override the result based on the ascending 659 * priority. 660 */ 661 if (fstate > state) 662 state = fstate; 663 } 664 665 return state; 666 } 667 668 struct pnv_ioda_pe *pnv_pci_bdfn_to_pe(struct pnv_phb *phb, u16 bdfn) 669 { 670 int pe_number = phb->ioda.pe_rmap[bdfn]; 671 672 if (pe_number == IODA_INVALID_PE) 673 return NULL; 674 675 return &phb->ioda.pe_array[pe_number]; 676 } 677 678 struct pnv_ioda_pe *pnv_ioda_get_pe(struct pci_dev *dev) 679 { 680 struct pnv_phb *phb = pci_bus_to_pnvhb(dev->bus); 681 struct pci_dn *pdn = pci_get_pdn(dev); 682 683 if (!pdn) 684 return NULL; 685 if (pdn->pe_number == IODA_INVALID_PE) 686 return NULL; 687 return &phb->ioda.pe_array[pdn->pe_number]; 688 } 689 690 static int pnv_ioda_set_one_peltv(struct pnv_phb *phb, 691 struct pnv_ioda_pe *parent, 692 struct pnv_ioda_pe *child, 693 bool is_add) 694 { 695 const char *desc = is_add ? "adding" : "removing"; 696 uint8_t op = is_add ? OPAL_ADD_PE_TO_DOMAIN : 697 OPAL_REMOVE_PE_FROM_DOMAIN; 698 struct pnv_ioda_pe *slave; 699 long rc; 700 701 /* Parent PE affects child PE */ 702 rc = opal_pci_set_peltv(phb->opal_id, parent->pe_number, 703 child->pe_number, op); 704 if (rc != OPAL_SUCCESS) { 705 pe_warn(child, "OPAL error %ld %s to parent PELTV\n", 706 rc, desc); 707 return -ENXIO; 708 } 709 710 if (!(child->flags & PNV_IODA_PE_MASTER)) 711 return 0; 712 713 /* Compound case: parent PE affects slave PEs */ 714 list_for_each_entry(slave, &child->slaves, list) { 715 rc = opal_pci_set_peltv(phb->opal_id, parent->pe_number, 716 slave->pe_number, op); 717 if (rc != OPAL_SUCCESS) { 718 pe_warn(slave, "OPAL error %ld %s to parent PELTV\n", 719 rc, desc); 720 return -ENXIO; 721 } 722 } 723 724 return 0; 725 } 726 727 static int pnv_ioda_set_peltv(struct pnv_phb *phb, 728 struct pnv_ioda_pe *pe, 729 bool is_add) 730 { 731 struct pnv_ioda_pe *slave; 732 struct pci_dev *pdev = NULL; 733 int ret; 734 735 /* 736 * Clear PE frozen state. If it's master PE, we need 737 * clear slave PE frozen state as well. 738 */ 739 if (is_add) { 740 opal_pci_eeh_freeze_clear(phb->opal_id, pe->pe_number, 741 OPAL_EEH_ACTION_CLEAR_FREEZE_ALL); 742 if (pe->flags & PNV_IODA_PE_MASTER) { 743 list_for_each_entry(slave, &pe->slaves, list) 744 opal_pci_eeh_freeze_clear(phb->opal_id, 745 slave->pe_number, 746 OPAL_EEH_ACTION_CLEAR_FREEZE_ALL); 747 } 748 } 749 750 /* 751 * Associate PE in PELT. We need add the PE into the 752 * corresponding PELT-V as well. Otherwise, the error 753 * originated from the PE might contribute to other 754 * PEs. 755 */ 756 ret = pnv_ioda_set_one_peltv(phb, pe, pe, is_add); 757 if (ret) 758 return ret; 759 760 /* For compound PEs, any one affects all of them */ 761 if (pe->flags & PNV_IODA_PE_MASTER) { 762 list_for_each_entry(slave, &pe->slaves, list) { 763 ret = pnv_ioda_set_one_peltv(phb, slave, pe, is_add); 764 if (ret) 765 return ret; 766 } 767 } 768 769 if (pe->flags & (PNV_IODA_PE_BUS_ALL | PNV_IODA_PE_BUS)) 770 pdev = pe->pbus->self; 771 else if (pe->flags & PNV_IODA_PE_DEV) 772 pdev = pe->pdev->bus->self; 773 #ifdef CONFIG_PCI_IOV 774 else if (pe->flags & PNV_IODA_PE_VF) 775 pdev = pe->parent_dev; 776 #endif /* CONFIG_PCI_IOV */ 777 while (pdev) { 778 struct pci_dn *pdn = pci_get_pdn(pdev); 779 struct pnv_ioda_pe *parent; 780 781 if (pdn && pdn->pe_number != IODA_INVALID_PE) { 782 parent = &phb->ioda.pe_array[pdn->pe_number]; 783 ret = pnv_ioda_set_one_peltv(phb, parent, pe, is_add); 784 if (ret) 785 return ret; 786 } 787 788 pdev = pdev->bus->self; 789 } 790 791 return 0; 792 } 793 794 static void pnv_ioda_unset_peltv(struct pnv_phb *phb, 795 struct pnv_ioda_pe *pe, 796 struct pci_dev *parent) 797 { 798 int64_t rc; 799 800 while (parent) { 801 struct pci_dn *pdn = pci_get_pdn(parent); 802 803 if (pdn && pdn->pe_number != IODA_INVALID_PE) { 804 rc = opal_pci_set_peltv(phb->opal_id, pdn->pe_number, 805 pe->pe_number, 806 OPAL_REMOVE_PE_FROM_DOMAIN); 807 /* XXX What to do in case of error ? */ 808 } 809 parent = parent->bus->self; 810 } 811 812 opal_pci_eeh_freeze_clear(phb->opal_id, pe->pe_number, 813 OPAL_EEH_ACTION_CLEAR_FREEZE_ALL); 814 815 /* Disassociate PE in PELT */ 816 rc = opal_pci_set_peltv(phb->opal_id, pe->pe_number, 817 pe->pe_number, OPAL_REMOVE_PE_FROM_DOMAIN); 818 if (rc) 819 pe_warn(pe, "OPAL error %lld remove self from PELTV\n", rc); 820 } 821 822 int pnv_ioda_deconfigure_pe(struct pnv_phb *phb, struct pnv_ioda_pe *pe) 823 { 824 struct pci_dev *parent; 825 uint8_t bcomp, dcomp, fcomp; 826 int64_t rc; 827 long rid_end, rid; 828 829 /* Currently, we just deconfigure VF PE. Bus PE will always there.*/ 830 if (pe->pbus) { 831 int count; 832 833 dcomp = OPAL_IGNORE_RID_DEVICE_NUMBER; 834 fcomp = OPAL_IGNORE_RID_FUNCTION_NUMBER; 835 parent = pe->pbus->self; 836 if (pe->flags & PNV_IODA_PE_BUS_ALL) 837 count = resource_size(&pe->pbus->busn_res); 838 else 839 count = 1; 840 841 switch(count) { 842 case 1: bcomp = OpalPciBusAll; break; 843 case 2: bcomp = OpalPciBus7Bits; break; 844 case 4: bcomp = OpalPciBus6Bits; break; 845 case 8: bcomp = OpalPciBus5Bits; break; 846 case 16: bcomp = OpalPciBus4Bits; break; 847 case 32: bcomp = OpalPciBus3Bits; break; 848 default: 849 dev_err(&pe->pbus->dev, "Number of subordinate buses %d unsupported\n", 850 count); 851 /* Do an exact match only */ 852 bcomp = OpalPciBusAll; 853 } 854 rid_end = pe->rid + (count << 8); 855 } else { 856 #ifdef CONFIG_PCI_IOV 857 if (pe->flags & PNV_IODA_PE_VF) 858 parent = pe->parent_dev; 859 else 860 #endif 861 parent = pe->pdev->bus->self; 862 bcomp = OpalPciBusAll; 863 dcomp = OPAL_COMPARE_RID_DEVICE_NUMBER; 864 fcomp = OPAL_COMPARE_RID_FUNCTION_NUMBER; 865 rid_end = pe->rid + 1; 866 } 867 868 /* Clear the reverse map */ 869 for (rid = pe->rid; rid < rid_end; rid++) 870 phb->ioda.pe_rmap[rid] = IODA_INVALID_PE; 871 872 /* 873 * Release from all parents PELT-V. NPUs don't have a PELTV 874 * table 875 */ 876 if (phb->type != PNV_PHB_NPU_OCAPI) 877 pnv_ioda_unset_peltv(phb, pe, parent); 878 879 rc = opal_pci_set_pe(phb->opal_id, pe->pe_number, pe->rid, 880 bcomp, dcomp, fcomp, OPAL_UNMAP_PE); 881 if (rc) 882 pe_err(pe, "OPAL error %lld trying to setup PELT table\n", rc); 883 884 pe->pbus = NULL; 885 pe->pdev = NULL; 886 #ifdef CONFIG_PCI_IOV 887 pe->parent_dev = NULL; 888 #endif 889 890 return 0; 891 } 892 893 int pnv_ioda_configure_pe(struct pnv_phb *phb, struct pnv_ioda_pe *pe) 894 { 895 uint8_t bcomp, dcomp, fcomp; 896 long rc, rid_end, rid; 897 898 /* Bus validation ? */ 899 if (pe->pbus) { 900 int count; 901 902 dcomp = OPAL_IGNORE_RID_DEVICE_NUMBER; 903 fcomp = OPAL_IGNORE_RID_FUNCTION_NUMBER; 904 if (pe->flags & PNV_IODA_PE_BUS_ALL) 905 count = resource_size(&pe->pbus->busn_res); 906 else 907 count = 1; 908 909 switch(count) { 910 case 1: bcomp = OpalPciBusAll; break; 911 case 2: bcomp = OpalPciBus7Bits; break; 912 case 4: bcomp = OpalPciBus6Bits; break; 913 case 8: bcomp = OpalPciBus5Bits; break; 914 case 16: bcomp = OpalPciBus4Bits; break; 915 case 32: bcomp = OpalPciBus3Bits; break; 916 default: 917 dev_err(&pe->pbus->dev, "Number of subordinate buses %d unsupported\n", 918 count); 919 /* Do an exact match only */ 920 bcomp = OpalPciBusAll; 921 } 922 rid_end = pe->rid + (count << 8); 923 } else { 924 bcomp = OpalPciBusAll; 925 dcomp = OPAL_COMPARE_RID_DEVICE_NUMBER; 926 fcomp = OPAL_COMPARE_RID_FUNCTION_NUMBER; 927 rid_end = pe->rid + 1; 928 } 929 930 /* 931 * Associate PE in PELT. We need add the PE into the 932 * corresponding PELT-V as well. Otherwise, the error 933 * originated from the PE might contribute to other 934 * PEs. 935 */ 936 rc = opal_pci_set_pe(phb->opal_id, pe->pe_number, pe->rid, 937 bcomp, dcomp, fcomp, OPAL_MAP_PE); 938 if (rc) { 939 pe_err(pe, "OPAL error %ld trying to setup PELT table\n", rc); 940 return -ENXIO; 941 } 942 943 /* 944 * Configure PELTV. NPUs don't have a PELTV table so skip 945 * configuration on them. 946 */ 947 if (phb->type != PNV_PHB_NPU_OCAPI) 948 pnv_ioda_set_peltv(phb, pe, true); 949 950 /* Setup reverse map */ 951 for (rid = pe->rid; rid < rid_end; rid++) 952 phb->ioda.pe_rmap[rid] = pe->pe_number; 953 954 /* Setup one MVTs on IODA1 */ 955 if (phb->type != PNV_PHB_IODA1) { 956 pe->mve_number = 0; 957 goto out; 958 } 959 960 pe->mve_number = pe->pe_number; 961 rc = opal_pci_set_mve(phb->opal_id, pe->mve_number, pe->pe_number); 962 if (rc != OPAL_SUCCESS) { 963 pe_err(pe, "OPAL error %ld setting up MVE %x\n", 964 rc, pe->mve_number); 965 pe->mve_number = -1; 966 } else { 967 rc = opal_pci_set_mve_enable(phb->opal_id, 968 pe->mve_number, OPAL_ENABLE_MVE); 969 if (rc) { 970 pe_err(pe, "OPAL error %ld enabling MVE %x\n", 971 rc, pe->mve_number); 972 pe->mve_number = -1; 973 } 974 } 975 976 out: 977 return 0; 978 } 979 980 static struct pnv_ioda_pe *pnv_ioda_setup_dev_PE(struct pci_dev *dev) 981 { 982 struct pnv_phb *phb = pci_bus_to_pnvhb(dev->bus); 983 struct pci_dn *pdn = pci_get_pdn(dev); 984 struct pnv_ioda_pe *pe; 985 986 if (!pdn) { 987 pr_err("%s: Device tree node not associated properly\n", 988 pci_name(dev)); 989 return NULL; 990 } 991 if (pdn->pe_number != IODA_INVALID_PE) 992 return NULL; 993 994 pe = pnv_ioda_alloc_pe(phb, 1); 995 if (!pe) { 996 pr_warn("%s: Not enough PE# available, disabling device\n", 997 pci_name(dev)); 998 return NULL; 999 } 1000 1001 /* NOTE: We don't get a reference for the pointer in the PE 1002 * data structure, both the device and PE structures should be 1003 * destroyed at the same time. 1004 * 1005 * At some point we want to remove the PDN completely anyways 1006 */ 1007 pdn->pe_number = pe->pe_number; 1008 pe->flags = PNV_IODA_PE_DEV; 1009 pe->pdev = dev; 1010 pe->pbus = NULL; 1011 pe->mve_number = -1; 1012 pe->rid = dev->bus->number << 8 | pdn->devfn; 1013 pe->device_count++; 1014 1015 pe_info(pe, "Associated device to PE\n"); 1016 1017 if (pnv_ioda_configure_pe(phb, pe)) { 1018 /* XXX What do we do here ? */ 1019 pnv_ioda_free_pe(pe); 1020 pdn->pe_number = IODA_INVALID_PE; 1021 pe->pdev = NULL; 1022 return NULL; 1023 } 1024 1025 /* Put PE to the list */ 1026 mutex_lock(&phb->ioda.pe_list_mutex); 1027 list_add_tail(&pe->list, &phb->ioda.pe_list); 1028 mutex_unlock(&phb->ioda.pe_list_mutex); 1029 return pe; 1030 } 1031 1032 /* 1033 * There're 2 types of PCI bus sensitive PEs: One that is compromised of 1034 * single PCI bus. Another one that contains the primary PCI bus and its 1035 * subordinate PCI devices and buses. The second type of PE is normally 1036 * orgiriated by PCIe-to-PCI bridge or PLX switch downstream ports. 1037 */ 1038 static struct pnv_ioda_pe *pnv_ioda_setup_bus_PE(struct pci_bus *bus, bool all) 1039 { 1040 struct pnv_phb *phb = pci_bus_to_pnvhb(bus); 1041 struct pnv_ioda_pe *pe = NULL; 1042 unsigned int pe_num; 1043 1044 /* 1045 * In partial hotplug case, the PE instance might be still alive. 1046 * We should reuse it instead of allocating a new one. 1047 */ 1048 pe_num = phb->ioda.pe_rmap[bus->number << 8]; 1049 if (WARN_ON(pe_num != IODA_INVALID_PE)) { 1050 pe = &phb->ioda.pe_array[pe_num]; 1051 return NULL; 1052 } 1053 1054 /* PE number for root bus should have been reserved */ 1055 if (pci_is_root_bus(bus)) 1056 pe = &phb->ioda.pe_array[phb->ioda.root_pe_idx]; 1057 1058 /* Check if PE is determined by M64 */ 1059 if (!pe) 1060 pe = pnv_ioda_pick_m64_pe(bus, all); 1061 1062 /* The PE number isn't pinned by M64 */ 1063 if (!pe) 1064 pe = pnv_ioda_alloc_pe(phb, 1); 1065 1066 if (!pe) { 1067 pr_warn("%s: Not enough PE# available for PCI bus %04x:%02x\n", 1068 __func__, pci_domain_nr(bus), bus->number); 1069 return NULL; 1070 } 1071 1072 pe->flags |= (all ? PNV_IODA_PE_BUS_ALL : PNV_IODA_PE_BUS); 1073 pe->pbus = bus; 1074 pe->pdev = NULL; 1075 pe->mve_number = -1; 1076 pe->rid = bus->busn_res.start << 8; 1077 1078 if (all) 1079 pe_info(pe, "Secondary bus %pad..%pad associated with PE#%x\n", 1080 &bus->busn_res.start, &bus->busn_res.end, 1081 pe->pe_number); 1082 else 1083 pe_info(pe, "Secondary bus %pad associated with PE#%x\n", 1084 &bus->busn_res.start, pe->pe_number); 1085 1086 if (pnv_ioda_configure_pe(phb, pe)) { 1087 /* XXX What do we do here ? */ 1088 pnv_ioda_free_pe(pe); 1089 pe->pbus = NULL; 1090 return NULL; 1091 } 1092 1093 /* Put PE to the list */ 1094 list_add_tail(&pe->list, &phb->ioda.pe_list); 1095 1096 return pe; 1097 } 1098 1099 static void pnv_pci_ioda1_setup_dma_pe(struct pnv_phb *phb, 1100 struct pnv_ioda_pe *pe); 1101 1102 static void pnv_pci_ioda_dma_dev_setup(struct pci_dev *pdev) 1103 { 1104 struct pnv_phb *phb = pci_bus_to_pnvhb(pdev->bus); 1105 struct pci_dn *pdn = pci_get_pdn(pdev); 1106 struct pnv_ioda_pe *pe; 1107 1108 /* Check if the BDFN for this device is associated with a PE yet */ 1109 pe = pnv_pci_bdfn_to_pe(phb, pdev->devfn | (pdev->bus->number << 8)); 1110 if (!pe) { 1111 /* VF PEs should be pre-configured in pnv_pci_sriov_enable() */ 1112 if (WARN_ON(pdev->is_virtfn)) 1113 return; 1114 1115 pnv_pci_configure_bus(pdev->bus); 1116 pe = pnv_pci_bdfn_to_pe(phb, pdev->devfn | (pdev->bus->number << 8)); 1117 pci_info(pdev, "Configured PE#%x\n", pe ? pe->pe_number : 0xfffff); 1118 1119 1120 /* 1121 * If we can't setup the IODA PE something has gone horribly 1122 * wrong and we can't enable DMA for the device. 1123 */ 1124 if (WARN_ON(!pe)) 1125 return; 1126 } else { 1127 pci_info(pdev, "Added to existing PE#%x\n", pe->pe_number); 1128 } 1129 1130 /* 1131 * We assume that bridges *probably* don't need to do any DMA so we can 1132 * skip allocating a TCE table, etc unless we get a non-bridge device. 1133 */ 1134 if (!pe->dma_setup_done && !pci_is_bridge(pdev)) { 1135 switch (phb->type) { 1136 case PNV_PHB_IODA1: 1137 pnv_pci_ioda1_setup_dma_pe(phb, pe); 1138 break; 1139 case PNV_PHB_IODA2: 1140 pnv_pci_ioda2_setup_dma_pe(phb, pe); 1141 break; 1142 default: 1143 pr_warn("%s: No DMA for PHB#%x (type %d)\n", 1144 __func__, phb->hose->global_number, phb->type); 1145 } 1146 } 1147 1148 if (pdn) 1149 pdn->pe_number = pe->pe_number; 1150 pe->device_count++; 1151 1152 WARN_ON(get_dma_ops(&pdev->dev) != &dma_iommu_ops); 1153 pdev->dev.archdata.dma_offset = pe->tce_bypass_base; 1154 set_iommu_table_base(&pdev->dev, pe->table_group.tables[0]); 1155 1156 /* PEs with a DMA weight of zero won't have a group */ 1157 if (pe->table_group.group) 1158 iommu_add_device(&pe->table_group, &pdev->dev); 1159 } 1160 1161 /* 1162 * Reconfigure TVE#0 to be usable as 64-bit DMA space. 1163 * 1164 * The first 4GB of virtual memory for a PE is reserved for 32-bit accesses. 1165 * Devices can only access more than that if bit 59 of the PCI address is set 1166 * by hardware, which indicates TVE#1 should be used instead of TVE#0. 1167 * Many PCI devices are not capable of addressing that many bits, and as a 1168 * result are limited to the 4GB of virtual memory made available to 32-bit 1169 * devices in TVE#0. 1170 * 1171 * In order to work around this, reconfigure TVE#0 to be suitable for 64-bit 1172 * devices by configuring the virtual memory past the first 4GB inaccessible 1173 * by 64-bit DMAs. This should only be used by devices that want more than 1174 * 4GB, and only on PEs that have no 32-bit devices. 1175 * 1176 * Currently this will only work on PHB3 (POWER8). 1177 */ 1178 static int pnv_pci_ioda_dma_64bit_bypass(struct pnv_ioda_pe *pe) 1179 { 1180 u64 window_size, table_size, tce_count, addr; 1181 struct page *table_pages; 1182 u64 tce_order = 28; /* 256MB TCEs */ 1183 __be64 *tces; 1184 s64 rc; 1185 1186 /* 1187 * Window size needs to be a power of two, but needs to account for 1188 * shifting memory by the 4GB offset required to skip 32bit space. 1189 */ 1190 window_size = roundup_pow_of_two(memory_hotplug_max() + (1ULL << 32)); 1191 tce_count = window_size >> tce_order; 1192 table_size = tce_count << 3; 1193 1194 if (table_size < PAGE_SIZE) 1195 table_size = PAGE_SIZE; 1196 1197 table_pages = alloc_pages_node(pe->phb->hose->node, GFP_KERNEL, 1198 get_order(table_size)); 1199 if (!table_pages) 1200 goto err; 1201 1202 tces = page_address(table_pages); 1203 if (!tces) 1204 goto err; 1205 1206 memset(tces, 0, table_size); 1207 1208 for (addr = 0; addr < memory_hotplug_max(); addr += (1 << tce_order)) { 1209 tces[(addr + (1ULL << 32)) >> tce_order] = 1210 cpu_to_be64(addr | TCE_PCI_READ | TCE_PCI_WRITE); 1211 } 1212 1213 rc = opal_pci_map_pe_dma_window(pe->phb->opal_id, 1214 pe->pe_number, 1215 /* reconfigure window 0 */ 1216 (pe->pe_number << 1) + 0, 1217 1, 1218 __pa(tces), 1219 table_size, 1220 1 << tce_order); 1221 if (rc == OPAL_SUCCESS) { 1222 pe_info(pe, "Using 64-bit DMA iommu bypass (through TVE#0)\n"); 1223 return 0; 1224 } 1225 err: 1226 pe_err(pe, "Error configuring 64-bit DMA bypass\n"); 1227 return -EIO; 1228 } 1229 1230 static bool pnv_pci_ioda_iommu_bypass_supported(struct pci_dev *pdev, 1231 u64 dma_mask) 1232 { 1233 struct pnv_phb *phb = pci_bus_to_pnvhb(pdev->bus); 1234 struct pci_dn *pdn = pci_get_pdn(pdev); 1235 struct pnv_ioda_pe *pe; 1236 1237 if (WARN_ON(!pdn || pdn->pe_number == IODA_INVALID_PE)) 1238 return false; 1239 1240 pe = &phb->ioda.pe_array[pdn->pe_number]; 1241 if (pe->tce_bypass_enabled) { 1242 u64 top = pe->tce_bypass_base + memblock_end_of_DRAM() - 1; 1243 if (dma_mask >= top) 1244 return true; 1245 } 1246 1247 /* 1248 * If the device can't set the TCE bypass bit but still wants 1249 * to access 4GB or more, on PHB3 we can reconfigure TVE#0 to 1250 * bypass the 32-bit region and be usable for 64-bit DMAs. 1251 * The device needs to be able to address all of this space. 1252 */ 1253 if (dma_mask >> 32 && 1254 dma_mask > (memory_hotplug_max() + (1ULL << 32)) && 1255 /* pe->pdev should be set if it's a single device, pe->pbus if not */ 1256 (pe->device_count == 1 || !pe->pbus) && 1257 phb->model == PNV_PHB_MODEL_PHB3) { 1258 /* Configure the bypass mode */ 1259 s64 rc = pnv_pci_ioda_dma_64bit_bypass(pe); 1260 if (rc) 1261 return false; 1262 /* 4GB offset bypasses 32-bit space */ 1263 pdev->dev.archdata.dma_offset = (1ULL << 32); 1264 return true; 1265 } 1266 1267 return false; 1268 } 1269 1270 static inline __be64 __iomem *pnv_ioda_get_inval_reg(struct pnv_phb *phb, 1271 bool real_mode) 1272 { 1273 return real_mode ? (__be64 __iomem *)(phb->regs_phys + 0x210) : 1274 (phb->regs + 0x210); 1275 } 1276 1277 static void pnv_pci_p7ioc_tce_invalidate(struct iommu_table *tbl, 1278 unsigned long index, unsigned long npages, bool rm) 1279 { 1280 struct iommu_table_group_link *tgl = list_first_entry_or_null( 1281 &tbl->it_group_list, struct iommu_table_group_link, 1282 next); 1283 struct pnv_ioda_pe *pe = container_of(tgl->table_group, 1284 struct pnv_ioda_pe, table_group); 1285 __be64 __iomem *invalidate = pnv_ioda_get_inval_reg(pe->phb, rm); 1286 unsigned long start, end, inc; 1287 1288 start = __pa(((__be64 *)tbl->it_base) + index - tbl->it_offset); 1289 end = __pa(((__be64 *)tbl->it_base) + index - tbl->it_offset + 1290 npages - 1); 1291 1292 /* p7ioc-style invalidation, 2 TCEs per write */ 1293 start |= (1ull << 63); 1294 end |= (1ull << 63); 1295 inc = 16; 1296 end |= inc - 1; /* round up end to be different than start */ 1297 1298 mb(); /* Ensure above stores are visible */ 1299 while (start <= end) { 1300 if (rm) 1301 __raw_rm_writeq_be(start, invalidate); 1302 else 1303 __raw_writeq_be(start, invalidate); 1304 1305 start += inc; 1306 } 1307 1308 /* 1309 * The iommu layer will do another mb() for us on build() 1310 * and we don't care on free() 1311 */ 1312 } 1313 1314 static int pnv_ioda1_tce_build(struct iommu_table *tbl, long index, 1315 long npages, unsigned long uaddr, 1316 enum dma_data_direction direction, 1317 unsigned long attrs) 1318 { 1319 int ret = pnv_tce_build(tbl, index, npages, uaddr, direction, 1320 attrs); 1321 1322 if (!ret) 1323 pnv_pci_p7ioc_tce_invalidate(tbl, index, npages, false); 1324 1325 return ret; 1326 } 1327 1328 #ifdef CONFIG_IOMMU_API 1329 /* Common for IODA1 and IODA2 */ 1330 static int pnv_ioda_tce_xchg_no_kill(struct iommu_table *tbl, long index, 1331 unsigned long *hpa, enum dma_data_direction *direction, 1332 bool realmode) 1333 { 1334 return pnv_tce_xchg(tbl, index, hpa, direction, !realmode); 1335 } 1336 #endif 1337 1338 static void pnv_ioda1_tce_free(struct iommu_table *tbl, long index, 1339 long npages) 1340 { 1341 pnv_tce_free(tbl, index, npages); 1342 1343 pnv_pci_p7ioc_tce_invalidate(tbl, index, npages, false); 1344 } 1345 1346 static struct iommu_table_ops pnv_ioda1_iommu_ops = { 1347 .set = pnv_ioda1_tce_build, 1348 #ifdef CONFIG_IOMMU_API 1349 .xchg_no_kill = pnv_ioda_tce_xchg_no_kill, 1350 .tce_kill = pnv_pci_p7ioc_tce_invalidate, 1351 .useraddrptr = pnv_tce_useraddrptr, 1352 #endif 1353 .clear = pnv_ioda1_tce_free, 1354 .get = pnv_tce_get, 1355 }; 1356 1357 #define PHB3_TCE_KILL_INVAL_ALL PPC_BIT(0) 1358 #define PHB3_TCE_KILL_INVAL_PE PPC_BIT(1) 1359 #define PHB3_TCE_KILL_INVAL_ONE PPC_BIT(2) 1360 1361 static inline void pnv_pci_phb3_tce_invalidate_pe(struct pnv_ioda_pe *pe) 1362 { 1363 /* 01xb - invalidate TCEs that match the specified PE# */ 1364 __be64 __iomem *invalidate = pnv_ioda_get_inval_reg(pe->phb, false); 1365 unsigned long val = PHB3_TCE_KILL_INVAL_PE | (pe->pe_number & 0xFF); 1366 1367 mb(); /* Ensure above stores are visible */ 1368 __raw_writeq_be(val, invalidate); 1369 } 1370 1371 static void pnv_pci_phb3_tce_invalidate(struct pnv_ioda_pe *pe, bool rm, 1372 unsigned shift, unsigned long index, 1373 unsigned long npages) 1374 { 1375 __be64 __iomem *invalidate = pnv_ioda_get_inval_reg(pe->phb, rm); 1376 unsigned long start, end, inc; 1377 1378 /* We'll invalidate DMA address in PE scope */ 1379 start = PHB3_TCE_KILL_INVAL_ONE; 1380 start |= (pe->pe_number & 0xFF); 1381 end = start; 1382 1383 /* Figure out the start, end and step */ 1384 start |= (index << shift); 1385 end |= ((index + npages - 1) << shift); 1386 inc = (0x1ull << shift); 1387 mb(); 1388 1389 while (start <= end) { 1390 if (rm) 1391 __raw_rm_writeq_be(start, invalidate); 1392 else 1393 __raw_writeq_be(start, invalidate); 1394 start += inc; 1395 } 1396 } 1397 1398 static inline void pnv_pci_ioda2_tce_invalidate_pe(struct pnv_ioda_pe *pe) 1399 { 1400 struct pnv_phb *phb = pe->phb; 1401 1402 if (phb->model == PNV_PHB_MODEL_PHB3 && phb->regs) 1403 pnv_pci_phb3_tce_invalidate_pe(pe); 1404 else 1405 opal_pci_tce_kill(phb->opal_id, OPAL_PCI_TCE_KILL_PE, 1406 pe->pe_number, 0, 0, 0); 1407 } 1408 1409 static void pnv_pci_ioda2_tce_invalidate(struct iommu_table *tbl, 1410 unsigned long index, unsigned long npages, bool rm) 1411 { 1412 struct iommu_table_group_link *tgl; 1413 1414 list_for_each_entry_lockless(tgl, &tbl->it_group_list, next) { 1415 struct pnv_ioda_pe *pe = container_of(tgl->table_group, 1416 struct pnv_ioda_pe, table_group); 1417 struct pnv_phb *phb = pe->phb; 1418 unsigned int shift = tbl->it_page_shift; 1419 1420 if (phb->model == PNV_PHB_MODEL_PHB3 && phb->regs) 1421 pnv_pci_phb3_tce_invalidate(pe, rm, shift, 1422 index, npages); 1423 else 1424 opal_pci_tce_kill(phb->opal_id, 1425 OPAL_PCI_TCE_KILL_PAGES, 1426 pe->pe_number, 1u << shift, 1427 index << shift, npages); 1428 } 1429 } 1430 1431 static int pnv_ioda2_tce_build(struct iommu_table *tbl, long index, 1432 long npages, unsigned long uaddr, 1433 enum dma_data_direction direction, 1434 unsigned long attrs) 1435 { 1436 int ret = pnv_tce_build(tbl, index, npages, uaddr, direction, 1437 attrs); 1438 1439 if (!ret) 1440 pnv_pci_ioda2_tce_invalidate(tbl, index, npages, false); 1441 1442 return ret; 1443 } 1444 1445 static void pnv_ioda2_tce_free(struct iommu_table *tbl, long index, 1446 long npages) 1447 { 1448 pnv_tce_free(tbl, index, npages); 1449 1450 pnv_pci_ioda2_tce_invalidate(tbl, index, npages, false); 1451 } 1452 1453 static struct iommu_table_ops pnv_ioda2_iommu_ops = { 1454 .set = pnv_ioda2_tce_build, 1455 #ifdef CONFIG_IOMMU_API 1456 .xchg_no_kill = pnv_ioda_tce_xchg_no_kill, 1457 .tce_kill = pnv_pci_ioda2_tce_invalidate, 1458 .useraddrptr = pnv_tce_useraddrptr, 1459 #endif 1460 .clear = pnv_ioda2_tce_free, 1461 .get = pnv_tce_get, 1462 .free = pnv_pci_ioda2_table_free_pages, 1463 }; 1464 1465 static int pnv_pci_ioda_dev_dma_weight(struct pci_dev *dev, void *data) 1466 { 1467 unsigned int *weight = (unsigned int *)data; 1468 1469 /* This is quite simplistic. The "base" weight of a device 1470 * is 10. 0 means no DMA is to be accounted for it. 1471 */ 1472 if (dev->hdr_type != PCI_HEADER_TYPE_NORMAL) 1473 return 0; 1474 1475 if (dev->class == PCI_CLASS_SERIAL_USB_UHCI || 1476 dev->class == PCI_CLASS_SERIAL_USB_OHCI || 1477 dev->class == PCI_CLASS_SERIAL_USB_EHCI) 1478 *weight += 3; 1479 else if ((dev->class >> 8) == PCI_CLASS_STORAGE_RAID) 1480 *weight += 15; 1481 else 1482 *weight += 10; 1483 1484 return 0; 1485 } 1486 1487 static unsigned int pnv_pci_ioda_pe_dma_weight(struct pnv_ioda_pe *pe) 1488 { 1489 unsigned int weight = 0; 1490 1491 /* SRIOV VF has same DMA32 weight as its PF */ 1492 #ifdef CONFIG_PCI_IOV 1493 if ((pe->flags & PNV_IODA_PE_VF) && pe->parent_dev) { 1494 pnv_pci_ioda_dev_dma_weight(pe->parent_dev, &weight); 1495 return weight; 1496 } 1497 #endif 1498 1499 if ((pe->flags & PNV_IODA_PE_DEV) && pe->pdev) { 1500 pnv_pci_ioda_dev_dma_weight(pe->pdev, &weight); 1501 } else if ((pe->flags & PNV_IODA_PE_BUS) && pe->pbus) { 1502 struct pci_dev *pdev; 1503 1504 list_for_each_entry(pdev, &pe->pbus->devices, bus_list) 1505 pnv_pci_ioda_dev_dma_weight(pdev, &weight); 1506 } else if ((pe->flags & PNV_IODA_PE_BUS_ALL) && pe->pbus) { 1507 pci_walk_bus(pe->pbus, pnv_pci_ioda_dev_dma_weight, &weight); 1508 } 1509 1510 return weight; 1511 } 1512 1513 static void pnv_pci_ioda1_setup_dma_pe(struct pnv_phb *phb, 1514 struct pnv_ioda_pe *pe) 1515 { 1516 1517 struct page *tce_mem = NULL; 1518 struct iommu_table *tbl; 1519 unsigned int weight, total_weight = 0; 1520 unsigned int tce32_segsz, base, segs, avail, i; 1521 int64_t rc; 1522 void *addr; 1523 1524 /* XXX FIXME: Handle 64-bit only DMA devices */ 1525 /* XXX FIXME: Provide 64-bit DMA facilities & non-4K TCE tables etc.. */ 1526 /* XXX FIXME: Allocate multi-level tables on PHB3 */ 1527 weight = pnv_pci_ioda_pe_dma_weight(pe); 1528 if (!weight) 1529 return; 1530 1531 pci_walk_bus(phb->hose->bus, pnv_pci_ioda_dev_dma_weight, 1532 &total_weight); 1533 segs = (weight * phb->ioda.dma32_count) / total_weight; 1534 if (!segs) 1535 segs = 1; 1536 1537 /* 1538 * Allocate contiguous DMA32 segments. We begin with the expected 1539 * number of segments. With one more attempt, the number of DMA32 1540 * segments to be allocated is decreased by one until one segment 1541 * is allocated successfully. 1542 */ 1543 do { 1544 for (base = 0; base <= phb->ioda.dma32_count - segs; base++) { 1545 for (avail = 0, i = base; i < base + segs; i++) { 1546 if (phb->ioda.dma32_segmap[i] == 1547 IODA_INVALID_PE) 1548 avail++; 1549 } 1550 1551 if (avail == segs) 1552 goto found; 1553 } 1554 } while (--segs); 1555 1556 if (!segs) { 1557 pe_warn(pe, "No available DMA32 segments\n"); 1558 return; 1559 } 1560 1561 found: 1562 tbl = pnv_pci_table_alloc(phb->hose->node); 1563 if (WARN_ON(!tbl)) 1564 return; 1565 1566 iommu_register_group(&pe->table_group, phb->hose->global_number, 1567 pe->pe_number); 1568 pnv_pci_link_table_and_group(phb->hose->node, 0, tbl, &pe->table_group); 1569 1570 /* Grab a 32-bit TCE table */ 1571 pe_info(pe, "DMA weight %d (%d), assigned (%d) %d DMA32 segments\n", 1572 weight, total_weight, base, segs); 1573 pe_info(pe, " Setting up 32-bit TCE table at %08x..%08x\n", 1574 base * PNV_IODA1_DMA32_SEGSIZE, 1575 (base + segs) * PNV_IODA1_DMA32_SEGSIZE - 1); 1576 1577 /* XXX Currently, we allocate one big contiguous table for the 1578 * TCEs. We only really need one chunk per 256M of TCE space 1579 * (ie per segment) but that's an optimization for later, it 1580 * requires some added smarts with our get/put_tce implementation 1581 * 1582 * Each TCE page is 4KB in size and each TCE entry occupies 8 1583 * bytes 1584 */ 1585 tce32_segsz = PNV_IODA1_DMA32_SEGSIZE >> (IOMMU_PAGE_SHIFT_4K - 3); 1586 tce_mem = alloc_pages_node(phb->hose->node, GFP_KERNEL, 1587 get_order(tce32_segsz * segs)); 1588 if (!tce_mem) { 1589 pe_err(pe, " Failed to allocate a 32-bit TCE memory\n"); 1590 goto fail; 1591 } 1592 addr = page_address(tce_mem); 1593 memset(addr, 0, tce32_segsz * segs); 1594 1595 /* Configure HW */ 1596 for (i = 0; i < segs; i++) { 1597 rc = opal_pci_map_pe_dma_window(phb->opal_id, 1598 pe->pe_number, 1599 base + i, 1, 1600 __pa(addr) + tce32_segsz * i, 1601 tce32_segsz, IOMMU_PAGE_SIZE_4K); 1602 if (rc) { 1603 pe_err(pe, " Failed to configure 32-bit TCE table, err %lld\n", 1604 rc); 1605 goto fail; 1606 } 1607 } 1608 1609 /* Setup DMA32 segment mapping */ 1610 for (i = base; i < base + segs; i++) 1611 phb->ioda.dma32_segmap[i] = pe->pe_number; 1612 1613 /* Setup linux iommu table */ 1614 pnv_pci_setup_iommu_table(tbl, addr, tce32_segsz * segs, 1615 base * PNV_IODA1_DMA32_SEGSIZE, 1616 IOMMU_PAGE_SHIFT_4K); 1617 1618 tbl->it_ops = &pnv_ioda1_iommu_ops; 1619 pe->table_group.tce32_start = tbl->it_offset << tbl->it_page_shift; 1620 pe->table_group.tce32_size = tbl->it_size << tbl->it_page_shift; 1621 if (!iommu_init_table(tbl, phb->hose->node, 0, 0)) 1622 panic("Failed to initialize iommu table"); 1623 1624 pe->dma_setup_done = true; 1625 return; 1626 fail: 1627 /* XXX Failure: Try to fallback to 64-bit only ? */ 1628 if (tce_mem) 1629 __free_pages(tce_mem, get_order(tce32_segsz * segs)); 1630 if (tbl) { 1631 pnv_pci_unlink_table_and_group(tbl, &pe->table_group); 1632 iommu_tce_table_put(tbl); 1633 } 1634 } 1635 1636 static long pnv_pci_ioda2_set_window(struct iommu_table_group *table_group, 1637 int num, struct iommu_table *tbl) 1638 { 1639 struct pnv_ioda_pe *pe = container_of(table_group, struct pnv_ioda_pe, 1640 table_group); 1641 struct pnv_phb *phb = pe->phb; 1642 int64_t rc; 1643 const unsigned long size = tbl->it_indirect_levels ? 1644 tbl->it_level_size : tbl->it_size; 1645 const __u64 start_addr = tbl->it_offset << tbl->it_page_shift; 1646 const __u64 win_size = tbl->it_size << tbl->it_page_shift; 1647 1648 pe_info(pe, "Setting up window#%d %llx..%llx pg=%lx\n", 1649 num, start_addr, start_addr + win_size - 1, 1650 IOMMU_PAGE_SIZE(tbl)); 1651 1652 /* 1653 * Map TCE table through TVT. The TVE index is the PE number 1654 * shifted by 1 bit for 32-bits DMA space. 1655 */ 1656 rc = opal_pci_map_pe_dma_window(phb->opal_id, 1657 pe->pe_number, 1658 (pe->pe_number << 1) + num, 1659 tbl->it_indirect_levels + 1, 1660 __pa(tbl->it_base), 1661 size << 3, 1662 IOMMU_PAGE_SIZE(tbl)); 1663 if (rc) { 1664 pe_err(pe, "Failed to configure TCE table, err %lld\n", rc); 1665 return rc; 1666 } 1667 1668 pnv_pci_link_table_and_group(phb->hose->node, num, 1669 tbl, &pe->table_group); 1670 pnv_pci_ioda2_tce_invalidate_pe(pe); 1671 1672 return 0; 1673 } 1674 1675 static void pnv_pci_ioda2_set_bypass(struct pnv_ioda_pe *pe, bool enable) 1676 { 1677 uint16_t window_id = (pe->pe_number << 1 ) + 1; 1678 int64_t rc; 1679 1680 pe_info(pe, "%sabling 64-bit DMA bypass\n", enable ? "En" : "Dis"); 1681 if (enable) { 1682 phys_addr_t top = memblock_end_of_DRAM(); 1683 1684 top = roundup_pow_of_two(top); 1685 rc = opal_pci_map_pe_dma_window_real(pe->phb->opal_id, 1686 pe->pe_number, 1687 window_id, 1688 pe->tce_bypass_base, 1689 top); 1690 } else { 1691 rc = opal_pci_map_pe_dma_window_real(pe->phb->opal_id, 1692 pe->pe_number, 1693 window_id, 1694 pe->tce_bypass_base, 1695 0); 1696 } 1697 if (rc) 1698 pe_err(pe, "OPAL error %lld configuring bypass window\n", rc); 1699 else 1700 pe->tce_bypass_enabled = enable; 1701 } 1702 1703 static long pnv_pci_ioda2_create_table(struct iommu_table_group *table_group, 1704 int num, __u32 page_shift, __u64 window_size, __u32 levels, 1705 bool alloc_userspace_copy, struct iommu_table **ptbl) 1706 { 1707 struct pnv_ioda_pe *pe = container_of(table_group, struct pnv_ioda_pe, 1708 table_group); 1709 int nid = pe->phb->hose->node; 1710 __u64 bus_offset = num ? pe->tce_bypass_base : table_group->tce32_start; 1711 long ret; 1712 struct iommu_table *tbl; 1713 1714 tbl = pnv_pci_table_alloc(nid); 1715 if (!tbl) 1716 return -ENOMEM; 1717 1718 tbl->it_ops = &pnv_ioda2_iommu_ops; 1719 1720 ret = pnv_pci_ioda2_table_alloc_pages(nid, 1721 bus_offset, page_shift, window_size, 1722 levels, alloc_userspace_copy, tbl); 1723 if (ret) { 1724 iommu_tce_table_put(tbl); 1725 return ret; 1726 } 1727 1728 *ptbl = tbl; 1729 1730 return 0; 1731 } 1732 1733 static long pnv_pci_ioda2_setup_default_config(struct pnv_ioda_pe *pe) 1734 { 1735 struct iommu_table *tbl = NULL; 1736 long rc; 1737 unsigned long res_start, res_end; 1738 1739 /* 1740 * crashkernel= specifies the kdump kernel's maximum memory at 1741 * some offset and there is no guaranteed the result is a power 1742 * of 2, which will cause errors later. 1743 */ 1744 const u64 max_memory = __rounddown_pow_of_two(memory_hotplug_max()); 1745 1746 /* 1747 * In memory constrained environments, e.g. kdump kernel, the 1748 * DMA window can be larger than available memory, which will 1749 * cause errors later. 1750 */ 1751 const u64 maxblock = 1UL << (PAGE_SHIFT + MAX_ORDER - 1); 1752 1753 /* 1754 * We create the default window as big as we can. The constraint is 1755 * the max order of allocation possible. The TCE table is likely to 1756 * end up being multilevel and with on-demand allocation in place, 1757 * the initial use is not going to be huge as the default window aims 1758 * to support crippled devices (i.e. not fully 64bit DMAble) only. 1759 */ 1760 /* iommu_table::it_map uses 1 bit per IOMMU page, hence 8 */ 1761 const u64 window_size = min((maxblock * 8) << PAGE_SHIFT, max_memory); 1762 /* Each TCE level cannot exceed maxblock so go multilevel if needed */ 1763 unsigned long tces_order = ilog2(window_size >> PAGE_SHIFT); 1764 unsigned long tcelevel_order = ilog2(maxblock >> 3); 1765 unsigned int levels = tces_order / tcelevel_order; 1766 1767 if (tces_order % tcelevel_order) 1768 levels += 1; 1769 /* 1770 * We try to stick to default levels (which is >1 at the moment) in 1771 * order to save memory by relying on on-demain TCE level allocation. 1772 */ 1773 levels = max_t(unsigned int, levels, POWERNV_IOMMU_DEFAULT_LEVELS); 1774 1775 rc = pnv_pci_ioda2_create_table(&pe->table_group, 0, PAGE_SHIFT, 1776 window_size, levels, false, &tbl); 1777 if (rc) { 1778 pe_err(pe, "Failed to create 32-bit TCE table, err %ld", 1779 rc); 1780 return rc; 1781 } 1782 1783 /* We use top part of 32bit space for MMIO so exclude it from DMA */ 1784 res_start = 0; 1785 res_end = 0; 1786 if (window_size > pe->phb->ioda.m32_pci_base) { 1787 res_start = pe->phb->ioda.m32_pci_base >> tbl->it_page_shift; 1788 res_end = min(window_size, SZ_4G) >> tbl->it_page_shift; 1789 } 1790 1791 if (iommu_init_table(tbl, pe->phb->hose->node, res_start, res_end)) 1792 rc = pnv_pci_ioda2_set_window(&pe->table_group, 0, tbl); 1793 else 1794 rc = -ENOMEM; 1795 if (rc) { 1796 pe_err(pe, "Failed to configure 32-bit TCE table, err %ld\n", rc); 1797 iommu_tce_table_put(tbl); 1798 tbl = NULL; /* This clears iommu_table_base below */ 1799 } 1800 if (!pnv_iommu_bypass_disabled) 1801 pnv_pci_ioda2_set_bypass(pe, true); 1802 1803 /* 1804 * Set table base for the case of IOMMU DMA use. Usually this is done 1805 * from dma_dev_setup() which is not called when a device is returned 1806 * from VFIO so do it here. 1807 */ 1808 if (pe->pdev) 1809 set_iommu_table_base(&pe->pdev->dev, tbl); 1810 1811 return 0; 1812 } 1813 1814 static long pnv_pci_ioda2_unset_window(struct iommu_table_group *table_group, 1815 int num) 1816 { 1817 struct pnv_ioda_pe *pe = container_of(table_group, struct pnv_ioda_pe, 1818 table_group); 1819 struct pnv_phb *phb = pe->phb; 1820 long ret; 1821 1822 pe_info(pe, "Removing DMA window #%d\n", num); 1823 1824 ret = opal_pci_map_pe_dma_window(phb->opal_id, pe->pe_number, 1825 (pe->pe_number << 1) + num, 1826 0/* levels */, 0/* table address */, 1827 0/* table size */, 0/* page size */); 1828 if (ret) 1829 pe_warn(pe, "Unmapping failed, ret = %ld\n", ret); 1830 else 1831 pnv_pci_ioda2_tce_invalidate_pe(pe); 1832 1833 pnv_pci_unlink_table_and_group(table_group->tables[num], table_group); 1834 1835 return ret; 1836 } 1837 1838 #ifdef CONFIG_IOMMU_API 1839 unsigned long pnv_pci_ioda2_get_table_size(__u32 page_shift, 1840 __u64 window_size, __u32 levels) 1841 { 1842 unsigned long bytes = 0; 1843 const unsigned window_shift = ilog2(window_size); 1844 unsigned entries_shift = window_shift - page_shift; 1845 unsigned table_shift = entries_shift + 3; 1846 unsigned long tce_table_size = max(0x1000UL, 1UL << table_shift); 1847 unsigned long direct_table_size; 1848 1849 if (!levels || (levels > POWERNV_IOMMU_MAX_LEVELS) || 1850 !is_power_of_2(window_size)) 1851 return 0; 1852 1853 /* Calculate a direct table size from window_size and levels */ 1854 entries_shift = (entries_shift + levels - 1) / levels; 1855 table_shift = entries_shift + 3; 1856 table_shift = max_t(unsigned, table_shift, PAGE_SHIFT); 1857 direct_table_size = 1UL << table_shift; 1858 1859 for ( ; levels; --levels) { 1860 bytes += ALIGN(tce_table_size, direct_table_size); 1861 1862 tce_table_size /= direct_table_size; 1863 tce_table_size <<= 3; 1864 tce_table_size = max_t(unsigned long, 1865 tce_table_size, direct_table_size); 1866 } 1867 1868 return bytes + bytes; /* one for HW table, one for userspace copy */ 1869 } 1870 1871 static long pnv_pci_ioda2_create_table_userspace( 1872 struct iommu_table_group *table_group, 1873 int num, __u32 page_shift, __u64 window_size, __u32 levels, 1874 struct iommu_table **ptbl) 1875 { 1876 long ret = pnv_pci_ioda2_create_table(table_group, 1877 num, page_shift, window_size, levels, true, ptbl); 1878 1879 if (!ret) 1880 (*ptbl)->it_allocated_size = pnv_pci_ioda2_get_table_size( 1881 page_shift, window_size, levels); 1882 return ret; 1883 } 1884 1885 static void pnv_ioda_setup_bus_dma(struct pnv_ioda_pe *pe, struct pci_bus *bus) 1886 { 1887 struct pci_dev *dev; 1888 1889 list_for_each_entry(dev, &bus->devices, bus_list) { 1890 set_iommu_table_base(&dev->dev, pe->table_group.tables[0]); 1891 dev->dev.archdata.dma_offset = pe->tce_bypass_base; 1892 1893 if ((pe->flags & PNV_IODA_PE_BUS_ALL) && dev->subordinate) 1894 pnv_ioda_setup_bus_dma(pe, dev->subordinate); 1895 } 1896 } 1897 1898 static void pnv_ioda2_take_ownership(struct iommu_table_group *table_group) 1899 { 1900 struct pnv_ioda_pe *pe = container_of(table_group, struct pnv_ioda_pe, 1901 table_group); 1902 /* Store @tbl as pnv_pci_ioda2_unset_window() resets it */ 1903 struct iommu_table *tbl = pe->table_group.tables[0]; 1904 1905 pnv_pci_ioda2_set_bypass(pe, false); 1906 pnv_pci_ioda2_unset_window(&pe->table_group, 0); 1907 if (pe->pbus) 1908 pnv_ioda_setup_bus_dma(pe, pe->pbus); 1909 else if (pe->pdev) 1910 set_iommu_table_base(&pe->pdev->dev, NULL); 1911 iommu_tce_table_put(tbl); 1912 } 1913 1914 static void pnv_ioda2_release_ownership(struct iommu_table_group *table_group) 1915 { 1916 struct pnv_ioda_pe *pe = container_of(table_group, struct pnv_ioda_pe, 1917 table_group); 1918 1919 pnv_pci_ioda2_setup_default_config(pe); 1920 if (pe->pbus) 1921 pnv_ioda_setup_bus_dma(pe, pe->pbus); 1922 } 1923 1924 static struct iommu_table_group_ops pnv_pci_ioda2_ops = { 1925 .get_table_size = pnv_pci_ioda2_get_table_size, 1926 .create_table = pnv_pci_ioda2_create_table_userspace, 1927 .set_window = pnv_pci_ioda2_set_window, 1928 .unset_window = pnv_pci_ioda2_unset_window, 1929 .take_ownership = pnv_ioda2_take_ownership, 1930 .release_ownership = pnv_ioda2_release_ownership, 1931 }; 1932 #endif 1933 1934 void pnv_pci_ioda2_setup_dma_pe(struct pnv_phb *phb, 1935 struct pnv_ioda_pe *pe) 1936 { 1937 int64_t rc; 1938 1939 /* TVE #1 is selected by PCI address bit 59 */ 1940 pe->tce_bypass_base = 1ull << 59; 1941 1942 /* The PE will reserve all possible 32-bits space */ 1943 pe_info(pe, "Setting up 32-bit TCE table at 0..%08x\n", 1944 phb->ioda.m32_pci_base); 1945 1946 /* Setup linux iommu table */ 1947 pe->table_group.tce32_start = 0; 1948 pe->table_group.tce32_size = phb->ioda.m32_pci_base; 1949 pe->table_group.max_dynamic_windows_supported = 1950 IOMMU_TABLE_GROUP_MAX_TABLES; 1951 pe->table_group.max_levels = POWERNV_IOMMU_MAX_LEVELS; 1952 pe->table_group.pgsizes = pnv_ioda_parse_tce_sizes(phb); 1953 1954 rc = pnv_pci_ioda2_setup_default_config(pe); 1955 if (rc) 1956 return; 1957 1958 #ifdef CONFIG_IOMMU_API 1959 pe->table_group.ops = &pnv_pci_ioda2_ops; 1960 iommu_register_group(&pe->table_group, phb->hose->global_number, 1961 pe->pe_number); 1962 #endif 1963 pe->dma_setup_done = true; 1964 } 1965 1966 /* 1967 * Called from KVM in real mode to EOI passthru interrupts. The ICP 1968 * EOI is handled directly in KVM in kvmppc_deliver_irq_passthru(). 1969 * 1970 * The IRQ data is mapped in the PCI-MSI domain and the EOI OPAL call 1971 * needs an HW IRQ number mapped in the XICS IRQ domain. The HW IRQ 1972 * numbers of the in-the-middle MSI domain are vector numbers and it's 1973 * good enough for OPAL. Use that. 1974 */ 1975 int64_t pnv_opal_pci_msi_eoi(struct irq_data *d) 1976 { 1977 struct pci_controller *hose = irq_data_get_irq_chip_data(d->parent_data); 1978 struct pnv_phb *phb = hose->private_data; 1979 1980 return opal_pci_msi_eoi(phb->opal_id, d->parent_data->hwirq); 1981 } 1982 1983 /* 1984 * The IRQ data is mapped in the XICS domain, with OPAL HW IRQ numbers 1985 */ 1986 static void pnv_ioda2_msi_eoi(struct irq_data *d) 1987 { 1988 int64_t rc; 1989 unsigned int hw_irq = (unsigned int)irqd_to_hwirq(d); 1990 struct pci_controller *hose = irq_data_get_irq_chip_data(d); 1991 struct pnv_phb *phb = hose->private_data; 1992 1993 rc = opal_pci_msi_eoi(phb->opal_id, hw_irq); 1994 WARN_ON_ONCE(rc); 1995 1996 icp_native_eoi(d); 1997 } 1998 1999 /* P8/CXL only */ 2000 void pnv_set_msi_irq_chip(struct pnv_phb *phb, unsigned int virq) 2001 { 2002 struct irq_data *idata; 2003 struct irq_chip *ichip; 2004 2005 /* The MSI EOI OPAL call is only needed on PHB3 */ 2006 if (phb->model != PNV_PHB_MODEL_PHB3) 2007 return; 2008 2009 if (!phb->ioda.irq_chip_init) { 2010 /* 2011 * First time we setup an MSI IRQ, we need to setup the 2012 * corresponding IRQ chip to route correctly. 2013 */ 2014 idata = irq_get_irq_data(virq); 2015 ichip = irq_data_get_irq_chip(idata); 2016 phb->ioda.irq_chip_init = 1; 2017 phb->ioda.irq_chip = *ichip; 2018 phb->ioda.irq_chip.irq_eoi = pnv_ioda2_msi_eoi; 2019 } 2020 irq_set_chip(virq, &phb->ioda.irq_chip); 2021 irq_set_chip_data(virq, phb->hose); 2022 } 2023 2024 static struct irq_chip pnv_pci_msi_irq_chip; 2025 2026 /* 2027 * Returns true iff chip is something that we could call 2028 * pnv_opal_pci_msi_eoi for. 2029 */ 2030 bool is_pnv_opal_msi(struct irq_chip *chip) 2031 { 2032 return chip == &pnv_pci_msi_irq_chip; 2033 } 2034 EXPORT_SYMBOL_GPL(is_pnv_opal_msi); 2035 2036 static int __pnv_pci_ioda_msi_setup(struct pnv_phb *phb, struct pci_dev *dev, 2037 unsigned int xive_num, 2038 unsigned int is_64, struct msi_msg *msg) 2039 { 2040 struct pnv_ioda_pe *pe = pnv_ioda_get_pe(dev); 2041 __be32 data; 2042 int rc; 2043 2044 dev_dbg(&dev->dev, "%s: setup %s-bit MSI for vector #%d\n", __func__, 2045 is_64 ? "64" : "32", xive_num); 2046 2047 /* No PE assigned ? bail out ... no MSI for you ! */ 2048 if (pe == NULL) 2049 return -ENXIO; 2050 2051 /* Check if we have an MVE */ 2052 if (pe->mve_number < 0) 2053 return -ENXIO; 2054 2055 /* Force 32-bit MSI on some broken devices */ 2056 if (dev->no_64bit_msi) 2057 is_64 = 0; 2058 2059 /* Assign XIVE to PE */ 2060 rc = opal_pci_set_xive_pe(phb->opal_id, pe->pe_number, xive_num); 2061 if (rc) { 2062 pr_warn("%s: OPAL error %d setting XIVE %d PE\n", 2063 pci_name(dev), rc, xive_num); 2064 return -EIO; 2065 } 2066 2067 if (is_64) { 2068 __be64 addr64; 2069 2070 rc = opal_get_msi_64(phb->opal_id, pe->mve_number, xive_num, 1, 2071 &addr64, &data); 2072 if (rc) { 2073 pr_warn("%s: OPAL error %d getting 64-bit MSI data\n", 2074 pci_name(dev), rc); 2075 return -EIO; 2076 } 2077 msg->address_hi = be64_to_cpu(addr64) >> 32; 2078 msg->address_lo = be64_to_cpu(addr64) & 0xfffffffful; 2079 } else { 2080 __be32 addr32; 2081 2082 rc = opal_get_msi_32(phb->opal_id, pe->mve_number, xive_num, 1, 2083 &addr32, &data); 2084 if (rc) { 2085 pr_warn("%s: OPAL error %d getting 32-bit MSI data\n", 2086 pci_name(dev), rc); 2087 return -EIO; 2088 } 2089 msg->address_hi = 0; 2090 msg->address_lo = be32_to_cpu(addr32); 2091 } 2092 msg->data = be32_to_cpu(data); 2093 2094 return 0; 2095 } 2096 2097 /* 2098 * The msi_free() op is called before irq_domain_free_irqs_top() when 2099 * the handler data is still available. Use that to clear the XIVE 2100 * controller. 2101 */ 2102 static void pnv_msi_ops_msi_free(struct irq_domain *domain, 2103 struct msi_domain_info *info, 2104 unsigned int irq) 2105 { 2106 if (xive_enabled()) 2107 xive_irq_free_data(irq); 2108 } 2109 2110 static struct msi_domain_ops pnv_pci_msi_domain_ops = { 2111 .msi_free = pnv_msi_ops_msi_free, 2112 }; 2113 2114 static void pnv_msi_shutdown(struct irq_data *d) 2115 { 2116 d = d->parent_data; 2117 if (d->chip->irq_shutdown) 2118 d->chip->irq_shutdown(d); 2119 } 2120 2121 static void pnv_msi_mask(struct irq_data *d) 2122 { 2123 pci_msi_mask_irq(d); 2124 irq_chip_mask_parent(d); 2125 } 2126 2127 static void pnv_msi_unmask(struct irq_data *d) 2128 { 2129 pci_msi_unmask_irq(d); 2130 irq_chip_unmask_parent(d); 2131 } 2132 2133 static struct irq_chip pnv_pci_msi_irq_chip = { 2134 .name = "PNV-PCI-MSI", 2135 .irq_shutdown = pnv_msi_shutdown, 2136 .irq_mask = pnv_msi_mask, 2137 .irq_unmask = pnv_msi_unmask, 2138 .irq_eoi = irq_chip_eoi_parent, 2139 }; 2140 2141 static struct msi_domain_info pnv_msi_domain_info = { 2142 .flags = (MSI_FLAG_USE_DEF_DOM_OPS | MSI_FLAG_USE_DEF_CHIP_OPS | 2143 MSI_FLAG_MULTI_PCI_MSI | MSI_FLAG_PCI_MSIX), 2144 .ops = &pnv_pci_msi_domain_ops, 2145 .chip = &pnv_pci_msi_irq_chip, 2146 }; 2147 2148 static void pnv_msi_compose_msg(struct irq_data *d, struct msi_msg *msg) 2149 { 2150 struct msi_desc *entry = irq_data_get_msi_desc(d); 2151 struct pci_dev *pdev = msi_desc_to_pci_dev(entry); 2152 struct pci_controller *hose = irq_data_get_irq_chip_data(d); 2153 struct pnv_phb *phb = hose->private_data; 2154 int rc; 2155 2156 rc = __pnv_pci_ioda_msi_setup(phb, pdev, d->hwirq, 2157 entry->pci.msi_attrib.is_64, msg); 2158 if (rc) 2159 dev_err(&pdev->dev, "Failed to setup %s-bit MSI #%ld : %d\n", 2160 entry->pci.msi_attrib.is_64 ? "64" : "32", d->hwirq, rc); 2161 } 2162 2163 /* 2164 * The IRQ data is mapped in the MSI domain in which HW IRQ numbers 2165 * correspond to vector numbers. 2166 */ 2167 static void pnv_msi_eoi(struct irq_data *d) 2168 { 2169 struct pci_controller *hose = irq_data_get_irq_chip_data(d); 2170 struct pnv_phb *phb = hose->private_data; 2171 2172 if (phb->model == PNV_PHB_MODEL_PHB3) { 2173 /* 2174 * The EOI OPAL call takes an OPAL HW IRQ number but 2175 * since it is translated into a vector number in 2176 * OPAL, use that directly. 2177 */ 2178 WARN_ON_ONCE(opal_pci_msi_eoi(phb->opal_id, d->hwirq)); 2179 } 2180 2181 irq_chip_eoi_parent(d); 2182 } 2183 2184 static struct irq_chip pnv_msi_irq_chip = { 2185 .name = "PNV-MSI", 2186 .irq_shutdown = pnv_msi_shutdown, 2187 .irq_mask = irq_chip_mask_parent, 2188 .irq_unmask = irq_chip_unmask_parent, 2189 .irq_eoi = pnv_msi_eoi, 2190 .irq_set_affinity = irq_chip_set_affinity_parent, 2191 .irq_compose_msi_msg = pnv_msi_compose_msg, 2192 }; 2193 2194 static int pnv_irq_parent_domain_alloc(struct irq_domain *domain, 2195 unsigned int virq, int hwirq) 2196 { 2197 struct irq_fwspec parent_fwspec; 2198 int ret; 2199 2200 parent_fwspec.fwnode = domain->parent->fwnode; 2201 parent_fwspec.param_count = 2; 2202 parent_fwspec.param[0] = hwirq; 2203 parent_fwspec.param[1] = IRQ_TYPE_EDGE_RISING; 2204 2205 ret = irq_domain_alloc_irqs_parent(domain, virq, 1, &parent_fwspec); 2206 if (ret) 2207 return ret; 2208 2209 return 0; 2210 } 2211 2212 static int pnv_irq_domain_alloc(struct irq_domain *domain, unsigned int virq, 2213 unsigned int nr_irqs, void *arg) 2214 { 2215 struct pci_controller *hose = domain->host_data; 2216 struct pnv_phb *phb = hose->private_data; 2217 msi_alloc_info_t *info = arg; 2218 struct pci_dev *pdev = msi_desc_to_pci_dev(info->desc); 2219 int hwirq; 2220 int i, ret; 2221 2222 hwirq = msi_bitmap_alloc_hwirqs(&phb->msi_bmp, nr_irqs); 2223 if (hwirq < 0) { 2224 dev_warn(&pdev->dev, "failed to find a free MSI\n"); 2225 return -ENOSPC; 2226 } 2227 2228 dev_dbg(&pdev->dev, "%s bridge %pOF %d/%x #%d\n", __func__, 2229 hose->dn, virq, hwirq, nr_irqs); 2230 2231 for (i = 0; i < nr_irqs; i++) { 2232 ret = pnv_irq_parent_domain_alloc(domain, virq + i, 2233 phb->msi_base + hwirq + i); 2234 if (ret) 2235 goto out; 2236 2237 irq_domain_set_hwirq_and_chip(domain, virq + i, hwirq + i, 2238 &pnv_msi_irq_chip, hose); 2239 } 2240 2241 return 0; 2242 2243 out: 2244 irq_domain_free_irqs_parent(domain, virq, i - 1); 2245 msi_bitmap_free_hwirqs(&phb->msi_bmp, hwirq, nr_irqs); 2246 return ret; 2247 } 2248 2249 static void pnv_irq_domain_free(struct irq_domain *domain, unsigned int virq, 2250 unsigned int nr_irqs) 2251 { 2252 struct irq_data *d = irq_domain_get_irq_data(domain, virq); 2253 struct pci_controller *hose = irq_data_get_irq_chip_data(d); 2254 struct pnv_phb *phb = hose->private_data; 2255 2256 pr_debug("%s bridge %pOF %d/%lx #%d\n", __func__, hose->dn, 2257 virq, d->hwirq, nr_irqs); 2258 2259 msi_bitmap_free_hwirqs(&phb->msi_bmp, d->hwirq, nr_irqs); 2260 /* XIVE domain is cleared through ->msi_free() */ 2261 } 2262 2263 static const struct irq_domain_ops pnv_irq_domain_ops = { 2264 .alloc = pnv_irq_domain_alloc, 2265 .free = pnv_irq_domain_free, 2266 }; 2267 2268 static int pnv_msi_allocate_domains(struct pci_controller *hose, unsigned int count) 2269 { 2270 struct pnv_phb *phb = hose->private_data; 2271 struct irq_domain *parent = irq_get_default_host(); 2272 2273 hose->fwnode = irq_domain_alloc_named_id_fwnode("PNV-MSI", phb->opal_id); 2274 if (!hose->fwnode) 2275 return -ENOMEM; 2276 2277 hose->dev_domain = irq_domain_create_hierarchy(parent, 0, count, 2278 hose->fwnode, 2279 &pnv_irq_domain_ops, hose); 2280 if (!hose->dev_domain) { 2281 pr_err("PCI: failed to create IRQ domain bridge %pOF (domain %d)\n", 2282 hose->dn, hose->global_number); 2283 irq_domain_free_fwnode(hose->fwnode); 2284 return -ENOMEM; 2285 } 2286 2287 hose->msi_domain = pci_msi_create_irq_domain(of_node_to_fwnode(hose->dn), 2288 &pnv_msi_domain_info, 2289 hose->dev_domain); 2290 if (!hose->msi_domain) { 2291 pr_err("PCI: failed to create MSI IRQ domain bridge %pOF (domain %d)\n", 2292 hose->dn, hose->global_number); 2293 irq_domain_free_fwnode(hose->fwnode); 2294 irq_domain_remove(hose->dev_domain); 2295 return -ENOMEM; 2296 } 2297 2298 return 0; 2299 } 2300 2301 static void pnv_pci_init_ioda_msis(struct pnv_phb *phb) 2302 { 2303 unsigned int count; 2304 const __be32 *prop = of_get_property(phb->hose->dn, 2305 "ibm,opal-msi-ranges", NULL); 2306 if (!prop) { 2307 /* BML Fallback */ 2308 prop = of_get_property(phb->hose->dn, "msi-ranges", NULL); 2309 } 2310 if (!prop) 2311 return; 2312 2313 phb->msi_base = be32_to_cpup(prop); 2314 count = be32_to_cpup(prop + 1); 2315 if (msi_bitmap_alloc(&phb->msi_bmp, count, phb->hose->dn)) { 2316 pr_err("PCI %d: Failed to allocate MSI bitmap !\n", 2317 phb->hose->global_number); 2318 return; 2319 } 2320 2321 pr_info(" Allocated bitmap for %d MSIs (base IRQ 0x%x)\n", 2322 count, phb->msi_base); 2323 2324 pnv_msi_allocate_domains(phb->hose, count); 2325 } 2326 2327 static void pnv_ioda_setup_pe_res(struct pnv_ioda_pe *pe, 2328 struct resource *res) 2329 { 2330 struct pnv_phb *phb = pe->phb; 2331 struct pci_bus_region region; 2332 int index; 2333 int64_t rc; 2334 2335 if (!res || !res->flags || res->start > res->end) 2336 return; 2337 2338 if (res->flags & IORESOURCE_IO) { 2339 region.start = res->start - phb->ioda.io_pci_base; 2340 region.end = res->end - phb->ioda.io_pci_base; 2341 index = region.start / phb->ioda.io_segsize; 2342 2343 while (index < phb->ioda.total_pe_num && 2344 region.start <= region.end) { 2345 phb->ioda.io_segmap[index] = pe->pe_number; 2346 rc = opal_pci_map_pe_mmio_window(phb->opal_id, 2347 pe->pe_number, OPAL_IO_WINDOW_TYPE, 0, index); 2348 if (rc != OPAL_SUCCESS) { 2349 pr_err("%s: Error %lld mapping IO segment#%d to PE#%x\n", 2350 __func__, rc, index, pe->pe_number); 2351 break; 2352 } 2353 2354 region.start += phb->ioda.io_segsize; 2355 index++; 2356 } 2357 } else if ((res->flags & IORESOURCE_MEM) && 2358 !pnv_pci_is_m64(phb, res)) { 2359 region.start = res->start - 2360 phb->hose->mem_offset[0] - 2361 phb->ioda.m32_pci_base; 2362 region.end = res->end - 2363 phb->hose->mem_offset[0] - 2364 phb->ioda.m32_pci_base; 2365 index = region.start / phb->ioda.m32_segsize; 2366 2367 while (index < phb->ioda.total_pe_num && 2368 region.start <= region.end) { 2369 phb->ioda.m32_segmap[index] = pe->pe_number; 2370 rc = opal_pci_map_pe_mmio_window(phb->opal_id, 2371 pe->pe_number, OPAL_M32_WINDOW_TYPE, 0, index); 2372 if (rc != OPAL_SUCCESS) { 2373 pr_err("%s: Error %lld mapping M32 segment#%d to PE#%x", 2374 __func__, rc, index, pe->pe_number); 2375 break; 2376 } 2377 2378 region.start += phb->ioda.m32_segsize; 2379 index++; 2380 } 2381 } 2382 } 2383 2384 /* 2385 * This function is supposed to be called on basis of PE from top 2386 * to bottom style. So the the I/O or MMIO segment assigned to 2387 * parent PE could be overridden by its child PEs if necessary. 2388 */ 2389 static void pnv_ioda_setup_pe_seg(struct pnv_ioda_pe *pe) 2390 { 2391 struct pci_dev *pdev; 2392 int i; 2393 2394 /* 2395 * NOTE: We only care PCI bus based PE for now. For PCI 2396 * device based PE, for example SRIOV sensitive VF should 2397 * be figured out later. 2398 */ 2399 BUG_ON(!(pe->flags & (PNV_IODA_PE_BUS | PNV_IODA_PE_BUS_ALL))); 2400 2401 list_for_each_entry(pdev, &pe->pbus->devices, bus_list) { 2402 for (i = 0; i <= PCI_ROM_RESOURCE; i++) 2403 pnv_ioda_setup_pe_res(pe, &pdev->resource[i]); 2404 2405 /* 2406 * If the PE contains all subordinate PCI buses, the 2407 * windows of the child bridges should be mapped to 2408 * the PE as well. 2409 */ 2410 if (!(pe->flags & PNV_IODA_PE_BUS_ALL) || !pci_is_bridge(pdev)) 2411 continue; 2412 for (i = 0; i < PCI_BRIDGE_RESOURCE_NUM; i++) 2413 pnv_ioda_setup_pe_res(pe, 2414 &pdev->resource[PCI_BRIDGE_RESOURCES + i]); 2415 } 2416 } 2417 2418 #ifdef CONFIG_DEBUG_FS 2419 static int pnv_pci_diag_data_set(void *data, u64 val) 2420 { 2421 struct pnv_phb *phb = data; 2422 s64 ret; 2423 2424 /* Retrieve the diag data from firmware */ 2425 ret = opal_pci_get_phb_diag_data2(phb->opal_id, phb->diag_data, 2426 phb->diag_data_size); 2427 if (ret != OPAL_SUCCESS) 2428 return -EIO; 2429 2430 /* Print the diag data to the kernel log */ 2431 pnv_pci_dump_phb_diag_data(phb->hose, phb->diag_data); 2432 return 0; 2433 } 2434 2435 DEFINE_DEBUGFS_ATTRIBUTE(pnv_pci_diag_data_fops, NULL, pnv_pci_diag_data_set, 2436 "%llu\n"); 2437 2438 static int pnv_pci_ioda_pe_dump(void *data, u64 val) 2439 { 2440 struct pnv_phb *phb = data; 2441 int pe_num; 2442 2443 for (pe_num = 0; pe_num < phb->ioda.total_pe_num; pe_num++) { 2444 struct pnv_ioda_pe *pe = &phb->ioda.pe_array[pe_num]; 2445 2446 if (!test_bit(pe_num, phb->ioda.pe_alloc)) 2447 continue; 2448 2449 pe_warn(pe, "rid: %04x dev count: %2d flags: %s%s%s%s%s%s\n", 2450 pe->rid, pe->device_count, 2451 (pe->flags & PNV_IODA_PE_DEV) ? "dev " : "", 2452 (pe->flags & PNV_IODA_PE_BUS) ? "bus " : "", 2453 (pe->flags & PNV_IODA_PE_BUS_ALL) ? "all " : "", 2454 (pe->flags & PNV_IODA_PE_MASTER) ? "master " : "", 2455 (pe->flags & PNV_IODA_PE_SLAVE) ? "slave " : "", 2456 (pe->flags & PNV_IODA_PE_VF) ? "vf " : ""); 2457 } 2458 2459 return 0; 2460 } 2461 2462 DEFINE_DEBUGFS_ATTRIBUTE(pnv_pci_ioda_pe_dump_fops, NULL, 2463 pnv_pci_ioda_pe_dump, "%llu\n"); 2464 2465 #endif /* CONFIG_DEBUG_FS */ 2466 2467 static void pnv_pci_ioda_create_dbgfs(void) 2468 { 2469 #ifdef CONFIG_DEBUG_FS 2470 struct pci_controller *hose, *tmp; 2471 struct pnv_phb *phb; 2472 char name[16]; 2473 2474 list_for_each_entry_safe(hose, tmp, &hose_list, list_node) { 2475 phb = hose->private_data; 2476 2477 sprintf(name, "PCI%04x", hose->global_number); 2478 phb->dbgfs = debugfs_create_dir(name, arch_debugfs_dir); 2479 2480 debugfs_create_file_unsafe("dump_diag_regs", 0200, phb->dbgfs, 2481 phb, &pnv_pci_diag_data_fops); 2482 debugfs_create_file_unsafe("dump_ioda_pe_state", 0200, phb->dbgfs, 2483 phb, &pnv_pci_ioda_pe_dump_fops); 2484 } 2485 #endif /* CONFIG_DEBUG_FS */ 2486 } 2487 2488 static void pnv_pci_enable_bridge(struct pci_bus *bus) 2489 { 2490 struct pci_dev *dev = bus->self; 2491 struct pci_bus *child; 2492 2493 /* Empty bus ? bail */ 2494 if (list_empty(&bus->devices)) 2495 return; 2496 2497 /* 2498 * If there's a bridge associated with that bus enable it. This works 2499 * around races in the generic code if the enabling is done during 2500 * parallel probing. This can be removed once those races have been 2501 * fixed. 2502 */ 2503 if (dev) { 2504 int rc = pci_enable_device(dev); 2505 if (rc) 2506 pci_err(dev, "Error enabling bridge (%d)\n", rc); 2507 pci_set_master(dev); 2508 } 2509 2510 /* Perform the same to child busses */ 2511 list_for_each_entry(child, &bus->children, node) 2512 pnv_pci_enable_bridge(child); 2513 } 2514 2515 static void pnv_pci_enable_bridges(void) 2516 { 2517 struct pci_controller *hose; 2518 2519 list_for_each_entry(hose, &hose_list, list_node) 2520 pnv_pci_enable_bridge(hose->bus); 2521 } 2522 2523 static void pnv_pci_ioda_fixup(void) 2524 { 2525 pnv_pci_ioda_create_dbgfs(); 2526 2527 pnv_pci_enable_bridges(); 2528 2529 #ifdef CONFIG_EEH 2530 pnv_eeh_post_init(); 2531 #endif 2532 } 2533 2534 /* 2535 * Returns the alignment for I/O or memory windows for P2P 2536 * bridges. That actually depends on how PEs are segmented. 2537 * For now, we return I/O or M32 segment size for PE sensitive 2538 * P2P bridges. Otherwise, the default values (4KiB for I/O, 2539 * 1MiB for memory) will be returned. 2540 * 2541 * The current PCI bus might be put into one PE, which was 2542 * create against the parent PCI bridge. For that case, we 2543 * needn't enlarge the alignment so that we can save some 2544 * resources. 2545 */ 2546 static resource_size_t pnv_pci_window_alignment(struct pci_bus *bus, 2547 unsigned long type) 2548 { 2549 struct pnv_phb *phb = pci_bus_to_pnvhb(bus); 2550 int num_pci_bridges = 0; 2551 struct pci_dev *bridge; 2552 2553 bridge = bus->self; 2554 while (bridge) { 2555 if (pci_pcie_type(bridge) == PCI_EXP_TYPE_PCI_BRIDGE) { 2556 num_pci_bridges++; 2557 if (num_pci_bridges >= 2) 2558 return 1; 2559 } 2560 2561 bridge = bridge->bus->self; 2562 } 2563 2564 /* 2565 * We fall back to M32 if M64 isn't supported. We enforce the M64 2566 * alignment for any 64-bit resource, PCIe doesn't care and 2567 * bridges only do 64-bit prefetchable anyway. 2568 */ 2569 if (phb->ioda.m64_segsize && pnv_pci_is_m64_flags(type)) 2570 return phb->ioda.m64_segsize; 2571 if (type & IORESOURCE_MEM) 2572 return phb->ioda.m32_segsize; 2573 2574 return phb->ioda.io_segsize; 2575 } 2576 2577 /* 2578 * We are updating root port or the upstream port of the 2579 * bridge behind the root port with PHB's windows in order 2580 * to accommodate the changes on required resources during 2581 * PCI (slot) hotplug, which is connected to either root 2582 * port or the downstream ports of PCIe switch behind the 2583 * root port. 2584 */ 2585 static void pnv_pci_fixup_bridge_resources(struct pci_bus *bus, 2586 unsigned long type) 2587 { 2588 struct pci_controller *hose = pci_bus_to_host(bus); 2589 struct pnv_phb *phb = hose->private_data; 2590 struct pci_dev *bridge = bus->self; 2591 struct resource *r, *w; 2592 bool msi_region = false; 2593 int i; 2594 2595 /* Check if we need apply fixup to the bridge's windows */ 2596 if (!pci_is_root_bus(bridge->bus) && 2597 !pci_is_root_bus(bridge->bus->self->bus)) 2598 return; 2599 2600 /* Fixup the resources */ 2601 for (i = 0; i < PCI_BRIDGE_RESOURCE_NUM; i++) { 2602 r = &bridge->resource[PCI_BRIDGE_RESOURCES + i]; 2603 if (!r->flags || !r->parent) 2604 continue; 2605 2606 w = NULL; 2607 if (r->flags & type & IORESOURCE_IO) 2608 w = &hose->io_resource; 2609 else if (pnv_pci_is_m64(phb, r) && 2610 (type & IORESOURCE_PREFETCH) && 2611 phb->ioda.m64_segsize) 2612 w = &hose->mem_resources[1]; 2613 else if (r->flags & type & IORESOURCE_MEM) { 2614 w = &hose->mem_resources[0]; 2615 msi_region = true; 2616 } 2617 2618 r->start = w->start; 2619 r->end = w->end; 2620 2621 /* The 64KB 32-bits MSI region shouldn't be included in 2622 * the 32-bits bridge window. Otherwise, we can see strange 2623 * issues. One of them is EEH error observed on Garrison. 2624 * 2625 * Exclude top 1MB region which is the minimal alignment of 2626 * 32-bits bridge window. 2627 */ 2628 if (msi_region) { 2629 r->end += 0x10000; 2630 r->end -= 0x100000; 2631 } 2632 } 2633 } 2634 2635 static void pnv_pci_configure_bus(struct pci_bus *bus) 2636 { 2637 struct pci_dev *bridge = bus->self; 2638 struct pnv_ioda_pe *pe; 2639 bool all = (bridge && pci_pcie_type(bridge) == PCI_EXP_TYPE_PCI_BRIDGE); 2640 2641 dev_info(&bus->dev, "Configuring PE for bus\n"); 2642 2643 /* Don't assign PE to PCI bus, which doesn't have subordinate devices */ 2644 if (WARN_ON(list_empty(&bus->devices))) 2645 return; 2646 2647 /* Reserve PEs according to used M64 resources */ 2648 pnv_ioda_reserve_m64_pe(bus, NULL, all); 2649 2650 /* 2651 * Assign PE. We might run here because of partial hotplug. 2652 * For the case, we just pick up the existing PE and should 2653 * not allocate resources again. 2654 */ 2655 pe = pnv_ioda_setup_bus_PE(bus, all); 2656 if (!pe) 2657 return; 2658 2659 pnv_ioda_setup_pe_seg(pe); 2660 } 2661 2662 static resource_size_t pnv_pci_default_alignment(void) 2663 { 2664 return PAGE_SIZE; 2665 } 2666 2667 /* Prevent enabling devices for which we couldn't properly 2668 * assign a PE 2669 */ 2670 static bool pnv_pci_enable_device_hook(struct pci_dev *dev) 2671 { 2672 struct pci_dn *pdn; 2673 2674 pdn = pci_get_pdn(dev); 2675 if (!pdn || pdn->pe_number == IODA_INVALID_PE) { 2676 pci_err(dev, "pci_enable_device() blocked, no PE assigned.\n"); 2677 return false; 2678 } 2679 2680 return true; 2681 } 2682 2683 static bool pnv_ocapi_enable_device_hook(struct pci_dev *dev) 2684 { 2685 struct pci_dn *pdn; 2686 struct pnv_ioda_pe *pe; 2687 2688 pdn = pci_get_pdn(dev); 2689 if (!pdn) 2690 return false; 2691 2692 if (pdn->pe_number == IODA_INVALID_PE) { 2693 pe = pnv_ioda_setup_dev_PE(dev); 2694 if (!pe) 2695 return false; 2696 } 2697 return true; 2698 } 2699 2700 static long pnv_pci_ioda1_unset_window(struct iommu_table_group *table_group, 2701 int num) 2702 { 2703 struct pnv_ioda_pe *pe = container_of(table_group, 2704 struct pnv_ioda_pe, table_group); 2705 struct pnv_phb *phb = pe->phb; 2706 unsigned int idx; 2707 long rc; 2708 2709 pe_info(pe, "Removing DMA window #%d\n", num); 2710 for (idx = 0; idx < phb->ioda.dma32_count; idx++) { 2711 if (phb->ioda.dma32_segmap[idx] != pe->pe_number) 2712 continue; 2713 2714 rc = opal_pci_map_pe_dma_window(phb->opal_id, pe->pe_number, 2715 idx, 0, 0ul, 0ul, 0ul); 2716 if (rc != OPAL_SUCCESS) { 2717 pe_warn(pe, "Failure %ld unmapping DMA32 segment#%d\n", 2718 rc, idx); 2719 return rc; 2720 } 2721 2722 phb->ioda.dma32_segmap[idx] = IODA_INVALID_PE; 2723 } 2724 2725 pnv_pci_unlink_table_and_group(table_group->tables[num], table_group); 2726 return OPAL_SUCCESS; 2727 } 2728 2729 static void pnv_pci_ioda1_release_pe_dma(struct pnv_ioda_pe *pe) 2730 { 2731 struct iommu_table *tbl = pe->table_group.tables[0]; 2732 int64_t rc; 2733 2734 if (!pe->dma_setup_done) 2735 return; 2736 2737 rc = pnv_pci_ioda1_unset_window(&pe->table_group, 0); 2738 if (rc != OPAL_SUCCESS) 2739 return; 2740 2741 pnv_pci_p7ioc_tce_invalidate(tbl, tbl->it_offset, tbl->it_size, false); 2742 if (pe->table_group.group) { 2743 iommu_group_put(pe->table_group.group); 2744 WARN_ON(pe->table_group.group); 2745 } 2746 2747 free_pages(tbl->it_base, get_order(tbl->it_size << 3)); 2748 iommu_tce_table_put(tbl); 2749 } 2750 2751 void pnv_pci_ioda2_release_pe_dma(struct pnv_ioda_pe *pe) 2752 { 2753 struct iommu_table *tbl = pe->table_group.tables[0]; 2754 int64_t rc; 2755 2756 if (!pe->dma_setup_done) 2757 return; 2758 2759 rc = pnv_pci_ioda2_unset_window(&pe->table_group, 0); 2760 if (rc) 2761 pe_warn(pe, "OPAL error %lld release DMA window\n", rc); 2762 2763 pnv_pci_ioda2_set_bypass(pe, false); 2764 if (pe->table_group.group) { 2765 iommu_group_put(pe->table_group.group); 2766 WARN_ON(pe->table_group.group); 2767 } 2768 2769 iommu_tce_table_put(tbl); 2770 } 2771 2772 static void pnv_ioda_free_pe_seg(struct pnv_ioda_pe *pe, 2773 unsigned short win, 2774 unsigned int *map) 2775 { 2776 struct pnv_phb *phb = pe->phb; 2777 int idx; 2778 int64_t rc; 2779 2780 for (idx = 0; idx < phb->ioda.total_pe_num; idx++) { 2781 if (map[idx] != pe->pe_number) 2782 continue; 2783 2784 rc = opal_pci_map_pe_mmio_window(phb->opal_id, 2785 phb->ioda.reserved_pe_idx, win, 0, idx); 2786 2787 if (rc != OPAL_SUCCESS) 2788 pe_warn(pe, "Error %lld unmapping (%d) segment#%d\n", 2789 rc, win, idx); 2790 2791 map[idx] = IODA_INVALID_PE; 2792 } 2793 } 2794 2795 static void pnv_ioda_release_pe_seg(struct pnv_ioda_pe *pe) 2796 { 2797 struct pnv_phb *phb = pe->phb; 2798 2799 if (phb->type == PNV_PHB_IODA1) { 2800 pnv_ioda_free_pe_seg(pe, OPAL_IO_WINDOW_TYPE, 2801 phb->ioda.io_segmap); 2802 pnv_ioda_free_pe_seg(pe, OPAL_M32_WINDOW_TYPE, 2803 phb->ioda.m32_segmap); 2804 /* M64 is pre-configured by pnv_ioda1_init_m64() */ 2805 } else if (phb->type == PNV_PHB_IODA2) { 2806 pnv_ioda_free_pe_seg(pe, OPAL_M32_WINDOW_TYPE, 2807 phb->ioda.m32_segmap); 2808 } 2809 } 2810 2811 static void pnv_ioda_release_pe(struct pnv_ioda_pe *pe) 2812 { 2813 struct pnv_phb *phb = pe->phb; 2814 struct pnv_ioda_pe *slave, *tmp; 2815 2816 pe_info(pe, "Releasing PE\n"); 2817 2818 mutex_lock(&phb->ioda.pe_list_mutex); 2819 list_del(&pe->list); 2820 mutex_unlock(&phb->ioda.pe_list_mutex); 2821 2822 switch (phb->type) { 2823 case PNV_PHB_IODA1: 2824 pnv_pci_ioda1_release_pe_dma(pe); 2825 break; 2826 case PNV_PHB_IODA2: 2827 pnv_pci_ioda2_release_pe_dma(pe); 2828 break; 2829 case PNV_PHB_NPU_OCAPI: 2830 break; 2831 default: 2832 WARN_ON(1); 2833 } 2834 2835 pnv_ioda_release_pe_seg(pe); 2836 pnv_ioda_deconfigure_pe(pe->phb, pe); 2837 2838 /* Release slave PEs in the compound PE */ 2839 if (pe->flags & PNV_IODA_PE_MASTER) { 2840 list_for_each_entry_safe(slave, tmp, &pe->slaves, list) { 2841 list_del(&slave->list); 2842 pnv_ioda_free_pe(slave); 2843 } 2844 } 2845 2846 /* 2847 * The PE for root bus can be removed because of hotplug in EEH 2848 * recovery for fenced PHB error. We need to mark the PE dead so 2849 * that it can be populated again in PCI hot add path. The PE 2850 * shouldn't be destroyed as it's the global reserved resource. 2851 */ 2852 if (phb->ioda.root_pe_idx == pe->pe_number) 2853 return; 2854 2855 pnv_ioda_free_pe(pe); 2856 } 2857 2858 static void pnv_pci_release_device(struct pci_dev *pdev) 2859 { 2860 struct pnv_phb *phb = pci_bus_to_pnvhb(pdev->bus); 2861 struct pci_dn *pdn = pci_get_pdn(pdev); 2862 struct pnv_ioda_pe *pe; 2863 2864 /* The VF PE state is torn down when sriov_disable() is called */ 2865 if (pdev->is_virtfn) 2866 return; 2867 2868 if (!pdn || pdn->pe_number == IODA_INVALID_PE) 2869 return; 2870 2871 #ifdef CONFIG_PCI_IOV 2872 /* 2873 * FIXME: Try move this to sriov_disable(). It's here since we allocate 2874 * the iov state at probe time since we need to fiddle with the IOV 2875 * resources. 2876 */ 2877 if (pdev->is_physfn) 2878 kfree(pdev->dev.archdata.iov_data); 2879 #endif 2880 2881 /* 2882 * PCI hotplug can happen as part of EEH error recovery. The @pdn 2883 * isn't removed and added afterwards in this scenario. We should 2884 * set the PE number in @pdn to an invalid one. Otherwise, the PE's 2885 * device count is decreased on removing devices while failing to 2886 * be increased on adding devices. It leads to unbalanced PE's device 2887 * count and eventually make normal PCI hotplug path broken. 2888 */ 2889 pe = &phb->ioda.pe_array[pdn->pe_number]; 2890 pdn->pe_number = IODA_INVALID_PE; 2891 2892 WARN_ON(--pe->device_count < 0); 2893 if (pe->device_count == 0) 2894 pnv_ioda_release_pe(pe); 2895 } 2896 2897 static void pnv_pci_ioda_shutdown(struct pci_controller *hose) 2898 { 2899 struct pnv_phb *phb = hose->private_data; 2900 2901 opal_pci_reset(phb->opal_id, OPAL_RESET_PCI_IODA_TABLE, 2902 OPAL_ASSERT_RESET); 2903 } 2904 2905 static void pnv_pci_ioda_dma_bus_setup(struct pci_bus *bus) 2906 { 2907 struct pnv_phb *phb = pci_bus_to_pnvhb(bus); 2908 struct pnv_ioda_pe *pe; 2909 2910 list_for_each_entry(pe, &phb->ioda.pe_list, list) { 2911 if (!(pe->flags & (PNV_IODA_PE_BUS | PNV_IODA_PE_BUS_ALL))) 2912 continue; 2913 2914 if (!pe->pbus) 2915 continue; 2916 2917 if (bus->number == ((pe->rid >> 8) & 0xFF)) { 2918 pe->pbus = bus; 2919 break; 2920 } 2921 } 2922 } 2923 2924 static const struct pci_controller_ops pnv_pci_ioda_controller_ops = { 2925 .dma_dev_setup = pnv_pci_ioda_dma_dev_setup, 2926 .dma_bus_setup = pnv_pci_ioda_dma_bus_setup, 2927 .iommu_bypass_supported = pnv_pci_ioda_iommu_bypass_supported, 2928 .enable_device_hook = pnv_pci_enable_device_hook, 2929 .release_device = pnv_pci_release_device, 2930 .window_alignment = pnv_pci_window_alignment, 2931 .setup_bridge = pnv_pci_fixup_bridge_resources, 2932 .reset_secondary_bus = pnv_pci_reset_secondary_bus, 2933 .shutdown = pnv_pci_ioda_shutdown, 2934 }; 2935 2936 static const struct pci_controller_ops pnv_npu_ocapi_ioda_controller_ops = { 2937 .enable_device_hook = pnv_ocapi_enable_device_hook, 2938 .release_device = pnv_pci_release_device, 2939 .window_alignment = pnv_pci_window_alignment, 2940 .reset_secondary_bus = pnv_pci_reset_secondary_bus, 2941 .shutdown = pnv_pci_ioda_shutdown, 2942 }; 2943 2944 static void __init pnv_pci_init_ioda_phb(struct device_node *np, 2945 u64 hub_id, int ioda_type) 2946 { 2947 struct pci_controller *hose; 2948 struct pnv_phb *phb; 2949 unsigned long size, m64map_off, m32map_off, pemap_off; 2950 unsigned long iomap_off = 0, dma32map_off = 0; 2951 struct pnv_ioda_pe *root_pe; 2952 struct resource r; 2953 const __be64 *prop64; 2954 const __be32 *prop32; 2955 int len; 2956 unsigned int segno; 2957 u64 phb_id; 2958 void *aux; 2959 long rc; 2960 2961 if (!of_device_is_available(np)) 2962 return; 2963 2964 pr_info("Initializing %s PHB (%pOF)\n", pnv_phb_names[ioda_type], np); 2965 2966 prop64 = of_get_property(np, "ibm,opal-phbid", NULL); 2967 if (!prop64) { 2968 pr_err(" Missing \"ibm,opal-phbid\" property !\n"); 2969 return; 2970 } 2971 phb_id = be64_to_cpup(prop64); 2972 pr_debug(" PHB-ID : 0x%016llx\n", phb_id); 2973 2974 phb = kzalloc(sizeof(*phb), GFP_KERNEL); 2975 if (!phb) 2976 panic("%s: Failed to allocate %zu bytes\n", __func__, 2977 sizeof(*phb)); 2978 2979 /* Allocate PCI controller */ 2980 phb->hose = hose = pcibios_alloc_controller(np); 2981 if (!phb->hose) { 2982 pr_err(" Can't allocate PCI controller for %pOF\n", 2983 np); 2984 memblock_free(phb, sizeof(struct pnv_phb)); 2985 return; 2986 } 2987 2988 spin_lock_init(&phb->lock); 2989 prop32 = of_get_property(np, "bus-range", &len); 2990 if (prop32 && len == 8) { 2991 hose->first_busno = be32_to_cpu(prop32[0]); 2992 hose->last_busno = be32_to_cpu(prop32[1]); 2993 } else { 2994 pr_warn(" Broken <bus-range> on %pOF\n", np); 2995 hose->first_busno = 0; 2996 hose->last_busno = 0xff; 2997 } 2998 hose->private_data = phb; 2999 phb->hub_id = hub_id; 3000 phb->opal_id = phb_id; 3001 phb->type = ioda_type; 3002 mutex_init(&phb->ioda.pe_alloc_mutex); 3003 3004 /* Detect specific models for error handling */ 3005 if (of_device_is_compatible(np, "ibm,p7ioc-pciex")) 3006 phb->model = PNV_PHB_MODEL_P7IOC; 3007 else if (of_device_is_compatible(np, "ibm,power8-pciex")) 3008 phb->model = PNV_PHB_MODEL_PHB3; 3009 else 3010 phb->model = PNV_PHB_MODEL_UNKNOWN; 3011 3012 /* Initialize diagnostic data buffer */ 3013 prop32 = of_get_property(np, "ibm,phb-diag-data-size", NULL); 3014 if (prop32) 3015 phb->diag_data_size = be32_to_cpup(prop32); 3016 else 3017 phb->diag_data_size = PNV_PCI_DIAG_BUF_SIZE; 3018 3019 phb->diag_data = kzalloc(phb->diag_data_size, GFP_KERNEL); 3020 if (!phb->diag_data) 3021 panic("%s: Failed to allocate %u bytes\n", __func__, 3022 phb->diag_data_size); 3023 3024 /* Parse 32-bit and IO ranges (if any) */ 3025 pci_process_bridge_OF_ranges(hose, np, !hose->global_number); 3026 3027 /* Get registers */ 3028 if (!of_address_to_resource(np, 0, &r)) { 3029 phb->regs_phys = r.start; 3030 phb->regs = ioremap(r.start, resource_size(&r)); 3031 if (phb->regs == NULL) 3032 pr_err(" Failed to map registers !\n"); 3033 } 3034 3035 /* Initialize more IODA stuff */ 3036 phb->ioda.total_pe_num = 1; 3037 prop32 = of_get_property(np, "ibm,opal-num-pes", NULL); 3038 if (prop32) 3039 phb->ioda.total_pe_num = be32_to_cpup(prop32); 3040 prop32 = of_get_property(np, "ibm,opal-reserved-pe", NULL); 3041 if (prop32) 3042 phb->ioda.reserved_pe_idx = be32_to_cpup(prop32); 3043 3044 /* Invalidate RID to PE# mapping */ 3045 for (segno = 0; segno < ARRAY_SIZE(phb->ioda.pe_rmap); segno++) 3046 phb->ioda.pe_rmap[segno] = IODA_INVALID_PE; 3047 3048 /* Parse 64-bit MMIO range */ 3049 pnv_ioda_parse_m64_window(phb); 3050 3051 phb->ioda.m32_size = resource_size(&hose->mem_resources[0]); 3052 /* FW Has already off top 64k of M32 space (MSI space) */ 3053 phb->ioda.m32_size += 0x10000; 3054 3055 phb->ioda.m32_segsize = phb->ioda.m32_size / phb->ioda.total_pe_num; 3056 phb->ioda.m32_pci_base = hose->mem_resources[0].start - hose->mem_offset[0]; 3057 phb->ioda.io_size = hose->pci_io_size; 3058 phb->ioda.io_segsize = phb->ioda.io_size / phb->ioda.total_pe_num; 3059 phb->ioda.io_pci_base = 0; /* XXX calculate this ? */ 3060 3061 /* Calculate how many 32-bit TCE segments we have */ 3062 phb->ioda.dma32_count = phb->ioda.m32_pci_base / 3063 PNV_IODA1_DMA32_SEGSIZE; 3064 3065 /* Allocate aux data & arrays. We don't have IO ports on PHB3 */ 3066 size = ALIGN(max_t(unsigned, phb->ioda.total_pe_num, 8) / 8, 3067 sizeof(unsigned long)); 3068 m64map_off = size; 3069 size += phb->ioda.total_pe_num * sizeof(phb->ioda.m64_segmap[0]); 3070 m32map_off = size; 3071 size += phb->ioda.total_pe_num * sizeof(phb->ioda.m32_segmap[0]); 3072 if (phb->type == PNV_PHB_IODA1) { 3073 iomap_off = size; 3074 size += phb->ioda.total_pe_num * sizeof(phb->ioda.io_segmap[0]); 3075 dma32map_off = size; 3076 size += phb->ioda.dma32_count * 3077 sizeof(phb->ioda.dma32_segmap[0]); 3078 } 3079 pemap_off = size; 3080 size += phb->ioda.total_pe_num * sizeof(struct pnv_ioda_pe); 3081 aux = kzalloc(size, GFP_KERNEL); 3082 if (!aux) 3083 panic("%s: Failed to allocate %lu bytes\n", __func__, size); 3084 3085 phb->ioda.pe_alloc = aux; 3086 phb->ioda.m64_segmap = aux + m64map_off; 3087 phb->ioda.m32_segmap = aux + m32map_off; 3088 for (segno = 0; segno < phb->ioda.total_pe_num; segno++) { 3089 phb->ioda.m64_segmap[segno] = IODA_INVALID_PE; 3090 phb->ioda.m32_segmap[segno] = IODA_INVALID_PE; 3091 } 3092 if (phb->type == PNV_PHB_IODA1) { 3093 phb->ioda.io_segmap = aux + iomap_off; 3094 for (segno = 0; segno < phb->ioda.total_pe_num; segno++) 3095 phb->ioda.io_segmap[segno] = IODA_INVALID_PE; 3096 3097 phb->ioda.dma32_segmap = aux + dma32map_off; 3098 for (segno = 0; segno < phb->ioda.dma32_count; segno++) 3099 phb->ioda.dma32_segmap[segno] = IODA_INVALID_PE; 3100 } 3101 phb->ioda.pe_array = aux + pemap_off; 3102 3103 /* 3104 * Choose PE number for root bus, which shouldn't have 3105 * M64 resources consumed by its child devices. To pick 3106 * the PE number adjacent to the reserved one if possible. 3107 */ 3108 pnv_ioda_reserve_pe(phb, phb->ioda.reserved_pe_idx); 3109 if (phb->ioda.reserved_pe_idx == 0) { 3110 phb->ioda.root_pe_idx = 1; 3111 pnv_ioda_reserve_pe(phb, phb->ioda.root_pe_idx); 3112 } else if (phb->ioda.reserved_pe_idx == (phb->ioda.total_pe_num - 1)) { 3113 phb->ioda.root_pe_idx = phb->ioda.reserved_pe_idx - 1; 3114 pnv_ioda_reserve_pe(phb, phb->ioda.root_pe_idx); 3115 } else { 3116 /* otherwise just allocate one */ 3117 root_pe = pnv_ioda_alloc_pe(phb, 1); 3118 phb->ioda.root_pe_idx = root_pe->pe_number; 3119 } 3120 3121 INIT_LIST_HEAD(&phb->ioda.pe_list); 3122 mutex_init(&phb->ioda.pe_list_mutex); 3123 3124 /* Calculate how many 32-bit TCE segments we have */ 3125 phb->ioda.dma32_count = phb->ioda.m32_pci_base / 3126 PNV_IODA1_DMA32_SEGSIZE; 3127 3128 #if 0 /* We should really do that ... */ 3129 rc = opal_pci_set_phb_mem_window(opal->phb_id, 3130 window_type, 3131 window_num, 3132 starting_real_address, 3133 starting_pci_address, 3134 segment_size); 3135 #endif 3136 3137 pr_info(" %03d (%03d) PE's M32: 0x%x [segment=0x%x]\n", 3138 phb->ioda.total_pe_num, phb->ioda.reserved_pe_idx, 3139 phb->ioda.m32_size, phb->ioda.m32_segsize); 3140 if (phb->ioda.m64_size) 3141 pr_info(" M64: 0x%lx [segment=0x%lx]\n", 3142 phb->ioda.m64_size, phb->ioda.m64_segsize); 3143 if (phb->ioda.io_size) 3144 pr_info(" IO: 0x%x [segment=0x%x]\n", 3145 phb->ioda.io_size, phb->ioda.io_segsize); 3146 3147 3148 phb->hose->ops = &pnv_pci_ops; 3149 phb->get_pe_state = pnv_ioda_get_pe_state; 3150 phb->freeze_pe = pnv_ioda_freeze_pe; 3151 phb->unfreeze_pe = pnv_ioda_unfreeze_pe; 3152 3153 /* Setup MSI support */ 3154 pnv_pci_init_ioda_msis(phb); 3155 3156 /* 3157 * We pass the PCI probe flag PCI_REASSIGN_ALL_RSRC here 3158 * to let the PCI core do resource assignment. It's supposed 3159 * that the PCI core will do correct I/O and MMIO alignment 3160 * for the P2P bridge bars so that each PCI bus (excluding 3161 * the child P2P bridges) can form individual PE. 3162 */ 3163 ppc_md.pcibios_fixup = pnv_pci_ioda_fixup; 3164 3165 switch (phb->type) { 3166 case PNV_PHB_NPU_OCAPI: 3167 hose->controller_ops = pnv_npu_ocapi_ioda_controller_ops; 3168 break; 3169 default: 3170 hose->controller_ops = pnv_pci_ioda_controller_ops; 3171 } 3172 3173 ppc_md.pcibios_default_alignment = pnv_pci_default_alignment; 3174 3175 #ifdef CONFIG_PCI_IOV 3176 ppc_md.pcibios_fixup_sriov = pnv_pci_ioda_fixup_iov; 3177 ppc_md.pcibios_iov_resource_alignment = pnv_pci_iov_resource_alignment; 3178 ppc_md.pcibios_sriov_enable = pnv_pcibios_sriov_enable; 3179 ppc_md.pcibios_sriov_disable = pnv_pcibios_sriov_disable; 3180 #endif 3181 3182 pci_add_flags(PCI_REASSIGN_ALL_RSRC); 3183 3184 /* Reset IODA tables to a clean state */ 3185 rc = opal_pci_reset(phb_id, OPAL_RESET_PCI_IODA_TABLE, OPAL_ASSERT_RESET); 3186 if (rc) 3187 pr_warn(" OPAL Error %ld performing IODA table reset !\n", rc); 3188 3189 /* 3190 * If we're running in kdump kernel, the previous kernel never 3191 * shutdown PCI devices correctly. We already got IODA table 3192 * cleaned out. So we have to issue PHB reset to stop all PCI 3193 * transactions from previous kernel. The ppc_pci_reset_phbs 3194 * kernel parameter will force this reset too. Additionally, 3195 * if the IODA reset above failed then use a bigger hammer. 3196 * This can happen if we get a PHB fatal error in very early 3197 * boot. 3198 */ 3199 if (is_kdump_kernel() || pci_reset_phbs || rc) { 3200 pr_info(" Issue PHB reset ...\n"); 3201 pnv_eeh_phb_reset(hose, EEH_RESET_FUNDAMENTAL); 3202 pnv_eeh_phb_reset(hose, EEH_RESET_DEACTIVATE); 3203 } 3204 3205 /* Remove M64 resource if we can't configure it successfully */ 3206 if (!phb->init_m64 || phb->init_m64(phb)) 3207 hose->mem_resources[1].flags = 0; 3208 3209 /* create pci_dn's for DT nodes under this PHB */ 3210 pci_devs_phb_init_dynamic(hose); 3211 } 3212 3213 void __init pnv_pci_init_ioda2_phb(struct device_node *np) 3214 { 3215 pnv_pci_init_ioda_phb(np, 0, PNV_PHB_IODA2); 3216 } 3217 3218 void __init pnv_pci_init_npu2_opencapi_phb(struct device_node *np) 3219 { 3220 pnv_pci_init_ioda_phb(np, 0, PNV_PHB_NPU_OCAPI); 3221 } 3222 3223 static void pnv_npu2_opencapi_cfg_size_fixup(struct pci_dev *dev) 3224 { 3225 struct pnv_phb *phb = pci_bus_to_pnvhb(dev->bus); 3226 3227 if (!machine_is(powernv)) 3228 return; 3229 3230 if (phb->type == PNV_PHB_NPU_OCAPI) 3231 dev->cfg_size = PCI_CFG_SPACE_EXP_SIZE; 3232 } 3233 DECLARE_PCI_FIXUP_EARLY(PCI_ANY_ID, PCI_ANY_ID, pnv_npu2_opencapi_cfg_size_fixup); 3234 3235 void __init pnv_pci_init_ioda_hub(struct device_node *np) 3236 { 3237 struct device_node *phbn; 3238 const __be64 *prop64; 3239 u64 hub_id; 3240 3241 pr_info("Probing IODA IO-Hub %pOF\n", np); 3242 3243 prop64 = of_get_property(np, "ibm,opal-hubid", NULL); 3244 if (!prop64) { 3245 pr_err(" Missing \"ibm,opal-hubid\" property !\n"); 3246 return; 3247 } 3248 hub_id = be64_to_cpup(prop64); 3249 pr_devel(" HUB-ID : 0x%016llx\n", hub_id); 3250 3251 /* Count child PHBs */ 3252 for_each_child_of_node(np, phbn) { 3253 /* Look for IODA1 PHBs */ 3254 if (of_device_is_compatible(phbn, "ibm,ioda-phb")) 3255 pnv_pci_init_ioda_phb(phbn, hub_id, PNV_PHB_IODA1); 3256 } 3257 } 3258