1 /* 2 * Support PCI/PCIe on PowerNV platforms 3 * 4 * Copyright 2011 Benjamin Herrenschmidt, IBM Corp. 5 * 6 * This program is free software; you can redistribute it and/or 7 * modify it under the terms of the GNU General Public License 8 * as published by the Free Software Foundation; either version 9 * 2 of the License, or (at your option) any later version. 10 */ 11 12 #undef DEBUG 13 14 #include <linux/kernel.h> 15 #include <linux/pci.h> 16 #include <linux/crash_dump.h> 17 #include <linux/delay.h> 18 #include <linux/string.h> 19 #include <linux/init.h> 20 #include <linux/bootmem.h> 21 #include <linux/irq.h> 22 #include <linux/io.h> 23 #include <linux/msi.h> 24 #include <linux/memblock.h> 25 #include <linux/iommu.h> 26 #include <linux/rculist.h> 27 #include <linux/sizes.h> 28 29 #include <asm/sections.h> 30 #include <asm/io.h> 31 #include <asm/prom.h> 32 #include <asm/pci-bridge.h> 33 #include <asm/machdep.h> 34 #include <asm/msi_bitmap.h> 35 #include <asm/ppc-pci.h> 36 #include <asm/opal.h> 37 #include <asm/iommu.h> 38 #include <asm/tce.h> 39 #include <asm/xics.h> 40 #include <asm/debugfs.h> 41 #include <asm/firmware.h> 42 #include <asm/pnv-pci.h> 43 #include <asm/mmzone.h> 44 45 #include <misc/cxl-base.h> 46 47 #include "powernv.h" 48 #include "pci.h" 49 50 #define PNV_IODA1_M64_NUM 16 /* Number of M64 BARs */ 51 #define PNV_IODA1_M64_SEGS 8 /* Segments per M64 BAR */ 52 #define PNV_IODA1_DMA32_SEGSIZE 0x10000000 53 54 #define POWERNV_IOMMU_DEFAULT_LEVELS 1 55 #define POWERNV_IOMMU_MAX_LEVELS 5 56 57 static const char * const pnv_phb_names[] = { "IODA1", "IODA2", "NPU" }; 58 static void pnv_pci_ioda2_table_free_pages(struct iommu_table *tbl); 59 60 void pe_level_printk(const struct pnv_ioda_pe *pe, const char *level, 61 const char *fmt, ...) 62 { 63 struct va_format vaf; 64 va_list args; 65 char pfix[32]; 66 67 va_start(args, fmt); 68 69 vaf.fmt = fmt; 70 vaf.va = &args; 71 72 if (pe->flags & PNV_IODA_PE_DEV) 73 strlcpy(pfix, dev_name(&pe->pdev->dev), sizeof(pfix)); 74 else if (pe->flags & (PNV_IODA_PE_BUS | PNV_IODA_PE_BUS_ALL)) 75 sprintf(pfix, "%04x:%02x ", 76 pci_domain_nr(pe->pbus), pe->pbus->number); 77 #ifdef CONFIG_PCI_IOV 78 else if (pe->flags & PNV_IODA_PE_VF) 79 sprintf(pfix, "%04x:%02x:%2x.%d", 80 pci_domain_nr(pe->parent_dev->bus), 81 (pe->rid & 0xff00) >> 8, 82 PCI_SLOT(pe->rid), PCI_FUNC(pe->rid)); 83 #endif /* CONFIG_PCI_IOV*/ 84 85 printk("%spci %s: [PE# %.2x] %pV", 86 level, pfix, pe->pe_number, &vaf); 87 88 va_end(args); 89 } 90 91 static bool pnv_iommu_bypass_disabled __read_mostly; 92 93 static int __init iommu_setup(char *str) 94 { 95 if (!str) 96 return -EINVAL; 97 98 while (*str) { 99 if (!strncmp(str, "nobypass", 8)) { 100 pnv_iommu_bypass_disabled = true; 101 pr_info("PowerNV: IOMMU bypass window disabled.\n"); 102 break; 103 } 104 str += strcspn(str, ","); 105 if (*str == ',') 106 str++; 107 } 108 109 return 0; 110 } 111 early_param("iommu", iommu_setup); 112 113 static inline bool pnv_pci_is_m64(struct pnv_phb *phb, struct resource *r) 114 { 115 /* 116 * WARNING: We cannot rely on the resource flags. The Linux PCI 117 * allocation code sometimes decides to put a 64-bit prefetchable 118 * BAR in the 32-bit window, so we have to compare the addresses. 119 * 120 * For simplicity we only test resource start. 121 */ 122 return (r->start >= phb->ioda.m64_base && 123 r->start < (phb->ioda.m64_base + phb->ioda.m64_size)); 124 } 125 126 static inline bool pnv_pci_is_m64_flags(unsigned long resource_flags) 127 { 128 unsigned long flags = (IORESOURCE_MEM_64 | IORESOURCE_PREFETCH); 129 130 return (resource_flags & flags) == flags; 131 } 132 133 static struct pnv_ioda_pe *pnv_ioda_init_pe(struct pnv_phb *phb, int pe_no) 134 { 135 s64 rc; 136 137 phb->ioda.pe_array[pe_no].phb = phb; 138 phb->ioda.pe_array[pe_no].pe_number = pe_no; 139 140 /* 141 * Clear the PE frozen state as it might be put into frozen state 142 * in the last PCI remove path. It's not harmful to do so when the 143 * PE is already in unfrozen state. 144 */ 145 rc = opal_pci_eeh_freeze_clear(phb->opal_id, pe_no, 146 OPAL_EEH_ACTION_CLEAR_FREEZE_ALL); 147 if (rc != OPAL_SUCCESS && rc != OPAL_UNSUPPORTED) 148 pr_warn("%s: Error %lld unfreezing PHB#%x-PE#%x\n", 149 __func__, rc, phb->hose->global_number, pe_no); 150 151 return &phb->ioda.pe_array[pe_no]; 152 } 153 154 static void pnv_ioda_reserve_pe(struct pnv_phb *phb, int pe_no) 155 { 156 if (!(pe_no >= 0 && pe_no < phb->ioda.total_pe_num)) { 157 pr_warn("%s: Invalid PE %x on PHB#%x\n", 158 __func__, pe_no, phb->hose->global_number); 159 return; 160 } 161 162 if (test_and_set_bit(pe_no, phb->ioda.pe_alloc)) 163 pr_debug("%s: PE %x was reserved on PHB#%x\n", 164 __func__, pe_no, phb->hose->global_number); 165 166 pnv_ioda_init_pe(phb, pe_no); 167 } 168 169 static struct pnv_ioda_pe *pnv_ioda_alloc_pe(struct pnv_phb *phb) 170 { 171 long pe; 172 173 for (pe = phb->ioda.total_pe_num - 1; pe >= 0; pe--) { 174 if (!test_and_set_bit(pe, phb->ioda.pe_alloc)) 175 return pnv_ioda_init_pe(phb, pe); 176 } 177 178 return NULL; 179 } 180 181 static void pnv_ioda_free_pe(struct pnv_ioda_pe *pe) 182 { 183 struct pnv_phb *phb = pe->phb; 184 unsigned int pe_num = pe->pe_number; 185 186 WARN_ON(pe->pdev); 187 188 memset(pe, 0, sizeof(struct pnv_ioda_pe)); 189 clear_bit(pe_num, phb->ioda.pe_alloc); 190 } 191 192 /* The default M64 BAR is shared by all PEs */ 193 static int pnv_ioda2_init_m64(struct pnv_phb *phb) 194 { 195 const char *desc; 196 struct resource *r; 197 s64 rc; 198 199 /* Configure the default M64 BAR */ 200 rc = opal_pci_set_phb_mem_window(phb->opal_id, 201 OPAL_M64_WINDOW_TYPE, 202 phb->ioda.m64_bar_idx, 203 phb->ioda.m64_base, 204 0, /* unused */ 205 phb->ioda.m64_size); 206 if (rc != OPAL_SUCCESS) { 207 desc = "configuring"; 208 goto fail; 209 } 210 211 /* Enable the default M64 BAR */ 212 rc = opal_pci_phb_mmio_enable(phb->opal_id, 213 OPAL_M64_WINDOW_TYPE, 214 phb->ioda.m64_bar_idx, 215 OPAL_ENABLE_M64_SPLIT); 216 if (rc != OPAL_SUCCESS) { 217 desc = "enabling"; 218 goto fail; 219 } 220 221 /* 222 * Exclude the segments for reserved and root bus PE, which 223 * are first or last two PEs. 224 */ 225 r = &phb->hose->mem_resources[1]; 226 if (phb->ioda.reserved_pe_idx == 0) 227 r->start += (2 * phb->ioda.m64_segsize); 228 else if (phb->ioda.reserved_pe_idx == (phb->ioda.total_pe_num - 1)) 229 r->end -= (2 * phb->ioda.m64_segsize); 230 else 231 pr_warn(" Cannot strip M64 segment for reserved PE#%x\n", 232 phb->ioda.reserved_pe_idx); 233 234 return 0; 235 236 fail: 237 pr_warn(" Failure %lld %s M64 BAR#%d\n", 238 rc, desc, phb->ioda.m64_bar_idx); 239 opal_pci_phb_mmio_enable(phb->opal_id, 240 OPAL_M64_WINDOW_TYPE, 241 phb->ioda.m64_bar_idx, 242 OPAL_DISABLE_M64); 243 return -EIO; 244 } 245 246 static void pnv_ioda_reserve_dev_m64_pe(struct pci_dev *pdev, 247 unsigned long *pe_bitmap) 248 { 249 struct pci_controller *hose = pci_bus_to_host(pdev->bus); 250 struct pnv_phb *phb = hose->private_data; 251 struct resource *r; 252 resource_size_t base, sgsz, start, end; 253 int segno, i; 254 255 base = phb->ioda.m64_base; 256 sgsz = phb->ioda.m64_segsize; 257 for (i = 0; i <= PCI_ROM_RESOURCE; i++) { 258 r = &pdev->resource[i]; 259 if (!r->parent || !pnv_pci_is_m64(phb, r)) 260 continue; 261 262 start = _ALIGN_DOWN(r->start - base, sgsz); 263 end = _ALIGN_UP(r->end - base, sgsz); 264 for (segno = start / sgsz; segno < end / sgsz; segno++) { 265 if (pe_bitmap) 266 set_bit(segno, pe_bitmap); 267 else 268 pnv_ioda_reserve_pe(phb, segno); 269 } 270 } 271 } 272 273 static int pnv_ioda1_init_m64(struct pnv_phb *phb) 274 { 275 struct resource *r; 276 int index; 277 278 /* 279 * There are 16 M64 BARs, each of which has 8 segments. So 280 * there are as many M64 segments as the maximum number of 281 * PEs, which is 128. 282 */ 283 for (index = 0; index < PNV_IODA1_M64_NUM; index++) { 284 unsigned long base, segsz = phb->ioda.m64_segsize; 285 int64_t rc; 286 287 base = phb->ioda.m64_base + 288 index * PNV_IODA1_M64_SEGS * segsz; 289 rc = opal_pci_set_phb_mem_window(phb->opal_id, 290 OPAL_M64_WINDOW_TYPE, index, base, 0, 291 PNV_IODA1_M64_SEGS * segsz); 292 if (rc != OPAL_SUCCESS) { 293 pr_warn(" Error %lld setting M64 PHB#%x-BAR#%d\n", 294 rc, phb->hose->global_number, index); 295 goto fail; 296 } 297 298 rc = opal_pci_phb_mmio_enable(phb->opal_id, 299 OPAL_M64_WINDOW_TYPE, index, 300 OPAL_ENABLE_M64_SPLIT); 301 if (rc != OPAL_SUCCESS) { 302 pr_warn(" Error %lld enabling M64 PHB#%x-BAR#%d\n", 303 rc, phb->hose->global_number, index); 304 goto fail; 305 } 306 } 307 308 /* 309 * Exclude the segments for reserved and root bus PE, which 310 * are first or last two PEs. 311 */ 312 r = &phb->hose->mem_resources[1]; 313 if (phb->ioda.reserved_pe_idx == 0) 314 r->start += (2 * phb->ioda.m64_segsize); 315 else if (phb->ioda.reserved_pe_idx == (phb->ioda.total_pe_num - 1)) 316 r->end -= (2 * phb->ioda.m64_segsize); 317 else 318 WARN(1, "Wrong reserved PE#%x on PHB#%x\n", 319 phb->ioda.reserved_pe_idx, phb->hose->global_number); 320 321 return 0; 322 323 fail: 324 for ( ; index >= 0; index--) 325 opal_pci_phb_mmio_enable(phb->opal_id, 326 OPAL_M64_WINDOW_TYPE, index, OPAL_DISABLE_M64); 327 328 return -EIO; 329 } 330 331 static void pnv_ioda_reserve_m64_pe(struct pci_bus *bus, 332 unsigned long *pe_bitmap, 333 bool all) 334 { 335 struct pci_dev *pdev; 336 337 list_for_each_entry(pdev, &bus->devices, bus_list) { 338 pnv_ioda_reserve_dev_m64_pe(pdev, pe_bitmap); 339 340 if (all && pdev->subordinate) 341 pnv_ioda_reserve_m64_pe(pdev->subordinate, 342 pe_bitmap, all); 343 } 344 } 345 346 static struct pnv_ioda_pe *pnv_ioda_pick_m64_pe(struct pci_bus *bus, bool all) 347 { 348 struct pci_controller *hose = pci_bus_to_host(bus); 349 struct pnv_phb *phb = hose->private_data; 350 struct pnv_ioda_pe *master_pe, *pe; 351 unsigned long size, *pe_alloc; 352 int i; 353 354 /* Root bus shouldn't use M64 */ 355 if (pci_is_root_bus(bus)) 356 return NULL; 357 358 /* Allocate bitmap */ 359 size = _ALIGN_UP(phb->ioda.total_pe_num / 8, sizeof(unsigned long)); 360 pe_alloc = kzalloc(size, GFP_KERNEL); 361 if (!pe_alloc) { 362 pr_warn("%s: Out of memory !\n", 363 __func__); 364 return NULL; 365 } 366 367 /* Figure out reserved PE numbers by the PE */ 368 pnv_ioda_reserve_m64_pe(bus, pe_alloc, all); 369 370 /* 371 * the current bus might not own M64 window and that's all 372 * contributed by its child buses. For the case, we needn't 373 * pick M64 dependent PE#. 374 */ 375 if (bitmap_empty(pe_alloc, phb->ioda.total_pe_num)) { 376 kfree(pe_alloc); 377 return NULL; 378 } 379 380 /* 381 * Figure out the master PE and put all slave PEs to master 382 * PE's list to form compound PE. 383 */ 384 master_pe = NULL; 385 i = -1; 386 while ((i = find_next_bit(pe_alloc, phb->ioda.total_pe_num, i + 1)) < 387 phb->ioda.total_pe_num) { 388 pe = &phb->ioda.pe_array[i]; 389 390 phb->ioda.m64_segmap[pe->pe_number] = pe->pe_number; 391 if (!master_pe) { 392 pe->flags |= PNV_IODA_PE_MASTER; 393 INIT_LIST_HEAD(&pe->slaves); 394 master_pe = pe; 395 } else { 396 pe->flags |= PNV_IODA_PE_SLAVE; 397 pe->master = master_pe; 398 list_add_tail(&pe->list, &master_pe->slaves); 399 } 400 401 /* 402 * P7IOC supports M64DT, which helps mapping M64 segment 403 * to one particular PE#. However, PHB3 has fixed mapping 404 * between M64 segment and PE#. In order to have same logic 405 * for P7IOC and PHB3, we enforce fixed mapping between M64 406 * segment and PE# on P7IOC. 407 */ 408 if (phb->type == PNV_PHB_IODA1) { 409 int64_t rc; 410 411 rc = opal_pci_map_pe_mmio_window(phb->opal_id, 412 pe->pe_number, OPAL_M64_WINDOW_TYPE, 413 pe->pe_number / PNV_IODA1_M64_SEGS, 414 pe->pe_number % PNV_IODA1_M64_SEGS); 415 if (rc != OPAL_SUCCESS) 416 pr_warn("%s: Error %lld mapping M64 for PHB#%x-PE#%x\n", 417 __func__, rc, phb->hose->global_number, 418 pe->pe_number); 419 } 420 } 421 422 kfree(pe_alloc); 423 return master_pe; 424 } 425 426 static void __init pnv_ioda_parse_m64_window(struct pnv_phb *phb) 427 { 428 struct pci_controller *hose = phb->hose; 429 struct device_node *dn = hose->dn; 430 struct resource *res; 431 u32 m64_range[2], i; 432 const __be32 *r; 433 u64 pci_addr; 434 435 if (phb->type != PNV_PHB_IODA1 && phb->type != PNV_PHB_IODA2) { 436 pr_info(" Not support M64 window\n"); 437 return; 438 } 439 440 if (!firmware_has_feature(FW_FEATURE_OPAL)) { 441 pr_info(" Firmware too old to support M64 window\n"); 442 return; 443 } 444 445 r = of_get_property(dn, "ibm,opal-m64-window", NULL); 446 if (!r) { 447 pr_info(" No <ibm,opal-m64-window> on %pOF\n", 448 dn); 449 return; 450 } 451 452 /* 453 * Find the available M64 BAR range and pickup the last one for 454 * covering the whole 64-bits space. We support only one range. 455 */ 456 if (of_property_read_u32_array(dn, "ibm,opal-available-m64-ranges", 457 m64_range, 2)) { 458 /* In absence of the property, assume 0..15 */ 459 m64_range[0] = 0; 460 m64_range[1] = 16; 461 } 462 /* We only support 64 bits in our allocator */ 463 if (m64_range[1] > 63) { 464 pr_warn("%s: Limiting M64 range to 63 (from %d) on PHB#%x\n", 465 __func__, m64_range[1], phb->hose->global_number); 466 m64_range[1] = 63; 467 } 468 /* Empty range, no m64 */ 469 if (m64_range[1] <= m64_range[0]) { 470 pr_warn("%s: M64 empty, disabling M64 usage on PHB#%x\n", 471 __func__, phb->hose->global_number); 472 return; 473 } 474 475 /* Configure M64 informations */ 476 res = &hose->mem_resources[1]; 477 res->name = dn->full_name; 478 res->start = of_translate_address(dn, r + 2); 479 res->end = res->start + of_read_number(r + 4, 2) - 1; 480 res->flags = (IORESOURCE_MEM | IORESOURCE_MEM_64 | IORESOURCE_PREFETCH); 481 pci_addr = of_read_number(r, 2); 482 hose->mem_offset[1] = res->start - pci_addr; 483 484 phb->ioda.m64_size = resource_size(res); 485 phb->ioda.m64_segsize = phb->ioda.m64_size / phb->ioda.total_pe_num; 486 phb->ioda.m64_base = pci_addr; 487 488 /* This lines up nicely with the display from processing OF ranges */ 489 pr_info(" MEM 0x%016llx..0x%016llx -> 0x%016llx (M64 #%d..%d)\n", 490 res->start, res->end, pci_addr, m64_range[0], 491 m64_range[0] + m64_range[1] - 1); 492 493 /* Mark all M64 used up by default */ 494 phb->ioda.m64_bar_alloc = (unsigned long)-1; 495 496 /* Use last M64 BAR to cover M64 window */ 497 m64_range[1]--; 498 phb->ioda.m64_bar_idx = m64_range[0] + m64_range[1]; 499 500 pr_info(" Using M64 #%d as default window\n", phb->ioda.m64_bar_idx); 501 502 /* Mark remaining ones free */ 503 for (i = m64_range[0]; i < m64_range[1]; i++) 504 clear_bit(i, &phb->ioda.m64_bar_alloc); 505 506 /* 507 * Setup init functions for M64 based on IODA version, IODA3 uses 508 * the IODA2 code. 509 */ 510 if (phb->type == PNV_PHB_IODA1) 511 phb->init_m64 = pnv_ioda1_init_m64; 512 else 513 phb->init_m64 = pnv_ioda2_init_m64; 514 phb->reserve_m64_pe = pnv_ioda_reserve_m64_pe; 515 phb->pick_m64_pe = pnv_ioda_pick_m64_pe; 516 } 517 518 static void pnv_ioda_freeze_pe(struct pnv_phb *phb, int pe_no) 519 { 520 struct pnv_ioda_pe *pe = &phb->ioda.pe_array[pe_no]; 521 struct pnv_ioda_pe *slave; 522 s64 rc; 523 524 /* Fetch master PE */ 525 if (pe->flags & PNV_IODA_PE_SLAVE) { 526 pe = pe->master; 527 if (WARN_ON(!pe || !(pe->flags & PNV_IODA_PE_MASTER))) 528 return; 529 530 pe_no = pe->pe_number; 531 } 532 533 /* Freeze master PE */ 534 rc = opal_pci_eeh_freeze_set(phb->opal_id, 535 pe_no, 536 OPAL_EEH_ACTION_SET_FREEZE_ALL); 537 if (rc != OPAL_SUCCESS) { 538 pr_warn("%s: Failure %lld freezing PHB#%x-PE#%x\n", 539 __func__, rc, phb->hose->global_number, pe_no); 540 return; 541 } 542 543 /* Freeze slave PEs */ 544 if (!(pe->flags & PNV_IODA_PE_MASTER)) 545 return; 546 547 list_for_each_entry(slave, &pe->slaves, list) { 548 rc = opal_pci_eeh_freeze_set(phb->opal_id, 549 slave->pe_number, 550 OPAL_EEH_ACTION_SET_FREEZE_ALL); 551 if (rc != OPAL_SUCCESS) 552 pr_warn("%s: Failure %lld freezing PHB#%x-PE#%x\n", 553 __func__, rc, phb->hose->global_number, 554 slave->pe_number); 555 } 556 } 557 558 static int pnv_ioda_unfreeze_pe(struct pnv_phb *phb, int pe_no, int opt) 559 { 560 struct pnv_ioda_pe *pe, *slave; 561 s64 rc; 562 563 /* Find master PE */ 564 pe = &phb->ioda.pe_array[pe_no]; 565 if (pe->flags & PNV_IODA_PE_SLAVE) { 566 pe = pe->master; 567 WARN_ON(!pe || !(pe->flags & PNV_IODA_PE_MASTER)); 568 pe_no = pe->pe_number; 569 } 570 571 /* Clear frozen state for master PE */ 572 rc = opal_pci_eeh_freeze_clear(phb->opal_id, pe_no, opt); 573 if (rc != OPAL_SUCCESS) { 574 pr_warn("%s: Failure %lld clear %d on PHB#%x-PE#%x\n", 575 __func__, rc, opt, phb->hose->global_number, pe_no); 576 return -EIO; 577 } 578 579 if (!(pe->flags & PNV_IODA_PE_MASTER)) 580 return 0; 581 582 /* Clear frozen state for slave PEs */ 583 list_for_each_entry(slave, &pe->slaves, list) { 584 rc = opal_pci_eeh_freeze_clear(phb->opal_id, 585 slave->pe_number, 586 opt); 587 if (rc != OPAL_SUCCESS) { 588 pr_warn("%s: Failure %lld clear %d on PHB#%x-PE#%x\n", 589 __func__, rc, opt, phb->hose->global_number, 590 slave->pe_number); 591 return -EIO; 592 } 593 } 594 595 return 0; 596 } 597 598 static int pnv_ioda_get_pe_state(struct pnv_phb *phb, int pe_no) 599 { 600 struct pnv_ioda_pe *slave, *pe; 601 u8 fstate, state; 602 __be16 pcierr; 603 s64 rc; 604 605 /* Sanity check on PE number */ 606 if (pe_no < 0 || pe_no >= phb->ioda.total_pe_num) 607 return OPAL_EEH_STOPPED_PERM_UNAVAIL; 608 609 /* 610 * Fetch the master PE and the PE instance might be 611 * not initialized yet. 612 */ 613 pe = &phb->ioda.pe_array[pe_no]; 614 if (pe->flags & PNV_IODA_PE_SLAVE) { 615 pe = pe->master; 616 WARN_ON(!pe || !(pe->flags & PNV_IODA_PE_MASTER)); 617 pe_no = pe->pe_number; 618 } 619 620 /* Check the master PE */ 621 rc = opal_pci_eeh_freeze_status(phb->opal_id, pe_no, 622 &state, &pcierr, NULL); 623 if (rc != OPAL_SUCCESS) { 624 pr_warn("%s: Failure %lld getting " 625 "PHB#%x-PE#%x state\n", 626 __func__, rc, 627 phb->hose->global_number, pe_no); 628 return OPAL_EEH_STOPPED_TEMP_UNAVAIL; 629 } 630 631 /* Check the slave PE */ 632 if (!(pe->flags & PNV_IODA_PE_MASTER)) 633 return state; 634 635 list_for_each_entry(slave, &pe->slaves, list) { 636 rc = opal_pci_eeh_freeze_status(phb->opal_id, 637 slave->pe_number, 638 &fstate, 639 &pcierr, 640 NULL); 641 if (rc != OPAL_SUCCESS) { 642 pr_warn("%s: Failure %lld getting " 643 "PHB#%x-PE#%x state\n", 644 __func__, rc, 645 phb->hose->global_number, slave->pe_number); 646 return OPAL_EEH_STOPPED_TEMP_UNAVAIL; 647 } 648 649 /* 650 * Override the result based on the ascending 651 * priority. 652 */ 653 if (fstate > state) 654 state = fstate; 655 } 656 657 return state; 658 } 659 660 /* Currently those 2 are only used when MSIs are enabled, this will change 661 * but in the meantime, we need to protect them to avoid warnings 662 */ 663 #ifdef CONFIG_PCI_MSI 664 struct pnv_ioda_pe *pnv_ioda_get_pe(struct pci_dev *dev) 665 { 666 struct pci_controller *hose = pci_bus_to_host(dev->bus); 667 struct pnv_phb *phb = hose->private_data; 668 struct pci_dn *pdn = pci_get_pdn(dev); 669 670 if (!pdn) 671 return NULL; 672 if (pdn->pe_number == IODA_INVALID_PE) 673 return NULL; 674 return &phb->ioda.pe_array[pdn->pe_number]; 675 } 676 #endif /* CONFIG_PCI_MSI */ 677 678 static int pnv_ioda_set_one_peltv(struct pnv_phb *phb, 679 struct pnv_ioda_pe *parent, 680 struct pnv_ioda_pe *child, 681 bool is_add) 682 { 683 const char *desc = is_add ? "adding" : "removing"; 684 uint8_t op = is_add ? OPAL_ADD_PE_TO_DOMAIN : 685 OPAL_REMOVE_PE_FROM_DOMAIN; 686 struct pnv_ioda_pe *slave; 687 long rc; 688 689 /* Parent PE affects child PE */ 690 rc = opal_pci_set_peltv(phb->opal_id, parent->pe_number, 691 child->pe_number, op); 692 if (rc != OPAL_SUCCESS) { 693 pe_warn(child, "OPAL error %ld %s to parent PELTV\n", 694 rc, desc); 695 return -ENXIO; 696 } 697 698 if (!(child->flags & PNV_IODA_PE_MASTER)) 699 return 0; 700 701 /* Compound case: parent PE affects slave PEs */ 702 list_for_each_entry(slave, &child->slaves, list) { 703 rc = opal_pci_set_peltv(phb->opal_id, parent->pe_number, 704 slave->pe_number, op); 705 if (rc != OPAL_SUCCESS) { 706 pe_warn(slave, "OPAL error %ld %s to parent PELTV\n", 707 rc, desc); 708 return -ENXIO; 709 } 710 } 711 712 return 0; 713 } 714 715 static int pnv_ioda_set_peltv(struct pnv_phb *phb, 716 struct pnv_ioda_pe *pe, 717 bool is_add) 718 { 719 struct pnv_ioda_pe *slave; 720 struct pci_dev *pdev = NULL; 721 int ret; 722 723 /* 724 * Clear PE frozen state. If it's master PE, we need 725 * clear slave PE frozen state as well. 726 */ 727 if (is_add) { 728 opal_pci_eeh_freeze_clear(phb->opal_id, pe->pe_number, 729 OPAL_EEH_ACTION_CLEAR_FREEZE_ALL); 730 if (pe->flags & PNV_IODA_PE_MASTER) { 731 list_for_each_entry(slave, &pe->slaves, list) 732 opal_pci_eeh_freeze_clear(phb->opal_id, 733 slave->pe_number, 734 OPAL_EEH_ACTION_CLEAR_FREEZE_ALL); 735 } 736 } 737 738 /* 739 * Associate PE in PELT. We need add the PE into the 740 * corresponding PELT-V as well. Otherwise, the error 741 * originated from the PE might contribute to other 742 * PEs. 743 */ 744 ret = pnv_ioda_set_one_peltv(phb, pe, pe, is_add); 745 if (ret) 746 return ret; 747 748 /* For compound PEs, any one affects all of them */ 749 if (pe->flags & PNV_IODA_PE_MASTER) { 750 list_for_each_entry(slave, &pe->slaves, list) { 751 ret = pnv_ioda_set_one_peltv(phb, slave, pe, is_add); 752 if (ret) 753 return ret; 754 } 755 } 756 757 if (pe->flags & (PNV_IODA_PE_BUS_ALL | PNV_IODA_PE_BUS)) 758 pdev = pe->pbus->self; 759 else if (pe->flags & PNV_IODA_PE_DEV) 760 pdev = pe->pdev->bus->self; 761 #ifdef CONFIG_PCI_IOV 762 else if (pe->flags & PNV_IODA_PE_VF) 763 pdev = pe->parent_dev; 764 #endif /* CONFIG_PCI_IOV */ 765 while (pdev) { 766 struct pci_dn *pdn = pci_get_pdn(pdev); 767 struct pnv_ioda_pe *parent; 768 769 if (pdn && pdn->pe_number != IODA_INVALID_PE) { 770 parent = &phb->ioda.pe_array[pdn->pe_number]; 771 ret = pnv_ioda_set_one_peltv(phb, parent, pe, is_add); 772 if (ret) 773 return ret; 774 } 775 776 pdev = pdev->bus->self; 777 } 778 779 return 0; 780 } 781 782 static int pnv_ioda_deconfigure_pe(struct pnv_phb *phb, struct pnv_ioda_pe *pe) 783 { 784 struct pci_dev *parent; 785 uint8_t bcomp, dcomp, fcomp; 786 int64_t rc; 787 long rid_end, rid; 788 789 /* Currently, we just deconfigure VF PE. Bus PE will always there.*/ 790 if (pe->pbus) { 791 int count; 792 793 dcomp = OPAL_IGNORE_RID_DEVICE_NUMBER; 794 fcomp = OPAL_IGNORE_RID_FUNCTION_NUMBER; 795 parent = pe->pbus->self; 796 if (pe->flags & PNV_IODA_PE_BUS_ALL) 797 count = pe->pbus->busn_res.end - pe->pbus->busn_res.start + 1; 798 else 799 count = 1; 800 801 switch(count) { 802 case 1: bcomp = OpalPciBusAll; break; 803 case 2: bcomp = OpalPciBus7Bits; break; 804 case 4: bcomp = OpalPciBus6Bits; break; 805 case 8: bcomp = OpalPciBus5Bits; break; 806 case 16: bcomp = OpalPciBus4Bits; break; 807 case 32: bcomp = OpalPciBus3Bits; break; 808 default: 809 dev_err(&pe->pbus->dev, "Number of subordinate buses %d unsupported\n", 810 count); 811 /* Do an exact match only */ 812 bcomp = OpalPciBusAll; 813 } 814 rid_end = pe->rid + (count << 8); 815 } else { 816 #ifdef CONFIG_PCI_IOV 817 if (pe->flags & PNV_IODA_PE_VF) 818 parent = pe->parent_dev; 819 else 820 #endif 821 parent = pe->pdev->bus->self; 822 bcomp = OpalPciBusAll; 823 dcomp = OPAL_COMPARE_RID_DEVICE_NUMBER; 824 fcomp = OPAL_COMPARE_RID_FUNCTION_NUMBER; 825 rid_end = pe->rid + 1; 826 } 827 828 /* Clear the reverse map */ 829 for (rid = pe->rid; rid < rid_end; rid++) 830 phb->ioda.pe_rmap[rid] = IODA_INVALID_PE; 831 832 /* Release from all parents PELT-V */ 833 while (parent) { 834 struct pci_dn *pdn = pci_get_pdn(parent); 835 if (pdn && pdn->pe_number != IODA_INVALID_PE) { 836 rc = opal_pci_set_peltv(phb->opal_id, pdn->pe_number, 837 pe->pe_number, OPAL_REMOVE_PE_FROM_DOMAIN); 838 /* XXX What to do in case of error ? */ 839 } 840 parent = parent->bus->self; 841 } 842 843 opal_pci_eeh_freeze_clear(phb->opal_id, pe->pe_number, 844 OPAL_EEH_ACTION_CLEAR_FREEZE_ALL); 845 846 /* Disassociate PE in PELT */ 847 rc = opal_pci_set_peltv(phb->opal_id, pe->pe_number, 848 pe->pe_number, OPAL_REMOVE_PE_FROM_DOMAIN); 849 if (rc) 850 pe_warn(pe, "OPAL error %ld remove self from PELTV\n", rc); 851 rc = opal_pci_set_pe(phb->opal_id, pe->pe_number, pe->rid, 852 bcomp, dcomp, fcomp, OPAL_UNMAP_PE); 853 if (rc) 854 pe_err(pe, "OPAL error %ld trying to setup PELT table\n", rc); 855 856 pe->pbus = NULL; 857 pe->pdev = NULL; 858 #ifdef CONFIG_PCI_IOV 859 pe->parent_dev = NULL; 860 #endif 861 862 return 0; 863 } 864 865 static int pnv_ioda_configure_pe(struct pnv_phb *phb, struct pnv_ioda_pe *pe) 866 { 867 struct pci_dev *parent; 868 uint8_t bcomp, dcomp, fcomp; 869 long rc, rid_end, rid; 870 871 /* Bus validation ? */ 872 if (pe->pbus) { 873 int count; 874 875 dcomp = OPAL_IGNORE_RID_DEVICE_NUMBER; 876 fcomp = OPAL_IGNORE_RID_FUNCTION_NUMBER; 877 parent = pe->pbus->self; 878 if (pe->flags & PNV_IODA_PE_BUS_ALL) 879 count = pe->pbus->busn_res.end - pe->pbus->busn_res.start + 1; 880 else 881 count = 1; 882 883 switch(count) { 884 case 1: bcomp = OpalPciBusAll; break; 885 case 2: bcomp = OpalPciBus7Bits; break; 886 case 4: bcomp = OpalPciBus6Bits; break; 887 case 8: bcomp = OpalPciBus5Bits; break; 888 case 16: bcomp = OpalPciBus4Bits; break; 889 case 32: bcomp = OpalPciBus3Bits; break; 890 default: 891 dev_err(&pe->pbus->dev, "Number of subordinate buses %d unsupported\n", 892 count); 893 /* Do an exact match only */ 894 bcomp = OpalPciBusAll; 895 } 896 rid_end = pe->rid + (count << 8); 897 } else { 898 #ifdef CONFIG_PCI_IOV 899 if (pe->flags & PNV_IODA_PE_VF) 900 parent = pe->parent_dev; 901 else 902 #endif /* CONFIG_PCI_IOV */ 903 parent = pe->pdev->bus->self; 904 bcomp = OpalPciBusAll; 905 dcomp = OPAL_COMPARE_RID_DEVICE_NUMBER; 906 fcomp = OPAL_COMPARE_RID_FUNCTION_NUMBER; 907 rid_end = pe->rid + 1; 908 } 909 910 /* 911 * Associate PE in PELT. We need add the PE into the 912 * corresponding PELT-V as well. Otherwise, the error 913 * originated from the PE might contribute to other 914 * PEs. 915 */ 916 rc = opal_pci_set_pe(phb->opal_id, pe->pe_number, pe->rid, 917 bcomp, dcomp, fcomp, OPAL_MAP_PE); 918 if (rc) { 919 pe_err(pe, "OPAL error %ld trying to setup PELT table\n", rc); 920 return -ENXIO; 921 } 922 923 /* 924 * Configure PELTV. NPUs don't have a PELTV table so skip 925 * configuration on them. 926 */ 927 if (phb->type != PNV_PHB_NPU) 928 pnv_ioda_set_peltv(phb, pe, true); 929 930 /* Setup reverse map */ 931 for (rid = pe->rid; rid < rid_end; rid++) 932 phb->ioda.pe_rmap[rid] = pe->pe_number; 933 934 /* Setup one MVTs on IODA1 */ 935 if (phb->type != PNV_PHB_IODA1) { 936 pe->mve_number = 0; 937 goto out; 938 } 939 940 pe->mve_number = pe->pe_number; 941 rc = opal_pci_set_mve(phb->opal_id, pe->mve_number, pe->pe_number); 942 if (rc != OPAL_SUCCESS) { 943 pe_err(pe, "OPAL error %ld setting up MVE %x\n", 944 rc, pe->mve_number); 945 pe->mve_number = -1; 946 } else { 947 rc = opal_pci_set_mve_enable(phb->opal_id, 948 pe->mve_number, OPAL_ENABLE_MVE); 949 if (rc) { 950 pe_err(pe, "OPAL error %ld enabling MVE %x\n", 951 rc, pe->mve_number); 952 pe->mve_number = -1; 953 } 954 } 955 956 out: 957 return 0; 958 } 959 960 #ifdef CONFIG_PCI_IOV 961 static int pnv_pci_vf_resource_shift(struct pci_dev *dev, int offset) 962 { 963 struct pci_dn *pdn = pci_get_pdn(dev); 964 int i; 965 struct resource *res, res2; 966 resource_size_t size; 967 u16 num_vfs; 968 969 if (!dev->is_physfn) 970 return -EINVAL; 971 972 /* 973 * "offset" is in VFs. The M64 windows are sized so that when they 974 * are segmented, each segment is the same size as the IOV BAR. 975 * Each segment is in a separate PE, and the high order bits of the 976 * address are the PE number. Therefore, each VF's BAR is in a 977 * separate PE, and changing the IOV BAR start address changes the 978 * range of PEs the VFs are in. 979 */ 980 num_vfs = pdn->num_vfs; 981 for (i = 0; i < PCI_SRIOV_NUM_BARS; i++) { 982 res = &dev->resource[i + PCI_IOV_RESOURCES]; 983 if (!res->flags || !res->parent) 984 continue; 985 986 /* 987 * The actual IOV BAR range is determined by the start address 988 * and the actual size for num_vfs VFs BAR. This check is to 989 * make sure that after shifting, the range will not overlap 990 * with another device. 991 */ 992 size = pci_iov_resource_size(dev, i + PCI_IOV_RESOURCES); 993 res2.flags = res->flags; 994 res2.start = res->start + (size * offset); 995 res2.end = res2.start + (size * num_vfs) - 1; 996 997 if (res2.end > res->end) { 998 dev_err(&dev->dev, "VF BAR%d: %pR would extend past %pR (trying to enable %d VFs shifted by %d)\n", 999 i, &res2, res, num_vfs, offset); 1000 return -EBUSY; 1001 } 1002 } 1003 1004 /* 1005 * After doing so, there would be a "hole" in the /proc/iomem when 1006 * offset is a positive value. It looks like the device return some 1007 * mmio back to the system, which actually no one could use it. 1008 */ 1009 for (i = 0; i < PCI_SRIOV_NUM_BARS; i++) { 1010 res = &dev->resource[i + PCI_IOV_RESOURCES]; 1011 if (!res->flags || !res->parent) 1012 continue; 1013 1014 size = pci_iov_resource_size(dev, i + PCI_IOV_RESOURCES); 1015 res2 = *res; 1016 res->start += size * offset; 1017 1018 dev_info(&dev->dev, "VF BAR%d: %pR shifted to %pR (%sabling %d VFs shifted by %d)\n", 1019 i, &res2, res, (offset > 0) ? "En" : "Dis", 1020 num_vfs, offset); 1021 pci_update_resource(dev, i + PCI_IOV_RESOURCES); 1022 } 1023 return 0; 1024 } 1025 #endif /* CONFIG_PCI_IOV */ 1026 1027 static struct pnv_ioda_pe *pnv_ioda_setup_dev_PE(struct pci_dev *dev) 1028 { 1029 struct pci_controller *hose = pci_bus_to_host(dev->bus); 1030 struct pnv_phb *phb = hose->private_data; 1031 struct pci_dn *pdn = pci_get_pdn(dev); 1032 struct pnv_ioda_pe *pe; 1033 1034 if (!pdn) { 1035 pr_err("%s: Device tree node not associated properly\n", 1036 pci_name(dev)); 1037 return NULL; 1038 } 1039 if (pdn->pe_number != IODA_INVALID_PE) 1040 return NULL; 1041 1042 pe = pnv_ioda_alloc_pe(phb); 1043 if (!pe) { 1044 pr_warning("%s: Not enough PE# available, disabling device\n", 1045 pci_name(dev)); 1046 return NULL; 1047 } 1048 1049 /* NOTE: We get only one ref to the pci_dev for the pdn, not for the 1050 * pointer in the PE data structure, both should be destroyed at the 1051 * same time. However, this needs to be looked at more closely again 1052 * once we actually start removing things (Hotplug, SR-IOV, ...) 1053 * 1054 * At some point we want to remove the PDN completely anyways 1055 */ 1056 pci_dev_get(dev); 1057 pdn->pcidev = dev; 1058 pdn->pe_number = pe->pe_number; 1059 pe->flags = PNV_IODA_PE_DEV; 1060 pe->pdev = dev; 1061 pe->pbus = NULL; 1062 pe->mve_number = -1; 1063 pe->rid = dev->bus->number << 8 | pdn->devfn; 1064 1065 pe_info(pe, "Associated device to PE\n"); 1066 1067 if (pnv_ioda_configure_pe(phb, pe)) { 1068 /* XXX What do we do here ? */ 1069 pnv_ioda_free_pe(pe); 1070 pdn->pe_number = IODA_INVALID_PE; 1071 pe->pdev = NULL; 1072 pci_dev_put(dev); 1073 return NULL; 1074 } 1075 1076 /* Put PE to the list */ 1077 list_add_tail(&pe->list, &phb->ioda.pe_list); 1078 1079 return pe; 1080 } 1081 1082 static void pnv_ioda_setup_same_PE(struct pci_bus *bus, struct pnv_ioda_pe *pe) 1083 { 1084 struct pci_dev *dev; 1085 1086 list_for_each_entry(dev, &bus->devices, bus_list) { 1087 struct pci_dn *pdn = pci_get_pdn(dev); 1088 1089 if (pdn == NULL) { 1090 pr_warn("%s: No device node associated with device !\n", 1091 pci_name(dev)); 1092 continue; 1093 } 1094 1095 /* 1096 * In partial hotplug case, the PCI device might be still 1097 * associated with the PE and needn't attach it to the PE 1098 * again. 1099 */ 1100 if (pdn->pe_number != IODA_INVALID_PE) 1101 continue; 1102 1103 pe->device_count++; 1104 pdn->pcidev = dev; 1105 pdn->pe_number = pe->pe_number; 1106 if ((pe->flags & PNV_IODA_PE_BUS_ALL) && dev->subordinate) 1107 pnv_ioda_setup_same_PE(dev->subordinate, pe); 1108 } 1109 } 1110 1111 /* 1112 * There're 2 types of PCI bus sensitive PEs: One that is compromised of 1113 * single PCI bus. Another one that contains the primary PCI bus and its 1114 * subordinate PCI devices and buses. The second type of PE is normally 1115 * orgiriated by PCIe-to-PCI bridge or PLX switch downstream ports. 1116 */ 1117 static struct pnv_ioda_pe *pnv_ioda_setup_bus_PE(struct pci_bus *bus, bool all) 1118 { 1119 struct pci_controller *hose = pci_bus_to_host(bus); 1120 struct pnv_phb *phb = hose->private_data; 1121 struct pnv_ioda_pe *pe = NULL; 1122 unsigned int pe_num; 1123 1124 /* 1125 * In partial hotplug case, the PE instance might be still alive. 1126 * We should reuse it instead of allocating a new one. 1127 */ 1128 pe_num = phb->ioda.pe_rmap[bus->number << 8]; 1129 if (pe_num != IODA_INVALID_PE) { 1130 pe = &phb->ioda.pe_array[pe_num]; 1131 pnv_ioda_setup_same_PE(bus, pe); 1132 return NULL; 1133 } 1134 1135 /* PE number for root bus should have been reserved */ 1136 if (pci_is_root_bus(bus) && 1137 phb->ioda.root_pe_idx != IODA_INVALID_PE) 1138 pe = &phb->ioda.pe_array[phb->ioda.root_pe_idx]; 1139 1140 /* Check if PE is determined by M64 */ 1141 if (!pe && phb->pick_m64_pe) 1142 pe = phb->pick_m64_pe(bus, all); 1143 1144 /* The PE number isn't pinned by M64 */ 1145 if (!pe) 1146 pe = pnv_ioda_alloc_pe(phb); 1147 1148 if (!pe) { 1149 pr_warning("%s: Not enough PE# available for PCI bus %04x:%02x\n", 1150 __func__, pci_domain_nr(bus), bus->number); 1151 return NULL; 1152 } 1153 1154 pe->flags |= (all ? PNV_IODA_PE_BUS_ALL : PNV_IODA_PE_BUS); 1155 pe->pbus = bus; 1156 pe->pdev = NULL; 1157 pe->mve_number = -1; 1158 pe->rid = bus->busn_res.start << 8; 1159 1160 if (all) 1161 pe_info(pe, "Secondary bus %d..%d associated with PE#%x\n", 1162 bus->busn_res.start, bus->busn_res.end, pe->pe_number); 1163 else 1164 pe_info(pe, "Secondary bus %d associated with PE#%x\n", 1165 bus->busn_res.start, pe->pe_number); 1166 1167 if (pnv_ioda_configure_pe(phb, pe)) { 1168 /* XXX What do we do here ? */ 1169 pnv_ioda_free_pe(pe); 1170 pe->pbus = NULL; 1171 return NULL; 1172 } 1173 1174 /* Associate it with all child devices */ 1175 pnv_ioda_setup_same_PE(bus, pe); 1176 1177 /* Put PE to the list */ 1178 list_add_tail(&pe->list, &phb->ioda.pe_list); 1179 1180 return pe; 1181 } 1182 1183 static struct pnv_ioda_pe *pnv_ioda_setup_npu_PE(struct pci_dev *npu_pdev) 1184 { 1185 int pe_num, found_pe = false, rc; 1186 long rid; 1187 struct pnv_ioda_pe *pe; 1188 struct pci_dev *gpu_pdev; 1189 struct pci_dn *npu_pdn; 1190 struct pci_controller *hose = pci_bus_to_host(npu_pdev->bus); 1191 struct pnv_phb *phb = hose->private_data; 1192 1193 /* 1194 * Due to a hardware errata PE#0 on the NPU is reserved for 1195 * error handling. This means we only have three PEs remaining 1196 * which need to be assigned to four links, implying some 1197 * links must share PEs. 1198 * 1199 * To achieve this we assign PEs such that NPUs linking the 1200 * same GPU get assigned the same PE. 1201 */ 1202 gpu_pdev = pnv_pci_get_gpu_dev(npu_pdev); 1203 for (pe_num = 0; pe_num < phb->ioda.total_pe_num; pe_num++) { 1204 pe = &phb->ioda.pe_array[pe_num]; 1205 if (!pe->pdev) 1206 continue; 1207 1208 if (pnv_pci_get_gpu_dev(pe->pdev) == gpu_pdev) { 1209 /* 1210 * This device has the same peer GPU so should 1211 * be assigned the same PE as the existing 1212 * peer NPU. 1213 */ 1214 dev_info(&npu_pdev->dev, 1215 "Associating to existing PE %x\n", pe_num); 1216 pci_dev_get(npu_pdev); 1217 npu_pdn = pci_get_pdn(npu_pdev); 1218 rid = npu_pdev->bus->number << 8 | npu_pdn->devfn; 1219 npu_pdn->pcidev = npu_pdev; 1220 npu_pdn->pe_number = pe_num; 1221 phb->ioda.pe_rmap[rid] = pe->pe_number; 1222 1223 /* Map the PE to this link */ 1224 rc = opal_pci_set_pe(phb->opal_id, pe_num, rid, 1225 OpalPciBusAll, 1226 OPAL_COMPARE_RID_DEVICE_NUMBER, 1227 OPAL_COMPARE_RID_FUNCTION_NUMBER, 1228 OPAL_MAP_PE); 1229 WARN_ON(rc != OPAL_SUCCESS); 1230 found_pe = true; 1231 break; 1232 } 1233 } 1234 1235 if (!found_pe) 1236 /* 1237 * Could not find an existing PE so allocate a new 1238 * one. 1239 */ 1240 return pnv_ioda_setup_dev_PE(npu_pdev); 1241 else 1242 return pe; 1243 } 1244 1245 static void pnv_ioda_setup_npu_PEs(struct pci_bus *bus) 1246 { 1247 struct pci_dev *pdev; 1248 1249 list_for_each_entry(pdev, &bus->devices, bus_list) 1250 pnv_ioda_setup_npu_PE(pdev); 1251 } 1252 1253 static void pnv_pci_ioda_setup_PEs(void) 1254 { 1255 struct pci_controller *hose, *tmp; 1256 struct pnv_phb *phb; 1257 1258 list_for_each_entry_safe(hose, tmp, &hose_list, list_node) { 1259 phb = hose->private_data; 1260 if (phb->type == PNV_PHB_NPU) { 1261 /* PE#0 is needed for error reporting */ 1262 pnv_ioda_reserve_pe(phb, 0); 1263 pnv_ioda_setup_npu_PEs(hose->bus); 1264 if (phb->model == PNV_PHB_MODEL_NPU2) 1265 pnv_npu2_init(phb); 1266 } 1267 } 1268 } 1269 1270 #ifdef CONFIG_PCI_IOV 1271 static int pnv_pci_vf_release_m64(struct pci_dev *pdev, u16 num_vfs) 1272 { 1273 struct pci_bus *bus; 1274 struct pci_controller *hose; 1275 struct pnv_phb *phb; 1276 struct pci_dn *pdn; 1277 int i, j; 1278 int m64_bars; 1279 1280 bus = pdev->bus; 1281 hose = pci_bus_to_host(bus); 1282 phb = hose->private_data; 1283 pdn = pci_get_pdn(pdev); 1284 1285 if (pdn->m64_single_mode) 1286 m64_bars = num_vfs; 1287 else 1288 m64_bars = 1; 1289 1290 for (i = 0; i < PCI_SRIOV_NUM_BARS; i++) 1291 for (j = 0; j < m64_bars; j++) { 1292 if (pdn->m64_map[j][i] == IODA_INVALID_M64) 1293 continue; 1294 opal_pci_phb_mmio_enable(phb->opal_id, 1295 OPAL_M64_WINDOW_TYPE, pdn->m64_map[j][i], 0); 1296 clear_bit(pdn->m64_map[j][i], &phb->ioda.m64_bar_alloc); 1297 pdn->m64_map[j][i] = IODA_INVALID_M64; 1298 } 1299 1300 kfree(pdn->m64_map); 1301 return 0; 1302 } 1303 1304 static int pnv_pci_vf_assign_m64(struct pci_dev *pdev, u16 num_vfs) 1305 { 1306 struct pci_bus *bus; 1307 struct pci_controller *hose; 1308 struct pnv_phb *phb; 1309 struct pci_dn *pdn; 1310 unsigned int win; 1311 struct resource *res; 1312 int i, j; 1313 int64_t rc; 1314 int total_vfs; 1315 resource_size_t size, start; 1316 int pe_num; 1317 int m64_bars; 1318 1319 bus = pdev->bus; 1320 hose = pci_bus_to_host(bus); 1321 phb = hose->private_data; 1322 pdn = pci_get_pdn(pdev); 1323 total_vfs = pci_sriov_get_totalvfs(pdev); 1324 1325 if (pdn->m64_single_mode) 1326 m64_bars = num_vfs; 1327 else 1328 m64_bars = 1; 1329 1330 pdn->m64_map = kmalloc_array(m64_bars, 1331 sizeof(*pdn->m64_map), 1332 GFP_KERNEL); 1333 if (!pdn->m64_map) 1334 return -ENOMEM; 1335 /* Initialize the m64_map to IODA_INVALID_M64 */ 1336 for (i = 0; i < m64_bars ; i++) 1337 for (j = 0; j < PCI_SRIOV_NUM_BARS; j++) 1338 pdn->m64_map[i][j] = IODA_INVALID_M64; 1339 1340 1341 for (i = 0; i < PCI_SRIOV_NUM_BARS; i++) { 1342 res = &pdev->resource[i + PCI_IOV_RESOURCES]; 1343 if (!res->flags || !res->parent) 1344 continue; 1345 1346 for (j = 0; j < m64_bars; j++) { 1347 do { 1348 win = find_next_zero_bit(&phb->ioda.m64_bar_alloc, 1349 phb->ioda.m64_bar_idx + 1, 0); 1350 1351 if (win >= phb->ioda.m64_bar_idx + 1) 1352 goto m64_failed; 1353 } while (test_and_set_bit(win, &phb->ioda.m64_bar_alloc)); 1354 1355 pdn->m64_map[j][i] = win; 1356 1357 if (pdn->m64_single_mode) { 1358 size = pci_iov_resource_size(pdev, 1359 PCI_IOV_RESOURCES + i); 1360 start = res->start + size * j; 1361 } else { 1362 size = resource_size(res); 1363 start = res->start; 1364 } 1365 1366 /* Map the M64 here */ 1367 if (pdn->m64_single_mode) { 1368 pe_num = pdn->pe_num_map[j]; 1369 rc = opal_pci_map_pe_mmio_window(phb->opal_id, 1370 pe_num, OPAL_M64_WINDOW_TYPE, 1371 pdn->m64_map[j][i], 0); 1372 } 1373 1374 rc = opal_pci_set_phb_mem_window(phb->opal_id, 1375 OPAL_M64_WINDOW_TYPE, 1376 pdn->m64_map[j][i], 1377 start, 1378 0, /* unused */ 1379 size); 1380 1381 1382 if (rc != OPAL_SUCCESS) { 1383 dev_err(&pdev->dev, "Failed to map M64 window #%d: %lld\n", 1384 win, rc); 1385 goto m64_failed; 1386 } 1387 1388 if (pdn->m64_single_mode) 1389 rc = opal_pci_phb_mmio_enable(phb->opal_id, 1390 OPAL_M64_WINDOW_TYPE, pdn->m64_map[j][i], 2); 1391 else 1392 rc = opal_pci_phb_mmio_enable(phb->opal_id, 1393 OPAL_M64_WINDOW_TYPE, pdn->m64_map[j][i], 1); 1394 1395 if (rc != OPAL_SUCCESS) { 1396 dev_err(&pdev->dev, "Failed to enable M64 window #%d: %llx\n", 1397 win, rc); 1398 goto m64_failed; 1399 } 1400 } 1401 } 1402 return 0; 1403 1404 m64_failed: 1405 pnv_pci_vf_release_m64(pdev, num_vfs); 1406 return -EBUSY; 1407 } 1408 1409 static long pnv_pci_ioda2_unset_window(struct iommu_table_group *table_group, 1410 int num); 1411 1412 static void pnv_pci_ioda2_release_dma_pe(struct pci_dev *dev, struct pnv_ioda_pe *pe) 1413 { 1414 struct iommu_table *tbl; 1415 int64_t rc; 1416 1417 tbl = pe->table_group.tables[0]; 1418 rc = pnv_pci_ioda2_unset_window(&pe->table_group, 0); 1419 if (rc) 1420 pe_warn(pe, "OPAL error %ld release DMA window\n", rc); 1421 1422 pnv_pci_ioda2_set_bypass(pe, false); 1423 if (pe->table_group.group) { 1424 iommu_group_put(pe->table_group.group); 1425 BUG_ON(pe->table_group.group); 1426 } 1427 iommu_tce_table_put(tbl); 1428 } 1429 1430 static void pnv_ioda_release_vf_PE(struct pci_dev *pdev) 1431 { 1432 struct pci_bus *bus; 1433 struct pci_controller *hose; 1434 struct pnv_phb *phb; 1435 struct pnv_ioda_pe *pe, *pe_n; 1436 struct pci_dn *pdn; 1437 1438 bus = pdev->bus; 1439 hose = pci_bus_to_host(bus); 1440 phb = hose->private_data; 1441 pdn = pci_get_pdn(pdev); 1442 1443 if (!pdev->is_physfn) 1444 return; 1445 1446 list_for_each_entry_safe(pe, pe_n, &phb->ioda.pe_list, list) { 1447 if (pe->parent_dev != pdev) 1448 continue; 1449 1450 pnv_pci_ioda2_release_dma_pe(pdev, pe); 1451 1452 /* Remove from list */ 1453 mutex_lock(&phb->ioda.pe_list_mutex); 1454 list_del(&pe->list); 1455 mutex_unlock(&phb->ioda.pe_list_mutex); 1456 1457 pnv_ioda_deconfigure_pe(phb, pe); 1458 1459 pnv_ioda_free_pe(pe); 1460 } 1461 } 1462 1463 void pnv_pci_sriov_disable(struct pci_dev *pdev) 1464 { 1465 struct pci_bus *bus; 1466 struct pci_controller *hose; 1467 struct pnv_phb *phb; 1468 struct pnv_ioda_pe *pe; 1469 struct pci_dn *pdn; 1470 u16 num_vfs, i; 1471 1472 bus = pdev->bus; 1473 hose = pci_bus_to_host(bus); 1474 phb = hose->private_data; 1475 pdn = pci_get_pdn(pdev); 1476 num_vfs = pdn->num_vfs; 1477 1478 /* Release VF PEs */ 1479 pnv_ioda_release_vf_PE(pdev); 1480 1481 if (phb->type == PNV_PHB_IODA2) { 1482 if (!pdn->m64_single_mode) 1483 pnv_pci_vf_resource_shift(pdev, -*pdn->pe_num_map); 1484 1485 /* Release M64 windows */ 1486 pnv_pci_vf_release_m64(pdev, num_vfs); 1487 1488 /* Release PE numbers */ 1489 if (pdn->m64_single_mode) { 1490 for (i = 0; i < num_vfs; i++) { 1491 if (pdn->pe_num_map[i] == IODA_INVALID_PE) 1492 continue; 1493 1494 pe = &phb->ioda.pe_array[pdn->pe_num_map[i]]; 1495 pnv_ioda_free_pe(pe); 1496 } 1497 } else 1498 bitmap_clear(phb->ioda.pe_alloc, *pdn->pe_num_map, num_vfs); 1499 /* Releasing pe_num_map */ 1500 kfree(pdn->pe_num_map); 1501 } 1502 } 1503 1504 static void pnv_pci_ioda2_setup_dma_pe(struct pnv_phb *phb, 1505 struct pnv_ioda_pe *pe); 1506 static void pnv_ioda_setup_vf_PE(struct pci_dev *pdev, u16 num_vfs) 1507 { 1508 struct pci_bus *bus; 1509 struct pci_controller *hose; 1510 struct pnv_phb *phb; 1511 struct pnv_ioda_pe *pe; 1512 int pe_num; 1513 u16 vf_index; 1514 struct pci_dn *pdn; 1515 1516 bus = pdev->bus; 1517 hose = pci_bus_to_host(bus); 1518 phb = hose->private_data; 1519 pdn = pci_get_pdn(pdev); 1520 1521 if (!pdev->is_physfn) 1522 return; 1523 1524 /* Reserve PE for each VF */ 1525 for (vf_index = 0; vf_index < num_vfs; vf_index++) { 1526 if (pdn->m64_single_mode) 1527 pe_num = pdn->pe_num_map[vf_index]; 1528 else 1529 pe_num = *pdn->pe_num_map + vf_index; 1530 1531 pe = &phb->ioda.pe_array[pe_num]; 1532 pe->pe_number = pe_num; 1533 pe->phb = phb; 1534 pe->flags = PNV_IODA_PE_VF; 1535 pe->pbus = NULL; 1536 pe->parent_dev = pdev; 1537 pe->mve_number = -1; 1538 pe->rid = (pci_iov_virtfn_bus(pdev, vf_index) << 8) | 1539 pci_iov_virtfn_devfn(pdev, vf_index); 1540 1541 pe_info(pe, "VF %04d:%02d:%02d.%d associated with PE#%x\n", 1542 hose->global_number, pdev->bus->number, 1543 PCI_SLOT(pci_iov_virtfn_devfn(pdev, vf_index)), 1544 PCI_FUNC(pci_iov_virtfn_devfn(pdev, vf_index)), pe_num); 1545 1546 if (pnv_ioda_configure_pe(phb, pe)) { 1547 /* XXX What do we do here ? */ 1548 pnv_ioda_free_pe(pe); 1549 pe->pdev = NULL; 1550 continue; 1551 } 1552 1553 /* Put PE to the list */ 1554 mutex_lock(&phb->ioda.pe_list_mutex); 1555 list_add_tail(&pe->list, &phb->ioda.pe_list); 1556 mutex_unlock(&phb->ioda.pe_list_mutex); 1557 1558 pnv_pci_ioda2_setup_dma_pe(phb, pe); 1559 } 1560 } 1561 1562 int pnv_pci_sriov_enable(struct pci_dev *pdev, u16 num_vfs) 1563 { 1564 struct pci_bus *bus; 1565 struct pci_controller *hose; 1566 struct pnv_phb *phb; 1567 struct pnv_ioda_pe *pe; 1568 struct pci_dn *pdn; 1569 int ret; 1570 u16 i; 1571 1572 bus = pdev->bus; 1573 hose = pci_bus_to_host(bus); 1574 phb = hose->private_data; 1575 pdn = pci_get_pdn(pdev); 1576 1577 if (phb->type == PNV_PHB_IODA2) { 1578 if (!pdn->vfs_expanded) { 1579 dev_info(&pdev->dev, "don't support this SRIOV device" 1580 " with non 64bit-prefetchable IOV BAR\n"); 1581 return -ENOSPC; 1582 } 1583 1584 /* 1585 * When M64 BARs functions in Single PE mode, the number of VFs 1586 * could be enabled must be less than the number of M64 BARs. 1587 */ 1588 if (pdn->m64_single_mode && num_vfs > phb->ioda.m64_bar_idx) { 1589 dev_info(&pdev->dev, "Not enough M64 BAR for VFs\n"); 1590 return -EBUSY; 1591 } 1592 1593 /* Allocating pe_num_map */ 1594 if (pdn->m64_single_mode) 1595 pdn->pe_num_map = kmalloc_array(num_vfs, 1596 sizeof(*pdn->pe_num_map), 1597 GFP_KERNEL); 1598 else 1599 pdn->pe_num_map = kmalloc(sizeof(*pdn->pe_num_map), GFP_KERNEL); 1600 1601 if (!pdn->pe_num_map) 1602 return -ENOMEM; 1603 1604 if (pdn->m64_single_mode) 1605 for (i = 0; i < num_vfs; i++) 1606 pdn->pe_num_map[i] = IODA_INVALID_PE; 1607 1608 /* Calculate available PE for required VFs */ 1609 if (pdn->m64_single_mode) { 1610 for (i = 0; i < num_vfs; i++) { 1611 pe = pnv_ioda_alloc_pe(phb); 1612 if (!pe) { 1613 ret = -EBUSY; 1614 goto m64_failed; 1615 } 1616 1617 pdn->pe_num_map[i] = pe->pe_number; 1618 } 1619 } else { 1620 mutex_lock(&phb->ioda.pe_alloc_mutex); 1621 *pdn->pe_num_map = bitmap_find_next_zero_area( 1622 phb->ioda.pe_alloc, phb->ioda.total_pe_num, 1623 0, num_vfs, 0); 1624 if (*pdn->pe_num_map >= phb->ioda.total_pe_num) { 1625 mutex_unlock(&phb->ioda.pe_alloc_mutex); 1626 dev_info(&pdev->dev, "Failed to enable VF%d\n", num_vfs); 1627 kfree(pdn->pe_num_map); 1628 return -EBUSY; 1629 } 1630 bitmap_set(phb->ioda.pe_alloc, *pdn->pe_num_map, num_vfs); 1631 mutex_unlock(&phb->ioda.pe_alloc_mutex); 1632 } 1633 pdn->num_vfs = num_vfs; 1634 1635 /* Assign M64 window accordingly */ 1636 ret = pnv_pci_vf_assign_m64(pdev, num_vfs); 1637 if (ret) { 1638 dev_info(&pdev->dev, "Not enough M64 window resources\n"); 1639 goto m64_failed; 1640 } 1641 1642 /* 1643 * When using one M64 BAR to map one IOV BAR, we need to shift 1644 * the IOV BAR according to the PE# allocated to the VFs. 1645 * Otherwise, the PE# for the VF will conflict with others. 1646 */ 1647 if (!pdn->m64_single_mode) { 1648 ret = pnv_pci_vf_resource_shift(pdev, *pdn->pe_num_map); 1649 if (ret) 1650 goto m64_failed; 1651 } 1652 } 1653 1654 /* Setup VF PEs */ 1655 pnv_ioda_setup_vf_PE(pdev, num_vfs); 1656 1657 return 0; 1658 1659 m64_failed: 1660 if (pdn->m64_single_mode) { 1661 for (i = 0; i < num_vfs; i++) { 1662 if (pdn->pe_num_map[i] == IODA_INVALID_PE) 1663 continue; 1664 1665 pe = &phb->ioda.pe_array[pdn->pe_num_map[i]]; 1666 pnv_ioda_free_pe(pe); 1667 } 1668 } else 1669 bitmap_clear(phb->ioda.pe_alloc, *pdn->pe_num_map, num_vfs); 1670 1671 /* Releasing pe_num_map */ 1672 kfree(pdn->pe_num_map); 1673 1674 return ret; 1675 } 1676 1677 int pcibios_sriov_disable(struct pci_dev *pdev) 1678 { 1679 pnv_pci_sriov_disable(pdev); 1680 1681 /* Release PCI data */ 1682 remove_dev_pci_data(pdev); 1683 return 0; 1684 } 1685 1686 int pcibios_sriov_enable(struct pci_dev *pdev, u16 num_vfs) 1687 { 1688 /* Allocate PCI data */ 1689 add_dev_pci_data(pdev); 1690 1691 return pnv_pci_sriov_enable(pdev, num_vfs); 1692 } 1693 #endif /* CONFIG_PCI_IOV */ 1694 1695 static void pnv_pci_ioda_dma_dev_setup(struct pnv_phb *phb, struct pci_dev *pdev) 1696 { 1697 struct pci_dn *pdn = pci_get_pdn(pdev); 1698 struct pnv_ioda_pe *pe; 1699 1700 /* 1701 * The function can be called while the PE# 1702 * hasn't been assigned. Do nothing for the 1703 * case. 1704 */ 1705 if (!pdn || pdn->pe_number == IODA_INVALID_PE) 1706 return; 1707 1708 pe = &phb->ioda.pe_array[pdn->pe_number]; 1709 WARN_ON(get_dma_ops(&pdev->dev) != &dma_iommu_ops); 1710 set_dma_offset(&pdev->dev, pe->tce_bypass_base); 1711 set_iommu_table_base(&pdev->dev, pe->table_group.tables[0]); 1712 /* 1713 * Note: iommu_add_device() will fail here as 1714 * for physical PE: the device is already added by now; 1715 * for virtual PE: sysfs entries are not ready yet and 1716 * tce_iommu_bus_notifier will add the device to a group later. 1717 */ 1718 } 1719 1720 static bool pnv_pci_ioda_pe_single_vendor(struct pnv_ioda_pe *pe) 1721 { 1722 unsigned short vendor = 0; 1723 struct pci_dev *pdev; 1724 1725 if (pe->device_count == 1) 1726 return true; 1727 1728 /* pe->pdev should be set if it's a single device, pe->pbus if not */ 1729 if (!pe->pbus) 1730 return true; 1731 1732 list_for_each_entry(pdev, &pe->pbus->devices, bus_list) { 1733 if (!vendor) { 1734 vendor = pdev->vendor; 1735 continue; 1736 } 1737 1738 if (pdev->vendor != vendor) 1739 return false; 1740 } 1741 1742 return true; 1743 } 1744 1745 /* 1746 * Reconfigure TVE#0 to be usable as 64-bit DMA space. 1747 * 1748 * The first 4GB of virtual memory for a PE is reserved for 32-bit accesses. 1749 * Devices can only access more than that if bit 59 of the PCI address is set 1750 * by hardware, which indicates TVE#1 should be used instead of TVE#0. 1751 * Many PCI devices are not capable of addressing that many bits, and as a 1752 * result are limited to the 4GB of virtual memory made available to 32-bit 1753 * devices in TVE#0. 1754 * 1755 * In order to work around this, reconfigure TVE#0 to be suitable for 64-bit 1756 * devices by configuring the virtual memory past the first 4GB inaccessible 1757 * by 64-bit DMAs. This should only be used by devices that want more than 1758 * 4GB, and only on PEs that have no 32-bit devices. 1759 * 1760 * Currently this will only work on PHB3 (POWER8). 1761 */ 1762 static int pnv_pci_ioda_dma_64bit_bypass(struct pnv_ioda_pe *pe) 1763 { 1764 u64 window_size, table_size, tce_count, addr; 1765 struct page *table_pages; 1766 u64 tce_order = 28; /* 256MB TCEs */ 1767 __be64 *tces; 1768 s64 rc; 1769 1770 /* 1771 * Window size needs to be a power of two, but needs to account for 1772 * shifting memory by the 4GB offset required to skip 32bit space. 1773 */ 1774 window_size = roundup_pow_of_two(memory_hotplug_max() + (1ULL << 32)); 1775 tce_count = window_size >> tce_order; 1776 table_size = tce_count << 3; 1777 1778 if (table_size < PAGE_SIZE) 1779 table_size = PAGE_SIZE; 1780 1781 table_pages = alloc_pages_node(pe->phb->hose->node, GFP_KERNEL, 1782 get_order(table_size)); 1783 if (!table_pages) 1784 goto err; 1785 1786 tces = page_address(table_pages); 1787 if (!tces) 1788 goto err; 1789 1790 memset(tces, 0, table_size); 1791 1792 for (addr = 0; addr < memory_hotplug_max(); addr += (1 << tce_order)) { 1793 tces[(addr + (1ULL << 32)) >> tce_order] = 1794 cpu_to_be64(addr | TCE_PCI_READ | TCE_PCI_WRITE); 1795 } 1796 1797 rc = opal_pci_map_pe_dma_window(pe->phb->opal_id, 1798 pe->pe_number, 1799 /* reconfigure window 0 */ 1800 (pe->pe_number << 1) + 0, 1801 1, 1802 __pa(tces), 1803 table_size, 1804 1 << tce_order); 1805 if (rc == OPAL_SUCCESS) { 1806 pe_info(pe, "Using 64-bit DMA iommu bypass (through TVE#0)\n"); 1807 return 0; 1808 } 1809 err: 1810 pe_err(pe, "Error configuring 64-bit DMA bypass\n"); 1811 return -EIO; 1812 } 1813 1814 static int pnv_pci_ioda_dma_set_mask(struct pci_dev *pdev, u64 dma_mask) 1815 { 1816 struct pci_controller *hose = pci_bus_to_host(pdev->bus); 1817 struct pnv_phb *phb = hose->private_data; 1818 struct pci_dn *pdn = pci_get_pdn(pdev); 1819 struct pnv_ioda_pe *pe; 1820 uint64_t top; 1821 bool bypass = false; 1822 s64 rc; 1823 1824 if (WARN_ON(!pdn || pdn->pe_number == IODA_INVALID_PE)) 1825 return -ENODEV;; 1826 1827 pe = &phb->ioda.pe_array[pdn->pe_number]; 1828 if (pe->tce_bypass_enabled) { 1829 top = pe->tce_bypass_base + memblock_end_of_DRAM() - 1; 1830 bypass = (dma_mask >= top); 1831 } 1832 1833 if (bypass) { 1834 dev_info(&pdev->dev, "Using 64-bit DMA iommu bypass\n"); 1835 set_dma_ops(&pdev->dev, &dma_direct_ops); 1836 } else { 1837 /* 1838 * If the device can't set the TCE bypass bit but still wants 1839 * to access 4GB or more, on PHB3 we can reconfigure TVE#0 to 1840 * bypass the 32-bit region and be usable for 64-bit DMAs. 1841 * The device needs to be able to address all of this space. 1842 */ 1843 if (dma_mask >> 32 && 1844 dma_mask > (memory_hotplug_max() + (1ULL << 32)) && 1845 pnv_pci_ioda_pe_single_vendor(pe) && 1846 phb->model == PNV_PHB_MODEL_PHB3) { 1847 /* Configure the bypass mode */ 1848 rc = pnv_pci_ioda_dma_64bit_bypass(pe); 1849 if (rc) 1850 return rc; 1851 /* 4GB offset bypasses 32-bit space */ 1852 set_dma_offset(&pdev->dev, (1ULL << 32)); 1853 set_dma_ops(&pdev->dev, &dma_direct_ops); 1854 } else if (dma_mask >> 32 && dma_mask != DMA_BIT_MASK(64)) { 1855 /* 1856 * Fail the request if a DMA mask between 32 and 64 bits 1857 * was requested but couldn't be fulfilled. Ideally we 1858 * would do this for 64-bits but historically we have 1859 * always fallen back to 32-bits. 1860 */ 1861 return -ENOMEM; 1862 } else { 1863 dev_info(&pdev->dev, "Using 32-bit DMA via iommu\n"); 1864 set_dma_ops(&pdev->dev, &dma_iommu_ops); 1865 } 1866 } 1867 *pdev->dev.dma_mask = dma_mask; 1868 1869 /* Update peer npu devices */ 1870 pnv_npu_try_dma_set_bypass(pdev, bypass); 1871 1872 return 0; 1873 } 1874 1875 static u64 pnv_pci_ioda_dma_get_required_mask(struct pci_dev *pdev) 1876 { 1877 struct pci_controller *hose = pci_bus_to_host(pdev->bus); 1878 struct pnv_phb *phb = hose->private_data; 1879 struct pci_dn *pdn = pci_get_pdn(pdev); 1880 struct pnv_ioda_pe *pe; 1881 u64 end, mask; 1882 1883 if (WARN_ON(!pdn || pdn->pe_number == IODA_INVALID_PE)) 1884 return 0; 1885 1886 pe = &phb->ioda.pe_array[pdn->pe_number]; 1887 if (!pe->tce_bypass_enabled) 1888 return __dma_get_required_mask(&pdev->dev); 1889 1890 1891 end = pe->tce_bypass_base + memblock_end_of_DRAM(); 1892 mask = 1ULL << (fls64(end) - 1); 1893 mask += mask - 1; 1894 1895 return mask; 1896 } 1897 1898 static void pnv_ioda_setup_bus_dma(struct pnv_ioda_pe *pe, 1899 struct pci_bus *bus, 1900 bool add_to_group) 1901 { 1902 struct pci_dev *dev; 1903 1904 list_for_each_entry(dev, &bus->devices, bus_list) { 1905 set_iommu_table_base(&dev->dev, pe->table_group.tables[0]); 1906 set_dma_offset(&dev->dev, pe->tce_bypass_base); 1907 if (add_to_group) 1908 iommu_add_device(&dev->dev); 1909 1910 if ((pe->flags & PNV_IODA_PE_BUS_ALL) && dev->subordinate) 1911 pnv_ioda_setup_bus_dma(pe, dev->subordinate, 1912 add_to_group); 1913 } 1914 } 1915 1916 static inline __be64 __iomem *pnv_ioda_get_inval_reg(struct pnv_phb *phb, 1917 bool real_mode) 1918 { 1919 return real_mode ? (__be64 __iomem *)(phb->regs_phys + 0x210) : 1920 (phb->regs + 0x210); 1921 } 1922 1923 static void pnv_pci_p7ioc_tce_invalidate(struct iommu_table *tbl, 1924 unsigned long index, unsigned long npages, bool rm) 1925 { 1926 struct iommu_table_group_link *tgl = list_first_entry_or_null( 1927 &tbl->it_group_list, struct iommu_table_group_link, 1928 next); 1929 struct pnv_ioda_pe *pe = container_of(tgl->table_group, 1930 struct pnv_ioda_pe, table_group); 1931 __be64 __iomem *invalidate = pnv_ioda_get_inval_reg(pe->phb, rm); 1932 unsigned long start, end, inc; 1933 1934 start = __pa(((__be64 *)tbl->it_base) + index - tbl->it_offset); 1935 end = __pa(((__be64 *)tbl->it_base) + index - tbl->it_offset + 1936 npages - 1); 1937 1938 /* p7ioc-style invalidation, 2 TCEs per write */ 1939 start |= (1ull << 63); 1940 end |= (1ull << 63); 1941 inc = 16; 1942 end |= inc - 1; /* round up end to be different than start */ 1943 1944 mb(); /* Ensure above stores are visible */ 1945 while (start <= end) { 1946 if (rm) 1947 __raw_rm_writeq(cpu_to_be64(start), invalidate); 1948 else 1949 __raw_writeq(cpu_to_be64(start), invalidate); 1950 start += inc; 1951 } 1952 1953 /* 1954 * The iommu layer will do another mb() for us on build() 1955 * and we don't care on free() 1956 */ 1957 } 1958 1959 static int pnv_ioda1_tce_build(struct iommu_table *tbl, long index, 1960 long npages, unsigned long uaddr, 1961 enum dma_data_direction direction, 1962 unsigned long attrs) 1963 { 1964 int ret = pnv_tce_build(tbl, index, npages, uaddr, direction, 1965 attrs); 1966 1967 if (!ret) 1968 pnv_pci_p7ioc_tce_invalidate(tbl, index, npages, false); 1969 1970 return ret; 1971 } 1972 1973 #ifdef CONFIG_IOMMU_API 1974 static int pnv_ioda1_tce_xchg(struct iommu_table *tbl, long index, 1975 unsigned long *hpa, enum dma_data_direction *direction) 1976 { 1977 long ret = pnv_tce_xchg(tbl, index, hpa, direction); 1978 1979 if (!ret) 1980 pnv_pci_p7ioc_tce_invalidate(tbl, index, 1, false); 1981 1982 return ret; 1983 } 1984 1985 static int pnv_ioda1_tce_xchg_rm(struct iommu_table *tbl, long index, 1986 unsigned long *hpa, enum dma_data_direction *direction) 1987 { 1988 long ret = pnv_tce_xchg(tbl, index, hpa, direction); 1989 1990 if (!ret) 1991 pnv_pci_p7ioc_tce_invalidate(tbl, index, 1, true); 1992 1993 return ret; 1994 } 1995 #endif 1996 1997 static void pnv_ioda1_tce_free(struct iommu_table *tbl, long index, 1998 long npages) 1999 { 2000 pnv_tce_free(tbl, index, npages); 2001 2002 pnv_pci_p7ioc_tce_invalidate(tbl, index, npages, false); 2003 } 2004 2005 static struct iommu_table_ops pnv_ioda1_iommu_ops = { 2006 .set = pnv_ioda1_tce_build, 2007 #ifdef CONFIG_IOMMU_API 2008 .exchange = pnv_ioda1_tce_xchg, 2009 .exchange_rm = pnv_ioda1_tce_xchg_rm, 2010 #endif 2011 .clear = pnv_ioda1_tce_free, 2012 .get = pnv_tce_get, 2013 }; 2014 2015 #define PHB3_TCE_KILL_INVAL_ALL PPC_BIT(0) 2016 #define PHB3_TCE_KILL_INVAL_PE PPC_BIT(1) 2017 #define PHB3_TCE_KILL_INVAL_ONE PPC_BIT(2) 2018 2019 static void pnv_pci_phb3_tce_invalidate_entire(struct pnv_phb *phb, bool rm) 2020 { 2021 __be64 __iomem *invalidate = pnv_ioda_get_inval_reg(phb, rm); 2022 const unsigned long val = PHB3_TCE_KILL_INVAL_ALL; 2023 2024 mb(); /* Ensure previous TCE table stores are visible */ 2025 if (rm) 2026 __raw_rm_writeq(cpu_to_be64(val), invalidate); 2027 else 2028 __raw_writeq(cpu_to_be64(val), invalidate); 2029 } 2030 2031 static inline void pnv_pci_phb3_tce_invalidate_pe(struct pnv_ioda_pe *pe) 2032 { 2033 /* 01xb - invalidate TCEs that match the specified PE# */ 2034 __be64 __iomem *invalidate = pnv_ioda_get_inval_reg(pe->phb, false); 2035 unsigned long val = PHB3_TCE_KILL_INVAL_PE | (pe->pe_number & 0xFF); 2036 2037 mb(); /* Ensure above stores are visible */ 2038 __raw_writeq(cpu_to_be64(val), invalidate); 2039 } 2040 2041 static void pnv_pci_phb3_tce_invalidate(struct pnv_ioda_pe *pe, bool rm, 2042 unsigned shift, unsigned long index, 2043 unsigned long npages) 2044 { 2045 __be64 __iomem *invalidate = pnv_ioda_get_inval_reg(pe->phb, rm); 2046 unsigned long start, end, inc; 2047 2048 /* We'll invalidate DMA address in PE scope */ 2049 start = PHB3_TCE_KILL_INVAL_ONE; 2050 start |= (pe->pe_number & 0xFF); 2051 end = start; 2052 2053 /* Figure out the start, end and step */ 2054 start |= (index << shift); 2055 end |= ((index + npages - 1) << shift); 2056 inc = (0x1ull << shift); 2057 mb(); 2058 2059 while (start <= end) { 2060 if (rm) 2061 __raw_rm_writeq(cpu_to_be64(start), invalidate); 2062 else 2063 __raw_writeq(cpu_to_be64(start), invalidate); 2064 start += inc; 2065 } 2066 } 2067 2068 static inline void pnv_pci_ioda2_tce_invalidate_pe(struct pnv_ioda_pe *pe) 2069 { 2070 struct pnv_phb *phb = pe->phb; 2071 2072 if (phb->model == PNV_PHB_MODEL_PHB3 && phb->regs) 2073 pnv_pci_phb3_tce_invalidate_pe(pe); 2074 else 2075 opal_pci_tce_kill(phb->opal_id, OPAL_PCI_TCE_KILL_PE, 2076 pe->pe_number, 0, 0, 0); 2077 } 2078 2079 static void pnv_pci_ioda2_tce_invalidate(struct iommu_table *tbl, 2080 unsigned long index, unsigned long npages, bool rm) 2081 { 2082 struct iommu_table_group_link *tgl; 2083 2084 list_for_each_entry_lockless(tgl, &tbl->it_group_list, next) { 2085 struct pnv_ioda_pe *pe = container_of(tgl->table_group, 2086 struct pnv_ioda_pe, table_group); 2087 struct pnv_phb *phb = pe->phb; 2088 unsigned int shift = tbl->it_page_shift; 2089 2090 /* 2091 * NVLink1 can use the TCE kill register directly as 2092 * it's the same as PHB3. NVLink2 is different and 2093 * should go via the OPAL call. 2094 */ 2095 if (phb->model == PNV_PHB_MODEL_NPU) { 2096 /* 2097 * The NVLink hardware does not support TCE kill 2098 * per TCE entry so we have to invalidate 2099 * the entire cache for it. 2100 */ 2101 pnv_pci_phb3_tce_invalidate_entire(phb, rm); 2102 continue; 2103 } 2104 if (phb->model == PNV_PHB_MODEL_PHB3 && phb->regs) 2105 pnv_pci_phb3_tce_invalidate(pe, rm, shift, 2106 index, npages); 2107 else 2108 opal_pci_tce_kill(phb->opal_id, 2109 OPAL_PCI_TCE_KILL_PAGES, 2110 pe->pe_number, 1u << shift, 2111 index << shift, npages); 2112 } 2113 } 2114 2115 void pnv_pci_ioda2_tce_invalidate_entire(struct pnv_phb *phb, bool rm) 2116 { 2117 if (phb->model == PNV_PHB_MODEL_NPU || phb->model == PNV_PHB_MODEL_PHB3) 2118 pnv_pci_phb3_tce_invalidate_entire(phb, rm); 2119 else 2120 opal_pci_tce_kill(phb->opal_id, OPAL_PCI_TCE_KILL, 0, 0, 0, 0); 2121 } 2122 2123 static int pnv_ioda2_tce_build(struct iommu_table *tbl, long index, 2124 long npages, unsigned long uaddr, 2125 enum dma_data_direction direction, 2126 unsigned long attrs) 2127 { 2128 int ret = pnv_tce_build(tbl, index, npages, uaddr, direction, 2129 attrs); 2130 2131 if (!ret) 2132 pnv_pci_ioda2_tce_invalidate(tbl, index, npages, false); 2133 2134 return ret; 2135 } 2136 2137 #ifdef CONFIG_IOMMU_API 2138 static int pnv_ioda2_tce_xchg(struct iommu_table *tbl, long index, 2139 unsigned long *hpa, enum dma_data_direction *direction) 2140 { 2141 long ret = pnv_tce_xchg(tbl, index, hpa, direction); 2142 2143 if (!ret) 2144 pnv_pci_ioda2_tce_invalidate(tbl, index, 1, false); 2145 2146 return ret; 2147 } 2148 2149 static int pnv_ioda2_tce_xchg_rm(struct iommu_table *tbl, long index, 2150 unsigned long *hpa, enum dma_data_direction *direction) 2151 { 2152 long ret = pnv_tce_xchg(tbl, index, hpa, direction); 2153 2154 if (!ret) 2155 pnv_pci_ioda2_tce_invalidate(tbl, index, 1, true); 2156 2157 return ret; 2158 } 2159 #endif 2160 2161 static void pnv_ioda2_tce_free(struct iommu_table *tbl, long index, 2162 long npages) 2163 { 2164 pnv_tce_free(tbl, index, npages); 2165 2166 pnv_pci_ioda2_tce_invalidate(tbl, index, npages, false); 2167 } 2168 2169 static void pnv_ioda2_table_free(struct iommu_table *tbl) 2170 { 2171 pnv_pci_ioda2_table_free_pages(tbl); 2172 } 2173 2174 static struct iommu_table_ops pnv_ioda2_iommu_ops = { 2175 .set = pnv_ioda2_tce_build, 2176 #ifdef CONFIG_IOMMU_API 2177 .exchange = pnv_ioda2_tce_xchg, 2178 .exchange_rm = pnv_ioda2_tce_xchg_rm, 2179 #endif 2180 .clear = pnv_ioda2_tce_free, 2181 .get = pnv_tce_get, 2182 .free = pnv_ioda2_table_free, 2183 }; 2184 2185 static int pnv_pci_ioda_dev_dma_weight(struct pci_dev *dev, void *data) 2186 { 2187 unsigned int *weight = (unsigned int *)data; 2188 2189 /* This is quite simplistic. The "base" weight of a device 2190 * is 10. 0 means no DMA is to be accounted for it. 2191 */ 2192 if (dev->hdr_type != PCI_HEADER_TYPE_NORMAL) 2193 return 0; 2194 2195 if (dev->class == PCI_CLASS_SERIAL_USB_UHCI || 2196 dev->class == PCI_CLASS_SERIAL_USB_OHCI || 2197 dev->class == PCI_CLASS_SERIAL_USB_EHCI) 2198 *weight += 3; 2199 else if ((dev->class >> 8) == PCI_CLASS_STORAGE_RAID) 2200 *weight += 15; 2201 else 2202 *weight += 10; 2203 2204 return 0; 2205 } 2206 2207 static unsigned int pnv_pci_ioda_pe_dma_weight(struct pnv_ioda_pe *pe) 2208 { 2209 unsigned int weight = 0; 2210 2211 /* SRIOV VF has same DMA32 weight as its PF */ 2212 #ifdef CONFIG_PCI_IOV 2213 if ((pe->flags & PNV_IODA_PE_VF) && pe->parent_dev) { 2214 pnv_pci_ioda_dev_dma_weight(pe->parent_dev, &weight); 2215 return weight; 2216 } 2217 #endif 2218 2219 if ((pe->flags & PNV_IODA_PE_DEV) && pe->pdev) { 2220 pnv_pci_ioda_dev_dma_weight(pe->pdev, &weight); 2221 } else if ((pe->flags & PNV_IODA_PE_BUS) && pe->pbus) { 2222 struct pci_dev *pdev; 2223 2224 list_for_each_entry(pdev, &pe->pbus->devices, bus_list) 2225 pnv_pci_ioda_dev_dma_weight(pdev, &weight); 2226 } else if ((pe->flags & PNV_IODA_PE_BUS_ALL) && pe->pbus) { 2227 pci_walk_bus(pe->pbus, pnv_pci_ioda_dev_dma_weight, &weight); 2228 } 2229 2230 return weight; 2231 } 2232 2233 static void pnv_pci_ioda1_setup_dma_pe(struct pnv_phb *phb, 2234 struct pnv_ioda_pe *pe) 2235 { 2236 2237 struct page *tce_mem = NULL; 2238 struct iommu_table *tbl; 2239 unsigned int weight, total_weight = 0; 2240 unsigned int tce32_segsz, base, segs, avail, i; 2241 int64_t rc; 2242 void *addr; 2243 2244 /* XXX FIXME: Handle 64-bit only DMA devices */ 2245 /* XXX FIXME: Provide 64-bit DMA facilities & non-4K TCE tables etc.. */ 2246 /* XXX FIXME: Allocate multi-level tables on PHB3 */ 2247 weight = pnv_pci_ioda_pe_dma_weight(pe); 2248 if (!weight) 2249 return; 2250 2251 pci_walk_bus(phb->hose->bus, pnv_pci_ioda_dev_dma_weight, 2252 &total_weight); 2253 segs = (weight * phb->ioda.dma32_count) / total_weight; 2254 if (!segs) 2255 segs = 1; 2256 2257 /* 2258 * Allocate contiguous DMA32 segments. We begin with the expected 2259 * number of segments. With one more attempt, the number of DMA32 2260 * segments to be allocated is decreased by one until one segment 2261 * is allocated successfully. 2262 */ 2263 do { 2264 for (base = 0; base <= phb->ioda.dma32_count - segs; base++) { 2265 for (avail = 0, i = base; i < base + segs; i++) { 2266 if (phb->ioda.dma32_segmap[i] == 2267 IODA_INVALID_PE) 2268 avail++; 2269 } 2270 2271 if (avail == segs) 2272 goto found; 2273 } 2274 } while (--segs); 2275 2276 if (!segs) { 2277 pe_warn(pe, "No available DMA32 segments\n"); 2278 return; 2279 } 2280 2281 found: 2282 tbl = pnv_pci_table_alloc(phb->hose->node); 2283 if (WARN_ON(!tbl)) 2284 return; 2285 2286 iommu_register_group(&pe->table_group, phb->hose->global_number, 2287 pe->pe_number); 2288 pnv_pci_link_table_and_group(phb->hose->node, 0, tbl, &pe->table_group); 2289 2290 /* Grab a 32-bit TCE table */ 2291 pe_info(pe, "DMA weight %d (%d), assigned (%d) %d DMA32 segments\n", 2292 weight, total_weight, base, segs); 2293 pe_info(pe, " Setting up 32-bit TCE table at %08x..%08x\n", 2294 base * PNV_IODA1_DMA32_SEGSIZE, 2295 (base + segs) * PNV_IODA1_DMA32_SEGSIZE - 1); 2296 2297 /* XXX Currently, we allocate one big contiguous table for the 2298 * TCEs. We only really need one chunk per 256M of TCE space 2299 * (ie per segment) but that's an optimization for later, it 2300 * requires some added smarts with our get/put_tce implementation 2301 * 2302 * Each TCE page is 4KB in size and each TCE entry occupies 8 2303 * bytes 2304 */ 2305 tce32_segsz = PNV_IODA1_DMA32_SEGSIZE >> (IOMMU_PAGE_SHIFT_4K - 3); 2306 tce_mem = alloc_pages_node(phb->hose->node, GFP_KERNEL, 2307 get_order(tce32_segsz * segs)); 2308 if (!tce_mem) { 2309 pe_err(pe, " Failed to allocate a 32-bit TCE memory\n"); 2310 goto fail; 2311 } 2312 addr = page_address(tce_mem); 2313 memset(addr, 0, tce32_segsz * segs); 2314 2315 /* Configure HW */ 2316 for (i = 0; i < segs; i++) { 2317 rc = opal_pci_map_pe_dma_window(phb->opal_id, 2318 pe->pe_number, 2319 base + i, 1, 2320 __pa(addr) + tce32_segsz * i, 2321 tce32_segsz, IOMMU_PAGE_SIZE_4K); 2322 if (rc) { 2323 pe_err(pe, " Failed to configure 32-bit TCE table," 2324 " err %ld\n", rc); 2325 goto fail; 2326 } 2327 } 2328 2329 /* Setup DMA32 segment mapping */ 2330 for (i = base; i < base + segs; i++) 2331 phb->ioda.dma32_segmap[i] = pe->pe_number; 2332 2333 /* Setup linux iommu table */ 2334 pnv_pci_setup_iommu_table(tbl, addr, tce32_segsz * segs, 2335 base * PNV_IODA1_DMA32_SEGSIZE, 2336 IOMMU_PAGE_SHIFT_4K); 2337 2338 tbl->it_ops = &pnv_ioda1_iommu_ops; 2339 pe->table_group.tce32_start = tbl->it_offset << tbl->it_page_shift; 2340 pe->table_group.tce32_size = tbl->it_size << tbl->it_page_shift; 2341 iommu_init_table(tbl, phb->hose->node); 2342 2343 if (pe->flags & PNV_IODA_PE_DEV) { 2344 /* 2345 * Setting table base here only for carrying iommu_group 2346 * further down to let iommu_add_device() do the job. 2347 * pnv_pci_ioda_dma_dev_setup will override it later anyway. 2348 */ 2349 set_iommu_table_base(&pe->pdev->dev, tbl); 2350 iommu_add_device(&pe->pdev->dev); 2351 } else if (pe->flags & (PNV_IODA_PE_BUS | PNV_IODA_PE_BUS_ALL)) 2352 pnv_ioda_setup_bus_dma(pe, pe->pbus, true); 2353 2354 return; 2355 fail: 2356 /* XXX Failure: Try to fallback to 64-bit only ? */ 2357 if (tce_mem) 2358 __free_pages(tce_mem, get_order(tce32_segsz * segs)); 2359 if (tbl) { 2360 pnv_pci_unlink_table_and_group(tbl, &pe->table_group); 2361 iommu_tce_table_put(tbl); 2362 } 2363 } 2364 2365 static long pnv_pci_ioda2_set_window(struct iommu_table_group *table_group, 2366 int num, struct iommu_table *tbl) 2367 { 2368 struct pnv_ioda_pe *pe = container_of(table_group, struct pnv_ioda_pe, 2369 table_group); 2370 struct pnv_phb *phb = pe->phb; 2371 int64_t rc; 2372 const unsigned long size = tbl->it_indirect_levels ? 2373 tbl->it_level_size : tbl->it_size; 2374 const __u64 start_addr = tbl->it_offset << tbl->it_page_shift; 2375 const __u64 win_size = tbl->it_size << tbl->it_page_shift; 2376 2377 pe_info(pe, "Setting up window#%d %llx..%llx pg=%x\n", num, 2378 start_addr, start_addr + win_size - 1, 2379 IOMMU_PAGE_SIZE(tbl)); 2380 2381 /* 2382 * Map TCE table through TVT. The TVE index is the PE number 2383 * shifted by 1 bit for 32-bits DMA space. 2384 */ 2385 rc = opal_pci_map_pe_dma_window(phb->opal_id, 2386 pe->pe_number, 2387 (pe->pe_number << 1) + num, 2388 tbl->it_indirect_levels + 1, 2389 __pa(tbl->it_base), 2390 size << 3, 2391 IOMMU_PAGE_SIZE(tbl)); 2392 if (rc) { 2393 pe_err(pe, "Failed to configure TCE table, err %ld\n", rc); 2394 return rc; 2395 } 2396 2397 pnv_pci_link_table_and_group(phb->hose->node, num, 2398 tbl, &pe->table_group); 2399 pnv_pci_ioda2_tce_invalidate_pe(pe); 2400 2401 return 0; 2402 } 2403 2404 void pnv_pci_ioda2_set_bypass(struct pnv_ioda_pe *pe, bool enable) 2405 { 2406 uint16_t window_id = (pe->pe_number << 1 ) + 1; 2407 int64_t rc; 2408 2409 pe_info(pe, "%sabling 64-bit DMA bypass\n", enable ? "En" : "Dis"); 2410 if (enable) { 2411 phys_addr_t top = memblock_end_of_DRAM(); 2412 2413 top = roundup_pow_of_two(top); 2414 rc = opal_pci_map_pe_dma_window_real(pe->phb->opal_id, 2415 pe->pe_number, 2416 window_id, 2417 pe->tce_bypass_base, 2418 top); 2419 } else { 2420 rc = opal_pci_map_pe_dma_window_real(pe->phb->opal_id, 2421 pe->pe_number, 2422 window_id, 2423 pe->tce_bypass_base, 2424 0); 2425 } 2426 if (rc) 2427 pe_err(pe, "OPAL error %lld configuring bypass window\n", rc); 2428 else 2429 pe->tce_bypass_enabled = enable; 2430 } 2431 2432 static long pnv_pci_ioda2_table_alloc_pages(int nid, __u64 bus_offset, 2433 __u32 page_shift, __u64 window_size, __u32 levels, 2434 struct iommu_table *tbl); 2435 2436 static long pnv_pci_ioda2_create_table(struct iommu_table_group *table_group, 2437 int num, __u32 page_shift, __u64 window_size, __u32 levels, 2438 struct iommu_table **ptbl) 2439 { 2440 struct pnv_ioda_pe *pe = container_of(table_group, struct pnv_ioda_pe, 2441 table_group); 2442 int nid = pe->phb->hose->node; 2443 __u64 bus_offset = num ? pe->tce_bypass_base : table_group->tce32_start; 2444 long ret; 2445 struct iommu_table *tbl; 2446 2447 tbl = pnv_pci_table_alloc(nid); 2448 if (!tbl) 2449 return -ENOMEM; 2450 2451 tbl->it_ops = &pnv_ioda2_iommu_ops; 2452 2453 ret = pnv_pci_ioda2_table_alloc_pages(nid, 2454 bus_offset, page_shift, window_size, 2455 levels, tbl); 2456 if (ret) { 2457 iommu_tce_table_put(tbl); 2458 return ret; 2459 } 2460 2461 *ptbl = tbl; 2462 2463 return 0; 2464 } 2465 2466 static long pnv_pci_ioda2_setup_default_config(struct pnv_ioda_pe *pe) 2467 { 2468 struct iommu_table *tbl = NULL; 2469 long rc; 2470 2471 /* 2472 * crashkernel= specifies the kdump kernel's maximum memory at 2473 * some offset and there is no guaranteed the result is a power 2474 * of 2, which will cause errors later. 2475 */ 2476 const u64 max_memory = __rounddown_pow_of_two(memory_hotplug_max()); 2477 2478 /* 2479 * In memory constrained environments, e.g. kdump kernel, the 2480 * DMA window can be larger than available memory, which will 2481 * cause errors later. 2482 */ 2483 const u64 window_size = min((u64)pe->table_group.tce32_size, max_memory); 2484 2485 rc = pnv_pci_ioda2_create_table(&pe->table_group, 0, 2486 IOMMU_PAGE_SHIFT_4K, 2487 window_size, 2488 POWERNV_IOMMU_DEFAULT_LEVELS, &tbl); 2489 if (rc) { 2490 pe_err(pe, "Failed to create 32-bit TCE table, err %ld", 2491 rc); 2492 return rc; 2493 } 2494 2495 iommu_init_table(tbl, pe->phb->hose->node); 2496 2497 rc = pnv_pci_ioda2_set_window(&pe->table_group, 0, tbl); 2498 if (rc) { 2499 pe_err(pe, "Failed to configure 32-bit TCE table, err %ld\n", 2500 rc); 2501 iommu_tce_table_put(tbl); 2502 return rc; 2503 } 2504 2505 if (!pnv_iommu_bypass_disabled) 2506 pnv_pci_ioda2_set_bypass(pe, true); 2507 2508 /* 2509 * Setting table base here only for carrying iommu_group 2510 * further down to let iommu_add_device() do the job. 2511 * pnv_pci_ioda_dma_dev_setup will override it later anyway. 2512 */ 2513 if (pe->flags & PNV_IODA_PE_DEV) 2514 set_iommu_table_base(&pe->pdev->dev, tbl); 2515 2516 return 0; 2517 } 2518 2519 #if defined(CONFIG_IOMMU_API) || defined(CONFIG_PCI_IOV) 2520 static long pnv_pci_ioda2_unset_window(struct iommu_table_group *table_group, 2521 int num) 2522 { 2523 struct pnv_ioda_pe *pe = container_of(table_group, struct pnv_ioda_pe, 2524 table_group); 2525 struct pnv_phb *phb = pe->phb; 2526 long ret; 2527 2528 pe_info(pe, "Removing DMA window #%d\n", num); 2529 2530 ret = opal_pci_map_pe_dma_window(phb->opal_id, pe->pe_number, 2531 (pe->pe_number << 1) + num, 2532 0/* levels */, 0/* table address */, 2533 0/* table size */, 0/* page size */); 2534 if (ret) 2535 pe_warn(pe, "Unmapping failed, ret = %ld\n", ret); 2536 else 2537 pnv_pci_ioda2_tce_invalidate_pe(pe); 2538 2539 pnv_pci_unlink_table_and_group(table_group->tables[num], table_group); 2540 2541 return ret; 2542 } 2543 #endif 2544 2545 #ifdef CONFIG_IOMMU_API 2546 static unsigned long pnv_pci_ioda2_get_table_size(__u32 page_shift, 2547 __u64 window_size, __u32 levels) 2548 { 2549 unsigned long bytes = 0; 2550 const unsigned window_shift = ilog2(window_size); 2551 unsigned entries_shift = window_shift - page_shift; 2552 unsigned table_shift = entries_shift + 3; 2553 unsigned long tce_table_size = max(0x1000UL, 1UL << table_shift); 2554 unsigned long direct_table_size; 2555 2556 if (!levels || (levels > POWERNV_IOMMU_MAX_LEVELS) || 2557 (window_size > memory_hotplug_max()) || 2558 !is_power_of_2(window_size)) 2559 return 0; 2560 2561 /* Calculate a direct table size from window_size and levels */ 2562 entries_shift = (entries_shift + levels - 1) / levels; 2563 table_shift = entries_shift + 3; 2564 table_shift = max_t(unsigned, table_shift, PAGE_SHIFT); 2565 direct_table_size = 1UL << table_shift; 2566 2567 for ( ; levels; --levels) { 2568 bytes += _ALIGN_UP(tce_table_size, direct_table_size); 2569 2570 tce_table_size /= direct_table_size; 2571 tce_table_size <<= 3; 2572 tce_table_size = max_t(unsigned long, 2573 tce_table_size, direct_table_size); 2574 } 2575 2576 return bytes; 2577 } 2578 2579 static void pnv_ioda2_take_ownership(struct iommu_table_group *table_group) 2580 { 2581 struct pnv_ioda_pe *pe = container_of(table_group, struct pnv_ioda_pe, 2582 table_group); 2583 /* Store @tbl as pnv_pci_ioda2_unset_window() resets it */ 2584 struct iommu_table *tbl = pe->table_group.tables[0]; 2585 2586 pnv_pci_ioda2_set_bypass(pe, false); 2587 pnv_pci_ioda2_unset_window(&pe->table_group, 0); 2588 if (pe->pbus) 2589 pnv_ioda_setup_bus_dma(pe, pe->pbus, false); 2590 iommu_tce_table_put(tbl); 2591 } 2592 2593 static void pnv_ioda2_release_ownership(struct iommu_table_group *table_group) 2594 { 2595 struct pnv_ioda_pe *pe = container_of(table_group, struct pnv_ioda_pe, 2596 table_group); 2597 2598 pnv_pci_ioda2_setup_default_config(pe); 2599 if (pe->pbus) 2600 pnv_ioda_setup_bus_dma(pe, pe->pbus, false); 2601 } 2602 2603 static struct iommu_table_group_ops pnv_pci_ioda2_ops = { 2604 .get_table_size = pnv_pci_ioda2_get_table_size, 2605 .create_table = pnv_pci_ioda2_create_table, 2606 .set_window = pnv_pci_ioda2_set_window, 2607 .unset_window = pnv_pci_ioda2_unset_window, 2608 .take_ownership = pnv_ioda2_take_ownership, 2609 .release_ownership = pnv_ioda2_release_ownership, 2610 }; 2611 2612 static int gpe_table_group_to_npe_cb(struct device *dev, void *opaque) 2613 { 2614 struct pci_controller *hose; 2615 struct pnv_phb *phb; 2616 struct pnv_ioda_pe **ptmppe = opaque; 2617 struct pci_dev *pdev = container_of(dev, struct pci_dev, dev); 2618 struct pci_dn *pdn = pci_get_pdn(pdev); 2619 2620 if (!pdn || pdn->pe_number == IODA_INVALID_PE) 2621 return 0; 2622 2623 hose = pci_bus_to_host(pdev->bus); 2624 phb = hose->private_data; 2625 if (phb->type != PNV_PHB_NPU) 2626 return 0; 2627 2628 *ptmppe = &phb->ioda.pe_array[pdn->pe_number]; 2629 2630 return 1; 2631 } 2632 2633 /* 2634 * This returns PE of associated NPU. 2635 * This assumes that NPU is in the same IOMMU group with GPU and there is 2636 * no other PEs. 2637 */ 2638 static struct pnv_ioda_pe *gpe_table_group_to_npe( 2639 struct iommu_table_group *table_group) 2640 { 2641 struct pnv_ioda_pe *npe = NULL; 2642 int ret = iommu_group_for_each_dev(table_group->group, &npe, 2643 gpe_table_group_to_npe_cb); 2644 2645 BUG_ON(!ret || !npe); 2646 2647 return npe; 2648 } 2649 2650 static long pnv_pci_ioda2_npu_set_window(struct iommu_table_group *table_group, 2651 int num, struct iommu_table *tbl) 2652 { 2653 long ret = pnv_pci_ioda2_set_window(table_group, num, tbl); 2654 2655 if (ret) 2656 return ret; 2657 2658 ret = pnv_npu_set_window(gpe_table_group_to_npe(table_group), num, tbl); 2659 if (ret) 2660 pnv_pci_ioda2_unset_window(table_group, num); 2661 2662 return ret; 2663 } 2664 2665 static long pnv_pci_ioda2_npu_unset_window( 2666 struct iommu_table_group *table_group, 2667 int num) 2668 { 2669 long ret = pnv_pci_ioda2_unset_window(table_group, num); 2670 2671 if (ret) 2672 return ret; 2673 2674 return pnv_npu_unset_window(gpe_table_group_to_npe(table_group), num); 2675 } 2676 2677 static void pnv_ioda2_npu_take_ownership(struct iommu_table_group *table_group) 2678 { 2679 /* 2680 * Detach NPU first as pnv_ioda2_take_ownership() will destroy 2681 * the iommu_table if 32bit DMA is enabled. 2682 */ 2683 pnv_npu_take_ownership(gpe_table_group_to_npe(table_group)); 2684 pnv_ioda2_take_ownership(table_group); 2685 } 2686 2687 static struct iommu_table_group_ops pnv_pci_ioda2_npu_ops = { 2688 .get_table_size = pnv_pci_ioda2_get_table_size, 2689 .create_table = pnv_pci_ioda2_create_table, 2690 .set_window = pnv_pci_ioda2_npu_set_window, 2691 .unset_window = pnv_pci_ioda2_npu_unset_window, 2692 .take_ownership = pnv_ioda2_npu_take_ownership, 2693 .release_ownership = pnv_ioda2_release_ownership, 2694 }; 2695 2696 static void pnv_pci_ioda_setup_iommu_api(void) 2697 { 2698 struct pci_controller *hose, *tmp; 2699 struct pnv_phb *phb; 2700 struct pnv_ioda_pe *pe, *gpe; 2701 2702 /* 2703 * Now we have all PHBs discovered, time to add NPU devices to 2704 * the corresponding IOMMU groups. 2705 */ 2706 list_for_each_entry_safe(hose, tmp, &hose_list, list_node) { 2707 phb = hose->private_data; 2708 2709 if (phb->type != PNV_PHB_NPU) 2710 continue; 2711 2712 list_for_each_entry(pe, &phb->ioda.pe_list, list) { 2713 gpe = pnv_pci_npu_setup_iommu(pe); 2714 if (gpe) 2715 gpe->table_group.ops = &pnv_pci_ioda2_npu_ops; 2716 } 2717 } 2718 } 2719 #else /* !CONFIG_IOMMU_API */ 2720 static void pnv_pci_ioda_setup_iommu_api(void) { }; 2721 #endif 2722 2723 static __be64 *pnv_pci_ioda2_table_do_alloc_pages(int nid, unsigned shift, 2724 unsigned levels, unsigned long limit, 2725 unsigned long *current_offset, unsigned long *total_allocated) 2726 { 2727 struct page *tce_mem = NULL; 2728 __be64 *addr, *tmp; 2729 unsigned order = max_t(unsigned, shift, PAGE_SHIFT) - PAGE_SHIFT; 2730 unsigned long allocated = 1UL << (order + PAGE_SHIFT); 2731 unsigned entries = 1UL << (shift - 3); 2732 long i; 2733 2734 tce_mem = alloc_pages_node(nid, GFP_KERNEL, order); 2735 if (!tce_mem) { 2736 pr_err("Failed to allocate a TCE memory, order=%d\n", order); 2737 return NULL; 2738 } 2739 addr = page_address(tce_mem); 2740 memset(addr, 0, allocated); 2741 *total_allocated += allocated; 2742 2743 --levels; 2744 if (!levels) { 2745 *current_offset += allocated; 2746 return addr; 2747 } 2748 2749 for (i = 0; i < entries; ++i) { 2750 tmp = pnv_pci_ioda2_table_do_alloc_pages(nid, shift, 2751 levels, limit, current_offset, total_allocated); 2752 if (!tmp) 2753 break; 2754 2755 addr[i] = cpu_to_be64(__pa(tmp) | 2756 TCE_PCI_READ | TCE_PCI_WRITE); 2757 2758 if (*current_offset >= limit) 2759 break; 2760 } 2761 2762 return addr; 2763 } 2764 2765 static void pnv_pci_ioda2_table_do_free_pages(__be64 *addr, 2766 unsigned long size, unsigned level); 2767 2768 static long pnv_pci_ioda2_table_alloc_pages(int nid, __u64 bus_offset, 2769 __u32 page_shift, __u64 window_size, __u32 levels, 2770 struct iommu_table *tbl) 2771 { 2772 void *addr; 2773 unsigned long offset = 0, level_shift, total_allocated = 0; 2774 const unsigned window_shift = ilog2(window_size); 2775 unsigned entries_shift = window_shift - page_shift; 2776 unsigned table_shift = max_t(unsigned, entries_shift + 3, PAGE_SHIFT); 2777 const unsigned long tce_table_size = 1UL << table_shift; 2778 2779 if (!levels || (levels > POWERNV_IOMMU_MAX_LEVELS)) 2780 return -EINVAL; 2781 2782 if ((window_size > memory_hotplug_max()) || !is_power_of_2(window_size)) 2783 return -EINVAL; 2784 2785 /* Adjust direct table size from window_size and levels */ 2786 entries_shift = (entries_shift + levels - 1) / levels; 2787 level_shift = entries_shift + 3; 2788 level_shift = max_t(unsigned, level_shift, PAGE_SHIFT); 2789 2790 if ((level_shift - 3) * levels + page_shift >= 60) 2791 return -EINVAL; 2792 2793 /* Allocate TCE table */ 2794 addr = pnv_pci_ioda2_table_do_alloc_pages(nid, level_shift, 2795 levels, tce_table_size, &offset, &total_allocated); 2796 2797 /* addr==NULL means that the first level allocation failed */ 2798 if (!addr) 2799 return -ENOMEM; 2800 2801 /* 2802 * First level was allocated but some lower level failed as 2803 * we did not allocate as much as we wanted, 2804 * release partially allocated table. 2805 */ 2806 if (offset < tce_table_size) { 2807 pnv_pci_ioda2_table_do_free_pages(addr, 2808 1ULL << (level_shift - 3), levels - 1); 2809 return -ENOMEM; 2810 } 2811 2812 /* Setup linux iommu table */ 2813 pnv_pci_setup_iommu_table(tbl, addr, tce_table_size, bus_offset, 2814 page_shift); 2815 tbl->it_level_size = 1ULL << (level_shift - 3); 2816 tbl->it_indirect_levels = levels - 1; 2817 tbl->it_allocated_size = total_allocated; 2818 2819 pr_devel("Created TCE table: ws=%08llx ts=%lx @%08llx\n", 2820 window_size, tce_table_size, bus_offset); 2821 2822 return 0; 2823 } 2824 2825 static void pnv_pci_ioda2_table_do_free_pages(__be64 *addr, 2826 unsigned long size, unsigned level) 2827 { 2828 const unsigned long addr_ul = (unsigned long) addr & 2829 ~(TCE_PCI_READ | TCE_PCI_WRITE); 2830 2831 if (level) { 2832 long i; 2833 u64 *tmp = (u64 *) addr_ul; 2834 2835 for (i = 0; i < size; ++i) { 2836 unsigned long hpa = be64_to_cpu(tmp[i]); 2837 2838 if (!(hpa & (TCE_PCI_READ | TCE_PCI_WRITE))) 2839 continue; 2840 2841 pnv_pci_ioda2_table_do_free_pages(__va(hpa), size, 2842 level - 1); 2843 } 2844 } 2845 2846 free_pages(addr_ul, get_order(size << 3)); 2847 } 2848 2849 static void pnv_pci_ioda2_table_free_pages(struct iommu_table *tbl) 2850 { 2851 const unsigned long size = tbl->it_indirect_levels ? 2852 tbl->it_level_size : tbl->it_size; 2853 2854 if (!tbl->it_size) 2855 return; 2856 2857 pnv_pci_ioda2_table_do_free_pages((__be64 *)tbl->it_base, size, 2858 tbl->it_indirect_levels); 2859 } 2860 2861 static void pnv_pci_ioda2_setup_dma_pe(struct pnv_phb *phb, 2862 struct pnv_ioda_pe *pe) 2863 { 2864 int64_t rc; 2865 2866 if (!pnv_pci_ioda_pe_dma_weight(pe)) 2867 return; 2868 2869 /* TVE #1 is selected by PCI address bit 59 */ 2870 pe->tce_bypass_base = 1ull << 59; 2871 2872 iommu_register_group(&pe->table_group, phb->hose->global_number, 2873 pe->pe_number); 2874 2875 /* The PE will reserve all possible 32-bits space */ 2876 pe_info(pe, "Setting up 32-bit TCE table at 0..%08x\n", 2877 phb->ioda.m32_pci_base); 2878 2879 /* Setup linux iommu table */ 2880 pe->table_group.tce32_start = 0; 2881 pe->table_group.tce32_size = phb->ioda.m32_pci_base; 2882 pe->table_group.max_dynamic_windows_supported = 2883 IOMMU_TABLE_GROUP_MAX_TABLES; 2884 pe->table_group.max_levels = POWERNV_IOMMU_MAX_LEVELS; 2885 pe->table_group.pgsizes = SZ_4K | SZ_64K | SZ_16M; 2886 #ifdef CONFIG_IOMMU_API 2887 pe->table_group.ops = &pnv_pci_ioda2_ops; 2888 #endif 2889 2890 rc = pnv_pci_ioda2_setup_default_config(pe); 2891 if (rc) 2892 return; 2893 2894 if (pe->flags & (PNV_IODA_PE_BUS | PNV_IODA_PE_BUS_ALL)) 2895 pnv_ioda_setup_bus_dma(pe, pe->pbus, true); 2896 } 2897 2898 #ifdef CONFIG_PCI_MSI 2899 int64_t pnv_opal_pci_msi_eoi(struct irq_chip *chip, unsigned int hw_irq) 2900 { 2901 struct pnv_phb *phb = container_of(chip, struct pnv_phb, 2902 ioda.irq_chip); 2903 2904 return opal_pci_msi_eoi(phb->opal_id, hw_irq); 2905 } 2906 2907 static void pnv_ioda2_msi_eoi(struct irq_data *d) 2908 { 2909 int64_t rc; 2910 unsigned int hw_irq = (unsigned int)irqd_to_hwirq(d); 2911 struct irq_chip *chip = irq_data_get_irq_chip(d); 2912 2913 rc = pnv_opal_pci_msi_eoi(chip, hw_irq); 2914 WARN_ON_ONCE(rc); 2915 2916 icp_native_eoi(d); 2917 } 2918 2919 2920 void pnv_set_msi_irq_chip(struct pnv_phb *phb, unsigned int virq) 2921 { 2922 struct irq_data *idata; 2923 struct irq_chip *ichip; 2924 2925 /* The MSI EOI OPAL call is only needed on PHB3 */ 2926 if (phb->model != PNV_PHB_MODEL_PHB3) 2927 return; 2928 2929 if (!phb->ioda.irq_chip_init) { 2930 /* 2931 * First time we setup an MSI IRQ, we need to setup the 2932 * corresponding IRQ chip to route correctly. 2933 */ 2934 idata = irq_get_irq_data(virq); 2935 ichip = irq_data_get_irq_chip(idata); 2936 phb->ioda.irq_chip_init = 1; 2937 phb->ioda.irq_chip = *ichip; 2938 phb->ioda.irq_chip.irq_eoi = pnv_ioda2_msi_eoi; 2939 } 2940 irq_set_chip(virq, &phb->ioda.irq_chip); 2941 } 2942 2943 /* 2944 * Returns true iff chip is something that we could call 2945 * pnv_opal_pci_msi_eoi for. 2946 */ 2947 bool is_pnv_opal_msi(struct irq_chip *chip) 2948 { 2949 return chip->irq_eoi == pnv_ioda2_msi_eoi; 2950 } 2951 EXPORT_SYMBOL_GPL(is_pnv_opal_msi); 2952 2953 static int pnv_pci_ioda_msi_setup(struct pnv_phb *phb, struct pci_dev *dev, 2954 unsigned int hwirq, unsigned int virq, 2955 unsigned int is_64, struct msi_msg *msg) 2956 { 2957 struct pnv_ioda_pe *pe = pnv_ioda_get_pe(dev); 2958 unsigned int xive_num = hwirq - phb->msi_base; 2959 __be32 data; 2960 int rc; 2961 2962 /* No PE assigned ? bail out ... no MSI for you ! */ 2963 if (pe == NULL) 2964 return -ENXIO; 2965 2966 /* Check if we have an MVE */ 2967 if (pe->mve_number < 0) 2968 return -ENXIO; 2969 2970 /* Force 32-bit MSI on some broken devices */ 2971 if (dev->no_64bit_msi) 2972 is_64 = 0; 2973 2974 /* Assign XIVE to PE */ 2975 rc = opal_pci_set_xive_pe(phb->opal_id, pe->pe_number, xive_num); 2976 if (rc) { 2977 pr_warn("%s: OPAL error %d setting XIVE %d PE\n", 2978 pci_name(dev), rc, xive_num); 2979 return -EIO; 2980 } 2981 2982 if (is_64) { 2983 __be64 addr64; 2984 2985 rc = opal_get_msi_64(phb->opal_id, pe->mve_number, xive_num, 1, 2986 &addr64, &data); 2987 if (rc) { 2988 pr_warn("%s: OPAL error %d getting 64-bit MSI data\n", 2989 pci_name(dev), rc); 2990 return -EIO; 2991 } 2992 msg->address_hi = be64_to_cpu(addr64) >> 32; 2993 msg->address_lo = be64_to_cpu(addr64) & 0xfffffffful; 2994 } else { 2995 __be32 addr32; 2996 2997 rc = opal_get_msi_32(phb->opal_id, pe->mve_number, xive_num, 1, 2998 &addr32, &data); 2999 if (rc) { 3000 pr_warn("%s: OPAL error %d getting 32-bit MSI data\n", 3001 pci_name(dev), rc); 3002 return -EIO; 3003 } 3004 msg->address_hi = 0; 3005 msg->address_lo = be32_to_cpu(addr32); 3006 } 3007 msg->data = be32_to_cpu(data); 3008 3009 pnv_set_msi_irq_chip(phb, virq); 3010 3011 pr_devel("%s: %s-bit MSI on hwirq %x (xive #%d)," 3012 " address=%x_%08x data=%x PE# %x\n", 3013 pci_name(dev), is_64 ? "64" : "32", hwirq, xive_num, 3014 msg->address_hi, msg->address_lo, data, pe->pe_number); 3015 3016 return 0; 3017 } 3018 3019 static void pnv_pci_init_ioda_msis(struct pnv_phb *phb) 3020 { 3021 unsigned int count; 3022 const __be32 *prop = of_get_property(phb->hose->dn, 3023 "ibm,opal-msi-ranges", NULL); 3024 if (!prop) { 3025 /* BML Fallback */ 3026 prop = of_get_property(phb->hose->dn, "msi-ranges", NULL); 3027 } 3028 if (!prop) 3029 return; 3030 3031 phb->msi_base = be32_to_cpup(prop); 3032 count = be32_to_cpup(prop + 1); 3033 if (msi_bitmap_alloc(&phb->msi_bmp, count, phb->hose->dn)) { 3034 pr_err("PCI %d: Failed to allocate MSI bitmap !\n", 3035 phb->hose->global_number); 3036 return; 3037 } 3038 3039 phb->msi_setup = pnv_pci_ioda_msi_setup; 3040 phb->msi32_support = 1; 3041 pr_info(" Allocated bitmap for %d MSIs (base IRQ 0x%x)\n", 3042 count, phb->msi_base); 3043 } 3044 #else 3045 static void pnv_pci_init_ioda_msis(struct pnv_phb *phb) { } 3046 #endif /* CONFIG_PCI_MSI */ 3047 3048 #ifdef CONFIG_PCI_IOV 3049 static void pnv_pci_ioda_fixup_iov_resources(struct pci_dev *pdev) 3050 { 3051 struct pci_controller *hose = pci_bus_to_host(pdev->bus); 3052 struct pnv_phb *phb = hose->private_data; 3053 const resource_size_t gate = phb->ioda.m64_segsize >> 2; 3054 struct resource *res; 3055 int i; 3056 resource_size_t size, total_vf_bar_sz; 3057 struct pci_dn *pdn; 3058 int mul, total_vfs; 3059 3060 if (!pdev->is_physfn || pdev->is_added) 3061 return; 3062 3063 pdn = pci_get_pdn(pdev); 3064 pdn->vfs_expanded = 0; 3065 pdn->m64_single_mode = false; 3066 3067 total_vfs = pci_sriov_get_totalvfs(pdev); 3068 mul = phb->ioda.total_pe_num; 3069 total_vf_bar_sz = 0; 3070 3071 for (i = 0; i < PCI_SRIOV_NUM_BARS; i++) { 3072 res = &pdev->resource[i + PCI_IOV_RESOURCES]; 3073 if (!res->flags || res->parent) 3074 continue; 3075 if (!pnv_pci_is_m64_flags(res->flags)) { 3076 dev_warn(&pdev->dev, "Don't support SR-IOV with" 3077 " non M64 VF BAR%d: %pR. \n", 3078 i, res); 3079 goto truncate_iov; 3080 } 3081 3082 total_vf_bar_sz += pci_iov_resource_size(pdev, 3083 i + PCI_IOV_RESOURCES); 3084 3085 /* 3086 * If bigger than quarter of M64 segment size, just round up 3087 * power of two. 3088 * 3089 * Generally, one M64 BAR maps one IOV BAR. To avoid conflict 3090 * with other devices, IOV BAR size is expanded to be 3091 * (total_pe * VF_BAR_size). When VF_BAR_size is half of M64 3092 * segment size , the expanded size would equal to half of the 3093 * whole M64 space size, which will exhaust the M64 Space and 3094 * limit the system flexibility. This is a design decision to 3095 * set the boundary to quarter of the M64 segment size. 3096 */ 3097 if (total_vf_bar_sz > gate) { 3098 mul = roundup_pow_of_two(total_vfs); 3099 dev_info(&pdev->dev, 3100 "VF BAR Total IOV size %llx > %llx, roundup to %d VFs\n", 3101 total_vf_bar_sz, gate, mul); 3102 pdn->m64_single_mode = true; 3103 break; 3104 } 3105 } 3106 3107 for (i = 0; i < PCI_SRIOV_NUM_BARS; i++) { 3108 res = &pdev->resource[i + PCI_IOV_RESOURCES]; 3109 if (!res->flags || res->parent) 3110 continue; 3111 3112 size = pci_iov_resource_size(pdev, i + PCI_IOV_RESOURCES); 3113 /* 3114 * On PHB3, the minimum size alignment of M64 BAR in single 3115 * mode is 32MB. 3116 */ 3117 if (pdn->m64_single_mode && (size < SZ_32M)) 3118 goto truncate_iov; 3119 dev_dbg(&pdev->dev, " Fixing VF BAR%d: %pR to\n", i, res); 3120 res->end = res->start + size * mul - 1; 3121 dev_dbg(&pdev->dev, " %pR\n", res); 3122 dev_info(&pdev->dev, "VF BAR%d: %pR (expanded to %d VFs for PE alignment)", 3123 i, res, mul); 3124 } 3125 pdn->vfs_expanded = mul; 3126 3127 return; 3128 3129 truncate_iov: 3130 /* To save MMIO space, IOV BAR is truncated. */ 3131 for (i = 0; i < PCI_SRIOV_NUM_BARS; i++) { 3132 res = &pdev->resource[i + PCI_IOV_RESOURCES]; 3133 res->flags = 0; 3134 res->end = res->start - 1; 3135 } 3136 } 3137 #endif /* CONFIG_PCI_IOV */ 3138 3139 static void pnv_ioda_setup_pe_res(struct pnv_ioda_pe *pe, 3140 struct resource *res) 3141 { 3142 struct pnv_phb *phb = pe->phb; 3143 struct pci_bus_region region; 3144 int index; 3145 int64_t rc; 3146 3147 if (!res || !res->flags || res->start > res->end) 3148 return; 3149 3150 if (res->flags & IORESOURCE_IO) { 3151 region.start = res->start - phb->ioda.io_pci_base; 3152 region.end = res->end - phb->ioda.io_pci_base; 3153 index = region.start / phb->ioda.io_segsize; 3154 3155 while (index < phb->ioda.total_pe_num && 3156 region.start <= region.end) { 3157 phb->ioda.io_segmap[index] = pe->pe_number; 3158 rc = opal_pci_map_pe_mmio_window(phb->opal_id, 3159 pe->pe_number, OPAL_IO_WINDOW_TYPE, 0, index); 3160 if (rc != OPAL_SUCCESS) { 3161 pr_err("%s: Error %lld mapping IO segment#%d to PE#%x\n", 3162 __func__, rc, index, pe->pe_number); 3163 break; 3164 } 3165 3166 region.start += phb->ioda.io_segsize; 3167 index++; 3168 } 3169 } else if ((res->flags & IORESOURCE_MEM) && 3170 !pnv_pci_is_m64(phb, res)) { 3171 region.start = res->start - 3172 phb->hose->mem_offset[0] - 3173 phb->ioda.m32_pci_base; 3174 region.end = res->end - 3175 phb->hose->mem_offset[0] - 3176 phb->ioda.m32_pci_base; 3177 index = region.start / phb->ioda.m32_segsize; 3178 3179 while (index < phb->ioda.total_pe_num && 3180 region.start <= region.end) { 3181 phb->ioda.m32_segmap[index] = pe->pe_number; 3182 rc = opal_pci_map_pe_mmio_window(phb->opal_id, 3183 pe->pe_number, OPAL_M32_WINDOW_TYPE, 0, index); 3184 if (rc != OPAL_SUCCESS) { 3185 pr_err("%s: Error %lld mapping M32 segment#%d to PE#%x", 3186 __func__, rc, index, pe->pe_number); 3187 break; 3188 } 3189 3190 region.start += phb->ioda.m32_segsize; 3191 index++; 3192 } 3193 } 3194 } 3195 3196 /* 3197 * This function is supposed to be called on basis of PE from top 3198 * to bottom style. So the the I/O or MMIO segment assigned to 3199 * parent PE could be overridden by its child PEs if necessary. 3200 */ 3201 static void pnv_ioda_setup_pe_seg(struct pnv_ioda_pe *pe) 3202 { 3203 struct pci_dev *pdev; 3204 int i; 3205 3206 /* 3207 * NOTE: We only care PCI bus based PE for now. For PCI 3208 * device based PE, for example SRIOV sensitive VF should 3209 * be figured out later. 3210 */ 3211 BUG_ON(!(pe->flags & (PNV_IODA_PE_BUS | PNV_IODA_PE_BUS_ALL))); 3212 3213 list_for_each_entry(pdev, &pe->pbus->devices, bus_list) { 3214 for (i = 0; i <= PCI_ROM_RESOURCE; i++) 3215 pnv_ioda_setup_pe_res(pe, &pdev->resource[i]); 3216 3217 /* 3218 * If the PE contains all subordinate PCI buses, the 3219 * windows of the child bridges should be mapped to 3220 * the PE as well. 3221 */ 3222 if (!(pe->flags & PNV_IODA_PE_BUS_ALL) || !pci_is_bridge(pdev)) 3223 continue; 3224 for (i = 0; i < PCI_BRIDGE_RESOURCE_NUM; i++) 3225 pnv_ioda_setup_pe_res(pe, 3226 &pdev->resource[PCI_BRIDGE_RESOURCES + i]); 3227 } 3228 } 3229 3230 #ifdef CONFIG_DEBUG_FS 3231 static int pnv_pci_diag_data_set(void *data, u64 val) 3232 { 3233 struct pci_controller *hose; 3234 struct pnv_phb *phb; 3235 s64 ret; 3236 3237 if (val != 1ULL) 3238 return -EINVAL; 3239 3240 hose = (struct pci_controller *)data; 3241 if (!hose || !hose->private_data) 3242 return -ENODEV; 3243 3244 phb = hose->private_data; 3245 3246 /* Retrieve the diag data from firmware */ 3247 ret = opal_pci_get_phb_diag_data2(phb->opal_id, phb->diag_data, 3248 phb->diag_data_size); 3249 if (ret != OPAL_SUCCESS) 3250 return -EIO; 3251 3252 /* Print the diag data to the kernel log */ 3253 pnv_pci_dump_phb_diag_data(phb->hose, phb->diag_data); 3254 return 0; 3255 } 3256 3257 DEFINE_SIMPLE_ATTRIBUTE(pnv_pci_diag_data_fops, NULL, 3258 pnv_pci_diag_data_set, "%llu\n"); 3259 3260 #endif /* CONFIG_DEBUG_FS */ 3261 3262 static void pnv_pci_ioda_create_dbgfs(void) 3263 { 3264 #ifdef CONFIG_DEBUG_FS 3265 struct pci_controller *hose, *tmp; 3266 struct pnv_phb *phb; 3267 char name[16]; 3268 3269 list_for_each_entry_safe(hose, tmp, &hose_list, list_node) { 3270 phb = hose->private_data; 3271 3272 /* Notify initialization of PHB done */ 3273 phb->initialized = 1; 3274 3275 sprintf(name, "PCI%04x", hose->global_number); 3276 phb->dbgfs = debugfs_create_dir(name, powerpc_debugfs_root); 3277 if (!phb->dbgfs) { 3278 pr_warning("%s: Error on creating debugfs on PHB#%x\n", 3279 __func__, hose->global_number); 3280 continue; 3281 } 3282 3283 debugfs_create_file("dump_diag_regs", 0200, phb->dbgfs, hose, 3284 &pnv_pci_diag_data_fops); 3285 } 3286 #endif /* CONFIG_DEBUG_FS */ 3287 } 3288 3289 static void pnv_pci_ioda_fixup(void) 3290 { 3291 pnv_pci_ioda_setup_PEs(); 3292 pnv_pci_ioda_setup_iommu_api(); 3293 pnv_pci_ioda_create_dbgfs(); 3294 3295 #ifdef CONFIG_EEH 3296 eeh_init(); 3297 eeh_addr_cache_build(); 3298 #endif 3299 } 3300 3301 /* 3302 * Returns the alignment for I/O or memory windows for P2P 3303 * bridges. That actually depends on how PEs are segmented. 3304 * For now, we return I/O or M32 segment size for PE sensitive 3305 * P2P bridges. Otherwise, the default values (4KiB for I/O, 3306 * 1MiB for memory) will be returned. 3307 * 3308 * The current PCI bus might be put into one PE, which was 3309 * create against the parent PCI bridge. For that case, we 3310 * needn't enlarge the alignment so that we can save some 3311 * resources. 3312 */ 3313 static resource_size_t pnv_pci_window_alignment(struct pci_bus *bus, 3314 unsigned long type) 3315 { 3316 struct pci_dev *bridge; 3317 struct pci_controller *hose = pci_bus_to_host(bus); 3318 struct pnv_phb *phb = hose->private_data; 3319 int num_pci_bridges = 0; 3320 3321 bridge = bus->self; 3322 while (bridge) { 3323 if (pci_pcie_type(bridge) == PCI_EXP_TYPE_PCI_BRIDGE) { 3324 num_pci_bridges++; 3325 if (num_pci_bridges >= 2) 3326 return 1; 3327 } 3328 3329 bridge = bridge->bus->self; 3330 } 3331 3332 /* 3333 * We fall back to M32 if M64 isn't supported. We enforce the M64 3334 * alignment for any 64-bit resource, PCIe doesn't care and 3335 * bridges only do 64-bit prefetchable anyway. 3336 */ 3337 if (phb->ioda.m64_segsize && pnv_pci_is_m64_flags(type)) 3338 return phb->ioda.m64_segsize; 3339 if (type & IORESOURCE_MEM) 3340 return phb->ioda.m32_segsize; 3341 3342 return phb->ioda.io_segsize; 3343 } 3344 3345 /* 3346 * We are updating root port or the upstream port of the 3347 * bridge behind the root port with PHB's windows in order 3348 * to accommodate the changes on required resources during 3349 * PCI (slot) hotplug, which is connected to either root 3350 * port or the downstream ports of PCIe switch behind the 3351 * root port. 3352 */ 3353 static void pnv_pci_fixup_bridge_resources(struct pci_bus *bus, 3354 unsigned long type) 3355 { 3356 struct pci_controller *hose = pci_bus_to_host(bus); 3357 struct pnv_phb *phb = hose->private_data; 3358 struct pci_dev *bridge = bus->self; 3359 struct resource *r, *w; 3360 bool msi_region = false; 3361 int i; 3362 3363 /* Check if we need apply fixup to the bridge's windows */ 3364 if (!pci_is_root_bus(bridge->bus) && 3365 !pci_is_root_bus(bridge->bus->self->bus)) 3366 return; 3367 3368 /* Fixup the resources */ 3369 for (i = 0; i < PCI_BRIDGE_RESOURCE_NUM; i++) { 3370 r = &bridge->resource[PCI_BRIDGE_RESOURCES + i]; 3371 if (!r->flags || !r->parent) 3372 continue; 3373 3374 w = NULL; 3375 if (r->flags & type & IORESOURCE_IO) 3376 w = &hose->io_resource; 3377 else if (pnv_pci_is_m64(phb, r) && 3378 (type & IORESOURCE_PREFETCH) && 3379 phb->ioda.m64_segsize) 3380 w = &hose->mem_resources[1]; 3381 else if (r->flags & type & IORESOURCE_MEM) { 3382 w = &hose->mem_resources[0]; 3383 msi_region = true; 3384 } 3385 3386 r->start = w->start; 3387 r->end = w->end; 3388 3389 /* The 64KB 32-bits MSI region shouldn't be included in 3390 * the 32-bits bridge window. Otherwise, we can see strange 3391 * issues. One of them is EEH error observed on Garrison. 3392 * 3393 * Exclude top 1MB region which is the minimal alignment of 3394 * 32-bits bridge window. 3395 */ 3396 if (msi_region) { 3397 r->end += 0x10000; 3398 r->end -= 0x100000; 3399 } 3400 } 3401 } 3402 3403 static void pnv_pci_setup_bridge(struct pci_bus *bus, unsigned long type) 3404 { 3405 struct pci_controller *hose = pci_bus_to_host(bus); 3406 struct pnv_phb *phb = hose->private_data; 3407 struct pci_dev *bridge = bus->self; 3408 struct pnv_ioda_pe *pe; 3409 bool all = (pci_pcie_type(bridge) == PCI_EXP_TYPE_PCI_BRIDGE); 3410 3411 /* Extend bridge's windows if necessary */ 3412 pnv_pci_fixup_bridge_resources(bus, type); 3413 3414 /* The PE for root bus should be realized before any one else */ 3415 if (!phb->ioda.root_pe_populated) { 3416 pe = pnv_ioda_setup_bus_PE(phb->hose->bus, false); 3417 if (pe) { 3418 phb->ioda.root_pe_idx = pe->pe_number; 3419 phb->ioda.root_pe_populated = true; 3420 } 3421 } 3422 3423 /* Don't assign PE to PCI bus, which doesn't have subordinate devices */ 3424 if (list_empty(&bus->devices)) 3425 return; 3426 3427 /* Reserve PEs according to used M64 resources */ 3428 if (phb->reserve_m64_pe) 3429 phb->reserve_m64_pe(bus, NULL, all); 3430 3431 /* 3432 * Assign PE. We might run here because of partial hotplug. 3433 * For the case, we just pick up the existing PE and should 3434 * not allocate resources again. 3435 */ 3436 pe = pnv_ioda_setup_bus_PE(bus, all); 3437 if (!pe) 3438 return; 3439 3440 pnv_ioda_setup_pe_seg(pe); 3441 switch (phb->type) { 3442 case PNV_PHB_IODA1: 3443 pnv_pci_ioda1_setup_dma_pe(phb, pe); 3444 break; 3445 case PNV_PHB_IODA2: 3446 pnv_pci_ioda2_setup_dma_pe(phb, pe); 3447 break; 3448 default: 3449 pr_warn("%s: No DMA for PHB#%x (type %d)\n", 3450 __func__, phb->hose->global_number, phb->type); 3451 } 3452 } 3453 3454 static resource_size_t pnv_pci_default_alignment(void) 3455 { 3456 return PAGE_SIZE; 3457 } 3458 3459 #ifdef CONFIG_PCI_IOV 3460 static resource_size_t pnv_pci_iov_resource_alignment(struct pci_dev *pdev, 3461 int resno) 3462 { 3463 struct pci_controller *hose = pci_bus_to_host(pdev->bus); 3464 struct pnv_phb *phb = hose->private_data; 3465 struct pci_dn *pdn = pci_get_pdn(pdev); 3466 resource_size_t align; 3467 3468 /* 3469 * On PowerNV platform, IOV BAR is mapped by M64 BAR to enable the 3470 * SR-IOV. While from hardware perspective, the range mapped by M64 3471 * BAR should be size aligned. 3472 * 3473 * When IOV BAR is mapped with M64 BAR in Single PE mode, the extra 3474 * powernv-specific hardware restriction is gone. But if just use the 3475 * VF BAR size as the alignment, PF BAR / VF BAR may be allocated with 3476 * in one segment of M64 #15, which introduces the PE conflict between 3477 * PF and VF. Based on this, the minimum alignment of an IOV BAR is 3478 * m64_segsize. 3479 * 3480 * This function returns the total IOV BAR size if M64 BAR is in 3481 * Shared PE mode or just VF BAR size if not. 3482 * If the M64 BAR is in Single PE mode, return the VF BAR size or 3483 * M64 segment size if IOV BAR size is less. 3484 */ 3485 align = pci_iov_resource_size(pdev, resno); 3486 if (!pdn->vfs_expanded) 3487 return align; 3488 if (pdn->m64_single_mode) 3489 return max(align, (resource_size_t)phb->ioda.m64_segsize); 3490 3491 return pdn->vfs_expanded * align; 3492 } 3493 #endif /* CONFIG_PCI_IOV */ 3494 3495 /* Prevent enabling devices for which we couldn't properly 3496 * assign a PE 3497 */ 3498 bool pnv_pci_enable_device_hook(struct pci_dev *dev) 3499 { 3500 struct pci_controller *hose = pci_bus_to_host(dev->bus); 3501 struct pnv_phb *phb = hose->private_data; 3502 struct pci_dn *pdn; 3503 3504 /* The function is probably called while the PEs have 3505 * not be created yet. For example, resource reassignment 3506 * during PCI probe period. We just skip the check if 3507 * PEs isn't ready. 3508 */ 3509 if (!phb->initialized) 3510 return true; 3511 3512 pdn = pci_get_pdn(dev); 3513 if (!pdn || pdn->pe_number == IODA_INVALID_PE) 3514 return false; 3515 3516 return true; 3517 } 3518 3519 static long pnv_pci_ioda1_unset_window(struct iommu_table_group *table_group, 3520 int num) 3521 { 3522 struct pnv_ioda_pe *pe = container_of(table_group, 3523 struct pnv_ioda_pe, table_group); 3524 struct pnv_phb *phb = pe->phb; 3525 unsigned int idx; 3526 long rc; 3527 3528 pe_info(pe, "Removing DMA window #%d\n", num); 3529 for (idx = 0; idx < phb->ioda.dma32_count; idx++) { 3530 if (phb->ioda.dma32_segmap[idx] != pe->pe_number) 3531 continue; 3532 3533 rc = opal_pci_map_pe_dma_window(phb->opal_id, pe->pe_number, 3534 idx, 0, 0ul, 0ul, 0ul); 3535 if (rc != OPAL_SUCCESS) { 3536 pe_warn(pe, "Failure %ld unmapping DMA32 segment#%d\n", 3537 rc, idx); 3538 return rc; 3539 } 3540 3541 phb->ioda.dma32_segmap[idx] = IODA_INVALID_PE; 3542 } 3543 3544 pnv_pci_unlink_table_and_group(table_group->tables[num], table_group); 3545 return OPAL_SUCCESS; 3546 } 3547 3548 static void pnv_pci_ioda1_release_pe_dma(struct pnv_ioda_pe *pe) 3549 { 3550 unsigned int weight = pnv_pci_ioda_pe_dma_weight(pe); 3551 struct iommu_table *tbl = pe->table_group.tables[0]; 3552 int64_t rc; 3553 3554 if (!weight) 3555 return; 3556 3557 rc = pnv_pci_ioda1_unset_window(&pe->table_group, 0); 3558 if (rc != OPAL_SUCCESS) 3559 return; 3560 3561 pnv_pci_p7ioc_tce_invalidate(tbl, tbl->it_offset, tbl->it_size, false); 3562 if (pe->table_group.group) { 3563 iommu_group_put(pe->table_group.group); 3564 WARN_ON(pe->table_group.group); 3565 } 3566 3567 free_pages(tbl->it_base, get_order(tbl->it_size << 3)); 3568 iommu_tce_table_put(tbl); 3569 } 3570 3571 static void pnv_pci_ioda2_release_pe_dma(struct pnv_ioda_pe *pe) 3572 { 3573 struct iommu_table *tbl = pe->table_group.tables[0]; 3574 unsigned int weight = pnv_pci_ioda_pe_dma_weight(pe); 3575 #ifdef CONFIG_IOMMU_API 3576 int64_t rc; 3577 #endif 3578 3579 if (!weight) 3580 return; 3581 3582 #ifdef CONFIG_IOMMU_API 3583 rc = pnv_pci_ioda2_unset_window(&pe->table_group, 0); 3584 if (rc) 3585 pe_warn(pe, "OPAL error %ld release DMA window\n", rc); 3586 #endif 3587 3588 pnv_pci_ioda2_set_bypass(pe, false); 3589 if (pe->table_group.group) { 3590 iommu_group_put(pe->table_group.group); 3591 WARN_ON(pe->table_group.group); 3592 } 3593 3594 pnv_pci_ioda2_table_free_pages(tbl); 3595 iommu_tce_table_put(tbl); 3596 } 3597 3598 static void pnv_ioda_free_pe_seg(struct pnv_ioda_pe *pe, 3599 unsigned short win, 3600 unsigned int *map) 3601 { 3602 struct pnv_phb *phb = pe->phb; 3603 int idx; 3604 int64_t rc; 3605 3606 for (idx = 0; idx < phb->ioda.total_pe_num; idx++) { 3607 if (map[idx] != pe->pe_number) 3608 continue; 3609 3610 if (win == OPAL_M64_WINDOW_TYPE) 3611 rc = opal_pci_map_pe_mmio_window(phb->opal_id, 3612 phb->ioda.reserved_pe_idx, win, 3613 idx / PNV_IODA1_M64_SEGS, 3614 idx % PNV_IODA1_M64_SEGS); 3615 else 3616 rc = opal_pci_map_pe_mmio_window(phb->opal_id, 3617 phb->ioda.reserved_pe_idx, win, 0, idx); 3618 3619 if (rc != OPAL_SUCCESS) 3620 pe_warn(pe, "Error %ld unmapping (%d) segment#%d\n", 3621 rc, win, idx); 3622 3623 map[idx] = IODA_INVALID_PE; 3624 } 3625 } 3626 3627 static void pnv_ioda_release_pe_seg(struct pnv_ioda_pe *pe) 3628 { 3629 struct pnv_phb *phb = pe->phb; 3630 3631 if (phb->type == PNV_PHB_IODA1) { 3632 pnv_ioda_free_pe_seg(pe, OPAL_IO_WINDOW_TYPE, 3633 phb->ioda.io_segmap); 3634 pnv_ioda_free_pe_seg(pe, OPAL_M32_WINDOW_TYPE, 3635 phb->ioda.m32_segmap); 3636 pnv_ioda_free_pe_seg(pe, OPAL_M64_WINDOW_TYPE, 3637 phb->ioda.m64_segmap); 3638 } else if (phb->type == PNV_PHB_IODA2) { 3639 pnv_ioda_free_pe_seg(pe, OPAL_M32_WINDOW_TYPE, 3640 phb->ioda.m32_segmap); 3641 } 3642 } 3643 3644 static void pnv_ioda_release_pe(struct pnv_ioda_pe *pe) 3645 { 3646 struct pnv_phb *phb = pe->phb; 3647 struct pnv_ioda_pe *slave, *tmp; 3648 3649 list_del(&pe->list); 3650 switch (phb->type) { 3651 case PNV_PHB_IODA1: 3652 pnv_pci_ioda1_release_pe_dma(pe); 3653 break; 3654 case PNV_PHB_IODA2: 3655 pnv_pci_ioda2_release_pe_dma(pe); 3656 break; 3657 default: 3658 WARN_ON(1); 3659 } 3660 3661 pnv_ioda_release_pe_seg(pe); 3662 pnv_ioda_deconfigure_pe(pe->phb, pe); 3663 3664 /* Release slave PEs in the compound PE */ 3665 if (pe->flags & PNV_IODA_PE_MASTER) { 3666 list_for_each_entry_safe(slave, tmp, &pe->slaves, list) { 3667 list_del(&slave->list); 3668 pnv_ioda_free_pe(slave); 3669 } 3670 } 3671 3672 /* 3673 * The PE for root bus can be removed because of hotplug in EEH 3674 * recovery for fenced PHB error. We need to mark the PE dead so 3675 * that it can be populated again in PCI hot add path. The PE 3676 * shouldn't be destroyed as it's the global reserved resource. 3677 */ 3678 if (phb->ioda.root_pe_populated && 3679 phb->ioda.root_pe_idx == pe->pe_number) 3680 phb->ioda.root_pe_populated = false; 3681 else 3682 pnv_ioda_free_pe(pe); 3683 } 3684 3685 static void pnv_pci_release_device(struct pci_dev *pdev) 3686 { 3687 struct pci_controller *hose = pci_bus_to_host(pdev->bus); 3688 struct pnv_phb *phb = hose->private_data; 3689 struct pci_dn *pdn = pci_get_pdn(pdev); 3690 struct pnv_ioda_pe *pe; 3691 3692 if (pdev->is_virtfn) 3693 return; 3694 3695 if (!pdn || pdn->pe_number == IODA_INVALID_PE) 3696 return; 3697 3698 /* 3699 * PCI hotplug can happen as part of EEH error recovery. The @pdn 3700 * isn't removed and added afterwards in this scenario. We should 3701 * set the PE number in @pdn to an invalid one. Otherwise, the PE's 3702 * device count is decreased on removing devices while failing to 3703 * be increased on adding devices. It leads to unbalanced PE's device 3704 * count and eventually make normal PCI hotplug path broken. 3705 */ 3706 pe = &phb->ioda.pe_array[pdn->pe_number]; 3707 pdn->pe_number = IODA_INVALID_PE; 3708 3709 WARN_ON(--pe->device_count < 0); 3710 if (pe->device_count == 0) 3711 pnv_ioda_release_pe(pe); 3712 } 3713 3714 static void pnv_pci_ioda_shutdown(struct pci_controller *hose) 3715 { 3716 struct pnv_phb *phb = hose->private_data; 3717 3718 opal_pci_reset(phb->opal_id, OPAL_RESET_PCI_IODA_TABLE, 3719 OPAL_ASSERT_RESET); 3720 } 3721 3722 static const struct pci_controller_ops pnv_pci_ioda_controller_ops = { 3723 .dma_dev_setup = pnv_pci_dma_dev_setup, 3724 .dma_bus_setup = pnv_pci_dma_bus_setup, 3725 #ifdef CONFIG_PCI_MSI 3726 .setup_msi_irqs = pnv_setup_msi_irqs, 3727 .teardown_msi_irqs = pnv_teardown_msi_irqs, 3728 #endif 3729 .enable_device_hook = pnv_pci_enable_device_hook, 3730 .release_device = pnv_pci_release_device, 3731 .window_alignment = pnv_pci_window_alignment, 3732 .setup_bridge = pnv_pci_setup_bridge, 3733 .reset_secondary_bus = pnv_pci_reset_secondary_bus, 3734 .dma_set_mask = pnv_pci_ioda_dma_set_mask, 3735 .dma_get_required_mask = pnv_pci_ioda_dma_get_required_mask, 3736 .shutdown = pnv_pci_ioda_shutdown, 3737 }; 3738 3739 static int pnv_npu_dma_set_mask(struct pci_dev *npdev, u64 dma_mask) 3740 { 3741 dev_err_once(&npdev->dev, 3742 "%s operation unsupported for NVLink devices\n", 3743 __func__); 3744 return -EPERM; 3745 } 3746 3747 static const struct pci_controller_ops pnv_npu_ioda_controller_ops = { 3748 .dma_dev_setup = pnv_pci_dma_dev_setup, 3749 #ifdef CONFIG_PCI_MSI 3750 .setup_msi_irqs = pnv_setup_msi_irqs, 3751 .teardown_msi_irqs = pnv_teardown_msi_irqs, 3752 #endif 3753 .enable_device_hook = pnv_pci_enable_device_hook, 3754 .window_alignment = pnv_pci_window_alignment, 3755 .reset_secondary_bus = pnv_pci_reset_secondary_bus, 3756 .dma_set_mask = pnv_npu_dma_set_mask, 3757 .shutdown = pnv_pci_ioda_shutdown, 3758 }; 3759 3760 #ifdef CONFIG_CXL_BASE 3761 const struct pci_controller_ops pnv_cxl_cx4_ioda_controller_ops = { 3762 .dma_dev_setup = pnv_pci_dma_dev_setup, 3763 .dma_bus_setup = pnv_pci_dma_bus_setup, 3764 #ifdef CONFIG_PCI_MSI 3765 .setup_msi_irqs = pnv_cxl_cx4_setup_msi_irqs, 3766 .teardown_msi_irqs = pnv_cxl_cx4_teardown_msi_irqs, 3767 #endif 3768 .enable_device_hook = pnv_cxl_enable_device_hook, 3769 .disable_device = pnv_cxl_disable_device, 3770 .release_device = pnv_pci_release_device, 3771 .window_alignment = pnv_pci_window_alignment, 3772 .setup_bridge = pnv_pci_setup_bridge, 3773 .reset_secondary_bus = pnv_pci_reset_secondary_bus, 3774 .dma_set_mask = pnv_pci_ioda_dma_set_mask, 3775 .dma_get_required_mask = pnv_pci_ioda_dma_get_required_mask, 3776 .shutdown = pnv_pci_ioda_shutdown, 3777 }; 3778 #endif 3779 3780 static void __init pnv_pci_init_ioda_phb(struct device_node *np, 3781 u64 hub_id, int ioda_type) 3782 { 3783 struct pci_controller *hose; 3784 struct pnv_phb *phb; 3785 unsigned long size, m64map_off, m32map_off, pemap_off; 3786 unsigned long iomap_off = 0, dma32map_off = 0; 3787 struct resource r; 3788 const __be64 *prop64; 3789 const __be32 *prop32; 3790 int len; 3791 unsigned int segno; 3792 u64 phb_id; 3793 void *aux; 3794 long rc; 3795 3796 if (!of_device_is_available(np)) 3797 return; 3798 3799 pr_info("Initializing %s PHB (%pOF)\n", pnv_phb_names[ioda_type], np); 3800 3801 prop64 = of_get_property(np, "ibm,opal-phbid", NULL); 3802 if (!prop64) { 3803 pr_err(" Missing \"ibm,opal-phbid\" property !\n"); 3804 return; 3805 } 3806 phb_id = be64_to_cpup(prop64); 3807 pr_debug(" PHB-ID : 0x%016llx\n", phb_id); 3808 3809 phb = memblock_virt_alloc(sizeof(struct pnv_phb), 0); 3810 3811 /* Allocate PCI controller */ 3812 phb->hose = hose = pcibios_alloc_controller(np); 3813 if (!phb->hose) { 3814 pr_err(" Can't allocate PCI controller for %pOF\n", 3815 np); 3816 memblock_free(__pa(phb), sizeof(struct pnv_phb)); 3817 return; 3818 } 3819 3820 spin_lock_init(&phb->lock); 3821 prop32 = of_get_property(np, "bus-range", &len); 3822 if (prop32 && len == 8) { 3823 hose->first_busno = be32_to_cpu(prop32[0]); 3824 hose->last_busno = be32_to_cpu(prop32[1]); 3825 } else { 3826 pr_warn(" Broken <bus-range> on %pOF\n", np); 3827 hose->first_busno = 0; 3828 hose->last_busno = 0xff; 3829 } 3830 hose->private_data = phb; 3831 phb->hub_id = hub_id; 3832 phb->opal_id = phb_id; 3833 phb->type = ioda_type; 3834 mutex_init(&phb->ioda.pe_alloc_mutex); 3835 3836 /* Detect specific models for error handling */ 3837 if (of_device_is_compatible(np, "ibm,p7ioc-pciex")) 3838 phb->model = PNV_PHB_MODEL_P7IOC; 3839 else if (of_device_is_compatible(np, "ibm,power8-pciex")) 3840 phb->model = PNV_PHB_MODEL_PHB3; 3841 else if (of_device_is_compatible(np, "ibm,power8-npu-pciex")) 3842 phb->model = PNV_PHB_MODEL_NPU; 3843 else if (of_device_is_compatible(np, "ibm,power9-npu-pciex")) 3844 phb->model = PNV_PHB_MODEL_NPU2; 3845 else 3846 phb->model = PNV_PHB_MODEL_UNKNOWN; 3847 3848 /* Initialize diagnostic data buffer */ 3849 prop32 = of_get_property(np, "ibm,phb-diag-data-size", NULL); 3850 if (prop32) 3851 phb->diag_data_size = be32_to_cpup(prop32); 3852 else 3853 phb->diag_data_size = PNV_PCI_DIAG_BUF_SIZE; 3854 3855 phb->diag_data = memblock_virt_alloc(phb->diag_data_size, 0); 3856 3857 /* Parse 32-bit and IO ranges (if any) */ 3858 pci_process_bridge_OF_ranges(hose, np, !hose->global_number); 3859 3860 /* Get registers */ 3861 if (!of_address_to_resource(np, 0, &r)) { 3862 phb->regs_phys = r.start; 3863 phb->regs = ioremap(r.start, resource_size(&r)); 3864 if (phb->regs == NULL) 3865 pr_err(" Failed to map registers !\n"); 3866 } 3867 3868 /* Initialize more IODA stuff */ 3869 phb->ioda.total_pe_num = 1; 3870 prop32 = of_get_property(np, "ibm,opal-num-pes", NULL); 3871 if (prop32) 3872 phb->ioda.total_pe_num = be32_to_cpup(prop32); 3873 prop32 = of_get_property(np, "ibm,opal-reserved-pe", NULL); 3874 if (prop32) 3875 phb->ioda.reserved_pe_idx = be32_to_cpup(prop32); 3876 3877 /* Invalidate RID to PE# mapping */ 3878 for (segno = 0; segno < ARRAY_SIZE(phb->ioda.pe_rmap); segno++) 3879 phb->ioda.pe_rmap[segno] = IODA_INVALID_PE; 3880 3881 /* Parse 64-bit MMIO range */ 3882 pnv_ioda_parse_m64_window(phb); 3883 3884 phb->ioda.m32_size = resource_size(&hose->mem_resources[0]); 3885 /* FW Has already off top 64k of M32 space (MSI space) */ 3886 phb->ioda.m32_size += 0x10000; 3887 3888 phb->ioda.m32_segsize = phb->ioda.m32_size / phb->ioda.total_pe_num; 3889 phb->ioda.m32_pci_base = hose->mem_resources[0].start - hose->mem_offset[0]; 3890 phb->ioda.io_size = hose->pci_io_size; 3891 phb->ioda.io_segsize = phb->ioda.io_size / phb->ioda.total_pe_num; 3892 phb->ioda.io_pci_base = 0; /* XXX calculate this ? */ 3893 3894 /* Calculate how many 32-bit TCE segments we have */ 3895 phb->ioda.dma32_count = phb->ioda.m32_pci_base / 3896 PNV_IODA1_DMA32_SEGSIZE; 3897 3898 /* Allocate aux data & arrays. We don't have IO ports on PHB3 */ 3899 size = _ALIGN_UP(max_t(unsigned, phb->ioda.total_pe_num, 8) / 8, 3900 sizeof(unsigned long)); 3901 m64map_off = size; 3902 size += phb->ioda.total_pe_num * sizeof(phb->ioda.m64_segmap[0]); 3903 m32map_off = size; 3904 size += phb->ioda.total_pe_num * sizeof(phb->ioda.m32_segmap[0]); 3905 if (phb->type == PNV_PHB_IODA1) { 3906 iomap_off = size; 3907 size += phb->ioda.total_pe_num * sizeof(phb->ioda.io_segmap[0]); 3908 dma32map_off = size; 3909 size += phb->ioda.dma32_count * 3910 sizeof(phb->ioda.dma32_segmap[0]); 3911 } 3912 pemap_off = size; 3913 size += phb->ioda.total_pe_num * sizeof(struct pnv_ioda_pe); 3914 aux = memblock_virt_alloc(size, 0); 3915 phb->ioda.pe_alloc = aux; 3916 phb->ioda.m64_segmap = aux + m64map_off; 3917 phb->ioda.m32_segmap = aux + m32map_off; 3918 for (segno = 0; segno < phb->ioda.total_pe_num; segno++) { 3919 phb->ioda.m64_segmap[segno] = IODA_INVALID_PE; 3920 phb->ioda.m32_segmap[segno] = IODA_INVALID_PE; 3921 } 3922 if (phb->type == PNV_PHB_IODA1) { 3923 phb->ioda.io_segmap = aux + iomap_off; 3924 for (segno = 0; segno < phb->ioda.total_pe_num; segno++) 3925 phb->ioda.io_segmap[segno] = IODA_INVALID_PE; 3926 3927 phb->ioda.dma32_segmap = aux + dma32map_off; 3928 for (segno = 0; segno < phb->ioda.dma32_count; segno++) 3929 phb->ioda.dma32_segmap[segno] = IODA_INVALID_PE; 3930 } 3931 phb->ioda.pe_array = aux + pemap_off; 3932 3933 /* 3934 * Choose PE number for root bus, which shouldn't have 3935 * M64 resources consumed by its child devices. To pick 3936 * the PE number adjacent to the reserved one if possible. 3937 */ 3938 pnv_ioda_reserve_pe(phb, phb->ioda.reserved_pe_idx); 3939 if (phb->ioda.reserved_pe_idx == 0) { 3940 phb->ioda.root_pe_idx = 1; 3941 pnv_ioda_reserve_pe(phb, phb->ioda.root_pe_idx); 3942 } else if (phb->ioda.reserved_pe_idx == (phb->ioda.total_pe_num - 1)) { 3943 phb->ioda.root_pe_idx = phb->ioda.reserved_pe_idx - 1; 3944 pnv_ioda_reserve_pe(phb, phb->ioda.root_pe_idx); 3945 } else { 3946 phb->ioda.root_pe_idx = IODA_INVALID_PE; 3947 } 3948 3949 INIT_LIST_HEAD(&phb->ioda.pe_list); 3950 mutex_init(&phb->ioda.pe_list_mutex); 3951 3952 /* Calculate how many 32-bit TCE segments we have */ 3953 phb->ioda.dma32_count = phb->ioda.m32_pci_base / 3954 PNV_IODA1_DMA32_SEGSIZE; 3955 3956 #if 0 /* We should really do that ... */ 3957 rc = opal_pci_set_phb_mem_window(opal->phb_id, 3958 window_type, 3959 window_num, 3960 starting_real_address, 3961 starting_pci_address, 3962 segment_size); 3963 #endif 3964 3965 pr_info(" %03d (%03d) PE's M32: 0x%x [segment=0x%x]\n", 3966 phb->ioda.total_pe_num, phb->ioda.reserved_pe_idx, 3967 phb->ioda.m32_size, phb->ioda.m32_segsize); 3968 if (phb->ioda.m64_size) 3969 pr_info(" M64: 0x%lx [segment=0x%lx]\n", 3970 phb->ioda.m64_size, phb->ioda.m64_segsize); 3971 if (phb->ioda.io_size) 3972 pr_info(" IO: 0x%x [segment=0x%x]\n", 3973 phb->ioda.io_size, phb->ioda.io_segsize); 3974 3975 3976 phb->hose->ops = &pnv_pci_ops; 3977 phb->get_pe_state = pnv_ioda_get_pe_state; 3978 phb->freeze_pe = pnv_ioda_freeze_pe; 3979 phb->unfreeze_pe = pnv_ioda_unfreeze_pe; 3980 3981 /* Setup MSI support */ 3982 pnv_pci_init_ioda_msis(phb); 3983 3984 /* 3985 * We pass the PCI probe flag PCI_REASSIGN_ALL_RSRC here 3986 * to let the PCI core do resource assignment. It's supposed 3987 * that the PCI core will do correct I/O and MMIO alignment 3988 * for the P2P bridge bars so that each PCI bus (excluding 3989 * the child P2P bridges) can form individual PE. 3990 */ 3991 ppc_md.pcibios_fixup = pnv_pci_ioda_fixup; 3992 3993 if (phb->type == PNV_PHB_NPU) { 3994 hose->controller_ops = pnv_npu_ioda_controller_ops; 3995 } else { 3996 phb->dma_dev_setup = pnv_pci_ioda_dma_dev_setup; 3997 hose->controller_ops = pnv_pci_ioda_controller_ops; 3998 } 3999 4000 ppc_md.pcibios_default_alignment = pnv_pci_default_alignment; 4001 4002 #ifdef CONFIG_PCI_IOV 4003 ppc_md.pcibios_fixup_sriov = pnv_pci_ioda_fixup_iov_resources; 4004 ppc_md.pcibios_iov_resource_alignment = pnv_pci_iov_resource_alignment; 4005 #endif 4006 4007 pci_add_flags(PCI_REASSIGN_ALL_RSRC); 4008 4009 /* Reset IODA tables to a clean state */ 4010 rc = opal_pci_reset(phb_id, OPAL_RESET_PCI_IODA_TABLE, OPAL_ASSERT_RESET); 4011 if (rc) 4012 pr_warning(" OPAL Error %ld performing IODA table reset !\n", rc); 4013 4014 /* 4015 * If we're running in kdump kernel, the previous kernel never 4016 * shutdown PCI devices correctly. We already got IODA table 4017 * cleaned out. So we have to issue PHB reset to stop all PCI 4018 * transactions from previous kernel. 4019 */ 4020 if (is_kdump_kernel()) { 4021 pr_info(" Issue PHB reset ...\n"); 4022 pnv_eeh_phb_reset(hose, EEH_RESET_FUNDAMENTAL); 4023 pnv_eeh_phb_reset(hose, EEH_RESET_DEACTIVATE); 4024 } 4025 4026 /* Remove M64 resource if we can't configure it successfully */ 4027 if (!phb->init_m64 || phb->init_m64(phb)) 4028 hose->mem_resources[1].flags = 0; 4029 } 4030 4031 void __init pnv_pci_init_ioda2_phb(struct device_node *np) 4032 { 4033 pnv_pci_init_ioda_phb(np, 0, PNV_PHB_IODA2); 4034 } 4035 4036 void __init pnv_pci_init_npu_phb(struct device_node *np) 4037 { 4038 pnv_pci_init_ioda_phb(np, 0, PNV_PHB_NPU); 4039 } 4040 4041 void __init pnv_pci_init_ioda_hub(struct device_node *np) 4042 { 4043 struct device_node *phbn; 4044 const __be64 *prop64; 4045 u64 hub_id; 4046 4047 pr_info("Probing IODA IO-Hub %pOF\n", np); 4048 4049 prop64 = of_get_property(np, "ibm,opal-hubid", NULL); 4050 if (!prop64) { 4051 pr_err(" Missing \"ibm,opal-hubid\" property !\n"); 4052 return; 4053 } 4054 hub_id = be64_to_cpup(prop64); 4055 pr_devel(" HUB-ID : 0x%016llx\n", hub_id); 4056 4057 /* Count child PHBs */ 4058 for_each_child_of_node(np, phbn) { 4059 /* Look for IODA1 PHBs */ 4060 if (of_device_is_compatible(phbn, "ibm,ioda-phb")) 4061 pnv_pci_init_ioda_phb(phbn, hub_id, PNV_PHB_IODA1); 4062 } 4063 } 4064