1 /* 2 * Support PCI/PCIe on PowerNV platforms 3 * 4 * Copyright 2011 Benjamin Herrenschmidt, IBM Corp. 5 * 6 * This program is free software; you can redistribute it and/or 7 * modify it under the terms of the GNU General Public License 8 * as published by the Free Software Foundation; either version 9 * 2 of the License, or (at your option) any later version. 10 */ 11 12 #undef DEBUG 13 14 #include <linux/kernel.h> 15 #include <linux/pci.h> 16 #include <linux/crash_dump.h> 17 #include <linux/debugfs.h> 18 #include <linux/delay.h> 19 #include <linux/string.h> 20 #include <linux/init.h> 21 #include <linux/bootmem.h> 22 #include <linux/irq.h> 23 #include <linux/io.h> 24 #include <linux/msi.h> 25 #include <linux/memblock.h> 26 #include <linux/iommu.h> 27 #include <linux/rculist.h> 28 #include <linux/sizes.h> 29 30 #include <asm/sections.h> 31 #include <asm/io.h> 32 #include <asm/prom.h> 33 #include <asm/pci-bridge.h> 34 #include <asm/machdep.h> 35 #include <asm/msi_bitmap.h> 36 #include <asm/ppc-pci.h> 37 #include <asm/opal.h> 38 #include <asm/iommu.h> 39 #include <asm/tce.h> 40 #include <asm/xics.h> 41 #include <asm/debug.h> 42 #include <asm/firmware.h> 43 #include <asm/pnv-pci.h> 44 #include <asm/mmzone.h> 45 46 #include <misc/cxl-base.h> 47 48 #include "powernv.h" 49 #include "pci.h" 50 51 /* 256M DMA window, 4K TCE pages, 8 bytes TCE */ 52 #define TCE32_TABLE_SIZE ((0x10000000 / 0x1000) * 8) 53 54 #define POWERNV_IOMMU_DEFAULT_LEVELS 1 55 #define POWERNV_IOMMU_MAX_LEVELS 5 56 57 static void pnv_pci_ioda2_table_free_pages(struct iommu_table *tbl); 58 59 static void pe_level_printk(const struct pnv_ioda_pe *pe, const char *level, 60 const char *fmt, ...) 61 { 62 struct va_format vaf; 63 va_list args; 64 char pfix[32]; 65 66 va_start(args, fmt); 67 68 vaf.fmt = fmt; 69 vaf.va = &args; 70 71 if (pe->flags & PNV_IODA_PE_DEV) 72 strlcpy(pfix, dev_name(&pe->pdev->dev), sizeof(pfix)); 73 else if (pe->flags & (PNV_IODA_PE_BUS | PNV_IODA_PE_BUS_ALL)) 74 sprintf(pfix, "%04x:%02x ", 75 pci_domain_nr(pe->pbus), pe->pbus->number); 76 #ifdef CONFIG_PCI_IOV 77 else if (pe->flags & PNV_IODA_PE_VF) 78 sprintf(pfix, "%04x:%02x:%2x.%d", 79 pci_domain_nr(pe->parent_dev->bus), 80 (pe->rid & 0xff00) >> 8, 81 PCI_SLOT(pe->rid), PCI_FUNC(pe->rid)); 82 #endif /* CONFIG_PCI_IOV*/ 83 84 printk("%spci %s: [PE# %.3d] %pV", 85 level, pfix, pe->pe_number, &vaf); 86 87 va_end(args); 88 } 89 90 #define pe_err(pe, fmt, ...) \ 91 pe_level_printk(pe, KERN_ERR, fmt, ##__VA_ARGS__) 92 #define pe_warn(pe, fmt, ...) \ 93 pe_level_printk(pe, KERN_WARNING, fmt, ##__VA_ARGS__) 94 #define pe_info(pe, fmt, ...) \ 95 pe_level_printk(pe, KERN_INFO, fmt, ##__VA_ARGS__) 96 97 static bool pnv_iommu_bypass_disabled __read_mostly; 98 99 static int __init iommu_setup(char *str) 100 { 101 if (!str) 102 return -EINVAL; 103 104 while (*str) { 105 if (!strncmp(str, "nobypass", 8)) { 106 pnv_iommu_bypass_disabled = true; 107 pr_info("PowerNV: IOMMU bypass window disabled.\n"); 108 break; 109 } 110 str += strcspn(str, ","); 111 if (*str == ',') 112 str++; 113 } 114 115 return 0; 116 } 117 early_param("iommu", iommu_setup); 118 119 /* 120 * stdcix is only supposed to be used in hypervisor real mode as per 121 * the architecture spec 122 */ 123 static inline void __raw_rm_writeq(u64 val, volatile void __iomem *paddr) 124 { 125 __asm__ __volatile__("stdcix %0,0,%1" 126 : : "r" (val), "r" (paddr) : "memory"); 127 } 128 129 static inline bool pnv_pci_is_mem_pref_64(unsigned long flags) 130 { 131 return ((flags & (IORESOURCE_MEM_64 | IORESOURCE_PREFETCH)) == 132 (IORESOURCE_MEM_64 | IORESOURCE_PREFETCH)); 133 } 134 135 static void pnv_ioda_reserve_pe(struct pnv_phb *phb, int pe_no) 136 { 137 if (!(pe_no >= 0 && pe_no < phb->ioda.total_pe)) { 138 pr_warn("%s: Invalid PE %d on PHB#%x\n", 139 __func__, pe_no, phb->hose->global_number); 140 return; 141 } 142 143 if (test_and_set_bit(pe_no, phb->ioda.pe_alloc)) 144 pr_debug("%s: PE %d was reserved on PHB#%x\n", 145 __func__, pe_no, phb->hose->global_number); 146 147 phb->ioda.pe_array[pe_no].phb = phb; 148 phb->ioda.pe_array[pe_no].pe_number = pe_no; 149 } 150 151 static int pnv_ioda_alloc_pe(struct pnv_phb *phb) 152 { 153 unsigned long pe; 154 155 do { 156 pe = find_next_zero_bit(phb->ioda.pe_alloc, 157 phb->ioda.total_pe, 0); 158 if (pe >= phb->ioda.total_pe) 159 return IODA_INVALID_PE; 160 } while(test_and_set_bit(pe, phb->ioda.pe_alloc)); 161 162 phb->ioda.pe_array[pe].phb = phb; 163 phb->ioda.pe_array[pe].pe_number = pe; 164 return pe; 165 } 166 167 static void pnv_ioda_free_pe(struct pnv_phb *phb, int pe) 168 { 169 WARN_ON(phb->ioda.pe_array[pe].pdev); 170 171 memset(&phb->ioda.pe_array[pe], 0, sizeof(struct pnv_ioda_pe)); 172 clear_bit(pe, phb->ioda.pe_alloc); 173 } 174 175 /* The default M64 BAR is shared by all PEs */ 176 static int pnv_ioda2_init_m64(struct pnv_phb *phb) 177 { 178 const char *desc; 179 struct resource *r; 180 s64 rc; 181 182 /* Configure the default M64 BAR */ 183 rc = opal_pci_set_phb_mem_window(phb->opal_id, 184 OPAL_M64_WINDOW_TYPE, 185 phb->ioda.m64_bar_idx, 186 phb->ioda.m64_base, 187 0, /* unused */ 188 phb->ioda.m64_size); 189 if (rc != OPAL_SUCCESS) { 190 desc = "configuring"; 191 goto fail; 192 } 193 194 /* Enable the default M64 BAR */ 195 rc = opal_pci_phb_mmio_enable(phb->opal_id, 196 OPAL_M64_WINDOW_TYPE, 197 phb->ioda.m64_bar_idx, 198 OPAL_ENABLE_M64_SPLIT); 199 if (rc != OPAL_SUCCESS) { 200 desc = "enabling"; 201 goto fail; 202 } 203 204 /* Mark the M64 BAR assigned */ 205 set_bit(phb->ioda.m64_bar_idx, &phb->ioda.m64_bar_alloc); 206 207 /* 208 * Strip off the segment used by the reserved PE, which is 209 * expected to be 0 or last one of PE capabicity. 210 */ 211 r = &phb->hose->mem_resources[1]; 212 if (phb->ioda.reserved_pe == 0) 213 r->start += phb->ioda.m64_segsize; 214 else if (phb->ioda.reserved_pe == (phb->ioda.total_pe - 1)) 215 r->end -= phb->ioda.m64_segsize; 216 else 217 pr_warn(" Cannot strip M64 segment for reserved PE#%d\n", 218 phb->ioda.reserved_pe); 219 220 return 0; 221 222 fail: 223 pr_warn(" Failure %lld %s M64 BAR#%d\n", 224 rc, desc, phb->ioda.m64_bar_idx); 225 opal_pci_phb_mmio_enable(phb->opal_id, 226 OPAL_M64_WINDOW_TYPE, 227 phb->ioda.m64_bar_idx, 228 OPAL_DISABLE_M64); 229 return -EIO; 230 } 231 232 static void pnv_ioda2_reserve_dev_m64_pe(struct pci_dev *pdev, 233 unsigned long *pe_bitmap) 234 { 235 struct pci_controller *hose = pci_bus_to_host(pdev->bus); 236 struct pnv_phb *phb = hose->private_data; 237 struct resource *r; 238 resource_size_t base, sgsz, start, end; 239 int segno, i; 240 241 base = phb->ioda.m64_base; 242 sgsz = phb->ioda.m64_segsize; 243 for (i = 0; i <= PCI_ROM_RESOURCE; i++) { 244 r = &pdev->resource[i]; 245 if (!r->parent || !pnv_pci_is_mem_pref_64(r->flags)) 246 continue; 247 248 start = _ALIGN_DOWN(r->start - base, sgsz); 249 end = _ALIGN_UP(r->end - base, sgsz); 250 for (segno = start / sgsz; segno < end / sgsz; segno++) { 251 if (pe_bitmap) 252 set_bit(segno, pe_bitmap); 253 else 254 pnv_ioda_reserve_pe(phb, segno); 255 } 256 } 257 } 258 259 static void pnv_ioda2_reserve_m64_pe(struct pci_bus *bus, 260 unsigned long *pe_bitmap, 261 bool all) 262 { 263 struct pci_dev *pdev; 264 265 list_for_each_entry(pdev, &bus->devices, bus_list) { 266 pnv_ioda2_reserve_dev_m64_pe(pdev, pe_bitmap); 267 268 if (all && pdev->subordinate) 269 pnv_ioda2_reserve_m64_pe(pdev->subordinate, 270 pe_bitmap, all); 271 } 272 } 273 274 static int pnv_ioda2_pick_m64_pe(struct pnv_phb *phb, 275 struct pci_bus *bus, bool all) 276 { 277 resource_size_t segsz = phb->ioda.m64_segsize; 278 struct pci_dev *pdev; 279 struct resource *r; 280 struct pnv_ioda_pe *master_pe, *pe; 281 unsigned long size, *pe_alloc; 282 bool found; 283 int start, i, j; 284 285 /* Root bus shouldn't use M64 */ 286 if (pci_is_root_bus(bus)) 287 return IODA_INVALID_PE; 288 289 /* We support only one M64 window on each bus */ 290 found = false; 291 pci_bus_for_each_resource(bus, r, i) { 292 if (r && r->parent && 293 pnv_pci_is_mem_pref_64(r->flags)) { 294 found = true; 295 break; 296 } 297 } 298 299 /* No M64 window found ? */ 300 if (!found) 301 return IODA_INVALID_PE; 302 303 /* Allocate bitmap */ 304 size = _ALIGN_UP(phb->ioda.total_pe / 8, sizeof(unsigned long)); 305 pe_alloc = kzalloc(size, GFP_KERNEL); 306 if (!pe_alloc) { 307 pr_warn("%s: Out of memory !\n", 308 __func__); 309 return IODA_INVALID_PE; 310 } 311 312 /* 313 * Figure out reserved PE numbers by the PE 314 * the its child PEs. 315 */ 316 start = (r->start - phb->ioda.m64_base) / segsz; 317 for (i = 0; i < resource_size(r) / segsz; i++) 318 set_bit(start + i, pe_alloc); 319 320 if (all) 321 goto done; 322 323 /* 324 * If the PE doesn't cover all subordinate buses, 325 * we need subtract from reserved PEs for children. 326 */ 327 list_for_each_entry(pdev, &bus->devices, bus_list) { 328 if (!pdev->subordinate) 329 continue; 330 331 pci_bus_for_each_resource(pdev->subordinate, r, i) { 332 if (!r || !r->parent || 333 !pnv_pci_is_mem_pref_64(r->flags)) 334 continue; 335 336 start = (r->start - phb->ioda.m64_base) / segsz; 337 for (j = 0; j < resource_size(r) / segsz ; j++) 338 clear_bit(start + j, pe_alloc); 339 } 340 } 341 342 /* 343 * the current bus might not own M64 window and that's all 344 * contributed by its child buses. For the case, we needn't 345 * pick M64 dependent PE#. 346 */ 347 if (bitmap_empty(pe_alloc, phb->ioda.total_pe)) { 348 kfree(pe_alloc); 349 return IODA_INVALID_PE; 350 } 351 352 /* 353 * Figure out the master PE and put all slave PEs to master 354 * PE's list to form compound PE. 355 */ 356 done: 357 master_pe = NULL; 358 i = -1; 359 while ((i = find_next_bit(pe_alloc, phb->ioda.total_pe, i + 1)) < 360 phb->ioda.total_pe) { 361 pe = &phb->ioda.pe_array[i]; 362 363 if (!master_pe) { 364 pe->flags |= PNV_IODA_PE_MASTER; 365 INIT_LIST_HEAD(&pe->slaves); 366 master_pe = pe; 367 } else { 368 pe->flags |= PNV_IODA_PE_SLAVE; 369 pe->master = master_pe; 370 list_add_tail(&pe->list, &master_pe->slaves); 371 } 372 } 373 374 kfree(pe_alloc); 375 return master_pe->pe_number; 376 } 377 378 static void __init pnv_ioda_parse_m64_window(struct pnv_phb *phb) 379 { 380 struct pci_controller *hose = phb->hose; 381 struct device_node *dn = hose->dn; 382 struct resource *res; 383 const u32 *r; 384 u64 pci_addr; 385 386 /* FIXME: Support M64 for P7IOC */ 387 if (phb->type != PNV_PHB_IODA2) { 388 pr_info(" Not support M64 window\n"); 389 return; 390 } 391 392 if (!firmware_has_feature(FW_FEATURE_OPALv3)) { 393 pr_info(" Firmware too old to support M64 window\n"); 394 return; 395 } 396 397 r = of_get_property(dn, "ibm,opal-m64-window", NULL); 398 if (!r) { 399 pr_info(" No <ibm,opal-m64-window> on %s\n", 400 dn->full_name); 401 return; 402 } 403 404 res = &hose->mem_resources[1]; 405 res->start = of_translate_address(dn, r + 2); 406 res->end = res->start + of_read_number(r + 4, 2) - 1; 407 res->flags = (IORESOURCE_MEM | IORESOURCE_MEM_64 | IORESOURCE_PREFETCH); 408 pci_addr = of_read_number(r, 2); 409 hose->mem_offset[1] = res->start - pci_addr; 410 411 phb->ioda.m64_size = resource_size(res); 412 phb->ioda.m64_segsize = phb->ioda.m64_size / phb->ioda.total_pe; 413 phb->ioda.m64_base = pci_addr; 414 415 pr_info(" MEM64 0x%016llx..0x%016llx -> 0x%016llx\n", 416 res->start, res->end, pci_addr); 417 418 /* Use last M64 BAR to cover M64 window */ 419 phb->ioda.m64_bar_idx = 15; 420 phb->init_m64 = pnv_ioda2_init_m64; 421 phb->reserve_m64_pe = pnv_ioda2_reserve_m64_pe; 422 phb->pick_m64_pe = pnv_ioda2_pick_m64_pe; 423 } 424 425 static void pnv_ioda_freeze_pe(struct pnv_phb *phb, int pe_no) 426 { 427 struct pnv_ioda_pe *pe = &phb->ioda.pe_array[pe_no]; 428 struct pnv_ioda_pe *slave; 429 s64 rc; 430 431 /* Fetch master PE */ 432 if (pe->flags & PNV_IODA_PE_SLAVE) { 433 pe = pe->master; 434 if (WARN_ON(!pe || !(pe->flags & PNV_IODA_PE_MASTER))) 435 return; 436 437 pe_no = pe->pe_number; 438 } 439 440 /* Freeze master PE */ 441 rc = opal_pci_eeh_freeze_set(phb->opal_id, 442 pe_no, 443 OPAL_EEH_ACTION_SET_FREEZE_ALL); 444 if (rc != OPAL_SUCCESS) { 445 pr_warn("%s: Failure %lld freezing PHB#%x-PE#%x\n", 446 __func__, rc, phb->hose->global_number, pe_no); 447 return; 448 } 449 450 /* Freeze slave PEs */ 451 if (!(pe->flags & PNV_IODA_PE_MASTER)) 452 return; 453 454 list_for_each_entry(slave, &pe->slaves, list) { 455 rc = opal_pci_eeh_freeze_set(phb->opal_id, 456 slave->pe_number, 457 OPAL_EEH_ACTION_SET_FREEZE_ALL); 458 if (rc != OPAL_SUCCESS) 459 pr_warn("%s: Failure %lld freezing PHB#%x-PE#%x\n", 460 __func__, rc, phb->hose->global_number, 461 slave->pe_number); 462 } 463 } 464 465 static int pnv_ioda_unfreeze_pe(struct pnv_phb *phb, int pe_no, int opt) 466 { 467 struct pnv_ioda_pe *pe, *slave; 468 s64 rc; 469 470 /* Find master PE */ 471 pe = &phb->ioda.pe_array[pe_no]; 472 if (pe->flags & PNV_IODA_PE_SLAVE) { 473 pe = pe->master; 474 WARN_ON(!pe || !(pe->flags & PNV_IODA_PE_MASTER)); 475 pe_no = pe->pe_number; 476 } 477 478 /* Clear frozen state for master PE */ 479 rc = opal_pci_eeh_freeze_clear(phb->opal_id, pe_no, opt); 480 if (rc != OPAL_SUCCESS) { 481 pr_warn("%s: Failure %lld clear %d on PHB#%x-PE#%x\n", 482 __func__, rc, opt, phb->hose->global_number, pe_no); 483 return -EIO; 484 } 485 486 if (!(pe->flags & PNV_IODA_PE_MASTER)) 487 return 0; 488 489 /* Clear frozen state for slave PEs */ 490 list_for_each_entry(slave, &pe->slaves, list) { 491 rc = opal_pci_eeh_freeze_clear(phb->opal_id, 492 slave->pe_number, 493 opt); 494 if (rc != OPAL_SUCCESS) { 495 pr_warn("%s: Failure %lld clear %d on PHB#%x-PE#%x\n", 496 __func__, rc, opt, phb->hose->global_number, 497 slave->pe_number); 498 return -EIO; 499 } 500 } 501 502 return 0; 503 } 504 505 static int pnv_ioda_get_pe_state(struct pnv_phb *phb, int pe_no) 506 { 507 struct pnv_ioda_pe *slave, *pe; 508 u8 fstate, state; 509 __be16 pcierr; 510 s64 rc; 511 512 /* Sanity check on PE number */ 513 if (pe_no < 0 || pe_no >= phb->ioda.total_pe) 514 return OPAL_EEH_STOPPED_PERM_UNAVAIL; 515 516 /* 517 * Fetch the master PE and the PE instance might be 518 * not initialized yet. 519 */ 520 pe = &phb->ioda.pe_array[pe_no]; 521 if (pe->flags & PNV_IODA_PE_SLAVE) { 522 pe = pe->master; 523 WARN_ON(!pe || !(pe->flags & PNV_IODA_PE_MASTER)); 524 pe_no = pe->pe_number; 525 } 526 527 /* Check the master PE */ 528 rc = opal_pci_eeh_freeze_status(phb->opal_id, pe_no, 529 &state, &pcierr, NULL); 530 if (rc != OPAL_SUCCESS) { 531 pr_warn("%s: Failure %lld getting " 532 "PHB#%x-PE#%x state\n", 533 __func__, rc, 534 phb->hose->global_number, pe_no); 535 return OPAL_EEH_STOPPED_TEMP_UNAVAIL; 536 } 537 538 /* Check the slave PE */ 539 if (!(pe->flags & PNV_IODA_PE_MASTER)) 540 return state; 541 542 list_for_each_entry(slave, &pe->slaves, list) { 543 rc = opal_pci_eeh_freeze_status(phb->opal_id, 544 slave->pe_number, 545 &fstate, 546 &pcierr, 547 NULL); 548 if (rc != OPAL_SUCCESS) { 549 pr_warn("%s: Failure %lld getting " 550 "PHB#%x-PE#%x state\n", 551 __func__, rc, 552 phb->hose->global_number, slave->pe_number); 553 return OPAL_EEH_STOPPED_TEMP_UNAVAIL; 554 } 555 556 /* 557 * Override the result based on the ascending 558 * priority. 559 */ 560 if (fstate > state) 561 state = fstate; 562 } 563 564 return state; 565 } 566 567 /* Currently those 2 are only used when MSIs are enabled, this will change 568 * but in the meantime, we need to protect them to avoid warnings 569 */ 570 #ifdef CONFIG_PCI_MSI 571 static struct pnv_ioda_pe *pnv_ioda_get_pe(struct pci_dev *dev) 572 { 573 struct pci_controller *hose = pci_bus_to_host(dev->bus); 574 struct pnv_phb *phb = hose->private_data; 575 struct pci_dn *pdn = pci_get_pdn(dev); 576 577 if (!pdn) 578 return NULL; 579 if (pdn->pe_number == IODA_INVALID_PE) 580 return NULL; 581 return &phb->ioda.pe_array[pdn->pe_number]; 582 } 583 #endif /* CONFIG_PCI_MSI */ 584 585 static int pnv_ioda_set_one_peltv(struct pnv_phb *phb, 586 struct pnv_ioda_pe *parent, 587 struct pnv_ioda_pe *child, 588 bool is_add) 589 { 590 const char *desc = is_add ? "adding" : "removing"; 591 uint8_t op = is_add ? OPAL_ADD_PE_TO_DOMAIN : 592 OPAL_REMOVE_PE_FROM_DOMAIN; 593 struct pnv_ioda_pe *slave; 594 long rc; 595 596 /* Parent PE affects child PE */ 597 rc = opal_pci_set_peltv(phb->opal_id, parent->pe_number, 598 child->pe_number, op); 599 if (rc != OPAL_SUCCESS) { 600 pe_warn(child, "OPAL error %ld %s to parent PELTV\n", 601 rc, desc); 602 return -ENXIO; 603 } 604 605 if (!(child->flags & PNV_IODA_PE_MASTER)) 606 return 0; 607 608 /* Compound case: parent PE affects slave PEs */ 609 list_for_each_entry(slave, &child->slaves, list) { 610 rc = opal_pci_set_peltv(phb->opal_id, parent->pe_number, 611 slave->pe_number, op); 612 if (rc != OPAL_SUCCESS) { 613 pe_warn(slave, "OPAL error %ld %s to parent PELTV\n", 614 rc, desc); 615 return -ENXIO; 616 } 617 } 618 619 return 0; 620 } 621 622 static int pnv_ioda_set_peltv(struct pnv_phb *phb, 623 struct pnv_ioda_pe *pe, 624 bool is_add) 625 { 626 struct pnv_ioda_pe *slave; 627 struct pci_dev *pdev = NULL; 628 int ret; 629 630 /* 631 * Clear PE frozen state. If it's master PE, we need 632 * clear slave PE frozen state as well. 633 */ 634 if (is_add) { 635 opal_pci_eeh_freeze_clear(phb->opal_id, pe->pe_number, 636 OPAL_EEH_ACTION_CLEAR_FREEZE_ALL); 637 if (pe->flags & PNV_IODA_PE_MASTER) { 638 list_for_each_entry(slave, &pe->slaves, list) 639 opal_pci_eeh_freeze_clear(phb->opal_id, 640 slave->pe_number, 641 OPAL_EEH_ACTION_CLEAR_FREEZE_ALL); 642 } 643 } 644 645 /* 646 * Associate PE in PELT. We need add the PE into the 647 * corresponding PELT-V as well. Otherwise, the error 648 * originated from the PE might contribute to other 649 * PEs. 650 */ 651 ret = pnv_ioda_set_one_peltv(phb, pe, pe, is_add); 652 if (ret) 653 return ret; 654 655 /* For compound PEs, any one affects all of them */ 656 if (pe->flags & PNV_IODA_PE_MASTER) { 657 list_for_each_entry(slave, &pe->slaves, list) { 658 ret = pnv_ioda_set_one_peltv(phb, slave, pe, is_add); 659 if (ret) 660 return ret; 661 } 662 } 663 664 if (pe->flags & (PNV_IODA_PE_BUS_ALL | PNV_IODA_PE_BUS)) 665 pdev = pe->pbus->self; 666 else if (pe->flags & PNV_IODA_PE_DEV) 667 pdev = pe->pdev->bus->self; 668 #ifdef CONFIG_PCI_IOV 669 else if (pe->flags & PNV_IODA_PE_VF) 670 pdev = pe->parent_dev->bus->self; 671 #endif /* CONFIG_PCI_IOV */ 672 while (pdev) { 673 struct pci_dn *pdn = pci_get_pdn(pdev); 674 struct pnv_ioda_pe *parent; 675 676 if (pdn && pdn->pe_number != IODA_INVALID_PE) { 677 parent = &phb->ioda.pe_array[pdn->pe_number]; 678 ret = pnv_ioda_set_one_peltv(phb, parent, pe, is_add); 679 if (ret) 680 return ret; 681 } 682 683 pdev = pdev->bus->self; 684 } 685 686 return 0; 687 } 688 689 #ifdef CONFIG_PCI_IOV 690 static int pnv_ioda_deconfigure_pe(struct pnv_phb *phb, struct pnv_ioda_pe *pe) 691 { 692 struct pci_dev *parent; 693 uint8_t bcomp, dcomp, fcomp; 694 int64_t rc; 695 long rid_end, rid; 696 697 /* Currently, we just deconfigure VF PE. Bus PE will always there.*/ 698 if (pe->pbus) { 699 int count; 700 701 dcomp = OPAL_IGNORE_RID_DEVICE_NUMBER; 702 fcomp = OPAL_IGNORE_RID_FUNCTION_NUMBER; 703 parent = pe->pbus->self; 704 if (pe->flags & PNV_IODA_PE_BUS_ALL) 705 count = pe->pbus->busn_res.end - pe->pbus->busn_res.start + 1; 706 else 707 count = 1; 708 709 switch(count) { 710 case 1: bcomp = OpalPciBusAll; break; 711 case 2: bcomp = OpalPciBus7Bits; break; 712 case 4: bcomp = OpalPciBus6Bits; break; 713 case 8: bcomp = OpalPciBus5Bits; break; 714 case 16: bcomp = OpalPciBus4Bits; break; 715 case 32: bcomp = OpalPciBus3Bits; break; 716 default: 717 dev_err(&pe->pbus->dev, "Number of subordinate buses %d unsupported\n", 718 count); 719 /* Do an exact match only */ 720 bcomp = OpalPciBusAll; 721 } 722 rid_end = pe->rid + (count << 8); 723 } else { 724 if (pe->flags & PNV_IODA_PE_VF) 725 parent = pe->parent_dev; 726 else 727 parent = pe->pdev->bus->self; 728 bcomp = OpalPciBusAll; 729 dcomp = OPAL_COMPARE_RID_DEVICE_NUMBER; 730 fcomp = OPAL_COMPARE_RID_FUNCTION_NUMBER; 731 rid_end = pe->rid + 1; 732 } 733 734 /* Clear the reverse map */ 735 for (rid = pe->rid; rid < rid_end; rid++) 736 phb->ioda.pe_rmap[rid] = 0; 737 738 /* Release from all parents PELT-V */ 739 while (parent) { 740 struct pci_dn *pdn = pci_get_pdn(parent); 741 if (pdn && pdn->pe_number != IODA_INVALID_PE) { 742 rc = opal_pci_set_peltv(phb->opal_id, pdn->pe_number, 743 pe->pe_number, OPAL_REMOVE_PE_FROM_DOMAIN); 744 /* XXX What to do in case of error ? */ 745 } 746 parent = parent->bus->self; 747 } 748 749 opal_pci_eeh_freeze_set(phb->opal_id, pe->pe_number, 750 OPAL_EEH_ACTION_CLEAR_FREEZE_ALL); 751 752 /* Disassociate PE in PELT */ 753 rc = opal_pci_set_peltv(phb->opal_id, pe->pe_number, 754 pe->pe_number, OPAL_REMOVE_PE_FROM_DOMAIN); 755 if (rc) 756 pe_warn(pe, "OPAL error %ld remove self from PELTV\n", rc); 757 rc = opal_pci_set_pe(phb->opal_id, pe->pe_number, pe->rid, 758 bcomp, dcomp, fcomp, OPAL_UNMAP_PE); 759 if (rc) 760 pe_err(pe, "OPAL error %ld trying to setup PELT table\n", rc); 761 762 pe->pbus = NULL; 763 pe->pdev = NULL; 764 pe->parent_dev = NULL; 765 766 return 0; 767 } 768 #endif /* CONFIG_PCI_IOV */ 769 770 static int pnv_ioda_configure_pe(struct pnv_phb *phb, struct pnv_ioda_pe *pe) 771 { 772 struct pci_dev *parent; 773 uint8_t bcomp, dcomp, fcomp; 774 long rc, rid_end, rid; 775 776 /* Bus validation ? */ 777 if (pe->pbus) { 778 int count; 779 780 dcomp = OPAL_IGNORE_RID_DEVICE_NUMBER; 781 fcomp = OPAL_IGNORE_RID_FUNCTION_NUMBER; 782 parent = pe->pbus->self; 783 if (pe->flags & PNV_IODA_PE_BUS_ALL) 784 count = pe->pbus->busn_res.end - pe->pbus->busn_res.start + 1; 785 else 786 count = 1; 787 788 switch(count) { 789 case 1: bcomp = OpalPciBusAll; break; 790 case 2: bcomp = OpalPciBus7Bits; break; 791 case 4: bcomp = OpalPciBus6Bits; break; 792 case 8: bcomp = OpalPciBus5Bits; break; 793 case 16: bcomp = OpalPciBus4Bits; break; 794 case 32: bcomp = OpalPciBus3Bits; break; 795 default: 796 dev_err(&pe->pbus->dev, "Number of subordinate buses %d unsupported\n", 797 count); 798 /* Do an exact match only */ 799 bcomp = OpalPciBusAll; 800 } 801 rid_end = pe->rid + (count << 8); 802 } else { 803 #ifdef CONFIG_PCI_IOV 804 if (pe->flags & PNV_IODA_PE_VF) 805 parent = pe->parent_dev; 806 else 807 #endif /* CONFIG_PCI_IOV */ 808 parent = pe->pdev->bus->self; 809 bcomp = OpalPciBusAll; 810 dcomp = OPAL_COMPARE_RID_DEVICE_NUMBER; 811 fcomp = OPAL_COMPARE_RID_FUNCTION_NUMBER; 812 rid_end = pe->rid + 1; 813 } 814 815 /* 816 * Associate PE in PELT. We need add the PE into the 817 * corresponding PELT-V as well. Otherwise, the error 818 * originated from the PE might contribute to other 819 * PEs. 820 */ 821 rc = opal_pci_set_pe(phb->opal_id, pe->pe_number, pe->rid, 822 bcomp, dcomp, fcomp, OPAL_MAP_PE); 823 if (rc) { 824 pe_err(pe, "OPAL error %ld trying to setup PELT table\n", rc); 825 return -ENXIO; 826 } 827 828 /* Configure PELTV */ 829 pnv_ioda_set_peltv(phb, pe, true); 830 831 /* Setup reverse map */ 832 for (rid = pe->rid; rid < rid_end; rid++) 833 phb->ioda.pe_rmap[rid] = pe->pe_number; 834 835 /* Setup one MVTs on IODA1 */ 836 if (phb->type != PNV_PHB_IODA1) { 837 pe->mve_number = 0; 838 goto out; 839 } 840 841 pe->mve_number = pe->pe_number; 842 rc = opal_pci_set_mve(phb->opal_id, pe->mve_number, pe->pe_number); 843 if (rc != OPAL_SUCCESS) { 844 pe_err(pe, "OPAL error %ld setting up MVE %d\n", 845 rc, pe->mve_number); 846 pe->mve_number = -1; 847 } else { 848 rc = opal_pci_set_mve_enable(phb->opal_id, 849 pe->mve_number, OPAL_ENABLE_MVE); 850 if (rc) { 851 pe_err(pe, "OPAL error %ld enabling MVE %d\n", 852 rc, pe->mve_number); 853 pe->mve_number = -1; 854 } 855 } 856 857 out: 858 return 0; 859 } 860 861 static void pnv_ioda_link_pe_by_weight(struct pnv_phb *phb, 862 struct pnv_ioda_pe *pe) 863 { 864 struct pnv_ioda_pe *lpe; 865 866 list_for_each_entry(lpe, &phb->ioda.pe_dma_list, dma_link) { 867 if (lpe->dma_weight < pe->dma_weight) { 868 list_add_tail(&pe->dma_link, &lpe->dma_link); 869 return; 870 } 871 } 872 list_add_tail(&pe->dma_link, &phb->ioda.pe_dma_list); 873 } 874 875 static unsigned int pnv_ioda_dma_weight(struct pci_dev *dev) 876 { 877 /* This is quite simplistic. The "base" weight of a device 878 * is 10. 0 means no DMA is to be accounted for it. 879 */ 880 881 /* If it's a bridge, no DMA */ 882 if (dev->hdr_type != PCI_HEADER_TYPE_NORMAL) 883 return 0; 884 885 /* Reduce the weight of slow USB controllers */ 886 if (dev->class == PCI_CLASS_SERIAL_USB_UHCI || 887 dev->class == PCI_CLASS_SERIAL_USB_OHCI || 888 dev->class == PCI_CLASS_SERIAL_USB_EHCI) 889 return 3; 890 891 /* Increase the weight of RAID (includes Obsidian) */ 892 if ((dev->class >> 8) == PCI_CLASS_STORAGE_RAID) 893 return 15; 894 895 /* Default */ 896 return 10; 897 } 898 899 #ifdef CONFIG_PCI_IOV 900 static int pnv_pci_vf_resource_shift(struct pci_dev *dev, int offset) 901 { 902 struct pci_dn *pdn = pci_get_pdn(dev); 903 int i; 904 struct resource *res, res2; 905 resource_size_t size; 906 u16 num_vfs; 907 908 if (!dev->is_physfn) 909 return -EINVAL; 910 911 /* 912 * "offset" is in VFs. The M64 windows are sized so that when they 913 * are segmented, each segment is the same size as the IOV BAR. 914 * Each segment is in a separate PE, and the high order bits of the 915 * address are the PE number. Therefore, each VF's BAR is in a 916 * separate PE, and changing the IOV BAR start address changes the 917 * range of PEs the VFs are in. 918 */ 919 num_vfs = pdn->num_vfs; 920 for (i = 0; i < PCI_SRIOV_NUM_BARS; i++) { 921 res = &dev->resource[i + PCI_IOV_RESOURCES]; 922 if (!res->flags || !res->parent) 923 continue; 924 925 if (!pnv_pci_is_mem_pref_64(res->flags)) 926 continue; 927 928 /* 929 * The actual IOV BAR range is determined by the start address 930 * and the actual size for num_vfs VFs BAR. This check is to 931 * make sure that after shifting, the range will not overlap 932 * with another device. 933 */ 934 size = pci_iov_resource_size(dev, i + PCI_IOV_RESOURCES); 935 res2.flags = res->flags; 936 res2.start = res->start + (size * offset); 937 res2.end = res2.start + (size * num_vfs) - 1; 938 939 if (res2.end > res->end) { 940 dev_err(&dev->dev, "VF BAR%d: %pR would extend past %pR (trying to enable %d VFs shifted by %d)\n", 941 i, &res2, res, num_vfs, offset); 942 return -EBUSY; 943 } 944 } 945 946 /* 947 * After doing so, there would be a "hole" in the /proc/iomem when 948 * offset is a positive value. It looks like the device return some 949 * mmio back to the system, which actually no one could use it. 950 */ 951 for (i = 0; i < PCI_SRIOV_NUM_BARS; i++) { 952 res = &dev->resource[i + PCI_IOV_RESOURCES]; 953 if (!res->flags || !res->parent) 954 continue; 955 956 if (!pnv_pci_is_mem_pref_64(res->flags)) 957 continue; 958 959 size = pci_iov_resource_size(dev, i + PCI_IOV_RESOURCES); 960 res2 = *res; 961 res->start += size * offset; 962 963 dev_info(&dev->dev, "VF BAR%d: %pR shifted to %pR (enabling %d VFs shifted by %d)\n", 964 i, &res2, res, num_vfs, offset); 965 pci_update_resource(dev, i + PCI_IOV_RESOURCES); 966 } 967 return 0; 968 } 969 #endif /* CONFIG_PCI_IOV */ 970 971 #if 0 972 static struct pnv_ioda_pe *pnv_ioda_setup_dev_PE(struct pci_dev *dev) 973 { 974 struct pci_controller *hose = pci_bus_to_host(dev->bus); 975 struct pnv_phb *phb = hose->private_data; 976 struct pci_dn *pdn = pci_get_pdn(dev); 977 struct pnv_ioda_pe *pe; 978 int pe_num; 979 980 if (!pdn) { 981 pr_err("%s: Device tree node not associated properly\n", 982 pci_name(dev)); 983 return NULL; 984 } 985 if (pdn->pe_number != IODA_INVALID_PE) 986 return NULL; 987 988 /* PE#0 has been pre-set */ 989 if (dev->bus->number == 0) 990 pe_num = 0; 991 else 992 pe_num = pnv_ioda_alloc_pe(phb); 993 if (pe_num == IODA_INVALID_PE) { 994 pr_warning("%s: Not enough PE# available, disabling device\n", 995 pci_name(dev)); 996 return NULL; 997 } 998 999 /* NOTE: We get only one ref to the pci_dev for the pdn, not for the 1000 * pointer in the PE data structure, both should be destroyed at the 1001 * same time. However, this needs to be looked at more closely again 1002 * once we actually start removing things (Hotplug, SR-IOV, ...) 1003 * 1004 * At some point we want to remove the PDN completely anyways 1005 */ 1006 pe = &phb->ioda.pe_array[pe_num]; 1007 pci_dev_get(dev); 1008 pdn->pcidev = dev; 1009 pdn->pe_number = pe_num; 1010 pe->pdev = dev; 1011 pe->pbus = NULL; 1012 pe->tce32_seg = -1; 1013 pe->mve_number = -1; 1014 pe->rid = dev->bus->number << 8 | pdn->devfn; 1015 1016 pe_info(pe, "Associated device to PE\n"); 1017 1018 if (pnv_ioda_configure_pe(phb, pe)) { 1019 /* XXX What do we do here ? */ 1020 if (pe_num) 1021 pnv_ioda_free_pe(phb, pe_num); 1022 pdn->pe_number = IODA_INVALID_PE; 1023 pe->pdev = NULL; 1024 pci_dev_put(dev); 1025 return NULL; 1026 } 1027 1028 /* Assign a DMA weight to the device */ 1029 pe->dma_weight = pnv_ioda_dma_weight(dev); 1030 if (pe->dma_weight != 0) { 1031 phb->ioda.dma_weight += pe->dma_weight; 1032 phb->ioda.dma_pe_count++; 1033 } 1034 1035 /* Link the PE */ 1036 pnv_ioda_link_pe_by_weight(phb, pe); 1037 1038 return pe; 1039 } 1040 #endif /* Useful for SRIOV case */ 1041 1042 static void pnv_ioda_setup_same_PE(struct pci_bus *bus, struct pnv_ioda_pe *pe) 1043 { 1044 struct pci_dev *dev; 1045 1046 list_for_each_entry(dev, &bus->devices, bus_list) { 1047 struct pci_dn *pdn = pci_get_pdn(dev); 1048 1049 if (pdn == NULL) { 1050 pr_warn("%s: No device node associated with device !\n", 1051 pci_name(dev)); 1052 continue; 1053 } 1054 pdn->pe_number = pe->pe_number; 1055 pe->dma_weight += pnv_ioda_dma_weight(dev); 1056 if ((pe->flags & PNV_IODA_PE_BUS_ALL) && dev->subordinate) 1057 pnv_ioda_setup_same_PE(dev->subordinate, pe); 1058 } 1059 } 1060 1061 /* 1062 * There're 2 types of PCI bus sensitive PEs: One that is compromised of 1063 * single PCI bus. Another one that contains the primary PCI bus and its 1064 * subordinate PCI devices and buses. The second type of PE is normally 1065 * orgiriated by PCIe-to-PCI bridge or PLX switch downstream ports. 1066 */ 1067 static void pnv_ioda_setup_bus_PE(struct pci_bus *bus, bool all) 1068 { 1069 struct pci_controller *hose = pci_bus_to_host(bus); 1070 struct pnv_phb *phb = hose->private_data; 1071 struct pnv_ioda_pe *pe; 1072 int pe_num = IODA_INVALID_PE; 1073 1074 /* Check if PE is determined by M64 */ 1075 if (phb->pick_m64_pe) 1076 pe_num = phb->pick_m64_pe(phb, bus, all); 1077 1078 /* The PE number isn't pinned by M64 */ 1079 if (pe_num == IODA_INVALID_PE) 1080 pe_num = pnv_ioda_alloc_pe(phb); 1081 1082 if (pe_num == IODA_INVALID_PE) { 1083 pr_warning("%s: Not enough PE# available for PCI bus %04x:%02x\n", 1084 __func__, pci_domain_nr(bus), bus->number); 1085 return; 1086 } 1087 1088 pe = &phb->ioda.pe_array[pe_num]; 1089 pe->flags |= (all ? PNV_IODA_PE_BUS_ALL : PNV_IODA_PE_BUS); 1090 pe->pbus = bus; 1091 pe->pdev = NULL; 1092 pe->tce32_seg = -1; 1093 pe->mve_number = -1; 1094 pe->rid = bus->busn_res.start << 8; 1095 pe->dma_weight = 0; 1096 1097 if (all) 1098 pe_info(pe, "Secondary bus %d..%d associated with PE#%d\n", 1099 bus->busn_res.start, bus->busn_res.end, pe_num); 1100 else 1101 pe_info(pe, "Secondary bus %d associated with PE#%d\n", 1102 bus->busn_res.start, pe_num); 1103 1104 if (pnv_ioda_configure_pe(phb, pe)) { 1105 /* XXX What do we do here ? */ 1106 if (pe_num) 1107 pnv_ioda_free_pe(phb, pe_num); 1108 pe->pbus = NULL; 1109 return; 1110 } 1111 1112 /* Associate it with all child devices */ 1113 pnv_ioda_setup_same_PE(bus, pe); 1114 1115 /* Put PE to the list */ 1116 list_add_tail(&pe->list, &phb->ioda.pe_list); 1117 1118 /* Account for one DMA PE if at least one DMA capable device exist 1119 * below the bridge 1120 */ 1121 if (pe->dma_weight != 0) { 1122 phb->ioda.dma_weight += pe->dma_weight; 1123 phb->ioda.dma_pe_count++; 1124 } 1125 1126 /* Link the PE */ 1127 pnv_ioda_link_pe_by_weight(phb, pe); 1128 } 1129 1130 static void pnv_ioda_setup_PEs(struct pci_bus *bus) 1131 { 1132 struct pci_dev *dev; 1133 1134 pnv_ioda_setup_bus_PE(bus, false); 1135 1136 list_for_each_entry(dev, &bus->devices, bus_list) { 1137 if (dev->subordinate) { 1138 if (pci_pcie_type(dev) == PCI_EXP_TYPE_PCI_BRIDGE) 1139 pnv_ioda_setup_bus_PE(dev->subordinate, true); 1140 else 1141 pnv_ioda_setup_PEs(dev->subordinate); 1142 } 1143 } 1144 } 1145 1146 /* 1147 * Configure PEs so that the downstream PCI buses and devices 1148 * could have their associated PE#. Unfortunately, we didn't 1149 * figure out the way to identify the PLX bridge yet. So we 1150 * simply put the PCI bus and the subordinate behind the root 1151 * port to PE# here. The game rule here is expected to be changed 1152 * as soon as we can detected PLX bridge correctly. 1153 */ 1154 static void pnv_pci_ioda_setup_PEs(void) 1155 { 1156 struct pci_controller *hose, *tmp; 1157 struct pnv_phb *phb; 1158 1159 list_for_each_entry_safe(hose, tmp, &hose_list, list_node) { 1160 phb = hose->private_data; 1161 1162 /* M64 layout might affect PE allocation */ 1163 if (phb->reserve_m64_pe) 1164 phb->reserve_m64_pe(hose->bus, NULL, true); 1165 1166 pnv_ioda_setup_PEs(hose->bus); 1167 } 1168 } 1169 1170 #ifdef CONFIG_PCI_IOV 1171 static int pnv_pci_vf_release_m64(struct pci_dev *pdev) 1172 { 1173 struct pci_bus *bus; 1174 struct pci_controller *hose; 1175 struct pnv_phb *phb; 1176 struct pci_dn *pdn; 1177 int i, j; 1178 1179 bus = pdev->bus; 1180 hose = pci_bus_to_host(bus); 1181 phb = hose->private_data; 1182 pdn = pci_get_pdn(pdev); 1183 1184 for (i = 0; i < PCI_SRIOV_NUM_BARS; i++) 1185 for (j = 0; j < M64_PER_IOV; j++) { 1186 if (pdn->m64_wins[i][j] == IODA_INVALID_M64) 1187 continue; 1188 opal_pci_phb_mmio_enable(phb->opal_id, 1189 OPAL_M64_WINDOW_TYPE, pdn->m64_wins[i][j], 0); 1190 clear_bit(pdn->m64_wins[i][j], &phb->ioda.m64_bar_alloc); 1191 pdn->m64_wins[i][j] = IODA_INVALID_M64; 1192 } 1193 1194 return 0; 1195 } 1196 1197 static int pnv_pci_vf_assign_m64(struct pci_dev *pdev, u16 num_vfs) 1198 { 1199 struct pci_bus *bus; 1200 struct pci_controller *hose; 1201 struct pnv_phb *phb; 1202 struct pci_dn *pdn; 1203 unsigned int win; 1204 struct resource *res; 1205 int i, j; 1206 int64_t rc; 1207 int total_vfs; 1208 resource_size_t size, start; 1209 int pe_num; 1210 int vf_groups; 1211 int vf_per_group; 1212 1213 bus = pdev->bus; 1214 hose = pci_bus_to_host(bus); 1215 phb = hose->private_data; 1216 pdn = pci_get_pdn(pdev); 1217 total_vfs = pci_sriov_get_totalvfs(pdev); 1218 1219 /* Initialize the m64_wins to IODA_INVALID_M64 */ 1220 for (i = 0; i < PCI_SRIOV_NUM_BARS; i++) 1221 for (j = 0; j < M64_PER_IOV; j++) 1222 pdn->m64_wins[i][j] = IODA_INVALID_M64; 1223 1224 if (pdn->m64_per_iov == M64_PER_IOV) { 1225 vf_groups = (num_vfs <= M64_PER_IOV) ? num_vfs: M64_PER_IOV; 1226 vf_per_group = (num_vfs <= M64_PER_IOV)? 1: 1227 roundup_pow_of_two(num_vfs) / pdn->m64_per_iov; 1228 } else { 1229 vf_groups = 1; 1230 vf_per_group = 1; 1231 } 1232 1233 for (i = 0; i < PCI_SRIOV_NUM_BARS; i++) { 1234 res = &pdev->resource[i + PCI_IOV_RESOURCES]; 1235 if (!res->flags || !res->parent) 1236 continue; 1237 1238 if (!pnv_pci_is_mem_pref_64(res->flags)) 1239 continue; 1240 1241 for (j = 0; j < vf_groups; j++) { 1242 do { 1243 win = find_next_zero_bit(&phb->ioda.m64_bar_alloc, 1244 phb->ioda.m64_bar_idx + 1, 0); 1245 1246 if (win >= phb->ioda.m64_bar_idx + 1) 1247 goto m64_failed; 1248 } while (test_and_set_bit(win, &phb->ioda.m64_bar_alloc)); 1249 1250 pdn->m64_wins[i][j] = win; 1251 1252 if (pdn->m64_per_iov == M64_PER_IOV) { 1253 size = pci_iov_resource_size(pdev, 1254 PCI_IOV_RESOURCES + i); 1255 size = size * vf_per_group; 1256 start = res->start + size * j; 1257 } else { 1258 size = resource_size(res); 1259 start = res->start; 1260 } 1261 1262 /* Map the M64 here */ 1263 if (pdn->m64_per_iov == M64_PER_IOV) { 1264 pe_num = pdn->offset + j; 1265 rc = opal_pci_map_pe_mmio_window(phb->opal_id, 1266 pe_num, OPAL_M64_WINDOW_TYPE, 1267 pdn->m64_wins[i][j], 0); 1268 } 1269 1270 rc = opal_pci_set_phb_mem_window(phb->opal_id, 1271 OPAL_M64_WINDOW_TYPE, 1272 pdn->m64_wins[i][j], 1273 start, 1274 0, /* unused */ 1275 size); 1276 1277 1278 if (rc != OPAL_SUCCESS) { 1279 dev_err(&pdev->dev, "Failed to map M64 window #%d: %lld\n", 1280 win, rc); 1281 goto m64_failed; 1282 } 1283 1284 if (pdn->m64_per_iov == M64_PER_IOV) 1285 rc = opal_pci_phb_mmio_enable(phb->opal_id, 1286 OPAL_M64_WINDOW_TYPE, pdn->m64_wins[i][j], 2); 1287 else 1288 rc = opal_pci_phb_mmio_enable(phb->opal_id, 1289 OPAL_M64_WINDOW_TYPE, pdn->m64_wins[i][j], 1); 1290 1291 if (rc != OPAL_SUCCESS) { 1292 dev_err(&pdev->dev, "Failed to enable M64 window #%d: %llx\n", 1293 win, rc); 1294 goto m64_failed; 1295 } 1296 } 1297 } 1298 return 0; 1299 1300 m64_failed: 1301 pnv_pci_vf_release_m64(pdev); 1302 return -EBUSY; 1303 } 1304 1305 static long pnv_pci_ioda2_unset_window(struct iommu_table_group *table_group, 1306 int num); 1307 static void pnv_pci_ioda2_set_bypass(struct pnv_ioda_pe *pe, bool enable); 1308 1309 static void pnv_pci_ioda2_release_dma_pe(struct pci_dev *dev, struct pnv_ioda_pe *pe) 1310 { 1311 struct iommu_table *tbl; 1312 int64_t rc; 1313 1314 tbl = pe->table_group.tables[0]; 1315 rc = pnv_pci_ioda2_unset_window(&pe->table_group, 0); 1316 if (rc) 1317 pe_warn(pe, "OPAL error %ld release DMA window\n", rc); 1318 1319 pnv_pci_ioda2_set_bypass(pe, false); 1320 if (pe->table_group.group) { 1321 iommu_group_put(pe->table_group.group); 1322 BUG_ON(pe->table_group.group); 1323 } 1324 pnv_pci_ioda2_table_free_pages(tbl); 1325 iommu_free_table(tbl, of_node_full_name(dev->dev.of_node)); 1326 } 1327 1328 static void pnv_ioda_release_vf_PE(struct pci_dev *pdev, u16 num_vfs) 1329 { 1330 struct pci_bus *bus; 1331 struct pci_controller *hose; 1332 struct pnv_phb *phb; 1333 struct pnv_ioda_pe *pe, *pe_n; 1334 struct pci_dn *pdn; 1335 u16 vf_index; 1336 int64_t rc; 1337 1338 bus = pdev->bus; 1339 hose = pci_bus_to_host(bus); 1340 phb = hose->private_data; 1341 pdn = pci_get_pdn(pdev); 1342 1343 if (!pdev->is_physfn) 1344 return; 1345 1346 if (pdn->m64_per_iov == M64_PER_IOV && num_vfs > M64_PER_IOV) { 1347 int vf_group; 1348 int vf_per_group; 1349 int vf_index1; 1350 1351 vf_per_group = roundup_pow_of_two(num_vfs) / pdn->m64_per_iov; 1352 1353 for (vf_group = 0; vf_group < M64_PER_IOV; vf_group++) 1354 for (vf_index = vf_group * vf_per_group; 1355 vf_index < (vf_group + 1) * vf_per_group && 1356 vf_index < num_vfs; 1357 vf_index++) 1358 for (vf_index1 = vf_group * vf_per_group; 1359 vf_index1 < (vf_group + 1) * vf_per_group && 1360 vf_index1 < num_vfs; 1361 vf_index1++){ 1362 1363 rc = opal_pci_set_peltv(phb->opal_id, 1364 pdn->offset + vf_index, 1365 pdn->offset + vf_index1, 1366 OPAL_REMOVE_PE_FROM_DOMAIN); 1367 1368 if (rc) 1369 dev_warn(&pdev->dev, "%s: Failed to unlink same group PE#%d(%lld)\n", 1370 __func__, 1371 pdn->offset + vf_index1, rc); 1372 } 1373 } 1374 1375 list_for_each_entry_safe(pe, pe_n, &phb->ioda.pe_list, list) { 1376 if (pe->parent_dev != pdev) 1377 continue; 1378 1379 pnv_pci_ioda2_release_dma_pe(pdev, pe); 1380 1381 /* Remove from list */ 1382 mutex_lock(&phb->ioda.pe_list_mutex); 1383 list_del(&pe->list); 1384 mutex_unlock(&phb->ioda.pe_list_mutex); 1385 1386 pnv_ioda_deconfigure_pe(phb, pe); 1387 1388 pnv_ioda_free_pe(phb, pe->pe_number); 1389 } 1390 } 1391 1392 void pnv_pci_sriov_disable(struct pci_dev *pdev) 1393 { 1394 struct pci_bus *bus; 1395 struct pci_controller *hose; 1396 struct pnv_phb *phb; 1397 struct pci_dn *pdn; 1398 struct pci_sriov *iov; 1399 u16 num_vfs; 1400 1401 bus = pdev->bus; 1402 hose = pci_bus_to_host(bus); 1403 phb = hose->private_data; 1404 pdn = pci_get_pdn(pdev); 1405 iov = pdev->sriov; 1406 num_vfs = pdn->num_vfs; 1407 1408 /* Release VF PEs */ 1409 pnv_ioda_release_vf_PE(pdev, num_vfs); 1410 1411 if (phb->type == PNV_PHB_IODA2) { 1412 if (pdn->m64_per_iov == 1) 1413 pnv_pci_vf_resource_shift(pdev, -pdn->offset); 1414 1415 /* Release M64 windows */ 1416 pnv_pci_vf_release_m64(pdev); 1417 1418 /* Release PE numbers */ 1419 bitmap_clear(phb->ioda.pe_alloc, pdn->offset, num_vfs); 1420 pdn->offset = 0; 1421 } 1422 } 1423 1424 static void pnv_pci_ioda2_setup_dma_pe(struct pnv_phb *phb, 1425 struct pnv_ioda_pe *pe); 1426 static void pnv_ioda_setup_vf_PE(struct pci_dev *pdev, u16 num_vfs) 1427 { 1428 struct pci_bus *bus; 1429 struct pci_controller *hose; 1430 struct pnv_phb *phb; 1431 struct pnv_ioda_pe *pe; 1432 int pe_num; 1433 u16 vf_index; 1434 struct pci_dn *pdn; 1435 int64_t rc; 1436 1437 bus = pdev->bus; 1438 hose = pci_bus_to_host(bus); 1439 phb = hose->private_data; 1440 pdn = pci_get_pdn(pdev); 1441 1442 if (!pdev->is_physfn) 1443 return; 1444 1445 /* Reserve PE for each VF */ 1446 for (vf_index = 0; vf_index < num_vfs; vf_index++) { 1447 pe_num = pdn->offset + vf_index; 1448 1449 pe = &phb->ioda.pe_array[pe_num]; 1450 pe->pe_number = pe_num; 1451 pe->phb = phb; 1452 pe->flags = PNV_IODA_PE_VF; 1453 pe->pbus = NULL; 1454 pe->parent_dev = pdev; 1455 pe->tce32_seg = -1; 1456 pe->mve_number = -1; 1457 pe->rid = (pci_iov_virtfn_bus(pdev, vf_index) << 8) | 1458 pci_iov_virtfn_devfn(pdev, vf_index); 1459 1460 pe_info(pe, "VF %04d:%02d:%02d.%d associated with PE#%d\n", 1461 hose->global_number, pdev->bus->number, 1462 PCI_SLOT(pci_iov_virtfn_devfn(pdev, vf_index)), 1463 PCI_FUNC(pci_iov_virtfn_devfn(pdev, vf_index)), pe_num); 1464 1465 if (pnv_ioda_configure_pe(phb, pe)) { 1466 /* XXX What do we do here ? */ 1467 if (pe_num) 1468 pnv_ioda_free_pe(phb, pe_num); 1469 pe->pdev = NULL; 1470 continue; 1471 } 1472 1473 /* Put PE to the list */ 1474 mutex_lock(&phb->ioda.pe_list_mutex); 1475 list_add_tail(&pe->list, &phb->ioda.pe_list); 1476 mutex_unlock(&phb->ioda.pe_list_mutex); 1477 1478 pnv_pci_ioda2_setup_dma_pe(phb, pe); 1479 } 1480 1481 if (pdn->m64_per_iov == M64_PER_IOV && num_vfs > M64_PER_IOV) { 1482 int vf_group; 1483 int vf_per_group; 1484 int vf_index1; 1485 1486 vf_per_group = roundup_pow_of_two(num_vfs) / pdn->m64_per_iov; 1487 1488 for (vf_group = 0; vf_group < M64_PER_IOV; vf_group++) { 1489 for (vf_index = vf_group * vf_per_group; 1490 vf_index < (vf_group + 1) * vf_per_group && 1491 vf_index < num_vfs; 1492 vf_index++) { 1493 for (vf_index1 = vf_group * vf_per_group; 1494 vf_index1 < (vf_group + 1) * vf_per_group && 1495 vf_index1 < num_vfs; 1496 vf_index1++) { 1497 1498 rc = opal_pci_set_peltv(phb->opal_id, 1499 pdn->offset + vf_index, 1500 pdn->offset + vf_index1, 1501 OPAL_ADD_PE_TO_DOMAIN); 1502 1503 if (rc) 1504 dev_warn(&pdev->dev, "%s: Failed to link same group PE#%d(%lld)\n", 1505 __func__, 1506 pdn->offset + vf_index1, rc); 1507 } 1508 } 1509 } 1510 } 1511 } 1512 1513 int pnv_pci_sriov_enable(struct pci_dev *pdev, u16 num_vfs) 1514 { 1515 struct pci_bus *bus; 1516 struct pci_controller *hose; 1517 struct pnv_phb *phb; 1518 struct pci_dn *pdn; 1519 int ret; 1520 1521 bus = pdev->bus; 1522 hose = pci_bus_to_host(bus); 1523 phb = hose->private_data; 1524 pdn = pci_get_pdn(pdev); 1525 1526 if (phb->type == PNV_PHB_IODA2) { 1527 /* Calculate available PE for required VFs */ 1528 mutex_lock(&phb->ioda.pe_alloc_mutex); 1529 pdn->offset = bitmap_find_next_zero_area( 1530 phb->ioda.pe_alloc, phb->ioda.total_pe, 1531 0, num_vfs, 0); 1532 if (pdn->offset >= phb->ioda.total_pe) { 1533 mutex_unlock(&phb->ioda.pe_alloc_mutex); 1534 dev_info(&pdev->dev, "Failed to enable VF%d\n", num_vfs); 1535 pdn->offset = 0; 1536 return -EBUSY; 1537 } 1538 bitmap_set(phb->ioda.pe_alloc, pdn->offset, num_vfs); 1539 pdn->num_vfs = num_vfs; 1540 mutex_unlock(&phb->ioda.pe_alloc_mutex); 1541 1542 /* Assign M64 window accordingly */ 1543 ret = pnv_pci_vf_assign_m64(pdev, num_vfs); 1544 if (ret) { 1545 dev_info(&pdev->dev, "Not enough M64 window resources\n"); 1546 goto m64_failed; 1547 } 1548 1549 /* 1550 * When using one M64 BAR to map one IOV BAR, we need to shift 1551 * the IOV BAR according to the PE# allocated to the VFs. 1552 * Otherwise, the PE# for the VF will conflict with others. 1553 */ 1554 if (pdn->m64_per_iov == 1) { 1555 ret = pnv_pci_vf_resource_shift(pdev, pdn->offset); 1556 if (ret) 1557 goto m64_failed; 1558 } 1559 } 1560 1561 /* Setup VF PEs */ 1562 pnv_ioda_setup_vf_PE(pdev, num_vfs); 1563 1564 return 0; 1565 1566 m64_failed: 1567 bitmap_clear(phb->ioda.pe_alloc, pdn->offset, num_vfs); 1568 pdn->offset = 0; 1569 1570 return ret; 1571 } 1572 1573 int pcibios_sriov_disable(struct pci_dev *pdev) 1574 { 1575 pnv_pci_sriov_disable(pdev); 1576 1577 /* Release PCI data */ 1578 remove_dev_pci_data(pdev); 1579 return 0; 1580 } 1581 1582 int pcibios_sriov_enable(struct pci_dev *pdev, u16 num_vfs) 1583 { 1584 /* Allocate PCI data */ 1585 add_dev_pci_data(pdev); 1586 1587 pnv_pci_sriov_enable(pdev, num_vfs); 1588 return 0; 1589 } 1590 #endif /* CONFIG_PCI_IOV */ 1591 1592 static void pnv_pci_ioda_dma_dev_setup(struct pnv_phb *phb, struct pci_dev *pdev) 1593 { 1594 struct pci_dn *pdn = pci_get_pdn(pdev); 1595 struct pnv_ioda_pe *pe; 1596 1597 /* 1598 * The function can be called while the PE# 1599 * hasn't been assigned. Do nothing for the 1600 * case. 1601 */ 1602 if (!pdn || pdn->pe_number == IODA_INVALID_PE) 1603 return; 1604 1605 pe = &phb->ioda.pe_array[pdn->pe_number]; 1606 WARN_ON(get_dma_ops(&pdev->dev) != &dma_iommu_ops); 1607 set_iommu_table_base(&pdev->dev, pe->table_group.tables[0]); 1608 /* 1609 * Note: iommu_add_device() will fail here as 1610 * for physical PE: the device is already added by now; 1611 * for virtual PE: sysfs entries are not ready yet and 1612 * tce_iommu_bus_notifier will add the device to a group later. 1613 */ 1614 } 1615 1616 static int pnv_pci_ioda_dma_set_mask(struct pci_dev *pdev, u64 dma_mask) 1617 { 1618 struct pci_controller *hose = pci_bus_to_host(pdev->bus); 1619 struct pnv_phb *phb = hose->private_data; 1620 struct pci_dn *pdn = pci_get_pdn(pdev); 1621 struct pnv_ioda_pe *pe; 1622 uint64_t top; 1623 bool bypass = false; 1624 1625 if (WARN_ON(!pdn || pdn->pe_number == IODA_INVALID_PE)) 1626 return -ENODEV;; 1627 1628 pe = &phb->ioda.pe_array[pdn->pe_number]; 1629 if (pe->tce_bypass_enabled) { 1630 top = pe->tce_bypass_base + memblock_end_of_DRAM() - 1; 1631 bypass = (dma_mask >= top); 1632 } 1633 1634 if (bypass) { 1635 dev_info(&pdev->dev, "Using 64-bit DMA iommu bypass\n"); 1636 set_dma_ops(&pdev->dev, &dma_direct_ops); 1637 } else { 1638 dev_info(&pdev->dev, "Using 32-bit DMA via iommu\n"); 1639 set_dma_ops(&pdev->dev, &dma_iommu_ops); 1640 } 1641 *pdev->dev.dma_mask = dma_mask; 1642 return 0; 1643 } 1644 1645 static u64 pnv_pci_ioda_dma_get_required_mask(struct pnv_phb *phb, 1646 struct pci_dev *pdev) 1647 { 1648 struct pci_dn *pdn = pci_get_pdn(pdev); 1649 struct pnv_ioda_pe *pe; 1650 u64 end, mask; 1651 1652 if (WARN_ON(!pdn || pdn->pe_number == IODA_INVALID_PE)) 1653 return 0; 1654 1655 pe = &phb->ioda.pe_array[pdn->pe_number]; 1656 if (!pe->tce_bypass_enabled) 1657 return __dma_get_required_mask(&pdev->dev); 1658 1659 1660 end = pe->tce_bypass_base + memblock_end_of_DRAM(); 1661 mask = 1ULL << (fls64(end) - 1); 1662 mask += mask - 1; 1663 1664 return mask; 1665 } 1666 1667 static void pnv_ioda_setup_bus_dma(struct pnv_ioda_pe *pe, 1668 struct pci_bus *bus) 1669 { 1670 struct pci_dev *dev; 1671 1672 list_for_each_entry(dev, &bus->devices, bus_list) { 1673 set_iommu_table_base(&dev->dev, pe->table_group.tables[0]); 1674 set_dma_offset(&dev->dev, pe->tce_bypass_base); 1675 iommu_add_device(&dev->dev); 1676 1677 if ((pe->flags & PNV_IODA_PE_BUS_ALL) && dev->subordinate) 1678 pnv_ioda_setup_bus_dma(pe, dev->subordinate); 1679 } 1680 } 1681 1682 static void pnv_pci_ioda1_tce_invalidate(struct iommu_table *tbl, 1683 unsigned long index, unsigned long npages, bool rm) 1684 { 1685 struct iommu_table_group_link *tgl = list_first_entry_or_null( 1686 &tbl->it_group_list, struct iommu_table_group_link, 1687 next); 1688 struct pnv_ioda_pe *pe = container_of(tgl->table_group, 1689 struct pnv_ioda_pe, table_group); 1690 __be64 __iomem *invalidate = rm ? 1691 (__be64 __iomem *)pe->phb->ioda.tce_inval_reg_phys : 1692 pe->phb->ioda.tce_inval_reg; 1693 unsigned long start, end, inc; 1694 const unsigned shift = tbl->it_page_shift; 1695 1696 start = __pa(((__be64 *)tbl->it_base) + index - tbl->it_offset); 1697 end = __pa(((__be64 *)tbl->it_base) + index - tbl->it_offset + 1698 npages - 1); 1699 1700 /* BML uses this case for p6/p7/galaxy2: Shift addr and put in node */ 1701 if (tbl->it_busno) { 1702 start <<= shift; 1703 end <<= shift; 1704 inc = 128ull << shift; 1705 start |= tbl->it_busno; 1706 end |= tbl->it_busno; 1707 } else if (tbl->it_type & TCE_PCI_SWINV_PAIR) { 1708 /* p7ioc-style invalidation, 2 TCEs per write */ 1709 start |= (1ull << 63); 1710 end |= (1ull << 63); 1711 inc = 16; 1712 } else { 1713 /* Default (older HW) */ 1714 inc = 128; 1715 } 1716 1717 end |= inc - 1; /* round up end to be different than start */ 1718 1719 mb(); /* Ensure above stores are visible */ 1720 while (start <= end) { 1721 if (rm) 1722 __raw_rm_writeq(cpu_to_be64(start), invalidate); 1723 else 1724 __raw_writeq(cpu_to_be64(start), invalidate); 1725 start += inc; 1726 } 1727 1728 /* 1729 * The iommu layer will do another mb() for us on build() 1730 * and we don't care on free() 1731 */ 1732 } 1733 1734 static int pnv_ioda1_tce_build(struct iommu_table *tbl, long index, 1735 long npages, unsigned long uaddr, 1736 enum dma_data_direction direction, 1737 struct dma_attrs *attrs) 1738 { 1739 int ret = pnv_tce_build(tbl, index, npages, uaddr, direction, 1740 attrs); 1741 1742 if (!ret && (tbl->it_type & TCE_PCI_SWINV_CREATE)) 1743 pnv_pci_ioda1_tce_invalidate(tbl, index, npages, false); 1744 1745 return ret; 1746 } 1747 1748 #ifdef CONFIG_IOMMU_API 1749 static int pnv_ioda1_tce_xchg(struct iommu_table *tbl, long index, 1750 unsigned long *hpa, enum dma_data_direction *direction) 1751 { 1752 long ret = pnv_tce_xchg(tbl, index, hpa, direction); 1753 1754 if (!ret && (tbl->it_type & 1755 (TCE_PCI_SWINV_CREATE | TCE_PCI_SWINV_FREE))) 1756 pnv_pci_ioda1_tce_invalidate(tbl, index, 1, false); 1757 1758 return ret; 1759 } 1760 #endif 1761 1762 static void pnv_ioda1_tce_free(struct iommu_table *tbl, long index, 1763 long npages) 1764 { 1765 pnv_tce_free(tbl, index, npages); 1766 1767 if (tbl->it_type & TCE_PCI_SWINV_FREE) 1768 pnv_pci_ioda1_tce_invalidate(tbl, index, npages, false); 1769 } 1770 1771 static struct iommu_table_ops pnv_ioda1_iommu_ops = { 1772 .set = pnv_ioda1_tce_build, 1773 #ifdef CONFIG_IOMMU_API 1774 .exchange = pnv_ioda1_tce_xchg, 1775 #endif 1776 .clear = pnv_ioda1_tce_free, 1777 .get = pnv_tce_get, 1778 }; 1779 1780 static inline void pnv_pci_ioda2_tce_invalidate_entire(struct pnv_ioda_pe *pe) 1781 { 1782 /* 01xb - invalidate TCEs that match the specified PE# */ 1783 unsigned long val = (0x4ull << 60) | (pe->pe_number & 0xFF); 1784 struct pnv_phb *phb = pe->phb; 1785 1786 if (!phb->ioda.tce_inval_reg) 1787 return; 1788 1789 mb(); /* Ensure above stores are visible */ 1790 __raw_writeq(cpu_to_be64(val), phb->ioda.tce_inval_reg); 1791 } 1792 1793 static void pnv_pci_ioda2_do_tce_invalidate(unsigned pe_number, bool rm, 1794 __be64 __iomem *invalidate, unsigned shift, 1795 unsigned long index, unsigned long npages) 1796 { 1797 unsigned long start, end, inc; 1798 1799 /* We'll invalidate DMA address in PE scope */ 1800 start = 0x2ull << 60; 1801 start |= (pe_number & 0xFF); 1802 end = start; 1803 1804 /* Figure out the start, end and step */ 1805 start |= (index << shift); 1806 end |= ((index + npages - 1) << shift); 1807 inc = (0x1ull << shift); 1808 mb(); 1809 1810 while (start <= end) { 1811 if (rm) 1812 __raw_rm_writeq(cpu_to_be64(start), invalidate); 1813 else 1814 __raw_writeq(cpu_to_be64(start), invalidate); 1815 start += inc; 1816 } 1817 } 1818 1819 static void pnv_pci_ioda2_tce_invalidate(struct iommu_table *tbl, 1820 unsigned long index, unsigned long npages, bool rm) 1821 { 1822 struct iommu_table_group_link *tgl; 1823 1824 list_for_each_entry_rcu(tgl, &tbl->it_group_list, next) { 1825 struct pnv_ioda_pe *pe = container_of(tgl->table_group, 1826 struct pnv_ioda_pe, table_group); 1827 __be64 __iomem *invalidate = rm ? 1828 (__be64 __iomem *)pe->phb->ioda.tce_inval_reg_phys : 1829 pe->phb->ioda.tce_inval_reg; 1830 1831 pnv_pci_ioda2_do_tce_invalidate(pe->pe_number, rm, 1832 invalidate, tbl->it_page_shift, 1833 index, npages); 1834 } 1835 } 1836 1837 static int pnv_ioda2_tce_build(struct iommu_table *tbl, long index, 1838 long npages, unsigned long uaddr, 1839 enum dma_data_direction direction, 1840 struct dma_attrs *attrs) 1841 { 1842 int ret = pnv_tce_build(tbl, index, npages, uaddr, direction, 1843 attrs); 1844 1845 if (!ret && (tbl->it_type & TCE_PCI_SWINV_CREATE)) 1846 pnv_pci_ioda2_tce_invalidate(tbl, index, npages, false); 1847 1848 return ret; 1849 } 1850 1851 #ifdef CONFIG_IOMMU_API 1852 static int pnv_ioda2_tce_xchg(struct iommu_table *tbl, long index, 1853 unsigned long *hpa, enum dma_data_direction *direction) 1854 { 1855 long ret = pnv_tce_xchg(tbl, index, hpa, direction); 1856 1857 if (!ret && (tbl->it_type & 1858 (TCE_PCI_SWINV_CREATE | TCE_PCI_SWINV_FREE))) 1859 pnv_pci_ioda2_tce_invalidate(tbl, index, 1, false); 1860 1861 return ret; 1862 } 1863 #endif 1864 1865 static void pnv_ioda2_tce_free(struct iommu_table *tbl, long index, 1866 long npages) 1867 { 1868 pnv_tce_free(tbl, index, npages); 1869 1870 if (tbl->it_type & TCE_PCI_SWINV_FREE) 1871 pnv_pci_ioda2_tce_invalidate(tbl, index, npages, false); 1872 } 1873 1874 static void pnv_ioda2_table_free(struct iommu_table *tbl) 1875 { 1876 pnv_pci_ioda2_table_free_pages(tbl); 1877 iommu_free_table(tbl, "pnv"); 1878 } 1879 1880 static struct iommu_table_ops pnv_ioda2_iommu_ops = { 1881 .set = pnv_ioda2_tce_build, 1882 #ifdef CONFIG_IOMMU_API 1883 .exchange = pnv_ioda2_tce_xchg, 1884 #endif 1885 .clear = pnv_ioda2_tce_free, 1886 .get = pnv_tce_get, 1887 .free = pnv_ioda2_table_free, 1888 }; 1889 1890 static void pnv_pci_ioda_setup_dma_pe(struct pnv_phb *phb, 1891 struct pnv_ioda_pe *pe, unsigned int base, 1892 unsigned int segs) 1893 { 1894 1895 struct page *tce_mem = NULL; 1896 struct iommu_table *tbl; 1897 unsigned int i; 1898 int64_t rc; 1899 void *addr; 1900 1901 /* XXX FIXME: Handle 64-bit only DMA devices */ 1902 /* XXX FIXME: Provide 64-bit DMA facilities & non-4K TCE tables etc.. */ 1903 /* XXX FIXME: Allocate multi-level tables on PHB3 */ 1904 1905 /* We shouldn't already have a 32-bit DMA associated */ 1906 if (WARN_ON(pe->tce32_seg >= 0)) 1907 return; 1908 1909 tbl = pnv_pci_table_alloc(phb->hose->node); 1910 iommu_register_group(&pe->table_group, phb->hose->global_number, 1911 pe->pe_number); 1912 pnv_pci_link_table_and_group(phb->hose->node, 0, tbl, &pe->table_group); 1913 1914 /* Grab a 32-bit TCE table */ 1915 pe->tce32_seg = base; 1916 pe_info(pe, " Setting up 32-bit TCE table at %08x..%08x\n", 1917 (base << 28), ((base + segs) << 28) - 1); 1918 1919 /* XXX Currently, we allocate one big contiguous table for the 1920 * TCEs. We only really need one chunk per 256M of TCE space 1921 * (ie per segment) but that's an optimization for later, it 1922 * requires some added smarts with our get/put_tce implementation 1923 */ 1924 tce_mem = alloc_pages_node(phb->hose->node, GFP_KERNEL, 1925 get_order(TCE32_TABLE_SIZE * segs)); 1926 if (!tce_mem) { 1927 pe_err(pe, " Failed to allocate a 32-bit TCE memory\n"); 1928 goto fail; 1929 } 1930 addr = page_address(tce_mem); 1931 memset(addr, 0, TCE32_TABLE_SIZE * segs); 1932 1933 /* Configure HW */ 1934 for (i = 0; i < segs; i++) { 1935 rc = opal_pci_map_pe_dma_window(phb->opal_id, 1936 pe->pe_number, 1937 base + i, 1, 1938 __pa(addr) + TCE32_TABLE_SIZE * i, 1939 TCE32_TABLE_SIZE, 0x1000); 1940 if (rc) { 1941 pe_err(pe, " Failed to configure 32-bit TCE table," 1942 " err %ld\n", rc); 1943 goto fail; 1944 } 1945 } 1946 1947 /* Setup linux iommu table */ 1948 pnv_pci_setup_iommu_table(tbl, addr, TCE32_TABLE_SIZE * segs, 1949 base << 28, IOMMU_PAGE_SHIFT_4K); 1950 1951 /* OPAL variant of P7IOC SW invalidated TCEs */ 1952 if (phb->ioda.tce_inval_reg) 1953 tbl->it_type |= (TCE_PCI_SWINV_CREATE | 1954 TCE_PCI_SWINV_FREE | 1955 TCE_PCI_SWINV_PAIR); 1956 1957 tbl->it_ops = &pnv_ioda1_iommu_ops; 1958 pe->table_group.tce32_start = tbl->it_offset << tbl->it_page_shift; 1959 pe->table_group.tce32_size = tbl->it_size << tbl->it_page_shift; 1960 iommu_init_table(tbl, phb->hose->node); 1961 1962 if (pe->flags & PNV_IODA_PE_DEV) { 1963 /* 1964 * Setting table base here only for carrying iommu_group 1965 * further down to let iommu_add_device() do the job. 1966 * pnv_pci_ioda_dma_dev_setup will override it later anyway. 1967 */ 1968 set_iommu_table_base(&pe->pdev->dev, tbl); 1969 iommu_add_device(&pe->pdev->dev); 1970 } else if (pe->flags & (PNV_IODA_PE_BUS | PNV_IODA_PE_BUS_ALL)) 1971 pnv_ioda_setup_bus_dma(pe, pe->pbus); 1972 1973 return; 1974 fail: 1975 /* XXX Failure: Try to fallback to 64-bit only ? */ 1976 if (pe->tce32_seg >= 0) 1977 pe->tce32_seg = -1; 1978 if (tce_mem) 1979 __free_pages(tce_mem, get_order(TCE32_TABLE_SIZE * segs)); 1980 if (tbl) { 1981 pnv_pci_unlink_table_and_group(tbl, &pe->table_group); 1982 iommu_free_table(tbl, "pnv"); 1983 } 1984 } 1985 1986 static long pnv_pci_ioda2_set_window(struct iommu_table_group *table_group, 1987 int num, struct iommu_table *tbl) 1988 { 1989 struct pnv_ioda_pe *pe = container_of(table_group, struct pnv_ioda_pe, 1990 table_group); 1991 struct pnv_phb *phb = pe->phb; 1992 int64_t rc; 1993 const unsigned long size = tbl->it_indirect_levels ? 1994 tbl->it_level_size : tbl->it_size; 1995 const __u64 start_addr = tbl->it_offset << tbl->it_page_shift; 1996 const __u64 win_size = tbl->it_size << tbl->it_page_shift; 1997 1998 pe_info(pe, "Setting up window#%d %llx..%llx pg=%x\n", num, 1999 start_addr, start_addr + win_size - 1, 2000 IOMMU_PAGE_SIZE(tbl)); 2001 2002 /* 2003 * Map TCE table through TVT. The TVE index is the PE number 2004 * shifted by 1 bit for 32-bits DMA space. 2005 */ 2006 rc = opal_pci_map_pe_dma_window(phb->opal_id, 2007 pe->pe_number, 2008 (pe->pe_number << 1) + num, 2009 tbl->it_indirect_levels + 1, 2010 __pa(tbl->it_base), 2011 size << 3, 2012 IOMMU_PAGE_SIZE(tbl)); 2013 if (rc) { 2014 pe_err(pe, "Failed to configure TCE table, err %ld\n", rc); 2015 return rc; 2016 } 2017 2018 pnv_pci_link_table_and_group(phb->hose->node, num, 2019 tbl, &pe->table_group); 2020 pnv_pci_ioda2_tce_invalidate_entire(pe); 2021 2022 return 0; 2023 } 2024 2025 static void pnv_pci_ioda2_set_bypass(struct pnv_ioda_pe *pe, bool enable) 2026 { 2027 uint16_t window_id = (pe->pe_number << 1 ) + 1; 2028 int64_t rc; 2029 2030 pe_info(pe, "%sabling 64-bit DMA bypass\n", enable ? "En" : "Dis"); 2031 if (enable) { 2032 phys_addr_t top = memblock_end_of_DRAM(); 2033 2034 top = roundup_pow_of_two(top); 2035 rc = opal_pci_map_pe_dma_window_real(pe->phb->opal_id, 2036 pe->pe_number, 2037 window_id, 2038 pe->tce_bypass_base, 2039 top); 2040 } else { 2041 rc = opal_pci_map_pe_dma_window_real(pe->phb->opal_id, 2042 pe->pe_number, 2043 window_id, 2044 pe->tce_bypass_base, 2045 0); 2046 } 2047 if (rc) 2048 pe_err(pe, "OPAL error %lld configuring bypass window\n", rc); 2049 else 2050 pe->tce_bypass_enabled = enable; 2051 } 2052 2053 static long pnv_pci_ioda2_table_alloc_pages(int nid, __u64 bus_offset, 2054 __u32 page_shift, __u64 window_size, __u32 levels, 2055 struct iommu_table *tbl); 2056 2057 static long pnv_pci_ioda2_create_table(struct iommu_table_group *table_group, 2058 int num, __u32 page_shift, __u64 window_size, __u32 levels, 2059 struct iommu_table **ptbl) 2060 { 2061 struct pnv_ioda_pe *pe = container_of(table_group, struct pnv_ioda_pe, 2062 table_group); 2063 int nid = pe->phb->hose->node; 2064 __u64 bus_offset = num ? pe->tce_bypass_base : table_group->tce32_start; 2065 long ret; 2066 struct iommu_table *tbl; 2067 2068 tbl = pnv_pci_table_alloc(nid); 2069 if (!tbl) 2070 return -ENOMEM; 2071 2072 ret = pnv_pci_ioda2_table_alloc_pages(nid, 2073 bus_offset, page_shift, window_size, 2074 levels, tbl); 2075 if (ret) { 2076 iommu_free_table(tbl, "pnv"); 2077 return ret; 2078 } 2079 2080 tbl->it_ops = &pnv_ioda2_iommu_ops; 2081 if (pe->phb->ioda.tce_inval_reg) 2082 tbl->it_type |= (TCE_PCI_SWINV_CREATE | TCE_PCI_SWINV_FREE); 2083 2084 *ptbl = tbl; 2085 2086 return 0; 2087 } 2088 2089 static long pnv_pci_ioda2_setup_default_config(struct pnv_ioda_pe *pe) 2090 { 2091 struct iommu_table *tbl = NULL; 2092 long rc; 2093 2094 rc = pnv_pci_ioda2_create_table(&pe->table_group, 0, 2095 IOMMU_PAGE_SHIFT_4K, 2096 pe->table_group.tce32_size, 2097 POWERNV_IOMMU_DEFAULT_LEVELS, &tbl); 2098 if (rc) { 2099 pe_err(pe, "Failed to create 32-bit TCE table, err %ld", 2100 rc); 2101 return rc; 2102 } 2103 2104 iommu_init_table(tbl, pe->phb->hose->node); 2105 2106 rc = pnv_pci_ioda2_set_window(&pe->table_group, 0, tbl); 2107 if (rc) { 2108 pe_err(pe, "Failed to configure 32-bit TCE table, err %ld\n", 2109 rc); 2110 pnv_ioda2_table_free(tbl); 2111 return rc; 2112 } 2113 2114 if (!pnv_iommu_bypass_disabled) 2115 pnv_pci_ioda2_set_bypass(pe, true); 2116 2117 /* OPAL variant of PHB3 invalidated TCEs */ 2118 if (pe->phb->ioda.tce_inval_reg) 2119 tbl->it_type |= (TCE_PCI_SWINV_CREATE | TCE_PCI_SWINV_FREE); 2120 2121 /* 2122 * Setting table base here only for carrying iommu_group 2123 * further down to let iommu_add_device() do the job. 2124 * pnv_pci_ioda_dma_dev_setup will override it later anyway. 2125 */ 2126 if (pe->flags & PNV_IODA_PE_DEV) 2127 set_iommu_table_base(&pe->pdev->dev, tbl); 2128 2129 return 0; 2130 } 2131 2132 #if defined(CONFIG_IOMMU_API) || defined(CONFIG_PCI_IOV) 2133 static long pnv_pci_ioda2_unset_window(struct iommu_table_group *table_group, 2134 int num) 2135 { 2136 struct pnv_ioda_pe *pe = container_of(table_group, struct pnv_ioda_pe, 2137 table_group); 2138 struct pnv_phb *phb = pe->phb; 2139 long ret; 2140 2141 pe_info(pe, "Removing DMA window #%d\n", num); 2142 2143 ret = opal_pci_map_pe_dma_window(phb->opal_id, pe->pe_number, 2144 (pe->pe_number << 1) + num, 2145 0/* levels */, 0/* table address */, 2146 0/* table size */, 0/* page size */); 2147 if (ret) 2148 pe_warn(pe, "Unmapping failed, ret = %ld\n", ret); 2149 else 2150 pnv_pci_ioda2_tce_invalidate_entire(pe); 2151 2152 pnv_pci_unlink_table_and_group(table_group->tables[num], table_group); 2153 2154 return ret; 2155 } 2156 #endif 2157 2158 #ifdef CONFIG_IOMMU_API 2159 static unsigned long pnv_pci_ioda2_get_table_size(__u32 page_shift, 2160 __u64 window_size, __u32 levels) 2161 { 2162 unsigned long bytes = 0; 2163 const unsigned window_shift = ilog2(window_size); 2164 unsigned entries_shift = window_shift - page_shift; 2165 unsigned table_shift = entries_shift + 3; 2166 unsigned long tce_table_size = max(0x1000UL, 1UL << table_shift); 2167 unsigned long direct_table_size; 2168 2169 if (!levels || (levels > POWERNV_IOMMU_MAX_LEVELS) || 2170 (window_size > memory_hotplug_max()) || 2171 !is_power_of_2(window_size)) 2172 return 0; 2173 2174 /* Calculate a direct table size from window_size and levels */ 2175 entries_shift = (entries_shift + levels - 1) / levels; 2176 table_shift = entries_shift + 3; 2177 table_shift = max_t(unsigned, table_shift, PAGE_SHIFT); 2178 direct_table_size = 1UL << table_shift; 2179 2180 for ( ; levels; --levels) { 2181 bytes += _ALIGN_UP(tce_table_size, direct_table_size); 2182 2183 tce_table_size /= direct_table_size; 2184 tce_table_size <<= 3; 2185 tce_table_size = _ALIGN_UP(tce_table_size, direct_table_size); 2186 } 2187 2188 return bytes; 2189 } 2190 2191 static void pnv_ioda2_take_ownership(struct iommu_table_group *table_group) 2192 { 2193 struct pnv_ioda_pe *pe = container_of(table_group, struct pnv_ioda_pe, 2194 table_group); 2195 /* Store @tbl as pnv_pci_ioda2_unset_window() resets it */ 2196 struct iommu_table *tbl = pe->table_group.tables[0]; 2197 2198 pnv_pci_ioda2_set_bypass(pe, false); 2199 pnv_pci_ioda2_unset_window(&pe->table_group, 0); 2200 pnv_ioda2_table_free(tbl); 2201 } 2202 2203 static void pnv_ioda2_release_ownership(struct iommu_table_group *table_group) 2204 { 2205 struct pnv_ioda_pe *pe = container_of(table_group, struct pnv_ioda_pe, 2206 table_group); 2207 2208 pnv_pci_ioda2_setup_default_config(pe); 2209 } 2210 2211 static struct iommu_table_group_ops pnv_pci_ioda2_ops = { 2212 .get_table_size = pnv_pci_ioda2_get_table_size, 2213 .create_table = pnv_pci_ioda2_create_table, 2214 .set_window = pnv_pci_ioda2_set_window, 2215 .unset_window = pnv_pci_ioda2_unset_window, 2216 .take_ownership = pnv_ioda2_take_ownership, 2217 .release_ownership = pnv_ioda2_release_ownership, 2218 }; 2219 #endif 2220 2221 static void pnv_pci_ioda_setup_opal_tce_kill(struct pnv_phb *phb) 2222 { 2223 const __be64 *swinvp; 2224 2225 /* OPAL variant of PHB3 invalidated TCEs */ 2226 swinvp = of_get_property(phb->hose->dn, "ibm,opal-tce-kill", NULL); 2227 if (!swinvp) 2228 return; 2229 2230 phb->ioda.tce_inval_reg_phys = be64_to_cpup(swinvp); 2231 phb->ioda.tce_inval_reg = ioremap(phb->ioda.tce_inval_reg_phys, 8); 2232 } 2233 2234 static __be64 *pnv_pci_ioda2_table_do_alloc_pages(int nid, unsigned shift, 2235 unsigned levels, unsigned long limit, 2236 unsigned long *current_offset) 2237 { 2238 struct page *tce_mem = NULL; 2239 __be64 *addr, *tmp; 2240 unsigned order = max_t(unsigned, shift, PAGE_SHIFT) - PAGE_SHIFT; 2241 unsigned long allocated = 1UL << (order + PAGE_SHIFT); 2242 unsigned entries = 1UL << (shift - 3); 2243 long i; 2244 2245 tce_mem = alloc_pages_node(nid, GFP_KERNEL, order); 2246 if (!tce_mem) { 2247 pr_err("Failed to allocate a TCE memory, order=%d\n", order); 2248 return NULL; 2249 } 2250 addr = page_address(tce_mem); 2251 memset(addr, 0, allocated); 2252 2253 --levels; 2254 if (!levels) { 2255 *current_offset += allocated; 2256 return addr; 2257 } 2258 2259 for (i = 0; i < entries; ++i) { 2260 tmp = pnv_pci_ioda2_table_do_alloc_pages(nid, shift, 2261 levels, limit, current_offset); 2262 if (!tmp) 2263 break; 2264 2265 addr[i] = cpu_to_be64(__pa(tmp) | 2266 TCE_PCI_READ | TCE_PCI_WRITE); 2267 2268 if (*current_offset >= limit) 2269 break; 2270 } 2271 2272 return addr; 2273 } 2274 2275 static void pnv_pci_ioda2_table_do_free_pages(__be64 *addr, 2276 unsigned long size, unsigned level); 2277 2278 static long pnv_pci_ioda2_table_alloc_pages(int nid, __u64 bus_offset, 2279 __u32 page_shift, __u64 window_size, __u32 levels, 2280 struct iommu_table *tbl) 2281 { 2282 void *addr; 2283 unsigned long offset = 0, level_shift; 2284 const unsigned window_shift = ilog2(window_size); 2285 unsigned entries_shift = window_shift - page_shift; 2286 unsigned table_shift = max_t(unsigned, entries_shift + 3, PAGE_SHIFT); 2287 const unsigned long tce_table_size = 1UL << table_shift; 2288 2289 if (!levels || (levels > POWERNV_IOMMU_MAX_LEVELS)) 2290 return -EINVAL; 2291 2292 if ((window_size > memory_hotplug_max()) || !is_power_of_2(window_size)) 2293 return -EINVAL; 2294 2295 /* Adjust direct table size from window_size and levels */ 2296 entries_shift = (entries_shift + levels - 1) / levels; 2297 level_shift = entries_shift + 3; 2298 level_shift = max_t(unsigned, level_shift, PAGE_SHIFT); 2299 2300 /* Allocate TCE table */ 2301 addr = pnv_pci_ioda2_table_do_alloc_pages(nid, level_shift, 2302 levels, tce_table_size, &offset); 2303 2304 /* addr==NULL means that the first level allocation failed */ 2305 if (!addr) 2306 return -ENOMEM; 2307 2308 /* 2309 * First level was allocated but some lower level failed as 2310 * we did not allocate as much as we wanted, 2311 * release partially allocated table. 2312 */ 2313 if (offset < tce_table_size) { 2314 pnv_pci_ioda2_table_do_free_pages(addr, 2315 1ULL << (level_shift - 3), levels - 1); 2316 return -ENOMEM; 2317 } 2318 2319 /* Setup linux iommu table */ 2320 pnv_pci_setup_iommu_table(tbl, addr, tce_table_size, bus_offset, 2321 page_shift); 2322 tbl->it_level_size = 1ULL << (level_shift - 3); 2323 tbl->it_indirect_levels = levels - 1; 2324 tbl->it_allocated_size = offset; 2325 2326 pr_devel("Created TCE table: ws=%08llx ts=%lx @%08llx\n", 2327 window_size, tce_table_size, bus_offset); 2328 2329 return 0; 2330 } 2331 2332 static void pnv_pci_ioda2_table_do_free_pages(__be64 *addr, 2333 unsigned long size, unsigned level) 2334 { 2335 const unsigned long addr_ul = (unsigned long) addr & 2336 ~(TCE_PCI_READ | TCE_PCI_WRITE); 2337 2338 if (level) { 2339 long i; 2340 u64 *tmp = (u64 *) addr_ul; 2341 2342 for (i = 0; i < size; ++i) { 2343 unsigned long hpa = be64_to_cpu(tmp[i]); 2344 2345 if (!(hpa & (TCE_PCI_READ | TCE_PCI_WRITE))) 2346 continue; 2347 2348 pnv_pci_ioda2_table_do_free_pages(__va(hpa), size, 2349 level - 1); 2350 } 2351 } 2352 2353 free_pages(addr_ul, get_order(size << 3)); 2354 } 2355 2356 static void pnv_pci_ioda2_table_free_pages(struct iommu_table *tbl) 2357 { 2358 const unsigned long size = tbl->it_indirect_levels ? 2359 tbl->it_level_size : tbl->it_size; 2360 2361 if (!tbl->it_size) 2362 return; 2363 2364 pnv_pci_ioda2_table_do_free_pages((__be64 *)tbl->it_base, size, 2365 tbl->it_indirect_levels); 2366 } 2367 2368 static void pnv_pci_ioda2_setup_dma_pe(struct pnv_phb *phb, 2369 struct pnv_ioda_pe *pe) 2370 { 2371 int64_t rc; 2372 2373 /* We shouldn't already have a 32-bit DMA associated */ 2374 if (WARN_ON(pe->tce32_seg >= 0)) 2375 return; 2376 2377 /* TVE #1 is selected by PCI address bit 59 */ 2378 pe->tce_bypass_base = 1ull << 59; 2379 2380 iommu_register_group(&pe->table_group, phb->hose->global_number, 2381 pe->pe_number); 2382 2383 /* The PE will reserve all possible 32-bits space */ 2384 pe->tce32_seg = 0; 2385 pe_info(pe, "Setting up 32-bit TCE table at 0..%08x\n", 2386 phb->ioda.m32_pci_base); 2387 2388 /* Setup linux iommu table */ 2389 pe->table_group.tce32_start = 0; 2390 pe->table_group.tce32_size = phb->ioda.m32_pci_base; 2391 pe->table_group.max_dynamic_windows_supported = 2392 IOMMU_TABLE_GROUP_MAX_TABLES; 2393 pe->table_group.max_levels = POWERNV_IOMMU_MAX_LEVELS; 2394 pe->table_group.pgsizes = SZ_4K | SZ_64K | SZ_16M; 2395 #ifdef CONFIG_IOMMU_API 2396 pe->table_group.ops = &pnv_pci_ioda2_ops; 2397 #endif 2398 2399 rc = pnv_pci_ioda2_setup_default_config(pe); 2400 if (rc) { 2401 if (pe->tce32_seg >= 0) 2402 pe->tce32_seg = -1; 2403 return; 2404 } 2405 2406 if (pe->flags & PNV_IODA_PE_DEV) 2407 iommu_add_device(&pe->pdev->dev); 2408 else if (pe->flags & (PNV_IODA_PE_BUS | PNV_IODA_PE_BUS_ALL)) 2409 pnv_ioda_setup_bus_dma(pe, pe->pbus); 2410 } 2411 2412 static void pnv_ioda_setup_dma(struct pnv_phb *phb) 2413 { 2414 struct pci_controller *hose = phb->hose; 2415 unsigned int residual, remaining, segs, tw, base; 2416 struct pnv_ioda_pe *pe; 2417 2418 /* If we have more PE# than segments available, hand out one 2419 * per PE until we run out and let the rest fail. If not, 2420 * then we assign at least one segment per PE, plus more based 2421 * on the amount of devices under that PE 2422 */ 2423 if (phb->ioda.dma_pe_count > phb->ioda.tce32_count) 2424 residual = 0; 2425 else 2426 residual = phb->ioda.tce32_count - 2427 phb->ioda.dma_pe_count; 2428 2429 pr_info("PCI: Domain %04x has %ld available 32-bit DMA segments\n", 2430 hose->global_number, phb->ioda.tce32_count); 2431 pr_info("PCI: %d PE# for a total weight of %d\n", 2432 phb->ioda.dma_pe_count, phb->ioda.dma_weight); 2433 2434 pnv_pci_ioda_setup_opal_tce_kill(phb); 2435 2436 /* Walk our PE list and configure their DMA segments, hand them 2437 * out one base segment plus any residual segments based on 2438 * weight 2439 */ 2440 remaining = phb->ioda.tce32_count; 2441 tw = phb->ioda.dma_weight; 2442 base = 0; 2443 list_for_each_entry(pe, &phb->ioda.pe_dma_list, dma_link) { 2444 if (!pe->dma_weight) 2445 continue; 2446 if (!remaining) { 2447 pe_warn(pe, "No DMA32 resources available\n"); 2448 continue; 2449 } 2450 segs = 1; 2451 if (residual) { 2452 segs += ((pe->dma_weight * residual) + (tw / 2)) / tw; 2453 if (segs > remaining) 2454 segs = remaining; 2455 } 2456 2457 /* 2458 * For IODA2 compliant PHB3, we needn't care about the weight. 2459 * The all available 32-bits DMA space will be assigned to 2460 * the specific PE. 2461 */ 2462 if (phb->type == PNV_PHB_IODA1) { 2463 pe_info(pe, "DMA weight %d, assigned %d DMA32 segments\n", 2464 pe->dma_weight, segs); 2465 pnv_pci_ioda_setup_dma_pe(phb, pe, base, segs); 2466 } else { 2467 pe_info(pe, "Assign DMA32 space\n"); 2468 segs = 0; 2469 pnv_pci_ioda2_setup_dma_pe(phb, pe); 2470 } 2471 2472 remaining -= segs; 2473 base += segs; 2474 } 2475 } 2476 2477 #ifdef CONFIG_PCI_MSI 2478 static void pnv_ioda2_msi_eoi(struct irq_data *d) 2479 { 2480 unsigned int hw_irq = (unsigned int)irqd_to_hwirq(d); 2481 struct irq_chip *chip = irq_data_get_irq_chip(d); 2482 struct pnv_phb *phb = container_of(chip, struct pnv_phb, 2483 ioda.irq_chip); 2484 int64_t rc; 2485 2486 rc = opal_pci_msi_eoi(phb->opal_id, hw_irq); 2487 WARN_ON_ONCE(rc); 2488 2489 icp_native_eoi(d); 2490 } 2491 2492 2493 static void set_msi_irq_chip(struct pnv_phb *phb, unsigned int virq) 2494 { 2495 struct irq_data *idata; 2496 struct irq_chip *ichip; 2497 2498 if (phb->type != PNV_PHB_IODA2) 2499 return; 2500 2501 if (!phb->ioda.irq_chip_init) { 2502 /* 2503 * First time we setup an MSI IRQ, we need to setup the 2504 * corresponding IRQ chip to route correctly. 2505 */ 2506 idata = irq_get_irq_data(virq); 2507 ichip = irq_data_get_irq_chip(idata); 2508 phb->ioda.irq_chip_init = 1; 2509 phb->ioda.irq_chip = *ichip; 2510 phb->ioda.irq_chip.irq_eoi = pnv_ioda2_msi_eoi; 2511 } 2512 irq_set_chip(virq, &phb->ioda.irq_chip); 2513 } 2514 2515 #ifdef CONFIG_CXL_BASE 2516 2517 struct device_node *pnv_pci_get_phb_node(struct pci_dev *dev) 2518 { 2519 struct pci_controller *hose = pci_bus_to_host(dev->bus); 2520 2521 return of_node_get(hose->dn); 2522 } 2523 EXPORT_SYMBOL(pnv_pci_get_phb_node); 2524 2525 int pnv_phb_to_cxl_mode(struct pci_dev *dev, uint64_t mode) 2526 { 2527 struct pci_controller *hose = pci_bus_to_host(dev->bus); 2528 struct pnv_phb *phb = hose->private_data; 2529 struct pnv_ioda_pe *pe; 2530 int rc; 2531 2532 pe = pnv_ioda_get_pe(dev); 2533 if (!pe) 2534 return -ENODEV; 2535 2536 pe_info(pe, "Switching PHB to CXL\n"); 2537 2538 rc = opal_pci_set_phb_cxl_mode(phb->opal_id, mode, pe->pe_number); 2539 if (rc) 2540 dev_err(&dev->dev, "opal_pci_set_phb_cxl_mode failed: %i\n", rc); 2541 2542 return rc; 2543 } 2544 EXPORT_SYMBOL(pnv_phb_to_cxl_mode); 2545 2546 /* Find PHB for cxl dev and allocate MSI hwirqs? 2547 * Returns the absolute hardware IRQ number 2548 */ 2549 int pnv_cxl_alloc_hwirqs(struct pci_dev *dev, int num) 2550 { 2551 struct pci_controller *hose = pci_bus_to_host(dev->bus); 2552 struct pnv_phb *phb = hose->private_data; 2553 int hwirq = msi_bitmap_alloc_hwirqs(&phb->msi_bmp, num); 2554 2555 if (hwirq < 0) { 2556 dev_warn(&dev->dev, "Failed to find a free MSI\n"); 2557 return -ENOSPC; 2558 } 2559 2560 return phb->msi_base + hwirq; 2561 } 2562 EXPORT_SYMBOL(pnv_cxl_alloc_hwirqs); 2563 2564 void pnv_cxl_release_hwirqs(struct pci_dev *dev, int hwirq, int num) 2565 { 2566 struct pci_controller *hose = pci_bus_to_host(dev->bus); 2567 struct pnv_phb *phb = hose->private_data; 2568 2569 msi_bitmap_free_hwirqs(&phb->msi_bmp, hwirq - phb->msi_base, num); 2570 } 2571 EXPORT_SYMBOL(pnv_cxl_release_hwirqs); 2572 2573 void pnv_cxl_release_hwirq_ranges(struct cxl_irq_ranges *irqs, 2574 struct pci_dev *dev) 2575 { 2576 struct pci_controller *hose = pci_bus_to_host(dev->bus); 2577 struct pnv_phb *phb = hose->private_data; 2578 int i, hwirq; 2579 2580 for (i = 1; i < CXL_IRQ_RANGES; i++) { 2581 if (!irqs->range[i]) 2582 continue; 2583 pr_devel("cxl release irq range 0x%x: offset: 0x%lx limit: %ld\n", 2584 i, irqs->offset[i], 2585 irqs->range[i]); 2586 hwirq = irqs->offset[i] - phb->msi_base; 2587 msi_bitmap_free_hwirqs(&phb->msi_bmp, hwirq, 2588 irqs->range[i]); 2589 } 2590 } 2591 EXPORT_SYMBOL(pnv_cxl_release_hwirq_ranges); 2592 2593 int pnv_cxl_alloc_hwirq_ranges(struct cxl_irq_ranges *irqs, 2594 struct pci_dev *dev, int num) 2595 { 2596 struct pci_controller *hose = pci_bus_to_host(dev->bus); 2597 struct pnv_phb *phb = hose->private_data; 2598 int i, hwirq, try; 2599 2600 memset(irqs, 0, sizeof(struct cxl_irq_ranges)); 2601 2602 /* 0 is reserved for the multiplexed PSL DSI interrupt */ 2603 for (i = 1; i < CXL_IRQ_RANGES && num; i++) { 2604 try = num; 2605 while (try) { 2606 hwirq = msi_bitmap_alloc_hwirqs(&phb->msi_bmp, try); 2607 if (hwirq >= 0) 2608 break; 2609 try /= 2; 2610 } 2611 if (!try) 2612 goto fail; 2613 2614 irqs->offset[i] = phb->msi_base + hwirq; 2615 irqs->range[i] = try; 2616 pr_devel("cxl alloc irq range 0x%x: offset: 0x%lx limit: %li\n", 2617 i, irqs->offset[i], irqs->range[i]); 2618 num -= try; 2619 } 2620 if (num) 2621 goto fail; 2622 2623 return 0; 2624 fail: 2625 pnv_cxl_release_hwirq_ranges(irqs, dev); 2626 return -ENOSPC; 2627 } 2628 EXPORT_SYMBOL(pnv_cxl_alloc_hwirq_ranges); 2629 2630 int pnv_cxl_get_irq_count(struct pci_dev *dev) 2631 { 2632 struct pci_controller *hose = pci_bus_to_host(dev->bus); 2633 struct pnv_phb *phb = hose->private_data; 2634 2635 return phb->msi_bmp.irq_count; 2636 } 2637 EXPORT_SYMBOL(pnv_cxl_get_irq_count); 2638 2639 int pnv_cxl_ioda_msi_setup(struct pci_dev *dev, unsigned int hwirq, 2640 unsigned int virq) 2641 { 2642 struct pci_controller *hose = pci_bus_to_host(dev->bus); 2643 struct pnv_phb *phb = hose->private_data; 2644 unsigned int xive_num = hwirq - phb->msi_base; 2645 struct pnv_ioda_pe *pe; 2646 int rc; 2647 2648 if (!(pe = pnv_ioda_get_pe(dev))) 2649 return -ENODEV; 2650 2651 /* Assign XIVE to PE */ 2652 rc = opal_pci_set_xive_pe(phb->opal_id, pe->pe_number, xive_num); 2653 if (rc) { 2654 pe_warn(pe, "%s: OPAL error %d setting msi_base 0x%x " 2655 "hwirq 0x%x XIVE 0x%x PE\n", 2656 pci_name(dev), rc, phb->msi_base, hwirq, xive_num); 2657 return -EIO; 2658 } 2659 set_msi_irq_chip(phb, virq); 2660 2661 return 0; 2662 } 2663 EXPORT_SYMBOL(pnv_cxl_ioda_msi_setup); 2664 #endif 2665 2666 static int pnv_pci_ioda_msi_setup(struct pnv_phb *phb, struct pci_dev *dev, 2667 unsigned int hwirq, unsigned int virq, 2668 unsigned int is_64, struct msi_msg *msg) 2669 { 2670 struct pnv_ioda_pe *pe = pnv_ioda_get_pe(dev); 2671 unsigned int xive_num = hwirq - phb->msi_base; 2672 __be32 data; 2673 int rc; 2674 2675 /* No PE assigned ? bail out ... no MSI for you ! */ 2676 if (pe == NULL) 2677 return -ENXIO; 2678 2679 /* Check if we have an MVE */ 2680 if (pe->mve_number < 0) 2681 return -ENXIO; 2682 2683 /* Force 32-bit MSI on some broken devices */ 2684 if (dev->no_64bit_msi) 2685 is_64 = 0; 2686 2687 /* Assign XIVE to PE */ 2688 rc = opal_pci_set_xive_pe(phb->opal_id, pe->pe_number, xive_num); 2689 if (rc) { 2690 pr_warn("%s: OPAL error %d setting XIVE %d PE\n", 2691 pci_name(dev), rc, xive_num); 2692 return -EIO; 2693 } 2694 2695 if (is_64) { 2696 __be64 addr64; 2697 2698 rc = opal_get_msi_64(phb->opal_id, pe->mve_number, xive_num, 1, 2699 &addr64, &data); 2700 if (rc) { 2701 pr_warn("%s: OPAL error %d getting 64-bit MSI data\n", 2702 pci_name(dev), rc); 2703 return -EIO; 2704 } 2705 msg->address_hi = be64_to_cpu(addr64) >> 32; 2706 msg->address_lo = be64_to_cpu(addr64) & 0xfffffffful; 2707 } else { 2708 __be32 addr32; 2709 2710 rc = opal_get_msi_32(phb->opal_id, pe->mve_number, xive_num, 1, 2711 &addr32, &data); 2712 if (rc) { 2713 pr_warn("%s: OPAL error %d getting 32-bit MSI data\n", 2714 pci_name(dev), rc); 2715 return -EIO; 2716 } 2717 msg->address_hi = 0; 2718 msg->address_lo = be32_to_cpu(addr32); 2719 } 2720 msg->data = be32_to_cpu(data); 2721 2722 set_msi_irq_chip(phb, virq); 2723 2724 pr_devel("%s: %s-bit MSI on hwirq %x (xive #%d)," 2725 " address=%x_%08x data=%x PE# %d\n", 2726 pci_name(dev), is_64 ? "64" : "32", hwirq, xive_num, 2727 msg->address_hi, msg->address_lo, data, pe->pe_number); 2728 2729 return 0; 2730 } 2731 2732 static void pnv_pci_init_ioda_msis(struct pnv_phb *phb) 2733 { 2734 unsigned int count; 2735 const __be32 *prop = of_get_property(phb->hose->dn, 2736 "ibm,opal-msi-ranges", NULL); 2737 if (!prop) { 2738 /* BML Fallback */ 2739 prop = of_get_property(phb->hose->dn, "msi-ranges", NULL); 2740 } 2741 if (!prop) 2742 return; 2743 2744 phb->msi_base = be32_to_cpup(prop); 2745 count = be32_to_cpup(prop + 1); 2746 if (msi_bitmap_alloc(&phb->msi_bmp, count, phb->hose->dn)) { 2747 pr_err("PCI %d: Failed to allocate MSI bitmap !\n", 2748 phb->hose->global_number); 2749 return; 2750 } 2751 2752 phb->msi_setup = pnv_pci_ioda_msi_setup; 2753 phb->msi32_support = 1; 2754 pr_info(" Allocated bitmap for %d MSIs (base IRQ 0x%x)\n", 2755 count, phb->msi_base); 2756 } 2757 #else 2758 static void pnv_pci_init_ioda_msis(struct pnv_phb *phb) { } 2759 #endif /* CONFIG_PCI_MSI */ 2760 2761 #ifdef CONFIG_PCI_IOV 2762 static void pnv_pci_ioda_fixup_iov_resources(struct pci_dev *pdev) 2763 { 2764 struct pci_controller *hose; 2765 struct pnv_phb *phb; 2766 struct resource *res; 2767 int i; 2768 resource_size_t size; 2769 struct pci_dn *pdn; 2770 int mul, total_vfs; 2771 2772 if (!pdev->is_physfn || pdev->is_added) 2773 return; 2774 2775 hose = pci_bus_to_host(pdev->bus); 2776 phb = hose->private_data; 2777 2778 pdn = pci_get_pdn(pdev); 2779 pdn->vfs_expanded = 0; 2780 2781 total_vfs = pci_sriov_get_totalvfs(pdev); 2782 pdn->m64_per_iov = 1; 2783 mul = phb->ioda.total_pe; 2784 2785 for (i = 0; i < PCI_SRIOV_NUM_BARS; i++) { 2786 res = &pdev->resource[i + PCI_IOV_RESOURCES]; 2787 if (!res->flags || res->parent) 2788 continue; 2789 if (!pnv_pci_is_mem_pref_64(res->flags)) { 2790 dev_warn(&pdev->dev, " non M64 VF BAR%d: %pR\n", 2791 i, res); 2792 continue; 2793 } 2794 2795 size = pci_iov_resource_size(pdev, i + PCI_IOV_RESOURCES); 2796 2797 /* bigger than 64M */ 2798 if (size > (1 << 26)) { 2799 dev_info(&pdev->dev, "PowerNV: VF BAR%d: %pR IOV size is bigger than 64M, roundup power2\n", 2800 i, res); 2801 pdn->m64_per_iov = M64_PER_IOV; 2802 mul = roundup_pow_of_two(total_vfs); 2803 break; 2804 } 2805 } 2806 2807 for (i = 0; i < PCI_SRIOV_NUM_BARS; i++) { 2808 res = &pdev->resource[i + PCI_IOV_RESOURCES]; 2809 if (!res->flags || res->parent) 2810 continue; 2811 if (!pnv_pci_is_mem_pref_64(res->flags)) { 2812 dev_warn(&pdev->dev, "Skipping expanding VF BAR%d: %pR\n", 2813 i, res); 2814 continue; 2815 } 2816 2817 dev_dbg(&pdev->dev, " Fixing VF BAR%d: %pR to\n", i, res); 2818 size = pci_iov_resource_size(pdev, i + PCI_IOV_RESOURCES); 2819 res->end = res->start + size * mul - 1; 2820 dev_dbg(&pdev->dev, " %pR\n", res); 2821 dev_info(&pdev->dev, "VF BAR%d: %pR (expanded to %d VFs for PE alignment)", 2822 i, res, mul); 2823 } 2824 pdn->vfs_expanded = mul; 2825 } 2826 #endif /* CONFIG_PCI_IOV */ 2827 2828 /* 2829 * This function is supposed to be called on basis of PE from top 2830 * to bottom style. So the the I/O or MMIO segment assigned to 2831 * parent PE could be overrided by its child PEs if necessary. 2832 */ 2833 static void pnv_ioda_setup_pe_seg(struct pci_controller *hose, 2834 struct pnv_ioda_pe *pe) 2835 { 2836 struct pnv_phb *phb = hose->private_data; 2837 struct pci_bus_region region; 2838 struct resource *res; 2839 int i, index; 2840 int rc; 2841 2842 /* 2843 * NOTE: We only care PCI bus based PE for now. For PCI 2844 * device based PE, for example SRIOV sensitive VF should 2845 * be figured out later. 2846 */ 2847 BUG_ON(!(pe->flags & (PNV_IODA_PE_BUS | PNV_IODA_PE_BUS_ALL))); 2848 2849 pci_bus_for_each_resource(pe->pbus, res, i) { 2850 if (!res || !res->flags || 2851 res->start > res->end) 2852 continue; 2853 2854 if (res->flags & IORESOURCE_IO) { 2855 region.start = res->start - phb->ioda.io_pci_base; 2856 region.end = res->end - phb->ioda.io_pci_base; 2857 index = region.start / phb->ioda.io_segsize; 2858 2859 while (index < phb->ioda.total_pe && 2860 region.start <= region.end) { 2861 phb->ioda.io_segmap[index] = pe->pe_number; 2862 rc = opal_pci_map_pe_mmio_window(phb->opal_id, 2863 pe->pe_number, OPAL_IO_WINDOW_TYPE, 0, index); 2864 if (rc != OPAL_SUCCESS) { 2865 pr_err("%s: OPAL error %d when mapping IO " 2866 "segment #%d to PE#%d\n", 2867 __func__, rc, index, pe->pe_number); 2868 break; 2869 } 2870 2871 region.start += phb->ioda.io_segsize; 2872 index++; 2873 } 2874 } else if ((res->flags & IORESOURCE_MEM) && 2875 !pnv_pci_is_mem_pref_64(res->flags)) { 2876 region.start = res->start - 2877 hose->mem_offset[0] - 2878 phb->ioda.m32_pci_base; 2879 region.end = res->end - 2880 hose->mem_offset[0] - 2881 phb->ioda.m32_pci_base; 2882 index = region.start / phb->ioda.m32_segsize; 2883 2884 while (index < phb->ioda.total_pe && 2885 region.start <= region.end) { 2886 phb->ioda.m32_segmap[index] = pe->pe_number; 2887 rc = opal_pci_map_pe_mmio_window(phb->opal_id, 2888 pe->pe_number, OPAL_M32_WINDOW_TYPE, 0, index); 2889 if (rc != OPAL_SUCCESS) { 2890 pr_err("%s: OPAL error %d when mapping M32 " 2891 "segment#%d to PE#%d", 2892 __func__, rc, index, pe->pe_number); 2893 break; 2894 } 2895 2896 region.start += phb->ioda.m32_segsize; 2897 index++; 2898 } 2899 } 2900 } 2901 } 2902 2903 static void pnv_pci_ioda_setup_seg(void) 2904 { 2905 struct pci_controller *tmp, *hose; 2906 struct pnv_phb *phb; 2907 struct pnv_ioda_pe *pe; 2908 2909 list_for_each_entry_safe(hose, tmp, &hose_list, list_node) { 2910 phb = hose->private_data; 2911 list_for_each_entry(pe, &phb->ioda.pe_list, list) { 2912 pnv_ioda_setup_pe_seg(hose, pe); 2913 } 2914 } 2915 } 2916 2917 static void pnv_pci_ioda_setup_DMA(void) 2918 { 2919 struct pci_controller *hose, *tmp; 2920 struct pnv_phb *phb; 2921 2922 list_for_each_entry_safe(hose, tmp, &hose_list, list_node) { 2923 pnv_ioda_setup_dma(hose->private_data); 2924 2925 /* Mark the PHB initialization done */ 2926 phb = hose->private_data; 2927 phb->initialized = 1; 2928 } 2929 } 2930 2931 static void pnv_pci_ioda_create_dbgfs(void) 2932 { 2933 #ifdef CONFIG_DEBUG_FS 2934 struct pci_controller *hose, *tmp; 2935 struct pnv_phb *phb; 2936 char name[16]; 2937 2938 list_for_each_entry_safe(hose, tmp, &hose_list, list_node) { 2939 phb = hose->private_data; 2940 2941 sprintf(name, "PCI%04x", hose->global_number); 2942 phb->dbgfs = debugfs_create_dir(name, powerpc_debugfs_root); 2943 if (!phb->dbgfs) 2944 pr_warning("%s: Error on creating debugfs on PHB#%x\n", 2945 __func__, hose->global_number); 2946 } 2947 #endif /* CONFIG_DEBUG_FS */ 2948 } 2949 2950 static void pnv_pci_ioda_fixup(void) 2951 { 2952 pnv_pci_ioda_setup_PEs(); 2953 pnv_pci_ioda_setup_seg(); 2954 pnv_pci_ioda_setup_DMA(); 2955 2956 pnv_pci_ioda_create_dbgfs(); 2957 2958 #ifdef CONFIG_EEH 2959 eeh_init(); 2960 eeh_addr_cache_build(); 2961 #endif 2962 } 2963 2964 /* 2965 * Returns the alignment for I/O or memory windows for P2P 2966 * bridges. That actually depends on how PEs are segmented. 2967 * For now, we return I/O or M32 segment size for PE sensitive 2968 * P2P bridges. Otherwise, the default values (4KiB for I/O, 2969 * 1MiB for memory) will be returned. 2970 * 2971 * The current PCI bus might be put into one PE, which was 2972 * create against the parent PCI bridge. For that case, we 2973 * needn't enlarge the alignment so that we can save some 2974 * resources. 2975 */ 2976 static resource_size_t pnv_pci_window_alignment(struct pci_bus *bus, 2977 unsigned long type) 2978 { 2979 struct pci_dev *bridge; 2980 struct pci_controller *hose = pci_bus_to_host(bus); 2981 struct pnv_phb *phb = hose->private_data; 2982 int num_pci_bridges = 0; 2983 2984 bridge = bus->self; 2985 while (bridge) { 2986 if (pci_pcie_type(bridge) == PCI_EXP_TYPE_PCI_BRIDGE) { 2987 num_pci_bridges++; 2988 if (num_pci_bridges >= 2) 2989 return 1; 2990 } 2991 2992 bridge = bridge->bus->self; 2993 } 2994 2995 /* We fail back to M32 if M64 isn't supported */ 2996 if (phb->ioda.m64_segsize && 2997 pnv_pci_is_mem_pref_64(type)) 2998 return phb->ioda.m64_segsize; 2999 if (type & IORESOURCE_MEM) 3000 return phb->ioda.m32_segsize; 3001 3002 return phb->ioda.io_segsize; 3003 } 3004 3005 #ifdef CONFIG_PCI_IOV 3006 static resource_size_t pnv_pci_iov_resource_alignment(struct pci_dev *pdev, 3007 int resno) 3008 { 3009 struct pci_dn *pdn = pci_get_pdn(pdev); 3010 resource_size_t align, iov_align; 3011 3012 iov_align = resource_size(&pdev->resource[resno]); 3013 if (iov_align) 3014 return iov_align; 3015 3016 align = pci_iov_resource_size(pdev, resno); 3017 if (pdn->vfs_expanded) 3018 return pdn->vfs_expanded * align; 3019 3020 return align; 3021 } 3022 #endif /* CONFIG_PCI_IOV */ 3023 3024 /* Prevent enabling devices for which we couldn't properly 3025 * assign a PE 3026 */ 3027 static bool pnv_pci_enable_device_hook(struct pci_dev *dev) 3028 { 3029 struct pci_controller *hose = pci_bus_to_host(dev->bus); 3030 struct pnv_phb *phb = hose->private_data; 3031 struct pci_dn *pdn; 3032 3033 /* The function is probably called while the PEs have 3034 * not be created yet. For example, resource reassignment 3035 * during PCI probe period. We just skip the check if 3036 * PEs isn't ready. 3037 */ 3038 if (!phb->initialized) 3039 return true; 3040 3041 pdn = pci_get_pdn(dev); 3042 if (!pdn || pdn->pe_number == IODA_INVALID_PE) 3043 return false; 3044 3045 return true; 3046 } 3047 3048 static u32 pnv_ioda_bdfn_to_pe(struct pnv_phb *phb, struct pci_bus *bus, 3049 u32 devfn) 3050 { 3051 return phb->ioda.pe_rmap[(bus->number << 8) | devfn]; 3052 } 3053 3054 static void pnv_pci_ioda_shutdown(struct pci_controller *hose) 3055 { 3056 struct pnv_phb *phb = hose->private_data; 3057 3058 opal_pci_reset(phb->opal_id, OPAL_RESET_PCI_IODA_TABLE, 3059 OPAL_ASSERT_RESET); 3060 } 3061 3062 static const struct pci_controller_ops pnv_pci_ioda_controller_ops = { 3063 .dma_dev_setup = pnv_pci_dma_dev_setup, 3064 #ifdef CONFIG_PCI_MSI 3065 .setup_msi_irqs = pnv_setup_msi_irqs, 3066 .teardown_msi_irqs = pnv_teardown_msi_irqs, 3067 #endif 3068 .enable_device_hook = pnv_pci_enable_device_hook, 3069 .window_alignment = pnv_pci_window_alignment, 3070 .reset_secondary_bus = pnv_pci_reset_secondary_bus, 3071 .dma_set_mask = pnv_pci_ioda_dma_set_mask, 3072 .shutdown = pnv_pci_ioda_shutdown, 3073 }; 3074 3075 static void __init pnv_pci_init_ioda_phb(struct device_node *np, 3076 u64 hub_id, int ioda_type) 3077 { 3078 struct pci_controller *hose; 3079 struct pnv_phb *phb; 3080 unsigned long size, m32map_off, pemap_off, iomap_off = 0; 3081 const __be64 *prop64; 3082 const __be32 *prop32; 3083 int len; 3084 u64 phb_id; 3085 void *aux; 3086 long rc; 3087 3088 pr_info("Initializing IODA%d OPAL PHB %s\n", ioda_type, np->full_name); 3089 3090 prop64 = of_get_property(np, "ibm,opal-phbid", NULL); 3091 if (!prop64) { 3092 pr_err(" Missing \"ibm,opal-phbid\" property !\n"); 3093 return; 3094 } 3095 phb_id = be64_to_cpup(prop64); 3096 pr_debug(" PHB-ID : 0x%016llx\n", phb_id); 3097 3098 phb = memblock_virt_alloc(sizeof(struct pnv_phb), 0); 3099 3100 /* Allocate PCI controller */ 3101 phb->hose = hose = pcibios_alloc_controller(np); 3102 if (!phb->hose) { 3103 pr_err(" Can't allocate PCI controller for %s\n", 3104 np->full_name); 3105 memblock_free(__pa(phb), sizeof(struct pnv_phb)); 3106 return; 3107 } 3108 3109 spin_lock_init(&phb->lock); 3110 prop32 = of_get_property(np, "bus-range", &len); 3111 if (prop32 && len == 8) { 3112 hose->first_busno = be32_to_cpu(prop32[0]); 3113 hose->last_busno = be32_to_cpu(prop32[1]); 3114 } else { 3115 pr_warn(" Broken <bus-range> on %s\n", np->full_name); 3116 hose->first_busno = 0; 3117 hose->last_busno = 0xff; 3118 } 3119 hose->private_data = phb; 3120 phb->hub_id = hub_id; 3121 phb->opal_id = phb_id; 3122 phb->type = ioda_type; 3123 mutex_init(&phb->ioda.pe_alloc_mutex); 3124 3125 /* Detect specific models for error handling */ 3126 if (of_device_is_compatible(np, "ibm,p7ioc-pciex")) 3127 phb->model = PNV_PHB_MODEL_P7IOC; 3128 else if (of_device_is_compatible(np, "ibm,power8-pciex")) 3129 phb->model = PNV_PHB_MODEL_PHB3; 3130 else 3131 phb->model = PNV_PHB_MODEL_UNKNOWN; 3132 3133 /* Parse 32-bit and IO ranges (if any) */ 3134 pci_process_bridge_OF_ranges(hose, np, !hose->global_number); 3135 3136 /* Get registers */ 3137 phb->regs = of_iomap(np, 0); 3138 if (phb->regs == NULL) 3139 pr_err(" Failed to map registers !\n"); 3140 3141 /* Initialize more IODA stuff */ 3142 phb->ioda.total_pe = 1; 3143 prop32 = of_get_property(np, "ibm,opal-num-pes", NULL); 3144 if (prop32) 3145 phb->ioda.total_pe = be32_to_cpup(prop32); 3146 prop32 = of_get_property(np, "ibm,opal-reserved-pe", NULL); 3147 if (prop32) 3148 phb->ioda.reserved_pe = be32_to_cpup(prop32); 3149 3150 /* Parse 64-bit MMIO range */ 3151 pnv_ioda_parse_m64_window(phb); 3152 3153 phb->ioda.m32_size = resource_size(&hose->mem_resources[0]); 3154 /* FW Has already off top 64k of M32 space (MSI space) */ 3155 phb->ioda.m32_size += 0x10000; 3156 3157 phb->ioda.m32_segsize = phb->ioda.m32_size / phb->ioda.total_pe; 3158 phb->ioda.m32_pci_base = hose->mem_resources[0].start - hose->mem_offset[0]; 3159 phb->ioda.io_size = hose->pci_io_size; 3160 phb->ioda.io_segsize = phb->ioda.io_size / phb->ioda.total_pe; 3161 phb->ioda.io_pci_base = 0; /* XXX calculate this ? */ 3162 3163 /* Allocate aux data & arrays. We don't have IO ports on PHB3 */ 3164 size = _ALIGN_UP(phb->ioda.total_pe / 8, sizeof(unsigned long)); 3165 m32map_off = size; 3166 size += phb->ioda.total_pe * sizeof(phb->ioda.m32_segmap[0]); 3167 if (phb->type == PNV_PHB_IODA1) { 3168 iomap_off = size; 3169 size += phb->ioda.total_pe * sizeof(phb->ioda.io_segmap[0]); 3170 } 3171 pemap_off = size; 3172 size += phb->ioda.total_pe * sizeof(struct pnv_ioda_pe); 3173 aux = memblock_virt_alloc(size, 0); 3174 phb->ioda.pe_alloc = aux; 3175 phb->ioda.m32_segmap = aux + m32map_off; 3176 if (phb->type == PNV_PHB_IODA1) 3177 phb->ioda.io_segmap = aux + iomap_off; 3178 phb->ioda.pe_array = aux + pemap_off; 3179 set_bit(phb->ioda.reserved_pe, phb->ioda.pe_alloc); 3180 3181 INIT_LIST_HEAD(&phb->ioda.pe_dma_list); 3182 INIT_LIST_HEAD(&phb->ioda.pe_list); 3183 mutex_init(&phb->ioda.pe_list_mutex); 3184 3185 /* Calculate how many 32-bit TCE segments we have */ 3186 phb->ioda.tce32_count = phb->ioda.m32_pci_base >> 28; 3187 3188 #if 0 /* We should really do that ... */ 3189 rc = opal_pci_set_phb_mem_window(opal->phb_id, 3190 window_type, 3191 window_num, 3192 starting_real_address, 3193 starting_pci_address, 3194 segment_size); 3195 #endif 3196 3197 pr_info(" %03d (%03d) PE's M32: 0x%x [segment=0x%x]\n", 3198 phb->ioda.total_pe, phb->ioda.reserved_pe, 3199 phb->ioda.m32_size, phb->ioda.m32_segsize); 3200 if (phb->ioda.m64_size) 3201 pr_info(" M64: 0x%lx [segment=0x%lx]\n", 3202 phb->ioda.m64_size, phb->ioda.m64_segsize); 3203 if (phb->ioda.io_size) 3204 pr_info(" IO: 0x%x [segment=0x%x]\n", 3205 phb->ioda.io_size, phb->ioda.io_segsize); 3206 3207 3208 phb->hose->ops = &pnv_pci_ops; 3209 phb->get_pe_state = pnv_ioda_get_pe_state; 3210 phb->freeze_pe = pnv_ioda_freeze_pe; 3211 phb->unfreeze_pe = pnv_ioda_unfreeze_pe; 3212 3213 /* Setup RID -> PE mapping function */ 3214 phb->bdfn_to_pe = pnv_ioda_bdfn_to_pe; 3215 3216 /* Setup TCEs */ 3217 phb->dma_dev_setup = pnv_pci_ioda_dma_dev_setup; 3218 phb->dma_get_required_mask = pnv_pci_ioda_dma_get_required_mask; 3219 3220 /* Setup MSI support */ 3221 pnv_pci_init_ioda_msis(phb); 3222 3223 /* 3224 * We pass the PCI probe flag PCI_REASSIGN_ALL_RSRC here 3225 * to let the PCI core do resource assignment. It's supposed 3226 * that the PCI core will do correct I/O and MMIO alignment 3227 * for the P2P bridge bars so that each PCI bus (excluding 3228 * the child P2P bridges) can form individual PE. 3229 */ 3230 ppc_md.pcibios_fixup = pnv_pci_ioda_fixup; 3231 hose->controller_ops = pnv_pci_ioda_controller_ops; 3232 3233 #ifdef CONFIG_PCI_IOV 3234 ppc_md.pcibios_fixup_sriov = pnv_pci_ioda_fixup_iov_resources; 3235 ppc_md.pcibios_iov_resource_alignment = pnv_pci_iov_resource_alignment; 3236 #endif 3237 3238 pci_add_flags(PCI_REASSIGN_ALL_RSRC); 3239 3240 /* Reset IODA tables to a clean state */ 3241 rc = opal_pci_reset(phb_id, OPAL_RESET_PCI_IODA_TABLE, OPAL_ASSERT_RESET); 3242 if (rc) 3243 pr_warning(" OPAL Error %ld performing IODA table reset !\n", rc); 3244 3245 /* If we're running in kdump kerenl, the previous kerenl never 3246 * shutdown PCI devices correctly. We already got IODA table 3247 * cleaned out. So we have to issue PHB reset to stop all PCI 3248 * transactions from previous kerenl. 3249 */ 3250 if (is_kdump_kernel()) { 3251 pr_info(" Issue PHB reset ...\n"); 3252 pnv_eeh_phb_reset(hose, EEH_RESET_FUNDAMENTAL); 3253 pnv_eeh_phb_reset(hose, EEH_RESET_DEACTIVATE); 3254 } 3255 3256 /* Remove M64 resource if we can't configure it successfully */ 3257 if (!phb->init_m64 || phb->init_m64(phb)) 3258 hose->mem_resources[1].flags = 0; 3259 } 3260 3261 void __init pnv_pci_init_ioda2_phb(struct device_node *np) 3262 { 3263 pnv_pci_init_ioda_phb(np, 0, PNV_PHB_IODA2); 3264 } 3265 3266 void __init pnv_pci_init_ioda_hub(struct device_node *np) 3267 { 3268 struct device_node *phbn; 3269 const __be64 *prop64; 3270 u64 hub_id; 3271 3272 pr_info("Probing IODA IO-Hub %s\n", np->full_name); 3273 3274 prop64 = of_get_property(np, "ibm,opal-hubid", NULL); 3275 if (!prop64) { 3276 pr_err(" Missing \"ibm,opal-hubid\" property !\n"); 3277 return; 3278 } 3279 hub_id = be64_to_cpup(prop64); 3280 pr_devel(" HUB-ID : 0x%016llx\n", hub_id); 3281 3282 /* Count child PHBs */ 3283 for_each_child_of_node(np, phbn) { 3284 /* Look for IODA1 PHBs */ 3285 if (of_device_is_compatible(phbn, "ibm,ioda-phb")) 3286 pnv_pci_init_ioda_phb(phbn, hub_id, PNV_PHB_IODA1); 3287 } 3288 } 3289