1 /* 2 * Support PCI/PCIe on PowerNV platforms 3 * 4 * Copyright 2011 Benjamin Herrenschmidt, IBM Corp. 5 * 6 * This program is free software; you can redistribute it and/or 7 * modify it under the terms of the GNU General Public License 8 * as published by the Free Software Foundation; either version 9 * 2 of the License, or (at your option) any later version. 10 */ 11 12 #undef DEBUG 13 14 #include <linux/kernel.h> 15 #include <linux/pci.h> 16 #include <linux/crash_dump.h> 17 #include <linux/debugfs.h> 18 #include <linux/delay.h> 19 #include <linux/string.h> 20 #include <linux/init.h> 21 #include <linux/bootmem.h> 22 #include <linux/irq.h> 23 #include <linux/io.h> 24 #include <linux/msi.h> 25 #include <linux/memblock.h> 26 #include <linux/iommu.h> 27 #include <linux/rculist.h> 28 #include <linux/sizes.h> 29 30 #include <asm/sections.h> 31 #include <asm/io.h> 32 #include <asm/prom.h> 33 #include <asm/pci-bridge.h> 34 #include <asm/machdep.h> 35 #include <asm/msi_bitmap.h> 36 #include <asm/ppc-pci.h> 37 #include <asm/opal.h> 38 #include <asm/iommu.h> 39 #include <asm/tce.h> 40 #include <asm/xics.h> 41 #include <asm/debug.h> 42 #include <asm/firmware.h> 43 #include <asm/pnv-pci.h> 44 #include <asm/mmzone.h> 45 46 #include <misc/cxl-base.h> 47 48 #include "powernv.h" 49 #include "pci.h" 50 51 #define PNV_IODA1_M64_NUM 16 /* Number of M64 BARs */ 52 #define PNV_IODA1_M64_SEGS 8 /* Segments per M64 BAR */ 53 #define PNV_IODA1_DMA32_SEGSIZE 0x10000000 54 55 #define POWERNV_IOMMU_DEFAULT_LEVELS 1 56 #define POWERNV_IOMMU_MAX_LEVELS 5 57 58 static void pnv_pci_ioda2_table_free_pages(struct iommu_table *tbl); 59 60 void pe_level_printk(const struct pnv_ioda_pe *pe, const char *level, 61 const char *fmt, ...) 62 { 63 struct va_format vaf; 64 va_list args; 65 char pfix[32]; 66 67 va_start(args, fmt); 68 69 vaf.fmt = fmt; 70 vaf.va = &args; 71 72 if (pe->flags & PNV_IODA_PE_DEV) 73 strlcpy(pfix, dev_name(&pe->pdev->dev), sizeof(pfix)); 74 else if (pe->flags & (PNV_IODA_PE_BUS | PNV_IODA_PE_BUS_ALL)) 75 sprintf(pfix, "%04x:%02x ", 76 pci_domain_nr(pe->pbus), pe->pbus->number); 77 #ifdef CONFIG_PCI_IOV 78 else if (pe->flags & PNV_IODA_PE_VF) 79 sprintf(pfix, "%04x:%02x:%2x.%d", 80 pci_domain_nr(pe->parent_dev->bus), 81 (pe->rid & 0xff00) >> 8, 82 PCI_SLOT(pe->rid), PCI_FUNC(pe->rid)); 83 #endif /* CONFIG_PCI_IOV*/ 84 85 printk("%spci %s: [PE# %.3d] %pV", 86 level, pfix, pe->pe_number, &vaf); 87 88 va_end(args); 89 } 90 91 static bool pnv_iommu_bypass_disabled __read_mostly; 92 93 static int __init iommu_setup(char *str) 94 { 95 if (!str) 96 return -EINVAL; 97 98 while (*str) { 99 if (!strncmp(str, "nobypass", 8)) { 100 pnv_iommu_bypass_disabled = true; 101 pr_info("PowerNV: IOMMU bypass window disabled.\n"); 102 break; 103 } 104 str += strcspn(str, ","); 105 if (*str == ',') 106 str++; 107 } 108 109 return 0; 110 } 111 early_param("iommu", iommu_setup); 112 113 static inline bool pnv_pci_is_mem_pref_64(unsigned long flags) 114 { 115 return ((flags & (IORESOURCE_MEM_64 | IORESOURCE_PREFETCH)) == 116 (IORESOURCE_MEM_64 | IORESOURCE_PREFETCH)); 117 } 118 119 static struct pnv_ioda_pe *pnv_ioda_init_pe(struct pnv_phb *phb, int pe_no) 120 { 121 phb->ioda.pe_array[pe_no].phb = phb; 122 phb->ioda.pe_array[pe_no].pe_number = pe_no; 123 124 return &phb->ioda.pe_array[pe_no]; 125 } 126 127 static void pnv_ioda_reserve_pe(struct pnv_phb *phb, int pe_no) 128 { 129 if (!(pe_no >= 0 && pe_no < phb->ioda.total_pe_num)) { 130 pr_warn("%s: Invalid PE %d on PHB#%x\n", 131 __func__, pe_no, phb->hose->global_number); 132 return; 133 } 134 135 if (test_and_set_bit(pe_no, phb->ioda.pe_alloc)) 136 pr_debug("%s: PE %d was reserved on PHB#%x\n", 137 __func__, pe_no, phb->hose->global_number); 138 139 pnv_ioda_init_pe(phb, pe_no); 140 } 141 142 static struct pnv_ioda_pe *pnv_ioda_alloc_pe(struct pnv_phb *phb) 143 { 144 unsigned long pe; 145 146 do { 147 pe = find_next_zero_bit(phb->ioda.pe_alloc, 148 phb->ioda.total_pe_num, 0); 149 if (pe >= phb->ioda.total_pe_num) 150 return NULL; 151 } while(test_and_set_bit(pe, phb->ioda.pe_alloc)); 152 153 return pnv_ioda_init_pe(phb, pe); 154 } 155 156 static void pnv_ioda_free_pe(struct pnv_ioda_pe *pe) 157 { 158 struct pnv_phb *phb = pe->phb; 159 160 WARN_ON(pe->pdev); 161 162 memset(pe, 0, sizeof(struct pnv_ioda_pe)); 163 clear_bit(pe->pe_number, phb->ioda.pe_alloc); 164 } 165 166 /* The default M64 BAR is shared by all PEs */ 167 static int pnv_ioda2_init_m64(struct pnv_phb *phb) 168 { 169 const char *desc; 170 struct resource *r; 171 s64 rc; 172 173 /* Configure the default M64 BAR */ 174 rc = opal_pci_set_phb_mem_window(phb->opal_id, 175 OPAL_M64_WINDOW_TYPE, 176 phb->ioda.m64_bar_idx, 177 phb->ioda.m64_base, 178 0, /* unused */ 179 phb->ioda.m64_size); 180 if (rc != OPAL_SUCCESS) { 181 desc = "configuring"; 182 goto fail; 183 } 184 185 /* Enable the default M64 BAR */ 186 rc = opal_pci_phb_mmio_enable(phb->opal_id, 187 OPAL_M64_WINDOW_TYPE, 188 phb->ioda.m64_bar_idx, 189 OPAL_ENABLE_M64_SPLIT); 190 if (rc != OPAL_SUCCESS) { 191 desc = "enabling"; 192 goto fail; 193 } 194 195 /* Mark the M64 BAR assigned */ 196 set_bit(phb->ioda.m64_bar_idx, &phb->ioda.m64_bar_alloc); 197 198 /* 199 * Strip off the segment used by the reserved PE, which is 200 * expected to be 0 or last one of PE capabicity. 201 */ 202 r = &phb->hose->mem_resources[1]; 203 if (phb->ioda.reserved_pe_idx == 0) 204 r->start += phb->ioda.m64_segsize; 205 else if (phb->ioda.reserved_pe_idx == (phb->ioda.total_pe_num - 1)) 206 r->end -= phb->ioda.m64_segsize; 207 else 208 pr_warn(" Cannot strip M64 segment for reserved PE#%d\n", 209 phb->ioda.reserved_pe_idx); 210 211 return 0; 212 213 fail: 214 pr_warn(" Failure %lld %s M64 BAR#%d\n", 215 rc, desc, phb->ioda.m64_bar_idx); 216 opal_pci_phb_mmio_enable(phb->opal_id, 217 OPAL_M64_WINDOW_TYPE, 218 phb->ioda.m64_bar_idx, 219 OPAL_DISABLE_M64); 220 return -EIO; 221 } 222 223 static void pnv_ioda_reserve_dev_m64_pe(struct pci_dev *pdev, 224 unsigned long *pe_bitmap) 225 { 226 struct pci_controller *hose = pci_bus_to_host(pdev->bus); 227 struct pnv_phb *phb = hose->private_data; 228 struct resource *r; 229 resource_size_t base, sgsz, start, end; 230 int segno, i; 231 232 base = phb->ioda.m64_base; 233 sgsz = phb->ioda.m64_segsize; 234 for (i = 0; i <= PCI_ROM_RESOURCE; i++) { 235 r = &pdev->resource[i]; 236 if (!r->parent || !pnv_pci_is_mem_pref_64(r->flags)) 237 continue; 238 239 start = _ALIGN_DOWN(r->start - base, sgsz); 240 end = _ALIGN_UP(r->end - base, sgsz); 241 for (segno = start / sgsz; segno < end / sgsz; segno++) { 242 if (pe_bitmap) 243 set_bit(segno, pe_bitmap); 244 else 245 pnv_ioda_reserve_pe(phb, segno); 246 } 247 } 248 } 249 250 static int pnv_ioda1_init_m64(struct pnv_phb *phb) 251 { 252 struct resource *r; 253 int index; 254 255 /* 256 * There are 16 M64 BARs, each of which has 8 segments. So 257 * there are as many M64 segments as the maximum number of 258 * PEs, which is 128. 259 */ 260 for (index = 0; index < PNV_IODA1_M64_NUM; index++) { 261 unsigned long base, segsz = phb->ioda.m64_segsize; 262 int64_t rc; 263 264 base = phb->ioda.m64_base + 265 index * PNV_IODA1_M64_SEGS * segsz; 266 rc = opal_pci_set_phb_mem_window(phb->opal_id, 267 OPAL_M64_WINDOW_TYPE, index, base, 0, 268 PNV_IODA1_M64_SEGS * segsz); 269 if (rc != OPAL_SUCCESS) { 270 pr_warn(" Error %lld setting M64 PHB#%d-BAR#%d\n", 271 rc, phb->hose->global_number, index); 272 goto fail; 273 } 274 275 rc = opal_pci_phb_mmio_enable(phb->opal_id, 276 OPAL_M64_WINDOW_TYPE, index, 277 OPAL_ENABLE_M64_SPLIT); 278 if (rc != OPAL_SUCCESS) { 279 pr_warn(" Error %lld enabling M64 PHB#%d-BAR#%d\n", 280 rc, phb->hose->global_number, index); 281 goto fail; 282 } 283 } 284 285 /* 286 * Exclude the segment used by the reserved PE, which 287 * is expected to be 0 or last supported PE#. 288 */ 289 r = &phb->hose->mem_resources[1]; 290 if (phb->ioda.reserved_pe_idx == 0) 291 r->start += phb->ioda.m64_segsize; 292 else if (phb->ioda.reserved_pe_idx == (phb->ioda.total_pe_num - 1)) 293 r->end -= phb->ioda.m64_segsize; 294 else 295 WARN(1, "Wrong reserved PE#%d on PHB#%d\n", 296 phb->ioda.reserved_pe_idx, phb->hose->global_number); 297 298 return 0; 299 300 fail: 301 for ( ; index >= 0; index--) 302 opal_pci_phb_mmio_enable(phb->opal_id, 303 OPAL_M64_WINDOW_TYPE, index, OPAL_DISABLE_M64); 304 305 return -EIO; 306 } 307 308 static void pnv_ioda_reserve_m64_pe(struct pci_bus *bus, 309 unsigned long *pe_bitmap, 310 bool all) 311 { 312 struct pci_dev *pdev; 313 314 list_for_each_entry(pdev, &bus->devices, bus_list) { 315 pnv_ioda_reserve_dev_m64_pe(pdev, pe_bitmap); 316 317 if (all && pdev->subordinate) 318 pnv_ioda_reserve_m64_pe(pdev->subordinate, 319 pe_bitmap, all); 320 } 321 } 322 323 static struct pnv_ioda_pe *pnv_ioda_pick_m64_pe(struct pci_bus *bus, bool all) 324 { 325 struct pci_controller *hose = pci_bus_to_host(bus); 326 struct pnv_phb *phb = hose->private_data; 327 struct pnv_ioda_pe *master_pe, *pe; 328 unsigned long size, *pe_alloc; 329 int i; 330 331 /* Root bus shouldn't use M64 */ 332 if (pci_is_root_bus(bus)) 333 return NULL; 334 335 /* Allocate bitmap */ 336 size = _ALIGN_UP(phb->ioda.total_pe_num / 8, sizeof(unsigned long)); 337 pe_alloc = kzalloc(size, GFP_KERNEL); 338 if (!pe_alloc) { 339 pr_warn("%s: Out of memory !\n", 340 __func__); 341 return NULL; 342 } 343 344 /* Figure out reserved PE numbers by the PE */ 345 pnv_ioda_reserve_m64_pe(bus, pe_alloc, all); 346 347 /* 348 * the current bus might not own M64 window and that's all 349 * contributed by its child buses. For the case, we needn't 350 * pick M64 dependent PE#. 351 */ 352 if (bitmap_empty(pe_alloc, phb->ioda.total_pe_num)) { 353 kfree(pe_alloc); 354 return NULL; 355 } 356 357 /* 358 * Figure out the master PE and put all slave PEs to master 359 * PE's list to form compound PE. 360 */ 361 master_pe = NULL; 362 i = -1; 363 while ((i = find_next_bit(pe_alloc, phb->ioda.total_pe_num, i + 1)) < 364 phb->ioda.total_pe_num) { 365 pe = &phb->ioda.pe_array[i]; 366 367 phb->ioda.m64_segmap[pe->pe_number] = pe->pe_number; 368 if (!master_pe) { 369 pe->flags |= PNV_IODA_PE_MASTER; 370 INIT_LIST_HEAD(&pe->slaves); 371 master_pe = pe; 372 } else { 373 pe->flags |= PNV_IODA_PE_SLAVE; 374 pe->master = master_pe; 375 list_add_tail(&pe->list, &master_pe->slaves); 376 } 377 378 /* 379 * P7IOC supports M64DT, which helps mapping M64 segment 380 * to one particular PE#. However, PHB3 has fixed mapping 381 * between M64 segment and PE#. In order to have same logic 382 * for P7IOC and PHB3, we enforce fixed mapping between M64 383 * segment and PE# on P7IOC. 384 */ 385 if (phb->type == PNV_PHB_IODA1) { 386 int64_t rc; 387 388 rc = opal_pci_map_pe_mmio_window(phb->opal_id, 389 pe->pe_number, OPAL_M64_WINDOW_TYPE, 390 pe->pe_number / PNV_IODA1_M64_SEGS, 391 pe->pe_number % PNV_IODA1_M64_SEGS); 392 if (rc != OPAL_SUCCESS) 393 pr_warn("%s: Error %lld mapping M64 for PHB#%d-PE#%d\n", 394 __func__, rc, phb->hose->global_number, 395 pe->pe_number); 396 } 397 } 398 399 kfree(pe_alloc); 400 return master_pe; 401 } 402 403 static void __init pnv_ioda_parse_m64_window(struct pnv_phb *phb) 404 { 405 struct pci_controller *hose = phb->hose; 406 struct device_node *dn = hose->dn; 407 struct resource *res; 408 const u32 *r; 409 u64 pci_addr; 410 411 if (phb->type != PNV_PHB_IODA1 && phb->type != PNV_PHB_IODA2) { 412 pr_info(" Not support M64 window\n"); 413 return; 414 } 415 416 if (!firmware_has_feature(FW_FEATURE_OPAL)) { 417 pr_info(" Firmware too old to support M64 window\n"); 418 return; 419 } 420 421 r = of_get_property(dn, "ibm,opal-m64-window", NULL); 422 if (!r) { 423 pr_info(" No <ibm,opal-m64-window> on %s\n", 424 dn->full_name); 425 return; 426 } 427 428 res = &hose->mem_resources[1]; 429 res->name = dn->full_name; 430 res->start = of_translate_address(dn, r + 2); 431 res->end = res->start + of_read_number(r + 4, 2) - 1; 432 res->flags = (IORESOURCE_MEM | IORESOURCE_MEM_64 | IORESOURCE_PREFETCH); 433 pci_addr = of_read_number(r, 2); 434 hose->mem_offset[1] = res->start - pci_addr; 435 436 phb->ioda.m64_size = resource_size(res); 437 phb->ioda.m64_segsize = phb->ioda.m64_size / phb->ioda.total_pe_num; 438 phb->ioda.m64_base = pci_addr; 439 440 pr_info(" MEM64 0x%016llx..0x%016llx -> 0x%016llx\n", 441 res->start, res->end, pci_addr); 442 443 /* Use last M64 BAR to cover M64 window */ 444 phb->ioda.m64_bar_idx = 15; 445 if (phb->type == PNV_PHB_IODA1) 446 phb->init_m64 = pnv_ioda1_init_m64; 447 else 448 phb->init_m64 = pnv_ioda2_init_m64; 449 phb->reserve_m64_pe = pnv_ioda_reserve_m64_pe; 450 phb->pick_m64_pe = pnv_ioda_pick_m64_pe; 451 } 452 453 static void pnv_ioda_freeze_pe(struct pnv_phb *phb, int pe_no) 454 { 455 struct pnv_ioda_pe *pe = &phb->ioda.pe_array[pe_no]; 456 struct pnv_ioda_pe *slave; 457 s64 rc; 458 459 /* Fetch master PE */ 460 if (pe->flags & PNV_IODA_PE_SLAVE) { 461 pe = pe->master; 462 if (WARN_ON(!pe || !(pe->flags & PNV_IODA_PE_MASTER))) 463 return; 464 465 pe_no = pe->pe_number; 466 } 467 468 /* Freeze master PE */ 469 rc = opal_pci_eeh_freeze_set(phb->opal_id, 470 pe_no, 471 OPAL_EEH_ACTION_SET_FREEZE_ALL); 472 if (rc != OPAL_SUCCESS) { 473 pr_warn("%s: Failure %lld freezing PHB#%x-PE#%x\n", 474 __func__, rc, phb->hose->global_number, pe_no); 475 return; 476 } 477 478 /* Freeze slave PEs */ 479 if (!(pe->flags & PNV_IODA_PE_MASTER)) 480 return; 481 482 list_for_each_entry(slave, &pe->slaves, list) { 483 rc = opal_pci_eeh_freeze_set(phb->opal_id, 484 slave->pe_number, 485 OPAL_EEH_ACTION_SET_FREEZE_ALL); 486 if (rc != OPAL_SUCCESS) 487 pr_warn("%s: Failure %lld freezing PHB#%x-PE#%x\n", 488 __func__, rc, phb->hose->global_number, 489 slave->pe_number); 490 } 491 } 492 493 static int pnv_ioda_unfreeze_pe(struct pnv_phb *phb, int pe_no, int opt) 494 { 495 struct pnv_ioda_pe *pe, *slave; 496 s64 rc; 497 498 /* Find master PE */ 499 pe = &phb->ioda.pe_array[pe_no]; 500 if (pe->flags & PNV_IODA_PE_SLAVE) { 501 pe = pe->master; 502 WARN_ON(!pe || !(pe->flags & PNV_IODA_PE_MASTER)); 503 pe_no = pe->pe_number; 504 } 505 506 /* Clear frozen state for master PE */ 507 rc = opal_pci_eeh_freeze_clear(phb->opal_id, pe_no, opt); 508 if (rc != OPAL_SUCCESS) { 509 pr_warn("%s: Failure %lld clear %d on PHB#%x-PE#%x\n", 510 __func__, rc, opt, phb->hose->global_number, pe_no); 511 return -EIO; 512 } 513 514 if (!(pe->flags & PNV_IODA_PE_MASTER)) 515 return 0; 516 517 /* Clear frozen state for slave PEs */ 518 list_for_each_entry(slave, &pe->slaves, list) { 519 rc = opal_pci_eeh_freeze_clear(phb->opal_id, 520 slave->pe_number, 521 opt); 522 if (rc != OPAL_SUCCESS) { 523 pr_warn("%s: Failure %lld clear %d on PHB#%x-PE#%x\n", 524 __func__, rc, opt, phb->hose->global_number, 525 slave->pe_number); 526 return -EIO; 527 } 528 } 529 530 return 0; 531 } 532 533 static int pnv_ioda_get_pe_state(struct pnv_phb *phb, int pe_no) 534 { 535 struct pnv_ioda_pe *slave, *pe; 536 u8 fstate, state; 537 __be16 pcierr; 538 s64 rc; 539 540 /* Sanity check on PE number */ 541 if (pe_no < 0 || pe_no >= phb->ioda.total_pe_num) 542 return OPAL_EEH_STOPPED_PERM_UNAVAIL; 543 544 /* 545 * Fetch the master PE and the PE instance might be 546 * not initialized yet. 547 */ 548 pe = &phb->ioda.pe_array[pe_no]; 549 if (pe->flags & PNV_IODA_PE_SLAVE) { 550 pe = pe->master; 551 WARN_ON(!pe || !(pe->flags & PNV_IODA_PE_MASTER)); 552 pe_no = pe->pe_number; 553 } 554 555 /* Check the master PE */ 556 rc = opal_pci_eeh_freeze_status(phb->opal_id, pe_no, 557 &state, &pcierr, NULL); 558 if (rc != OPAL_SUCCESS) { 559 pr_warn("%s: Failure %lld getting " 560 "PHB#%x-PE#%x state\n", 561 __func__, rc, 562 phb->hose->global_number, pe_no); 563 return OPAL_EEH_STOPPED_TEMP_UNAVAIL; 564 } 565 566 /* Check the slave PE */ 567 if (!(pe->flags & PNV_IODA_PE_MASTER)) 568 return state; 569 570 list_for_each_entry(slave, &pe->slaves, list) { 571 rc = opal_pci_eeh_freeze_status(phb->opal_id, 572 slave->pe_number, 573 &fstate, 574 &pcierr, 575 NULL); 576 if (rc != OPAL_SUCCESS) { 577 pr_warn("%s: Failure %lld getting " 578 "PHB#%x-PE#%x state\n", 579 __func__, rc, 580 phb->hose->global_number, slave->pe_number); 581 return OPAL_EEH_STOPPED_TEMP_UNAVAIL; 582 } 583 584 /* 585 * Override the result based on the ascending 586 * priority. 587 */ 588 if (fstate > state) 589 state = fstate; 590 } 591 592 return state; 593 } 594 595 /* Currently those 2 are only used when MSIs are enabled, this will change 596 * but in the meantime, we need to protect them to avoid warnings 597 */ 598 #ifdef CONFIG_PCI_MSI 599 static struct pnv_ioda_pe *pnv_ioda_get_pe(struct pci_dev *dev) 600 { 601 struct pci_controller *hose = pci_bus_to_host(dev->bus); 602 struct pnv_phb *phb = hose->private_data; 603 struct pci_dn *pdn = pci_get_pdn(dev); 604 605 if (!pdn) 606 return NULL; 607 if (pdn->pe_number == IODA_INVALID_PE) 608 return NULL; 609 return &phb->ioda.pe_array[pdn->pe_number]; 610 } 611 #endif /* CONFIG_PCI_MSI */ 612 613 static int pnv_ioda_set_one_peltv(struct pnv_phb *phb, 614 struct pnv_ioda_pe *parent, 615 struct pnv_ioda_pe *child, 616 bool is_add) 617 { 618 const char *desc = is_add ? "adding" : "removing"; 619 uint8_t op = is_add ? OPAL_ADD_PE_TO_DOMAIN : 620 OPAL_REMOVE_PE_FROM_DOMAIN; 621 struct pnv_ioda_pe *slave; 622 long rc; 623 624 /* Parent PE affects child PE */ 625 rc = opal_pci_set_peltv(phb->opal_id, parent->pe_number, 626 child->pe_number, op); 627 if (rc != OPAL_SUCCESS) { 628 pe_warn(child, "OPAL error %ld %s to parent PELTV\n", 629 rc, desc); 630 return -ENXIO; 631 } 632 633 if (!(child->flags & PNV_IODA_PE_MASTER)) 634 return 0; 635 636 /* Compound case: parent PE affects slave PEs */ 637 list_for_each_entry(slave, &child->slaves, list) { 638 rc = opal_pci_set_peltv(phb->opal_id, parent->pe_number, 639 slave->pe_number, op); 640 if (rc != OPAL_SUCCESS) { 641 pe_warn(slave, "OPAL error %ld %s to parent PELTV\n", 642 rc, desc); 643 return -ENXIO; 644 } 645 } 646 647 return 0; 648 } 649 650 static int pnv_ioda_set_peltv(struct pnv_phb *phb, 651 struct pnv_ioda_pe *pe, 652 bool is_add) 653 { 654 struct pnv_ioda_pe *slave; 655 struct pci_dev *pdev = NULL; 656 int ret; 657 658 /* 659 * Clear PE frozen state. If it's master PE, we need 660 * clear slave PE frozen state as well. 661 */ 662 if (is_add) { 663 opal_pci_eeh_freeze_clear(phb->opal_id, pe->pe_number, 664 OPAL_EEH_ACTION_CLEAR_FREEZE_ALL); 665 if (pe->flags & PNV_IODA_PE_MASTER) { 666 list_for_each_entry(slave, &pe->slaves, list) 667 opal_pci_eeh_freeze_clear(phb->opal_id, 668 slave->pe_number, 669 OPAL_EEH_ACTION_CLEAR_FREEZE_ALL); 670 } 671 } 672 673 /* 674 * Associate PE in PELT. We need add the PE into the 675 * corresponding PELT-V as well. Otherwise, the error 676 * originated from the PE might contribute to other 677 * PEs. 678 */ 679 ret = pnv_ioda_set_one_peltv(phb, pe, pe, is_add); 680 if (ret) 681 return ret; 682 683 /* For compound PEs, any one affects all of them */ 684 if (pe->flags & PNV_IODA_PE_MASTER) { 685 list_for_each_entry(slave, &pe->slaves, list) { 686 ret = pnv_ioda_set_one_peltv(phb, slave, pe, is_add); 687 if (ret) 688 return ret; 689 } 690 } 691 692 if (pe->flags & (PNV_IODA_PE_BUS_ALL | PNV_IODA_PE_BUS)) 693 pdev = pe->pbus->self; 694 else if (pe->flags & PNV_IODA_PE_DEV) 695 pdev = pe->pdev->bus->self; 696 #ifdef CONFIG_PCI_IOV 697 else if (pe->flags & PNV_IODA_PE_VF) 698 pdev = pe->parent_dev; 699 #endif /* CONFIG_PCI_IOV */ 700 while (pdev) { 701 struct pci_dn *pdn = pci_get_pdn(pdev); 702 struct pnv_ioda_pe *parent; 703 704 if (pdn && pdn->pe_number != IODA_INVALID_PE) { 705 parent = &phb->ioda.pe_array[pdn->pe_number]; 706 ret = pnv_ioda_set_one_peltv(phb, parent, pe, is_add); 707 if (ret) 708 return ret; 709 } 710 711 pdev = pdev->bus->self; 712 } 713 714 return 0; 715 } 716 717 #ifdef CONFIG_PCI_IOV 718 static int pnv_ioda_deconfigure_pe(struct pnv_phb *phb, struct pnv_ioda_pe *pe) 719 { 720 struct pci_dev *parent; 721 uint8_t bcomp, dcomp, fcomp; 722 int64_t rc; 723 long rid_end, rid; 724 725 /* Currently, we just deconfigure VF PE. Bus PE will always there.*/ 726 if (pe->pbus) { 727 int count; 728 729 dcomp = OPAL_IGNORE_RID_DEVICE_NUMBER; 730 fcomp = OPAL_IGNORE_RID_FUNCTION_NUMBER; 731 parent = pe->pbus->self; 732 if (pe->flags & PNV_IODA_PE_BUS_ALL) 733 count = pe->pbus->busn_res.end - pe->pbus->busn_res.start + 1; 734 else 735 count = 1; 736 737 switch(count) { 738 case 1: bcomp = OpalPciBusAll; break; 739 case 2: bcomp = OpalPciBus7Bits; break; 740 case 4: bcomp = OpalPciBus6Bits; break; 741 case 8: bcomp = OpalPciBus5Bits; break; 742 case 16: bcomp = OpalPciBus4Bits; break; 743 case 32: bcomp = OpalPciBus3Bits; break; 744 default: 745 dev_err(&pe->pbus->dev, "Number of subordinate buses %d unsupported\n", 746 count); 747 /* Do an exact match only */ 748 bcomp = OpalPciBusAll; 749 } 750 rid_end = pe->rid + (count << 8); 751 } else { 752 if (pe->flags & PNV_IODA_PE_VF) 753 parent = pe->parent_dev; 754 else 755 parent = pe->pdev->bus->self; 756 bcomp = OpalPciBusAll; 757 dcomp = OPAL_COMPARE_RID_DEVICE_NUMBER; 758 fcomp = OPAL_COMPARE_RID_FUNCTION_NUMBER; 759 rid_end = pe->rid + 1; 760 } 761 762 /* Clear the reverse map */ 763 for (rid = pe->rid; rid < rid_end; rid++) 764 phb->ioda.pe_rmap[rid] = 0; 765 766 /* Release from all parents PELT-V */ 767 while (parent) { 768 struct pci_dn *pdn = pci_get_pdn(parent); 769 if (pdn && pdn->pe_number != IODA_INVALID_PE) { 770 rc = opal_pci_set_peltv(phb->opal_id, pdn->pe_number, 771 pe->pe_number, OPAL_REMOVE_PE_FROM_DOMAIN); 772 /* XXX What to do in case of error ? */ 773 } 774 parent = parent->bus->self; 775 } 776 777 opal_pci_eeh_freeze_clear(phb->opal_id, pe->pe_number, 778 OPAL_EEH_ACTION_CLEAR_FREEZE_ALL); 779 780 /* Disassociate PE in PELT */ 781 rc = opal_pci_set_peltv(phb->opal_id, pe->pe_number, 782 pe->pe_number, OPAL_REMOVE_PE_FROM_DOMAIN); 783 if (rc) 784 pe_warn(pe, "OPAL error %ld remove self from PELTV\n", rc); 785 rc = opal_pci_set_pe(phb->opal_id, pe->pe_number, pe->rid, 786 bcomp, dcomp, fcomp, OPAL_UNMAP_PE); 787 if (rc) 788 pe_err(pe, "OPAL error %ld trying to setup PELT table\n", rc); 789 790 pe->pbus = NULL; 791 pe->pdev = NULL; 792 pe->parent_dev = NULL; 793 794 return 0; 795 } 796 #endif /* CONFIG_PCI_IOV */ 797 798 static int pnv_ioda_configure_pe(struct pnv_phb *phb, struct pnv_ioda_pe *pe) 799 { 800 struct pci_dev *parent; 801 uint8_t bcomp, dcomp, fcomp; 802 long rc, rid_end, rid; 803 804 /* Bus validation ? */ 805 if (pe->pbus) { 806 int count; 807 808 dcomp = OPAL_IGNORE_RID_DEVICE_NUMBER; 809 fcomp = OPAL_IGNORE_RID_FUNCTION_NUMBER; 810 parent = pe->pbus->self; 811 if (pe->flags & PNV_IODA_PE_BUS_ALL) 812 count = pe->pbus->busn_res.end - pe->pbus->busn_res.start + 1; 813 else 814 count = 1; 815 816 switch(count) { 817 case 1: bcomp = OpalPciBusAll; break; 818 case 2: bcomp = OpalPciBus7Bits; break; 819 case 4: bcomp = OpalPciBus6Bits; break; 820 case 8: bcomp = OpalPciBus5Bits; break; 821 case 16: bcomp = OpalPciBus4Bits; break; 822 case 32: bcomp = OpalPciBus3Bits; break; 823 default: 824 dev_err(&pe->pbus->dev, "Number of subordinate buses %d unsupported\n", 825 count); 826 /* Do an exact match only */ 827 bcomp = OpalPciBusAll; 828 } 829 rid_end = pe->rid + (count << 8); 830 } else { 831 #ifdef CONFIG_PCI_IOV 832 if (pe->flags & PNV_IODA_PE_VF) 833 parent = pe->parent_dev; 834 else 835 #endif /* CONFIG_PCI_IOV */ 836 parent = pe->pdev->bus->self; 837 bcomp = OpalPciBusAll; 838 dcomp = OPAL_COMPARE_RID_DEVICE_NUMBER; 839 fcomp = OPAL_COMPARE_RID_FUNCTION_NUMBER; 840 rid_end = pe->rid + 1; 841 } 842 843 /* 844 * Associate PE in PELT. We need add the PE into the 845 * corresponding PELT-V as well. Otherwise, the error 846 * originated from the PE might contribute to other 847 * PEs. 848 */ 849 rc = opal_pci_set_pe(phb->opal_id, pe->pe_number, pe->rid, 850 bcomp, dcomp, fcomp, OPAL_MAP_PE); 851 if (rc) { 852 pe_err(pe, "OPAL error %ld trying to setup PELT table\n", rc); 853 return -ENXIO; 854 } 855 856 /* 857 * Configure PELTV. NPUs don't have a PELTV table so skip 858 * configuration on them. 859 */ 860 if (phb->type != PNV_PHB_NPU) 861 pnv_ioda_set_peltv(phb, pe, true); 862 863 /* Setup reverse map */ 864 for (rid = pe->rid; rid < rid_end; rid++) 865 phb->ioda.pe_rmap[rid] = pe->pe_number; 866 867 /* Setup one MVTs on IODA1 */ 868 if (phb->type != PNV_PHB_IODA1) { 869 pe->mve_number = 0; 870 goto out; 871 } 872 873 pe->mve_number = pe->pe_number; 874 rc = opal_pci_set_mve(phb->opal_id, pe->mve_number, pe->pe_number); 875 if (rc != OPAL_SUCCESS) { 876 pe_err(pe, "OPAL error %ld setting up MVE %d\n", 877 rc, pe->mve_number); 878 pe->mve_number = -1; 879 } else { 880 rc = opal_pci_set_mve_enable(phb->opal_id, 881 pe->mve_number, OPAL_ENABLE_MVE); 882 if (rc) { 883 pe_err(pe, "OPAL error %ld enabling MVE %d\n", 884 rc, pe->mve_number); 885 pe->mve_number = -1; 886 } 887 } 888 889 out: 890 return 0; 891 } 892 893 #ifdef CONFIG_PCI_IOV 894 static int pnv_pci_vf_resource_shift(struct pci_dev *dev, int offset) 895 { 896 struct pci_dn *pdn = pci_get_pdn(dev); 897 int i; 898 struct resource *res, res2; 899 resource_size_t size; 900 u16 num_vfs; 901 902 if (!dev->is_physfn) 903 return -EINVAL; 904 905 /* 906 * "offset" is in VFs. The M64 windows are sized so that when they 907 * are segmented, each segment is the same size as the IOV BAR. 908 * Each segment is in a separate PE, and the high order bits of the 909 * address are the PE number. Therefore, each VF's BAR is in a 910 * separate PE, and changing the IOV BAR start address changes the 911 * range of PEs the VFs are in. 912 */ 913 num_vfs = pdn->num_vfs; 914 for (i = 0; i < PCI_SRIOV_NUM_BARS; i++) { 915 res = &dev->resource[i + PCI_IOV_RESOURCES]; 916 if (!res->flags || !res->parent) 917 continue; 918 919 /* 920 * The actual IOV BAR range is determined by the start address 921 * and the actual size for num_vfs VFs BAR. This check is to 922 * make sure that after shifting, the range will not overlap 923 * with another device. 924 */ 925 size = pci_iov_resource_size(dev, i + PCI_IOV_RESOURCES); 926 res2.flags = res->flags; 927 res2.start = res->start + (size * offset); 928 res2.end = res2.start + (size * num_vfs) - 1; 929 930 if (res2.end > res->end) { 931 dev_err(&dev->dev, "VF BAR%d: %pR would extend past %pR (trying to enable %d VFs shifted by %d)\n", 932 i, &res2, res, num_vfs, offset); 933 return -EBUSY; 934 } 935 } 936 937 /* 938 * After doing so, there would be a "hole" in the /proc/iomem when 939 * offset is a positive value. It looks like the device return some 940 * mmio back to the system, which actually no one could use it. 941 */ 942 for (i = 0; i < PCI_SRIOV_NUM_BARS; i++) { 943 res = &dev->resource[i + PCI_IOV_RESOURCES]; 944 if (!res->flags || !res->parent) 945 continue; 946 947 size = pci_iov_resource_size(dev, i + PCI_IOV_RESOURCES); 948 res2 = *res; 949 res->start += size * offset; 950 951 dev_info(&dev->dev, "VF BAR%d: %pR shifted to %pR (%sabling %d VFs shifted by %d)\n", 952 i, &res2, res, (offset > 0) ? "En" : "Dis", 953 num_vfs, offset); 954 pci_update_resource(dev, i + PCI_IOV_RESOURCES); 955 } 956 return 0; 957 } 958 #endif /* CONFIG_PCI_IOV */ 959 960 static struct pnv_ioda_pe *pnv_ioda_setup_dev_PE(struct pci_dev *dev) 961 { 962 struct pci_controller *hose = pci_bus_to_host(dev->bus); 963 struct pnv_phb *phb = hose->private_data; 964 struct pci_dn *pdn = pci_get_pdn(dev); 965 struct pnv_ioda_pe *pe; 966 967 if (!pdn) { 968 pr_err("%s: Device tree node not associated properly\n", 969 pci_name(dev)); 970 return NULL; 971 } 972 if (pdn->pe_number != IODA_INVALID_PE) 973 return NULL; 974 975 pe = pnv_ioda_alloc_pe(phb); 976 if (!pe) { 977 pr_warning("%s: Not enough PE# available, disabling device\n", 978 pci_name(dev)); 979 return NULL; 980 } 981 982 /* NOTE: We get only one ref to the pci_dev for the pdn, not for the 983 * pointer in the PE data structure, both should be destroyed at the 984 * same time. However, this needs to be looked at more closely again 985 * once we actually start removing things (Hotplug, SR-IOV, ...) 986 * 987 * At some point we want to remove the PDN completely anyways 988 */ 989 pci_dev_get(dev); 990 pdn->pcidev = dev; 991 pdn->pe_number = pe->pe_number; 992 pe->flags = PNV_IODA_PE_DEV; 993 pe->pdev = dev; 994 pe->pbus = NULL; 995 pe->mve_number = -1; 996 pe->rid = dev->bus->number << 8 | pdn->devfn; 997 998 pe_info(pe, "Associated device to PE\n"); 999 1000 if (pnv_ioda_configure_pe(phb, pe)) { 1001 /* XXX What do we do here ? */ 1002 pnv_ioda_free_pe(pe); 1003 pdn->pe_number = IODA_INVALID_PE; 1004 pe->pdev = NULL; 1005 pci_dev_put(dev); 1006 return NULL; 1007 } 1008 1009 return pe; 1010 } 1011 1012 static void pnv_ioda_setup_same_PE(struct pci_bus *bus, struct pnv_ioda_pe *pe) 1013 { 1014 struct pci_dev *dev; 1015 1016 list_for_each_entry(dev, &bus->devices, bus_list) { 1017 struct pci_dn *pdn = pci_get_pdn(dev); 1018 1019 if (pdn == NULL) { 1020 pr_warn("%s: No device node associated with device !\n", 1021 pci_name(dev)); 1022 continue; 1023 } 1024 pdn->pcidev = dev; 1025 pdn->pe_number = pe->pe_number; 1026 if ((pe->flags & PNV_IODA_PE_BUS_ALL) && dev->subordinate) 1027 pnv_ioda_setup_same_PE(dev->subordinate, pe); 1028 } 1029 } 1030 1031 /* 1032 * There're 2 types of PCI bus sensitive PEs: One that is compromised of 1033 * single PCI bus. Another one that contains the primary PCI bus and its 1034 * subordinate PCI devices and buses. The second type of PE is normally 1035 * orgiriated by PCIe-to-PCI bridge or PLX switch downstream ports. 1036 */ 1037 static struct pnv_ioda_pe *pnv_ioda_setup_bus_PE(struct pci_bus *bus, bool all) 1038 { 1039 struct pci_controller *hose = pci_bus_to_host(bus); 1040 struct pnv_phb *phb = hose->private_data; 1041 struct pnv_ioda_pe *pe = NULL; 1042 1043 /* Check if PE is determined by M64 */ 1044 if (phb->pick_m64_pe) 1045 pe = phb->pick_m64_pe(bus, all); 1046 1047 /* The PE number isn't pinned by M64 */ 1048 if (!pe) 1049 pe = pnv_ioda_alloc_pe(phb); 1050 1051 if (!pe) { 1052 pr_warning("%s: Not enough PE# available for PCI bus %04x:%02x\n", 1053 __func__, pci_domain_nr(bus), bus->number); 1054 return NULL; 1055 } 1056 1057 pe->flags |= (all ? PNV_IODA_PE_BUS_ALL : PNV_IODA_PE_BUS); 1058 pe->pbus = bus; 1059 pe->pdev = NULL; 1060 pe->mve_number = -1; 1061 pe->rid = bus->busn_res.start << 8; 1062 1063 if (all) 1064 pe_info(pe, "Secondary bus %d..%d associated with PE#%d\n", 1065 bus->busn_res.start, bus->busn_res.end, pe->pe_number); 1066 else 1067 pe_info(pe, "Secondary bus %d associated with PE#%d\n", 1068 bus->busn_res.start, pe->pe_number); 1069 1070 if (pnv_ioda_configure_pe(phb, pe)) { 1071 /* XXX What do we do here ? */ 1072 pnv_ioda_free_pe(pe); 1073 pe->pbus = NULL; 1074 return NULL; 1075 } 1076 1077 /* Associate it with all child devices */ 1078 pnv_ioda_setup_same_PE(bus, pe); 1079 1080 /* Put PE to the list */ 1081 list_add_tail(&pe->list, &phb->ioda.pe_list); 1082 1083 return pe; 1084 } 1085 1086 static struct pnv_ioda_pe *pnv_ioda_setup_npu_PE(struct pci_dev *npu_pdev) 1087 { 1088 int pe_num, found_pe = false, rc; 1089 long rid; 1090 struct pnv_ioda_pe *pe; 1091 struct pci_dev *gpu_pdev; 1092 struct pci_dn *npu_pdn; 1093 struct pci_controller *hose = pci_bus_to_host(npu_pdev->bus); 1094 struct pnv_phb *phb = hose->private_data; 1095 1096 /* 1097 * Due to a hardware errata PE#0 on the NPU is reserved for 1098 * error handling. This means we only have three PEs remaining 1099 * which need to be assigned to four links, implying some 1100 * links must share PEs. 1101 * 1102 * To achieve this we assign PEs such that NPUs linking the 1103 * same GPU get assigned the same PE. 1104 */ 1105 gpu_pdev = pnv_pci_get_gpu_dev(npu_pdev); 1106 for (pe_num = 0; pe_num < phb->ioda.total_pe_num; pe_num++) { 1107 pe = &phb->ioda.pe_array[pe_num]; 1108 if (!pe->pdev) 1109 continue; 1110 1111 if (pnv_pci_get_gpu_dev(pe->pdev) == gpu_pdev) { 1112 /* 1113 * This device has the same peer GPU so should 1114 * be assigned the same PE as the existing 1115 * peer NPU. 1116 */ 1117 dev_info(&npu_pdev->dev, 1118 "Associating to existing PE %d\n", pe_num); 1119 pci_dev_get(npu_pdev); 1120 npu_pdn = pci_get_pdn(npu_pdev); 1121 rid = npu_pdev->bus->number << 8 | npu_pdn->devfn; 1122 npu_pdn->pcidev = npu_pdev; 1123 npu_pdn->pe_number = pe_num; 1124 phb->ioda.pe_rmap[rid] = pe->pe_number; 1125 1126 /* Map the PE to this link */ 1127 rc = opal_pci_set_pe(phb->opal_id, pe_num, rid, 1128 OpalPciBusAll, 1129 OPAL_COMPARE_RID_DEVICE_NUMBER, 1130 OPAL_COMPARE_RID_FUNCTION_NUMBER, 1131 OPAL_MAP_PE); 1132 WARN_ON(rc != OPAL_SUCCESS); 1133 found_pe = true; 1134 break; 1135 } 1136 } 1137 1138 if (!found_pe) 1139 /* 1140 * Could not find an existing PE so allocate a new 1141 * one. 1142 */ 1143 return pnv_ioda_setup_dev_PE(npu_pdev); 1144 else 1145 return pe; 1146 } 1147 1148 static void pnv_ioda_setup_npu_PEs(struct pci_bus *bus) 1149 { 1150 struct pci_dev *pdev; 1151 1152 list_for_each_entry(pdev, &bus->devices, bus_list) 1153 pnv_ioda_setup_npu_PE(pdev); 1154 } 1155 1156 static void pnv_ioda_setup_PEs(struct pci_bus *bus) 1157 { 1158 struct pci_dev *dev; 1159 1160 pnv_ioda_setup_bus_PE(bus, false); 1161 1162 list_for_each_entry(dev, &bus->devices, bus_list) { 1163 if (dev->subordinate) { 1164 if (pci_pcie_type(dev) == PCI_EXP_TYPE_PCI_BRIDGE) 1165 pnv_ioda_setup_bus_PE(dev->subordinate, true); 1166 else 1167 pnv_ioda_setup_PEs(dev->subordinate); 1168 } 1169 } 1170 } 1171 1172 /* 1173 * Configure PEs so that the downstream PCI buses and devices 1174 * could have their associated PE#. Unfortunately, we didn't 1175 * figure out the way to identify the PLX bridge yet. So we 1176 * simply put the PCI bus and the subordinate behind the root 1177 * port to PE# here. The game rule here is expected to be changed 1178 * as soon as we can detected PLX bridge correctly. 1179 */ 1180 static void pnv_pci_ioda_setup_PEs(void) 1181 { 1182 struct pci_controller *hose, *tmp; 1183 struct pnv_phb *phb; 1184 1185 list_for_each_entry_safe(hose, tmp, &hose_list, list_node) { 1186 phb = hose->private_data; 1187 1188 /* M64 layout might affect PE allocation */ 1189 if (phb->reserve_m64_pe) 1190 phb->reserve_m64_pe(hose->bus, NULL, true); 1191 1192 /* 1193 * On NPU PHB, we expect separate PEs for individual PCI 1194 * functions. PCI bus dependent PEs are required for the 1195 * remaining types of PHBs. 1196 */ 1197 if (phb->type == PNV_PHB_NPU) { 1198 /* PE#0 is needed for error reporting */ 1199 pnv_ioda_reserve_pe(phb, 0); 1200 pnv_ioda_setup_npu_PEs(hose->bus); 1201 } else 1202 pnv_ioda_setup_PEs(hose->bus); 1203 } 1204 } 1205 1206 #ifdef CONFIG_PCI_IOV 1207 static int pnv_pci_vf_release_m64(struct pci_dev *pdev, u16 num_vfs) 1208 { 1209 struct pci_bus *bus; 1210 struct pci_controller *hose; 1211 struct pnv_phb *phb; 1212 struct pci_dn *pdn; 1213 int i, j; 1214 int m64_bars; 1215 1216 bus = pdev->bus; 1217 hose = pci_bus_to_host(bus); 1218 phb = hose->private_data; 1219 pdn = pci_get_pdn(pdev); 1220 1221 if (pdn->m64_single_mode) 1222 m64_bars = num_vfs; 1223 else 1224 m64_bars = 1; 1225 1226 for (i = 0; i < PCI_SRIOV_NUM_BARS; i++) 1227 for (j = 0; j < m64_bars; j++) { 1228 if (pdn->m64_map[j][i] == IODA_INVALID_M64) 1229 continue; 1230 opal_pci_phb_mmio_enable(phb->opal_id, 1231 OPAL_M64_WINDOW_TYPE, pdn->m64_map[j][i], 0); 1232 clear_bit(pdn->m64_map[j][i], &phb->ioda.m64_bar_alloc); 1233 pdn->m64_map[j][i] = IODA_INVALID_M64; 1234 } 1235 1236 kfree(pdn->m64_map); 1237 return 0; 1238 } 1239 1240 static int pnv_pci_vf_assign_m64(struct pci_dev *pdev, u16 num_vfs) 1241 { 1242 struct pci_bus *bus; 1243 struct pci_controller *hose; 1244 struct pnv_phb *phb; 1245 struct pci_dn *pdn; 1246 unsigned int win; 1247 struct resource *res; 1248 int i, j; 1249 int64_t rc; 1250 int total_vfs; 1251 resource_size_t size, start; 1252 int pe_num; 1253 int m64_bars; 1254 1255 bus = pdev->bus; 1256 hose = pci_bus_to_host(bus); 1257 phb = hose->private_data; 1258 pdn = pci_get_pdn(pdev); 1259 total_vfs = pci_sriov_get_totalvfs(pdev); 1260 1261 if (pdn->m64_single_mode) 1262 m64_bars = num_vfs; 1263 else 1264 m64_bars = 1; 1265 1266 pdn->m64_map = kmalloc(sizeof(*pdn->m64_map) * m64_bars, GFP_KERNEL); 1267 if (!pdn->m64_map) 1268 return -ENOMEM; 1269 /* Initialize the m64_map to IODA_INVALID_M64 */ 1270 for (i = 0; i < m64_bars ; i++) 1271 for (j = 0; j < PCI_SRIOV_NUM_BARS; j++) 1272 pdn->m64_map[i][j] = IODA_INVALID_M64; 1273 1274 1275 for (i = 0; i < PCI_SRIOV_NUM_BARS; i++) { 1276 res = &pdev->resource[i + PCI_IOV_RESOURCES]; 1277 if (!res->flags || !res->parent) 1278 continue; 1279 1280 for (j = 0; j < m64_bars; j++) { 1281 do { 1282 win = find_next_zero_bit(&phb->ioda.m64_bar_alloc, 1283 phb->ioda.m64_bar_idx + 1, 0); 1284 1285 if (win >= phb->ioda.m64_bar_idx + 1) 1286 goto m64_failed; 1287 } while (test_and_set_bit(win, &phb->ioda.m64_bar_alloc)); 1288 1289 pdn->m64_map[j][i] = win; 1290 1291 if (pdn->m64_single_mode) { 1292 size = pci_iov_resource_size(pdev, 1293 PCI_IOV_RESOURCES + i); 1294 start = res->start + size * j; 1295 } else { 1296 size = resource_size(res); 1297 start = res->start; 1298 } 1299 1300 /* Map the M64 here */ 1301 if (pdn->m64_single_mode) { 1302 pe_num = pdn->pe_num_map[j]; 1303 rc = opal_pci_map_pe_mmio_window(phb->opal_id, 1304 pe_num, OPAL_M64_WINDOW_TYPE, 1305 pdn->m64_map[j][i], 0); 1306 } 1307 1308 rc = opal_pci_set_phb_mem_window(phb->opal_id, 1309 OPAL_M64_WINDOW_TYPE, 1310 pdn->m64_map[j][i], 1311 start, 1312 0, /* unused */ 1313 size); 1314 1315 1316 if (rc != OPAL_SUCCESS) { 1317 dev_err(&pdev->dev, "Failed to map M64 window #%d: %lld\n", 1318 win, rc); 1319 goto m64_failed; 1320 } 1321 1322 if (pdn->m64_single_mode) 1323 rc = opal_pci_phb_mmio_enable(phb->opal_id, 1324 OPAL_M64_WINDOW_TYPE, pdn->m64_map[j][i], 2); 1325 else 1326 rc = opal_pci_phb_mmio_enable(phb->opal_id, 1327 OPAL_M64_WINDOW_TYPE, pdn->m64_map[j][i], 1); 1328 1329 if (rc != OPAL_SUCCESS) { 1330 dev_err(&pdev->dev, "Failed to enable M64 window #%d: %llx\n", 1331 win, rc); 1332 goto m64_failed; 1333 } 1334 } 1335 } 1336 return 0; 1337 1338 m64_failed: 1339 pnv_pci_vf_release_m64(pdev, num_vfs); 1340 return -EBUSY; 1341 } 1342 1343 static long pnv_pci_ioda2_unset_window(struct iommu_table_group *table_group, 1344 int num); 1345 static void pnv_pci_ioda2_set_bypass(struct pnv_ioda_pe *pe, bool enable); 1346 1347 static void pnv_pci_ioda2_release_dma_pe(struct pci_dev *dev, struct pnv_ioda_pe *pe) 1348 { 1349 struct iommu_table *tbl; 1350 int64_t rc; 1351 1352 tbl = pe->table_group.tables[0]; 1353 rc = pnv_pci_ioda2_unset_window(&pe->table_group, 0); 1354 if (rc) 1355 pe_warn(pe, "OPAL error %ld release DMA window\n", rc); 1356 1357 pnv_pci_ioda2_set_bypass(pe, false); 1358 if (pe->table_group.group) { 1359 iommu_group_put(pe->table_group.group); 1360 BUG_ON(pe->table_group.group); 1361 } 1362 pnv_pci_ioda2_table_free_pages(tbl); 1363 iommu_free_table(tbl, of_node_full_name(dev->dev.of_node)); 1364 } 1365 1366 static void pnv_ioda_release_vf_PE(struct pci_dev *pdev) 1367 { 1368 struct pci_bus *bus; 1369 struct pci_controller *hose; 1370 struct pnv_phb *phb; 1371 struct pnv_ioda_pe *pe, *pe_n; 1372 struct pci_dn *pdn; 1373 1374 bus = pdev->bus; 1375 hose = pci_bus_to_host(bus); 1376 phb = hose->private_data; 1377 pdn = pci_get_pdn(pdev); 1378 1379 if (!pdev->is_physfn) 1380 return; 1381 1382 list_for_each_entry_safe(pe, pe_n, &phb->ioda.pe_list, list) { 1383 if (pe->parent_dev != pdev) 1384 continue; 1385 1386 pnv_pci_ioda2_release_dma_pe(pdev, pe); 1387 1388 /* Remove from list */ 1389 mutex_lock(&phb->ioda.pe_list_mutex); 1390 list_del(&pe->list); 1391 mutex_unlock(&phb->ioda.pe_list_mutex); 1392 1393 pnv_ioda_deconfigure_pe(phb, pe); 1394 1395 pnv_ioda_free_pe(pe); 1396 } 1397 } 1398 1399 void pnv_pci_sriov_disable(struct pci_dev *pdev) 1400 { 1401 struct pci_bus *bus; 1402 struct pci_controller *hose; 1403 struct pnv_phb *phb; 1404 struct pnv_ioda_pe *pe; 1405 struct pci_dn *pdn; 1406 struct pci_sriov *iov; 1407 u16 num_vfs, i; 1408 1409 bus = pdev->bus; 1410 hose = pci_bus_to_host(bus); 1411 phb = hose->private_data; 1412 pdn = pci_get_pdn(pdev); 1413 iov = pdev->sriov; 1414 num_vfs = pdn->num_vfs; 1415 1416 /* Release VF PEs */ 1417 pnv_ioda_release_vf_PE(pdev); 1418 1419 if (phb->type == PNV_PHB_IODA2) { 1420 if (!pdn->m64_single_mode) 1421 pnv_pci_vf_resource_shift(pdev, -*pdn->pe_num_map); 1422 1423 /* Release M64 windows */ 1424 pnv_pci_vf_release_m64(pdev, num_vfs); 1425 1426 /* Release PE numbers */ 1427 if (pdn->m64_single_mode) { 1428 for (i = 0; i < num_vfs; i++) { 1429 if (pdn->pe_num_map[i] == IODA_INVALID_PE) 1430 continue; 1431 1432 pe = &phb->ioda.pe_array[pdn->pe_num_map[i]]; 1433 pnv_ioda_free_pe(pe); 1434 } 1435 } else 1436 bitmap_clear(phb->ioda.pe_alloc, *pdn->pe_num_map, num_vfs); 1437 /* Releasing pe_num_map */ 1438 kfree(pdn->pe_num_map); 1439 } 1440 } 1441 1442 static void pnv_pci_ioda2_setup_dma_pe(struct pnv_phb *phb, 1443 struct pnv_ioda_pe *pe); 1444 static void pnv_ioda_setup_vf_PE(struct pci_dev *pdev, u16 num_vfs) 1445 { 1446 struct pci_bus *bus; 1447 struct pci_controller *hose; 1448 struct pnv_phb *phb; 1449 struct pnv_ioda_pe *pe; 1450 int pe_num; 1451 u16 vf_index; 1452 struct pci_dn *pdn; 1453 1454 bus = pdev->bus; 1455 hose = pci_bus_to_host(bus); 1456 phb = hose->private_data; 1457 pdn = pci_get_pdn(pdev); 1458 1459 if (!pdev->is_physfn) 1460 return; 1461 1462 /* Reserve PE for each VF */ 1463 for (vf_index = 0; vf_index < num_vfs; vf_index++) { 1464 if (pdn->m64_single_mode) 1465 pe_num = pdn->pe_num_map[vf_index]; 1466 else 1467 pe_num = *pdn->pe_num_map + vf_index; 1468 1469 pe = &phb->ioda.pe_array[pe_num]; 1470 pe->pe_number = pe_num; 1471 pe->phb = phb; 1472 pe->flags = PNV_IODA_PE_VF; 1473 pe->pbus = NULL; 1474 pe->parent_dev = pdev; 1475 pe->mve_number = -1; 1476 pe->rid = (pci_iov_virtfn_bus(pdev, vf_index) << 8) | 1477 pci_iov_virtfn_devfn(pdev, vf_index); 1478 1479 pe_info(pe, "VF %04d:%02d:%02d.%d associated with PE#%d\n", 1480 hose->global_number, pdev->bus->number, 1481 PCI_SLOT(pci_iov_virtfn_devfn(pdev, vf_index)), 1482 PCI_FUNC(pci_iov_virtfn_devfn(pdev, vf_index)), pe_num); 1483 1484 if (pnv_ioda_configure_pe(phb, pe)) { 1485 /* XXX What do we do here ? */ 1486 pnv_ioda_free_pe(pe); 1487 pe->pdev = NULL; 1488 continue; 1489 } 1490 1491 /* Put PE to the list */ 1492 mutex_lock(&phb->ioda.pe_list_mutex); 1493 list_add_tail(&pe->list, &phb->ioda.pe_list); 1494 mutex_unlock(&phb->ioda.pe_list_mutex); 1495 1496 pnv_pci_ioda2_setup_dma_pe(phb, pe); 1497 } 1498 } 1499 1500 int pnv_pci_sriov_enable(struct pci_dev *pdev, u16 num_vfs) 1501 { 1502 struct pci_bus *bus; 1503 struct pci_controller *hose; 1504 struct pnv_phb *phb; 1505 struct pnv_ioda_pe *pe; 1506 struct pci_dn *pdn; 1507 int ret; 1508 u16 i; 1509 1510 bus = pdev->bus; 1511 hose = pci_bus_to_host(bus); 1512 phb = hose->private_data; 1513 pdn = pci_get_pdn(pdev); 1514 1515 if (phb->type == PNV_PHB_IODA2) { 1516 if (!pdn->vfs_expanded) { 1517 dev_info(&pdev->dev, "don't support this SRIOV device" 1518 " with non 64bit-prefetchable IOV BAR\n"); 1519 return -ENOSPC; 1520 } 1521 1522 /* 1523 * When M64 BARs functions in Single PE mode, the number of VFs 1524 * could be enabled must be less than the number of M64 BARs. 1525 */ 1526 if (pdn->m64_single_mode && num_vfs > phb->ioda.m64_bar_idx) { 1527 dev_info(&pdev->dev, "Not enough M64 BAR for VFs\n"); 1528 return -EBUSY; 1529 } 1530 1531 /* Allocating pe_num_map */ 1532 if (pdn->m64_single_mode) 1533 pdn->pe_num_map = kmalloc(sizeof(*pdn->pe_num_map) * num_vfs, 1534 GFP_KERNEL); 1535 else 1536 pdn->pe_num_map = kmalloc(sizeof(*pdn->pe_num_map), GFP_KERNEL); 1537 1538 if (!pdn->pe_num_map) 1539 return -ENOMEM; 1540 1541 if (pdn->m64_single_mode) 1542 for (i = 0; i < num_vfs; i++) 1543 pdn->pe_num_map[i] = IODA_INVALID_PE; 1544 1545 /* Calculate available PE for required VFs */ 1546 if (pdn->m64_single_mode) { 1547 for (i = 0; i < num_vfs; i++) { 1548 pe = pnv_ioda_alloc_pe(phb); 1549 if (!pe) { 1550 ret = -EBUSY; 1551 goto m64_failed; 1552 } 1553 1554 pdn->pe_num_map[i] = pe->pe_number; 1555 } 1556 } else { 1557 mutex_lock(&phb->ioda.pe_alloc_mutex); 1558 *pdn->pe_num_map = bitmap_find_next_zero_area( 1559 phb->ioda.pe_alloc, phb->ioda.total_pe_num, 1560 0, num_vfs, 0); 1561 if (*pdn->pe_num_map >= phb->ioda.total_pe_num) { 1562 mutex_unlock(&phb->ioda.pe_alloc_mutex); 1563 dev_info(&pdev->dev, "Failed to enable VF%d\n", num_vfs); 1564 kfree(pdn->pe_num_map); 1565 return -EBUSY; 1566 } 1567 bitmap_set(phb->ioda.pe_alloc, *pdn->pe_num_map, num_vfs); 1568 mutex_unlock(&phb->ioda.pe_alloc_mutex); 1569 } 1570 pdn->num_vfs = num_vfs; 1571 1572 /* Assign M64 window accordingly */ 1573 ret = pnv_pci_vf_assign_m64(pdev, num_vfs); 1574 if (ret) { 1575 dev_info(&pdev->dev, "Not enough M64 window resources\n"); 1576 goto m64_failed; 1577 } 1578 1579 /* 1580 * When using one M64 BAR to map one IOV BAR, we need to shift 1581 * the IOV BAR according to the PE# allocated to the VFs. 1582 * Otherwise, the PE# for the VF will conflict with others. 1583 */ 1584 if (!pdn->m64_single_mode) { 1585 ret = pnv_pci_vf_resource_shift(pdev, *pdn->pe_num_map); 1586 if (ret) 1587 goto m64_failed; 1588 } 1589 } 1590 1591 /* Setup VF PEs */ 1592 pnv_ioda_setup_vf_PE(pdev, num_vfs); 1593 1594 return 0; 1595 1596 m64_failed: 1597 if (pdn->m64_single_mode) { 1598 for (i = 0; i < num_vfs; i++) { 1599 if (pdn->pe_num_map[i] == IODA_INVALID_PE) 1600 continue; 1601 1602 pe = &phb->ioda.pe_array[pdn->pe_num_map[i]]; 1603 pnv_ioda_free_pe(pe); 1604 } 1605 } else 1606 bitmap_clear(phb->ioda.pe_alloc, *pdn->pe_num_map, num_vfs); 1607 1608 /* Releasing pe_num_map */ 1609 kfree(pdn->pe_num_map); 1610 1611 return ret; 1612 } 1613 1614 int pcibios_sriov_disable(struct pci_dev *pdev) 1615 { 1616 pnv_pci_sriov_disable(pdev); 1617 1618 /* Release PCI data */ 1619 remove_dev_pci_data(pdev); 1620 return 0; 1621 } 1622 1623 int pcibios_sriov_enable(struct pci_dev *pdev, u16 num_vfs) 1624 { 1625 /* Allocate PCI data */ 1626 add_dev_pci_data(pdev); 1627 1628 return pnv_pci_sriov_enable(pdev, num_vfs); 1629 } 1630 #endif /* CONFIG_PCI_IOV */ 1631 1632 static void pnv_pci_ioda_dma_dev_setup(struct pnv_phb *phb, struct pci_dev *pdev) 1633 { 1634 struct pci_dn *pdn = pci_get_pdn(pdev); 1635 struct pnv_ioda_pe *pe; 1636 1637 /* 1638 * The function can be called while the PE# 1639 * hasn't been assigned. Do nothing for the 1640 * case. 1641 */ 1642 if (!pdn || pdn->pe_number == IODA_INVALID_PE) 1643 return; 1644 1645 pe = &phb->ioda.pe_array[pdn->pe_number]; 1646 WARN_ON(get_dma_ops(&pdev->dev) != &dma_iommu_ops); 1647 set_dma_offset(&pdev->dev, pe->tce_bypass_base); 1648 set_iommu_table_base(&pdev->dev, pe->table_group.tables[0]); 1649 /* 1650 * Note: iommu_add_device() will fail here as 1651 * for physical PE: the device is already added by now; 1652 * for virtual PE: sysfs entries are not ready yet and 1653 * tce_iommu_bus_notifier will add the device to a group later. 1654 */ 1655 } 1656 1657 static int pnv_pci_ioda_dma_set_mask(struct pci_dev *pdev, u64 dma_mask) 1658 { 1659 struct pci_controller *hose = pci_bus_to_host(pdev->bus); 1660 struct pnv_phb *phb = hose->private_data; 1661 struct pci_dn *pdn = pci_get_pdn(pdev); 1662 struct pnv_ioda_pe *pe; 1663 uint64_t top; 1664 bool bypass = false; 1665 1666 if (WARN_ON(!pdn || pdn->pe_number == IODA_INVALID_PE)) 1667 return -ENODEV;; 1668 1669 pe = &phb->ioda.pe_array[pdn->pe_number]; 1670 if (pe->tce_bypass_enabled) { 1671 top = pe->tce_bypass_base + memblock_end_of_DRAM() - 1; 1672 bypass = (dma_mask >= top); 1673 } 1674 1675 if (bypass) { 1676 dev_info(&pdev->dev, "Using 64-bit DMA iommu bypass\n"); 1677 set_dma_ops(&pdev->dev, &dma_direct_ops); 1678 } else { 1679 dev_info(&pdev->dev, "Using 32-bit DMA via iommu\n"); 1680 set_dma_ops(&pdev->dev, &dma_iommu_ops); 1681 } 1682 *pdev->dev.dma_mask = dma_mask; 1683 1684 /* Update peer npu devices */ 1685 pnv_npu_try_dma_set_bypass(pdev, bypass); 1686 1687 return 0; 1688 } 1689 1690 static u64 pnv_pci_ioda_dma_get_required_mask(struct pci_dev *pdev) 1691 { 1692 struct pci_controller *hose = pci_bus_to_host(pdev->bus); 1693 struct pnv_phb *phb = hose->private_data; 1694 struct pci_dn *pdn = pci_get_pdn(pdev); 1695 struct pnv_ioda_pe *pe; 1696 u64 end, mask; 1697 1698 if (WARN_ON(!pdn || pdn->pe_number == IODA_INVALID_PE)) 1699 return 0; 1700 1701 pe = &phb->ioda.pe_array[pdn->pe_number]; 1702 if (!pe->tce_bypass_enabled) 1703 return __dma_get_required_mask(&pdev->dev); 1704 1705 1706 end = pe->tce_bypass_base + memblock_end_of_DRAM(); 1707 mask = 1ULL << (fls64(end) - 1); 1708 mask += mask - 1; 1709 1710 return mask; 1711 } 1712 1713 static void pnv_ioda_setup_bus_dma(struct pnv_ioda_pe *pe, 1714 struct pci_bus *bus) 1715 { 1716 struct pci_dev *dev; 1717 1718 list_for_each_entry(dev, &bus->devices, bus_list) { 1719 set_iommu_table_base(&dev->dev, pe->table_group.tables[0]); 1720 set_dma_offset(&dev->dev, pe->tce_bypass_base); 1721 iommu_add_device(&dev->dev); 1722 1723 if ((pe->flags & PNV_IODA_PE_BUS_ALL) && dev->subordinate) 1724 pnv_ioda_setup_bus_dma(pe, dev->subordinate); 1725 } 1726 } 1727 1728 static void pnv_pci_ioda1_tce_invalidate(struct iommu_table *tbl, 1729 unsigned long index, unsigned long npages, bool rm) 1730 { 1731 struct iommu_table_group_link *tgl = list_first_entry_or_null( 1732 &tbl->it_group_list, struct iommu_table_group_link, 1733 next); 1734 struct pnv_ioda_pe *pe = container_of(tgl->table_group, 1735 struct pnv_ioda_pe, table_group); 1736 __be64 __iomem *invalidate = rm ? 1737 (__be64 __iomem *)pe->phb->ioda.tce_inval_reg_phys : 1738 pe->phb->ioda.tce_inval_reg; 1739 unsigned long start, end, inc; 1740 const unsigned shift = tbl->it_page_shift; 1741 1742 start = __pa(((__be64 *)tbl->it_base) + index - tbl->it_offset); 1743 end = __pa(((__be64 *)tbl->it_base) + index - tbl->it_offset + 1744 npages - 1); 1745 1746 /* BML uses this case for p6/p7/galaxy2: Shift addr and put in node */ 1747 if (tbl->it_busno) { 1748 start <<= shift; 1749 end <<= shift; 1750 inc = 128ull << shift; 1751 start |= tbl->it_busno; 1752 end |= tbl->it_busno; 1753 } else if (tbl->it_type & TCE_PCI_SWINV_PAIR) { 1754 /* p7ioc-style invalidation, 2 TCEs per write */ 1755 start |= (1ull << 63); 1756 end |= (1ull << 63); 1757 inc = 16; 1758 } else { 1759 /* Default (older HW) */ 1760 inc = 128; 1761 } 1762 1763 end |= inc - 1; /* round up end to be different than start */ 1764 1765 mb(); /* Ensure above stores are visible */ 1766 while (start <= end) { 1767 if (rm) 1768 __raw_rm_writeq(cpu_to_be64(start), invalidate); 1769 else 1770 __raw_writeq(cpu_to_be64(start), invalidate); 1771 start += inc; 1772 } 1773 1774 /* 1775 * The iommu layer will do another mb() for us on build() 1776 * and we don't care on free() 1777 */ 1778 } 1779 1780 static int pnv_ioda1_tce_build(struct iommu_table *tbl, long index, 1781 long npages, unsigned long uaddr, 1782 enum dma_data_direction direction, 1783 struct dma_attrs *attrs) 1784 { 1785 int ret = pnv_tce_build(tbl, index, npages, uaddr, direction, 1786 attrs); 1787 1788 if (!ret && (tbl->it_type & TCE_PCI_SWINV_CREATE)) 1789 pnv_pci_ioda1_tce_invalidate(tbl, index, npages, false); 1790 1791 return ret; 1792 } 1793 1794 #ifdef CONFIG_IOMMU_API 1795 static int pnv_ioda1_tce_xchg(struct iommu_table *tbl, long index, 1796 unsigned long *hpa, enum dma_data_direction *direction) 1797 { 1798 long ret = pnv_tce_xchg(tbl, index, hpa, direction); 1799 1800 if (!ret && (tbl->it_type & 1801 (TCE_PCI_SWINV_CREATE | TCE_PCI_SWINV_FREE))) 1802 pnv_pci_ioda1_tce_invalidate(tbl, index, 1, false); 1803 1804 return ret; 1805 } 1806 #endif 1807 1808 static void pnv_ioda1_tce_free(struct iommu_table *tbl, long index, 1809 long npages) 1810 { 1811 pnv_tce_free(tbl, index, npages); 1812 1813 if (tbl->it_type & TCE_PCI_SWINV_FREE) 1814 pnv_pci_ioda1_tce_invalidate(tbl, index, npages, false); 1815 } 1816 1817 static struct iommu_table_ops pnv_ioda1_iommu_ops = { 1818 .set = pnv_ioda1_tce_build, 1819 #ifdef CONFIG_IOMMU_API 1820 .exchange = pnv_ioda1_tce_xchg, 1821 #endif 1822 .clear = pnv_ioda1_tce_free, 1823 .get = pnv_tce_get, 1824 }; 1825 1826 #define TCE_KILL_INVAL_ALL PPC_BIT(0) 1827 #define TCE_KILL_INVAL_PE PPC_BIT(1) 1828 #define TCE_KILL_INVAL_TCE PPC_BIT(2) 1829 1830 void pnv_pci_ioda2_tce_invalidate_entire(struct pnv_phb *phb, bool rm) 1831 { 1832 const unsigned long val = TCE_KILL_INVAL_ALL; 1833 1834 mb(); /* Ensure previous TCE table stores are visible */ 1835 if (rm) 1836 __raw_rm_writeq(cpu_to_be64(val), 1837 (__be64 __iomem *) 1838 phb->ioda.tce_inval_reg_phys); 1839 else 1840 __raw_writeq(cpu_to_be64(val), phb->ioda.tce_inval_reg); 1841 } 1842 1843 static inline void pnv_pci_ioda2_tce_invalidate_pe(struct pnv_ioda_pe *pe) 1844 { 1845 /* 01xb - invalidate TCEs that match the specified PE# */ 1846 unsigned long val = TCE_KILL_INVAL_PE | (pe->pe_number & 0xFF); 1847 struct pnv_phb *phb = pe->phb; 1848 1849 if (!phb->ioda.tce_inval_reg) 1850 return; 1851 1852 mb(); /* Ensure above stores are visible */ 1853 __raw_writeq(cpu_to_be64(val), phb->ioda.tce_inval_reg); 1854 } 1855 1856 static void pnv_pci_ioda2_do_tce_invalidate(unsigned pe_number, bool rm, 1857 __be64 __iomem *invalidate, unsigned shift, 1858 unsigned long index, unsigned long npages) 1859 { 1860 unsigned long start, end, inc; 1861 1862 /* We'll invalidate DMA address in PE scope */ 1863 start = TCE_KILL_INVAL_TCE; 1864 start |= (pe_number & 0xFF); 1865 end = start; 1866 1867 /* Figure out the start, end and step */ 1868 start |= (index << shift); 1869 end |= ((index + npages - 1) << shift); 1870 inc = (0x1ull << shift); 1871 mb(); 1872 1873 while (start <= end) { 1874 if (rm) 1875 __raw_rm_writeq(cpu_to_be64(start), invalidate); 1876 else 1877 __raw_writeq(cpu_to_be64(start), invalidate); 1878 start += inc; 1879 } 1880 } 1881 1882 static void pnv_pci_ioda2_tce_invalidate(struct iommu_table *tbl, 1883 unsigned long index, unsigned long npages, bool rm) 1884 { 1885 struct iommu_table_group_link *tgl; 1886 1887 list_for_each_entry_rcu(tgl, &tbl->it_group_list, next) { 1888 struct pnv_ioda_pe *pe = container_of(tgl->table_group, 1889 struct pnv_ioda_pe, table_group); 1890 __be64 __iomem *invalidate = rm ? 1891 (__be64 __iomem *)pe->phb->ioda.tce_inval_reg_phys : 1892 pe->phb->ioda.tce_inval_reg; 1893 1894 if (pe->phb->type == PNV_PHB_NPU) { 1895 /* 1896 * The NVLink hardware does not support TCE kill 1897 * per TCE entry so we have to invalidate 1898 * the entire cache for it. 1899 */ 1900 pnv_pci_ioda2_tce_invalidate_entire(pe->phb, rm); 1901 continue; 1902 } 1903 pnv_pci_ioda2_do_tce_invalidate(pe->pe_number, rm, 1904 invalidate, tbl->it_page_shift, 1905 index, npages); 1906 } 1907 } 1908 1909 static int pnv_ioda2_tce_build(struct iommu_table *tbl, long index, 1910 long npages, unsigned long uaddr, 1911 enum dma_data_direction direction, 1912 struct dma_attrs *attrs) 1913 { 1914 int ret = pnv_tce_build(tbl, index, npages, uaddr, direction, 1915 attrs); 1916 1917 if (!ret && (tbl->it_type & TCE_PCI_SWINV_CREATE)) 1918 pnv_pci_ioda2_tce_invalidate(tbl, index, npages, false); 1919 1920 return ret; 1921 } 1922 1923 #ifdef CONFIG_IOMMU_API 1924 static int pnv_ioda2_tce_xchg(struct iommu_table *tbl, long index, 1925 unsigned long *hpa, enum dma_data_direction *direction) 1926 { 1927 long ret = pnv_tce_xchg(tbl, index, hpa, direction); 1928 1929 if (!ret && (tbl->it_type & 1930 (TCE_PCI_SWINV_CREATE | TCE_PCI_SWINV_FREE))) 1931 pnv_pci_ioda2_tce_invalidate(tbl, index, 1, false); 1932 1933 return ret; 1934 } 1935 #endif 1936 1937 static void pnv_ioda2_tce_free(struct iommu_table *tbl, long index, 1938 long npages) 1939 { 1940 pnv_tce_free(tbl, index, npages); 1941 1942 if (tbl->it_type & TCE_PCI_SWINV_FREE) 1943 pnv_pci_ioda2_tce_invalidate(tbl, index, npages, false); 1944 } 1945 1946 static void pnv_ioda2_table_free(struct iommu_table *tbl) 1947 { 1948 pnv_pci_ioda2_table_free_pages(tbl); 1949 iommu_free_table(tbl, "pnv"); 1950 } 1951 1952 static struct iommu_table_ops pnv_ioda2_iommu_ops = { 1953 .set = pnv_ioda2_tce_build, 1954 #ifdef CONFIG_IOMMU_API 1955 .exchange = pnv_ioda2_tce_xchg, 1956 #endif 1957 .clear = pnv_ioda2_tce_free, 1958 .get = pnv_tce_get, 1959 .free = pnv_ioda2_table_free, 1960 }; 1961 1962 static int pnv_pci_ioda_dev_dma_weight(struct pci_dev *dev, void *data) 1963 { 1964 unsigned int *weight = (unsigned int *)data; 1965 1966 /* This is quite simplistic. The "base" weight of a device 1967 * is 10. 0 means no DMA is to be accounted for it. 1968 */ 1969 if (dev->hdr_type != PCI_HEADER_TYPE_NORMAL) 1970 return 0; 1971 1972 if (dev->class == PCI_CLASS_SERIAL_USB_UHCI || 1973 dev->class == PCI_CLASS_SERIAL_USB_OHCI || 1974 dev->class == PCI_CLASS_SERIAL_USB_EHCI) 1975 *weight += 3; 1976 else if ((dev->class >> 8) == PCI_CLASS_STORAGE_RAID) 1977 *weight += 15; 1978 else 1979 *weight += 10; 1980 1981 return 0; 1982 } 1983 1984 static unsigned int pnv_pci_ioda_pe_dma_weight(struct pnv_ioda_pe *pe) 1985 { 1986 unsigned int weight = 0; 1987 1988 /* SRIOV VF has same DMA32 weight as its PF */ 1989 #ifdef CONFIG_PCI_IOV 1990 if ((pe->flags & PNV_IODA_PE_VF) && pe->parent_dev) { 1991 pnv_pci_ioda_dev_dma_weight(pe->parent_dev, &weight); 1992 return weight; 1993 } 1994 #endif 1995 1996 if ((pe->flags & PNV_IODA_PE_DEV) && pe->pdev) { 1997 pnv_pci_ioda_dev_dma_weight(pe->pdev, &weight); 1998 } else if ((pe->flags & PNV_IODA_PE_BUS) && pe->pbus) { 1999 struct pci_dev *pdev; 2000 2001 list_for_each_entry(pdev, &pe->pbus->devices, bus_list) 2002 pnv_pci_ioda_dev_dma_weight(pdev, &weight); 2003 } else if ((pe->flags & PNV_IODA_PE_BUS_ALL) && pe->pbus) { 2004 pci_walk_bus(pe->pbus, pnv_pci_ioda_dev_dma_weight, &weight); 2005 } 2006 2007 return weight; 2008 } 2009 2010 static void pnv_pci_ioda1_setup_dma_pe(struct pnv_phb *phb, 2011 struct pnv_ioda_pe *pe) 2012 { 2013 2014 struct page *tce_mem = NULL; 2015 struct iommu_table *tbl; 2016 unsigned int weight, total_weight = 0; 2017 unsigned int tce32_segsz, base, segs, avail, i; 2018 int64_t rc; 2019 void *addr; 2020 2021 /* XXX FIXME: Handle 64-bit only DMA devices */ 2022 /* XXX FIXME: Provide 64-bit DMA facilities & non-4K TCE tables etc.. */ 2023 /* XXX FIXME: Allocate multi-level tables on PHB3 */ 2024 weight = pnv_pci_ioda_pe_dma_weight(pe); 2025 if (!weight) 2026 return; 2027 2028 pci_walk_bus(phb->hose->bus, pnv_pci_ioda_dev_dma_weight, 2029 &total_weight); 2030 segs = (weight * phb->ioda.dma32_count) / total_weight; 2031 if (!segs) 2032 segs = 1; 2033 2034 /* 2035 * Allocate contiguous DMA32 segments. We begin with the expected 2036 * number of segments. With one more attempt, the number of DMA32 2037 * segments to be allocated is decreased by one until one segment 2038 * is allocated successfully. 2039 */ 2040 do { 2041 for (base = 0; base <= phb->ioda.dma32_count - segs; base++) { 2042 for (avail = 0, i = base; i < base + segs; i++) { 2043 if (phb->ioda.dma32_segmap[i] == 2044 IODA_INVALID_PE) 2045 avail++; 2046 } 2047 2048 if (avail == segs) 2049 goto found; 2050 } 2051 } while (--segs); 2052 2053 if (!segs) { 2054 pe_warn(pe, "No available DMA32 segments\n"); 2055 return; 2056 } 2057 2058 found: 2059 tbl = pnv_pci_table_alloc(phb->hose->node); 2060 iommu_register_group(&pe->table_group, phb->hose->global_number, 2061 pe->pe_number); 2062 pnv_pci_link_table_and_group(phb->hose->node, 0, tbl, &pe->table_group); 2063 2064 /* Grab a 32-bit TCE table */ 2065 pe_info(pe, "DMA weight %d (%d), assigned (%d) %d DMA32 segments\n", 2066 weight, total_weight, base, segs); 2067 pe_info(pe, " Setting up 32-bit TCE table at %08x..%08x\n", 2068 base * PNV_IODA1_DMA32_SEGSIZE, 2069 (base + segs) * PNV_IODA1_DMA32_SEGSIZE - 1); 2070 2071 /* XXX Currently, we allocate one big contiguous table for the 2072 * TCEs. We only really need one chunk per 256M of TCE space 2073 * (ie per segment) but that's an optimization for later, it 2074 * requires some added smarts with our get/put_tce implementation 2075 * 2076 * Each TCE page is 4KB in size and each TCE entry occupies 8 2077 * bytes 2078 */ 2079 tce32_segsz = PNV_IODA1_DMA32_SEGSIZE >> (IOMMU_PAGE_SHIFT_4K - 3); 2080 tce_mem = alloc_pages_node(phb->hose->node, GFP_KERNEL, 2081 get_order(tce32_segsz * segs)); 2082 if (!tce_mem) { 2083 pe_err(pe, " Failed to allocate a 32-bit TCE memory\n"); 2084 goto fail; 2085 } 2086 addr = page_address(tce_mem); 2087 memset(addr, 0, tce32_segsz * segs); 2088 2089 /* Configure HW */ 2090 for (i = 0; i < segs; i++) { 2091 rc = opal_pci_map_pe_dma_window(phb->opal_id, 2092 pe->pe_number, 2093 base + i, 1, 2094 __pa(addr) + tce32_segsz * i, 2095 tce32_segsz, IOMMU_PAGE_SIZE_4K); 2096 if (rc) { 2097 pe_err(pe, " Failed to configure 32-bit TCE table," 2098 " err %ld\n", rc); 2099 goto fail; 2100 } 2101 } 2102 2103 /* Setup DMA32 segment mapping */ 2104 for (i = base; i < base + segs; i++) 2105 phb->ioda.dma32_segmap[i] = pe->pe_number; 2106 2107 /* Setup linux iommu table */ 2108 pnv_pci_setup_iommu_table(tbl, addr, tce32_segsz * segs, 2109 base * PNV_IODA1_DMA32_SEGSIZE, 2110 IOMMU_PAGE_SHIFT_4K); 2111 2112 /* OPAL variant of P7IOC SW invalidated TCEs */ 2113 if (phb->ioda.tce_inval_reg) 2114 tbl->it_type |= (TCE_PCI_SWINV_CREATE | 2115 TCE_PCI_SWINV_FREE | 2116 TCE_PCI_SWINV_PAIR); 2117 2118 tbl->it_ops = &pnv_ioda1_iommu_ops; 2119 pe->table_group.tce32_start = tbl->it_offset << tbl->it_page_shift; 2120 pe->table_group.tce32_size = tbl->it_size << tbl->it_page_shift; 2121 iommu_init_table(tbl, phb->hose->node); 2122 2123 if (pe->flags & PNV_IODA_PE_DEV) { 2124 /* 2125 * Setting table base here only for carrying iommu_group 2126 * further down to let iommu_add_device() do the job. 2127 * pnv_pci_ioda_dma_dev_setup will override it later anyway. 2128 */ 2129 set_iommu_table_base(&pe->pdev->dev, tbl); 2130 iommu_add_device(&pe->pdev->dev); 2131 } else if (pe->flags & (PNV_IODA_PE_BUS | PNV_IODA_PE_BUS_ALL)) 2132 pnv_ioda_setup_bus_dma(pe, pe->pbus); 2133 2134 return; 2135 fail: 2136 /* XXX Failure: Try to fallback to 64-bit only ? */ 2137 if (tce_mem) 2138 __free_pages(tce_mem, get_order(tce32_segsz * segs)); 2139 if (tbl) { 2140 pnv_pci_unlink_table_and_group(tbl, &pe->table_group); 2141 iommu_free_table(tbl, "pnv"); 2142 } 2143 } 2144 2145 static long pnv_pci_ioda2_set_window(struct iommu_table_group *table_group, 2146 int num, struct iommu_table *tbl) 2147 { 2148 struct pnv_ioda_pe *pe = container_of(table_group, struct pnv_ioda_pe, 2149 table_group); 2150 struct pnv_phb *phb = pe->phb; 2151 int64_t rc; 2152 const unsigned long size = tbl->it_indirect_levels ? 2153 tbl->it_level_size : tbl->it_size; 2154 const __u64 start_addr = tbl->it_offset << tbl->it_page_shift; 2155 const __u64 win_size = tbl->it_size << tbl->it_page_shift; 2156 2157 pe_info(pe, "Setting up window#%d %llx..%llx pg=%x\n", num, 2158 start_addr, start_addr + win_size - 1, 2159 IOMMU_PAGE_SIZE(tbl)); 2160 2161 /* 2162 * Map TCE table through TVT. The TVE index is the PE number 2163 * shifted by 1 bit for 32-bits DMA space. 2164 */ 2165 rc = opal_pci_map_pe_dma_window(phb->opal_id, 2166 pe->pe_number, 2167 (pe->pe_number << 1) + num, 2168 tbl->it_indirect_levels + 1, 2169 __pa(tbl->it_base), 2170 size << 3, 2171 IOMMU_PAGE_SIZE(tbl)); 2172 if (rc) { 2173 pe_err(pe, "Failed to configure TCE table, err %ld\n", rc); 2174 return rc; 2175 } 2176 2177 pnv_pci_link_table_and_group(phb->hose->node, num, 2178 tbl, &pe->table_group); 2179 pnv_pci_ioda2_tce_invalidate_pe(pe); 2180 2181 return 0; 2182 } 2183 2184 static void pnv_pci_ioda2_set_bypass(struct pnv_ioda_pe *pe, bool enable) 2185 { 2186 uint16_t window_id = (pe->pe_number << 1 ) + 1; 2187 int64_t rc; 2188 2189 pe_info(pe, "%sabling 64-bit DMA bypass\n", enable ? "En" : "Dis"); 2190 if (enable) { 2191 phys_addr_t top = memblock_end_of_DRAM(); 2192 2193 top = roundup_pow_of_two(top); 2194 rc = opal_pci_map_pe_dma_window_real(pe->phb->opal_id, 2195 pe->pe_number, 2196 window_id, 2197 pe->tce_bypass_base, 2198 top); 2199 } else { 2200 rc = opal_pci_map_pe_dma_window_real(pe->phb->opal_id, 2201 pe->pe_number, 2202 window_id, 2203 pe->tce_bypass_base, 2204 0); 2205 } 2206 if (rc) 2207 pe_err(pe, "OPAL error %lld configuring bypass window\n", rc); 2208 else 2209 pe->tce_bypass_enabled = enable; 2210 } 2211 2212 static long pnv_pci_ioda2_table_alloc_pages(int nid, __u64 bus_offset, 2213 __u32 page_shift, __u64 window_size, __u32 levels, 2214 struct iommu_table *tbl); 2215 2216 static long pnv_pci_ioda2_create_table(struct iommu_table_group *table_group, 2217 int num, __u32 page_shift, __u64 window_size, __u32 levels, 2218 struct iommu_table **ptbl) 2219 { 2220 struct pnv_ioda_pe *pe = container_of(table_group, struct pnv_ioda_pe, 2221 table_group); 2222 int nid = pe->phb->hose->node; 2223 __u64 bus_offset = num ? pe->tce_bypass_base : table_group->tce32_start; 2224 long ret; 2225 struct iommu_table *tbl; 2226 2227 tbl = pnv_pci_table_alloc(nid); 2228 if (!tbl) 2229 return -ENOMEM; 2230 2231 ret = pnv_pci_ioda2_table_alloc_pages(nid, 2232 bus_offset, page_shift, window_size, 2233 levels, tbl); 2234 if (ret) { 2235 iommu_free_table(tbl, "pnv"); 2236 return ret; 2237 } 2238 2239 tbl->it_ops = &pnv_ioda2_iommu_ops; 2240 if (pe->phb->ioda.tce_inval_reg) 2241 tbl->it_type |= (TCE_PCI_SWINV_CREATE | TCE_PCI_SWINV_FREE); 2242 2243 *ptbl = tbl; 2244 2245 return 0; 2246 } 2247 2248 static long pnv_pci_ioda2_setup_default_config(struct pnv_ioda_pe *pe) 2249 { 2250 struct iommu_table *tbl = NULL; 2251 long rc; 2252 2253 /* 2254 * crashkernel= specifies the kdump kernel's maximum memory at 2255 * some offset and there is no guaranteed the result is a power 2256 * of 2, which will cause errors later. 2257 */ 2258 const u64 max_memory = __rounddown_pow_of_two(memory_hotplug_max()); 2259 2260 /* 2261 * In memory constrained environments, e.g. kdump kernel, the 2262 * DMA window can be larger than available memory, which will 2263 * cause errors later. 2264 */ 2265 const u64 window_size = min((u64)pe->table_group.tce32_size, max_memory); 2266 2267 rc = pnv_pci_ioda2_create_table(&pe->table_group, 0, 2268 IOMMU_PAGE_SHIFT_4K, 2269 window_size, 2270 POWERNV_IOMMU_DEFAULT_LEVELS, &tbl); 2271 if (rc) { 2272 pe_err(pe, "Failed to create 32-bit TCE table, err %ld", 2273 rc); 2274 return rc; 2275 } 2276 2277 iommu_init_table(tbl, pe->phb->hose->node); 2278 2279 rc = pnv_pci_ioda2_set_window(&pe->table_group, 0, tbl); 2280 if (rc) { 2281 pe_err(pe, "Failed to configure 32-bit TCE table, err %ld\n", 2282 rc); 2283 pnv_ioda2_table_free(tbl); 2284 return rc; 2285 } 2286 2287 if (!pnv_iommu_bypass_disabled) 2288 pnv_pci_ioda2_set_bypass(pe, true); 2289 2290 /* OPAL variant of PHB3 invalidated TCEs */ 2291 if (pe->phb->ioda.tce_inval_reg) 2292 tbl->it_type |= (TCE_PCI_SWINV_CREATE | TCE_PCI_SWINV_FREE); 2293 2294 /* 2295 * Setting table base here only for carrying iommu_group 2296 * further down to let iommu_add_device() do the job. 2297 * pnv_pci_ioda_dma_dev_setup will override it later anyway. 2298 */ 2299 if (pe->flags & PNV_IODA_PE_DEV) 2300 set_iommu_table_base(&pe->pdev->dev, tbl); 2301 2302 return 0; 2303 } 2304 2305 #if defined(CONFIG_IOMMU_API) || defined(CONFIG_PCI_IOV) 2306 static long pnv_pci_ioda2_unset_window(struct iommu_table_group *table_group, 2307 int num) 2308 { 2309 struct pnv_ioda_pe *pe = container_of(table_group, struct pnv_ioda_pe, 2310 table_group); 2311 struct pnv_phb *phb = pe->phb; 2312 long ret; 2313 2314 pe_info(pe, "Removing DMA window #%d\n", num); 2315 2316 ret = opal_pci_map_pe_dma_window(phb->opal_id, pe->pe_number, 2317 (pe->pe_number << 1) + num, 2318 0/* levels */, 0/* table address */, 2319 0/* table size */, 0/* page size */); 2320 if (ret) 2321 pe_warn(pe, "Unmapping failed, ret = %ld\n", ret); 2322 else 2323 pnv_pci_ioda2_tce_invalidate_pe(pe); 2324 2325 pnv_pci_unlink_table_and_group(table_group->tables[num], table_group); 2326 2327 return ret; 2328 } 2329 #endif 2330 2331 #ifdef CONFIG_IOMMU_API 2332 static unsigned long pnv_pci_ioda2_get_table_size(__u32 page_shift, 2333 __u64 window_size, __u32 levels) 2334 { 2335 unsigned long bytes = 0; 2336 const unsigned window_shift = ilog2(window_size); 2337 unsigned entries_shift = window_shift - page_shift; 2338 unsigned table_shift = entries_shift + 3; 2339 unsigned long tce_table_size = max(0x1000UL, 1UL << table_shift); 2340 unsigned long direct_table_size; 2341 2342 if (!levels || (levels > POWERNV_IOMMU_MAX_LEVELS) || 2343 (window_size > memory_hotplug_max()) || 2344 !is_power_of_2(window_size)) 2345 return 0; 2346 2347 /* Calculate a direct table size from window_size and levels */ 2348 entries_shift = (entries_shift + levels - 1) / levels; 2349 table_shift = entries_shift + 3; 2350 table_shift = max_t(unsigned, table_shift, PAGE_SHIFT); 2351 direct_table_size = 1UL << table_shift; 2352 2353 for ( ; levels; --levels) { 2354 bytes += _ALIGN_UP(tce_table_size, direct_table_size); 2355 2356 tce_table_size /= direct_table_size; 2357 tce_table_size <<= 3; 2358 tce_table_size = _ALIGN_UP(tce_table_size, direct_table_size); 2359 } 2360 2361 return bytes; 2362 } 2363 2364 static void pnv_ioda2_take_ownership(struct iommu_table_group *table_group) 2365 { 2366 struct pnv_ioda_pe *pe = container_of(table_group, struct pnv_ioda_pe, 2367 table_group); 2368 /* Store @tbl as pnv_pci_ioda2_unset_window() resets it */ 2369 struct iommu_table *tbl = pe->table_group.tables[0]; 2370 2371 pnv_pci_ioda2_set_bypass(pe, false); 2372 pnv_pci_ioda2_unset_window(&pe->table_group, 0); 2373 pnv_ioda2_table_free(tbl); 2374 } 2375 2376 static void pnv_ioda2_release_ownership(struct iommu_table_group *table_group) 2377 { 2378 struct pnv_ioda_pe *pe = container_of(table_group, struct pnv_ioda_pe, 2379 table_group); 2380 2381 pnv_pci_ioda2_setup_default_config(pe); 2382 } 2383 2384 static struct iommu_table_group_ops pnv_pci_ioda2_ops = { 2385 .get_table_size = pnv_pci_ioda2_get_table_size, 2386 .create_table = pnv_pci_ioda2_create_table, 2387 .set_window = pnv_pci_ioda2_set_window, 2388 .unset_window = pnv_pci_ioda2_unset_window, 2389 .take_ownership = pnv_ioda2_take_ownership, 2390 .release_ownership = pnv_ioda2_release_ownership, 2391 }; 2392 2393 static int gpe_table_group_to_npe_cb(struct device *dev, void *opaque) 2394 { 2395 struct pci_controller *hose; 2396 struct pnv_phb *phb; 2397 struct pnv_ioda_pe **ptmppe = opaque; 2398 struct pci_dev *pdev = container_of(dev, struct pci_dev, dev); 2399 struct pci_dn *pdn = pci_get_pdn(pdev); 2400 2401 if (!pdn || pdn->pe_number == IODA_INVALID_PE) 2402 return 0; 2403 2404 hose = pci_bus_to_host(pdev->bus); 2405 phb = hose->private_data; 2406 if (phb->type != PNV_PHB_NPU) 2407 return 0; 2408 2409 *ptmppe = &phb->ioda.pe_array[pdn->pe_number]; 2410 2411 return 1; 2412 } 2413 2414 /* 2415 * This returns PE of associated NPU. 2416 * This assumes that NPU is in the same IOMMU group with GPU and there is 2417 * no other PEs. 2418 */ 2419 static struct pnv_ioda_pe *gpe_table_group_to_npe( 2420 struct iommu_table_group *table_group) 2421 { 2422 struct pnv_ioda_pe *npe = NULL; 2423 int ret = iommu_group_for_each_dev(table_group->group, &npe, 2424 gpe_table_group_to_npe_cb); 2425 2426 BUG_ON(!ret || !npe); 2427 2428 return npe; 2429 } 2430 2431 static long pnv_pci_ioda2_npu_set_window(struct iommu_table_group *table_group, 2432 int num, struct iommu_table *tbl) 2433 { 2434 long ret = pnv_pci_ioda2_set_window(table_group, num, tbl); 2435 2436 if (ret) 2437 return ret; 2438 2439 ret = pnv_npu_set_window(gpe_table_group_to_npe(table_group), num, tbl); 2440 if (ret) 2441 pnv_pci_ioda2_unset_window(table_group, num); 2442 2443 return ret; 2444 } 2445 2446 static long pnv_pci_ioda2_npu_unset_window( 2447 struct iommu_table_group *table_group, 2448 int num) 2449 { 2450 long ret = pnv_pci_ioda2_unset_window(table_group, num); 2451 2452 if (ret) 2453 return ret; 2454 2455 return pnv_npu_unset_window(gpe_table_group_to_npe(table_group), num); 2456 } 2457 2458 static void pnv_ioda2_npu_take_ownership(struct iommu_table_group *table_group) 2459 { 2460 /* 2461 * Detach NPU first as pnv_ioda2_take_ownership() will destroy 2462 * the iommu_table if 32bit DMA is enabled. 2463 */ 2464 pnv_npu_take_ownership(gpe_table_group_to_npe(table_group)); 2465 pnv_ioda2_take_ownership(table_group); 2466 } 2467 2468 static struct iommu_table_group_ops pnv_pci_ioda2_npu_ops = { 2469 .get_table_size = pnv_pci_ioda2_get_table_size, 2470 .create_table = pnv_pci_ioda2_create_table, 2471 .set_window = pnv_pci_ioda2_npu_set_window, 2472 .unset_window = pnv_pci_ioda2_npu_unset_window, 2473 .take_ownership = pnv_ioda2_npu_take_ownership, 2474 .release_ownership = pnv_ioda2_release_ownership, 2475 }; 2476 2477 static void pnv_pci_ioda_setup_iommu_api(void) 2478 { 2479 struct pci_controller *hose, *tmp; 2480 struct pnv_phb *phb; 2481 struct pnv_ioda_pe *pe, *gpe; 2482 2483 /* 2484 * Now we have all PHBs discovered, time to add NPU devices to 2485 * the corresponding IOMMU groups. 2486 */ 2487 list_for_each_entry_safe(hose, tmp, &hose_list, list_node) { 2488 phb = hose->private_data; 2489 2490 if (phb->type != PNV_PHB_NPU) 2491 continue; 2492 2493 list_for_each_entry(pe, &phb->ioda.pe_list, list) { 2494 gpe = pnv_pci_npu_setup_iommu(pe); 2495 if (gpe) 2496 gpe->table_group.ops = &pnv_pci_ioda2_npu_ops; 2497 } 2498 } 2499 } 2500 #else /* !CONFIG_IOMMU_API */ 2501 static void pnv_pci_ioda_setup_iommu_api(void) { }; 2502 #endif 2503 2504 static void pnv_pci_ioda_setup_opal_tce_kill(struct pnv_phb *phb) 2505 { 2506 const __be64 *swinvp; 2507 2508 /* OPAL variant of PHB3 invalidated TCEs */ 2509 swinvp = of_get_property(phb->hose->dn, "ibm,opal-tce-kill", NULL); 2510 if (!swinvp) 2511 return; 2512 2513 phb->ioda.tce_inval_reg_phys = be64_to_cpup(swinvp); 2514 phb->ioda.tce_inval_reg = ioremap(phb->ioda.tce_inval_reg_phys, 8); 2515 } 2516 2517 static __be64 *pnv_pci_ioda2_table_do_alloc_pages(int nid, unsigned shift, 2518 unsigned levels, unsigned long limit, 2519 unsigned long *current_offset, unsigned long *total_allocated) 2520 { 2521 struct page *tce_mem = NULL; 2522 __be64 *addr, *tmp; 2523 unsigned order = max_t(unsigned, shift, PAGE_SHIFT) - PAGE_SHIFT; 2524 unsigned long allocated = 1UL << (order + PAGE_SHIFT); 2525 unsigned entries = 1UL << (shift - 3); 2526 long i; 2527 2528 tce_mem = alloc_pages_node(nid, GFP_KERNEL, order); 2529 if (!tce_mem) { 2530 pr_err("Failed to allocate a TCE memory, order=%d\n", order); 2531 return NULL; 2532 } 2533 addr = page_address(tce_mem); 2534 memset(addr, 0, allocated); 2535 *total_allocated += allocated; 2536 2537 --levels; 2538 if (!levels) { 2539 *current_offset += allocated; 2540 return addr; 2541 } 2542 2543 for (i = 0; i < entries; ++i) { 2544 tmp = pnv_pci_ioda2_table_do_alloc_pages(nid, shift, 2545 levels, limit, current_offset, total_allocated); 2546 if (!tmp) 2547 break; 2548 2549 addr[i] = cpu_to_be64(__pa(tmp) | 2550 TCE_PCI_READ | TCE_PCI_WRITE); 2551 2552 if (*current_offset >= limit) 2553 break; 2554 } 2555 2556 return addr; 2557 } 2558 2559 static void pnv_pci_ioda2_table_do_free_pages(__be64 *addr, 2560 unsigned long size, unsigned level); 2561 2562 static long pnv_pci_ioda2_table_alloc_pages(int nid, __u64 bus_offset, 2563 __u32 page_shift, __u64 window_size, __u32 levels, 2564 struct iommu_table *tbl) 2565 { 2566 void *addr; 2567 unsigned long offset = 0, level_shift, total_allocated = 0; 2568 const unsigned window_shift = ilog2(window_size); 2569 unsigned entries_shift = window_shift - page_shift; 2570 unsigned table_shift = max_t(unsigned, entries_shift + 3, PAGE_SHIFT); 2571 const unsigned long tce_table_size = 1UL << table_shift; 2572 2573 if (!levels || (levels > POWERNV_IOMMU_MAX_LEVELS)) 2574 return -EINVAL; 2575 2576 if ((window_size > memory_hotplug_max()) || !is_power_of_2(window_size)) 2577 return -EINVAL; 2578 2579 /* Adjust direct table size from window_size and levels */ 2580 entries_shift = (entries_shift + levels - 1) / levels; 2581 level_shift = entries_shift + 3; 2582 level_shift = max_t(unsigned, level_shift, PAGE_SHIFT); 2583 2584 /* Allocate TCE table */ 2585 addr = pnv_pci_ioda2_table_do_alloc_pages(nid, level_shift, 2586 levels, tce_table_size, &offset, &total_allocated); 2587 2588 /* addr==NULL means that the first level allocation failed */ 2589 if (!addr) 2590 return -ENOMEM; 2591 2592 /* 2593 * First level was allocated but some lower level failed as 2594 * we did not allocate as much as we wanted, 2595 * release partially allocated table. 2596 */ 2597 if (offset < tce_table_size) { 2598 pnv_pci_ioda2_table_do_free_pages(addr, 2599 1ULL << (level_shift - 3), levels - 1); 2600 return -ENOMEM; 2601 } 2602 2603 /* Setup linux iommu table */ 2604 pnv_pci_setup_iommu_table(tbl, addr, tce_table_size, bus_offset, 2605 page_shift); 2606 tbl->it_level_size = 1ULL << (level_shift - 3); 2607 tbl->it_indirect_levels = levels - 1; 2608 tbl->it_allocated_size = total_allocated; 2609 2610 pr_devel("Created TCE table: ws=%08llx ts=%lx @%08llx\n", 2611 window_size, tce_table_size, bus_offset); 2612 2613 return 0; 2614 } 2615 2616 static void pnv_pci_ioda2_table_do_free_pages(__be64 *addr, 2617 unsigned long size, unsigned level) 2618 { 2619 const unsigned long addr_ul = (unsigned long) addr & 2620 ~(TCE_PCI_READ | TCE_PCI_WRITE); 2621 2622 if (level) { 2623 long i; 2624 u64 *tmp = (u64 *) addr_ul; 2625 2626 for (i = 0; i < size; ++i) { 2627 unsigned long hpa = be64_to_cpu(tmp[i]); 2628 2629 if (!(hpa & (TCE_PCI_READ | TCE_PCI_WRITE))) 2630 continue; 2631 2632 pnv_pci_ioda2_table_do_free_pages(__va(hpa), size, 2633 level - 1); 2634 } 2635 } 2636 2637 free_pages(addr_ul, get_order(size << 3)); 2638 } 2639 2640 static void pnv_pci_ioda2_table_free_pages(struct iommu_table *tbl) 2641 { 2642 const unsigned long size = tbl->it_indirect_levels ? 2643 tbl->it_level_size : tbl->it_size; 2644 2645 if (!tbl->it_size) 2646 return; 2647 2648 pnv_pci_ioda2_table_do_free_pages((__be64 *)tbl->it_base, size, 2649 tbl->it_indirect_levels); 2650 } 2651 2652 static void pnv_pci_ioda2_setup_dma_pe(struct pnv_phb *phb, 2653 struct pnv_ioda_pe *pe) 2654 { 2655 int64_t rc; 2656 2657 /* TVE #1 is selected by PCI address bit 59 */ 2658 pe->tce_bypass_base = 1ull << 59; 2659 2660 iommu_register_group(&pe->table_group, phb->hose->global_number, 2661 pe->pe_number); 2662 2663 /* The PE will reserve all possible 32-bits space */ 2664 pe_info(pe, "Setting up 32-bit TCE table at 0..%08x\n", 2665 phb->ioda.m32_pci_base); 2666 2667 /* Setup linux iommu table */ 2668 pe->table_group.tce32_start = 0; 2669 pe->table_group.tce32_size = phb->ioda.m32_pci_base; 2670 pe->table_group.max_dynamic_windows_supported = 2671 IOMMU_TABLE_GROUP_MAX_TABLES; 2672 pe->table_group.max_levels = POWERNV_IOMMU_MAX_LEVELS; 2673 pe->table_group.pgsizes = SZ_4K | SZ_64K | SZ_16M; 2674 #ifdef CONFIG_IOMMU_API 2675 pe->table_group.ops = &pnv_pci_ioda2_ops; 2676 #endif 2677 2678 rc = pnv_pci_ioda2_setup_default_config(pe); 2679 if (rc) 2680 return; 2681 2682 if (pe->flags & PNV_IODA_PE_DEV) 2683 iommu_add_device(&pe->pdev->dev); 2684 else if (pe->flags & (PNV_IODA_PE_BUS | PNV_IODA_PE_BUS_ALL)) 2685 pnv_ioda_setup_bus_dma(pe, pe->pbus); 2686 } 2687 2688 static void pnv_ioda_setup_dma(struct pnv_phb *phb) 2689 { 2690 struct pci_controller *hose = phb->hose; 2691 struct pnv_ioda_pe *pe; 2692 unsigned int weight; 2693 2694 /* If we have more PE# than segments available, hand out one 2695 * per PE until we run out and let the rest fail. If not, 2696 * then we assign at least one segment per PE, plus more based 2697 * on the amount of devices under that PE 2698 */ 2699 pr_info("PCI: Domain %04x has %d available 32-bit DMA segments\n", 2700 hose->global_number, phb->ioda.dma32_count); 2701 2702 pnv_pci_ioda_setup_opal_tce_kill(phb); 2703 2704 /* Walk our PE list and configure their DMA segments */ 2705 list_for_each_entry(pe, &phb->ioda.pe_list, list) { 2706 weight = pnv_pci_ioda_pe_dma_weight(pe); 2707 if (!weight) 2708 continue; 2709 2710 /* 2711 * For IODA2 compliant PHB3, we needn't care about the weight. 2712 * The all available 32-bits DMA space will be assigned to 2713 * the specific PE. 2714 */ 2715 if (phb->type == PNV_PHB_IODA1) { 2716 pnv_pci_ioda1_setup_dma_pe(phb, pe); 2717 } else if (phb->type == PNV_PHB_IODA2) { 2718 pe_info(pe, "Assign DMA32 space\n"); 2719 pnv_pci_ioda2_setup_dma_pe(phb, pe); 2720 } else if (phb->type == PNV_PHB_NPU) { 2721 /* 2722 * We initialise the DMA space for an NPU PHB 2723 * after setup of the PHB is complete as we 2724 * point the NPU TVT to the the same location 2725 * as the PHB3 TVT. 2726 */ 2727 } 2728 } 2729 } 2730 2731 #ifdef CONFIG_PCI_MSI 2732 static void pnv_ioda2_msi_eoi(struct irq_data *d) 2733 { 2734 unsigned int hw_irq = (unsigned int)irqd_to_hwirq(d); 2735 struct irq_chip *chip = irq_data_get_irq_chip(d); 2736 struct pnv_phb *phb = container_of(chip, struct pnv_phb, 2737 ioda.irq_chip); 2738 int64_t rc; 2739 2740 rc = opal_pci_msi_eoi(phb->opal_id, hw_irq); 2741 WARN_ON_ONCE(rc); 2742 2743 icp_native_eoi(d); 2744 } 2745 2746 2747 static void set_msi_irq_chip(struct pnv_phb *phb, unsigned int virq) 2748 { 2749 struct irq_data *idata; 2750 struct irq_chip *ichip; 2751 2752 if (phb->type != PNV_PHB_IODA2) 2753 return; 2754 2755 if (!phb->ioda.irq_chip_init) { 2756 /* 2757 * First time we setup an MSI IRQ, we need to setup the 2758 * corresponding IRQ chip to route correctly. 2759 */ 2760 idata = irq_get_irq_data(virq); 2761 ichip = irq_data_get_irq_chip(idata); 2762 phb->ioda.irq_chip_init = 1; 2763 phb->ioda.irq_chip = *ichip; 2764 phb->ioda.irq_chip.irq_eoi = pnv_ioda2_msi_eoi; 2765 } 2766 irq_set_chip(virq, &phb->ioda.irq_chip); 2767 } 2768 2769 #ifdef CONFIG_CXL_BASE 2770 2771 struct device_node *pnv_pci_get_phb_node(struct pci_dev *dev) 2772 { 2773 struct pci_controller *hose = pci_bus_to_host(dev->bus); 2774 2775 return of_node_get(hose->dn); 2776 } 2777 EXPORT_SYMBOL(pnv_pci_get_phb_node); 2778 2779 int pnv_phb_to_cxl_mode(struct pci_dev *dev, uint64_t mode) 2780 { 2781 struct pci_controller *hose = pci_bus_to_host(dev->bus); 2782 struct pnv_phb *phb = hose->private_data; 2783 struct pnv_ioda_pe *pe; 2784 int rc; 2785 2786 pe = pnv_ioda_get_pe(dev); 2787 if (!pe) 2788 return -ENODEV; 2789 2790 pe_info(pe, "Switching PHB to CXL\n"); 2791 2792 rc = opal_pci_set_phb_cxl_mode(phb->opal_id, mode, pe->pe_number); 2793 if (rc) 2794 dev_err(&dev->dev, "opal_pci_set_phb_cxl_mode failed: %i\n", rc); 2795 2796 return rc; 2797 } 2798 EXPORT_SYMBOL(pnv_phb_to_cxl_mode); 2799 2800 /* Find PHB for cxl dev and allocate MSI hwirqs? 2801 * Returns the absolute hardware IRQ number 2802 */ 2803 int pnv_cxl_alloc_hwirqs(struct pci_dev *dev, int num) 2804 { 2805 struct pci_controller *hose = pci_bus_to_host(dev->bus); 2806 struct pnv_phb *phb = hose->private_data; 2807 int hwirq = msi_bitmap_alloc_hwirqs(&phb->msi_bmp, num); 2808 2809 if (hwirq < 0) { 2810 dev_warn(&dev->dev, "Failed to find a free MSI\n"); 2811 return -ENOSPC; 2812 } 2813 2814 return phb->msi_base + hwirq; 2815 } 2816 EXPORT_SYMBOL(pnv_cxl_alloc_hwirqs); 2817 2818 void pnv_cxl_release_hwirqs(struct pci_dev *dev, int hwirq, int num) 2819 { 2820 struct pci_controller *hose = pci_bus_to_host(dev->bus); 2821 struct pnv_phb *phb = hose->private_data; 2822 2823 msi_bitmap_free_hwirqs(&phb->msi_bmp, hwirq - phb->msi_base, num); 2824 } 2825 EXPORT_SYMBOL(pnv_cxl_release_hwirqs); 2826 2827 void pnv_cxl_release_hwirq_ranges(struct cxl_irq_ranges *irqs, 2828 struct pci_dev *dev) 2829 { 2830 struct pci_controller *hose = pci_bus_to_host(dev->bus); 2831 struct pnv_phb *phb = hose->private_data; 2832 int i, hwirq; 2833 2834 for (i = 1; i < CXL_IRQ_RANGES; i++) { 2835 if (!irqs->range[i]) 2836 continue; 2837 pr_devel("cxl release irq range 0x%x: offset: 0x%lx limit: %ld\n", 2838 i, irqs->offset[i], 2839 irqs->range[i]); 2840 hwirq = irqs->offset[i] - phb->msi_base; 2841 msi_bitmap_free_hwirqs(&phb->msi_bmp, hwirq, 2842 irqs->range[i]); 2843 } 2844 } 2845 EXPORT_SYMBOL(pnv_cxl_release_hwirq_ranges); 2846 2847 int pnv_cxl_alloc_hwirq_ranges(struct cxl_irq_ranges *irqs, 2848 struct pci_dev *dev, int num) 2849 { 2850 struct pci_controller *hose = pci_bus_to_host(dev->bus); 2851 struct pnv_phb *phb = hose->private_data; 2852 int i, hwirq, try; 2853 2854 memset(irqs, 0, sizeof(struct cxl_irq_ranges)); 2855 2856 /* 0 is reserved for the multiplexed PSL DSI interrupt */ 2857 for (i = 1; i < CXL_IRQ_RANGES && num; i++) { 2858 try = num; 2859 while (try) { 2860 hwirq = msi_bitmap_alloc_hwirqs(&phb->msi_bmp, try); 2861 if (hwirq >= 0) 2862 break; 2863 try /= 2; 2864 } 2865 if (!try) 2866 goto fail; 2867 2868 irqs->offset[i] = phb->msi_base + hwirq; 2869 irqs->range[i] = try; 2870 pr_devel("cxl alloc irq range 0x%x: offset: 0x%lx limit: %li\n", 2871 i, irqs->offset[i], irqs->range[i]); 2872 num -= try; 2873 } 2874 if (num) 2875 goto fail; 2876 2877 return 0; 2878 fail: 2879 pnv_cxl_release_hwirq_ranges(irqs, dev); 2880 return -ENOSPC; 2881 } 2882 EXPORT_SYMBOL(pnv_cxl_alloc_hwirq_ranges); 2883 2884 int pnv_cxl_get_irq_count(struct pci_dev *dev) 2885 { 2886 struct pci_controller *hose = pci_bus_to_host(dev->bus); 2887 struct pnv_phb *phb = hose->private_data; 2888 2889 return phb->msi_bmp.irq_count; 2890 } 2891 EXPORT_SYMBOL(pnv_cxl_get_irq_count); 2892 2893 int pnv_cxl_ioda_msi_setup(struct pci_dev *dev, unsigned int hwirq, 2894 unsigned int virq) 2895 { 2896 struct pci_controller *hose = pci_bus_to_host(dev->bus); 2897 struct pnv_phb *phb = hose->private_data; 2898 unsigned int xive_num = hwirq - phb->msi_base; 2899 struct pnv_ioda_pe *pe; 2900 int rc; 2901 2902 if (!(pe = pnv_ioda_get_pe(dev))) 2903 return -ENODEV; 2904 2905 /* Assign XIVE to PE */ 2906 rc = opal_pci_set_xive_pe(phb->opal_id, pe->pe_number, xive_num); 2907 if (rc) { 2908 pe_warn(pe, "%s: OPAL error %d setting msi_base 0x%x " 2909 "hwirq 0x%x XIVE 0x%x PE\n", 2910 pci_name(dev), rc, phb->msi_base, hwirq, xive_num); 2911 return -EIO; 2912 } 2913 set_msi_irq_chip(phb, virq); 2914 2915 return 0; 2916 } 2917 EXPORT_SYMBOL(pnv_cxl_ioda_msi_setup); 2918 #endif 2919 2920 static int pnv_pci_ioda_msi_setup(struct pnv_phb *phb, struct pci_dev *dev, 2921 unsigned int hwirq, unsigned int virq, 2922 unsigned int is_64, struct msi_msg *msg) 2923 { 2924 struct pnv_ioda_pe *pe = pnv_ioda_get_pe(dev); 2925 unsigned int xive_num = hwirq - phb->msi_base; 2926 __be32 data; 2927 int rc; 2928 2929 /* No PE assigned ? bail out ... no MSI for you ! */ 2930 if (pe == NULL) 2931 return -ENXIO; 2932 2933 /* Check if we have an MVE */ 2934 if (pe->mve_number < 0) 2935 return -ENXIO; 2936 2937 /* Force 32-bit MSI on some broken devices */ 2938 if (dev->no_64bit_msi) 2939 is_64 = 0; 2940 2941 /* Assign XIVE to PE */ 2942 rc = opal_pci_set_xive_pe(phb->opal_id, pe->pe_number, xive_num); 2943 if (rc) { 2944 pr_warn("%s: OPAL error %d setting XIVE %d PE\n", 2945 pci_name(dev), rc, xive_num); 2946 return -EIO; 2947 } 2948 2949 if (is_64) { 2950 __be64 addr64; 2951 2952 rc = opal_get_msi_64(phb->opal_id, pe->mve_number, xive_num, 1, 2953 &addr64, &data); 2954 if (rc) { 2955 pr_warn("%s: OPAL error %d getting 64-bit MSI data\n", 2956 pci_name(dev), rc); 2957 return -EIO; 2958 } 2959 msg->address_hi = be64_to_cpu(addr64) >> 32; 2960 msg->address_lo = be64_to_cpu(addr64) & 0xfffffffful; 2961 } else { 2962 __be32 addr32; 2963 2964 rc = opal_get_msi_32(phb->opal_id, pe->mve_number, xive_num, 1, 2965 &addr32, &data); 2966 if (rc) { 2967 pr_warn("%s: OPAL error %d getting 32-bit MSI data\n", 2968 pci_name(dev), rc); 2969 return -EIO; 2970 } 2971 msg->address_hi = 0; 2972 msg->address_lo = be32_to_cpu(addr32); 2973 } 2974 msg->data = be32_to_cpu(data); 2975 2976 set_msi_irq_chip(phb, virq); 2977 2978 pr_devel("%s: %s-bit MSI on hwirq %x (xive #%d)," 2979 " address=%x_%08x data=%x PE# %d\n", 2980 pci_name(dev), is_64 ? "64" : "32", hwirq, xive_num, 2981 msg->address_hi, msg->address_lo, data, pe->pe_number); 2982 2983 return 0; 2984 } 2985 2986 static void pnv_pci_init_ioda_msis(struct pnv_phb *phb) 2987 { 2988 unsigned int count; 2989 const __be32 *prop = of_get_property(phb->hose->dn, 2990 "ibm,opal-msi-ranges", NULL); 2991 if (!prop) { 2992 /* BML Fallback */ 2993 prop = of_get_property(phb->hose->dn, "msi-ranges", NULL); 2994 } 2995 if (!prop) 2996 return; 2997 2998 phb->msi_base = be32_to_cpup(prop); 2999 count = be32_to_cpup(prop + 1); 3000 if (msi_bitmap_alloc(&phb->msi_bmp, count, phb->hose->dn)) { 3001 pr_err("PCI %d: Failed to allocate MSI bitmap !\n", 3002 phb->hose->global_number); 3003 return; 3004 } 3005 3006 phb->msi_setup = pnv_pci_ioda_msi_setup; 3007 phb->msi32_support = 1; 3008 pr_info(" Allocated bitmap for %d MSIs (base IRQ 0x%x)\n", 3009 count, phb->msi_base); 3010 } 3011 #else 3012 static void pnv_pci_init_ioda_msis(struct pnv_phb *phb) { } 3013 #endif /* CONFIG_PCI_MSI */ 3014 3015 #ifdef CONFIG_PCI_IOV 3016 static void pnv_pci_ioda_fixup_iov_resources(struct pci_dev *pdev) 3017 { 3018 struct pci_controller *hose = pci_bus_to_host(pdev->bus); 3019 struct pnv_phb *phb = hose->private_data; 3020 const resource_size_t gate = phb->ioda.m64_segsize >> 2; 3021 struct resource *res; 3022 int i; 3023 resource_size_t size, total_vf_bar_sz; 3024 struct pci_dn *pdn; 3025 int mul, total_vfs; 3026 3027 if (!pdev->is_physfn || pdev->is_added) 3028 return; 3029 3030 pdn = pci_get_pdn(pdev); 3031 pdn->vfs_expanded = 0; 3032 pdn->m64_single_mode = false; 3033 3034 total_vfs = pci_sriov_get_totalvfs(pdev); 3035 mul = phb->ioda.total_pe_num; 3036 total_vf_bar_sz = 0; 3037 3038 for (i = 0; i < PCI_SRIOV_NUM_BARS; i++) { 3039 res = &pdev->resource[i + PCI_IOV_RESOURCES]; 3040 if (!res->flags || res->parent) 3041 continue; 3042 if (!pnv_pci_is_mem_pref_64(res->flags)) { 3043 dev_warn(&pdev->dev, "Don't support SR-IOV with" 3044 " non M64 VF BAR%d: %pR. \n", 3045 i, res); 3046 goto truncate_iov; 3047 } 3048 3049 total_vf_bar_sz += pci_iov_resource_size(pdev, 3050 i + PCI_IOV_RESOURCES); 3051 3052 /* 3053 * If bigger than quarter of M64 segment size, just round up 3054 * power of two. 3055 * 3056 * Generally, one M64 BAR maps one IOV BAR. To avoid conflict 3057 * with other devices, IOV BAR size is expanded to be 3058 * (total_pe * VF_BAR_size). When VF_BAR_size is half of M64 3059 * segment size , the expanded size would equal to half of the 3060 * whole M64 space size, which will exhaust the M64 Space and 3061 * limit the system flexibility. This is a design decision to 3062 * set the boundary to quarter of the M64 segment size. 3063 */ 3064 if (total_vf_bar_sz > gate) { 3065 mul = roundup_pow_of_two(total_vfs); 3066 dev_info(&pdev->dev, 3067 "VF BAR Total IOV size %llx > %llx, roundup to %d VFs\n", 3068 total_vf_bar_sz, gate, mul); 3069 pdn->m64_single_mode = true; 3070 break; 3071 } 3072 } 3073 3074 for (i = 0; i < PCI_SRIOV_NUM_BARS; i++) { 3075 res = &pdev->resource[i + PCI_IOV_RESOURCES]; 3076 if (!res->flags || res->parent) 3077 continue; 3078 3079 size = pci_iov_resource_size(pdev, i + PCI_IOV_RESOURCES); 3080 /* 3081 * On PHB3, the minimum size alignment of M64 BAR in single 3082 * mode is 32MB. 3083 */ 3084 if (pdn->m64_single_mode && (size < SZ_32M)) 3085 goto truncate_iov; 3086 dev_dbg(&pdev->dev, " Fixing VF BAR%d: %pR to\n", i, res); 3087 res->end = res->start + size * mul - 1; 3088 dev_dbg(&pdev->dev, " %pR\n", res); 3089 dev_info(&pdev->dev, "VF BAR%d: %pR (expanded to %d VFs for PE alignment)", 3090 i, res, mul); 3091 } 3092 pdn->vfs_expanded = mul; 3093 3094 return; 3095 3096 truncate_iov: 3097 /* To save MMIO space, IOV BAR is truncated. */ 3098 for (i = 0; i < PCI_SRIOV_NUM_BARS; i++) { 3099 res = &pdev->resource[i + PCI_IOV_RESOURCES]; 3100 res->flags = 0; 3101 res->end = res->start - 1; 3102 } 3103 } 3104 #endif /* CONFIG_PCI_IOV */ 3105 3106 static void pnv_ioda_setup_pe_res(struct pnv_ioda_pe *pe, 3107 struct resource *res) 3108 { 3109 struct pnv_phb *phb = pe->phb; 3110 struct pci_bus_region region; 3111 int index; 3112 int64_t rc; 3113 3114 if (!res || !res->flags || res->start > res->end) 3115 return; 3116 3117 if (res->flags & IORESOURCE_IO) { 3118 region.start = res->start - phb->ioda.io_pci_base; 3119 region.end = res->end - phb->ioda.io_pci_base; 3120 index = region.start / phb->ioda.io_segsize; 3121 3122 while (index < phb->ioda.total_pe_num && 3123 region.start <= region.end) { 3124 phb->ioda.io_segmap[index] = pe->pe_number; 3125 rc = opal_pci_map_pe_mmio_window(phb->opal_id, 3126 pe->pe_number, OPAL_IO_WINDOW_TYPE, 0, index); 3127 if (rc != OPAL_SUCCESS) { 3128 pr_err("%s: Error %lld mapping IO segment#%d to PE#%d\n", 3129 __func__, rc, index, pe->pe_number); 3130 break; 3131 } 3132 3133 region.start += phb->ioda.io_segsize; 3134 index++; 3135 } 3136 } else if ((res->flags & IORESOURCE_MEM) && 3137 !pnv_pci_is_mem_pref_64(res->flags)) { 3138 region.start = res->start - 3139 phb->hose->mem_offset[0] - 3140 phb->ioda.m32_pci_base; 3141 region.end = res->end - 3142 phb->hose->mem_offset[0] - 3143 phb->ioda.m32_pci_base; 3144 index = region.start / phb->ioda.m32_segsize; 3145 3146 while (index < phb->ioda.total_pe_num && 3147 region.start <= region.end) { 3148 phb->ioda.m32_segmap[index] = pe->pe_number; 3149 rc = opal_pci_map_pe_mmio_window(phb->opal_id, 3150 pe->pe_number, OPAL_M32_WINDOW_TYPE, 0, index); 3151 if (rc != OPAL_SUCCESS) { 3152 pr_err("%s: Error %lld mapping M32 segment#%d to PE#%d", 3153 __func__, rc, index, pe->pe_number); 3154 break; 3155 } 3156 3157 region.start += phb->ioda.m32_segsize; 3158 index++; 3159 } 3160 } 3161 } 3162 3163 /* 3164 * This function is supposed to be called on basis of PE from top 3165 * to bottom style. So the the I/O or MMIO segment assigned to 3166 * parent PE could be overrided by its child PEs if necessary. 3167 */ 3168 static void pnv_ioda_setup_pe_seg(struct pnv_ioda_pe *pe) 3169 { 3170 struct pci_dev *pdev; 3171 int i; 3172 3173 /* 3174 * NOTE: We only care PCI bus based PE for now. For PCI 3175 * device based PE, for example SRIOV sensitive VF should 3176 * be figured out later. 3177 */ 3178 BUG_ON(!(pe->flags & (PNV_IODA_PE_BUS | PNV_IODA_PE_BUS_ALL))); 3179 3180 list_for_each_entry(pdev, &pe->pbus->devices, bus_list) { 3181 for (i = 0; i <= PCI_ROM_RESOURCE; i++) 3182 pnv_ioda_setup_pe_res(pe, &pdev->resource[i]); 3183 3184 /* 3185 * If the PE contains all subordinate PCI buses, the 3186 * windows of the child bridges should be mapped to 3187 * the PE as well. 3188 */ 3189 if (!(pe->flags & PNV_IODA_PE_BUS_ALL) || !pci_is_bridge(pdev)) 3190 continue; 3191 for (i = 0; i < PCI_BRIDGE_RESOURCE_NUM; i++) 3192 pnv_ioda_setup_pe_res(pe, 3193 &pdev->resource[PCI_BRIDGE_RESOURCES + i]); 3194 } 3195 } 3196 3197 static void pnv_pci_ioda_setup_seg(void) 3198 { 3199 struct pci_controller *tmp, *hose; 3200 struct pnv_phb *phb; 3201 struct pnv_ioda_pe *pe; 3202 3203 list_for_each_entry_safe(hose, tmp, &hose_list, list_node) { 3204 phb = hose->private_data; 3205 3206 /* NPU PHB does not support IO or MMIO segmentation */ 3207 if (phb->type == PNV_PHB_NPU) 3208 continue; 3209 3210 list_for_each_entry(pe, &phb->ioda.pe_list, list) { 3211 pnv_ioda_setup_pe_seg(pe); 3212 } 3213 } 3214 } 3215 3216 static void pnv_pci_ioda_setup_DMA(void) 3217 { 3218 struct pci_controller *hose, *tmp; 3219 struct pnv_phb *phb; 3220 3221 list_for_each_entry_safe(hose, tmp, &hose_list, list_node) { 3222 pnv_ioda_setup_dma(hose->private_data); 3223 3224 /* Mark the PHB initialization done */ 3225 phb = hose->private_data; 3226 phb->initialized = 1; 3227 } 3228 3229 pnv_pci_ioda_setup_iommu_api(); 3230 } 3231 3232 static void pnv_pci_ioda_create_dbgfs(void) 3233 { 3234 #ifdef CONFIG_DEBUG_FS 3235 struct pci_controller *hose, *tmp; 3236 struct pnv_phb *phb; 3237 char name[16]; 3238 3239 list_for_each_entry_safe(hose, tmp, &hose_list, list_node) { 3240 phb = hose->private_data; 3241 3242 sprintf(name, "PCI%04x", hose->global_number); 3243 phb->dbgfs = debugfs_create_dir(name, powerpc_debugfs_root); 3244 if (!phb->dbgfs) 3245 pr_warning("%s: Error on creating debugfs on PHB#%x\n", 3246 __func__, hose->global_number); 3247 } 3248 #endif /* CONFIG_DEBUG_FS */ 3249 } 3250 3251 static void pnv_pci_ioda_fixup(void) 3252 { 3253 pnv_pci_ioda_setup_PEs(); 3254 pnv_pci_ioda_setup_seg(); 3255 pnv_pci_ioda_setup_DMA(); 3256 3257 pnv_pci_ioda_create_dbgfs(); 3258 3259 #ifdef CONFIG_EEH 3260 eeh_init(); 3261 eeh_addr_cache_build(); 3262 #endif 3263 } 3264 3265 /* 3266 * Returns the alignment for I/O or memory windows for P2P 3267 * bridges. That actually depends on how PEs are segmented. 3268 * For now, we return I/O or M32 segment size for PE sensitive 3269 * P2P bridges. Otherwise, the default values (4KiB for I/O, 3270 * 1MiB for memory) will be returned. 3271 * 3272 * The current PCI bus might be put into one PE, which was 3273 * create against the parent PCI bridge. For that case, we 3274 * needn't enlarge the alignment so that we can save some 3275 * resources. 3276 */ 3277 static resource_size_t pnv_pci_window_alignment(struct pci_bus *bus, 3278 unsigned long type) 3279 { 3280 struct pci_dev *bridge; 3281 struct pci_controller *hose = pci_bus_to_host(bus); 3282 struct pnv_phb *phb = hose->private_data; 3283 int num_pci_bridges = 0; 3284 3285 bridge = bus->self; 3286 while (bridge) { 3287 if (pci_pcie_type(bridge) == PCI_EXP_TYPE_PCI_BRIDGE) { 3288 num_pci_bridges++; 3289 if (num_pci_bridges >= 2) 3290 return 1; 3291 } 3292 3293 bridge = bridge->bus->self; 3294 } 3295 3296 /* We fail back to M32 if M64 isn't supported */ 3297 if (phb->ioda.m64_segsize && 3298 pnv_pci_is_mem_pref_64(type)) 3299 return phb->ioda.m64_segsize; 3300 if (type & IORESOURCE_MEM) 3301 return phb->ioda.m32_segsize; 3302 3303 return phb->ioda.io_segsize; 3304 } 3305 3306 #ifdef CONFIG_PCI_IOV 3307 static resource_size_t pnv_pci_iov_resource_alignment(struct pci_dev *pdev, 3308 int resno) 3309 { 3310 struct pci_controller *hose = pci_bus_to_host(pdev->bus); 3311 struct pnv_phb *phb = hose->private_data; 3312 struct pci_dn *pdn = pci_get_pdn(pdev); 3313 resource_size_t align; 3314 3315 /* 3316 * On PowerNV platform, IOV BAR is mapped by M64 BAR to enable the 3317 * SR-IOV. While from hardware perspective, the range mapped by M64 3318 * BAR should be size aligned. 3319 * 3320 * When IOV BAR is mapped with M64 BAR in Single PE mode, the extra 3321 * powernv-specific hardware restriction is gone. But if just use the 3322 * VF BAR size as the alignment, PF BAR / VF BAR may be allocated with 3323 * in one segment of M64 #15, which introduces the PE conflict between 3324 * PF and VF. Based on this, the minimum alignment of an IOV BAR is 3325 * m64_segsize. 3326 * 3327 * This function returns the total IOV BAR size if M64 BAR is in 3328 * Shared PE mode or just VF BAR size if not. 3329 * If the M64 BAR is in Single PE mode, return the VF BAR size or 3330 * M64 segment size if IOV BAR size is less. 3331 */ 3332 align = pci_iov_resource_size(pdev, resno); 3333 if (!pdn->vfs_expanded) 3334 return align; 3335 if (pdn->m64_single_mode) 3336 return max(align, (resource_size_t)phb->ioda.m64_segsize); 3337 3338 return pdn->vfs_expanded * align; 3339 } 3340 #endif /* CONFIG_PCI_IOV */ 3341 3342 /* Prevent enabling devices for which we couldn't properly 3343 * assign a PE 3344 */ 3345 static bool pnv_pci_enable_device_hook(struct pci_dev *dev) 3346 { 3347 struct pci_controller *hose = pci_bus_to_host(dev->bus); 3348 struct pnv_phb *phb = hose->private_data; 3349 struct pci_dn *pdn; 3350 3351 /* The function is probably called while the PEs have 3352 * not be created yet. For example, resource reassignment 3353 * during PCI probe period. We just skip the check if 3354 * PEs isn't ready. 3355 */ 3356 if (!phb->initialized) 3357 return true; 3358 3359 pdn = pci_get_pdn(dev); 3360 if (!pdn || pdn->pe_number == IODA_INVALID_PE) 3361 return false; 3362 3363 return true; 3364 } 3365 3366 static void pnv_pci_ioda_shutdown(struct pci_controller *hose) 3367 { 3368 struct pnv_phb *phb = hose->private_data; 3369 3370 opal_pci_reset(phb->opal_id, OPAL_RESET_PCI_IODA_TABLE, 3371 OPAL_ASSERT_RESET); 3372 } 3373 3374 static const struct pci_controller_ops pnv_pci_ioda_controller_ops = { 3375 .dma_dev_setup = pnv_pci_dma_dev_setup, 3376 .dma_bus_setup = pnv_pci_dma_bus_setup, 3377 #ifdef CONFIG_PCI_MSI 3378 .setup_msi_irqs = pnv_setup_msi_irqs, 3379 .teardown_msi_irqs = pnv_teardown_msi_irqs, 3380 #endif 3381 .enable_device_hook = pnv_pci_enable_device_hook, 3382 .window_alignment = pnv_pci_window_alignment, 3383 .reset_secondary_bus = pnv_pci_reset_secondary_bus, 3384 .dma_set_mask = pnv_pci_ioda_dma_set_mask, 3385 .dma_get_required_mask = pnv_pci_ioda_dma_get_required_mask, 3386 .shutdown = pnv_pci_ioda_shutdown, 3387 }; 3388 3389 static int pnv_npu_dma_set_mask(struct pci_dev *npdev, u64 dma_mask) 3390 { 3391 dev_err_once(&npdev->dev, 3392 "%s operation unsupported for NVLink devices\n", 3393 __func__); 3394 return -EPERM; 3395 } 3396 3397 static const struct pci_controller_ops pnv_npu_ioda_controller_ops = { 3398 .dma_dev_setup = pnv_pci_dma_dev_setup, 3399 #ifdef CONFIG_PCI_MSI 3400 .setup_msi_irqs = pnv_setup_msi_irqs, 3401 .teardown_msi_irqs = pnv_teardown_msi_irqs, 3402 #endif 3403 .enable_device_hook = pnv_pci_enable_device_hook, 3404 .window_alignment = pnv_pci_window_alignment, 3405 .reset_secondary_bus = pnv_pci_reset_secondary_bus, 3406 .dma_set_mask = pnv_npu_dma_set_mask, 3407 .shutdown = pnv_pci_ioda_shutdown, 3408 }; 3409 3410 static void __init pnv_pci_init_ioda_phb(struct device_node *np, 3411 u64 hub_id, int ioda_type) 3412 { 3413 struct pci_controller *hose; 3414 struct pnv_phb *phb; 3415 unsigned long size, m64map_off, m32map_off, pemap_off; 3416 unsigned long iomap_off = 0, dma32map_off = 0; 3417 const __be64 *prop64; 3418 const __be32 *prop32; 3419 int len; 3420 unsigned int segno; 3421 u64 phb_id; 3422 void *aux; 3423 long rc; 3424 3425 pr_info("Initializing IODA%d OPAL PHB %s\n", ioda_type, np->full_name); 3426 3427 prop64 = of_get_property(np, "ibm,opal-phbid", NULL); 3428 if (!prop64) { 3429 pr_err(" Missing \"ibm,opal-phbid\" property !\n"); 3430 return; 3431 } 3432 phb_id = be64_to_cpup(prop64); 3433 pr_debug(" PHB-ID : 0x%016llx\n", phb_id); 3434 3435 phb = memblock_virt_alloc(sizeof(struct pnv_phb), 0); 3436 3437 /* Allocate PCI controller */ 3438 phb->hose = hose = pcibios_alloc_controller(np); 3439 if (!phb->hose) { 3440 pr_err(" Can't allocate PCI controller for %s\n", 3441 np->full_name); 3442 memblock_free(__pa(phb), sizeof(struct pnv_phb)); 3443 return; 3444 } 3445 3446 spin_lock_init(&phb->lock); 3447 prop32 = of_get_property(np, "bus-range", &len); 3448 if (prop32 && len == 8) { 3449 hose->first_busno = be32_to_cpu(prop32[0]); 3450 hose->last_busno = be32_to_cpu(prop32[1]); 3451 } else { 3452 pr_warn(" Broken <bus-range> on %s\n", np->full_name); 3453 hose->first_busno = 0; 3454 hose->last_busno = 0xff; 3455 } 3456 hose->private_data = phb; 3457 phb->hub_id = hub_id; 3458 phb->opal_id = phb_id; 3459 phb->type = ioda_type; 3460 mutex_init(&phb->ioda.pe_alloc_mutex); 3461 3462 /* Detect specific models for error handling */ 3463 if (of_device_is_compatible(np, "ibm,p7ioc-pciex")) 3464 phb->model = PNV_PHB_MODEL_P7IOC; 3465 else if (of_device_is_compatible(np, "ibm,power8-pciex")) 3466 phb->model = PNV_PHB_MODEL_PHB3; 3467 else if (of_device_is_compatible(np, "ibm,power8-npu-pciex")) 3468 phb->model = PNV_PHB_MODEL_NPU; 3469 else 3470 phb->model = PNV_PHB_MODEL_UNKNOWN; 3471 3472 /* Parse 32-bit and IO ranges (if any) */ 3473 pci_process_bridge_OF_ranges(hose, np, !hose->global_number); 3474 3475 /* Get registers */ 3476 phb->regs = of_iomap(np, 0); 3477 if (phb->regs == NULL) 3478 pr_err(" Failed to map registers !\n"); 3479 3480 /* Initialize more IODA stuff */ 3481 phb->ioda.total_pe_num = 1; 3482 prop32 = of_get_property(np, "ibm,opal-num-pes", NULL); 3483 if (prop32) 3484 phb->ioda.total_pe_num = be32_to_cpup(prop32); 3485 prop32 = of_get_property(np, "ibm,opal-reserved-pe", NULL); 3486 if (prop32) 3487 phb->ioda.reserved_pe_idx = be32_to_cpup(prop32); 3488 3489 /* Parse 64-bit MMIO range */ 3490 pnv_ioda_parse_m64_window(phb); 3491 3492 phb->ioda.m32_size = resource_size(&hose->mem_resources[0]); 3493 /* FW Has already off top 64k of M32 space (MSI space) */ 3494 phb->ioda.m32_size += 0x10000; 3495 3496 phb->ioda.m32_segsize = phb->ioda.m32_size / phb->ioda.total_pe_num; 3497 phb->ioda.m32_pci_base = hose->mem_resources[0].start - hose->mem_offset[0]; 3498 phb->ioda.io_size = hose->pci_io_size; 3499 phb->ioda.io_segsize = phb->ioda.io_size / phb->ioda.total_pe_num; 3500 phb->ioda.io_pci_base = 0; /* XXX calculate this ? */ 3501 3502 /* Calculate how many 32-bit TCE segments we have */ 3503 phb->ioda.dma32_count = phb->ioda.m32_pci_base / 3504 PNV_IODA1_DMA32_SEGSIZE; 3505 3506 /* Allocate aux data & arrays. We don't have IO ports on PHB3 */ 3507 size = _ALIGN_UP(max_t(unsigned, phb->ioda.total_pe_num, 8) / 8, 3508 sizeof(unsigned long)); 3509 m64map_off = size; 3510 size += phb->ioda.total_pe_num * sizeof(phb->ioda.m64_segmap[0]); 3511 m32map_off = size; 3512 size += phb->ioda.total_pe_num * sizeof(phb->ioda.m32_segmap[0]); 3513 if (phb->type == PNV_PHB_IODA1) { 3514 iomap_off = size; 3515 size += phb->ioda.total_pe_num * sizeof(phb->ioda.io_segmap[0]); 3516 dma32map_off = size; 3517 size += phb->ioda.dma32_count * 3518 sizeof(phb->ioda.dma32_segmap[0]); 3519 } 3520 pemap_off = size; 3521 size += phb->ioda.total_pe_num * sizeof(struct pnv_ioda_pe); 3522 aux = memblock_virt_alloc(size, 0); 3523 phb->ioda.pe_alloc = aux; 3524 phb->ioda.m64_segmap = aux + m64map_off; 3525 phb->ioda.m32_segmap = aux + m32map_off; 3526 for (segno = 0; segno < phb->ioda.total_pe_num; segno++) { 3527 phb->ioda.m64_segmap[segno] = IODA_INVALID_PE; 3528 phb->ioda.m32_segmap[segno] = IODA_INVALID_PE; 3529 } 3530 if (phb->type == PNV_PHB_IODA1) { 3531 phb->ioda.io_segmap = aux + iomap_off; 3532 for (segno = 0; segno < phb->ioda.total_pe_num; segno++) 3533 phb->ioda.io_segmap[segno] = IODA_INVALID_PE; 3534 3535 phb->ioda.dma32_segmap = aux + dma32map_off; 3536 for (segno = 0; segno < phb->ioda.dma32_count; segno++) 3537 phb->ioda.dma32_segmap[segno] = IODA_INVALID_PE; 3538 } 3539 phb->ioda.pe_array = aux + pemap_off; 3540 set_bit(phb->ioda.reserved_pe_idx, phb->ioda.pe_alloc); 3541 3542 INIT_LIST_HEAD(&phb->ioda.pe_list); 3543 mutex_init(&phb->ioda.pe_list_mutex); 3544 3545 /* Calculate how many 32-bit TCE segments we have */ 3546 phb->ioda.dma32_count = phb->ioda.m32_pci_base / 3547 PNV_IODA1_DMA32_SEGSIZE; 3548 3549 #if 0 /* We should really do that ... */ 3550 rc = opal_pci_set_phb_mem_window(opal->phb_id, 3551 window_type, 3552 window_num, 3553 starting_real_address, 3554 starting_pci_address, 3555 segment_size); 3556 #endif 3557 3558 pr_info(" %03d (%03d) PE's M32: 0x%x [segment=0x%x]\n", 3559 phb->ioda.total_pe_num, phb->ioda.reserved_pe_idx, 3560 phb->ioda.m32_size, phb->ioda.m32_segsize); 3561 if (phb->ioda.m64_size) 3562 pr_info(" M64: 0x%lx [segment=0x%lx]\n", 3563 phb->ioda.m64_size, phb->ioda.m64_segsize); 3564 if (phb->ioda.io_size) 3565 pr_info(" IO: 0x%x [segment=0x%x]\n", 3566 phb->ioda.io_size, phb->ioda.io_segsize); 3567 3568 3569 phb->hose->ops = &pnv_pci_ops; 3570 phb->get_pe_state = pnv_ioda_get_pe_state; 3571 phb->freeze_pe = pnv_ioda_freeze_pe; 3572 phb->unfreeze_pe = pnv_ioda_unfreeze_pe; 3573 3574 /* Setup MSI support */ 3575 pnv_pci_init_ioda_msis(phb); 3576 3577 /* 3578 * We pass the PCI probe flag PCI_REASSIGN_ALL_RSRC here 3579 * to let the PCI core do resource assignment. It's supposed 3580 * that the PCI core will do correct I/O and MMIO alignment 3581 * for the P2P bridge bars so that each PCI bus (excluding 3582 * the child P2P bridges) can form individual PE. 3583 */ 3584 ppc_md.pcibios_fixup = pnv_pci_ioda_fixup; 3585 3586 if (phb->type == PNV_PHB_NPU) { 3587 hose->controller_ops = pnv_npu_ioda_controller_ops; 3588 } else { 3589 phb->dma_dev_setup = pnv_pci_ioda_dma_dev_setup; 3590 hose->controller_ops = pnv_pci_ioda_controller_ops; 3591 } 3592 3593 #ifdef CONFIG_PCI_IOV 3594 ppc_md.pcibios_fixup_sriov = pnv_pci_ioda_fixup_iov_resources; 3595 ppc_md.pcibios_iov_resource_alignment = pnv_pci_iov_resource_alignment; 3596 #endif 3597 3598 pci_add_flags(PCI_REASSIGN_ALL_RSRC); 3599 3600 /* Reset IODA tables to a clean state */ 3601 rc = opal_pci_reset(phb_id, OPAL_RESET_PCI_IODA_TABLE, OPAL_ASSERT_RESET); 3602 if (rc) 3603 pr_warning(" OPAL Error %ld performing IODA table reset !\n", rc); 3604 3605 /* If we're running in kdump kerenl, the previous kerenl never 3606 * shutdown PCI devices correctly. We already got IODA table 3607 * cleaned out. So we have to issue PHB reset to stop all PCI 3608 * transactions from previous kerenl. 3609 */ 3610 if (is_kdump_kernel()) { 3611 pr_info(" Issue PHB reset ...\n"); 3612 pnv_eeh_phb_reset(hose, EEH_RESET_FUNDAMENTAL); 3613 pnv_eeh_phb_reset(hose, EEH_RESET_DEACTIVATE); 3614 } 3615 3616 /* Remove M64 resource if we can't configure it successfully */ 3617 if (!phb->init_m64 || phb->init_m64(phb)) 3618 hose->mem_resources[1].flags = 0; 3619 } 3620 3621 void __init pnv_pci_init_ioda2_phb(struct device_node *np) 3622 { 3623 pnv_pci_init_ioda_phb(np, 0, PNV_PHB_IODA2); 3624 } 3625 3626 void __init pnv_pci_init_npu_phb(struct device_node *np) 3627 { 3628 pnv_pci_init_ioda_phb(np, 0, PNV_PHB_NPU); 3629 } 3630 3631 void __init pnv_pci_init_ioda_hub(struct device_node *np) 3632 { 3633 struct device_node *phbn; 3634 const __be64 *prop64; 3635 u64 hub_id; 3636 3637 pr_info("Probing IODA IO-Hub %s\n", np->full_name); 3638 3639 prop64 = of_get_property(np, "ibm,opal-hubid", NULL); 3640 if (!prop64) { 3641 pr_err(" Missing \"ibm,opal-hubid\" property !\n"); 3642 return; 3643 } 3644 hub_id = be64_to_cpup(prop64); 3645 pr_devel(" HUB-ID : 0x%016llx\n", hub_id); 3646 3647 /* Count child PHBs */ 3648 for_each_child_of_node(np, phbn) { 3649 /* Look for IODA1 PHBs */ 3650 if (of_device_is_compatible(phbn, "ibm,ioda-phb")) 3651 pnv_pci_init_ioda_phb(phbn, hub_id, PNV_PHB_IODA1); 3652 } 3653 } 3654