1 // SPDX-License-Identifier: GPL-2.0-or-later 2 /* 3 * Support PCI/PCIe on PowerNV platforms 4 * 5 * Copyright 2011 Benjamin Herrenschmidt, IBM Corp. 6 */ 7 8 #undef DEBUG 9 10 #include <linux/kernel.h> 11 #include <linux/pci.h> 12 #include <linux/crash_dump.h> 13 #include <linux/delay.h> 14 #include <linux/string.h> 15 #include <linux/init.h> 16 #include <linux/memblock.h> 17 #include <linux/irq.h> 18 #include <linux/io.h> 19 #include <linux/msi.h> 20 #include <linux/iommu.h> 21 #include <linux/rculist.h> 22 #include <linux/sizes.h> 23 24 #include <asm/sections.h> 25 #include <asm/io.h> 26 #include <asm/prom.h> 27 #include <asm/pci-bridge.h> 28 #include <asm/machdep.h> 29 #include <asm/msi_bitmap.h> 30 #include <asm/ppc-pci.h> 31 #include <asm/opal.h> 32 #include <asm/iommu.h> 33 #include <asm/tce.h> 34 #include <asm/xics.h> 35 #include <asm/debugfs.h> 36 #include <asm/firmware.h> 37 #include <asm/pnv-pci.h> 38 #include <asm/mmzone.h> 39 40 #include <misc/cxl-base.h> 41 42 #include "powernv.h" 43 #include "pci.h" 44 #include "../../../../drivers/pci/pci.h" 45 46 #define PNV_IODA1_M64_NUM 16 /* Number of M64 BARs */ 47 #define PNV_IODA1_M64_SEGS 8 /* Segments per M64 BAR */ 48 #define PNV_IODA1_DMA32_SEGSIZE 0x10000000 49 50 static const char * const pnv_phb_names[] = { "IODA1", "IODA2", "NPU_NVLINK", 51 "NPU_OCAPI" }; 52 53 static void pnv_pci_ioda2_set_bypass(struct pnv_ioda_pe *pe, bool enable); 54 55 void pe_level_printk(const struct pnv_ioda_pe *pe, const char *level, 56 const char *fmt, ...) 57 { 58 struct va_format vaf; 59 va_list args; 60 char pfix[32]; 61 62 va_start(args, fmt); 63 64 vaf.fmt = fmt; 65 vaf.va = &args; 66 67 if (pe->flags & PNV_IODA_PE_DEV) 68 strlcpy(pfix, dev_name(&pe->pdev->dev), sizeof(pfix)); 69 else if (pe->flags & (PNV_IODA_PE_BUS | PNV_IODA_PE_BUS_ALL)) 70 sprintf(pfix, "%04x:%02x ", 71 pci_domain_nr(pe->pbus), pe->pbus->number); 72 #ifdef CONFIG_PCI_IOV 73 else if (pe->flags & PNV_IODA_PE_VF) 74 sprintf(pfix, "%04x:%02x:%2x.%d", 75 pci_domain_nr(pe->parent_dev->bus), 76 (pe->rid & 0xff00) >> 8, 77 PCI_SLOT(pe->rid), PCI_FUNC(pe->rid)); 78 #endif /* CONFIG_PCI_IOV*/ 79 80 printk("%spci %s: [PE# %.2x] %pV", 81 level, pfix, pe->pe_number, &vaf); 82 83 va_end(args); 84 } 85 86 static bool pnv_iommu_bypass_disabled __read_mostly; 87 static bool pci_reset_phbs __read_mostly; 88 89 static int __init iommu_setup(char *str) 90 { 91 if (!str) 92 return -EINVAL; 93 94 while (*str) { 95 if (!strncmp(str, "nobypass", 8)) { 96 pnv_iommu_bypass_disabled = true; 97 pr_info("PowerNV: IOMMU bypass window disabled.\n"); 98 break; 99 } 100 str += strcspn(str, ","); 101 if (*str == ',') 102 str++; 103 } 104 105 return 0; 106 } 107 early_param("iommu", iommu_setup); 108 109 static int __init pci_reset_phbs_setup(char *str) 110 { 111 pci_reset_phbs = true; 112 return 0; 113 } 114 115 early_param("ppc_pci_reset_phbs", pci_reset_phbs_setup); 116 117 static inline bool pnv_pci_is_m64(struct pnv_phb *phb, struct resource *r) 118 { 119 /* 120 * WARNING: We cannot rely on the resource flags. The Linux PCI 121 * allocation code sometimes decides to put a 64-bit prefetchable 122 * BAR in the 32-bit window, so we have to compare the addresses. 123 * 124 * For simplicity we only test resource start. 125 */ 126 return (r->start >= phb->ioda.m64_base && 127 r->start < (phb->ioda.m64_base + phb->ioda.m64_size)); 128 } 129 130 static inline bool pnv_pci_is_m64_flags(unsigned long resource_flags) 131 { 132 unsigned long flags = (IORESOURCE_MEM_64 | IORESOURCE_PREFETCH); 133 134 return (resource_flags & flags) == flags; 135 } 136 137 static struct pnv_ioda_pe *pnv_ioda_init_pe(struct pnv_phb *phb, int pe_no) 138 { 139 s64 rc; 140 141 phb->ioda.pe_array[pe_no].phb = phb; 142 phb->ioda.pe_array[pe_no].pe_number = pe_no; 143 144 /* 145 * Clear the PE frozen state as it might be put into frozen state 146 * in the last PCI remove path. It's not harmful to do so when the 147 * PE is already in unfrozen state. 148 */ 149 rc = opal_pci_eeh_freeze_clear(phb->opal_id, pe_no, 150 OPAL_EEH_ACTION_CLEAR_FREEZE_ALL); 151 if (rc != OPAL_SUCCESS && rc != OPAL_UNSUPPORTED) 152 pr_warn("%s: Error %lld unfreezing PHB#%x-PE#%x\n", 153 __func__, rc, phb->hose->global_number, pe_no); 154 155 return &phb->ioda.pe_array[pe_no]; 156 } 157 158 static void pnv_ioda_reserve_pe(struct pnv_phb *phb, int pe_no) 159 { 160 if (!(pe_no >= 0 && pe_no < phb->ioda.total_pe_num)) { 161 pr_warn("%s: Invalid PE %x on PHB#%x\n", 162 __func__, pe_no, phb->hose->global_number); 163 return; 164 } 165 166 if (test_and_set_bit(pe_no, phb->ioda.pe_alloc)) 167 pr_debug("%s: PE %x was reserved on PHB#%x\n", 168 __func__, pe_no, phb->hose->global_number); 169 170 pnv_ioda_init_pe(phb, pe_no); 171 } 172 173 static struct pnv_ioda_pe *pnv_ioda_alloc_pe(struct pnv_phb *phb) 174 { 175 long pe; 176 177 for (pe = phb->ioda.total_pe_num - 1; pe >= 0; pe--) { 178 if (!test_and_set_bit(pe, phb->ioda.pe_alloc)) 179 return pnv_ioda_init_pe(phb, pe); 180 } 181 182 return NULL; 183 } 184 185 static void pnv_ioda_free_pe(struct pnv_ioda_pe *pe) 186 { 187 struct pnv_phb *phb = pe->phb; 188 unsigned int pe_num = pe->pe_number; 189 190 WARN_ON(pe->pdev); 191 WARN_ON(pe->npucomp); /* NPUs are not supposed to be freed */ 192 kfree(pe->npucomp); 193 memset(pe, 0, sizeof(struct pnv_ioda_pe)); 194 clear_bit(pe_num, phb->ioda.pe_alloc); 195 } 196 197 /* The default M64 BAR is shared by all PEs */ 198 static int pnv_ioda2_init_m64(struct pnv_phb *phb) 199 { 200 const char *desc; 201 struct resource *r; 202 s64 rc; 203 204 /* Configure the default M64 BAR */ 205 rc = opal_pci_set_phb_mem_window(phb->opal_id, 206 OPAL_M64_WINDOW_TYPE, 207 phb->ioda.m64_bar_idx, 208 phb->ioda.m64_base, 209 0, /* unused */ 210 phb->ioda.m64_size); 211 if (rc != OPAL_SUCCESS) { 212 desc = "configuring"; 213 goto fail; 214 } 215 216 /* Enable the default M64 BAR */ 217 rc = opal_pci_phb_mmio_enable(phb->opal_id, 218 OPAL_M64_WINDOW_TYPE, 219 phb->ioda.m64_bar_idx, 220 OPAL_ENABLE_M64_SPLIT); 221 if (rc != OPAL_SUCCESS) { 222 desc = "enabling"; 223 goto fail; 224 } 225 226 /* 227 * Exclude the segments for reserved and root bus PE, which 228 * are first or last two PEs. 229 */ 230 r = &phb->hose->mem_resources[1]; 231 if (phb->ioda.reserved_pe_idx == 0) 232 r->start += (2 * phb->ioda.m64_segsize); 233 else if (phb->ioda.reserved_pe_idx == (phb->ioda.total_pe_num - 1)) 234 r->end -= (2 * phb->ioda.m64_segsize); 235 else 236 pr_warn(" Cannot strip M64 segment for reserved PE#%x\n", 237 phb->ioda.reserved_pe_idx); 238 239 return 0; 240 241 fail: 242 pr_warn(" Failure %lld %s M64 BAR#%d\n", 243 rc, desc, phb->ioda.m64_bar_idx); 244 opal_pci_phb_mmio_enable(phb->opal_id, 245 OPAL_M64_WINDOW_TYPE, 246 phb->ioda.m64_bar_idx, 247 OPAL_DISABLE_M64); 248 return -EIO; 249 } 250 251 static void pnv_ioda_reserve_dev_m64_pe(struct pci_dev *pdev, 252 unsigned long *pe_bitmap) 253 { 254 struct pci_controller *hose = pci_bus_to_host(pdev->bus); 255 struct pnv_phb *phb = hose->private_data; 256 struct resource *r; 257 resource_size_t base, sgsz, start, end; 258 int segno, i; 259 260 base = phb->ioda.m64_base; 261 sgsz = phb->ioda.m64_segsize; 262 for (i = 0; i <= PCI_ROM_RESOURCE; i++) { 263 r = &pdev->resource[i]; 264 if (!r->parent || !pnv_pci_is_m64(phb, r)) 265 continue; 266 267 start = _ALIGN_DOWN(r->start - base, sgsz); 268 end = _ALIGN_UP(r->end - base, sgsz); 269 for (segno = start / sgsz; segno < end / sgsz; segno++) { 270 if (pe_bitmap) 271 set_bit(segno, pe_bitmap); 272 else 273 pnv_ioda_reserve_pe(phb, segno); 274 } 275 } 276 } 277 278 static int pnv_ioda1_init_m64(struct pnv_phb *phb) 279 { 280 struct resource *r; 281 int index; 282 283 /* 284 * There are 16 M64 BARs, each of which has 8 segments. So 285 * there are as many M64 segments as the maximum number of 286 * PEs, which is 128. 287 */ 288 for (index = 0; index < PNV_IODA1_M64_NUM; index++) { 289 unsigned long base, segsz = phb->ioda.m64_segsize; 290 int64_t rc; 291 292 base = phb->ioda.m64_base + 293 index * PNV_IODA1_M64_SEGS * segsz; 294 rc = opal_pci_set_phb_mem_window(phb->opal_id, 295 OPAL_M64_WINDOW_TYPE, index, base, 0, 296 PNV_IODA1_M64_SEGS * segsz); 297 if (rc != OPAL_SUCCESS) { 298 pr_warn(" Error %lld setting M64 PHB#%x-BAR#%d\n", 299 rc, phb->hose->global_number, index); 300 goto fail; 301 } 302 303 rc = opal_pci_phb_mmio_enable(phb->opal_id, 304 OPAL_M64_WINDOW_TYPE, index, 305 OPAL_ENABLE_M64_SPLIT); 306 if (rc != OPAL_SUCCESS) { 307 pr_warn(" Error %lld enabling M64 PHB#%x-BAR#%d\n", 308 rc, phb->hose->global_number, index); 309 goto fail; 310 } 311 } 312 313 /* 314 * Exclude the segments for reserved and root bus PE, which 315 * are first or last two PEs. 316 */ 317 r = &phb->hose->mem_resources[1]; 318 if (phb->ioda.reserved_pe_idx == 0) 319 r->start += (2 * phb->ioda.m64_segsize); 320 else if (phb->ioda.reserved_pe_idx == (phb->ioda.total_pe_num - 1)) 321 r->end -= (2 * phb->ioda.m64_segsize); 322 else 323 WARN(1, "Wrong reserved PE#%x on PHB#%x\n", 324 phb->ioda.reserved_pe_idx, phb->hose->global_number); 325 326 return 0; 327 328 fail: 329 for ( ; index >= 0; index--) 330 opal_pci_phb_mmio_enable(phb->opal_id, 331 OPAL_M64_WINDOW_TYPE, index, OPAL_DISABLE_M64); 332 333 return -EIO; 334 } 335 336 static void pnv_ioda_reserve_m64_pe(struct pci_bus *bus, 337 unsigned long *pe_bitmap, 338 bool all) 339 { 340 struct pci_dev *pdev; 341 342 list_for_each_entry(pdev, &bus->devices, bus_list) { 343 pnv_ioda_reserve_dev_m64_pe(pdev, pe_bitmap); 344 345 if (all && pdev->subordinate) 346 pnv_ioda_reserve_m64_pe(pdev->subordinate, 347 pe_bitmap, all); 348 } 349 } 350 351 static struct pnv_ioda_pe *pnv_ioda_pick_m64_pe(struct pci_bus *bus, bool all) 352 { 353 struct pci_controller *hose = pci_bus_to_host(bus); 354 struct pnv_phb *phb = hose->private_data; 355 struct pnv_ioda_pe *master_pe, *pe; 356 unsigned long size, *pe_alloc; 357 int i; 358 359 /* Root bus shouldn't use M64 */ 360 if (pci_is_root_bus(bus)) 361 return NULL; 362 363 /* Allocate bitmap */ 364 size = _ALIGN_UP(phb->ioda.total_pe_num / 8, sizeof(unsigned long)); 365 pe_alloc = kzalloc(size, GFP_KERNEL); 366 if (!pe_alloc) { 367 pr_warn("%s: Out of memory !\n", 368 __func__); 369 return NULL; 370 } 371 372 /* Figure out reserved PE numbers by the PE */ 373 pnv_ioda_reserve_m64_pe(bus, pe_alloc, all); 374 375 /* 376 * the current bus might not own M64 window and that's all 377 * contributed by its child buses. For the case, we needn't 378 * pick M64 dependent PE#. 379 */ 380 if (bitmap_empty(pe_alloc, phb->ioda.total_pe_num)) { 381 kfree(pe_alloc); 382 return NULL; 383 } 384 385 /* 386 * Figure out the master PE and put all slave PEs to master 387 * PE's list to form compound PE. 388 */ 389 master_pe = NULL; 390 i = -1; 391 while ((i = find_next_bit(pe_alloc, phb->ioda.total_pe_num, i + 1)) < 392 phb->ioda.total_pe_num) { 393 pe = &phb->ioda.pe_array[i]; 394 395 phb->ioda.m64_segmap[pe->pe_number] = pe->pe_number; 396 if (!master_pe) { 397 pe->flags |= PNV_IODA_PE_MASTER; 398 INIT_LIST_HEAD(&pe->slaves); 399 master_pe = pe; 400 } else { 401 pe->flags |= PNV_IODA_PE_SLAVE; 402 pe->master = master_pe; 403 list_add_tail(&pe->list, &master_pe->slaves); 404 } 405 406 /* 407 * P7IOC supports M64DT, which helps mapping M64 segment 408 * to one particular PE#. However, PHB3 has fixed mapping 409 * between M64 segment and PE#. In order to have same logic 410 * for P7IOC and PHB3, we enforce fixed mapping between M64 411 * segment and PE# on P7IOC. 412 */ 413 if (phb->type == PNV_PHB_IODA1) { 414 int64_t rc; 415 416 rc = opal_pci_map_pe_mmio_window(phb->opal_id, 417 pe->pe_number, OPAL_M64_WINDOW_TYPE, 418 pe->pe_number / PNV_IODA1_M64_SEGS, 419 pe->pe_number % PNV_IODA1_M64_SEGS); 420 if (rc != OPAL_SUCCESS) 421 pr_warn("%s: Error %lld mapping M64 for PHB#%x-PE#%x\n", 422 __func__, rc, phb->hose->global_number, 423 pe->pe_number); 424 } 425 } 426 427 kfree(pe_alloc); 428 return master_pe; 429 } 430 431 static void __init pnv_ioda_parse_m64_window(struct pnv_phb *phb) 432 { 433 struct pci_controller *hose = phb->hose; 434 struct device_node *dn = hose->dn; 435 struct resource *res; 436 u32 m64_range[2], i; 437 const __be32 *r; 438 u64 pci_addr; 439 440 if (phb->type != PNV_PHB_IODA1 && phb->type != PNV_PHB_IODA2) { 441 pr_info(" Not support M64 window\n"); 442 return; 443 } 444 445 if (!firmware_has_feature(FW_FEATURE_OPAL)) { 446 pr_info(" Firmware too old to support M64 window\n"); 447 return; 448 } 449 450 r = of_get_property(dn, "ibm,opal-m64-window", NULL); 451 if (!r) { 452 pr_info(" No <ibm,opal-m64-window> on %pOF\n", 453 dn); 454 return; 455 } 456 457 /* 458 * Find the available M64 BAR range and pickup the last one for 459 * covering the whole 64-bits space. We support only one range. 460 */ 461 if (of_property_read_u32_array(dn, "ibm,opal-available-m64-ranges", 462 m64_range, 2)) { 463 /* In absence of the property, assume 0..15 */ 464 m64_range[0] = 0; 465 m64_range[1] = 16; 466 } 467 /* We only support 64 bits in our allocator */ 468 if (m64_range[1] > 63) { 469 pr_warn("%s: Limiting M64 range to 63 (from %d) on PHB#%x\n", 470 __func__, m64_range[1], phb->hose->global_number); 471 m64_range[1] = 63; 472 } 473 /* Empty range, no m64 */ 474 if (m64_range[1] <= m64_range[0]) { 475 pr_warn("%s: M64 empty, disabling M64 usage on PHB#%x\n", 476 __func__, phb->hose->global_number); 477 return; 478 } 479 480 /* Configure M64 informations */ 481 res = &hose->mem_resources[1]; 482 res->name = dn->full_name; 483 res->start = of_translate_address(dn, r + 2); 484 res->end = res->start + of_read_number(r + 4, 2) - 1; 485 res->flags = (IORESOURCE_MEM | IORESOURCE_MEM_64 | IORESOURCE_PREFETCH); 486 pci_addr = of_read_number(r, 2); 487 hose->mem_offset[1] = res->start - pci_addr; 488 489 phb->ioda.m64_size = resource_size(res); 490 phb->ioda.m64_segsize = phb->ioda.m64_size / phb->ioda.total_pe_num; 491 phb->ioda.m64_base = pci_addr; 492 493 /* This lines up nicely with the display from processing OF ranges */ 494 pr_info(" MEM 0x%016llx..0x%016llx -> 0x%016llx (M64 #%d..%d)\n", 495 res->start, res->end, pci_addr, m64_range[0], 496 m64_range[0] + m64_range[1] - 1); 497 498 /* Mark all M64 used up by default */ 499 phb->ioda.m64_bar_alloc = (unsigned long)-1; 500 501 /* Use last M64 BAR to cover M64 window */ 502 m64_range[1]--; 503 phb->ioda.m64_bar_idx = m64_range[0] + m64_range[1]; 504 505 pr_info(" Using M64 #%d as default window\n", phb->ioda.m64_bar_idx); 506 507 /* Mark remaining ones free */ 508 for (i = m64_range[0]; i < m64_range[1]; i++) 509 clear_bit(i, &phb->ioda.m64_bar_alloc); 510 511 /* 512 * Setup init functions for M64 based on IODA version, IODA3 uses 513 * the IODA2 code. 514 */ 515 if (phb->type == PNV_PHB_IODA1) 516 phb->init_m64 = pnv_ioda1_init_m64; 517 else 518 phb->init_m64 = pnv_ioda2_init_m64; 519 } 520 521 static void pnv_ioda_freeze_pe(struct pnv_phb *phb, int pe_no) 522 { 523 struct pnv_ioda_pe *pe = &phb->ioda.pe_array[pe_no]; 524 struct pnv_ioda_pe *slave; 525 s64 rc; 526 527 /* Fetch master PE */ 528 if (pe->flags & PNV_IODA_PE_SLAVE) { 529 pe = pe->master; 530 if (WARN_ON(!pe || !(pe->flags & PNV_IODA_PE_MASTER))) 531 return; 532 533 pe_no = pe->pe_number; 534 } 535 536 /* Freeze master PE */ 537 rc = opal_pci_eeh_freeze_set(phb->opal_id, 538 pe_no, 539 OPAL_EEH_ACTION_SET_FREEZE_ALL); 540 if (rc != OPAL_SUCCESS) { 541 pr_warn("%s: Failure %lld freezing PHB#%x-PE#%x\n", 542 __func__, rc, phb->hose->global_number, pe_no); 543 return; 544 } 545 546 /* Freeze slave PEs */ 547 if (!(pe->flags & PNV_IODA_PE_MASTER)) 548 return; 549 550 list_for_each_entry(slave, &pe->slaves, list) { 551 rc = opal_pci_eeh_freeze_set(phb->opal_id, 552 slave->pe_number, 553 OPAL_EEH_ACTION_SET_FREEZE_ALL); 554 if (rc != OPAL_SUCCESS) 555 pr_warn("%s: Failure %lld freezing PHB#%x-PE#%x\n", 556 __func__, rc, phb->hose->global_number, 557 slave->pe_number); 558 } 559 } 560 561 static int pnv_ioda_unfreeze_pe(struct pnv_phb *phb, int pe_no, int opt) 562 { 563 struct pnv_ioda_pe *pe, *slave; 564 s64 rc; 565 566 /* Find master PE */ 567 pe = &phb->ioda.pe_array[pe_no]; 568 if (pe->flags & PNV_IODA_PE_SLAVE) { 569 pe = pe->master; 570 WARN_ON(!pe || !(pe->flags & PNV_IODA_PE_MASTER)); 571 pe_no = pe->pe_number; 572 } 573 574 /* Clear frozen state for master PE */ 575 rc = opal_pci_eeh_freeze_clear(phb->opal_id, pe_no, opt); 576 if (rc != OPAL_SUCCESS) { 577 pr_warn("%s: Failure %lld clear %d on PHB#%x-PE#%x\n", 578 __func__, rc, opt, phb->hose->global_number, pe_no); 579 return -EIO; 580 } 581 582 if (!(pe->flags & PNV_IODA_PE_MASTER)) 583 return 0; 584 585 /* Clear frozen state for slave PEs */ 586 list_for_each_entry(slave, &pe->slaves, list) { 587 rc = opal_pci_eeh_freeze_clear(phb->opal_id, 588 slave->pe_number, 589 opt); 590 if (rc != OPAL_SUCCESS) { 591 pr_warn("%s: Failure %lld clear %d on PHB#%x-PE#%x\n", 592 __func__, rc, opt, phb->hose->global_number, 593 slave->pe_number); 594 return -EIO; 595 } 596 } 597 598 return 0; 599 } 600 601 static int pnv_ioda_get_pe_state(struct pnv_phb *phb, int pe_no) 602 { 603 struct pnv_ioda_pe *slave, *pe; 604 u8 fstate = 0, state; 605 __be16 pcierr = 0; 606 s64 rc; 607 608 /* Sanity check on PE number */ 609 if (pe_no < 0 || pe_no >= phb->ioda.total_pe_num) 610 return OPAL_EEH_STOPPED_PERM_UNAVAIL; 611 612 /* 613 * Fetch the master PE and the PE instance might be 614 * not initialized yet. 615 */ 616 pe = &phb->ioda.pe_array[pe_no]; 617 if (pe->flags & PNV_IODA_PE_SLAVE) { 618 pe = pe->master; 619 WARN_ON(!pe || !(pe->flags & PNV_IODA_PE_MASTER)); 620 pe_no = pe->pe_number; 621 } 622 623 /* Check the master PE */ 624 rc = opal_pci_eeh_freeze_status(phb->opal_id, pe_no, 625 &state, &pcierr, NULL); 626 if (rc != OPAL_SUCCESS) { 627 pr_warn("%s: Failure %lld getting " 628 "PHB#%x-PE#%x state\n", 629 __func__, rc, 630 phb->hose->global_number, pe_no); 631 return OPAL_EEH_STOPPED_TEMP_UNAVAIL; 632 } 633 634 /* Check the slave PE */ 635 if (!(pe->flags & PNV_IODA_PE_MASTER)) 636 return state; 637 638 list_for_each_entry(slave, &pe->slaves, list) { 639 rc = opal_pci_eeh_freeze_status(phb->opal_id, 640 slave->pe_number, 641 &fstate, 642 &pcierr, 643 NULL); 644 if (rc != OPAL_SUCCESS) { 645 pr_warn("%s: Failure %lld getting " 646 "PHB#%x-PE#%x state\n", 647 __func__, rc, 648 phb->hose->global_number, slave->pe_number); 649 return OPAL_EEH_STOPPED_TEMP_UNAVAIL; 650 } 651 652 /* 653 * Override the result based on the ascending 654 * priority. 655 */ 656 if (fstate > state) 657 state = fstate; 658 } 659 660 return state; 661 } 662 663 struct pnv_ioda_pe *pnv_ioda_get_pe(struct pci_dev *dev) 664 { 665 struct pci_controller *hose = pci_bus_to_host(dev->bus); 666 struct pnv_phb *phb = hose->private_data; 667 struct pci_dn *pdn = pci_get_pdn(dev); 668 669 if (!pdn) 670 return NULL; 671 if (pdn->pe_number == IODA_INVALID_PE) 672 return NULL; 673 return &phb->ioda.pe_array[pdn->pe_number]; 674 } 675 676 static int pnv_ioda_set_one_peltv(struct pnv_phb *phb, 677 struct pnv_ioda_pe *parent, 678 struct pnv_ioda_pe *child, 679 bool is_add) 680 { 681 const char *desc = is_add ? "adding" : "removing"; 682 uint8_t op = is_add ? OPAL_ADD_PE_TO_DOMAIN : 683 OPAL_REMOVE_PE_FROM_DOMAIN; 684 struct pnv_ioda_pe *slave; 685 long rc; 686 687 /* Parent PE affects child PE */ 688 rc = opal_pci_set_peltv(phb->opal_id, parent->pe_number, 689 child->pe_number, op); 690 if (rc != OPAL_SUCCESS) { 691 pe_warn(child, "OPAL error %ld %s to parent PELTV\n", 692 rc, desc); 693 return -ENXIO; 694 } 695 696 if (!(child->flags & PNV_IODA_PE_MASTER)) 697 return 0; 698 699 /* Compound case: parent PE affects slave PEs */ 700 list_for_each_entry(slave, &child->slaves, list) { 701 rc = opal_pci_set_peltv(phb->opal_id, parent->pe_number, 702 slave->pe_number, op); 703 if (rc != OPAL_SUCCESS) { 704 pe_warn(slave, "OPAL error %ld %s to parent PELTV\n", 705 rc, desc); 706 return -ENXIO; 707 } 708 } 709 710 return 0; 711 } 712 713 static int pnv_ioda_set_peltv(struct pnv_phb *phb, 714 struct pnv_ioda_pe *pe, 715 bool is_add) 716 { 717 struct pnv_ioda_pe *slave; 718 struct pci_dev *pdev = NULL; 719 int ret; 720 721 /* 722 * Clear PE frozen state. If it's master PE, we need 723 * clear slave PE frozen state as well. 724 */ 725 if (is_add) { 726 opal_pci_eeh_freeze_clear(phb->opal_id, pe->pe_number, 727 OPAL_EEH_ACTION_CLEAR_FREEZE_ALL); 728 if (pe->flags & PNV_IODA_PE_MASTER) { 729 list_for_each_entry(slave, &pe->slaves, list) 730 opal_pci_eeh_freeze_clear(phb->opal_id, 731 slave->pe_number, 732 OPAL_EEH_ACTION_CLEAR_FREEZE_ALL); 733 } 734 } 735 736 /* 737 * Associate PE in PELT. We need add the PE into the 738 * corresponding PELT-V as well. Otherwise, the error 739 * originated from the PE might contribute to other 740 * PEs. 741 */ 742 ret = pnv_ioda_set_one_peltv(phb, pe, pe, is_add); 743 if (ret) 744 return ret; 745 746 /* For compound PEs, any one affects all of them */ 747 if (pe->flags & PNV_IODA_PE_MASTER) { 748 list_for_each_entry(slave, &pe->slaves, list) { 749 ret = pnv_ioda_set_one_peltv(phb, slave, pe, is_add); 750 if (ret) 751 return ret; 752 } 753 } 754 755 if (pe->flags & (PNV_IODA_PE_BUS_ALL | PNV_IODA_PE_BUS)) 756 pdev = pe->pbus->self; 757 else if (pe->flags & PNV_IODA_PE_DEV) 758 pdev = pe->pdev->bus->self; 759 #ifdef CONFIG_PCI_IOV 760 else if (pe->flags & PNV_IODA_PE_VF) 761 pdev = pe->parent_dev; 762 #endif /* CONFIG_PCI_IOV */ 763 while (pdev) { 764 struct pci_dn *pdn = pci_get_pdn(pdev); 765 struct pnv_ioda_pe *parent; 766 767 if (pdn && pdn->pe_number != IODA_INVALID_PE) { 768 parent = &phb->ioda.pe_array[pdn->pe_number]; 769 ret = pnv_ioda_set_one_peltv(phb, parent, pe, is_add); 770 if (ret) 771 return ret; 772 } 773 774 pdev = pdev->bus->self; 775 } 776 777 return 0; 778 } 779 780 static int pnv_ioda_deconfigure_pe(struct pnv_phb *phb, struct pnv_ioda_pe *pe) 781 { 782 struct pci_dev *parent; 783 uint8_t bcomp, dcomp, fcomp; 784 int64_t rc; 785 long rid_end, rid; 786 787 /* Currently, we just deconfigure VF PE. Bus PE will always there.*/ 788 if (pe->pbus) { 789 int count; 790 791 dcomp = OPAL_IGNORE_RID_DEVICE_NUMBER; 792 fcomp = OPAL_IGNORE_RID_FUNCTION_NUMBER; 793 parent = pe->pbus->self; 794 if (pe->flags & PNV_IODA_PE_BUS_ALL) 795 count = resource_size(&pe->pbus->busn_res); 796 else 797 count = 1; 798 799 switch(count) { 800 case 1: bcomp = OpalPciBusAll; break; 801 case 2: bcomp = OpalPciBus7Bits; break; 802 case 4: bcomp = OpalPciBus6Bits; break; 803 case 8: bcomp = OpalPciBus5Bits; break; 804 case 16: bcomp = OpalPciBus4Bits; break; 805 case 32: bcomp = OpalPciBus3Bits; break; 806 default: 807 dev_err(&pe->pbus->dev, "Number of subordinate buses %d unsupported\n", 808 count); 809 /* Do an exact match only */ 810 bcomp = OpalPciBusAll; 811 } 812 rid_end = pe->rid + (count << 8); 813 } else { 814 #ifdef CONFIG_PCI_IOV 815 if (pe->flags & PNV_IODA_PE_VF) 816 parent = pe->parent_dev; 817 else 818 #endif 819 parent = pe->pdev->bus->self; 820 bcomp = OpalPciBusAll; 821 dcomp = OPAL_COMPARE_RID_DEVICE_NUMBER; 822 fcomp = OPAL_COMPARE_RID_FUNCTION_NUMBER; 823 rid_end = pe->rid + 1; 824 } 825 826 /* Clear the reverse map */ 827 for (rid = pe->rid; rid < rid_end; rid++) 828 phb->ioda.pe_rmap[rid] = IODA_INVALID_PE; 829 830 /* Release from all parents PELT-V */ 831 while (parent) { 832 struct pci_dn *pdn = pci_get_pdn(parent); 833 if (pdn && pdn->pe_number != IODA_INVALID_PE) { 834 rc = opal_pci_set_peltv(phb->opal_id, pdn->pe_number, 835 pe->pe_number, OPAL_REMOVE_PE_FROM_DOMAIN); 836 /* XXX What to do in case of error ? */ 837 } 838 parent = parent->bus->self; 839 } 840 841 opal_pci_eeh_freeze_clear(phb->opal_id, pe->pe_number, 842 OPAL_EEH_ACTION_CLEAR_FREEZE_ALL); 843 844 /* Disassociate PE in PELT */ 845 rc = opal_pci_set_peltv(phb->opal_id, pe->pe_number, 846 pe->pe_number, OPAL_REMOVE_PE_FROM_DOMAIN); 847 if (rc) 848 pe_warn(pe, "OPAL error %lld remove self from PELTV\n", rc); 849 rc = opal_pci_set_pe(phb->opal_id, pe->pe_number, pe->rid, 850 bcomp, dcomp, fcomp, OPAL_UNMAP_PE); 851 if (rc) 852 pe_err(pe, "OPAL error %lld trying to setup PELT table\n", rc); 853 854 pe->pbus = NULL; 855 pe->pdev = NULL; 856 #ifdef CONFIG_PCI_IOV 857 pe->parent_dev = NULL; 858 #endif 859 860 return 0; 861 } 862 863 static int pnv_ioda_configure_pe(struct pnv_phb *phb, struct pnv_ioda_pe *pe) 864 { 865 struct pci_dev *parent; 866 uint8_t bcomp, dcomp, fcomp; 867 long rc, rid_end, rid; 868 869 /* Bus validation ? */ 870 if (pe->pbus) { 871 int count; 872 873 dcomp = OPAL_IGNORE_RID_DEVICE_NUMBER; 874 fcomp = OPAL_IGNORE_RID_FUNCTION_NUMBER; 875 parent = pe->pbus->self; 876 if (pe->flags & PNV_IODA_PE_BUS_ALL) 877 count = resource_size(&pe->pbus->busn_res); 878 else 879 count = 1; 880 881 switch(count) { 882 case 1: bcomp = OpalPciBusAll; break; 883 case 2: bcomp = OpalPciBus7Bits; break; 884 case 4: bcomp = OpalPciBus6Bits; break; 885 case 8: bcomp = OpalPciBus5Bits; break; 886 case 16: bcomp = OpalPciBus4Bits; break; 887 case 32: bcomp = OpalPciBus3Bits; break; 888 default: 889 dev_err(&pe->pbus->dev, "Number of subordinate buses %d unsupported\n", 890 count); 891 /* Do an exact match only */ 892 bcomp = OpalPciBusAll; 893 } 894 rid_end = pe->rid + (count << 8); 895 } else { 896 #ifdef CONFIG_PCI_IOV 897 if (pe->flags & PNV_IODA_PE_VF) 898 parent = pe->parent_dev; 899 else 900 #endif /* CONFIG_PCI_IOV */ 901 parent = pe->pdev->bus->self; 902 bcomp = OpalPciBusAll; 903 dcomp = OPAL_COMPARE_RID_DEVICE_NUMBER; 904 fcomp = OPAL_COMPARE_RID_FUNCTION_NUMBER; 905 rid_end = pe->rid + 1; 906 } 907 908 /* 909 * Associate PE in PELT. We need add the PE into the 910 * corresponding PELT-V as well. Otherwise, the error 911 * originated from the PE might contribute to other 912 * PEs. 913 */ 914 rc = opal_pci_set_pe(phb->opal_id, pe->pe_number, pe->rid, 915 bcomp, dcomp, fcomp, OPAL_MAP_PE); 916 if (rc) { 917 pe_err(pe, "OPAL error %ld trying to setup PELT table\n", rc); 918 return -ENXIO; 919 } 920 921 /* 922 * Configure PELTV. NPUs don't have a PELTV table so skip 923 * configuration on them. 924 */ 925 if (phb->type != PNV_PHB_NPU_NVLINK && phb->type != PNV_PHB_NPU_OCAPI) 926 pnv_ioda_set_peltv(phb, pe, true); 927 928 /* Setup reverse map */ 929 for (rid = pe->rid; rid < rid_end; rid++) 930 phb->ioda.pe_rmap[rid] = pe->pe_number; 931 932 /* Setup one MVTs on IODA1 */ 933 if (phb->type != PNV_PHB_IODA1) { 934 pe->mve_number = 0; 935 goto out; 936 } 937 938 pe->mve_number = pe->pe_number; 939 rc = opal_pci_set_mve(phb->opal_id, pe->mve_number, pe->pe_number); 940 if (rc != OPAL_SUCCESS) { 941 pe_err(pe, "OPAL error %ld setting up MVE %x\n", 942 rc, pe->mve_number); 943 pe->mve_number = -1; 944 } else { 945 rc = opal_pci_set_mve_enable(phb->opal_id, 946 pe->mve_number, OPAL_ENABLE_MVE); 947 if (rc) { 948 pe_err(pe, "OPAL error %ld enabling MVE %x\n", 949 rc, pe->mve_number); 950 pe->mve_number = -1; 951 } 952 } 953 954 out: 955 return 0; 956 } 957 958 #ifdef CONFIG_PCI_IOV 959 static int pnv_pci_vf_resource_shift(struct pci_dev *dev, int offset) 960 { 961 struct pci_dn *pdn = pci_get_pdn(dev); 962 int i; 963 struct resource *res, res2; 964 resource_size_t size; 965 u16 num_vfs; 966 967 if (!dev->is_physfn) 968 return -EINVAL; 969 970 /* 971 * "offset" is in VFs. The M64 windows are sized so that when they 972 * are segmented, each segment is the same size as the IOV BAR. 973 * Each segment is in a separate PE, and the high order bits of the 974 * address are the PE number. Therefore, each VF's BAR is in a 975 * separate PE, and changing the IOV BAR start address changes the 976 * range of PEs the VFs are in. 977 */ 978 num_vfs = pdn->num_vfs; 979 for (i = 0; i < PCI_SRIOV_NUM_BARS; i++) { 980 res = &dev->resource[i + PCI_IOV_RESOURCES]; 981 if (!res->flags || !res->parent) 982 continue; 983 984 /* 985 * The actual IOV BAR range is determined by the start address 986 * and the actual size for num_vfs VFs BAR. This check is to 987 * make sure that after shifting, the range will not overlap 988 * with another device. 989 */ 990 size = pci_iov_resource_size(dev, i + PCI_IOV_RESOURCES); 991 res2.flags = res->flags; 992 res2.start = res->start + (size * offset); 993 res2.end = res2.start + (size * num_vfs) - 1; 994 995 if (res2.end > res->end) { 996 dev_err(&dev->dev, "VF BAR%d: %pR would extend past %pR (trying to enable %d VFs shifted by %d)\n", 997 i, &res2, res, num_vfs, offset); 998 return -EBUSY; 999 } 1000 } 1001 1002 /* 1003 * Since M64 BAR shares segments among all possible 256 PEs, 1004 * we have to shift the beginning of PF IOV BAR to make it start from 1005 * the segment which belongs to the PE number assigned to the first VF. 1006 * This creates a "hole" in the /proc/iomem which could be used for 1007 * allocating other resources so we reserve this area below and 1008 * release when IOV is released. 1009 */ 1010 for (i = 0; i < PCI_SRIOV_NUM_BARS; i++) { 1011 res = &dev->resource[i + PCI_IOV_RESOURCES]; 1012 if (!res->flags || !res->parent) 1013 continue; 1014 1015 size = pci_iov_resource_size(dev, i + PCI_IOV_RESOURCES); 1016 res2 = *res; 1017 res->start += size * offset; 1018 1019 dev_info(&dev->dev, "VF BAR%d: %pR shifted to %pR (%sabling %d VFs shifted by %d)\n", 1020 i, &res2, res, (offset > 0) ? "En" : "Dis", 1021 num_vfs, offset); 1022 1023 if (offset < 0) { 1024 devm_release_resource(&dev->dev, &pdn->holes[i]); 1025 memset(&pdn->holes[i], 0, sizeof(pdn->holes[i])); 1026 } 1027 1028 pci_update_resource(dev, i + PCI_IOV_RESOURCES); 1029 1030 if (offset > 0) { 1031 pdn->holes[i].start = res2.start; 1032 pdn->holes[i].end = res2.start + size * offset - 1; 1033 pdn->holes[i].flags = IORESOURCE_BUS; 1034 pdn->holes[i].name = "pnv_iov_reserved"; 1035 devm_request_resource(&dev->dev, res->parent, 1036 &pdn->holes[i]); 1037 } 1038 } 1039 return 0; 1040 } 1041 #endif /* CONFIG_PCI_IOV */ 1042 1043 static struct pnv_ioda_pe *pnv_ioda_setup_dev_PE(struct pci_dev *dev) 1044 { 1045 struct pci_controller *hose = pci_bus_to_host(dev->bus); 1046 struct pnv_phb *phb = hose->private_data; 1047 struct pci_dn *pdn = pci_get_pdn(dev); 1048 struct pnv_ioda_pe *pe; 1049 1050 if (!pdn) { 1051 pr_err("%s: Device tree node not associated properly\n", 1052 pci_name(dev)); 1053 return NULL; 1054 } 1055 if (pdn->pe_number != IODA_INVALID_PE) 1056 return NULL; 1057 1058 pe = pnv_ioda_alloc_pe(phb); 1059 if (!pe) { 1060 pr_warn("%s: Not enough PE# available, disabling device\n", 1061 pci_name(dev)); 1062 return NULL; 1063 } 1064 1065 /* NOTE: We don't get a reference for the pointer in the PE 1066 * data structure, both the device and PE structures should be 1067 * destroyed at the same time. However, removing nvlink 1068 * devices will need some work. 1069 * 1070 * At some point we want to remove the PDN completely anyways 1071 */ 1072 pdn->pe_number = pe->pe_number; 1073 pe->flags = PNV_IODA_PE_DEV; 1074 pe->pdev = dev; 1075 pe->pbus = NULL; 1076 pe->mve_number = -1; 1077 pe->rid = dev->bus->number << 8 | pdn->devfn; 1078 1079 pe_info(pe, "Associated device to PE\n"); 1080 1081 if (pnv_ioda_configure_pe(phb, pe)) { 1082 /* XXX What do we do here ? */ 1083 pnv_ioda_free_pe(pe); 1084 pdn->pe_number = IODA_INVALID_PE; 1085 pe->pdev = NULL; 1086 return NULL; 1087 } 1088 1089 /* Put PE to the list */ 1090 mutex_lock(&phb->ioda.pe_list_mutex); 1091 list_add_tail(&pe->list, &phb->ioda.pe_list); 1092 mutex_unlock(&phb->ioda.pe_list_mutex); 1093 return pe; 1094 } 1095 1096 static void pnv_ioda_setup_same_PE(struct pci_bus *bus, struct pnv_ioda_pe *pe) 1097 { 1098 struct pci_dev *dev; 1099 1100 list_for_each_entry(dev, &bus->devices, bus_list) { 1101 struct pci_dn *pdn = pci_get_pdn(dev); 1102 1103 if (pdn == NULL) { 1104 pr_warn("%s: No device node associated with device !\n", 1105 pci_name(dev)); 1106 continue; 1107 } 1108 1109 /* 1110 * In partial hotplug case, the PCI device might be still 1111 * associated with the PE and needn't attach it to the PE 1112 * again. 1113 */ 1114 if (pdn->pe_number != IODA_INVALID_PE) 1115 continue; 1116 1117 pe->device_count++; 1118 pdn->pe_number = pe->pe_number; 1119 if ((pe->flags & PNV_IODA_PE_BUS_ALL) && dev->subordinate) 1120 pnv_ioda_setup_same_PE(dev->subordinate, pe); 1121 } 1122 } 1123 1124 /* 1125 * There're 2 types of PCI bus sensitive PEs: One that is compromised of 1126 * single PCI bus. Another one that contains the primary PCI bus and its 1127 * subordinate PCI devices and buses. The second type of PE is normally 1128 * orgiriated by PCIe-to-PCI bridge or PLX switch downstream ports. 1129 */ 1130 static struct pnv_ioda_pe *pnv_ioda_setup_bus_PE(struct pci_bus *bus, bool all) 1131 { 1132 struct pci_controller *hose = pci_bus_to_host(bus); 1133 struct pnv_phb *phb = hose->private_data; 1134 struct pnv_ioda_pe *pe = NULL; 1135 unsigned int pe_num; 1136 1137 /* 1138 * In partial hotplug case, the PE instance might be still alive. 1139 * We should reuse it instead of allocating a new one. 1140 */ 1141 pe_num = phb->ioda.pe_rmap[bus->number << 8]; 1142 if (pe_num != IODA_INVALID_PE) { 1143 pe = &phb->ioda.pe_array[pe_num]; 1144 pnv_ioda_setup_same_PE(bus, pe); 1145 return NULL; 1146 } 1147 1148 /* PE number for root bus should have been reserved */ 1149 if (pci_is_root_bus(bus) && 1150 phb->ioda.root_pe_idx != IODA_INVALID_PE) 1151 pe = &phb->ioda.pe_array[phb->ioda.root_pe_idx]; 1152 1153 /* Check if PE is determined by M64 */ 1154 if (!pe) 1155 pe = pnv_ioda_pick_m64_pe(bus, all); 1156 1157 /* The PE number isn't pinned by M64 */ 1158 if (!pe) 1159 pe = pnv_ioda_alloc_pe(phb); 1160 1161 if (!pe) { 1162 pr_warn("%s: Not enough PE# available for PCI bus %04x:%02x\n", 1163 __func__, pci_domain_nr(bus), bus->number); 1164 return NULL; 1165 } 1166 1167 pe->flags |= (all ? PNV_IODA_PE_BUS_ALL : PNV_IODA_PE_BUS); 1168 pe->pbus = bus; 1169 pe->pdev = NULL; 1170 pe->mve_number = -1; 1171 pe->rid = bus->busn_res.start << 8; 1172 1173 if (all) 1174 pe_info(pe, "Secondary bus %pad..%pad associated with PE#%x\n", 1175 &bus->busn_res.start, &bus->busn_res.end, 1176 pe->pe_number); 1177 else 1178 pe_info(pe, "Secondary bus %pad associated with PE#%x\n", 1179 &bus->busn_res.start, pe->pe_number); 1180 1181 if (pnv_ioda_configure_pe(phb, pe)) { 1182 /* XXX What do we do here ? */ 1183 pnv_ioda_free_pe(pe); 1184 pe->pbus = NULL; 1185 return NULL; 1186 } 1187 1188 /* Associate it with all child devices */ 1189 pnv_ioda_setup_same_PE(bus, pe); 1190 1191 /* Put PE to the list */ 1192 list_add_tail(&pe->list, &phb->ioda.pe_list); 1193 1194 return pe; 1195 } 1196 1197 static struct pnv_ioda_pe *pnv_ioda_setup_npu_PE(struct pci_dev *npu_pdev) 1198 { 1199 int pe_num, found_pe = false, rc; 1200 long rid; 1201 struct pnv_ioda_pe *pe; 1202 struct pci_dev *gpu_pdev; 1203 struct pci_dn *npu_pdn; 1204 struct pci_controller *hose = pci_bus_to_host(npu_pdev->bus); 1205 struct pnv_phb *phb = hose->private_data; 1206 1207 /* 1208 * Intentionally leak a reference on the npu device (for 1209 * nvlink only; this is not an opencapi path) to make sure it 1210 * never goes away, as it's been the case all along and some 1211 * work is needed otherwise. 1212 */ 1213 pci_dev_get(npu_pdev); 1214 1215 /* 1216 * Due to a hardware errata PE#0 on the NPU is reserved for 1217 * error handling. This means we only have three PEs remaining 1218 * which need to be assigned to four links, implying some 1219 * links must share PEs. 1220 * 1221 * To achieve this we assign PEs such that NPUs linking the 1222 * same GPU get assigned the same PE. 1223 */ 1224 gpu_pdev = pnv_pci_get_gpu_dev(npu_pdev); 1225 for (pe_num = 0; pe_num < phb->ioda.total_pe_num; pe_num++) { 1226 pe = &phb->ioda.pe_array[pe_num]; 1227 if (!pe->pdev) 1228 continue; 1229 1230 if (pnv_pci_get_gpu_dev(pe->pdev) == gpu_pdev) { 1231 /* 1232 * This device has the same peer GPU so should 1233 * be assigned the same PE as the existing 1234 * peer NPU. 1235 */ 1236 dev_info(&npu_pdev->dev, 1237 "Associating to existing PE %x\n", pe_num); 1238 npu_pdn = pci_get_pdn(npu_pdev); 1239 rid = npu_pdev->bus->number << 8 | npu_pdn->devfn; 1240 npu_pdn->pe_number = pe_num; 1241 phb->ioda.pe_rmap[rid] = pe->pe_number; 1242 1243 /* Map the PE to this link */ 1244 rc = opal_pci_set_pe(phb->opal_id, pe_num, rid, 1245 OpalPciBusAll, 1246 OPAL_COMPARE_RID_DEVICE_NUMBER, 1247 OPAL_COMPARE_RID_FUNCTION_NUMBER, 1248 OPAL_MAP_PE); 1249 WARN_ON(rc != OPAL_SUCCESS); 1250 found_pe = true; 1251 break; 1252 } 1253 } 1254 1255 if (!found_pe) 1256 /* 1257 * Could not find an existing PE so allocate a new 1258 * one. 1259 */ 1260 return pnv_ioda_setup_dev_PE(npu_pdev); 1261 else 1262 return pe; 1263 } 1264 1265 static void pnv_ioda_setup_npu_PEs(struct pci_bus *bus) 1266 { 1267 struct pci_dev *pdev; 1268 1269 list_for_each_entry(pdev, &bus->devices, bus_list) 1270 pnv_ioda_setup_npu_PE(pdev); 1271 } 1272 1273 static void pnv_pci_ioda_setup_PEs(void) 1274 { 1275 struct pci_controller *hose; 1276 struct pnv_phb *phb; 1277 struct pci_bus *bus; 1278 struct pci_dev *pdev; 1279 struct pnv_ioda_pe *pe; 1280 1281 list_for_each_entry(hose, &hose_list, list_node) { 1282 phb = hose->private_data; 1283 if (phb->type == PNV_PHB_NPU_NVLINK) { 1284 /* PE#0 is needed for error reporting */ 1285 pnv_ioda_reserve_pe(phb, 0); 1286 pnv_ioda_setup_npu_PEs(hose->bus); 1287 if (phb->model == PNV_PHB_MODEL_NPU2) 1288 WARN_ON_ONCE(pnv_npu2_init(hose)); 1289 } 1290 if (phb->type == PNV_PHB_NPU_OCAPI) { 1291 bus = hose->bus; 1292 list_for_each_entry(pdev, &bus->devices, bus_list) 1293 pnv_ioda_setup_dev_PE(pdev); 1294 } 1295 } 1296 list_for_each_entry(hose, &hose_list, list_node) { 1297 phb = hose->private_data; 1298 if (phb->type != PNV_PHB_IODA2) 1299 continue; 1300 1301 list_for_each_entry(pe, &phb->ioda.pe_list, list) 1302 pnv_npu2_map_lpar(pe, MSR_DR | MSR_PR | MSR_HV); 1303 } 1304 } 1305 1306 #ifdef CONFIG_PCI_IOV 1307 static int pnv_pci_vf_release_m64(struct pci_dev *pdev, u16 num_vfs) 1308 { 1309 struct pci_bus *bus; 1310 struct pci_controller *hose; 1311 struct pnv_phb *phb; 1312 struct pci_dn *pdn; 1313 int i, j; 1314 int m64_bars; 1315 1316 bus = pdev->bus; 1317 hose = pci_bus_to_host(bus); 1318 phb = hose->private_data; 1319 pdn = pci_get_pdn(pdev); 1320 1321 if (pdn->m64_single_mode) 1322 m64_bars = num_vfs; 1323 else 1324 m64_bars = 1; 1325 1326 for (i = 0; i < PCI_SRIOV_NUM_BARS; i++) 1327 for (j = 0; j < m64_bars; j++) { 1328 if (pdn->m64_map[j][i] == IODA_INVALID_M64) 1329 continue; 1330 opal_pci_phb_mmio_enable(phb->opal_id, 1331 OPAL_M64_WINDOW_TYPE, pdn->m64_map[j][i], 0); 1332 clear_bit(pdn->m64_map[j][i], &phb->ioda.m64_bar_alloc); 1333 pdn->m64_map[j][i] = IODA_INVALID_M64; 1334 } 1335 1336 kfree(pdn->m64_map); 1337 return 0; 1338 } 1339 1340 static int pnv_pci_vf_assign_m64(struct pci_dev *pdev, u16 num_vfs) 1341 { 1342 struct pci_bus *bus; 1343 struct pci_controller *hose; 1344 struct pnv_phb *phb; 1345 struct pci_dn *pdn; 1346 unsigned int win; 1347 struct resource *res; 1348 int i, j; 1349 int64_t rc; 1350 int total_vfs; 1351 resource_size_t size, start; 1352 int pe_num; 1353 int m64_bars; 1354 1355 bus = pdev->bus; 1356 hose = pci_bus_to_host(bus); 1357 phb = hose->private_data; 1358 pdn = pci_get_pdn(pdev); 1359 total_vfs = pci_sriov_get_totalvfs(pdev); 1360 1361 if (pdn->m64_single_mode) 1362 m64_bars = num_vfs; 1363 else 1364 m64_bars = 1; 1365 1366 pdn->m64_map = kmalloc_array(m64_bars, 1367 sizeof(*pdn->m64_map), 1368 GFP_KERNEL); 1369 if (!pdn->m64_map) 1370 return -ENOMEM; 1371 /* Initialize the m64_map to IODA_INVALID_M64 */ 1372 for (i = 0; i < m64_bars ; i++) 1373 for (j = 0; j < PCI_SRIOV_NUM_BARS; j++) 1374 pdn->m64_map[i][j] = IODA_INVALID_M64; 1375 1376 1377 for (i = 0; i < PCI_SRIOV_NUM_BARS; i++) { 1378 res = &pdev->resource[i + PCI_IOV_RESOURCES]; 1379 if (!res->flags || !res->parent) 1380 continue; 1381 1382 for (j = 0; j < m64_bars; j++) { 1383 do { 1384 win = find_next_zero_bit(&phb->ioda.m64_bar_alloc, 1385 phb->ioda.m64_bar_idx + 1, 0); 1386 1387 if (win >= phb->ioda.m64_bar_idx + 1) 1388 goto m64_failed; 1389 } while (test_and_set_bit(win, &phb->ioda.m64_bar_alloc)); 1390 1391 pdn->m64_map[j][i] = win; 1392 1393 if (pdn->m64_single_mode) { 1394 size = pci_iov_resource_size(pdev, 1395 PCI_IOV_RESOURCES + i); 1396 start = res->start + size * j; 1397 } else { 1398 size = resource_size(res); 1399 start = res->start; 1400 } 1401 1402 /* Map the M64 here */ 1403 if (pdn->m64_single_mode) { 1404 pe_num = pdn->pe_num_map[j]; 1405 rc = opal_pci_map_pe_mmio_window(phb->opal_id, 1406 pe_num, OPAL_M64_WINDOW_TYPE, 1407 pdn->m64_map[j][i], 0); 1408 } 1409 1410 rc = opal_pci_set_phb_mem_window(phb->opal_id, 1411 OPAL_M64_WINDOW_TYPE, 1412 pdn->m64_map[j][i], 1413 start, 1414 0, /* unused */ 1415 size); 1416 1417 1418 if (rc != OPAL_SUCCESS) { 1419 dev_err(&pdev->dev, "Failed to map M64 window #%d: %lld\n", 1420 win, rc); 1421 goto m64_failed; 1422 } 1423 1424 if (pdn->m64_single_mode) 1425 rc = opal_pci_phb_mmio_enable(phb->opal_id, 1426 OPAL_M64_WINDOW_TYPE, pdn->m64_map[j][i], 2); 1427 else 1428 rc = opal_pci_phb_mmio_enable(phb->opal_id, 1429 OPAL_M64_WINDOW_TYPE, pdn->m64_map[j][i], 1); 1430 1431 if (rc != OPAL_SUCCESS) { 1432 dev_err(&pdev->dev, "Failed to enable M64 window #%d: %llx\n", 1433 win, rc); 1434 goto m64_failed; 1435 } 1436 } 1437 } 1438 return 0; 1439 1440 m64_failed: 1441 pnv_pci_vf_release_m64(pdev, num_vfs); 1442 return -EBUSY; 1443 } 1444 1445 static long pnv_pci_ioda2_unset_window(struct iommu_table_group *table_group, 1446 int num); 1447 1448 static void pnv_pci_ioda2_release_dma_pe(struct pci_dev *dev, struct pnv_ioda_pe *pe) 1449 { 1450 struct iommu_table *tbl; 1451 int64_t rc; 1452 1453 tbl = pe->table_group.tables[0]; 1454 rc = pnv_pci_ioda2_unset_window(&pe->table_group, 0); 1455 if (rc) 1456 pe_warn(pe, "OPAL error %lld release DMA window\n", rc); 1457 1458 pnv_pci_ioda2_set_bypass(pe, false); 1459 if (pe->table_group.group) { 1460 iommu_group_put(pe->table_group.group); 1461 BUG_ON(pe->table_group.group); 1462 } 1463 iommu_tce_table_put(tbl); 1464 } 1465 1466 static void pnv_ioda_release_vf_PE(struct pci_dev *pdev) 1467 { 1468 struct pci_bus *bus; 1469 struct pci_controller *hose; 1470 struct pnv_phb *phb; 1471 struct pnv_ioda_pe *pe, *pe_n; 1472 struct pci_dn *pdn; 1473 1474 bus = pdev->bus; 1475 hose = pci_bus_to_host(bus); 1476 phb = hose->private_data; 1477 pdn = pci_get_pdn(pdev); 1478 1479 if (!pdev->is_physfn) 1480 return; 1481 1482 list_for_each_entry_safe(pe, pe_n, &phb->ioda.pe_list, list) { 1483 if (pe->parent_dev != pdev) 1484 continue; 1485 1486 pnv_pci_ioda2_release_dma_pe(pdev, pe); 1487 1488 /* Remove from list */ 1489 mutex_lock(&phb->ioda.pe_list_mutex); 1490 list_del(&pe->list); 1491 mutex_unlock(&phb->ioda.pe_list_mutex); 1492 1493 pnv_ioda_deconfigure_pe(phb, pe); 1494 1495 pnv_ioda_free_pe(pe); 1496 } 1497 } 1498 1499 void pnv_pci_sriov_disable(struct pci_dev *pdev) 1500 { 1501 struct pci_bus *bus; 1502 struct pci_controller *hose; 1503 struct pnv_phb *phb; 1504 struct pnv_ioda_pe *pe; 1505 struct pci_dn *pdn; 1506 u16 num_vfs, i; 1507 1508 bus = pdev->bus; 1509 hose = pci_bus_to_host(bus); 1510 phb = hose->private_data; 1511 pdn = pci_get_pdn(pdev); 1512 num_vfs = pdn->num_vfs; 1513 1514 /* Release VF PEs */ 1515 pnv_ioda_release_vf_PE(pdev); 1516 1517 if (phb->type == PNV_PHB_IODA2) { 1518 if (!pdn->m64_single_mode) 1519 pnv_pci_vf_resource_shift(pdev, -*pdn->pe_num_map); 1520 1521 /* Release M64 windows */ 1522 pnv_pci_vf_release_m64(pdev, num_vfs); 1523 1524 /* Release PE numbers */ 1525 if (pdn->m64_single_mode) { 1526 for (i = 0; i < num_vfs; i++) { 1527 if (pdn->pe_num_map[i] == IODA_INVALID_PE) 1528 continue; 1529 1530 pe = &phb->ioda.pe_array[pdn->pe_num_map[i]]; 1531 pnv_ioda_free_pe(pe); 1532 } 1533 } else 1534 bitmap_clear(phb->ioda.pe_alloc, *pdn->pe_num_map, num_vfs); 1535 /* Releasing pe_num_map */ 1536 kfree(pdn->pe_num_map); 1537 } 1538 } 1539 1540 static void pnv_pci_ioda2_setup_dma_pe(struct pnv_phb *phb, 1541 struct pnv_ioda_pe *pe); 1542 #ifdef CONFIG_IOMMU_API 1543 static void pnv_ioda_setup_bus_iommu_group(struct pnv_ioda_pe *pe, 1544 struct iommu_table_group *table_group, struct pci_bus *bus); 1545 1546 #endif 1547 static void pnv_ioda_setup_vf_PE(struct pci_dev *pdev, u16 num_vfs) 1548 { 1549 struct pci_bus *bus; 1550 struct pci_controller *hose; 1551 struct pnv_phb *phb; 1552 struct pnv_ioda_pe *pe; 1553 int pe_num; 1554 u16 vf_index; 1555 struct pci_dn *pdn; 1556 1557 bus = pdev->bus; 1558 hose = pci_bus_to_host(bus); 1559 phb = hose->private_data; 1560 pdn = pci_get_pdn(pdev); 1561 1562 if (!pdev->is_physfn) 1563 return; 1564 1565 /* Reserve PE for each VF */ 1566 for (vf_index = 0; vf_index < num_vfs; vf_index++) { 1567 int vf_devfn = pci_iov_virtfn_devfn(pdev, vf_index); 1568 int vf_bus = pci_iov_virtfn_bus(pdev, vf_index); 1569 struct pci_dn *vf_pdn; 1570 1571 if (pdn->m64_single_mode) 1572 pe_num = pdn->pe_num_map[vf_index]; 1573 else 1574 pe_num = *pdn->pe_num_map + vf_index; 1575 1576 pe = &phb->ioda.pe_array[pe_num]; 1577 pe->pe_number = pe_num; 1578 pe->phb = phb; 1579 pe->flags = PNV_IODA_PE_VF; 1580 pe->pbus = NULL; 1581 pe->parent_dev = pdev; 1582 pe->mve_number = -1; 1583 pe->rid = (vf_bus << 8) | vf_devfn; 1584 1585 pe_info(pe, "VF %04d:%02d:%02d.%d associated with PE#%x\n", 1586 hose->global_number, pdev->bus->number, 1587 PCI_SLOT(vf_devfn), PCI_FUNC(vf_devfn), pe_num); 1588 1589 if (pnv_ioda_configure_pe(phb, pe)) { 1590 /* XXX What do we do here ? */ 1591 pnv_ioda_free_pe(pe); 1592 pe->pdev = NULL; 1593 continue; 1594 } 1595 1596 /* Put PE to the list */ 1597 mutex_lock(&phb->ioda.pe_list_mutex); 1598 list_add_tail(&pe->list, &phb->ioda.pe_list); 1599 mutex_unlock(&phb->ioda.pe_list_mutex); 1600 1601 /* associate this pe to it's pdn */ 1602 list_for_each_entry(vf_pdn, &pdn->parent->child_list, list) { 1603 if (vf_pdn->busno == vf_bus && 1604 vf_pdn->devfn == vf_devfn) { 1605 vf_pdn->pe_number = pe_num; 1606 break; 1607 } 1608 } 1609 1610 pnv_pci_ioda2_setup_dma_pe(phb, pe); 1611 #ifdef CONFIG_IOMMU_API 1612 iommu_register_group(&pe->table_group, 1613 pe->phb->hose->global_number, pe->pe_number); 1614 pnv_ioda_setup_bus_iommu_group(pe, &pe->table_group, NULL); 1615 #endif 1616 } 1617 } 1618 1619 int pnv_pci_sriov_enable(struct pci_dev *pdev, u16 num_vfs) 1620 { 1621 struct pci_bus *bus; 1622 struct pci_controller *hose; 1623 struct pnv_phb *phb; 1624 struct pnv_ioda_pe *pe; 1625 struct pci_dn *pdn; 1626 int ret; 1627 u16 i; 1628 1629 bus = pdev->bus; 1630 hose = pci_bus_to_host(bus); 1631 phb = hose->private_data; 1632 pdn = pci_get_pdn(pdev); 1633 1634 if (phb->type == PNV_PHB_IODA2) { 1635 if (!pdn->vfs_expanded) { 1636 dev_info(&pdev->dev, "don't support this SRIOV device" 1637 " with non 64bit-prefetchable IOV BAR\n"); 1638 return -ENOSPC; 1639 } 1640 1641 /* 1642 * When M64 BARs functions in Single PE mode, the number of VFs 1643 * could be enabled must be less than the number of M64 BARs. 1644 */ 1645 if (pdn->m64_single_mode && num_vfs > phb->ioda.m64_bar_idx) { 1646 dev_info(&pdev->dev, "Not enough M64 BAR for VFs\n"); 1647 return -EBUSY; 1648 } 1649 1650 /* Allocating pe_num_map */ 1651 if (pdn->m64_single_mode) 1652 pdn->pe_num_map = kmalloc_array(num_vfs, 1653 sizeof(*pdn->pe_num_map), 1654 GFP_KERNEL); 1655 else 1656 pdn->pe_num_map = kmalloc(sizeof(*pdn->pe_num_map), GFP_KERNEL); 1657 1658 if (!pdn->pe_num_map) 1659 return -ENOMEM; 1660 1661 if (pdn->m64_single_mode) 1662 for (i = 0; i < num_vfs; i++) 1663 pdn->pe_num_map[i] = IODA_INVALID_PE; 1664 1665 /* Calculate available PE for required VFs */ 1666 if (pdn->m64_single_mode) { 1667 for (i = 0; i < num_vfs; i++) { 1668 pe = pnv_ioda_alloc_pe(phb); 1669 if (!pe) { 1670 ret = -EBUSY; 1671 goto m64_failed; 1672 } 1673 1674 pdn->pe_num_map[i] = pe->pe_number; 1675 } 1676 } else { 1677 mutex_lock(&phb->ioda.pe_alloc_mutex); 1678 *pdn->pe_num_map = bitmap_find_next_zero_area( 1679 phb->ioda.pe_alloc, phb->ioda.total_pe_num, 1680 0, num_vfs, 0); 1681 if (*pdn->pe_num_map >= phb->ioda.total_pe_num) { 1682 mutex_unlock(&phb->ioda.pe_alloc_mutex); 1683 dev_info(&pdev->dev, "Failed to enable VF%d\n", num_vfs); 1684 kfree(pdn->pe_num_map); 1685 return -EBUSY; 1686 } 1687 bitmap_set(phb->ioda.pe_alloc, *pdn->pe_num_map, num_vfs); 1688 mutex_unlock(&phb->ioda.pe_alloc_mutex); 1689 } 1690 pdn->num_vfs = num_vfs; 1691 1692 /* Assign M64 window accordingly */ 1693 ret = pnv_pci_vf_assign_m64(pdev, num_vfs); 1694 if (ret) { 1695 dev_info(&pdev->dev, "Not enough M64 window resources\n"); 1696 goto m64_failed; 1697 } 1698 1699 /* 1700 * When using one M64 BAR to map one IOV BAR, we need to shift 1701 * the IOV BAR according to the PE# allocated to the VFs. 1702 * Otherwise, the PE# for the VF will conflict with others. 1703 */ 1704 if (!pdn->m64_single_mode) { 1705 ret = pnv_pci_vf_resource_shift(pdev, *pdn->pe_num_map); 1706 if (ret) 1707 goto m64_failed; 1708 } 1709 } 1710 1711 /* Setup VF PEs */ 1712 pnv_ioda_setup_vf_PE(pdev, num_vfs); 1713 1714 return 0; 1715 1716 m64_failed: 1717 if (pdn->m64_single_mode) { 1718 for (i = 0; i < num_vfs; i++) { 1719 if (pdn->pe_num_map[i] == IODA_INVALID_PE) 1720 continue; 1721 1722 pe = &phb->ioda.pe_array[pdn->pe_num_map[i]]; 1723 pnv_ioda_free_pe(pe); 1724 } 1725 } else 1726 bitmap_clear(phb->ioda.pe_alloc, *pdn->pe_num_map, num_vfs); 1727 1728 /* Releasing pe_num_map */ 1729 kfree(pdn->pe_num_map); 1730 1731 return ret; 1732 } 1733 1734 int pnv_pcibios_sriov_disable(struct pci_dev *pdev) 1735 { 1736 pnv_pci_sriov_disable(pdev); 1737 1738 /* Release PCI data */ 1739 remove_dev_pci_data(pdev); 1740 return 0; 1741 } 1742 1743 int pnv_pcibios_sriov_enable(struct pci_dev *pdev, u16 num_vfs) 1744 { 1745 /* Allocate PCI data */ 1746 add_dev_pci_data(pdev); 1747 1748 return pnv_pci_sriov_enable(pdev, num_vfs); 1749 } 1750 #endif /* CONFIG_PCI_IOV */ 1751 1752 static void pnv_pci_ioda_dma_dev_setup(struct pnv_phb *phb, struct pci_dev *pdev) 1753 { 1754 struct pci_dn *pdn = pci_get_pdn(pdev); 1755 struct pnv_ioda_pe *pe; 1756 1757 /* 1758 * The function can be called while the PE# 1759 * hasn't been assigned. Do nothing for the 1760 * case. 1761 */ 1762 if (!pdn || pdn->pe_number == IODA_INVALID_PE) 1763 return; 1764 1765 pe = &phb->ioda.pe_array[pdn->pe_number]; 1766 WARN_ON(get_dma_ops(&pdev->dev) != &dma_iommu_ops); 1767 pdev->dev.archdata.dma_offset = pe->tce_bypass_base; 1768 set_iommu_table_base(&pdev->dev, pe->table_group.tables[0]); 1769 /* 1770 * Note: iommu_add_device() will fail here as 1771 * for physical PE: the device is already added by now; 1772 * for virtual PE: sysfs entries are not ready yet and 1773 * tce_iommu_bus_notifier will add the device to a group later. 1774 */ 1775 } 1776 1777 /* 1778 * Reconfigure TVE#0 to be usable as 64-bit DMA space. 1779 * 1780 * The first 4GB of virtual memory for a PE is reserved for 32-bit accesses. 1781 * Devices can only access more than that if bit 59 of the PCI address is set 1782 * by hardware, which indicates TVE#1 should be used instead of TVE#0. 1783 * Many PCI devices are not capable of addressing that many bits, and as a 1784 * result are limited to the 4GB of virtual memory made available to 32-bit 1785 * devices in TVE#0. 1786 * 1787 * In order to work around this, reconfigure TVE#0 to be suitable for 64-bit 1788 * devices by configuring the virtual memory past the first 4GB inaccessible 1789 * by 64-bit DMAs. This should only be used by devices that want more than 1790 * 4GB, and only on PEs that have no 32-bit devices. 1791 * 1792 * Currently this will only work on PHB3 (POWER8). 1793 */ 1794 static int pnv_pci_ioda_dma_64bit_bypass(struct pnv_ioda_pe *pe) 1795 { 1796 u64 window_size, table_size, tce_count, addr; 1797 struct page *table_pages; 1798 u64 tce_order = 28; /* 256MB TCEs */ 1799 __be64 *tces; 1800 s64 rc; 1801 1802 /* 1803 * Window size needs to be a power of two, but needs to account for 1804 * shifting memory by the 4GB offset required to skip 32bit space. 1805 */ 1806 window_size = roundup_pow_of_two(memory_hotplug_max() + (1ULL << 32)); 1807 tce_count = window_size >> tce_order; 1808 table_size = tce_count << 3; 1809 1810 if (table_size < PAGE_SIZE) 1811 table_size = PAGE_SIZE; 1812 1813 table_pages = alloc_pages_node(pe->phb->hose->node, GFP_KERNEL, 1814 get_order(table_size)); 1815 if (!table_pages) 1816 goto err; 1817 1818 tces = page_address(table_pages); 1819 if (!tces) 1820 goto err; 1821 1822 memset(tces, 0, table_size); 1823 1824 for (addr = 0; addr < memory_hotplug_max(); addr += (1 << tce_order)) { 1825 tces[(addr + (1ULL << 32)) >> tce_order] = 1826 cpu_to_be64(addr | TCE_PCI_READ | TCE_PCI_WRITE); 1827 } 1828 1829 rc = opal_pci_map_pe_dma_window(pe->phb->opal_id, 1830 pe->pe_number, 1831 /* reconfigure window 0 */ 1832 (pe->pe_number << 1) + 0, 1833 1, 1834 __pa(tces), 1835 table_size, 1836 1 << tce_order); 1837 if (rc == OPAL_SUCCESS) { 1838 pe_info(pe, "Using 64-bit DMA iommu bypass (through TVE#0)\n"); 1839 return 0; 1840 } 1841 err: 1842 pe_err(pe, "Error configuring 64-bit DMA bypass\n"); 1843 return -EIO; 1844 } 1845 1846 static bool pnv_pci_ioda_iommu_bypass_supported(struct pci_dev *pdev, 1847 u64 dma_mask) 1848 { 1849 struct pci_controller *hose = pci_bus_to_host(pdev->bus); 1850 struct pnv_phb *phb = hose->private_data; 1851 struct pci_dn *pdn = pci_get_pdn(pdev); 1852 struct pnv_ioda_pe *pe; 1853 1854 if (WARN_ON(!pdn || pdn->pe_number == IODA_INVALID_PE)) 1855 return false; 1856 1857 pe = &phb->ioda.pe_array[pdn->pe_number]; 1858 if (pe->tce_bypass_enabled) { 1859 u64 top = pe->tce_bypass_base + memblock_end_of_DRAM() - 1; 1860 if (dma_mask >= top) 1861 return true; 1862 } 1863 1864 /* 1865 * If the device can't set the TCE bypass bit but still wants 1866 * to access 4GB or more, on PHB3 we can reconfigure TVE#0 to 1867 * bypass the 32-bit region and be usable for 64-bit DMAs. 1868 * The device needs to be able to address all of this space. 1869 */ 1870 if (dma_mask >> 32 && 1871 dma_mask > (memory_hotplug_max() + (1ULL << 32)) && 1872 /* pe->pdev should be set if it's a single device, pe->pbus if not */ 1873 (pe->device_count == 1 || !pe->pbus) && 1874 phb->model == PNV_PHB_MODEL_PHB3) { 1875 /* Configure the bypass mode */ 1876 s64 rc = pnv_pci_ioda_dma_64bit_bypass(pe); 1877 if (rc) 1878 return false; 1879 /* 4GB offset bypasses 32-bit space */ 1880 pdev->dev.archdata.dma_offset = (1ULL << 32); 1881 return true; 1882 } 1883 1884 return false; 1885 } 1886 1887 static void pnv_ioda_setup_bus_dma(struct pnv_ioda_pe *pe, struct pci_bus *bus) 1888 { 1889 struct pci_dev *dev; 1890 1891 list_for_each_entry(dev, &bus->devices, bus_list) { 1892 set_iommu_table_base(&dev->dev, pe->table_group.tables[0]); 1893 dev->dev.archdata.dma_offset = pe->tce_bypass_base; 1894 1895 if ((pe->flags & PNV_IODA_PE_BUS_ALL) && dev->subordinate) 1896 pnv_ioda_setup_bus_dma(pe, dev->subordinate); 1897 } 1898 } 1899 1900 static inline __be64 __iomem *pnv_ioda_get_inval_reg(struct pnv_phb *phb, 1901 bool real_mode) 1902 { 1903 return real_mode ? (__be64 __iomem *)(phb->regs_phys + 0x210) : 1904 (phb->regs + 0x210); 1905 } 1906 1907 static void pnv_pci_p7ioc_tce_invalidate(struct iommu_table *tbl, 1908 unsigned long index, unsigned long npages, bool rm) 1909 { 1910 struct iommu_table_group_link *tgl = list_first_entry_or_null( 1911 &tbl->it_group_list, struct iommu_table_group_link, 1912 next); 1913 struct pnv_ioda_pe *pe = container_of(tgl->table_group, 1914 struct pnv_ioda_pe, table_group); 1915 __be64 __iomem *invalidate = pnv_ioda_get_inval_reg(pe->phb, rm); 1916 unsigned long start, end, inc; 1917 1918 start = __pa(((__be64 *)tbl->it_base) + index - tbl->it_offset); 1919 end = __pa(((__be64 *)tbl->it_base) + index - tbl->it_offset + 1920 npages - 1); 1921 1922 /* p7ioc-style invalidation, 2 TCEs per write */ 1923 start |= (1ull << 63); 1924 end |= (1ull << 63); 1925 inc = 16; 1926 end |= inc - 1; /* round up end to be different than start */ 1927 1928 mb(); /* Ensure above stores are visible */ 1929 while (start <= end) { 1930 if (rm) 1931 __raw_rm_writeq_be(start, invalidate); 1932 else 1933 __raw_writeq_be(start, invalidate); 1934 1935 start += inc; 1936 } 1937 1938 /* 1939 * The iommu layer will do another mb() for us on build() 1940 * and we don't care on free() 1941 */ 1942 } 1943 1944 static int pnv_ioda1_tce_build(struct iommu_table *tbl, long index, 1945 long npages, unsigned long uaddr, 1946 enum dma_data_direction direction, 1947 unsigned long attrs) 1948 { 1949 int ret = pnv_tce_build(tbl, index, npages, uaddr, direction, 1950 attrs); 1951 1952 if (!ret) 1953 pnv_pci_p7ioc_tce_invalidate(tbl, index, npages, false); 1954 1955 return ret; 1956 } 1957 1958 #ifdef CONFIG_IOMMU_API 1959 /* Common for IODA1 and IODA2 */ 1960 static int pnv_ioda_tce_xchg_no_kill(struct iommu_table *tbl, long index, 1961 unsigned long *hpa, enum dma_data_direction *direction, 1962 bool realmode) 1963 { 1964 return pnv_tce_xchg(tbl, index, hpa, direction, !realmode); 1965 } 1966 #endif 1967 1968 static void pnv_ioda1_tce_free(struct iommu_table *tbl, long index, 1969 long npages) 1970 { 1971 pnv_tce_free(tbl, index, npages); 1972 1973 pnv_pci_p7ioc_tce_invalidate(tbl, index, npages, false); 1974 } 1975 1976 static struct iommu_table_ops pnv_ioda1_iommu_ops = { 1977 .set = pnv_ioda1_tce_build, 1978 #ifdef CONFIG_IOMMU_API 1979 .xchg_no_kill = pnv_ioda_tce_xchg_no_kill, 1980 .tce_kill = pnv_pci_p7ioc_tce_invalidate, 1981 .useraddrptr = pnv_tce_useraddrptr, 1982 #endif 1983 .clear = pnv_ioda1_tce_free, 1984 .get = pnv_tce_get, 1985 }; 1986 1987 #define PHB3_TCE_KILL_INVAL_ALL PPC_BIT(0) 1988 #define PHB3_TCE_KILL_INVAL_PE PPC_BIT(1) 1989 #define PHB3_TCE_KILL_INVAL_ONE PPC_BIT(2) 1990 1991 static void pnv_pci_phb3_tce_invalidate_entire(struct pnv_phb *phb, bool rm) 1992 { 1993 __be64 __iomem *invalidate = pnv_ioda_get_inval_reg(phb, rm); 1994 const unsigned long val = PHB3_TCE_KILL_INVAL_ALL; 1995 1996 mb(); /* Ensure previous TCE table stores are visible */ 1997 if (rm) 1998 __raw_rm_writeq_be(val, invalidate); 1999 else 2000 __raw_writeq_be(val, invalidate); 2001 } 2002 2003 static inline void pnv_pci_phb3_tce_invalidate_pe(struct pnv_ioda_pe *pe) 2004 { 2005 /* 01xb - invalidate TCEs that match the specified PE# */ 2006 __be64 __iomem *invalidate = pnv_ioda_get_inval_reg(pe->phb, false); 2007 unsigned long val = PHB3_TCE_KILL_INVAL_PE | (pe->pe_number & 0xFF); 2008 2009 mb(); /* Ensure above stores are visible */ 2010 __raw_writeq_be(val, invalidate); 2011 } 2012 2013 static void pnv_pci_phb3_tce_invalidate(struct pnv_ioda_pe *pe, bool rm, 2014 unsigned shift, unsigned long index, 2015 unsigned long npages) 2016 { 2017 __be64 __iomem *invalidate = pnv_ioda_get_inval_reg(pe->phb, rm); 2018 unsigned long start, end, inc; 2019 2020 /* We'll invalidate DMA address in PE scope */ 2021 start = PHB3_TCE_KILL_INVAL_ONE; 2022 start |= (pe->pe_number & 0xFF); 2023 end = start; 2024 2025 /* Figure out the start, end and step */ 2026 start |= (index << shift); 2027 end |= ((index + npages - 1) << shift); 2028 inc = (0x1ull << shift); 2029 mb(); 2030 2031 while (start <= end) { 2032 if (rm) 2033 __raw_rm_writeq_be(start, invalidate); 2034 else 2035 __raw_writeq_be(start, invalidate); 2036 start += inc; 2037 } 2038 } 2039 2040 static inline void pnv_pci_ioda2_tce_invalidate_pe(struct pnv_ioda_pe *pe) 2041 { 2042 struct pnv_phb *phb = pe->phb; 2043 2044 if (phb->model == PNV_PHB_MODEL_PHB3 && phb->regs) 2045 pnv_pci_phb3_tce_invalidate_pe(pe); 2046 else 2047 opal_pci_tce_kill(phb->opal_id, OPAL_PCI_TCE_KILL_PE, 2048 pe->pe_number, 0, 0, 0); 2049 } 2050 2051 static void pnv_pci_ioda2_tce_invalidate(struct iommu_table *tbl, 2052 unsigned long index, unsigned long npages, bool rm) 2053 { 2054 struct iommu_table_group_link *tgl; 2055 2056 list_for_each_entry_lockless(tgl, &tbl->it_group_list, next) { 2057 struct pnv_ioda_pe *pe = container_of(tgl->table_group, 2058 struct pnv_ioda_pe, table_group); 2059 struct pnv_phb *phb = pe->phb; 2060 unsigned int shift = tbl->it_page_shift; 2061 2062 /* 2063 * NVLink1 can use the TCE kill register directly as 2064 * it's the same as PHB3. NVLink2 is different and 2065 * should go via the OPAL call. 2066 */ 2067 if (phb->model == PNV_PHB_MODEL_NPU) { 2068 /* 2069 * The NVLink hardware does not support TCE kill 2070 * per TCE entry so we have to invalidate 2071 * the entire cache for it. 2072 */ 2073 pnv_pci_phb3_tce_invalidate_entire(phb, rm); 2074 continue; 2075 } 2076 if (phb->model == PNV_PHB_MODEL_PHB3 && phb->regs) 2077 pnv_pci_phb3_tce_invalidate(pe, rm, shift, 2078 index, npages); 2079 else 2080 opal_pci_tce_kill(phb->opal_id, 2081 OPAL_PCI_TCE_KILL_PAGES, 2082 pe->pe_number, 1u << shift, 2083 index << shift, npages); 2084 } 2085 } 2086 2087 void pnv_pci_ioda2_tce_invalidate_entire(struct pnv_phb *phb, bool rm) 2088 { 2089 if (phb->model == PNV_PHB_MODEL_NPU || phb->model == PNV_PHB_MODEL_PHB3) 2090 pnv_pci_phb3_tce_invalidate_entire(phb, rm); 2091 else 2092 opal_pci_tce_kill(phb->opal_id, OPAL_PCI_TCE_KILL, 0, 0, 0, 0); 2093 } 2094 2095 static int pnv_ioda2_tce_build(struct iommu_table *tbl, long index, 2096 long npages, unsigned long uaddr, 2097 enum dma_data_direction direction, 2098 unsigned long attrs) 2099 { 2100 int ret = pnv_tce_build(tbl, index, npages, uaddr, direction, 2101 attrs); 2102 2103 if (!ret) 2104 pnv_pci_ioda2_tce_invalidate(tbl, index, npages, false); 2105 2106 return ret; 2107 } 2108 2109 static void pnv_ioda2_tce_free(struct iommu_table *tbl, long index, 2110 long npages) 2111 { 2112 pnv_tce_free(tbl, index, npages); 2113 2114 pnv_pci_ioda2_tce_invalidate(tbl, index, npages, false); 2115 } 2116 2117 static struct iommu_table_ops pnv_ioda2_iommu_ops = { 2118 .set = pnv_ioda2_tce_build, 2119 #ifdef CONFIG_IOMMU_API 2120 .xchg_no_kill = pnv_ioda_tce_xchg_no_kill, 2121 .tce_kill = pnv_pci_ioda2_tce_invalidate, 2122 .useraddrptr = pnv_tce_useraddrptr, 2123 #endif 2124 .clear = pnv_ioda2_tce_free, 2125 .get = pnv_tce_get, 2126 .free = pnv_pci_ioda2_table_free_pages, 2127 }; 2128 2129 static int pnv_pci_ioda_dev_dma_weight(struct pci_dev *dev, void *data) 2130 { 2131 unsigned int *weight = (unsigned int *)data; 2132 2133 /* This is quite simplistic. The "base" weight of a device 2134 * is 10. 0 means no DMA is to be accounted for it. 2135 */ 2136 if (dev->hdr_type != PCI_HEADER_TYPE_NORMAL) 2137 return 0; 2138 2139 if (dev->class == PCI_CLASS_SERIAL_USB_UHCI || 2140 dev->class == PCI_CLASS_SERIAL_USB_OHCI || 2141 dev->class == PCI_CLASS_SERIAL_USB_EHCI) 2142 *weight += 3; 2143 else if ((dev->class >> 8) == PCI_CLASS_STORAGE_RAID) 2144 *weight += 15; 2145 else 2146 *weight += 10; 2147 2148 return 0; 2149 } 2150 2151 static unsigned int pnv_pci_ioda_pe_dma_weight(struct pnv_ioda_pe *pe) 2152 { 2153 unsigned int weight = 0; 2154 2155 /* SRIOV VF has same DMA32 weight as its PF */ 2156 #ifdef CONFIG_PCI_IOV 2157 if ((pe->flags & PNV_IODA_PE_VF) && pe->parent_dev) { 2158 pnv_pci_ioda_dev_dma_weight(pe->parent_dev, &weight); 2159 return weight; 2160 } 2161 #endif 2162 2163 if ((pe->flags & PNV_IODA_PE_DEV) && pe->pdev) { 2164 pnv_pci_ioda_dev_dma_weight(pe->pdev, &weight); 2165 } else if ((pe->flags & PNV_IODA_PE_BUS) && pe->pbus) { 2166 struct pci_dev *pdev; 2167 2168 list_for_each_entry(pdev, &pe->pbus->devices, bus_list) 2169 pnv_pci_ioda_dev_dma_weight(pdev, &weight); 2170 } else if ((pe->flags & PNV_IODA_PE_BUS_ALL) && pe->pbus) { 2171 pci_walk_bus(pe->pbus, pnv_pci_ioda_dev_dma_weight, &weight); 2172 } 2173 2174 return weight; 2175 } 2176 2177 static void pnv_pci_ioda1_setup_dma_pe(struct pnv_phb *phb, 2178 struct pnv_ioda_pe *pe) 2179 { 2180 2181 struct page *tce_mem = NULL; 2182 struct iommu_table *tbl; 2183 unsigned int weight, total_weight = 0; 2184 unsigned int tce32_segsz, base, segs, avail, i; 2185 int64_t rc; 2186 void *addr; 2187 2188 /* XXX FIXME: Handle 64-bit only DMA devices */ 2189 /* XXX FIXME: Provide 64-bit DMA facilities & non-4K TCE tables etc.. */ 2190 /* XXX FIXME: Allocate multi-level tables on PHB3 */ 2191 weight = pnv_pci_ioda_pe_dma_weight(pe); 2192 if (!weight) 2193 return; 2194 2195 pci_walk_bus(phb->hose->bus, pnv_pci_ioda_dev_dma_weight, 2196 &total_weight); 2197 segs = (weight * phb->ioda.dma32_count) / total_weight; 2198 if (!segs) 2199 segs = 1; 2200 2201 /* 2202 * Allocate contiguous DMA32 segments. We begin with the expected 2203 * number of segments. With one more attempt, the number of DMA32 2204 * segments to be allocated is decreased by one until one segment 2205 * is allocated successfully. 2206 */ 2207 do { 2208 for (base = 0; base <= phb->ioda.dma32_count - segs; base++) { 2209 for (avail = 0, i = base; i < base + segs; i++) { 2210 if (phb->ioda.dma32_segmap[i] == 2211 IODA_INVALID_PE) 2212 avail++; 2213 } 2214 2215 if (avail == segs) 2216 goto found; 2217 } 2218 } while (--segs); 2219 2220 if (!segs) { 2221 pe_warn(pe, "No available DMA32 segments\n"); 2222 return; 2223 } 2224 2225 found: 2226 tbl = pnv_pci_table_alloc(phb->hose->node); 2227 if (WARN_ON(!tbl)) 2228 return; 2229 2230 iommu_register_group(&pe->table_group, phb->hose->global_number, 2231 pe->pe_number); 2232 pnv_pci_link_table_and_group(phb->hose->node, 0, tbl, &pe->table_group); 2233 2234 /* Grab a 32-bit TCE table */ 2235 pe_info(pe, "DMA weight %d (%d), assigned (%d) %d DMA32 segments\n", 2236 weight, total_weight, base, segs); 2237 pe_info(pe, " Setting up 32-bit TCE table at %08x..%08x\n", 2238 base * PNV_IODA1_DMA32_SEGSIZE, 2239 (base + segs) * PNV_IODA1_DMA32_SEGSIZE - 1); 2240 2241 /* XXX Currently, we allocate one big contiguous table for the 2242 * TCEs. We only really need one chunk per 256M of TCE space 2243 * (ie per segment) but that's an optimization for later, it 2244 * requires some added smarts with our get/put_tce implementation 2245 * 2246 * Each TCE page is 4KB in size and each TCE entry occupies 8 2247 * bytes 2248 */ 2249 tce32_segsz = PNV_IODA1_DMA32_SEGSIZE >> (IOMMU_PAGE_SHIFT_4K - 3); 2250 tce_mem = alloc_pages_node(phb->hose->node, GFP_KERNEL, 2251 get_order(tce32_segsz * segs)); 2252 if (!tce_mem) { 2253 pe_err(pe, " Failed to allocate a 32-bit TCE memory\n"); 2254 goto fail; 2255 } 2256 addr = page_address(tce_mem); 2257 memset(addr, 0, tce32_segsz * segs); 2258 2259 /* Configure HW */ 2260 for (i = 0; i < segs; i++) { 2261 rc = opal_pci_map_pe_dma_window(phb->opal_id, 2262 pe->pe_number, 2263 base + i, 1, 2264 __pa(addr) + tce32_segsz * i, 2265 tce32_segsz, IOMMU_PAGE_SIZE_4K); 2266 if (rc) { 2267 pe_err(pe, " Failed to configure 32-bit TCE table, err %lld\n", 2268 rc); 2269 goto fail; 2270 } 2271 } 2272 2273 /* Setup DMA32 segment mapping */ 2274 for (i = base; i < base + segs; i++) 2275 phb->ioda.dma32_segmap[i] = pe->pe_number; 2276 2277 /* Setup linux iommu table */ 2278 pnv_pci_setup_iommu_table(tbl, addr, tce32_segsz * segs, 2279 base * PNV_IODA1_DMA32_SEGSIZE, 2280 IOMMU_PAGE_SHIFT_4K); 2281 2282 tbl->it_ops = &pnv_ioda1_iommu_ops; 2283 pe->table_group.tce32_start = tbl->it_offset << tbl->it_page_shift; 2284 pe->table_group.tce32_size = tbl->it_size << tbl->it_page_shift; 2285 iommu_init_table(tbl, phb->hose->node, 0, 0); 2286 2287 if (pe->flags & (PNV_IODA_PE_BUS | PNV_IODA_PE_BUS_ALL)) 2288 pnv_ioda_setup_bus_dma(pe, pe->pbus); 2289 2290 return; 2291 fail: 2292 /* XXX Failure: Try to fallback to 64-bit only ? */ 2293 if (tce_mem) 2294 __free_pages(tce_mem, get_order(tce32_segsz * segs)); 2295 if (tbl) { 2296 pnv_pci_unlink_table_and_group(tbl, &pe->table_group); 2297 iommu_tce_table_put(tbl); 2298 } 2299 } 2300 2301 static long pnv_pci_ioda2_set_window(struct iommu_table_group *table_group, 2302 int num, struct iommu_table *tbl) 2303 { 2304 struct pnv_ioda_pe *pe = container_of(table_group, struct pnv_ioda_pe, 2305 table_group); 2306 struct pnv_phb *phb = pe->phb; 2307 int64_t rc; 2308 const unsigned long size = tbl->it_indirect_levels ? 2309 tbl->it_level_size : tbl->it_size; 2310 const __u64 start_addr = tbl->it_offset << tbl->it_page_shift; 2311 const __u64 win_size = tbl->it_size << tbl->it_page_shift; 2312 2313 pe_info(pe, "Setting up window#%d %llx..%llx pg=%lx\n", 2314 num, start_addr, start_addr + win_size - 1, 2315 IOMMU_PAGE_SIZE(tbl)); 2316 2317 /* 2318 * Map TCE table through TVT. The TVE index is the PE number 2319 * shifted by 1 bit for 32-bits DMA space. 2320 */ 2321 rc = opal_pci_map_pe_dma_window(phb->opal_id, 2322 pe->pe_number, 2323 (pe->pe_number << 1) + num, 2324 tbl->it_indirect_levels + 1, 2325 __pa(tbl->it_base), 2326 size << 3, 2327 IOMMU_PAGE_SIZE(tbl)); 2328 if (rc) { 2329 pe_err(pe, "Failed to configure TCE table, err %lld\n", rc); 2330 return rc; 2331 } 2332 2333 pnv_pci_link_table_and_group(phb->hose->node, num, 2334 tbl, &pe->table_group); 2335 pnv_pci_ioda2_tce_invalidate_pe(pe); 2336 2337 return 0; 2338 } 2339 2340 static void pnv_pci_ioda2_set_bypass(struct pnv_ioda_pe *pe, bool enable) 2341 { 2342 uint16_t window_id = (pe->pe_number << 1 ) + 1; 2343 int64_t rc; 2344 2345 pe_info(pe, "%sabling 64-bit DMA bypass\n", enable ? "En" : "Dis"); 2346 if (enable) { 2347 phys_addr_t top = memblock_end_of_DRAM(); 2348 2349 top = roundup_pow_of_two(top); 2350 rc = opal_pci_map_pe_dma_window_real(pe->phb->opal_id, 2351 pe->pe_number, 2352 window_id, 2353 pe->tce_bypass_base, 2354 top); 2355 } else { 2356 rc = opal_pci_map_pe_dma_window_real(pe->phb->opal_id, 2357 pe->pe_number, 2358 window_id, 2359 pe->tce_bypass_base, 2360 0); 2361 } 2362 if (rc) 2363 pe_err(pe, "OPAL error %lld configuring bypass window\n", rc); 2364 else 2365 pe->tce_bypass_enabled = enable; 2366 } 2367 2368 static long pnv_pci_ioda2_create_table(struct iommu_table_group *table_group, 2369 int num, __u32 page_shift, __u64 window_size, __u32 levels, 2370 bool alloc_userspace_copy, struct iommu_table **ptbl) 2371 { 2372 struct pnv_ioda_pe *pe = container_of(table_group, struct pnv_ioda_pe, 2373 table_group); 2374 int nid = pe->phb->hose->node; 2375 __u64 bus_offset = num ? pe->tce_bypass_base : table_group->tce32_start; 2376 long ret; 2377 struct iommu_table *tbl; 2378 2379 tbl = pnv_pci_table_alloc(nid); 2380 if (!tbl) 2381 return -ENOMEM; 2382 2383 tbl->it_ops = &pnv_ioda2_iommu_ops; 2384 2385 ret = pnv_pci_ioda2_table_alloc_pages(nid, 2386 bus_offset, page_shift, window_size, 2387 levels, alloc_userspace_copy, tbl); 2388 if (ret) { 2389 iommu_tce_table_put(tbl); 2390 return ret; 2391 } 2392 2393 *ptbl = tbl; 2394 2395 return 0; 2396 } 2397 2398 static long pnv_pci_ioda2_setup_default_config(struct pnv_ioda_pe *pe) 2399 { 2400 struct iommu_table *tbl = NULL; 2401 long rc; 2402 unsigned long res_start, res_end; 2403 2404 /* 2405 * crashkernel= specifies the kdump kernel's maximum memory at 2406 * some offset and there is no guaranteed the result is a power 2407 * of 2, which will cause errors later. 2408 */ 2409 const u64 max_memory = __rounddown_pow_of_two(memory_hotplug_max()); 2410 2411 /* 2412 * In memory constrained environments, e.g. kdump kernel, the 2413 * DMA window can be larger than available memory, which will 2414 * cause errors later. 2415 */ 2416 const u64 maxblock = 1UL << (PAGE_SHIFT + MAX_ORDER - 1); 2417 2418 /* 2419 * We create the default window as big as we can. The constraint is 2420 * the max order of allocation possible. The TCE table is likely to 2421 * end up being multilevel and with on-demand allocation in place, 2422 * the initial use is not going to be huge as the default window aims 2423 * to support crippled devices (i.e. not fully 64bit DMAble) only. 2424 */ 2425 /* iommu_table::it_map uses 1 bit per IOMMU page, hence 8 */ 2426 const u64 window_size = min((maxblock * 8) << PAGE_SHIFT, max_memory); 2427 /* Each TCE level cannot exceed maxblock so go multilevel if needed */ 2428 unsigned long tces_order = ilog2(window_size >> PAGE_SHIFT); 2429 unsigned long tcelevel_order = ilog2(maxblock >> 3); 2430 unsigned int levels = tces_order / tcelevel_order; 2431 2432 if (tces_order % tcelevel_order) 2433 levels += 1; 2434 /* 2435 * We try to stick to default levels (which is >1 at the moment) in 2436 * order to save memory by relying on on-demain TCE level allocation. 2437 */ 2438 levels = max_t(unsigned int, levels, POWERNV_IOMMU_DEFAULT_LEVELS); 2439 2440 rc = pnv_pci_ioda2_create_table(&pe->table_group, 0, PAGE_SHIFT, 2441 window_size, levels, false, &tbl); 2442 if (rc) { 2443 pe_err(pe, "Failed to create 32-bit TCE table, err %ld", 2444 rc); 2445 return rc; 2446 } 2447 2448 /* We use top part of 32bit space for MMIO so exclude it from DMA */ 2449 res_start = 0; 2450 res_end = 0; 2451 if (window_size > pe->phb->ioda.m32_pci_base) { 2452 res_start = pe->phb->ioda.m32_pci_base >> tbl->it_page_shift; 2453 res_end = min(window_size, SZ_4G) >> tbl->it_page_shift; 2454 } 2455 iommu_init_table(tbl, pe->phb->hose->node, res_start, res_end); 2456 2457 rc = pnv_pci_ioda2_set_window(&pe->table_group, 0, tbl); 2458 if (rc) { 2459 pe_err(pe, "Failed to configure 32-bit TCE table, err %ld\n", 2460 rc); 2461 iommu_tce_table_put(tbl); 2462 return rc; 2463 } 2464 2465 if (!pnv_iommu_bypass_disabled) 2466 pnv_pci_ioda2_set_bypass(pe, true); 2467 2468 /* 2469 * Set table base for the case of IOMMU DMA use. Usually this is done 2470 * from dma_dev_setup() which is not called when a device is returned 2471 * from VFIO so do it here. 2472 */ 2473 if (pe->pdev) 2474 set_iommu_table_base(&pe->pdev->dev, tbl); 2475 2476 return 0; 2477 } 2478 2479 #if defined(CONFIG_IOMMU_API) || defined(CONFIG_PCI_IOV) 2480 static long pnv_pci_ioda2_unset_window(struct iommu_table_group *table_group, 2481 int num) 2482 { 2483 struct pnv_ioda_pe *pe = container_of(table_group, struct pnv_ioda_pe, 2484 table_group); 2485 struct pnv_phb *phb = pe->phb; 2486 long ret; 2487 2488 pe_info(pe, "Removing DMA window #%d\n", num); 2489 2490 ret = opal_pci_map_pe_dma_window(phb->opal_id, pe->pe_number, 2491 (pe->pe_number << 1) + num, 2492 0/* levels */, 0/* table address */, 2493 0/* table size */, 0/* page size */); 2494 if (ret) 2495 pe_warn(pe, "Unmapping failed, ret = %ld\n", ret); 2496 else 2497 pnv_pci_ioda2_tce_invalidate_pe(pe); 2498 2499 pnv_pci_unlink_table_and_group(table_group->tables[num], table_group); 2500 2501 return ret; 2502 } 2503 #endif 2504 2505 #ifdef CONFIG_IOMMU_API 2506 unsigned long pnv_pci_ioda2_get_table_size(__u32 page_shift, 2507 __u64 window_size, __u32 levels) 2508 { 2509 unsigned long bytes = 0; 2510 const unsigned window_shift = ilog2(window_size); 2511 unsigned entries_shift = window_shift - page_shift; 2512 unsigned table_shift = entries_shift + 3; 2513 unsigned long tce_table_size = max(0x1000UL, 1UL << table_shift); 2514 unsigned long direct_table_size; 2515 2516 if (!levels || (levels > POWERNV_IOMMU_MAX_LEVELS) || 2517 !is_power_of_2(window_size)) 2518 return 0; 2519 2520 /* Calculate a direct table size from window_size and levels */ 2521 entries_shift = (entries_shift + levels - 1) / levels; 2522 table_shift = entries_shift + 3; 2523 table_shift = max_t(unsigned, table_shift, PAGE_SHIFT); 2524 direct_table_size = 1UL << table_shift; 2525 2526 for ( ; levels; --levels) { 2527 bytes += _ALIGN_UP(tce_table_size, direct_table_size); 2528 2529 tce_table_size /= direct_table_size; 2530 tce_table_size <<= 3; 2531 tce_table_size = max_t(unsigned long, 2532 tce_table_size, direct_table_size); 2533 } 2534 2535 return bytes + bytes; /* one for HW table, one for userspace copy */ 2536 } 2537 2538 static long pnv_pci_ioda2_create_table_userspace( 2539 struct iommu_table_group *table_group, 2540 int num, __u32 page_shift, __u64 window_size, __u32 levels, 2541 struct iommu_table **ptbl) 2542 { 2543 long ret = pnv_pci_ioda2_create_table(table_group, 2544 num, page_shift, window_size, levels, true, ptbl); 2545 2546 if (!ret) 2547 (*ptbl)->it_allocated_size = pnv_pci_ioda2_get_table_size( 2548 page_shift, window_size, levels); 2549 return ret; 2550 } 2551 2552 static void pnv_ioda2_take_ownership(struct iommu_table_group *table_group) 2553 { 2554 struct pnv_ioda_pe *pe = container_of(table_group, struct pnv_ioda_pe, 2555 table_group); 2556 /* Store @tbl as pnv_pci_ioda2_unset_window() resets it */ 2557 struct iommu_table *tbl = pe->table_group.tables[0]; 2558 2559 pnv_pci_ioda2_set_bypass(pe, false); 2560 pnv_pci_ioda2_unset_window(&pe->table_group, 0); 2561 if (pe->pbus) 2562 pnv_ioda_setup_bus_dma(pe, pe->pbus); 2563 else if (pe->pdev) 2564 set_iommu_table_base(&pe->pdev->dev, NULL); 2565 iommu_tce_table_put(tbl); 2566 } 2567 2568 static void pnv_ioda2_release_ownership(struct iommu_table_group *table_group) 2569 { 2570 struct pnv_ioda_pe *pe = container_of(table_group, struct pnv_ioda_pe, 2571 table_group); 2572 2573 pnv_pci_ioda2_setup_default_config(pe); 2574 if (pe->pbus) 2575 pnv_ioda_setup_bus_dma(pe, pe->pbus); 2576 } 2577 2578 static struct iommu_table_group_ops pnv_pci_ioda2_ops = { 2579 .get_table_size = pnv_pci_ioda2_get_table_size, 2580 .create_table = pnv_pci_ioda2_create_table_userspace, 2581 .set_window = pnv_pci_ioda2_set_window, 2582 .unset_window = pnv_pci_ioda2_unset_window, 2583 .take_ownership = pnv_ioda2_take_ownership, 2584 .release_ownership = pnv_ioda2_release_ownership, 2585 }; 2586 2587 static void pnv_ioda_setup_bus_iommu_group_add_devices(struct pnv_ioda_pe *pe, 2588 struct iommu_table_group *table_group, 2589 struct pci_bus *bus) 2590 { 2591 struct pci_dev *dev; 2592 2593 list_for_each_entry(dev, &bus->devices, bus_list) { 2594 iommu_add_device(table_group, &dev->dev); 2595 2596 if ((pe->flags & PNV_IODA_PE_BUS_ALL) && dev->subordinate) 2597 pnv_ioda_setup_bus_iommu_group_add_devices(pe, 2598 table_group, dev->subordinate); 2599 } 2600 } 2601 2602 static void pnv_ioda_setup_bus_iommu_group(struct pnv_ioda_pe *pe, 2603 struct iommu_table_group *table_group, struct pci_bus *bus) 2604 { 2605 2606 if (pe->flags & PNV_IODA_PE_DEV) 2607 iommu_add_device(table_group, &pe->pdev->dev); 2608 2609 if ((pe->flags & (PNV_IODA_PE_BUS | PNV_IODA_PE_BUS_ALL)) || bus) 2610 pnv_ioda_setup_bus_iommu_group_add_devices(pe, table_group, 2611 bus); 2612 } 2613 2614 static unsigned long pnv_ioda_parse_tce_sizes(struct pnv_phb *phb); 2615 2616 static void pnv_pci_ioda_setup_iommu_api(void) 2617 { 2618 struct pci_controller *hose; 2619 struct pnv_phb *phb; 2620 struct pnv_ioda_pe *pe; 2621 2622 /* 2623 * There are 4 types of PEs: 2624 * - PNV_IODA_PE_BUS: a downstream port with an adapter, 2625 * created from pnv_pci_setup_bridge(); 2626 * - PNV_IODA_PE_BUS_ALL: a PCI-PCIX bridge with devices behind it, 2627 * created from pnv_pci_setup_bridge(); 2628 * - PNV_IODA_PE_VF: a SRIOV virtual function, 2629 * created from pnv_pcibios_sriov_enable(); 2630 * - PNV_IODA_PE_DEV: an NPU or OCAPI device, 2631 * created from pnv_pci_ioda_fixup(). 2632 * 2633 * Normally a PE is represented by an IOMMU group, however for 2634 * devices with side channels the groups need to be more strict. 2635 */ 2636 list_for_each_entry(hose, &hose_list, list_node) { 2637 phb = hose->private_data; 2638 2639 if (phb->type == PNV_PHB_NPU_NVLINK || 2640 phb->type == PNV_PHB_NPU_OCAPI) 2641 continue; 2642 2643 list_for_each_entry(pe, &phb->ioda.pe_list, list) { 2644 struct iommu_table_group *table_group; 2645 2646 table_group = pnv_try_setup_npu_table_group(pe); 2647 if (!table_group) { 2648 if (!pnv_pci_ioda_pe_dma_weight(pe)) 2649 continue; 2650 2651 table_group = &pe->table_group; 2652 iommu_register_group(&pe->table_group, 2653 pe->phb->hose->global_number, 2654 pe->pe_number); 2655 } 2656 pnv_ioda_setup_bus_iommu_group(pe, table_group, 2657 pe->pbus); 2658 } 2659 } 2660 2661 /* 2662 * Now we have all PHBs discovered, time to add NPU devices to 2663 * the corresponding IOMMU groups. 2664 */ 2665 list_for_each_entry(hose, &hose_list, list_node) { 2666 unsigned long pgsizes; 2667 2668 phb = hose->private_data; 2669 2670 if (phb->type != PNV_PHB_NPU_NVLINK) 2671 continue; 2672 2673 pgsizes = pnv_ioda_parse_tce_sizes(phb); 2674 list_for_each_entry(pe, &phb->ioda.pe_list, list) { 2675 /* 2676 * IODA2 bridges get this set up from 2677 * pci_controller_ops::setup_bridge but NPU bridges 2678 * do not have this hook defined so we do it here. 2679 */ 2680 pe->table_group.pgsizes = pgsizes; 2681 pnv_npu_compound_attach(pe); 2682 } 2683 } 2684 } 2685 #else /* !CONFIG_IOMMU_API */ 2686 static void pnv_pci_ioda_setup_iommu_api(void) { }; 2687 #endif 2688 2689 static unsigned long pnv_ioda_parse_tce_sizes(struct pnv_phb *phb) 2690 { 2691 struct pci_controller *hose = phb->hose; 2692 struct device_node *dn = hose->dn; 2693 unsigned long mask = 0; 2694 int i, rc, count; 2695 u32 val; 2696 2697 count = of_property_count_u32_elems(dn, "ibm,supported-tce-sizes"); 2698 if (count <= 0) { 2699 mask = SZ_4K | SZ_64K; 2700 /* Add 16M for POWER8 by default */ 2701 if (cpu_has_feature(CPU_FTR_ARCH_207S) && 2702 !cpu_has_feature(CPU_FTR_ARCH_300)) 2703 mask |= SZ_16M | SZ_256M; 2704 return mask; 2705 } 2706 2707 for (i = 0; i < count; i++) { 2708 rc = of_property_read_u32_index(dn, "ibm,supported-tce-sizes", 2709 i, &val); 2710 if (rc == 0) 2711 mask |= 1ULL << val; 2712 } 2713 2714 return mask; 2715 } 2716 2717 static void pnv_pci_ioda2_setup_dma_pe(struct pnv_phb *phb, 2718 struct pnv_ioda_pe *pe) 2719 { 2720 int64_t rc; 2721 2722 if (!pnv_pci_ioda_pe_dma_weight(pe)) 2723 return; 2724 2725 /* TVE #1 is selected by PCI address bit 59 */ 2726 pe->tce_bypass_base = 1ull << 59; 2727 2728 /* The PE will reserve all possible 32-bits space */ 2729 pe_info(pe, "Setting up 32-bit TCE table at 0..%08x\n", 2730 phb->ioda.m32_pci_base); 2731 2732 /* Setup linux iommu table */ 2733 pe->table_group.tce32_start = 0; 2734 pe->table_group.tce32_size = phb->ioda.m32_pci_base; 2735 pe->table_group.max_dynamic_windows_supported = 2736 IOMMU_TABLE_GROUP_MAX_TABLES; 2737 pe->table_group.max_levels = POWERNV_IOMMU_MAX_LEVELS; 2738 pe->table_group.pgsizes = pnv_ioda_parse_tce_sizes(phb); 2739 #ifdef CONFIG_IOMMU_API 2740 pe->table_group.ops = &pnv_pci_ioda2_ops; 2741 #endif 2742 2743 rc = pnv_pci_ioda2_setup_default_config(pe); 2744 if (rc) 2745 return; 2746 2747 if (pe->flags & (PNV_IODA_PE_BUS | PNV_IODA_PE_BUS_ALL)) 2748 pnv_ioda_setup_bus_dma(pe, pe->pbus); 2749 } 2750 2751 int64_t pnv_opal_pci_msi_eoi(struct irq_chip *chip, unsigned int hw_irq) 2752 { 2753 struct pnv_phb *phb = container_of(chip, struct pnv_phb, 2754 ioda.irq_chip); 2755 2756 return opal_pci_msi_eoi(phb->opal_id, hw_irq); 2757 } 2758 2759 static void pnv_ioda2_msi_eoi(struct irq_data *d) 2760 { 2761 int64_t rc; 2762 unsigned int hw_irq = (unsigned int)irqd_to_hwirq(d); 2763 struct irq_chip *chip = irq_data_get_irq_chip(d); 2764 2765 rc = pnv_opal_pci_msi_eoi(chip, hw_irq); 2766 WARN_ON_ONCE(rc); 2767 2768 icp_native_eoi(d); 2769 } 2770 2771 2772 void pnv_set_msi_irq_chip(struct pnv_phb *phb, unsigned int virq) 2773 { 2774 struct irq_data *idata; 2775 struct irq_chip *ichip; 2776 2777 /* The MSI EOI OPAL call is only needed on PHB3 */ 2778 if (phb->model != PNV_PHB_MODEL_PHB3) 2779 return; 2780 2781 if (!phb->ioda.irq_chip_init) { 2782 /* 2783 * First time we setup an MSI IRQ, we need to setup the 2784 * corresponding IRQ chip to route correctly. 2785 */ 2786 idata = irq_get_irq_data(virq); 2787 ichip = irq_data_get_irq_chip(idata); 2788 phb->ioda.irq_chip_init = 1; 2789 phb->ioda.irq_chip = *ichip; 2790 phb->ioda.irq_chip.irq_eoi = pnv_ioda2_msi_eoi; 2791 } 2792 irq_set_chip(virq, &phb->ioda.irq_chip); 2793 } 2794 2795 /* 2796 * Returns true iff chip is something that we could call 2797 * pnv_opal_pci_msi_eoi for. 2798 */ 2799 bool is_pnv_opal_msi(struct irq_chip *chip) 2800 { 2801 return chip->irq_eoi == pnv_ioda2_msi_eoi; 2802 } 2803 EXPORT_SYMBOL_GPL(is_pnv_opal_msi); 2804 2805 static int pnv_pci_ioda_msi_setup(struct pnv_phb *phb, struct pci_dev *dev, 2806 unsigned int hwirq, unsigned int virq, 2807 unsigned int is_64, struct msi_msg *msg) 2808 { 2809 struct pnv_ioda_pe *pe = pnv_ioda_get_pe(dev); 2810 unsigned int xive_num = hwirq - phb->msi_base; 2811 __be32 data; 2812 int rc; 2813 2814 /* No PE assigned ? bail out ... no MSI for you ! */ 2815 if (pe == NULL) 2816 return -ENXIO; 2817 2818 /* Check if we have an MVE */ 2819 if (pe->mve_number < 0) 2820 return -ENXIO; 2821 2822 /* Force 32-bit MSI on some broken devices */ 2823 if (dev->no_64bit_msi) 2824 is_64 = 0; 2825 2826 /* Assign XIVE to PE */ 2827 rc = opal_pci_set_xive_pe(phb->opal_id, pe->pe_number, xive_num); 2828 if (rc) { 2829 pr_warn("%s: OPAL error %d setting XIVE %d PE\n", 2830 pci_name(dev), rc, xive_num); 2831 return -EIO; 2832 } 2833 2834 if (is_64) { 2835 __be64 addr64; 2836 2837 rc = opal_get_msi_64(phb->opal_id, pe->mve_number, xive_num, 1, 2838 &addr64, &data); 2839 if (rc) { 2840 pr_warn("%s: OPAL error %d getting 64-bit MSI data\n", 2841 pci_name(dev), rc); 2842 return -EIO; 2843 } 2844 msg->address_hi = be64_to_cpu(addr64) >> 32; 2845 msg->address_lo = be64_to_cpu(addr64) & 0xfffffffful; 2846 } else { 2847 __be32 addr32; 2848 2849 rc = opal_get_msi_32(phb->opal_id, pe->mve_number, xive_num, 1, 2850 &addr32, &data); 2851 if (rc) { 2852 pr_warn("%s: OPAL error %d getting 32-bit MSI data\n", 2853 pci_name(dev), rc); 2854 return -EIO; 2855 } 2856 msg->address_hi = 0; 2857 msg->address_lo = be32_to_cpu(addr32); 2858 } 2859 msg->data = be32_to_cpu(data); 2860 2861 pnv_set_msi_irq_chip(phb, virq); 2862 2863 pr_devel("%s: %s-bit MSI on hwirq %x (xive #%d)," 2864 " address=%x_%08x data=%x PE# %x\n", 2865 pci_name(dev), is_64 ? "64" : "32", hwirq, xive_num, 2866 msg->address_hi, msg->address_lo, data, pe->pe_number); 2867 2868 return 0; 2869 } 2870 2871 static void pnv_pci_init_ioda_msis(struct pnv_phb *phb) 2872 { 2873 unsigned int count; 2874 const __be32 *prop = of_get_property(phb->hose->dn, 2875 "ibm,opal-msi-ranges", NULL); 2876 if (!prop) { 2877 /* BML Fallback */ 2878 prop = of_get_property(phb->hose->dn, "msi-ranges", NULL); 2879 } 2880 if (!prop) 2881 return; 2882 2883 phb->msi_base = be32_to_cpup(prop); 2884 count = be32_to_cpup(prop + 1); 2885 if (msi_bitmap_alloc(&phb->msi_bmp, count, phb->hose->dn)) { 2886 pr_err("PCI %d: Failed to allocate MSI bitmap !\n", 2887 phb->hose->global_number); 2888 return; 2889 } 2890 2891 phb->msi_setup = pnv_pci_ioda_msi_setup; 2892 phb->msi32_support = 1; 2893 pr_info(" Allocated bitmap for %d MSIs (base IRQ 0x%x)\n", 2894 count, phb->msi_base); 2895 } 2896 2897 #ifdef CONFIG_PCI_IOV 2898 static void pnv_pci_ioda_fixup_iov_resources(struct pci_dev *pdev) 2899 { 2900 struct pci_controller *hose = pci_bus_to_host(pdev->bus); 2901 struct pnv_phb *phb = hose->private_data; 2902 const resource_size_t gate = phb->ioda.m64_segsize >> 2; 2903 struct resource *res; 2904 int i; 2905 resource_size_t size, total_vf_bar_sz; 2906 struct pci_dn *pdn; 2907 int mul, total_vfs; 2908 2909 if (!pdev->is_physfn || pci_dev_is_added(pdev)) 2910 return; 2911 2912 pdn = pci_get_pdn(pdev); 2913 pdn->vfs_expanded = 0; 2914 pdn->m64_single_mode = false; 2915 2916 total_vfs = pci_sriov_get_totalvfs(pdev); 2917 mul = phb->ioda.total_pe_num; 2918 total_vf_bar_sz = 0; 2919 2920 for (i = 0; i < PCI_SRIOV_NUM_BARS; i++) { 2921 res = &pdev->resource[i + PCI_IOV_RESOURCES]; 2922 if (!res->flags || res->parent) 2923 continue; 2924 if (!pnv_pci_is_m64_flags(res->flags)) { 2925 dev_warn(&pdev->dev, "Don't support SR-IOV with" 2926 " non M64 VF BAR%d: %pR. \n", 2927 i, res); 2928 goto truncate_iov; 2929 } 2930 2931 total_vf_bar_sz += pci_iov_resource_size(pdev, 2932 i + PCI_IOV_RESOURCES); 2933 2934 /* 2935 * If bigger than quarter of M64 segment size, just round up 2936 * power of two. 2937 * 2938 * Generally, one M64 BAR maps one IOV BAR. To avoid conflict 2939 * with other devices, IOV BAR size is expanded to be 2940 * (total_pe * VF_BAR_size). When VF_BAR_size is half of M64 2941 * segment size , the expanded size would equal to half of the 2942 * whole M64 space size, which will exhaust the M64 Space and 2943 * limit the system flexibility. This is a design decision to 2944 * set the boundary to quarter of the M64 segment size. 2945 */ 2946 if (total_vf_bar_sz > gate) { 2947 mul = roundup_pow_of_two(total_vfs); 2948 dev_info(&pdev->dev, 2949 "VF BAR Total IOV size %llx > %llx, roundup to %d VFs\n", 2950 total_vf_bar_sz, gate, mul); 2951 pdn->m64_single_mode = true; 2952 break; 2953 } 2954 } 2955 2956 for (i = 0; i < PCI_SRIOV_NUM_BARS; i++) { 2957 res = &pdev->resource[i + PCI_IOV_RESOURCES]; 2958 if (!res->flags || res->parent) 2959 continue; 2960 2961 size = pci_iov_resource_size(pdev, i + PCI_IOV_RESOURCES); 2962 /* 2963 * On PHB3, the minimum size alignment of M64 BAR in single 2964 * mode is 32MB. 2965 */ 2966 if (pdn->m64_single_mode && (size < SZ_32M)) 2967 goto truncate_iov; 2968 dev_dbg(&pdev->dev, " Fixing VF BAR%d: %pR to\n", i, res); 2969 res->end = res->start + size * mul - 1; 2970 dev_dbg(&pdev->dev, " %pR\n", res); 2971 dev_info(&pdev->dev, "VF BAR%d: %pR (expanded to %d VFs for PE alignment)", 2972 i, res, mul); 2973 } 2974 pdn->vfs_expanded = mul; 2975 2976 return; 2977 2978 truncate_iov: 2979 /* To save MMIO space, IOV BAR is truncated. */ 2980 for (i = 0; i < PCI_SRIOV_NUM_BARS; i++) { 2981 res = &pdev->resource[i + PCI_IOV_RESOURCES]; 2982 res->flags = 0; 2983 res->end = res->start - 1; 2984 } 2985 } 2986 #endif /* CONFIG_PCI_IOV */ 2987 2988 static void pnv_ioda_setup_pe_res(struct pnv_ioda_pe *pe, 2989 struct resource *res) 2990 { 2991 struct pnv_phb *phb = pe->phb; 2992 struct pci_bus_region region; 2993 int index; 2994 int64_t rc; 2995 2996 if (!res || !res->flags || res->start > res->end) 2997 return; 2998 2999 if (res->flags & IORESOURCE_IO) { 3000 region.start = res->start - phb->ioda.io_pci_base; 3001 region.end = res->end - phb->ioda.io_pci_base; 3002 index = region.start / phb->ioda.io_segsize; 3003 3004 while (index < phb->ioda.total_pe_num && 3005 region.start <= region.end) { 3006 phb->ioda.io_segmap[index] = pe->pe_number; 3007 rc = opal_pci_map_pe_mmio_window(phb->opal_id, 3008 pe->pe_number, OPAL_IO_WINDOW_TYPE, 0, index); 3009 if (rc != OPAL_SUCCESS) { 3010 pr_err("%s: Error %lld mapping IO segment#%d to PE#%x\n", 3011 __func__, rc, index, pe->pe_number); 3012 break; 3013 } 3014 3015 region.start += phb->ioda.io_segsize; 3016 index++; 3017 } 3018 } else if ((res->flags & IORESOURCE_MEM) && 3019 !pnv_pci_is_m64(phb, res)) { 3020 region.start = res->start - 3021 phb->hose->mem_offset[0] - 3022 phb->ioda.m32_pci_base; 3023 region.end = res->end - 3024 phb->hose->mem_offset[0] - 3025 phb->ioda.m32_pci_base; 3026 index = region.start / phb->ioda.m32_segsize; 3027 3028 while (index < phb->ioda.total_pe_num && 3029 region.start <= region.end) { 3030 phb->ioda.m32_segmap[index] = pe->pe_number; 3031 rc = opal_pci_map_pe_mmio_window(phb->opal_id, 3032 pe->pe_number, OPAL_M32_WINDOW_TYPE, 0, index); 3033 if (rc != OPAL_SUCCESS) { 3034 pr_err("%s: Error %lld mapping M32 segment#%d to PE#%x", 3035 __func__, rc, index, pe->pe_number); 3036 break; 3037 } 3038 3039 region.start += phb->ioda.m32_segsize; 3040 index++; 3041 } 3042 } 3043 } 3044 3045 /* 3046 * This function is supposed to be called on basis of PE from top 3047 * to bottom style. So the the I/O or MMIO segment assigned to 3048 * parent PE could be overridden by its child PEs if necessary. 3049 */ 3050 static void pnv_ioda_setup_pe_seg(struct pnv_ioda_pe *pe) 3051 { 3052 struct pci_dev *pdev; 3053 int i; 3054 3055 /* 3056 * NOTE: We only care PCI bus based PE for now. For PCI 3057 * device based PE, for example SRIOV sensitive VF should 3058 * be figured out later. 3059 */ 3060 BUG_ON(!(pe->flags & (PNV_IODA_PE_BUS | PNV_IODA_PE_BUS_ALL))); 3061 3062 list_for_each_entry(pdev, &pe->pbus->devices, bus_list) { 3063 for (i = 0; i <= PCI_ROM_RESOURCE; i++) 3064 pnv_ioda_setup_pe_res(pe, &pdev->resource[i]); 3065 3066 /* 3067 * If the PE contains all subordinate PCI buses, the 3068 * windows of the child bridges should be mapped to 3069 * the PE as well. 3070 */ 3071 if (!(pe->flags & PNV_IODA_PE_BUS_ALL) || !pci_is_bridge(pdev)) 3072 continue; 3073 for (i = 0; i < PCI_BRIDGE_RESOURCE_NUM; i++) 3074 pnv_ioda_setup_pe_res(pe, 3075 &pdev->resource[PCI_BRIDGE_RESOURCES + i]); 3076 } 3077 } 3078 3079 #ifdef CONFIG_DEBUG_FS 3080 static int pnv_pci_diag_data_set(void *data, u64 val) 3081 { 3082 struct pci_controller *hose; 3083 struct pnv_phb *phb; 3084 s64 ret; 3085 3086 if (val != 1ULL) 3087 return -EINVAL; 3088 3089 hose = (struct pci_controller *)data; 3090 if (!hose || !hose->private_data) 3091 return -ENODEV; 3092 3093 phb = hose->private_data; 3094 3095 /* Retrieve the diag data from firmware */ 3096 ret = opal_pci_get_phb_diag_data2(phb->opal_id, phb->diag_data, 3097 phb->diag_data_size); 3098 if (ret != OPAL_SUCCESS) 3099 return -EIO; 3100 3101 /* Print the diag data to the kernel log */ 3102 pnv_pci_dump_phb_diag_data(phb->hose, phb->diag_data); 3103 return 0; 3104 } 3105 3106 DEFINE_DEBUGFS_ATTRIBUTE(pnv_pci_diag_data_fops, NULL, pnv_pci_diag_data_set, 3107 "%llu\n"); 3108 3109 #endif /* CONFIG_DEBUG_FS */ 3110 3111 static void pnv_pci_ioda_create_dbgfs(void) 3112 { 3113 #ifdef CONFIG_DEBUG_FS 3114 struct pci_controller *hose, *tmp; 3115 struct pnv_phb *phb; 3116 char name[16]; 3117 3118 list_for_each_entry_safe(hose, tmp, &hose_list, list_node) { 3119 phb = hose->private_data; 3120 3121 /* Notify initialization of PHB done */ 3122 phb->initialized = 1; 3123 3124 sprintf(name, "PCI%04x", hose->global_number); 3125 phb->dbgfs = debugfs_create_dir(name, powerpc_debugfs_root); 3126 if (!phb->dbgfs) { 3127 pr_warn("%s: Error on creating debugfs on PHB#%x\n", 3128 __func__, hose->global_number); 3129 continue; 3130 } 3131 3132 debugfs_create_file_unsafe("dump_diag_regs", 0200, phb->dbgfs, 3133 hose, &pnv_pci_diag_data_fops); 3134 } 3135 #endif /* CONFIG_DEBUG_FS */ 3136 } 3137 3138 static void pnv_pci_enable_bridge(struct pci_bus *bus) 3139 { 3140 struct pci_dev *dev = bus->self; 3141 struct pci_bus *child; 3142 3143 /* Empty bus ? bail */ 3144 if (list_empty(&bus->devices)) 3145 return; 3146 3147 /* 3148 * If there's a bridge associated with that bus enable it. This works 3149 * around races in the generic code if the enabling is done during 3150 * parallel probing. This can be removed once those races have been 3151 * fixed. 3152 */ 3153 if (dev) { 3154 int rc = pci_enable_device(dev); 3155 if (rc) 3156 pci_err(dev, "Error enabling bridge (%d)\n", rc); 3157 pci_set_master(dev); 3158 } 3159 3160 /* Perform the same to child busses */ 3161 list_for_each_entry(child, &bus->children, node) 3162 pnv_pci_enable_bridge(child); 3163 } 3164 3165 static void pnv_pci_enable_bridges(void) 3166 { 3167 struct pci_controller *hose; 3168 3169 list_for_each_entry(hose, &hose_list, list_node) 3170 pnv_pci_enable_bridge(hose->bus); 3171 } 3172 3173 static void pnv_pci_ioda_fixup(void) 3174 { 3175 pnv_pci_ioda_setup_PEs(); 3176 pnv_pci_ioda_setup_iommu_api(); 3177 pnv_pci_ioda_create_dbgfs(); 3178 3179 pnv_pci_enable_bridges(); 3180 3181 #ifdef CONFIG_EEH 3182 pnv_eeh_post_init(); 3183 #endif 3184 } 3185 3186 /* 3187 * Returns the alignment for I/O or memory windows for P2P 3188 * bridges. That actually depends on how PEs are segmented. 3189 * For now, we return I/O or M32 segment size for PE sensitive 3190 * P2P bridges. Otherwise, the default values (4KiB for I/O, 3191 * 1MiB for memory) will be returned. 3192 * 3193 * The current PCI bus might be put into one PE, which was 3194 * create against the parent PCI bridge. For that case, we 3195 * needn't enlarge the alignment so that we can save some 3196 * resources. 3197 */ 3198 static resource_size_t pnv_pci_window_alignment(struct pci_bus *bus, 3199 unsigned long type) 3200 { 3201 struct pci_dev *bridge; 3202 struct pci_controller *hose = pci_bus_to_host(bus); 3203 struct pnv_phb *phb = hose->private_data; 3204 int num_pci_bridges = 0; 3205 3206 bridge = bus->self; 3207 while (bridge) { 3208 if (pci_pcie_type(bridge) == PCI_EXP_TYPE_PCI_BRIDGE) { 3209 num_pci_bridges++; 3210 if (num_pci_bridges >= 2) 3211 return 1; 3212 } 3213 3214 bridge = bridge->bus->self; 3215 } 3216 3217 /* 3218 * We fall back to M32 if M64 isn't supported. We enforce the M64 3219 * alignment for any 64-bit resource, PCIe doesn't care and 3220 * bridges only do 64-bit prefetchable anyway. 3221 */ 3222 if (phb->ioda.m64_segsize && pnv_pci_is_m64_flags(type)) 3223 return phb->ioda.m64_segsize; 3224 if (type & IORESOURCE_MEM) 3225 return phb->ioda.m32_segsize; 3226 3227 return phb->ioda.io_segsize; 3228 } 3229 3230 /* 3231 * We are updating root port or the upstream port of the 3232 * bridge behind the root port with PHB's windows in order 3233 * to accommodate the changes on required resources during 3234 * PCI (slot) hotplug, which is connected to either root 3235 * port or the downstream ports of PCIe switch behind the 3236 * root port. 3237 */ 3238 static void pnv_pci_fixup_bridge_resources(struct pci_bus *bus, 3239 unsigned long type) 3240 { 3241 struct pci_controller *hose = pci_bus_to_host(bus); 3242 struct pnv_phb *phb = hose->private_data; 3243 struct pci_dev *bridge = bus->self; 3244 struct resource *r, *w; 3245 bool msi_region = false; 3246 int i; 3247 3248 /* Check if we need apply fixup to the bridge's windows */ 3249 if (!pci_is_root_bus(bridge->bus) && 3250 !pci_is_root_bus(bridge->bus->self->bus)) 3251 return; 3252 3253 /* Fixup the resources */ 3254 for (i = 0; i < PCI_BRIDGE_RESOURCE_NUM; i++) { 3255 r = &bridge->resource[PCI_BRIDGE_RESOURCES + i]; 3256 if (!r->flags || !r->parent) 3257 continue; 3258 3259 w = NULL; 3260 if (r->flags & type & IORESOURCE_IO) 3261 w = &hose->io_resource; 3262 else if (pnv_pci_is_m64(phb, r) && 3263 (type & IORESOURCE_PREFETCH) && 3264 phb->ioda.m64_segsize) 3265 w = &hose->mem_resources[1]; 3266 else if (r->flags & type & IORESOURCE_MEM) { 3267 w = &hose->mem_resources[0]; 3268 msi_region = true; 3269 } 3270 3271 r->start = w->start; 3272 r->end = w->end; 3273 3274 /* The 64KB 32-bits MSI region shouldn't be included in 3275 * the 32-bits bridge window. Otherwise, we can see strange 3276 * issues. One of them is EEH error observed on Garrison. 3277 * 3278 * Exclude top 1MB region which is the minimal alignment of 3279 * 32-bits bridge window. 3280 */ 3281 if (msi_region) { 3282 r->end += 0x10000; 3283 r->end -= 0x100000; 3284 } 3285 } 3286 } 3287 3288 static void pnv_pci_setup_bridge(struct pci_bus *bus, unsigned long type) 3289 { 3290 struct pci_controller *hose = pci_bus_to_host(bus); 3291 struct pnv_phb *phb = hose->private_data; 3292 struct pci_dev *bridge = bus->self; 3293 struct pnv_ioda_pe *pe; 3294 bool all = (pci_pcie_type(bridge) == PCI_EXP_TYPE_PCI_BRIDGE); 3295 3296 /* Extend bridge's windows if necessary */ 3297 pnv_pci_fixup_bridge_resources(bus, type); 3298 3299 /* The PE for root bus should be realized before any one else */ 3300 if (!phb->ioda.root_pe_populated) { 3301 pe = pnv_ioda_setup_bus_PE(phb->hose->bus, false); 3302 if (pe) { 3303 phb->ioda.root_pe_idx = pe->pe_number; 3304 phb->ioda.root_pe_populated = true; 3305 } 3306 } 3307 3308 /* Don't assign PE to PCI bus, which doesn't have subordinate devices */ 3309 if (list_empty(&bus->devices)) 3310 return; 3311 3312 /* Reserve PEs according to used M64 resources */ 3313 pnv_ioda_reserve_m64_pe(bus, NULL, all); 3314 3315 /* 3316 * Assign PE. We might run here because of partial hotplug. 3317 * For the case, we just pick up the existing PE and should 3318 * not allocate resources again. 3319 */ 3320 pe = pnv_ioda_setup_bus_PE(bus, all); 3321 if (!pe) 3322 return; 3323 3324 pnv_ioda_setup_pe_seg(pe); 3325 switch (phb->type) { 3326 case PNV_PHB_IODA1: 3327 pnv_pci_ioda1_setup_dma_pe(phb, pe); 3328 break; 3329 case PNV_PHB_IODA2: 3330 pnv_pci_ioda2_setup_dma_pe(phb, pe); 3331 break; 3332 default: 3333 pr_warn("%s: No DMA for PHB#%x (type %d)\n", 3334 __func__, phb->hose->global_number, phb->type); 3335 } 3336 } 3337 3338 static resource_size_t pnv_pci_default_alignment(void) 3339 { 3340 return PAGE_SIZE; 3341 } 3342 3343 #ifdef CONFIG_PCI_IOV 3344 static resource_size_t pnv_pci_iov_resource_alignment(struct pci_dev *pdev, 3345 int resno) 3346 { 3347 struct pci_controller *hose = pci_bus_to_host(pdev->bus); 3348 struct pnv_phb *phb = hose->private_data; 3349 struct pci_dn *pdn = pci_get_pdn(pdev); 3350 resource_size_t align; 3351 3352 /* 3353 * On PowerNV platform, IOV BAR is mapped by M64 BAR to enable the 3354 * SR-IOV. While from hardware perspective, the range mapped by M64 3355 * BAR should be size aligned. 3356 * 3357 * When IOV BAR is mapped with M64 BAR in Single PE mode, the extra 3358 * powernv-specific hardware restriction is gone. But if just use the 3359 * VF BAR size as the alignment, PF BAR / VF BAR may be allocated with 3360 * in one segment of M64 #15, which introduces the PE conflict between 3361 * PF and VF. Based on this, the minimum alignment of an IOV BAR is 3362 * m64_segsize. 3363 * 3364 * This function returns the total IOV BAR size if M64 BAR is in 3365 * Shared PE mode or just VF BAR size if not. 3366 * If the M64 BAR is in Single PE mode, return the VF BAR size or 3367 * M64 segment size if IOV BAR size is less. 3368 */ 3369 align = pci_iov_resource_size(pdev, resno); 3370 if (!pdn->vfs_expanded) 3371 return align; 3372 if (pdn->m64_single_mode) 3373 return max(align, (resource_size_t)phb->ioda.m64_segsize); 3374 3375 return pdn->vfs_expanded * align; 3376 } 3377 #endif /* CONFIG_PCI_IOV */ 3378 3379 /* Prevent enabling devices for which we couldn't properly 3380 * assign a PE 3381 */ 3382 static bool pnv_pci_enable_device_hook(struct pci_dev *dev) 3383 { 3384 struct pci_controller *hose = pci_bus_to_host(dev->bus); 3385 struct pnv_phb *phb = hose->private_data; 3386 struct pci_dn *pdn; 3387 3388 /* The function is probably called while the PEs have 3389 * not be created yet. For example, resource reassignment 3390 * during PCI probe period. We just skip the check if 3391 * PEs isn't ready. 3392 */ 3393 if (!phb->initialized) 3394 return true; 3395 3396 pdn = pci_get_pdn(dev); 3397 if (!pdn || pdn->pe_number == IODA_INVALID_PE) 3398 return false; 3399 3400 return true; 3401 } 3402 3403 static long pnv_pci_ioda1_unset_window(struct iommu_table_group *table_group, 3404 int num) 3405 { 3406 struct pnv_ioda_pe *pe = container_of(table_group, 3407 struct pnv_ioda_pe, table_group); 3408 struct pnv_phb *phb = pe->phb; 3409 unsigned int idx; 3410 long rc; 3411 3412 pe_info(pe, "Removing DMA window #%d\n", num); 3413 for (idx = 0; idx < phb->ioda.dma32_count; idx++) { 3414 if (phb->ioda.dma32_segmap[idx] != pe->pe_number) 3415 continue; 3416 3417 rc = opal_pci_map_pe_dma_window(phb->opal_id, pe->pe_number, 3418 idx, 0, 0ul, 0ul, 0ul); 3419 if (rc != OPAL_SUCCESS) { 3420 pe_warn(pe, "Failure %ld unmapping DMA32 segment#%d\n", 3421 rc, idx); 3422 return rc; 3423 } 3424 3425 phb->ioda.dma32_segmap[idx] = IODA_INVALID_PE; 3426 } 3427 3428 pnv_pci_unlink_table_and_group(table_group->tables[num], table_group); 3429 return OPAL_SUCCESS; 3430 } 3431 3432 static void pnv_pci_ioda1_release_pe_dma(struct pnv_ioda_pe *pe) 3433 { 3434 unsigned int weight = pnv_pci_ioda_pe_dma_weight(pe); 3435 struct iommu_table *tbl = pe->table_group.tables[0]; 3436 int64_t rc; 3437 3438 if (!weight) 3439 return; 3440 3441 rc = pnv_pci_ioda1_unset_window(&pe->table_group, 0); 3442 if (rc != OPAL_SUCCESS) 3443 return; 3444 3445 pnv_pci_p7ioc_tce_invalidate(tbl, tbl->it_offset, tbl->it_size, false); 3446 if (pe->table_group.group) { 3447 iommu_group_put(pe->table_group.group); 3448 WARN_ON(pe->table_group.group); 3449 } 3450 3451 free_pages(tbl->it_base, get_order(tbl->it_size << 3)); 3452 iommu_tce_table_put(tbl); 3453 } 3454 3455 static void pnv_pci_ioda2_release_pe_dma(struct pnv_ioda_pe *pe) 3456 { 3457 struct iommu_table *tbl = pe->table_group.tables[0]; 3458 unsigned int weight = pnv_pci_ioda_pe_dma_weight(pe); 3459 #ifdef CONFIG_IOMMU_API 3460 int64_t rc; 3461 #endif 3462 3463 if (!weight) 3464 return; 3465 3466 #ifdef CONFIG_IOMMU_API 3467 rc = pnv_pci_ioda2_unset_window(&pe->table_group, 0); 3468 if (rc) 3469 pe_warn(pe, "OPAL error %lld release DMA window\n", rc); 3470 #endif 3471 3472 pnv_pci_ioda2_set_bypass(pe, false); 3473 if (pe->table_group.group) { 3474 iommu_group_put(pe->table_group.group); 3475 WARN_ON(pe->table_group.group); 3476 } 3477 3478 iommu_tce_table_put(tbl); 3479 } 3480 3481 static void pnv_ioda_free_pe_seg(struct pnv_ioda_pe *pe, 3482 unsigned short win, 3483 unsigned int *map) 3484 { 3485 struct pnv_phb *phb = pe->phb; 3486 int idx; 3487 int64_t rc; 3488 3489 for (idx = 0; idx < phb->ioda.total_pe_num; idx++) { 3490 if (map[idx] != pe->pe_number) 3491 continue; 3492 3493 if (win == OPAL_M64_WINDOW_TYPE) 3494 rc = opal_pci_map_pe_mmio_window(phb->opal_id, 3495 phb->ioda.reserved_pe_idx, win, 3496 idx / PNV_IODA1_M64_SEGS, 3497 idx % PNV_IODA1_M64_SEGS); 3498 else 3499 rc = opal_pci_map_pe_mmio_window(phb->opal_id, 3500 phb->ioda.reserved_pe_idx, win, 0, idx); 3501 3502 if (rc != OPAL_SUCCESS) 3503 pe_warn(pe, "Error %lld unmapping (%d) segment#%d\n", 3504 rc, win, idx); 3505 3506 map[idx] = IODA_INVALID_PE; 3507 } 3508 } 3509 3510 static void pnv_ioda_release_pe_seg(struct pnv_ioda_pe *pe) 3511 { 3512 struct pnv_phb *phb = pe->phb; 3513 3514 if (phb->type == PNV_PHB_IODA1) { 3515 pnv_ioda_free_pe_seg(pe, OPAL_IO_WINDOW_TYPE, 3516 phb->ioda.io_segmap); 3517 pnv_ioda_free_pe_seg(pe, OPAL_M32_WINDOW_TYPE, 3518 phb->ioda.m32_segmap); 3519 pnv_ioda_free_pe_seg(pe, OPAL_M64_WINDOW_TYPE, 3520 phb->ioda.m64_segmap); 3521 } else if (phb->type == PNV_PHB_IODA2) { 3522 pnv_ioda_free_pe_seg(pe, OPAL_M32_WINDOW_TYPE, 3523 phb->ioda.m32_segmap); 3524 } 3525 } 3526 3527 static void pnv_ioda_release_pe(struct pnv_ioda_pe *pe) 3528 { 3529 struct pnv_phb *phb = pe->phb; 3530 struct pnv_ioda_pe *slave, *tmp; 3531 3532 mutex_lock(&phb->ioda.pe_list_mutex); 3533 list_del(&pe->list); 3534 mutex_unlock(&phb->ioda.pe_list_mutex); 3535 3536 switch (phb->type) { 3537 case PNV_PHB_IODA1: 3538 pnv_pci_ioda1_release_pe_dma(pe); 3539 break; 3540 case PNV_PHB_IODA2: 3541 pnv_pci_ioda2_release_pe_dma(pe); 3542 break; 3543 default: 3544 WARN_ON(1); 3545 } 3546 3547 pnv_ioda_release_pe_seg(pe); 3548 pnv_ioda_deconfigure_pe(pe->phb, pe); 3549 3550 /* Release slave PEs in the compound PE */ 3551 if (pe->flags & PNV_IODA_PE_MASTER) { 3552 list_for_each_entry_safe(slave, tmp, &pe->slaves, list) { 3553 list_del(&slave->list); 3554 pnv_ioda_free_pe(slave); 3555 } 3556 } 3557 3558 /* 3559 * The PE for root bus can be removed because of hotplug in EEH 3560 * recovery for fenced PHB error. We need to mark the PE dead so 3561 * that it can be populated again in PCI hot add path. The PE 3562 * shouldn't be destroyed as it's the global reserved resource. 3563 */ 3564 if (phb->ioda.root_pe_populated && 3565 phb->ioda.root_pe_idx == pe->pe_number) 3566 phb->ioda.root_pe_populated = false; 3567 else 3568 pnv_ioda_free_pe(pe); 3569 } 3570 3571 static void pnv_pci_release_device(struct pci_dev *pdev) 3572 { 3573 struct pci_controller *hose = pci_bus_to_host(pdev->bus); 3574 struct pnv_phb *phb = hose->private_data; 3575 struct pci_dn *pdn = pci_get_pdn(pdev); 3576 struct pnv_ioda_pe *pe; 3577 3578 if (pdev->is_virtfn) 3579 return; 3580 3581 if (!pdn || pdn->pe_number == IODA_INVALID_PE) 3582 return; 3583 3584 /* 3585 * PCI hotplug can happen as part of EEH error recovery. The @pdn 3586 * isn't removed and added afterwards in this scenario. We should 3587 * set the PE number in @pdn to an invalid one. Otherwise, the PE's 3588 * device count is decreased on removing devices while failing to 3589 * be increased on adding devices. It leads to unbalanced PE's device 3590 * count and eventually make normal PCI hotplug path broken. 3591 */ 3592 pe = &phb->ioda.pe_array[pdn->pe_number]; 3593 pdn->pe_number = IODA_INVALID_PE; 3594 3595 WARN_ON(--pe->device_count < 0); 3596 if (pe->device_count == 0) 3597 pnv_ioda_release_pe(pe); 3598 } 3599 3600 static void pnv_npu_disable_device(struct pci_dev *pdev) 3601 { 3602 struct eeh_dev *edev = pci_dev_to_eeh_dev(pdev); 3603 struct eeh_pe *eehpe = edev ? edev->pe : NULL; 3604 3605 if (eehpe && eeh_ops && eeh_ops->reset) 3606 eeh_ops->reset(eehpe, EEH_RESET_HOT); 3607 } 3608 3609 static void pnv_pci_ioda_shutdown(struct pci_controller *hose) 3610 { 3611 struct pnv_phb *phb = hose->private_data; 3612 3613 opal_pci_reset(phb->opal_id, OPAL_RESET_PCI_IODA_TABLE, 3614 OPAL_ASSERT_RESET); 3615 } 3616 3617 static const struct pci_controller_ops pnv_pci_ioda_controller_ops = { 3618 .dma_dev_setup = pnv_pci_dma_dev_setup, 3619 .dma_bus_setup = pnv_pci_dma_bus_setup, 3620 .iommu_bypass_supported = pnv_pci_ioda_iommu_bypass_supported, 3621 .setup_msi_irqs = pnv_setup_msi_irqs, 3622 .teardown_msi_irqs = pnv_teardown_msi_irqs, 3623 .enable_device_hook = pnv_pci_enable_device_hook, 3624 .release_device = pnv_pci_release_device, 3625 .window_alignment = pnv_pci_window_alignment, 3626 .setup_bridge = pnv_pci_setup_bridge, 3627 .reset_secondary_bus = pnv_pci_reset_secondary_bus, 3628 .shutdown = pnv_pci_ioda_shutdown, 3629 }; 3630 3631 static const struct pci_controller_ops pnv_npu_ioda_controller_ops = { 3632 .dma_dev_setup = pnv_pci_dma_dev_setup, 3633 .setup_msi_irqs = pnv_setup_msi_irqs, 3634 .teardown_msi_irqs = pnv_teardown_msi_irqs, 3635 .enable_device_hook = pnv_pci_enable_device_hook, 3636 .window_alignment = pnv_pci_window_alignment, 3637 .reset_secondary_bus = pnv_pci_reset_secondary_bus, 3638 .shutdown = pnv_pci_ioda_shutdown, 3639 .disable_device = pnv_npu_disable_device, 3640 }; 3641 3642 static const struct pci_controller_ops pnv_npu_ocapi_ioda_controller_ops = { 3643 .enable_device_hook = pnv_pci_enable_device_hook, 3644 .window_alignment = pnv_pci_window_alignment, 3645 .reset_secondary_bus = pnv_pci_reset_secondary_bus, 3646 .shutdown = pnv_pci_ioda_shutdown, 3647 }; 3648 3649 static void __init pnv_pci_init_ioda_phb(struct device_node *np, 3650 u64 hub_id, int ioda_type) 3651 { 3652 struct pci_controller *hose; 3653 struct pnv_phb *phb; 3654 unsigned long size, m64map_off, m32map_off, pemap_off; 3655 unsigned long iomap_off = 0, dma32map_off = 0; 3656 struct resource r; 3657 const __be64 *prop64; 3658 const __be32 *prop32; 3659 int len; 3660 unsigned int segno; 3661 u64 phb_id; 3662 void *aux; 3663 long rc; 3664 3665 if (!of_device_is_available(np)) 3666 return; 3667 3668 pr_info("Initializing %s PHB (%pOF)\n", pnv_phb_names[ioda_type], np); 3669 3670 prop64 = of_get_property(np, "ibm,opal-phbid", NULL); 3671 if (!prop64) { 3672 pr_err(" Missing \"ibm,opal-phbid\" property !\n"); 3673 return; 3674 } 3675 phb_id = be64_to_cpup(prop64); 3676 pr_debug(" PHB-ID : 0x%016llx\n", phb_id); 3677 3678 phb = memblock_alloc(sizeof(*phb), SMP_CACHE_BYTES); 3679 if (!phb) 3680 panic("%s: Failed to allocate %zu bytes\n", __func__, 3681 sizeof(*phb)); 3682 3683 /* Allocate PCI controller */ 3684 phb->hose = hose = pcibios_alloc_controller(np); 3685 if (!phb->hose) { 3686 pr_err(" Can't allocate PCI controller for %pOF\n", 3687 np); 3688 memblock_free(__pa(phb), sizeof(struct pnv_phb)); 3689 return; 3690 } 3691 3692 spin_lock_init(&phb->lock); 3693 prop32 = of_get_property(np, "bus-range", &len); 3694 if (prop32 && len == 8) { 3695 hose->first_busno = be32_to_cpu(prop32[0]); 3696 hose->last_busno = be32_to_cpu(prop32[1]); 3697 } else { 3698 pr_warn(" Broken <bus-range> on %pOF\n", np); 3699 hose->first_busno = 0; 3700 hose->last_busno = 0xff; 3701 } 3702 hose->private_data = phb; 3703 phb->hub_id = hub_id; 3704 phb->opal_id = phb_id; 3705 phb->type = ioda_type; 3706 mutex_init(&phb->ioda.pe_alloc_mutex); 3707 3708 /* Detect specific models for error handling */ 3709 if (of_device_is_compatible(np, "ibm,p7ioc-pciex")) 3710 phb->model = PNV_PHB_MODEL_P7IOC; 3711 else if (of_device_is_compatible(np, "ibm,power8-pciex")) 3712 phb->model = PNV_PHB_MODEL_PHB3; 3713 else if (of_device_is_compatible(np, "ibm,power8-npu-pciex")) 3714 phb->model = PNV_PHB_MODEL_NPU; 3715 else if (of_device_is_compatible(np, "ibm,power9-npu-pciex")) 3716 phb->model = PNV_PHB_MODEL_NPU2; 3717 else 3718 phb->model = PNV_PHB_MODEL_UNKNOWN; 3719 3720 /* Initialize diagnostic data buffer */ 3721 prop32 = of_get_property(np, "ibm,phb-diag-data-size", NULL); 3722 if (prop32) 3723 phb->diag_data_size = be32_to_cpup(prop32); 3724 else 3725 phb->diag_data_size = PNV_PCI_DIAG_BUF_SIZE; 3726 3727 phb->diag_data = memblock_alloc(phb->diag_data_size, SMP_CACHE_BYTES); 3728 if (!phb->diag_data) 3729 panic("%s: Failed to allocate %u bytes\n", __func__, 3730 phb->diag_data_size); 3731 3732 /* Parse 32-bit and IO ranges (if any) */ 3733 pci_process_bridge_OF_ranges(hose, np, !hose->global_number); 3734 3735 /* Get registers */ 3736 if (!of_address_to_resource(np, 0, &r)) { 3737 phb->regs_phys = r.start; 3738 phb->regs = ioremap(r.start, resource_size(&r)); 3739 if (phb->regs == NULL) 3740 pr_err(" Failed to map registers !\n"); 3741 } 3742 3743 /* Initialize more IODA stuff */ 3744 phb->ioda.total_pe_num = 1; 3745 prop32 = of_get_property(np, "ibm,opal-num-pes", NULL); 3746 if (prop32) 3747 phb->ioda.total_pe_num = be32_to_cpup(prop32); 3748 prop32 = of_get_property(np, "ibm,opal-reserved-pe", NULL); 3749 if (prop32) 3750 phb->ioda.reserved_pe_idx = be32_to_cpup(prop32); 3751 3752 /* Invalidate RID to PE# mapping */ 3753 for (segno = 0; segno < ARRAY_SIZE(phb->ioda.pe_rmap); segno++) 3754 phb->ioda.pe_rmap[segno] = IODA_INVALID_PE; 3755 3756 /* Parse 64-bit MMIO range */ 3757 pnv_ioda_parse_m64_window(phb); 3758 3759 phb->ioda.m32_size = resource_size(&hose->mem_resources[0]); 3760 /* FW Has already off top 64k of M32 space (MSI space) */ 3761 phb->ioda.m32_size += 0x10000; 3762 3763 phb->ioda.m32_segsize = phb->ioda.m32_size / phb->ioda.total_pe_num; 3764 phb->ioda.m32_pci_base = hose->mem_resources[0].start - hose->mem_offset[0]; 3765 phb->ioda.io_size = hose->pci_io_size; 3766 phb->ioda.io_segsize = phb->ioda.io_size / phb->ioda.total_pe_num; 3767 phb->ioda.io_pci_base = 0; /* XXX calculate this ? */ 3768 3769 /* Calculate how many 32-bit TCE segments we have */ 3770 phb->ioda.dma32_count = phb->ioda.m32_pci_base / 3771 PNV_IODA1_DMA32_SEGSIZE; 3772 3773 /* Allocate aux data & arrays. We don't have IO ports on PHB3 */ 3774 size = _ALIGN_UP(max_t(unsigned, phb->ioda.total_pe_num, 8) / 8, 3775 sizeof(unsigned long)); 3776 m64map_off = size; 3777 size += phb->ioda.total_pe_num * sizeof(phb->ioda.m64_segmap[0]); 3778 m32map_off = size; 3779 size += phb->ioda.total_pe_num * sizeof(phb->ioda.m32_segmap[0]); 3780 if (phb->type == PNV_PHB_IODA1) { 3781 iomap_off = size; 3782 size += phb->ioda.total_pe_num * sizeof(phb->ioda.io_segmap[0]); 3783 dma32map_off = size; 3784 size += phb->ioda.dma32_count * 3785 sizeof(phb->ioda.dma32_segmap[0]); 3786 } 3787 pemap_off = size; 3788 size += phb->ioda.total_pe_num * sizeof(struct pnv_ioda_pe); 3789 aux = memblock_alloc(size, SMP_CACHE_BYTES); 3790 if (!aux) 3791 panic("%s: Failed to allocate %lu bytes\n", __func__, size); 3792 phb->ioda.pe_alloc = aux; 3793 phb->ioda.m64_segmap = aux + m64map_off; 3794 phb->ioda.m32_segmap = aux + m32map_off; 3795 for (segno = 0; segno < phb->ioda.total_pe_num; segno++) { 3796 phb->ioda.m64_segmap[segno] = IODA_INVALID_PE; 3797 phb->ioda.m32_segmap[segno] = IODA_INVALID_PE; 3798 } 3799 if (phb->type == PNV_PHB_IODA1) { 3800 phb->ioda.io_segmap = aux + iomap_off; 3801 for (segno = 0; segno < phb->ioda.total_pe_num; segno++) 3802 phb->ioda.io_segmap[segno] = IODA_INVALID_PE; 3803 3804 phb->ioda.dma32_segmap = aux + dma32map_off; 3805 for (segno = 0; segno < phb->ioda.dma32_count; segno++) 3806 phb->ioda.dma32_segmap[segno] = IODA_INVALID_PE; 3807 } 3808 phb->ioda.pe_array = aux + pemap_off; 3809 3810 /* 3811 * Choose PE number for root bus, which shouldn't have 3812 * M64 resources consumed by its child devices. To pick 3813 * the PE number adjacent to the reserved one if possible. 3814 */ 3815 pnv_ioda_reserve_pe(phb, phb->ioda.reserved_pe_idx); 3816 if (phb->ioda.reserved_pe_idx == 0) { 3817 phb->ioda.root_pe_idx = 1; 3818 pnv_ioda_reserve_pe(phb, phb->ioda.root_pe_idx); 3819 } else if (phb->ioda.reserved_pe_idx == (phb->ioda.total_pe_num - 1)) { 3820 phb->ioda.root_pe_idx = phb->ioda.reserved_pe_idx - 1; 3821 pnv_ioda_reserve_pe(phb, phb->ioda.root_pe_idx); 3822 } else { 3823 phb->ioda.root_pe_idx = IODA_INVALID_PE; 3824 } 3825 3826 INIT_LIST_HEAD(&phb->ioda.pe_list); 3827 mutex_init(&phb->ioda.pe_list_mutex); 3828 3829 /* Calculate how many 32-bit TCE segments we have */ 3830 phb->ioda.dma32_count = phb->ioda.m32_pci_base / 3831 PNV_IODA1_DMA32_SEGSIZE; 3832 3833 #if 0 /* We should really do that ... */ 3834 rc = opal_pci_set_phb_mem_window(opal->phb_id, 3835 window_type, 3836 window_num, 3837 starting_real_address, 3838 starting_pci_address, 3839 segment_size); 3840 #endif 3841 3842 pr_info(" %03d (%03d) PE's M32: 0x%x [segment=0x%x]\n", 3843 phb->ioda.total_pe_num, phb->ioda.reserved_pe_idx, 3844 phb->ioda.m32_size, phb->ioda.m32_segsize); 3845 if (phb->ioda.m64_size) 3846 pr_info(" M64: 0x%lx [segment=0x%lx]\n", 3847 phb->ioda.m64_size, phb->ioda.m64_segsize); 3848 if (phb->ioda.io_size) 3849 pr_info(" IO: 0x%x [segment=0x%x]\n", 3850 phb->ioda.io_size, phb->ioda.io_segsize); 3851 3852 3853 phb->hose->ops = &pnv_pci_ops; 3854 phb->get_pe_state = pnv_ioda_get_pe_state; 3855 phb->freeze_pe = pnv_ioda_freeze_pe; 3856 phb->unfreeze_pe = pnv_ioda_unfreeze_pe; 3857 3858 /* Setup MSI support */ 3859 pnv_pci_init_ioda_msis(phb); 3860 3861 /* 3862 * We pass the PCI probe flag PCI_REASSIGN_ALL_RSRC here 3863 * to let the PCI core do resource assignment. It's supposed 3864 * that the PCI core will do correct I/O and MMIO alignment 3865 * for the P2P bridge bars so that each PCI bus (excluding 3866 * the child P2P bridges) can form individual PE. 3867 */ 3868 ppc_md.pcibios_fixup = pnv_pci_ioda_fixup; 3869 3870 switch (phb->type) { 3871 case PNV_PHB_NPU_NVLINK: 3872 hose->controller_ops = pnv_npu_ioda_controller_ops; 3873 break; 3874 case PNV_PHB_NPU_OCAPI: 3875 hose->controller_ops = pnv_npu_ocapi_ioda_controller_ops; 3876 break; 3877 default: 3878 phb->dma_dev_setup = pnv_pci_ioda_dma_dev_setup; 3879 hose->controller_ops = pnv_pci_ioda_controller_ops; 3880 } 3881 3882 ppc_md.pcibios_default_alignment = pnv_pci_default_alignment; 3883 3884 #ifdef CONFIG_PCI_IOV 3885 ppc_md.pcibios_fixup_sriov = pnv_pci_ioda_fixup_iov_resources; 3886 ppc_md.pcibios_iov_resource_alignment = pnv_pci_iov_resource_alignment; 3887 ppc_md.pcibios_sriov_enable = pnv_pcibios_sriov_enable; 3888 ppc_md.pcibios_sriov_disable = pnv_pcibios_sriov_disable; 3889 #endif 3890 3891 pci_add_flags(PCI_REASSIGN_ALL_RSRC); 3892 3893 /* Reset IODA tables to a clean state */ 3894 rc = opal_pci_reset(phb_id, OPAL_RESET_PCI_IODA_TABLE, OPAL_ASSERT_RESET); 3895 if (rc) 3896 pr_warn(" OPAL Error %ld performing IODA table reset !\n", rc); 3897 3898 /* 3899 * If we're running in kdump kernel, the previous kernel never 3900 * shutdown PCI devices correctly. We already got IODA table 3901 * cleaned out. So we have to issue PHB reset to stop all PCI 3902 * transactions from previous kernel. The ppc_pci_reset_phbs 3903 * kernel parameter will force this reset too. Additionally, 3904 * if the IODA reset above failed then use a bigger hammer. 3905 * This can happen if we get a PHB fatal error in very early 3906 * boot. 3907 */ 3908 if (is_kdump_kernel() || pci_reset_phbs || rc) { 3909 pr_info(" Issue PHB reset ...\n"); 3910 pnv_eeh_phb_reset(hose, EEH_RESET_FUNDAMENTAL); 3911 pnv_eeh_phb_reset(hose, EEH_RESET_DEACTIVATE); 3912 } 3913 3914 /* Remove M64 resource if we can't configure it successfully */ 3915 if (!phb->init_m64 || phb->init_m64(phb)) 3916 hose->mem_resources[1].flags = 0; 3917 } 3918 3919 void __init pnv_pci_init_ioda2_phb(struct device_node *np) 3920 { 3921 pnv_pci_init_ioda_phb(np, 0, PNV_PHB_IODA2); 3922 } 3923 3924 void __init pnv_pci_init_npu_phb(struct device_node *np) 3925 { 3926 pnv_pci_init_ioda_phb(np, 0, PNV_PHB_NPU_NVLINK); 3927 } 3928 3929 void __init pnv_pci_init_npu2_opencapi_phb(struct device_node *np) 3930 { 3931 pnv_pci_init_ioda_phb(np, 0, PNV_PHB_NPU_OCAPI); 3932 } 3933 3934 static void pnv_npu2_opencapi_cfg_size_fixup(struct pci_dev *dev) 3935 { 3936 struct pci_controller *hose = pci_bus_to_host(dev->bus); 3937 struct pnv_phb *phb = hose->private_data; 3938 3939 if (!machine_is(powernv)) 3940 return; 3941 3942 if (phb->type == PNV_PHB_NPU_OCAPI) 3943 dev->cfg_size = PCI_CFG_SPACE_EXP_SIZE; 3944 } 3945 DECLARE_PCI_FIXUP_EARLY(PCI_ANY_ID, PCI_ANY_ID, pnv_npu2_opencapi_cfg_size_fixup); 3946 3947 void __init pnv_pci_init_ioda_hub(struct device_node *np) 3948 { 3949 struct device_node *phbn; 3950 const __be64 *prop64; 3951 u64 hub_id; 3952 3953 pr_info("Probing IODA IO-Hub %pOF\n", np); 3954 3955 prop64 = of_get_property(np, "ibm,opal-hubid", NULL); 3956 if (!prop64) { 3957 pr_err(" Missing \"ibm,opal-hubid\" property !\n"); 3958 return; 3959 } 3960 hub_id = be64_to_cpup(prop64); 3961 pr_devel(" HUB-ID : 0x%016llx\n", hub_id); 3962 3963 /* Count child PHBs */ 3964 for_each_child_of_node(np, phbn) { 3965 /* Look for IODA1 PHBs */ 3966 if (of_device_is_compatible(phbn, "ibm,ioda-phb")) 3967 pnv_pci_init_ioda_phb(phbn, hub_id, PNV_PHB_IODA1); 3968 } 3969 } 3970