1 /*
2  * Support PCI/PCIe on PowerNV platforms
3  *
4  * Copyright 2011 Benjamin Herrenschmidt, IBM Corp.
5  *
6  * This program is free software; you can redistribute it and/or
7  * modify it under the terms of the GNU General Public License
8  * as published by the Free Software Foundation; either version
9  * 2 of the License, or (at your option) any later version.
10  */
11 
12 #undef DEBUG
13 
14 #include <linux/kernel.h>
15 #include <linux/pci.h>
16 #include <linux/crash_dump.h>
17 #include <linux/debugfs.h>
18 #include <linux/delay.h>
19 #include <linux/string.h>
20 #include <linux/init.h>
21 #include <linux/bootmem.h>
22 #include <linux/irq.h>
23 #include <linux/io.h>
24 #include <linux/msi.h>
25 #include <linux/memblock.h>
26 #include <linux/iommu.h>
27 #include <linux/rculist.h>
28 #include <linux/sizes.h>
29 
30 #include <asm/sections.h>
31 #include <asm/io.h>
32 #include <asm/prom.h>
33 #include <asm/pci-bridge.h>
34 #include <asm/machdep.h>
35 #include <asm/msi_bitmap.h>
36 #include <asm/ppc-pci.h>
37 #include <asm/opal.h>
38 #include <asm/iommu.h>
39 #include <asm/tce.h>
40 #include <asm/xics.h>
41 #include <asm/debug.h>
42 #include <asm/firmware.h>
43 #include <asm/pnv-pci.h>
44 #include <asm/mmzone.h>
45 
46 #include <misc/cxl-base.h>
47 
48 #include "powernv.h"
49 #include "pci.h"
50 
51 /* 256M DMA window, 4K TCE pages, 8 bytes TCE */
52 #define TCE32_TABLE_SIZE	((0x10000000 / 0x1000) * 8)
53 
54 #define POWERNV_IOMMU_DEFAULT_LEVELS	1
55 #define POWERNV_IOMMU_MAX_LEVELS	5
56 
57 static void pnv_pci_ioda2_table_free_pages(struct iommu_table *tbl);
58 
59 static void pe_level_printk(const struct pnv_ioda_pe *pe, const char *level,
60 			    const char *fmt, ...)
61 {
62 	struct va_format vaf;
63 	va_list args;
64 	char pfix[32];
65 
66 	va_start(args, fmt);
67 
68 	vaf.fmt = fmt;
69 	vaf.va = &args;
70 
71 	if (pe->flags & PNV_IODA_PE_DEV)
72 		strlcpy(pfix, dev_name(&pe->pdev->dev), sizeof(pfix));
73 	else if (pe->flags & (PNV_IODA_PE_BUS | PNV_IODA_PE_BUS_ALL))
74 		sprintf(pfix, "%04x:%02x     ",
75 			pci_domain_nr(pe->pbus), pe->pbus->number);
76 #ifdef CONFIG_PCI_IOV
77 	else if (pe->flags & PNV_IODA_PE_VF)
78 		sprintf(pfix, "%04x:%02x:%2x.%d",
79 			pci_domain_nr(pe->parent_dev->bus),
80 			(pe->rid & 0xff00) >> 8,
81 			PCI_SLOT(pe->rid), PCI_FUNC(pe->rid));
82 #endif /* CONFIG_PCI_IOV*/
83 
84 	printk("%spci %s: [PE# %.3d] %pV",
85 	       level, pfix, pe->pe_number, &vaf);
86 
87 	va_end(args);
88 }
89 
90 #define pe_err(pe, fmt, ...)					\
91 	pe_level_printk(pe, KERN_ERR, fmt, ##__VA_ARGS__)
92 #define pe_warn(pe, fmt, ...)					\
93 	pe_level_printk(pe, KERN_WARNING, fmt, ##__VA_ARGS__)
94 #define pe_info(pe, fmt, ...)					\
95 	pe_level_printk(pe, KERN_INFO, fmt, ##__VA_ARGS__)
96 
97 static bool pnv_iommu_bypass_disabled __read_mostly;
98 
99 static int __init iommu_setup(char *str)
100 {
101 	if (!str)
102 		return -EINVAL;
103 
104 	while (*str) {
105 		if (!strncmp(str, "nobypass", 8)) {
106 			pnv_iommu_bypass_disabled = true;
107 			pr_info("PowerNV: IOMMU bypass window disabled.\n");
108 			break;
109 		}
110 		str += strcspn(str, ",");
111 		if (*str == ',')
112 			str++;
113 	}
114 
115 	return 0;
116 }
117 early_param("iommu", iommu_setup);
118 
119 static inline bool pnv_pci_is_mem_pref_64(unsigned long flags)
120 {
121 	return ((flags & (IORESOURCE_MEM_64 | IORESOURCE_PREFETCH)) ==
122 		(IORESOURCE_MEM_64 | IORESOURCE_PREFETCH));
123 }
124 
125 static void pnv_ioda_reserve_pe(struct pnv_phb *phb, int pe_no)
126 {
127 	if (!(pe_no >= 0 && pe_no < phb->ioda.total_pe)) {
128 		pr_warn("%s: Invalid PE %d on PHB#%x\n",
129 			__func__, pe_no, phb->hose->global_number);
130 		return;
131 	}
132 
133 	if (test_and_set_bit(pe_no, phb->ioda.pe_alloc))
134 		pr_debug("%s: PE %d was reserved on PHB#%x\n",
135 			 __func__, pe_no, phb->hose->global_number);
136 
137 	phb->ioda.pe_array[pe_no].phb = phb;
138 	phb->ioda.pe_array[pe_no].pe_number = pe_no;
139 }
140 
141 static int pnv_ioda_alloc_pe(struct pnv_phb *phb)
142 {
143 	unsigned long pe;
144 
145 	do {
146 		pe = find_next_zero_bit(phb->ioda.pe_alloc,
147 					phb->ioda.total_pe, 0);
148 		if (pe >= phb->ioda.total_pe)
149 			return IODA_INVALID_PE;
150 	} while(test_and_set_bit(pe, phb->ioda.pe_alloc));
151 
152 	phb->ioda.pe_array[pe].phb = phb;
153 	phb->ioda.pe_array[pe].pe_number = pe;
154 	return pe;
155 }
156 
157 static void pnv_ioda_free_pe(struct pnv_phb *phb, int pe)
158 {
159 	WARN_ON(phb->ioda.pe_array[pe].pdev);
160 
161 	memset(&phb->ioda.pe_array[pe], 0, sizeof(struct pnv_ioda_pe));
162 	clear_bit(pe, phb->ioda.pe_alloc);
163 }
164 
165 /* The default M64 BAR is shared by all PEs */
166 static int pnv_ioda2_init_m64(struct pnv_phb *phb)
167 {
168 	const char *desc;
169 	struct resource *r;
170 	s64 rc;
171 
172 	/* Configure the default M64 BAR */
173 	rc = opal_pci_set_phb_mem_window(phb->opal_id,
174 					 OPAL_M64_WINDOW_TYPE,
175 					 phb->ioda.m64_bar_idx,
176 					 phb->ioda.m64_base,
177 					 0, /* unused */
178 					 phb->ioda.m64_size);
179 	if (rc != OPAL_SUCCESS) {
180 		desc = "configuring";
181 		goto fail;
182 	}
183 
184 	/* Enable the default M64 BAR */
185 	rc = opal_pci_phb_mmio_enable(phb->opal_id,
186 				      OPAL_M64_WINDOW_TYPE,
187 				      phb->ioda.m64_bar_idx,
188 				      OPAL_ENABLE_M64_SPLIT);
189 	if (rc != OPAL_SUCCESS) {
190 		desc = "enabling";
191 		goto fail;
192 	}
193 
194 	/* Mark the M64 BAR assigned */
195 	set_bit(phb->ioda.m64_bar_idx, &phb->ioda.m64_bar_alloc);
196 
197 	/*
198 	 * Strip off the segment used by the reserved PE, which is
199 	 * expected to be 0 or last one of PE capabicity.
200 	 */
201 	r = &phb->hose->mem_resources[1];
202 	if (phb->ioda.reserved_pe == 0)
203 		r->start += phb->ioda.m64_segsize;
204 	else if (phb->ioda.reserved_pe == (phb->ioda.total_pe - 1))
205 		r->end -= phb->ioda.m64_segsize;
206 	else
207 		pr_warn("  Cannot strip M64 segment for reserved PE#%d\n",
208 			phb->ioda.reserved_pe);
209 
210 	return 0;
211 
212 fail:
213 	pr_warn("  Failure %lld %s M64 BAR#%d\n",
214 		rc, desc, phb->ioda.m64_bar_idx);
215 	opal_pci_phb_mmio_enable(phb->opal_id,
216 				 OPAL_M64_WINDOW_TYPE,
217 				 phb->ioda.m64_bar_idx,
218 				 OPAL_DISABLE_M64);
219 	return -EIO;
220 }
221 
222 static void pnv_ioda2_reserve_dev_m64_pe(struct pci_dev *pdev,
223 					 unsigned long *pe_bitmap)
224 {
225 	struct pci_controller *hose = pci_bus_to_host(pdev->bus);
226 	struct pnv_phb *phb = hose->private_data;
227 	struct resource *r;
228 	resource_size_t base, sgsz, start, end;
229 	int segno, i;
230 
231 	base = phb->ioda.m64_base;
232 	sgsz = phb->ioda.m64_segsize;
233 	for (i = 0; i <= PCI_ROM_RESOURCE; i++) {
234 		r = &pdev->resource[i];
235 		if (!r->parent || !pnv_pci_is_mem_pref_64(r->flags))
236 			continue;
237 
238 		start = _ALIGN_DOWN(r->start - base, sgsz);
239 		end = _ALIGN_UP(r->end - base, sgsz);
240 		for (segno = start / sgsz; segno < end / sgsz; segno++) {
241 			if (pe_bitmap)
242 				set_bit(segno, pe_bitmap);
243 			else
244 				pnv_ioda_reserve_pe(phb, segno);
245 		}
246 	}
247 }
248 
249 static void pnv_ioda2_reserve_m64_pe(struct pci_bus *bus,
250 				     unsigned long *pe_bitmap,
251 				     bool all)
252 {
253 	struct pci_dev *pdev;
254 
255 	list_for_each_entry(pdev, &bus->devices, bus_list) {
256 		pnv_ioda2_reserve_dev_m64_pe(pdev, pe_bitmap);
257 
258 		if (all && pdev->subordinate)
259 			pnv_ioda2_reserve_m64_pe(pdev->subordinate,
260 						 pe_bitmap, all);
261 	}
262 }
263 
264 static int pnv_ioda2_pick_m64_pe(struct pci_bus *bus, bool all)
265 {
266 	struct pci_controller *hose = pci_bus_to_host(bus);
267 	struct pnv_phb *phb = hose->private_data;
268 	struct pnv_ioda_pe *master_pe, *pe;
269 	unsigned long size, *pe_alloc;
270 	int i;
271 
272 	/* Root bus shouldn't use M64 */
273 	if (pci_is_root_bus(bus))
274 		return IODA_INVALID_PE;
275 
276 	/* Allocate bitmap */
277 	size = _ALIGN_UP(phb->ioda.total_pe / 8, sizeof(unsigned long));
278 	pe_alloc = kzalloc(size, GFP_KERNEL);
279 	if (!pe_alloc) {
280 		pr_warn("%s: Out of memory !\n",
281 			__func__);
282 		return IODA_INVALID_PE;
283 	}
284 
285 	/* Figure out reserved PE numbers by the PE */
286 	pnv_ioda2_reserve_m64_pe(bus, pe_alloc, all);
287 
288 	/*
289 	 * the current bus might not own M64 window and that's all
290 	 * contributed by its child buses. For the case, we needn't
291 	 * pick M64 dependent PE#.
292 	 */
293 	if (bitmap_empty(pe_alloc, phb->ioda.total_pe)) {
294 		kfree(pe_alloc);
295 		return IODA_INVALID_PE;
296 	}
297 
298 	/*
299 	 * Figure out the master PE and put all slave PEs to master
300 	 * PE's list to form compound PE.
301 	 */
302 	master_pe = NULL;
303 	i = -1;
304 	while ((i = find_next_bit(pe_alloc, phb->ioda.total_pe, i + 1)) <
305 		phb->ioda.total_pe) {
306 		pe = &phb->ioda.pe_array[i];
307 
308 		if (!master_pe) {
309 			pe->flags |= PNV_IODA_PE_MASTER;
310 			INIT_LIST_HEAD(&pe->slaves);
311 			master_pe = pe;
312 		} else {
313 			pe->flags |= PNV_IODA_PE_SLAVE;
314 			pe->master = master_pe;
315 			list_add_tail(&pe->list, &master_pe->slaves);
316 		}
317 	}
318 
319 	kfree(pe_alloc);
320 	return master_pe->pe_number;
321 }
322 
323 static void __init pnv_ioda_parse_m64_window(struct pnv_phb *phb)
324 {
325 	struct pci_controller *hose = phb->hose;
326 	struct device_node *dn = hose->dn;
327 	struct resource *res;
328 	const u32 *r;
329 	u64 pci_addr;
330 
331 	/* FIXME: Support M64 for P7IOC */
332 	if (phb->type != PNV_PHB_IODA2) {
333 		pr_info("  Not support M64 window\n");
334 		return;
335 	}
336 
337 	if (!firmware_has_feature(FW_FEATURE_OPAL)) {
338 		pr_info("  Firmware too old to support M64 window\n");
339 		return;
340 	}
341 
342 	r = of_get_property(dn, "ibm,opal-m64-window", NULL);
343 	if (!r) {
344 		pr_info("  No <ibm,opal-m64-window> on %s\n",
345 			dn->full_name);
346 		return;
347 	}
348 
349 	res = &hose->mem_resources[1];
350 	res->name = dn->full_name;
351 	res->start = of_translate_address(dn, r + 2);
352 	res->end = res->start + of_read_number(r + 4, 2) - 1;
353 	res->flags = (IORESOURCE_MEM | IORESOURCE_MEM_64 | IORESOURCE_PREFETCH);
354 	pci_addr = of_read_number(r, 2);
355 	hose->mem_offset[1] = res->start - pci_addr;
356 
357 	phb->ioda.m64_size = resource_size(res);
358 	phb->ioda.m64_segsize = phb->ioda.m64_size / phb->ioda.total_pe;
359 	phb->ioda.m64_base = pci_addr;
360 
361 	pr_info(" MEM64 0x%016llx..0x%016llx -> 0x%016llx\n",
362 			res->start, res->end, pci_addr);
363 
364 	/* Use last M64 BAR to cover M64 window */
365 	phb->ioda.m64_bar_idx = 15;
366 	phb->init_m64 = pnv_ioda2_init_m64;
367 	phb->reserve_m64_pe = pnv_ioda2_reserve_m64_pe;
368 	phb->pick_m64_pe = pnv_ioda2_pick_m64_pe;
369 }
370 
371 static void pnv_ioda_freeze_pe(struct pnv_phb *phb, int pe_no)
372 {
373 	struct pnv_ioda_pe *pe = &phb->ioda.pe_array[pe_no];
374 	struct pnv_ioda_pe *slave;
375 	s64 rc;
376 
377 	/* Fetch master PE */
378 	if (pe->flags & PNV_IODA_PE_SLAVE) {
379 		pe = pe->master;
380 		if (WARN_ON(!pe || !(pe->flags & PNV_IODA_PE_MASTER)))
381 			return;
382 
383 		pe_no = pe->pe_number;
384 	}
385 
386 	/* Freeze master PE */
387 	rc = opal_pci_eeh_freeze_set(phb->opal_id,
388 				     pe_no,
389 				     OPAL_EEH_ACTION_SET_FREEZE_ALL);
390 	if (rc != OPAL_SUCCESS) {
391 		pr_warn("%s: Failure %lld freezing PHB#%x-PE#%x\n",
392 			__func__, rc, phb->hose->global_number, pe_no);
393 		return;
394 	}
395 
396 	/* Freeze slave PEs */
397 	if (!(pe->flags & PNV_IODA_PE_MASTER))
398 		return;
399 
400 	list_for_each_entry(slave, &pe->slaves, list) {
401 		rc = opal_pci_eeh_freeze_set(phb->opal_id,
402 					     slave->pe_number,
403 					     OPAL_EEH_ACTION_SET_FREEZE_ALL);
404 		if (rc != OPAL_SUCCESS)
405 			pr_warn("%s: Failure %lld freezing PHB#%x-PE#%x\n",
406 				__func__, rc, phb->hose->global_number,
407 				slave->pe_number);
408 	}
409 }
410 
411 static int pnv_ioda_unfreeze_pe(struct pnv_phb *phb, int pe_no, int opt)
412 {
413 	struct pnv_ioda_pe *pe, *slave;
414 	s64 rc;
415 
416 	/* Find master PE */
417 	pe = &phb->ioda.pe_array[pe_no];
418 	if (pe->flags & PNV_IODA_PE_SLAVE) {
419 		pe = pe->master;
420 		WARN_ON(!pe || !(pe->flags & PNV_IODA_PE_MASTER));
421 		pe_no = pe->pe_number;
422 	}
423 
424 	/* Clear frozen state for master PE */
425 	rc = opal_pci_eeh_freeze_clear(phb->opal_id, pe_no, opt);
426 	if (rc != OPAL_SUCCESS) {
427 		pr_warn("%s: Failure %lld clear %d on PHB#%x-PE#%x\n",
428 			__func__, rc, opt, phb->hose->global_number, pe_no);
429 		return -EIO;
430 	}
431 
432 	if (!(pe->flags & PNV_IODA_PE_MASTER))
433 		return 0;
434 
435 	/* Clear frozen state for slave PEs */
436 	list_for_each_entry(slave, &pe->slaves, list) {
437 		rc = opal_pci_eeh_freeze_clear(phb->opal_id,
438 					     slave->pe_number,
439 					     opt);
440 		if (rc != OPAL_SUCCESS) {
441 			pr_warn("%s: Failure %lld clear %d on PHB#%x-PE#%x\n",
442 				__func__, rc, opt, phb->hose->global_number,
443 				slave->pe_number);
444 			return -EIO;
445 		}
446 	}
447 
448 	return 0;
449 }
450 
451 static int pnv_ioda_get_pe_state(struct pnv_phb *phb, int pe_no)
452 {
453 	struct pnv_ioda_pe *slave, *pe;
454 	u8 fstate, state;
455 	__be16 pcierr;
456 	s64 rc;
457 
458 	/* Sanity check on PE number */
459 	if (pe_no < 0 || pe_no >= phb->ioda.total_pe)
460 		return OPAL_EEH_STOPPED_PERM_UNAVAIL;
461 
462 	/*
463 	 * Fetch the master PE and the PE instance might be
464 	 * not initialized yet.
465 	 */
466 	pe = &phb->ioda.pe_array[pe_no];
467 	if (pe->flags & PNV_IODA_PE_SLAVE) {
468 		pe = pe->master;
469 		WARN_ON(!pe || !(pe->flags & PNV_IODA_PE_MASTER));
470 		pe_no = pe->pe_number;
471 	}
472 
473 	/* Check the master PE */
474 	rc = opal_pci_eeh_freeze_status(phb->opal_id, pe_no,
475 					&state, &pcierr, NULL);
476 	if (rc != OPAL_SUCCESS) {
477 		pr_warn("%s: Failure %lld getting "
478 			"PHB#%x-PE#%x state\n",
479 			__func__, rc,
480 			phb->hose->global_number, pe_no);
481 		return OPAL_EEH_STOPPED_TEMP_UNAVAIL;
482 	}
483 
484 	/* Check the slave PE */
485 	if (!(pe->flags & PNV_IODA_PE_MASTER))
486 		return state;
487 
488 	list_for_each_entry(slave, &pe->slaves, list) {
489 		rc = opal_pci_eeh_freeze_status(phb->opal_id,
490 						slave->pe_number,
491 						&fstate,
492 						&pcierr,
493 						NULL);
494 		if (rc != OPAL_SUCCESS) {
495 			pr_warn("%s: Failure %lld getting "
496 				"PHB#%x-PE#%x state\n",
497 				__func__, rc,
498 				phb->hose->global_number, slave->pe_number);
499 			return OPAL_EEH_STOPPED_TEMP_UNAVAIL;
500 		}
501 
502 		/*
503 		 * Override the result based on the ascending
504 		 * priority.
505 		 */
506 		if (fstate > state)
507 			state = fstate;
508 	}
509 
510 	return state;
511 }
512 
513 /* Currently those 2 are only used when MSIs are enabled, this will change
514  * but in the meantime, we need to protect them to avoid warnings
515  */
516 #ifdef CONFIG_PCI_MSI
517 static struct pnv_ioda_pe *pnv_ioda_get_pe(struct pci_dev *dev)
518 {
519 	struct pci_controller *hose = pci_bus_to_host(dev->bus);
520 	struct pnv_phb *phb = hose->private_data;
521 	struct pci_dn *pdn = pci_get_pdn(dev);
522 
523 	if (!pdn)
524 		return NULL;
525 	if (pdn->pe_number == IODA_INVALID_PE)
526 		return NULL;
527 	return &phb->ioda.pe_array[pdn->pe_number];
528 }
529 #endif /* CONFIG_PCI_MSI */
530 
531 static int pnv_ioda_set_one_peltv(struct pnv_phb *phb,
532 				  struct pnv_ioda_pe *parent,
533 				  struct pnv_ioda_pe *child,
534 				  bool is_add)
535 {
536 	const char *desc = is_add ? "adding" : "removing";
537 	uint8_t op = is_add ? OPAL_ADD_PE_TO_DOMAIN :
538 			      OPAL_REMOVE_PE_FROM_DOMAIN;
539 	struct pnv_ioda_pe *slave;
540 	long rc;
541 
542 	/* Parent PE affects child PE */
543 	rc = opal_pci_set_peltv(phb->opal_id, parent->pe_number,
544 				child->pe_number, op);
545 	if (rc != OPAL_SUCCESS) {
546 		pe_warn(child, "OPAL error %ld %s to parent PELTV\n",
547 			rc, desc);
548 		return -ENXIO;
549 	}
550 
551 	if (!(child->flags & PNV_IODA_PE_MASTER))
552 		return 0;
553 
554 	/* Compound case: parent PE affects slave PEs */
555 	list_for_each_entry(slave, &child->slaves, list) {
556 		rc = opal_pci_set_peltv(phb->opal_id, parent->pe_number,
557 					slave->pe_number, op);
558 		if (rc != OPAL_SUCCESS) {
559 			pe_warn(slave, "OPAL error %ld %s to parent PELTV\n",
560 				rc, desc);
561 			return -ENXIO;
562 		}
563 	}
564 
565 	return 0;
566 }
567 
568 static int pnv_ioda_set_peltv(struct pnv_phb *phb,
569 			      struct pnv_ioda_pe *pe,
570 			      bool is_add)
571 {
572 	struct pnv_ioda_pe *slave;
573 	struct pci_dev *pdev = NULL;
574 	int ret;
575 
576 	/*
577 	 * Clear PE frozen state. If it's master PE, we need
578 	 * clear slave PE frozen state as well.
579 	 */
580 	if (is_add) {
581 		opal_pci_eeh_freeze_clear(phb->opal_id, pe->pe_number,
582 					  OPAL_EEH_ACTION_CLEAR_FREEZE_ALL);
583 		if (pe->flags & PNV_IODA_PE_MASTER) {
584 			list_for_each_entry(slave, &pe->slaves, list)
585 				opal_pci_eeh_freeze_clear(phb->opal_id,
586 							  slave->pe_number,
587 							  OPAL_EEH_ACTION_CLEAR_FREEZE_ALL);
588 		}
589 	}
590 
591 	/*
592 	 * Associate PE in PELT. We need add the PE into the
593 	 * corresponding PELT-V as well. Otherwise, the error
594 	 * originated from the PE might contribute to other
595 	 * PEs.
596 	 */
597 	ret = pnv_ioda_set_one_peltv(phb, pe, pe, is_add);
598 	if (ret)
599 		return ret;
600 
601 	/* For compound PEs, any one affects all of them */
602 	if (pe->flags & PNV_IODA_PE_MASTER) {
603 		list_for_each_entry(slave, &pe->slaves, list) {
604 			ret = pnv_ioda_set_one_peltv(phb, slave, pe, is_add);
605 			if (ret)
606 				return ret;
607 		}
608 	}
609 
610 	if (pe->flags & (PNV_IODA_PE_BUS_ALL | PNV_IODA_PE_BUS))
611 		pdev = pe->pbus->self;
612 	else if (pe->flags & PNV_IODA_PE_DEV)
613 		pdev = pe->pdev->bus->self;
614 #ifdef CONFIG_PCI_IOV
615 	else if (pe->flags & PNV_IODA_PE_VF)
616 		pdev = pe->parent_dev;
617 #endif /* CONFIG_PCI_IOV */
618 	while (pdev) {
619 		struct pci_dn *pdn = pci_get_pdn(pdev);
620 		struct pnv_ioda_pe *parent;
621 
622 		if (pdn && pdn->pe_number != IODA_INVALID_PE) {
623 			parent = &phb->ioda.pe_array[pdn->pe_number];
624 			ret = pnv_ioda_set_one_peltv(phb, parent, pe, is_add);
625 			if (ret)
626 				return ret;
627 		}
628 
629 		pdev = pdev->bus->self;
630 	}
631 
632 	return 0;
633 }
634 
635 #ifdef CONFIG_PCI_IOV
636 static int pnv_ioda_deconfigure_pe(struct pnv_phb *phb, struct pnv_ioda_pe *pe)
637 {
638 	struct pci_dev *parent;
639 	uint8_t bcomp, dcomp, fcomp;
640 	int64_t rc;
641 	long rid_end, rid;
642 
643 	/* Currently, we just deconfigure VF PE. Bus PE will always there.*/
644 	if (pe->pbus) {
645 		int count;
646 
647 		dcomp = OPAL_IGNORE_RID_DEVICE_NUMBER;
648 		fcomp = OPAL_IGNORE_RID_FUNCTION_NUMBER;
649 		parent = pe->pbus->self;
650 		if (pe->flags & PNV_IODA_PE_BUS_ALL)
651 			count = pe->pbus->busn_res.end - pe->pbus->busn_res.start + 1;
652 		else
653 			count = 1;
654 
655 		switch(count) {
656 		case  1: bcomp = OpalPciBusAll;         break;
657 		case  2: bcomp = OpalPciBus7Bits;       break;
658 		case  4: bcomp = OpalPciBus6Bits;       break;
659 		case  8: bcomp = OpalPciBus5Bits;       break;
660 		case 16: bcomp = OpalPciBus4Bits;       break;
661 		case 32: bcomp = OpalPciBus3Bits;       break;
662 		default:
663 			dev_err(&pe->pbus->dev, "Number of subordinate buses %d unsupported\n",
664 			        count);
665 			/* Do an exact match only */
666 			bcomp = OpalPciBusAll;
667 		}
668 		rid_end = pe->rid + (count << 8);
669 	} else {
670 		if (pe->flags & PNV_IODA_PE_VF)
671 			parent = pe->parent_dev;
672 		else
673 			parent = pe->pdev->bus->self;
674 		bcomp = OpalPciBusAll;
675 		dcomp = OPAL_COMPARE_RID_DEVICE_NUMBER;
676 		fcomp = OPAL_COMPARE_RID_FUNCTION_NUMBER;
677 		rid_end = pe->rid + 1;
678 	}
679 
680 	/* Clear the reverse map */
681 	for (rid = pe->rid; rid < rid_end; rid++)
682 		phb->ioda.pe_rmap[rid] = 0;
683 
684 	/* Release from all parents PELT-V */
685 	while (parent) {
686 		struct pci_dn *pdn = pci_get_pdn(parent);
687 		if (pdn && pdn->pe_number != IODA_INVALID_PE) {
688 			rc = opal_pci_set_peltv(phb->opal_id, pdn->pe_number,
689 						pe->pe_number, OPAL_REMOVE_PE_FROM_DOMAIN);
690 			/* XXX What to do in case of error ? */
691 		}
692 		parent = parent->bus->self;
693 	}
694 
695 	opal_pci_eeh_freeze_clear(phb->opal_id, pe->pe_number,
696 				  OPAL_EEH_ACTION_CLEAR_FREEZE_ALL);
697 
698 	/* Disassociate PE in PELT */
699 	rc = opal_pci_set_peltv(phb->opal_id, pe->pe_number,
700 				pe->pe_number, OPAL_REMOVE_PE_FROM_DOMAIN);
701 	if (rc)
702 		pe_warn(pe, "OPAL error %ld remove self from PELTV\n", rc);
703 	rc = opal_pci_set_pe(phb->opal_id, pe->pe_number, pe->rid,
704 			     bcomp, dcomp, fcomp, OPAL_UNMAP_PE);
705 	if (rc)
706 		pe_err(pe, "OPAL error %ld trying to setup PELT table\n", rc);
707 
708 	pe->pbus = NULL;
709 	pe->pdev = NULL;
710 	pe->parent_dev = NULL;
711 
712 	return 0;
713 }
714 #endif /* CONFIG_PCI_IOV */
715 
716 static int pnv_ioda_configure_pe(struct pnv_phb *phb, struct pnv_ioda_pe *pe)
717 {
718 	struct pci_dev *parent;
719 	uint8_t bcomp, dcomp, fcomp;
720 	long rc, rid_end, rid;
721 
722 	/* Bus validation ? */
723 	if (pe->pbus) {
724 		int count;
725 
726 		dcomp = OPAL_IGNORE_RID_DEVICE_NUMBER;
727 		fcomp = OPAL_IGNORE_RID_FUNCTION_NUMBER;
728 		parent = pe->pbus->self;
729 		if (pe->flags & PNV_IODA_PE_BUS_ALL)
730 			count = pe->pbus->busn_res.end - pe->pbus->busn_res.start + 1;
731 		else
732 			count = 1;
733 
734 		switch(count) {
735 		case  1: bcomp = OpalPciBusAll;		break;
736 		case  2: bcomp = OpalPciBus7Bits;	break;
737 		case  4: bcomp = OpalPciBus6Bits;	break;
738 		case  8: bcomp = OpalPciBus5Bits;	break;
739 		case 16: bcomp = OpalPciBus4Bits;	break;
740 		case 32: bcomp = OpalPciBus3Bits;	break;
741 		default:
742 			dev_err(&pe->pbus->dev, "Number of subordinate buses %d unsupported\n",
743 			        count);
744 			/* Do an exact match only */
745 			bcomp = OpalPciBusAll;
746 		}
747 		rid_end = pe->rid + (count << 8);
748 	} else {
749 #ifdef CONFIG_PCI_IOV
750 		if (pe->flags & PNV_IODA_PE_VF)
751 			parent = pe->parent_dev;
752 		else
753 #endif /* CONFIG_PCI_IOV */
754 			parent = pe->pdev->bus->self;
755 		bcomp = OpalPciBusAll;
756 		dcomp = OPAL_COMPARE_RID_DEVICE_NUMBER;
757 		fcomp = OPAL_COMPARE_RID_FUNCTION_NUMBER;
758 		rid_end = pe->rid + 1;
759 	}
760 
761 	/*
762 	 * Associate PE in PELT. We need add the PE into the
763 	 * corresponding PELT-V as well. Otherwise, the error
764 	 * originated from the PE might contribute to other
765 	 * PEs.
766 	 */
767 	rc = opal_pci_set_pe(phb->opal_id, pe->pe_number, pe->rid,
768 			     bcomp, dcomp, fcomp, OPAL_MAP_PE);
769 	if (rc) {
770 		pe_err(pe, "OPAL error %ld trying to setup PELT table\n", rc);
771 		return -ENXIO;
772 	}
773 
774 	/*
775 	 * Configure PELTV. NPUs don't have a PELTV table so skip
776 	 * configuration on them.
777 	 */
778 	if (phb->type != PNV_PHB_NPU)
779 		pnv_ioda_set_peltv(phb, pe, true);
780 
781 	/* Setup reverse map */
782 	for (rid = pe->rid; rid < rid_end; rid++)
783 		phb->ioda.pe_rmap[rid] = pe->pe_number;
784 
785 	/* Setup one MVTs on IODA1 */
786 	if (phb->type != PNV_PHB_IODA1) {
787 		pe->mve_number = 0;
788 		goto out;
789 	}
790 
791 	pe->mve_number = pe->pe_number;
792 	rc = opal_pci_set_mve(phb->opal_id, pe->mve_number, pe->pe_number);
793 	if (rc != OPAL_SUCCESS) {
794 		pe_err(pe, "OPAL error %ld setting up MVE %d\n",
795 		       rc, pe->mve_number);
796 		pe->mve_number = -1;
797 	} else {
798 		rc = opal_pci_set_mve_enable(phb->opal_id,
799 					     pe->mve_number, OPAL_ENABLE_MVE);
800 		if (rc) {
801 			pe_err(pe, "OPAL error %ld enabling MVE %d\n",
802 			       rc, pe->mve_number);
803 			pe->mve_number = -1;
804 		}
805 	}
806 
807 out:
808 	return 0;
809 }
810 
811 static void pnv_ioda_link_pe_by_weight(struct pnv_phb *phb,
812 				       struct pnv_ioda_pe *pe)
813 {
814 	struct pnv_ioda_pe *lpe;
815 
816 	list_for_each_entry(lpe, &phb->ioda.pe_dma_list, dma_link) {
817 		if (lpe->dma_weight < pe->dma_weight) {
818 			list_add_tail(&pe->dma_link, &lpe->dma_link);
819 			return;
820 		}
821 	}
822 	list_add_tail(&pe->dma_link, &phb->ioda.pe_dma_list);
823 }
824 
825 static unsigned int pnv_ioda_dma_weight(struct pci_dev *dev)
826 {
827 	/* This is quite simplistic. The "base" weight of a device
828 	 * is 10. 0 means no DMA is to be accounted for it.
829 	 */
830 
831 	/* If it's a bridge, no DMA */
832 	if (dev->hdr_type != PCI_HEADER_TYPE_NORMAL)
833 		return 0;
834 
835 	/* Reduce the weight of slow USB controllers */
836 	if (dev->class == PCI_CLASS_SERIAL_USB_UHCI ||
837 	    dev->class == PCI_CLASS_SERIAL_USB_OHCI ||
838 	    dev->class == PCI_CLASS_SERIAL_USB_EHCI)
839 		return 3;
840 
841 	/* Increase the weight of RAID (includes Obsidian) */
842 	if ((dev->class >> 8) == PCI_CLASS_STORAGE_RAID)
843 		return 15;
844 
845 	/* Default */
846 	return 10;
847 }
848 
849 #ifdef CONFIG_PCI_IOV
850 static int pnv_pci_vf_resource_shift(struct pci_dev *dev, int offset)
851 {
852 	struct pci_dn *pdn = pci_get_pdn(dev);
853 	int i;
854 	struct resource *res, res2;
855 	resource_size_t size;
856 	u16 num_vfs;
857 
858 	if (!dev->is_physfn)
859 		return -EINVAL;
860 
861 	/*
862 	 * "offset" is in VFs.  The M64 windows are sized so that when they
863 	 * are segmented, each segment is the same size as the IOV BAR.
864 	 * Each segment is in a separate PE, and the high order bits of the
865 	 * address are the PE number.  Therefore, each VF's BAR is in a
866 	 * separate PE, and changing the IOV BAR start address changes the
867 	 * range of PEs the VFs are in.
868 	 */
869 	num_vfs = pdn->num_vfs;
870 	for (i = 0; i < PCI_SRIOV_NUM_BARS; i++) {
871 		res = &dev->resource[i + PCI_IOV_RESOURCES];
872 		if (!res->flags || !res->parent)
873 			continue;
874 
875 		if (!pnv_pci_is_mem_pref_64(res->flags))
876 			continue;
877 
878 		/*
879 		 * The actual IOV BAR range is determined by the start address
880 		 * and the actual size for num_vfs VFs BAR.  This check is to
881 		 * make sure that after shifting, the range will not overlap
882 		 * with another device.
883 		 */
884 		size = pci_iov_resource_size(dev, i + PCI_IOV_RESOURCES);
885 		res2.flags = res->flags;
886 		res2.start = res->start + (size * offset);
887 		res2.end = res2.start + (size * num_vfs) - 1;
888 
889 		if (res2.end > res->end) {
890 			dev_err(&dev->dev, "VF BAR%d: %pR would extend past %pR (trying to enable %d VFs shifted by %d)\n",
891 				i, &res2, res, num_vfs, offset);
892 			return -EBUSY;
893 		}
894 	}
895 
896 	/*
897 	 * After doing so, there would be a "hole" in the /proc/iomem when
898 	 * offset is a positive value. It looks like the device return some
899 	 * mmio back to the system, which actually no one could use it.
900 	 */
901 	for (i = 0; i < PCI_SRIOV_NUM_BARS; i++) {
902 		res = &dev->resource[i + PCI_IOV_RESOURCES];
903 		if (!res->flags || !res->parent)
904 			continue;
905 
906 		if (!pnv_pci_is_mem_pref_64(res->flags))
907 			continue;
908 
909 		size = pci_iov_resource_size(dev, i + PCI_IOV_RESOURCES);
910 		res2 = *res;
911 		res->start += size * offset;
912 
913 		dev_info(&dev->dev, "VF BAR%d: %pR shifted to %pR (%sabling %d VFs shifted by %d)\n",
914 			 i, &res2, res, (offset > 0) ? "En" : "Dis",
915 			 num_vfs, offset);
916 		pci_update_resource(dev, i + PCI_IOV_RESOURCES);
917 	}
918 	return 0;
919 }
920 #endif /* CONFIG_PCI_IOV */
921 
922 static struct pnv_ioda_pe *pnv_ioda_setup_dev_PE(struct pci_dev *dev)
923 {
924 	struct pci_controller *hose = pci_bus_to_host(dev->bus);
925 	struct pnv_phb *phb = hose->private_data;
926 	struct pci_dn *pdn = pci_get_pdn(dev);
927 	struct pnv_ioda_pe *pe;
928 	int pe_num;
929 
930 	if (!pdn) {
931 		pr_err("%s: Device tree node not associated properly\n",
932 			   pci_name(dev));
933 		return NULL;
934 	}
935 	if (pdn->pe_number != IODA_INVALID_PE)
936 		return NULL;
937 
938 	pe_num = pnv_ioda_alloc_pe(phb);
939 	if (pe_num == IODA_INVALID_PE) {
940 		pr_warning("%s: Not enough PE# available, disabling device\n",
941 			   pci_name(dev));
942 		return NULL;
943 	}
944 
945 	/* NOTE: We get only one ref to the pci_dev for the pdn, not for the
946 	 * pointer in the PE data structure, both should be destroyed at the
947 	 * same time. However, this needs to be looked at more closely again
948 	 * once we actually start removing things (Hotplug, SR-IOV, ...)
949 	 *
950 	 * At some point we want to remove the PDN completely anyways
951 	 */
952 	pe = &phb->ioda.pe_array[pe_num];
953 	pci_dev_get(dev);
954 	pdn->pcidev = dev;
955 	pdn->pe_number = pe_num;
956 	pe->flags = PNV_IODA_PE_DEV;
957 	pe->pdev = dev;
958 	pe->pbus = NULL;
959 	pe->tce32_seg = -1;
960 	pe->mve_number = -1;
961 	pe->rid = dev->bus->number << 8 | pdn->devfn;
962 
963 	pe_info(pe, "Associated device to PE\n");
964 
965 	if (pnv_ioda_configure_pe(phb, pe)) {
966 		/* XXX What do we do here ? */
967 		if (pe_num)
968 			pnv_ioda_free_pe(phb, pe_num);
969 		pdn->pe_number = IODA_INVALID_PE;
970 		pe->pdev = NULL;
971 		pci_dev_put(dev);
972 		return NULL;
973 	}
974 
975 	/* Assign a DMA weight to the device */
976 	pe->dma_weight = pnv_ioda_dma_weight(dev);
977 	if (pe->dma_weight != 0) {
978 		phb->ioda.dma_weight += pe->dma_weight;
979 		phb->ioda.dma_pe_count++;
980 	}
981 
982 	/* Link the PE */
983 	pnv_ioda_link_pe_by_weight(phb, pe);
984 
985 	return pe;
986 }
987 
988 static void pnv_ioda_setup_same_PE(struct pci_bus *bus, struct pnv_ioda_pe *pe)
989 {
990 	struct pci_dev *dev;
991 
992 	list_for_each_entry(dev, &bus->devices, bus_list) {
993 		struct pci_dn *pdn = pci_get_pdn(dev);
994 
995 		if (pdn == NULL) {
996 			pr_warn("%s: No device node associated with device !\n",
997 				pci_name(dev));
998 			continue;
999 		}
1000 		pdn->pcidev = dev;
1001 		pdn->pe_number = pe->pe_number;
1002 		pe->dma_weight += pnv_ioda_dma_weight(dev);
1003 		if ((pe->flags & PNV_IODA_PE_BUS_ALL) && dev->subordinate)
1004 			pnv_ioda_setup_same_PE(dev->subordinate, pe);
1005 	}
1006 }
1007 
1008 /*
1009  * There're 2 types of PCI bus sensitive PEs: One that is compromised of
1010  * single PCI bus. Another one that contains the primary PCI bus and its
1011  * subordinate PCI devices and buses. The second type of PE is normally
1012  * orgiriated by PCIe-to-PCI bridge or PLX switch downstream ports.
1013  */
1014 static void pnv_ioda_setup_bus_PE(struct pci_bus *bus, bool all)
1015 {
1016 	struct pci_controller *hose = pci_bus_to_host(bus);
1017 	struct pnv_phb *phb = hose->private_data;
1018 	struct pnv_ioda_pe *pe;
1019 	int pe_num = IODA_INVALID_PE;
1020 
1021 	/* Check if PE is determined by M64 */
1022 	if (phb->pick_m64_pe)
1023 		pe_num = phb->pick_m64_pe(bus, all);
1024 
1025 	/* The PE number isn't pinned by M64 */
1026 	if (pe_num == IODA_INVALID_PE)
1027 		pe_num = pnv_ioda_alloc_pe(phb);
1028 
1029 	if (pe_num == IODA_INVALID_PE) {
1030 		pr_warning("%s: Not enough PE# available for PCI bus %04x:%02x\n",
1031 			__func__, pci_domain_nr(bus), bus->number);
1032 		return;
1033 	}
1034 
1035 	pe = &phb->ioda.pe_array[pe_num];
1036 	pe->flags |= (all ? PNV_IODA_PE_BUS_ALL : PNV_IODA_PE_BUS);
1037 	pe->pbus = bus;
1038 	pe->pdev = NULL;
1039 	pe->tce32_seg = -1;
1040 	pe->mve_number = -1;
1041 	pe->rid = bus->busn_res.start << 8;
1042 	pe->dma_weight = 0;
1043 
1044 	if (all)
1045 		pe_info(pe, "Secondary bus %d..%d associated with PE#%d\n",
1046 			bus->busn_res.start, bus->busn_res.end, pe_num);
1047 	else
1048 		pe_info(pe, "Secondary bus %d associated with PE#%d\n",
1049 			bus->busn_res.start, pe_num);
1050 
1051 	if (pnv_ioda_configure_pe(phb, pe)) {
1052 		/* XXX What do we do here ? */
1053 		if (pe_num)
1054 			pnv_ioda_free_pe(phb, pe_num);
1055 		pe->pbus = NULL;
1056 		return;
1057 	}
1058 
1059 	/* Associate it with all child devices */
1060 	pnv_ioda_setup_same_PE(bus, pe);
1061 
1062 	/* Put PE to the list */
1063 	list_add_tail(&pe->list, &phb->ioda.pe_list);
1064 
1065 	/* Account for one DMA PE if at least one DMA capable device exist
1066 	 * below the bridge
1067 	 */
1068 	if (pe->dma_weight != 0) {
1069 		phb->ioda.dma_weight += pe->dma_weight;
1070 		phb->ioda.dma_pe_count++;
1071 	}
1072 
1073 	/* Link the PE */
1074 	pnv_ioda_link_pe_by_weight(phb, pe);
1075 }
1076 
1077 static struct pnv_ioda_pe *pnv_ioda_setup_npu_PE(struct pci_dev *npu_pdev)
1078 {
1079 	int pe_num, found_pe = false, rc;
1080 	long rid;
1081 	struct pnv_ioda_pe *pe;
1082 	struct pci_dev *gpu_pdev;
1083 	struct pci_dn *npu_pdn;
1084 	struct pci_controller *hose = pci_bus_to_host(npu_pdev->bus);
1085 	struct pnv_phb *phb = hose->private_data;
1086 
1087 	/*
1088 	 * Due to a hardware errata PE#0 on the NPU is reserved for
1089 	 * error handling. This means we only have three PEs remaining
1090 	 * which need to be assigned to four links, implying some
1091 	 * links must share PEs.
1092 	 *
1093 	 * To achieve this we assign PEs such that NPUs linking the
1094 	 * same GPU get assigned the same PE.
1095 	 */
1096 	gpu_pdev = pnv_pci_get_gpu_dev(npu_pdev);
1097 	for (pe_num = 0; pe_num < phb->ioda.total_pe; pe_num++) {
1098 		pe = &phb->ioda.pe_array[pe_num];
1099 		if (!pe->pdev)
1100 			continue;
1101 
1102 		if (pnv_pci_get_gpu_dev(pe->pdev) == gpu_pdev) {
1103 			/*
1104 			 * This device has the same peer GPU so should
1105 			 * be assigned the same PE as the existing
1106 			 * peer NPU.
1107 			 */
1108 			dev_info(&npu_pdev->dev,
1109 				"Associating to existing PE %d\n", pe_num);
1110 			pci_dev_get(npu_pdev);
1111 			npu_pdn = pci_get_pdn(npu_pdev);
1112 			rid = npu_pdev->bus->number << 8 | npu_pdn->devfn;
1113 			npu_pdn->pcidev = npu_pdev;
1114 			npu_pdn->pe_number = pe_num;
1115 			pe->dma_weight += pnv_ioda_dma_weight(npu_pdev);
1116 			phb->ioda.pe_rmap[rid] = pe->pe_number;
1117 
1118 			/* Map the PE to this link */
1119 			rc = opal_pci_set_pe(phb->opal_id, pe_num, rid,
1120 					OpalPciBusAll,
1121 					OPAL_COMPARE_RID_DEVICE_NUMBER,
1122 					OPAL_COMPARE_RID_FUNCTION_NUMBER,
1123 					OPAL_MAP_PE);
1124 			WARN_ON(rc != OPAL_SUCCESS);
1125 			found_pe = true;
1126 			break;
1127 		}
1128 	}
1129 
1130 	if (!found_pe)
1131 		/*
1132 		 * Could not find an existing PE so allocate a new
1133 		 * one.
1134 		 */
1135 		return pnv_ioda_setup_dev_PE(npu_pdev);
1136 	else
1137 		return pe;
1138 }
1139 
1140 static void pnv_ioda_setup_npu_PEs(struct pci_bus *bus)
1141 {
1142 	struct pci_dev *pdev;
1143 
1144 	list_for_each_entry(pdev, &bus->devices, bus_list)
1145 		pnv_ioda_setup_npu_PE(pdev);
1146 }
1147 
1148 static void pnv_ioda_setup_PEs(struct pci_bus *bus)
1149 {
1150 	struct pci_dev *dev;
1151 
1152 	pnv_ioda_setup_bus_PE(bus, false);
1153 
1154 	list_for_each_entry(dev, &bus->devices, bus_list) {
1155 		if (dev->subordinate) {
1156 			if (pci_pcie_type(dev) == PCI_EXP_TYPE_PCI_BRIDGE)
1157 				pnv_ioda_setup_bus_PE(dev->subordinate, true);
1158 			else
1159 				pnv_ioda_setup_PEs(dev->subordinate);
1160 		}
1161 	}
1162 }
1163 
1164 /*
1165  * Configure PEs so that the downstream PCI buses and devices
1166  * could have their associated PE#. Unfortunately, we didn't
1167  * figure out the way to identify the PLX bridge yet. So we
1168  * simply put the PCI bus and the subordinate behind the root
1169  * port to PE# here. The game rule here is expected to be changed
1170  * as soon as we can detected PLX bridge correctly.
1171  */
1172 static void pnv_pci_ioda_setup_PEs(void)
1173 {
1174 	struct pci_controller *hose, *tmp;
1175 	struct pnv_phb *phb;
1176 
1177 	list_for_each_entry_safe(hose, tmp, &hose_list, list_node) {
1178 		phb = hose->private_data;
1179 
1180 		/* M64 layout might affect PE allocation */
1181 		if (phb->reserve_m64_pe)
1182 			phb->reserve_m64_pe(hose->bus, NULL, true);
1183 
1184 		/*
1185 		 * On NPU PHB, we expect separate PEs for individual PCI
1186 		 * functions. PCI bus dependent PEs are required for the
1187 		 * remaining types of PHBs.
1188 		 */
1189 		if (phb->type == PNV_PHB_NPU) {
1190 			/* PE#0 is needed for error reporting */
1191 			pnv_ioda_reserve_pe(phb, 0);
1192 			pnv_ioda_setup_npu_PEs(hose->bus);
1193 		} else
1194 			pnv_ioda_setup_PEs(hose->bus);
1195 	}
1196 }
1197 
1198 #ifdef CONFIG_PCI_IOV
1199 static int pnv_pci_vf_release_m64(struct pci_dev *pdev)
1200 {
1201 	struct pci_bus        *bus;
1202 	struct pci_controller *hose;
1203 	struct pnv_phb        *phb;
1204 	struct pci_dn         *pdn;
1205 	int                    i, j;
1206 
1207 	bus = pdev->bus;
1208 	hose = pci_bus_to_host(bus);
1209 	phb = hose->private_data;
1210 	pdn = pci_get_pdn(pdev);
1211 
1212 	for (i = 0; i < PCI_SRIOV_NUM_BARS; i++)
1213 		for (j = 0; j < M64_PER_IOV; j++) {
1214 			if (pdn->m64_wins[i][j] == IODA_INVALID_M64)
1215 				continue;
1216 			opal_pci_phb_mmio_enable(phb->opal_id,
1217 				OPAL_M64_WINDOW_TYPE, pdn->m64_wins[i][j], 0);
1218 			clear_bit(pdn->m64_wins[i][j], &phb->ioda.m64_bar_alloc);
1219 			pdn->m64_wins[i][j] = IODA_INVALID_M64;
1220 		}
1221 
1222 	return 0;
1223 }
1224 
1225 static int pnv_pci_vf_assign_m64(struct pci_dev *pdev, u16 num_vfs)
1226 {
1227 	struct pci_bus        *bus;
1228 	struct pci_controller *hose;
1229 	struct pnv_phb        *phb;
1230 	struct pci_dn         *pdn;
1231 	unsigned int           win;
1232 	struct resource       *res;
1233 	int                    i, j;
1234 	int64_t                rc;
1235 	int                    total_vfs;
1236 	resource_size_t        size, start;
1237 	int                    pe_num;
1238 	int                    vf_groups;
1239 	int                    vf_per_group;
1240 
1241 	bus = pdev->bus;
1242 	hose = pci_bus_to_host(bus);
1243 	phb = hose->private_data;
1244 	pdn = pci_get_pdn(pdev);
1245 	total_vfs = pci_sriov_get_totalvfs(pdev);
1246 
1247 	/* Initialize the m64_wins to IODA_INVALID_M64 */
1248 	for (i = 0; i < PCI_SRIOV_NUM_BARS; i++)
1249 		for (j = 0; j < M64_PER_IOV; j++)
1250 			pdn->m64_wins[i][j] = IODA_INVALID_M64;
1251 
1252 	if (pdn->m64_per_iov == M64_PER_IOV) {
1253 		vf_groups = (num_vfs <= M64_PER_IOV) ? num_vfs: M64_PER_IOV;
1254 		vf_per_group = (num_vfs <= M64_PER_IOV)? 1:
1255 			roundup_pow_of_two(num_vfs) / pdn->m64_per_iov;
1256 	} else {
1257 		vf_groups = 1;
1258 		vf_per_group = 1;
1259 	}
1260 
1261 	for (i = 0; i < PCI_SRIOV_NUM_BARS; i++) {
1262 		res = &pdev->resource[i + PCI_IOV_RESOURCES];
1263 		if (!res->flags || !res->parent)
1264 			continue;
1265 
1266 		if (!pnv_pci_is_mem_pref_64(res->flags))
1267 			continue;
1268 
1269 		for (j = 0; j < vf_groups; j++) {
1270 			do {
1271 				win = find_next_zero_bit(&phb->ioda.m64_bar_alloc,
1272 						phb->ioda.m64_bar_idx + 1, 0);
1273 
1274 				if (win >= phb->ioda.m64_bar_idx + 1)
1275 					goto m64_failed;
1276 			} while (test_and_set_bit(win, &phb->ioda.m64_bar_alloc));
1277 
1278 			pdn->m64_wins[i][j] = win;
1279 
1280 			if (pdn->m64_per_iov == M64_PER_IOV) {
1281 				size = pci_iov_resource_size(pdev,
1282 							PCI_IOV_RESOURCES + i);
1283 				size = size * vf_per_group;
1284 				start = res->start + size * j;
1285 			} else {
1286 				size = resource_size(res);
1287 				start = res->start;
1288 			}
1289 
1290 			/* Map the M64 here */
1291 			if (pdn->m64_per_iov == M64_PER_IOV) {
1292 				pe_num = pdn->offset + j;
1293 				rc = opal_pci_map_pe_mmio_window(phb->opal_id,
1294 						pe_num, OPAL_M64_WINDOW_TYPE,
1295 						pdn->m64_wins[i][j], 0);
1296 			}
1297 
1298 			rc = opal_pci_set_phb_mem_window(phb->opal_id,
1299 						 OPAL_M64_WINDOW_TYPE,
1300 						 pdn->m64_wins[i][j],
1301 						 start,
1302 						 0, /* unused */
1303 						 size);
1304 
1305 
1306 			if (rc != OPAL_SUCCESS) {
1307 				dev_err(&pdev->dev, "Failed to map M64 window #%d: %lld\n",
1308 					win, rc);
1309 				goto m64_failed;
1310 			}
1311 
1312 			if (pdn->m64_per_iov == M64_PER_IOV)
1313 				rc = opal_pci_phb_mmio_enable(phb->opal_id,
1314 				     OPAL_M64_WINDOW_TYPE, pdn->m64_wins[i][j], 2);
1315 			else
1316 				rc = opal_pci_phb_mmio_enable(phb->opal_id,
1317 				     OPAL_M64_WINDOW_TYPE, pdn->m64_wins[i][j], 1);
1318 
1319 			if (rc != OPAL_SUCCESS) {
1320 				dev_err(&pdev->dev, "Failed to enable M64 window #%d: %llx\n",
1321 					win, rc);
1322 				goto m64_failed;
1323 			}
1324 		}
1325 	}
1326 	return 0;
1327 
1328 m64_failed:
1329 	pnv_pci_vf_release_m64(pdev);
1330 	return -EBUSY;
1331 }
1332 
1333 static long pnv_pci_ioda2_unset_window(struct iommu_table_group *table_group,
1334 		int num);
1335 static void pnv_pci_ioda2_set_bypass(struct pnv_ioda_pe *pe, bool enable);
1336 
1337 static void pnv_pci_ioda2_release_dma_pe(struct pci_dev *dev, struct pnv_ioda_pe *pe)
1338 {
1339 	struct iommu_table    *tbl;
1340 	int64_t               rc;
1341 
1342 	tbl = pe->table_group.tables[0];
1343 	rc = pnv_pci_ioda2_unset_window(&pe->table_group, 0);
1344 	if (rc)
1345 		pe_warn(pe, "OPAL error %ld release DMA window\n", rc);
1346 
1347 	pnv_pci_ioda2_set_bypass(pe, false);
1348 	if (pe->table_group.group) {
1349 		iommu_group_put(pe->table_group.group);
1350 		BUG_ON(pe->table_group.group);
1351 	}
1352 	pnv_pci_ioda2_table_free_pages(tbl);
1353 	iommu_free_table(tbl, of_node_full_name(dev->dev.of_node));
1354 }
1355 
1356 static void pnv_ioda_release_vf_PE(struct pci_dev *pdev, u16 num_vfs)
1357 {
1358 	struct pci_bus        *bus;
1359 	struct pci_controller *hose;
1360 	struct pnv_phb        *phb;
1361 	struct pnv_ioda_pe    *pe, *pe_n;
1362 	struct pci_dn         *pdn;
1363 	u16                    vf_index;
1364 	int64_t                rc;
1365 
1366 	bus = pdev->bus;
1367 	hose = pci_bus_to_host(bus);
1368 	phb = hose->private_data;
1369 	pdn = pci_get_pdn(pdev);
1370 
1371 	if (!pdev->is_physfn)
1372 		return;
1373 
1374 	if (pdn->m64_per_iov == M64_PER_IOV && num_vfs > M64_PER_IOV) {
1375 		int   vf_group;
1376 		int   vf_per_group;
1377 		int   vf_index1;
1378 
1379 		vf_per_group = roundup_pow_of_two(num_vfs) / pdn->m64_per_iov;
1380 
1381 		for (vf_group = 0; vf_group < M64_PER_IOV; vf_group++)
1382 			for (vf_index = vf_group * vf_per_group;
1383 				vf_index < (vf_group + 1) * vf_per_group &&
1384 				vf_index < num_vfs;
1385 				vf_index++)
1386 				for (vf_index1 = vf_group * vf_per_group;
1387 					vf_index1 < (vf_group + 1) * vf_per_group &&
1388 					vf_index1 < num_vfs;
1389 					vf_index1++){
1390 
1391 					rc = opal_pci_set_peltv(phb->opal_id,
1392 						pdn->offset + vf_index,
1393 						pdn->offset + vf_index1,
1394 						OPAL_REMOVE_PE_FROM_DOMAIN);
1395 
1396 					if (rc)
1397 					    dev_warn(&pdev->dev, "%s: Failed to unlink same group PE#%d(%lld)\n",
1398 						__func__,
1399 						pdn->offset + vf_index1, rc);
1400 				}
1401 	}
1402 
1403 	list_for_each_entry_safe(pe, pe_n, &phb->ioda.pe_list, list) {
1404 		if (pe->parent_dev != pdev)
1405 			continue;
1406 
1407 		pnv_pci_ioda2_release_dma_pe(pdev, pe);
1408 
1409 		/* Remove from list */
1410 		mutex_lock(&phb->ioda.pe_list_mutex);
1411 		list_del(&pe->list);
1412 		mutex_unlock(&phb->ioda.pe_list_mutex);
1413 
1414 		pnv_ioda_deconfigure_pe(phb, pe);
1415 
1416 		pnv_ioda_free_pe(phb, pe->pe_number);
1417 	}
1418 }
1419 
1420 void pnv_pci_sriov_disable(struct pci_dev *pdev)
1421 {
1422 	struct pci_bus        *bus;
1423 	struct pci_controller *hose;
1424 	struct pnv_phb        *phb;
1425 	struct pci_dn         *pdn;
1426 	struct pci_sriov      *iov;
1427 	u16 num_vfs;
1428 
1429 	bus = pdev->bus;
1430 	hose = pci_bus_to_host(bus);
1431 	phb = hose->private_data;
1432 	pdn = pci_get_pdn(pdev);
1433 	iov = pdev->sriov;
1434 	num_vfs = pdn->num_vfs;
1435 
1436 	/* Release VF PEs */
1437 	pnv_ioda_release_vf_PE(pdev, num_vfs);
1438 
1439 	if (phb->type == PNV_PHB_IODA2) {
1440 		if (pdn->m64_per_iov == 1)
1441 			pnv_pci_vf_resource_shift(pdev, -pdn->offset);
1442 
1443 		/* Release M64 windows */
1444 		pnv_pci_vf_release_m64(pdev);
1445 
1446 		/* Release PE numbers */
1447 		bitmap_clear(phb->ioda.pe_alloc, pdn->offset, num_vfs);
1448 		pdn->offset = 0;
1449 	}
1450 }
1451 
1452 static void pnv_pci_ioda2_setup_dma_pe(struct pnv_phb *phb,
1453 				       struct pnv_ioda_pe *pe);
1454 static void pnv_ioda_setup_vf_PE(struct pci_dev *pdev, u16 num_vfs)
1455 {
1456 	struct pci_bus        *bus;
1457 	struct pci_controller *hose;
1458 	struct pnv_phb        *phb;
1459 	struct pnv_ioda_pe    *pe;
1460 	int                    pe_num;
1461 	u16                    vf_index;
1462 	struct pci_dn         *pdn;
1463 	int64_t                rc;
1464 
1465 	bus = pdev->bus;
1466 	hose = pci_bus_to_host(bus);
1467 	phb = hose->private_data;
1468 	pdn = pci_get_pdn(pdev);
1469 
1470 	if (!pdev->is_physfn)
1471 		return;
1472 
1473 	/* Reserve PE for each VF */
1474 	for (vf_index = 0; vf_index < num_vfs; vf_index++) {
1475 		pe_num = pdn->offset + vf_index;
1476 
1477 		pe = &phb->ioda.pe_array[pe_num];
1478 		pe->pe_number = pe_num;
1479 		pe->phb = phb;
1480 		pe->flags = PNV_IODA_PE_VF;
1481 		pe->pbus = NULL;
1482 		pe->parent_dev = pdev;
1483 		pe->tce32_seg = -1;
1484 		pe->mve_number = -1;
1485 		pe->rid = (pci_iov_virtfn_bus(pdev, vf_index) << 8) |
1486 			   pci_iov_virtfn_devfn(pdev, vf_index);
1487 
1488 		pe_info(pe, "VF %04d:%02d:%02d.%d associated with PE#%d\n",
1489 			hose->global_number, pdev->bus->number,
1490 			PCI_SLOT(pci_iov_virtfn_devfn(pdev, vf_index)),
1491 			PCI_FUNC(pci_iov_virtfn_devfn(pdev, vf_index)), pe_num);
1492 
1493 		if (pnv_ioda_configure_pe(phb, pe)) {
1494 			/* XXX What do we do here ? */
1495 			if (pe_num)
1496 				pnv_ioda_free_pe(phb, pe_num);
1497 			pe->pdev = NULL;
1498 			continue;
1499 		}
1500 
1501 		/* Put PE to the list */
1502 		mutex_lock(&phb->ioda.pe_list_mutex);
1503 		list_add_tail(&pe->list, &phb->ioda.pe_list);
1504 		mutex_unlock(&phb->ioda.pe_list_mutex);
1505 
1506 		pnv_pci_ioda2_setup_dma_pe(phb, pe);
1507 	}
1508 
1509 	if (pdn->m64_per_iov == M64_PER_IOV && num_vfs > M64_PER_IOV) {
1510 		int   vf_group;
1511 		int   vf_per_group;
1512 		int   vf_index1;
1513 
1514 		vf_per_group = roundup_pow_of_two(num_vfs) / pdn->m64_per_iov;
1515 
1516 		for (vf_group = 0; vf_group < M64_PER_IOV; vf_group++) {
1517 			for (vf_index = vf_group * vf_per_group;
1518 			     vf_index < (vf_group + 1) * vf_per_group &&
1519 			     vf_index < num_vfs;
1520 			     vf_index++) {
1521 				for (vf_index1 = vf_group * vf_per_group;
1522 				     vf_index1 < (vf_group + 1) * vf_per_group &&
1523 				     vf_index1 < num_vfs;
1524 				     vf_index1++) {
1525 
1526 					rc = opal_pci_set_peltv(phb->opal_id,
1527 						pdn->offset + vf_index,
1528 						pdn->offset + vf_index1,
1529 						OPAL_ADD_PE_TO_DOMAIN);
1530 
1531 					if (rc)
1532 					    dev_warn(&pdev->dev, "%s: Failed to link same group PE#%d(%lld)\n",
1533 						__func__,
1534 						pdn->offset + vf_index1, rc);
1535 				}
1536 			}
1537 		}
1538 	}
1539 }
1540 
1541 int pnv_pci_sriov_enable(struct pci_dev *pdev, u16 num_vfs)
1542 {
1543 	struct pci_bus        *bus;
1544 	struct pci_controller *hose;
1545 	struct pnv_phb        *phb;
1546 	struct pci_dn         *pdn;
1547 	int                    ret;
1548 
1549 	bus = pdev->bus;
1550 	hose = pci_bus_to_host(bus);
1551 	phb = hose->private_data;
1552 	pdn = pci_get_pdn(pdev);
1553 
1554 	if (phb->type == PNV_PHB_IODA2) {
1555 		/* Calculate available PE for required VFs */
1556 		mutex_lock(&phb->ioda.pe_alloc_mutex);
1557 		pdn->offset = bitmap_find_next_zero_area(
1558 			phb->ioda.pe_alloc, phb->ioda.total_pe,
1559 			0, num_vfs, 0);
1560 		if (pdn->offset >= phb->ioda.total_pe) {
1561 			mutex_unlock(&phb->ioda.pe_alloc_mutex);
1562 			dev_info(&pdev->dev, "Failed to enable VF%d\n", num_vfs);
1563 			pdn->offset = 0;
1564 			return -EBUSY;
1565 		}
1566 		bitmap_set(phb->ioda.pe_alloc, pdn->offset, num_vfs);
1567 		pdn->num_vfs = num_vfs;
1568 		mutex_unlock(&phb->ioda.pe_alloc_mutex);
1569 
1570 		/* Assign M64 window accordingly */
1571 		ret = pnv_pci_vf_assign_m64(pdev, num_vfs);
1572 		if (ret) {
1573 			dev_info(&pdev->dev, "Not enough M64 window resources\n");
1574 			goto m64_failed;
1575 		}
1576 
1577 		/*
1578 		 * When using one M64 BAR to map one IOV BAR, we need to shift
1579 		 * the IOV BAR according to the PE# allocated to the VFs.
1580 		 * Otherwise, the PE# for the VF will conflict with others.
1581 		 */
1582 		if (pdn->m64_per_iov == 1) {
1583 			ret = pnv_pci_vf_resource_shift(pdev, pdn->offset);
1584 			if (ret)
1585 				goto m64_failed;
1586 		}
1587 	}
1588 
1589 	/* Setup VF PEs */
1590 	pnv_ioda_setup_vf_PE(pdev, num_vfs);
1591 
1592 	return 0;
1593 
1594 m64_failed:
1595 	bitmap_clear(phb->ioda.pe_alloc, pdn->offset, num_vfs);
1596 	pdn->offset = 0;
1597 
1598 	return ret;
1599 }
1600 
1601 int pcibios_sriov_disable(struct pci_dev *pdev)
1602 {
1603 	pnv_pci_sriov_disable(pdev);
1604 
1605 	/* Release PCI data */
1606 	remove_dev_pci_data(pdev);
1607 	return 0;
1608 }
1609 
1610 int pcibios_sriov_enable(struct pci_dev *pdev, u16 num_vfs)
1611 {
1612 	/* Allocate PCI data */
1613 	add_dev_pci_data(pdev);
1614 
1615 	pnv_pci_sriov_enable(pdev, num_vfs);
1616 	return 0;
1617 }
1618 #endif /* CONFIG_PCI_IOV */
1619 
1620 static void pnv_pci_ioda_dma_dev_setup(struct pnv_phb *phb, struct pci_dev *pdev)
1621 {
1622 	struct pci_dn *pdn = pci_get_pdn(pdev);
1623 	struct pnv_ioda_pe *pe;
1624 
1625 	/*
1626 	 * The function can be called while the PE#
1627 	 * hasn't been assigned. Do nothing for the
1628 	 * case.
1629 	 */
1630 	if (!pdn || pdn->pe_number == IODA_INVALID_PE)
1631 		return;
1632 
1633 	pe = &phb->ioda.pe_array[pdn->pe_number];
1634 	WARN_ON(get_dma_ops(&pdev->dev) != &dma_iommu_ops);
1635 	set_dma_offset(&pdev->dev, pe->tce_bypass_base);
1636 	set_iommu_table_base(&pdev->dev, pe->table_group.tables[0]);
1637 	/*
1638 	 * Note: iommu_add_device() will fail here as
1639 	 * for physical PE: the device is already added by now;
1640 	 * for virtual PE: sysfs entries are not ready yet and
1641 	 * tce_iommu_bus_notifier will add the device to a group later.
1642 	 */
1643 }
1644 
1645 static int pnv_pci_ioda_dma_set_mask(struct pci_dev *pdev, u64 dma_mask)
1646 {
1647 	struct pci_controller *hose = pci_bus_to_host(pdev->bus);
1648 	struct pnv_phb *phb = hose->private_data;
1649 	struct pci_dn *pdn = pci_get_pdn(pdev);
1650 	struct pnv_ioda_pe *pe;
1651 	uint64_t top;
1652 	bool bypass = false;
1653 	struct pci_dev *linked_npu_dev;
1654 	int i;
1655 
1656 	if (WARN_ON(!pdn || pdn->pe_number == IODA_INVALID_PE))
1657 		return -ENODEV;;
1658 
1659 	pe = &phb->ioda.pe_array[pdn->pe_number];
1660 	if (pe->tce_bypass_enabled) {
1661 		top = pe->tce_bypass_base + memblock_end_of_DRAM() - 1;
1662 		bypass = (dma_mask >= top);
1663 	}
1664 
1665 	if (bypass) {
1666 		dev_info(&pdev->dev, "Using 64-bit DMA iommu bypass\n");
1667 		set_dma_ops(&pdev->dev, &dma_direct_ops);
1668 	} else {
1669 		dev_info(&pdev->dev, "Using 32-bit DMA via iommu\n");
1670 		set_dma_ops(&pdev->dev, &dma_iommu_ops);
1671 	}
1672 	*pdev->dev.dma_mask = dma_mask;
1673 
1674 	/* Update peer npu devices */
1675 	if (pe->flags & PNV_IODA_PE_PEER)
1676 		for (i = 0; i < PNV_IODA_MAX_PEER_PES; i++) {
1677 			if (!pe->peers[i])
1678 				continue;
1679 
1680 			linked_npu_dev = pe->peers[i]->pdev;
1681 			if (dma_get_mask(&linked_npu_dev->dev) != dma_mask)
1682 				dma_set_mask(&linked_npu_dev->dev, dma_mask);
1683 		}
1684 
1685 	return 0;
1686 }
1687 
1688 static u64 pnv_pci_ioda_dma_get_required_mask(struct pci_dev *pdev)
1689 {
1690 	struct pci_controller *hose = pci_bus_to_host(pdev->bus);
1691 	struct pnv_phb *phb = hose->private_data;
1692 	struct pci_dn *pdn = pci_get_pdn(pdev);
1693 	struct pnv_ioda_pe *pe;
1694 	u64 end, mask;
1695 
1696 	if (WARN_ON(!pdn || pdn->pe_number == IODA_INVALID_PE))
1697 		return 0;
1698 
1699 	pe = &phb->ioda.pe_array[pdn->pe_number];
1700 	if (!pe->tce_bypass_enabled)
1701 		return __dma_get_required_mask(&pdev->dev);
1702 
1703 
1704 	end = pe->tce_bypass_base + memblock_end_of_DRAM();
1705 	mask = 1ULL << (fls64(end) - 1);
1706 	mask += mask - 1;
1707 
1708 	return mask;
1709 }
1710 
1711 static void pnv_ioda_setup_bus_dma(struct pnv_ioda_pe *pe,
1712 				   struct pci_bus *bus)
1713 {
1714 	struct pci_dev *dev;
1715 
1716 	list_for_each_entry(dev, &bus->devices, bus_list) {
1717 		set_iommu_table_base(&dev->dev, pe->table_group.tables[0]);
1718 		set_dma_offset(&dev->dev, pe->tce_bypass_base);
1719 		iommu_add_device(&dev->dev);
1720 
1721 		if ((pe->flags & PNV_IODA_PE_BUS_ALL) && dev->subordinate)
1722 			pnv_ioda_setup_bus_dma(pe, dev->subordinate);
1723 	}
1724 }
1725 
1726 static void pnv_pci_ioda1_tce_invalidate(struct iommu_table *tbl,
1727 		unsigned long index, unsigned long npages, bool rm)
1728 {
1729 	struct iommu_table_group_link *tgl = list_first_entry_or_null(
1730 			&tbl->it_group_list, struct iommu_table_group_link,
1731 			next);
1732 	struct pnv_ioda_pe *pe = container_of(tgl->table_group,
1733 			struct pnv_ioda_pe, table_group);
1734 	__be64 __iomem *invalidate = rm ?
1735 		(__be64 __iomem *)pe->phb->ioda.tce_inval_reg_phys :
1736 		pe->phb->ioda.tce_inval_reg;
1737 	unsigned long start, end, inc;
1738 	const unsigned shift = tbl->it_page_shift;
1739 
1740 	start = __pa(((__be64 *)tbl->it_base) + index - tbl->it_offset);
1741 	end = __pa(((__be64 *)tbl->it_base) + index - tbl->it_offset +
1742 			npages - 1);
1743 
1744 	/* BML uses this case for p6/p7/galaxy2: Shift addr and put in node */
1745 	if (tbl->it_busno) {
1746 		start <<= shift;
1747 		end <<= shift;
1748 		inc = 128ull << shift;
1749 		start |= tbl->it_busno;
1750 		end |= tbl->it_busno;
1751 	} else if (tbl->it_type & TCE_PCI_SWINV_PAIR) {
1752 		/* p7ioc-style invalidation, 2 TCEs per write */
1753 		start |= (1ull << 63);
1754 		end |= (1ull << 63);
1755 		inc = 16;
1756         } else {
1757 		/* Default (older HW) */
1758                 inc = 128;
1759 	}
1760 
1761         end |= inc - 1;	/* round up end to be different than start */
1762 
1763         mb(); /* Ensure above stores are visible */
1764         while (start <= end) {
1765 		if (rm)
1766 			__raw_rm_writeq(cpu_to_be64(start), invalidate);
1767 		else
1768 			__raw_writeq(cpu_to_be64(start), invalidate);
1769                 start += inc;
1770         }
1771 
1772 	/*
1773 	 * The iommu layer will do another mb() for us on build()
1774 	 * and we don't care on free()
1775 	 */
1776 }
1777 
1778 static int pnv_ioda1_tce_build(struct iommu_table *tbl, long index,
1779 		long npages, unsigned long uaddr,
1780 		enum dma_data_direction direction,
1781 		struct dma_attrs *attrs)
1782 {
1783 	int ret = pnv_tce_build(tbl, index, npages, uaddr, direction,
1784 			attrs);
1785 
1786 	if (!ret && (tbl->it_type & TCE_PCI_SWINV_CREATE))
1787 		pnv_pci_ioda1_tce_invalidate(tbl, index, npages, false);
1788 
1789 	return ret;
1790 }
1791 
1792 #ifdef CONFIG_IOMMU_API
1793 static int pnv_ioda1_tce_xchg(struct iommu_table *tbl, long index,
1794 		unsigned long *hpa, enum dma_data_direction *direction)
1795 {
1796 	long ret = pnv_tce_xchg(tbl, index, hpa, direction);
1797 
1798 	if (!ret && (tbl->it_type &
1799 			(TCE_PCI_SWINV_CREATE | TCE_PCI_SWINV_FREE)))
1800 		pnv_pci_ioda1_tce_invalidate(tbl, index, 1, false);
1801 
1802 	return ret;
1803 }
1804 #endif
1805 
1806 static void pnv_ioda1_tce_free(struct iommu_table *tbl, long index,
1807 		long npages)
1808 {
1809 	pnv_tce_free(tbl, index, npages);
1810 
1811 	if (tbl->it_type & TCE_PCI_SWINV_FREE)
1812 		pnv_pci_ioda1_tce_invalidate(tbl, index, npages, false);
1813 }
1814 
1815 static struct iommu_table_ops pnv_ioda1_iommu_ops = {
1816 	.set = pnv_ioda1_tce_build,
1817 #ifdef CONFIG_IOMMU_API
1818 	.exchange = pnv_ioda1_tce_xchg,
1819 #endif
1820 	.clear = pnv_ioda1_tce_free,
1821 	.get = pnv_tce_get,
1822 };
1823 
1824 static inline void pnv_pci_ioda2_tce_invalidate_entire(struct pnv_ioda_pe *pe)
1825 {
1826 	/* 01xb - invalidate TCEs that match the specified PE# */
1827 	unsigned long val = (0x4ull << 60) | (pe->pe_number & 0xFF);
1828 	struct pnv_phb *phb = pe->phb;
1829 	struct pnv_ioda_pe *npe;
1830 	int i;
1831 
1832 	if (!phb->ioda.tce_inval_reg)
1833 		return;
1834 
1835 	mb(); /* Ensure above stores are visible */
1836 	__raw_writeq(cpu_to_be64(val), phb->ioda.tce_inval_reg);
1837 
1838 	if (pe->flags & PNV_IODA_PE_PEER)
1839 		for (i = 0; i < PNV_IODA_MAX_PEER_PES; i++) {
1840 			npe = pe->peers[i];
1841 			if (!npe || npe->phb->type != PNV_PHB_NPU)
1842 				continue;
1843 
1844 			pnv_npu_tce_invalidate_entire(npe);
1845 		}
1846 }
1847 
1848 static void pnv_pci_ioda2_do_tce_invalidate(unsigned pe_number, bool rm,
1849 		__be64 __iomem *invalidate, unsigned shift,
1850 		unsigned long index, unsigned long npages)
1851 {
1852 	unsigned long start, end, inc;
1853 
1854 	/* We'll invalidate DMA address in PE scope */
1855 	start = 0x2ull << 60;
1856 	start |= (pe_number & 0xFF);
1857 	end = start;
1858 
1859 	/* Figure out the start, end and step */
1860 	start |= (index << shift);
1861 	end |= ((index + npages - 1) << shift);
1862 	inc = (0x1ull << shift);
1863 	mb();
1864 
1865 	while (start <= end) {
1866 		if (rm)
1867 			__raw_rm_writeq(cpu_to_be64(start), invalidate);
1868 		else
1869 			__raw_writeq(cpu_to_be64(start), invalidate);
1870 		start += inc;
1871 	}
1872 }
1873 
1874 static void pnv_pci_ioda2_tce_invalidate(struct iommu_table *tbl,
1875 		unsigned long index, unsigned long npages, bool rm)
1876 {
1877 	struct iommu_table_group_link *tgl;
1878 
1879 	list_for_each_entry_rcu(tgl, &tbl->it_group_list, next) {
1880 		struct pnv_ioda_pe *npe;
1881 		struct pnv_ioda_pe *pe = container_of(tgl->table_group,
1882 				struct pnv_ioda_pe, table_group);
1883 		__be64 __iomem *invalidate = rm ?
1884 			(__be64 __iomem *)pe->phb->ioda.tce_inval_reg_phys :
1885 			pe->phb->ioda.tce_inval_reg;
1886 		int i;
1887 
1888 		pnv_pci_ioda2_do_tce_invalidate(pe->pe_number, rm,
1889 			invalidate, tbl->it_page_shift,
1890 			index, npages);
1891 
1892 		if (pe->flags & PNV_IODA_PE_PEER)
1893 			/* Invalidate PEs using the same TCE table */
1894 			for (i = 0; i < PNV_IODA_MAX_PEER_PES; i++) {
1895 				npe = pe->peers[i];
1896 				if (!npe || npe->phb->type != PNV_PHB_NPU)
1897 					continue;
1898 
1899 				pnv_npu_tce_invalidate(npe, tbl, index,
1900 							npages, rm);
1901 			}
1902 	}
1903 }
1904 
1905 static int pnv_ioda2_tce_build(struct iommu_table *tbl, long index,
1906 		long npages, unsigned long uaddr,
1907 		enum dma_data_direction direction,
1908 		struct dma_attrs *attrs)
1909 {
1910 	int ret = pnv_tce_build(tbl, index, npages, uaddr, direction,
1911 			attrs);
1912 
1913 	if (!ret && (tbl->it_type & TCE_PCI_SWINV_CREATE))
1914 		pnv_pci_ioda2_tce_invalidate(tbl, index, npages, false);
1915 
1916 	return ret;
1917 }
1918 
1919 #ifdef CONFIG_IOMMU_API
1920 static int pnv_ioda2_tce_xchg(struct iommu_table *tbl, long index,
1921 		unsigned long *hpa, enum dma_data_direction *direction)
1922 {
1923 	long ret = pnv_tce_xchg(tbl, index, hpa, direction);
1924 
1925 	if (!ret && (tbl->it_type &
1926 			(TCE_PCI_SWINV_CREATE | TCE_PCI_SWINV_FREE)))
1927 		pnv_pci_ioda2_tce_invalidate(tbl, index, 1, false);
1928 
1929 	return ret;
1930 }
1931 #endif
1932 
1933 static void pnv_ioda2_tce_free(struct iommu_table *tbl, long index,
1934 		long npages)
1935 {
1936 	pnv_tce_free(tbl, index, npages);
1937 
1938 	if (tbl->it_type & TCE_PCI_SWINV_FREE)
1939 		pnv_pci_ioda2_tce_invalidate(tbl, index, npages, false);
1940 }
1941 
1942 static void pnv_ioda2_table_free(struct iommu_table *tbl)
1943 {
1944 	pnv_pci_ioda2_table_free_pages(tbl);
1945 	iommu_free_table(tbl, "pnv");
1946 }
1947 
1948 static struct iommu_table_ops pnv_ioda2_iommu_ops = {
1949 	.set = pnv_ioda2_tce_build,
1950 #ifdef CONFIG_IOMMU_API
1951 	.exchange = pnv_ioda2_tce_xchg,
1952 #endif
1953 	.clear = pnv_ioda2_tce_free,
1954 	.get = pnv_tce_get,
1955 	.free = pnv_ioda2_table_free,
1956 };
1957 
1958 static void pnv_pci_ioda_setup_dma_pe(struct pnv_phb *phb,
1959 				      struct pnv_ioda_pe *pe, unsigned int base,
1960 				      unsigned int segs)
1961 {
1962 
1963 	struct page *tce_mem = NULL;
1964 	struct iommu_table *tbl;
1965 	unsigned int i;
1966 	int64_t rc;
1967 	void *addr;
1968 
1969 	/* XXX FIXME: Handle 64-bit only DMA devices */
1970 	/* XXX FIXME: Provide 64-bit DMA facilities & non-4K TCE tables etc.. */
1971 	/* XXX FIXME: Allocate multi-level tables on PHB3 */
1972 
1973 	/* We shouldn't already have a 32-bit DMA associated */
1974 	if (WARN_ON(pe->tce32_seg >= 0))
1975 		return;
1976 
1977 	tbl = pnv_pci_table_alloc(phb->hose->node);
1978 	iommu_register_group(&pe->table_group, phb->hose->global_number,
1979 			pe->pe_number);
1980 	pnv_pci_link_table_and_group(phb->hose->node, 0, tbl, &pe->table_group);
1981 
1982 	/* Grab a 32-bit TCE table */
1983 	pe->tce32_seg = base;
1984 	pe_info(pe, " Setting up 32-bit TCE table at %08x..%08x\n",
1985 		(base << 28), ((base + segs) << 28) - 1);
1986 
1987 	/* XXX Currently, we allocate one big contiguous table for the
1988 	 * TCEs. We only really need one chunk per 256M of TCE space
1989 	 * (ie per segment) but that's an optimization for later, it
1990 	 * requires some added smarts with our get/put_tce implementation
1991 	 */
1992 	tce_mem = alloc_pages_node(phb->hose->node, GFP_KERNEL,
1993 				   get_order(TCE32_TABLE_SIZE * segs));
1994 	if (!tce_mem) {
1995 		pe_err(pe, " Failed to allocate a 32-bit TCE memory\n");
1996 		goto fail;
1997 	}
1998 	addr = page_address(tce_mem);
1999 	memset(addr, 0, TCE32_TABLE_SIZE * segs);
2000 
2001 	/* Configure HW */
2002 	for (i = 0; i < segs; i++) {
2003 		rc = opal_pci_map_pe_dma_window(phb->opal_id,
2004 					      pe->pe_number,
2005 					      base + i, 1,
2006 					      __pa(addr) + TCE32_TABLE_SIZE * i,
2007 					      TCE32_TABLE_SIZE, 0x1000);
2008 		if (rc) {
2009 			pe_err(pe, " Failed to configure 32-bit TCE table,"
2010 			       " err %ld\n", rc);
2011 			goto fail;
2012 		}
2013 	}
2014 
2015 	/* Setup linux iommu table */
2016 	pnv_pci_setup_iommu_table(tbl, addr, TCE32_TABLE_SIZE * segs,
2017 				  base << 28, IOMMU_PAGE_SHIFT_4K);
2018 
2019 	/* OPAL variant of P7IOC SW invalidated TCEs */
2020 	if (phb->ioda.tce_inval_reg)
2021 		tbl->it_type |= (TCE_PCI_SWINV_CREATE |
2022 				 TCE_PCI_SWINV_FREE   |
2023 				 TCE_PCI_SWINV_PAIR);
2024 
2025 	tbl->it_ops = &pnv_ioda1_iommu_ops;
2026 	pe->table_group.tce32_start = tbl->it_offset << tbl->it_page_shift;
2027 	pe->table_group.tce32_size = tbl->it_size << tbl->it_page_shift;
2028 	iommu_init_table(tbl, phb->hose->node);
2029 
2030 	if (pe->flags & PNV_IODA_PE_DEV) {
2031 		/*
2032 		 * Setting table base here only for carrying iommu_group
2033 		 * further down to let iommu_add_device() do the job.
2034 		 * pnv_pci_ioda_dma_dev_setup will override it later anyway.
2035 		 */
2036 		set_iommu_table_base(&pe->pdev->dev, tbl);
2037 		iommu_add_device(&pe->pdev->dev);
2038 	} else if (pe->flags & (PNV_IODA_PE_BUS | PNV_IODA_PE_BUS_ALL))
2039 		pnv_ioda_setup_bus_dma(pe, pe->pbus);
2040 
2041 	return;
2042  fail:
2043 	/* XXX Failure: Try to fallback to 64-bit only ? */
2044 	if (pe->tce32_seg >= 0)
2045 		pe->tce32_seg = -1;
2046 	if (tce_mem)
2047 		__free_pages(tce_mem, get_order(TCE32_TABLE_SIZE * segs));
2048 	if (tbl) {
2049 		pnv_pci_unlink_table_and_group(tbl, &pe->table_group);
2050 		iommu_free_table(tbl, "pnv");
2051 	}
2052 }
2053 
2054 static long pnv_pci_ioda2_set_window(struct iommu_table_group *table_group,
2055 		int num, struct iommu_table *tbl)
2056 {
2057 	struct pnv_ioda_pe *pe = container_of(table_group, struct pnv_ioda_pe,
2058 			table_group);
2059 	struct pnv_phb *phb = pe->phb;
2060 	int64_t rc;
2061 	const unsigned long size = tbl->it_indirect_levels ?
2062 			tbl->it_level_size : tbl->it_size;
2063 	const __u64 start_addr = tbl->it_offset << tbl->it_page_shift;
2064 	const __u64 win_size = tbl->it_size << tbl->it_page_shift;
2065 
2066 	pe_info(pe, "Setting up window#%d %llx..%llx pg=%x\n", num,
2067 			start_addr, start_addr + win_size - 1,
2068 			IOMMU_PAGE_SIZE(tbl));
2069 
2070 	/*
2071 	 * Map TCE table through TVT. The TVE index is the PE number
2072 	 * shifted by 1 bit for 32-bits DMA space.
2073 	 */
2074 	rc = opal_pci_map_pe_dma_window(phb->opal_id,
2075 			pe->pe_number,
2076 			(pe->pe_number << 1) + num,
2077 			tbl->it_indirect_levels + 1,
2078 			__pa(tbl->it_base),
2079 			size << 3,
2080 			IOMMU_PAGE_SIZE(tbl));
2081 	if (rc) {
2082 		pe_err(pe, "Failed to configure TCE table, err %ld\n", rc);
2083 		return rc;
2084 	}
2085 
2086 	pnv_pci_link_table_and_group(phb->hose->node, num,
2087 			tbl, &pe->table_group);
2088 	pnv_pci_ioda2_tce_invalidate_entire(pe);
2089 
2090 	return 0;
2091 }
2092 
2093 static void pnv_pci_ioda2_set_bypass(struct pnv_ioda_pe *pe, bool enable)
2094 {
2095 	uint16_t window_id = (pe->pe_number << 1 ) + 1;
2096 	int64_t rc;
2097 
2098 	pe_info(pe, "%sabling 64-bit DMA bypass\n", enable ? "En" : "Dis");
2099 	if (enable) {
2100 		phys_addr_t top = memblock_end_of_DRAM();
2101 
2102 		top = roundup_pow_of_two(top);
2103 		rc = opal_pci_map_pe_dma_window_real(pe->phb->opal_id,
2104 						     pe->pe_number,
2105 						     window_id,
2106 						     pe->tce_bypass_base,
2107 						     top);
2108 	} else {
2109 		rc = opal_pci_map_pe_dma_window_real(pe->phb->opal_id,
2110 						     pe->pe_number,
2111 						     window_id,
2112 						     pe->tce_bypass_base,
2113 						     0);
2114 	}
2115 	if (rc)
2116 		pe_err(pe, "OPAL error %lld configuring bypass window\n", rc);
2117 	else
2118 		pe->tce_bypass_enabled = enable;
2119 }
2120 
2121 static long pnv_pci_ioda2_table_alloc_pages(int nid, __u64 bus_offset,
2122 		__u32 page_shift, __u64 window_size, __u32 levels,
2123 		struct iommu_table *tbl);
2124 
2125 static long pnv_pci_ioda2_create_table(struct iommu_table_group *table_group,
2126 		int num, __u32 page_shift, __u64 window_size, __u32 levels,
2127 		struct iommu_table **ptbl)
2128 {
2129 	struct pnv_ioda_pe *pe = container_of(table_group, struct pnv_ioda_pe,
2130 			table_group);
2131 	int nid = pe->phb->hose->node;
2132 	__u64 bus_offset = num ? pe->tce_bypass_base : table_group->tce32_start;
2133 	long ret;
2134 	struct iommu_table *tbl;
2135 
2136 	tbl = pnv_pci_table_alloc(nid);
2137 	if (!tbl)
2138 		return -ENOMEM;
2139 
2140 	ret = pnv_pci_ioda2_table_alloc_pages(nid,
2141 			bus_offset, page_shift, window_size,
2142 			levels, tbl);
2143 	if (ret) {
2144 		iommu_free_table(tbl, "pnv");
2145 		return ret;
2146 	}
2147 
2148 	tbl->it_ops = &pnv_ioda2_iommu_ops;
2149 	if (pe->phb->ioda.tce_inval_reg)
2150 		tbl->it_type |= (TCE_PCI_SWINV_CREATE | TCE_PCI_SWINV_FREE);
2151 
2152 	*ptbl = tbl;
2153 
2154 	return 0;
2155 }
2156 
2157 static long pnv_pci_ioda2_setup_default_config(struct pnv_ioda_pe *pe)
2158 {
2159 	struct iommu_table *tbl = NULL;
2160 	long rc;
2161 
2162 	/*
2163 	 * crashkernel= specifies the kdump kernel's maximum memory at
2164 	 * some offset and there is no guaranteed the result is a power
2165 	 * of 2, which will cause errors later.
2166 	 */
2167 	const u64 max_memory = __rounddown_pow_of_two(memory_hotplug_max());
2168 
2169 	/*
2170 	 * In memory constrained environments, e.g. kdump kernel, the
2171 	 * DMA window can be larger than available memory, which will
2172 	 * cause errors later.
2173 	 */
2174 	const u64 window_size = min((u64)pe->table_group.tce32_size, max_memory);
2175 
2176 	rc = pnv_pci_ioda2_create_table(&pe->table_group, 0,
2177 			IOMMU_PAGE_SHIFT_4K,
2178 			window_size,
2179 			POWERNV_IOMMU_DEFAULT_LEVELS, &tbl);
2180 	if (rc) {
2181 		pe_err(pe, "Failed to create 32-bit TCE table, err %ld",
2182 				rc);
2183 		return rc;
2184 	}
2185 
2186 	iommu_init_table(tbl, pe->phb->hose->node);
2187 
2188 	rc = pnv_pci_ioda2_set_window(&pe->table_group, 0, tbl);
2189 	if (rc) {
2190 		pe_err(pe, "Failed to configure 32-bit TCE table, err %ld\n",
2191 				rc);
2192 		pnv_ioda2_table_free(tbl);
2193 		return rc;
2194 	}
2195 
2196 	if (!pnv_iommu_bypass_disabled)
2197 		pnv_pci_ioda2_set_bypass(pe, true);
2198 
2199 	/* OPAL variant of PHB3 invalidated TCEs */
2200 	if (pe->phb->ioda.tce_inval_reg)
2201 		tbl->it_type |= (TCE_PCI_SWINV_CREATE | TCE_PCI_SWINV_FREE);
2202 
2203 	/*
2204 	 * Setting table base here only for carrying iommu_group
2205 	 * further down to let iommu_add_device() do the job.
2206 	 * pnv_pci_ioda_dma_dev_setup will override it later anyway.
2207 	 */
2208 	if (pe->flags & PNV_IODA_PE_DEV)
2209 		set_iommu_table_base(&pe->pdev->dev, tbl);
2210 
2211 	return 0;
2212 }
2213 
2214 #if defined(CONFIG_IOMMU_API) || defined(CONFIG_PCI_IOV)
2215 static long pnv_pci_ioda2_unset_window(struct iommu_table_group *table_group,
2216 		int num)
2217 {
2218 	struct pnv_ioda_pe *pe = container_of(table_group, struct pnv_ioda_pe,
2219 			table_group);
2220 	struct pnv_phb *phb = pe->phb;
2221 	long ret;
2222 
2223 	pe_info(pe, "Removing DMA window #%d\n", num);
2224 
2225 	ret = opal_pci_map_pe_dma_window(phb->opal_id, pe->pe_number,
2226 			(pe->pe_number << 1) + num,
2227 			0/* levels */, 0/* table address */,
2228 			0/* table size */, 0/* page size */);
2229 	if (ret)
2230 		pe_warn(pe, "Unmapping failed, ret = %ld\n", ret);
2231 	else
2232 		pnv_pci_ioda2_tce_invalidate_entire(pe);
2233 
2234 	pnv_pci_unlink_table_and_group(table_group->tables[num], table_group);
2235 
2236 	return ret;
2237 }
2238 #endif
2239 
2240 #ifdef CONFIG_IOMMU_API
2241 static unsigned long pnv_pci_ioda2_get_table_size(__u32 page_shift,
2242 		__u64 window_size, __u32 levels)
2243 {
2244 	unsigned long bytes = 0;
2245 	const unsigned window_shift = ilog2(window_size);
2246 	unsigned entries_shift = window_shift - page_shift;
2247 	unsigned table_shift = entries_shift + 3;
2248 	unsigned long tce_table_size = max(0x1000UL, 1UL << table_shift);
2249 	unsigned long direct_table_size;
2250 
2251 	if (!levels || (levels > POWERNV_IOMMU_MAX_LEVELS) ||
2252 			(window_size > memory_hotplug_max()) ||
2253 			!is_power_of_2(window_size))
2254 		return 0;
2255 
2256 	/* Calculate a direct table size from window_size and levels */
2257 	entries_shift = (entries_shift + levels - 1) / levels;
2258 	table_shift = entries_shift + 3;
2259 	table_shift = max_t(unsigned, table_shift, PAGE_SHIFT);
2260 	direct_table_size =  1UL << table_shift;
2261 
2262 	for ( ; levels; --levels) {
2263 		bytes += _ALIGN_UP(tce_table_size, direct_table_size);
2264 
2265 		tce_table_size /= direct_table_size;
2266 		tce_table_size <<= 3;
2267 		tce_table_size = _ALIGN_UP(tce_table_size, direct_table_size);
2268 	}
2269 
2270 	return bytes;
2271 }
2272 
2273 static void pnv_ioda2_take_ownership(struct iommu_table_group *table_group)
2274 {
2275 	struct pnv_ioda_pe *pe = container_of(table_group, struct pnv_ioda_pe,
2276 						table_group);
2277 	/* Store @tbl as pnv_pci_ioda2_unset_window() resets it */
2278 	struct iommu_table *tbl = pe->table_group.tables[0];
2279 
2280 	pnv_pci_ioda2_set_bypass(pe, false);
2281 	pnv_pci_ioda2_unset_window(&pe->table_group, 0);
2282 	pnv_ioda2_table_free(tbl);
2283 }
2284 
2285 static void pnv_ioda2_release_ownership(struct iommu_table_group *table_group)
2286 {
2287 	struct pnv_ioda_pe *pe = container_of(table_group, struct pnv_ioda_pe,
2288 						table_group);
2289 
2290 	pnv_pci_ioda2_setup_default_config(pe);
2291 }
2292 
2293 static struct iommu_table_group_ops pnv_pci_ioda2_ops = {
2294 	.get_table_size = pnv_pci_ioda2_get_table_size,
2295 	.create_table = pnv_pci_ioda2_create_table,
2296 	.set_window = pnv_pci_ioda2_set_window,
2297 	.unset_window = pnv_pci_ioda2_unset_window,
2298 	.take_ownership = pnv_ioda2_take_ownership,
2299 	.release_ownership = pnv_ioda2_release_ownership,
2300 };
2301 #endif
2302 
2303 static void pnv_pci_ioda_setup_opal_tce_kill(struct pnv_phb *phb)
2304 {
2305 	const __be64 *swinvp;
2306 
2307 	/* OPAL variant of PHB3 invalidated TCEs */
2308 	swinvp = of_get_property(phb->hose->dn, "ibm,opal-tce-kill", NULL);
2309 	if (!swinvp)
2310 		return;
2311 
2312 	phb->ioda.tce_inval_reg_phys = be64_to_cpup(swinvp);
2313 	phb->ioda.tce_inval_reg = ioremap(phb->ioda.tce_inval_reg_phys, 8);
2314 }
2315 
2316 static __be64 *pnv_pci_ioda2_table_do_alloc_pages(int nid, unsigned shift,
2317 		unsigned levels, unsigned long limit,
2318 		unsigned long *current_offset, unsigned long *total_allocated)
2319 {
2320 	struct page *tce_mem = NULL;
2321 	__be64 *addr, *tmp;
2322 	unsigned order = max_t(unsigned, shift, PAGE_SHIFT) - PAGE_SHIFT;
2323 	unsigned long allocated = 1UL << (order + PAGE_SHIFT);
2324 	unsigned entries = 1UL << (shift - 3);
2325 	long i;
2326 
2327 	tce_mem = alloc_pages_node(nid, GFP_KERNEL, order);
2328 	if (!tce_mem) {
2329 		pr_err("Failed to allocate a TCE memory, order=%d\n", order);
2330 		return NULL;
2331 	}
2332 	addr = page_address(tce_mem);
2333 	memset(addr, 0, allocated);
2334 	*total_allocated += allocated;
2335 
2336 	--levels;
2337 	if (!levels) {
2338 		*current_offset += allocated;
2339 		return addr;
2340 	}
2341 
2342 	for (i = 0; i < entries; ++i) {
2343 		tmp = pnv_pci_ioda2_table_do_alloc_pages(nid, shift,
2344 				levels, limit, current_offset, total_allocated);
2345 		if (!tmp)
2346 			break;
2347 
2348 		addr[i] = cpu_to_be64(__pa(tmp) |
2349 				TCE_PCI_READ | TCE_PCI_WRITE);
2350 
2351 		if (*current_offset >= limit)
2352 			break;
2353 	}
2354 
2355 	return addr;
2356 }
2357 
2358 static void pnv_pci_ioda2_table_do_free_pages(__be64 *addr,
2359 		unsigned long size, unsigned level);
2360 
2361 static long pnv_pci_ioda2_table_alloc_pages(int nid, __u64 bus_offset,
2362 		__u32 page_shift, __u64 window_size, __u32 levels,
2363 		struct iommu_table *tbl)
2364 {
2365 	void *addr;
2366 	unsigned long offset = 0, level_shift, total_allocated = 0;
2367 	const unsigned window_shift = ilog2(window_size);
2368 	unsigned entries_shift = window_shift - page_shift;
2369 	unsigned table_shift = max_t(unsigned, entries_shift + 3, PAGE_SHIFT);
2370 	const unsigned long tce_table_size = 1UL << table_shift;
2371 
2372 	if (!levels || (levels > POWERNV_IOMMU_MAX_LEVELS))
2373 		return -EINVAL;
2374 
2375 	if ((window_size > memory_hotplug_max()) || !is_power_of_2(window_size))
2376 		return -EINVAL;
2377 
2378 	/* Adjust direct table size from window_size and levels */
2379 	entries_shift = (entries_shift + levels - 1) / levels;
2380 	level_shift = entries_shift + 3;
2381 	level_shift = max_t(unsigned, level_shift, PAGE_SHIFT);
2382 
2383 	/* Allocate TCE table */
2384 	addr = pnv_pci_ioda2_table_do_alloc_pages(nid, level_shift,
2385 			levels, tce_table_size, &offset, &total_allocated);
2386 
2387 	/* addr==NULL means that the first level allocation failed */
2388 	if (!addr)
2389 		return -ENOMEM;
2390 
2391 	/*
2392 	 * First level was allocated but some lower level failed as
2393 	 * we did not allocate as much as we wanted,
2394 	 * release partially allocated table.
2395 	 */
2396 	if (offset < tce_table_size) {
2397 		pnv_pci_ioda2_table_do_free_pages(addr,
2398 				1ULL << (level_shift - 3), levels - 1);
2399 		return -ENOMEM;
2400 	}
2401 
2402 	/* Setup linux iommu table */
2403 	pnv_pci_setup_iommu_table(tbl, addr, tce_table_size, bus_offset,
2404 			page_shift);
2405 	tbl->it_level_size = 1ULL << (level_shift - 3);
2406 	tbl->it_indirect_levels = levels - 1;
2407 	tbl->it_allocated_size = total_allocated;
2408 
2409 	pr_devel("Created TCE table: ws=%08llx ts=%lx @%08llx\n",
2410 			window_size, tce_table_size, bus_offset);
2411 
2412 	return 0;
2413 }
2414 
2415 static void pnv_pci_ioda2_table_do_free_pages(__be64 *addr,
2416 		unsigned long size, unsigned level)
2417 {
2418 	const unsigned long addr_ul = (unsigned long) addr &
2419 			~(TCE_PCI_READ | TCE_PCI_WRITE);
2420 
2421 	if (level) {
2422 		long i;
2423 		u64 *tmp = (u64 *) addr_ul;
2424 
2425 		for (i = 0; i < size; ++i) {
2426 			unsigned long hpa = be64_to_cpu(tmp[i]);
2427 
2428 			if (!(hpa & (TCE_PCI_READ | TCE_PCI_WRITE)))
2429 				continue;
2430 
2431 			pnv_pci_ioda2_table_do_free_pages(__va(hpa), size,
2432 					level - 1);
2433 		}
2434 	}
2435 
2436 	free_pages(addr_ul, get_order(size << 3));
2437 }
2438 
2439 static void pnv_pci_ioda2_table_free_pages(struct iommu_table *tbl)
2440 {
2441 	const unsigned long size = tbl->it_indirect_levels ?
2442 			tbl->it_level_size : tbl->it_size;
2443 
2444 	if (!tbl->it_size)
2445 		return;
2446 
2447 	pnv_pci_ioda2_table_do_free_pages((__be64 *)tbl->it_base, size,
2448 			tbl->it_indirect_levels);
2449 }
2450 
2451 static void pnv_pci_ioda2_setup_dma_pe(struct pnv_phb *phb,
2452 				       struct pnv_ioda_pe *pe)
2453 {
2454 	int64_t rc;
2455 
2456 	/* We shouldn't already have a 32-bit DMA associated */
2457 	if (WARN_ON(pe->tce32_seg >= 0))
2458 		return;
2459 
2460 	/* TVE #1 is selected by PCI address bit 59 */
2461 	pe->tce_bypass_base = 1ull << 59;
2462 
2463 	iommu_register_group(&pe->table_group, phb->hose->global_number,
2464 			pe->pe_number);
2465 
2466 	/* The PE will reserve all possible 32-bits space */
2467 	pe->tce32_seg = 0;
2468 	pe_info(pe, "Setting up 32-bit TCE table at 0..%08x\n",
2469 		phb->ioda.m32_pci_base);
2470 
2471 	/* Setup linux iommu table */
2472 	pe->table_group.tce32_start = 0;
2473 	pe->table_group.tce32_size = phb->ioda.m32_pci_base;
2474 	pe->table_group.max_dynamic_windows_supported =
2475 			IOMMU_TABLE_GROUP_MAX_TABLES;
2476 	pe->table_group.max_levels = POWERNV_IOMMU_MAX_LEVELS;
2477 	pe->table_group.pgsizes = SZ_4K | SZ_64K | SZ_16M;
2478 #ifdef CONFIG_IOMMU_API
2479 	pe->table_group.ops = &pnv_pci_ioda2_ops;
2480 #endif
2481 
2482 	rc = pnv_pci_ioda2_setup_default_config(pe);
2483 	if (rc) {
2484 		if (pe->tce32_seg >= 0)
2485 			pe->tce32_seg = -1;
2486 		return;
2487 	}
2488 
2489 	if (pe->flags & PNV_IODA_PE_DEV)
2490 		iommu_add_device(&pe->pdev->dev);
2491 	else if (pe->flags & (PNV_IODA_PE_BUS | PNV_IODA_PE_BUS_ALL))
2492 		pnv_ioda_setup_bus_dma(pe, pe->pbus);
2493 }
2494 
2495 static void pnv_ioda_setup_dma(struct pnv_phb *phb)
2496 {
2497 	struct pci_controller *hose = phb->hose;
2498 	unsigned int residual, remaining, segs, tw, base;
2499 	struct pnv_ioda_pe *pe;
2500 
2501 	/* If we have more PE# than segments available, hand out one
2502 	 * per PE until we run out and let the rest fail. If not,
2503 	 * then we assign at least one segment per PE, plus more based
2504 	 * on the amount of devices under that PE
2505 	 */
2506 	if (phb->ioda.dma_pe_count > phb->ioda.tce32_count)
2507 		residual = 0;
2508 	else
2509 		residual = phb->ioda.tce32_count -
2510 			phb->ioda.dma_pe_count;
2511 
2512 	pr_info("PCI: Domain %04x has %ld available 32-bit DMA segments\n",
2513 		hose->global_number, phb->ioda.tce32_count);
2514 	pr_info("PCI: %d PE# for a total weight of %d\n",
2515 		phb->ioda.dma_pe_count, phb->ioda.dma_weight);
2516 
2517 	pnv_pci_ioda_setup_opal_tce_kill(phb);
2518 
2519 	/* Walk our PE list and configure their DMA segments, hand them
2520 	 * out one base segment plus any residual segments based on
2521 	 * weight
2522 	 */
2523 	remaining = phb->ioda.tce32_count;
2524 	tw = phb->ioda.dma_weight;
2525 	base = 0;
2526 	list_for_each_entry(pe, &phb->ioda.pe_dma_list, dma_link) {
2527 		if (!pe->dma_weight)
2528 			continue;
2529 		if (!remaining) {
2530 			pe_warn(pe, "No DMA32 resources available\n");
2531 			continue;
2532 		}
2533 		segs = 1;
2534 		if (residual) {
2535 			segs += ((pe->dma_weight * residual)  + (tw / 2)) / tw;
2536 			if (segs > remaining)
2537 				segs = remaining;
2538 		}
2539 
2540 		/*
2541 		 * For IODA2 compliant PHB3, we needn't care about the weight.
2542 		 * The all available 32-bits DMA space will be assigned to
2543 		 * the specific PE.
2544 		 */
2545 		if (phb->type == PNV_PHB_IODA1) {
2546 			pe_info(pe, "DMA weight %d, assigned %d DMA32 segments\n",
2547 				pe->dma_weight, segs);
2548 			pnv_pci_ioda_setup_dma_pe(phb, pe, base, segs);
2549 		} else if (phb->type == PNV_PHB_IODA2) {
2550 			pe_info(pe, "Assign DMA32 space\n");
2551 			segs = 0;
2552 			pnv_pci_ioda2_setup_dma_pe(phb, pe);
2553 		} else if (phb->type == PNV_PHB_NPU) {
2554 			/*
2555 			 * We initialise the DMA space for an NPU PHB
2556 			 * after setup of the PHB is complete as we
2557 			 * point the NPU TVT to the the same location
2558 			 * as the PHB3 TVT.
2559 			 */
2560 		}
2561 
2562 		remaining -= segs;
2563 		base += segs;
2564 	}
2565 }
2566 
2567 #ifdef CONFIG_PCI_MSI
2568 static void pnv_ioda2_msi_eoi(struct irq_data *d)
2569 {
2570 	unsigned int hw_irq = (unsigned int)irqd_to_hwirq(d);
2571 	struct irq_chip *chip = irq_data_get_irq_chip(d);
2572 	struct pnv_phb *phb = container_of(chip, struct pnv_phb,
2573 					   ioda.irq_chip);
2574 	int64_t rc;
2575 
2576 	rc = opal_pci_msi_eoi(phb->opal_id, hw_irq);
2577 	WARN_ON_ONCE(rc);
2578 
2579 	icp_native_eoi(d);
2580 }
2581 
2582 
2583 static void set_msi_irq_chip(struct pnv_phb *phb, unsigned int virq)
2584 {
2585 	struct irq_data *idata;
2586 	struct irq_chip *ichip;
2587 
2588 	if (phb->type != PNV_PHB_IODA2)
2589 		return;
2590 
2591 	if (!phb->ioda.irq_chip_init) {
2592 		/*
2593 		 * First time we setup an MSI IRQ, we need to setup the
2594 		 * corresponding IRQ chip to route correctly.
2595 		 */
2596 		idata = irq_get_irq_data(virq);
2597 		ichip = irq_data_get_irq_chip(idata);
2598 		phb->ioda.irq_chip_init = 1;
2599 		phb->ioda.irq_chip = *ichip;
2600 		phb->ioda.irq_chip.irq_eoi = pnv_ioda2_msi_eoi;
2601 	}
2602 	irq_set_chip(virq, &phb->ioda.irq_chip);
2603 }
2604 
2605 #ifdef CONFIG_CXL_BASE
2606 
2607 struct device_node *pnv_pci_get_phb_node(struct pci_dev *dev)
2608 {
2609 	struct pci_controller *hose = pci_bus_to_host(dev->bus);
2610 
2611 	return of_node_get(hose->dn);
2612 }
2613 EXPORT_SYMBOL(pnv_pci_get_phb_node);
2614 
2615 int pnv_phb_to_cxl_mode(struct pci_dev *dev, uint64_t mode)
2616 {
2617 	struct pci_controller *hose = pci_bus_to_host(dev->bus);
2618 	struct pnv_phb *phb = hose->private_data;
2619 	struct pnv_ioda_pe *pe;
2620 	int rc;
2621 
2622 	pe = pnv_ioda_get_pe(dev);
2623 	if (!pe)
2624 		return -ENODEV;
2625 
2626 	pe_info(pe, "Switching PHB to CXL\n");
2627 
2628 	rc = opal_pci_set_phb_cxl_mode(phb->opal_id, mode, pe->pe_number);
2629 	if (rc)
2630 		dev_err(&dev->dev, "opal_pci_set_phb_cxl_mode failed: %i\n", rc);
2631 
2632 	return rc;
2633 }
2634 EXPORT_SYMBOL(pnv_phb_to_cxl_mode);
2635 
2636 /* Find PHB for cxl dev and allocate MSI hwirqs?
2637  * Returns the absolute hardware IRQ number
2638  */
2639 int pnv_cxl_alloc_hwirqs(struct pci_dev *dev, int num)
2640 {
2641 	struct pci_controller *hose = pci_bus_to_host(dev->bus);
2642 	struct pnv_phb *phb = hose->private_data;
2643 	int hwirq = msi_bitmap_alloc_hwirqs(&phb->msi_bmp, num);
2644 
2645 	if (hwirq < 0) {
2646 		dev_warn(&dev->dev, "Failed to find a free MSI\n");
2647 		return -ENOSPC;
2648 	}
2649 
2650 	return phb->msi_base + hwirq;
2651 }
2652 EXPORT_SYMBOL(pnv_cxl_alloc_hwirqs);
2653 
2654 void pnv_cxl_release_hwirqs(struct pci_dev *dev, int hwirq, int num)
2655 {
2656 	struct pci_controller *hose = pci_bus_to_host(dev->bus);
2657 	struct pnv_phb *phb = hose->private_data;
2658 
2659 	msi_bitmap_free_hwirqs(&phb->msi_bmp, hwirq - phb->msi_base, num);
2660 }
2661 EXPORT_SYMBOL(pnv_cxl_release_hwirqs);
2662 
2663 void pnv_cxl_release_hwirq_ranges(struct cxl_irq_ranges *irqs,
2664 				  struct pci_dev *dev)
2665 {
2666 	struct pci_controller *hose = pci_bus_to_host(dev->bus);
2667 	struct pnv_phb *phb = hose->private_data;
2668 	int i, hwirq;
2669 
2670 	for (i = 1; i < CXL_IRQ_RANGES; i++) {
2671 		if (!irqs->range[i])
2672 			continue;
2673 		pr_devel("cxl release irq range 0x%x: offset: 0x%lx  limit: %ld\n",
2674 			 i, irqs->offset[i],
2675 			 irqs->range[i]);
2676 		hwirq = irqs->offset[i] - phb->msi_base;
2677 		msi_bitmap_free_hwirqs(&phb->msi_bmp, hwirq,
2678 				       irqs->range[i]);
2679 	}
2680 }
2681 EXPORT_SYMBOL(pnv_cxl_release_hwirq_ranges);
2682 
2683 int pnv_cxl_alloc_hwirq_ranges(struct cxl_irq_ranges *irqs,
2684 			       struct pci_dev *dev, int num)
2685 {
2686 	struct pci_controller *hose = pci_bus_to_host(dev->bus);
2687 	struct pnv_phb *phb = hose->private_data;
2688 	int i, hwirq, try;
2689 
2690 	memset(irqs, 0, sizeof(struct cxl_irq_ranges));
2691 
2692 	/* 0 is reserved for the multiplexed PSL DSI interrupt */
2693 	for (i = 1; i < CXL_IRQ_RANGES && num; i++) {
2694 		try = num;
2695 		while (try) {
2696 			hwirq = msi_bitmap_alloc_hwirqs(&phb->msi_bmp, try);
2697 			if (hwirq >= 0)
2698 				break;
2699 			try /= 2;
2700 		}
2701 		if (!try)
2702 			goto fail;
2703 
2704 		irqs->offset[i] = phb->msi_base + hwirq;
2705 		irqs->range[i] = try;
2706 		pr_devel("cxl alloc irq range 0x%x: offset: 0x%lx  limit: %li\n",
2707 			 i, irqs->offset[i], irqs->range[i]);
2708 		num -= try;
2709 	}
2710 	if (num)
2711 		goto fail;
2712 
2713 	return 0;
2714 fail:
2715 	pnv_cxl_release_hwirq_ranges(irqs, dev);
2716 	return -ENOSPC;
2717 }
2718 EXPORT_SYMBOL(pnv_cxl_alloc_hwirq_ranges);
2719 
2720 int pnv_cxl_get_irq_count(struct pci_dev *dev)
2721 {
2722 	struct pci_controller *hose = pci_bus_to_host(dev->bus);
2723 	struct pnv_phb *phb = hose->private_data;
2724 
2725 	return phb->msi_bmp.irq_count;
2726 }
2727 EXPORT_SYMBOL(pnv_cxl_get_irq_count);
2728 
2729 int pnv_cxl_ioda_msi_setup(struct pci_dev *dev, unsigned int hwirq,
2730 			   unsigned int virq)
2731 {
2732 	struct pci_controller *hose = pci_bus_to_host(dev->bus);
2733 	struct pnv_phb *phb = hose->private_data;
2734 	unsigned int xive_num = hwirq - phb->msi_base;
2735 	struct pnv_ioda_pe *pe;
2736 	int rc;
2737 
2738 	if (!(pe = pnv_ioda_get_pe(dev)))
2739 		return -ENODEV;
2740 
2741 	/* Assign XIVE to PE */
2742 	rc = opal_pci_set_xive_pe(phb->opal_id, pe->pe_number, xive_num);
2743 	if (rc) {
2744 		pe_warn(pe, "%s: OPAL error %d setting msi_base 0x%x "
2745 			"hwirq 0x%x XIVE 0x%x PE\n",
2746 			pci_name(dev), rc, phb->msi_base, hwirq, xive_num);
2747 		return -EIO;
2748 	}
2749 	set_msi_irq_chip(phb, virq);
2750 
2751 	return 0;
2752 }
2753 EXPORT_SYMBOL(pnv_cxl_ioda_msi_setup);
2754 #endif
2755 
2756 static int pnv_pci_ioda_msi_setup(struct pnv_phb *phb, struct pci_dev *dev,
2757 				  unsigned int hwirq, unsigned int virq,
2758 				  unsigned int is_64, struct msi_msg *msg)
2759 {
2760 	struct pnv_ioda_pe *pe = pnv_ioda_get_pe(dev);
2761 	unsigned int xive_num = hwirq - phb->msi_base;
2762 	__be32 data;
2763 	int rc;
2764 
2765 	/* No PE assigned ? bail out ... no MSI for you ! */
2766 	if (pe == NULL)
2767 		return -ENXIO;
2768 
2769 	/* Check if we have an MVE */
2770 	if (pe->mve_number < 0)
2771 		return -ENXIO;
2772 
2773 	/* Force 32-bit MSI on some broken devices */
2774 	if (dev->no_64bit_msi)
2775 		is_64 = 0;
2776 
2777 	/* Assign XIVE to PE */
2778 	rc = opal_pci_set_xive_pe(phb->opal_id, pe->pe_number, xive_num);
2779 	if (rc) {
2780 		pr_warn("%s: OPAL error %d setting XIVE %d PE\n",
2781 			pci_name(dev), rc, xive_num);
2782 		return -EIO;
2783 	}
2784 
2785 	if (is_64) {
2786 		__be64 addr64;
2787 
2788 		rc = opal_get_msi_64(phb->opal_id, pe->mve_number, xive_num, 1,
2789 				     &addr64, &data);
2790 		if (rc) {
2791 			pr_warn("%s: OPAL error %d getting 64-bit MSI data\n",
2792 				pci_name(dev), rc);
2793 			return -EIO;
2794 		}
2795 		msg->address_hi = be64_to_cpu(addr64) >> 32;
2796 		msg->address_lo = be64_to_cpu(addr64) & 0xfffffffful;
2797 	} else {
2798 		__be32 addr32;
2799 
2800 		rc = opal_get_msi_32(phb->opal_id, pe->mve_number, xive_num, 1,
2801 				     &addr32, &data);
2802 		if (rc) {
2803 			pr_warn("%s: OPAL error %d getting 32-bit MSI data\n",
2804 				pci_name(dev), rc);
2805 			return -EIO;
2806 		}
2807 		msg->address_hi = 0;
2808 		msg->address_lo = be32_to_cpu(addr32);
2809 	}
2810 	msg->data = be32_to_cpu(data);
2811 
2812 	set_msi_irq_chip(phb, virq);
2813 
2814 	pr_devel("%s: %s-bit MSI on hwirq %x (xive #%d),"
2815 		 " address=%x_%08x data=%x PE# %d\n",
2816 		 pci_name(dev), is_64 ? "64" : "32", hwirq, xive_num,
2817 		 msg->address_hi, msg->address_lo, data, pe->pe_number);
2818 
2819 	return 0;
2820 }
2821 
2822 static void pnv_pci_init_ioda_msis(struct pnv_phb *phb)
2823 {
2824 	unsigned int count;
2825 	const __be32 *prop = of_get_property(phb->hose->dn,
2826 					     "ibm,opal-msi-ranges", NULL);
2827 	if (!prop) {
2828 		/* BML Fallback */
2829 		prop = of_get_property(phb->hose->dn, "msi-ranges", NULL);
2830 	}
2831 	if (!prop)
2832 		return;
2833 
2834 	phb->msi_base = be32_to_cpup(prop);
2835 	count = be32_to_cpup(prop + 1);
2836 	if (msi_bitmap_alloc(&phb->msi_bmp, count, phb->hose->dn)) {
2837 		pr_err("PCI %d: Failed to allocate MSI bitmap !\n",
2838 		       phb->hose->global_number);
2839 		return;
2840 	}
2841 
2842 	phb->msi_setup = pnv_pci_ioda_msi_setup;
2843 	phb->msi32_support = 1;
2844 	pr_info("  Allocated bitmap for %d MSIs (base IRQ 0x%x)\n",
2845 		count, phb->msi_base);
2846 }
2847 #else
2848 static void pnv_pci_init_ioda_msis(struct pnv_phb *phb) { }
2849 #endif /* CONFIG_PCI_MSI */
2850 
2851 #ifdef CONFIG_PCI_IOV
2852 static void pnv_pci_ioda_fixup_iov_resources(struct pci_dev *pdev)
2853 {
2854 	struct pci_controller *hose;
2855 	struct pnv_phb *phb;
2856 	struct resource *res;
2857 	int i;
2858 	resource_size_t size;
2859 	struct pci_dn *pdn;
2860 	int mul, total_vfs;
2861 
2862 	if (!pdev->is_physfn || pdev->is_added)
2863 		return;
2864 
2865 	hose = pci_bus_to_host(pdev->bus);
2866 	phb = hose->private_data;
2867 
2868 	pdn = pci_get_pdn(pdev);
2869 	pdn->vfs_expanded = 0;
2870 
2871 	total_vfs = pci_sriov_get_totalvfs(pdev);
2872 	pdn->m64_per_iov = 1;
2873 	mul = phb->ioda.total_pe;
2874 
2875 	for (i = 0; i < PCI_SRIOV_NUM_BARS; i++) {
2876 		res = &pdev->resource[i + PCI_IOV_RESOURCES];
2877 		if (!res->flags || res->parent)
2878 			continue;
2879 		if (!pnv_pci_is_mem_pref_64(res->flags)) {
2880 			dev_warn(&pdev->dev, " non M64 VF BAR%d: %pR\n",
2881 				 i, res);
2882 			continue;
2883 		}
2884 
2885 		size = pci_iov_resource_size(pdev, i + PCI_IOV_RESOURCES);
2886 
2887 		/* bigger than 64M */
2888 		if (size > (1 << 26)) {
2889 			dev_info(&pdev->dev, "PowerNV: VF BAR%d: %pR IOV size is bigger than 64M, roundup power2\n",
2890 				 i, res);
2891 			pdn->m64_per_iov = M64_PER_IOV;
2892 			mul = roundup_pow_of_two(total_vfs);
2893 			break;
2894 		}
2895 	}
2896 
2897 	for (i = 0; i < PCI_SRIOV_NUM_BARS; i++) {
2898 		res = &pdev->resource[i + PCI_IOV_RESOURCES];
2899 		if (!res->flags || res->parent)
2900 			continue;
2901 		if (!pnv_pci_is_mem_pref_64(res->flags)) {
2902 			dev_warn(&pdev->dev, "Skipping expanding VF BAR%d: %pR\n",
2903 				 i, res);
2904 			continue;
2905 		}
2906 
2907 		dev_dbg(&pdev->dev, " Fixing VF BAR%d: %pR to\n", i, res);
2908 		size = pci_iov_resource_size(pdev, i + PCI_IOV_RESOURCES);
2909 		res->end = res->start + size * mul - 1;
2910 		dev_dbg(&pdev->dev, "                       %pR\n", res);
2911 		dev_info(&pdev->dev, "VF BAR%d: %pR (expanded to %d VFs for PE alignment)",
2912 			 i, res, mul);
2913 	}
2914 	pdn->vfs_expanded = mul;
2915 }
2916 #endif /* CONFIG_PCI_IOV */
2917 
2918 /*
2919  * This function is supposed to be called on basis of PE from top
2920  * to bottom style. So the the I/O or MMIO segment assigned to
2921  * parent PE could be overrided by its child PEs if necessary.
2922  */
2923 static void pnv_ioda_setup_pe_seg(struct pci_controller *hose,
2924 				  struct pnv_ioda_pe *pe)
2925 {
2926 	struct pnv_phb *phb = hose->private_data;
2927 	struct pci_bus_region region;
2928 	struct resource *res;
2929 	int i, index;
2930 	int rc;
2931 
2932 	/*
2933 	 * NOTE: We only care PCI bus based PE for now. For PCI
2934 	 * device based PE, for example SRIOV sensitive VF should
2935 	 * be figured out later.
2936 	 */
2937 	BUG_ON(!(pe->flags & (PNV_IODA_PE_BUS | PNV_IODA_PE_BUS_ALL)));
2938 
2939 	pci_bus_for_each_resource(pe->pbus, res, i) {
2940 		if (!res || !res->flags ||
2941 		    res->start > res->end)
2942 			continue;
2943 
2944 		if (res->flags & IORESOURCE_IO) {
2945 			region.start = res->start - phb->ioda.io_pci_base;
2946 			region.end   = res->end - phb->ioda.io_pci_base;
2947 			index = region.start / phb->ioda.io_segsize;
2948 
2949 			while (index < phb->ioda.total_pe &&
2950 			       region.start <= region.end) {
2951 				phb->ioda.io_segmap[index] = pe->pe_number;
2952 				rc = opal_pci_map_pe_mmio_window(phb->opal_id,
2953 					pe->pe_number, OPAL_IO_WINDOW_TYPE, 0, index);
2954 				if (rc != OPAL_SUCCESS) {
2955 					pr_err("%s: OPAL error %d when mapping IO "
2956 					       "segment #%d to PE#%d\n",
2957 					       __func__, rc, index, pe->pe_number);
2958 					break;
2959 				}
2960 
2961 				region.start += phb->ioda.io_segsize;
2962 				index++;
2963 			}
2964 		} else if ((res->flags & IORESOURCE_MEM) &&
2965 			   !pnv_pci_is_mem_pref_64(res->flags)) {
2966 			region.start = res->start -
2967 				       hose->mem_offset[0] -
2968 				       phb->ioda.m32_pci_base;
2969 			region.end   = res->end -
2970 				       hose->mem_offset[0] -
2971 				       phb->ioda.m32_pci_base;
2972 			index = region.start / phb->ioda.m32_segsize;
2973 
2974 			while (index < phb->ioda.total_pe &&
2975 			       region.start <= region.end) {
2976 				phb->ioda.m32_segmap[index] = pe->pe_number;
2977 				rc = opal_pci_map_pe_mmio_window(phb->opal_id,
2978 					pe->pe_number, OPAL_M32_WINDOW_TYPE, 0, index);
2979 				if (rc != OPAL_SUCCESS) {
2980 					pr_err("%s: OPAL error %d when mapping M32 "
2981 					       "segment#%d to PE#%d",
2982 					       __func__, rc, index, pe->pe_number);
2983 					break;
2984 				}
2985 
2986 				region.start += phb->ioda.m32_segsize;
2987 				index++;
2988 			}
2989 		}
2990 	}
2991 }
2992 
2993 static void pnv_pci_ioda_setup_seg(void)
2994 {
2995 	struct pci_controller *tmp, *hose;
2996 	struct pnv_phb *phb;
2997 	struct pnv_ioda_pe *pe;
2998 
2999 	list_for_each_entry_safe(hose, tmp, &hose_list, list_node) {
3000 		phb = hose->private_data;
3001 
3002 		/* NPU PHB does not support IO or MMIO segmentation */
3003 		if (phb->type == PNV_PHB_NPU)
3004 			continue;
3005 
3006 		list_for_each_entry(pe, &phb->ioda.pe_list, list) {
3007 			pnv_ioda_setup_pe_seg(hose, pe);
3008 		}
3009 	}
3010 }
3011 
3012 static void pnv_pci_ioda_setup_DMA(void)
3013 {
3014 	struct pci_controller *hose, *tmp;
3015 	struct pnv_phb *phb;
3016 
3017 	list_for_each_entry_safe(hose, tmp, &hose_list, list_node) {
3018 		pnv_ioda_setup_dma(hose->private_data);
3019 
3020 		/* Mark the PHB initialization done */
3021 		phb = hose->private_data;
3022 		phb->initialized = 1;
3023 	}
3024 }
3025 
3026 static void pnv_pci_ioda_create_dbgfs(void)
3027 {
3028 #ifdef CONFIG_DEBUG_FS
3029 	struct pci_controller *hose, *tmp;
3030 	struct pnv_phb *phb;
3031 	char name[16];
3032 
3033 	list_for_each_entry_safe(hose, tmp, &hose_list, list_node) {
3034 		phb = hose->private_data;
3035 
3036 		sprintf(name, "PCI%04x", hose->global_number);
3037 		phb->dbgfs = debugfs_create_dir(name, powerpc_debugfs_root);
3038 		if (!phb->dbgfs)
3039 			pr_warning("%s: Error on creating debugfs on PHB#%x\n",
3040 				__func__, hose->global_number);
3041 	}
3042 #endif /* CONFIG_DEBUG_FS */
3043 }
3044 
3045 static void pnv_npu_ioda_fixup(void)
3046 {
3047 	bool enable_bypass;
3048 	struct pci_controller *hose, *tmp;
3049 	struct pnv_phb *phb;
3050 	struct pnv_ioda_pe *pe;
3051 
3052 	list_for_each_entry_safe(hose, tmp, &hose_list, list_node) {
3053 		phb = hose->private_data;
3054 		if (phb->type != PNV_PHB_NPU)
3055 			continue;
3056 
3057 		list_for_each_entry(pe, &phb->ioda.pe_dma_list, dma_link) {
3058 			enable_bypass = dma_get_mask(&pe->pdev->dev) ==
3059 				DMA_BIT_MASK(64);
3060 			pnv_npu_init_dma_pe(pe);
3061 			pnv_npu_dma_set_bypass(pe, enable_bypass);
3062 		}
3063 	}
3064 }
3065 
3066 static void pnv_pci_ioda_fixup(void)
3067 {
3068 	pnv_pci_ioda_setup_PEs();
3069 	pnv_pci_ioda_setup_seg();
3070 	pnv_pci_ioda_setup_DMA();
3071 
3072 	pnv_pci_ioda_create_dbgfs();
3073 
3074 #ifdef CONFIG_EEH
3075 	eeh_init();
3076 	eeh_addr_cache_build();
3077 #endif
3078 
3079 	/* Link NPU IODA tables to their PCI devices. */
3080 	pnv_npu_ioda_fixup();
3081 }
3082 
3083 /*
3084  * Returns the alignment for I/O or memory windows for P2P
3085  * bridges. That actually depends on how PEs are segmented.
3086  * For now, we return I/O or M32 segment size for PE sensitive
3087  * P2P bridges. Otherwise, the default values (4KiB for I/O,
3088  * 1MiB for memory) will be returned.
3089  *
3090  * The current PCI bus might be put into one PE, which was
3091  * create against the parent PCI bridge. For that case, we
3092  * needn't enlarge the alignment so that we can save some
3093  * resources.
3094  */
3095 static resource_size_t pnv_pci_window_alignment(struct pci_bus *bus,
3096 						unsigned long type)
3097 {
3098 	struct pci_dev *bridge;
3099 	struct pci_controller *hose = pci_bus_to_host(bus);
3100 	struct pnv_phb *phb = hose->private_data;
3101 	int num_pci_bridges = 0;
3102 
3103 	bridge = bus->self;
3104 	while (bridge) {
3105 		if (pci_pcie_type(bridge) == PCI_EXP_TYPE_PCI_BRIDGE) {
3106 			num_pci_bridges++;
3107 			if (num_pci_bridges >= 2)
3108 				return 1;
3109 		}
3110 
3111 		bridge = bridge->bus->self;
3112 	}
3113 
3114 	/* We fail back to M32 if M64 isn't supported */
3115 	if (phb->ioda.m64_segsize &&
3116 	    pnv_pci_is_mem_pref_64(type))
3117 		return phb->ioda.m64_segsize;
3118 	if (type & IORESOURCE_MEM)
3119 		return phb->ioda.m32_segsize;
3120 
3121 	return phb->ioda.io_segsize;
3122 }
3123 
3124 #ifdef CONFIG_PCI_IOV
3125 static resource_size_t pnv_pci_iov_resource_alignment(struct pci_dev *pdev,
3126 						      int resno)
3127 {
3128 	struct pci_dn *pdn = pci_get_pdn(pdev);
3129 	resource_size_t align, iov_align;
3130 
3131 	iov_align = resource_size(&pdev->resource[resno]);
3132 	if (iov_align)
3133 		return iov_align;
3134 
3135 	align = pci_iov_resource_size(pdev, resno);
3136 	if (pdn->vfs_expanded)
3137 		return pdn->vfs_expanded * align;
3138 
3139 	return align;
3140 }
3141 #endif /* CONFIG_PCI_IOV */
3142 
3143 /* Prevent enabling devices for which we couldn't properly
3144  * assign a PE
3145  */
3146 static bool pnv_pci_enable_device_hook(struct pci_dev *dev)
3147 {
3148 	struct pci_controller *hose = pci_bus_to_host(dev->bus);
3149 	struct pnv_phb *phb = hose->private_data;
3150 	struct pci_dn *pdn;
3151 
3152 	/* The function is probably called while the PEs have
3153 	 * not be created yet. For example, resource reassignment
3154 	 * during PCI probe period. We just skip the check if
3155 	 * PEs isn't ready.
3156 	 */
3157 	if (!phb->initialized)
3158 		return true;
3159 
3160 	pdn = pci_get_pdn(dev);
3161 	if (!pdn || pdn->pe_number == IODA_INVALID_PE)
3162 		return false;
3163 
3164 	return true;
3165 }
3166 
3167 static u32 pnv_ioda_bdfn_to_pe(struct pnv_phb *phb, struct pci_bus *bus,
3168 			       u32 devfn)
3169 {
3170 	return phb->ioda.pe_rmap[(bus->number << 8) | devfn];
3171 }
3172 
3173 static void pnv_pci_ioda_shutdown(struct pci_controller *hose)
3174 {
3175 	struct pnv_phb *phb = hose->private_data;
3176 
3177 	opal_pci_reset(phb->opal_id, OPAL_RESET_PCI_IODA_TABLE,
3178 		       OPAL_ASSERT_RESET);
3179 }
3180 
3181 static const struct pci_controller_ops pnv_pci_ioda_controller_ops = {
3182        .dma_dev_setup = pnv_pci_dma_dev_setup,
3183 #ifdef CONFIG_PCI_MSI
3184        .setup_msi_irqs = pnv_setup_msi_irqs,
3185        .teardown_msi_irqs = pnv_teardown_msi_irqs,
3186 #endif
3187        .enable_device_hook = pnv_pci_enable_device_hook,
3188        .window_alignment = pnv_pci_window_alignment,
3189        .reset_secondary_bus = pnv_pci_reset_secondary_bus,
3190        .dma_set_mask = pnv_pci_ioda_dma_set_mask,
3191        .dma_get_required_mask = pnv_pci_ioda_dma_get_required_mask,
3192        .shutdown = pnv_pci_ioda_shutdown,
3193 };
3194 
3195 static const struct pci_controller_ops pnv_npu_ioda_controller_ops = {
3196 	.dma_dev_setup = pnv_pci_dma_dev_setup,
3197 #ifdef CONFIG_PCI_MSI
3198 	.setup_msi_irqs = pnv_setup_msi_irqs,
3199 	.teardown_msi_irqs = pnv_teardown_msi_irqs,
3200 #endif
3201 	.enable_device_hook = pnv_pci_enable_device_hook,
3202 	.window_alignment = pnv_pci_window_alignment,
3203 	.reset_secondary_bus = pnv_pci_reset_secondary_bus,
3204 	.dma_set_mask = pnv_npu_dma_set_mask,
3205 	.shutdown = pnv_pci_ioda_shutdown,
3206 };
3207 
3208 static void __init pnv_pci_init_ioda_phb(struct device_node *np,
3209 					 u64 hub_id, int ioda_type)
3210 {
3211 	struct pci_controller *hose;
3212 	struct pnv_phb *phb;
3213 	unsigned long size, m32map_off, pemap_off, iomap_off = 0;
3214 	const __be64 *prop64;
3215 	const __be32 *prop32;
3216 	int len;
3217 	u64 phb_id;
3218 	void *aux;
3219 	long rc;
3220 
3221 	pr_info("Initializing IODA%d OPAL PHB %s\n", ioda_type, np->full_name);
3222 
3223 	prop64 = of_get_property(np, "ibm,opal-phbid", NULL);
3224 	if (!prop64) {
3225 		pr_err("  Missing \"ibm,opal-phbid\" property !\n");
3226 		return;
3227 	}
3228 	phb_id = be64_to_cpup(prop64);
3229 	pr_debug("  PHB-ID  : 0x%016llx\n", phb_id);
3230 
3231 	phb = memblock_virt_alloc(sizeof(struct pnv_phb), 0);
3232 
3233 	/* Allocate PCI controller */
3234 	phb->hose = hose = pcibios_alloc_controller(np);
3235 	if (!phb->hose) {
3236 		pr_err("  Can't allocate PCI controller for %s\n",
3237 		       np->full_name);
3238 		memblock_free(__pa(phb), sizeof(struct pnv_phb));
3239 		return;
3240 	}
3241 
3242 	spin_lock_init(&phb->lock);
3243 	prop32 = of_get_property(np, "bus-range", &len);
3244 	if (prop32 && len == 8) {
3245 		hose->first_busno = be32_to_cpu(prop32[0]);
3246 		hose->last_busno = be32_to_cpu(prop32[1]);
3247 	} else {
3248 		pr_warn("  Broken <bus-range> on %s\n", np->full_name);
3249 		hose->first_busno = 0;
3250 		hose->last_busno = 0xff;
3251 	}
3252 	hose->private_data = phb;
3253 	phb->hub_id = hub_id;
3254 	phb->opal_id = phb_id;
3255 	phb->type = ioda_type;
3256 	mutex_init(&phb->ioda.pe_alloc_mutex);
3257 
3258 	/* Detect specific models for error handling */
3259 	if (of_device_is_compatible(np, "ibm,p7ioc-pciex"))
3260 		phb->model = PNV_PHB_MODEL_P7IOC;
3261 	else if (of_device_is_compatible(np, "ibm,power8-pciex"))
3262 		phb->model = PNV_PHB_MODEL_PHB3;
3263 	else if (of_device_is_compatible(np, "ibm,power8-npu-pciex"))
3264 		phb->model = PNV_PHB_MODEL_NPU;
3265 	else
3266 		phb->model = PNV_PHB_MODEL_UNKNOWN;
3267 
3268 	/* Parse 32-bit and IO ranges (if any) */
3269 	pci_process_bridge_OF_ranges(hose, np, !hose->global_number);
3270 
3271 	/* Get registers */
3272 	phb->regs = of_iomap(np, 0);
3273 	if (phb->regs == NULL)
3274 		pr_err("  Failed to map registers !\n");
3275 
3276 	/* Initialize more IODA stuff */
3277 	phb->ioda.total_pe = 1;
3278 	prop32 = of_get_property(np, "ibm,opal-num-pes", NULL);
3279 	if (prop32)
3280 		phb->ioda.total_pe = be32_to_cpup(prop32);
3281 	prop32 = of_get_property(np, "ibm,opal-reserved-pe", NULL);
3282 	if (prop32)
3283 		phb->ioda.reserved_pe = be32_to_cpup(prop32);
3284 
3285 	/* Parse 64-bit MMIO range */
3286 	pnv_ioda_parse_m64_window(phb);
3287 
3288 	phb->ioda.m32_size = resource_size(&hose->mem_resources[0]);
3289 	/* FW Has already off top 64k of M32 space (MSI space) */
3290 	phb->ioda.m32_size += 0x10000;
3291 
3292 	phb->ioda.m32_segsize = phb->ioda.m32_size / phb->ioda.total_pe;
3293 	phb->ioda.m32_pci_base = hose->mem_resources[0].start - hose->mem_offset[0];
3294 	phb->ioda.io_size = hose->pci_io_size;
3295 	phb->ioda.io_segsize = phb->ioda.io_size / phb->ioda.total_pe;
3296 	phb->ioda.io_pci_base = 0; /* XXX calculate this ? */
3297 
3298 	/* Allocate aux data & arrays. We don't have IO ports on PHB3 */
3299 	size = _ALIGN_UP(phb->ioda.total_pe / 8, sizeof(unsigned long));
3300 	m32map_off = size;
3301 	size += phb->ioda.total_pe * sizeof(phb->ioda.m32_segmap[0]);
3302 	if (phb->type == PNV_PHB_IODA1) {
3303 		iomap_off = size;
3304 		size += phb->ioda.total_pe * sizeof(phb->ioda.io_segmap[0]);
3305 	}
3306 	pemap_off = size;
3307 	size += phb->ioda.total_pe * sizeof(struct pnv_ioda_pe);
3308 	aux = memblock_virt_alloc(size, 0);
3309 	phb->ioda.pe_alloc = aux;
3310 	phb->ioda.m32_segmap = aux + m32map_off;
3311 	if (phb->type == PNV_PHB_IODA1)
3312 		phb->ioda.io_segmap = aux + iomap_off;
3313 	phb->ioda.pe_array = aux + pemap_off;
3314 	set_bit(phb->ioda.reserved_pe, phb->ioda.pe_alloc);
3315 
3316 	INIT_LIST_HEAD(&phb->ioda.pe_dma_list);
3317 	INIT_LIST_HEAD(&phb->ioda.pe_list);
3318 	mutex_init(&phb->ioda.pe_list_mutex);
3319 
3320 	/* Calculate how many 32-bit TCE segments we have */
3321 	phb->ioda.tce32_count = phb->ioda.m32_pci_base >> 28;
3322 
3323 #if 0 /* We should really do that ... */
3324 	rc = opal_pci_set_phb_mem_window(opal->phb_id,
3325 					 window_type,
3326 					 window_num,
3327 					 starting_real_address,
3328 					 starting_pci_address,
3329 					 segment_size);
3330 #endif
3331 
3332 	pr_info("  %03d (%03d) PE's M32: 0x%x [segment=0x%x]\n",
3333 		phb->ioda.total_pe, phb->ioda.reserved_pe,
3334 		phb->ioda.m32_size, phb->ioda.m32_segsize);
3335 	if (phb->ioda.m64_size)
3336 		pr_info("                 M64: 0x%lx [segment=0x%lx]\n",
3337 			phb->ioda.m64_size, phb->ioda.m64_segsize);
3338 	if (phb->ioda.io_size)
3339 		pr_info("                  IO: 0x%x [segment=0x%x]\n",
3340 			phb->ioda.io_size, phb->ioda.io_segsize);
3341 
3342 
3343 	phb->hose->ops = &pnv_pci_ops;
3344 	phb->get_pe_state = pnv_ioda_get_pe_state;
3345 	phb->freeze_pe = pnv_ioda_freeze_pe;
3346 	phb->unfreeze_pe = pnv_ioda_unfreeze_pe;
3347 
3348 	/* Setup RID -> PE mapping function */
3349 	phb->bdfn_to_pe = pnv_ioda_bdfn_to_pe;
3350 
3351 	/* Setup TCEs */
3352 	phb->dma_dev_setup = pnv_pci_ioda_dma_dev_setup;
3353 
3354 	/* Setup MSI support */
3355 	pnv_pci_init_ioda_msis(phb);
3356 
3357 	/*
3358 	 * We pass the PCI probe flag PCI_REASSIGN_ALL_RSRC here
3359 	 * to let the PCI core do resource assignment. It's supposed
3360 	 * that the PCI core will do correct I/O and MMIO alignment
3361 	 * for the P2P bridge bars so that each PCI bus (excluding
3362 	 * the child P2P bridges) can form individual PE.
3363 	 */
3364 	ppc_md.pcibios_fixup = pnv_pci_ioda_fixup;
3365 
3366 	if (phb->type == PNV_PHB_NPU)
3367 		hose->controller_ops = pnv_npu_ioda_controller_ops;
3368 	else
3369 		hose->controller_ops = pnv_pci_ioda_controller_ops;
3370 
3371 #ifdef CONFIG_PCI_IOV
3372 	ppc_md.pcibios_fixup_sriov = pnv_pci_ioda_fixup_iov_resources;
3373 	ppc_md.pcibios_iov_resource_alignment = pnv_pci_iov_resource_alignment;
3374 #endif
3375 
3376 	pci_add_flags(PCI_REASSIGN_ALL_RSRC);
3377 
3378 	/* Reset IODA tables to a clean state */
3379 	rc = opal_pci_reset(phb_id, OPAL_RESET_PCI_IODA_TABLE, OPAL_ASSERT_RESET);
3380 	if (rc)
3381 		pr_warning("  OPAL Error %ld performing IODA table reset !\n", rc);
3382 
3383 	/* If we're running in kdump kerenl, the previous kerenl never
3384 	 * shutdown PCI devices correctly. We already got IODA table
3385 	 * cleaned out. So we have to issue PHB reset to stop all PCI
3386 	 * transactions from previous kerenl.
3387 	 */
3388 	if (is_kdump_kernel()) {
3389 		pr_info("  Issue PHB reset ...\n");
3390 		pnv_eeh_phb_reset(hose, EEH_RESET_FUNDAMENTAL);
3391 		pnv_eeh_phb_reset(hose, EEH_RESET_DEACTIVATE);
3392 	}
3393 
3394 	/* Remove M64 resource if we can't configure it successfully */
3395 	if (!phb->init_m64 || phb->init_m64(phb))
3396 		hose->mem_resources[1].flags = 0;
3397 }
3398 
3399 void __init pnv_pci_init_ioda2_phb(struct device_node *np)
3400 {
3401 	pnv_pci_init_ioda_phb(np, 0, PNV_PHB_IODA2);
3402 }
3403 
3404 void __init pnv_pci_init_npu_phb(struct device_node *np)
3405 {
3406 	pnv_pci_init_ioda_phb(np, 0, PNV_PHB_NPU);
3407 }
3408 
3409 void __init pnv_pci_init_ioda_hub(struct device_node *np)
3410 {
3411 	struct device_node *phbn;
3412 	const __be64 *prop64;
3413 	u64 hub_id;
3414 
3415 	pr_info("Probing IODA IO-Hub %s\n", np->full_name);
3416 
3417 	prop64 = of_get_property(np, "ibm,opal-hubid", NULL);
3418 	if (!prop64) {
3419 		pr_err(" Missing \"ibm,opal-hubid\" property !\n");
3420 		return;
3421 	}
3422 	hub_id = be64_to_cpup(prop64);
3423 	pr_devel(" HUB-ID : 0x%016llx\n", hub_id);
3424 
3425 	/* Count child PHBs */
3426 	for_each_child_of_node(np, phbn) {
3427 		/* Look for IODA1 PHBs */
3428 		if (of_device_is_compatible(phbn, "ibm,ioda-phb"))
3429 			pnv_pci_init_ioda_phb(phbn, hub_id, PNV_PHB_IODA1);
3430 	}
3431 }
3432