1 // SPDX-License-Identifier: GPL-2.0-or-later
2 /*
3  * Support PCI/PCIe on PowerNV platforms
4  *
5  * Copyright 2011 Benjamin Herrenschmidt, IBM Corp.
6  */
7 
8 #undef DEBUG
9 
10 #include <linux/kernel.h>
11 #include <linux/pci.h>
12 #include <linux/crash_dump.h>
13 #include <linux/delay.h>
14 #include <linux/string.h>
15 #include <linux/init.h>
16 #include <linux/memblock.h>
17 #include <linux/irq.h>
18 #include <linux/io.h>
19 #include <linux/msi.h>
20 #include <linux/iommu.h>
21 #include <linux/rculist.h>
22 #include <linux/sizes.h>
23 
24 #include <asm/sections.h>
25 #include <asm/io.h>
26 #include <asm/prom.h>
27 #include <asm/pci-bridge.h>
28 #include <asm/machdep.h>
29 #include <asm/msi_bitmap.h>
30 #include <asm/ppc-pci.h>
31 #include <asm/opal.h>
32 #include <asm/iommu.h>
33 #include <asm/tce.h>
34 #include <asm/xics.h>
35 #include <asm/debugfs.h>
36 #include <asm/firmware.h>
37 #include <asm/pnv-pci.h>
38 #include <asm/mmzone.h>
39 
40 #include <misc/cxl-base.h>
41 
42 #include "powernv.h"
43 #include "pci.h"
44 #include "../../../../drivers/pci/pci.h"
45 
46 #define PNV_IODA1_M64_NUM	16	/* Number of M64 BARs	*/
47 #define PNV_IODA1_M64_SEGS	8	/* Segments per M64 BAR	*/
48 #define PNV_IODA1_DMA32_SEGSIZE	0x10000000
49 
50 static const char * const pnv_phb_names[] = { "IODA1", "IODA2", "NPU_NVLINK",
51 					      "NPU_OCAPI" };
52 
53 static void pnv_pci_ioda2_set_bypass(struct pnv_ioda_pe *pe, bool enable);
54 
55 void pe_level_printk(const struct pnv_ioda_pe *pe, const char *level,
56 			    const char *fmt, ...)
57 {
58 	struct va_format vaf;
59 	va_list args;
60 	char pfix[32];
61 
62 	va_start(args, fmt);
63 
64 	vaf.fmt = fmt;
65 	vaf.va = &args;
66 
67 	if (pe->flags & PNV_IODA_PE_DEV)
68 		strlcpy(pfix, dev_name(&pe->pdev->dev), sizeof(pfix));
69 	else if (pe->flags & (PNV_IODA_PE_BUS | PNV_IODA_PE_BUS_ALL))
70 		sprintf(pfix, "%04x:%02x     ",
71 			pci_domain_nr(pe->pbus), pe->pbus->number);
72 #ifdef CONFIG_PCI_IOV
73 	else if (pe->flags & PNV_IODA_PE_VF)
74 		sprintf(pfix, "%04x:%02x:%2x.%d",
75 			pci_domain_nr(pe->parent_dev->bus),
76 			(pe->rid & 0xff00) >> 8,
77 			PCI_SLOT(pe->rid), PCI_FUNC(pe->rid));
78 #endif /* CONFIG_PCI_IOV*/
79 
80 	printk("%spci %s: [PE# %.2x] %pV",
81 	       level, pfix, pe->pe_number, &vaf);
82 
83 	va_end(args);
84 }
85 
86 static bool pnv_iommu_bypass_disabled __read_mostly;
87 static bool pci_reset_phbs __read_mostly;
88 
89 static int __init iommu_setup(char *str)
90 {
91 	if (!str)
92 		return -EINVAL;
93 
94 	while (*str) {
95 		if (!strncmp(str, "nobypass", 8)) {
96 			pnv_iommu_bypass_disabled = true;
97 			pr_info("PowerNV: IOMMU bypass window disabled.\n");
98 			break;
99 		}
100 		str += strcspn(str, ",");
101 		if (*str == ',')
102 			str++;
103 	}
104 
105 	return 0;
106 }
107 early_param("iommu", iommu_setup);
108 
109 static int __init pci_reset_phbs_setup(char *str)
110 {
111 	pci_reset_phbs = true;
112 	return 0;
113 }
114 
115 early_param("ppc_pci_reset_phbs", pci_reset_phbs_setup);
116 
117 static inline bool pnv_pci_is_m64(struct pnv_phb *phb, struct resource *r)
118 {
119 	/*
120 	 * WARNING: We cannot rely on the resource flags. The Linux PCI
121 	 * allocation code sometimes decides to put a 64-bit prefetchable
122 	 * BAR in the 32-bit window, so we have to compare the addresses.
123 	 *
124 	 * For simplicity we only test resource start.
125 	 */
126 	return (r->start >= phb->ioda.m64_base &&
127 		r->start < (phb->ioda.m64_base + phb->ioda.m64_size));
128 }
129 
130 static inline bool pnv_pci_is_m64_flags(unsigned long resource_flags)
131 {
132 	unsigned long flags = (IORESOURCE_MEM_64 | IORESOURCE_PREFETCH);
133 
134 	return (resource_flags & flags) == flags;
135 }
136 
137 static struct pnv_ioda_pe *pnv_ioda_init_pe(struct pnv_phb *phb, int pe_no)
138 {
139 	s64 rc;
140 
141 	phb->ioda.pe_array[pe_no].phb = phb;
142 	phb->ioda.pe_array[pe_no].pe_number = pe_no;
143 
144 	/*
145 	 * Clear the PE frozen state as it might be put into frozen state
146 	 * in the last PCI remove path. It's not harmful to do so when the
147 	 * PE is already in unfrozen state.
148 	 */
149 	rc = opal_pci_eeh_freeze_clear(phb->opal_id, pe_no,
150 				       OPAL_EEH_ACTION_CLEAR_FREEZE_ALL);
151 	if (rc != OPAL_SUCCESS && rc != OPAL_UNSUPPORTED)
152 		pr_warn("%s: Error %lld unfreezing PHB#%x-PE#%x\n",
153 			__func__, rc, phb->hose->global_number, pe_no);
154 
155 	return &phb->ioda.pe_array[pe_no];
156 }
157 
158 static void pnv_ioda_reserve_pe(struct pnv_phb *phb, int pe_no)
159 {
160 	if (!(pe_no >= 0 && pe_no < phb->ioda.total_pe_num)) {
161 		pr_warn("%s: Invalid PE %x on PHB#%x\n",
162 			__func__, pe_no, phb->hose->global_number);
163 		return;
164 	}
165 
166 	if (test_and_set_bit(pe_no, phb->ioda.pe_alloc))
167 		pr_debug("%s: PE %x was reserved on PHB#%x\n",
168 			 __func__, pe_no, phb->hose->global_number);
169 
170 	pnv_ioda_init_pe(phb, pe_no);
171 }
172 
173 static struct pnv_ioda_pe *pnv_ioda_alloc_pe(struct pnv_phb *phb)
174 {
175 	long pe;
176 
177 	for (pe = phb->ioda.total_pe_num - 1; pe >= 0; pe--) {
178 		if (!test_and_set_bit(pe, phb->ioda.pe_alloc))
179 			return pnv_ioda_init_pe(phb, pe);
180 	}
181 
182 	return NULL;
183 }
184 
185 static void pnv_ioda_free_pe(struct pnv_ioda_pe *pe)
186 {
187 	struct pnv_phb *phb = pe->phb;
188 	unsigned int pe_num = pe->pe_number;
189 
190 	WARN_ON(pe->pdev);
191 	WARN_ON(pe->npucomp); /* NPUs for nvlink are not supposed to be freed */
192 	kfree(pe->npucomp);
193 	memset(pe, 0, sizeof(struct pnv_ioda_pe));
194 	clear_bit(pe_num, phb->ioda.pe_alloc);
195 }
196 
197 /* The default M64 BAR is shared by all PEs */
198 static int pnv_ioda2_init_m64(struct pnv_phb *phb)
199 {
200 	const char *desc;
201 	struct resource *r;
202 	s64 rc;
203 
204 	/* Configure the default M64 BAR */
205 	rc = opal_pci_set_phb_mem_window(phb->opal_id,
206 					 OPAL_M64_WINDOW_TYPE,
207 					 phb->ioda.m64_bar_idx,
208 					 phb->ioda.m64_base,
209 					 0, /* unused */
210 					 phb->ioda.m64_size);
211 	if (rc != OPAL_SUCCESS) {
212 		desc = "configuring";
213 		goto fail;
214 	}
215 
216 	/* Enable the default M64 BAR */
217 	rc = opal_pci_phb_mmio_enable(phb->opal_id,
218 				      OPAL_M64_WINDOW_TYPE,
219 				      phb->ioda.m64_bar_idx,
220 				      OPAL_ENABLE_M64_SPLIT);
221 	if (rc != OPAL_SUCCESS) {
222 		desc = "enabling";
223 		goto fail;
224 	}
225 
226 	/*
227 	 * Exclude the segments for reserved and root bus PE, which
228 	 * are first or last two PEs.
229 	 */
230 	r = &phb->hose->mem_resources[1];
231 	if (phb->ioda.reserved_pe_idx == 0)
232 		r->start += (2 * phb->ioda.m64_segsize);
233 	else if (phb->ioda.reserved_pe_idx == (phb->ioda.total_pe_num - 1))
234 		r->end -= (2 * phb->ioda.m64_segsize);
235 	else
236 		pr_warn("  Cannot strip M64 segment for reserved PE#%x\n",
237 			phb->ioda.reserved_pe_idx);
238 
239 	return 0;
240 
241 fail:
242 	pr_warn("  Failure %lld %s M64 BAR#%d\n",
243 		rc, desc, phb->ioda.m64_bar_idx);
244 	opal_pci_phb_mmio_enable(phb->opal_id,
245 				 OPAL_M64_WINDOW_TYPE,
246 				 phb->ioda.m64_bar_idx,
247 				 OPAL_DISABLE_M64);
248 	return -EIO;
249 }
250 
251 static void pnv_ioda_reserve_dev_m64_pe(struct pci_dev *pdev,
252 					 unsigned long *pe_bitmap)
253 {
254 	struct pci_controller *hose = pci_bus_to_host(pdev->bus);
255 	struct pnv_phb *phb = hose->private_data;
256 	struct resource *r;
257 	resource_size_t base, sgsz, start, end;
258 	int segno, i;
259 
260 	base = phb->ioda.m64_base;
261 	sgsz = phb->ioda.m64_segsize;
262 	for (i = 0; i <= PCI_ROM_RESOURCE; i++) {
263 		r = &pdev->resource[i];
264 		if (!r->parent || !pnv_pci_is_m64(phb, r))
265 			continue;
266 
267 		start = _ALIGN_DOWN(r->start - base, sgsz);
268 		end = _ALIGN_UP(r->end - base, sgsz);
269 		for (segno = start / sgsz; segno < end / sgsz; segno++) {
270 			if (pe_bitmap)
271 				set_bit(segno, pe_bitmap);
272 			else
273 				pnv_ioda_reserve_pe(phb, segno);
274 		}
275 	}
276 }
277 
278 static int pnv_ioda1_init_m64(struct pnv_phb *phb)
279 {
280 	struct resource *r;
281 	int index;
282 
283 	/*
284 	 * There are 16 M64 BARs, each of which has 8 segments. So
285 	 * there are as many M64 segments as the maximum number of
286 	 * PEs, which is 128.
287 	 */
288 	for (index = 0; index < PNV_IODA1_M64_NUM; index++) {
289 		unsigned long base, segsz = phb->ioda.m64_segsize;
290 		int64_t rc;
291 
292 		base = phb->ioda.m64_base +
293 		       index * PNV_IODA1_M64_SEGS * segsz;
294 		rc = opal_pci_set_phb_mem_window(phb->opal_id,
295 				OPAL_M64_WINDOW_TYPE, index, base, 0,
296 				PNV_IODA1_M64_SEGS * segsz);
297 		if (rc != OPAL_SUCCESS) {
298 			pr_warn("  Error %lld setting M64 PHB#%x-BAR#%d\n",
299 				rc, phb->hose->global_number, index);
300 			goto fail;
301 		}
302 
303 		rc = opal_pci_phb_mmio_enable(phb->opal_id,
304 				OPAL_M64_WINDOW_TYPE, index,
305 				OPAL_ENABLE_M64_SPLIT);
306 		if (rc != OPAL_SUCCESS) {
307 			pr_warn("  Error %lld enabling M64 PHB#%x-BAR#%d\n",
308 				rc, phb->hose->global_number, index);
309 			goto fail;
310 		}
311 	}
312 
313 	/*
314 	 * Exclude the segments for reserved and root bus PE, which
315 	 * are first or last two PEs.
316 	 */
317 	r = &phb->hose->mem_resources[1];
318 	if (phb->ioda.reserved_pe_idx == 0)
319 		r->start += (2 * phb->ioda.m64_segsize);
320 	else if (phb->ioda.reserved_pe_idx == (phb->ioda.total_pe_num - 1))
321 		r->end -= (2 * phb->ioda.m64_segsize);
322 	else
323 		WARN(1, "Wrong reserved PE#%x on PHB#%x\n",
324 		     phb->ioda.reserved_pe_idx, phb->hose->global_number);
325 
326 	return 0;
327 
328 fail:
329 	for ( ; index >= 0; index--)
330 		opal_pci_phb_mmio_enable(phb->opal_id,
331 			OPAL_M64_WINDOW_TYPE, index, OPAL_DISABLE_M64);
332 
333 	return -EIO;
334 }
335 
336 static void pnv_ioda_reserve_m64_pe(struct pci_bus *bus,
337 				    unsigned long *pe_bitmap,
338 				    bool all)
339 {
340 	struct pci_dev *pdev;
341 
342 	list_for_each_entry(pdev, &bus->devices, bus_list) {
343 		pnv_ioda_reserve_dev_m64_pe(pdev, pe_bitmap);
344 
345 		if (all && pdev->subordinate)
346 			pnv_ioda_reserve_m64_pe(pdev->subordinate,
347 						pe_bitmap, all);
348 	}
349 }
350 
351 static struct pnv_ioda_pe *pnv_ioda_pick_m64_pe(struct pci_bus *bus, bool all)
352 {
353 	struct pci_controller *hose = pci_bus_to_host(bus);
354 	struct pnv_phb *phb = hose->private_data;
355 	struct pnv_ioda_pe *master_pe, *pe;
356 	unsigned long size, *pe_alloc;
357 	int i;
358 
359 	/* Root bus shouldn't use M64 */
360 	if (pci_is_root_bus(bus))
361 		return NULL;
362 
363 	/* Allocate bitmap */
364 	size = _ALIGN_UP(phb->ioda.total_pe_num / 8, sizeof(unsigned long));
365 	pe_alloc = kzalloc(size, GFP_KERNEL);
366 	if (!pe_alloc) {
367 		pr_warn("%s: Out of memory !\n",
368 			__func__);
369 		return NULL;
370 	}
371 
372 	/* Figure out reserved PE numbers by the PE */
373 	pnv_ioda_reserve_m64_pe(bus, pe_alloc, all);
374 
375 	/*
376 	 * the current bus might not own M64 window and that's all
377 	 * contributed by its child buses. For the case, we needn't
378 	 * pick M64 dependent PE#.
379 	 */
380 	if (bitmap_empty(pe_alloc, phb->ioda.total_pe_num)) {
381 		kfree(pe_alloc);
382 		return NULL;
383 	}
384 
385 	/*
386 	 * Figure out the master PE and put all slave PEs to master
387 	 * PE's list to form compound PE.
388 	 */
389 	master_pe = NULL;
390 	i = -1;
391 	while ((i = find_next_bit(pe_alloc, phb->ioda.total_pe_num, i + 1)) <
392 		phb->ioda.total_pe_num) {
393 		pe = &phb->ioda.pe_array[i];
394 
395 		phb->ioda.m64_segmap[pe->pe_number] = pe->pe_number;
396 		if (!master_pe) {
397 			pe->flags |= PNV_IODA_PE_MASTER;
398 			INIT_LIST_HEAD(&pe->slaves);
399 			master_pe = pe;
400 		} else {
401 			pe->flags |= PNV_IODA_PE_SLAVE;
402 			pe->master = master_pe;
403 			list_add_tail(&pe->list, &master_pe->slaves);
404 		}
405 
406 		/*
407 		 * P7IOC supports M64DT, which helps mapping M64 segment
408 		 * to one particular PE#. However, PHB3 has fixed mapping
409 		 * between M64 segment and PE#. In order to have same logic
410 		 * for P7IOC and PHB3, we enforce fixed mapping between M64
411 		 * segment and PE# on P7IOC.
412 		 */
413 		if (phb->type == PNV_PHB_IODA1) {
414 			int64_t rc;
415 
416 			rc = opal_pci_map_pe_mmio_window(phb->opal_id,
417 					pe->pe_number, OPAL_M64_WINDOW_TYPE,
418 					pe->pe_number / PNV_IODA1_M64_SEGS,
419 					pe->pe_number % PNV_IODA1_M64_SEGS);
420 			if (rc != OPAL_SUCCESS)
421 				pr_warn("%s: Error %lld mapping M64 for PHB#%x-PE#%x\n",
422 					__func__, rc, phb->hose->global_number,
423 					pe->pe_number);
424 		}
425 	}
426 
427 	kfree(pe_alloc);
428 	return master_pe;
429 }
430 
431 static void __init pnv_ioda_parse_m64_window(struct pnv_phb *phb)
432 {
433 	struct pci_controller *hose = phb->hose;
434 	struct device_node *dn = hose->dn;
435 	struct resource *res;
436 	u32 m64_range[2], i;
437 	const __be32 *r;
438 	u64 pci_addr;
439 
440 	if (phb->type != PNV_PHB_IODA1 && phb->type != PNV_PHB_IODA2) {
441 		pr_info("  Not support M64 window\n");
442 		return;
443 	}
444 
445 	if (!firmware_has_feature(FW_FEATURE_OPAL)) {
446 		pr_info("  Firmware too old to support M64 window\n");
447 		return;
448 	}
449 
450 	r = of_get_property(dn, "ibm,opal-m64-window", NULL);
451 	if (!r) {
452 		pr_info("  No <ibm,opal-m64-window> on %pOF\n",
453 			dn);
454 		return;
455 	}
456 
457 	/*
458 	 * Find the available M64 BAR range and pickup the last one for
459 	 * covering the whole 64-bits space. We support only one range.
460 	 */
461 	if (of_property_read_u32_array(dn, "ibm,opal-available-m64-ranges",
462 				       m64_range, 2)) {
463 		/* In absence of the property, assume 0..15 */
464 		m64_range[0] = 0;
465 		m64_range[1] = 16;
466 	}
467 	/* We only support 64 bits in our allocator */
468 	if (m64_range[1] > 63) {
469 		pr_warn("%s: Limiting M64 range to 63 (from %d) on PHB#%x\n",
470 			__func__, m64_range[1], phb->hose->global_number);
471 		m64_range[1] = 63;
472 	}
473 	/* Empty range, no m64 */
474 	if (m64_range[1] <= m64_range[0]) {
475 		pr_warn("%s: M64 empty, disabling M64 usage on PHB#%x\n",
476 			__func__, phb->hose->global_number);
477 		return;
478 	}
479 
480 	/* Configure M64 informations */
481 	res = &hose->mem_resources[1];
482 	res->name = dn->full_name;
483 	res->start = of_translate_address(dn, r + 2);
484 	res->end = res->start + of_read_number(r + 4, 2) - 1;
485 	res->flags = (IORESOURCE_MEM | IORESOURCE_MEM_64 | IORESOURCE_PREFETCH);
486 	pci_addr = of_read_number(r, 2);
487 	hose->mem_offset[1] = res->start - pci_addr;
488 
489 	phb->ioda.m64_size = resource_size(res);
490 	phb->ioda.m64_segsize = phb->ioda.m64_size / phb->ioda.total_pe_num;
491 	phb->ioda.m64_base = pci_addr;
492 
493 	/* This lines up nicely with the display from processing OF ranges */
494 	pr_info(" MEM 0x%016llx..0x%016llx -> 0x%016llx (M64 #%d..%d)\n",
495 		res->start, res->end, pci_addr, m64_range[0],
496 		m64_range[0] + m64_range[1] - 1);
497 
498 	/* Mark all M64 used up by default */
499 	phb->ioda.m64_bar_alloc = (unsigned long)-1;
500 
501 	/* Use last M64 BAR to cover M64 window */
502 	m64_range[1]--;
503 	phb->ioda.m64_bar_idx = m64_range[0] + m64_range[1];
504 
505 	pr_info(" Using M64 #%d as default window\n", phb->ioda.m64_bar_idx);
506 
507 	/* Mark remaining ones free */
508 	for (i = m64_range[0]; i < m64_range[1]; i++)
509 		clear_bit(i, &phb->ioda.m64_bar_alloc);
510 
511 	/*
512 	 * Setup init functions for M64 based on IODA version, IODA3 uses
513 	 * the IODA2 code.
514 	 */
515 	if (phb->type == PNV_PHB_IODA1)
516 		phb->init_m64 = pnv_ioda1_init_m64;
517 	else
518 		phb->init_m64 = pnv_ioda2_init_m64;
519 }
520 
521 static void pnv_ioda_freeze_pe(struct pnv_phb *phb, int pe_no)
522 {
523 	struct pnv_ioda_pe *pe = &phb->ioda.pe_array[pe_no];
524 	struct pnv_ioda_pe *slave;
525 	s64 rc;
526 
527 	/* Fetch master PE */
528 	if (pe->flags & PNV_IODA_PE_SLAVE) {
529 		pe = pe->master;
530 		if (WARN_ON(!pe || !(pe->flags & PNV_IODA_PE_MASTER)))
531 			return;
532 
533 		pe_no = pe->pe_number;
534 	}
535 
536 	/* Freeze master PE */
537 	rc = opal_pci_eeh_freeze_set(phb->opal_id,
538 				     pe_no,
539 				     OPAL_EEH_ACTION_SET_FREEZE_ALL);
540 	if (rc != OPAL_SUCCESS) {
541 		pr_warn("%s: Failure %lld freezing PHB#%x-PE#%x\n",
542 			__func__, rc, phb->hose->global_number, pe_no);
543 		return;
544 	}
545 
546 	/* Freeze slave PEs */
547 	if (!(pe->flags & PNV_IODA_PE_MASTER))
548 		return;
549 
550 	list_for_each_entry(slave, &pe->slaves, list) {
551 		rc = opal_pci_eeh_freeze_set(phb->opal_id,
552 					     slave->pe_number,
553 					     OPAL_EEH_ACTION_SET_FREEZE_ALL);
554 		if (rc != OPAL_SUCCESS)
555 			pr_warn("%s: Failure %lld freezing PHB#%x-PE#%x\n",
556 				__func__, rc, phb->hose->global_number,
557 				slave->pe_number);
558 	}
559 }
560 
561 static int pnv_ioda_unfreeze_pe(struct pnv_phb *phb, int pe_no, int opt)
562 {
563 	struct pnv_ioda_pe *pe, *slave;
564 	s64 rc;
565 
566 	/* Find master PE */
567 	pe = &phb->ioda.pe_array[pe_no];
568 	if (pe->flags & PNV_IODA_PE_SLAVE) {
569 		pe = pe->master;
570 		WARN_ON(!pe || !(pe->flags & PNV_IODA_PE_MASTER));
571 		pe_no = pe->pe_number;
572 	}
573 
574 	/* Clear frozen state for master PE */
575 	rc = opal_pci_eeh_freeze_clear(phb->opal_id, pe_no, opt);
576 	if (rc != OPAL_SUCCESS) {
577 		pr_warn("%s: Failure %lld clear %d on PHB#%x-PE#%x\n",
578 			__func__, rc, opt, phb->hose->global_number, pe_no);
579 		return -EIO;
580 	}
581 
582 	if (!(pe->flags & PNV_IODA_PE_MASTER))
583 		return 0;
584 
585 	/* Clear frozen state for slave PEs */
586 	list_for_each_entry(slave, &pe->slaves, list) {
587 		rc = opal_pci_eeh_freeze_clear(phb->opal_id,
588 					     slave->pe_number,
589 					     opt);
590 		if (rc != OPAL_SUCCESS) {
591 			pr_warn("%s: Failure %lld clear %d on PHB#%x-PE#%x\n",
592 				__func__, rc, opt, phb->hose->global_number,
593 				slave->pe_number);
594 			return -EIO;
595 		}
596 	}
597 
598 	return 0;
599 }
600 
601 static int pnv_ioda_get_pe_state(struct pnv_phb *phb, int pe_no)
602 {
603 	struct pnv_ioda_pe *slave, *pe;
604 	u8 fstate = 0, state;
605 	__be16 pcierr = 0;
606 	s64 rc;
607 
608 	/* Sanity check on PE number */
609 	if (pe_no < 0 || pe_no >= phb->ioda.total_pe_num)
610 		return OPAL_EEH_STOPPED_PERM_UNAVAIL;
611 
612 	/*
613 	 * Fetch the master PE and the PE instance might be
614 	 * not initialized yet.
615 	 */
616 	pe = &phb->ioda.pe_array[pe_no];
617 	if (pe->flags & PNV_IODA_PE_SLAVE) {
618 		pe = pe->master;
619 		WARN_ON(!pe || !(pe->flags & PNV_IODA_PE_MASTER));
620 		pe_no = pe->pe_number;
621 	}
622 
623 	/* Check the master PE */
624 	rc = opal_pci_eeh_freeze_status(phb->opal_id, pe_no,
625 					&state, &pcierr, NULL);
626 	if (rc != OPAL_SUCCESS) {
627 		pr_warn("%s: Failure %lld getting "
628 			"PHB#%x-PE#%x state\n",
629 			__func__, rc,
630 			phb->hose->global_number, pe_no);
631 		return OPAL_EEH_STOPPED_TEMP_UNAVAIL;
632 	}
633 
634 	/* Check the slave PE */
635 	if (!(pe->flags & PNV_IODA_PE_MASTER))
636 		return state;
637 
638 	list_for_each_entry(slave, &pe->slaves, list) {
639 		rc = opal_pci_eeh_freeze_status(phb->opal_id,
640 						slave->pe_number,
641 						&fstate,
642 						&pcierr,
643 						NULL);
644 		if (rc != OPAL_SUCCESS) {
645 			pr_warn("%s: Failure %lld getting "
646 				"PHB#%x-PE#%x state\n",
647 				__func__, rc,
648 				phb->hose->global_number, slave->pe_number);
649 			return OPAL_EEH_STOPPED_TEMP_UNAVAIL;
650 		}
651 
652 		/*
653 		 * Override the result based on the ascending
654 		 * priority.
655 		 */
656 		if (fstate > state)
657 			state = fstate;
658 	}
659 
660 	return state;
661 }
662 
663 struct pnv_ioda_pe *pnv_ioda_get_pe(struct pci_dev *dev)
664 {
665 	struct pci_controller *hose = pci_bus_to_host(dev->bus);
666 	struct pnv_phb *phb = hose->private_data;
667 	struct pci_dn *pdn = pci_get_pdn(dev);
668 
669 	if (!pdn)
670 		return NULL;
671 	if (pdn->pe_number == IODA_INVALID_PE)
672 		return NULL;
673 	return &phb->ioda.pe_array[pdn->pe_number];
674 }
675 
676 static int pnv_ioda_set_one_peltv(struct pnv_phb *phb,
677 				  struct pnv_ioda_pe *parent,
678 				  struct pnv_ioda_pe *child,
679 				  bool is_add)
680 {
681 	const char *desc = is_add ? "adding" : "removing";
682 	uint8_t op = is_add ? OPAL_ADD_PE_TO_DOMAIN :
683 			      OPAL_REMOVE_PE_FROM_DOMAIN;
684 	struct pnv_ioda_pe *slave;
685 	long rc;
686 
687 	/* Parent PE affects child PE */
688 	rc = opal_pci_set_peltv(phb->opal_id, parent->pe_number,
689 				child->pe_number, op);
690 	if (rc != OPAL_SUCCESS) {
691 		pe_warn(child, "OPAL error %ld %s to parent PELTV\n",
692 			rc, desc);
693 		return -ENXIO;
694 	}
695 
696 	if (!(child->flags & PNV_IODA_PE_MASTER))
697 		return 0;
698 
699 	/* Compound case: parent PE affects slave PEs */
700 	list_for_each_entry(slave, &child->slaves, list) {
701 		rc = opal_pci_set_peltv(phb->opal_id, parent->pe_number,
702 					slave->pe_number, op);
703 		if (rc != OPAL_SUCCESS) {
704 			pe_warn(slave, "OPAL error %ld %s to parent PELTV\n",
705 				rc, desc);
706 			return -ENXIO;
707 		}
708 	}
709 
710 	return 0;
711 }
712 
713 static int pnv_ioda_set_peltv(struct pnv_phb *phb,
714 			      struct pnv_ioda_pe *pe,
715 			      bool is_add)
716 {
717 	struct pnv_ioda_pe *slave;
718 	struct pci_dev *pdev = NULL;
719 	int ret;
720 
721 	/*
722 	 * Clear PE frozen state. If it's master PE, we need
723 	 * clear slave PE frozen state as well.
724 	 */
725 	if (is_add) {
726 		opal_pci_eeh_freeze_clear(phb->opal_id, pe->pe_number,
727 					  OPAL_EEH_ACTION_CLEAR_FREEZE_ALL);
728 		if (pe->flags & PNV_IODA_PE_MASTER) {
729 			list_for_each_entry(slave, &pe->slaves, list)
730 				opal_pci_eeh_freeze_clear(phb->opal_id,
731 							  slave->pe_number,
732 							  OPAL_EEH_ACTION_CLEAR_FREEZE_ALL);
733 		}
734 	}
735 
736 	/*
737 	 * Associate PE in PELT. We need add the PE into the
738 	 * corresponding PELT-V as well. Otherwise, the error
739 	 * originated from the PE might contribute to other
740 	 * PEs.
741 	 */
742 	ret = pnv_ioda_set_one_peltv(phb, pe, pe, is_add);
743 	if (ret)
744 		return ret;
745 
746 	/* For compound PEs, any one affects all of them */
747 	if (pe->flags & PNV_IODA_PE_MASTER) {
748 		list_for_each_entry(slave, &pe->slaves, list) {
749 			ret = pnv_ioda_set_one_peltv(phb, slave, pe, is_add);
750 			if (ret)
751 				return ret;
752 		}
753 	}
754 
755 	if (pe->flags & (PNV_IODA_PE_BUS_ALL | PNV_IODA_PE_BUS))
756 		pdev = pe->pbus->self;
757 	else if (pe->flags & PNV_IODA_PE_DEV)
758 		pdev = pe->pdev->bus->self;
759 #ifdef CONFIG_PCI_IOV
760 	else if (pe->flags & PNV_IODA_PE_VF)
761 		pdev = pe->parent_dev;
762 #endif /* CONFIG_PCI_IOV */
763 	while (pdev) {
764 		struct pci_dn *pdn = pci_get_pdn(pdev);
765 		struct pnv_ioda_pe *parent;
766 
767 		if (pdn && pdn->pe_number != IODA_INVALID_PE) {
768 			parent = &phb->ioda.pe_array[pdn->pe_number];
769 			ret = pnv_ioda_set_one_peltv(phb, parent, pe, is_add);
770 			if (ret)
771 				return ret;
772 		}
773 
774 		pdev = pdev->bus->self;
775 	}
776 
777 	return 0;
778 }
779 
780 static void pnv_ioda_unset_peltv(struct pnv_phb *phb,
781 				 struct pnv_ioda_pe *pe,
782 				 struct pci_dev *parent)
783 {
784 	int64_t rc;
785 
786 	while (parent) {
787 		struct pci_dn *pdn = pci_get_pdn(parent);
788 
789 		if (pdn && pdn->pe_number != IODA_INVALID_PE) {
790 			rc = opal_pci_set_peltv(phb->opal_id, pdn->pe_number,
791 						pe->pe_number,
792 						OPAL_REMOVE_PE_FROM_DOMAIN);
793 			/* XXX What to do in case of error ? */
794 		}
795 		parent = parent->bus->self;
796 	}
797 
798 	opal_pci_eeh_freeze_clear(phb->opal_id, pe->pe_number,
799 				  OPAL_EEH_ACTION_CLEAR_FREEZE_ALL);
800 
801 	/* Disassociate PE in PELT */
802 	rc = opal_pci_set_peltv(phb->opal_id, pe->pe_number,
803 				pe->pe_number, OPAL_REMOVE_PE_FROM_DOMAIN);
804 	if (rc)
805 		pe_warn(pe, "OPAL error %lld remove self from PELTV\n", rc);
806 }
807 
808 static int pnv_ioda_deconfigure_pe(struct pnv_phb *phb, struct pnv_ioda_pe *pe)
809 {
810 	struct pci_dev *parent;
811 	uint8_t bcomp, dcomp, fcomp;
812 	int64_t rc;
813 	long rid_end, rid;
814 
815 	/* Currently, we just deconfigure VF PE. Bus PE will always there.*/
816 	if (pe->pbus) {
817 		int count;
818 
819 		dcomp = OPAL_IGNORE_RID_DEVICE_NUMBER;
820 		fcomp = OPAL_IGNORE_RID_FUNCTION_NUMBER;
821 		parent = pe->pbus->self;
822 		if (pe->flags & PNV_IODA_PE_BUS_ALL)
823 			count = resource_size(&pe->pbus->busn_res);
824 		else
825 			count = 1;
826 
827 		switch(count) {
828 		case  1: bcomp = OpalPciBusAll;         break;
829 		case  2: bcomp = OpalPciBus7Bits;       break;
830 		case  4: bcomp = OpalPciBus6Bits;       break;
831 		case  8: bcomp = OpalPciBus5Bits;       break;
832 		case 16: bcomp = OpalPciBus4Bits;       break;
833 		case 32: bcomp = OpalPciBus3Bits;       break;
834 		default:
835 			dev_err(&pe->pbus->dev, "Number of subordinate buses %d unsupported\n",
836 			        count);
837 			/* Do an exact match only */
838 			bcomp = OpalPciBusAll;
839 		}
840 		rid_end = pe->rid + (count << 8);
841 	} else {
842 #ifdef CONFIG_PCI_IOV
843 		if (pe->flags & PNV_IODA_PE_VF)
844 			parent = pe->parent_dev;
845 		else
846 #endif
847 			parent = pe->pdev->bus->self;
848 		bcomp = OpalPciBusAll;
849 		dcomp = OPAL_COMPARE_RID_DEVICE_NUMBER;
850 		fcomp = OPAL_COMPARE_RID_FUNCTION_NUMBER;
851 		rid_end = pe->rid + 1;
852 	}
853 
854 	/* Clear the reverse map */
855 	for (rid = pe->rid; rid < rid_end; rid++)
856 		phb->ioda.pe_rmap[rid] = IODA_INVALID_PE;
857 
858 	/*
859 	 * Release from all parents PELT-V. NPUs don't have a PELTV
860 	 * table
861 	 */
862 	if (phb->type != PNV_PHB_NPU_NVLINK && phb->type != PNV_PHB_NPU_OCAPI)
863 		pnv_ioda_unset_peltv(phb, pe, parent);
864 
865 	rc = opal_pci_set_pe(phb->opal_id, pe->pe_number, pe->rid,
866 			     bcomp, dcomp, fcomp, OPAL_UNMAP_PE);
867 	if (rc)
868 		pe_err(pe, "OPAL error %lld trying to setup PELT table\n", rc);
869 
870 	pe->pbus = NULL;
871 	pe->pdev = NULL;
872 #ifdef CONFIG_PCI_IOV
873 	pe->parent_dev = NULL;
874 #endif
875 
876 	return 0;
877 }
878 
879 static int pnv_ioda_configure_pe(struct pnv_phb *phb, struct pnv_ioda_pe *pe)
880 {
881 	struct pci_dev *parent;
882 	uint8_t bcomp, dcomp, fcomp;
883 	long rc, rid_end, rid;
884 
885 	/* Bus validation ? */
886 	if (pe->pbus) {
887 		int count;
888 
889 		dcomp = OPAL_IGNORE_RID_DEVICE_NUMBER;
890 		fcomp = OPAL_IGNORE_RID_FUNCTION_NUMBER;
891 		parent = pe->pbus->self;
892 		if (pe->flags & PNV_IODA_PE_BUS_ALL)
893 			count = resource_size(&pe->pbus->busn_res);
894 		else
895 			count = 1;
896 
897 		switch(count) {
898 		case  1: bcomp = OpalPciBusAll;		break;
899 		case  2: bcomp = OpalPciBus7Bits;	break;
900 		case  4: bcomp = OpalPciBus6Bits;	break;
901 		case  8: bcomp = OpalPciBus5Bits;	break;
902 		case 16: bcomp = OpalPciBus4Bits;	break;
903 		case 32: bcomp = OpalPciBus3Bits;	break;
904 		default:
905 			dev_err(&pe->pbus->dev, "Number of subordinate buses %d unsupported\n",
906 			        count);
907 			/* Do an exact match only */
908 			bcomp = OpalPciBusAll;
909 		}
910 		rid_end = pe->rid + (count << 8);
911 	} else {
912 #ifdef CONFIG_PCI_IOV
913 		if (pe->flags & PNV_IODA_PE_VF)
914 			parent = pe->parent_dev;
915 		else
916 #endif /* CONFIG_PCI_IOV */
917 			parent = pe->pdev->bus->self;
918 		bcomp = OpalPciBusAll;
919 		dcomp = OPAL_COMPARE_RID_DEVICE_NUMBER;
920 		fcomp = OPAL_COMPARE_RID_FUNCTION_NUMBER;
921 		rid_end = pe->rid + 1;
922 	}
923 
924 	/*
925 	 * Associate PE in PELT. We need add the PE into the
926 	 * corresponding PELT-V as well. Otherwise, the error
927 	 * originated from the PE might contribute to other
928 	 * PEs.
929 	 */
930 	rc = opal_pci_set_pe(phb->opal_id, pe->pe_number, pe->rid,
931 			     bcomp, dcomp, fcomp, OPAL_MAP_PE);
932 	if (rc) {
933 		pe_err(pe, "OPAL error %ld trying to setup PELT table\n", rc);
934 		return -ENXIO;
935 	}
936 
937 	/*
938 	 * Configure PELTV. NPUs don't have a PELTV table so skip
939 	 * configuration on them.
940 	 */
941 	if (phb->type != PNV_PHB_NPU_NVLINK && phb->type != PNV_PHB_NPU_OCAPI)
942 		pnv_ioda_set_peltv(phb, pe, true);
943 
944 	/* Setup reverse map */
945 	for (rid = pe->rid; rid < rid_end; rid++)
946 		phb->ioda.pe_rmap[rid] = pe->pe_number;
947 
948 	/* Setup one MVTs on IODA1 */
949 	if (phb->type != PNV_PHB_IODA1) {
950 		pe->mve_number = 0;
951 		goto out;
952 	}
953 
954 	pe->mve_number = pe->pe_number;
955 	rc = opal_pci_set_mve(phb->opal_id, pe->mve_number, pe->pe_number);
956 	if (rc != OPAL_SUCCESS) {
957 		pe_err(pe, "OPAL error %ld setting up MVE %x\n",
958 		       rc, pe->mve_number);
959 		pe->mve_number = -1;
960 	} else {
961 		rc = opal_pci_set_mve_enable(phb->opal_id,
962 					     pe->mve_number, OPAL_ENABLE_MVE);
963 		if (rc) {
964 			pe_err(pe, "OPAL error %ld enabling MVE %x\n",
965 			       rc, pe->mve_number);
966 			pe->mve_number = -1;
967 		}
968 	}
969 
970 out:
971 	return 0;
972 }
973 
974 #ifdef CONFIG_PCI_IOV
975 static int pnv_pci_vf_resource_shift(struct pci_dev *dev, int offset)
976 {
977 	struct pci_dn *pdn = pci_get_pdn(dev);
978 	int i;
979 	struct resource *res, res2;
980 	resource_size_t size;
981 	u16 num_vfs;
982 
983 	if (!dev->is_physfn)
984 		return -EINVAL;
985 
986 	/*
987 	 * "offset" is in VFs.  The M64 windows are sized so that when they
988 	 * are segmented, each segment is the same size as the IOV BAR.
989 	 * Each segment is in a separate PE, and the high order bits of the
990 	 * address are the PE number.  Therefore, each VF's BAR is in a
991 	 * separate PE, and changing the IOV BAR start address changes the
992 	 * range of PEs the VFs are in.
993 	 */
994 	num_vfs = pdn->num_vfs;
995 	for (i = 0; i < PCI_SRIOV_NUM_BARS; i++) {
996 		res = &dev->resource[i + PCI_IOV_RESOURCES];
997 		if (!res->flags || !res->parent)
998 			continue;
999 
1000 		/*
1001 		 * The actual IOV BAR range is determined by the start address
1002 		 * and the actual size for num_vfs VFs BAR.  This check is to
1003 		 * make sure that after shifting, the range will not overlap
1004 		 * with another device.
1005 		 */
1006 		size = pci_iov_resource_size(dev, i + PCI_IOV_RESOURCES);
1007 		res2.flags = res->flags;
1008 		res2.start = res->start + (size * offset);
1009 		res2.end = res2.start + (size * num_vfs) - 1;
1010 
1011 		if (res2.end > res->end) {
1012 			dev_err(&dev->dev, "VF BAR%d: %pR would extend past %pR (trying to enable %d VFs shifted by %d)\n",
1013 				i, &res2, res, num_vfs, offset);
1014 			return -EBUSY;
1015 		}
1016 	}
1017 
1018 	/*
1019 	 * Since M64 BAR shares segments among all possible 256 PEs,
1020 	 * we have to shift the beginning of PF IOV BAR to make it start from
1021 	 * the segment which belongs to the PE number assigned to the first VF.
1022 	 * This creates a "hole" in the /proc/iomem which could be used for
1023 	 * allocating other resources so we reserve this area below and
1024 	 * release when IOV is released.
1025 	 */
1026 	for (i = 0; i < PCI_SRIOV_NUM_BARS; i++) {
1027 		res = &dev->resource[i + PCI_IOV_RESOURCES];
1028 		if (!res->flags || !res->parent)
1029 			continue;
1030 
1031 		size = pci_iov_resource_size(dev, i + PCI_IOV_RESOURCES);
1032 		res2 = *res;
1033 		res->start += size * offset;
1034 
1035 		dev_info(&dev->dev, "VF BAR%d: %pR shifted to %pR (%sabling %d VFs shifted by %d)\n",
1036 			 i, &res2, res, (offset > 0) ? "En" : "Dis",
1037 			 num_vfs, offset);
1038 
1039 		if (offset < 0) {
1040 			devm_release_resource(&dev->dev, &pdn->holes[i]);
1041 			memset(&pdn->holes[i], 0, sizeof(pdn->holes[i]));
1042 		}
1043 
1044 		pci_update_resource(dev, i + PCI_IOV_RESOURCES);
1045 
1046 		if (offset > 0) {
1047 			pdn->holes[i].start = res2.start;
1048 			pdn->holes[i].end = res2.start + size * offset - 1;
1049 			pdn->holes[i].flags = IORESOURCE_BUS;
1050 			pdn->holes[i].name = "pnv_iov_reserved";
1051 			devm_request_resource(&dev->dev, res->parent,
1052 					&pdn->holes[i]);
1053 		}
1054 	}
1055 	return 0;
1056 }
1057 #endif /* CONFIG_PCI_IOV */
1058 
1059 static struct pnv_ioda_pe *pnv_ioda_setup_dev_PE(struct pci_dev *dev)
1060 {
1061 	struct pci_controller *hose = pci_bus_to_host(dev->bus);
1062 	struct pnv_phb *phb = hose->private_data;
1063 	struct pci_dn *pdn = pci_get_pdn(dev);
1064 	struct pnv_ioda_pe *pe;
1065 
1066 	if (!pdn) {
1067 		pr_err("%s: Device tree node not associated properly\n",
1068 			   pci_name(dev));
1069 		return NULL;
1070 	}
1071 	if (pdn->pe_number != IODA_INVALID_PE)
1072 		return NULL;
1073 
1074 	pe = pnv_ioda_alloc_pe(phb);
1075 	if (!pe) {
1076 		pr_warn("%s: Not enough PE# available, disabling device\n",
1077 			pci_name(dev));
1078 		return NULL;
1079 	}
1080 
1081 	/* NOTE: We don't get a reference for the pointer in the PE
1082 	 * data structure, both the device and PE structures should be
1083 	 * destroyed at the same time. However, removing nvlink
1084 	 * devices will need some work.
1085 	 *
1086 	 * At some point we want to remove the PDN completely anyways
1087 	 */
1088 	pdn->pe_number = pe->pe_number;
1089 	pe->flags = PNV_IODA_PE_DEV;
1090 	pe->pdev = dev;
1091 	pe->pbus = NULL;
1092 	pe->mve_number = -1;
1093 	pe->rid = dev->bus->number << 8 | pdn->devfn;
1094 	pe->device_count++;
1095 
1096 	pe_info(pe, "Associated device to PE\n");
1097 
1098 	if (pnv_ioda_configure_pe(phb, pe)) {
1099 		/* XXX What do we do here ? */
1100 		pnv_ioda_free_pe(pe);
1101 		pdn->pe_number = IODA_INVALID_PE;
1102 		pe->pdev = NULL;
1103 		return NULL;
1104 	}
1105 
1106 	/* Put PE to the list */
1107 	mutex_lock(&phb->ioda.pe_list_mutex);
1108 	list_add_tail(&pe->list, &phb->ioda.pe_list);
1109 	mutex_unlock(&phb->ioda.pe_list_mutex);
1110 	return pe;
1111 }
1112 
1113 static void pnv_ioda_setup_same_PE(struct pci_bus *bus, struct pnv_ioda_pe *pe)
1114 {
1115 	struct pci_dev *dev;
1116 
1117 	list_for_each_entry(dev, &bus->devices, bus_list) {
1118 		struct pci_dn *pdn = pci_get_pdn(dev);
1119 
1120 		if (pdn == NULL) {
1121 			pr_warn("%s: No device node associated with device !\n",
1122 				pci_name(dev));
1123 			continue;
1124 		}
1125 
1126 		/*
1127 		 * In partial hotplug case, the PCI device might be still
1128 		 * associated with the PE and needn't attach it to the PE
1129 		 * again.
1130 		 */
1131 		if (pdn->pe_number != IODA_INVALID_PE)
1132 			continue;
1133 
1134 		pe->device_count++;
1135 		pdn->pe_number = pe->pe_number;
1136 		if ((pe->flags & PNV_IODA_PE_BUS_ALL) && dev->subordinate)
1137 			pnv_ioda_setup_same_PE(dev->subordinate, pe);
1138 	}
1139 }
1140 
1141 /*
1142  * There're 2 types of PCI bus sensitive PEs: One that is compromised of
1143  * single PCI bus. Another one that contains the primary PCI bus and its
1144  * subordinate PCI devices and buses. The second type of PE is normally
1145  * orgiriated by PCIe-to-PCI bridge or PLX switch downstream ports.
1146  */
1147 static struct pnv_ioda_pe *pnv_ioda_setup_bus_PE(struct pci_bus *bus, bool all)
1148 {
1149 	struct pci_controller *hose = pci_bus_to_host(bus);
1150 	struct pnv_phb *phb = hose->private_data;
1151 	struct pnv_ioda_pe *pe = NULL;
1152 	unsigned int pe_num;
1153 
1154 	/*
1155 	 * In partial hotplug case, the PE instance might be still alive.
1156 	 * We should reuse it instead of allocating a new one.
1157 	 */
1158 	pe_num = phb->ioda.pe_rmap[bus->number << 8];
1159 	if (pe_num != IODA_INVALID_PE) {
1160 		pe = &phb->ioda.pe_array[pe_num];
1161 		pnv_ioda_setup_same_PE(bus, pe);
1162 		return NULL;
1163 	}
1164 
1165 	/* PE number for root bus should have been reserved */
1166 	if (pci_is_root_bus(bus) &&
1167 	    phb->ioda.root_pe_idx != IODA_INVALID_PE)
1168 		pe = &phb->ioda.pe_array[phb->ioda.root_pe_idx];
1169 
1170 	/* Check if PE is determined by M64 */
1171 	if (!pe)
1172 		pe = pnv_ioda_pick_m64_pe(bus, all);
1173 
1174 	/* The PE number isn't pinned by M64 */
1175 	if (!pe)
1176 		pe = pnv_ioda_alloc_pe(phb);
1177 
1178 	if (!pe) {
1179 		pr_warn("%s: Not enough PE# available for PCI bus %04x:%02x\n",
1180 			__func__, pci_domain_nr(bus), bus->number);
1181 		return NULL;
1182 	}
1183 
1184 	pe->flags |= (all ? PNV_IODA_PE_BUS_ALL : PNV_IODA_PE_BUS);
1185 	pe->pbus = bus;
1186 	pe->pdev = NULL;
1187 	pe->mve_number = -1;
1188 	pe->rid = bus->busn_res.start << 8;
1189 
1190 	if (all)
1191 		pe_info(pe, "Secondary bus %pad..%pad associated with PE#%x\n",
1192 			&bus->busn_res.start, &bus->busn_res.end,
1193 			pe->pe_number);
1194 	else
1195 		pe_info(pe, "Secondary bus %pad associated with PE#%x\n",
1196 			&bus->busn_res.start, pe->pe_number);
1197 
1198 	if (pnv_ioda_configure_pe(phb, pe)) {
1199 		/* XXX What do we do here ? */
1200 		pnv_ioda_free_pe(pe);
1201 		pe->pbus = NULL;
1202 		return NULL;
1203 	}
1204 
1205 	/* Associate it with all child devices */
1206 	pnv_ioda_setup_same_PE(bus, pe);
1207 
1208 	/* Put PE to the list */
1209 	list_add_tail(&pe->list, &phb->ioda.pe_list);
1210 
1211 	return pe;
1212 }
1213 
1214 static struct pnv_ioda_pe *pnv_ioda_setup_npu_PE(struct pci_dev *npu_pdev)
1215 {
1216 	int pe_num, found_pe = false, rc;
1217 	long rid;
1218 	struct pnv_ioda_pe *pe;
1219 	struct pci_dev *gpu_pdev;
1220 	struct pci_dn *npu_pdn;
1221 	struct pci_controller *hose = pci_bus_to_host(npu_pdev->bus);
1222 	struct pnv_phb *phb = hose->private_data;
1223 
1224 	/*
1225 	 * Intentionally leak a reference on the npu device (for
1226 	 * nvlink only; this is not an opencapi path) to make sure it
1227 	 * never goes away, as it's been the case all along and some
1228 	 * work is needed otherwise.
1229 	 */
1230 	pci_dev_get(npu_pdev);
1231 
1232 	/*
1233 	 * Due to a hardware errata PE#0 on the NPU is reserved for
1234 	 * error handling. This means we only have three PEs remaining
1235 	 * which need to be assigned to four links, implying some
1236 	 * links must share PEs.
1237 	 *
1238 	 * To achieve this we assign PEs such that NPUs linking the
1239 	 * same GPU get assigned the same PE.
1240 	 */
1241 	gpu_pdev = pnv_pci_get_gpu_dev(npu_pdev);
1242 	for (pe_num = 0; pe_num < phb->ioda.total_pe_num; pe_num++) {
1243 		pe = &phb->ioda.pe_array[pe_num];
1244 		if (!pe->pdev)
1245 			continue;
1246 
1247 		if (pnv_pci_get_gpu_dev(pe->pdev) == gpu_pdev) {
1248 			/*
1249 			 * This device has the same peer GPU so should
1250 			 * be assigned the same PE as the existing
1251 			 * peer NPU.
1252 			 */
1253 			dev_info(&npu_pdev->dev,
1254 				"Associating to existing PE %x\n", pe_num);
1255 			npu_pdn = pci_get_pdn(npu_pdev);
1256 			rid = npu_pdev->bus->number << 8 | npu_pdn->devfn;
1257 			npu_pdn->pe_number = pe_num;
1258 			phb->ioda.pe_rmap[rid] = pe->pe_number;
1259 			pe->device_count++;
1260 
1261 			/* Map the PE to this link */
1262 			rc = opal_pci_set_pe(phb->opal_id, pe_num, rid,
1263 					OpalPciBusAll,
1264 					OPAL_COMPARE_RID_DEVICE_NUMBER,
1265 					OPAL_COMPARE_RID_FUNCTION_NUMBER,
1266 					OPAL_MAP_PE);
1267 			WARN_ON(rc != OPAL_SUCCESS);
1268 			found_pe = true;
1269 			break;
1270 		}
1271 	}
1272 
1273 	if (!found_pe)
1274 		/*
1275 		 * Could not find an existing PE so allocate a new
1276 		 * one.
1277 		 */
1278 		return pnv_ioda_setup_dev_PE(npu_pdev);
1279 	else
1280 		return pe;
1281 }
1282 
1283 static void pnv_ioda_setup_npu_PEs(struct pci_bus *bus)
1284 {
1285 	struct pci_dev *pdev;
1286 
1287 	list_for_each_entry(pdev, &bus->devices, bus_list)
1288 		pnv_ioda_setup_npu_PE(pdev);
1289 }
1290 
1291 static void pnv_pci_ioda_setup_PEs(void)
1292 {
1293 	struct pci_controller *hose;
1294 	struct pnv_phb *phb;
1295 	struct pnv_ioda_pe *pe;
1296 
1297 	list_for_each_entry(hose, &hose_list, list_node) {
1298 		phb = hose->private_data;
1299 		if (phb->type == PNV_PHB_NPU_NVLINK) {
1300 			/* PE#0 is needed for error reporting */
1301 			pnv_ioda_reserve_pe(phb, 0);
1302 			pnv_ioda_setup_npu_PEs(hose->bus);
1303 			if (phb->model == PNV_PHB_MODEL_NPU2)
1304 				WARN_ON_ONCE(pnv_npu2_init(hose));
1305 		}
1306 	}
1307 	list_for_each_entry(hose, &hose_list, list_node) {
1308 		phb = hose->private_data;
1309 		if (phb->type != PNV_PHB_IODA2)
1310 			continue;
1311 
1312 		list_for_each_entry(pe, &phb->ioda.pe_list, list)
1313 			pnv_npu2_map_lpar(pe, MSR_DR | MSR_PR | MSR_HV);
1314 	}
1315 }
1316 
1317 #ifdef CONFIG_PCI_IOV
1318 static int pnv_pci_vf_release_m64(struct pci_dev *pdev, u16 num_vfs)
1319 {
1320 	struct pci_bus        *bus;
1321 	struct pci_controller *hose;
1322 	struct pnv_phb        *phb;
1323 	struct pci_dn         *pdn;
1324 	int                    i, j;
1325 	int                    m64_bars;
1326 
1327 	bus = pdev->bus;
1328 	hose = pci_bus_to_host(bus);
1329 	phb = hose->private_data;
1330 	pdn = pci_get_pdn(pdev);
1331 
1332 	if (pdn->m64_single_mode)
1333 		m64_bars = num_vfs;
1334 	else
1335 		m64_bars = 1;
1336 
1337 	for (i = 0; i < PCI_SRIOV_NUM_BARS; i++)
1338 		for (j = 0; j < m64_bars; j++) {
1339 			if (pdn->m64_map[j][i] == IODA_INVALID_M64)
1340 				continue;
1341 			opal_pci_phb_mmio_enable(phb->opal_id,
1342 				OPAL_M64_WINDOW_TYPE, pdn->m64_map[j][i], 0);
1343 			clear_bit(pdn->m64_map[j][i], &phb->ioda.m64_bar_alloc);
1344 			pdn->m64_map[j][i] = IODA_INVALID_M64;
1345 		}
1346 
1347 	kfree(pdn->m64_map);
1348 	return 0;
1349 }
1350 
1351 static int pnv_pci_vf_assign_m64(struct pci_dev *pdev, u16 num_vfs)
1352 {
1353 	struct pci_bus        *bus;
1354 	struct pci_controller *hose;
1355 	struct pnv_phb        *phb;
1356 	struct pci_dn         *pdn;
1357 	unsigned int           win;
1358 	struct resource       *res;
1359 	int                    i, j;
1360 	int64_t                rc;
1361 	int                    total_vfs;
1362 	resource_size_t        size, start;
1363 	int                    pe_num;
1364 	int                    m64_bars;
1365 
1366 	bus = pdev->bus;
1367 	hose = pci_bus_to_host(bus);
1368 	phb = hose->private_data;
1369 	pdn = pci_get_pdn(pdev);
1370 	total_vfs = pci_sriov_get_totalvfs(pdev);
1371 
1372 	if (pdn->m64_single_mode)
1373 		m64_bars = num_vfs;
1374 	else
1375 		m64_bars = 1;
1376 
1377 	pdn->m64_map = kmalloc_array(m64_bars,
1378 				     sizeof(*pdn->m64_map),
1379 				     GFP_KERNEL);
1380 	if (!pdn->m64_map)
1381 		return -ENOMEM;
1382 	/* Initialize the m64_map to IODA_INVALID_M64 */
1383 	for (i = 0; i < m64_bars ; i++)
1384 		for (j = 0; j < PCI_SRIOV_NUM_BARS; j++)
1385 			pdn->m64_map[i][j] = IODA_INVALID_M64;
1386 
1387 
1388 	for (i = 0; i < PCI_SRIOV_NUM_BARS; i++) {
1389 		res = &pdev->resource[i + PCI_IOV_RESOURCES];
1390 		if (!res->flags || !res->parent)
1391 			continue;
1392 
1393 		for (j = 0; j < m64_bars; j++) {
1394 			do {
1395 				win = find_next_zero_bit(&phb->ioda.m64_bar_alloc,
1396 						phb->ioda.m64_bar_idx + 1, 0);
1397 
1398 				if (win >= phb->ioda.m64_bar_idx + 1)
1399 					goto m64_failed;
1400 			} while (test_and_set_bit(win, &phb->ioda.m64_bar_alloc));
1401 
1402 			pdn->m64_map[j][i] = win;
1403 
1404 			if (pdn->m64_single_mode) {
1405 				size = pci_iov_resource_size(pdev,
1406 							PCI_IOV_RESOURCES + i);
1407 				start = res->start + size * j;
1408 			} else {
1409 				size = resource_size(res);
1410 				start = res->start;
1411 			}
1412 
1413 			/* Map the M64 here */
1414 			if (pdn->m64_single_mode) {
1415 				pe_num = pdn->pe_num_map[j];
1416 				rc = opal_pci_map_pe_mmio_window(phb->opal_id,
1417 						pe_num, OPAL_M64_WINDOW_TYPE,
1418 						pdn->m64_map[j][i], 0);
1419 			}
1420 
1421 			rc = opal_pci_set_phb_mem_window(phb->opal_id,
1422 						 OPAL_M64_WINDOW_TYPE,
1423 						 pdn->m64_map[j][i],
1424 						 start,
1425 						 0, /* unused */
1426 						 size);
1427 
1428 
1429 			if (rc != OPAL_SUCCESS) {
1430 				dev_err(&pdev->dev, "Failed to map M64 window #%d: %lld\n",
1431 					win, rc);
1432 				goto m64_failed;
1433 			}
1434 
1435 			if (pdn->m64_single_mode)
1436 				rc = opal_pci_phb_mmio_enable(phb->opal_id,
1437 				     OPAL_M64_WINDOW_TYPE, pdn->m64_map[j][i], 2);
1438 			else
1439 				rc = opal_pci_phb_mmio_enable(phb->opal_id,
1440 				     OPAL_M64_WINDOW_TYPE, pdn->m64_map[j][i], 1);
1441 
1442 			if (rc != OPAL_SUCCESS) {
1443 				dev_err(&pdev->dev, "Failed to enable M64 window #%d: %llx\n",
1444 					win, rc);
1445 				goto m64_failed;
1446 			}
1447 		}
1448 	}
1449 	return 0;
1450 
1451 m64_failed:
1452 	pnv_pci_vf_release_m64(pdev, num_vfs);
1453 	return -EBUSY;
1454 }
1455 
1456 static long pnv_pci_ioda2_unset_window(struct iommu_table_group *table_group,
1457 		int num);
1458 
1459 static void pnv_pci_ioda2_release_dma_pe(struct pci_dev *dev, struct pnv_ioda_pe *pe)
1460 {
1461 	struct iommu_table    *tbl;
1462 	int64_t               rc;
1463 
1464 	tbl = pe->table_group.tables[0];
1465 	rc = pnv_pci_ioda2_unset_window(&pe->table_group, 0);
1466 	if (rc)
1467 		pe_warn(pe, "OPAL error %lld release DMA window\n", rc);
1468 
1469 	pnv_pci_ioda2_set_bypass(pe, false);
1470 	if (pe->table_group.group) {
1471 		iommu_group_put(pe->table_group.group);
1472 		BUG_ON(pe->table_group.group);
1473 	}
1474 	iommu_tce_table_put(tbl);
1475 }
1476 
1477 static void pnv_ioda_release_vf_PE(struct pci_dev *pdev)
1478 {
1479 	struct pci_bus        *bus;
1480 	struct pci_controller *hose;
1481 	struct pnv_phb        *phb;
1482 	struct pnv_ioda_pe    *pe, *pe_n;
1483 	struct pci_dn         *pdn;
1484 
1485 	bus = pdev->bus;
1486 	hose = pci_bus_to_host(bus);
1487 	phb = hose->private_data;
1488 	pdn = pci_get_pdn(pdev);
1489 
1490 	if (!pdev->is_physfn)
1491 		return;
1492 
1493 	list_for_each_entry_safe(pe, pe_n, &phb->ioda.pe_list, list) {
1494 		if (pe->parent_dev != pdev)
1495 			continue;
1496 
1497 		pnv_pci_ioda2_release_dma_pe(pdev, pe);
1498 
1499 		/* Remove from list */
1500 		mutex_lock(&phb->ioda.pe_list_mutex);
1501 		list_del(&pe->list);
1502 		mutex_unlock(&phb->ioda.pe_list_mutex);
1503 
1504 		pnv_ioda_deconfigure_pe(phb, pe);
1505 
1506 		pnv_ioda_free_pe(pe);
1507 	}
1508 }
1509 
1510 void pnv_pci_sriov_disable(struct pci_dev *pdev)
1511 {
1512 	struct pci_bus        *bus;
1513 	struct pci_controller *hose;
1514 	struct pnv_phb        *phb;
1515 	struct pnv_ioda_pe    *pe;
1516 	struct pci_dn         *pdn;
1517 	u16                    num_vfs, i;
1518 
1519 	bus = pdev->bus;
1520 	hose = pci_bus_to_host(bus);
1521 	phb = hose->private_data;
1522 	pdn = pci_get_pdn(pdev);
1523 	num_vfs = pdn->num_vfs;
1524 
1525 	/* Release VF PEs */
1526 	pnv_ioda_release_vf_PE(pdev);
1527 
1528 	if (phb->type == PNV_PHB_IODA2) {
1529 		if (!pdn->m64_single_mode)
1530 			pnv_pci_vf_resource_shift(pdev, -*pdn->pe_num_map);
1531 
1532 		/* Release M64 windows */
1533 		pnv_pci_vf_release_m64(pdev, num_vfs);
1534 
1535 		/* Release PE numbers */
1536 		if (pdn->m64_single_mode) {
1537 			for (i = 0; i < num_vfs; i++) {
1538 				if (pdn->pe_num_map[i] == IODA_INVALID_PE)
1539 					continue;
1540 
1541 				pe = &phb->ioda.pe_array[pdn->pe_num_map[i]];
1542 				pnv_ioda_free_pe(pe);
1543 			}
1544 		} else
1545 			bitmap_clear(phb->ioda.pe_alloc, *pdn->pe_num_map, num_vfs);
1546 		/* Releasing pe_num_map */
1547 		kfree(pdn->pe_num_map);
1548 	}
1549 }
1550 
1551 static void pnv_pci_ioda2_setup_dma_pe(struct pnv_phb *phb,
1552 				       struct pnv_ioda_pe *pe);
1553 #ifdef CONFIG_IOMMU_API
1554 static void pnv_ioda_setup_bus_iommu_group(struct pnv_ioda_pe *pe,
1555 		struct iommu_table_group *table_group, struct pci_bus *bus);
1556 
1557 #endif
1558 static void pnv_ioda_setup_vf_PE(struct pci_dev *pdev, u16 num_vfs)
1559 {
1560 	struct pci_bus        *bus;
1561 	struct pci_controller *hose;
1562 	struct pnv_phb        *phb;
1563 	struct pnv_ioda_pe    *pe;
1564 	int                    pe_num;
1565 	u16                    vf_index;
1566 	struct pci_dn         *pdn;
1567 
1568 	bus = pdev->bus;
1569 	hose = pci_bus_to_host(bus);
1570 	phb = hose->private_data;
1571 	pdn = pci_get_pdn(pdev);
1572 
1573 	if (!pdev->is_physfn)
1574 		return;
1575 
1576 	/* Reserve PE for each VF */
1577 	for (vf_index = 0; vf_index < num_vfs; vf_index++) {
1578 		int vf_devfn = pci_iov_virtfn_devfn(pdev, vf_index);
1579 		int vf_bus = pci_iov_virtfn_bus(pdev, vf_index);
1580 		struct pci_dn *vf_pdn;
1581 
1582 		if (pdn->m64_single_mode)
1583 			pe_num = pdn->pe_num_map[vf_index];
1584 		else
1585 			pe_num = *pdn->pe_num_map + vf_index;
1586 
1587 		pe = &phb->ioda.pe_array[pe_num];
1588 		pe->pe_number = pe_num;
1589 		pe->phb = phb;
1590 		pe->flags = PNV_IODA_PE_VF;
1591 		pe->pbus = NULL;
1592 		pe->parent_dev = pdev;
1593 		pe->mve_number = -1;
1594 		pe->rid = (vf_bus << 8) | vf_devfn;
1595 
1596 		pe_info(pe, "VF %04d:%02d:%02d.%d associated with PE#%x\n",
1597 			hose->global_number, pdev->bus->number,
1598 			PCI_SLOT(vf_devfn), PCI_FUNC(vf_devfn), pe_num);
1599 
1600 		if (pnv_ioda_configure_pe(phb, pe)) {
1601 			/* XXX What do we do here ? */
1602 			pnv_ioda_free_pe(pe);
1603 			pe->pdev = NULL;
1604 			continue;
1605 		}
1606 
1607 		/* Put PE to the list */
1608 		mutex_lock(&phb->ioda.pe_list_mutex);
1609 		list_add_tail(&pe->list, &phb->ioda.pe_list);
1610 		mutex_unlock(&phb->ioda.pe_list_mutex);
1611 
1612 		/* associate this pe to it's pdn */
1613 		list_for_each_entry(vf_pdn, &pdn->parent->child_list, list) {
1614 			if (vf_pdn->busno == vf_bus &&
1615 			    vf_pdn->devfn == vf_devfn) {
1616 				vf_pdn->pe_number = pe_num;
1617 				break;
1618 			}
1619 		}
1620 
1621 		pnv_pci_ioda2_setup_dma_pe(phb, pe);
1622 #ifdef CONFIG_IOMMU_API
1623 		iommu_register_group(&pe->table_group,
1624 				pe->phb->hose->global_number, pe->pe_number);
1625 		pnv_ioda_setup_bus_iommu_group(pe, &pe->table_group, NULL);
1626 #endif
1627 	}
1628 }
1629 
1630 int pnv_pci_sriov_enable(struct pci_dev *pdev, u16 num_vfs)
1631 {
1632 	struct pci_bus        *bus;
1633 	struct pci_controller *hose;
1634 	struct pnv_phb        *phb;
1635 	struct pnv_ioda_pe    *pe;
1636 	struct pci_dn         *pdn;
1637 	int                    ret;
1638 	u16                    i;
1639 
1640 	bus = pdev->bus;
1641 	hose = pci_bus_to_host(bus);
1642 	phb = hose->private_data;
1643 	pdn = pci_get_pdn(pdev);
1644 
1645 	if (phb->type == PNV_PHB_IODA2) {
1646 		if (!pdn->vfs_expanded) {
1647 			dev_info(&pdev->dev, "don't support this SRIOV device"
1648 				" with non 64bit-prefetchable IOV BAR\n");
1649 			return -ENOSPC;
1650 		}
1651 
1652 		/*
1653 		 * When M64 BARs functions in Single PE mode, the number of VFs
1654 		 * could be enabled must be less than the number of M64 BARs.
1655 		 */
1656 		if (pdn->m64_single_mode && num_vfs > phb->ioda.m64_bar_idx) {
1657 			dev_info(&pdev->dev, "Not enough M64 BAR for VFs\n");
1658 			return -EBUSY;
1659 		}
1660 
1661 		/* Allocating pe_num_map */
1662 		if (pdn->m64_single_mode)
1663 			pdn->pe_num_map = kmalloc_array(num_vfs,
1664 							sizeof(*pdn->pe_num_map),
1665 							GFP_KERNEL);
1666 		else
1667 			pdn->pe_num_map = kmalloc(sizeof(*pdn->pe_num_map), GFP_KERNEL);
1668 
1669 		if (!pdn->pe_num_map)
1670 			return -ENOMEM;
1671 
1672 		if (pdn->m64_single_mode)
1673 			for (i = 0; i < num_vfs; i++)
1674 				pdn->pe_num_map[i] = IODA_INVALID_PE;
1675 
1676 		/* Calculate available PE for required VFs */
1677 		if (pdn->m64_single_mode) {
1678 			for (i = 0; i < num_vfs; i++) {
1679 				pe = pnv_ioda_alloc_pe(phb);
1680 				if (!pe) {
1681 					ret = -EBUSY;
1682 					goto m64_failed;
1683 				}
1684 
1685 				pdn->pe_num_map[i] = pe->pe_number;
1686 			}
1687 		} else {
1688 			mutex_lock(&phb->ioda.pe_alloc_mutex);
1689 			*pdn->pe_num_map = bitmap_find_next_zero_area(
1690 				phb->ioda.pe_alloc, phb->ioda.total_pe_num,
1691 				0, num_vfs, 0);
1692 			if (*pdn->pe_num_map >= phb->ioda.total_pe_num) {
1693 				mutex_unlock(&phb->ioda.pe_alloc_mutex);
1694 				dev_info(&pdev->dev, "Failed to enable VF%d\n", num_vfs);
1695 				kfree(pdn->pe_num_map);
1696 				return -EBUSY;
1697 			}
1698 			bitmap_set(phb->ioda.pe_alloc, *pdn->pe_num_map, num_vfs);
1699 			mutex_unlock(&phb->ioda.pe_alloc_mutex);
1700 		}
1701 		pdn->num_vfs = num_vfs;
1702 
1703 		/* Assign M64 window accordingly */
1704 		ret = pnv_pci_vf_assign_m64(pdev, num_vfs);
1705 		if (ret) {
1706 			dev_info(&pdev->dev, "Not enough M64 window resources\n");
1707 			goto m64_failed;
1708 		}
1709 
1710 		/*
1711 		 * When using one M64 BAR to map one IOV BAR, we need to shift
1712 		 * the IOV BAR according to the PE# allocated to the VFs.
1713 		 * Otherwise, the PE# for the VF will conflict with others.
1714 		 */
1715 		if (!pdn->m64_single_mode) {
1716 			ret = pnv_pci_vf_resource_shift(pdev, *pdn->pe_num_map);
1717 			if (ret)
1718 				goto m64_failed;
1719 		}
1720 	}
1721 
1722 	/* Setup VF PEs */
1723 	pnv_ioda_setup_vf_PE(pdev, num_vfs);
1724 
1725 	return 0;
1726 
1727 m64_failed:
1728 	if (pdn->m64_single_mode) {
1729 		for (i = 0; i < num_vfs; i++) {
1730 			if (pdn->pe_num_map[i] == IODA_INVALID_PE)
1731 				continue;
1732 
1733 			pe = &phb->ioda.pe_array[pdn->pe_num_map[i]];
1734 			pnv_ioda_free_pe(pe);
1735 		}
1736 	} else
1737 		bitmap_clear(phb->ioda.pe_alloc, *pdn->pe_num_map, num_vfs);
1738 
1739 	/* Releasing pe_num_map */
1740 	kfree(pdn->pe_num_map);
1741 
1742 	return ret;
1743 }
1744 
1745 int pnv_pcibios_sriov_disable(struct pci_dev *pdev)
1746 {
1747 	pnv_pci_sriov_disable(pdev);
1748 
1749 	/* Release PCI data */
1750 	remove_sriov_vf_pdns(pdev);
1751 	return 0;
1752 }
1753 
1754 int pnv_pcibios_sriov_enable(struct pci_dev *pdev, u16 num_vfs)
1755 {
1756 	/* Allocate PCI data */
1757 	add_sriov_vf_pdns(pdev);
1758 
1759 	return pnv_pci_sriov_enable(pdev, num_vfs);
1760 }
1761 #endif /* CONFIG_PCI_IOV */
1762 
1763 static void pnv_pci_ioda_dma_dev_setup(struct pci_dev *pdev)
1764 {
1765 	struct pci_controller *hose = pci_bus_to_host(pdev->bus);
1766 	struct pnv_phb *phb = hose->private_data;
1767 	struct pci_dn *pdn = pci_get_pdn(pdev);
1768 	struct pnv_ioda_pe *pe;
1769 
1770 	/*
1771 	 * The function can be called while the PE#
1772 	 * hasn't been assigned. Do nothing for the
1773 	 * case.
1774 	 */
1775 	if (!pdn || pdn->pe_number == IODA_INVALID_PE)
1776 		return;
1777 
1778 	pe = &phb->ioda.pe_array[pdn->pe_number];
1779 	WARN_ON(get_dma_ops(&pdev->dev) != &dma_iommu_ops);
1780 	pdev->dev.archdata.dma_offset = pe->tce_bypass_base;
1781 	set_iommu_table_base(&pdev->dev, pe->table_group.tables[0]);
1782 	/*
1783 	 * Note: iommu_add_device() will fail here as
1784 	 * for physical PE: the device is already added by now;
1785 	 * for virtual PE: sysfs entries are not ready yet and
1786 	 * tce_iommu_bus_notifier will add the device to a group later.
1787 	 */
1788 }
1789 
1790 /*
1791  * Reconfigure TVE#0 to be usable as 64-bit DMA space.
1792  *
1793  * The first 4GB of virtual memory for a PE is reserved for 32-bit accesses.
1794  * Devices can only access more than that if bit 59 of the PCI address is set
1795  * by hardware, which indicates TVE#1 should be used instead of TVE#0.
1796  * Many PCI devices are not capable of addressing that many bits, and as a
1797  * result are limited to the 4GB of virtual memory made available to 32-bit
1798  * devices in TVE#0.
1799  *
1800  * In order to work around this, reconfigure TVE#0 to be suitable for 64-bit
1801  * devices by configuring the virtual memory past the first 4GB inaccessible
1802  * by 64-bit DMAs.  This should only be used by devices that want more than
1803  * 4GB, and only on PEs that have no 32-bit devices.
1804  *
1805  * Currently this will only work on PHB3 (POWER8).
1806  */
1807 static int pnv_pci_ioda_dma_64bit_bypass(struct pnv_ioda_pe *pe)
1808 {
1809 	u64 window_size, table_size, tce_count, addr;
1810 	struct page *table_pages;
1811 	u64 tce_order = 28; /* 256MB TCEs */
1812 	__be64 *tces;
1813 	s64 rc;
1814 
1815 	/*
1816 	 * Window size needs to be a power of two, but needs to account for
1817 	 * shifting memory by the 4GB offset required to skip 32bit space.
1818 	 */
1819 	window_size = roundup_pow_of_two(memory_hotplug_max() + (1ULL << 32));
1820 	tce_count = window_size >> tce_order;
1821 	table_size = tce_count << 3;
1822 
1823 	if (table_size < PAGE_SIZE)
1824 		table_size = PAGE_SIZE;
1825 
1826 	table_pages = alloc_pages_node(pe->phb->hose->node, GFP_KERNEL,
1827 				       get_order(table_size));
1828 	if (!table_pages)
1829 		goto err;
1830 
1831 	tces = page_address(table_pages);
1832 	if (!tces)
1833 		goto err;
1834 
1835 	memset(tces, 0, table_size);
1836 
1837 	for (addr = 0; addr < memory_hotplug_max(); addr += (1 << tce_order)) {
1838 		tces[(addr + (1ULL << 32)) >> tce_order] =
1839 			cpu_to_be64(addr | TCE_PCI_READ | TCE_PCI_WRITE);
1840 	}
1841 
1842 	rc = opal_pci_map_pe_dma_window(pe->phb->opal_id,
1843 					pe->pe_number,
1844 					/* reconfigure window 0 */
1845 					(pe->pe_number << 1) + 0,
1846 					1,
1847 					__pa(tces),
1848 					table_size,
1849 					1 << tce_order);
1850 	if (rc == OPAL_SUCCESS) {
1851 		pe_info(pe, "Using 64-bit DMA iommu bypass (through TVE#0)\n");
1852 		return 0;
1853 	}
1854 err:
1855 	pe_err(pe, "Error configuring 64-bit DMA bypass\n");
1856 	return -EIO;
1857 }
1858 
1859 static bool pnv_pci_ioda_iommu_bypass_supported(struct pci_dev *pdev,
1860 		u64 dma_mask)
1861 {
1862 	struct pci_controller *hose = pci_bus_to_host(pdev->bus);
1863 	struct pnv_phb *phb = hose->private_data;
1864 	struct pci_dn *pdn = pci_get_pdn(pdev);
1865 	struct pnv_ioda_pe *pe;
1866 
1867 	if (WARN_ON(!pdn || pdn->pe_number == IODA_INVALID_PE))
1868 		return false;
1869 
1870 	pe = &phb->ioda.pe_array[pdn->pe_number];
1871 	if (pe->tce_bypass_enabled) {
1872 		u64 top = pe->tce_bypass_base + memblock_end_of_DRAM() - 1;
1873 		if (dma_mask >= top)
1874 			return true;
1875 	}
1876 
1877 	/*
1878 	 * If the device can't set the TCE bypass bit but still wants
1879 	 * to access 4GB or more, on PHB3 we can reconfigure TVE#0 to
1880 	 * bypass the 32-bit region and be usable for 64-bit DMAs.
1881 	 * The device needs to be able to address all of this space.
1882 	 */
1883 	if (dma_mask >> 32 &&
1884 	    dma_mask > (memory_hotplug_max() + (1ULL << 32)) &&
1885 	    /* pe->pdev should be set if it's a single device, pe->pbus if not */
1886 	    (pe->device_count == 1 || !pe->pbus) &&
1887 	    phb->model == PNV_PHB_MODEL_PHB3) {
1888 		/* Configure the bypass mode */
1889 		s64 rc = pnv_pci_ioda_dma_64bit_bypass(pe);
1890 		if (rc)
1891 			return false;
1892 		/* 4GB offset bypasses 32-bit space */
1893 		pdev->dev.archdata.dma_offset = (1ULL << 32);
1894 		return true;
1895 	}
1896 
1897 	return false;
1898 }
1899 
1900 static void pnv_ioda_setup_bus_dma(struct pnv_ioda_pe *pe, struct pci_bus *bus)
1901 {
1902 	struct pci_dev *dev;
1903 
1904 	list_for_each_entry(dev, &bus->devices, bus_list) {
1905 		set_iommu_table_base(&dev->dev, pe->table_group.tables[0]);
1906 		dev->dev.archdata.dma_offset = pe->tce_bypass_base;
1907 
1908 		if ((pe->flags & PNV_IODA_PE_BUS_ALL) && dev->subordinate)
1909 			pnv_ioda_setup_bus_dma(pe, dev->subordinate);
1910 	}
1911 }
1912 
1913 static inline __be64 __iomem *pnv_ioda_get_inval_reg(struct pnv_phb *phb,
1914 						     bool real_mode)
1915 {
1916 	return real_mode ? (__be64 __iomem *)(phb->regs_phys + 0x210) :
1917 		(phb->regs + 0x210);
1918 }
1919 
1920 static void pnv_pci_p7ioc_tce_invalidate(struct iommu_table *tbl,
1921 		unsigned long index, unsigned long npages, bool rm)
1922 {
1923 	struct iommu_table_group_link *tgl = list_first_entry_or_null(
1924 			&tbl->it_group_list, struct iommu_table_group_link,
1925 			next);
1926 	struct pnv_ioda_pe *pe = container_of(tgl->table_group,
1927 			struct pnv_ioda_pe, table_group);
1928 	__be64 __iomem *invalidate = pnv_ioda_get_inval_reg(pe->phb, rm);
1929 	unsigned long start, end, inc;
1930 
1931 	start = __pa(((__be64 *)tbl->it_base) + index - tbl->it_offset);
1932 	end = __pa(((__be64 *)tbl->it_base) + index - tbl->it_offset +
1933 			npages - 1);
1934 
1935 	/* p7ioc-style invalidation, 2 TCEs per write */
1936 	start |= (1ull << 63);
1937 	end |= (1ull << 63);
1938 	inc = 16;
1939         end |= inc - 1;	/* round up end to be different than start */
1940 
1941         mb(); /* Ensure above stores are visible */
1942         while (start <= end) {
1943 		if (rm)
1944 			__raw_rm_writeq_be(start, invalidate);
1945 		else
1946 			__raw_writeq_be(start, invalidate);
1947 
1948                 start += inc;
1949         }
1950 
1951 	/*
1952 	 * The iommu layer will do another mb() for us on build()
1953 	 * and we don't care on free()
1954 	 */
1955 }
1956 
1957 static int pnv_ioda1_tce_build(struct iommu_table *tbl, long index,
1958 		long npages, unsigned long uaddr,
1959 		enum dma_data_direction direction,
1960 		unsigned long attrs)
1961 {
1962 	int ret = pnv_tce_build(tbl, index, npages, uaddr, direction,
1963 			attrs);
1964 
1965 	if (!ret)
1966 		pnv_pci_p7ioc_tce_invalidate(tbl, index, npages, false);
1967 
1968 	return ret;
1969 }
1970 
1971 #ifdef CONFIG_IOMMU_API
1972 /* Common for IODA1 and IODA2 */
1973 static int pnv_ioda_tce_xchg_no_kill(struct iommu_table *tbl, long index,
1974 		unsigned long *hpa, enum dma_data_direction *direction,
1975 		bool realmode)
1976 {
1977 	return pnv_tce_xchg(tbl, index, hpa, direction, !realmode);
1978 }
1979 #endif
1980 
1981 static void pnv_ioda1_tce_free(struct iommu_table *tbl, long index,
1982 		long npages)
1983 {
1984 	pnv_tce_free(tbl, index, npages);
1985 
1986 	pnv_pci_p7ioc_tce_invalidate(tbl, index, npages, false);
1987 }
1988 
1989 static struct iommu_table_ops pnv_ioda1_iommu_ops = {
1990 	.set = pnv_ioda1_tce_build,
1991 #ifdef CONFIG_IOMMU_API
1992 	.xchg_no_kill = pnv_ioda_tce_xchg_no_kill,
1993 	.tce_kill = pnv_pci_p7ioc_tce_invalidate,
1994 	.useraddrptr = pnv_tce_useraddrptr,
1995 #endif
1996 	.clear = pnv_ioda1_tce_free,
1997 	.get = pnv_tce_get,
1998 };
1999 
2000 #define PHB3_TCE_KILL_INVAL_ALL		PPC_BIT(0)
2001 #define PHB3_TCE_KILL_INVAL_PE		PPC_BIT(1)
2002 #define PHB3_TCE_KILL_INVAL_ONE		PPC_BIT(2)
2003 
2004 static void pnv_pci_phb3_tce_invalidate_entire(struct pnv_phb *phb, bool rm)
2005 {
2006 	__be64 __iomem *invalidate = pnv_ioda_get_inval_reg(phb, rm);
2007 	const unsigned long val = PHB3_TCE_KILL_INVAL_ALL;
2008 
2009 	mb(); /* Ensure previous TCE table stores are visible */
2010 	if (rm)
2011 		__raw_rm_writeq_be(val, invalidate);
2012 	else
2013 		__raw_writeq_be(val, invalidate);
2014 }
2015 
2016 static inline void pnv_pci_phb3_tce_invalidate_pe(struct pnv_ioda_pe *pe)
2017 {
2018 	/* 01xb - invalidate TCEs that match the specified PE# */
2019 	__be64 __iomem *invalidate = pnv_ioda_get_inval_reg(pe->phb, false);
2020 	unsigned long val = PHB3_TCE_KILL_INVAL_PE | (pe->pe_number & 0xFF);
2021 
2022 	mb(); /* Ensure above stores are visible */
2023 	__raw_writeq_be(val, invalidate);
2024 }
2025 
2026 static void pnv_pci_phb3_tce_invalidate(struct pnv_ioda_pe *pe, bool rm,
2027 					unsigned shift, unsigned long index,
2028 					unsigned long npages)
2029 {
2030 	__be64 __iomem *invalidate = pnv_ioda_get_inval_reg(pe->phb, rm);
2031 	unsigned long start, end, inc;
2032 
2033 	/* We'll invalidate DMA address in PE scope */
2034 	start = PHB3_TCE_KILL_INVAL_ONE;
2035 	start |= (pe->pe_number & 0xFF);
2036 	end = start;
2037 
2038 	/* Figure out the start, end and step */
2039 	start |= (index << shift);
2040 	end |= ((index + npages - 1) << shift);
2041 	inc = (0x1ull << shift);
2042 	mb();
2043 
2044 	while (start <= end) {
2045 		if (rm)
2046 			__raw_rm_writeq_be(start, invalidate);
2047 		else
2048 			__raw_writeq_be(start, invalidate);
2049 		start += inc;
2050 	}
2051 }
2052 
2053 static inline void pnv_pci_ioda2_tce_invalidate_pe(struct pnv_ioda_pe *pe)
2054 {
2055 	struct pnv_phb *phb = pe->phb;
2056 
2057 	if (phb->model == PNV_PHB_MODEL_PHB3 && phb->regs)
2058 		pnv_pci_phb3_tce_invalidate_pe(pe);
2059 	else
2060 		opal_pci_tce_kill(phb->opal_id, OPAL_PCI_TCE_KILL_PE,
2061 				  pe->pe_number, 0, 0, 0);
2062 }
2063 
2064 static void pnv_pci_ioda2_tce_invalidate(struct iommu_table *tbl,
2065 		unsigned long index, unsigned long npages, bool rm)
2066 {
2067 	struct iommu_table_group_link *tgl;
2068 
2069 	list_for_each_entry_lockless(tgl, &tbl->it_group_list, next) {
2070 		struct pnv_ioda_pe *pe = container_of(tgl->table_group,
2071 				struct pnv_ioda_pe, table_group);
2072 		struct pnv_phb *phb = pe->phb;
2073 		unsigned int shift = tbl->it_page_shift;
2074 
2075 		/*
2076 		 * NVLink1 can use the TCE kill register directly as
2077 		 * it's the same as PHB3. NVLink2 is different and
2078 		 * should go via the OPAL call.
2079 		 */
2080 		if (phb->model == PNV_PHB_MODEL_NPU) {
2081 			/*
2082 			 * The NVLink hardware does not support TCE kill
2083 			 * per TCE entry so we have to invalidate
2084 			 * the entire cache for it.
2085 			 */
2086 			pnv_pci_phb3_tce_invalidate_entire(phb, rm);
2087 			continue;
2088 		}
2089 		if (phb->model == PNV_PHB_MODEL_PHB3 && phb->regs)
2090 			pnv_pci_phb3_tce_invalidate(pe, rm, shift,
2091 						    index, npages);
2092 		else
2093 			opal_pci_tce_kill(phb->opal_id,
2094 					  OPAL_PCI_TCE_KILL_PAGES,
2095 					  pe->pe_number, 1u << shift,
2096 					  index << shift, npages);
2097 	}
2098 }
2099 
2100 void pnv_pci_ioda2_tce_invalidate_entire(struct pnv_phb *phb, bool rm)
2101 {
2102 	if (phb->model == PNV_PHB_MODEL_NPU || phb->model == PNV_PHB_MODEL_PHB3)
2103 		pnv_pci_phb3_tce_invalidate_entire(phb, rm);
2104 	else
2105 		opal_pci_tce_kill(phb->opal_id, OPAL_PCI_TCE_KILL, 0, 0, 0, 0);
2106 }
2107 
2108 static int pnv_ioda2_tce_build(struct iommu_table *tbl, long index,
2109 		long npages, unsigned long uaddr,
2110 		enum dma_data_direction direction,
2111 		unsigned long attrs)
2112 {
2113 	int ret = pnv_tce_build(tbl, index, npages, uaddr, direction,
2114 			attrs);
2115 
2116 	if (!ret)
2117 		pnv_pci_ioda2_tce_invalidate(tbl, index, npages, false);
2118 
2119 	return ret;
2120 }
2121 
2122 static void pnv_ioda2_tce_free(struct iommu_table *tbl, long index,
2123 		long npages)
2124 {
2125 	pnv_tce_free(tbl, index, npages);
2126 
2127 	pnv_pci_ioda2_tce_invalidate(tbl, index, npages, false);
2128 }
2129 
2130 static struct iommu_table_ops pnv_ioda2_iommu_ops = {
2131 	.set = pnv_ioda2_tce_build,
2132 #ifdef CONFIG_IOMMU_API
2133 	.xchg_no_kill = pnv_ioda_tce_xchg_no_kill,
2134 	.tce_kill = pnv_pci_ioda2_tce_invalidate,
2135 	.useraddrptr = pnv_tce_useraddrptr,
2136 #endif
2137 	.clear = pnv_ioda2_tce_free,
2138 	.get = pnv_tce_get,
2139 	.free = pnv_pci_ioda2_table_free_pages,
2140 };
2141 
2142 static int pnv_pci_ioda_dev_dma_weight(struct pci_dev *dev, void *data)
2143 {
2144 	unsigned int *weight = (unsigned int *)data;
2145 
2146 	/* This is quite simplistic. The "base" weight of a device
2147 	 * is 10. 0 means no DMA is to be accounted for it.
2148 	 */
2149 	if (dev->hdr_type != PCI_HEADER_TYPE_NORMAL)
2150 		return 0;
2151 
2152 	if (dev->class == PCI_CLASS_SERIAL_USB_UHCI ||
2153 	    dev->class == PCI_CLASS_SERIAL_USB_OHCI ||
2154 	    dev->class == PCI_CLASS_SERIAL_USB_EHCI)
2155 		*weight += 3;
2156 	else if ((dev->class >> 8) == PCI_CLASS_STORAGE_RAID)
2157 		*weight += 15;
2158 	else
2159 		*weight += 10;
2160 
2161 	return 0;
2162 }
2163 
2164 static unsigned int pnv_pci_ioda_pe_dma_weight(struct pnv_ioda_pe *pe)
2165 {
2166 	unsigned int weight = 0;
2167 
2168 	/* SRIOV VF has same DMA32 weight as its PF */
2169 #ifdef CONFIG_PCI_IOV
2170 	if ((pe->flags & PNV_IODA_PE_VF) && pe->parent_dev) {
2171 		pnv_pci_ioda_dev_dma_weight(pe->parent_dev, &weight);
2172 		return weight;
2173 	}
2174 #endif
2175 
2176 	if ((pe->flags & PNV_IODA_PE_DEV) && pe->pdev) {
2177 		pnv_pci_ioda_dev_dma_weight(pe->pdev, &weight);
2178 	} else if ((pe->flags & PNV_IODA_PE_BUS) && pe->pbus) {
2179 		struct pci_dev *pdev;
2180 
2181 		list_for_each_entry(pdev, &pe->pbus->devices, bus_list)
2182 			pnv_pci_ioda_dev_dma_weight(pdev, &weight);
2183 	} else if ((pe->flags & PNV_IODA_PE_BUS_ALL) && pe->pbus) {
2184 		pci_walk_bus(pe->pbus, pnv_pci_ioda_dev_dma_weight, &weight);
2185 	}
2186 
2187 	return weight;
2188 }
2189 
2190 static void pnv_pci_ioda1_setup_dma_pe(struct pnv_phb *phb,
2191 				       struct pnv_ioda_pe *pe)
2192 {
2193 
2194 	struct page *tce_mem = NULL;
2195 	struct iommu_table *tbl;
2196 	unsigned int weight, total_weight = 0;
2197 	unsigned int tce32_segsz, base, segs, avail, i;
2198 	int64_t rc;
2199 	void *addr;
2200 
2201 	/* XXX FIXME: Handle 64-bit only DMA devices */
2202 	/* XXX FIXME: Provide 64-bit DMA facilities & non-4K TCE tables etc.. */
2203 	/* XXX FIXME: Allocate multi-level tables on PHB3 */
2204 	weight = pnv_pci_ioda_pe_dma_weight(pe);
2205 	if (!weight)
2206 		return;
2207 
2208 	pci_walk_bus(phb->hose->bus, pnv_pci_ioda_dev_dma_weight,
2209 		     &total_weight);
2210 	segs = (weight * phb->ioda.dma32_count) / total_weight;
2211 	if (!segs)
2212 		segs = 1;
2213 
2214 	/*
2215 	 * Allocate contiguous DMA32 segments. We begin with the expected
2216 	 * number of segments. With one more attempt, the number of DMA32
2217 	 * segments to be allocated is decreased by one until one segment
2218 	 * is allocated successfully.
2219 	 */
2220 	do {
2221 		for (base = 0; base <= phb->ioda.dma32_count - segs; base++) {
2222 			for (avail = 0, i = base; i < base + segs; i++) {
2223 				if (phb->ioda.dma32_segmap[i] ==
2224 				    IODA_INVALID_PE)
2225 					avail++;
2226 			}
2227 
2228 			if (avail == segs)
2229 				goto found;
2230 		}
2231 	} while (--segs);
2232 
2233 	if (!segs) {
2234 		pe_warn(pe, "No available DMA32 segments\n");
2235 		return;
2236 	}
2237 
2238 found:
2239 	tbl = pnv_pci_table_alloc(phb->hose->node);
2240 	if (WARN_ON(!tbl))
2241 		return;
2242 
2243 	iommu_register_group(&pe->table_group, phb->hose->global_number,
2244 			pe->pe_number);
2245 	pnv_pci_link_table_and_group(phb->hose->node, 0, tbl, &pe->table_group);
2246 
2247 	/* Grab a 32-bit TCE table */
2248 	pe_info(pe, "DMA weight %d (%d), assigned (%d) %d DMA32 segments\n",
2249 		weight, total_weight, base, segs);
2250 	pe_info(pe, " Setting up 32-bit TCE table at %08x..%08x\n",
2251 		base * PNV_IODA1_DMA32_SEGSIZE,
2252 		(base + segs) * PNV_IODA1_DMA32_SEGSIZE - 1);
2253 
2254 	/* XXX Currently, we allocate one big contiguous table for the
2255 	 * TCEs. We only really need one chunk per 256M of TCE space
2256 	 * (ie per segment) but that's an optimization for later, it
2257 	 * requires some added smarts with our get/put_tce implementation
2258 	 *
2259 	 * Each TCE page is 4KB in size and each TCE entry occupies 8
2260 	 * bytes
2261 	 */
2262 	tce32_segsz = PNV_IODA1_DMA32_SEGSIZE >> (IOMMU_PAGE_SHIFT_4K - 3);
2263 	tce_mem = alloc_pages_node(phb->hose->node, GFP_KERNEL,
2264 				   get_order(tce32_segsz * segs));
2265 	if (!tce_mem) {
2266 		pe_err(pe, " Failed to allocate a 32-bit TCE memory\n");
2267 		goto fail;
2268 	}
2269 	addr = page_address(tce_mem);
2270 	memset(addr, 0, tce32_segsz * segs);
2271 
2272 	/* Configure HW */
2273 	for (i = 0; i < segs; i++) {
2274 		rc = opal_pci_map_pe_dma_window(phb->opal_id,
2275 					      pe->pe_number,
2276 					      base + i, 1,
2277 					      __pa(addr) + tce32_segsz * i,
2278 					      tce32_segsz, IOMMU_PAGE_SIZE_4K);
2279 		if (rc) {
2280 			pe_err(pe, " Failed to configure 32-bit TCE table, err %lld\n",
2281 			       rc);
2282 			goto fail;
2283 		}
2284 	}
2285 
2286 	/* Setup DMA32 segment mapping */
2287 	for (i = base; i < base + segs; i++)
2288 		phb->ioda.dma32_segmap[i] = pe->pe_number;
2289 
2290 	/* Setup linux iommu table */
2291 	pnv_pci_setup_iommu_table(tbl, addr, tce32_segsz * segs,
2292 				  base * PNV_IODA1_DMA32_SEGSIZE,
2293 				  IOMMU_PAGE_SHIFT_4K);
2294 
2295 	tbl->it_ops = &pnv_ioda1_iommu_ops;
2296 	pe->table_group.tce32_start = tbl->it_offset << tbl->it_page_shift;
2297 	pe->table_group.tce32_size = tbl->it_size << tbl->it_page_shift;
2298 	iommu_init_table(tbl, phb->hose->node, 0, 0);
2299 
2300 	if (pe->flags & (PNV_IODA_PE_BUS | PNV_IODA_PE_BUS_ALL))
2301 		pnv_ioda_setup_bus_dma(pe, pe->pbus);
2302 
2303 	return;
2304  fail:
2305 	/* XXX Failure: Try to fallback to 64-bit only ? */
2306 	if (tce_mem)
2307 		__free_pages(tce_mem, get_order(tce32_segsz * segs));
2308 	if (tbl) {
2309 		pnv_pci_unlink_table_and_group(tbl, &pe->table_group);
2310 		iommu_tce_table_put(tbl);
2311 	}
2312 }
2313 
2314 static long pnv_pci_ioda2_set_window(struct iommu_table_group *table_group,
2315 		int num, struct iommu_table *tbl)
2316 {
2317 	struct pnv_ioda_pe *pe = container_of(table_group, struct pnv_ioda_pe,
2318 			table_group);
2319 	struct pnv_phb *phb = pe->phb;
2320 	int64_t rc;
2321 	const unsigned long size = tbl->it_indirect_levels ?
2322 			tbl->it_level_size : tbl->it_size;
2323 	const __u64 start_addr = tbl->it_offset << tbl->it_page_shift;
2324 	const __u64 win_size = tbl->it_size << tbl->it_page_shift;
2325 
2326 	pe_info(pe, "Setting up window#%d %llx..%llx pg=%lx\n",
2327 		num, start_addr, start_addr + win_size - 1,
2328 		IOMMU_PAGE_SIZE(tbl));
2329 
2330 	/*
2331 	 * Map TCE table through TVT. The TVE index is the PE number
2332 	 * shifted by 1 bit for 32-bits DMA space.
2333 	 */
2334 	rc = opal_pci_map_pe_dma_window(phb->opal_id,
2335 			pe->pe_number,
2336 			(pe->pe_number << 1) + num,
2337 			tbl->it_indirect_levels + 1,
2338 			__pa(tbl->it_base),
2339 			size << 3,
2340 			IOMMU_PAGE_SIZE(tbl));
2341 	if (rc) {
2342 		pe_err(pe, "Failed to configure TCE table, err %lld\n", rc);
2343 		return rc;
2344 	}
2345 
2346 	pnv_pci_link_table_and_group(phb->hose->node, num,
2347 			tbl, &pe->table_group);
2348 	pnv_pci_ioda2_tce_invalidate_pe(pe);
2349 
2350 	return 0;
2351 }
2352 
2353 static void pnv_pci_ioda2_set_bypass(struct pnv_ioda_pe *pe, bool enable)
2354 {
2355 	uint16_t window_id = (pe->pe_number << 1 ) + 1;
2356 	int64_t rc;
2357 
2358 	pe_info(pe, "%sabling 64-bit DMA bypass\n", enable ? "En" : "Dis");
2359 	if (enable) {
2360 		phys_addr_t top = memblock_end_of_DRAM();
2361 
2362 		top = roundup_pow_of_two(top);
2363 		rc = opal_pci_map_pe_dma_window_real(pe->phb->opal_id,
2364 						     pe->pe_number,
2365 						     window_id,
2366 						     pe->tce_bypass_base,
2367 						     top);
2368 	} else {
2369 		rc = opal_pci_map_pe_dma_window_real(pe->phb->opal_id,
2370 						     pe->pe_number,
2371 						     window_id,
2372 						     pe->tce_bypass_base,
2373 						     0);
2374 	}
2375 	if (rc)
2376 		pe_err(pe, "OPAL error %lld configuring bypass window\n", rc);
2377 	else
2378 		pe->tce_bypass_enabled = enable;
2379 }
2380 
2381 static long pnv_pci_ioda2_create_table(struct iommu_table_group *table_group,
2382 		int num, __u32 page_shift, __u64 window_size, __u32 levels,
2383 		bool alloc_userspace_copy, struct iommu_table **ptbl)
2384 {
2385 	struct pnv_ioda_pe *pe = container_of(table_group, struct pnv_ioda_pe,
2386 			table_group);
2387 	int nid = pe->phb->hose->node;
2388 	__u64 bus_offset = num ? pe->tce_bypass_base : table_group->tce32_start;
2389 	long ret;
2390 	struct iommu_table *tbl;
2391 
2392 	tbl = pnv_pci_table_alloc(nid);
2393 	if (!tbl)
2394 		return -ENOMEM;
2395 
2396 	tbl->it_ops = &pnv_ioda2_iommu_ops;
2397 
2398 	ret = pnv_pci_ioda2_table_alloc_pages(nid,
2399 			bus_offset, page_shift, window_size,
2400 			levels, alloc_userspace_copy, tbl);
2401 	if (ret) {
2402 		iommu_tce_table_put(tbl);
2403 		return ret;
2404 	}
2405 
2406 	*ptbl = tbl;
2407 
2408 	return 0;
2409 }
2410 
2411 static long pnv_pci_ioda2_setup_default_config(struct pnv_ioda_pe *pe)
2412 {
2413 	struct iommu_table *tbl = NULL;
2414 	long rc;
2415 	unsigned long res_start, res_end;
2416 
2417 	/*
2418 	 * crashkernel= specifies the kdump kernel's maximum memory at
2419 	 * some offset and there is no guaranteed the result is a power
2420 	 * of 2, which will cause errors later.
2421 	 */
2422 	const u64 max_memory = __rounddown_pow_of_two(memory_hotplug_max());
2423 
2424 	/*
2425 	 * In memory constrained environments, e.g. kdump kernel, the
2426 	 * DMA window can be larger than available memory, which will
2427 	 * cause errors later.
2428 	 */
2429 	const u64 maxblock = 1UL << (PAGE_SHIFT + MAX_ORDER - 1);
2430 
2431 	/*
2432 	 * We create the default window as big as we can. The constraint is
2433 	 * the max order of allocation possible. The TCE table is likely to
2434 	 * end up being multilevel and with on-demand allocation in place,
2435 	 * the initial use is not going to be huge as the default window aims
2436 	 * to support crippled devices (i.e. not fully 64bit DMAble) only.
2437 	 */
2438 	/* iommu_table::it_map uses 1 bit per IOMMU page, hence 8 */
2439 	const u64 window_size = min((maxblock * 8) << PAGE_SHIFT, max_memory);
2440 	/* Each TCE level cannot exceed maxblock so go multilevel if needed */
2441 	unsigned long tces_order = ilog2(window_size >> PAGE_SHIFT);
2442 	unsigned long tcelevel_order = ilog2(maxblock >> 3);
2443 	unsigned int levels = tces_order / tcelevel_order;
2444 
2445 	if (tces_order % tcelevel_order)
2446 		levels += 1;
2447 	/*
2448 	 * We try to stick to default levels (which is >1 at the moment) in
2449 	 * order to save memory by relying on on-demain TCE level allocation.
2450 	 */
2451 	levels = max_t(unsigned int, levels, POWERNV_IOMMU_DEFAULT_LEVELS);
2452 
2453 	rc = pnv_pci_ioda2_create_table(&pe->table_group, 0, PAGE_SHIFT,
2454 			window_size, levels, false, &tbl);
2455 	if (rc) {
2456 		pe_err(pe, "Failed to create 32-bit TCE table, err %ld",
2457 				rc);
2458 		return rc;
2459 	}
2460 
2461 	/* We use top part of 32bit space for MMIO so exclude it from DMA */
2462 	res_start = 0;
2463 	res_end = 0;
2464 	if (window_size > pe->phb->ioda.m32_pci_base) {
2465 		res_start = pe->phb->ioda.m32_pci_base >> tbl->it_page_shift;
2466 		res_end = min(window_size, SZ_4G) >> tbl->it_page_shift;
2467 	}
2468 	iommu_init_table(tbl, pe->phb->hose->node, res_start, res_end);
2469 
2470 	rc = pnv_pci_ioda2_set_window(&pe->table_group, 0, tbl);
2471 	if (rc) {
2472 		pe_err(pe, "Failed to configure 32-bit TCE table, err %ld\n",
2473 				rc);
2474 		iommu_tce_table_put(tbl);
2475 		return rc;
2476 	}
2477 
2478 	if (!pnv_iommu_bypass_disabled)
2479 		pnv_pci_ioda2_set_bypass(pe, true);
2480 
2481 	/*
2482 	 * Set table base for the case of IOMMU DMA use. Usually this is done
2483 	 * from dma_dev_setup() which is not called when a device is returned
2484 	 * from VFIO so do it here.
2485 	 */
2486 	if (pe->pdev)
2487 		set_iommu_table_base(&pe->pdev->dev, tbl);
2488 
2489 	return 0;
2490 }
2491 
2492 #if defined(CONFIG_IOMMU_API) || defined(CONFIG_PCI_IOV)
2493 static long pnv_pci_ioda2_unset_window(struct iommu_table_group *table_group,
2494 		int num)
2495 {
2496 	struct pnv_ioda_pe *pe = container_of(table_group, struct pnv_ioda_pe,
2497 			table_group);
2498 	struct pnv_phb *phb = pe->phb;
2499 	long ret;
2500 
2501 	pe_info(pe, "Removing DMA window #%d\n", num);
2502 
2503 	ret = opal_pci_map_pe_dma_window(phb->opal_id, pe->pe_number,
2504 			(pe->pe_number << 1) + num,
2505 			0/* levels */, 0/* table address */,
2506 			0/* table size */, 0/* page size */);
2507 	if (ret)
2508 		pe_warn(pe, "Unmapping failed, ret = %ld\n", ret);
2509 	else
2510 		pnv_pci_ioda2_tce_invalidate_pe(pe);
2511 
2512 	pnv_pci_unlink_table_and_group(table_group->tables[num], table_group);
2513 
2514 	return ret;
2515 }
2516 #endif
2517 
2518 #ifdef CONFIG_IOMMU_API
2519 unsigned long pnv_pci_ioda2_get_table_size(__u32 page_shift,
2520 		__u64 window_size, __u32 levels)
2521 {
2522 	unsigned long bytes = 0;
2523 	const unsigned window_shift = ilog2(window_size);
2524 	unsigned entries_shift = window_shift - page_shift;
2525 	unsigned table_shift = entries_shift + 3;
2526 	unsigned long tce_table_size = max(0x1000UL, 1UL << table_shift);
2527 	unsigned long direct_table_size;
2528 
2529 	if (!levels || (levels > POWERNV_IOMMU_MAX_LEVELS) ||
2530 			!is_power_of_2(window_size))
2531 		return 0;
2532 
2533 	/* Calculate a direct table size from window_size and levels */
2534 	entries_shift = (entries_shift + levels - 1) / levels;
2535 	table_shift = entries_shift + 3;
2536 	table_shift = max_t(unsigned, table_shift, PAGE_SHIFT);
2537 	direct_table_size =  1UL << table_shift;
2538 
2539 	for ( ; levels; --levels) {
2540 		bytes += _ALIGN_UP(tce_table_size, direct_table_size);
2541 
2542 		tce_table_size /= direct_table_size;
2543 		tce_table_size <<= 3;
2544 		tce_table_size = max_t(unsigned long,
2545 				tce_table_size, direct_table_size);
2546 	}
2547 
2548 	return bytes + bytes; /* one for HW table, one for userspace copy */
2549 }
2550 
2551 static long pnv_pci_ioda2_create_table_userspace(
2552 		struct iommu_table_group *table_group,
2553 		int num, __u32 page_shift, __u64 window_size, __u32 levels,
2554 		struct iommu_table **ptbl)
2555 {
2556 	long ret = pnv_pci_ioda2_create_table(table_group,
2557 			num, page_shift, window_size, levels, true, ptbl);
2558 
2559 	if (!ret)
2560 		(*ptbl)->it_allocated_size = pnv_pci_ioda2_get_table_size(
2561 				page_shift, window_size, levels);
2562 	return ret;
2563 }
2564 
2565 static void pnv_ioda2_take_ownership(struct iommu_table_group *table_group)
2566 {
2567 	struct pnv_ioda_pe *pe = container_of(table_group, struct pnv_ioda_pe,
2568 						table_group);
2569 	/* Store @tbl as pnv_pci_ioda2_unset_window() resets it */
2570 	struct iommu_table *tbl = pe->table_group.tables[0];
2571 
2572 	pnv_pci_ioda2_set_bypass(pe, false);
2573 	pnv_pci_ioda2_unset_window(&pe->table_group, 0);
2574 	if (pe->pbus)
2575 		pnv_ioda_setup_bus_dma(pe, pe->pbus);
2576 	else if (pe->pdev)
2577 		set_iommu_table_base(&pe->pdev->dev, NULL);
2578 	iommu_tce_table_put(tbl);
2579 }
2580 
2581 static void pnv_ioda2_release_ownership(struct iommu_table_group *table_group)
2582 {
2583 	struct pnv_ioda_pe *pe = container_of(table_group, struct pnv_ioda_pe,
2584 						table_group);
2585 
2586 	pnv_pci_ioda2_setup_default_config(pe);
2587 	if (pe->pbus)
2588 		pnv_ioda_setup_bus_dma(pe, pe->pbus);
2589 }
2590 
2591 static struct iommu_table_group_ops pnv_pci_ioda2_ops = {
2592 	.get_table_size = pnv_pci_ioda2_get_table_size,
2593 	.create_table = pnv_pci_ioda2_create_table_userspace,
2594 	.set_window = pnv_pci_ioda2_set_window,
2595 	.unset_window = pnv_pci_ioda2_unset_window,
2596 	.take_ownership = pnv_ioda2_take_ownership,
2597 	.release_ownership = pnv_ioda2_release_ownership,
2598 };
2599 
2600 static void pnv_ioda_setup_bus_iommu_group_add_devices(struct pnv_ioda_pe *pe,
2601 		struct iommu_table_group *table_group,
2602 		struct pci_bus *bus)
2603 {
2604 	struct pci_dev *dev;
2605 
2606 	list_for_each_entry(dev, &bus->devices, bus_list) {
2607 		iommu_add_device(table_group, &dev->dev);
2608 
2609 		if ((pe->flags & PNV_IODA_PE_BUS_ALL) && dev->subordinate)
2610 			pnv_ioda_setup_bus_iommu_group_add_devices(pe,
2611 					table_group, dev->subordinate);
2612 	}
2613 }
2614 
2615 static void pnv_ioda_setup_bus_iommu_group(struct pnv_ioda_pe *pe,
2616 		struct iommu_table_group *table_group, struct pci_bus *bus)
2617 {
2618 
2619 	if (pe->flags & PNV_IODA_PE_DEV)
2620 		iommu_add_device(table_group, &pe->pdev->dev);
2621 
2622 	if ((pe->flags & (PNV_IODA_PE_BUS | PNV_IODA_PE_BUS_ALL)) || bus)
2623 		pnv_ioda_setup_bus_iommu_group_add_devices(pe, table_group,
2624 				bus);
2625 }
2626 
2627 static unsigned long pnv_ioda_parse_tce_sizes(struct pnv_phb *phb);
2628 
2629 static void pnv_pci_ioda_setup_iommu_api(void)
2630 {
2631 	struct pci_controller *hose;
2632 	struct pnv_phb *phb;
2633 	struct pnv_ioda_pe *pe;
2634 
2635 	/*
2636 	 * There are 4 types of PEs:
2637 	 * - PNV_IODA_PE_BUS: a downstream port with an adapter,
2638 	 *   created from pnv_pci_setup_bridge();
2639 	 * - PNV_IODA_PE_BUS_ALL: a PCI-PCIX bridge with devices behind it,
2640 	 *   created from pnv_pci_setup_bridge();
2641 	 * - PNV_IODA_PE_VF: a SRIOV virtual function,
2642 	 *   created from pnv_pcibios_sriov_enable();
2643 	 * - PNV_IODA_PE_DEV: an NPU or OCAPI device,
2644 	 *   created from pnv_pci_ioda_fixup().
2645 	 *
2646 	 * Normally a PE is represented by an IOMMU group, however for
2647 	 * devices with side channels the groups need to be more strict.
2648 	 */
2649 	list_for_each_entry(hose, &hose_list, list_node) {
2650 		phb = hose->private_data;
2651 
2652 		if (phb->type == PNV_PHB_NPU_NVLINK ||
2653 		    phb->type == PNV_PHB_NPU_OCAPI)
2654 			continue;
2655 
2656 		list_for_each_entry(pe, &phb->ioda.pe_list, list) {
2657 			struct iommu_table_group *table_group;
2658 
2659 			table_group = pnv_try_setup_npu_table_group(pe);
2660 			if (!table_group) {
2661 				if (!pnv_pci_ioda_pe_dma_weight(pe))
2662 					continue;
2663 
2664 				table_group = &pe->table_group;
2665 				iommu_register_group(&pe->table_group,
2666 						pe->phb->hose->global_number,
2667 						pe->pe_number);
2668 			}
2669 			pnv_ioda_setup_bus_iommu_group(pe, table_group,
2670 					pe->pbus);
2671 		}
2672 	}
2673 
2674 	/*
2675 	 * Now we have all PHBs discovered, time to add NPU devices to
2676 	 * the corresponding IOMMU groups.
2677 	 */
2678 	list_for_each_entry(hose, &hose_list, list_node) {
2679 		unsigned long  pgsizes;
2680 
2681 		phb = hose->private_data;
2682 
2683 		if (phb->type != PNV_PHB_NPU_NVLINK)
2684 			continue;
2685 
2686 		pgsizes = pnv_ioda_parse_tce_sizes(phb);
2687 		list_for_each_entry(pe, &phb->ioda.pe_list, list) {
2688 			/*
2689 			 * IODA2 bridges get this set up from
2690 			 * pci_controller_ops::setup_bridge but NPU bridges
2691 			 * do not have this hook defined so we do it here.
2692 			 */
2693 			pe->table_group.pgsizes = pgsizes;
2694 			pnv_npu_compound_attach(pe);
2695 		}
2696 	}
2697 }
2698 #else /* !CONFIG_IOMMU_API */
2699 static void pnv_pci_ioda_setup_iommu_api(void) { };
2700 #endif
2701 
2702 static unsigned long pnv_ioda_parse_tce_sizes(struct pnv_phb *phb)
2703 {
2704 	struct pci_controller *hose = phb->hose;
2705 	struct device_node *dn = hose->dn;
2706 	unsigned long mask = 0;
2707 	int i, rc, count;
2708 	u32 val;
2709 
2710 	count = of_property_count_u32_elems(dn, "ibm,supported-tce-sizes");
2711 	if (count <= 0) {
2712 		mask = SZ_4K | SZ_64K;
2713 		/* Add 16M for POWER8 by default */
2714 		if (cpu_has_feature(CPU_FTR_ARCH_207S) &&
2715 				!cpu_has_feature(CPU_FTR_ARCH_300))
2716 			mask |= SZ_16M | SZ_256M;
2717 		return mask;
2718 	}
2719 
2720 	for (i = 0; i < count; i++) {
2721 		rc = of_property_read_u32_index(dn, "ibm,supported-tce-sizes",
2722 						i, &val);
2723 		if (rc == 0)
2724 			mask |= 1ULL << val;
2725 	}
2726 
2727 	return mask;
2728 }
2729 
2730 static void pnv_pci_ioda2_setup_dma_pe(struct pnv_phb *phb,
2731 				       struct pnv_ioda_pe *pe)
2732 {
2733 	int64_t rc;
2734 
2735 	if (!pnv_pci_ioda_pe_dma_weight(pe))
2736 		return;
2737 
2738 	/* TVE #1 is selected by PCI address bit 59 */
2739 	pe->tce_bypass_base = 1ull << 59;
2740 
2741 	/* The PE will reserve all possible 32-bits space */
2742 	pe_info(pe, "Setting up 32-bit TCE table at 0..%08x\n",
2743 		phb->ioda.m32_pci_base);
2744 
2745 	/* Setup linux iommu table */
2746 	pe->table_group.tce32_start = 0;
2747 	pe->table_group.tce32_size = phb->ioda.m32_pci_base;
2748 	pe->table_group.max_dynamic_windows_supported =
2749 			IOMMU_TABLE_GROUP_MAX_TABLES;
2750 	pe->table_group.max_levels = POWERNV_IOMMU_MAX_LEVELS;
2751 	pe->table_group.pgsizes = pnv_ioda_parse_tce_sizes(phb);
2752 #ifdef CONFIG_IOMMU_API
2753 	pe->table_group.ops = &pnv_pci_ioda2_ops;
2754 #endif
2755 
2756 	rc = pnv_pci_ioda2_setup_default_config(pe);
2757 	if (rc)
2758 		return;
2759 
2760 	if (pe->flags & (PNV_IODA_PE_BUS | PNV_IODA_PE_BUS_ALL))
2761 		pnv_ioda_setup_bus_dma(pe, pe->pbus);
2762 }
2763 
2764 int64_t pnv_opal_pci_msi_eoi(struct irq_chip *chip, unsigned int hw_irq)
2765 {
2766 	struct pnv_phb *phb = container_of(chip, struct pnv_phb,
2767 					   ioda.irq_chip);
2768 
2769 	return opal_pci_msi_eoi(phb->opal_id, hw_irq);
2770 }
2771 
2772 static void pnv_ioda2_msi_eoi(struct irq_data *d)
2773 {
2774 	int64_t rc;
2775 	unsigned int hw_irq = (unsigned int)irqd_to_hwirq(d);
2776 	struct irq_chip *chip = irq_data_get_irq_chip(d);
2777 
2778 	rc = pnv_opal_pci_msi_eoi(chip, hw_irq);
2779 	WARN_ON_ONCE(rc);
2780 
2781 	icp_native_eoi(d);
2782 }
2783 
2784 
2785 void pnv_set_msi_irq_chip(struct pnv_phb *phb, unsigned int virq)
2786 {
2787 	struct irq_data *idata;
2788 	struct irq_chip *ichip;
2789 
2790 	/* The MSI EOI OPAL call is only needed on PHB3 */
2791 	if (phb->model != PNV_PHB_MODEL_PHB3)
2792 		return;
2793 
2794 	if (!phb->ioda.irq_chip_init) {
2795 		/*
2796 		 * First time we setup an MSI IRQ, we need to setup the
2797 		 * corresponding IRQ chip to route correctly.
2798 		 */
2799 		idata = irq_get_irq_data(virq);
2800 		ichip = irq_data_get_irq_chip(idata);
2801 		phb->ioda.irq_chip_init = 1;
2802 		phb->ioda.irq_chip = *ichip;
2803 		phb->ioda.irq_chip.irq_eoi = pnv_ioda2_msi_eoi;
2804 	}
2805 	irq_set_chip(virq, &phb->ioda.irq_chip);
2806 }
2807 
2808 /*
2809  * Returns true iff chip is something that we could call
2810  * pnv_opal_pci_msi_eoi for.
2811  */
2812 bool is_pnv_opal_msi(struct irq_chip *chip)
2813 {
2814 	return chip->irq_eoi == pnv_ioda2_msi_eoi;
2815 }
2816 EXPORT_SYMBOL_GPL(is_pnv_opal_msi);
2817 
2818 static int pnv_pci_ioda_msi_setup(struct pnv_phb *phb, struct pci_dev *dev,
2819 				  unsigned int hwirq, unsigned int virq,
2820 				  unsigned int is_64, struct msi_msg *msg)
2821 {
2822 	struct pnv_ioda_pe *pe = pnv_ioda_get_pe(dev);
2823 	unsigned int xive_num = hwirq - phb->msi_base;
2824 	__be32 data;
2825 	int rc;
2826 
2827 	/* No PE assigned ? bail out ... no MSI for you ! */
2828 	if (pe == NULL)
2829 		return -ENXIO;
2830 
2831 	/* Check if we have an MVE */
2832 	if (pe->mve_number < 0)
2833 		return -ENXIO;
2834 
2835 	/* Force 32-bit MSI on some broken devices */
2836 	if (dev->no_64bit_msi)
2837 		is_64 = 0;
2838 
2839 	/* Assign XIVE to PE */
2840 	rc = opal_pci_set_xive_pe(phb->opal_id, pe->pe_number, xive_num);
2841 	if (rc) {
2842 		pr_warn("%s: OPAL error %d setting XIVE %d PE\n",
2843 			pci_name(dev), rc, xive_num);
2844 		return -EIO;
2845 	}
2846 
2847 	if (is_64) {
2848 		__be64 addr64;
2849 
2850 		rc = opal_get_msi_64(phb->opal_id, pe->mve_number, xive_num, 1,
2851 				     &addr64, &data);
2852 		if (rc) {
2853 			pr_warn("%s: OPAL error %d getting 64-bit MSI data\n",
2854 				pci_name(dev), rc);
2855 			return -EIO;
2856 		}
2857 		msg->address_hi = be64_to_cpu(addr64) >> 32;
2858 		msg->address_lo = be64_to_cpu(addr64) & 0xfffffffful;
2859 	} else {
2860 		__be32 addr32;
2861 
2862 		rc = opal_get_msi_32(phb->opal_id, pe->mve_number, xive_num, 1,
2863 				     &addr32, &data);
2864 		if (rc) {
2865 			pr_warn("%s: OPAL error %d getting 32-bit MSI data\n",
2866 				pci_name(dev), rc);
2867 			return -EIO;
2868 		}
2869 		msg->address_hi = 0;
2870 		msg->address_lo = be32_to_cpu(addr32);
2871 	}
2872 	msg->data = be32_to_cpu(data);
2873 
2874 	pnv_set_msi_irq_chip(phb, virq);
2875 
2876 	pr_devel("%s: %s-bit MSI on hwirq %x (xive #%d),"
2877 		 " address=%x_%08x data=%x PE# %x\n",
2878 		 pci_name(dev), is_64 ? "64" : "32", hwirq, xive_num,
2879 		 msg->address_hi, msg->address_lo, data, pe->pe_number);
2880 
2881 	return 0;
2882 }
2883 
2884 static void pnv_pci_init_ioda_msis(struct pnv_phb *phb)
2885 {
2886 	unsigned int count;
2887 	const __be32 *prop = of_get_property(phb->hose->dn,
2888 					     "ibm,opal-msi-ranges", NULL);
2889 	if (!prop) {
2890 		/* BML Fallback */
2891 		prop = of_get_property(phb->hose->dn, "msi-ranges", NULL);
2892 	}
2893 	if (!prop)
2894 		return;
2895 
2896 	phb->msi_base = be32_to_cpup(prop);
2897 	count = be32_to_cpup(prop + 1);
2898 	if (msi_bitmap_alloc(&phb->msi_bmp, count, phb->hose->dn)) {
2899 		pr_err("PCI %d: Failed to allocate MSI bitmap !\n",
2900 		       phb->hose->global_number);
2901 		return;
2902 	}
2903 
2904 	phb->msi_setup = pnv_pci_ioda_msi_setup;
2905 	phb->msi32_support = 1;
2906 	pr_info("  Allocated bitmap for %d MSIs (base IRQ 0x%x)\n",
2907 		count, phb->msi_base);
2908 }
2909 
2910 #ifdef CONFIG_PCI_IOV
2911 static void pnv_pci_ioda_fixup_iov_resources(struct pci_dev *pdev)
2912 {
2913 	struct pci_controller *hose = pci_bus_to_host(pdev->bus);
2914 	struct pnv_phb *phb = hose->private_data;
2915 	const resource_size_t gate = phb->ioda.m64_segsize >> 2;
2916 	struct resource *res;
2917 	int i;
2918 	resource_size_t size, total_vf_bar_sz;
2919 	struct pci_dn *pdn;
2920 	int mul, total_vfs;
2921 
2922 	pdn = pci_get_pdn(pdev);
2923 	pdn->vfs_expanded = 0;
2924 	pdn->m64_single_mode = false;
2925 
2926 	total_vfs = pci_sriov_get_totalvfs(pdev);
2927 	mul = phb->ioda.total_pe_num;
2928 	total_vf_bar_sz = 0;
2929 
2930 	for (i = 0; i < PCI_SRIOV_NUM_BARS; i++) {
2931 		res = &pdev->resource[i + PCI_IOV_RESOURCES];
2932 		if (!res->flags || res->parent)
2933 			continue;
2934 		if (!pnv_pci_is_m64_flags(res->flags)) {
2935 			dev_warn(&pdev->dev, "Don't support SR-IOV with"
2936 					" non M64 VF BAR%d: %pR. \n",
2937 				 i, res);
2938 			goto truncate_iov;
2939 		}
2940 
2941 		total_vf_bar_sz += pci_iov_resource_size(pdev,
2942 				i + PCI_IOV_RESOURCES);
2943 
2944 		/*
2945 		 * If bigger than quarter of M64 segment size, just round up
2946 		 * power of two.
2947 		 *
2948 		 * Generally, one M64 BAR maps one IOV BAR. To avoid conflict
2949 		 * with other devices, IOV BAR size is expanded to be
2950 		 * (total_pe * VF_BAR_size).  When VF_BAR_size is half of M64
2951 		 * segment size , the expanded size would equal to half of the
2952 		 * whole M64 space size, which will exhaust the M64 Space and
2953 		 * limit the system flexibility.  This is a design decision to
2954 		 * set the boundary to quarter of the M64 segment size.
2955 		 */
2956 		if (total_vf_bar_sz > gate) {
2957 			mul = roundup_pow_of_two(total_vfs);
2958 			dev_info(&pdev->dev,
2959 				"VF BAR Total IOV size %llx > %llx, roundup to %d VFs\n",
2960 				total_vf_bar_sz, gate, mul);
2961 			pdn->m64_single_mode = true;
2962 			break;
2963 		}
2964 	}
2965 
2966 	for (i = 0; i < PCI_SRIOV_NUM_BARS; i++) {
2967 		res = &pdev->resource[i + PCI_IOV_RESOURCES];
2968 		if (!res->flags || res->parent)
2969 			continue;
2970 
2971 		size = pci_iov_resource_size(pdev, i + PCI_IOV_RESOURCES);
2972 		/*
2973 		 * On PHB3, the minimum size alignment of M64 BAR in single
2974 		 * mode is 32MB.
2975 		 */
2976 		if (pdn->m64_single_mode && (size < SZ_32M))
2977 			goto truncate_iov;
2978 		dev_dbg(&pdev->dev, " Fixing VF BAR%d: %pR to\n", i, res);
2979 		res->end = res->start + size * mul - 1;
2980 		dev_dbg(&pdev->dev, "                       %pR\n", res);
2981 		dev_info(&pdev->dev, "VF BAR%d: %pR (expanded to %d VFs for PE alignment)",
2982 			 i, res, mul);
2983 	}
2984 	pdn->vfs_expanded = mul;
2985 
2986 	return;
2987 
2988 truncate_iov:
2989 	/* To save MMIO space, IOV BAR is truncated. */
2990 	for (i = 0; i < PCI_SRIOV_NUM_BARS; i++) {
2991 		res = &pdev->resource[i + PCI_IOV_RESOURCES];
2992 		res->flags = 0;
2993 		res->end = res->start - 1;
2994 	}
2995 }
2996 
2997 static void pnv_pci_ioda_fixup_iov(struct pci_dev *pdev)
2998 {
2999 	if (WARN_ON(pci_dev_is_added(pdev)))
3000 		return;
3001 
3002 	if (pdev->is_virtfn) {
3003 		struct pnv_ioda_pe *pe = pnv_ioda_get_pe(pdev);
3004 
3005 		/*
3006 		 * VF PEs are single-device PEs so their pdev pointer needs to
3007 		 * be set. The pdev doesn't exist when the PE is allocated (in
3008 		 * (pcibios_sriov_enable()) so we fix it up here.
3009 		 */
3010 		pe->pdev = pdev;
3011 		WARN_ON(!(pe->flags & PNV_IODA_PE_VF));
3012 	} else if (pdev->is_physfn) {
3013 		/*
3014 		 * For PFs adjust their allocated IOV resources to match what
3015 		 * the PHB can support using it's M64 BAR table.
3016 		 */
3017 		pnv_pci_ioda_fixup_iov_resources(pdev);
3018 	}
3019 }
3020 #endif /* CONFIG_PCI_IOV */
3021 
3022 static void pnv_ioda_setup_pe_res(struct pnv_ioda_pe *pe,
3023 				  struct resource *res)
3024 {
3025 	struct pnv_phb *phb = pe->phb;
3026 	struct pci_bus_region region;
3027 	int index;
3028 	int64_t rc;
3029 
3030 	if (!res || !res->flags || res->start > res->end)
3031 		return;
3032 
3033 	if (res->flags & IORESOURCE_IO) {
3034 		region.start = res->start - phb->ioda.io_pci_base;
3035 		region.end   = res->end - phb->ioda.io_pci_base;
3036 		index = region.start / phb->ioda.io_segsize;
3037 
3038 		while (index < phb->ioda.total_pe_num &&
3039 		       region.start <= region.end) {
3040 			phb->ioda.io_segmap[index] = pe->pe_number;
3041 			rc = opal_pci_map_pe_mmio_window(phb->opal_id,
3042 				pe->pe_number, OPAL_IO_WINDOW_TYPE, 0, index);
3043 			if (rc != OPAL_SUCCESS) {
3044 				pr_err("%s: Error %lld mapping IO segment#%d to PE#%x\n",
3045 				       __func__, rc, index, pe->pe_number);
3046 				break;
3047 			}
3048 
3049 			region.start += phb->ioda.io_segsize;
3050 			index++;
3051 		}
3052 	} else if ((res->flags & IORESOURCE_MEM) &&
3053 		   !pnv_pci_is_m64(phb, res)) {
3054 		region.start = res->start -
3055 			       phb->hose->mem_offset[0] -
3056 			       phb->ioda.m32_pci_base;
3057 		region.end   = res->end -
3058 			       phb->hose->mem_offset[0] -
3059 			       phb->ioda.m32_pci_base;
3060 		index = region.start / phb->ioda.m32_segsize;
3061 
3062 		while (index < phb->ioda.total_pe_num &&
3063 		       region.start <= region.end) {
3064 			phb->ioda.m32_segmap[index] = pe->pe_number;
3065 			rc = opal_pci_map_pe_mmio_window(phb->opal_id,
3066 				pe->pe_number, OPAL_M32_WINDOW_TYPE, 0, index);
3067 			if (rc != OPAL_SUCCESS) {
3068 				pr_err("%s: Error %lld mapping M32 segment#%d to PE#%x",
3069 				       __func__, rc, index, pe->pe_number);
3070 				break;
3071 			}
3072 
3073 			region.start += phb->ioda.m32_segsize;
3074 			index++;
3075 		}
3076 	}
3077 }
3078 
3079 /*
3080  * This function is supposed to be called on basis of PE from top
3081  * to bottom style. So the the I/O or MMIO segment assigned to
3082  * parent PE could be overridden by its child PEs if necessary.
3083  */
3084 static void pnv_ioda_setup_pe_seg(struct pnv_ioda_pe *pe)
3085 {
3086 	struct pci_dev *pdev;
3087 	int i;
3088 
3089 	/*
3090 	 * NOTE: We only care PCI bus based PE for now. For PCI
3091 	 * device based PE, for example SRIOV sensitive VF should
3092 	 * be figured out later.
3093 	 */
3094 	BUG_ON(!(pe->flags & (PNV_IODA_PE_BUS | PNV_IODA_PE_BUS_ALL)));
3095 
3096 	list_for_each_entry(pdev, &pe->pbus->devices, bus_list) {
3097 		for (i = 0; i <= PCI_ROM_RESOURCE; i++)
3098 			pnv_ioda_setup_pe_res(pe, &pdev->resource[i]);
3099 
3100 		/*
3101 		 * If the PE contains all subordinate PCI buses, the
3102 		 * windows of the child bridges should be mapped to
3103 		 * the PE as well.
3104 		 */
3105 		if (!(pe->flags & PNV_IODA_PE_BUS_ALL) || !pci_is_bridge(pdev))
3106 			continue;
3107 		for (i = 0; i < PCI_BRIDGE_RESOURCE_NUM; i++)
3108 			pnv_ioda_setup_pe_res(pe,
3109 				&pdev->resource[PCI_BRIDGE_RESOURCES + i]);
3110 	}
3111 }
3112 
3113 #ifdef CONFIG_DEBUG_FS
3114 static int pnv_pci_diag_data_set(void *data, u64 val)
3115 {
3116 	struct pnv_phb *phb = data;
3117 	s64 ret;
3118 
3119 	/* Retrieve the diag data from firmware */
3120 	ret = opal_pci_get_phb_diag_data2(phb->opal_id, phb->diag_data,
3121 					  phb->diag_data_size);
3122 	if (ret != OPAL_SUCCESS)
3123 		return -EIO;
3124 
3125 	/* Print the diag data to the kernel log */
3126 	pnv_pci_dump_phb_diag_data(phb->hose, phb->diag_data);
3127 	return 0;
3128 }
3129 
3130 DEFINE_DEBUGFS_ATTRIBUTE(pnv_pci_diag_data_fops, NULL, pnv_pci_diag_data_set,
3131 			 "%llu\n");
3132 
3133 static int pnv_pci_ioda_pe_dump(void *data, u64 val)
3134 {
3135 	struct pnv_phb *phb = data;
3136 	int pe_num;
3137 
3138 	for (pe_num = 0; pe_num < phb->ioda.total_pe_num; pe_num++) {
3139 		struct pnv_ioda_pe *pe = &phb->ioda.pe_array[pe_num];
3140 
3141 		if (!test_bit(pe_num, phb->ioda.pe_alloc))
3142 			continue;
3143 
3144 		pe_warn(pe, "rid: %04x dev count: %2d flags: %s%s%s%s%s%s\n",
3145 			pe->rid, pe->device_count,
3146 			(pe->flags & PNV_IODA_PE_DEV) ? "dev " : "",
3147 			(pe->flags & PNV_IODA_PE_BUS) ? "bus " : "",
3148 			(pe->flags & PNV_IODA_PE_BUS_ALL) ? "all " : "",
3149 			(pe->flags & PNV_IODA_PE_MASTER) ? "master " : "",
3150 			(pe->flags & PNV_IODA_PE_SLAVE) ? "slave " : "",
3151 			(pe->flags & PNV_IODA_PE_VF) ? "vf " : "");
3152 	}
3153 
3154 	return 0;
3155 }
3156 
3157 DEFINE_DEBUGFS_ATTRIBUTE(pnv_pci_ioda_pe_dump_fops, NULL,
3158 			 pnv_pci_ioda_pe_dump, "%llu\n");
3159 
3160 #endif /* CONFIG_DEBUG_FS */
3161 
3162 static void pnv_pci_ioda_create_dbgfs(void)
3163 {
3164 #ifdef CONFIG_DEBUG_FS
3165 	struct pci_controller *hose, *tmp;
3166 	struct pnv_phb *phb;
3167 	char name[16];
3168 
3169 	list_for_each_entry_safe(hose, tmp, &hose_list, list_node) {
3170 		phb = hose->private_data;
3171 
3172 		/* Notify initialization of PHB done */
3173 		phb->initialized = 1;
3174 
3175 		sprintf(name, "PCI%04x", hose->global_number);
3176 		phb->dbgfs = debugfs_create_dir(name, powerpc_debugfs_root);
3177 
3178 		debugfs_create_file_unsafe("dump_diag_regs", 0200, phb->dbgfs,
3179 					   phb, &pnv_pci_diag_data_fops);
3180 		debugfs_create_file_unsafe("dump_ioda_pe_state", 0200, phb->dbgfs,
3181 					   phb, &pnv_pci_ioda_pe_dump_fops);
3182 	}
3183 #endif /* CONFIG_DEBUG_FS */
3184 }
3185 
3186 static void pnv_pci_enable_bridge(struct pci_bus *bus)
3187 {
3188 	struct pci_dev *dev = bus->self;
3189 	struct pci_bus *child;
3190 
3191 	/* Empty bus ? bail */
3192 	if (list_empty(&bus->devices))
3193 		return;
3194 
3195 	/*
3196 	 * If there's a bridge associated with that bus enable it. This works
3197 	 * around races in the generic code if the enabling is done during
3198 	 * parallel probing. This can be removed once those races have been
3199 	 * fixed.
3200 	 */
3201 	if (dev) {
3202 		int rc = pci_enable_device(dev);
3203 		if (rc)
3204 			pci_err(dev, "Error enabling bridge (%d)\n", rc);
3205 		pci_set_master(dev);
3206 	}
3207 
3208 	/* Perform the same to child busses */
3209 	list_for_each_entry(child, &bus->children, node)
3210 		pnv_pci_enable_bridge(child);
3211 }
3212 
3213 static void pnv_pci_enable_bridges(void)
3214 {
3215 	struct pci_controller *hose;
3216 
3217 	list_for_each_entry(hose, &hose_list, list_node)
3218 		pnv_pci_enable_bridge(hose->bus);
3219 }
3220 
3221 static void pnv_pci_ioda_fixup(void)
3222 {
3223 	pnv_pci_ioda_setup_PEs();
3224 	pnv_pci_ioda_setup_iommu_api();
3225 	pnv_pci_ioda_create_dbgfs();
3226 
3227 	pnv_pci_enable_bridges();
3228 
3229 #ifdef CONFIG_EEH
3230 	pnv_eeh_post_init();
3231 #endif
3232 }
3233 
3234 /*
3235  * Returns the alignment for I/O or memory windows for P2P
3236  * bridges. That actually depends on how PEs are segmented.
3237  * For now, we return I/O or M32 segment size for PE sensitive
3238  * P2P bridges. Otherwise, the default values (4KiB for I/O,
3239  * 1MiB for memory) will be returned.
3240  *
3241  * The current PCI bus might be put into one PE, which was
3242  * create against the parent PCI bridge. For that case, we
3243  * needn't enlarge the alignment so that we can save some
3244  * resources.
3245  */
3246 static resource_size_t pnv_pci_window_alignment(struct pci_bus *bus,
3247 						unsigned long type)
3248 {
3249 	struct pci_dev *bridge;
3250 	struct pci_controller *hose = pci_bus_to_host(bus);
3251 	struct pnv_phb *phb = hose->private_data;
3252 	int num_pci_bridges = 0;
3253 
3254 	bridge = bus->self;
3255 	while (bridge) {
3256 		if (pci_pcie_type(bridge) == PCI_EXP_TYPE_PCI_BRIDGE) {
3257 			num_pci_bridges++;
3258 			if (num_pci_bridges >= 2)
3259 				return 1;
3260 		}
3261 
3262 		bridge = bridge->bus->self;
3263 	}
3264 
3265 	/*
3266 	 * We fall back to M32 if M64 isn't supported. We enforce the M64
3267 	 * alignment for any 64-bit resource, PCIe doesn't care and
3268 	 * bridges only do 64-bit prefetchable anyway.
3269 	 */
3270 	if (phb->ioda.m64_segsize && pnv_pci_is_m64_flags(type))
3271 		return phb->ioda.m64_segsize;
3272 	if (type & IORESOURCE_MEM)
3273 		return phb->ioda.m32_segsize;
3274 
3275 	return phb->ioda.io_segsize;
3276 }
3277 
3278 /*
3279  * We are updating root port or the upstream port of the
3280  * bridge behind the root port with PHB's windows in order
3281  * to accommodate the changes on required resources during
3282  * PCI (slot) hotplug, which is connected to either root
3283  * port or the downstream ports of PCIe switch behind the
3284  * root port.
3285  */
3286 static void pnv_pci_fixup_bridge_resources(struct pci_bus *bus,
3287 					   unsigned long type)
3288 {
3289 	struct pci_controller *hose = pci_bus_to_host(bus);
3290 	struct pnv_phb *phb = hose->private_data;
3291 	struct pci_dev *bridge = bus->self;
3292 	struct resource *r, *w;
3293 	bool msi_region = false;
3294 	int i;
3295 
3296 	/* Check if we need apply fixup to the bridge's windows */
3297 	if (!pci_is_root_bus(bridge->bus) &&
3298 	    !pci_is_root_bus(bridge->bus->self->bus))
3299 		return;
3300 
3301 	/* Fixup the resources */
3302 	for (i = 0; i < PCI_BRIDGE_RESOURCE_NUM; i++) {
3303 		r = &bridge->resource[PCI_BRIDGE_RESOURCES + i];
3304 		if (!r->flags || !r->parent)
3305 			continue;
3306 
3307 		w = NULL;
3308 		if (r->flags & type & IORESOURCE_IO)
3309 			w = &hose->io_resource;
3310 		else if (pnv_pci_is_m64(phb, r) &&
3311 			 (type & IORESOURCE_PREFETCH) &&
3312 			 phb->ioda.m64_segsize)
3313 			w = &hose->mem_resources[1];
3314 		else if (r->flags & type & IORESOURCE_MEM) {
3315 			w = &hose->mem_resources[0];
3316 			msi_region = true;
3317 		}
3318 
3319 		r->start = w->start;
3320 		r->end = w->end;
3321 
3322 		/* The 64KB 32-bits MSI region shouldn't be included in
3323 		 * the 32-bits bridge window. Otherwise, we can see strange
3324 		 * issues. One of them is EEH error observed on Garrison.
3325 		 *
3326 		 * Exclude top 1MB region which is the minimal alignment of
3327 		 * 32-bits bridge window.
3328 		 */
3329 		if (msi_region) {
3330 			r->end += 0x10000;
3331 			r->end -= 0x100000;
3332 		}
3333 	}
3334 }
3335 
3336 static void pnv_pci_setup_bridge(struct pci_bus *bus, unsigned long type)
3337 {
3338 	struct pci_controller *hose = pci_bus_to_host(bus);
3339 	struct pnv_phb *phb = hose->private_data;
3340 	struct pci_dev *bridge = bus->self;
3341 	struct pnv_ioda_pe *pe;
3342 	bool all = (pci_pcie_type(bridge) == PCI_EXP_TYPE_PCI_BRIDGE);
3343 
3344 	/* Extend bridge's windows if necessary */
3345 	pnv_pci_fixup_bridge_resources(bus, type);
3346 
3347 	/* The PE for root bus should be realized before any one else */
3348 	if (!phb->ioda.root_pe_populated) {
3349 		pe = pnv_ioda_setup_bus_PE(phb->hose->bus, false);
3350 		if (pe) {
3351 			phb->ioda.root_pe_idx = pe->pe_number;
3352 			phb->ioda.root_pe_populated = true;
3353 		}
3354 	}
3355 
3356 	/* Don't assign PE to PCI bus, which doesn't have subordinate devices */
3357 	if (list_empty(&bus->devices))
3358 		return;
3359 
3360 	/* Reserve PEs according to used M64 resources */
3361 	pnv_ioda_reserve_m64_pe(bus, NULL, all);
3362 
3363 	/*
3364 	 * Assign PE. We might run here because of partial hotplug.
3365 	 * For the case, we just pick up the existing PE and should
3366 	 * not allocate resources again.
3367 	 */
3368 	pe = pnv_ioda_setup_bus_PE(bus, all);
3369 	if (!pe)
3370 		return;
3371 
3372 	pnv_ioda_setup_pe_seg(pe);
3373 	switch (phb->type) {
3374 	case PNV_PHB_IODA1:
3375 		pnv_pci_ioda1_setup_dma_pe(phb, pe);
3376 		break;
3377 	case PNV_PHB_IODA2:
3378 		pnv_pci_ioda2_setup_dma_pe(phb, pe);
3379 		break;
3380 	default:
3381 		pr_warn("%s: No DMA for PHB#%x (type %d)\n",
3382 			__func__, phb->hose->global_number, phb->type);
3383 	}
3384 }
3385 
3386 static resource_size_t pnv_pci_default_alignment(void)
3387 {
3388 	return PAGE_SIZE;
3389 }
3390 
3391 #ifdef CONFIG_PCI_IOV
3392 static resource_size_t pnv_pci_iov_resource_alignment(struct pci_dev *pdev,
3393 						      int resno)
3394 {
3395 	struct pci_controller *hose = pci_bus_to_host(pdev->bus);
3396 	struct pnv_phb *phb = hose->private_data;
3397 	struct pci_dn *pdn = pci_get_pdn(pdev);
3398 	resource_size_t align;
3399 
3400 	/*
3401 	 * On PowerNV platform, IOV BAR is mapped by M64 BAR to enable the
3402 	 * SR-IOV. While from hardware perspective, the range mapped by M64
3403 	 * BAR should be size aligned.
3404 	 *
3405 	 * When IOV BAR is mapped with M64 BAR in Single PE mode, the extra
3406 	 * powernv-specific hardware restriction is gone. But if just use the
3407 	 * VF BAR size as the alignment, PF BAR / VF BAR may be allocated with
3408 	 * in one segment of M64 #15, which introduces the PE conflict between
3409 	 * PF and VF. Based on this, the minimum alignment of an IOV BAR is
3410 	 * m64_segsize.
3411 	 *
3412 	 * This function returns the total IOV BAR size if M64 BAR is in
3413 	 * Shared PE mode or just VF BAR size if not.
3414 	 * If the M64 BAR is in Single PE mode, return the VF BAR size or
3415 	 * M64 segment size if IOV BAR size is less.
3416 	 */
3417 	align = pci_iov_resource_size(pdev, resno);
3418 	if (!pdn->vfs_expanded)
3419 		return align;
3420 	if (pdn->m64_single_mode)
3421 		return max(align, (resource_size_t)phb->ioda.m64_segsize);
3422 
3423 	return pdn->vfs_expanded * align;
3424 }
3425 #endif /* CONFIG_PCI_IOV */
3426 
3427 /* Prevent enabling devices for which we couldn't properly
3428  * assign a PE
3429  */
3430 static bool pnv_pci_enable_device_hook(struct pci_dev *dev)
3431 {
3432 	struct pci_controller *hose = pci_bus_to_host(dev->bus);
3433 	struct pnv_phb *phb = hose->private_data;
3434 	struct pci_dn *pdn;
3435 
3436 	/* The function is probably called while the PEs have
3437 	 * not be created yet. For example, resource reassignment
3438 	 * during PCI probe period. We just skip the check if
3439 	 * PEs isn't ready.
3440 	 */
3441 	if (!phb->initialized)
3442 		return true;
3443 
3444 	pdn = pci_get_pdn(dev);
3445 	if (!pdn || pdn->pe_number == IODA_INVALID_PE)
3446 		return false;
3447 
3448 	return true;
3449 }
3450 
3451 static bool pnv_ocapi_enable_device_hook(struct pci_dev *dev)
3452 {
3453 	struct pci_controller *hose = pci_bus_to_host(dev->bus);
3454 	struct pnv_phb *phb = hose->private_data;
3455 	struct pci_dn *pdn;
3456 	struct pnv_ioda_pe *pe;
3457 
3458 	if (!phb->initialized)
3459 		return true;
3460 
3461 	pdn = pci_get_pdn(dev);
3462 	if (!pdn)
3463 		return false;
3464 
3465 	if (pdn->pe_number == IODA_INVALID_PE) {
3466 		pe = pnv_ioda_setup_dev_PE(dev);
3467 		if (!pe)
3468 			return false;
3469 	}
3470 	return true;
3471 }
3472 
3473 static long pnv_pci_ioda1_unset_window(struct iommu_table_group *table_group,
3474 				       int num)
3475 {
3476 	struct pnv_ioda_pe *pe = container_of(table_group,
3477 					      struct pnv_ioda_pe, table_group);
3478 	struct pnv_phb *phb = pe->phb;
3479 	unsigned int idx;
3480 	long rc;
3481 
3482 	pe_info(pe, "Removing DMA window #%d\n", num);
3483 	for (idx = 0; idx < phb->ioda.dma32_count; idx++) {
3484 		if (phb->ioda.dma32_segmap[idx] != pe->pe_number)
3485 			continue;
3486 
3487 		rc = opal_pci_map_pe_dma_window(phb->opal_id, pe->pe_number,
3488 						idx, 0, 0ul, 0ul, 0ul);
3489 		if (rc != OPAL_SUCCESS) {
3490 			pe_warn(pe, "Failure %ld unmapping DMA32 segment#%d\n",
3491 				rc, idx);
3492 			return rc;
3493 		}
3494 
3495 		phb->ioda.dma32_segmap[idx] = IODA_INVALID_PE;
3496 	}
3497 
3498 	pnv_pci_unlink_table_and_group(table_group->tables[num], table_group);
3499 	return OPAL_SUCCESS;
3500 }
3501 
3502 static void pnv_pci_ioda1_release_pe_dma(struct pnv_ioda_pe *pe)
3503 {
3504 	unsigned int weight = pnv_pci_ioda_pe_dma_weight(pe);
3505 	struct iommu_table *tbl = pe->table_group.tables[0];
3506 	int64_t rc;
3507 
3508 	if (!weight)
3509 		return;
3510 
3511 	rc = pnv_pci_ioda1_unset_window(&pe->table_group, 0);
3512 	if (rc != OPAL_SUCCESS)
3513 		return;
3514 
3515 	pnv_pci_p7ioc_tce_invalidate(tbl, tbl->it_offset, tbl->it_size, false);
3516 	if (pe->table_group.group) {
3517 		iommu_group_put(pe->table_group.group);
3518 		WARN_ON(pe->table_group.group);
3519 	}
3520 
3521 	free_pages(tbl->it_base, get_order(tbl->it_size << 3));
3522 	iommu_tce_table_put(tbl);
3523 }
3524 
3525 static void pnv_pci_ioda2_release_pe_dma(struct pnv_ioda_pe *pe)
3526 {
3527 	struct iommu_table *tbl = pe->table_group.tables[0];
3528 	unsigned int weight = pnv_pci_ioda_pe_dma_weight(pe);
3529 #ifdef CONFIG_IOMMU_API
3530 	int64_t rc;
3531 #endif
3532 
3533 	if (!weight)
3534 		return;
3535 
3536 #ifdef CONFIG_IOMMU_API
3537 	rc = pnv_pci_ioda2_unset_window(&pe->table_group, 0);
3538 	if (rc)
3539 		pe_warn(pe, "OPAL error %lld release DMA window\n", rc);
3540 #endif
3541 
3542 	pnv_pci_ioda2_set_bypass(pe, false);
3543 	if (pe->table_group.group) {
3544 		iommu_group_put(pe->table_group.group);
3545 		WARN_ON(pe->table_group.group);
3546 	}
3547 
3548 	iommu_tce_table_put(tbl);
3549 }
3550 
3551 static void pnv_ioda_free_pe_seg(struct pnv_ioda_pe *pe,
3552 				 unsigned short win,
3553 				 unsigned int *map)
3554 {
3555 	struct pnv_phb *phb = pe->phb;
3556 	int idx;
3557 	int64_t rc;
3558 
3559 	for (idx = 0; idx < phb->ioda.total_pe_num; idx++) {
3560 		if (map[idx] != pe->pe_number)
3561 			continue;
3562 
3563 		if (win == OPAL_M64_WINDOW_TYPE)
3564 			rc = opal_pci_map_pe_mmio_window(phb->opal_id,
3565 					phb->ioda.reserved_pe_idx, win,
3566 					idx / PNV_IODA1_M64_SEGS,
3567 					idx % PNV_IODA1_M64_SEGS);
3568 		else
3569 			rc = opal_pci_map_pe_mmio_window(phb->opal_id,
3570 					phb->ioda.reserved_pe_idx, win, 0, idx);
3571 
3572 		if (rc != OPAL_SUCCESS)
3573 			pe_warn(pe, "Error %lld unmapping (%d) segment#%d\n",
3574 				rc, win, idx);
3575 
3576 		map[idx] = IODA_INVALID_PE;
3577 	}
3578 }
3579 
3580 static void pnv_ioda_release_pe_seg(struct pnv_ioda_pe *pe)
3581 {
3582 	struct pnv_phb *phb = pe->phb;
3583 
3584 	if (phb->type == PNV_PHB_IODA1) {
3585 		pnv_ioda_free_pe_seg(pe, OPAL_IO_WINDOW_TYPE,
3586 				     phb->ioda.io_segmap);
3587 		pnv_ioda_free_pe_seg(pe, OPAL_M32_WINDOW_TYPE,
3588 				     phb->ioda.m32_segmap);
3589 		pnv_ioda_free_pe_seg(pe, OPAL_M64_WINDOW_TYPE,
3590 				     phb->ioda.m64_segmap);
3591 	} else if (phb->type == PNV_PHB_IODA2) {
3592 		pnv_ioda_free_pe_seg(pe, OPAL_M32_WINDOW_TYPE,
3593 				     phb->ioda.m32_segmap);
3594 	}
3595 }
3596 
3597 static void pnv_ioda_release_pe(struct pnv_ioda_pe *pe)
3598 {
3599 	struct pnv_phb *phb = pe->phb;
3600 	struct pnv_ioda_pe *slave, *tmp;
3601 
3602 	mutex_lock(&phb->ioda.pe_list_mutex);
3603 	list_del(&pe->list);
3604 	mutex_unlock(&phb->ioda.pe_list_mutex);
3605 
3606 	switch (phb->type) {
3607 	case PNV_PHB_IODA1:
3608 		pnv_pci_ioda1_release_pe_dma(pe);
3609 		break;
3610 	case PNV_PHB_IODA2:
3611 		pnv_pci_ioda2_release_pe_dma(pe);
3612 		break;
3613 	case PNV_PHB_NPU_OCAPI:
3614 		break;
3615 	default:
3616 		WARN_ON(1);
3617 	}
3618 
3619 	pnv_ioda_release_pe_seg(pe);
3620 	pnv_ioda_deconfigure_pe(pe->phb, pe);
3621 
3622 	/* Release slave PEs in the compound PE */
3623 	if (pe->flags & PNV_IODA_PE_MASTER) {
3624 		list_for_each_entry_safe(slave, tmp, &pe->slaves, list) {
3625 			list_del(&slave->list);
3626 			pnv_ioda_free_pe(slave);
3627 		}
3628 	}
3629 
3630 	/*
3631 	 * The PE for root bus can be removed because of hotplug in EEH
3632 	 * recovery for fenced PHB error. We need to mark the PE dead so
3633 	 * that it can be populated again in PCI hot add path. The PE
3634 	 * shouldn't be destroyed as it's the global reserved resource.
3635 	 */
3636 	if (phb->ioda.root_pe_populated &&
3637 	    phb->ioda.root_pe_idx == pe->pe_number)
3638 		phb->ioda.root_pe_populated = false;
3639 	else
3640 		pnv_ioda_free_pe(pe);
3641 }
3642 
3643 static void pnv_pci_release_device(struct pci_dev *pdev)
3644 {
3645 	struct pci_controller *hose = pci_bus_to_host(pdev->bus);
3646 	struct pnv_phb *phb = hose->private_data;
3647 	struct pci_dn *pdn = pci_get_pdn(pdev);
3648 	struct pnv_ioda_pe *pe;
3649 
3650 	if (pdev->is_virtfn)
3651 		return;
3652 
3653 	if (!pdn || pdn->pe_number == IODA_INVALID_PE)
3654 		return;
3655 
3656 	/*
3657 	 * PCI hotplug can happen as part of EEH error recovery. The @pdn
3658 	 * isn't removed and added afterwards in this scenario. We should
3659 	 * set the PE number in @pdn to an invalid one. Otherwise, the PE's
3660 	 * device count is decreased on removing devices while failing to
3661 	 * be increased on adding devices. It leads to unbalanced PE's device
3662 	 * count and eventually make normal PCI hotplug path broken.
3663 	 */
3664 	pe = &phb->ioda.pe_array[pdn->pe_number];
3665 	pdn->pe_number = IODA_INVALID_PE;
3666 
3667 	WARN_ON(--pe->device_count < 0);
3668 	if (pe->device_count == 0)
3669 		pnv_ioda_release_pe(pe);
3670 }
3671 
3672 static void pnv_npu_disable_device(struct pci_dev *pdev)
3673 {
3674 	struct eeh_dev *edev = pci_dev_to_eeh_dev(pdev);
3675 	struct eeh_pe *eehpe = edev ? edev->pe : NULL;
3676 
3677 	if (eehpe && eeh_ops && eeh_ops->reset)
3678 		eeh_ops->reset(eehpe, EEH_RESET_HOT);
3679 }
3680 
3681 static void pnv_pci_ioda_shutdown(struct pci_controller *hose)
3682 {
3683 	struct pnv_phb *phb = hose->private_data;
3684 
3685 	opal_pci_reset(phb->opal_id, OPAL_RESET_PCI_IODA_TABLE,
3686 		       OPAL_ASSERT_RESET);
3687 }
3688 
3689 static void pnv_pci_ioda_dma_bus_setup(struct pci_bus *bus)
3690 {
3691 	struct pci_controller *hose = bus->sysdata;
3692 	struct pnv_phb *phb = hose->private_data;
3693 	struct pnv_ioda_pe *pe;
3694 
3695 	list_for_each_entry(pe, &phb->ioda.pe_list, list) {
3696 		if (!(pe->flags & (PNV_IODA_PE_BUS | PNV_IODA_PE_BUS_ALL)))
3697 			continue;
3698 
3699 		if (!pe->pbus)
3700 			continue;
3701 
3702 		if (bus->number == ((pe->rid >> 8) & 0xFF)) {
3703 			pe->pbus = bus;
3704 			break;
3705 		}
3706 	}
3707 }
3708 
3709 static const struct pci_controller_ops pnv_pci_ioda_controller_ops = {
3710 	.dma_dev_setup		= pnv_pci_ioda_dma_dev_setup,
3711 	.dma_bus_setup		= pnv_pci_ioda_dma_bus_setup,
3712 	.iommu_bypass_supported	= pnv_pci_ioda_iommu_bypass_supported,
3713 	.setup_msi_irqs		= pnv_setup_msi_irqs,
3714 	.teardown_msi_irqs	= pnv_teardown_msi_irqs,
3715 	.enable_device_hook	= pnv_pci_enable_device_hook,
3716 	.release_device		= pnv_pci_release_device,
3717 	.window_alignment	= pnv_pci_window_alignment,
3718 	.setup_bridge		= pnv_pci_setup_bridge,
3719 	.reset_secondary_bus	= pnv_pci_reset_secondary_bus,
3720 	.shutdown		= pnv_pci_ioda_shutdown,
3721 };
3722 
3723 static const struct pci_controller_ops pnv_npu_ioda_controller_ops = {
3724 	.setup_msi_irqs		= pnv_setup_msi_irqs,
3725 	.teardown_msi_irqs	= pnv_teardown_msi_irqs,
3726 	.enable_device_hook	= pnv_pci_enable_device_hook,
3727 	.window_alignment	= pnv_pci_window_alignment,
3728 	.reset_secondary_bus	= pnv_pci_reset_secondary_bus,
3729 	.shutdown		= pnv_pci_ioda_shutdown,
3730 	.disable_device		= pnv_npu_disable_device,
3731 };
3732 
3733 static const struct pci_controller_ops pnv_npu_ocapi_ioda_controller_ops = {
3734 	.enable_device_hook	= pnv_ocapi_enable_device_hook,
3735 	.release_device		= pnv_pci_release_device,
3736 	.window_alignment	= pnv_pci_window_alignment,
3737 	.reset_secondary_bus	= pnv_pci_reset_secondary_bus,
3738 	.shutdown		= pnv_pci_ioda_shutdown,
3739 };
3740 
3741 static void __init pnv_pci_init_ioda_phb(struct device_node *np,
3742 					 u64 hub_id, int ioda_type)
3743 {
3744 	struct pci_controller *hose;
3745 	struct pnv_phb *phb;
3746 	unsigned long size, m64map_off, m32map_off, pemap_off;
3747 	unsigned long iomap_off = 0, dma32map_off = 0;
3748 	struct resource r;
3749 	const __be64 *prop64;
3750 	const __be32 *prop32;
3751 	int len;
3752 	unsigned int segno;
3753 	u64 phb_id;
3754 	void *aux;
3755 	long rc;
3756 
3757 	if (!of_device_is_available(np))
3758 		return;
3759 
3760 	pr_info("Initializing %s PHB (%pOF)\n",	pnv_phb_names[ioda_type], np);
3761 
3762 	prop64 = of_get_property(np, "ibm,opal-phbid", NULL);
3763 	if (!prop64) {
3764 		pr_err("  Missing \"ibm,opal-phbid\" property !\n");
3765 		return;
3766 	}
3767 	phb_id = be64_to_cpup(prop64);
3768 	pr_debug("  PHB-ID  : 0x%016llx\n", phb_id);
3769 
3770 	phb = memblock_alloc(sizeof(*phb), SMP_CACHE_BYTES);
3771 	if (!phb)
3772 		panic("%s: Failed to allocate %zu bytes\n", __func__,
3773 		      sizeof(*phb));
3774 
3775 	/* Allocate PCI controller */
3776 	phb->hose = hose = pcibios_alloc_controller(np);
3777 	if (!phb->hose) {
3778 		pr_err("  Can't allocate PCI controller for %pOF\n",
3779 		       np);
3780 		memblock_free(__pa(phb), sizeof(struct pnv_phb));
3781 		return;
3782 	}
3783 
3784 	spin_lock_init(&phb->lock);
3785 	prop32 = of_get_property(np, "bus-range", &len);
3786 	if (prop32 && len == 8) {
3787 		hose->first_busno = be32_to_cpu(prop32[0]);
3788 		hose->last_busno = be32_to_cpu(prop32[1]);
3789 	} else {
3790 		pr_warn("  Broken <bus-range> on %pOF\n", np);
3791 		hose->first_busno = 0;
3792 		hose->last_busno = 0xff;
3793 	}
3794 	hose->private_data = phb;
3795 	phb->hub_id = hub_id;
3796 	phb->opal_id = phb_id;
3797 	phb->type = ioda_type;
3798 	mutex_init(&phb->ioda.pe_alloc_mutex);
3799 
3800 	/* Detect specific models for error handling */
3801 	if (of_device_is_compatible(np, "ibm,p7ioc-pciex"))
3802 		phb->model = PNV_PHB_MODEL_P7IOC;
3803 	else if (of_device_is_compatible(np, "ibm,power8-pciex"))
3804 		phb->model = PNV_PHB_MODEL_PHB3;
3805 	else if (of_device_is_compatible(np, "ibm,power8-npu-pciex"))
3806 		phb->model = PNV_PHB_MODEL_NPU;
3807 	else if (of_device_is_compatible(np, "ibm,power9-npu-pciex"))
3808 		phb->model = PNV_PHB_MODEL_NPU2;
3809 	else
3810 		phb->model = PNV_PHB_MODEL_UNKNOWN;
3811 
3812 	/* Initialize diagnostic data buffer */
3813 	prop32 = of_get_property(np, "ibm,phb-diag-data-size", NULL);
3814 	if (prop32)
3815 		phb->diag_data_size = be32_to_cpup(prop32);
3816 	else
3817 		phb->diag_data_size = PNV_PCI_DIAG_BUF_SIZE;
3818 
3819 	phb->diag_data = memblock_alloc(phb->diag_data_size, SMP_CACHE_BYTES);
3820 	if (!phb->diag_data)
3821 		panic("%s: Failed to allocate %u bytes\n", __func__,
3822 		      phb->diag_data_size);
3823 
3824 	/* Parse 32-bit and IO ranges (if any) */
3825 	pci_process_bridge_OF_ranges(hose, np, !hose->global_number);
3826 
3827 	/* Get registers */
3828 	if (!of_address_to_resource(np, 0, &r)) {
3829 		phb->regs_phys = r.start;
3830 		phb->regs = ioremap(r.start, resource_size(&r));
3831 		if (phb->regs == NULL)
3832 			pr_err("  Failed to map registers !\n");
3833 	}
3834 
3835 	/* Initialize more IODA stuff */
3836 	phb->ioda.total_pe_num = 1;
3837 	prop32 = of_get_property(np, "ibm,opal-num-pes", NULL);
3838 	if (prop32)
3839 		phb->ioda.total_pe_num = be32_to_cpup(prop32);
3840 	prop32 = of_get_property(np, "ibm,opal-reserved-pe", NULL);
3841 	if (prop32)
3842 		phb->ioda.reserved_pe_idx = be32_to_cpup(prop32);
3843 
3844 	/* Invalidate RID to PE# mapping */
3845 	for (segno = 0; segno < ARRAY_SIZE(phb->ioda.pe_rmap); segno++)
3846 		phb->ioda.pe_rmap[segno] = IODA_INVALID_PE;
3847 
3848 	/* Parse 64-bit MMIO range */
3849 	pnv_ioda_parse_m64_window(phb);
3850 
3851 	phb->ioda.m32_size = resource_size(&hose->mem_resources[0]);
3852 	/* FW Has already off top 64k of M32 space (MSI space) */
3853 	phb->ioda.m32_size += 0x10000;
3854 
3855 	phb->ioda.m32_segsize = phb->ioda.m32_size / phb->ioda.total_pe_num;
3856 	phb->ioda.m32_pci_base = hose->mem_resources[0].start - hose->mem_offset[0];
3857 	phb->ioda.io_size = hose->pci_io_size;
3858 	phb->ioda.io_segsize = phb->ioda.io_size / phb->ioda.total_pe_num;
3859 	phb->ioda.io_pci_base = 0; /* XXX calculate this ? */
3860 
3861 	/* Calculate how many 32-bit TCE segments we have */
3862 	phb->ioda.dma32_count = phb->ioda.m32_pci_base /
3863 				PNV_IODA1_DMA32_SEGSIZE;
3864 
3865 	/* Allocate aux data & arrays. We don't have IO ports on PHB3 */
3866 	size = _ALIGN_UP(max_t(unsigned, phb->ioda.total_pe_num, 8) / 8,
3867 			sizeof(unsigned long));
3868 	m64map_off = size;
3869 	size += phb->ioda.total_pe_num * sizeof(phb->ioda.m64_segmap[0]);
3870 	m32map_off = size;
3871 	size += phb->ioda.total_pe_num * sizeof(phb->ioda.m32_segmap[0]);
3872 	if (phb->type == PNV_PHB_IODA1) {
3873 		iomap_off = size;
3874 		size += phb->ioda.total_pe_num * sizeof(phb->ioda.io_segmap[0]);
3875 		dma32map_off = size;
3876 		size += phb->ioda.dma32_count *
3877 			sizeof(phb->ioda.dma32_segmap[0]);
3878 	}
3879 	pemap_off = size;
3880 	size += phb->ioda.total_pe_num * sizeof(struct pnv_ioda_pe);
3881 	aux = memblock_alloc(size, SMP_CACHE_BYTES);
3882 	if (!aux)
3883 		panic("%s: Failed to allocate %lu bytes\n", __func__, size);
3884 	phb->ioda.pe_alloc = aux;
3885 	phb->ioda.m64_segmap = aux + m64map_off;
3886 	phb->ioda.m32_segmap = aux + m32map_off;
3887 	for (segno = 0; segno < phb->ioda.total_pe_num; segno++) {
3888 		phb->ioda.m64_segmap[segno] = IODA_INVALID_PE;
3889 		phb->ioda.m32_segmap[segno] = IODA_INVALID_PE;
3890 	}
3891 	if (phb->type == PNV_PHB_IODA1) {
3892 		phb->ioda.io_segmap = aux + iomap_off;
3893 		for (segno = 0; segno < phb->ioda.total_pe_num; segno++)
3894 			phb->ioda.io_segmap[segno] = IODA_INVALID_PE;
3895 
3896 		phb->ioda.dma32_segmap = aux + dma32map_off;
3897 		for (segno = 0; segno < phb->ioda.dma32_count; segno++)
3898 			phb->ioda.dma32_segmap[segno] = IODA_INVALID_PE;
3899 	}
3900 	phb->ioda.pe_array = aux + pemap_off;
3901 
3902 	/*
3903 	 * Choose PE number for root bus, which shouldn't have
3904 	 * M64 resources consumed by its child devices. To pick
3905 	 * the PE number adjacent to the reserved one if possible.
3906 	 */
3907 	pnv_ioda_reserve_pe(phb, phb->ioda.reserved_pe_idx);
3908 	if (phb->ioda.reserved_pe_idx == 0) {
3909 		phb->ioda.root_pe_idx = 1;
3910 		pnv_ioda_reserve_pe(phb, phb->ioda.root_pe_idx);
3911 	} else if (phb->ioda.reserved_pe_idx == (phb->ioda.total_pe_num - 1)) {
3912 		phb->ioda.root_pe_idx = phb->ioda.reserved_pe_idx - 1;
3913 		pnv_ioda_reserve_pe(phb, phb->ioda.root_pe_idx);
3914 	} else {
3915 		phb->ioda.root_pe_idx = IODA_INVALID_PE;
3916 	}
3917 
3918 	INIT_LIST_HEAD(&phb->ioda.pe_list);
3919 	mutex_init(&phb->ioda.pe_list_mutex);
3920 
3921 	/* Calculate how many 32-bit TCE segments we have */
3922 	phb->ioda.dma32_count = phb->ioda.m32_pci_base /
3923 				PNV_IODA1_DMA32_SEGSIZE;
3924 
3925 #if 0 /* We should really do that ... */
3926 	rc = opal_pci_set_phb_mem_window(opal->phb_id,
3927 					 window_type,
3928 					 window_num,
3929 					 starting_real_address,
3930 					 starting_pci_address,
3931 					 segment_size);
3932 #endif
3933 
3934 	pr_info("  %03d (%03d) PE's M32: 0x%x [segment=0x%x]\n",
3935 		phb->ioda.total_pe_num, phb->ioda.reserved_pe_idx,
3936 		phb->ioda.m32_size, phb->ioda.m32_segsize);
3937 	if (phb->ioda.m64_size)
3938 		pr_info("                 M64: 0x%lx [segment=0x%lx]\n",
3939 			phb->ioda.m64_size, phb->ioda.m64_segsize);
3940 	if (phb->ioda.io_size)
3941 		pr_info("                  IO: 0x%x [segment=0x%x]\n",
3942 			phb->ioda.io_size, phb->ioda.io_segsize);
3943 
3944 
3945 	phb->hose->ops = &pnv_pci_ops;
3946 	phb->get_pe_state = pnv_ioda_get_pe_state;
3947 	phb->freeze_pe = pnv_ioda_freeze_pe;
3948 	phb->unfreeze_pe = pnv_ioda_unfreeze_pe;
3949 
3950 	/* Setup MSI support */
3951 	pnv_pci_init_ioda_msis(phb);
3952 
3953 	/*
3954 	 * We pass the PCI probe flag PCI_REASSIGN_ALL_RSRC here
3955 	 * to let the PCI core do resource assignment. It's supposed
3956 	 * that the PCI core will do correct I/O and MMIO alignment
3957 	 * for the P2P bridge bars so that each PCI bus (excluding
3958 	 * the child P2P bridges) can form individual PE.
3959 	 */
3960 	ppc_md.pcibios_fixup = pnv_pci_ioda_fixup;
3961 
3962 	switch (phb->type) {
3963 	case PNV_PHB_NPU_NVLINK:
3964 		hose->controller_ops = pnv_npu_ioda_controller_ops;
3965 		break;
3966 	case PNV_PHB_NPU_OCAPI:
3967 		hose->controller_ops = pnv_npu_ocapi_ioda_controller_ops;
3968 		break;
3969 	default:
3970 		hose->controller_ops = pnv_pci_ioda_controller_ops;
3971 	}
3972 
3973 	ppc_md.pcibios_default_alignment = pnv_pci_default_alignment;
3974 
3975 #ifdef CONFIG_PCI_IOV
3976 	ppc_md.pcibios_fixup_sriov = pnv_pci_ioda_fixup_iov;
3977 	ppc_md.pcibios_iov_resource_alignment = pnv_pci_iov_resource_alignment;
3978 	ppc_md.pcibios_sriov_enable = pnv_pcibios_sriov_enable;
3979 	ppc_md.pcibios_sriov_disable = pnv_pcibios_sriov_disable;
3980 #endif
3981 
3982 	pci_add_flags(PCI_REASSIGN_ALL_RSRC);
3983 
3984 	/* Reset IODA tables to a clean state */
3985 	rc = opal_pci_reset(phb_id, OPAL_RESET_PCI_IODA_TABLE, OPAL_ASSERT_RESET);
3986 	if (rc)
3987 		pr_warn("  OPAL Error %ld performing IODA table reset !\n", rc);
3988 
3989 	/*
3990 	 * If we're running in kdump kernel, the previous kernel never
3991 	 * shutdown PCI devices correctly. We already got IODA table
3992 	 * cleaned out. So we have to issue PHB reset to stop all PCI
3993 	 * transactions from previous kernel. The ppc_pci_reset_phbs
3994 	 * kernel parameter will force this reset too. Additionally,
3995 	 * if the IODA reset above failed then use a bigger hammer.
3996 	 * This can happen if we get a PHB fatal error in very early
3997 	 * boot.
3998 	 */
3999 	if (is_kdump_kernel() || pci_reset_phbs || rc) {
4000 		pr_info("  Issue PHB reset ...\n");
4001 		pnv_eeh_phb_reset(hose, EEH_RESET_FUNDAMENTAL);
4002 		pnv_eeh_phb_reset(hose, EEH_RESET_DEACTIVATE);
4003 	}
4004 
4005 	/* Remove M64 resource if we can't configure it successfully */
4006 	if (!phb->init_m64 || phb->init_m64(phb))
4007 		hose->mem_resources[1].flags = 0;
4008 }
4009 
4010 void __init pnv_pci_init_ioda2_phb(struct device_node *np)
4011 {
4012 	pnv_pci_init_ioda_phb(np, 0, PNV_PHB_IODA2);
4013 }
4014 
4015 void __init pnv_pci_init_npu_phb(struct device_node *np)
4016 {
4017 	pnv_pci_init_ioda_phb(np, 0, PNV_PHB_NPU_NVLINK);
4018 }
4019 
4020 void __init pnv_pci_init_npu2_opencapi_phb(struct device_node *np)
4021 {
4022 	pnv_pci_init_ioda_phb(np, 0, PNV_PHB_NPU_OCAPI);
4023 }
4024 
4025 static void pnv_npu2_opencapi_cfg_size_fixup(struct pci_dev *dev)
4026 {
4027 	struct pci_controller *hose = pci_bus_to_host(dev->bus);
4028 	struct pnv_phb *phb = hose->private_data;
4029 
4030 	if (!machine_is(powernv))
4031 		return;
4032 
4033 	if (phb->type == PNV_PHB_NPU_OCAPI)
4034 		dev->cfg_size = PCI_CFG_SPACE_EXP_SIZE;
4035 }
4036 DECLARE_PCI_FIXUP_EARLY(PCI_ANY_ID, PCI_ANY_ID, pnv_npu2_opencapi_cfg_size_fixup);
4037 
4038 void __init pnv_pci_init_ioda_hub(struct device_node *np)
4039 {
4040 	struct device_node *phbn;
4041 	const __be64 *prop64;
4042 	u64 hub_id;
4043 
4044 	pr_info("Probing IODA IO-Hub %pOF\n", np);
4045 
4046 	prop64 = of_get_property(np, "ibm,opal-hubid", NULL);
4047 	if (!prop64) {
4048 		pr_err(" Missing \"ibm,opal-hubid\" property !\n");
4049 		return;
4050 	}
4051 	hub_id = be64_to_cpup(prop64);
4052 	pr_devel(" HUB-ID : 0x%016llx\n", hub_id);
4053 
4054 	/* Count child PHBs */
4055 	for_each_child_of_node(np, phbn) {
4056 		/* Look for IODA1 PHBs */
4057 		if (of_device_is_compatible(phbn, "ibm,ioda-phb"))
4058 			pnv_pci_init_ioda_phb(phbn, hub_id, PNV_PHB_IODA1);
4059 	}
4060 }
4061