1 /* 2 * Support PCI/PCIe on PowerNV platforms 3 * 4 * Copyright 2011 Benjamin Herrenschmidt, IBM Corp. 5 * 6 * This program is free software; you can redistribute it and/or 7 * modify it under the terms of the GNU General Public License 8 * as published by the Free Software Foundation; either version 9 * 2 of the License, or (at your option) any later version. 10 */ 11 12 #undef DEBUG 13 14 #include <linux/kernel.h> 15 #include <linux/pci.h> 16 #include <linux/crash_dump.h> 17 #include <linux/debugfs.h> 18 #include <linux/delay.h> 19 #include <linux/string.h> 20 #include <linux/init.h> 21 #include <linux/bootmem.h> 22 #include <linux/irq.h> 23 #include <linux/io.h> 24 #include <linux/msi.h> 25 #include <linux/memblock.h> 26 #include <linux/iommu.h> 27 #include <linux/rculist.h> 28 #include <linux/sizes.h> 29 30 #include <asm/sections.h> 31 #include <asm/io.h> 32 #include <asm/prom.h> 33 #include <asm/pci-bridge.h> 34 #include <asm/machdep.h> 35 #include <asm/msi_bitmap.h> 36 #include <asm/ppc-pci.h> 37 #include <asm/opal.h> 38 #include <asm/iommu.h> 39 #include <asm/tce.h> 40 #include <asm/xics.h> 41 #include <asm/debug.h> 42 #include <asm/firmware.h> 43 #include <asm/pnv-pci.h> 44 #include <asm/mmzone.h> 45 46 #include <misc/cxl-base.h> 47 48 #include "powernv.h" 49 #include "pci.h" 50 51 #define PNV_IODA1_M64_NUM 16 /* Number of M64 BARs */ 52 #define PNV_IODA1_M64_SEGS 8 /* Segments per M64 BAR */ 53 #define PNV_IODA1_DMA32_SEGSIZE 0x10000000 54 55 #define POWERNV_IOMMU_DEFAULT_LEVELS 1 56 #define POWERNV_IOMMU_MAX_LEVELS 5 57 58 static void pnv_pci_ioda2_table_free_pages(struct iommu_table *tbl); 59 60 static void pe_level_printk(const struct pnv_ioda_pe *pe, const char *level, 61 const char *fmt, ...) 62 { 63 struct va_format vaf; 64 va_list args; 65 char pfix[32]; 66 67 va_start(args, fmt); 68 69 vaf.fmt = fmt; 70 vaf.va = &args; 71 72 if (pe->flags & PNV_IODA_PE_DEV) 73 strlcpy(pfix, dev_name(&pe->pdev->dev), sizeof(pfix)); 74 else if (pe->flags & (PNV_IODA_PE_BUS | PNV_IODA_PE_BUS_ALL)) 75 sprintf(pfix, "%04x:%02x ", 76 pci_domain_nr(pe->pbus), pe->pbus->number); 77 #ifdef CONFIG_PCI_IOV 78 else if (pe->flags & PNV_IODA_PE_VF) 79 sprintf(pfix, "%04x:%02x:%2x.%d", 80 pci_domain_nr(pe->parent_dev->bus), 81 (pe->rid & 0xff00) >> 8, 82 PCI_SLOT(pe->rid), PCI_FUNC(pe->rid)); 83 #endif /* CONFIG_PCI_IOV*/ 84 85 printk("%spci %s: [PE# %.3d] %pV", 86 level, pfix, pe->pe_number, &vaf); 87 88 va_end(args); 89 } 90 91 #define pe_err(pe, fmt, ...) \ 92 pe_level_printk(pe, KERN_ERR, fmt, ##__VA_ARGS__) 93 #define pe_warn(pe, fmt, ...) \ 94 pe_level_printk(pe, KERN_WARNING, fmt, ##__VA_ARGS__) 95 #define pe_info(pe, fmt, ...) \ 96 pe_level_printk(pe, KERN_INFO, fmt, ##__VA_ARGS__) 97 98 static bool pnv_iommu_bypass_disabled __read_mostly; 99 100 static int __init iommu_setup(char *str) 101 { 102 if (!str) 103 return -EINVAL; 104 105 while (*str) { 106 if (!strncmp(str, "nobypass", 8)) { 107 pnv_iommu_bypass_disabled = true; 108 pr_info("PowerNV: IOMMU bypass window disabled.\n"); 109 break; 110 } 111 str += strcspn(str, ","); 112 if (*str == ',') 113 str++; 114 } 115 116 return 0; 117 } 118 early_param("iommu", iommu_setup); 119 120 static inline bool pnv_pci_is_mem_pref_64(unsigned long flags) 121 { 122 return ((flags & (IORESOURCE_MEM_64 | IORESOURCE_PREFETCH)) == 123 (IORESOURCE_MEM_64 | IORESOURCE_PREFETCH)); 124 } 125 126 static void pnv_ioda_reserve_pe(struct pnv_phb *phb, int pe_no) 127 { 128 if (!(pe_no >= 0 && pe_no < phb->ioda.total_pe_num)) { 129 pr_warn("%s: Invalid PE %d on PHB#%x\n", 130 __func__, pe_no, phb->hose->global_number); 131 return; 132 } 133 134 if (test_and_set_bit(pe_no, phb->ioda.pe_alloc)) 135 pr_debug("%s: PE %d was reserved on PHB#%x\n", 136 __func__, pe_no, phb->hose->global_number); 137 138 phb->ioda.pe_array[pe_no].phb = phb; 139 phb->ioda.pe_array[pe_no].pe_number = pe_no; 140 } 141 142 static unsigned int pnv_ioda_alloc_pe(struct pnv_phb *phb) 143 { 144 unsigned long pe; 145 146 do { 147 pe = find_next_zero_bit(phb->ioda.pe_alloc, 148 phb->ioda.total_pe_num, 0); 149 if (pe >= phb->ioda.total_pe_num) 150 return IODA_INVALID_PE; 151 } while(test_and_set_bit(pe, phb->ioda.pe_alloc)); 152 153 phb->ioda.pe_array[pe].phb = phb; 154 phb->ioda.pe_array[pe].pe_number = pe; 155 return pe; 156 } 157 158 static void pnv_ioda_free_pe(struct pnv_phb *phb, int pe) 159 { 160 WARN_ON(phb->ioda.pe_array[pe].pdev); 161 162 memset(&phb->ioda.pe_array[pe], 0, sizeof(struct pnv_ioda_pe)); 163 clear_bit(pe, phb->ioda.pe_alloc); 164 } 165 166 /* The default M64 BAR is shared by all PEs */ 167 static int pnv_ioda2_init_m64(struct pnv_phb *phb) 168 { 169 const char *desc; 170 struct resource *r; 171 s64 rc; 172 173 /* Configure the default M64 BAR */ 174 rc = opal_pci_set_phb_mem_window(phb->opal_id, 175 OPAL_M64_WINDOW_TYPE, 176 phb->ioda.m64_bar_idx, 177 phb->ioda.m64_base, 178 0, /* unused */ 179 phb->ioda.m64_size); 180 if (rc != OPAL_SUCCESS) { 181 desc = "configuring"; 182 goto fail; 183 } 184 185 /* Enable the default M64 BAR */ 186 rc = opal_pci_phb_mmio_enable(phb->opal_id, 187 OPAL_M64_WINDOW_TYPE, 188 phb->ioda.m64_bar_idx, 189 OPAL_ENABLE_M64_SPLIT); 190 if (rc != OPAL_SUCCESS) { 191 desc = "enabling"; 192 goto fail; 193 } 194 195 /* Mark the M64 BAR assigned */ 196 set_bit(phb->ioda.m64_bar_idx, &phb->ioda.m64_bar_alloc); 197 198 /* 199 * Strip off the segment used by the reserved PE, which is 200 * expected to be 0 or last one of PE capabicity. 201 */ 202 r = &phb->hose->mem_resources[1]; 203 if (phb->ioda.reserved_pe_idx == 0) 204 r->start += phb->ioda.m64_segsize; 205 else if (phb->ioda.reserved_pe_idx == (phb->ioda.total_pe_num - 1)) 206 r->end -= phb->ioda.m64_segsize; 207 else 208 pr_warn(" Cannot strip M64 segment for reserved PE#%d\n", 209 phb->ioda.reserved_pe_idx); 210 211 return 0; 212 213 fail: 214 pr_warn(" Failure %lld %s M64 BAR#%d\n", 215 rc, desc, phb->ioda.m64_bar_idx); 216 opal_pci_phb_mmio_enable(phb->opal_id, 217 OPAL_M64_WINDOW_TYPE, 218 phb->ioda.m64_bar_idx, 219 OPAL_DISABLE_M64); 220 return -EIO; 221 } 222 223 static void pnv_ioda_reserve_dev_m64_pe(struct pci_dev *pdev, 224 unsigned long *pe_bitmap) 225 { 226 struct pci_controller *hose = pci_bus_to_host(pdev->bus); 227 struct pnv_phb *phb = hose->private_data; 228 struct resource *r; 229 resource_size_t base, sgsz, start, end; 230 int segno, i; 231 232 base = phb->ioda.m64_base; 233 sgsz = phb->ioda.m64_segsize; 234 for (i = 0; i <= PCI_ROM_RESOURCE; i++) { 235 r = &pdev->resource[i]; 236 if (!r->parent || !pnv_pci_is_mem_pref_64(r->flags)) 237 continue; 238 239 start = _ALIGN_DOWN(r->start - base, sgsz); 240 end = _ALIGN_UP(r->end - base, sgsz); 241 for (segno = start / sgsz; segno < end / sgsz; segno++) { 242 if (pe_bitmap) 243 set_bit(segno, pe_bitmap); 244 else 245 pnv_ioda_reserve_pe(phb, segno); 246 } 247 } 248 } 249 250 static int pnv_ioda1_init_m64(struct pnv_phb *phb) 251 { 252 struct resource *r; 253 int index; 254 255 /* 256 * There are 16 M64 BARs, each of which has 8 segments. So 257 * there are as many M64 segments as the maximum number of 258 * PEs, which is 128. 259 */ 260 for (index = 0; index < PNV_IODA1_M64_NUM; index++) { 261 unsigned long base, segsz = phb->ioda.m64_segsize; 262 int64_t rc; 263 264 base = phb->ioda.m64_base + 265 index * PNV_IODA1_M64_SEGS * segsz; 266 rc = opal_pci_set_phb_mem_window(phb->opal_id, 267 OPAL_M64_WINDOW_TYPE, index, base, 0, 268 PNV_IODA1_M64_SEGS * segsz); 269 if (rc != OPAL_SUCCESS) { 270 pr_warn(" Error %lld setting M64 PHB#%d-BAR#%d\n", 271 rc, phb->hose->global_number, index); 272 goto fail; 273 } 274 275 rc = opal_pci_phb_mmio_enable(phb->opal_id, 276 OPAL_M64_WINDOW_TYPE, index, 277 OPAL_ENABLE_M64_SPLIT); 278 if (rc != OPAL_SUCCESS) { 279 pr_warn(" Error %lld enabling M64 PHB#%d-BAR#%d\n", 280 rc, phb->hose->global_number, index); 281 goto fail; 282 } 283 } 284 285 /* 286 * Exclude the segment used by the reserved PE, which 287 * is expected to be 0 or last supported PE#. 288 */ 289 r = &phb->hose->mem_resources[1]; 290 if (phb->ioda.reserved_pe_idx == 0) 291 r->start += phb->ioda.m64_segsize; 292 else if (phb->ioda.reserved_pe_idx == (phb->ioda.total_pe_num - 1)) 293 r->end -= phb->ioda.m64_segsize; 294 else 295 WARN(1, "Wrong reserved PE#%d on PHB#%d\n", 296 phb->ioda.reserved_pe_idx, phb->hose->global_number); 297 298 return 0; 299 300 fail: 301 for ( ; index >= 0; index--) 302 opal_pci_phb_mmio_enable(phb->opal_id, 303 OPAL_M64_WINDOW_TYPE, index, OPAL_DISABLE_M64); 304 305 return -EIO; 306 } 307 308 static void pnv_ioda_reserve_m64_pe(struct pci_bus *bus, 309 unsigned long *pe_bitmap, 310 bool all) 311 { 312 struct pci_dev *pdev; 313 314 list_for_each_entry(pdev, &bus->devices, bus_list) { 315 pnv_ioda_reserve_dev_m64_pe(pdev, pe_bitmap); 316 317 if (all && pdev->subordinate) 318 pnv_ioda_reserve_m64_pe(pdev->subordinate, 319 pe_bitmap, all); 320 } 321 } 322 323 static unsigned int pnv_ioda_pick_m64_pe(struct pci_bus *bus, bool all) 324 { 325 struct pci_controller *hose = pci_bus_to_host(bus); 326 struct pnv_phb *phb = hose->private_data; 327 struct pnv_ioda_pe *master_pe, *pe; 328 unsigned long size, *pe_alloc; 329 int i; 330 331 /* Root bus shouldn't use M64 */ 332 if (pci_is_root_bus(bus)) 333 return IODA_INVALID_PE; 334 335 /* Allocate bitmap */ 336 size = _ALIGN_UP(phb->ioda.total_pe_num / 8, sizeof(unsigned long)); 337 pe_alloc = kzalloc(size, GFP_KERNEL); 338 if (!pe_alloc) { 339 pr_warn("%s: Out of memory !\n", 340 __func__); 341 return IODA_INVALID_PE; 342 } 343 344 /* Figure out reserved PE numbers by the PE */ 345 pnv_ioda_reserve_m64_pe(bus, pe_alloc, all); 346 347 /* 348 * the current bus might not own M64 window and that's all 349 * contributed by its child buses. For the case, we needn't 350 * pick M64 dependent PE#. 351 */ 352 if (bitmap_empty(pe_alloc, phb->ioda.total_pe_num)) { 353 kfree(pe_alloc); 354 return IODA_INVALID_PE; 355 } 356 357 /* 358 * Figure out the master PE and put all slave PEs to master 359 * PE's list to form compound PE. 360 */ 361 master_pe = NULL; 362 i = -1; 363 while ((i = find_next_bit(pe_alloc, phb->ioda.total_pe_num, i + 1)) < 364 phb->ioda.total_pe_num) { 365 pe = &phb->ioda.pe_array[i]; 366 367 phb->ioda.m64_segmap[pe->pe_number] = pe->pe_number; 368 if (!master_pe) { 369 pe->flags |= PNV_IODA_PE_MASTER; 370 INIT_LIST_HEAD(&pe->slaves); 371 master_pe = pe; 372 } else { 373 pe->flags |= PNV_IODA_PE_SLAVE; 374 pe->master = master_pe; 375 list_add_tail(&pe->list, &master_pe->slaves); 376 } 377 378 /* 379 * P7IOC supports M64DT, which helps mapping M64 segment 380 * to one particular PE#. However, PHB3 has fixed mapping 381 * between M64 segment and PE#. In order to have same logic 382 * for P7IOC and PHB3, we enforce fixed mapping between M64 383 * segment and PE# on P7IOC. 384 */ 385 if (phb->type == PNV_PHB_IODA1) { 386 int64_t rc; 387 388 rc = opal_pci_map_pe_mmio_window(phb->opal_id, 389 pe->pe_number, OPAL_M64_WINDOW_TYPE, 390 pe->pe_number / PNV_IODA1_M64_SEGS, 391 pe->pe_number % PNV_IODA1_M64_SEGS); 392 if (rc != OPAL_SUCCESS) 393 pr_warn("%s: Error %lld mapping M64 for PHB#%d-PE#%d\n", 394 __func__, rc, phb->hose->global_number, 395 pe->pe_number); 396 } 397 } 398 399 kfree(pe_alloc); 400 return master_pe->pe_number; 401 } 402 403 static void __init pnv_ioda_parse_m64_window(struct pnv_phb *phb) 404 { 405 struct pci_controller *hose = phb->hose; 406 struct device_node *dn = hose->dn; 407 struct resource *res; 408 const u32 *r; 409 u64 pci_addr; 410 411 if (phb->type != PNV_PHB_IODA1 && phb->type != PNV_PHB_IODA2) { 412 pr_info(" Not support M64 window\n"); 413 return; 414 } 415 416 if (!firmware_has_feature(FW_FEATURE_OPAL)) { 417 pr_info(" Firmware too old to support M64 window\n"); 418 return; 419 } 420 421 r = of_get_property(dn, "ibm,opal-m64-window", NULL); 422 if (!r) { 423 pr_info(" No <ibm,opal-m64-window> on %s\n", 424 dn->full_name); 425 return; 426 } 427 428 res = &hose->mem_resources[1]; 429 res->name = dn->full_name; 430 res->start = of_translate_address(dn, r + 2); 431 res->end = res->start + of_read_number(r + 4, 2) - 1; 432 res->flags = (IORESOURCE_MEM | IORESOURCE_MEM_64 | IORESOURCE_PREFETCH); 433 pci_addr = of_read_number(r, 2); 434 hose->mem_offset[1] = res->start - pci_addr; 435 436 phb->ioda.m64_size = resource_size(res); 437 phb->ioda.m64_segsize = phb->ioda.m64_size / phb->ioda.total_pe_num; 438 phb->ioda.m64_base = pci_addr; 439 440 pr_info(" MEM64 0x%016llx..0x%016llx -> 0x%016llx\n", 441 res->start, res->end, pci_addr); 442 443 /* Use last M64 BAR to cover M64 window */ 444 phb->ioda.m64_bar_idx = 15; 445 if (phb->type == PNV_PHB_IODA1) 446 phb->init_m64 = pnv_ioda1_init_m64; 447 else 448 phb->init_m64 = pnv_ioda2_init_m64; 449 phb->reserve_m64_pe = pnv_ioda_reserve_m64_pe; 450 phb->pick_m64_pe = pnv_ioda_pick_m64_pe; 451 } 452 453 static void pnv_ioda_freeze_pe(struct pnv_phb *phb, int pe_no) 454 { 455 struct pnv_ioda_pe *pe = &phb->ioda.pe_array[pe_no]; 456 struct pnv_ioda_pe *slave; 457 s64 rc; 458 459 /* Fetch master PE */ 460 if (pe->flags & PNV_IODA_PE_SLAVE) { 461 pe = pe->master; 462 if (WARN_ON(!pe || !(pe->flags & PNV_IODA_PE_MASTER))) 463 return; 464 465 pe_no = pe->pe_number; 466 } 467 468 /* Freeze master PE */ 469 rc = opal_pci_eeh_freeze_set(phb->opal_id, 470 pe_no, 471 OPAL_EEH_ACTION_SET_FREEZE_ALL); 472 if (rc != OPAL_SUCCESS) { 473 pr_warn("%s: Failure %lld freezing PHB#%x-PE#%x\n", 474 __func__, rc, phb->hose->global_number, pe_no); 475 return; 476 } 477 478 /* Freeze slave PEs */ 479 if (!(pe->flags & PNV_IODA_PE_MASTER)) 480 return; 481 482 list_for_each_entry(slave, &pe->slaves, list) { 483 rc = opal_pci_eeh_freeze_set(phb->opal_id, 484 slave->pe_number, 485 OPAL_EEH_ACTION_SET_FREEZE_ALL); 486 if (rc != OPAL_SUCCESS) 487 pr_warn("%s: Failure %lld freezing PHB#%x-PE#%x\n", 488 __func__, rc, phb->hose->global_number, 489 slave->pe_number); 490 } 491 } 492 493 static int pnv_ioda_unfreeze_pe(struct pnv_phb *phb, int pe_no, int opt) 494 { 495 struct pnv_ioda_pe *pe, *slave; 496 s64 rc; 497 498 /* Find master PE */ 499 pe = &phb->ioda.pe_array[pe_no]; 500 if (pe->flags & PNV_IODA_PE_SLAVE) { 501 pe = pe->master; 502 WARN_ON(!pe || !(pe->flags & PNV_IODA_PE_MASTER)); 503 pe_no = pe->pe_number; 504 } 505 506 /* Clear frozen state for master PE */ 507 rc = opal_pci_eeh_freeze_clear(phb->opal_id, pe_no, opt); 508 if (rc != OPAL_SUCCESS) { 509 pr_warn("%s: Failure %lld clear %d on PHB#%x-PE#%x\n", 510 __func__, rc, opt, phb->hose->global_number, pe_no); 511 return -EIO; 512 } 513 514 if (!(pe->flags & PNV_IODA_PE_MASTER)) 515 return 0; 516 517 /* Clear frozen state for slave PEs */ 518 list_for_each_entry(slave, &pe->slaves, list) { 519 rc = opal_pci_eeh_freeze_clear(phb->opal_id, 520 slave->pe_number, 521 opt); 522 if (rc != OPAL_SUCCESS) { 523 pr_warn("%s: Failure %lld clear %d on PHB#%x-PE#%x\n", 524 __func__, rc, opt, phb->hose->global_number, 525 slave->pe_number); 526 return -EIO; 527 } 528 } 529 530 return 0; 531 } 532 533 static int pnv_ioda_get_pe_state(struct pnv_phb *phb, int pe_no) 534 { 535 struct pnv_ioda_pe *slave, *pe; 536 u8 fstate, state; 537 __be16 pcierr; 538 s64 rc; 539 540 /* Sanity check on PE number */ 541 if (pe_no < 0 || pe_no >= phb->ioda.total_pe_num) 542 return OPAL_EEH_STOPPED_PERM_UNAVAIL; 543 544 /* 545 * Fetch the master PE and the PE instance might be 546 * not initialized yet. 547 */ 548 pe = &phb->ioda.pe_array[pe_no]; 549 if (pe->flags & PNV_IODA_PE_SLAVE) { 550 pe = pe->master; 551 WARN_ON(!pe || !(pe->flags & PNV_IODA_PE_MASTER)); 552 pe_no = pe->pe_number; 553 } 554 555 /* Check the master PE */ 556 rc = opal_pci_eeh_freeze_status(phb->opal_id, pe_no, 557 &state, &pcierr, NULL); 558 if (rc != OPAL_SUCCESS) { 559 pr_warn("%s: Failure %lld getting " 560 "PHB#%x-PE#%x state\n", 561 __func__, rc, 562 phb->hose->global_number, pe_no); 563 return OPAL_EEH_STOPPED_TEMP_UNAVAIL; 564 } 565 566 /* Check the slave PE */ 567 if (!(pe->flags & PNV_IODA_PE_MASTER)) 568 return state; 569 570 list_for_each_entry(slave, &pe->slaves, list) { 571 rc = opal_pci_eeh_freeze_status(phb->opal_id, 572 slave->pe_number, 573 &fstate, 574 &pcierr, 575 NULL); 576 if (rc != OPAL_SUCCESS) { 577 pr_warn("%s: Failure %lld getting " 578 "PHB#%x-PE#%x state\n", 579 __func__, rc, 580 phb->hose->global_number, slave->pe_number); 581 return OPAL_EEH_STOPPED_TEMP_UNAVAIL; 582 } 583 584 /* 585 * Override the result based on the ascending 586 * priority. 587 */ 588 if (fstate > state) 589 state = fstate; 590 } 591 592 return state; 593 } 594 595 /* Currently those 2 are only used when MSIs are enabled, this will change 596 * but in the meantime, we need to protect them to avoid warnings 597 */ 598 #ifdef CONFIG_PCI_MSI 599 static struct pnv_ioda_pe *pnv_ioda_get_pe(struct pci_dev *dev) 600 { 601 struct pci_controller *hose = pci_bus_to_host(dev->bus); 602 struct pnv_phb *phb = hose->private_data; 603 struct pci_dn *pdn = pci_get_pdn(dev); 604 605 if (!pdn) 606 return NULL; 607 if (pdn->pe_number == IODA_INVALID_PE) 608 return NULL; 609 return &phb->ioda.pe_array[pdn->pe_number]; 610 } 611 #endif /* CONFIG_PCI_MSI */ 612 613 static int pnv_ioda_set_one_peltv(struct pnv_phb *phb, 614 struct pnv_ioda_pe *parent, 615 struct pnv_ioda_pe *child, 616 bool is_add) 617 { 618 const char *desc = is_add ? "adding" : "removing"; 619 uint8_t op = is_add ? OPAL_ADD_PE_TO_DOMAIN : 620 OPAL_REMOVE_PE_FROM_DOMAIN; 621 struct pnv_ioda_pe *slave; 622 long rc; 623 624 /* Parent PE affects child PE */ 625 rc = opal_pci_set_peltv(phb->opal_id, parent->pe_number, 626 child->pe_number, op); 627 if (rc != OPAL_SUCCESS) { 628 pe_warn(child, "OPAL error %ld %s to parent PELTV\n", 629 rc, desc); 630 return -ENXIO; 631 } 632 633 if (!(child->flags & PNV_IODA_PE_MASTER)) 634 return 0; 635 636 /* Compound case: parent PE affects slave PEs */ 637 list_for_each_entry(slave, &child->slaves, list) { 638 rc = opal_pci_set_peltv(phb->opal_id, parent->pe_number, 639 slave->pe_number, op); 640 if (rc != OPAL_SUCCESS) { 641 pe_warn(slave, "OPAL error %ld %s to parent PELTV\n", 642 rc, desc); 643 return -ENXIO; 644 } 645 } 646 647 return 0; 648 } 649 650 static int pnv_ioda_set_peltv(struct pnv_phb *phb, 651 struct pnv_ioda_pe *pe, 652 bool is_add) 653 { 654 struct pnv_ioda_pe *slave; 655 struct pci_dev *pdev = NULL; 656 int ret; 657 658 /* 659 * Clear PE frozen state. If it's master PE, we need 660 * clear slave PE frozen state as well. 661 */ 662 if (is_add) { 663 opal_pci_eeh_freeze_clear(phb->opal_id, pe->pe_number, 664 OPAL_EEH_ACTION_CLEAR_FREEZE_ALL); 665 if (pe->flags & PNV_IODA_PE_MASTER) { 666 list_for_each_entry(slave, &pe->slaves, list) 667 opal_pci_eeh_freeze_clear(phb->opal_id, 668 slave->pe_number, 669 OPAL_EEH_ACTION_CLEAR_FREEZE_ALL); 670 } 671 } 672 673 /* 674 * Associate PE in PELT. We need add the PE into the 675 * corresponding PELT-V as well. Otherwise, the error 676 * originated from the PE might contribute to other 677 * PEs. 678 */ 679 ret = pnv_ioda_set_one_peltv(phb, pe, pe, is_add); 680 if (ret) 681 return ret; 682 683 /* For compound PEs, any one affects all of them */ 684 if (pe->flags & PNV_IODA_PE_MASTER) { 685 list_for_each_entry(slave, &pe->slaves, list) { 686 ret = pnv_ioda_set_one_peltv(phb, slave, pe, is_add); 687 if (ret) 688 return ret; 689 } 690 } 691 692 if (pe->flags & (PNV_IODA_PE_BUS_ALL | PNV_IODA_PE_BUS)) 693 pdev = pe->pbus->self; 694 else if (pe->flags & PNV_IODA_PE_DEV) 695 pdev = pe->pdev->bus->self; 696 #ifdef CONFIG_PCI_IOV 697 else if (pe->flags & PNV_IODA_PE_VF) 698 pdev = pe->parent_dev; 699 #endif /* CONFIG_PCI_IOV */ 700 while (pdev) { 701 struct pci_dn *pdn = pci_get_pdn(pdev); 702 struct pnv_ioda_pe *parent; 703 704 if (pdn && pdn->pe_number != IODA_INVALID_PE) { 705 parent = &phb->ioda.pe_array[pdn->pe_number]; 706 ret = pnv_ioda_set_one_peltv(phb, parent, pe, is_add); 707 if (ret) 708 return ret; 709 } 710 711 pdev = pdev->bus->self; 712 } 713 714 return 0; 715 } 716 717 #ifdef CONFIG_PCI_IOV 718 static int pnv_ioda_deconfigure_pe(struct pnv_phb *phb, struct pnv_ioda_pe *pe) 719 { 720 struct pci_dev *parent; 721 uint8_t bcomp, dcomp, fcomp; 722 int64_t rc; 723 long rid_end, rid; 724 725 /* Currently, we just deconfigure VF PE. Bus PE will always there.*/ 726 if (pe->pbus) { 727 int count; 728 729 dcomp = OPAL_IGNORE_RID_DEVICE_NUMBER; 730 fcomp = OPAL_IGNORE_RID_FUNCTION_NUMBER; 731 parent = pe->pbus->self; 732 if (pe->flags & PNV_IODA_PE_BUS_ALL) 733 count = pe->pbus->busn_res.end - pe->pbus->busn_res.start + 1; 734 else 735 count = 1; 736 737 switch(count) { 738 case 1: bcomp = OpalPciBusAll; break; 739 case 2: bcomp = OpalPciBus7Bits; break; 740 case 4: bcomp = OpalPciBus6Bits; break; 741 case 8: bcomp = OpalPciBus5Bits; break; 742 case 16: bcomp = OpalPciBus4Bits; break; 743 case 32: bcomp = OpalPciBus3Bits; break; 744 default: 745 dev_err(&pe->pbus->dev, "Number of subordinate buses %d unsupported\n", 746 count); 747 /* Do an exact match only */ 748 bcomp = OpalPciBusAll; 749 } 750 rid_end = pe->rid + (count << 8); 751 } else { 752 if (pe->flags & PNV_IODA_PE_VF) 753 parent = pe->parent_dev; 754 else 755 parent = pe->pdev->bus->self; 756 bcomp = OpalPciBusAll; 757 dcomp = OPAL_COMPARE_RID_DEVICE_NUMBER; 758 fcomp = OPAL_COMPARE_RID_FUNCTION_NUMBER; 759 rid_end = pe->rid + 1; 760 } 761 762 /* Clear the reverse map */ 763 for (rid = pe->rid; rid < rid_end; rid++) 764 phb->ioda.pe_rmap[rid] = 0; 765 766 /* Release from all parents PELT-V */ 767 while (parent) { 768 struct pci_dn *pdn = pci_get_pdn(parent); 769 if (pdn && pdn->pe_number != IODA_INVALID_PE) { 770 rc = opal_pci_set_peltv(phb->opal_id, pdn->pe_number, 771 pe->pe_number, OPAL_REMOVE_PE_FROM_DOMAIN); 772 /* XXX What to do in case of error ? */ 773 } 774 parent = parent->bus->self; 775 } 776 777 opal_pci_eeh_freeze_clear(phb->opal_id, pe->pe_number, 778 OPAL_EEH_ACTION_CLEAR_FREEZE_ALL); 779 780 /* Disassociate PE in PELT */ 781 rc = opal_pci_set_peltv(phb->opal_id, pe->pe_number, 782 pe->pe_number, OPAL_REMOVE_PE_FROM_DOMAIN); 783 if (rc) 784 pe_warn(pe, "OPAL error %ld remove self from PELTV\n", rc); 785 rc = opal_pci_set_pe(phb->opal_id, pe->pe_number, pe->rid, 786 bcomp, dcomp, fcomp, OPAL_UNMAP_PE); 787 if (rc) 788 pe_err(pe, "OPAL error %ld trying to setup PELT table\n", rc); 789 790 pe->pbus = NULL; 791 pe->pdev = NULL; 792 pe->parent_dev = NULL; 793 794 return 0; 795 } 796 #endif /* CONFIG_PCI_IOV */ 797 798 static int pnv_ioda_configure_pe(struct pnv_phb *phb, struct pnv_ioda_pe *pe) 799 { 800 struct pci_dev *parent; 801 uint8_t bcomp, dcomp, fcomp; 802 long rc, rid_end, rid; 803 804 /* Bus validation ? */ 805 if (pe->pbus) { 806 int count; 807 808 dcomp = OPAL_IGNORE_RID_DEVICE_NUMBER; 809 fcomp = OPAL_IGNORE_RID_FUNCTION_NUMBER; 810 parent = pe->pbus->self; 811 if (pe->flags & PNV_IODA_PE_BUS_ALL) 812 count = pe->pbus->busn_res.end - pe->pbus->busn_res.start + 1; 813 else 814 count = 1; 815 816 switch(count) { 817 case 1: bcomp = OpalPciBusAll; break; 818 case 2: bcomp = OpalPciBus7Bits; break; 819 case 4: bcomp = OpalPciBus6Bits; break; 820 case 8: bcomp = OpalPciBus5Bits; break; 821 case 16: bcomp = OpalPciBus4Bits; break; 822 case 32: bcomp = OpalPciBus3Bits; break; 823 default: 824 dev_err(&pe->pbus->dev, "Number of subordinate buses %d unsupported\n", 825 count); 826 /* Do an exact match only */ 827 bcomp = OpalPciBusAll; 828 } 829 rid_end = pe->rid + (count << 8); 830 } else { 831 #ifdef CONFIG_PCI_IOV 832 if (pe->flags & PNV_IODA_PE_VF) 833 parent = pe->parent_dev; 834 else 835 #endif /* CONFIG_PCI_IOV */ 836 parent = pe->pdev->bus->self; 837 bcomp = OpalPciBusAll; 838 dcomp = OPAL_COMPARE_RID_DEVICE_NUMBER; 839 fcomp = OPAL_COMPARE_RID_FUNCTION_NUMBER; 840 rid_end = pe->rid + 1; 841 } 842 843 /* 844 * Associate PE in PELT. We need add the PE into the 845 * corresponding PELT-V as well. Otherwise, the error 846 * originated from the PE might contribute to other 847 * PEs. 848 */ 849 rc = opal_pci_set_pe(phb->opal_id, pe->pe_number, pe->rid, 850 bcomp, dcomp, fcomp, OPAL_MAP_PE); 851 if (rc) { 852 pe_err(pe, "OPAL error %ld trying to setup PELT table\n", rc); 853 return -ENXIO; 854 } 855 856 /* 857 * Configure PELTV. NPUs don't have a PELTV table so skip 858 * configuration on them. 859 */ 860 if (phb->type != PNV_PHB_NPU) 861 pnv_ioda_set_peltv(phb, pe, true); 862 863 /* Setup reverse map */ 864 for (rid = pe->rid; rid < rid_end; rid++) 865 phb->ioda.pe_rmap[rid] = pe->pe_number; 866 867 /* Setup one MVTs on IODA1 */ 868 if (phb->type != PNV_PHB_IODA1) { 869 pe->mve_number = 0; 870 goto out; 871 } 872 873 pe->mve_number = pe->pe_number; 874 rc = opal_pci_set_mve(phb->opal_id, pe->mve_number, pe->pe_number); 875 if (rc != OPAL_SUCCESS) { 876 pe_err(pe, "OPAL error %ld setting up MVE %d\n", 877 rc, pe->mve_number); 878 pe->mve_number = -1; 879 } else { 880 rc = opal_pci_set_mve_enable(phb->opal_id, 881 pe->mve_number, OPAL_ENABLE_MVE); 882 if (rc) { 883 pe_err(pe, "OPAL error %ld enabling MVE %d\n", 884 rc, pe->mve_number); 885 pe->mve_number = -1; 886 } 887 } 888 889 out: 890 return 0; 891 } 892 893 #ifdef CONFIG_PCI_IOV 894 static int pnv_pci_vf_resource_shift(struct pci_dev *dev, int offset) 895 { 896 struct pci_dn *pdn = pci_get_pdn(dev); 897 int i; 898 struct resource *res, res2; 899 resource_size_t size; 900 u16 num_vfs; 901 902 if (!dev->is_physfn) 903 return -EINVAL; 904 905 /* 906 * "offset" is in VFs. The M64 windows are sized so that when they 907 * are segmented, each segment is the same size as the IOV BAR. 908 * Each segment is in a separate PE, and the high order bits of the 909 * address are the PE number. Therefore, each VF's BAR is in a 910 * separate PE, and changing the IOV BAR start address changes the 911 * range of PEs the VFs are in. 912 */ 913 num_vfs = pdn->num_vfs; 914 for (i = 0; i < PCI_SRIOV_NUM_BARS; i++) { 915 res = &dev->resource[i + PCI_IOV_RESOURCES]; 916 if (!res->flags || !res->parent) 917 continue; 918 919 /* 920 * The actual IOV BAR range is determined by the start address 921 * and the actual size for num_vfs VFs BAR. This check is to 922 * make sure that after shifting, the range will not overlap 923 * with another device. 924 */ 925 size = pci_iov_resource_size(dev, i + PCI_IOV_RESOURCES); 926 res2.flags = res->flags; 927 res2.start = res->start + (size * offset); 928 res2.end = res2.start + (size * num_vfs) - 1; 929 930 if (res2.end > res->end) { 931 dev_err(&dev->dev, "VF BAR%d: %pR would extend past %pR (trying to enable %d VFs shifted by %d)\n", 932 i, &res2, res, num_vfs, offset); 933 return -EBUSY; 934 } 935 } 936 937 /* 938 * After doing so, there would be a "hole" in the /proc/iomem when 939 * offset is a positive value. It looks like the device return some 940 * mmio back to the system, which actually no one could use it. 941 */ 942 for (i = 0; i < PCI_SRIOV_NUM_BARS; i++) { 943 res = &dev->resource[i + PCI_IOV_RESOURCES]; 944 if (!res->flags || !res->parent) 945 continue; 946 947 size = pci_iov_resource_size(dev, i + PCI_IOV_RESOURCES); 948 res2 = *res; 949 res->start += size * offset; 950 951 dev_info(&dev->dev, "VF BAR%d: %pR shifted to %pR (%sabling %d VFs shifted by %d)\n", 952 i, &res2, res, (offset > 0) ? "En" : "Dis", 953 num_vfs, offset); 954 pci_update_resource(dev, i + PCI_IOV_RESOURCES); 955 } 956 return 0; 957 } 958 #endif /* CONFIG_PCI_IOV */ 959 960 static struct pnv_ioda_pe *pnv_ioda_setup_dev_PE(struct pci_dev *dev) 961 { 962 struct pci_controller *hose = pci_bus_to_host(dev->bus); 963 struct pnv_phb *phb = hose->private_data; 964 struct pci_dn *pdn = pci_get_pdn(dev); 965 struct pnv_ioda_pe *pe; 966 unsigned int pe_num; 967 968 if (!pdn) { 969 pr_err("%s: Device tree node not associated properly\n", 970 pci_name(dev)); 971 return NULL; 972 } 973 if (pdn->pe_number != IODA_INVALID_PE) 974 return NULL; 975 976 pe_num = pnv_ioda_alloc_pe(phb); 977 if (pe_num == IODA_INVALID_PE) { 978 pr_warning("%s: Not enough PE# available, disabling device\n", 979 pci_name(dev)); 980 return NULL; 981 } 982 983 /* NOTE: We get only one ref to the pci_dev for the pdn, not for the 984 * pointer in the PE data structure, both should be destroyed at the 985 * same time. However, this needs to be looked at more closely again 986 * once we actually start removing things (Hotplug, SR-IOV, ...) 987 * 988 * At some point we want to remove the PDN completely anyways 989 */ 990 pe = &phb->ioda.pe_array[pe_num]; 991 pci_dev_get(dev); 992 pdn->pcidev = dev; 993 pdn->pe_number = pe_num; 994 pe->flags = PNV_IODA_PE_DEV; 995 pe->pdev = dev; 996 pe->pbus = NULL; 997 pe->mve_number = -1; 998 pe->rid = dev->bus->number << 8 | pdn->devfn; 999 1000 pe_info(pe, "Associated device to PE\n"); 1001 1002 if (pnv_ioda_configure_pe(phb, pe)) { 1003 /* XXX What do we do here ? */ 1004 if (pe_num) 1005 pnv_ioda_free_pe(phb, pe_num); 1006 pdn->pe_number = IODA_INVALID_PE; 1007 pe->pdev = NULL; 1008 pci_dev_put(dev); 1009 return NULL; 1010 } 1011 1012 return pe; 1013 } 1014 1015 static void pnv_ioda_setup_same_PE(struct pci_bus *bus, struct pnv_ioda_pe *pe) 1016 { 1017 struct pci_dev *dev; 1018 1019 list_for_each_entry(dev, &bus->devices, bus_list) { 1020 struct pci_dn *pdn = pci_get_pdn(dev); 1021 1022 if (pdn == NULL) { 1023 pr_warn("%s: No device node associated with device !\n", 1024 pci_name(dev)); 1025 continue; 1026 } 1027 pdn->pcidev = dev; 1028 pdn->pe_number = pe->pe_number; 1029 if ((pe->flags & PNV_IODA_PE_BUS_ALL) && dev->subordinate) 1030 pnv_ioda_setup_same_PE(dev->subordinate, pe); 1031 } 1032 } 1033 1034 /* 1035 * There're 2 types of PCI bus sensitive PEs: One that is compromised of 1036 * single PCI bus. Another one that contains the primary PCI bus and its 1037 * subordinate PCI devices and buses. The second type of PE is normally 1038 * orgiriated by PCIe-to-PCI bridge or PLX switch downstream ports. 1039 */ 1040 static void pnv_ioda_setup_bus_PE(struct pci_bus *bus, bool all) 1041 { 1042 struct pci_controller *hose = pci_bus_to_host(bus); 1043 struct pnv_phb *phb = hose->private_data; 1044 struct pnv_ioda_pe *pe; 1045 unsigned int pe_num = IODA_INVALID_PE; 1046 1047 /* Check if PE is determined by M64 */ 1048 if (phb->pick_m64_pe) 1049 pe_num = phb->pick_m64_pe(bus, all); 1050 1051 /* The PE number isn't pinned by M64 */ 1052 if (pe_num == IODA_INVALID_PE) 1053 pe_num = pnv_ioda_alloc_pe(phb); 1054 1055 if (pe_num == IODA_INVALID_PE) { 1056 pr_warning("%s: Not enough PE# available for PCI bus %04x:%02x\n", 1057 __func__, pci_domain_nr(bus), bus->number); 1058 return; 1059 } 1060 1061 pe = &phb->ioda.pe_array[pe_num]; 1062 pe->flags |= (all ? PNV_IODA_PE_BUS_ALL : PNV_IODA_PE_BUS); 1063 pe->pbus = bus; 1064 pe->pdev = NULL; 1065 pe->mve_number = -1; 1066 pe->rid = bus->busn_res.start << 8; 1067 1068 if (all) 1069 pe_info(pe, "Secondary bus %d..%d associated with PE#%d\n", 1070 bus->busn_res.start, bus->busn_res.end, pe_num); 1071 else 1072 pe_info(pe, "Secondary bus %d associated with PE#%d\n", 1073 bus->busn_res.start, pe_num); 1074 1075 if (pnv_ioda_configure_pe(phb, pe)) { 1076 /* XXX What do we do here ? */ 1077 if (pe_num) 1078 pnv_ioda_free_pe(phb, pe_num); 1079 pe->pbus = NULL; 1080 return; 1081 } 1082 1083 /* Associate it with all child devices */ 1084 pnv_ioda_setup_same_PE(bus, pe); 1085 1086 /* Put PE to the list */ 1087 list_add_tail(&pe->list, &phb->ioda.pe_list); 1088 } 1089 1090 static struct pnv_ioda_pe *pnv_ioda_setup_npu_PE(struct pci_dev *npu_pdev) 1091 { 1092 int pe_num, found_pe = false, rc; 1093 long rid; 1094 struct pnv_ioda_pe *pe; 1095 struct pci_dev *gpu_pdev; 1096 struct pci_dn *npu_pdn; 1097 struct pci_controller *hose = pci_bus_to_host(npu_pdev->bus); 1098 struct pnv_phb *phb = hose->private_data; 1099 1100 /* 1101 * Due to a hardware errata PE#0 on the NPU is reserved for 1102 * error handling. This means we only have three PEs remaining 1103 * which need to be assigned to four links, implying some 1104 * links must share PEs. 1105 * 1106 * To achieve this we assign PEs such that NPUs linking the 1107 * same GPU get assigned the same PE. 1108 */ 1109 gpu_pdev = pnv_pci_get_gpu_dev(npu_pdev); 1110 for (pe_num = 0; pe_num < phb->ioda.total_pe_num; pe_num++) { 1111 pe = &phb->ioda.pe_array[pe_num]; 1112 if (!pe->pdev) 1113 continue; 1114 1115 if (pnv_pci_get_gpu_dev(pe->pdev) == gpu_pdev) { 1116 /* 1117 * This device has the same peer GPU so should 1118 * be assigned the same PE as the existing 1119 * peer NPU. 1120 */ 1121 dev_info(&npu_pdev->dev, 1122 "Associating to existing PE %d\n", pe_num); 1123 pci_dev_get(npu_pdev); 1124 npu_pdn = pci_get_pdn(npu_pdev); 1125 rid = npu_pdev->bus->number << 8 | npu_pdn->devfn; 1126 npu_pdn->pcidev = npu_pdev; 1127 npu_pdn->pe_number = pe_num; 1128 phb->ioda.pe_rmap[rid] = pe->pe_number; 1129 1130 /* Map the PE to this link */ 1131 rc = opal_pci_set_pe(phb->opal_id, pe_num, rid, 1132 OpalPciBusAll, 1133 OPAL_COMPARE_RID_DEVICE_NUMBER, 1134 OPAL_COMPARE_RID_FUNCTION_NUMBER, 1135 OPAL_MAP_PE); 1136 WARN_ON(rc != OPAL_SUCCESS); 1137 found_pe = true; 1138 break; 1139 } 1140 } 1141 1142 if (!found_pe) 1143 /* 1144 * Could not find an existing PE so allocate a new 1145 * one. 1146 */ 1147 return pnv_ioda_setup_dev_PE(npu_pdev); 1148 else 1149 return pe; 1150 } 1151 1152 static void pnv_ioda_setup_npu_PEs(struct pci_bus *bus) 1153 { 1154 struct pci_dev *pdev; 1155 1156 list_for_each_entry(pdev, &bus->devices, bus_list) 1157 pnv_ioda_setup_npu_PE(pdev); 1158 } 1159 1160 static void pnv_ioda_setup_PEs(struct pci_bus *bus) 1161 { 1162 struct pci_dev *dev; 1163 1164 pnv_ioda_setup_bus_PE(bus, false); 1165 1166 list_for_each_entry(dev, &bus->devices, bus_list) { 1167 if (dev->subordinate) { 1168 if (pci_pcie_type(dev) == PCI_EXP_TYPE_PCI_BRIDGE) 1169 pnv_ioda_setup_bus_PE(dev->subordinate, true); 1170 else 1171 pnv_ioda_setup_PEs(dev->subordinate); 1172 } 1173 } 1174 } 1175 1176 /* 1177 * Configure PEs so that the downstream PCI buses and devices 1178 * could have their associated PE#. Unfortunately, we didn't 1179 * figure out the way to identify the PLX bridge yet. So we 1180 * simply put the PCI bus and the subordinate behind the root 1181 * port to PE# here. The game rule here is expected to be changed 1182 * as soon as we can detected PLX bridge correctly. 1183 */ 1184 static void pnv_pci_ioda_setup_PEs(void) 1185 { 1186 struct pci_controller *hose, *tmp; 1187 struct pnv_phb *phb; 1188 1189 list_for_each_entry_safe(hose, tmp, &hose_list, list_node) { 1190 phb = hose->private_data; 1191 1192 /* M64 layout might affect PE allocation */ 1193 if (phb->reserve_m64_pe) 1194 phb->reserve_m64_pe(hose->bus, NULL, true); 1195 1196 /* 1197 * On NPU PHB, we expect separate PEs for individual PCI 1198 * functions. PCI bus dependent PEs are required for the 1199 * remaining types of PHBs. 1200 */ 1201 if (phb->type == PNV_PHB_NPU) { 1202 /* PE#0 is needed for error reporting */ 1203 pnv_ioda_reserve_pe(phb, 0); 1204 pnv_ioda_setup_npu_PEs(hose->bus); 1205 } else 1206 pnv_ioda_setup_PEs(hose->bus); 1207 } 1208 } 1209 1210 #ifdef CONFIG_PCI_IOV 1211 static int pnv_pci_vf_release_m64(struct pci_dev *pdev, u16 num_vfs) 1212 { 1213 struct pci_bus *bus; 1214 struct pci_controller *hose; 1215 struct pnv_phb *phb; 1216 struct pci_dn *pdn; 1217 int i, j; 1218 int m64_bars; 1219 1220 bus = pdev->bus; 1221 hose = pci_bus_to_host(bus); 1222 phb = hose->private_data; 1223 pdn = pci_get_pdn(pdev); 1224 1225 if (pdn->m64_single_mode) 1226 m64_bars = num_vfs; 1227 else 1228 m64_bars = 1; 1229 1230 for (i = 0; i < PCI_SRIOV_NUM_BARS; i++) 1231 for (j = 0; j < m64_bars; j++) { 1232 if (pdn->m64_map[j][i] == IODA_INVALID_M64) 1233 continue; 1234 opal_pci_phb_mmio_enable(phb->opal_id, 1235 OPAL_M64_WINDOW_TYPE, pdn->m64_map[j][i], 0); 1236 clear_bit(pdn->m64_map[j][i], &phb->ioda.m64_bar_alloc); 1237 pdn->m64_map[j][i] = IODA_INVALID_M64; 1238 } 1239 1240 kfree(pdn->m64_map); 1241 return 0; 1242 } 1243 1244 static int pnv_pci_vf_assign_m64(struct pci_dev *pdev, u16 num_vfs) 1245 { 1246 struct pci_bus *bus; 1247 struct pci_controller *hose; 1248 struct pnv_phb *phb; 1249 struct pci_dn *pdn; 1250 unsigned int win; 1251 struct resource *res; 1252 int i, j; 1253 int64_t rc; 1254 int total_vfs; 1255 resource_size_t size, start; 1256 int pe_num; 1257 int m64_bars; 1258 1259 bus = pdev->bus; 1260 hose = pci_bus_to_host(bus); 1261 phb = hose->private_data; 1262 pdn = pci_get_pdn(pdev); 1263 total_vfs = pci_sriov_get_totalvfs(pdev); 1264 1265 if (pdn->m64_single_mode) 1266 m64_bars = num_vfs; 1267 else 1268 m64_bars = 1; 1269 1270 pdn->m64_map = kmalloc(sizeof(*pdn->m64_map) * m64_bars, GFP_KERNEL); 1271 if (!pdn->m64_map) 1272 return -ENOMEM; 1273 /* Initialize the m64_map to IODA_INVALID_M64 */ 1274 for (i = 0; i < m64_bars ; i++) 1275 for (j = 0; j < PCI_SRIOV_NUM_BARS; j++) 1276 pdn->m64_map[i][j] = IODA_INVALID_M64; 1277 1278 1279 for (i = 0; i < PCI_SRIOV_NUM_BARS; i++) { 1280 res = &pdev->resource[i + PCI_IOV_RESOURCES]; 1281 if (!res->flags || !res->parent) 1282 continue; 1283 1284 for (j = 0; j < m64_bars; j++) { 1285 do { 1286 win = find_next_zero_bit(&phb->ioda.m64_bar_alloc, 1287 phb->ioda.m64_bar_idx + 1, 0); 1288 1289 if (win >= phb->ioda.m64_bar_idx + 1) 1290 goto m64_failed; 1291 } while (test_and_set_bit(win, &phb->ioda.m64_bar_alloc)); 1292 1293 pdn->m64_map[j][i] = win; 1294 1295 if (pdn->m64_single_mode) { 1296 size = pci_iov_resource_size(pdev, 1297 PCI_IOV_RESOURCES + i); 1298 start = res->start + size * j; 1299 } else { 1300 size = resource_size(res); 1301 start = res->start; 1302 } 1303 1304 /* Map the M64 here */ 1305 if (pdn->m64_single_mode) { 1306 pe_num = pdn->pe_num_map[j]; 1307 rc = opal_pci_map_pe_mmio_window(phb->opal_id, 1308 pe_num, OPAL_M64_WINDOW_TYPE, 1309 pdn->m64_map[j][i], 0); 1310 } 1311 1312 rc = opal_pci_set_phb_mem_window(phb->opal_id, 1313 OPAL_M64_WINDOW_TYPE, 1314 pdn->m64_map[j][i], 1315 start, 1316 0, /* unused */ 1317 size); 1318 1319 1320 if (rc != OPAL_SUCCESS) { 1321 dev_err(&pdev->dev, "Failed to map M64 window #%d: %lld\n", 1322 win, rc); 1323 goto m64_failed; 1324 } 1325 1326 if (pdn->m64_single_mode) 1327 rc = opal_pci_phb_mmio_enable(phb->opal_id, 1328 OPAL_M64_WINDOW_TYPE, pdn->m64_map[j][i], 2); 1329 else 1330 rc = opal_pci_phb_mmio_enable(phb->opal_id, 1331 OPAL_M64_WINDOW_TYPE, pdn->m64_map[j][i], 1); 1332 1333 if (rc != OPAL_SUCCESS) { 1334 dev_err(&pdev->dev, "Failed to enable M64 window #%d: %llx\n", 1335 win, rc); 1336 goto m64_failed; 1337 } 1338 } 1339 } 1340 return 0; 1341 1342 m64_failed: 1343 pnv_pci_vf_release_m64(pdev, num_vfs); 1344 return -EBUSY; 1345 } 1346 1347 static long pnv_pci_ioda2_unset_window(struct iommu_table_group *table_group, 1348 int num); 1349 static void pnv_pci_ioda2_set_bypass(struct pnv_ioda_pe *pe, bool enable); 1350 1351 static void pnv_pci_ioda2_release_dma_pe(struct pci_dev *dev, struct pnv_ioda_pe *pe) 1352 { 1353 struct iommu_table *tbl; 1354 int64_t rc; 1355 1356 tbl = pe->table_group.tables[0]; 1357 rc = pnv_pci_ioda2_unset_window(&pe->table_group, 0); 1358 if (rc) 1359 pe_warn(pe, "OPAL error %ld release DMA window\n", rc); 1360 1361 pnv_pci_ioda2_set_bypass(pe, false); 1362 if (pe->table_group.group) { 1363 iommu_group_put(pe->table_group.group); 1364 BUG_ON(pe->table_group.group); 1365 } 1366 pnv_pci_ioda2_table_free_pages(tbl); 1367 iommu_free_table(tbl, of_node_full_name(dev->dev.of_node)); 1368 } 1369 1370 static void pnv_ioda_release_vf_PE(struct pci_dev *pdev) 1371 { 1372 struct pci_bus *bus; 1373 struct pci_controller *hose; 1374 struct pnv_phb *phb; 1375 struct pnv_ioda_pe *pe, *pe_n; 1376 struct pci_dn *pdn; 1377 1378 bus = pdev->bus; 1379 hose = pci_bus_to_host(bus); 1380 phb = hose->private_data; 1381 pdn = pci_get_pdn(pdev); 1382 1383 if (!pdev->is_physfn) 1384 return; 1385 1386 list_for_each_entry_safe(pe, pe_n, &phb->ioda.pe_list, list) { 1387 if (pe->parent_dev != pdev) 1388 continue; 1389 1390 pnv_pci_ioda2_release_dma_pe(pdev, pe); 1391 1392 /* Remove from list */ 1393 mutex_lock(&phb->ioda.pe_list_mutex); 1394 list_del(&pe->list); 1395 mutex_unlock(&phb->ioda.pe_list_mutex); 1396 1397 pnv_ioda_deconfigure_pe(phb, pe); 1398 1399 pnv_ioda_free_pe(phb, pe->pe_number); 1400 } 1401 } 1402 1403 void pnv_pci_sriov_disable(struct pci_dev *pdev) 1404 { 1405 struct pci_bus *bus; 1406 struct pci_controller *hose; 1407 struct pnv_phb *phb; 1408 struct pci_dn *pdn; 1409 struct pci_sriov *iov; 1410 u16 num_vfs, i; 1411 1412 bus = pdev->bus; 1413 hose = pci_bus_to_host(bus); 1414 phb = hose->private_data; 1415 pdn = pci_get_pdn(pdev); 1416 iov = pdev->sriov; 1417 num_vfs = pdn->num_vfs; 1418 1419 /* Release VF PEs */ 1420 pnv_ioda_release_vf_PE(pdev); 1421 1422 if (phb->type == PNV_PHB_IODA2) { 1423 if (!pdn->m64_single_mode) 1424 pnv_pci_vf_resource_shift(pdev, -*pdn->pe_num_map); 1425 1426 /* Release M64 windows */ 1427 pnv_pci_vf_release_m64(pdev, num_vfs); 1428 1429 /* Release PE numbers */ 1430 if (pdn->m64_single_mode) { 1431 for (i = 0; i < num_vfs; i++) { 1432 if (pdn->pe_num_map[i] != IODA_INVALID_PE) 1433 pnv_ioda_free_pe(phb, pdn->pe_num_map[i]); 1434 } 1435 } else 1436 bitmap_clear(phb->ioda.pe_alloc, *pdn->pe_num_map, num_vfs); 1437 /* Releasing pe_num_map */ 1438 kfree(pdn->pe_num_map); 1439 } 1440 } 1441 1442 static void pnv_pci_ioda2_setup_dma_pe(struct pnv_phb *phb, 1443 struct pnv_ioda_pe *pe); 1444 static void pnv_ioda_setup_vf_PE(struct pci_dev *pdev, u16 num_vfs) 1445 { 1446 struct pci_bus *bus; 1447 struct pci_controller *hose; 1448 struct pnv_phb *phb; 1449 struct pnv_ioda_pe *pe; 1450 int pe_num; 1451 u16 vf_index; 1452 struct pci_dn *pdn; 1453 1454 bus = pdev->bus; 1455 hose = pci_bus_to_host(bus); 1456 phb = hose->private_data; 1457 pdn = pci_get_pdn(pdev); 1458 1459 if (!pdev->is_physfn) 1460 return; 1461 1462 /* Reserve PE for each VF */ 1463 for (vf_index = 0; vf_index < num_vfs; vf_index++) { 1464 if (pdn->m64_single_mode) 1465 pe_num = pdn->pe_num_map[vf_index]; 1466 else 1467 pe_num = *pdn->pe_num_map + vf_index; 1468 1469 pe = &phb->ioda.pe_array[pe_num]; 1470 pe->pe_number = pe_num; 1471 pe->phb = phb; 1472 pe->flags = PNV_IODA_PE_VF; 1473 pe->pbus = NULL; 1474 pe->parent_dev = pdev; 1475 pe->mve_number = -1; 1476 pe->rid = (pci_iov_virtfn_bus(pdev, vf_index) << 8) | 1477 pci_iov_virtfn_devfn(pdev, vf_index); 1478 1479 pe_info(pe, "VF %04d:%02d:%02d.%d associated with PE#%d\n", 1480 hose->global_number, pdev->bus->number, 1481 PCI_SLOT(pci_iov_virtfn_devfn(pdev, vf_index)), 1482 PCI_FUNC(pci_iov_virtfn_devfn(pdev, vf_index)), pe_num); 1483 1484 if (pnv_ioda_configure_pe(phb, pe)) { 1485 /* XXX What do we do here ? */ 1486 if (pe_num) 1487 pnv_ioda_free_pe(phb, pe_num); 1488 pe->pdev = NULL; 1489 continue; 1490 } 1491 1492 /* Put PE to the list */ 1493 mutex_lock(&phb->ioda.pe_list_mutex); 1494 list_add_tail(&pe->list, &phb->ioda.pe_list); 1495 mutex_unlock(&phb->ioda.pe_list_mutex); 1496 1497 pnv_pci_ioda2_setup_dma_pe(phb, pe); 1498 } 1499 } 1500 1501 int pnv_pci_sriov_enable(struct pci_dev *pdev, u16 num_vfs) 1502 { 1503 struct pci_bus *bus; 1504 struct pci_controller *hose; 1505 struct pnv_phb *phb; 1506 struct pci_dn *pdn; 1507 int ret; 1508 u16 i; 1509 1510 bus = pdev->bus; 1511 hose = pci_bus_to_host(bus); 1512 phb = hose->private_data; 1513 pdn = pci_get_pdn(pdev); 1514 1515 if (phb->type == PNV_PHB_IODA2) { 1516 if (!pdn->vfs_expanded) { 1517 dev_info(&pdev->dev, "don't support this SRIOV device" 1518 " with non 64bit-prefetchable IOV BAR\n"); 1519 return -ENOSPC; 1520 } 1521 1522 /* 1523 * When M64 BARs functions in Single PE mode, the number of VFs 1524 * could be enabled must be less than the number of M64 BARs. 1525 */ 1526 if (pdn->m64_single_mode && num_vfs > phb->ioda.m64_bar_idx) { 1527 dev_info(&pdev->dev, "Not enough M64 BAR for VFs\n"); 1528 return -EBUSY; 1529 } 1530 1531 /* Allocating pe_num_map */ 1532 if (pdn->m64_single_mode) 1533 pdn->pe_num_map = kmalloc(sizeof(*pdn->pe_num_map) * num_vfs, 1534 GFP_KERNEL); 1535 else 1536 pdn->pe_num_map = kmalloc(sizeof(*pdn->pe_num_map), GFP_KERNEL); 1537 1538 if (!pdn->pe_num_map) 1539 return -ENOMEM; 1540 1541 if (pdn->m64_single_mode) 1542 for (i = 0; i < num_vfs; i++) 1543 pdn->pe_num_map[i] = IODA_INVALID_PE; 1544 1545 /* Calculate available PE for required VFs */ 1546 if (pdn->m64_single_mode) { 1547 for (i = 0; i < num_vfs; i++) { 1548 pdn->pe_num_map[i] = pnv_ioda_alloc_pe(phb); 1549 if (pdn->pe_num_map[i] == IODA_INVALID_PE) { 1550 ret = -EBUSY; 1551 goto m64_failed; 1552 } 1553 } 1554 } else { 1555 mutex_lock(&phb->ioda.pe_alloc_mutex); 1556 *pdn->pe_num_map = bitmap_find_next_zero_area( 1557 phb->ioda.pe_alloc, phb->ioda.total_pe_num, 1558 0, num_vfs, 0); 1559 if (*pdn->pe_num_map >= phb->ioda.total_pe_num) { 1560 mutex_unlock(&phb->ioda.pe_alloc_mutex); 1561 dev_info(&pdev->dev, "Failed to enable VF%d\n", num_vfs); 1562 kfree(pdn->pe_num_map); 1563 return -EBUSY; 1564 } 1565 bitmap_set(phb->ioda.pe_alloc, *pdn->pe_num_map, num_vfs); 1566 mutex_unlock(&phb->ioda.pe_alloc_mutex); 1567 } 1568 pdn->num_vfs = num_vfs; 1569 1570 /* Assign M64 window accordingly */ 1571 ret = pnv_pci_vf_assign_m64(pdev, num_vfs); 1572 if (ret) { 1573 dev_info(&pdev->dev, "Not enough M64 window resources\n"); 1574 goto m64_failed; 1575 } 1576 1577 /* 1578 * When using one M64 BAR to map one IOV BAR, we need to shift 1579 * the IOV BAR according to the PE# allocated to the VFs. 1580 * Otherwise, the PE# for the VF will conflict with others. 1581 */ 1582 if (!pdn->m64_single_mode) { 1583 ret = pnv_pci_vf_resource_shift(pdev, *pdn->pe_num_map); 1584 if (ret) 1585 goto m64_failed; 1586 } 1587 } 1588 1589 /* Setup VF PEs */ 1590 pnv_ioda_setup_vf_PE(pdev, num_vfs); 1591 1592 return 0; 1593 1594 m64_failed: 1595 if (pdn->m64_single_mode) { 1596 for (i = 0; i < num_vfs; i++) { 1597 if (pdn->pe_num_map[i] != IODA_INVALID_PE) 1598 pnv_ioda_free_pe(phb, pdn->pe_num_map[i]); 1599 } 1600 } else 1601 bitmap_clear(phb->ioda.pe_alloc, *pdn->pe_num_map, num_vfs); 1602 1603 /* Releasing pe_num_map */ 1604 kfree(pdn->pe_num_map); 1605 1606 return ret; 1607 } 1608 1609 int pcibios_sriov_disable(struct pci_dev *pdev) 1610 { 1611 pnv_pci_sriov_disable(pdev); 1612 1613 /* Release PCI data */ 1614 remove_dev_pci_data(pdev); 1615 return 0; 1616 } 1617 1618 int pcibios_sriov_enable(struct pci_dev *pdev, u16 num_vfs) 1619 { 1620 /* Allocate PCI data */ 1621 add_dev_pci_data(pdev); 1622 1623 return pnv_pci_sriov_enable(pdev, num_vfs); 1624 } 1625 #endif /* CONFIG_PCI_IOV */ 1626 1627 static void pnv_pci_ioda_dma_dev_setup(struct pnv_phb *phb, struct pci_dev *pdev) 1628 { 1629 struct pci_dn *pdn = pci_get_pdn(pdev); 1630 struct pnv_ioda_pe *pe; 1631 1632 /* 1633 * The function can be called while the PE# 1634 * hasn't been assigned. Do nothing for the 1635 * case. 1636 */ 1637 if (!pdn || pdn->pe_number == IODA_INVALID_PE) 1638 return; 1639 1640 pe = &phb->ioda.pe_array[pdn->pe_number]; 1641 WARN_ON(get_dma_ops(&pdev->dev) != &dma_iommu_ops); 1642 set_dma_offset(&pdev->dev, pe->tce_bypass_base); 1643 set_iommu_table_base(&pdev->dev, pe->table_group.tables[0]); 1644 /* 1645 * Note: iommu_add_device() will fail here as 1646 * for physical PE: the device is already added by now; 1647 * for virtual PE: sysfs entries are not ready yet and 1648 * tce_iommu_bus_notifier will add the device to a group later. 1649 */ 1650 } 1651 1652 static int pnv_pci_ioda_dma_set_mask(struct pci_dev *pdev, u64 dma_mask) 1653 { 1654 struct pci_controller *hose = pci_bus_to_host(pdev->bus); 1655 struct pnv_phb *phb = hose->private_data; 1656 struct pci_dn *pdn = pci_get_pdn(pdev); 1657 struct pnv_ioda_pe *pe; 1658 uint64_t top; 1659 bool bypass = false; 1660 struct pci_dev *linked_npu_dev; 1661 int i; 1662 1663 if (WARN_ON(!pdn || pdn->pe_number == IODA_INVALID_PE)) 1664 return -ENODEV;; 1665 1666 pe = &phb->ioda.pe_array[pdn->pe_number]; 1667 if (pe->tce_bypass_enabled) { 1668 top = pe->tce_bypass_base + memblock_end_of_DRAM() - 1; 1669 bypass = (dma_mask >= top); 1670 } 1671 1672 if (bypass) { 1673 dev_info(&pdev->dev, "Using 64-bit DMA iommu bypass\n"); 1674 set_dma_ops(&pdev->dev, &dma_direct_ops); 1675 } else { 1676 dev_info(&pdev->dev, "Using 32-bit DMA via iommu\n"); 1677 set_dma_ops(&pdev->dev, &dma_iommu_ops); 1678 } 1679 *pdev->dev.dma_mask = dma_mask; 1680 1681 /* Update peer npu devices */ 1682 if (pe->flags & PNV_IODA_PE_PEER) 1683 for (i = 0; i < PNV_IODA_MAX_PEER_PES; i++) { 1684 if (!pe->peers[i]) 1685 continue; 1686 1687 linked_npu_dev = pe->peers[i]->pdev; 1688 if (dma_get_mask(&linked_npu_dev->dev) != dma_mask) 1689 dma_set_mask(&linked_npu_dev->dev, dma_mask); 1690 } 1691 1692 return 0; 1693 } 1694 1695 static u64 pnv_pci_ioda_dma_get_required_mask(struct pci_dev *pdev) 1696 { 1697 struct pci_controller *hose = pci_bus_to_host(pdev->bus); 1698 struct pnv_phb *phb = hose->private_data; 1699 struct pci_dn *pdn = pci_get_pdn(pdev); 1700 struct pnv_ioda_pe *pe; 1701 u64 end, mask; 1702 1703 if (WARN_ON(!pdn || pdn->pe_number == IODA_INVALID_PE)) 1704 return 0; 1705 1706 pe = &phb->ioda.pe_array[pdn->pe_number]; 1707 if (!pe->tce_bypass_enabled) 1708 return __dma_get_required_mask(&pdev->dev); 1709 1710 1711 end = pe->tce_bypass_base + memblock_end_of_DRAM(); 1712 mask = 1ULL << (fls64(end) - 1); 1713 mask += mask - 1; 1714 1715 return mask; 1716 } 1717 1718 static void pnv_ioda_setup_bus_dma(struct pnv_ioda_pe *pe, 1719 struct pci_bus *bus) 1720 { 1721 struct pci_dev *dev; 1722 1723 list_for_each_entry(dev, &bus->devices, bus_list) { 1724 set_iommu_table_base(&dev->dev, pe->table_group.tables[0]); 1725 set_dma_offset(&dev->dev, pe->tce_bypass_base); 1726 iommu_add_device(&dev->dev); 1727 1728 if ((pe->flags & PNV_IODA_PE_BUS_ALL) && dev->subordinate) 1729 pnv_ioda_setup_bus_dma(pe, dev->subordinate); 1730 } 1731 } 1732 1733 static void pnv_pci_ioda1_tce_invalidate(struct iommu_table *tbl, 1734 unsigned long index, unsigned long npages, bool rm) 1735 { 1736 struct iommu_table_group_link *tgl = list_first_entry_or_null( 1737 &tbl->it_group_list, struct iommu_table_group_link, 1738 next); 1739 struct pnv_ioda_pe *pe = container_of(tgl->table_group, 1740 struct pnv_ioda_pe, table_group); 1741 __be64 __iomem *invalidate = rm ? 1742 (__be64 __iomem *)pe->phb->ioda.tce_inval_reg_phys : 1743 pe->phb->ioda.tce_inval_reg; 1744 unsigned long start, end, inc; 1745 const unsigned shift = tbl->it_page_shift; 1746 1747 start = __pa(((__be64 *)tbl->it_base) + index - tbl->it_offset); 1748 end = __pa(((__be64 *)tbl->it_base) + index - tbl->it_offset + 1749 npages - 1); 1750 1751 /* BML uses this case for p6/p7/galaxy2: Shift addr and put in node */ 1752 if (tbl->it_busno) { 1753 start <<= shift; 1754 end <<= shift; 1755 inc = 128ull << shift; 1756 start |= tbl->it_busno; 1757 end |= tbl->it_busno; 1758 } else if (tbl->it_type & TCE_PCI_SWINV_PAIR) { 1759 /* p7ioc-style invalidation, 2 TCEs per write */ 1760 start |= (1ull << 63); 1761 end |= (1ull << 63); 1762 inc = 16; 1763 } else { 1764 /* Default (older HW) */ 1765 inc = 128; 1766 } 1767 1768 end |= inc - 1; /* round up end to be different than start */ 1769 1770 mb(); /* Ensure above stores are visible */ 1771 while (start <= end) { 1772 if (rm) 1773 __raw_rm_writeq(cpu_to_be64(start), invalidate); 1774 else 1775 __raw_writeq(cpu_to_be64(start), invalidate); 1776 start += inc; 1777 } 1778 1779 /* 1780 * The iommu layer will do another mb() for us on build() 1781 * and we don't care on free() 1782 */ 1783 } 1784 1785 static int pnv_ioda1_tce_build(struct iommu_table *tbl, long index, 1786 long npages, unsigned long uaddr, 1787 enum dma_data_direction direction, 1788 struct dma_attrs *attrs) 1789 { 1790 int ret = pnv_tce_build(tbl, index, npages, uaddr, direction, 1791 attrs); 1792 1793 if (!ret && (tbl->it_type & TCE_PCI_SWINV_CREATE)) 1794 pnv_pci_ioda1_tce_invalidate(tbl, index, npages, false); 1795 1796 return ret; 1797 } 1798 1799 #ifdef CONFIG_IOMMU_API 1800 static int pnv_ioda1_tce_xchg(struct iommu_table *tbl, long index, 1801 unsigned long *hpa, enum dma_data_direction *direction) 1802 { 1803 long ret = pnv_tce_xchg(tbl, index, hpa, direction); 1804 1805 if (!ret && (tbl->it_type & 1806 (TCE_PCI_SWINV_CREATE | TCE_PCI_SWINV_FREE))) 1807 pnv_pci_ioda1_tce_invalidate(tbl, index, 1, false); 1808 1809 return ret; 1810 } 1811 #endif 1812 1813 static void pnv_ioda1_tce_free(struct iommu_table *tbl, long index, 1814 long npages) 1815 { 1816 pnv_tce_free(tbl, index, npages); 1817 1818 if (tbl->it_type & TCE_PCI_SWINV_FREE) 1819 pnv_pci_ioda1_tce_invalidate(tbl, index, npages, false); 1820 } 1821 1822 static struct iommu_table_ops pnv_ioda1_iommu_ops = { 1823 .set = pnv_ioda1_tce_build, 1824 #ifdef CONFIG_IOMMU_API 1825 .exchange = pnv_ioda1_tce_xchg, 1826 #endif 1827 .clear = pnv_ioda1_tce_free, 1828 .get = pnv_tce_get, 1829 }; 1830 1831 static inline void pnv_pci_ioda2_tce_invalidate_entire(struct pnv_ioda_pe *pe) 1832 { 1833 /* 01xb - invalidate TCEs that match the specified PE# */ 1834 unsigned long val = (0x4ull << 60) | (pe->pe_number & 0xFF); 1835 struct pnv_phb *phb = pe->phb; 1836 struct pnv_ioda_pe *npe; 1837 int i; 1838 1839 if (!phb->ioda.tce_inval_reg) 1840 return; 1841 1842 mb(); /* Ensure above stores are visible */ 1843 __raw_writeq(cpu_to_be64(val), phb->ioda.tce_inval_reg); 1844 1845 if (pe->flags & PNV_IODA_PE_PEER) 1846 for (i = 0; i < PNV_IODA_MAX_PEER_PES; i++) { 1847 npe = pe->peers[i]; 1848 if (!npe || npe->phb->type != PNV_PHB_NPU) 1849 continue; 1850 1851 pnv_npu_tce_invalidate_entire(npe); 1852 } 1853 } 1854 1855 static void pnv_pci_ioda2_do_tce_invalidate(unsigned pe_number, bool rm, 1856 __be64 __iomem *invalidate, unsigned shift, 1857 unsigned long index, unsigned long npages) 1858 { 1859 unsigned long start, end, inc; 1860 1861 /* We'll invalidate DMA address in PE scope */ 1862 start = 0x2ull << 60; 1863 start |= (pe_number & 0xFF); 1864 end = start; 1865 1866 /* Figure out the start, end and step */ 1867 start |= (index << shift); 1868 end |= ((index + npages - 1) << shift); 1869 inc = (0x1ull << shift); 1870 mb(); 1871 1872 while (start <= end) { 1873 if (rm) 1874 __raw_rm_writeq(cpu_to_be64(start), invalidate); 1875 else 1876 __raw_writeq(cpu_to_be64(start), invalidate); 1877 start += inc; 1878 } 1879 } 1880 1881 static void pnv_pci_ioda2_tce_invalidate(struct iommu_table *tbl, 1882 unsigned long index, unsigned long npages, bool rm) 1883 { 1884 struct iommu_table_group_link *tgl; 1885 1886 list_for_each_entry_rcu(tgl, &tbl->it_group_list, next) { 1887 struct pnv_ioda_pe *npe; 1888 struct pnv_ioda_pe *pe = container_of(tgl->table_group, 1889 struct pnv_ioda_pe, table_group); 1890 __be64 __iomem *invalidate = rm ? 1891 (__be64 __iomem *)pe->phb->ioda.tce_inval_reg_phys : 1892 pe->phb->ioda.tce_inval_reg; 1893 int i; 1894 1895 pnv_pci_ioda2_do_tce_invalidate(pe->pe_number, rm, 1896 invalidate, tbl->it_page_shift, 1897 index, npages); 1898 1899 if (pe->flags & PNV_IODA_PE_PEER) 1900 /* Invalidate PEs using the same TCE table */ 1901 for (i = 0; i < PNV_IODA_MAX_PEER_PES; i++) { 1902 npe = pe->peers[i]; 1903 if (!npe || npe->phb->type != PNV_PHB_NPU) 1904 continue; 1905 1906 pnv_npu_tce_invalidate(npe, tbl, index, 1907 npages, rm); 1908 } 1909 } 1910 } 1911 1912 static int pnv_ioda2_tce_build(struct iommu_table *tbl, long index, 1913 long npages, unsigned long uaddr, 1914 enum dma_data_direction direction, 1915 struct dma_attrs *attrs) 1916 { 1917 int ret = pnv_tce_build(tbl, index, npages, uaddr, direction, 1918 attrs); 1919 1920 if (!ret && (tbl->it_type & TCE_PCI_SWINV_CREATE)) 1921 pnv_pci_ioda2_tce_invalidate(tbl, index, npages, false); 1922 1923 return ret; 1924 } 1925 1926 #ifdef CONFIG_IOMMU_API 1927 static int pnv_ioda2_tce_xchg(struct iommu_table *tbl, long index, 1928 unsigned long *hpa, enum dma_data_direction *direction) 1929 { 1930 long ret = pnv_tce_xchg(tbl, index, hpa, direction); 1931 1932 if (!ret && (tbl->it_type & 1933 (TCE_PCI_SWINV_CREATE | TCE_PCI_SWINV_FREE))) 1934 pnv_pci_ioda2_tce_invalidate(tbl, index, 1, false); 1935 1936 return ret; 1937 } 1938 #endif 1939 1940 static void pnv_ioda2_tce_free(struct iommu_table *tbl, long index, 1941 long npages) 1942 { 1943 pnv_tce_free(tbl, index, npages); 1944 1945 if (tbl->it_type & TCE_PCI_SWINV_FREE) 1946 pnv_pci_ioda2_tce_invalidate(tbl, index, npages, false); 1947 } 1948 1949 static void pnv_ioda2_table_free(struct iommu_table *tbl) 1950 { 1951 pnv_pci_ioda2_table_free_pages(tbl); 1952 iommu_free_table(tbl, "pnv"); 1953 } 1954 1955 static struct iommu_table_ops pnv_ioda2_iommu_ops = { 1956 .set = pnv_ioda2_tce_build, 1957 #ifdef CONFIG_IOMMU_API 1958 .exchange = pnv_ioda2_tce_xchg, 1959 #endif 1960 .clear = pnv_ioda2_tce_free, 1961 .get = pnv_tce_get, 1962 .free = pnv_ioda2_table_free, 1963 }; 1964 1965 static int pnv_pci_ioda_dev_dma_weight(struct pci_dev *dev, void *data) 1966 { 1967 unsigned int *weight = (unsigned int *)data; 1968 1969 /* This is quite simplistic. The "base" weight of a device 1970 * is 10. 0 means no DMA is to be accounted for it. 1971 */ 1972 if (dev->hdr_type != PCI_HEADER_TYPE_NORMAL) 1973 return 0; 1974 1975 if (dev->class == PCI_CLASS_SERIAL_USB_UHCI || 1976 dev->class == PCI_CLASS_SERIAL_USB_OHCI || 1977 dev->class == PCI_CLASS_SERIAL_USB_EHCI) 1978 *weight += 3; 1979 else if ((dev->class >> 8) == PCI_CLASS_STORAGE_RAID) 1980 *weight += 15; 1981 else 1982 *weight += 10; 1983 1984 return 0; 1985 } 1986 1987 static unsigned int pnv_pci_ioda_pe_dma_weight(struct pnv_ioda_pe *pe) 1988 { 1989 unsigned int weight = 0; 1990 1991 /* SRIOV VF has same DMA32 weight as its PF */ 1992 #ifdef CONFIG_PCI_IOV 1993 if ((pe->flags & PNV_IODA_PE_VF) && pe->parent_dev) { 1994 pnv_pci_ioda_dev_dma_weight(pe->parent_dev, &weight); 1995 return weight; 1996 } 1997 #endif 1998 1999 if ((pe->flags & PNV_IODA_PE_DEV) && pe->pdev) { 2000 pnv_pci_ioda_dev_dma_weight(pe->pdev, &weight); 2001 } else if ((pe->flags & PNV_IODA_PE_BUS) && pe->pbus) { 2002 struct pci_dev *pdev; 2003 2004 list_for_each_entry(pdev, &pe->pbus->devices, bus_list) 2005 pnv_pci_ioda_dev_dma_weight(pdev, &weight); 2006 } else if ((pe->flags & PNV_IODA_PE_BUS_ALL) && pe->pbus) { 2007 pci_walk_bus(pe->pbus, pnv_pci_ioda_dev_dma_weight, &weight); 2008 } 2009 2010 return weight; 2011 } 2012 2013 static void pnv_pci_ioda1_setup_dma_pe(struct pnv_phb *phb, 2014 struct pnv_ioda_pe *pe) 2015 { 2016 2017 struct page *tce_mem = NULL; 2018 struct iommu_table *tbl; 2019 unsigned int weight, total_weight = 0; 2020 unsigned int tce32_segsz, base, segs, avail, i; 2021 int64_t rc; 2022 void *addr; 2023 2024 /* XXX FIXME: Handle 64-bit only DMA devices */ 2025 /* XXX FIXME: Provide 64-bit DMA facilities & non-4K TCE tables etc.. */ 2026 /* XXX FIXME: Allocate multi-level tables on PHB3 */ 2027 weight = pnv_pci_ioda_pe_dma_weight(pe); 2028 if (!weight) 2029 return; 2030 2031 pci_walk_bus(phb->hose->bus, pnv_pci_ioda_dev_dma_weight, 2032 &total_weight); 2033 segs = (weight * phb->ioda.dma32_count) / total_weight; 2034 if (!segs) 2035 segs = 1; 2036 2037 /* 2038 * Allocate contiguous DMA32 segments. We begin with the expected 2039 * number of segments. With one more attempt, the number of DMA32 2040 * segments to be allocated is decreased by one until one segment 2041 * is allocated successfully. 2042 */ 2043 do { 2044 for (base = 0; base <= phb->ioda.dma32_count - segs; base++) { 2045 for (avail = 0, i = base; i < base + segs; i++) { 2046 if (phb->ioda.dma32_segmap[i] == 2047 IODA_INVALID_PE) 2048 avail++; 2049 } 2050 2051 if (avail == segs) 2052 goto found; 2053 } 2054 } while (--segs); 2055 2056 if (!segs) { 2057 pe_warn(pe, "No available DMA32 segments\n"); 2058 return; 2059 } 2060 2061 found: 2062 tbl = pnv_pci_table_alloc(phb->hose->node); 2063 iommu_register_group(&pe->table_group, phb->hose->global_number, 2064 pe->pe_number); 2065 pnv_pci_link_table_and_group(phb->hose->node, 0, tbl, &pe->table_group); 2066 2067 /* Grab a 32-bit TCE table */ 2068 pe_info(pe, "DMA weight %d (%d), assigned (%d) %d DMA32 segments\n", 2069 weight, total_weight, base, segs); 2070 pe_info(pe, " Setting up 32-bit TCE table at %08x..%08x\n", 2071 base * PNV_IODA1_DMA32_SEGSIZE, 2072 (base + segs) * PNV_IODA1_DMA32_SEGSIZE - 1); 2073 2074 /* XXX Currently, we allocate one big contiguous table for the 2075 * TCEs. We only really need one chunk per 256M of TCE space 2076 * (ie per segment) but that's an optimization for later, it 2077 * requires some added smarts with our get/put_tce implementation 2078 * 2079 * Each TCE page is 4KB in size and each TCE entry occupies 8 2080 * bytes 2081 */ 2082 tce32_segsz = PNV_IODA1_DMA32_SEGSIZE >> (IOMMU_PAGE_SHIFT_4K - 3); 2083 tce_mem = alloc_pages_node(phb->hose->node, GFP_KERNEL, 2084 get_order(tce32_segsz * segs)); 2085 if (!tce_mem) { 2086 pe_err(pe, " Failed to allocate a 32-bit TCE memory\n"); 2087 goto fail; 2088 } 2089 addr = page_address(tce_mem); 2090 memset(addr, 0, tce32_segsz * segs); 2091 2092 /* Configure HW */ 2093 for (i = 0; i < segs; i++) { 2094 rc = opal_pci_map_pe_dma_window(phb->opal_id, 2095 pe->pe_number, 2096 base + i, 1, 2097 __pa(addr) + tce32_segsz * i, 2098 tce32_segsz, IOMMU_PAGE_SIZE_4K); 2099 if (rc) { 2100 pe_err(pe, " Failed to configure 32-bit TCE table," 2101 " err %ld\n", rc); 2102 goto fail; 2103 } 2104 } 2105 2106 /* Setup DMA32 segment mapping */ 2107 for (i = base; i < base + segs; i++) 2108 phb->ioda.dma32_segmap[i] = pe->pe_number; 2109 2110 /* Setup linux iommu table */ 2111 pnv_pci_setup_iommu_table(tbl, addr, tce32_segsz * segs, 2112 base * PNV_IODA1_DMA32_SEGSIZE, 2113 IOMMU_PAGE_SHIFT_4K); 2114 2115 /* OPAL variant of P7IOC SW invalidated TCEs */ 2116 if (phb->ioda.tce_inval_reg) 2117 tbl->it_type |= (TCE_PCI_SWINV_CREATE | 2118 TCE_PCI_SWINV_FREE | 2119 TCE_PCI_SWINV_PAIR); 2120 2121 tbl->it_ops = &pnv_ioda1_iommu_ops; 2122 pe->table_group.tce32_start = tbl->it_offset << tbl->it_page_shift; 2123 pe->table_group.tce32_size = tbl->it_size << tbl->it_page_shift; 2124 iommu_init_table(tbl, phb->hose->node); 2125 2126 if (pe->flags & PNV_IODA_PE_DEV) { 2127 /* 2128 * Setting table base here only for carrying iommu_group 2129 * further down to let iommu_add_device() do the job. 2130 * pnv_pci_ioda_dma_dev_setup will override it later anyway. 2131 */ 2132 set_iommu_table_base(&pe->pdev->dev, tbl); 2133 iommu_add_device(&pe->pdev->dev); 2134 } else if (pe->flags & (PNV_IODA_PE_BUS | PNV_IODA_PE_BUS_ALL)) 2135 pnv_ioda_setup_bus_dma(pe, pe->pbus); 2136 2137 return; 2138 fail: 2139 /* XXX Failure: Try to fallback to 64-bit only ? */ 2140 if (tce_mem) 2141 __free_pages(tce_mem, get_order(tce32_segsz * segs)); 2142 if (tbl) { 2143 pnv_pci_unlink_table_and_group(tbl, &pe->table_group); 2144 iommu_free_table(tbl, "pnv"); 2145 } 2146 } 2147 2148 static long pnv_pci_ioda2_set_window(struct iommu_table_group *table_group, 2149 int num, struct iommu_table *tbl) 2150 { 2151 struct pnv_ioda_pe *pe = container_of(table_group, struct pnv_ioda_pe, 2152 table_group); 2153 struct pnv_phb *phb = pe->phb; 2154 int64_t rc; 2155 const unsigned long size = tbl->it_indirect_levels ? 2156 tbl->it_level_size : tbl->it_size; 2157 const __u64 start_addr = tbl->it_offset << tbl->it_page_shift; 2158 const __u64 win_size = tbl->it_size << tbl->it_page_shift; 2159 2160 pe_info(pe, "Setting up window#%d %llx..%llx pg=%x\n", num, 2161 start_addr, start_addr + win_size - 1, 2162 IOMMU_PAGE_SIZE(tbl)); 2163 2164 /* 2165 * Map TCE table through TVT. The TVE index is the PE number 2166 * shifted by 1 bit for 32-bits DMA space. 2167 */ 2168 rc = opal_pci_map_pe_dma_window(phb->opal_id, 2169 pe->pe_number, 2170 (pe->pe_number << 1) + num, 2171 tbl->it_indirect_levels + 1, 2172 __pa(tbl->it_base), 2173 size << 3, 2174 IOMMU_PAGE_SIZE(tbl)); 2175 if (rc) { 2176 pe_err(pe, "Failed to configure TCE table, err %ld\n", rc); 2177 return rc; 2178 } 2179 2180 pnv_pci_link_table_and_group(phb->hose->node, num, 2181 tbl, &pe->table_group); 2182 pnv_pci_ioda2_tce_invalidate_entire(pe); 2183 2184 return 0; 2185 } 2186 2187 static void pnv_pci_ioda2_set_bypass(struct pnv_ioda_pe *pe, bool enable) 2188 { 2189 uint16_t window_id = (pe->pe_number << 1 ) + 1; 2190 int64_t rc; 2191 2192 pe_info(pe, "%sabling 64-bit DMA bypass\n", enable ? "En" : "Dis"); 2193 if (enable) { 2194 phys_addr_t top = memblock_end_of_DRAM(); 2195 2196 top = roundup_pow_of_two(top); 2197 rc = opal_pci_map_pe_dma_window_real(pe->phb->opal_id, 2198 pe->pe_number, 2199 window_id, 2200 pe->tce_bypass_base, 2201 top); 2202 } else { 2203 rc = opal_pci_map_pe_dma_window_real(pe->phb->opal_id, 2204 pe->pe_number, 2205 window_id, 2206 pe->tce_bypass_base, 2207 0); 2208 } 2209 if (rc) 2210 pe_err(pe, "OPAL error %lld configuring bypass window\n", rc); 2211 else 2212 pe->tce_bypass_enabled = enable; 2213 } 2214 2215 static long pnv_pci_ioda2_table_alloc_pages(int nid, __u64 bus_offset, 2216 __u32 page_shift, __u64 window_size, __u32 levels, 2217 struct iommu_table *tbl); 2218 2219 static long pnv_pci_ioda2_create_table(struct iommu_table_group *table_group, 2220 int num, __u32 page_shift, __u64 window_size, __u32 levels, 2221 struct iommu_table **ptbl) 2222 { 2223 struct pnv_ioda_pe *pe = container_of(table_group, struct pnv_ioda_pe, 2224 table_group); 2225 int nid = pe->phb->hose->node; 2226 __u64 bus_offset = num ? pe->tce_bypass_base : table_group->tce32_start; 2227 long ret; 2228 struct iommu_table *tbl; 2229 2230 tbl = pnv_pci_table_alloc(nid); 2231 if (!tbl) 2232 return -ENOMEM; 2233 2234 ret = pnv_pci_ioda2_table_alloc_pages(nid, 2235 bus_offset, page_shift, window_size, 2236 levels, tbl); 2237 if (ret) { 2238 iommu_free_table(tbl, "pnv"); 2239 return ret; 2240 } 2241 2242 tbl->it_ops = &pnv_ioda2_iommu_ops; 2243 if (pe->phb->ioda.tce_inval_reg) 2244 tbl->it_type |= (TCE_PCI_SWINV_CREATE | TCE_PCI_SWINV_FREE); 2245 2246 *ptbl = tbl; 2247 2248 return 0; 2249 } 2250 2251 static long pnv_pci_ioda2_setup_default_config(struct pnv_ioda_pe *pe) 2252 { 2253 struct iommu_table *tbl = NULL; 2254 long rc; 2255 2256 /* 2257 * crashkernel= specifies the kdump kernel's maximum memory at 2258 * some offset and there is no guaranteed the result is a power 2259 * of 2, which will cause errors later. 2260 */ 2261 const u64 max_memory = __rounddown_pow_of_two(memory_hotplug_max()); 2262 2263 /* 2264 * In memory constrained environments, e.g. kdump kernel, the 2265 * DMA window can be larger than available memory, which will 2266 * cause errors later. 2267 */ 2268 const u64 window_size = min((u64)pe->table_group.tce32_size, max_memory); 2269 2270 rc = pnv_pci_ioda2_create_table(&pe->table_group, 0, 2271 IOMMU_PAGE_SHIFT_4K, 2272 window_size, 2273 POWERNV_IOMMU_DEFAULT_LEVELS, &tbl); 2274 if (rc) { 2275 pe_err(pe, "Failed to create 32-bit TCE table, err %ld", 2276 rc); 2277 return rc; 2278 } 2279 2280 iommu_init_table(tbl, pe->phb->hose->node); 2281 2282 rc = pnv_pci_ioda2_set_window(&pe->table_group, 0, tbl); 2283 if (rc) { 2284 pe_err(pe, "Failed to configure 32-bit TCE table, err %ld\n", 2285 rc); 2286 pnv_ioda2_table_free(tbl); 2287 return rc; 2288 } 2289 2290 if (!pnv_iommu_bypass_disabled) 2291 pnv_pci_ioda2_set_bypass(pe, true); 2292 2293 /* OPAL variant of PHB3 invalidated TCEs */ 2294 if (pe->phb->ioda.tce_inval_reg) 2295 tbl->it_type |= (TCE_PCI_SWINV_CREATE | TCE_PCI_SWINV_FREE); 2296 2297 /* 2298 * Setting table base here only for carrying iommu_group 2299 * further down to let iommu_add_device() do the job. 2300 * pnv_pci_ioda_dma_dev_setup will override it later anyway. 2301 */ 2302 if (pe->flags & PNV_IODA_PE_DEV) 2303 set_iommu_table_base(&pe->pdev->dev, tbl); 2304 2305 return 0; 2306 } 2307 2308 #if defined(CONFIG_IOMMU_API) || defined(CONFIG_PCI_IOV) 2309 static long pnv_pci_ioda2_unset_window(struct iommu_table_group *table_group, 2310 int num) 2311 { 2312 struct pnv_ioda_pe *pe = container_of(table_group, struct pnv_ioda_pe, 2313 table_group); 2314 struct pnv_phb *phb = pe->phb; 2315 long ret; 2316 2317 pe_info(pe, "Removing DMA window #%d\n", num); 2318 2319 ret = opal_pci_map_pe_dma_window(phb->opal_id, pe->pe_number, 2320 (pe->pe_number << 1) + num, 2321 0/* levels */, 0/* table address */, 2322 0/* table size */, 0/* page size */); 2323 if (ret) 2324 pe_warn(pe, "Unmapping failed, ret = %ld\n", ret); 2325 else 2326 pnv_pci_ioda2_tce_invalidate_entire(pe); 2327 2328 pnv_pci_unlink_table_and_group(table_group->tables[num], table_group); 2329 2330 return ret; 2331 } 2332 #endif 2333 2334 #ifdef CONFIG_IOMMU_API 2335 static unsigned long pnv_pci_ioda2_get_table_size(__u32 page_shift, 2336 __u64 window_size, __u32 levels) 2337 { 2338 unsigned long bytes = 0; 2339 const unsigned window_shift = ilog2(window_size); 2340 unsigned entries_shift = window_shift - page_shift; 2341 unsigned table_shift = entries_shift + 3; 2342 unsigned long tce_table_size = max(0x1000UL, 1UL << table_shift); 2343 unsigned long direct_table_size; 2344 2345 if (!levels || (levels > POWERNV_IOMMU_MAX_LEVELS) || 2346 (window_size > memory_hotplug_max()) || 2347 !is_power_of_2(window_size)) 2348 return 0; 2349 2350 /* Calculate a direct table size from window_size and levels */ 2351 entries_shift = (entries_shift + levels - 1) / levels; 2352 table_shift = entries_shift + 3; 2353 table_shift = max_t(unsigned, table_shift, PAGE_SHIFT); 2354 direct_table_size = 1UL << table_shift; 2355 2356 for ( ; levels; --levels) { 2357 bytes += _ALIGN_UP(tce_table_size, direct_table_size); 2358 2359 tce_table_size /= direct_table_size; 2360 tce_table_size <<= 3; 2361 tce_table_size = _ALIGN_UP(tce_table_size, direct_table_size); 2362 } 2363 2364 return bytes; 2365 } 2366 2367 static void pnv_ioda2_take_ownership(struct iommu_table_group *table_group) 2368 { 2369 struct pnv_ioda_pe *pe = container_of(table_group, struct pnv_ioda_pe, 2370 table_group); 2371 /* Store @tbl as pnv_pci_ioda2_unset_window() resets it */ 2372 struct iommu_table *tbl = pe->table_group.tables[0]; 2373 2374 pnv_pci_ioda2_set_bypass(pe, false); 2375 pnv_pci_ioda2_unset_window(&pe->table_group, 0); 2376 pnv_ioda2_table_free(tbl); 2377 } 2378 2379 static void pnv_ioda2_release_ownership(struct iommu_table_group *table_group) 2380 { 2381 struct pnv_ioda_pe *pe = container_of(table_group, struct pnv_ioda_pe, 2382 table_group); 2383 2384 pnv_pci_ioda2_setup_default_config(pe); 2385 } 2386 2387 static struct iommu_table_group_ops pnv_pci_ioda2_ops = { 2388 .get_table_size = pnv_pci_ioda2_get_table_size, 2389 .create_table = pnv_pci_ioda2_create_table, 2390 .set_window = pnv_pci_ioda2_set_window, 2391 .unset_window = pnv_pci_ioda2_unset_window, 2392 .take_ownership = pnv_ioda2_take_ownership, 2393 .release_ownership = pnv_ioda2_release_ownership, 2394 }; 2395 #endif 2396 2397 static void pnv_pci_ioda_setup_opal_tce_kill(struct pnv_phb *phb) 2398 { 2399 const __be64 *swinvp; 2400 2401 /* OPAL variant of PHB3 invalidated TCEs */ 2402 swinvp = of_get_property(phb->hose->dn, "ibm,opal-tce-kill", NULL); 2403 if (!swinvp) 2404 return; 2405 2406 phb->ioda.tce_inval_reg_phys = be64_to_cpup(swinvp); 2407 phb->ioda.tce_inval_reg = ioremap(phb->ioda.tce_inval_reg_phys, 8); 2408 } 2409 2410 static __be64 *pnv_pci_ioda2_table_do_alloc_pages(int nid, unsigned shift, 2411 unsigned levels, unsigned long limit, 2412 unsigned long *current_offset, unsigned long *total_allocated) 2413 { 2414 struct page *tce_mem = NULL; 2415 __be64 *addr, *tmp; 2416 unsigned order = max_t(unsigned, shift, PAGE_SHIFT) - PAGE_SHIFT; 2417 unsigned long allocated = 1UL << (order + PAGE_SHIFT); 2418 unsigned entries = 1UL << (shift - 3); 2419 long i; 2420 2421 tce_mem = alloc_pages_node(nid, GFP_KERNEL, order); 2422 if (!tce_mem) { 2423 pr_err("Failed to allocate a TCE memory, order=%d\n", order); 2424 return NULL; 2425 } 2426 addr = page_address(tce_mem); 2427 memset(addr, 0, allocated); 2428 *total_allocated += allocated; 2429 2430 --levels; 2431 if (!levels) { 2432 *current_offset += allocated; 2433 return addr; 2434 } 2435 2436 for (i = 0; i < entries; ++i) { 2437 tmp = pnv_pci_ioda2_table_do_alloc_pages(nid, shift, 2438 levels, limit, current_offset, total_allocated); 2439 if (!tmp) 2440 break; 2441 2442 addr[i] = cpu_to_be64(__pa(tmp) | 2443 TCE_PCI_READ | TCE_PCI_WRITE); 2444 2445 if (*current_offset >= limit) 2446 break; 2447 } 2448 2449 return addr; 2450 } 2451 2452 static void pnv_pci_ioda2_table_do_free_pages(__be64 *addr, 2453 unsigned long size, unsigned level); 2454 2455 static long pnv_pci_ioda2_table_alloc_pages(int nid, __u64 bus_offset, 2456 __u32 page_shift, __u64 window_size, __u32 levels, 2457 struct iommu_table *tbl) 2458 { 2459 void *addr; 2460 unsigned long offset = 0, level_shift, total_allocated = 0; 2461 const unsigned window_shift = ilog2(window_size); 2462 unsigned entries_shift = window_shift - page_shift; 2463 unsigned table_shift = max_t(unsigned, entries_shift + 3, PAGE_SHIFT); 2464 const unsigned long tce_table_size = 1UL << table_shift; 2465 2466 if (!levels || (levels > POWERNV_IOMMU_MAX_LEVELS)) 2467 return -EINVAL; 2468 2469 if ((window_size > memory_hotplug_max()) || !is_power_of_2(window_size)) 2470 return -EINVAL; 2471 2472 /* Adjust direct table size from window_size and levels */ 2473 entries_shift = (entries_shift + levels - 1) / levels; 2474 level_shift = entries_shift + 3; 2475 level_shift = max_t(unsigned, level_shift, PAGE_SHIFT); 2476 2477 /* Allocate TCE table */ 2478 addr = pnv_pci_ioda2_table_do_alloc_pages(nid, level_shift, 2479 levels, tce_table_size, &offset, &total_allocated); 2480 2481 /* addr==NULL means that the first level allocation failed */ 2482 if (!addr) 2483 return -ENOMEM; 2484 2485 /* 2486 * First level was allocated but some lower level failed as 2487 * we did not allocate as much as we wanted, 2488 * release partially allocated table. 2489 */ 2490 if (offset < tce_table_size) { 2491 pnv_pci_ioda2_table_do_free_pages(addr, 2492 1ULL << (level_shift - 3), levels - 1); 2493 return -ENOMEM; 2494 } 2495 2496 /* Setup linux iommu table */ 2497 pnv_pci_setup_iommu_table(tbl, addr, tce_table_size, bus_offset, 2498 page_shift); 2499 tbl->it_level_size = 1ULL << (level_shift - 3); 2500 tbl->it_indirect_levels = levels - 1; 2501 tbl->it_allocated_size = total_allocated; 2502 2503 pr_devel("Created TCE table: ws=%08llx ts=%lx @%08llx\n", 2504 window_size, tce_table_size, bus_offset); 2505 2506 return 0; 2507 } 2508 2509 static void pnv_pci_ioda2_table_do_free_pages(__be64 *addr, 2510 unsigned long size, unsigned level) 2511 { 2512 const unsigned long addr_ul = (unsigned long) addr & 2513 ~(TCE_PCI_READ | TCE_PCI_WRITE); 2514 2515 if (level) { 2516 long i; 2517 u64 *tmp = (u64 *) addr_ul; 2518 2519 for (i = 0; i < size; ++i) { 2520 unsigned long hpa = be64_to_cpu(tmp[i]); 2521 2522 if (!(hpa & (TCE_PCI_READ | TCE_PCI_WRITE))) 2523 continue; 2524 2525 pnv_pci_ioda2_table_do_free_pages(__va(hpa), size, 2526 level - 1); 2527 } 2528 } 2529 2530 free_pages(addr_ul, get_order(size << 3)); 2531 } 2532 2533 static void pnv_pci_ioda2_table_free_pages(struct iommu_table *tbl) 2534 { 2535 const unsigned long size = tbl->it_indirect_levels ? 2536 tbl->it_level_size : tbl->it_size; 2537 2538 if (!tbl->it_size) 2539 return; 2540 2541 pnv_pci_ioda2_table_do_free_pages((__be64 *)tbl->it_base, size, 2542 tbl->it_indirect_levels); 2543 } 2544 2545 static void pnv_pci_ioda2_setup_dma_pe(struct pnv_phb *phb, 2546 struct pnv_ioda_pe *pe) 2547 { 2548 int64_t rc; 2549 2550 /* TVE #1 is selected by PCI address bit 59 */ 2551 pe->tce_bypass_base = 1ull << 59; 2552 2553 iommu_register_group(&pe->table_group, phb->hose->global_number, 2554 pe->pe_number); 2555 2556 /* The PE will reserve all possible 32-bits space */ 2557 pe_info(pe, "Setting up 32-bit TCE table at 0..%08x\n", 2558 phb->ioda.m32_pci_base); 2559 2560 /* Setup linux iommu table */ 2561 pe->table_group.tce32_start = 0; 2562 pe->table_group.tce32_size = phb->ioda.m32_pci_base; 2563 pe->table_group.max_dynamic_windows_supported = 2564 IOMMU_TABLE_GROUP_MAX_TABLES; 2565 pe->table_group.max_levels = POWERNV_IOMMU_MAX_LEVELS; 2566 pe->table_group.pgsizes = SZ_4K | SZ_64K | SZ_16M; 2567 #ifdef CONFIG_IOMMU_API 2568 pe->table_group.ops = &pnv_pci_ioda2_ops; 2569 #endif 2570 2571 rc = pnv_pci_ioda2_setup_default_config(pe); 2572 if (rc) 2573 return; 2574 2575 if (pe->flags & PNV_IODA_PE_DEV) 2576 iommu_add_device(&pe->pdev->dev); 2577 else if (pe->flags & (PNV_IODA_PE_BUS | PNV_IODA_PE_BUS_ALL)) 2578 pnv_ioda_setup_bus_dma(pe, pe->pbus); 2579 } 2580 2581 static void pnv_ioda_setup_dma(struct pnv_phb *phb) 2582 { 2583 struct pci_controller *hose = phb->hose; 2584 struct pnv_ioda_pe *pe; 2585 unsigned int weight; 2586 2587 /* If we have more PE# than segments available, hand out one 2588 * per PE until we run out and let the rest fail. If not, 2589 * then we assign at least one segment per PE, plus more based 2590 * on the amount of devices under that PE 2591 */ 2592 pr_info("PCI: Domain %04x has %d available 32-bit DMA segments\n", 2593 hose->global_number, phb->ioda.dma32_count); 2594 2595 pnv_pci_ioda_setup_opal_tce_kill(phb); 2596 2597 /* Walk our PE list and configure their DMA segments */ 2598 list_for_each_entry(pe, &phb->ioda.pe_list, list) { 2599 weight = pnv_pci_ioda_pe_dma_weight(pe); 2600 if (!weight) 2601 continue; 2602 2603 /* 2604 * For IODA2 compliant PHB3, we needn't care about the weight. 2605 * The all available 32-bits DMA space will be assigned to 2606 * the specific PE. 2607 */ 2608 if (phb->type == PNV_PHB_IODA1) { 2609 pnv_pci_ioda1_setup_dma_pe(phb, pe); 2610 } else if (phb->type == PNV_PHB_IODA2) { 2611 pe_info(pe, "Assign DMA32 space\n"); 2612 pnv_pci_ioda2_setup_dma_pe(phb, pe); 2613 } else if (phb->type == PNV_PHB_NPU) { 2614 /* 2615 * We initialise the DMA space for an NPU PHB 2616 * after setup of the PHB is complete as we 2617 * point the NPU TVT to the the same location 2618 * as the PHB3 TVT. 2619 */ 2620 } 2621 } 2622 } 2623 2624 #ifdef CONFIG_PCI_MSI 2625 static void pnv_ioda2_msi_eoi(struct irq_data *d) 2626 { 2627 unsigned int hw_irq = (unsigned int)irqd_to_hwirq(d); 2628 struct irq_chip *chip = irq_data_get_irq_chip(d); 2629 struct pnv_phb *phb = container_of(chip, struct pnv_phb, 2630 ioda.irq_chip); 2631 int64_t rc; 2632 2633 rc = opal_pci_msi_eoi(phb->opal_id, hw_irq); 2634 WARN_ON_ONCE(rc); 2635 2636 icp_native_eoi(d); 2637 } 2638 2639 2640 static void set_msi_irq_chip(struct pnv_phb *phb, unsigned int virq) 2641 { 2642 struct irq_data *idata; 2643 struct irq_chip *ichip; 2644 2645 if (phb->type != PNV_PHB_IODA2) 2646 return; 2647 2648 if (!phb->ioda.irq_chip_init) { 2649 /* 2650 * First time we setup an MSI IRQ, we need to setup the 2651 * corresponding IRQ chip to route correctly. 2652 */ 2653 idata = irq_get_irq_data(virq); 2654 ichip = irq_data_get_irq_chip(idata); 2655 phb->ioda.irq_chip_init = 1; 2656 phb->ioda.irq_chip = *ichip; 2657 phb->ioda.irq_chip.irq_eoi = pnv_ioda2_msi_eoi; 2658 } 2659 irq_set_chip(virq, &phb->ioda.irq_chip); 2660 } 2661 2662 #ifdef CONFIG_CXL_BASE 2663 2664 struct device_node *pnv_pci_get_phb_node(struct pci_dev *dev) 2665 { 2666 struct pci_controller *hose = pci_bus_to_host(dev->bus); 2667 2668 return of_node_get(hose->dn); 2669 } 2670 EXPORT_SYMBOL(pnv_pci_get_phb_node); 2671 2672 int pnv_phb_to_cxl_mode(struct pci_dev *dev, uint64_t mode) 2673 { 2674 struct pci_controller *hose = pci_bus_to_host(dev->bus); 2675 struct pnv_phb *phb = hose->private_data; 2676 struct pnv_ioda_pe *pe; 2677 int rc; 2678 2679 pe = pnv_ioda_get_pe(dev); 2680 if (!pe) 2681 return -ENODEV; 2682 2683 pe_info(pe, "Switching PHB to CXL\n"); 2684 2685 rc = opal_pci_set_phb_cxl_mode(phb->opal_id, mode, pe->pe_number); 2686 if (rc) 2687 dev_err(&dev->dev, "opal_pci_set_phb_cxl_mode failed: %i\n", rc); 2688 2689 return rc; 2690 } 2691 EXPORT_SYMBOL(pnv_phb_to_cxl_mode); 2692 2693 /* Find PHB for cxl dev and allocate MSI hwirqs? 2694 * Returns the absolute hardware IRQ number 2695 */ 2696 int pnv_cxl_alloc_hwirqs(struct pci_dev *dev, int num) 2697 { 2698 struct pci_controller *hose = pci_bus_to_host(dev->bus); 2699 struct pnv_phb *phb = hose->private_data; 2700 int hwirq = msi_bitmap_alloc_hwirqs(&phb->msi_bmp, num); 2701 2702 if (hwirq < 0) { 2703 dev_warn(&dev->dev, "Failed to find a free MSI\n"); 2704 return -ENOSPC; 2705 } 2706 2707 return phb->msi_base + hwirq; 2708 } 2709 EXPORT_SYMBOL(pnv_cxl_alloc_hwirqs); 2710 2711 void pnv_cxl_release_hwirqs(struct pci_dev *dev, int hwirq, int num) 2712 { 2713 struct pci_controller *hose = pci_bus_to_host(dev->bus); 2714 struct pnv_phb *phb = hose->private_data; 2715 2716 msi_bitmap_free_hwirqs(&phb->msi_bmp, hwirq - phb->msi_base, num); 2717 } 2718 EXPORT_SYMBOL(pnv_cxl_release_hwirqs); 2719 2720 void pnv_cxl_release_hwirq_ranges(struct cxl_irq_ranges *irqs, 2721 struct pci_dev *dev) 2722 { 2723 struct pci_controller *hose = pci_bus_to_host(dev->bus); 2724 struct pnv_phb *phb = hose->private_data; 2725 int i, hwirq; 2726 2727 for (i = 1; i < CXL_IRQ_RANGES; i++) { 2728 if (!irqs->range[i]) 2729 continue; 2730 pr_devel("cxl release irq range 0x%x: offset: 0x%lx limit: %ld\n", 2731 i, irqs->offset[i], 2732 irqs->range[i]); 2733 hwirq = irqs->offset[i] - phb->msi_base; 2734 msi_bitmap_free_hwirqs(&phb->msi_bmp, hwirq, 2735 irqs->range[i]); 2736 } 2737 } 2738 EXPORT_SYMBOL(pnv_cxl_release_hwirq_ranges); 2739 2740 int pnv_cxl_alloc_hwirq_ranges(struct cxl_irq_ranges *irqs, 2741 struct pci_dev *dev, int num) 2742 { 2743 struct pci_controller *hose = pci_bus_to_host(dev->bus); 2744 struct pnv_phb *phb = hose->private_data; 2745 int i, hwirq, try; 2746 2747 memset(irqs, 0, sizeof(struct cxl_irq_ranges)); 2748 2749 /* 0 is reserved for the multiplexed PSL DSI interrupt */ 2750 for (i = 1; i < CXL_IRQ_RANGES && num; i++) { 2751 try = num; 2752 while (try) { 2753 hwirq = msi_bitmap_alloc_hwirqs(&phb->msi_bmp, try); 2754 if (hwirq >= 0) 2755 break; 2756 try /= 2; 2757 } 2758 if (!try) 2759 goto fail; 2760 2761 irqs->offset[i] = phb->msi_base + hwirq; 2762 irqs->range[i] = try; 2763 pr_devel("cxl alloc irq range 0x%x: offset: 0x%lx limit: %li\n", 2764 i, irqs->offset[i], irqs->range[i]); 2765 num -= try; 2766 } 2767 if (num) 2768 goto fail; 2769 2770 return 0; 2771 fail: 2772 pnv_cxl_release_hwirq_ranges(irqs, dev); 2773 return -ENOSPC; 2774 } 2775 EXPORT_SYMBOL(pnv_cxl_alloc_hwirq_ranges); 2776 2777 int pnv_cxl_get_irq_count(struct pci_dev *dev) 2778 { 2779 struct pci_controller *hose = pci_bus_to_host(dev->bus); 2780 struct pnv_phb *phb = hose->private_data; 2781 2782 return phb->msi_bmp.irq_count; 2783 } 2784 EXPORT_SYMBOL(pnv_cxl_get_irq_count); 2785 2786 int pnv_cxl_ioda_msi_setup(struct pci_dev *dev, unsigned int hwirq, 2787 unsigned int virq) 2788 { 2789 struct pci_controller *hose = pci_bus_to_host(dev->bus); 2790 struct pnv_phb *phb = hose->private_data; 2791 unsigned int xive_num = hwirq - phb->msi_base; 2792 struct pnv_ioda_pe *pe; 2793 int rc; 2794 2795 if (!(pe = pnv_ioda_get_pe(dev))) 2796 return -ENODEV; 2797 2798 /* Assign XIVE to PE */ 2799 rc = opal_pci_set_xive_pe(phb->opal_id, pe->pe_number, xive_num); 2800 if (rc) { 2801 pe_warn(pe, "%s: OPAL error %d setting msi_base 0x%x " 2802 "hwirq 0x%x XIVE 0x%x PE\n", 2803 pci_name(dev), rc, phb->msi_base, hwirq, xive_num); 2804 return -EIO; 2805 } 2806 set_msi_irq_chip(phb, virq); 2807 2808 return 0; 2809 } 2810 EXPORT_SYMBOL(pnv_cxl_ioda_msi_setup); 2811 #endif 2812 2813 static int pnv_pci_ioda_msi_setup(struct pnv_phb *phb, struct pci_dev *dev, 2814 unsigned int hwirq, unsigned int virq, 2815 unsigned int is_64, struct msi_msg *msg) 2816 { 2817 struct pnv_ioda_pe *pe = pnv_ioda_get_pe(dev); 2818 unsigned int xive_num = hwirq - phb->msi_base; 2819 __be32 data; 2820 int rc; 2821 2822 /* No PE assigned ? bail out ... no MSI for you ! */ 2823 if (pe == NULL) 2824 return -ENXIO; 2825 2826 /* Check if we have an MVE */ 2827 if (pe->mve_number < 0) 2828 return -ENXIO; 2829 2830 /* Force 32-bit MSI on some broken devices */ 2831 if (dev->no_64bit_msi) 2832 is_64 = 0; 2833 2834 /* Assign XIVE to PE */ 2835 rc = opal_pci_set_xive_pe(phb->opal_id, pe->pe_number, xive_num); 2836 if (rc) { 2837 pr_warn("%s: OPAL error %d setting XIVE %d PE\n", 2838 pci_name(dev), rc, xive_num); 2839 return -EIO; 2840 } 2841 2842 if (is_64) { 2843 __be64 addr64; 2844 2845 rc = opal_get_msi_64(phb->opal_id, pe->mve_number, xive_num, 1, 2846 &addr64, &data); 2847 if (rc) { 2848 pr_warn("%s: OPAL error %d getting 64-bit MSI data\n", 2849 pci_name(dev), rc); 2850 return -EIO; 2851 } 2852 msg->address_hi = be64_to_cpu(addr64) >> 32; 2853 msg->address_lo = be64_to_cpu(addr64) & 0xfffffffful; 2854 } else { 2855 __be32 addr32; 2856 2857 rc = opal_get_msi_32(phb->opal_id, pe->mve_number, xive_num, 1, 2858 &addr32, &data); 2859 if (rc) { 2860 pr_warn("%s: OPAL error %d getting 32-bit MSI data\n", 2861 pci_name(dev), rc); 2862 return -EIO; 2863 } 2864 msg->address_hi = 0; 2865 msg->address_lo = be32_to_cpu(addr32); 2866 } 2867 msg->data = be32_to_cpu(data); 2868 2869 set_msi_irq_chip(phb, virq); 2870 2871 pr_devel("%s: %s-bit MSI on hwirq %x (xive #%d)," 2872 " address=%x_%08x data=%x PE# %d\n", 2873 pci_name(dev), is_64 ? "64" : "32", hwirq, xive_num, 2874 msg->address_hi, msg->address_lo, data, pe->pe_number); 2875 2876 return 0; 2877 } 2878 2879 static void pnv_pci_init_ioda_msis(struct pnv_phb *phb) 2880 { 2881 unsigned int count; 2882 const __be32 *prop = of_get_property(phb->hose->dn, 2883 "ibm,opal-msi-ranges", NULL); 2884 if (!prop) { 2885 /* BML Fallback */ 2886 prop = of_get_property(phb->hose->dn, "msi-ranges", NULL); 2887 } 2888 if (!prop) 2889 return; 2890 2891 phb->msi_base = be32_to_cpup(prop); 2892 count = be32_to_cpup(prop + 1); 2893 if (msi_bitmap_alloc(&phb->msi_bmp, count, phb->hose->dn)) { 2894 pr_err("PCI %d: Failed to allocate MSI bitmap !\n", 2895 phb->hose->global_number); 2896 return; 2897 } 2898 2899 phb->msi_setup = pnv_pci_ioda_msi_setup; 2900 phb->msi32_support = 1; 2901 pr_info(" Allocated bitmap for %d MSIs (base IRQ 0x%x)\n", 2902 count, phb->msi_base); 2903 } 2904 #else 2905 static void pnv_pci_init_ioda_msis(struct pnv_phb *phb) { } 2906 #endif /* CONFIG_PCI_MSI */ 2907 2908 #ifdef CONFIG_PCI_IOV 2909 static void pnv_pci_ioda_fixup_iov_resources(struct pci_dev *pdev) 2910 { 2911 struct pci_controller *hose = pci_bus_to_host(pdev->bus); 2912 struct pnv_phb *phb = hose->private_data; 2913 const resource_size_t gate = phb->ioda.m64_segsize >> 2; 2914 struct resource *res; 2915 int i; 2916 resource_size_t size, total_vf_bar_sz; 2917 struct pci_dn *pdn; 2918 int mul, total_vfs; 2919 2920 if (!pdev->is_physfn || pdev->is_added) 2921 return; 2922 2923 pdn = pci_get_pdn(pdev); 2924 pdn->vfs_expanded = 0; 2925 pdn->m64_single_mode = false; 2926 2927 total_vfs = pci_sriov_get_totalvfs(pdev); 2928 mul = phb->ioda.total_pe_num; 2929 total_vf_bar_sz = 0; 2930 2931 for (i = 0; i < PCI_SRIOV_NUM_BARS; i++) { 2932 res = &pdev->resource[i + PCI_IOV_RESOURCES]; 2933 if (!res->flags || res->parent) 2934 continue; 2935 if (!pnv_pci_is_mem_pref_64(res->flags)) { 2936 dev_warn(&pdev->dev, "Don't support SR-IOV with" 2937 " non M64 VF BAR%d: %pR. \n", 2938 i, res); 2939 goto truncate_iov; 2940 } 2941 2942 total_vf_bar_sz += pci_iov_resource_size(pdev, 2943 i + PCI_IOV_RESOURCES); 2944 2945 /* 2946 * If bigger than quarter of M64 segment size, just round up 2947 * power of two. 2948 * 2949 * Generally, one M64 BAR maps one IOV BAR. To avoid conflict 2950 * with other devices, IOV BAR size is expanded to be 2951 * (total_pe * VF_BAR_size). When VF_BAR_size is half of M64 2952 * segment size , the expanded size would equal to half of the 2953 * whole M64 space size, which will exhaust the M64 Space and 2954 * limit the system flexibility. This is a design decision to 2955 * set the boundary to quarter of the M64 segment size. 2956 */ 2957 if (total_vf_bar_sz > gate) { 2958 mul = roundup_pow_of_two(total_vfs); 2959 dev_info(&pdev->dev, 2960 "VF BAR Total IOV size %llx > %llx, roundup to %d VFs\n", 2961 total_vf_bar_sz, gate, mul); 2962 pdn->m64_single_mode = true; 2963 break; 2964 } 2965 } 2966 2967 for (i = 0; i < PCI_SRIOV_NUM_BARS; i++) { 2968 res = &pdev->resource[i + PCI_IOV_RESOURCES]; 2969 if (!res->flags || res->parent) 2970 continue; 2971 2972 size = pci_iov_resource_size(pdev, i + PCI_IOV_RESOURCES); 2973 /* 2974 * On PHB3, the minimum size alignment of M64 BAR in single 2975 * mode is 32MB. 2976 */ 2977 if (pdn->m64_single_mode && (size < SZ_32M)) 2978 goto truncate_iov; 2979 dev_dbg(&pdev->dev, " Fixing VF BAR%d: %pR to\n", i, res); 2980 res->end = res->start + size * mul - 1; 2981 dev_dbg(&pdev->dev, " %pR\n", res); 2982 dev_info(&pdev->dev, "VF BAR%d: %pR (expanded to %d VFs for PE alignment)", 2983 i, res, mul); 2984 } 2985 pdn->vfs_expanded = mul; 2986 2987 return; 2988 2989 truncate_iov: 2990 /* To save MMIO space, IOV BAR is truncated. */ 2991 for (i = 0; i < PCI_SRIOV_NUM_BARS; i++) { 2992 res = &pdev->resource[i + PCI_IOV_RESOURCES]; 2993 res->flags = 0; 2994 res->end = res->start - 1; 2995 } 2996 } 2997 #endif /* CONFIG_PCI_IOV */ 2998 2999 static void pnv_ioda_setup_pe_res(struct pnv_ioda_pe *pe, 3000 struct resource *res) 3001 { 3002 struct pnv_phb *phb = pe->phb; 3003 struct pci_bus_region region; 3004 int index; 3005 int64_t rc; 3006 3007 if (!res || !res->flags || res->start > res->end) 3008 return; 3009 3010 if (res->flags & IORESOURCE_IO) { 3011 region.start = res->start - phb->ioda.io_pci_base; 3012 region.end = res->end - phb->ioda.io_pci_base; 3013 index = region.start / phb->ioda.io_segsize; 3014 3015 while (index < phb->ioda.total_pe_num && 3016 region.start <= region.end) { 3017 phb->ioda.io_segmap[index] = pe->pe_number; 3018 rc = opal_pci_map_pe_mmio_window(phb->opal_id, 3019 pe->pe_number, OPAL_IO_WINDOW_TYPE, 0, index); 3020 if (rc != OPAL_SUCCESS) { 3021 pr_err("%s: Error %lld mapping IO segment#%d to PE#%d\n", 3022 __func__, rc, index, pe->pe_number); 3023 break; 3024 } 3025 3026 region.start += phb->ioda.io_segsize; 3027 index++; 3028 } 3029 } else if ((res->flags & IORESOURCE_MEM) && 3030 !pnv_pci_is_mem_pref_64(res->flags)) { 3031 region.start = res->start - 3032 phb->hose->mem_offset[0] - 3033 phb->ioda.m32_pci_base; 3034 region.end = res->end - 3035 phb->hose->mem_offset[0] - 3036 phb->ioda.m32_pci_base; 3037 index = region.start / phb->ioda.m32_segsize; 3038 3039 while (index < phb->ioda.total_pe_num && 3040 region.start <= region.end) { 3041 phb->ioda.m32_segmap[index] = pe->pe_number; 3042 rc = opal_pci_map_pe_mmio_window(phb->opal_id, 3043 pe->pe_number, OPAL_M32_WINDOW_TYPE, 0, index); 3044 if (rc != OPAL_SUCCESS) { 3045 pr_err("%s: Error %lld mapping M32 segment#%d to PE#%d", 3046 __func__, rc, index, pe->pe_number); 3047 break; 3048 } 3049 3050 region.start += phb->ioda.m32_segsize; 3051 index++; 3052 } 3053 } 3054 } 3055 3056 /* 3057 * This function is supposed to be called on basis of PE from top 3058 * to bottom style. So the the I/O or MMIO segment assigned to 3059 * parent PE could be overrided by its child PEs if necessary. 3060 */ 3061 static void pnv_ioda_setup_pe_seg(struct pnv_ioda_pe *pe) 3062 { 3063 struct pci_dev *pdev; 3064 int i; 3065 3066 /* 3067 * NOTE: We only care PCI bus based PE for now. For PCI 3068 * device based PE, for example SRIOV sensitive VF should 3069 * be figured out later. 3070 */ 3071 BUG_ON(!(pe->flags & (PNV_IODA_PE_BUS | PNV_IODA_PE_BUS_ALL))); 3072 3073 list_for_each_entry(pdev, &pe->pbus->devices, bus_list) { 3074 for (i = 0; i <= PCI_ROM_RESOURCE; i++) 3075 pnv_ioda_setup_pe_res(pe, &pdev->resource[i]); 3076 3077 /* 3078 * If the PE contains all subordinate PCI buses, the 3079 * windows of the child bridges should be mapped to 3080 * the PE as well. 3081 */ 3082 if (!(pe->flags & PNV_IODA_PE_BUS_ALL) || !pci_is_bridge(pdev)) 3083 continue; 3084 for (i = 0; i < PCI_BRIDGE_RESOURCE_NUM; i++) 3085 pnv_ioda_setup_pe_res(pe, 3086 &pdev->resource[PCI_BRIDGE_RESOURCES + i]); 3087 } 3088 } 3089 3090 static void pnv_pci_ioda_setup_seg(void) 3091 { 3092 struct pci_controller *tmp, *hose; 3093 struct pnv_phb *phb; 3094 struct pnv_ioda_pe *pe; 3095 3096 list_for_each_entry_safe(hose, tmp, &hose_list, list_node) { 3097 phb = hose->private_data; 3098 3099 /* NPU PHB does not support IO or MMIO segmentation */ 3100 if (phb->type == PNV_PHB_NPU) 3101 continue; 3102 3103 list_for_each_entry(pe, &phb->ioda.pe_list, list) { 3104 pnv_ioda_setup_pe_seg(pe); 3105 } 3106 } 3107 } 3108 3109 static void pnv_pci_ioda_setup_DMA(void) 3110 { 3111 struct pci_controller *hose, *tmp; 3112 struct pnv_phb *phb; 3113 3114 list_for_each_entry_safe(hose, tmp, &hose_list, list_node) { 3115 pnv_ioda_setup_dma(hose->private_data); 3116 3117 /* Mark the PHB initialization done */ 3118 phb = hose->private_data; 3119 phb->initialized = 1; 3120 } 3121 } 3122 3123 static void pnv_pci_ioda_create_dbgfs(void) 3124 { 3125 #ifdef CONFIG_DEBUG_FS 3126 struct pci_controller *hose, *tmp; 3127 struct pnv_phb *phb; 3128 char name[16]; 3129 3130 list_for_each_entry_safe(hose, tmp, &hose_list, list_node) { 3131 phb = hose->private_data; 3132 3133 sprintf(name, "PCI%04x", hose->global_number); 3134 phb->dbgfs = debugfs_create_dir(name, powerpc_debugfs_root); 3135 if (!phb->dbgfs) 3136 pr_warning("%s: Error on creating debugfs on PHB#%x\n", 3137 __func__, hose->global_number); 3138 } 3139 #endif /* CONFIG_DEBUG_FS */ 3140 } 3141 3142 static void pnv_npu_ioda_fixup(void) 3143 { 3144 bool enable_bypass; 3145 struct pci_controller *hose, *tmp; 3146 struct pnv_phb *phb; 3147 struct pnv_ioda_pe *pe; 3148 unsigned int weight; 3149 3150 list_for_each_entry_safe(hose, tmp, &hose_list, list_node) { 3151 phb = hose->private_data; 3152 if (phb->type != PNV_PHB_NPU) 3153 continue; 3154 3155 list_for_each_entry(pe, &phb->ioda.pe_list, list) { 3156 weight = pnv_pci_ioda_pe_dma_weight(pe); 3157 if (WARN_ON(!weight)) 3158 continue; 3159 3160 enable_bypass = dma_get_mask(&pe->pdev->dev) == 3161 DMA_BIT_MASK(64); 3162 pnv_npu_init_dma_pe(pe); 3163 pnv_npu_dma_set_bypass(pe, enable_bypass); 3164 } 3165 } 3166 } 3167 3168 static void pnv_pci_ioda_fixup(void) 3169 { 3170 pnv_pci_ioda_setup_PEs(); 3171 pnv_pci_ioda_setup_seg(); 3172 pnv_pci_ioda_setup_DMA(); 3173 3174 pnv_pci_ioda_create_dbgfs(); 3175 3176 #ifdef CONFIG_EEH 3177 eeh_init(); 3178 eeh_addr_cache_build(); 3179 #endif 3180 3181 /* Link NPU IODA tables to their PCI devices. */ 3182 pnv_npu_ioda_fixup(); 3183 } 3184 3185 /* 3186 * Returns the alignment for I/O or memory windows for P2P 3187 * bridges. That actually depends on how PEs are segmented. 3188 * For now, we return I/O or M32 segment size for PE sensitive 3189 * P2P bridges. Otherwise, the default values (4KiB for I/O, 3190 * 1MiB for memory) will be returned. 3191 * 3192 * The current PCI bus might be put into one PE, which was 3193 * create against the parent PCI bridge. For that case, we 3194 * needn't enlarge the alignment so that we can save some 3195 * resources. 3196 */ 3197 static resource_size_t pnv_pci_window_alignment(struct pci_bus *bus, 3198 unsigned long type) 3199 { 3200 struct pci_dev *bridge; 3201 struct pci_controller *hose = pci_bus_to_host(bus); 3202 struct pnv_phb *phb = hose->private_data; 3203 int num_pci_bridges = 0; 3204 3205 bridge = bus->self; 3206 while (bridge) { 3207 if (pci_pcie_type(bridge) == PCI_EXP_TYPE_PCI_BRIDGE) { 3208 num_pci_bridges++; 3209 if (num_pci_bridges >= 2) 3210 return 1; 3211 } 3212 3213 bridge = bridge->bus->self; 3214 } 3215 3216 /* We fail back to M32 if M64 isn't supported */ 3217 if (phb->ioda.m64_segsize && 3218 pnv_pci_is_mem_pref_64(type)) 3219 return phb->ioda.m64_segsize; 3220 if (type & IORESOURCE_MEM) 3221 return phb->ioda.m32_segsize; 3222 3223 return phb->ioda.io_segsize; 3224 } 3225 3226 #ifdef CONFIG_PCI_IOV 3227 static resource_size_t pnv_pci_iov_resource_alignment(struct pci_dev *pdev, 3228 int resno) 3229 { 3230 struct pci_controller *hose = pci_bus_to_host(pdev->bus); 3231 struct pnv_phb *phb = hose->private_data; 3232 struct pci_dn *pdn = pci_get_pdn(pdev); 3233 resource_size_t align; 3234 3235 /* 3236 * On PowerNV platform, IOV BAR is mapped by M64 BAR to enable the 3237 * SR-IOV. While from hardware perspective, the range mapped by M64 3238 * BAR should be size aligned. 3239 * 3240 * When IOV BAR is mapped with M64 BAR in Single PE mode, the extra 3241 * powernv-specific hardware restriction is gone. But if just use the 3242 * VF BAR size as the alignment, PF BAR / VF BAR may be allocated with 3243 * in one segment of M64 #15, which introduces the PE conflict between 3244 * PF and VF. Based on this, the minimum alignment of an IOV BAR is 3245 * m64_segsize. 3246 * 3247 * This function returns the total IOV BAR size if M64 BAR is in 3248 * Shared PE mode or just VF BAR size if not. 3249 * If the M64 BAR is in Single PE mode, return the VF BAR size or 3250 * M64 segment size if IOV BAR size is less. 3251 */ 3252 align = pci_iov_resource_size(pdev, resno); 3253 if (!pdn->vfs_expanded) 3254 return align; 3255 if (pdn->m64_single_mode) 3256 return max(align, (resource_size_t)phb->ioda.m64_segsize); 3257 3258 return pdn->vfs_expanded * align; 3259 } 3260 #endif /* CONFIG_PCI_IOV */ 3261 3262 /* Prevent enabling devices for which we couldn't properly 3263 * assign a PE 3264 */ 3265 static bool pnv_pci_enable_device_hook(struct pci_dev *dev) 3266 { 3267 struct pci_controller *hose = pci_bus_to_host(dev->bus); 3268 struct pnv_phb *phb = hose->private_data; 3269 struct pci_dn *pdn; 3270 3271 /* The function is probably called while the PEs have 3272 * not be created yet. For example, resource reassignment 3273 * during PCI probe period. We just skip the check if 3274 * PEs isn't ready. 3275 */ 3276 if (!phb->initialized) 3277 return true; 3278 3279 pdn = pci_get_pdn(dev); 3280 if (!pdn || pdn->pe_number == IODA_INVALID_PE) 3281 return false; 3282 3283 return true; 3284 } 3285 3286 static void pnv_pci_ioda_shutdown(struct pci_controller *hose) 3287 { 3288 struct pnv_phb *phb = hose->private_data; 3289 3290 opal_pci_reset(phb->opal_id, OPAL_RESET_PCI_IODA_TABLE, 3291 OPAL_ASSERT_RESET); 3292 } 3293 3294 static const struct pci_controller_ops pnv_pci_ioda_controller_ops = { 3295 .dma_dev_setup = pnv_pci_dma_dev_setup, 3296 .dma_bus_setup = pnv_pci_dma_bus_setup, 3297 #ifdef CONFIG_PCI_MSI 3298 .setup_msi_irqs = pnv_setup_msi_irqs, 3299 .teardown_msi_irqs = pnv_teardown_msi_irqs, 3300 #endif 3301 .enable_device_hook = pnv_pci_enable_device_hook, 3302 .window_alignment = pnv_pci_window_alignment, 3303 .reset_secondary_bus = pnv_pci_reset_secondary_bus, 3304 .dma_set_mask = pnv_pci_ioda_dma_set_mask, 3305 .dma_get_required_mask = pnv_pci_ioda_dma_get_required_mask, 3306 .shutdown = pnv_pci_ioda_shutdown, 3307 }; 3308 3309 static const struct pci_controller_ops pnv_npu_ioda_controller_ops = { 3310 .dma_dev_setup = pnv_pci_dma_dev_setup, 3311 #ifdef CONFIG_PCI_MSI 3312 .setup_msi_irqs = pnv_setup_msi_irqs, 3313 .teardown_msi_irqs = pnv_teardown_msi_irqs, 3314 #endif 3315 .enable_device_hook = pnv_pci_enable_device_hook, 3316 .window_alignment = pnv_pci_window_alignment, 3317 .reset_secondary_bus = pnv_pci_reset_secondary_bus, 3318 .dma_set_mask = pnv_npu_dma_set_mask, 3319 .shutdown = pnv_pci_ioda_shutdown, 3320 }; 3321 3322 static void __init pnv_pci_init_ioda_phb(struct device_node *np, 3323 u64 hub_id, int ioda_type) 3324 { 3325 struct pci_controller *hose; 3326 struct pnv_phb *phb; 3327 unsigned long size, m64map_off, m32map_off, pemap_off; 3328 unsigned long iomap_off = 0, dma32map_off = 0; 3329 const __be64 *prop64; 3330 const __be32 *prop32; 3331 int len; 3332 unsigned int segno; 3333 u64 phb_id; 3334 void *aux; 3335 long rc; 3336 3337 pr_info("Initializing IODA%d OPAL PHB %s\n", ioda_type, np->full_name); 3338 3339 prop64 = of_get_property(np, "ibm,opal-phbid", NULL); 3340 if (!prop64) { 3341 pr_err(" Missing \"ibm,opal-phbid\" property !\n"); 3342 return; 3343 } 3344 phb_id = be64_to_cpup(prop64); 3345 pr_debug(" PHB-ID : 0x%016llx\n", phb_id); 3346 3347 phb = memblock_virt_alloc(sizeof(struct pnv_phb), 0); 3348 3349 /* Allocate PCI controller */ 3350 phb->hose = hose = pcibios_alloc_controller(np); 3351 if (!phb->hose) { 3352 pr_err(" Can't allocate PCI controller for %s\n", 3353 np->full_name); 3354 memblock_free(__pa(phb), sizeof(struct pnv_phb)); 3355 return; 3356 } 3357 3358 spin_lock_init(&phb->lock); 3359 prop32 = of_get_property(np, "bus-range", &len); 3360 if (prop32 && len == 8) { 3361 hose->first_busno = be32_to_cpu(prop32[0]); 3362 hose->last_busno = be32_to_cpu(prop32[1]); 3363 } else { 3364 pr_warn(" Broken <bus-range> on %s\n", np->full_name); 3365 hose->first_busno = 0; 3366 hose->last_busno = 0xff; 3367 } 3368 hose->private_data = phb; 3369 phb->hub_id = hub_id; 3370 phb->opal_id = phb_id; 3371 phb->type = ioda_type; 3372 mutex_init(&phb->ioda.pe_alloc_mutex); 3373 3374 /* Detect specific models for error handling */ 3375 if (of_device_is_compatible(np, "ibm,p7ioc-pciex")) 3376 phb->model = PNV_PHB_MODEL_P7IOC; 3377 else if (of_device_is_compatible(np, "ibm,power8-pciex")) 3378 phb->model = PNV_PHB_MODEL_PHB3; 3379 else if (of_device_is_compatible(np, "ibm,power8-npu-pciex")) 3380 phb->model = PNV_PHB_MODEL_NPU; 3381 else 3382 phb->model = PNV_PHB_MODEL_UNKNOWN; 3383 3384 /* Parse 32-bit and IO ranges (if any) */ 3385 pci_process_bridge_OF_ranges(hose, np, !hose->global_number); 3386 3387 /* Get registers */ 3388 phb->regs = of_iomap(np, 0); 3389 if (phb->regs == NULL) 3390 pr_err(" Failed to map registers !\n"); 3391 3392 /* Initialize more IODA stuff */ 3393 phb->ioda.total_pe_num = 1; 3394 prop32 = of_get_property(np, "ibm,opal-num-pes", NULL); 3395 if (prop32) 3396 phb->ioda.total_pe_num = be32_to_cpup(prop32); 3397 prop32 = of_get_property(np, "ibm,opal-reserved-pe", NULL); 3398 if (prop32) 3399 phb->ioda.reserved_pe_idx = be32_to_cpup(prop32); 3400 3401 /* Parse 64-bit MMIO range */ 3402 pnv_ioda_parse_m64_window(phb); 3403 3404 phb->ioda.m32_size = resource_size(&hose->mem_resources[0]); 3405 /* FW Has already off top 64k of M32 space (MSI space) */ 3406 phb->ioda.m32_size += 0x10000; 3407 3408 phb->ioda.m32_segsize = phb->ioda.m32_size / phb->ioda.total_pe_num; 3409 phb->ioda.m32_pci_base = hose->mem_resources[0].start - hose->mem_offset[0]; 3410 phb->ioda.io_size = hose->pci_io_size; 3411 phb->ioda.io_segsize = phb->ioda.io_size / phb->ioda.total_pe_num; 3412 phb->ioda.io_pci_base = 0; /* XXX calculate this ? */ 3413 3414 /* Calculate how many 32-bit TCE segments we have */ 3415 phb->ioda.dma32_count = phb->ioda.m32_pci_base / 3416 PNV_IODA1_DMA32_SEGSIZE; 3417 3418 /* Allocate aux data & arrays. We don't have IO ports on PHB3 */ 3419 size = _ALIGN_UP(phb->ioda.total_pe_num / 8, sizeof(unsigned long)); 3420 m64map_off = size; 3421 size += phb->ioda.total_pe_num * sizeof(phb->ioda.m64_segmap[0]); 3422 m32map_off = size; 3423 size += phb->ioda.total_pe_num * sizeof(phb->ioda.m32_segmap[0]); 3424 if (phb->type == PNV_PHB_IODA1) { 3425 iomap_off = size; 3426 size += phb->ioda.total_pe_num * sizeof(phb->ioda.io_segmap[0]); 3427 dma32map_off = size; 3428 size += phb->ioda.dma32_count * 3429 sizeof(phb->ioda.dma32_segmap[0]); 3430 } 3431 pemap_off = size; 3432 size += phb->ioda.total_pe_num * sizeof(struct pnv_ioda_pe); 3433 aux = memblock_virt_alloc(size, 0); 3434 phb->ioda.pe_alloc = aux; 3435 phb->ioda.m64_segmap = aux + m64map_off; 3436 phb->ioda.m32_segmap = aux + m32map_off; 3437 for (segno = 0; segno < phb->ioda.total_pe_num; segno++) { 3438 phb->ioda.m64_segmap[segno] = IODA_INVALID_PE; 3439 phb->ioda.m32_segmap[segno] = IODA_INVALID_PE; 3440 } 3441 if (phb->type == PNV_PHB_IODA1) { 3442 phb->ioda.io_segmap = aux + iomap_off; 3443 for (segno = 0; segno < phb->ioda.total_pe_num; segno++) 3444 phb->ioda.io_segmap[segno] = IODA_INVALID_PE; 3445 3446 phb->ioda.dma32_segmap = aux + dma32map_off; 3447 for (segno = 0; segno < phb->ioda.dma32_count; segno++) 3448 phb->ioda.dma32_segmap[segno] = IODA_INVALID_PE; 3449 } 3450 phb->ioda.pe_array = aux + pemap_off; 3451 set_bit(phb->ioda.reserved_pe_idx, phb->ioda.pe_alloc); 3452 3453 INIT_LIST_HEAD(&phb->ioda.pe_list); 3454 mutex_init(&phb->ioda.pe_list_mutex); 3455 3456 /* Calculate how many 32-bit TCE segments we have */ 3457 phb->ioda.dma32_count = phb->ioda.m32_pci_base / 3458 PNV_IODA1_DMA32_SEGSIZE; 3459 3460 #if 0 /* We should really do that ... */ 3461 rc = opal_pci_set_phb_mem_window(opal->phb_id, 3462 window_type, 3463 window_num, 3464 starting_real_address, 3465 starting_pci_address, 3466 segment_size); 3467 #endif 3468 3469 pr_info(" %03d (%03d) PE's M32: 0x%x [segment=0x%x]\n", 3470 phb->ioda.total_pe_num, phb->ioda.reserved_pe_idx, 3471 phb->ioda.m32_size, phb->ioda.m32_segsize); 3472 if (phb->ioda.m64_size) 3473 pr_info(" M64: 0x%lx [segment=0x%lx]\n", 3474 phb->ioda.m64_size, phb->ioda.m64_segsize); 3475 if (phb->ioda.io_size) 3476 pr_info(" IO: 0x%x [segment=0x%x]\n", 3477 phb->ioda.io_size, phb->ioda.io_segsize); 3478 3479 3480 phb->hose->ops = &pnv_pci_ops; 3481 phb->get_pe_state = pnv_ioda_get_pe_state; 3482 phb->freeze_pe = pnv_ioda_freeze_pe; 3483 phb->unfreeze_pe = pnv_ioda_unfreeze_pe; 3484 3485 /* Setup TCEs */ 3486 phb->dma_dev_setup = pnv_pci_ioda_dma_dev_setup; 3487 3488 /* Setup MSI support */ 3489 pnv_pci_init_ioda_msis(phb); 3490 3491 /* 3492 * We pass the PCI probe flag PCI_REASSIGN_ALL_RSRC here 3493 * to let the PCI core do resource assignment. It's supposed 3494 * that the PCI core will do correct I/O and MMIO alignment 3495 * for the P2P bridge bars so that each PCI bus (excluding 3496 * the child P2P bridges) can form individual PE. 3497 */ 3498 ppc_md.pcibios_fixup = pnv_pci_ioda_fixup; 3499 3500 if (phb->type == PNV_PHB_NPU) 3501 hose->controller_ops = pnv_npu_ioda_controller_ops; 3502 else 3503 hose->controller_ops = pnv_pci_ioda_controller_ops; 3504 3505 #ifdef CONFIG_PCI_IOV 3506 ppc_md.pcibios_fixup_sriov = pnv_pci_ioda_fixup_iov_resources; 3507 ppc_md.pcibios_iov_resource_alignment = pnv_pci_iov_resource_alignment; 3508 #endif 3509 3510 pci_add_flags(PCI_REASSIGN_ALL_RSRC); 3511 3512 /* Reset IODA tables to a clean state */ 3513 rc = opal_pci_reset(phb_id, OPAL_RESET_PCI_IODA_TABLE, OPAL_ASSERT_RESET); 3514 if (rc) 3515 pr_warning(" OPAL Error %ld performing IODA table reset !\n", rc); 3516 3517 /* If we're running in kdump kerenl, the previous kerenl never 3518 * shutdown PCI devices correctly. We already got IODA table 3519 * cleaned out. So we have to issue PHB reset to stop all PCI 3520 * transactions from previous kerenl. 3521 */ 3522 if (is_kdump_kernel()) { 3523 pr_info(" Issue PHB reset ...\n"); 3524 pnv_eeh_phb_reset(hose, EEH_RESET_FUNDAMENTAL); 3525 pnv_eeh_phb_reset(hose, EEH_RESET_DEACTIVATE); 3526 } 3527 3528 /* Remove M64 resource if we can't configure it successfully */ 3529 if (!phb->init_m64 || phb->init_m64(phb)) 3530 hose->mem_resources[1].flags = 0; 3531 } 3532 3533 void __init pnv_pci_init_ioda2_phb(struct device_node *np) 3534 { 3535 pnv_pci_init_ioda_phb(np, 0, PNV_PHB_IODA2); 3536 } 3537 3538 void __init pnv_pci_init_npu_phb(struct device_node *np) 3539 { 3540 pnv_pci_init_ioda_phb(np, 0, PNV_PHB_NPU); 3541 } 3542 3543 void __init pnv_pci_init_ioda_hub(struct device_node *np) 3544 { 3545 struct device_node *phbn; 3546 const __be64 *prop64; 3547 u64 hub_id; 3548 3549 pr_info("Probing IODA IO-Hub %s\n", np->full_name); 3550 3551 prop64 = of_get_property(np, "ibm,opal-hubid", NULL); 3552 if (!prop64) { 3553 pr_err(" Missing \"ibm,opal-hubid\" property !\n"); 3554 return; 3555 } 3556 hub_id = be64_to_cpup(prop64); 3557 pr_devel(" HUB-ID : 0x%016llx\n", hub_id); 3558 3559 /* Count child PHBs */ 3560 for_each_child_of_node(np, phbn) { 3561 /* Look for IODA1 PHBs */ 3562 if (of_device_is_compatible(phbn, "ibm,ioda-phb")) 3563 pnv_pci_init_ioda_phb(phbn, hub_id, PNV_PHB_IODA1); 3564 } 3565 } 3566