1 /* 2 * Support PCI/PCIe on PowerNV platforms 3 * 4 * Copyright 2011 Benjamin Herrenschmidt, IBM Corp. 5 * 6 * This program is free software; you can redistribute it and/or 7 * modify it under the terms of the GNU General Public License 8 * as published by the Free Software Foundation; either version 9 * 2 of the License, or (at your option) any later version. 10 */ 11 12 #undef DEBUG 13 14 #include <linux/kernel.h> 15 #include <linux/pci.h> 16 #include <linux/delay.h> 17 #include <linux/string.h> 18 #include <linux/init.h> 19 #include <linux/bootmem.h> 20 #include <linux/irq.h> 21 #include <linux/io.h> 22 #include <linux/msi.h> 23 24 #include <asm/sections.h> 25 #include <asm/io.h> 26 #include <asm/prom.h> 27 #include <asm/pci-bridge.h> 28 #include <asm/machdep.h> 29 #include <asm/ppc-pci.h> 30 #include <asm/opal.h> 31 #include <asm/iommu.h> 32 #include <asm/tce.h> 33 34 #include "powernv.h" 35 #include "pci.h" 36 37 struct resource_wrap { 38 struct list_head link; 39 resource_size_t size; 40 resource_size_t align; 41 struct pci_dev *dev; /* Set if it's a device */ 42 struct pci_bus *bus; /* Set if it's a bridge */ 43 }; 44 45 static int __pe_printk(const char *level, const struct pnv_ioda_pe *pe, 46 struct va_format *vaf) 47 { 48 char pfix[32]; 49 50 if (pe->pdev) 51 strlcpy(pfix, dev_name(&pe->pdev->dev), sizeof(pfix)); 52 else 53 sprintf(pfix, "%04x:%02x ", 54 pci_domain_nr(pe->pbus), pe->pbus->number); 55 return printk("pci %s%s: [PE# %.3d] %pV", level, pfix, pe->pe_number, vaf); 56 } 57 58 #define define_pe_printk_level(func, kern_level) \ 59 static int func(const struct pnv_ioda_pe *pe, const char *fmt, ...) \ 60 { \ 61 struct va_format vaf; \ 62 va_list args; \ 63 int r; \ 64 \ 65 va_start(args, fmt); \ 66 \ 67 vaf.fmt = fmt; \ 68 vaf.va = &args; \ 69 \ 70 r = __pe_printk(kern_level, pe, &vaf); \ 71 va_end(args); \ 72 \ 73 return r; \ 74 } \ 75 76 define_pe_printk_level(pe_err, KERN_ERR); 77 define_pe_printk_level(pe_warn, KERN_WARNING); 78 define_pe_printk_level(pe_info, KERN_INFO); 79 80 81 /* Calculate resource usage & alignment requirement of a single 82 * device. This will also assign all resources within the device 83 * for a given type starting at 0 for the biggest one and then 84 * assigning in decreasing order of size. 85 */ 86 static void __devinit pnv_ioda_calc_dev(struct pci_dev *dev, unsigned int flags, 87 resource_size_t *size, 88 resource_size_t *align) 89 { 90 resource_size_t start; 91 struct resource *r; 92 int i; 93 94 pr_devel(" -> CDR %s\n", pci_name(dev)); 95 96 *size = *align = 0; 97 98 /* Clear the resources out and mark them all unset */ 99 for (i = 0; i <= PCI_ROM_RESOURCE; i++) { 100 r = &dev->resource[i]; 101 if (!(r->flags & flags)) 102 continue; 103 if (r->start) { 104 r->end -= r->start; 105 r->start = 0; 106 } 107 r->flags |= IORESOURCE_UNSET; 108 } 109 110 /* We currently keep all memory resources together, we 111 * will handle prefetch & 64-bit separately in the future 112 * but for now we stick everybody in M32 113 */ 114 start = 0; 115 for (;;) { 116 resource_size_t max_size = 0; 117 int max_no = -1; 118 119 /* Find next biggest resource */ 120 for (i = 0; i <= PCI_ROM_RESOURCE; i++) { 121 r = &dev->resource[i]; 122 if (!(r->flags & IORESOURCE_UNSET) || 123 !(r->flags & flags)) 124 continue; 125 if (resource_size(r) > max_size) { 126 max_size = resource_size(r); 127 max_no = i; 128 } 129 } 130 if (max_no < 0) 131 break; 132 r = &dev->resource[max_no]; 133 if (max_size > *align) 134 *align = max_size; 135 *size += max_size; 136 r->start = start; 137 start += max_size; 138 r->end = r->start + max_size - 1; 139 r->flags &= ~IORESOURCE_UNSET; 140 pr_devel(" -> R%d %016llx..%016llx\n", 141 max_no, r->start, r->end); 142 } 143 pr_devel(" <- CDR %s size=%llx align=%llx\n", 144 pci_name(dev), *size, *align); 145 } 146 147 /* Allocate a resource "wrap" for a given device or bridge and 148 * insert it at the right position in the sorted list 149 */ 150 static void __devinit pnv_ioda_add_wrap(struct list_head *list, 151 struct pci_bus *bus, 152 struct pci_dev *dev, 153 resource_size_t size, 154 resource_size_t align) 155 { 156 struct resource_wrap *w1, *w = kzalloc(sizeof(*w), GFP_KERNEL); 157 158 w->size = size; 159 w->align = align; 160 w->dev = dev; 161 w->bus = bus; 162 163 list_for_each_entry(w1, list, link) { 164 if (w1->align < align) { 165 list_add_tail(&w->link, &w1->link); 166 return; 167 } 168 } 169 list_add_tail(&w->link, list); 170 } 171 172 /* Offset device resources of a given type */ 173 static void __devinit pnv_ioda_offset_dev(struct pci_dev *dev, 174 unsigned int flags, 175 resource_size_t offset) 176 { 177 struct resource *r; 178 int i; 179 180 pr_devel(" -> ODR %s [%x] +%016llx\n", pci_name(dev), flags, offset); 181 182 for (i = 0; i <= PCI_ROM_RESOURCE; i++) { 183 r = &dev->resource[i]; 184 if (r->flags & flags) { 185 dev->resource[i].start += offset; 186 dev->resource[i].end += offset; 187 } 188 } 189 190 pr_devel(" <- ODR %s [%x] +%016llx\n", pci_name(dev), flags, offset); 191 } 192 193 /* Offset bus resources (& all children) of a given type */ 194 static void __devinit pnv_ioda_offset_bus(struct pci_bus *bus, 195 unsigned int flags, 196 resource_size_t offset) 197 { 198 struct resource *r; 199 struct pci_dev *dev; 200 struct pci_bus *cbus; 201 int i; 202 203 pr_devel(" -> OBR %s [%x] +%016llx\n", 204 bus->self ? pci_name(bus->self) : "root", flags, offset); 205 206 pci_bus_for_each_resource(bus, r, i) { 207 if (r && (r->flags & flags)) { 208 r->start += offset; 209 r->end += offset; 210 } 211 } 212 list_for_each_entry(dev, &bus->devices, bus_list) 213 pnv_ioda_offset_dev(dev, flags, offset); 214 list_for_each_entry(cbus, &bus->children, node) 215 pnv_ioda_offset_bus(cbus, flags, offset); 216 217 pr_devel(" <- OBR %s [%x]\n", 218 bus->self ? pci_name(bus->self) : "root", flags); 219 } 220 221 /* This is the guts of our IODA resource allocation. This is called 222 * recursively for each bus in the system. It calculates all the 223 * necessary size and requirements for children and assign them 224 * resources such that: 225 * 226 * - Each function fits in it's own contiguous set of IO/M32 227 * segment 228 * 229 * - All segments behind a P2P bridge are contiguous and obey 230 * alignment constraints of those bridges 231 */ 232 static void __devinit pnv_ioda_calc_bus(struct pci_bus *bus, unsigned int flags, 233 resource_size_t *size, 234 resource_size_t *align) 235 { 236 struct pci_controller *hose = pci_bus_to_host(bus); 237 struct pnv_phb *phb = hose->private_data; 238 resource_size_t dev_size, dev_align, start; 239 resource_size_t min_align, min_balign; 240 struct pci_dev *cdev; 241 struct pci_bus *cbus; 242 struct list_head head; 243 struct resource_wrap *w; 244 unsigned int bres; 245 246 *size = *align = 0; 247 248 pr_devel("-> CBR %s [%x]\n", 249 bus->self ? pci_name(bus->self) : "root", flags); 250 251 /* Calculate alignment requirements based on the type 252 * of resource we are working on 253 */ 254 if (flags & IORESOURCE_IO) { 255 bres = 0; 256 min_align = phb->ioda.io_segsize; 257 min_balign = 0x1000; 258 } else { 259 bres = 1; 260 min_align = phb->ioda.m32_segsize; 261 min_balign = 0x100000; 262 } 263 264 /* Gather all our children resources ordered by alignment */ 265 INIT_LIST_HEAD(&head); 266 267 /* - Busses */ 268 list_for_each_entry(cbus, &bus->children, node) { 269 pnv_ioda_calc_bus(cbus, flags, &dev_size, &dev_align); 270 pnv_ioda_add_wrap(&head, cbus, NULL, dev_size, dev_align); 271 } 272 273 /* - Devices */ 274 list_for_each_entry(cdev, &bus->devices, bus_list) { 275 pnv_ioda_calc_dev(cdev, flags, &dev_size, &dev_align); 276 /* Align them to segment size */ 277 if (dev_align < min_align) 278 dev_align = min_align; 279 pnv_ioda_add_wrap(&head, NULL, cdev, dev_size, dev_align); 280 } 281 if (list_empty(&head)) 282 goto empty; 283 284 /* Now we can do two things: assign offsets to them within that 285 * level and get our total alignment & size requirements. The 286 * assignment algorithm is going to be uber-trivial for now, we 287 * can try to be smarter later at filling out holes. 288 */ 289 if (bus->self) { 290 /* No offset for downstream bridges */ 291 start = 0; 292 } else { 293 /* Offset from the root */ 294 if (flags & IORESOURCE_IO) 295 /* Don't hand out IO 0 */ 296 start = hose->io_resource.start + 0x1000; 297 else 298 start = hose->mem_resources[0].start; 299 } 300 while(!list_empty(&head)) { 301 w = list_first_entry(&head, struct resource_wrap, link); 302 list_del(&w->link); 303 if (w->size) { 304 if (start) { 305 start = ALIGN(start, w->align); 306 if (w->dev) 307 pnv_ioda_offset_dev(w->dev,flags,start); 308 else if (w->bus) 309 pnv_ioda_offset_bus(w->bus,flags,start); 310 } 311 if (w->align > *align) 312 *align = w->align; 313 } 314 start += w->size; 315 kfree(w); 316 } 317 *size = start; 318 319 /* Align and setup bridge resources */ 320 *align = max_t(resource_size_t, *align, 321 max_t(resource_size_t, min_align, min_balign)); 322 *size = ALIGN(*size, 323 max_t(resource_size_t, min_align, min_balign)); 324 empty: 325 /* Only setup P2P's, not the PHB itself */ 326 if (bus->self) { 327 struct resource *res = bus->resource[bres]; 328 329 if (WARN_ON(res == NULL)) 330 return; 331 332 /* 333 * FIXME: We should probably export and call 334 * pci_bridge_check_ranges() to properly re-initialize 335 * the PCI portion of the flags here, and to detect 336 * what the bridge actually supports. 337 */ 338 res->start = 0; 339 res->flags = (*size) ? flags : 0; 340 res->end = (*size) ? (*size - 1) : 0; 341 } 342 343 pr_devel("<- CBR %s [%x] *size=%016llx *align=%016llx\n", 344 bus->self ? pci_name(bus->self) : "root", flags,*size,*align); 345 } 346 347 static struct pci_dn *pnv_ioda_get_pdn(struct pci_dev *dev) 348 { 349 struct device_node *np; 350 351 np = pci_device_to_OF_node(dev); 352 if (!np) 353 return NULL; 354 return PCI_DN(np); 355 } 356 357 static void __devinit pnv_ioda_setup_pe_segments(struct pci_dev *dev) 358 { 359 struct pci_controller *hose = pci_bus_to_host(dev->bus); 360 struct pnv_phb *phb = hose->private_data; 361 struct pci_dn *pdn = pnv_ioda_get_pdn(dev); 362 unsigned int pe, i; 363 resource_size_t pos; 364 struct resource io_res; 365 struct resource m32_res; 366 struct pci_bus_region region; 367 int rc; 368 369 /* Anything not referenced in the device-tree gets PE#0 */ 370 pe = pdn ? pdn->pe_number : 0; 371 372 /* Calculate the device min/max */ 373 io_res.start = m32_res.start = (resource_size_t)-1; 374 io_res.end = m32_res.end = 0; 375 io_res.flags = IORESOURCE_IO; 376 m32_res.flags = IORESOURCE_MEM; 377 378 for (i = 0; i <= PCI_ROM_RESOURCE; i++) { 379 struct resource *r = NULL; 380 if (dev->resource[i].flags & IORESOURCE_IO) 381 r = &io_res; 382 if (dev->resource[i].flags & IORESOURCE_MEM) 383 r = &m32_res; 384 if (!r) 385 continue; 386 if (dev->resource[i].start < r->start) 387 r->start = dev->resource[i].start; 388 if (dev->resource[i].end > r->end) 389 r->end = dev->resource[i].end; 390 } 391 392 /* Setup IO segments */ 393 if (io_res.start < io_res.end) { 394 pcibios_resource_to_bus(dev, ®ion, &io_res); 395 pos = region.start; 396 i = pos / phb->ioda.io_segsize; 397 while(i < phb->ioda.total_pe && pos <= region.end) { 398 if (phb->ioda.io_segmap[i]) { 399 pr_err("%s: Trying to use IO seg #%d which is" 400 " already used by PE# %d\n", 401 pci_name(dev), i, 402 phb->ioda.io_segmap[i]); 403 /* XXX DO SOMETHING TO DISABLE DEVICE ? */ 404 break; 405 } 406 phb->ioda.io_segmap[i] = pe; 407 rc = opal_pci_map_pe_mmio_window(phb->opal_id, pe, 408 OPAL_IO_WINDOW_TYPE, 409 0, i); 410 if (rc != OPAL_SUCCESS) { 411 pr_err("%s: OPAL error %d setting up mapping" 412 " for IO seg# %d\n", 413 pci_name(dev), rc, i); 414 /* XXX DO SOMETHING TO DISABLE DEVICE ? */ 415 break; 416 } 417 pos += phb->ioda.io_segsize; 418 i++; 419 }; 420 } 421 422 /* Setup M32 segments */ 423 if (m32_res.start < m32_res.end) { 424 pcibios_resource_to_bus(dev, ®ion, &m32_res); 425 pos = region.start; 426 i = pos / phb->ioda.m32_segsize; 427 while(i < phb->ioda.total_pe && pos <= region.end) { 428 if (phb->ioda.m32_segmap[i]) { 429 pr_err("%s: Trying to use M32 seg #%d which is" 430 " already used by PE# %d\n", 431 pci_name(dev), i, 432 phb->ioda.m32_segmap[i]); 433 /* XXX DO SOMETHING TO DISABLE DEVICE ? */ 434 break; 435 } 436 phb->ioda.m32_segmap[i] = pe; 437 rc = opal_pci_map_pe_mmio_window(phb->opal_id, pe, 438 OPAL_M32_WINDOW_TYPE, 439 0, i); 440 if (rc != OPAL_SUCCESS) { 441 pr_err("%s: OPAL error %d setting up mapping" 442 " for M32 seg# %d\n", 443 pci_name(dev), rc, i); 444 /* XXX DO SOMETHING TO DISABLE DEVICE ? */ 445 break; 446 } 447 pos += phb->ioda.m32_segsize; 448 i++; 449 } 450 } 451 } 452 453 /* Check if a resource still fits in the total IO or M32 range 454 * for a given PHB 455 */ 456 static int __devinit pnv_ioda_resource_fit(struct pci_controller *hose, 457 struct resource *r) 458 { 459 struct resource *bounds; 460 461 if (r->flags & IORESOURCE_IO) 462 bounds = &hose->io_resource; 463 else if (r->flags & IORESOURCE_MEM) 464 bounds = &hose->mem_resources[0]; 465 else 466 return 1; 467 468 if (r->start >= bounds->start && r->end <= bounds->end) 469 return 1; 470 r->flags = 0; 471 return 0; 472 } 473 474 static void __devinit pnv_ioda_update_resources(struct pci_bus *bus) 475 { 476 struct pci_controller *hose = pci_bus_to_host(bus); 477 struct pci_bus *cbus; 478 struct pci_dev *cdev; 479 unsigned int i; 480 481 /* We used to clear all device enables here. However it looks like 482 * clearing MEM enable causes Obsidian (IPR SCS) to go bonkers, 483 * and shoot fatal errors to the PHB which in turns fences itself 484 * and we can't recover from that ... yet. So for now, let's leave 485 * the enables as-is and hope for the best. 486 */ 487 488 /* Check if bus resources fit in our IO or M32 range */ 489 for (i = 0; bus->self && (i < 2); i++) { 490 struct resource *r = bus->resource[i]; 491 if (r && !pnv_ioda_resource_fit(hose, r)) 492 pr_err("%s: Bus %d resource %d disabled, no room\n", 493 pci_name(bus->self), bus->number, i); 494 } 495 496 /* Update self if it's not a PHB */ 497 if (bus->self) 498 pci_setup_bridge(bus); 499 500 /* Update child devices */ 501 list_for_each_entry(cdev, &bus->devices, bus_list) { 502 /* Check if resource fits, if not, disabled it */ 503 for (i = 0; i <= PCI_ROM_RESOURCE; i++) { 504 struct resource *r = &cdev->resource[i]; 505 if (!pnv_ioda_resource_fit(hose, r)) 506 pr_err("%s: Resource %d disabled, no room\n", 507 pci_name(cdev), i); 508 } 509 510 /* Assign segments */ 511 pnv_ioda_setup_pe_segments(cdev); 512 513 /* Update HW BARs */ 514 for (i = 0; i <= PCI_ROM_RESOURCE; i++) 515 pci_update_resource(cdev, i); 516 } 517 518 /* Update child busses */ 519 list_for_each_entry(cbus, &bus->children, node) 520 pnv_ioda_update_resources(cbus); 521 } 522 523 static int __devinit pnv_ioda_alloc_pe(struct pnv_phb *phb) 524 { 525 unsigned long pe; 526 527 do { 528 pe = find_next_zero_bit(phb->ioda.pe_alloc, 529 phb->ioda.total_pe, 0); 530 if (pe >= phb->ioda.total_pe) 531 return IODA_INVALID_PE; 532 } while(test_and_set_bit(pe, phb->ioda.pe_alloc)); 533 534 phb->ioda.pe_array[pe].pe_number = pe; 535 return pe; 536 } 537 538 static void __devinit pnv_ioda_free_pe(struct pnv_phb *phb, int pe) 539 { 540 WARN_ON(phb->ioda.pe_array[pe].pdev); 541 542 memset(&phb->ioda.pe_array[pe], 0, sizeof(struct pnv_ioda_pe)); 543 clear_bit(pe, phb->ioda.pe_alloc); 544 } 545 546 /* Currently those 2 are only used when MSIs are enabled, this will change 547 * but in the meantime, we need to protect them to avoid warnings 548 */ 549 #ifdef CONFIG_PCI_MSI 550 static struct pnv_ioda_pe * __devinit pnv_ioda_get_pe(struct pci_dev *dev) 551 { 552 struct pci_controller *hose = pci_bus_to_host(dev->bus); 553 struct pnv_phb *phb = hose->private_data; 554 struct pci_dn *pdn = pnv_ioda_get_pdn(dev); 555 556 if (!pdn) 557 return NULL; 558 if (pdn->pe_number == IODA_INVALID_PE) 559 return NULL; 560 return &phb->ioda.pe_array[pdn->pe_number]; 561 } 562 #endif /* CONFIG_PCI_MSI */ 563 564 static int __devinit pnv_ioda_configure_pe(struct pnv_phb *phb, 565 struct pnv_ioda_pe *pe) 566 { 567 struct pci_dev *parent; 568 uint8_t bcomp, dcomp, fcomp; 569 long rc, rid_end, rid; 570 571 /* Bus validation ? */ 572 if (pe->pbus) { 573 int count; 574 575 dcomp = OPAL_IGNORE_RID_DEVICE_NUMBER; 576 fcomp = OPAL_IGNORE_RID_FUNCTION_NUMBER; 577 parent = pe->pbus->self; 578 if (pe->flags & PNV_IODA_PE_BUS_ALL) 579 count = pe->pbus->busn_res.end - pe->pbus->busn_res.start + 1; 580 else 581 count = 1; 582 583 switch(count) { 584 case 1: bcomp = OpalPciBusAll; break; 585 case 2: bcomp = OpalPciBus7Bits; break; 586 case 4: bcomp = OpalPciBus6Bits; break; 587 case 8: bcomp = OpalPciBus5Bits; break; 588 case 16: bcomp = OpalPciBus4Bits; break; 589 case 32: bcomp = OpalPciBus3Bits; break; 590 default: 591 pr_err("%s: Number of subordinate busses %d" 592 " unsupported\n", 593 pci_name(pe->pbus->self), count); 594 /* Do an exact match only */ 595 bcomp = OpalPciBusAll; 596 } 597 rid_end = pe->rid + (count << 8); 598 } else { 599 parent = pe->pdev->bus->self; 600 bcomp = OpalPciBusAll; 601 dcomp = OPAL_COMPARE_RID_DEVICE_NUMBER; 602 fcomp = OPAL_COMPARE_RID_FUNCTION_NUMBER; 603 rid_end = pe->rid + 1; 604 } 605 606 /* Associate PE in PELT */ 607 rc = opal_pci_set_pe(phb->opal_id, pe->pe_number, pe->rid, 608 bcomp, dcomp, fcomp, OPAL_MAP_PE); 609 if (rc) { 610 pe_err(pe, "OPAL error %ld trying to setup PELT table\n", rc); 611 return -ENXIO; 612 } 613 opal_pci_eeh_freeze_clear(phb->opal_id, pe->pe_number, 614 OPAL_EEH_ACTION_CLEAR_FREEZE_ALL); 615 616 /* Add to all parents PELT-V */ 617 while (parent) { 618 struct pci_dn *pdn = pnv_ioda_get_pdn(parent); 619 if (pdn && pdn->pe_number != IODA_INVALID_PE) { 620 rc = opal_pci_set_peltv(phb->opal_id, pdn->pe_number, 621 pe->pe_number, OPAL_ADD_PE_TO_DOMAIN); 622 /* XXX What to do in case of error ? */ 623 } 624 parent = parent->bus->self; 625 } 626 /* Setup reverse map */ 627 for (rid = pe->rid; rid < rid_end; rid++) 628 phb->ioda.pe_rmap[rid] = pe->pe_number; 629 630 /* Setup one MVTs on IODA1 */ 631 if (phb->type == PNV_PHB_IODA1) { 632 pe->mve_number = pe->pe_number; 633 rc = opal_pci_set_mve(phb->opal_id, pe->mve_number, 634 pe->pe_number); 635 if (rc) { 636 pe_err(pe, "OPAL error %ld setting up MVE %d\n", 637 rc, pe->mve_number); 638 pe->mve_number = -1; 639 } else { 640 rc = opal_pci_set_mve_enable(phb->opal_id, 641 pe->mve_number, OPAL_ENABLE_MVE); 642 if (rc) { 643 pe_err(pe, "OPAL error %ld enabling MVE %d\n", 644 rc, pe->mve_number); 645 pe->mve_number = -1; 646 } 647 } 648 } else if (phb->type == PNV_PHB_IODA2) 649 pe->mve_number = 0; 650 651 return 0; 652 } 653 654 static void __devinit pnv_ioda_link_pe_by_weight(struct pnv_phb *phb, 655 struct pnv_ioda_pe *pe) 656 { 657 struct pnv_ioda_pe *lpe; 658 659 list_for_each_entry(lpe, &phb->ioda.pe_dma_list, dma_link) { 660 if (lpe->dma_weight < pe->dma_weight) { 661 list_add_tail(&pe->dma_link, &lpe->dma_link); 662 return; 663 } 664 } 665 list_add_tail(&pe->dma_link, &phb->ioda.pe_dma_list); 666 } 667 668 static unsigned int pnv_ioda_dma_weight(struct pci_dev *dev) 669 { 670 /* This is quite simplistic. The "base" weight of a device 671 * is 10. 0 means no DMA is to be accounted for it. 672 */ 673 674 /* If it's a bridge, no DMA */ 675 if (dev->hdr_type != PCI_HEADER_TYPE_NORMAL) 676 return 0; 677 678 /* Reduce the weight of slow USB controllers */ 679 if (dev->class == PCI_CLASS_SERIAL_USB_UHCI || 680 dev->class == PCI_CLASS_SERIAL_USB_OHCI || 681 dev->class == PCI_CLASS_SERIAL_USB_EHCI) 682 return 3; 683 684 /* Increase the weight of RAID (includes Obsidian) */ 685 if ((dev->class >> 8) == PCI_CLASS_STORAGE_RAID) 686 return 15; 687 688 /* Default */ 689 return 10; 690 } 691 692 #if 0 693 static struct pnv_ioda_pe * __devinit pnv_ioda_setup_dev_PE(struct pci_dev *dev) 694 { 695 struct pci_controller *hose = pci_bus_to_host(dev->bus); 696 struct pnv_phb *phb = hose->private_data; 697 struct pci_dn *pdn = pnv_ioda_get_pdn(dev); 698 struct pnv_ioda_pe *pe; 699 int pe_num; 700 701 if (!pdn) { 702 pr_err("%s: Device tree node not associated properly\n", 703 pci_name(dev)); 704 return NULL; 705 } 706 if (pdn->pe_number != IODA_INVALID_PE) 707 return NULL; 708 709 /* PE#0 has been pre-set */ 710 if (dev->bus->number == 0) 711 pe_num = 0; 712 else 713 pe_num = pnv_ioda_alloc_pe(phb); 714 if (pe_num == IODA_INVALID_PE) { 715 pr_warning("%s: Not enough PE# available, disabling device\n", 716 pci_name(dev)); 717 return NULL; 718 } 719 720 /* NOTE: We get only one ref to the pci_dev for the pdn, not for the 721 * pointer in the PE data structure, both should be destroyed at the 722 * same time. However, this needs to be looked at more closely again 723 * once we actually start removing things (Hotplug, SR-IOV, ...) 724 * 725 * At some point we want to remove the PDN completely anyways 726 */ 727 pe = &phb->ioda.pe_array[pe_num]; 728 pci_dev_get(dev); 729 pdn->pcidev = dev; 730 pdn->pe_number = pe_num; 731 pe->pdev = dev; 732 pe->pbus = NULL; 733 pe->tce32_seg = -1; 734 pe->mve_number = -1; 735 pe->rid = dev->bus->number << 8 | pdn->devfn; 736 737 pe_info(pe, "Associated device to PE\n"); 738 739 if (pnv_ioda_configure_pe(phb, pe)) { 740 /* XXX What do we do here ? */ 741 if (pe_num) 742 pnv_ioda_free_pe(phb, pe_num); 743 pdn->pe_number = IODA_INVALID_PE; 744 pe->pdev = NULL; 745 pci_dev_put(dev); 746 return NULL; 747 } 748 749 /* Assign a DMA weight to the device */ 750 pe->dma_weight = pnv_ioda_dma_weight(dev); 751 if (pe->dma_weight != 0) { 752 phb->ioda.dma_weight += pe->dma_weight; 753 phb->ioda.dma_pe_count++; 754 } 755 756 /* Link the PE */ 757 pnv_ioda_link_pe_by_weight(phb, pe); 758 759 return pe; 760 } 761 #endif /* Useful for SRIOV case */ 762 763 static void pnv_ioda_setup_same_PE(struct pci_bus *bus, struct pnv_ioda_pe *pe) 764 { 765 struct pci_dev *dev; 766 767 list_for_each_entry(dev, &bus->devices, bus_list) { 768 struct pci_dn *pdn = pnv_ioda_get_pdn(dev); 769 770 if (pdn == NULL) { 771 pr_warn("%s: No device node associated with device !\n", 772 pci_name(dev)); 773 continue; 774 } 775 pci_dev_get(dev); 776 pdn->pcidev = dev; 777 pdn->pe_number = pe->pe_number; 778 pe->dma_weight += pnv_ioda_dma_weight(dev); 779 if ((pe->flags & PNV_IODA_PE_BUS_ALL) && dev->subordinate) 780 pnv_ioda_setup_same_PE(dev->subordinate, pe); 781 } 782 } 783 784 /* 785 * There're 2 types of PCI bus sensitive PEs: One that is compromised of 786 * single PCI bus. Another one that contains the primary PCI bus and its 787 * subordinate PCI devices and buses. The second type of PE is normally 788 * orgiriated by PCIe-to-PCI bridge or PLX switch downstream ports. 789 */ 790 static void __devinit pnv_ioda_setup_bus_PE(struct pci_bus *bus, int all) 791 { 792 struct pci_controller *hose = pci_bus_to_host(bus); 793 struct pnv_phb *phb = hose->private_data; 794 struct pnv_ioda_pe *pe; 795 int pe_num; 796 797 pe_num = pnv_ioda_alloc_pe(phb); 798 if (pe_num == IODA_INVALID_PE) { 799 pr_warning("%s: Not enough PE# available for PCI bus %04x:%02x\n", 800 __func__, pci_domain_nr(bus), bus->number); 801 return; 802 } 803 804 pe = &phb->ioda.pe_array[pe_num]; 805 pe->flags = (all ? PNV_IODA_PE_BUS_ALL : PNV_IODA_PE_BUS); 806 pe->pbus = bus; 807 pe->pdev = NULL; 808 pe->tce32_seg = -1; 809 pe->mve_number = -1; 810 pe->rid = bus->busn_res.start << 8; 811 pe->dma_weight = 0; 812 813 if (all) 814 pe_info(pe, "Secondary bus %d..%d associated with PE#%d\n", 815 bus->busn_res.start, bus->busn_res.end, pe_num); 816 else 817 pe_info(pe, "Secondary bus %d associated with PE#%d\n", 818 bus->busn_res.start, pe_num); 819 820 if (pnv_ioda_configure_pe(phb, pe)) { 821 /* XXX What do we do here ? */ 822 if (pe_num) 823 pnv_ioda_free_pe(phb, pe_num); 824 pe->pbus = NULL; 825 return; 826 } 827 828 /* Associate it with all child devices */ 829 pnv_ioda_setup_same_PE(bus, pe); 830 831 /* Put PE to the list */ 832 list_add_tail(&pe->list, &phb->ioda.pe_list); 833 834 /* Account for one DMA PE if at least one DMA capable device exist 835 * below the bridge 836 */ 837 if (pe->dma_weight != 0) { 838 phb->ioda.dma_weight += pe->dma_weight; 839 phb->ioda.dma_pe_count++; 840 } 841 842 /* Link the PE */ 843 pnv_ioda_link_pe_by_weight(phb, pe); 844 } 845 846 static void __devinit pnv_ioda_setup_PEs(struct pci_bus *bus) 847 { 848 struct pci_dev *dev; 849 850 pnv_ioda_setup_bus_PE(bus, 0); 851 852 list_for_each_entry(dev, &bus->devices, bus_list) { 853 if (dev->subordinate) { 854 if (pci_pcie_type(dev) == PCI_EXP_TYPE_PCI_BRIDGE) 855 pnv_ioda_setup_bus_PE(dev->subordinate, 1); 856 else 857 pnv_ioda_setup_PEs(dev->subordinate); 858 } 859 } 860 } 861 862 /* 863 * Configure PEs so that the downstream PCI buses and devices 864 * could have their associated PE#. Unfortunately, we didn't 865 * figure out the way to identify the PLX bridge yet. So we 866 * simply put the PCI bus and the subordinate behind the root 867 * port to PE# here. The game rule here is expected to be changed 868 * as soon as we can detected PLX bridge correctly. 869 */ 870 static void __devinit pnv_pci_ioda_setup_PEs(void) 871 { 872 struct pci_controller *hose, *tmp; 873 874 list_for_each_entry_safe(hose, tmp, &hose_list, list_node) { 875 pnv_ioda_setup_PEs(hose->bus); 876 } 877 } 878 879 static void __devinit pnv_pci_ioda_dma_dev_setup(struct pnv_phb *phb, 880 struct pci_dev *dev) 881 { 882 /* We delay DMA setup after we have assigned all PE# */ 883 } 884 885 static void __devinit pnv_ioda_setup_bus_dma(struct pnv_ioda_pe *pe, 886 struct pci_bus *bus) 887 { 888 struct pci_dev *dev; 889 890 list_for_each_entry(dev, &bus->devices, bus_list) { 891 set_iommu_table_base(&dev->dev, &pe->tce32_table); 892 if (dev->subordinate) 893 pnv_ioda_setup_bus_dma(pe, dev->subordinate); 894 } 895 } 896 897 static void __devinit pnv_pci_ioda_setup_dma_pe(struct pnv_phb *phb, 898 struct pnv_ioda_pe *pe, 899 unsigned int base, 900 unsigned int segs) 901 { 902 903 struct page *tce_mem = NULL; 904 const __be64 *swinvp; 905 struct iommu_table *tbl; 906 unsigned int i; 907 int64_t rc; 908 void *addr; 909 910 /* 256M DMA window, 4K TCE pages, 8 bytes TCE */ 911 #define TCE32_TABLE_SIZE ((0x10000000 / 0x1000) * 8) 912 913 /* XXX FIXME: Handle 64-bit only DMA devices */ 914 /* XXX FIXME: Provide 64-bit DMA facilities & non-4K TCE tables etc.. */ 915 /* XXX FIXME: Allocate multi-level tables on PHB3 */ 916 917 /* We shouldn't already have a 32-bit DMA associated */ 918 if (WARN_ON(pe->tce32_seg >= 0)) 919 return; 920 921 /* Grab a 32-bit TCE table */ 922 pe->tce32_seg = base; 923 pe_info(pe, " Setting up 32-bit TCE table at %08x..%08x\n", 924 (base << 28), ((base + segs) << 28) - 1); 925 926 /* XXX Currently, we allocate one big contiguous table for the 927 * TCEs. We only really need one chunk per 256M of TCE space 928 * (ie per segment) but that's an optimization for later, it 929 * requires some added smarts with our get/put_tce implementation 930 */ 931 tce_mem = alloc_pages_node(phb->hose->node, GFP_KERNEL, 932 get_order(TCE32_TABLE_SIZE * segs)); 933 if (!tce_mem) { 934 pe_err(pe, " Failed to allocate a 32-bit TCE memory\n"); 935 goto fail; 936 } 937 addr = page_address(tce_mem); 938 memset(addr, 0, TCE32_TABLE_SIZE * segs); 939 940 /* Configure HW */ 941 for (i = 0; i < segs; i++) { 942 rc = opal_pci_map_pe_dma_window(phb->opal_id, 943 pe->pe_number, 944 base + i, 1, 945 __pa(addr) + TCE32_TABLE_SIZE * i, 946 TCE32_TABLE_SIZE, 0x1000); 947 if (rc) { 948 pe_err(pe, " Failed to configure 32-bit TCE table," 949 " err %ld\n", rc); 950 goto fail; 951 } 952 } 953 954 /* Setup linux iommu table */ 955 tbl = &pe->tce32_table; 956 pnv_pci_setup_iommu_table(tbl, addr, TCE32_TABLE_SIZE * segs, 957 base << 28); 958 959 /* OPAL variant of P7IOC SW invalidated TCEs */ 960 swinvp = of_get_property(phb->hose->dn, "ibm,opal-tce-kill", NULL); 961 if (swinvp) { 962 /* We need a couple more fields -- an address and a data 963 * to or. Since the bus is only printed out on table free 964 * errors, and on the first pass the data will be a relative 965 * bus number, print that out instead. 966 */ 967 tbl->it_busno = 0; 968 tbl->it_index = (unsigned long)ioremap(be64_to_cpup(swinvp), 8); 969 tbl->it_type = TCE_PCI_SWINV_CREATE | TCE_PCI_SWINV_FREE 970 | TCE_PCI_SWINV_PAIR; 971 } 972 iommu_init_table(tbl, phb->hose->node); 973 974 if (pe->pdev) 975 set_iommu_table_base(&pe->pdev->dev, tbl); 976 else 977 pnv_ioda_setup_bus_dma(pe, pe->pbus); 978 979 return; 980 fail: 981 /* XXX Failure: Try to fallback to 64-bit only ? */ 982 if (pe->tce32_seg >= 0) 983 pe->tce32_seg = -1; 984 if (tce_mem) 985 __free_pages(tce_mem, get_order(TCE32_TABLE_SIZE * segs)); 986 } 987 988 static void __devinit pnv_ioda_setup_dma(struct pnv_phb *phb) 989 { 990 struct pci_controller *hose = phb->hose; 991 unsigned int residual, remaining, segs, tw, base; 992 struct pnv_ioda_pe *pe; 993 994 /* If we have more PE# than segments available, hand out one 995 * per PE until we run out and let the rest fail. If not, 996 * then we assign at least one segment per PE, plus more based 997 * on the amount of devices under that PE 998 */ 999 if (phb->ioda.dma_pe_count > phb->ioda.tce32_count) 1000 residual = 0; 1001 else 1002 residual = phb->ioda.tce32_count - 1003 phb->ioda.dma_pe_count; 1004 1005 pr_info("PCI: Domain %04x has %ld available 32-bit DMA segments\n", 1006 hose->global_number, phb->ioda.tce32_count); 1007 pr_info("PCI: %d PE# for a total weight of %d\n", 1008 phb->ioda.dma_pe_count, phb->ioda.dma_weight); 1009 1010 /* Walk our PE list and configure their DMA segments, hand them 1011 * out one base segment plus any residual segments based on 1012 * weight 1013 */ 1014 remaining = phb->ioda.tce32_count; 1015 tw = phb->ioda.dma_weight; 1016 base = 0; 1017 list_for_each_entry(pe, &phb->ioda.pe_dma_list, dma_link) { 1018 if (!pe->dma_weight) 1019 continue; 1020 if (!remaining) { 1021 pe_warn(pe, "No DMA32 resources available\n"); 1022 continue; 1023 } 1024 segs = 1; 1025 if (residual) { 1026 segs += ((pe->dma_weight * residual) + (tw / 2)) / tw; 1027 if (segs > remaining) 1028 segs = remaining; 1029 } 1030 pe_info(pe, "DMA weight %d, assigned %d DMA32 segments\n", 1031 pe->dma_weight, segs); 1032 pnv_pci_ioda_setup_dma_pe(phb, pe, base, segs); 1033 remaining -= segs; 1034 base += segs; 1035 } 1036 } 1037 1038 #ifdef CONFIG_PCI_MSI 1039 static int pnv_pci_ioda_msi_setup(struct pnv_phb *phb, struct pci_dev *dev, 1040 unsigned int hwirq, unsigned int is_64, 1041 struct msi_msg *msg) 1042 { 1043 struct pnv_ioda_pe *pe = pnv_ioda_get_pe(dev); 1044 unsigned int xive_num = hwirq - phb->msi_base; 1045 uint64_t addr64; 1046 uint32_t addr32, data; 1047 int rc; 1048 1049 /* No PE assigned ? bail out ... no MSI for you ! */ 1050 if (pe == NULL) 1051 return -ENXIO; 1052 1053 /* Check if we have an MVE */ 1054 if (pe->mve_number < 0) 1055 return -ENXIO; 1056 1057 /* Assign XIVE to PE */ 1058 rc = opal_pci_set_xive_pe(phb->opal_id, pe->pe_number, xive_num); 1059 if (rc) { 1060 pr_warn("%s: OPAL error %d setting XIVE %d PE\n", 1061 pci_name(dev), rc, xive_num); 1062 return -EIO; 1063 } 1064 1065 if (is_64) { 1066 rc = opal_get_msi_64(phb->opal_id, pe->mve_number, xive_num, 1, 1067 &addr64, &data); 1068 if (rc) { 1069 pr_warn("%s: OPAL error %d getting 64-bit MSI data\n", 1070 pci_name(dev), rc); 1071 return -EIO; 1072 } 1073 msg->address_hi = addr64 >> 32; 1074 msg->address_lo = addr64 & 0xfffffffful; 1075 } else { 1076 rc = opal_get_msi_32(phb->opal_id, pe->mve_number, xive_num, 1, 1077 &addr32, &data); 1078 if (rc) { 1079 pr_warn("%s: OPAL error %d getting 32-bit MSI data\n", 1080 pci_name(dev), rc); 1081 return -EIO; 1082 } 1083 msg->address_hi = 0; 1084 msg->address_lo = addr32; 1085 } 1086 msg->data = data; 1087 1088 pr_devel("%s: %s-bit MSI on hwirq %x (xive #%d)," 1089 " address=%x_%08x data=%x PE# %d\n", 1090 pci_name(dev), is_64 ? "64" : "32", hwirq, xive_num, 1091 msg->address_hi, msg->address_lo, data, pe->pe_number); 1092 1093 return 0; 1094 } 1095 1096 static void pnv_pci_init_ioda_msis(struct pnv_phb *phb) 1097 { 1098 unsigned int bmap_size; 1099 const __be32 *prop = of_get_property(phb->hose->dn, 1100 "ibm,opal-msi-ranges", NULL); 1101 if (!prop) { 1102 /* BML Fallback */ 1103 prop = of_get_property(phb->hose->dn, "msi-ranges", NULL); 1104 } 1105 if (!prop) 1106 return; 1107 1108 phb->msi_base = be32_to_cpup(prop); 1109 phb->msi_count = be32_to_cpup(prop + 1); 1110 bmap_size = BITS_TO_LONGS(phb->msi_count) * sizeof(unsigned long); 1111 phb->msi_map = zalloc_maybe_bootmem(bmap_size, GFP_KERNEL); 1112 if (!phb->msi_map) { 1113 pr_err("PCI %d: Failed to allocate MSI bitmap !\n", 1114 phb->hose->global_number); 1115 return; 1116 } 1117 phb->msi_setup = pnv_pci_ioda_msi_setup; 1118 phb->msi32_support = 1; 1119 pr_info(" Allocated bitmap for %d MSIs (base IRQ 0x%x)\n", 1120 phb->msi_count, phb->msi_base); 1121 } 1122 #else 1123 static void pnv_pci_init_ioda_msis(struct pnv_phb *phb) { } 1124 #endif /* CONFIG_PCI_MSI */ 1125 1126 /* This is the starting point of our IODA specific resource 1127 * allocation process 1128 */ 1129 static void __devinit pnv_pci_ioda_fixup_phb(struct pci_controller *hose) 1130 { 1131 resource_size_t size, align; 1132 struct pci_bus *child; 1133 1134 /* Associate PEs per functions */ 1135 pnv_ioda_setup_PEs(hose->bus); 1136 1137 /* Calculate all resources */ 1138 pnv_ioda_calc_bus(hose->bus, IORESOURCE_IO, &size, &align); 1139 pnv_ioda_calc_bus(hose->bus, IORESOURCE_MEM, &size, &align); 1140 1141 /* Apply then to HW */ 1142 pnv_ioda_update_resources(hose->bus); 1143 1144 /* Setup DMA */ 1145 pnv_ioda_setup_dma(hose->private_data); 1146 1147 /* Configure PCI Express settings */ 1148 list_for_each_entry(child, &hose->bus->children, node) { 1149 struct pci_dev *self = child->self; 1150 if (!self) 1151 continue; 1152 pcie_bus_configure_settings(child, self->pcie_mpss); 1153 } 1154 } 1155 1156 /* 1157 * This function is supposed to be called on basis of PE from top 1158 * to bottom style. So the the I/O or MMIO segment assigned to 1159 * parent PE could be overrided by its child PEs if necessary. 1160 */ 1161 static void __devinit pnv_ioda_setup_pe_seg(struct pci_controller *hose, 1162 struct pnv_ioda_pe *pe) 1163 { 1164 struct pnv_phb *phb = hose->private_data; 1165 struct pci_bus_region region; 1166 struct resource *res; 1167 int i, index; 1168 int rc; 1169 1170 /* 1171 * NOTE: We only care PCI bus based PE for now. For PCI 1172 * device based PE, for example SRIOV sensitive VF should 1173 * be figured out later. 1174 */ 1175 BUG_ON(!(pe->flags & (PNV_IODA_PE_BUS | PNV_IODA_PE_BUS_ALL))); 1176 1177 pci_bus_for_each_resource(pe->pbus, res, i) { 1178 if (!res || !res->flags || 1179 res->start > res->end) 1180 continue; 1181 1182 if (res->flags & IORESOURCE_IO) { 1183 region.start = res->start - phb->ioda.io_pci_base; 1184 region.end = res->end - phb->ioda.io_pci_base; 1185 index = region.start / phb->ioda.io_segsize; 1186 1187 while (index < phb->ioda.total_pe && 1188 region.start <= region.end) { 1189 phb->ioda.io_segmap[index] = pe->pe_number; 1190 rc = opal_pci_map_pe_mmio_window(phb->opal_id, 1191 pe->pe_number, OPAL_IO_WINDOW_TYPE, 0, index); 1192 if (rc != OPAL_SUCCESS) { 1193 pr_err("%s: OPAL error %d when mapping IO " 1194 "segment #%d to PE#%d\n", 1195 __func__, rc, index, pe->pe_number); 1196 break; 1197 } 1198 1199 region.start += phb->ioda.io_segsize; 1200 index++; 1201 } 1202 } else if (res->flags & IORESOURCE_MEM) { 1203 region.start = res->start - 1204 hose->pci_mem_offset - 1205 phb->ioda.m32_pci_base; 1206 region.end = res->end - 1207 hose->pci_mem_offset - 1208 phb->ioda.m32_pci_base; 1209 index = region.start / phb->ioda.m32_segsize; 1210 1211 while (index < phb->ioda.total_pe && 1212 region.start <= region.end) { 1213 phb->ioda.m32_segmap[index] = pe->pe_number; 1214 rc = opal_pci_map_pe_mmio_window(phb->opal_id, 1215 pe->pe_number, OPAL_M32_WINDOW_TYPE, 0, index); 1216 if (rc != OPAL_SUCCESS) { 1217 pr_err("%s: OPAL error %d when mapping M32 " 1218 "segment#%d to PE#%d", 1219 __func__, rc, index, pe->pe_number); 1220 break; 1221 } 1222 1223 region.start += phb->ioda.m32_segsize; 1224 index++; 1225 } 1226 } 1227 } 1228 } 1229 1230 static void __devinit pnv_pci_ioda_setup_seg(void) 1231 { 1232 struct pci_controller *tmp, *hose; 1233 struct pnv_phb *phb; 1234 struct pnv_ioda_pe *pe; 1235 1236 list_for_each_entry_safe(hose, tmp, &hose_list, list_node) { 1237 phb = hose->private_data; 1238 list_for_each_entry(pe, &phb->ioda.pe_list, list) { 1239 pnv_ioda_setup_pe_seg(hose, pe); 1240 } 1241 } 1242 } 1243 1244 static void __devinit pnv_pci_ioda_fixup(void) 1245 { 1246 pnv_pci_ioda_setup_PEs(); 1247 pnv_pci_ioda_setup_seg(); 1248 } 1249 1250 /* 1251 * Returns the alignment for I/O or memory windows for P2P 1252 * bridges. That actually depends on how PEs are segmented. 1253 * For now, we return I/O or M32 segment size for PE sensitive 1254 * P2P bridges. Otherwise, the default values (4KiB for I/O, 1255 * 1MiB for memory) will be returned. 1256 * 1257 * The current PCI bus might be put into one PE, which was 1258 * create against the parent PCI bridge. For that case, we 1259 * needn't enlarge the alignment so that we can save some 1260 * resources. 1261 */ 1262 static resource_size_t pnv_pci_window_alignment(struct pci_bus *bus, 1263 unsigned long type) 1264 { 1265 struct pci_dev *bridge; 1266 struct pci_controller *hose = pci_bus_to_host(bus); 1267 struct pnv_phb *phb = hose->private_data; 1268 int num_pci_bridges = 0; 1269 1270 bridge = bus->self; 1271 while (bridge) { 1272 if (pci_pcie_type(bridge) == PCI_EXP_TYPE_PCI_BRIDGE) { 1273 num_pci_bridges++; 1274 if (num_pci_bridges >= 2) 1275 return 1; 1276 } 1277 1278 bridge = bridge->bus->self; 1279 } 1280 1281 /* We need support prefetchable memory window later */ 1282 if (type & IORESOURCE_MEM) 1283 return phb->ioda.m32_segsize; 1284 1285 return phb->ioda.io_segsize; 1286 } 1287 1288 /* Prevent enabling devices for which we couldn't properly 1289 * assign a PE 1290 */ 1291 static int __devinit pnv_pci_enable_device_hook(struct pci_dev *dev) 1292 { 1293 struct pci_dn *pdn = pnv_ioda_get_pdn(dev); 1294 1295 if (!pdn || pdn->pe_number == IODA_INVALID_PE) 1296 return -EINVAL; 1297 return 0; 1298 } 1299 1300 static u32 pnv_ioda_bdfn_to_pe(struct pnv_phb *phb, struct pci_bus *bus, 1301 u32 devfn) 1302 { 1303 return phb->ioda.pe_rmap[(bus->number << 8) | devfn]; 1304 } 1305 1306 void __init pnv_pci_init_ioda1_phb(struct device_node *np) 1307 { 1308 struct pci_controller *hose; 1309 static int primary = 1; 1310 struct pnv_phb *phb; 1311 unsigned long size, m32map_off, iomap_off, pemap_off; 1312 const u64 *prop64; 1313 u64 phb_id; 1314 void *aux; 1315 long rc; 1316 1317 pr_info(" Initializing IODA OPAL PHB %s\n", np->full_name); 1318 1319 prop64 = of_get_property(np, "ibm,opal-phbid", NULL); 1320 if (!prop64) { 1321 pr_err(" Missing \"ibm,opal-phbid\" property !\n"); 1322 return; 1323 } 1324 phb_id = be64_to_cpup(prop64); 1325 pr_debug(" PHB-ID : 0x%016llx\n", phb_id); 1326 1327 phb = alloc_bootmem(sizeof(struct pnv_phb)); 1328 if (phb) { 1329 memset(phb, 0, sizeof(struct pnv_phb)); 1330 phb->hose = hose = pcibios_alloc_controller(np); 1331 } 1332 if (!phb || !phb->hose) { 1333 pr_err("PCI: Failed to allocate PCI controller for %s\n", 1334 np->full_name); 1335 return; 1336 } 1337 1338 spin_lock_init(&phb->lock); 1339 /* XXX Use device-tree */ 1340 hose->first_busno = 0; 1341 hose->last_busno = 0xff; 1342 hose->private_data = phb; 1343 phb->opal_id = phb_id; 1344 phb->type = PNV_PHB_IODA1; 1345 1346 /* Detect specific models for error handling */ 1347 if (of_device_is_compatible(np, "ibm,p7ioc-pciex")) 1348 phb->model = PNV_PHB_MODEL_P7IOC; 1349 else 1350 phb->model = PNV_PHB_MODEL_UNKNOWN; 1351 1352 /* We parse "ranges" now since we need to deduce the register base 1353 * from the IO base 1354 */ 1355 pci_process_bridge_OF_ranges(phb->hose, np, primary); 1356 primary = 0; 1357 1358 /* Magic formula from Milton */ 1359 phb->regs = of_iomap(np, 0); 1360 if (phb->regs == NULL) 1361 pr_err(" Failed to map registers !\n"); 1362 1363 1364 /* XXX This is hack-a-thon. This needs to be changed so that: 1365 * - we obtain stuff like PE# etc... from device-tree 1366 * - we properly re-allocate M32 ourselves 1367 * (the OFW one isn't very good) 1368 */ 1369 1370 /* Initialize more IODA stuff */ 1371 phb->ioda.total_pe = 128; 1372 1373 phb->ioda.m32_size = resource_size(&hose->mem_resources[0]); 1374 /* OFW Has already off top 64k of M32 space (MSI space) */ 1375 phb->ioda.m32_size += 0x10000; 1376 1377 phb->ioda.m32_segsize = phb->ioda.m32_size / phb->ioda.total_pe; 1378 phb->ioda.m32_pci_base = hose->mem_resources[0].start - 1379 hose->pci_mem_offset; 1380 phb->ioda.io_size = hose->pci_io_size; 1381 phb->ioda.io_segsize = phb->ioda.io_size / phb->ioda.total_pe; 1382 phb->ioda.io_pci_base = 0; /* XXX calculate this ? */ 1383 1384 /* Allocate aux data & arrays */ 1385 size = _ALIGN_UP(phb->ioda.total_pe / 8, sizeof(unsigned long)); 1386 m32map_off = size; 1387 size += phb->ioda.total_pe; 1388 iomap_off = size; 1389 size += phb->ioda.total_pe; 1390 pemap_off = size; 1391 size += phb->ioda.total_pe * sizeof(struct pnv_ioda_pe); 1392 aux = alloc_bootmem(size); 1393 memset(aux, 0, size); 1394 phb->ioda.pe_alloc = aux; 1395 phb->ioda.m32_segmap = aux + m32map_off; 1396 phb->ioda.io_segmap = aux + iomap_off; 1397 phb->ioda.pe_array = aux + pemap_off; 1398 set_bit(0, phb->ioda.pe_alloc); 1399 1400 INIT_LIST_HEAD(&phb->ioda.pe_dma_list); 1401 INIT_LIST_HEAD(&phb->ioda.pe_list); 1402 1403 /* Calculate how many 32-bit TCE segments we have */ 1404 phb->ioda.tce32_count = phb->ioda.m32_pci_base >> 28; 1405 1406 /* Clear unusable m64 */ 1407 hose->mem_resources[1].flags = 0; 1408 hose->mem_resources[1].start = 0; 1409 hose->mem_resources[1].end = 0; 1410 hose->mem_resources[2].flags = 0; 1411 hose->mem_resources[2].start = 0; 1412 hose->mem_resources[2].end = 0; 1413 1414 #if 0 1415 rc = opal_pci_set_phb_mem_window(opal->phb_id, 1416 window_type, 1417 window_num, 1418 starting_real_address, 1419 starting_pci_address, 1420 segment_size); 1421 #endif 1422 1423 pr_info(" %d PE's M32: 0x%x [segment=0x%x] IO: 0x%x [segment=0x%x]\n", 1424 phb->ioda.total_pe, 1425 phb->ioda.m32_size, phb->ioda.m32_segsize, 1426 phb->ioda.io_size, phb->ioda.io_segsize); 1427 1428 if (phb->regs) { 1429 pr_devel(" BUID = 0x%016llx\n", in_be64(phb->regs + 0x100)); 1430 pr_devel(" PHB2_CR = 0x%016llx\n", in_be64(phb->regs + 0x160)); 1431 pr_devel(" IO_BAR = 0x%016llx\n", in_be64(phb->regs + 0x170)); 1432 pr_devel(" IO_BAMR = 0x%016llx\n", in_be64(phb->regs + 0x178)); 1433 pr_devel(" IO_SAR = 0x%016llx\n", in_be64(phb->regs + 0x180)); 1434 pr_devel(" M32_BAR = 0x%016llx\n", in_be64(phb->regs + 0x190)); 1435 pr_devel(" M32_BAMR = 0x%016llx\n", in_be64(phb->regs + 0x198)); 1436 pr_devel(" M32_SAR = 0x%016llx\n", in_be64(phb->regs + 0x1a0)); 1437 } 1438 phb->hose->ops = &pnv_pci_ops; 1439 1440 /* Setup RID -> PE mapping function */ 1441 phb->bdfn_to_pe = pnv_ioda_bdfn_to_pe; 1442 1443 /* Setup TCEs */ 1444 phb->dma_dev_setup = pnv_pci_ioda_dma_dev_setup; 1445 1446 /* Setup MSI support */ 1447 pnv_pci_init_ioda_msis(phb); 1448 1449 /* We set both PCI_PROBE_ONLY and PCI_REASSIGN_ALL_RSRC. This is an 1450 * odd combination which essentially means that we skip all resource 1451 * fixups and assignments in the generic code, and do it all 1452 * ourselves here 1453 */ 1454 ppc_md.pcibios_fixup_phb = pnv_pci_ioda_fixup_phb; 1455 ppc_md.pcibios_fixup = pnv_pci_ioda_fixup; 1456 ppc_md.pcibios_enable_device_hook = pnv_pci_enable_device_hook; 1457 ppc_md.pcibios_window_alignment = pnv_pci_window_alignment; 1458 pci_add_flags(PCI_PROBE_ONLY | PCI_REASSIGN_ALL_RSRC); 1459 1460 /* Reset IODA tables to a clean state */ 1461 rc = opal_pci_reset(phb_id, OPAL_PCI_IODA_TABLE_RESET, OPAL_ASSERT_RESET); 1462 if (rc) 1463 pr_warning(" OPAL Error %ld performing IODA table reset !\n", rc); 1464 opal_pci_set_pe(phb_id, 0, 0, 7, 1, 1 , OPAL_MAP_PE); 1465 } 1466 1467 void __init pnv_pci_init_ioda_hub(struct device_node *np) 1468 { 1469 struct device_node *phbn; 1470 const u64 *prop64; 1471 u64 hub_id; 1472 1473 pr_info("Probing IODA IO-Hub %s\n", np->full_name); 1474 1475 prop64 = of_get_property(np, "ibm,opal-hubid", NULL); 1476 if (!prop64) { 1477 pr_err(" Missing \"ibm,opal-hubid\" property !\n"); 1478 return; 1479 } 1480 hub_id = be64_to_cpup(prop64); 1481 pr_devel(" HUB-ID : 0x%016llx\n", hub_id); 1482 1483 /* Count child PHBs */ 1484 for_each_child_of_node(np, phbn) { 1485 /* Look for IODA1 PHBs */ 1486 if (of_device_is_compatible(phbn, "ibm,ioda-phb")) 1487 pnv_pci_init_ioda1_phb(phbn); 1488 } 1489 } 1490