1 /* 2 * Support PCI/PCIe on PowerNV platforms 3 * 4 * Copyright 2011 Benjamin Herrenschmidt, IBM Corp. 5 * 6 * This program is free software; you can redistribute it and/or 7 * modify it under the terms of the GNU General Public License 8 * as published by the Free Software Foundation; either version 9 * 2 of the License, or (at your option) any later version. 10 */ 11 12 #undef DEBUG 13 14 #include <linux/kernel.h> 15 #include <linux/pci.h> 16 #include <linux/crash_dump.h> 17 #include <linux/delay.h> 18 #include <linux/string.h> 19 #include <linux/init.h> 20 #include <linux/bootmem.h> 21 #include <linux/irq.h> 22 #include <linux/io.h> 23 #include <linux/msi.h> 24 #include <linux/memblock.h> 25 #include <linux/iommu.h> 26 #include <linux/rculist.h> 27 #include <linux/sizes.h> 28 29 #include <asm/sections.h> 30 #include <asm/io.h> 31 #include <asm/prom.h> 32 #include <asm/pci-bridge.h> 33 #include <asm/machdep.h> 34 #include <asm/msi_bitmap.h> 35 #include <asm/ppc-pci.h> 36 #include <asm/opal.h> 37 #include <asm/iommu.h> 38 #include <asm/tce.h> 39 #include <asm/xics.h> 40 #include <asm/debugfs.h> 41 #include <asm/firmware.h> 42 #include <asm/pnv-pci.h> 43 #include <asm/mmzone.h> 44 45 #include <misc/cxl-base.h> 46 47 #include "powernv.h" 48 #include "pci.h" 49 50 #define PNV_IODA1_M64_NUM 16 /* Number of M64 BARs */ 51 #define PNV_IODA1_M64_SEGS 8 /* Segments per M64 BAR */ 52 #define PNV_IODA1_DMA32_SEGSIZE 0x10000000 53 54 #define POWERNV_IOMMU_DEFAULT_LEVELS 1 55 #define POWERNV_IOMMU_MAX_LEVELS 5 56 57 static const char * const pnv_phb_names[] = { "IODA1", "IODA2", "NPU_NVLINK", 58 "NPU_OCAPI" }; 59 static void pnv_pci_ioda2_table_free_pages(struct iommu_table *tbl); 60 61 void pe_level_printk(const struct pnv_ioda_pe *pe, const char *level, 62 const char *fmt, ...) 63 { 64 struct va_format vaf; 65 va_list args; 66 char pfix[32]; 67 68 va_start(args, fmt); 69 70 vaf.fmt = fmt; 71 vaf.va = &args; 72 73 if (pe->flags & PNV_IODA_PE_DEV) 74 strlcpy(pfix, dev_name(&pe->pdev->dev), sizeof(pfix)); 75 else if (pe->flags & (PNV_IODA_PE_BUS | PNV_IODA_PE_BUS_ALL)) 76 sprintf(pfix, "%04x:%02x ", 77 pci_domain_nr(pe->pbus), pe->pbus->number); 78 #ifdef CONFIG_PCI_IOV 79 else if (pe->flags & PNV_IODA_PE_VF) 80 sprintf(pfix, "%04x:%02x:%2x.%d", 81 pci_domain_nr(pe->parent_dev->bus), 82 (pe->rid & 0xff00) >> 8, 83 PCI_SLOT(pe->rid), PCI_FUNC(pe->rid)); 84 #endif /* CONFIG_PCI_IOV*/ 85 86 printk("%spci %s: [PE# %.2x] %pV", 87 level, pfix, pe->pe_number, &vaf); 88 89 va_end(args); 90 } 91 92 static bool pnv_iommu_bypass_disabled __read_mostly; 93 static bool pci_reset_phbs __read_mostly; 94 95 static int __init iommu_setup(char *str) 96 { 97 if (!str) 98 return -EINVAL; 99 100 while (*str) { 101 if (!strncmp(str, "nobypass", 8)) { 102 pnv_iommu_bypass_disabled = true; 103 pr_info("PowerNV: IOMMU bypass window disabled.\n"); 104 break; 105 } 106 str += strcspn(str, ","); 107 if (*str == ',') 108 str++; 109 } 110 111 return 0; 112 } 113 early_param("iommu", iommu_setup); 114 115 static int __init pci_reset_phbs_setup(char *str) 116 { 117 pci_reset_phbs = true; 118 return 0; 119 } 120 121 early_param("ppc_pci_reset_phbs", pci_reset_phbs_setup); 122 123 static inline bool pnv_pci_is_m64(struct pnv_phb *phb, struct resource *r) 124 { 125 /* 126 * WARNING: We cannot rely on the resource flags. The Linux PCI 127 * allocation code sometimes decides to put a 64-bit prefetchable 128 * BAR in the 32-bit window, so we have to compare the addresses. 129 * 130 * For simplicity we only test resource start. 131 */ 132 return (r->start >= phb->ioda.m64_base && 133 r->start < (phb->ioda.m64_base + phb->ioda.m64_size)); 134 } 135 136 static inline bool pnv_pci_is_m64_flags(unsigned long resource_flags) 137 { 138 unsigned long flags = (IORESOURCE_MEM_64 | IORESOURCE_PREFETCH); 139 140 return (resource_flags & flags) == flags; 141 } 142 143 static struct pnv_ioda_pe *pnv_ioda_init_pe(struct pnv_phb *phb, int pe_no) 144 { 145 s64 rc; 146 147 phb->ioda.pe_array[pe_no].phb = phb; 148 phb->ioda.pe_array[pe_no].pe_number = pe_no; 149 150 /* 151 * Clear the PE frozen state as it might be put into frozen state 152 * in the last PCI remove path. It's not harmful to do so when the 153 * PE is already in unfrozen state. 154 */ 155 rc = opal_pci_eeh_freeze_clear(phb->opal_id, pe_no, 156 OPAL_EEH_ACTION_CLEAR_FREEZE_ALL); 157 if (rc != OPAL_SUCCESS && rc != OPAL_UNSUPPORTED) 158 pr_warn("%s: Error %lld unfreezing PHB#%x-PE#%x\n", 159 __func__, rc, phb->hose->global_number, pe_no); 160 161 return &phb->ioda.pe_array[pe_no]; 162 } 163 164 static void pnv_ioda_reserve_pe(struct pnv_phb *phb, int pe_no) 165 { 166 if (!(pe_no >= 0 && pe_no < phb->ioda.total_pe_num)) { 167 pr_warn("%s: Invalid PE %x on PHB#%x\n", 168 __func__, pe_no, phb->hose->global_number); 169 return; 170 } 171 172 if (test_and_set_bit(pe_no, phb->ioda.pe_alloc)) 173 pr_debug("%s: PE %x was reserved on PHB#%x\n", 174 __func__, pe_no, phb->hose->global_number); 175 176 pnv_ioda_init_pe(phb, pe_no); 177 } 178 179 static struct pnv_ioda_pe *pnv_ioda_alloc_pe(struct pnv_phb *phb) 180 { 181 long pe; 182 183 for (pe = phb->ioda.total_pe_num - 1; pe >= 0; pe--) { 184 if (!test_and_set_bit(pe, phb->ioda.pe_alloc)) 185 return pnv_ioda_init_pe(phb, pe); 186 } 187 188 return NULL; 189 } 190 191 static void pnv_ioda_free_pe(struct pnv_ioda_pe *pe) 192 { 193 struct pnv_phb *phb = pe->phb; 194 unsigned int pe_num = pe->pe_number; 195 196 WARN_ON(pe->pdev); 197 198 memset(pe, 0, sizeof(struct pnv_ioda_pe)); 199 clear_bit(pe_num, phb->ioda.pe_alloc); 200 } 201 202 /* The default M64 BAR is shared by all PEs */ 203 static int pnv_ioda2_init_m64(struct pnv_phb *phb) 204 { 205 const char *desc; 206 struct resource *r; 207 s64 rc; 208 209 /* Configure the default M64 BAR */ 210 rc = opal_pci_set_phb_mem_window(phb->opal_id, 211 OPAL_M64_WINDOW_TYPE, 212 phb->ioda.m64_bar_idx, 213 phb->ioda.m64_base, 214 0, /* unused */ 215 phb->ioda.m64_size); 216 if (rc != OPAL_SUCCESS) { 217 desc = "configuring"; 218 goto fail; 219 } 220 221 /* Enable the default M64 BAR */ 222 rc = opal_pci_phb_mmio_enable(phb->opal_id, 223 OPAL_M64_WINDOW_TYPE, 224 phb->ioda.m64_bar_idx, 225 OPAL_ENABLE_M64_SPLIT); 226 if (rc != OPAL_SUCCESS) { 227 desc = "enabling"; 228 goto fail; 229 } 230 231 /* 232 * Exclude the segments for reserved and root bus PE, which 233 * are first or last two PEs. 234 */ 235 r = &phb->hose->mem_resources[1]; 236 if (phb->ioda.reserved_pe_idx == 0) 237 r->start += (2 * phb->ioda.m64_segsize); 238 else if (phb->ioda.reserved_pe_idx == (phb->ioda.total_pe_num - 1)) 239 r->end -= (2 * phb->ioda.m64_segsize); 240 else 241 pr_warn(" Cannot strip M64 segment for reserved PE#%x\n", 242 phb->ioda.reserved_pe_idx); 243 244 return 0; 245 246 fail: 247 pr_warn(" Failure %lld %s M64 BAR#%d\n", 248 rc, desc, phb->ioda.m64_bar_idx); 249 opal_pci_phb_mmio_enable(phb->opal_id, 250 OPAL_M64_WINDOW_TYPE, 251 phb->ioda.m64_bar_idx, 252 OPAL_DISABLE_M64); 253 return -EIO; 254 } 255 256 static void pnv_ioda_reserve_dev_m64_pe(struct pci_dev *pdev, 257 unsigned long *pe_bitmap) 258 { 259 struct pci_controller *hose = pci_bus_to_host(pdev->bus); 260 struct pnv_phb *phb = hose->private_data; 261 struct resource *r; 262 resource_size_t base, sgsz, start, end; 263 int segno, i; 264 265 base = phb->ioda.m64_base; 266 sgsz = phb->ioda.m64_segsize; 267 for (i = 0; i <= PCI_ROM_RESOURCE; i++) { 268 r = &pdev->resource[i]; 269 if (!r->parent || !pnv_pci_is_m64(phb, r)) 270 continue; 271 272 start = _ALIGN_DOWN(r->start - base, sgsz); 273 end = _ALIGN_UP(r->end - base, sgsz); 274 for (segno = start / sgsz; segno < end / sgsz; segno++) { 275 if (pe_bitmap) 276 set_bit(segno, pe_bitmap); 277 else 278 pnv_ioda_reserve_pe(phb, segno); 279 } 280 } 281 } 282 283 static int pnv_ioda1_init_m64(struct pnv_phb *phb) 284 { 285 struct resource *r; 286 int index; 287 288 /* 289 * There are 16 M64 BARs, each of which has 8 segments. So 290 * there are as many M64 segments as the maximum number of 291 * PEs, which is 128. 292 */ 293 for (index = 0; index < PNV_IODA1_M64_NUM; index++) { 294 unsigned long base, segsz = phb->ioda.m64_segsize; 295 int64_t rc; 296 297 base = phb->ioda.m64_base + 298 index * PNV_IODA1_M64_SEGS * segsz; 299 rc = opal_pci_set_phb_mem_window(phb->opal_id, 300 OPAL_M64_WINDOW_TYPE, index, base, 0, 301 PNV_IODA1_M64_SEGS * segsz); 302 if (rc != OPAL_SUCCESS) { 303 pr_warn(" Error %lld setting M64 PHB#%x-BAR#%d\n", 304 rc, phb->hose->global_number, index); 305 goto fail; 306 } 307 308 rc = opal_pci_phb_mmio_enable(phb->opal_id, 309 OPAL_M64_WINDOW_TYPE, index, 310 OPAL_ENABLE_M64_SPLIT); 311 if (rc != OPAL_SUCCESS) { 312 pr_warn(" Error %lld enabling M64 PHB#%x-BAR#%d\n", 313 rc, phb->hose->global_number, index); 314 goto fail; 315 } 316 } 317 318 /* 319 * Exclude the segments for reserved and root bus PE, which 320 * are first or last two PEs. 321 */ 322 r = &phb->hose->mem_resources[1]; 323 if (phb->ioda.reserved_pe_idx == 0) 324 r->start += (2 * phb->ioda.m64_segsize); 325 else if (phb->ioda.reserved_pe_idx == (phb->ioda.total_pe_num - 1)) 326 r->end -= (2 * phb->ioda.m64_segsize); 327 else 328 WARN(1, "Wrong reserved PE#%x on PHB#%x\n", 329 phb->ioda.reserved_pe_idx, phb->hose->global_number); 330 331 return 0; 332 333 fail: 334 for ( ; index >= 0; index--) 335 opal_pci_phb_mmio_enable(phb->opal_id, 336 OPAL_M64_WINDOW_TYPE, index, OPAL_DISABLE_M64); 337 338 return -EIO; 339 } 340 341 static void pnv_ioda_reserve_m64_pe(struct pci_bus *bus, 342 unsigned long *pe_bitmap, 343 bool all) 344 { 345 struct pci_dev *pdev; 346 347 list_for_each_entry(pdev, &bus->devices, bus_list) { 348 pnv_ioda_reserve_dev_m64_pe(pdev, pe_bitmap); 349 350 if (all && pdev->subordinate) 351 pnv_ioda_reserve_m64_pe(pdev->subordinate, 352 pe_bitmap, all); 353 } 354 } 355 356 static struct pnv_ioda_pe *pnv_ioda_pick_m64_pe(struct pci_bus *bus, bool all) 357 { 358 struct pci_controller *hose = pci_bus_to_host(bus); 359 struct pnv_phb *phb = hose->private_data; 360 struct pnv_ioda_pe *master_pe, *pe; 361 unsigned long size, *pe_alloc; 362 int i; 363 364 /* Root bus shouldn't use M64 */ 365 if (pci_is_root_bus(bus)) 366 return NULL; 367 368 /* Allocate bitmap */ 369 size = _ALIGN_UP(phb->ioda.total_pe_num / 8, sizeof(unsigned long)); 370 pe_alloc = kzalloc(size, GFP_KERNEL); 371 if (!pe_alloc) { 372 pr_warn("%s: Out of memory !\n", 373 __func__); 374 return NULL; 375 } 376 377 /* Figure out reserved PE numbers by the PE */ 378 pnv_ioda_reserve_m64_pe(bus, pe_alloc, all); 379 380 /* 381 * the current bus might not own M64 window and that's all 382 * contributed by its child buses. For the case, we needn't 383 * pick M64 dependent PE#. 384 */ 385 if (bitmap_empty(pe_alloc, phb->ioda.total_pe_num)) { 386 kfree(pe_alloc); 387 return NULL; 388 } 389 390 /* 391 * Figure out the master PE and put all slave PEs to master 392 * PE's list to form compound PE. 393 */ 394 master_pe = NULL; 395 i = -1; 396 while ((i = find_next_bit(pe_alloc, phb->ioda.total_pe_num, i + 1)) < 397 phb->ioda.total_pe_num) { 398 pe = &phb->ioda.pe_array[i]; 399 400 phb->ioda.m64_segmap[pe->pe_number] = pe->pe_number; 401 if (!master_pe) { 402 pe->flags |= PNV_IODA_PE_MASTER; 403 INIT_LIST_HEAD(&pe->slaves); 404 master_pe = pe; 405 } else { 406 pe->flags |= PNV_IODA_PE_SLAVE; 407 pe->master = master_pe; 408 list_add_tail(&pe->list, &master_pe->slaves); 409 } 410 411 /* 412 * P7IOC supports M64DT, which helps mapping M64 segment 413 * to one particular PE#. However, PHB3 has fixed mapping 414 * between M64 segment and PE#. In order to have same logic 415 * for P7IOC and PHB3, we enforce fixed mapping between M64 416 * segment and PE# on P7IOC. 417 */ 418 if (phb->type == PNV_PHB_IODA1) { 419 int64_t rc; 420 421 rc = opal_pci_map_pe_mmio_window(phb->opal_id, 422 pe->pe_number, OPAL_M64_WINDOW_TYPE, 423 pe->pe_number / PNV_IODA1_M64_SEGS, 424 pe->pe_number % PNV_IODA1_M64_SEGS); 425 if (rc != OPAL_SUCCESS) 426 pr_warn("%s: Error %lld mapping M64 for PHB#%x-PE#%x\n", 427 __func__, rc, phb->hose->global_number, 428 pe->pe_number); 429 } 430 } 431 432 kfree(pe_alloc); 433 return master_pe; 434 } 435 436 static void __init pnv_ioda_parse_m64_window(struct pnv_phb *phb) 437 { 438 struct pci_controller *hose = phb->hose; 439 struct device_node *dn = hose->dn; 440 struct resource *res; 441 u32 m64_range[2], i; 442 const __be32 *r; 443 u64 pci_addr; 444 445 if (phb->type != PNV_PHB_IODA1 && phb->type != PNV_PHB_IODA2) { 446 pr_info(" Not support M64 window\n"); 447 return; 448 } 449 450 if (!firmware_has_feature(FW_FEATURE_OPAL)) { 451 pr_info(" Firmware too old to support M64 window\n"); 452 return; 453 } 454 455 r = of_get_property(dn, "ibm,opal-m64-window", NULL); 456 if (!r) { 457 pr_info(" No <ibm,opal-m64-window> on %pOF\n", 458 dn); 459 return; 460 } 461 462 /* 463 * Find the available M64 BAR range and pickup the last one for 464 * covering the whole 64-bits space. We support only one range. 465 */ 466 if (of_property_read_u32_array(dn, "ibm,opal-available-m64-ranges", 467 m64_range, 2)) { 468 /* In absence of the property, assume 0..15 */ 469 m64_range[0] = 0; 470 m64_range[1] = 16; 471 } 472 /* We only support 64 bits in our allocator */ 473 if (m64_range[1] > 63) { 474 pr_warn("%s: Limiting M64 range to 63 (from %d) on PHB#%x\n", 475 __func__, m64_range[1], phb->hose->global_number); 476 m64_range[1] = 63; 477 } 478 /* Empty range, no m64 */ 479 if (m64_range[1] <= m64_range[0]) { 480 pr_warn("%s: M64 empty, disabling M64 usage on PHB#%x\n", 481 __func__, phb->hose->global_number); 482 return; 483 } 484 485 /* Configure M64 informations */ 486 res = &hose->mem_resources[1]; 487 res->name = dn->full_name; 488 res->start = of_translate_address(dn, r + 2); 489 res->end = res->start + of_read_number(r + 4, 2) - 1; 490 res->flags = (IORESOURCE_MEM | IORESOURCE_MEM_64 | IORESOURCE_PREFETCH); 491 pci_addr = of_read_number(r, 2); 492 hose->mem_offset[1] = res->start - pci_addr; 493 494 phb->ioda.m64_size = resource_size(res); 495 phb->ioda.m64_segsize = phb->ioda.m64_size / phb->ioda.total_pe_num; 496 phb->ioda.m64_base = pci_addr; 497 498 /* This lines up nicely with the display from processing OF ranges */ 499 pr_info(" MEM 0x%016llx..0x%016llx -> 0x%016llx (M64 #%d..%d)\n", 500 res->start, res->end, pci_addr, m64_range[0], 501 m64_range[0] + m64_range[1] - 1); 502 503 /* Mark all M64 used up by default */ 504 phb->ioda.m64_bar_alloc = (unsigned long)-1; 505 506 /* Use last M64 BAR to cover M64 window */ 507 m64_range[1]--; 508 phb->ioda.m64_bar_idx = m64_range[0] + m64_range[1]; 509 510 pr_info(" Using M64 #%d as default window\n", phb->ioda.m64_bar_idx); 511 512 /* Mark remaining ones free */ 513 for (i = m64_range[0]; i < m64_range[1]; i++) 514 clear_bit(i, &phb->ioda.m64_bar_alloc); 515 516 /* 517 * Setup init functions for M64 based on IODA version, IODA3 uses 518 * the IODA2 code. 519 */ 520 if (phb->type == PNV_PHB_IODA1) 521 phb->init_m64 = pnv_ioda1_init_m64; 522 else 523 phb->init_m64 = pnv_ioda2_init_m64; 524 phb->reserve_m64_pe = pnv_ioda_reserve_m64_pe; 525 phb->pick_m64_pe = pnv_ioda_pick_m64_pe; 526 } 527 528 static void pnv_ioda_freeze_pe(struct pnv_phb *phb, int pe_no) 529 { 530 struct pnv_ioda_pe *pe = &phb->ioda.pe_array[pe_no]; 531 struct pnv_ioda_pe *slave; 532 s64 rc; 533 534 /* Fetch master PE */ 535 if (pe->flags & PNV_IODA_PE_SLAVE) { 536 pe = pe->master; 537 if (WARN_ON(!pe || !(pe->flags & PNV_IODA_PE_MASTER))) 538 return; 539 540 pe_no = pe->pe_number; 541 } 542 543 /* Freeze master PE */ 544 rc = opal_pci_eeh_freeze_set(phb->opal_id, 545 pe_no, 546 OPAL_EEH_ACTION_SET_FREEZE_ALL); 547 if (rc != OPAL_SUCCESS) { 548 pr_warn("%s: Failure %lld freezing PHB#%x-PE#%x\n", 549 __func__, rc, phb->hose->global_number, pe_no); 550 return; 551 } 552 553 /* Freeze slave PEs */ 554 if (!(pe->flags & PNV_IODA_PE_MASTER)) 555 return; 556 557 list_for_each_entry(slave, &pe->slaves, list) { 558 rc = opal_pci_eeh_freeze_set(phb->opal_id, 559 slave->pe_number, 560 OPAL_EEH_ACTION_SET_FREEZE_ALL); 561 if (rc != OPAL_SUCCESS) 562 pr_warn("%s: Failure %lld freezing PHB#%x-PE#%x\n", 563 __func__, rc, phb->hose->global_number, 564 slave->pe_number); 565 } 566 } 567 568 static int pnv_ioda_unfreeze_pe(struct pnv_phb *phb, int pe_no, int opt) 569 { 570 struct pnv_ioda_pe *pe, *slave; 571 s64 rc; 572 573 /* Find master PE */ 574 pe = &phb->ioda.pe_array[pe_no]; 575 if (pe->flags & PNV_IODA_PE_SLAVE) { 576 pe = pe->master; 577 WARN_ON(!pe || !(pe->flags & PNV_IODA_PE_MASTER)); 578 pe_no = pe->pe_number; 579 } 580 581 /* Clear frozen state for master PE */ 582 rc = opal_pci_eeh_freeze_clear(phb->opal_id, pe_no, opt); 583 if (rc != OPAL_SUCCESS) { 584 pr_warn("%s: Failure %lld clear %d on PHB#%x-PE#%x\n", 585 __func__, rc, opt, phb->hose->global_number, pe_no); 586 return -EIO; 587 } 588 589 if (!(pe->flags & PNV_IODA_PE_MASTER)) 590 return 0; 591 592 /* Clear frozen state for slave PEs */ 593 list_for_each_entry(slave, &pe->slaves, list) { 594 rc = opal_pci_eeh_freeze_clear(phb->opal_id, 595 slave->pe_number, 596 opt); 597 if (rc != OPAL_SUCCESS) { 598 pr_warn("%s: Failure %lld clear %d on PHB#%x-PE#%x\n", 599 __func__, rc, opt, phb->hose->global_number, 600 slave->pe_number); 601 return -EIO; 602 } 603 } 604 605 return 0; 606 } 607 608 static int pnv_ioda_get_pe_state(struct pnv_phb *phb, int pe_no) 609 { 610 struct pnv_ioda_pe *slave, *pe; 611 u8 fstate, state; 612 __be16 pcierr; 613 s64 rc; 614 615 /* Sanity check on PE number */ 616 if (pe_no < 0 || pe_no >= phb->ioda.total_pe_num) 617 return OPAL_EEH_STOPPED_PERM_UNAVAIL; 618 619 /* 620 * Fetch the master PE and the PE instance might be 621 * not initialized yet. 622 */ 623 pe = &phb->ioda.pe_array[pe_no]; 624 if (pe->flags & PNV_IODA_PE_SLAVE) { 625 pe = pe->master; 626 WARN_ON(!pe || !(pe->flags & PNV_IODA_PE_MASTER)); 627 pe_no = pe->pe_number; 628 } 629 630 /* Check the master PE */ 631 rc = opal_pci_eeh_freeze_status(phb->opal_id, pe_no, 632 &state, &pcierr, NULL); 633 if (rc != OPAL_SUCCESS) { 634 pr_warn("%s: Failure %lld getting " 635 "PHB#%x-PE#%x state\n", 636 __func__, rc, 637 phb->hose->global_number, pe_no); 638 return OPAL_EEH_STOPPED_TEMP_UNAVAIL; 639 } 640 641 /* Check the slave PE */ 642 if (!(pe->flags & PNV_IODA_PE_MASTER)) 643 return state; 644 645 list_for_each_entry(slave, &pe->slaves, list) { 646 rc = opal_pci_eeh_freeze_status(phb->opal_id, 647 slave->pe_number, 648 &fstate, 649 &pcierr, 650 NULL); 651 if (rc != OPAL_SUCCESS) { 652 pr_warn("%s: Failure %lld getting " 653 "PHB#%x-PE#%x state\n", 654 __func__, rc, 655 phb->hose->global_number, slave->pe_number); 656 return OPAL_EEH_STOPPED_TEMP_UNAVAIL; 657 } 658 659 /* 660 * Override the result based on the ascending 661 * priority. 662 */ 663 if (fstate > state) 664 state = fstate; 665 } 666 667 return state; 668 } 669 670 /* Currently those 2 are only used when MSIs are enabled, this will change 671 * but in the meantime, we need to protect them to avoid warnings 672 */ 673 #ifdef CONFIG_PCI_MSI 674 struct pnv_ioda_pe *pnv_ioda_get_pe(struct pci_dev *dev) 675 { 676 struct pci_controller *hose = pci_bus_to_host(dev->bus); 677 struct pnv_phb *phb = hose->private_data; 678 struct pci_dn *pdn = pci_get_pdn(dev); 679 680 if (!pdn) 681 return NULL; 682 if (pdn->pe_number == IODA_INVALID_PE) 683 return NULL; 684 return &phb->ioda.pe_array[pdn->pe_number]; 685 } 686 #endif /* CONFIG_PCI_MSI */ 687 688 static int pnv_ioda_set_one_peltv(struct pnv_phb *phb, 689 struct pnv_ioda_pe *parent, 690 struct pnv_ioda_pe *child, 691 bool is_add) 692 { 693 const char *desc = is_add ? "adding" : "removing"; 694 uint8_t op = is_add ? OPAL_ADD_PE_TO_DOMAIN : 695 OPAL_REMOVE_PE_FROM_DOMAIN; 696 struct pnv_ioda_pe *slave; 697 long rc; 698 699 /* Parent PE affects child PE */ 700 rc = opal_pci_set_peltv(phb->opal_id, parent->pe_number, 701 child->pe_number, op); 702 if (rc != OPAL_SUCCESS) { 703 pe_warn(child, "OPAL error %ld %s to parent PELTV\n", 704 rc, desc); 705 return -ENXIO; 706 } 707 708 if (!(child->flags & PNV_IODA_PE_MASTER)) 709 return 0; 710 711 /* Compound case: parent PE affects slave PEs */ 712 list_for_each_entry(slave, &child->slaves, list) { 713 rc = opal_pci_set_peltv(phb->opal_id, parent->pe_number, 714 slave->pe_number, op); 715 if (rc != OPAL_SUCCESS) { 716 pe_warn(slave, "OPAL error %ld %s to parent PELTV\n", 717 rc, desc); 718 return -ENXIO; 719 } 720 } 721 722 return 0; 723 } 724 725 static int pnv_ioda_set_peltv(struct pnv_phb *phb, 726 struct pnv_ioda_pe *pe, 727 bool is_add) 728 { 729 struct pnv_ioda_pe *slave; 730 struct pci_dev *pdev = NULL; 731 int ret; 732 733 /* 734 * Clear PE frozen state. If it's master PE, we need 735 * clear slave PE frozen state as well. 736 */ 737 if (is_add) { 738 opal_pci_eeh_freeze_clear(phb->opal_id, pe->pe_number, 739 OPAL_EEH_ACTION_CLEAR_FREEZE_ALL); 740 if (pe->flags & PNV_IODA_PE_MASTER) { 741 list_for_each_entry(slave, &pe->slaves, list) 742 opal_pci_eeh_freeze_clear(phb->opal_id, 743 slave->pe_number, 744 OPAL_EEH_ACTION_CLEAR_FREEZE_ALL); 745 } 746 } 747 748 /* 749 * Associate PE in PELT. We need add the PE into the 750 * corresponding PELT-V as well. Otherwise, the error 751 * originated from the PE might contribute to other 752 * PEs. 753 */ 754 ret = pnv_ioda_set_one_peltv(phb, pe, pe, is_add); 755 if (ret) 756 return ret; 757 758 /* For compound PEs, any one affects all of them */ 759 if (pe->flags & PNV_IODA_PE_MASTER) { 760 list_for_each_entry(slave, &pe->slaves, list) { 761 ret = pnv_ioda_set_one_peltv(phb, slave, pe, is_add); 762 if (ret) 763 return ret; 764 } 765 } 766 767 if (pe->flags & (PNV_IODA_PE_BUS_ALL | PNV_IODA_PE_BUS)) 768 pdev = pe->pbus->self; 769 else if (pe->flags & PNV_IODA_PE_DEV) 770 pdev = pe->pdev->bus->self; 771 #ifdef CONFIG_PCI_IOV 772 else if (pe->flags & PNV_IODA_PE_VF) 773 pdev = pe->parent_dev; 774 #endif /* CONFIG_PCI_IOV */ 775 while (pdev) { 776 struct pci_dn *pdn = pci_get_pdn(pdev); 777 struct pnv_ioda_pe *parent; 778 779 if (pdn && pdn->pe_number != IODA_INVALID_PE) { 780 parent = &phb->ioda.pe_array[pdn->pe_number]; 781 ret = pnv_ioda_set_one_peltv(phb, parent, pe, is_add); 782 if (ret) 783 return ret; 784 } 785 786 pdev = pdev->bus->self; 787 } 788 789 return 0; 790 } 791 792 static int pnv_ioda_deconfigure_pe(struct pnv_phb *phb, struct pnv_ioda_pe *pe) 793 { 794 struct pci_dev *parent; 795 uint8_t bcomp, dcomp, fcomp; 796 int64_t rc; 797 long rid_end, rid; 798 799 /* Currently, we just deconfigure VF PE. Bus PE will always there.*/ 800 if (pe->pbus) { 801 int count; 802 803 dcomp = OPAL_IGNORE_RID_DEVICE_NUMBER; 804 fcomp = OPAL_IGNORE_RID_FUNCTION_NUMBER; 805 parent = pe->pbus->self; 806 if (pe->flags & PNV_IODA_PE_BUS_ALL) 807 count = pe->pbus->busn_res.end - pe->pbus->busn_res.start + 1; 808 else 809 count = 1; 810 811 switch(count) { 812 case 1: bcomp = OpalPciBusAll; break; 813 case 2: bcomp = OpalPciBus7Bits; break; 814 case 4: bcomp = OpalPciBus6Bits; break; 815 case 8: bcomp = OpalPciBus5Bits; break; 816 case 16: bcomp = OpalPciBus4Bits; break; 817 case 32: bcomp = OpalPciBus3Bits; break; 818 default: 819 dev_err(&pe->pbus->dev, "Number of subordinate buses %d unsupported\n", 820 count); 821 /* Do an exact match only */ 822 bcomp = OpalPciBusAll; 823 } 824 rid_end = pe->rid + (count << 8); 825 } else { 826 #ifdef CONFIG_PCI_IOV 827 if (pe->flags & PNV_IODA_PE_VF) 828 parent = pe->parent_dev; 829 else 830 #endif 831 parent = pe->pdev->bus->self; 832 bcomp = OpalPciBusAll; 833 dcomp = OPAL_COMPARE_RID_DEVICE_NUMBER; 834 fcomp = OPAL_COMPARE_RID_FUNCTION_NUMBER; 835 rid_end = pe->rid + 1; 836 } 837 838 /* Clear the reverse map */ 839 for (rid = pe->rid; rid < rid_end; rid++) 840 phb->ioda.pe_rmap[rid] = IODA_INVALID_PE; 841 842 /* Release from all parents PELT-V */ 843 while (parent) { 844 struct pci_dn *pdn = pci_get_pdn(parent); 845 if (pdn && pdn->pe_number != IODA_INVALID_PE) { 846 rc = opal_pci_set_peltv(phb->opal_id, pdn->pe_number, 847 pe->pe_number, OPAL_REMOVE_PE_FROM_DOMAIN); 848 /* XXX What to do in case of error ? */ 849 } 850 parent = parent->bus->self; 851 } 852 853 opal_pci_eeh_freeze_clear(phb->opal_id, pe->pe_number, 854 OPAL_EEH_ACTION_CLEAR_FREEZE_ALL); 855 856 /* Disassociate PE in PELT */ 857 rc = opal_pci_set_peltv(phb->opal_id, pe->pe_number, 858 pe->pe_number, OPAL_REMOVE_PE_FROM_DOMAIN); 859 if (rc) 860 pe_warn(pe, "OPAL error %ld remove self from PELTV\n", rc); 861 rc = opal_pci_set_pe(phb->opal_id, pe->pe_number, pe->rid, 862 bcomp, dcomp, fcomp, OPAL_UNMAP_PE); 863 if (rc) 864 pe_err(pe, "OPAL error %ld trying to setup PELT table\n", rc); 865 866 pe->pbus = NULL; 867 pe->pdev = NULL; 868 #ifdef CONFIG_PCI_IOV 869 pe->parent_dev = NULL; 870 #endif 871 872 return 0; 873 } 874 875 static int pnv_ioda_configure_pe(struct pnv_phb *phb, struct pnv_ioda_pe *pe) 876 { 877 struct pci_dev *parent; 878 uint8_t bcomp, dcomp, fcomp; 879 long rc, rid_end, rid; 880 881 /* Bus validation ? */ 882 if (pe->pbus) { 883 int count; 884 885 dcomp = OPAL_IGNORE_RID_DEVICE_NUMBER; 886 fcomp = OPAL_IGNORE_RID_FUNCTION_NUMBER; 887 parent = pe->pbus->self; 888 if (pe->flags & PNV_IODA_PE_BUS_ALL) 889 count = pe->pbus->busn_res.end - pe->pbus->busn_res.start + 1; 890 else 891 count = 1; 892 893 switch(count) { 894 case 1: bcomp = OpalPciBusAll; break; 895 case 2: bcomp = OpalPciBus7Bits; break; 896 case 4: bcomp = OpalPciBus6Bits; break; 897 case 8: bcomp = OpalPciBus5Bits; break; 898 case 16: bcomp = OpalPciBus4Bits; break; 899 case 32: bcomp = OpalPciBus3Bits; break; 900 default: 901 dev_err(&pe->pbus->dev, "Number of subordinate buses %d unsupported\n", 902 count); 903 /* Do an exact match only */ 904 bcomp = OpalPciBusAll; 905 } 906 rid_end = pe->rid + (count << 8); 907 } else { 908 #ifdef CONFIG_PCI_IOV 909 if (pe->flags & PNV_IODA_PE_VF) 910 parent = pe->parent_dev; 911 else 912 #endif /* CONFIG_PCI_IOV */ 913 parent = pe->pdev->bus->self; 914 bcomp = OpalPciBusAll; 915 dcomp = OPAL_COMPARE_RID_DEVICE_NUMBER; 916 fcomp = OPAL_COMPARE_RID_FUNCTION_NUMBER; 917 rid_end = pe->rid + 1; 918 } 919 920 /* 921 * Associate PE in PELT. We need add the PE into the 922 * corresponding PELT-V as well. Otherwise, the error 923 * originated from the PE might contribute to other 924 * PEs. 925 */ 926 rc = opal_pci_set_pe(phb->opal_id, pe->pe_number, pe->rid, 927 bcomp, dcomp, fcomp, OPAL_MAP_PE); 928 if (rc) { 929 pe_err(pe, "OPAL error %ld trying to setup PELT table\n", rc); 930 return -ENXIO; 931 } 932 933 /* 934 * Configure PELTV. NPUs don't have a PELTV table so skip 935 * configuration on them. 936 */ 937 if (phb->type != PNV_PHB_NPU_NVLINK && phb->type != PNV_PHB_NPU_OCAPI) 938 pnv_ioda_set_peltv(phb, pe, true); 939 940 /* Setup reverse map */ 941 for (rid = pe->rid; rid < rid_end; rid++) 942 phb->ioda.pe_rmap[rid] = pe->pe_number; 943 944 /* Setup one MVTs on IODA1 */ 945 if (phb->type != PNV_PHB_IODA1) { 946 pe->mve_number = 0; 947 goto out; 948 } 949 950 pe->mve_number = pe->pe_number; 951 rc = opal_pci_set_mve(phb->opal_id, pe->mve_number, pe->pe_number); 952 if (rc != OPAL_SUCCESS) { 953 pe_err(pe, "OPAL error %ld setting up MVE %x\n", 954 rc, pe->mve_number); 955 pe->mve_number = -1; 956 } else { 957 rc = opal_pci_set_mve_enable(phb->opal_id, 958 pe->mve_number, OPAL_ENABLE_MVE); 959 if (rc) { 960 pe_err(pe, "OPAL error %ld enabling MVE %x\n", 961 rc, pe->mve_number); 962 pe->mve_number = -1; 963 } 964 } 965 966 out: 967 return 0; 968 } 969 970 #ifdef CONFIG_PCI_IOV 971 static int pnv_pci_vf_resource_shift(struct pci_dev *dev, int offset) 972 { 973 struct pci_dn *pdn = pci_get_pdn(dev); 974 int i; 975 struct resource *res, res2; 976 resource_size_t size; 977 u16 num_vfs; 978 979 if (!dev->is_physfn) 980 return -EINVAL; 981 982 /* 983 * "offset" is in VFs. The M64 windows are sized so that when they 984 * are segmented, each segment is the same size as the IOV BAR. 985 * Each segment is in a separate PE, and the high order bits of the 986 * address are the PE number. Therefore, each VF's BAR is in a 987 * separate PE, and changing the IOV BAR start address changes the 988 * range of PEs the VFs are in. 989 */ 990 num_vfs = pdn->num_vfs; 991 for (i = 0; i < PCI_SRIOV_NUM_BARS; i++) { 992 res = &dev->resource[i + PCI_IOV_RESOURCES]; 993 if (!res->flags || !res->parent) 994 continue; 995 996 /* 997 * The actual IOV BAR range is determined by the start address 998 * and the actual size for num_vfs VFs BAR. This check is to 999 * make sure that after shifting, the range will not overlap 1000 * with another device. 1001 */ 1002 size = pci_iov_resource_size(dev, i + PCI_IOV_RESOURCES); 1003 res2.flags = res->flags; 1004 res2.start = res->start + (size * offset); 1005 res2.end = res2.start + (size * num_vfs) - 1; 1006 1007 if (res2.end > res->end) { 1008 dev_err(&dev->dev, "VF BAR%d: %pR would extend past %pR (trying to enable %d VFs shifted by %d)\n", 1009 i, &res2, res, num_vfs, offset); 1010 return -EBUSY; 1011 } 1012 } 1013 1014 /* 1015 * Since M64 BAR shares segments among all possible 256 PEs, 1016 * we have to shift the beginning of PF IOV BAR to make it start from 1017 * the segment which belongs to the PE number assigned to the first VF. 1018 * This creates a "hole" in the /proc/iomem which could be used for 1019 * allocating other resources so we reserve this area below and 1020 * release when IOV is released. 1021 */ 1022 for (i = 0; i < PCI_SRIOV_NUM_BARS; i++) { 1023 res = &dev->resource[i + PCI_IOV_RESOURCES]; 1024 if (!res->flags || !res->parent) 1025 continue; 1026 1027 size = pci_iov_resource_size(dev, i + PCI_IOV_RESOURCES); 1028 res2 = *res; 1029 res->start += size * offset; 1030 1031 dev_info(&dev->dev, "VF BAR%d: %pR shifted to %pR (%sabling %d VFs shifted by %d)\n", 1032 i, &res2, res, (offset > 0) ? "En" : "Dis", 1033 num_vfs, offset); 1034 1035 if (offset < 0) { 1036 devm_release_resource(&dev->dev, &pdn->holes[i]); 1037 memset(&pdn->holes[i], 0, sizeof(pdn->holes[i])); 1038 } 1039 1040 pci_update_resource(dev, i + PCI_IOV_RESOURCES); 1041 1042 if (offset > 0) { 1043 pdn->holes[i].start = res2.start; 1044 pdn->holes[i].end = res2.start + size * offset - 1; 1045 pdn->holes[i].flags = IORESOURCE_BUS; 1046 pdn->holes[i].name = "pnv_iov_reserved"; 1047 devm_request_resource(&dev->dev, res->parent, 1048 &pdn->holes[i]); 1049 } 1050 } 1051 return 0; 1052 } 1053 #endif /* CONFIG_PCI_IOV */ 1054 1055 static struct pnv_ioda_pe *pnv_ioda_setup_dev_PE(struct pci_dev *dev) 1056 { 1057 struct pci_controller *hose = pci_bus_to_host(dev->bus); 1058 struct pnv_phb *phb = hose->private_data; 1059 struct pci_dn *pdn = pci_get_pdn(dev); 1060 struct pnv_ioda_pe *pe; 1061 1062 if (!pdn) { 1063 pr_err("%s: Device tree node not associated properly\n", 1064 pci_name(dev)); 1065 return NULL; 1066 } 1067 if (pdn->pe_number != IODA_INVALID_PE) 1068 return NULL; 1069 1070 pe = pnv_ioda_alloc_pe(phb); 1071 if (!pe) { 1072 pr_warn("%s: Not enough PE# available, disabling device\n", 1073 pci_name(dev)); 1074 return NULL; 1075 } 1076 1077 /* NOTE: We get only one ref to the pci_dev for the pdn, not for the 1078 * pointer in the PE data structure, both should be destroyed at the 1079 * same time. However, this needs to be looked at more closely again 1080 * once we actually start removing things (Hotplug, SR-IOV, ...) 1081 * 1082 * At some point we want to remove the PDN completely anyways 1083 */ 1084 pci_dev_get(dev); 1085 pdn->pe_number = pe->pe_number; 1086 pe->flags = PNV_IODA_PE_DEV; 1087 pe->pdev = dev; 1088 pe->pbus = NULL; 1089 pe->mve_number = -1; 1090 pe->rid = dev->bus->number << 8 | pdn->devfn; 1091 1092 pe_info(pe, "Associated device to PE\n"); 1093 1094 if (pnv_ioda_configure_pe(phb, pe)) { 1095 /* XXX What do we do here ? */ 1096 pnv_ioda_free_pe(pe); 1097 pdn->pe_number = IODA_INVALID_PE; 1098 pe->pdev = NULL; 1099 pci_dev_put(dev); 1100 return NULL; 1101 } 1102 1103 /* Put PE to the list */ 1104 list_add_tail(&pe->list, &phb->ioda.pe_list); 1105 1106 return pe; 1107 } 1108 1109 static void pnv_ioda_setup_same_PE(struct pci_bus *bus, struct pnv_ioda_pe *pe) 1110 { 1111 struct pci_dev *dev; 1112 1113 list_for_each_entry(dev, &bus->devices, bus_list) { 1114 struct pci_dn *pdn = pci_get_pdn(dev); 1115 1116 if (pdn == NULL) { 1117 pr_warn("%s: No device node associated with device !\n", 1118 pci_name(dev)); 1119 continue; 1120 } 1121 1122 /* 1123 * In partial hotplug case, the PCI device might be still 1124 * associated with the PE and needn't attach it to the PE 1125 * again. 1126 */ 1127 if (pdn->pe_number != IODA_INVALID_PE) 1128 continue; 1129 1130 pe->device_count++; 1131 pdn->pe_number = pe->pe_number; 1132 if ((pe->flags & PNV_IODA_PE_BUS_ALL) && dev->subordinate) 1133 pnv_ioda_setup_same_PE(dev->subordinate, pe); 1134 } 1135 } 1136 1137 /* 1138 * There're 2 types of PCI bus sensitive PEs: One that is compromised of 1139 * single PCI bus. Another one that contains the primary PCI bus and its 1140 * subordinate PCI devices and buses. The second type of PE is normally 1141 * orgiriated by PCIe-to-PCI bridge or PLX switch downstream ports. 1142 */ 1143 static struct pnv_ioda_pe *pnv_ioda_setup_bus_PE(struct pci_bus *bus, bool all) 1144 { 1145 struct pci_controller *hose = pci_bus_to_host(bus); 1146 struct pnv_phb *phb = hose->private_data; 1147 struct pnv_ioda_pe *pe = NULL; 1148 unsigned int pe_num; 1149 1150 /* 1151 * In partial hotplug case, the PE instance might be still alive. 1152 * We should reuse it instead of allocating a new one. 1153 */ 1154 pe_num = phb->ioda.pe_rmap[bus->number << 8]; 1155 if (pe_num != IODA_INVALID_PE) { 1156 pe = &phb->ioda.pe_array[pe_num]; 1157 pnv_ioda_setup_same_PE(bus, pe); 1158 return NULL; 1159 } 1160 1161 /* PE number for root bus should have been reserved */ 1162 if (pci_is_root_bus(bus) && 1163 phb->ioda.root_pe_idx != IODA_INVALID_PE) 1164 pe = &phb->ioda.pe_array[phb->ioda.root_pe_idx]; 1165 1166 /* Check if PE is determined by M64 */ 1167 if (!pe && phb->pick_m64_pe) 1168 pe = phb->pick_m64_pe(bus, all); 1169 1170 /* The PE number isn't pinned by M64 */ 1171 if (!pe) 1172 pe = pnv_ioda_alloc_pe(phb); 1173 1174 if (!pe) { 1175 pr_warn("%s: Not enough PE# available for PCI bus %04x:%02x\n", 1176 __func__, pci_domain_nr(bus), bus->number); 1177 return NULL; 1178 } 1179 1180 pe->flags |= (all ? PNV_IODA_PE_BUS_ALL : PNV_IODA_PE_BUS); 1181 pe->pbus = bus; 1182 pe->pdev = NULL; 1183 pe->mve_number = -1; 1184 pe->rid = bus->busn_res.start << 8; 1185 1186 if (all) 1187 pe_info(pe, "Secondary bus %d..%d associated with PE#%x\n", 1188 bus->busn_res.start, bus->busn_res.end, pe->pe_number); 1189 else 1190 pe_info(pe, "Secondary bus %d associated with PE#%x\n", 1191 bus->busn_res.start, pe->pe_number); 1192 1193 if (pnv_ioda_configure_pe(phb, pe)) { 1194 /* XXX What do we do here ? */ 1195 pnv_ioda_free_pe(pe); 1196 pe->pbus = NULL; 1197 return NULL; 1198 } 1199 1200 /* Associate it with all child devices */ 1201 pnv_ioda_setup_same_PE(bus, pe); 1202 1203 /* Put PE to the list */ 1204 list_add_tail(&pe->list, &phb->ioda.pe_list); 1205 1206 return pe; 1207 } 1208 1209 static struct pnv_ioda_pe *pnv_ioda_setup_npu_PE(struct pci_dev *npu_pdev) 1210 { 1211 int pe_num, found_pe = false, rc; 1212 long rid; 1213 struct pnv_ioda_pe *pe; 1214 struct pci_dev *gpu_pdev; 1215 struct pci_dn *npu_pdn; 1216 struct pci_controller *hose = pci_bus_to_host(npu_pdev->bus); 1217 struct pnv_phb *phb = hose->private_data; 1218 1219 /* 1220 * Due to a hardware errata PE#0 on the NPU is reserved for 1221 * error handling. This means we only have three PEs remaining 1222 * which need to be assigned to four links, implying some 1223 * links must share PEs. 1224 * 1225 * To achieve this we assign PEs such that NPUs linking the 1226 * same GPU get assigned the same PE. 1227 */ 1228 gpu_pdev = pnv_pci_get_gpu_dev(npu_pdev); 1229 for (pe_num = 0; pe_num < phb->ioda.total_pe_num; pe_num++) { 1230 pe = &phb->ioda.pe_array[pe_num]; 1231 if (!pe->pdev) 1232 continue; 1233 1234 if (pnv_pci_get_gpu_dev(pe->pdev) == gpu_pdev) { 1235 /* 1236 * This device has the same peer GPU so should 1237 * be assigned the same PE as the existing 1238 * peer NPU. 1239 */ 1240 dev_info(&npu_pdev->dev, 1241 "Associating to existing PE %x\n", pe_num); 1242 pci_dev_get(npu_pdev); 1243 npu_pdn = pci_get_pdn(npu_pdev); 1244 rid = npu_pdev->bus->number << 8 | npu_pdn->devfn; 1245 npu_pdn->pe_number = pe_num; 1246 phb->ioda.pe_rmap[rid] = pe->pe_number; 1247 1248 /* Map the PE to this link */ 1249 rc = opal_pci_set_pe(phb->opal_id, pe_num, rid, 1250 OpalPciBusAll, 1251 OPAL_COMPARE_RID_DEVICE_NUMBER, 1252 OPAL_COMPARE_RID_FUNCTION_NUMBER, 1253 OPAL_MAP_PE); 1254 WARN_ON(rc != OPAL_SUCCESS); 1255 found_pe = true; 1256 break; 1257 } 1258 } 1259 1260 if (!found_pe) 1261 /* 1262 * Could not find an existing PE so allocate a new 1263 * one. 1264 */ 1265 return pnv_ioda_setup_dev_PE(npu_pdev); 1266 else 1267 return pe; 1268 } 1269 1270 static void pnv_ioda_setup_npu_PEs(struct pci_bus *bus) 1271 { 1272 struct pci_dev *pdev; 1273 1274 list_for_each_entry(pdev, &bus->devices, bus_list) 1275 pnv_ioda_setup_npu_PE(pdev); 1276 } 1277 1278 static void pnv_pci_ioda_setup_PEs(void) 1279 { 1280 struct pci_controller *hose, *tmp; 1281 struct pnv_phb *phb; 1282 struct pci_bus *bus; 1283 struct pci_dev *pdev; 1284 1285 list_for_each_entry_safe(hose, tmp, &hose_list, list_node) { 1286 phb = hose->private_data; 1287 if (phb->type == PNV_PHB_NPU_NVLINK) { 1288 /* PE#0 is needed for error reporting */ 1289 pnv_ioda_reserve_pe(phb, 0); 1290 pnv_ioda_setup_npu_PEs(hose->bus); 1291 if (phb->model == PNV_PHB_MODEL_NPU2) 1292 pnv_npu2_init(phb); 1293 } 1294 if (phb->type == PNV_PHB_NPU_OCAPI) { 1295 bus = hose->bus; 1296 list_for_each_entry(pdev, &bus->devices, bus_list) 1297 pnv_ioda_setup_dev_PE(pdev); 1298 } 1299 } 1300 } 1301 1302 #ifdef CONFIG_PCI_IOV 1303 static int pnv_pci_vf_release_m64(struct pci_dev *pdev, u16 num_vfs) 1304 { 1305 struct pci_bus *bus; 1306 struct pci_controller *hose; 1307 struct pnv_phb *phb; 1308 struct pci_dn *pdn; 1309 int i, j; 1310 int m64_bars; 1311 1312 bus = pdev->bus; 1313 hose = pci_bus_to_host(bus); 1314 phb = hose->private_data; 1315 pdn = pci_get_pdn(pdev); 1316 1317 if (pdn->m64_single_mode) 1318 m64_bars = num_vfs; 1319 else 1320 m64_bars = 1; 1321 1322 for (i = 0; i < PCI_SRIOV_NUM_BARS; i++) 1323 for (j = 0; j < m64_bars; j++) { 1324 if (pdn->m64_map[j][i] == IODA_INVALID_M64) 1325 continue; 1326 opal_pci_phb_mmio_enable(phb->opal_id, 1327 OPAL_M64_WINDOW_TYPE, pdn->m64_map[j][i], 0); 1328 clear_bit(pdn->m64_map[j][i], &phb->ioda.m64_bar_alloc); 1329 pdn->m64_map[j][i] = IODA_INVALID_M64; 1330 } 1331 1332 kfree(pdn->m64_map); 1333 return 0; 1334 } 1335 1336 static int pnv_pci_vf_assign_m64(struct pci_dev *pdev, u16 num_vfs) 1337 { 1338 struct pci_bus *bus; 1339 struct pci_controller *hose; 1340 struct pnv_phb *phb; 1341 struct pci_dn *pdn; 1342 unsigned int win; 1343 struct resource *res; 1344 int i, j; 1345 int64_t rc; 1346 int total_vfs; 1347 resource_size_t size, start; 1348 int pe_num; 1349 int m64_bars; 1350 1351 bus = pdev->bus; 1352 hose = pci_bus_to_host(bus); 1353 phb = hose->private_data; 1354 pdn = pci_get_pdn(pdev); 1355 total_vfs = pci_sriov_get_totalvfs(pdev); 1356 1357 if (pdn->m64_single_mode) 1358 m64_bars = num_vfs; 1359 else 1360 m64_bars = 1; 1361 1362 pdn->m64_map = kmalloc_array(m64_bars, 1363 sizeof(*pdn->m64_map), 1364 GFP_KERNEL); 1365 if (!pdn->m64_map) 1366 return -ENOMEM; 1367 /* Initialize the m64_map to IODA_INVALID_M64 */ 1368 for (i = 0; i < m64_bars ; i++) 1369 for (j = 0; j < PCI_SRIOV_NUM_BARS; j++) 1370 pdn->m64_map[i][j] = IODA_INVALID_M64; 1371 1372 1373 for (i = 0; i < PCI_SRIOV_NUM_BARS; i++) { 1374 res = &pdev->resource[i + PCI_IOV_RESOURCES]; 1375 if (!res->flags || !res->parent) 1376 continue; 1377 1378 for (j = 0; j < m64_bars; j++) { 1379 do { 1380 win = find_next_zero_bit(&phb->ioda.m64_bar_alloc, 1381 phb->ioda.m64_bar_idx + 1, 0); 1382 1383 if (win >= phb->ioda.m64_bar_idx + 1) 1384 goto m64_failed; 1385 } while (test_and_set_bit(win, &phb->ioda.m64_bar_alloc)); 1386 1387 pdn->m64_map[j][i] = win; 1388 1389 if (pdn->m64_single_mode) { 1390 size = pci_iov_resource_size(pdev, 1391 PCI_IOV_RESOURCES + i); 1392 start = res->start + size * j; 1393 } else { 1394 size = resource_size(res); 1395 start = res->start; 1396 } 1397 1398 /* Map the M64 here */ 1399 if (pdn->m64_single_mode) { 1400 pe_num = pdn->pe_num_map[j]; 1401 rc = opal_pci_map_pe_mmio_window(phb->opal_id, 1402 pe_num, OPAL_M64_WINDOW_TYPE, 1403 pdn->m64_map[j][i], 0); 1404 } 1405 1406 rc = opal_pci_set_phb_mem_window(phb->opal_id, 1407 OPAL_M64_WINDOW_TYPE, 1408 pdn->m64_map[j][i], 1409 start, 1410 0, /* unused */ 1411 size); 1412 1413 1414 if (rc != OPAL_SUCCESS) { 1415 dev_err(&pdev->dev, "Failed to map M64 window #%d: %lld\n", 1416 win, rc); 1417 goto m64_failed; 1418 } 1419 1420 if (pdn->m64_single_mode) 1421 rc = opal_pci_phb_mmio_enable(phb->opal_id, 1422 OPAL_M64_WINDOW_TYPE, pdn->m64_map[j][i], 2); 1423 else 1424 rc = opal_pci_phb_mmio_enable(phb->opal_id, 1425 OPAL_M64_WINDOW_TYPE, pdn->m64_map[j][i], 1); 1426 1427 if (rc != OPAL_SUCCESS) { 1428 dev_err(&pdev->dev, "Failed to enable M64 window #%d: %llx\n", 1429 win, rc); 1430 goto m64_failed; 1431 } 1432 } 1433 } 1434 return 0; 1435 1436 m64_failed: 1437 pnv_pci_vf_release_m64(pdev, num_vfs); 1438 return -EBUSY; 1439 } 1440 1441 static long pnv_pci_ioda2_unset_window(struct iommu_table_group *table_group, 1442 int num); 1443 1444 static void pnv_pci_ioda2_release_dma_pe(struct pci_dev *dev, struct pnv_ioda_pe *pe) 1445 { 1446 struct iommu_table *tbl; 1447 int64_t rc; 1448 1449 tbl = pe->table_group.tables[0]; 1450 rc = pnv_pci_ioda2_unset_window(&pe->table_group, 0); 1451 if (rc) 1452 pe_warn(pe, "OPAL error %ld release DMA window\n", rc); 1453 1454 pnv_pci_ioda2_set_bypass(pe, false); 1455 if (pe->table_group.group) { 1456 iommu_group_put(pe->table_group.group); 1457 BUG_ON(pe->table_group.group); 1458 } 1459 iommu_tce_table_put(tbl); 1460 } 1461 1462 static void pnv_ioda_release_vf_PE(struct pci_dev *pdev) 1463 { 1464 struct pci_bus *bus; 1465 struct pci_controller *hose; 1466 struct pnv_phb *phb; 1467 struct pnv_ioda_pe *pe, *pe_n; 1468 struct pci_dn *pdn; 1469 1470 bus = pdev->bus; 1471 hose = pci_bus_to_host(bus); 1472 phb = hose->private_data; 1473 pdn = pci_get_pdn(pdev); 1474 1475 if (!pdev->is_physfn) 1476 return; 1477 1478 list_for_each_entry_safe(pe, pe_n, &phb->ioda.pe_list, list) { 1479 if (pe->parent_dev != pdev) 1480 continue; 1481 1482 pnv_pci_ioda2_release_dma_pe(pdev, pe); 1483 1484 /* Remove from list */ 1485 mutex_lock(&phb->ioda.pe_list_mutex); 1486 list_del(&pe->list); 1487 mutex_unlock(&phb->ioda.pe_list_mutex); 1488 1489 pnv_ioda_deconfigure_pe(phb, pe); 1490 1491 pnv_ioda_free_pe(pe); 1492 } 1493 } 1494 1495 void pnv_pci_sriov_disable(struct pci_dev *pdev) 1496 { 1497 struct pci_bus *bus; 1498 struct pci_controller *hose; 1499 struct pnv_phb *phb; 1500 struct pnv_ioda_pe *pe; 1501 struct pci_dn *pdn; 1502 u16 num_vfs, i; 1503 1504 bus = pdev->bus; 1505 hose = pci_bus_to_host(bus); 1506 phb = hose->private_data; 1507 pdn = pci_get_pdn(pdev); 1508 num_vfs = pdn->num_vfs; 1509 1510 /* Release VF PEs */ 1511 pnv_ioda_release_vf_PE(pdev); 1512 1513 if (phb->type == PNV_PHB_IODA2) { 1514 if (!pdn->m64_single_mode) 1515 pnv_pci_vf_resource_shift(pdev, -*pdn->pe_num_map); 1516 1517 /* Release M64 windows */ 1518 pnv_pci_vf_release_m64(pdev, num_vfs); 1519 1520 /* Release PE numbers */ 1521 if (pdn->m64_single_mode) { 1522 for (i = 0; i < num_vfs; i++) { 1523 if (pdn->pe_num_map[i] == IODA_INVALID_PE) 1524 continue; 1525 1526 pe = &phb->ioda.pe_array[pdn->pe_num_map[i]]; 1527 pnv_ioda_free_pe(pe); 1528 } 1529 } else 1530 bitmap_clear(phb->ioda.pe_alloc, *pdn->pe_num_map, num_vfs); 1531 /* Releasing pe_num_map */ 1532 kfree(pdn->pe_num_map); 1533 } 1534 } 1535 1536 static void pnv_pci_ioda2_setup_dma_pe(struct pnv_phb *phb, 1537 struct pnv_ioda_pe *pe); 1538 static void pnv_ioda_setup_vf_PE(struct pci_dev *pdev, u16 num_vfs) 1539 { 1540 struct pci_bus *bus; 1541 struct pci_controller *hose; 1542 struct pnv_phb *phb; 1543 struct pnv_ioda_pe *pe; 1544 int pe_num; 1545 u16 vf_index; 1546 struct pci_dn *pdn; 1547 1548 bus = pdev->bus; 1549 hose = pci_bus_to_host(bus); 1550 phb = hose->private_data; 1551 pdn = pci_get_pdn(pdev); 1552 1553 if (!pdev->is_physfn) 1554 return; 1555 1556 /* Reserve PE for each VF */ 1557 for (vf_index = 0; vf_index < num_vfs; vf_index++) { 1558 if (pdn->m64_single_mode) 1559 pe_num = pdn->pe_num_map[vf_index]; 1560 else 1561 pe_num = *pdn->pe_num_map + vf_index; 1562 1563 pe = &phb->ioda.pe_array[pe_num]; 1564 pe->pe_number = pe_num; 1565 pe->phb = phb; 1566 pe->flags = PNV_IODA_PE_VF; 1567 pe->pbus = NULL; 1568 pe->parent_dev = pdev; 1569 pe->mve_number = -1; 1570 pe->rid = (pci_iov_virtfn_bus(pdev, vf_index) << 8) | 1571 pci_iov_virtfn_devfn(pdev, vf_index); 1572 1573 pe_info(pe, "VF %04d:%02d:%02d.%d associated with PE#%x\n", 1574 hose->global_number, pdev->bus->number, 1575 PCI_SLOT(pci_iov_virtfn_devfn(pdev, vf_index)), 1576 PCI_FUNC(pci_iov_virtfn_devfn(pdev, vf_index)), pe_num); 1577 1578 if (pnv_ioda_configure_pe(phb, pe)) { 1579 /* XXX What do we do here ? */ 1580 pnv_ioda_free_pe(pe); 1581 pe->pdev = NULL; 1582 continue; 1583 } 1584 1585 /* Put PE to the list */ 1586 mutex_lock(&phb->ioda.pe_list_mutex); 1587 list_add_tail(&pe->list, &phb->ioda.pe_list); 1588 mutex_unlock(&phb->ioda.pe_list_mutex); 1589 1590 pnv_pci_ioda2_setup_dma_pe(phb, pe); 1591 } 1592 } 1593 1594 int pnv_pci_sriov_enable(struct pci_dev *pdev, u16 num_vfs) 1595 { 1596 struct pci_bus *bus; 1597 struct pci_controller *hose; 1598 struct pnv_phb *phb; 1599 struct pnv_ioda_pe *pe; 1600 struct pci_dn *pdn; 1601 int ret; 1602 u16 i; 1603 1604 bus = pdev->bus; 1605 hose = pci_bus_to_host(bus); 1606 phb = hose->private_data; 1607 pdn = pci_get_pdn(pdev); 1608 1609 if (phb->type == PNV_PHB_IODA2) { 1610 if (!pdn->vfs_expanded) { 1611 dev_info(&pdev->dev, "don't support this SRIOV device" 1612 " with non 64bit-prefetchable IOV BAR\n"); 1613 return -ENOSPC; 1614 } 1615 1616 /* 1617 * When M64 BARs functions in Single PE mode, the number of VFs 1618 * could be enabled must be less than the number of M64 BARs. 1619 */ 1620 if (pdn->m64_single_mode && num_vfs > phb->ioda.m64_bar_idx) { 1621 dev_info(&pdev->dev, "Not enough M64 BAR for VFs\n"); 1622 return -EBUSY; 1623 } 1624 1625 /* Allocating pe_num_map */ 1626 if (pdn->m64_single_mode) 1627 pdn->pe_num_map = kmalloc_array(num_vfs, 1628 sizeof(*pdn->pe_num_map), 1629 GFP_KERNEL); 1630 else 1631 pdn->pe_num_map = kmalloc(sizeof(*pdn->pe_num_map), GFP_KERNEL); 1632 1633 if (!pdn->pe_num_map) 1634 return -ENOMEM; 1635 1636 if (pdn->m64_single_mode) 1637 for (i = 0; i < num_vfs; i++) 1638 pdn->pe_num_map[i] = IODA_INVALID_PE; 1639 1640 /* Calculate available PE for required VFs */ 1641 if (pdn->m64_single_mode) { 1642 for (i = 0; i < num_vfs; i++) { 1643 pe = pnv_ioda_alloc_pe(phb); 1644 if (!pe) { 1645 ret = -EBUSY; 1646 goto m64_failed; 1647 } 1648 1649 pdn->pe_num_map[i] = pe->pe_number; 1650 } 1651 } else { 1652 mutex_lock(&phb->ioda.pe_alloc_mutex); 1653 *pdn->pe_num_map = bitmap_find_next_zero_area( 1654 phb->ioda.pe_alloc, phb->ioda.total_pe_num, 1655 0, num_vfs, 0); 1656 if (*pdn->pe_num_map >= phb->ioda.total_pe_num) { 1657 mutex_unlock(&phb->ioda.pe_alloc_mutex); 1658 dev_info(&pdev->dev, "Failed to enable VF%d\n", num_vfs); 1659 kfree(pdn->pe_num_map); 1660 return -EBUSY; 1661 } 1662 bitmap_set(phb->ioda.pe_alloc, *pdn->pe_num_map, num_vfs); 1663 mutex_unlock(&phb->ioda.pe_alloc_mutex); 1664 } 1665 pdn->num_vfs = num_vfs; 1666 1667 /* Assign M64 window accordingly */ 1668 ret = pnv_pci_vf_assign_m64(pdev, num_vfs); 1669 if (ret) { 1670 dev_info(&pdev->dev, "Not enough M64 window resources\n"); 1671 goto m64_failed; 1672 } 1673 1674 /* 1675 * When using one M64 BAR to map one IOV BAR, we need to shift 1676 * the IOV BAR according to the PE# allocated to the VFs. 1677 * Otherwise, the PE# for the VF will conflict with others. 1678 */ 1679 if (!pdn->m64_single_mode) { 1680 ret = pnv_pci_vf_resource_shift(pdev, *pdn->pe_num_map); 1681 if (ret) 1682 goto m64_failed; 1683 } 1684 } 1685 1686 /* Setup VF PEs */ 1687 pnv_ioda_setup_vf_PE(pdev, num_vfs); 1688 1689 return 0; 1690 1691 m64_failed: 1692 if (pdn->m64_single_mode) { 1693 for (i = 0; i < num_vfs; i++) { 1694 if (pdn->pe_num_map[i] == IODA_INVALID_PE) 1695 continue; 1696 1697 pe = &phb->ioda.pe_array[pdn->pe_num_map[i]]; 1698 pnv_ioda_free_pe(pe); 1699 } 1700 } else 1701 bitmap_clear(phb->ioda.pe_alloc, *pdn->pe_num_map, num_vfs); 1702 1703 /* Releasing pe_num_map */ 1704 kfree(pdn->pe_num_map); 1705 1706 return ret; 1707 } 1708 1709 int pnv_pcibios_sriov_disable(struct pci_dev *pdev) 1710 { 1711 pnv_pci_sriov_disable(pdev); 1712 1713 /* Release PCI data */ 1714 remove_dev_pci_data(pdev); 1715 return 0; 1716 } 1717 1718 int pnv_pcibios_sriov_enable(struct pci_dev *pdev, u16 num_vfs) 1719 { 1720 /* Allocate PCI data */ 1721 add_dev_pci_data(pdev); 1722 1723 return pnv_pci_sriov_enable(pdev, num_vfs); 1724 } 1725 #endif /* CONFIG_PCI_IOV */ 1726 1727 static void pnv_pci_ioda_dma_dev_setup(struct pnv_phb *phb, struct pci_dev *pdev) 1728 { 1729 struct pci_dn *pdn = pci_get_pdn(pdev); 1730 struct pnv_ioda_pe *pe; 1731 1732 /* 1733 * The function can be called while the PE# 1734 * hasn't been assigned. Do nothing for the 1735 * case. 1736 */ 1737 if (!pdn || pdn->pe_number == IODA_INVALID_PE) 1738 return; 1739 1740 pe = &phb->ioda.pe_array[pdn->pe_number]; 1741 WARN_ON(get_dma_ops(&pdev->dev) != &dma_iommu_ops); 1742 set_dma_offset(&pdev->dev, pe->tce_bypass_base); 1743 set_iommu_table_base(&pdev->dev, pe->table_group.tables[0]); 1744 /* 1745 * Note: iommu_add_device() will fail here as 1746 * for physical PE: the device is already added by now; 1747 * for virtual PE: sysfs entries are not ready yet and 1748 * tce_iommu_bus_notifier will add the device to a group later. 1749 */ 1750 } 1751 1752 static bool pnv_pci_ioda_pe_single_vendor(struct pnv_ioda_pe *pe) 1753 { 1754 unsigned short vendor = 0; 1755 struct pci_dev *pdev; 1756 1757 if (pe->device_count == 1) 1758 return true; 1759 1760 /* pe->pdev should be set if it's a single device, pe->pbus if not */ 1761 if (!pe->pbus) 1762 return true; 1763 1764 list_for_each_entry(pdev, &pe->pbus->devices, bus_list) { 1765 if (!vendor) { 1766 vendor = pdev->vendor; 1767 continue; 1768 } 1769 1770 if (pdev->vendor != vendor) 1771 return false; 1772 } 1773 1774 return true; 1775 } 1776 1777 /* 1778 * Reconfigure TVE#0 to be usable as 64-bit DMA space. 1779 * 1780 * The first 4GB of virtual memory for a PE is reserved for 32-bit accesses. 1781 * Devices can only access more than that if bit 59 of the PCI address is set 1782 * by hardware, which indicates TVE#1 should be used instead of TVE#0. 1783 * Many PCI devices are not capable of addressing that many bits, and as a 1784 * result are limited to the 4GB of virtual memory made available to 32-bit 1785 * devices in TVE#0. 1786 * 1787 * In order to work around this, reconfigure TVE#0 to be suitable for 64-bit 1788 * devices by configuring the virtual memory past the first 4GB inaccessible 1789 * by 64-bit DMAs. This should only be used by devices that want more than 1790 * 4GB, and only on PEs that have no 32-bit devices. 1791 * 1792 * Currently this will only work on PHB3 (POWER8). 1793 */ 1794 static int pnv_pci_ioda_dma_64bit_bypass(struct pnv_ioda_pe *pe) 1795 { 1796 u64 window_size, table_size, tce_count, addr; 1797 struct page *table_pages; 1798 u64 tce_order = 28; /* 256MB TCEs */ 1799 __be64 *tces; 1800 s64 rc; 1801 1802 /* 1803 * Window size needs to be a power of two, but needs to account for 1804 * shifting memory by the 4GB offset required to skip 32bit space. 1805 */ 1806 window_size = roundup_pow_of_two(memory_hotplug_max() + (1ULL << 32)); 1807 tce_count = window_size >> tce_order; 1808 table_size = tce_count << 3; 1809 1810 if (table_size < PAGE_SIZE) 1811 table_size = PAGE_SIZE; 1812 1813 table_pages = alloc_pages_node(pe->phb->hose->node, GFP_KERNEL, 1814 get_order(table_size)); 1815 if (!table_pages) 1816 goto err; 1817 1818 tces = page_address(table_pages); 1819 if (!tces) 1820 goto err; 1821 1822 memset(tces, 0, table_size); 1823 1824 for (addr = 0; addr < memory_hotplug_max(); addr += (1 << tce_order)) { 1825 tces[(addr + (1ULL << 32)) >> tce_order] = 1826 cpu_to_be64(addr | TCE_PCI_READ | TCE_PCI_WRITE); 1827 } 1828 1829 rc = opal_pci_map_pe_dma_window(pe->phb->opal_id, 1830 pe->pe_number, 1831 /* reconfigure window 0 */ 1832 (pe->pe_number << 1) + 0, 1833 1, 1834 __pa(tces), 1835 table_size, 1836 1 << tce_order); 1837 if (rc == OPAL_SUCCESS) { 1838 pe_info(pe, "Using 64-bit DMA iommu bypass (through TVE#0)\n"); 1839 return 0; 1840 } 1841 err: 1842 pe_err(pe, "Error configuring 64-bit DMA bypass\n"); 1843 return -EIO; 1844 } 1845 1846 static int pnv_pci_ioda_dma_set_mask(struct pci_dev *pdev, u64 dma_mask) 1847 { 1848 struct pci_controller *hose = pci_bus_to_host(pdev->bus); 1849 struct pnv_phb *phb = hose->private_data; 1850 struct pci_dn *pdn = pci_get_pdn(pdev); 1851 struct pnv_ioda_pe *pe; 1852 uint64_t top; 1853 bool bypass = false; 1854 s64 rc; 1855 1856 if (WARN_ON(!pdn || pdn->pe_number == IODA_INVALID_PE)) 1857 return -ENODEV; 1858 1859 pe = &phb->ioda.pe_array[pdn->pe_number]; 1860 if (pe->tce_bypass_enabled) { 1861 top = pe->tce_bypass_base + memblock_end_of_DRAM() - 1; 1862 bypass = (dma_mask >= top); 1863 } 1864 1865 if (bypass) { 1866 dev_info(&pdev->dev, "Using 64-bit DMA iommu bypass\n"); 1867 set_dma_ops(&pdev->dev, &dma_nommu_ops); 1868 } else { 1869 /* 1870 * If the device can't set the TCE bypass bit but still wants 1871 * to access 4GB or more, on PHB3 we can reconfigure TVE#0 to 1872 * bypass the 32-bit region and be usable for 64-bit DMAs. 1873 * The device needs to be able to address all of this space. 1874 */ 1875 if (dma_mask >> 32 && 1876 dma_mask > (memory_hotplug_max() + (1ULL << 32)) && 1877 pnv_pci_ioda_pe_single_vendor(pe) && 1878 phb->model == PNV_PHB_MODEL_PHB3) { 1879 /* Configure the bypass mode */ 1880 rc = pnv_pci_ioda_dma_64bit_bypass(pe); 1881 if (rc) 1882 return rc; 1883 /* 4GB offset bypasses 32-bit space */ 1884 set_dma_offset(&pdev->dev, (1ULL << 32)); 1885 set_dma_ops(&pdev->dev, &dma_nommu_ops); 1886 } else if (dma_mask >> 32 && dma_mask != DMA_BIT_MASK(64)) { 1887 /* 1888 * Fail the request if a DMA mask between 32 and 64 bits 1889 * was requested but couldn't be fulfilled. Ideally we 1890 * would do this for 64-bits but historically we have 1891 * always fallen back to 32-bits. 1892 */ 1893 return -ENOMEM; 1894 } else { 1895 dev_info(&pdev->dev, "Using 32-bit DMA via iommu\n"); 1896 set_dma_ops(&pdev->dev, &dma_iommu_ops); 1897 } 1898 } 1899 *pdev->dev.dma_mask = dma_mask; 1900 1901 /* Update peer npu devices */ 1902 pnv_npu_try_dma_set_bypass(pdev, bypass); 1903 1904 return 0; 1905 } 1906 1907 static u64 pnv_pci_ioda_dma_get_required_mask(struct pci_dev *pdev) 1908 { 1909 struct pci_controller *hose = pci_bus_to_host(pdev->bus); 1910 struct pnv_phb *phb = hose->private_data; 1911 struct pci_dn *pdn = pci_get_pdn(pdev); 1912 struct pnv_ioda_pe *pe; 1913 u64 end, mask; 1914 1915 if (WARN_ON(!pdn || pdn->pe_number == IODA_INVALID_PE)) 1916 return 0; 1917 1918 pe = &phb->ioda.pe_array[pdn->pe_number]; 1919 if (!pe->tce_bypass_enabled) 1920 return __dma_get_required_mask(&pdev->dev); 1921 1922 1923 end = pe->tce_bypass_base + memblock_end_of_DRAM(); 1924 mask = 1ULL << (fls64(end) - 1); 1925 mask += mask - 1; 1926 1927 return mask; 1928 } 1929 1930 static void pnv_ioda_setup_bus_dma(struct pnv_ioda_pe *pe, 1931 struct pci_bus *bus, 1932 bool add_to_group) 1933 { 1934 struct pci_dev *dev; 1935 1936 list_for_each_entry(dev, &bus->devices, bus_list) { 1937 set_iommu_table_base(&dev->dev, pe->table_group.tables[0]); 1938 set_dma_offset(&dev->dev, pe->tce_bypass_base); 1939 if (add_to_group) 1940 iommu_add_device(&dev->dev); 1941 1942 if ((pe->flags & PNV_IODA_PE_BUS_ALL) && dev->subordinate) 1943 pnv_ioda_setup_bus_dma(pe, dev->subordinate, 1944 add_to_group); 1945 } 1946 } 1947 1948 static inline __be64 __iomem *pnv_ioda_get_inval_reg(struct pnv_phb *phb, 1949 bool real_mode) 1950 { 1951 return real_mode ? (__be64 __iomem *)(phb->regs_phys + 0x210) : 1952 (phb->regs + 0x210); 1953 } 1954 1955 static void pnv_pci_p7ioc_tce_invalidate(struct iommu_table *tbl, 1956 unsigned long index, unsigned long npages, bool rm) 1957 { 1958 struct iommu_table_group_link *tgl = list_first_entry_or_null( 1959 &tbl->it_group_list, struct iommu_table_group_link, 1960 next); 1961 struct pnv_ioda_pe *pe = container_of(tgl->table_group, 1962 struct pnv_ioda_pe, table_group); 1963 __be64 __iomem *invalidate = pnv_ioda_get_inval_reg(pe->phb, rm); 1964 unsigned long start, end, inc; 1965 1966 start = __pa(((__be64 *)tbl->it_base) + index - tbl->it_offset); 1967 end = __pa(((__be64 *)tbl->it_base) + index - tbl->it_offset + 1968 npages - 1); 1969 1970 /* p7ioc-style invalidation, 2 TCEs per write */ 1971 start |= (1ull << 63); 1972 end |= (1ull << 63); 1973 inc = 16; 1974 end |= inc - 1; /* round up end to be different than start */ 1975 1976 mb(); /* Ensure above stores are visible */ 1977 while (start <= end) { 1978 if (rm) 1979 __raw_rm_writeq_be(start, invalidate); 1980 else 1981 __raw_writeq_be(start, invalidate); 1982 1983 start += inc; 1984 } 1985 1986 /* 1987 * The iommu layer will do another mb() for us on build() 1988 * and we don't care on free() 1989 */ 1990 } 1991 1992 static int pnv_ioda1_tce_build(struct iommu_table *tbl, long index, 1993 long npages, unsigned long uaddr, 1994 enum dma_data_direction direction, 1995 unsigned long attrs) 1996 { 1997 int ret = pnv_tce_build(tbl, index, npages, uaddr, direction, 1998 attrs); 1999 2000 if (!ret) 2001 pnv_pci_p7ioc_tce_invalidate(tbl, index, npages, false); 2002 2003 return ret; 2004 } 2005 2006 #ifdef CONFIG_IOMMU_API 2007 static int pnv_ioda1_tce_xchg(struct iommu_table *tbl, long index, 2008 unsigned long *hpa, enum dma_data_direction *direction) 2009 { 2010 long ret = pnv_tce_xchg(tbl, index, hpa, direction); 2011 2012 if (!ret) 2013 pnv_pci_p7ioc_tce_invalidate(tbl, index, 1, false); 2014 2015 return ret; 2016 } 2017 2018 static int pnv_ioda1_tce_xchg_rm(struct iommu_table *tbl, long index, 2019 unsigned long *hpa, enum dma_data_direction *direction) 2020 { 2021 long ret = pnv_tce_xchg(tbl, index, hpa, direction); 2022 2023 if (!ret) 2024 pnv_pci_p7ioc_tce_invalidate(tbl, index, 1, true); 2025 2026 return ret; 2027 } 2028 #endif 2029 2030 static void pnv_ioda1_tce_free(struct iommu_table *tbl, long index, 2031 long npages) 2032 { 2033 pnv_tce_free(tbl, index, npages); 2034 2035 pnv_pci_p7ioc_tce_invalidate(tbl, index, npages, false); 2036 } 2037 2038 static struct iommu_table_ops pnv_ioda1_iommu_ops = { 2039 .set = pnv_ioda1_tce_build, 2040 #ifdef CONFIG_IOMMU_API 2041 .exchange = pnv_ioda1_tce_xchg, 2042 .exchange_rm = pnv_ioda1_tce_xchg_rm, 2043 #endif 2044 .clear = pnv_ioda1_tce_free, 2045 .get = pnv_tce_get, 2046 }; 2047 2048 #define PHB3_TCE_KILL_INVAL_ALL PPC_BIT(0) 2049 #define PHB3_TCE_KILL_INVAL_PE PPC_BIT(1) 2050 #define PHB3_TCE_KILL_INVAL_ONE PPC_BIT(2) 2051 2052 static void pnv_pci_phb3_tce_invalidate_entire(struct pnv_phb *phb, bool rm) 2053 { 2054 __be64 __iomem *invalidate = pnv_ioda_get_inval_reg(phb, rm); 2055 const unsigned long val = PHB3_TCE_KILL_INVAL_ALL; 2056 2057 mb(); /* Ensure previous TCE table stores are visible */ 2058 if (rm) 2059 __raw_rm_writeq_be(val, invalidate); 2060 else 2061 __raw_writeq_be(val, invalidate); 2062 } 2063 2064 static inline void pnv_pci_phb3_tce_invalidate_pe(struct pnv_ioda_pe *pe) 2065 { 2066 /* 01xb - invalidate TCEs that match the specified PE# */ 2067 __be64 __iomem *invalidate = pnv_ioda_get_inval_reg(pe->phb, false); 2068 unsigned long val = PHB3_TCE_KILL_INVAL_PE | (pe->pe_number & 0xFF); 2069 2070 mb(); /* Ensure above stores are visible */ 2071 __raw_writeq_be(val, invalidate); 2072 } 2073 2074 static void pnv_pci_phb3_tce_invalidate(struct pnv_ioda_pe *pe, bool rm, 2075 unsigned shift, unsigned long index, 2076 unsigned long npages) 2077 { 2078 __be64 __iomem *invalidate = pnv_ioda_get_inval_reg(pe->phb, rm); 2079 unsigned long start, end, inc; 2080 2081 /* We'll invalidate DMA address in PE scope */ 2082 start = PHB3_TCE_KILL_INVAL_ONE; 2083 start |= (pe->pe_number & 0xFF); 2084 end = start; 2085 2086 /* Figure out the start, end and step */ 2087 start |= (index << shift); 2088 end |= ((index + npages - 1) << shift); 2089 inc = (0x1ull << shift); 2090 mb(); 2091 2092 while (start <= end) { 2093 if (rm) 2094 __raw_rm_writeq_be(start, invalidate); 2095 else 2096 __raw_writeq_be(start, invalidate); 2097 start += inc; 2098 } 2099 } 2100 2101 static inline void pnv_pci_ioda2_tce_invalidate_pe(struct pnv_ioda_pe *pe) 2102 { 2103 struct pnv_phb *phb = pe->phb; 2104 2105 if (phb->model == PNV_PHB_MODEL_PHB3 && phb->regs) 2106 pnv_pci_phb3_tce_invalidate_pe(pe); 2107 else 2108 opal_pci_tce_kill(phb->opal_id, OPAL_PCI_TCE_KILL_PE, 2109 pe->pe_number, 0, 0, 0); 2110 } 2111 2112 static void pnv_pci_ioda2_tce_invalidate(struct iommu_table *tbl, 2113 unsigned long index, unsigned long npages, bool rm) 2114 { 2115 struct iommu_table_group_link *tgl; 2116 2117 list_for_each_entry_lockless(tgl, &tbl->it_group_list, next) { 2118 struct pnv_ioda_pe *pe = container_of(tgl->table_group, 2119 struct pnv_ioda_pe, table_group); 2120 struct pnv_phb *phb = pe->phb; 2121 unsigned int shift = tbl->it_page_shift; 2122 2123 /* 2124 * NVLink1 can use the TCE kill register directly as 2125 * it's the same as PHB3. NVLink2 is different and 2126 * should go via the OPAL call. 2127 */ 2128 if (phb->model == PNV_PHB_MODEL_NPU) { 2129 /* 2130 * The NVLink hardware does not support TCE kill 2131 * per TCE entry so we have to invalidate 2132 * the entire cache for it. 2133 */ 2134 pnv_pci_phb3_tce_invalidate_entire(phb, rm); 2135 continue; 2136 } 2137 if (phb->model == PNV_PHB_MODEL_PHB3 && phb->regs) 2138 pnv_pci_phb3_tce_invalidate(pe, rm, shift, 2139 index, npages); 2140 else 2141 opal_pci_tce_kill(phb->opal_id, 2142 OPAL_PCI_TCE_KILL_PAGES, 2143 pe->pe_number, 1u << shift, 2144 index << shift, npages); 2145 } 2146 } 2147 2148 void pnv_pci_ioda2_tce_invalidate_entire(struct pnv_phb *phb, bool rm) 2149 { 2150 if (phb->model == PNV_PHB_MODEL_NPU || phb->model == PNV_PHB_MODEL_PHB3) 2151 pnv_pci_phb3_tce_invalidate_entire(phb, rm); 2152 else 2153 opal_pci_tce_kill(phb->opal_id, OPAL_PCI_TCE_KILL, 0, 0, 0, 0); 2154 } 2155 2156 static int pnv_ioda2_tce_build(struct iommu_table *tbl, long index, 2157 long npages, unsigned long uaddr, 2158 enum dma_data_direction direction, 2159 unsigned long attrs) 2160 { 2161 int ret = pnv_tce_build(tbl, index, npages, uaddr, direction, 2162 attrs); 2163 2164 if (!ret) 2165 pnv_pci_ioda2_tce_invalidate(tbl, index, npages, false); 2166 2167 return ret; 2168 } 2169 2170 #ifdef CONFIG_IOMMU_API 2171 static int pnv_ioda2_tce_xchg(struct iommu_table *tbl, long index, 2172 unsigned long *hpa, enum dma_data_direction *direction) 2173 { 2174 long ret = pnv_tce_xchg(tbl, index, hpa, direction); 2175 2176 if (!ret) 2177 pnv_pci_ioda2_tce_invalidate(tbl, index, 1, false); 2178 2179 return ret; 2180 } 2181 2182 static int pnv_ioda2_tce_xchg_rm(struct iommu_table *tbl, long index, 2183 unsigned long *hpa, enum dma_data_direction *direction) 2184 { 2185 long ret = pnv_tce_xchg(tbl, index, hpa, direction); 2186 2187 if (!ret) 2188 pnv_pci_ioda2_tce_invalidate(tbl, index, 1, true); 2189 2190 return ret; 2191 } 2192 #endif 2193 2194 static void pnv_ioda2_tce_free(struct iommu_table *tbl, long index, 2195 long npages) 2196 { 2197 pnv_tce_free(tbl, index, npages); 2198 2199 pnv_pci_ioda2_tce_invalidate(tbl, index, npages, false); 2200 } 2201 2202 static void pnv_ioda2_table_free(struct iommu_table *tbl) 2203 { 2204 pnv_pci_ioda2_table_free_pages(tbl); 2205 } 2206 2207 static struct iommu_table_ops pnv_ioda2_iommu_ops = { 2208 .set = pnv_ioda2_tce_build, 2209 #ifdef CONFIG_IOMMU_API 2210 .exchange = pnv_ioda2_tce_xchg, 2211 .exchange_rm = pnv_ioda2_tce_xchg_rm, 2212 #endif 2213 .clear = pnv_ioda2_tce_free, 2214 .get = pnv_tce_get, 2215 .free = pnv_ioda2_table_free, 2216 }; 2217 2218 static int pnv_pci_ioda_dev_dma_weight(struct pci_dev *dev, void *data) 2219 { 2220 unsigned int *weight = (unsigned int *)data; 2221 2222 /* This is quite simplistic. The "base" weight of a device 2223 * is 10. 0 means no DMA is to be accounted for it. 2224 */ 2225 if (dev->hdr_type != PCI_HEADER_TYPE_NORMAL) 2226 return 0; 2227 2228 if (dev->class == PCI_CLASS_SERIAL_USB_UHCI || 2229 dev->class == PCI_CLASS_SERIAL_USB_OHCI || 2230 dev->class == PCI_CLASS_SERIAL_USB_EHCI) 2231 *weight += 3; 2232 else if ((dev->class >> 8) == PCI_CLASS_STORAGE_RAID) 2233 *weight += 15; 2234 else 2235 *weight += 10; 2236 2237 return 0; 2238 } 2239 2240 static unsigned int pnv_pci_ioda_pe_dma_weight(struct pnv_ioda_pe *pe) 2241 { 2242 unsigned int weight = 0; 2243 2244 /* SRIOV VF has same DMA32 weight as its PF */ 2245 #ifdef CONFIG_PCI_IOV 2246 if ((pe->flags & PNV_IODA_PE_VF) && pe->parent_dev) { 2247 pnv_pci_ioda_dev_dma_weight(pe->parent_dev, &weight); 2248 return weight; 2249 } 2250 #endif 2251 2252 if ((pe->flags & PNV_IODA_PE_DEV) && pe->pdev) { 2253 pnv_pci_ioda_dev_dma_weight(pe->pdev, &weight); 2254 } else if ((pe->flags & PNV_IODA_PE_BUS) && pe->pbus) { 2255 struct pci_dev *pdev; 2256 2257 list_for_each_entry(pdev, &pe->pbus->devices, bus_list) 2258 pnv_pci_ioda_dev_dma_weight(pdev, &weight); 2259 } else if ((pe->flags & PNV_IODA_PE_BUS_ALL) && pe->pbus) { 2260 pci_walk_bus(pe->pbus, pnv_pci_ioda_dev_dma_weight, &weight); 2261 } 2262 2263 return weight; 2264 } 2265 2266 static void pnv_pci_ioda1_setup_dma_pe(struct pnv_phb *phb, 2267 struct pnv_ioda_pe *pe) 2268 { 2269 2270 struct page *tce_mem = NULL; 2271 struct iommu_table *tbl; 2272 unsigned int weight, total_weight = 0; 2273 unsigned int tce32_segsz, base, segs, avail, i; 2274 int64_t rc; 2275 void *addr; 2276 2277 /* XXX FIXME: Handle 64-bit only DMA devices */ 2278 /* XXX FIXME: Provide 64-bit DMA facilities & non-4K TCE tables etc.. */ 2279 /* XXX FIXME: Allocate multi-level tables on PHB3 */ 2280 weight = pnv_pci_ioda_pe_dma_weight(pe); 2281 if (!weight) 2282 return; 2283 2284 pci_walk_bus(phb->hose->bus, pnv_pci_ioda_dev_dma_weight, 2285 &total_weight); 2286 segs = (weight * phb->ioda.dma32_count) / total_weight; 2287 if (!segs) 2288 segs = 1; 2289 2290 /* 2291 * Allocate contiguous DMA32 segments. We begin with the expected 2292 * number of segments. With one more attempt, the number of DMA32 2293 * segments to be allocated is decreased by one until one segment 2294 * is allocated successfully. 2295 */ 2296 do { 2297 for (base = 0; base <= phb->ioda.dma32_count - segs; base++) { 2298 for (avail = 0, i = base; i < base + segs; i++) { 2299 if (phb->ioda.dma32_segmap[i] == 2300 IODA_INVALID_PE) 2301 avail++; 2302 } 2303 2304 if (avail == segs) 2305 goto found; 2306 } 2307 } while (--segs); 2308 2309 if (!segs) { 2310 pe_warn(pe, "No available DMA32 segments\n"); 2311 return; 2312 } 2313 2314 found: 2315 tbl = pnv_pci_table_alloc(phb->hose->node); 2316 if (WARN_ON(!tbl)) 2317 return; 2318 2319 iommu_register_group(&pe->table_group, phb->hose->global_number, 2320 pe->pe_number); 2321 pnv_pci_link_table_and_group(phb->hose->node, 0, tbl, &pe->table_group); 2322 2323 /* Grab a 32-bit TCE table */ 2324 pe_info(pe, "DMA weight %d (%d), assigned (%d) %d DMA32 segments\n", 2325 weight, total_weight, base, segs); 2326 pe_info(pe, " Setting up 32-bit TCE table at %08x..%08x\n", 2327 base * PNV_IODA1_DMA32_SEGSIZE, 2328 (base + segs) * PNV_IODA1_DMA32_SEGSIZE - 1); 2329 2330 /* XXX Currently, we allocate one big contiguous table for the 2331 * TCEs. We only really need one chunk per 256M of TCE space 2332 * (ie per segment) but that's an optimization for later, it 2333 * requires some added smarts with our get/put_tce implementation 2334 * 2335 * Each TCE page is 4KB in size and each TCE entry occupies 8 2336 * bytes 2337 */ 2338 tce32_segsz = PNV_IODA1_DMA32_SEGSIZE >> (IOMMU_PAGE_SHIFT_4K - 3); 2339 tce_mem = alloc_pages_node(phb->hose->node, GFP_KERNEL, 2340 get_order(tce32_segsz * segs)); 2341 if (!tce_mem) { 2342 pe_err(pe, " Failed to allocate a 32-bit TCE memory\n"); 2343 goto fail; 2344 } 2345 addr = page_address(tce_mem); 2346 memset(addr, 0, tce32_segsz * segs); 2347 2348 /* Configure HW */ 2349 for (i = 0; i < segs; i++) { 2350 rc = opal_pci_map_pe_dma_window(phb->opal_id, 2351 pe->pe_number, 2352 base + i, 1, 2353 __pa(addr) + tce32_segsz * i, 2354 tce32_segsz, IOMMU_PAGE_SIZE_4K); 2355 if (rc) { 2356 pe_err(pe, " Failed to configure 32-bit TCE table," 2357 " err %ld\n", rc); 2358 goto fail; 2359 } 2360 } 2361 2362 /* Setup DMA32 segment mapping */ 2363 for (i = base; i < base + segs; i++) 2364 phb->ioda.dma32_segmap[i] = pe->pe_number; 2365 2366 /* Setup linux iommu table */ 2367 pnv_pci_setup_iommu_table(tbl, addr, tce32_segsz * segs, 2368 base * PNV_IODA1_DMA32_SEGSIZE, 2369 IOMMU_PAGE_SHIFT_4K); 2370 2371 tbl->it_ops = &pnv_ioda1_iommu_ops; 2372 pe->table_group.tce32_start = tbl->it_offset << tbl->it_page_shift; 2373 pe->table_group.tce32_size = tbl->it_size << tbl->it_page_shift; 2374 iommu_init_table(tbl, phb->hose->node); 2375 2376 if (pe->flags & PNV_IODA_PE_DEV) { 2377 /* 2378 * Setting table base here only for carrying iommu_group 2379 * further down to let iommu_add_device() do the job. 2380 * pnv_pci_ioda_dma_dev_setup will override it later anyway. 2381 */ 2382 set_iommu_table_base(&pe->pdev->dev, tbl); 2383 iommu_add_device(&pe->pdev->dev); 2384 } else if (pe->flags & (PNV_IODA_PE_BUS | PNV_IODA_PE_BUS_ALL)) 2385 pnv_ioda_setup_bus_dma(pe, pe->pbus, true); 2386 2387 return; 2388 fail: 2389 /* XXX Failure: Try to fallback to 64-bit only ? */ 2390 if (tce_mem) 2391 __free_pages(tce_mem, get_order(tce32_segsz * segs)); 2392 if (tbl) { 2393 pnv_pci_unlink_table_and_group(tbl, &pe->table_group); 2394 iommu_tce_table_put(tbl); 2395 } 2396 } 2397 2398 static long pnv_pci_ioda2_set_window(struct iommu_table_group *table_group, 2399 int num, struct iommu_table *tbl) 2400 { 2401 struct pnv_ioda_pe *pe = container_of(table_group, struct pnv_ioda_pe, 2402 table_group); 2403 struct pnv_phb *phb = pe->phb; 2404 int64_t rc; 2405 const unsigned long size = tbl->it_indirect_levels ? 2406 tbl->it_level_size : tbl->it_size; 2407 const __u64 start_addr = tbl->it_offset << tbl->it_page_shift; 2408 const __u64 win_size = tbl->it_size << tbl->it_page_shift; 2409 2410 pe_info(pe, "Setting up window#%d %llx..%llx pg=%x\n", num, 2411 start_addr, start_addr + win_size - 1, 2412 IOMMU_PAGE_SIZE(tbl)); 2413 2414 /* 2415 * Map TCE table through TVT. The TVE index is the PE number 2416 * shifted by 1 bit for 32-bits DMA space. 2417 */ 2418 rc = opal_pci_map_pe_dma_window(phb->opal_id, 2419 pe->pe_number, 2420 (pe->pe_number << 1) + num, 2421 tbl->it_indirect_levels + 1, 2422 __pa(tbl->it_base), 2423 size << 3, 2424 IOMMU_PAGE_SIZE(tbl)); 2425 if (rc) { 2426 pe_err(pe, "Failed to configure TCE table, err %ld\n", rc); 2427 return rc; 2428 } 2429 2430 pnv_pci_link_table_and_group(phb->hose->node, num, 2431 tbl, &pe->table_group); 2432 pnv_pci_ioda2_tce_invalidate_pe(pe); 2433 2434 return 0; 2435 } 2436 2437 void pnv_pci_ioda2_set_bypass(struct pnv_ioda_pe *pe, bool enable) 2438 { 2439 uint16_t window_id = (pe->pe_number << 1 ) + 1; 2440 int64_t rc; 2441 2442 pe_info(pe, "%sabling 64-bit DMA bypass\n", enable ? "En" : "Dis"); 2443 if (enable) { 2444 phys_addr_t top = memblock_end_of_DRAM(); 2445 2446 top = roundup_pow_of_two(top); 2447 rc = opal_pci_map_pe_dma_window_real(pe->phb->opal_id, 2448 pe->pe_number, 2449 window_id, 2450 pe->tce_bypass_base, 2451 top); 2452 } else { 2453 rc = opal_pci_map_pe_dma_window_real(pe->phb->opal_id, 2454 pe->pe_number, 2455 window_id, 2456 pe->tce_bypass_base, 2457 0); 2458 } 2459 if (rc) 2460 pe_err(pe, "OPAL error %lld configuring bypass window\n", rc); 2461 else 2462 pe->tce_bypass_enabled = enable; 2463 } 2464 2465 static long pnv_pci_ioda2_table_alloc_pages(int nid, __u64 bus_offset, 2466 __u32 page_shift, __u64 window_size, __u32 levels, 2467 struct iommu_table *tbl); 2468 2469 static long pnv_pci_ioda2_create_table(struct iommu_table_group *table_group, 2470 int num, __u32 page_shift, __u64 window_size, __u32 levels, 2471 struct iommu_table **ptbl) 2472 { 2473 struct pnv_ioda_pe *pe = container_of(table_group, struct pnv_ioda_pe, 2474 table_group); 2475 int nid = pe->phb->hose->node; 2476 __u64 bus_offset = num ? pe->tce_bypass_base : table_group->tce32_start; 2477 long ret; 2478 struct iommu_table *tbl; 2479 2480 tbl = pnv_pci_table_alloc(nid); 2481 if (!tbl) 2482 return -ENOMEM; 2483 2484 tbl->it_ops = &pnv_ioda2_iommu_ops; 2485 2486 ret = pnv_pci_ioda2_table_alloc_pages(nid, 2487 bus_offset, page_shift, window_size, 2488 levels, tbl); 2489 if (ret) { 2490 iommu_tce_table_put(tbl); 2491 return ret; 2492 } 2493 2494 *ptbl = tbl; 2495 2496 return 0; 2497 } 2498 2499 static long pnv_pci_ioda2_setup_default_config(struct pnv_ioda_pe *pe) 2500 { 2501 struct iommu_table *tbl = NULL; 2502 long rc; 2503 2504 /* 2505 * crashkernel= specifies the kdump kernel's maximum memory at 2506 * some offset and there is no guaranteed the result is a power 2507 * of 2, which will cause errors later. 2508 */ 2509 const u64 max_memory = __rounddown_pow_of_two(memory_hotplug_max()); 2510 2511 /* 2512 * In memory constrained environments, e.g. kdump kernel, the 2513 * DMA window can be larger than available memory, which will 2514 * cause errors later. 2515 */ 2516 const u64 window_size = min((u64)pe->table_group.tce32_size, max_memory); 2517 2518 rc = pnv_pci_ioda2_create_table(&pe->table_group, 0, 2519 IOMMU_PAGE_SHIFT_4K, 2520 window_size, 2521 POWERNV_IOMMU_DEFAULT_LEVELS, &tbl); 2522 if (rc) { 2523 pe_err(pe, "Failed to create 32-bit TCE table, err %ld", 2524 rc); 2525 return rc; 2526 } 2527 2528 iommu_init_table(tbl, pe->phb->hose->node); 2529 2530 rc = pnv_pci_ioda2_set_window(&pe->table_group, 0, tbl); 2531 if (rc) { 2532 pe_err(pe, "Failed to configure 32-bit TCE table, err %ld\n", 2533 rc); 2534 iommu_tce_table_put(tbl); 2535 return rc; 2536 } 2537 2538 if (!pnv_iommu_bypass_disabled) 2539 pnv_pci_ioda2_set_bypass(pe, true); 2540 2541 /* 2542 * Setting table base here only for carrying iommu_group 2543 * further down to let iommu_add_device() do the job. 2544 * pnv_pci_ioda_dma_dev_setup will override it later anyway. 2545 */ 2546 if (pe->flags & PNV_IODA_PE_DEV) 2547 set_iommu_table_base(&pe->pdev->dev, tbl); 2548 2549 return 0; 2550 } 2551 2552 #if defined(CONFIG_IOMMU_API) || defined(CONFIG_PCI_IOV) 2553 static long pnv_pci_ioda2_unset_window(struct iommu_table_group *table_group, 2554 int num) 2555 { 2556 struct pnv_ioda_pe *pe = container_of(table_group, struct pnv_ioda_pe, 2557 table_group); 2558 struct pnv_phb *phb = pe->phb; 2559 long ret; 2560 2561 pe_info(pe, "Removing DMA window #%d\n", num); 2562 2563 ret = opal_pci_map_pe_dma_window(phb->opal_id, pe->pe_number, 2564 (pe->pe_number << 1) + num, 2565 0/* levels */, 0/* table address */, 2566 0/* table size */, 0/* page size */); 2567 if (ret) 2568 pe_warn(pe, "Unmapping failed, ret = %ld\n", ret); 2569 else 2570 pnv_pci_ioda2_tce_invalidate_pe(pe); 2571 2572 pnv_pci_unlink_table_and_group(table_group->tables[num], table_group); 2573 2574 return ret; 2575 } 2576 #endif 2577 2578 #ifdef CONFIG_IOMMU_API 2579 static unsigned long pnv_pci_ioda2_get_table_size(__u32 page_shift, 2580 __u64 window_size, __u32 levels) 2581 { 2582 unsigned long bytes = 0; 2583 const unsigned window_shift = ilog2(window_size); 2584 unsigned entries_shift = window_shift - page_shift; 2585 unsigned table_shift = entries_shift + 3; 2586 unsigned long tce_table_size = max(0x1000UL, 1UL << table_shift); 2587 unsigned long direct_table_size; 2588 2589 if (!levels || (levels > POWERNV_IOMMU_MAX_LEVELS) || 2590 !is_power_of_2(window_size)) 2591 return 0; 2592 2593 /* Calculate a direct table size from window_size and levels */ 2594 entries_shift = (entries_shift + levels - 1) / levels; 2595 table_shift = entries_shift + 3; 2596 table_shift = max_t(unsigned, table_shift, PAGE_SHIFT); 2597 direct_table_size = 1UL << table_shift; 2598 2599 for ( ; levels; --levels) { 2600 bytes += _ALIGN_UP(tce_table_size, direct_table_size); 2601 2602 tce_table_size /= direct_table_size; 2603 tce_table_size <<= 3; 2604 tce_table_size = max_t(unsigned long, 2605 tce_table_size, direct_table_size); 2606 } 2607 2608 return bytes; 2609 } 2610 2611 static void pnv_ioda2_take_ownership(struct iommu_table_group *table_group) 2612 { 2613 struct pnv_ioda_pe *pe = container_of(table_group, struct pnv_ioda_pe, 2614 table_group); 2615 /* Store @tbl as pnv_pci_ioda2_unset_window() resets it */ 2616 struct iommu_table *tbl = pe->table_group.tables[0]; 2617 2618 pnv_pci_ioda2_set_bypass(pe, false); 2619 pnv_pci_ioda2_unset_window(&pe->table_group, 0); 2620 if (pe->pbus) 2621 pnv_ioda_setup_bus_dma(pe, pe->pbus, false); 2622 iommu_tce_table_put(tbl); 2623 } 2624 2625 static void pnv_ioda2_release_ownership(struct iommu_table_group *table_group) 2626 { 2627 struct pnv_ioda_pe *pe = container_of(table_group, struct pnv_ioda_pe, 2628 table_group); 2629 2630 pnv_pci_ioda2_setup_default_config(pe); 2631 if (pe->pbus) 2632 pnv_ioda_setup_bus_dma(pe, pe->pbus, false); 2633 } 2634 2635 static struct iommu_table_group_ops pnv_pci_ioda2_ops = { 2636 .get_table_size = pnv_pci_ioda2_get_table_size, 2637 .create_table = pnv_pci_ioda2_create_table, 2638 .set_window = pnv_pci_ioda2_set_window, 2639 .unset_window = pnv_pci_ioda2_unset_window, 2640 .take_ownership = pnv_ioda2_take_ownership, 2641 .release_ownership = pnv_ioda2_release_ownership, 2642 }; 2643 2644 static int gpe_table_group_to_npe_cb(struct device *dev, void *opaque) 2645 { 2646 struct pci_controller *hose; 2647 struct pnv_phb *phb; 2648 struct pnv_ioda_pe **ptmppe = opaque; 2649 struct pci_dev *pdev = container_of(dev, struct pci_dev, dev); 2650 struct pci_dn *pdn = pci_get_pdn(pdev); 2651 2652 if (!pdn || pdn->pe_number == IODA_INVALID_PE) 2653 return 0; 2654 2655 hose = pci_bus_to_host(pdev->bus); 2656 phb = hose->private_data; 2657 if (phb->type != PNV_PHB_NPU_NVLINK) 2658 return 0; 2659 2660 *ptmppe = &phb->ioda.pe_array[pdn->pe_number]; 2661 2662 return 1; 2663 } 2664 2665 /* 2666 * This returns PE of associated NPU. 2667 * This assumes that NPU is in the same IOMMU group with GPU and there is 2668 * no other PEs. 2669 */ 2670 static struct pnv_ioda_pe *gpe_table_group_to_npe( 2671 struct iommu_table_group *table_group) 2672 { 2673 struct pnv_ioda_pe *npe = NULL; 2674 int ret = iommu_group_for_each_dev(table_group->group, &npe, 2675 gpe_table_group_to_npe_cb); 2676 2677 BUG_ON(!ret || !npe); 2678 2679 return npe; 2680 } 2681 2682 static long pnv_pci_ioda2_npu_set_window(struct iommu_table_group *table_group, 2683 int num, struct iommu_table *tbl) 2684 { 2685 struct pnv_ioda_pe *npe = gpe_table_group_to_npe(table_group); 2686 int num2 = (num == 0) ? 1 : 0; 2687 long ret = pnv_pci_ioda2_set_window(table_group, num, tbl); 2688 2689 if (ret) 2690 return ret; 2691 2692 if (table_group->tables[num2]) 2693 pnv_npu_unset_window(npe, num2); 2694 2695 ret = pnv_npu_set_window(npe, num, tbl); 2696 if (ret) { 2697 pnv_pci_ioda2_unset_window(table_group, num); 2698 if (table_group->tables[num2]) 2699 pnv_npu_set_window(npe, num2, 2700 table_group->tables[num2]); 2701 } 2702 2703 return ret; 2704 } 2705 2706 static long pnv_pci_ioda2_npu_unset_window( 2707 struct iommu_table_group *table_group, 2708 int num) 2709 { 2710 struct pnv_ioda_pe *npe = gpe_table_group_to_npe(table_group); 2711 int num2 = (num == 0) ? 1 : 0; 2712 long ret = pnv_pci_ioda2_unset_window(table_group, num); 2713 2714 if (ret) 2715 return ret; 2716 2717 if (!npe->table_group.tables[num]) 2718 return 0; 2719 2720 ret = pnv_npu_unset_window(npe, num); 2721 if (ret) 2722 return ret; 2723 2724 if (table_group->tables[num2]) 2725 ret = pnv_npu_set_window(npe, num2, table_group->tables[num2]); 2726 2727 return ret; 2728 } 2729 2730 static void pnv_ioda2_npu_take_ownership(struct iommu_table_group *table_group) 2731 { 2732 /* 2733 * Detach NPU first as pnv_ioda2_take_ownership() will destroy 2734 * the iommu_table if 32bit DMA is enabled. 2735 */ 2736 pnv_npu_take_ownership(gpe_table_group_to_npe(table_group)); 2737 pnv_ioda2_take_ownership(table_group); 2738 } 2739 2740 static struct iommu_table_group_ops pnv_pci_ioda2_npu_ops = { 2741 .get_table_size = pnv_pci_ioda2_get_table_size, 2742 .create_table = pnv_pci_ioda2_create_table, 2743 .set_window = pnv_pci_ioda2_npu_set_window, 2744 .unset_window = pnv_pci_ioda2_npu_unset_window, 2745 .take_ownership = pnv_ioda2_npu_take_ownership, 2746 .release_ownership = pnv_ioda2_release_ownership, 2747 }; 2748 2749 static void pnv_pci_ioda_setup_iommu_api(void) 2750 { 2751 struct pci_controller *hose, *tmp; 2752 struct pnv_phb *phb; 2753 struct pnv_ioda_pe *pe, *gpe; 2754 2755 /* 2756 * Now we have all PHBs discovered, time to add NPU devices to 2757 * the corresponding IOMMU groups. 2758 */ 2759 list_for_each_entry_safe(hose, tmp, &hose_list, list_node) { 2760 phb = hose->private_data; 2761 2762 if (phb->type != PNV_PHB_NPU_NVLINK) 2763 continue; 2764 2765 list_for_each_entry(pe, &phb->ioda.pe_list, list) { 2766 gpe = pnv_pci_npu_setup_iommu(pe); 2767 if (gpe) 2768 gpe->table_group.ops = &pnv_pci_ioda2_npu_ops; 2769 } 2770 } 2771 } 2772 #else /* !CONFIG_IOMMU_API */ 2773 static void pnv_pci_ioda_setup_iommu_api(void) { }; 2774 #endif 2775 2776 static __be64 *pnv_pci_ioda2_table_do_alloc_pages(int nid, unsigned shift, 2777 unsigned levels, unsigned long limit, 2778 unsigned long *current_offset, unsigned long *total_allocated) 2779 { 2780 struct page *tce_mem = NULL; 2781 __be64 *addr, *tmp; 2782 unsigned order = max_t(unsigned, shift, PAGE_SHIFT) - PAGE_SHIFT; 2783 unsigned long allocated = 1UL << (order + PAGE_SHIFT); 2784 unsigned entries = 1UL << (shift - 3); 2785 long i; 2786 2787 tce_mem = alloc_pages_node(nid, GFP_KERNEL, order); 2788 if (!tce_mem) { 2789 pr_err("Failed to allocate a TCE memory, order=%d\n", order); 2790 return NULL; 2791 } 2792 addr = page_address(tce_mem); 2793 memset(addr, 0, allocated); 2794 *total_allocated += allocated; 2795 2796 --levels; 2797 if (!levels) { 2798 *current_offset += allocated; 2799 return addr; 2800 } 2801 2802 for (i = 0; i < entries; ++i) { 2803 tmp = pnv_pci_ioda2_table_do_alloc_pages(nid, shift, 2804 levels, limit, current_offset, total_allocated); 2805 if (!tmp) 2806 break; 2807 2808 addr[i] = cpu_to_be64(__pa(tmp) | 2809 TCE_PCI_READ | TCE_PCI_WRITE); 2810 2811 if (*current_offset >= limit) 2812 break; 2813 } 2814 2815 return addr; 2816 } 2817 2818 static void pnv_pci_ioda2_table_do_free_pages(__be64 *addr, 2819 unsigned long size, unsigned level); 2820 2821 static long pnv_pci_ioda2_table_alloc_pages(int nid, __u64 bus_offset, 2822 __u32 page_shift, __u64 window_size, __u32 levels, 2823 struct iommu_table *tbl) 2824 { 2825 void *addr; 2826 unsigned long offset = 0, level_shift, total_allocated = 0; 2827 const unsigned window_shift = ilog2(window_size); 2828 unsigned entries_shift = window_shift - page_shift; 2829 unsigned table_shift = max_t(unsigned, entries_shift + 3, PAGE_SHIFT); 2830 const unsigned long tce_table_size = 1UL << table_shift; 2831 2832 if (!levels || (levels > POWERNV_IOMMU_MAX_LEVELS)) 2833 return -EINVAL; 2834 2835 if (!is_power_of_2(window_size)) 2836 return -EINVAL; 2837 2838 /* Adjust direct table size from window_size and levels */ 2839 entries_shift = (entries_shift + levels - 1) / levels; 2840 level_shift = entries_shift + 3; 2841 level_shift = max_t(unsigned, level_shift, PAGE_SHIFT); 2842 2843 if ((level_shift - 3) * levels + page_shift >= 55) 2844 return -EINVAL; 2845 2846 /* Allocate TCE table */ 2847 addr = pnv_pci_ioda2_table_do_alloc_pages(nid, level_shift, 2848 levels, tce_table_size, &offset, &total_allocated); 2849 2850 /* addr==NULL means that the first level allocation failed */ 2851 if (!addr) 2852 return -ENOMEM; 2853 2854 /* 2855 * First level was allocated but some lower level failed as 2856 * we did not allocate as much as we wanted, 2857 * release partially allocated table. 2858 */ 2859 if (offset < tce_table_size) { 2860 pnv_pci_ioda2_table_do_free_pages(addr, 2861 1ULL << (level_shift - 3), levels - 1); 2862 return -ENOMEM; 2863 } 2864 2865 /* Setup linux iommu table */ 2866 pnv_pci_setup_iommu_table(tbl, addr, tce_table_size, bus_offset, 2867 page_shift); 2868 tbl->it_level_size = 1ULL << (level_shift - 3); 2869 tbl->it_indirect_levels = levels - 1; 2870 tbl->it_allocated_size = total_allocated; 2871 2872 pr_devel("Created TCE table: ws=%08llx ts=%lx @%08llx\n", 2873 window_size, tce_table_size, bus_offset); 2874 2875 return 0; 2876 } 2877 2878 static void pnv_pci_ioda2_table_do_free_pages(__be64 *addr, 2879 unsigned long size, unsigned level) 2880 { 2881 const unsigned long addr_ul = (unsigned long) addr & 2882 ~(TCE_PCI_READ | TCE_PCI_WRITE); 2883 2884 if (level) { 2885 long i; 2886 u64 *tmp = (u64 *) addr_ul; 2887 2888 for (i = 0; i < size; ++i) { 2889 unsigned long hpa = be64_to_cpu(tmp[i]); 2890 2891 if (!(hpa & (TCE_PCI_READ | TCE_PCI_WRITE))) 2892 continue; 2893 2894 pnv_pci_ioda2_table_do_free_pages(__va(hpa), size, 2895 level - 1); 2896 } 2897 } 2898 2899 free_pages(addr_ul, get_order(size << 3)); 2900 } 2901 2902 static void pnv_pci_ioda2_table_free_pages(struct iommu_table *tbl) 2903 { 2904 const unsigned long size = tbl->it_indirect_levels ? 2905 tbl->it_level_size : tbl->it_size; 2906 2907 if (!tbl->it_size) 2908 return; 2909 2910 pnv_pci_ioda2_table_do_free_pages((__be64 *)tbl->it_base, size, 2911 tbl->it_indirect_levels); 2912 } 2913 2914 static unsigned long pnv_ioda_parse_tce_sizes(struct pnv_phb *phb) 2915 { 2916 struct pci_controller *hose = phb->hose; 2917 struct device_node *dn = hose->dn; 2918 unsigned long mask = 0; 2919 int i, rc, count; 2920 u32 val; 2921 2922 count = of_property_count_u32_elems(dn, "ibm,supported-tce-sizes"); 2923 if (count <= 0) { 2924 mask = SZ_4K | SZ_64K; 2925 /* Add 16M for POWER8 by default */ 2926 if (cpu_has_feature(CPU_FTR_ARCH_207S) && 2927 !cpu_has_feature(CPU_FTR_ARCH_300)) 2928 mask |= SZ_16M; 2929 return mask; 2930 } 2931 2932 for (i = 0; i < count; i++) { 2933 rc = of_property_read_u32_index(dn, "ibm,supported-tce-sizes", 2934 i, &val); 2935 if (rc == 0) 2936 mask |= 1ULL << val; 2937 } 2938 2939 return mask; 2940 } 2941 2942 static void pnv_pci_ioda2_setup_dma_pe(struct pnv_phb *phb, 2943 struct pnv_ioda_pe *pe) 2944 { 2945 int64_t rc; 2946 2947 if (!pnv_pci_ioda_pe_dma_weight(pe)) 2948 return; 2949 2950 /* TVE #1 is selected by PCI address bit 59 */ 2951 pe->tce_bypass_base = 1ull << 59; 2952 2953 iommu_register_group(&pe->table_group, phb->hose->global_number, 2954 pe->pe_number); 2955 2956 /* The PE will reserve all possible 32-bits space */ 2957 pe_info(pe, "Setting up 32-bit TCE table at 0..%08x\n", 2958 phb->ioda.m32_pci_base); 2959 2960 /* Setup linux iommu table */ 2961 pe->table_group.tce32_start = 0; 2962 pe->table_group.tce32_size = phb->ioda.m32_pci_base; 2963 pe->table_group.max_dynamic_windows_supported = 2964 IOMMU_TABLE_GROUP_MAX_TABLES; 2965 pe->table_group.max_levels = POWERNV_IOMMU_MAX_LEVELS; 2966 pe->table_group.pgsizes = pnv_ioda_parse_tce_sizes(phb); 2967 #ifdef CONFIG_IOMMU_API 2968 pe->table_group.ops = &pnv_pci_ioda2_ops; 2969 #endif 2970 2971 rc = pnv_pci_ioda2_setup_default_config(pe); 2972 if (rc) 2973 return; 2974 2975 if (pe->flags & (PNV_IODA_PE_BUS | PNV_IODA_PE_BUS_ALL)) 2976 pnv_ioda_setup_bus_dma(pe, pe->pbus, true); 2977 } 2978 2979 #ifdef CONFIG_PCI_MSI 2980 int64_t pnv_opal_pci_msi_eoi(struct irq_chip *chip, unsigned int hw_irq) 2981 { 2982 struct pnv_phb *phb = container_of(chip, struct pnv_phb, 2983 ioda.irq_chip); 2984 2985 return opal_pci_msi_eoi(phb->opal_id, hw_irq); 2986 } 2987 2988 static void pnv_ioda2_msi_eoi(struct irq_data *d) 2989 { 2990 int64_t rc; 2991 unsigned int hw_irq = (unsigned int)irqd_to_hwirq(d); 2992 struct irq_chip *chip = irq_data_get_irq_chip(d); 2993 2994 rc = pnv_opal_pci_msi_eoi(chip, hw_irq); 2995 WARN_ON_ONCE(rc); 2996 2997 icp_native_eoi(d); 2998 } 2999 3000 3001 void pnv_set_msi_irq_chip(struct pnv_phb *phb, unsigned int virq) 3002 { 3003 struct irq_data *idata; 3004 struct irq_chip *ichip; 3005 3006 /* The MSI EOI OPAL call is only needed on PHB3 */ 3007 if (phb->model != PNV_PHB_MODEL_PHB3) 3008 return; 3009 3010 if (!phb->ioda.irq_chip_init) { 3011 /* 3012 * First time we setup an MSI IRQ, we need to setup the 3013 * corresponding IRQ chip to route correctly. 3014 */ 3015 idata = irq_get_irq_data(virq); 3016 ichip = irq_data_get_irq_chip(idata); 3017 phb->ioda.irq_chip_init = 1; 3018 phb->ioda.irq_chip = *ichip; 3019 phb->ioda.irq_chip.irq_eoi = pnv_ioda2_msi_eoi; 3020 } 3021 irq_set_chip(virq, &phb->ioda.irq_chip); 3022 } 3023 3024 /* 3025 * Returns true iff chip is something that we could call 3026 * pnv_opal_pci_msi_eoi for. 3027 */ 3028 bool is_pnv_opal_msi(struct irq_chip *chip) 3029 { 3030 return chip->irq_eoi == pnv_ioda2_msi_eoi; 3031 } 3032 EXPORT_SYMBOL_GPL(is_pnv_opal_msi); 3033 3034 static int pnv_pci_ioda_msi_setup(struct pnv_phb *phb, struct pci_dev *dev, 3035 unsigned int hwirq, unsigned int virq, 3036 unsigned int is_64, struct msi_msg *msg) 3037 { 3038 struct pnv_ioda_pe *pe = pnv_ioda_get_pe(dev); 3039 unsigned int xive_num = hwirq - phb->msi_base; 3040 __be32 data; 3041 int rc; 3042 3043 /* No PE assigned ? bail out ... no MSI for you ! */ 3044 if (pe == NULL) 3045 return -ENXIO; 3046 3047 /* Check if we have an MVE */ 3048 if (pe->mve_number < 0) 3049 return -ENXIO; 3050 3051 /* Force 32-bit MSI on some broken devices */ 3052 if (dev->no_64bit_msi) 3053 is_64 = 0; 3054 3055 /* Assign XIVE to PE */ 3056 rc = opal_pci_set_xive_pe(phb->opal_id, pe->pe_number, xive_num); 3057 if (rc) { 3058 pr_warn("%s: OPAL error %d setting XIVE %d PE\n", 3059 pci_name(dev), rc, xive_num); 3060 return -EIO; 3061 } 3062 3063 if (is_64) { 3064 __be64 addr64; 3065 3066 rc = opal_get_msi_64(phb->opal_id, pe->mve_number, xive_num, 1, 3067 &addr64, &data); 3068 if (rc) { 3069 pr_warn("%s: OPAL error %d getting 64-bit MSI data\n", 3070 pci_name(dev), rc); 3071 return -EIO; 3072 } 3073 msg->address_hi = be64_to_cpu(addr64) >> 32; 3074 msg->address_lo = be64_to_cpu(addr64) & 0xfffffffful; 3075 } else { 3076 __be32 addr32; 3077 3078 rc = opal_get_msi_32(phb->opal_id, pe->mve_number, xive_num, 1, 3079 &addr32, &data); 3080 if (rc) { 3081 pr_warn("%s: OPAL error %d getting 32-bit MSI data\n", 3082 pci_name(dev), rc); 3083 return -EIO; 3084 } 3085 msg->address_hi = 0; 3086 msg->address_lo = be32_to_cpu(addr32); 3087 } 3088 msg->data = be32_to_cpu(data); 3089 3090 pnv_set_msi_irq_chip(phb, virq); 3091 3092 pr_devel("%s: %s-bit MSI on hwirq %x (xive #%d)," 3093 " address=%x_%08x data=%x PE# %x\n", 3094 pci_name(dev), is_64 ? "64" : "32", hwirq, xive_num, 3095 msg->address_hi, msg->address_lo, data, pe->pe_number); 3096 3097 return 0; 3098 } 3099 3100 static void pnv_pci_init_ioda_msis(struct pnv_phb *phb) 3101 { 3102 unsigned int count; 3103 const __be32 *prop = of_get_property(phb->hose->dn, 3104 "ibm,opal-msi-ranges", NULL); 3105 if (!prop) { 3106 /* BML Fallback */ 3107 prop = of_get_property(phb->hose->dn, "msi-ranges", NULL); 3108 } 3109 if (!prop) 3110 return; 3111 3112 phb->msi_base = be32_to_cpup(prop); 3113 count = be32_to_cpup(prop + 1); 3114 if (msi_bitmap_alloc(&phb->msi_bmp, count, phb->hose->dn)) { 3115 pr_err("PCI %d: Failed to allocate MSI bitmap !\n", 3116 phb->hose->global_number); 3117 return; 3118 } 3119 3120 phb->msi_setup = pnv_pci_ioda_msi_setup; 3121 phb->msi32_support = 1; 3122 pr_info(" Allocated bitmap for %d MSIs (base IRQ 0x%x)\n", 3123 count, phb->msi_base); 3124 } 3125 #else 3126 static void pnv_pci_init_ioda_msis(struct pnv_phb *phb) { } 3127 #endif /* CONFIG_PCI_MSI */ 3128 3129 #ifdef CONFIG_PCI_IOV 3130 static void pnv_pci_ioda_fixup_iov_resources(struct pci_dev *pdev) 3131 { 3132 struct pci_controller *hose = pci_bus_to_host(pdev->bus); 3133 struct pnv_phb *phb = hose->private_data; 3134 const resource_size_t gate = phb->ioda.m64_segsize >> 2; 3135 struct resource *res; 3136 int i; 3137 resource_size_t size, total_vf_bar_sz; 3138 struct pci_dn *pdn; 3139 int mul, total_vfs; 3140 3141 if (!pdev->is_physfn || pdev->is_added) 3142 return; 3143 3144 pdn = pci_get_pdn(pdev); 3145 pdn->vfs_expanded = 0; 3146 pdn->m64_single_mode = false; 3147 3148 total_vfs = pci_sriov_get_totalvfs(pdev); 3149 mul = phb->ioda.total_pe_num; 3150 total_vf_bar_sz = 0; 3151 3152 for (i = 0; i < PCI_SRIOV_NUM_BARS; i++) { 3153 res = &pdev->resource[i + PCI_IOV_RESOURCES]; 3154 if (!res->flags || res->parent) 3155 continue; 3156 if (!pnv_pci_is_m64_flags(res->flags)) { 3157 dev_warn(&pdev->dev, "Don't support SR-IOV with" 3158 " non M64 VF BAR%d: %pR. \n", 3159 i, res); 3160 goto truncate_iov; 3161 } 3162 3163 total_vf_bar_sz += pci_iov_resource_size(pdev, 3164 i + PCI_IOV_RESOURCES); 3165 3166 /* 3167 * If bigger than quarter of M64 segment size, just round up 3168 * power of two. 3169 * 3170 * Generally, one M64 BAR maps one IOV BAR. To avoid conflict 3171 * with other devices, IOV BAR size is expanded to be 3172 * (total_pe * VF_BAR_size). When VF_BAR_size is half of M64 3173 * segment size , the expanded size would equal to half of the 3174 * whole M64 space size, which will exhaust the M64 Space and 3175 * limit the system flexibility. This is a design decision to 3176 * set the boundary to quarter of the M64 segment size. 3177 */ 3178 if (total_vf_bar_sz > gate) { 3179 mul = roundup_pow_of_two(total_vfs); 3180 dev_info(&pdev->dev, 3181 "VF BAR Total IOV size %llx > %llx, roundup to %d VFs\n", 3182 total_vf_bar_sz, gate, mul); 3183 pdn->m64_single_mode = true; 3184 break; 3185 } 3186 } 3187 3188 for (i = 0; i < PCI_SRIOV_NUM_BARS; i++) { 3189 res = &pdev->resource[i + PCI_IOV_RESOURCES]; 3190 if (!res->flags || res->parent) 3191 continue; 3192 3193 size = pci_iov_resource_size(pdev, i + PCI_IOV_RESOURCES); 3194 /* 3195 * On PHB3, the minimum size alignment of M64 BAR in single 3196 * mode is 32MB. 3197 */ 3198 if (pdn->m64_single_mode && (size < SZ_32M)) 3199 goto truncate_iov; 3200 dev_dbg(&pdev->dev, " Fixing VF BAR%d: %pR to\n", i, res); 3201 res->end = res->start + size * mul - 1; 3202 dev_dbg(&pdev->dev, " %pR\n", res); 3203 dev_info(&pdev->dev, "VF BAR%d: %pR (expanded to %d VFs for PE alignment)", 3204 i, res, mul); 3205 } 3206 pdn->vfs_expanded = mul; 3207 3208 return; 3209 3210 truncate_iov: 3211 /* To save MMIO space, IOV BAR is truncated. */ 3212 for (i = 0; i < PCI_SRIOV_NUM_BARS; i++) { 3213 res = &pdev->resource[i + PCI_IOV_RESOURCES]; 3214 res->flags = 0; 3215 res->end = res->start - 1; 3216 } 3217 } 3218 #endif /* CONFIG_PCI_IOV */ 3219 3220 static void pnv_ioda_setup_pe_res(struct pnv_ioda_pe *pe, 3221 struct resource *res) 3222 { 3223 struct pnv_phb *phb = pe->phb; 3224 struct pci_bus_region region; 3225 int index; 3226 int64_t rc; 3227 3228 if (!res || !res->flags || res->start > res->end) 3229 return; 3230 3231 if (res->flags & IORESOURCE_IO) { 3232 region.start = res->start - phb->ioda.io_pci_base; 3233 region.end = res->end - phb->ioda.io_pci_base; 3234 index = region.start / phb->ioda.io_segsize; 3235 3236 while (index < phb->ioda.total_pe_num && 3237 region.start <= region.end) { 3238 phb->ioda.io_segmap[index] = pe->pe_number; 3239 rc = opal_pci_map_pe_mmio_window(phb->opal_id, 3240 pe->pe_number, OPAL_IO_WINDOW_TYPE, 0, index); 3241 if (rc != OPAL_SUCCESS) { 3242 pr_err("%s: Error %lld mapping IO segment#%d to PE#%x\n", 3243 __func__, rc, index, pe->pe_number); 3244 break; 3245 } 3246 3247 region.start += phb->ioda.io_segsize; 3248 index++; 3249 } 3250 } else if ((res->flags & IORESOURCE_MEM) && 3251 !pnv_pci_is_m64(phb, res)) { 3252 region.start = res->start - 3253 phb->hose->mem_offset[0] - 3254 phb->ioda.m32_pci_base; 3255 region.end = res->end - 3256 phb->hose->mem_offset[0] - 3257 phb->ioda.m32_pci_base; 3258 index = region.start / phb->ioda.m32_segsize; 3259 3260 while (index < phb->ioda.total_pe_num && 3261 region.start <= region.end) { 3262 phb->ioda.m32_segmap[index] = pe->pe_number; 3263 rc = opal_pci_map_pe_mmio_window(phb->opal_id, 3264 pe->pe_number, OPAL_M32_WINDOW_TYPE, 0, index); 3265 if (rc != OPAL_SUCCESS) { 3266 pr_err("%s: Error %lld mapping M32 segment#%d to PE#%x", 3267 __func__, rc, index, pe->pe_number); 3268 break; 3269 } 3270 3271 region.start += phb->ioda.m32_segsize; 3272 index++; 3273 } 3274 } 3275 } 3276 3277 /* 3278 * This function is supposed to be called on basis of PE from top 3279 * to bottom style. So the the I/O or MMIO segment assigned to 3280 * parent PE could be overridden by its child PEs if necessary. 3281 */ 3282 static void pnv_ioda_setup_pe_seg(struct pnv_ioda_pe *pe) 3283 { 3284 struct pci_dev *pdev; 3285 int i; 3286 3287 /* 3288 * NOTE: We only care PCI bus based PE for now. For PCI 3289 * device based PE, for example SRIOV sensitive VF should 3290 * be figured out later. 3291 */ 3292 BUG_ON(!(pe->flags & (PNV_IODA_PE_BUS | PNV_IODA_PE_BUS_ALL))); 3293 3294 list_for_each_entry(pdev, &pe->pbus->devices, bus_list) { 3295 for (i = 0; i <= PCI_ROM_RESOURCE; i++) 3296 pnv_ioda_setup_pe_res(pe, &pdev->resource[i]); 3297 3298 /* 3299 * If the PE contains all subordinate PCI buses, the 3300 * windows of the child bridges should be mapped to 3301 * the PE as well. 3302 */ 3303 if (!(pe->flags & PNV_IODA_PE_BUS_ALL) || !pci_is_bridge(pdev)) 3304 continue; 3305 for (i = 0; i < PCI_BRIDGE_RESOURCE_NUM; i++) 3306 pnv_ioda_setup_pe_res(pe, 3307 &pdev->resource[PCI_BRIDGE_RESOURCES + i]); 3308 } 3309 } 3310 3311 #ifdef CONFIG_DEBUG_FS 3312 static int pnv_pci_diag_data_set(void *data, u64 val) 3313 { 3314 struct pci_controller *hose; 3315 struct pnv_phb *phb; 3316 s64 ret; 3317 3318 if (val != 1ULL) 3319 return -EINVAL; 3320 3321 hose = (struct pci_controller *)data; 3322 if (!hose || !hose->private_data) 3323 return -ENODEV; 3324 3325 phb = hose->private_data; 3326 3327 /* Retrieve the diag data from firmware */ 3328 ret = opal_pci_get_phb_diag_data2(phb->opal_id, phb->diag_data, 3329 phb->diag_data_size); 3330 if (ret != OPAL_SUCCESS) 3331 return -EIO; 3332 3333 /* Print the diag data to the kernel log */ 3334 pnv_pci_dump_phb_diag_data(phb->hose, phb->diag_data); 3335 return 0; 3336 } 3337 3338 DEFINE_SIMPLE_ATTRIBUTE(pnv_pci_diag_data_fops, NULL, 3339 pnv_pci_diag_data_set, "%llu\n"); 3340 3341 #endif /* CONFIG_DEBUG_FS */ 3342 3343 static void pnv_pci_ioda_create_dbgfs(void) 3344 { 3345 #ifdef CONFIG_DEBUG_FS 3346 struct pci_controller *hose, *tmp; 3347 struct pnv_phb *phb; 3348 char name[16]; 3349 3350 list_for_each_entry_safe(hose, tmp, &hose_list, list_node) { 3351 phb = hose->private_data; 3352 3353 /* Notify initialization of PHB done */ 3354 phb->initialized = 1; 3355 3356 sprintf(name, "PCI%04x", hose->global_number); 3357 phb->dbgfs = debugfs_create_dir(name, powerpc_debugfs_root); 3358 if (!phb->dbgfs) { 3359 pr_warn("%s: Error on creating debugfs on PHB#%x\n", 3360 __func__, hose->global_number); 3361 continue; 3362 } 3363 3364 debugfs_create_file("dump_diag_regs", 0200, phb->dbgfs, hose, 3365 &pnv_pci_diag_data_fops); 3366 } 3367 #endif /* CONFIG_DEBUG_FS */ 3368 } 3369 3370 static void pnv_pci_ioda_fixup(void) 3371 { 3372 pnv_pci_ioda_setup_PEs(); 3373 pnv_pci_ioda_setup_iommu_api(); 3374 pnv_pci_ioda_create_dbgfs(); 3375 3376 #ifdef CONFIG_EEH 3377 pnv_eeh_post_init(); 3378 #endif 3379 } 3380 3381 /* 3382 * Returns the alignment for I/O or memory windows for P2P 3383 * bridges. That actually depends on how PEs are segmented. 3384 * For now, we return I/O or M32 segment size for PE sensitive 3385 * P2P bridges. Otherwise, the default values (4KiB for I/O, 3386 * 1MiB for memory) will be returned. 3387 * 3388 * The current PCI bus might be put into one PE, which was 3389 * create against the parent PCI bridge. For that case, we 3390 * needn't enlarge the alignment so that we can save some 3391 * resources. 3392 */ 3393 static resource_size_t pnv_pci_window_alignment(struct pci_bus *bus, 3394 unsigned long type) 3395 { 3396 struct pci_dev *bridge; 3397 struct pci_controller *hose = pci_bus_to_host(bus); 3398 struct pnv_phb *phb = hose->private_data; 3399 int num_pci_bridges = 0; 3400 3401 bridge = bus->self; 3402 while (bridge) { 3403 if (pci_pcie_type(bridge) == PCI_EXP_TYPE_PCI_BRIDGE) { 3404 num_pci_bridges++; 3405 if (num_pci_bridges >= 2) 3406 return 1; 3407 } 3408 3409 bridge = bridge->bus->self; 3410 } 3411 3412 /* 3413 * We fall back to M32 if M64 isn't supported. We enforce the M64 3414 * alignment for any 64-bit resource, PCIe doesn't care and 3415 * bridges only do 64-bit prefetchable anyway. 3416 */ 3417 if (phb->ioda.m64_segsize && pnv_pci_is_m64_flags(type)) 3418 return phb->ioda.m64_segsize; 3419 if (type & IORESOURCE_MEM) 3420 return phb->ioda.m32_segsize; 3421 3422 return phb->ioda.io_segsize; 3423 } 3424 3425 /* 3426 * We are updating root port or the upstream port of the 3427 * bridge behind the root port with PHB's windows in order 3428 * to accommodate the changes on required resources during 3429 * PCI (slot) hotplug, which is connected to either root 3430 * port or the downstream ports of PCIe switch behind the 3431 * root port. 3432 */ 3433 static void pnv_pci_fixup_bridge_resources(struct pci_bus *bus, 3434 unsigned long type) 3435 { 3436 struct pci_controller *hose = pci_bus_to_host(bus); 3437 struct pnv_phb *phb = hose->private_data; 3438 struct pci_dev *bridge = bus->self; 3439 struct resource *r, *w; 3440 bool msi_region = false; 3441 int i; 3442 3443 /* Check if we need apply fixup to the bridge's windows */ 3444 if (!pci_is_root_bus(bridge->bus) && 3445 !pci_is_root_bus(bridge->bus->self->bus)) 3446 return; 3447 3448 /* Fixup the resources */ 3449 for (i = 0; i < PCI_BRIDGE_RESOURCE_NUM; i++) { 3450 r = &bridge->resource[PCI_BRIDGE_RESOURCES + i]; 3451 if (!r->flags || !r->parent) 3452 continue; 3453 3454 w = NULL; 3455 if (r->flags & type & IORESOURCE_IO) 3456 w = &hose->io_resource; 3457 else if (pnv_pci_is_m64(phb, r) && 3458 (type & IORESOURCE_PREFETCH) && 3459 phb->ioda.m64_segsize) 3460 w = &hose->mem_resources[1]; 3461 else if (r->flags & type & IORESOURCE_MEM) { 3462 w = &hose->mem_resources[0]; 3463 msi_region = true; 3464 } 3465 3466 r->start = w->start; 3467 r->end = w->end; 3468 3469 /* The 64KB 32-bits MSI region shouldn't be included in 3470 * the 32-bits bridge window. Otherwise, we can see strange 3471 * issues. One of them is EEH error observed on Garrison. 3472 * 3473 * Exclude top 1MB region which is the minimal alignment of 3474 * 32-bits bridge window. 3475 */ 3476 if (msi_region) { 3477 r->end += 0x10000; 3478 r->end -= 0x100000; 3479 } 3480 } 3481 } 3482 3483 static void pnv_pci_setup_bridge(struct pci_bus *bus, unsigned long type) 3484 { 3485 struct pci_controller *hose = pci_bus_to_host(bus); 3486 struct pnv_phb *phb = hose->private_data; 3487 struct pci_dev *bridge = bus->self; 3488 struct pnv_ioda_pe *pe; 3489 bool all = (pci_pcie_type(bridge) == PCI_EXP_TYPE_PCI_BRIDGE); 3490 3491 /* Extend bridge's windows if necessary */ 3492 pnv_pci_fixup_bridge_resources(bus, type); 3493 3494 /* The PE for root bus should be realized before any one else */ 3495 if (!phb->ioda.root_pe_populated) { 3496 pe = pnv_ioda_setup_bus_PE(phb->hose->bus, false); 3497 if (pe) { 3498 phb->ioda.root_pe_idx = pe->pe_number; 3499 phb->ioda.root_pe_populated = true; 3500 } 3501 } 3502 3503 /* Don't assign PE to PCI bus, which doesn't have subordinate devices */ 3504 if (list_empty(&bus->devices)) 3505 return; 3506 3507 /* Reserve PEs according to used M64 resources */ 3508 if (phb->reserve_m64_pe) 3509 phb->reserve_m64_pe(bus, NULL, all); 3510 3511 /* 3512 * Assign PE. We might run here because of partial hotplug. 3513 * For the case, we just pick up the existing PE and should 3514 * not allocate resources again. 3515 */ 3516 pe = pnv_ioda_setup_bus_PE(bus, all); 3517 if (!pe) 3518 return; 3519 3520 pnv_ioda_setup_pe_seg(pe); 3521 switch (phb->type) { 3522 case PNV_PHB_IODA1: 3523 pnv_pci_ioda1_setup_dma_pe(phb, pe); 3524 break; 3525 case PNV_PHB_IODA2: 3526 pnv_pci_ioda2_setup_dma_pe(phb, pe); 3527 break; 3528 default: 3529 pr_warn("%s: No DMA for PHB#%x (type %d)\n", 3530 __func__, phb->hose->global_number, phb->type); 3531 } 3532 } 3533 3534 static resource_size_t pnv_pci_default_alignment(void) 3535 { 3536 return PAGE_SIZE; 3537 } 3538 3539 #ifdef CONFIG_PCI_IOV 3540 static resource_size_t pnv_pci_iov_resource_alignment(struct pci_dev *pdev, 3541 int resno) 3542 { 3543 struct pci_controller *hose = pci_bus_to_host(pdev->bus); 3544 struct pnv_phb *phb = hose->private_data; 3545 struct pci_dn *pdn = pci_get_pdn(pdev); 3546 resource_size_t align; 3547 3548 /* 3549 * On PowerNV platform, IOV BAR is mapped by M64 BAR to enable the 3550 * SR-IOV. While from hardware perspective, the range mapped by M64 3551 * BAR should be size aligned. 3552 * 3553 * When IOV BAR is mapped with M64 BAR in Single PE mode, the extra 3554 * powernv-specific hardware restriction is gone. But if just use the 3555 * VF BAR size as the alignment, PF BAR / VF BAR may be allocated with 3556 * in one segment of M64 #15, which introduces the PE conflict between 3557 * PF and VF. Based on this, the minimum alignment of an IOV BAR is 3558 * m64_segsize. 3559 * 3560 * This function returns the total IOV BAR size if M64 BAR is in 3561 * Shared PE mode or just VF BAR size if not. 3562 * If the M64 BAR is in Single PE mode, return the VF BAR size or 3563 * M64 segment size if IOV BAR size is less. 3564 */ 3565 align = pci_iov_resource_size(pdev, resno); 3566 if (!pdn->vfs_expanded) 3567 return align; 3568 if (pdn->m64_single_mode) 3569 return max(align, (resource_size_t)phb->ioda.m64_segsize); 3570 3571 return pdn->vfs_expanded * align; 3572 } 3573 #endif /* CONFIG_PCI_IOV */ 3574 3575 /* Prevent enabling devices for which we couldn't properly 3576 * assign a PE 3577 */ 3578 bool pnv_pci_enable_device_hook(struct pci_dev *dev) 3579 { 3580 struct pci_controller *hose = pci_bus_to_host(dev->bus); 3581 struct pnv_phb *phb = hose->private_data; 3582 struct pci_dn *pdn; 3583 3584 /* The function is probably called while the PEs have 3585 * not be created yet. For example, resource reassignment 3586 * during PCI probe period. We just skip the check if 3587 * PEs isn't ready. 3588 */ 3589 if (!phb->initialized) 3590 return true; 3591 3592 pdn = pci_get_pdn(dev); 3593 if (!pdn || pdn->pe_number == IODA_INVALID_PE) 3594 return false; 3595 3596 return true; 3597 } 3598 3599 static long pnv_pci_ioda1_unset_window(struct iommu_table_group *table_group, 3600 int num) 3601 { 3602 struct pnv_ioda_pe *pe = container_of(table_group, 3603 struct pnv_ioda_pe, table_group); 3604 struct pnv_phb *phb = pe->phb; 3605 unsigned int idx; 3606 long rc; 3607 3608 pe_info(pe, "Removing DMA window #%d\n", num); 3609 for (idx = 0; idx < phb->ioda.dma32_count; idx++) { 3610 if (phb->ioda.dma32_segmap[idx] != pe->pe_number) 3611 continue; 3612 3613 rc = opal_pci_map_pe_dma_window(phb->opal_id, pe->pe_number, 3614 idx, 0, 0ul, 0ul, 0ul); 3615 if (rc != OPAL_SUCCESS) { 3616 pe_warn(pe, "Failure %ld unmapping DMA32 segment#%d\n", 3617 rc, idx); 3618 return rc; 3619 } 3620 3621 phb->ioda.dma32_segmap[idx] = IODA_INVALID_PE; 3622 } 3623 3624 pnv_pci_unlink_table_and_group(table_group->tables[num], table_group); 3625 return OPAL_SUCCESS; 3626 } 3627 3628 static void pnv_pci_ioda1_release_pe_dma(struct pnv_ioda_pe *pe) 3629 { 3630 unsigned int weight = pnv_pci_ioda_pe_dma_weight(pe); 3631 struct iommu_table *tbl = pe->table_group.tables[0]; 3632 int64_t rc; 3633 3634 if (!weight) 3635 return; 3636 3637 rc = pnv_pci_ioda1_unset_window(&pe->table_group, 0); 3638 if (rc != OPAL_SUCCESS) 3639 return; 3640 3641 pnv_pci_p7ioc_tce_invalidate(tbl, tbl->it_offset, tbl->it_size, false); 3642 if (pe->table_group.group) { 3643 iommu_group_put(pe->table_group.group); 3644 WARN_ON(pe->table_group.group); 3645 } 3646 3647 free_pages(tbl->it_base, get_order(tbl->it_size << 3)); 3648 iommu_tce_table_put(tbl); 3649 } 3650 3651 static void pnv_pci_ioda2_release_pe_dma(struct pnv_ioda_pe *pe) 3652 { 3653 struct iommu_table *tbl = pe->table_group.tables[0]; 3654 unsigned int weight = pnv_pci_ioda_pe_dma_weight(pe); 3655 #ifdef CONFIG_IOMMU_API 3656 int64_t rc; 3657 #endif 3658 3659 if (!weight) 3660 return; 3661 3662 #ifdef CONFIG_IOMMU_API 3663 rc = pnv_pci_ioda2_unset_window(&pe->table_group, 0); 3664 if (rc) 3665 pe_warn(pe, "OPAL error %ld release DMA window\n", rc); 3666 #endif 3667 3668 pnv_pci_ioda2_set_bypass(pe, false); 3669 if (pe->table_group.group) { 3670 iommu_group_put(pe->table_group.group); 3671 WARN_ON(pe->table_group.group); 3672 } 3673 3674 iommu_tce_table_put(tbl); 3675 } 3676 3677 static void pnv_ioda_free_pe_seg(struct pnv_ioda_pe *pe, 3678 unsigned short win, 3679 unsigned int *map) 3680 { 3681 struct pnv_phb *phb = pe->phb; 3682 int idx; 3683 int64_t rc; 3684 3685 for (idx = 0; idx < phb->ioda.total_pe_num; idx++) { 3686 if (map[idx] != pe->pe_number) 3687 continue; 3688 3689 if (win == OPAL_M64_WINDOW_TYPE) 3690 rc = opal_pci_map_pe_mmio_window(phb->opal_id, 3691 phb->ioda.reserved_pe_idx, win, 3692 idx / PNV_IODA1_M64_SEGS, 3693 idx % PNV_IODA1_M64_SEGS); 3694 else 3695 rc = opal_pci_map_pe_mmio_window(phb->opal_id, 3696 phb->ioda.reserved_pe_idx, win, 0, idx); 3697 3698 if (rc != OPAL_SUCCESS) 3699 pe_warn(pe, "Error %ld unmapping (%d) segment#%d\n", 3700 rc, win, idx); 3701 3702 map[idx] = IODA_INVALID_PE; 3703 } 3704 } 3705 3706 static void pnv_ioda_release_pe_seg(struct pnv_ioda_pe *pe) 3707 { 3708 struct pnv_phb *phb = pe->phb; 3709 3710 if (phb->type == PNV_PHB_IODA1) { 3711 pnv_ioda_free_pe_seg(pe, OPAL_IO_WINDOW_TYPE, 3712 phb->ioda.io_segmap); 3713 pnv_ioda_free_pe_seg(pe, OPAL_M32_WINDOW_TYPE, 3714 phb->ioda.m32_segmap); 3715 pnv_ioda_free_pe_seg(pe, OPAL_M64_WINDOW_TYPE, 3716 phb->ioda.m64_segmap); 3717 } else if (phb->type == PNV_PHB_IODA2) { 3718 pnv_ioda_free_pe_seg(pe, OPAL_M32_WINDOW_TYPE, 3719 phb->ioda.m32_segmap); 3720 } 3721 } 3722 3723 static void pnv_ioda_release_pe(struct pnv_ioda_pe *pe) 3724 { 3725 struct pnv_phb *phb = pe->phb; 3726 struct pnv_ioda_pe *slave, *tmp; 3727 3728 list_del(&pe->list); 3729 switch (phb->type) { 3730 case PNV_PHB_IODA1: 3731 pnv_pci_ioda1_release_pe_dma(pe); 3732 break; 3733 case PNV_PHB_IODA2: 3734 pnv_pci_ioda2_release_pe_dma(pe); 3735 break; 3736 default: 3737 WARN_ON(1); 3738 } 3739 3740 pnv_ioda_release_pe_seg(pe); 3741 pnv_ioda_deconfigure_pe(pe->phb, pe); 3742 3743 /* Release slave PEs in the compound PE */ 3744 if (pe->flags & PNV_IODA_PE_MASTER) { 3745 list_for_each_entry_safe(slave, tmp, &pe->slaves, list) { 3746 list_del(&slave->list); 3747 pnv_ioda_free_pe(slave); 3748 } 3749 } 3750 3751 /* 3752 * The PE for root bus can be removed because of hotplug in EEH 3753 * recovery for fenced PHB error. We need to mark the PE dead so 3754 * that it can be populated again in PCI hot add path. The PE 3755 * shouldn't be destroyed as it's the global reserved resource. 3756 */ 3757 if (phb->ioda.root_pe_populated && 3758 phb->ioda.root_pe_idx == pe->pe_number) 3759 phb->ioda.root_pe_populated = false; 3760 else 3761 pnv_ioda_free_pe(pe); 3762 } 3763 3764 static void pnv_pci_release_device(struct pci_dev *pdev) 3765 { 3766 struct pci_controller *hose = pci_bus_to_host(pdev->bus); 3767 struct pnv_phb *phb = hose->private_data; 3768 struct pci_dn *pdn = pci_get_pdn(pdev); 3769 struct pnv_ioda_pe *pe; 3770 3771 if (pdev->is_virtfn) 3772 return; 3773 3774 if (!pdn || pdn->pe_number == IODA_INVALID_PE) 3775 return; 3776 3777 /* 3778 * PCI hotplug can happen as part of EEH error recovery. The @pdn 3779 * isn't removed and added afterwards in this scenario. We should 3780 * set the PE number in @pdn to an invalid one. Otherwise, the PE's 3781 * device count is decreased on removing devices while failing to 3782 * be increased on adding devices. It leads to unbalanced PE's device 3783 * count and eventually make normal PCI hotplug path broken. 3784 */ 3785 pe = &phb->ioda.pe_array[pdn->pe_number]; 3786 pdn->pe_number = IODA_INVALID_PE; 3787 3788 WARN_ON(--pe->device_count < 0); 3789 if (pe->device_count == 0) 3790 pnv_ioda_release_pe(pe); 3791 } 3792 3793 static void pnv_pci_ioda_shutdown(struct pci_controller *hose) 3794 { 3795 struct pnv_phb *phb = hose->private_data; 3796 3797 opal_pci_reset(phb->opal_id, OPAL_RESET_PCI_IODA_TABLE, 3798 OPAL_ASSERT_RESET); 3799 } 3800 3801 static const struct pci_controller_ops pnv_pci_ioda_controller_ops = { 3802 .dma_dev_setup = pnv_pci_dma_dev_setup, 3803 .dma_bus_setup = pnv_pci_dma_bus_setup, 3804 #ifdef CONFIG_PCI_MSI 3805 .setup_msi_irqs = pnv_setup_msi_irqs, 3806 .teardown_msi_irqs = pnv_teardown_msi_irqs, 3807 #endif 3808 .enable_device_hook = pnv_pci_enable_device_hook, 3809 .release_device = pnv_pci_release_device, 3810 .window_alignment = pnv_pci_window_alignment, 3811 .setup_bridge = pnv_pci_setup_bridge, 3812 .reset_secondary_bus = pnv_pci_reset_secondary_bus, 3813 .dma_set_mask = pnv_pci_ioda_dma_set_mask, 3814 .dma_get_required_mask = pnv_pci_ioda_dma_get_required_mask, 3815 .shutdown = pnv_pci_ioda_shutdown, 3816 }; 3817 3818 static int pnv_npu_dma_set_mask(struct pci_dev *npdev, u64 dma_mask) 3819 { 3820 dev_err_once(&npdev->dev, 3821 "%s operation unsupported for NVLink devices\n", 3822 __func__); 3823 return -EPERM; 3824 } 3825 3826 static const struct pci_controller_ops pnv_npu_ioda_controller_ops = { 3827 .dma_dev_setup = pnv_pci_dma_dev_setup, 3828 #ifdef CONFIG_PCI_MSI 3829 .setup_msi_irqs = pnv_setup_msi_irqs, 3830 .teardown_msi_irqs = pnv_teardown_msi_irqs, 3831 #endif 3832 .enable_device_hook = pnv_pci_enable_device_hook, 3833 .window_alignment = pnv_pci_window_alignment, 3834 .reset_secondary_bus = pnv_pci_reset_secondary_bus, 3835 .dma_set_mask = pnv_npu_dma_set_mask, 3836 .shutdown = pnv_pci_ioda_shutdown, 3837 }; 3838 3839 static const struct pci_controller_ops pnv_npu_ocapi_ioda_controller_ops = { 3840 .enable_device_hook = pnv_pci_enable_device_hook, 3841 .window_alignment = pnv_pci_window_alignment, 3842 .reset_secondary_bus = pnv_pci_reset_secondary_bus, 3843 .shutdown = pnv_pci_ioda_shutdown, 3844 }; 3845 3846 #ifdef CONFIG_CXL_BASE 3847 const struct pci_controller_ops pnv_cxl_cx4_ioda_controller_ops = { 3848 .dma_dev_setup = pnv_pci_dma_dev_setup, 3849 .dma_bus_setup = pnv_pci_dma_bus_setup, 3850 .enable_device_hook = pnv_cxl_enable_device_hook, 3851 .disable_device = pnv_cxl_disable_device, 3852 .release_device = pnv_pci_release_device, 3853 .window_alignment = pnv_pci_window_alignment, 3854 .setup_bridge = pnv_pci_setup_bridge, 3855 .reset_secondary_bus = pnv_pci_reset_secondary_bus, 3856 .dma_set_mask = pnv_pci_ioda_dma_set_mask, 3857 .dma_get_required_mask = pnv_pci_ioda_dma_get_required_mask, 3858 .shutdown = pnv_pci_ioda_shutdown, 3859 }; 3860 #endif 3861 3862 static void __init pnv_pci_init_ioda_phb(struct device_node *np, 3863 u64 hub_id, int ioda_type) 3864 { 3865 struct pci_controller *hose; 3866 struct pnv_phb *phb; 3867 unsigned long size, m64map_off, m32map_off, pemap_off; 3868 unsigned long iomap_off = 0, dma32map_off = 0; 3869 struct resource r; 3870 const __be64 *prop64; 3871 const __be32 *prop32; 3872 int len; 3873 unsigned int segno; 3874 u64 phb_id; 3875 void *aux; 3876 long rc; 3877 3878 if (!of_device_is_available(np)) 3879 return; 3880 3881 pr_info("Initializing %s PHB (%pOF)\n", pnv_phb_names[ioda_type], np); 3882 3883 prop64 = of_get_property(np, "ibm,opal-phbid", NULL); 3884 if (!prop64) { 3885 pr_err(" Missing \"ibm,opal-phbid\" property !\n"); 3886 return; 3887 } 3888 phb_id = be64_to_cpup(prop64); 3889 pr_debug(" PHB-ID : 0x%016llx\n", phb_id); 3890 3891 phb = memblock_virt_alloc(sizeof(*phb), 0); 3892 3893 /* Allocate PCI controller */ 3894 phb->hose = hose = pcibios_alloc_controller(np); 3895 if (!phb->hose) { 3896 pr_err(" Can't allocate PCI controller for %pOF\n", 3897 np); 3898 memblock_free(__pa(phb), sizeof(struct pnv_phb)); 3899 return; 3900 } 3901 3902 spin_lock_init(&phb->lock); 3903 prop32 = of_get_property(np, "bus-range", &len); 3904 if (prop32 && len == 8) { 3905 hose->first_busno = be32_to_cpu(prop32[0]); 3906 hose->last_busno = be32_to_cpu(prop32[1]); 3907 } else { 3908 pr_warn(" Broken <bus-range> on %pOF\n", np); 3909 hose->first_busno = 0; 3910 hose->last_busno = 0xff; 3911 } 3912 hose->private_data = phb; 3913 phb->hub_id = hub_id; 3914 phb->opal_id = phb_id; 3915 phb->type = ioda_type; 3916 mutex_init(&phb->ioda.pe_alloc_mutex); 3917 3918 /* Detect specific models for error handling */ 3919 if (of_device_is_compatible(np, "ibm,p7ioc-pciex")) 3920 phb->model = PNV_PHB_MODEL_P7IOC; 3921 else if (of_device_is_compatible(np, "ibm,power8-pciex")) 3922 phb->model = PNV_PHB_MODEL_PHB3; 3923 else if (of_device_is_compatible(np, "ibm,power8-npu-pciex")) 3924 phb->model = PNV_PHB_MODEL_NPU; 3925 else if (of_device_is_compatible(np, "ibm,power9-npu-pciex")) 3926 phb->model = PNV_PHB_MODEL_NPU2; 3927 else 3928 phb->model = PNV_PHB_MODEL_UNKNOWN; 3929 3930 /* Initialize diagnostic data buffer */ 3931 prop32 = of_get_property(np, "ibm,phb-diag-data-size", NULL); 3932 if (prop32) 3933 phb->diag_data_size = be32_to_cpup(prop32); 3934 else 3935 phb->diag_data_size = PNV_PCI_DIAG_BUF_SIZE; 3936 3937 phb->diag_data = memblock_virt_alloc(phb->diag_data_size, 0); 3938 3939 /* Parse 32-bit and IO ranges (if any) */ 3940 pci_process_bridge_OF_ranges(hose, np, !hose->global_number); 3941 3942 /* Get registers */ 3943 if (!of_address_to_resource(np, 0, &r)) { 3944 phb->regs_phys = r.start; 3945 phb->regs = ioremap(r.start, resource_size(&r)); 3946 if (phb->regs == NULL) 3947 pr_err(" Failed to map registers !\n"); 3948 } 3949 3950 /* Initialize more IODA stuff */ 3951 phb->ioda.total_pe_num = 1; 3952 prop32 = of_get_property(np, "ibm,opal-num-pes", NULL); 3953 if (prop32) 3954 phb->ioda.total_pe_num = be32_to_cpup(prop32); 3955 prop32 = of_get_property(np, "ibm,opal-reserved-pe", NULL); 3956 if (prop32) 3957 phb->ioda.reserved_pe_idx = be32_to_cpup(prop32); 3958 3959 /* Invalidate RID to PE# mapping */ 3960 for (segno = 0; segno < ARRAY_SIZE(phb->ioda.pe_rmap); segno++) 3961 phb->ioda.pe_rmap[segno] = IODA_INVALID_PE; 3962 3963 /* Parse 64-bit MMIO range */ 3964 pnv_ioda_parse_m64_window(phb); 3965 3966 phb->ioda.m32_size = resource_size(&hose->mem_resources[0]); 3967 /* FW Has already off top 64k of M32 space (MSI space) */ 3968 phb->ioda.m32_size += 0x10000; 3969 3970 phb->ioda.m32_segsize = phb->ioda.m32_size / phb->ioda.total_pe_num; 3971 phb->ioda.m32_pci_base = hose->mem_resources[0].start - hose->mem_offset[0]; 3972 phb->ioda.io_size = hose->pci_io_size; 3973 phb->ioda.io_segsize = phb->ioda.io_size / phb->ioda.total_pe_num; 3974 phb->ioda.io_pci_base = 0; /* XXX calculate this ? */ 3975 3976 /* Calculate how many 32-bit TCE segments we have */ 3977 phb->ioda.dma32_count = phb->ioda.m32_pci_base / 3978 PNV_IODA1_DMA32_SEGSIZE; 3979 3980 /* Allocate aux data & arrays. We don't have IO ports on PHB3 */ 3981 size = _ALIGN_UP(max_t(unsigned, phb->ioda.total_pe_num, 8) / 8, 3982 sizeof(unsigned long)); 3983 m64map_off = size; 3984 size += phb->ioda.total_pe_num * sizeof(phb->ioda.m64_segmap[0]); 3985 m32map_off = size; 3986 size += phb->ioda.total_pe_num * sizeof(phb->ioda.m32_segmap[0]); 3987 if (phb->type == PNV_PHB_IODA1) { 3988 iomap_off = size; 3989 size += phb->ioda.total_pe_num * sizeof(phb->ioda.io_segmap[0]); 3990 dma32map_off = size; 3991 size += phb->ioda.dma32_count * 3992 sizeof(phb->ioda.dma32_segmap[0]); 3993 } 3994 pemap_off = size; 3995 size += phb->ioda.total_pe_num * sizeof(struct pnv_ioda_pe); 3996 aux = memblock_virt_alloc(size, 0); 3997 phb->ioda.pe_alloc = aux; 3998 phb->ioda.m64_segmap = aux + m64map_off; 3999 phb->ioda.m32_segmap = aux + m32map_off; 4000 for (segno = 0; segno < phb->ioda.total_pe_num; segno++) { 4001 phb->ioda.m64_segmap[segno] = IODA_INVALID_PE; 4002 phb->ioda.m32_segmap[segno] = IODA_INVALID_PE; 4003 } 4004 if (phb->type == PNV_PHB_IODA1) { 4005 phb->ioda.io_segmap = aux + iomap_off; 4006 for (segno = 0; segno < phb->ioda.total_pe_num; segno++) 4007 phb->ioda.io_segmap[segno] = IODA_INVALID_PE; 4008 4009 phb->ioda.dma32_segmap = aux + dma32map_off; 4010 for (segno = 0; segno < phb->ioda.dma32_count; segno++) 4011 phb->ioda.dma32_segmap[segno] = IODA_INVALID_PE; 4012 } 4013 phb->ioda.pe_array = aux + pemap_off; 4014 4015 /* 4016 * Choose PE number for root bus, which shouldn't have 4017 * M64 resources consumed by its child devices. To pick 4018 * the PE number adjacent to the reserved one if possible. 4019 */ 4020 pnv_ioda_reserve_pe(phb, phb->ioda.reserved_pe_idx); 4021 if (phb->ioda.reserved_pe_idx == 0) { 4022 phb->ioda.root_pe_idx = 1; 4023 pnv_ioda_reserve_pe(phb, phb->ioda.root_pe_idx); 4024 } else if (phb->ioda.reserved_pe_idx == (phb->ioda.total_pe_num - 1)) { 4025 phb->ioda.root_pe_idx = phb->ioda.reserved_pe_idx - 1; 4026 pnv_ioda_reserve_pe(phb, phb->ioda.root_pe_idx); 4027 } else { 4028 phb->ioda.root_pe_idx = IODA_INVALID_PE; 4029 } 4030 4031 INIT_LIST_HEAD(&phb->ioda.pe_list); 4032 mutex_init(&phb->ioda.pe_list_mutex); 4033 4034 /* Calculate how many 32-bit TCE segments we have */ 4035 phb->ioda.dma32_count = phb->ioda.m32_pci_base / 4036 PNV_IODA1_DMA32_SEGSIZE; 4037 4038 #if 0 /* We should really do that ... */ 4039 rc = opal_pci_set_phb_mem_window(opal->phb_id, 4040 window_type, 4041 window_num, 4042 starting_real_address, 4043 starting_pci_address, 4044 segment_size); 4045 #endif 4046 4047 pr_info(" %03d (%03d) PE's M32: 0x%x [segment=0x%x]\n", 4048 phb->ioda.total_pe_num, phb->ioda.reserved_pe_idx, 4049 phb->ioda.m32_size, phb->ioda.m32_segsize); 4050 if (phb->ioda.m64_size) 4051 pr_info(" M64: 0x%lx [segment=0x%lx]\n", 4052 phb->ioda.m64_size, phb->ioda.m64_segsize); 4053 if (phb->ioda.io_size) 4054 pr_info(" IO: 0x%x [segment=0x%x]\n", 4055 phb->ioda.io_size, phb->ioda.io_segsize); 4056 4057 4058 phb->hose->ops = &pnv_pci_ops; 4059 phb->get_pe_state = pnv_ioda_get_pe_state; 4060 phb->freeze_pe = pnv_ioda_freeze_pe; 4061 phb->unfreeze_pe = pnv_ioda_unfreeze_pe; 4062 4063 /* Setup MSI support */ 4064 pnv_pci_init_ioda_msis(phb); 4065 4066 /* 4067 * We pass the PCI probe flag PCI_REASSIGN_ALL_RSRC here 4068 * to let the PCI core do resource assignment. It's supposed 4069 * that the PCI core will do correct I/O and MMIO alignment 4070 * for the P2P bridge bars so that each PCI bus (excluding 4071 * the child P2P bridges) can form individual PE. 4072 */ 4073 ppc_md.pcibios_fixup = pnv_pci_ioda_fixup; 4074 4075 switch (phb->type) { 4076 case PNV_PHB_NPU_NVLINK: 4077 hose->controller_ops = pnv_npu_ioda_controller_ops; 4078 break; 4079 case PNV_PHB_NPU_OCAPI: 4080 hose->controller_ops = pnv_npu_ocapi_ioda_controller_ops; 4081 break; 4082 default: 4083 phb->dma_dev_setup = pnv_pci_ioda_dma_dev_setup; 4084 hose->controller_ops = pnv_pci_ioda_controller_ops; 4085 } 4086 4087 ppc_md.pcibios_default_alignment = pnv_pci_default_alignment; 4088 4089 #ifdef CONFIG_PCI_IOV 4090 ppc_md.pcibios_fixup_sriov = pnv_pci_ioda_fixup_iov_resources; 4091 ppc_md.pcibios_iov_resource_alignment = pnv_pci_iov_resource_alignment; 4092 ppc_md.pcibios_sriov_enable = pnv_pcibios_sriov_enable; 4093 ppc_md.pcibios_sriov_disable = pnv_pcibios_sriov_disable; 4094 #endif 4095 4096 pci_add_flags(PCI_REASSIGN_ALL_RSRC); 4097 4098 /* Reset IODA tables to a clean state */ 4099 rc = opal_pci_reset(phb_id, OPAL_RESET_PCI_IODA_TABLE, OPAL_ASSERT_RESET); 4100 if (rc) 4101 pr_warn(" OPAL Error %ld performing IODA table reset !\n", rc); 4102 4103 /* 4104 * If we're running in kdump kernel, the previous kernel never 4105 * shutdown PCI devices correctly. We already got IODA table 4106 * cleaned out. So we have to issue PHB reset to stop all PCI 4107 * transactions from previous kernel. The ppc_pci_reset_phbs 4108 * kernel parameter will force this reset too. 4109 */ 4110 if (is_kdump_kernel() || pci_reset_phbs) { 4111 pr_info(" Issue PHB reset ...\n"); 4112 pnv_eeh_phb_reset(hose, EEH_RESET_FUNDAMENTAL); 4113 pnv_eeh_phb_reset(hose, EEH_RESET_DEACTIVATE); 4114 } 4115 4116 /* Remove M64 resource if we can't configure it successfully */ 4117 if (!phb->init_m64 || phb->init_m64(phb)) 4118 hose->mem_resources[1].flags = 0; 4119 } 4120 4121 void __init pnv_pci_init_ioda2_phb(struct device_node *np) 4122 { 4123 pnv_pci_init_ioda_phb(np, 0, PNV_PHB_IODA2); 4124 } 4125 4126 void __init pnv_pci_init_npu_phb(struct device_node *np) 4127 { 4128 pnv_pci_init_ioda_phb(np, 0, PNV_PHB_NPU_NVLINK); 4129 } 4130 4131 void __init pnv_pci_init_npu2_opencapi_phb(struct device_node *np) 4132 { 4133 pnv_pci_init_ioda_phb(np, 0, PNV_PHB_NPU_OCAPI); 4134 } 4135 4136 static void pnv_npu2_opencapi_cfg_size_fixup(struct pci_dev *dev) 4137 { 4138 struct pci_controller *hose = pci_bus_to_host(dev->bus); 4139 struct pnv_phb *phb = hose->private_data; 4140 4141 if (!machine_is(powernv)) 4142 return; 4143 4144 if (phb->type == PNV_PHB_NPU_OCAPI) 4145 dev->cfg_size = PCI_CFG_SPACE_EXP_SIZE; 4146 } 4147 DECLARE_PCI_FIXUP_EARLY(PCI_ANY_ID, PCI_ANY_ID, pnv_npu2_opencapi_cfg_size_fixup); 4148 4149 void __init pnv_pci_init_ioda_hub(struct device_node *np) 4150 { 4151 struct device_node *phbn; 4152 const __be64 *prop64; 4153 u64 hub_id; 4154 4155 pr_info("Probing IODA IO-Hub %pOF\n", np); 4156 4157 prop64 = of_get_property(np, "ibm,opal-hubid", NULL); 4158 if (!prop64) { 4159 pr_err(" Missing \"ibm,opal-hubid\" property !\n"); 4160 return; 4161 } 4162 hub_id = be64_to_cpup(prop64); 4163 pr_devel(" HUB-ID : 0x%016llx\n", hub_id); 4164 4165 /* Count child PHBs */ 4166 for_each_child_of_node(np, phbn) { 4167 /* Look for IODA1 PHBs */ 4168 if (of_device_is_compatible(phbn, "ibm,ioda-phb")) 4169 pnv_pci_init_ioda_phb(phbn, hub_id, PNV_PHB_IODA1); 4170 } 4171 } 4172