12874c5fdSThomas Gleixner // SPDX-License-Identifier: GPL-2.0-or-later
2184cd4a3SBenjamin Herrenschmidt /*
3184cd4a3SBenjamin Herrenschmidt * Support PCI/PCIe on PowerNV platforms
4184cd4a3SBenjamin Herrenschmidt *
5184cd4a3SBenjamin Herrenschmidt * Copyright 2011 Benjamin Herrenschmidt, IBM Corp.
6184cd4a3SBenjamin Herrenschmidt */
7184cd4a3SBenjamin Herrenschmidt
8cee72d5bSBenjamin Herrenschmidt #undef DEBUG
9184cd4a3SBenjamin Herrenschmidt
10184cd4a3SBenjamin Herrenschmidt #include <linux/kernel.h>
11184cd4a3SBenjamin Herrenschmidt #include <linux/pci.h>
12361f2a2aSGavin Shan #include <linux/crash_dump.h>
13184cd4a3SBenjamin Herrenschmidt #include <linux/delay.h>
14184cd4a3SBenjamin Herrenschmidt #include <linux/string.h>
15184cd4a3SBenjamin Herrenschmidt #include <linux/init.h>
1657c8a661SMike Rapoport #include <linux/memblock.h>
17184cd4a3SBenjamin Herrenschmidt #include <linux/irq.h>
18184cd4a3SBenjamin Herrenschmidt #include <linux/io.h>
19184cd4a3SBenjamin Herrenschmidt #include <linux/msi.h>
20ac9a5889SAlexey Kardashevskiy #include <linux/iommu.h>
21e57080f1SAlexey Kardashevskiy #include <linux/rculist.h>
224793d65dSAlexey Kardashevskiy #include <linux/sizes.h>
23dbf77fedSAneesh Kumar K.V #include <linux/debugfs.h>
24e6f6390aSChristophe Leroy #include <linux/of_address.h>
25e6f6390aSChristophe Leroy #include <linux/of_irq.h>
26184cd4a3SBenjamin Herrenschmidt
27184cd4a3SBenjamin Herrenschmidt #include <asm/sections.h>
28184cd4a3SBenjamin Herrenschmidt #include <asm/io.h>
29184cd4a3SBenjamin Herrenschmidt #include <asm/pci-bridge.h>
30184cd4a3SBenjamin Herrenschmidt #include <asm/machdep.h>
31fb1b55d6SGavin Shan #include <asm/msi_bitmap.h>
32184cd4a3SBenjamin Herrenschmidt #include <asm/ppc-pci.h>
33184cd4a3SBenjamin Herrenschmidt #include <asm/opal.h>
34184cd4a3SBenjamin Herrenschmidt #include <asm/iommu.h>
35184cd4a3SBenjamin Herrenschmidt #include <asm/tce.h>
36137436c9SGavin Shan #include <asm/xics.h>
37262af557SGuo Chao #include <asm/firmware.h>
3880c49c7eSIan Munsie #include <asm/pnv-pci.h>
39aca6913fSAlexey Kardashevskiy #include <asm/mmzone.h>
400fcfe224SCédric Le Goater #include <asm/xive.h>
4180c49c7eSIan Munsie
42ec249dd8SMichael Neuling #include <misc/cxl-base.h>
43184cd4a3SBenjamin Herrenschmidt
44184cd4a3SBenjamin Herrenschmidt #include "powernv.h"
45184cd4a3SBenjamin Herrenschmidt #include "pci.h"
4644bda4b7SHari Vyas #include "../../../../drivers/pci/pci.h"
47184cd4a3SBenjamin Herrenschmidt
4898e61df5SJoel Stanley /* This array is indexed with enum pnv_phb_type */
4998e61df5SJoel Stanley static const char * const pnv_phb_names[] = { "IODA2", "NPU_OCAPI" };
50aca6913fSAlexey Kardashevskiy
51c498a4f9SChristoph Hellwig static void pnv_pci_ioda2_set_bypass(struct pnv_ioda_pe *pe, bool enable);
52dc3d8f85SOliver O'Halloran static void pnv_pci_configure_bus(struct pci_bus *bus);
53c498a4f9SChristoph Hellwig
pe_level_printk(const struct pnv_ioda_pe * pe,const char * level,const char * fmt,...)547d623e42SAlexey Kardashevskiy void pe_level_printk(const struct pnv_ioda_pe *pe, const char *level,
556d31c2faSJoe Perches const char *fmt, ...)
566d31c2faSJoe Perches {
576d31c2faSJoe Perches struct va_format vaf;
586d31c2faSJoe Perches va_list args;
596d31c2faSJoe Perches char pfix[32];
60184cd4a3SBenjamin Herrenschmidt
616d31c2faSJoe Perches va_start(args, fmt);
626d31c2faSJoe Perches
636d31c2faSJoe Perches vaf.fmt = fmt;
646d31c2faSJoe Perches vaf.va = &args;
656d31c2faSJoe Perches
66781a868fSWei Yang if (pe->flags & PNV_IODA_PE_DEV)
6714be3756SWolfram Sang strscpy(pfix, dev_name(&pe->pdev->dev), sizeof(pfix));
68781a868fSWei Yang else if (pe->flags & (PNV_IODA_PE_BUS | PNV_IODA_PE_BUS_ALL))
696d31c2faSJoe Perches sprintf(pfix, "%04x:%02x ",
706d31c2faSJoe Perches pci_domain_nr(pe->pbus), pe->pbus->number);
71781a868fSWei Yang #ifdef CONFIG_PCI_IOV
72781a868fSWei Yang else if (pe->flags & PNV_IODA_PE_VF)
73781a868fSWei Yang sprintf(pfix, "%04x:%02x:%2x.%d",
74781a868fSWei Yang pci_domain_nr(pe->parent_dev->bus),
75781a868fSWei Yang (pe->rid & 0xff00) >> 8,
76781a868fSWei Yang PCI_SLOT(pe->rid), PCI_FUNC(pe->rid));
77781a868fSWei Yang #endif /* CONFIG_PCI_IOV*/
786d31c2faSJoe Perches
791f52f176SRussell Currey printk("%spci %s: [PE# %.2x] %pV",
806d31c2faSJoe Perches level, pfix, pe->pe_number, &vaf);
816d31c2faSJoe Perches
826d31c2faSJoe Perches va_end(args);
836d31c2faSJoe Perches }
846d31c2faSJoe Perches
854e287840SThadeu Lima de Souza Cascardo static bool pnv_iommu_bypass_disabled __read_mostly;
8645baee14SGuilherme G. Piccoli static bool pci_reset_phbs __read_mostly;
874e287840SThadeu Lima de Souza Cascardo
iommu_setup(char * str)884e287840SThadeu Lima de Souza Cascardo static int __init iommu_setup(char *str)
894e287840SThadeu Lima de Souza Cascardo {
904e287840SThadeu Lima de Souza Cascardo if (!str)
914e287840SThadeu Lima de Souza Cascardo return -EINVAL;
924e287840SThadeu Lima de Souza Cascardo
934e287840SThadeu Lima de Souza Cascardo while (*str) {
944e287840SThadeu Lima de Souza Cascardo if (!strncmp(str, "nobypass", 8)) {
954e287840SThadeu Lima de Souza Cascardo pnv_iommu_bypass_disabled = true;
964e287840SThadeu Lima de Souza Cascardo pr_info("PowerNV: IOMMU bypass window disabled.\n");
974e287840SThadeu Lima de Souza Cascardo break;
984e287840SThadeu Lima de Souza Cascardo }
994e287840SThadeu Lima de Souza Cascardo str += strcspn(str, ",");
1004e287840SThadeu Lima de Souza Cascardo if (*str == ',')
1014e287840SThadeu Lima de Souza Cascardo str++;
1024e287840SThadeu Lima de Souza Cascardo }
1034e287840SThadeu Lima de Souza Cascardo
1044e287840SThadeu Lima de Souza Cascardo return 0;
1054e287840SThadeu Lima de Souza Cascardo }
1064e287840SThadeu Lima de Souza Cascardo early_param("iommu", iommu_setup);
1074e287840SThadeu Lima de Souza Cascardo
pci_reset_phbs_setup(char * str)10845baee14SGuilherme G. Piccoli static int __init pci_reset_phbs_setup(char *str)
10945baee14SGuilherme G. Piccoli {
11045baee14SGuilherme G. Piccoli pci_reset_phbs = true;
11145baee14SGuilherme G. Piccoli return 0;
11245baee14SGuilherme G. Piccoli }
11345baee14SGuilherme G. Piccoli
11445baee14SGuilherme G. Piccoli early_param("ppc_pci_reset_phbs", pci_reset_phbs_setup);
11545baee14SGuilherme G. Piccoli
pnv_ioda_init_pe(struct pnv_phb * phb,int pe_no)1161e916772SGavin Shan static struct pnv_ioda_pe *pnv_ioda_init_pe(struct pnv_phb *phb, int pe_no)
1171e916772SGavin Shan {
118313483ddSGavin Shan s64 rc;
119313483ddSGavin Shan
1201e916772SGavin Shan phb->ioda.pe_array[pe_no].phb = phb;
1211e916772SGavin Shan phb->ioda.pe_array[pe_no].pe_number = pe_no;
12201e12629SOliver O'Halloran phb->ioda.pe_array[pe_no].dma_setup_done = false;
1231e916772SGavin Shan
124313483ddSGavin Shan /*
125313483ddSGavin Shan * Clear the PE frozen state as it might be put into frozen state
126313483ddSGavin Shan * in the last PCI remove path. It's not harmful to do so when the
127313483ddSGavin Shan * PE is already in unfrozen state.
128313483ddSGavin Shan */
129313483ddSGavin Shan rc = opal_pci_eeh_freeze_clear(phb->opal_id, pe_no,
130313483ddSGavin Shan OPAL_EEH_ACTION_CLEAR_FREEZE_ALL);
131d4791db5SRussell Currey if (rc != OPAL_SUCCESS && rc != OPAL_UNSUPPORTED)
1321f52f176SRussell Currey pr_warn("%s: Error %lld unfreezing PHB#%x-PE#%x\n",
133313483ddSGavin Shan __func__, rc, phb->hose->global_number, pe_no);
134313483ddSGavin Shan
1351e916772SGavin Shan return &phb->ioda.pe_array[pe_no];
1361e916772SGavin Shan }
1371e916772SGavin Shan
pnv_ioda_reserve_pe(struct pnv_phb * phb,int pe_no)1384b82ab18SGavin Shan static void pnv_ioda_reserve_pe(struct pnv_phb *phb, int pe_no)
1394b82ab18SGavin Shan {
14092b8f137SGavin Shan if (!(pe_no >= 0 && pe_no < phb->ioda.total_pe_num)) {
1411f52f176SRussell Currey pr_warn("%s: Invalid PE %x on PHB#%x\n",
1424b82ab18SGavin Shan __func__, pe_no, phb->hose->global_number);
1434b82ab18SGavin Shan return;
1444b82ab18SGavin Shan }
1454b82ab18SGavin Shan
146a4bc676eSOliver O'Halloran mutex_lock(&phb->ioda.pe_alloc_mutex);
147e9dc4d7fSGavin Shan if (test_and_set_bit(pe_no, phb->ioda.pe_alloc))
1481f52f176SRussell Currey pr_debug("%s: PE %x was reserved on PHB#%x\n",
1494b82ab18SGavin Shan __func__, pe_no, phb->hose->global_number);
150a4bc676eSOliver O'Halloran mutex_unlock(&phb->ioda.pe_alloc_mutex);
1514b82ab18SGavin Shan
1521e916772SGavin Shan pnv_ioda_init_pe(phb, pe_no);
1534b82ab18SGavin Shan }
1544b82ab18SGavin Shan
pnv_ioda_alloc_pe(struct pnv_phb * phb,int count)155a4bc676eSOliver O'Halloran struct pnv_ioda_pe *pnv_ioda_alloc_pe(struct pnv_phb *phb, int count)
156184cd4a3SBenjamin Herrenschmidt {
157a4bc676eSOliver O'Halloran struct pnv_ioda_pe *ret = NULL;
158a4bc676eSOliver O'Halloran int run = 0, pe, i;
159184cd4a3SBenjamin Herrenschmidt
160a4bc676eSOliver O'Halloran mutex_lock(&phb->ioda.pe_alloc_mutex);
161a4bc676eSOliver O'Halloran
162a4bc676eSOliver O'Halloran /* scan backwards for a run of @count cleared bits */
1639fcd6f4aSGavin Shan for (pe = phb->ioda.total_pe_num - 1; pe >= 0; pe--) {
164a4bc676eSOliver O'Halloran if (test_bit(pe, phb->ioda.pe_alloc)) {
165a4bc676eSOliver O'Halloran run = 0;
166a4bc676eSOliver O'Halloran continue;
167184cd4a3SBenjamin Herrenschmidt }
168184cd4a3SBenjamin Herrenschmidt
169a4bc676eSOliver O'Halloran run++;
170a4bc676eSOliver O'Halloran if (run == count)
171a4bc676eSOliver O'Halloran break;
172a4bc676eSOliver O'Halloran }
173a4bc676eSOliver O'Halloran if (run != count)
174a4bc676eSOliver O'Halloran goto out;
175a4bc676eSOliver O'Halloran
176a4bc676eSOliver O'Halloran for (i = pe; i < pe + count; i++) {
177a4bc676eSOliver O'Halloran set_bit(i, phb->ioda.pe_alloc);
178a4bc676eSOliver O'Halloran pnv_ioda_init_pe(phb, i);
179a4bc676eSOliver O'Halloran }
180a4bc676eSOliver O'Halloran ret = &phb->ioda.pe_array[pe];
181a4bc676eSOliver O'Halloran
182a4bc676eSOliver O'Halloran out:
183a4bc676eSOliver O'Halloran mutex_unlock(&phb->ioda.pe_alloc_mutex);
184a4bc676eSOliver O'Halloran return ret;
1859fcd6f4aSGavin Shan }
1869fcd6f4aSGavin Shan
pnv_ioda_free_pe(struct pnv_ioda_pe * pe)18737b59ef0SOliver O'Halloran void pnv_ioda_free_pe(struct pnv_ioda_pe *pe)
188184cd4a3SBenjamin Herrenschmidt {
1891e916772SGavin Shan struct pnv_phb *phb = pe->phb;
190caa58f80SGavin Shan unsigned int pe_num = pe->pe_number;
191184cd4a3SBenjamin Herrenschmidt
1921e916772SGavin Shan WARN_ON(pe->pdev);
1931e916772SGavin Shan memset(pe, 0, sizeof(struct pnv_ioda_pe));
194a4bc676eSOliver O'Halloran
195a4bc676eSOliver O'Halloran mutex_lock(&phb->ioda.pe_alloc_mutex);
196caa58f80SGavin Shan clear_bit(pe_num, phb->ioda.pe_alloc);
197a4bc676eSOliver O'Halloran mutex_unlock(&phb->ioda.pe_alloc_mutex);
198184cd4a3SBenjamin Herrenschmidt }
199184cd4a3SBenjamin Herrenschmidt
200262af557SGuo Chao /* The default M64 BAR is shared by all PEs */
pnv_ioda2_init_m64(struct pnv_phb * phb)201262af557SGuo Chao static int pnv_ioda2_init_m64(struct pnv_phb *phb)
202262af557SGuo Chao {
203262af557SGuo Chao const char *desc;
204262af557SGuo Chao struct resource *r;
205262af557SGuo Chao s64 rc;
206262af557SGuo Chao
207262af557SGuo Chao /* Configure the default M64 BAR */
208262af557SGuo Chao rc = opal_pci_set_phb_mem_window(phb->opal_id,
209262af557SGuo Chao OPAL_M64_WINDOW_TYPE,
210262af557SGuo Chao phb->ioda.m64_bar_idx,
211262af557SGuo Chao phb->ioda.m64_base,
212262af557SGuo Chao 0, /* unused */
213262af557SGuo Chao phb->ioda.m64_size);
214262af557SGuo Chao if (rc != OPAL_SUCCESS) {
215262af557SGuo Chao desc = "configuring";
216262af557SGuo Chao goto fail;
217262af557SGuo Chao }
218262af557SGuo Chao
219262af557SGuo Chao /* Enable the default M64 BAR */
220262af557SGuo Chao rc = opal_pci_phb_mmio_enable(phb->opal_id,
221262af557SGuo Chao OPAL_M64_WINDOW_TYPE,
222262af557SGuo Chao phb->ioda.m64_bar_idx,
223262af557SGuo Chao OPAL_ENABLE_M64_SPLIT);
224262af557SGuo Chao if (rc != OPAL_SUCCESS) {
225262af557SGuo Chao desc = "enabling";
226262af557SGuo Chao goto fail;
227262af557SGuo Chao }
228262af557SGuo Chao
229262af557SGuo Chao /*
23063803c39SGavin Shan * Exclude the segments for reserved and root bus PE, which
23163803c39SGavin Shan * are first or last two PEs.
232262af557SGuo Chao */
233262af557SGuo Chao r = &phb->hose->mem_resources[1];
23492b8f137SGavin Shan if (phb->ioda.reserved_pe_idx == 0)
23563803c39SGavin Shan r->start += (2 * phb->ioda.m64_segsize);
23692b8f137SGavin Shan else if (phb->ioda.reserved_pe_idx == (phb->ioda.total_pe_num - 1))
23763803c39SGavin Shan r->end -= (2 * phb->ioda.m64_segsize);
238262af557SGuo Chao else
2391f52f176SRussell Currey pr_warn(" Cannot strip M64 segment for reserved PE#%x\n",
24092b8f137SGavin Shan phb->ioda.reserved_pe_idx);
241262af557SGuo Chao
242262af557SGuo Chao return 0;
243262af557SGuo Chao
244262af557SGuo Chao fail:
245262af557SGuo Chao pr_warn(" Failure %lld %s M64 BAR#%d\n",
246262af557SGuo Chao rc, desc, phb->ioda.m64_bar_idx);
247262af557SGuo Chao opal_pci_phb_mmio_enable(phb->opal_id,
248262af557SGuo Chao OPAL_M64_WINDOW_TYPE,
249262af557SGuo Chao phb->ioda.m64_bar_idx,
250262af557SGuo Chao OPAL_DISABLE_M64);
251262af557SGuo Chao return -EIO;
252262af557SGuo Chao }
253262af557SGuo Chao
pnv_ioda_reserve_dev_m64_pe(struct pci_dev * pdev,unsigned long * pe_bitmap)254c430670aSGavin Shan static void pnv_ioda_reserve_dev_m64_pe(struct pci_dev *pdev,
25596a2f92bSGavin Shan unsigned long *pe_bitmap)
256262af557SGuo Chao {
2575609ffddSOliver O'Halloran struct pnv_phb *phb = pci_bus_to_pnvhb(pdev->bus);
258262af557SGuo Chao struct resource *r;
25996a2f92bSGavin Shan resource_size_t base, sgsz, start, end;
26096a2f92bSGavin Shan int segno, i;
261262af557SGuo Chao
26296a2f92bSGavin Shan base = phb->ioda.m64_base;
26396a2f92bSGavin Shan sgsz = phb->ioda.m64_segsize;
26496a2f92bSGavin Shan for (i = 0; i <= PCI_ROM_RESOURCE; i++) {
26596a2f92bSGavin Shan r = &pdev->resource[i];
2665958d19aSBenjamin Herrenschmidt if (!r->parent || !pnv_pci_is_m64(phb, r))
267262af557SGuo Chao continue;
268262af557SGuo Chao
269e96d904eSChristophe Leroy start = ALIGN_DOWN(r->start - base, sgsz);
270b7115316SChristophe Leroy end = ALIGN(r->end - base, sgsz);
27196a2f92bSGavin Shan for (segno = start / sgsz; segno < end / sgsz; segno++) {
27296a2f92bSGavin Shan if (pe_bitmap)
27396a2f92bSGavin Shan set_bit(segno, pe_bitmap);
27496a2f92bSGavin Shan else
27596a2f92bSGavin Shan pnv_ioda_reserve_pe(phb, segno);
276262af557SGuo Chao }
277262af557SGuo Chao }
278262af557SGuo Chao }
279262af557SGuo Chao
pnv_ioda_reserve_m64_pe(struct pci_bus * bus,unsigned long * pe_bitmap,bool all)280c430670aSGavin Shan static void pnv_ioda_reserve_m64_pe(struct pci_bus *bus,
28196a2f92bSGavin Shan unsigned long *pe_bitmap,
28296a2f92bSGavin Shan bool all)
283262af557SGuo Chao {
284262af557SGuo Chao struct pci_dev *pdev;
28596a2f92bSGavin Shan
28696a2f92bSGavin Shan list_for_each_entry(pdev, &bus->devices, bus_list) {
287c430670aSGavin Shan pnv_ioda_reserve_dev_m64_pe(pdev, pe_bitmap);
28896a2f92bSGavin Shan
28996a2f92bSGavin Shan if (all && pdev->subordinate)
290c430670aSGavin Shan pnv_ioda_reserve_m64_pe(pdev->subordinate,
29196a2f92bSGavin Shan pe_bitmap, all);
29296a2f92bSGavin Shan }
29396a2f92bSGavin Shan }
29496a2f92bSGavin Shan
pnv_ioda_pick_m64_pe(struct pci_bus * bus,bool all)2951e916772SGavin Shan static struct pnv_ioda_pe *pnv_ioda_pick_m64_pe(struct pci_bus *bus, bool all)
296262af557SGuo Chao {
2975609ffddSOliver O'Halloran struct pnv_phb *phb = pci_bus_to_pnvhb(bus);
298262af557SGuo Chao struct pnv_ioda_pe *master_pe, *pe;
299262af557SGuo Chao unsigned long size, *pe_alloc;
30026ba248dSGavin Shan int i;
301262af557SGuo Chao
302262af557SGuo Chao /* Root bus shouldn't use M64 */
303262af557SGuo Chao if (pci_is_root_bus(bus))
3041e916772SGavin Shan return NULL;
305262af557SGuo Chao
306262af557SGuo Chao /* Allocate bitmap */
307b7115316SChristophe Leroy size = ALIGN(phb->ioda.total_pe_num / 8, sizeof(unsigned long));
308262af557SGuo Chao pe_alloc = kzalloc(size, GFP_KERNEL);
309262af557SGuo Chao if (!pe_alloc) {
310262af557SGuo Chao pr_warn("%s: Out of memory !\n",
311262af557SGuo Chao __func__);
3121e916772SGavin Shan return NULL;
313262af557SGuo Chao }
314262af557SGuo Chao
31526ba248dSGavin Shan /* Figure out reserved PE numbers by the PE */
316c430670aSGavin Shan pnv_ioda_reserve_m64_pe(bus, pe_alloc, all);
317262af557SGuo Chao
318262af557SGuo Chao /*
319262af557SGuo Chao * the current bus might not own M64 window and that's all
320262af557SGuo Chao * contributed by its child buses. For the case, we needn't
321262af557SGuo Chao * pick M64 dependent PE#.
322262af557SGuo Chao */
32392b8f137SGavin Shan if (bitmap_empty(pe_alloc, phb->ioda.total_pe_num)) {
324262af557SGuo Chao kfree(pe_alloc);
3251e916772SGavin Shan return NULL;
326262af557SGuo Chao }
327262af557SGuo Chao
328262af557SGuo Chao /*
329262af557SGuo Chao * Figure out the master PE and put all slave PEs to master
330262af557SGuo Chao * PE's list to form compound PE.
331262af557SGuo Chao */
332262af557SGuo Chao master_pe = NULL;
333262af557SGuo Chao i = -1;
33492b8f137SGavin Shan while ((i = find_next_bit(pe_alloc, phb->ioda.total_pe_num, i + 1)) <
33592b8f137SGavin Shan phb->ioda.total_pe_num) {
336262af557SGuo Chao pe = &phb->ioda.pe_array[i];
337262af557SGuo Chao
33893289d8cSGavin Shan phb->ioda.m64_segmap[pe->pe_number] = pe->pe_number;
339262af557SGuo Chao if (!master_pe) {
340262af557SGuo Chao pe->flags |= PNV_IODA_PE_MASTER;
341262af557SGuo Chao INIT_LIST_HEAD(&pe->slaves);
342262af557SGuo Chao master_pe = pe;
343262af557SGuo Chao } else {
344262af557SGuo Chao pe->flags |= PNV_IODA_PE_SLAVE;
345262af557SGuo Chao pe->master = master_pe;
346262af557SGuo Chao list_add_tail(&pe->list, &master_pe->slaves);
347262af557SGuo Chao }
348262af557SGuo Chao }
349262af557SGuo Chao
350262af557SGuo Chao kfree(pe_alloc);
3511e916772SGavin Shan return master_pe;
352262af557SGuo Chao }
353262af557SGuo Chao
pnv_ioda_parse_m64_window(struct pnv_phb * phb)354262af557SGuo Chao static void __init pnv_ioda_parse_m64_window(struct pnv_phb *phb)
355262af557SGuo Chao {
356262af557SGuo Chao struct pci_controller *hose = phb->hose;
357262af557SGuo Chao struct device_node *dn = hose->dn;
358262af557SGuo Chao struct resource *res;
359a1339fafSBenjamin Herrenschmidt u32 m64_range[2], i;
3600e7736c6SGavin Shan const __be32 *r;
361262af557SGuo Chao u64 pci_addr;
362262af557SGuo Chao
36398e61df5SJoel Stanley if (phb->type != PNV_PHB_IODA2) {
3641665c4a8SGavin Shan pr_info(" Not support M64 window\n");
3651665c4a8SGavin Shan return;
3661665c4a8SGavin Shan }
3671665c4a8SGavin Shan
368e4d54f71SStewart Smith if (!firmware_has_feature(FW_FEATURE_OPAL)) {
369262af557SGuo Chao pr_info(" Firmware too old to support M64 window\n");
370262af557SGuo Chao return;
371262af557SGuo Chao }
372262af557SGuo Chao
373262af557SGuo Chao r = of_get_property(dn, "ibm,opal-m64-window", NULL);
374262af557SGuo Chao if (!r) {
375b7c670d6SRob Herring pr_info(" No <ibm,opal-m64-window> on %pOF\n",
376b7c670d6SRob Herring dn);
377262af557SGuo Chao return;
378262af557SGuo Chao }
379262af557SGuo Chao
380a1339fafSBenjamin Herrenschmidt /*
381a1339fafSBenjamin Herrenschmidt * Find the available M64 BAR range and pickup the last one for
382a1339fafSBenjamin Herrenschmidt * covering the whole 64-bits space. We support only one range.
383a1339fafSBenjamin Herrenschmidt */
384a1339fafSBenjamin Herrenschmidt if (of_property_read_u32_array(dn, "ibm,opal-available-m64-ranges",
385a1339fafSBenjamin Herrenschmidt m64_range, 2)) {
386a1339fafSBenjamin Herrenschmidt /* In absence of the property, assume 0..15 */
387a1339fafSBenjamin Herrenschmidt m64_range[0] = 0;
388a1339fafSBenjamin Herrenschmidt m64_range[1] = 16;
389a1339fafSBenjamin Herrenschmidt }
390a1339fafSBenjamin Herrenschmidt /* We only support 64 bits in our allocator */
391a1339fafSBenjamin Herrenschmidt if (m64_range[1] > 63) {
392a1339fafSBenjamin Herrenschmidt pr_warn("%s: Limiting M64 range to 63 (from %d) on PHB#%x\n",
393a1339fafSBenjamin Herrenschmidt __func__, m64_range[1], phb->hose->global_number);
394a1339fafSBenjamin Herrenschmidt m64_range[1] = 63;
395a1339fafSBenjamin Herrenschmidt }
396a1339fafSBenjamin Herrenschmidt /* Empty range, no m64 */
397a1339fafSBenjamin Herrenschmidt if (m64_range[1] <= m64_range[0]) {
398a1339fafSBenjamin Herrenschmidt pr_warn("%s: M64 empty, disabling M64 usage on PHB#%x\n",
399a1339fafSBenjamin Herrenschmidt __func__, phb->hose->global_number);
400a1339fafSBenjamin Herrenschmidt return;
401a1339fafSBenjamin Herrenschmidt }
402a1339fafSBenjamin Herrenschmidt
403a1339fafSBenjamin Herrenschmidt /* Configure M64 informations */
404262af557SGuo Chao res = &hose->mem_resources[1];
405e80c4e7cSGavin Shan res->name = dn->full_name;
406262af557SGuo Chao res->start = of_translate_address(dn, r + 2);
407262af557SGuo Chao res->end = res->start + of_read_number(r + 4, 2) - 1;
408262af557SGuo Chao res->flags = (IORESOURCE_MEM | IORESOURCE_MEM_64 | IORESOURCE_PREFETCH);
409262af557SGuo Chao pci_addr = of_read_number(r, 2);
410262af557SGuo Chao hose->mem_offset[1] = res->start - pci_addr;
411262af557SGuo Chao
412262af557SGuo Chao phb->ioda.m64_size = resource_size(res);
41392b8f137SGavin Shan phb->ioda.m64_segsize = phb->ioda.m64_size / phb->ioda.total_pe_num;
414262af557SGuo Chao phb->ioda.m64_base = pci_addr;
415262af557SGuo Chao
416a1339fafSBenjamin Herrenschmidt /* This lines up nicely with the display from processing OF ranges */
417a1339fafSBenjamin Herrenschmidt pr_info(" MEM 0x%016llx..0x%016llx -> 0x%016llx (M64 #%d..%d)\n",
418a1339fafSBenjamin Herrenschmidt res->start, res->end, pci_addr, m64_range[0],
419a1339fafSBenjamin Herrenschmidt m64_range[0] + m64_range[1] - 1);
420a1339fafSBenjamin Herrenschmidt
421a1339fafSBenjamin Herrenschmidt /* Mark all M64 used up by default */
422a1339fafSBenjamin Herrenschmidt phb->ioda.m64_bar_alloc = (unsigned long)-1;
423e9863e68SWei Yang
424262af557SGuo Chao /* Use last M64 BAR to cover M64 window */
425a1339fafSBenjamin Herrenschmidt m64_range[1]--;
426a1339fafSBenjamin Herrenschmidt phb->ioda.m64_bar_idx = m64_range[0] + m64_range[1];
427a1339fafSBenjamin Herrenschmidt
428a1339fafSBenjamin Herrenschmidt pr_info(" Using M64 #%d as default window\n", phb->ioda.m64_bar_idx);
429a1339fafSBenjamin Herrenschmidt
430a1339fafSBenjamin Herrenschmidt /* Mark remaining ones free */
431a1339fafSBenjamin Herrenschmidt for (i = m64_range[0]; i < m64_range[1]; i++)
432a1339fafSBenjamin Herrenschmidt clear_bit(i, &phb->ioda.m64_bar_alloc);
433a1339fafSBenjamin Herrenschmidt
434a1339fafSBenjamin Herrenschmidt /*
435a1339fafSBenjamin Herrenschmidt * Setup init functions for M64 based on IODA version, IODA3 uses
436a1339fafSBenjamin Herrenschmidt * the IODA2 code.
437a1339fafSBenjamin Herrenschmidt */
438262af557SGuo Chao phb->init_m64 = pnv_ioda2_init_m64;
439262af557SGuo Chao }
440262af557SGuo Chao
pnv_ioda_freeze_pe(struct pnv_phb * phb,int pe_no)44149dec922SGavin Shan static void pnv_ioda_freeze_pe(struct pnv_phb *phb, int pe_no)
44249dec922SGavin Shan {
44349dec922SGavin Shan struct pnv_ioda_pe *pe = &phb->ioda.pe_array[pe_no];
44449dec922SGavin Shan struct pnv_ioda_pe *slave;
44549dec922SGavin Shan s64 rc;
44649dec922SGavin Shan
44749dec922SGavin Shan /* Fetch master PE */
44849dec922SGavin Shan if (pe->flags & PNV_IODA_PE_SLAVE) {
44949dec922SGavin Shan pe = pe->master;
450ec8e4e9dSGavin Shan if (WARN_ON(!pe || !(pe->flags & PNV_IODA_PE_MASTER)))
451ec8e4e9dSGavin Shan return;
452ec8e4e9dSGavin Shan
45349dec922SGavin Shan pe_no = pe->pe_number;
45449dec922SGavin Shan }
45549dec922SGavin Shan
45649dec922SGavin Shan /* Freeze master PE */
45749dec922SGavin Shan rc = opal_pci_eeh_freeze_set(phb->opal_id,
45849dec922SGavin Shan pe_no,
45949dec922SGavin Shan OPAL_EEH_ACTION_SET_FREEZE_ALL);
46049dec922SGavin Shan if (rc != OPAL_SUCCESS) {
46149dec922SGavin Shan pr_warn("%s: Failure %lld freezing PHB#%x-PE#%x\n",
46249dec922SGavin Shan __func__, rc, phb->hose->global_number, pe_no);
46349dec922SGavin Shan return;
46449dec922SGavin Shan }
46549dec922SGavin Shan
46649dec922SGavin Shan /* Freeze slave PEs */
46749dec922SGavin Shan if (!(pe->flags & PNV_IODA_PE_MASTER))
46849dec922SGavin Shan return;
46949dec922SGavin Shan
47049dec922SGavin Shan list_for_each_entry(slave, &pe->slaves, list) {
47149dec922SGavin Shan rc = opal_pci_eeh_freeze_set(phb->opal_id,
47249dec922SGavin Shan slave->pe_number,
47349dec922SGavin Shan OPAL_EEH_ACTION_SET_FREEZE_ALL);
47449dec922SGavin Shan if (rc != OPAL_SUCCESS)
47549dec922SGavin Shan pr_warn("%s: Failure %lld freezing PHB#%x-PE#%x\n",
47649dec922SGavin Shan __func__, rc, phb->hose->global_number,
47749dec922SGavin Shan slave->pe_number);
47849dec922SGavin Shan }
47949dec922SGavin Shan }
48049dec922SGavin Shan
pnv_ioda_unfreeze_pe(struct pnv_phb * phb,int pe_no,int opt)481e51df2c1SAnton Blanchard static int pnv_ioda_unfreeze_pe(struct pnv_phb *phb, int pe_no, int opt)
48249dec922SGavin Shan {
48349dec922SGavin Shan struct pnv_ioda_pe *pe, *slave;
48449dec922SGavin Shan s64 rc;
48549dec922SGavin Shan
48649dec922SGavin Shan /* Find master PE */
48749dec922SGavin Shan pe = &phb->ioda.pe_array[pe_no];
48849dec922SGavin Shan if (pe->flags & PNV_IODA_PE_SLAVE) {
48949dec922SGavin Shan pe = pe->master;
49049dec922SGavin Shan WARN_ON(!pe || !(pe->flags & PNV_IODA_PE_MASTER));
49149dec922SGavin Shan pe_no = pe->pe_number;
49249dec922SGavin Shan }
49349dec922SGavin Shan
49449dec922SGavin Shan /* Clear frozen state for master PE */
49549dec922SGavin Shan rc = opal_pci_eeh_freeze_clear(phb->opal_id, pe_no, opt);
49649dec922SGavin Shan if (rc != OPAL_SUCCESS) {
49749dec922SGavin Shan pr_warn("%s: Failure %lld clear %d on PHB#%x-PE#%x\n",
49849dec922SGavin Shan __func__, rc, opt, phb->hose->global_number, pe_no);
49949dec922SGavin Shan return -EIO;
50049dec922SGavin Shan }
50149dec922SGavin Shan
50249dec922SGavin Shan if (!(pe->flags & PNV_IODA_PE_MASTER))
50349dec922SGavin Shan return 0;
50449dec922SGavin Shan
50549dec922SGavin Shan /* Clear frozen state for slave PEs */
50649dec922SGavin Shan list_for_each_entry(slave, &pe->slaves, list) {
50749dec922SGavin Shan rc = opal_pci_eeh_freeze_clear(phb->opal_id,
50849dec922SGavin Shan slave->pe_number,
50949dec922SGavin Shan opt);
51049dec922SGavin Shan if (rc != OPAL_SUCCESS) {
51149dec922SGavin Shan pr_warn("%s: Failure %lld clear %d on PHB#%x-PE#%x\n",
51249dec922SGavin Shan __func__, rc, opt, phb->hose->global_number,
51349dec922SGavin Shan slave->pe_number);
51449dec922SGavin Shan return -EIO;
51549dec922SGavin Shan }
51649dec922SGavin Shan }
51749dec922SGavin Shan
51849dec922SGavin Shan return 0;
51949dec922SGavin Shan }
52049dec922SGavin Shan
pnv_ioda_get_pe_state(struct pnv_phb * phb,int pe_no)52149dec922SGavin Shan static int pnv_ioda_get_pe_state(struct pnv_phb *phb, int pe_no)
52249dec922SGavin Shan {
52349dec922SGavin Shan struct pnv_ioda_pe *slave, *pe;
524c2057701SAlexey Kardashevskiy u8 fstate = 0, state;
525c2057701SAlexey Kardashevskiy __be16 pcierr = 0;
52649dec922SGavin Shan s64 rc;
52749dec922SGavin Shan
52849dec922SGavin Shan /* Sanity check on PE number */
52992b8f137SGavin Shan if (pe_no < 0 || pe_no >= phb->ioda.total_pe_num)
53049dec922SGavin Shan return OPAL_EEH_STOPPED_PERM_UNAVAIL;
53149dec922SGavin Shan
53249dec922SGavin Shan /*
53349dec922SGavin Shan * Fetch the master PE and the PE instance might be
53449dec922SGavin Shan * not initialized yet.
53549dec922SGavin Shan */
53649dec922SGavin Shan pe = &phb->ioda.pe_array[pe_no];
53749dec922SGavin Shan if (pe->flags & PNV_IODA_PE_SLAVE) {
53849dec922SGavin Shan pe = pe->master;
53949dec922SGavin Shan WARN_ON(!pe || !(pe->flags & PNV_IODA_PE_MASTER));
54049dec922SGavin Shan pe_no = pe->pe_number;
54149dec922SGavin Shan }
54249dec922SGavin Shan
54349dec922SGavin Shan /* Check the master PE */
54449dec922SGavin Shan rc = opal_pci_eeh_freeze_status(phb->opal_id, pe_no,
54549dec922SGavin Shan &state, &pcierr, NULL);
54649dec922SGavin Shan if (rc != OPAL_SUCCESS) {
54749dec922SGavin Shan pr_warn("%s: Failure %lld getting "
54849dec922SGavin Shan "PHB#%x-PE#%x state\n",
54949dec922SGavin Shan __func__, rc,
55049dec922SGavin Shan phb->hose->global_number, pe_no);
55149dec922SGavin Shan return OPAL_EEH_STOPPED_TEMP_UNAVAIL;
55249dec922SGavin Shan }
55349dec922SGavin Shan
55449dec922SGavin Shan /* Check the slave PE */
55549dec922SGavin Shan if (!(pe->flags & PNV_IODA_PE_MASTER))
55649dec922SGavin Shan return state;
55749dec922SGavin Shan
55849dec922SGavin Shan list_for_each_entry(slave, &pe->slaves, list) {
55949dec922SGavin Shan rc = opal_pci_eeh_freeze_status(phb->opal_id,
56049dec922SGavin Shan slave->pe_number,
56149dec922SGavin Shan &fstate,
56249dec922SGavin Shan &pcierr,
56349dec922SGavin Shan NULL);
56449dec922SGavin Shan if (rc != OPAL_SUCCESS) {
56549dec922SGavin Shan pr_warn("%s: Failure %lld getting "
56649dec922SGavin Shan "PHB#%x-PE#%x state\n",
56749dec922SGavin Shan __func__, rc,
56849dec922SGavin Shan phb->hose->global_number, slave->pe_number);
56949dec922SGavin Shan return OPAL_EEH_STOPPED_TEMP_UNAVAIL;
57049dec922SGavin Shan }
57149dec922SGavin Shan
57249dec922SGavin Shan /*
57349dec922SGavin Shan * Override the result based on the ascending
57449dec922SGavin Shan * priority.
57549dec922SGavin Shan */
57649dec922SGavin Shan if (fstate > state)
57749dec922SGavin Shan state = fstate;
57849dec922SGavin Shan }
57949dec922SGavin Shan
58049dec922SGavin Shan return state;
58149dec922SGavin Shan }
58249dec922SGavin Shan
pnv_pci_bdfn_to_pe(struct pnv_phb * phb,u16 bdfn)583a8d7d5fcSOliver O'Halloran struct pnv_ioda_pe *pnv_pci_bdfn_to_pe(struct pnv_phb *phb, u16 bdfn)
584a8d7d5fcSOliver O'Halloran {
585a8d7d5fcSOliver O'Halloran int pe_number = phb->ioda.pe_rmap[bdfn];
586a8d7d5fcSOliver O'Halloran
587a8d7d5fcSOliver O'Halloran if (pe_number == IODA_INVALID_PE)
588a8d7d5fcSOliver O'Halloran return NULL;
589a8d7d5fcSOliver O'Halloran
590a8d7d5fcSOliver O'Halloran return &phb->ioda.pe_array[pe_number];
591a8d7d5fcSOliver O'Halloran }
592a8d7d5fcSOliver O'Halloran
pnv_ioda_get_pe(struct pci_dev * dev)593f456834aSIan Munsie struct pnv_ioda_pe *pnv_ioda_get_pe(struct pci_dev *dev)
594184cd4a3SBenjamin Herrenschmidt {
5955609ffddSOliver O'Halloran struct pnv_phb *phb = pci_bus_to_pnvhb(dev->bus);
596b72c1f65SBenjamin Herrenschmidt struct pci_dn *pdn = pci_get_pdn(dev);
597184cd4a3SBenjamin Herrenschmidt
598184cd4a3SBenjamin Herrenschmidt if (!pdn)
599184cd4a3SBenjamin Herrenschmidt return NULL;
600184cd4a3SBenjamin Herrenschmidt if (pdn->pe_number == IODA_INVALID_PE)
601184cd4a3SBenjamin Herrenschmidt return NULL;
602184cd4a3SBenjamin Herrenschmidt return &phb->ioda.pe_array[pdn->pe_number];
603184cd4a3SBenjamin Herrenschmidt }
604184cd4a3SBenjamin Herrenschmidt
pnv_ioda_set_one_peltv(struct pnv_phb * phb,struct pnv_ioda_pe * parent,struct pnv_ioda_pe * child,bool is_add)605b131a842SGavin Shan static int pnv_ioda_set_one_peltv(struct pnv_phb *phb,
606b131a842SGavin Shan struct pnv_ioda_pe *parent,
607b131a842SGavin Shan struct pnv_ioda_pe *child,
608b131a842SGavin Shan bool is_add)
609b131a842SGavin Shan {
610b131a842SGavin Shan const char *desc = is_add ? "adding" : "removing";
611b131a842SGavin Shan uint8_t op = is_add ? OPAL_ADD_PE_TO_DOMAIN :
612b131a842SGavin Shan OPAL_REMOVE_PE_FROM_DOMAIN;
613b131a842SGavin Shan struct pnv_ioda_pe *slave;
614b131a842SGavin Shan long rc;
615b131a842SGavin Shan
616b131a842SGavin Shan /* Parent PE affects child PE */
617b131a842SGavin Shan rc = opal_pci_set_peltv(phb->opal_id, parent->pe_number,
618b131a842SGavin Shan child->pe_number, op);
619b131a842SGavin Shan if (rc != OPAL_SUCCESS) {
620b131a842SGavin Shan pe_warn(child, "OPAL error %ld %s to parent PELTV\n",
621b131a842SGavin Shan rc, desc);
622b131a842SGavin Shan return -ENXIO;
623b131a842SGavin Shan }
624b131a842SGavin Shan
625b131a842SGavin Shan if (!(child->flags & PNV_IODA_PE_MASTER))
626b131a842SGavin Shan return 0;
627b131a842SGavin Shan
628b131a842SGavin Shan /* Compound case: parent PE affects slave PEs */
629b131a842SGavin Shan list_for_each_entry(slave, &child->slaves, list) {
630b131a842SGavin Shan rc = opal_pci_set_peltv(phb->opal_id, parent->pe_number,
631b131a842SGavin Shan slave->pe_number, op);
632b131a842SGavin Shan if (rc != OPAL_SUCCESS) {
633b131a842SGavin Shan pe_warn(slave, "OPAL error %ld %s to parent PELTV\n",
634b131a842SGavin Shan rc, desc);
635b131a842SGavin Shan return -ENXIO;
636b131a842SGavin Shan }
637b131a842SGavin Shan }
638b131a842SGavin Shan
639b131a842SGavin Shan return 0;
640b131a842SGavin Shan }
641b131a842SGavin Shan
pnv_ioda_set_peltv(struct pnv_phb * phb,struct pnv_ioda_pe * pe,bool is_add)642b131a842SGavin Shan static int pnv_ioda_set_peltv(struct pnv_phb *phb,
643b131a842SGavin Shan struct pnv_ioda_pe *pe,
644b131a842SGavin Shan bool is_add)
645b131a842SGavin Shan {
646b131a842SGavin Shan struct pnv_ioda_pe *slave;
647781a868fSWei Yang struct pci_dev *pdev = NULL;
648b131a842SGavin Shan int ret;
649b131a842SGavin Shan
650b131a842SGavin Shan /*
651b131a842SGavin Shan * Clear PE frozen state. If it's master PE, we need
652b131a842SGavin Shan * clear slave PE frozen state as well.
653b131a842SGavin Shan */
654b131a842SGavin Shan if (is_add) {
655b131a842SGavin Shan opal_pci_eeh_freeze_clear(phb->opal_id, pe->pe_number,
656b131a842SGavin Shan OPAL_EEH_ACTION_CLEAR_FREEZE_ALL);
657b131a842SGavin Shan if (pe->flags & PNV_IODA_PE_MASTER) {
658b131a842SGavin Shan list_for_each_entry(slave, &pe->slaves, list)
659b131a842SGavin Shan opal_pci_eeh_freeze_clear(phb->opal_id,
660b131a842SGavin Shan slave->pe_number,
661b131a842SGavin Shan OPAL_EEH_ACTION_CLEAR_FREEZE_ALL);
662b131a842SGavin Shan }
663b131a842SGavin Shan }
664b131a842SGavin Shan
665b131a842SGavin Shan /*
666b131a842SGavin Shan * Associate PE in PELT. We need add the PE into the
667b131a842SGavin Shan * corresponding PELT-V as well. Otherwise, the error
668b131a842SGavin Shan * originated from the PE might contribute to other
669b131a842SGavin Shan * PEs.
670b131a842SGavin Shan */
671b131a842SGavin Shan ret = pnv_ioda_set_one_peltv(phb, pe, pe, is_add);
672b131a842SGavin Shan if (ret)
673b131a842SGavin Shan return ret;
674b131a842SGavin Shan
675b131a842SGavin Shan /* For compound PEs, any one affects all of them */
676b131a842SGavin Shan if (pe->flags & PNV_IODA_PE_MASTER) {
677b131a842SGavin Shan list_for_each_entry(slave, &pe->slaves, list) {
678b131a842SGavin Shan ret = pnv_ioda_set_one_peltv(phb, slave, pe, is_add);
679b131a842SGavin Shan if (ret)
680b131a842SGavin Shan return ret;
681b131a842SGavin Shan }
682b131a842SGavin Shan }
683b131a842SGavin Shan
684b131a842SGavin Shan if (pe->flags & (PNV_IODA_PE_BUS_ALL | PNV_IODA_PE_BUS))
685b131a842SGavin Shan pdev = pe->pbus->self;
686781a868fSWei Yang else if (pe->flags & PNV_IODA_PE_DEV)
687b131a842SGavin Shan pdev = pe->pdev->bus->self;
688781a868fSWei Yang #ifdef CONFIG_PCI_IOV
689781a868fSWei Yang else if (pe->flags & PNV_IODA_PE_VF)
690283e2d8aSGavin Shan pdev = pe->parent_dev;
691781a868fSWei Yang #endif /* CONFIG_PCI_IOV */
692b131a842SGavin Shan while (pdev) {
693b131a842SGavin Shan struct pci_dn *pdn = pci_get_pdn(pdev);
694b131a842SGavin Shan struct pnv_ioda_pe *parent;
695b131a842SGavin Shan
696b131a842SGavin Shan if (pdn && pdn->pe_number != IODA_INVALID_PE) {
697b131a842SGavin Shan parent = &phb->ioda.pe_array[pdn->pe_number];
698b131a842SGavin Shan ret = pnv_ioda_set_one_peltv(phb, parent, pe, is_add);
699b131a842SGavin Shan if (ret)
700b131a842SGavin Shan return ret;
701b131a842SGavin Shan }
702b131a842SGavin Shan
703b131a842SGavin Shan pdev = pdev->bus->self;
704b131a842SGavin Shan }
705b131a842SGavin Shan
706b131a842SGavin Shan return 0;
707b131a842SGavin Shan }
708b131a842SGavin Shan
pnv_ioda_unset_peltv(struct pnv_phb * phb,struct pnv_ioda_pe * pe,struct pci_dev * parent)709f724385fSFrederic Barrat static void pnv_ioda_unset_peltv(struct pnv_phb *phb,
710f724385fSFrederic Barrat struct pnv_ioda_pe *pe,
711f724385fSFrederic Barrat struct pci_dev *parent)
712f724385fSFrederic Barrat {
713f724385fSFrederic Barrat int64_t rc;
714f724385fSFrederic Barrat
715f724385fSFrederic Barrat while (parent) {
716f724385fSFrederic Barrat struct pci_dn *pdn = pci_get_pdn(parent);
717f724385fSFrederic Barrat
718f724385fSFrederic Barrat if (pdn && pdn->pe_number != IODA_INVALID_PE) {
719f724385fSFrederic Barrat rc = opal_pci_set_peltv(phb->opal_id, pdn->pe_number,
720f724385fSFrederic Barrat pe->pe_number,
721f724385fSFrederic Barrat OPAL_REMOVE_PE_FROM_DOMAIN);
722f724385fSFrederic Barrat /* XXX What to do in case of error ? */
723f724385fSFrederic Barrat }
724f724385fSFrederic Barrat parent = parent->bus->self;
725f724385fSFrederic Barrat }
726f724385fSFrederic Barrat
727f724385fSFrederic Barrat opal_pci_eeh_freeze_clear(phb->opal_id, pe->pe_number,
728f724385fSFrederic Barrat OPAL_EEH_ACTION_CLEAR_FREEZE_ALL);
729f724385fSFrederic Barrat
730f724385fSFrederic Barrat /* Disassociate PE in PELT */
731f724385fSFrederic Barrat rc = opal_pci_set_peltv(phb->opal_id, pe->pe_number,
732f724385fSFrederic Barrat pe->pe_number, OPAL_REMOVE_PE_FROM_DOMAIN);
733f724385fSFrederic Barrat if (rc)
734f724385fSFrederic Barrat pe_warn(pe, "OPAL error %lld remove self from PELTV\n", rc);
735f724385fSFrederic Barrat }
736f724385fSFrederic Barrat
pnv_ioda_deconfigure_pe(struct pnv_phb * phb,struct pnv_ioda_pe * pe)73737b59ef0SOliver O'Halloran int pnv_ioda_deconfigure_pe(struct pnv_phb *phb, struct pnv_ioda_pe *pe)
738781a868fSWei Yang {
739781a868fSWei Yang struct pci_dev *parent;
740781a868fSWei Yang uint8_t bcomp, dcomp, fcomp;
741781a868fSWei Yang int64_t rc;
742781a868fSWei Yang long rid_end, rid;
743781a868fSWei Yang
744781a868fSWei Yang /* Currently, we just deconfigure VF PE. Bus PE will always there.*/
745781a868fSWei Yang if (pe->pbus) {
746781a868fSWei Yang int count;
747781a868fSWei Yang
748781a868fSWei Yang dcomp = OPAL_IGNORE_RID_DEVICE_NUMBER;
749781a868fSWei Yang fcomp = OPAL_IGNORE_RID_FUNCTION_NUMBER;
750781a868fSWei Yang parent = pe->pbus->self;
751781a868fSWei Yang if (pe->flags & PNV_IODA_PE_BUS_ALL)
752552aa086SJulia Lawall count = resource_size(&pe->pbus->busn_res);
753781a868fSWei Yang else
754781a868fSWei Yang count = 1;
755781a868fSWei Yang
756781a868fSWei Yang switch(count) {
757781a868fSWei Yang case 1: bcomp = OpalPciBusAll; break;
758781a868fSWei Yang case 2: bcomp = OpalPciBus7Bits; break;
759781a868fSWei Yang case 4: bcomp = OpalPciBus6Bits; break;
760781a868fSWei Yang case 8: bcomp = OpalPciBus5Bits; break;
761781a868fSWei Yang case 16: bcomp = OpalPciBus4Bits; break;
762781a868fSWei Yang case 32: bcomp = OpalPciBus3Bits; break;
763781a868fSWei Yang default:
764781a868fSWei Yang dev_err(&pe->pbus->dev, "Number of subordinate buses %d unsupported\n",
765781a868fSWei Yang count);
766781a868fSWei Yang /* Do an exact match only */
767781a868fSWei Yang bcomp = OpalPciBusAll;
768781a868fSWei Yang }
769781a868fSWei Yang rid_end = pe->rid + (count << 8);
770781a868fSWei Yang } else {
77193e01a50SGavin Shan #ifdef CONFIG_PCI_IOV
772781a868fSWei Yang if (pe->flags & PNV_IODA_PE_VF)
773781a868fSWei Yang parent = pe->parent_dev;
774781a868fSWei Yang else
77593e01a50SGavin Shan #endif
776781a868fSWei Yang parent = pe->pdev->bus->self;
777781a868fSWei Yang bcomp = OpalPciBusAll;
778781a868fSWei Yang dcomp = OPAL_COMPARE_RID_DEVICE_NUMBER;
779781a868fSWei Yang fcomp = OPAL_COMPARE_RID_FUNCTION_NUMBER;
780781a868fSWei Yang rid_end = pe->rid + 1;
781781a868fSWei Yang }
782781a868fSWei Yang
783781a868fSWei Yang /* Clear the reverse map */
784781a868fSWei Yang for (rid = pe->rid; rid < rid_end; rid++)
785c127562aSGavin Shan phb->ioda.pe_rmap[rid] = IODA_INVALID_PE;
786781a868fSWei Yang
787f724385fSFrederic Barrat /*
788f724385fSFrederic Barrat * Release from all parents PELT-V. NPUs don't have a PELTV
789f724385fSFrederic Barrat * table
790f724385fSFrederic Barrat */
791562d1e20SChristoph Hellwig if (phb->type != PNV_PHB_NPU_OCAPI)
792f724385fSFrederic Barrat pnv_ioda_unset_peltv(phb, pe, parent);
793781a868fSWei Yang
794781a868fSWei Yang rc = opal_pci_set_pe(phb->opal_id, pe->pe_number, pe->rid,
795781a868fSWei Yang bcomp, dcomp, fcomp, OPAL_UNMAP_PE);
796781a868fSWei Yang if (rc)
7971e496391SJoe Perches pe_err(pe, "OPAL error %lld trying to setup PELT table\n", rc);
798781a868fSWei Yang
799781a868fSWei Yang pe->pbus = NULL;
800781a868fSWei Yang pe->pdev = NULL;
80193e01a50SGavin Shan #ifdef CONFIG_PCI_IOV
802781a868fSWei Yang pe->parent_dev = NULL;
80393e01a50SGavin Shan #endif
804781a868fSWei Yang
805781a868fSWei Yang return 0;
806781a868fSWei Yang }
807781a868fSWei Yang
pnv_ioda_configure_pe(struct pnv_phb * phb,struct pnv_ioda_pe * pe)80837b59ef0SOliver O'Halloran int pnv_ioda_configure_pe(struct pnv_phb *phb, struct pnv_ioda_pe *pe)
809184cd4a3SBenjamin Herrenschmidt {
810184cd4a3SBenjamin Herrenschmidt uint8_t bcomp, dcomp, fcomp;
811184cd4a3SBenjamin Herrenschmidt long rc, rid_end, rid;
812184cd4a3SBenjamin Herrenschmidt
813184cd4a3SBenjamin Herrenschmidt /* Bus validation ? */
814184cd4a3SBenjamin Herrenschmidt if (pe->pbus) {
815184cd4a3SBenjamin Herrenschmidt int count;
816184cd4a3SBenjamin Herrenschmidt
817184cd4a3SBenjamin Herrenschmidt dcomp = OPAL_IGNORE_RID_DEVICE_NUMBER;
818184cd4a3SBenjamin Herrenschmidt fcomp = OPAL_IGNORE_RID_FUNCTION_NUMBER;
819fb446ad0SGavin Shan if (pe->flags & PNV_IODA_PE_BUS_ALL)
820552aa086SJulia Lawall count = resource_size(&pe->pbus->busn_res);
821fb446ad0SGavin Shan else
822fb446ad0SGavin Shan count = 1;
823fb446ad0SGavin Shan
824184cd4a3SBenjamin Herrenschmidt switch(count) {
825184cd4a3SBenjamin Herrenschmidt case 1: bcomp = OpalPciBusAll; break;
826184cd4a3SBenjamin Herrenschmidt case 2: bcomp = OpalPciBus7Bits; break;
827184cd4a3SBenjamin Herrenschmidt case 4: bcomp = OpalPciBus6Bits; break;
828184cd4a3SBenjamin Herrenschmidt case 8: bcomp = OpalPciBus5Bits; break;
829184cd4a3SBenjamin Herrenschmidt case 16: bcomp = OpalPciBus4Bits; break;
830184cd4a3SBenjamin Herrenschmidt case 32: bcomp = OpalPciBus3Bits; break;
831184cd4a3SBenjamin Herrenschmidt default:
832781a868fSWei Yang dev_err(&pe->pbus->dev, "Number of subordinate buses %d unsupported\n",
833781a868fSWei Yang count);
834184cd4a3SBenjamin Herrenschmidt /* Do an exact match only */
835184cd4a3SBenjamin Herrenschmidt bcomp = OpalPciBusAll;
836184cd4a3SBenjamin Herrenschmidt }
837184cd4a3SBenjamin Herrenschmidt rid_end = pe->rid + (count << 8);
838184cd4a3SBenjamin Herrenschmidt } else {
839184cd4a3SBenjamin Herrenschmidt bcomp = OpalPciBusAll;
840184cd4a3SBenjamin Herrenschmidt dcomp = OPAL_COMPARE_RID_DEVICE_NUMBER;
841184cd4a3SBenjamin Herrenschmidt fcomp = OPAL_COMPARE_RID_FUNCTION_NUMBER;
842184cd4a3SBenjamin Herrenschmidt rid_end = pe->rid + 1;
843184cd4a3SBenjamin Herrenschmidt }
844184cd4a3SBenjamin Herrenschmidt
845631ad691SGavin Shan /*
846631ad691SGavin Shan * Associate PE in PELT. We need add the PE into the
847631ad691SGavin Shan * corresponding PELT-V as well. Otherwise, the error
848631ad691SGavin Shan * originated from the PE might contribute to other
849631ad691SGavin Shan * PEs.
850631ad691SGavin Shan */
851184cd4a3SBenjamin Herrenschmidt rc = opal_pci_set_pe(phb->opal_id, pe->pe_number, pe->rid,
852184cd4a3SBenjamin Herrenschmidt bcomp, dcomp, fcomp, OPAL_MAP_PE);
853184cd4a3SBenjamin Herrenschmidt if (rc) {
854184cd4a3SBenjamin Herrenschmidt pe_err(pe, "OPAL error %ld trying to setup PELT table\n", rc);
855184cd4a3SBenjamin Herrenschmidt return -ENXIO;
856184cd4a3SBenjamin Herrenschmidt }
857631ad691SGavin Shan
8585d2aa710SAlistair Popple /*
8595d2aa710SAlistair Popple * Configure PELTV. NPUs don't have a PELTV table so skip
8605d2aa710SAlistair Popple * configuration on them.
8615d2aa710SAlistair Popple */
862562d1e20SChristoph Hellwig if (phb->type != PNV_PHB_NPU_OCAPI)
863b131a842SGavin Shan pnv_ioda_set_peltv(phb, pe, true);
864184cd4a3SBenjamin Herrenschmidt
865184cd4a3SBenjamin Herrenschmidt /* Setup reverse map */
866184cd4a3SBenjamin Herrenschmidt for (rid = pe->rid; rid < rid_end; rid++)
867184cd4a3SBenjamin Herrenschmidt phb->ioda.pe_rmap[rid] = pe->pe_number;
868184cd4a3SBenjamin Herrenschmidt
8694773f76bSGavin Shan pe->mve_number = 0;
8704773f76bSGavin Shan
871184cd4a3SBenjamin Herrenschmidt return 0;
872184cd4a3SBenjamin Herrenschmidt }
873184cd4a3SBenjamin Herrenschmidt
pnv_ioda_setup_dev_PE(struct pci_dev * dev)874cad5cef6SGreg Kroah-Hartman static struct pnv_ioda_pe *pnv_ioda_setup_dev_PE(struct pci_dev *dev)
875184cd4a3SBenjamin Herrenschmidt {
8765609ffddSOliver O'Halloran struct pnv_phb *phb = pci_bus_to_pnvhb(dev->bus);
877b72c1f65SBenjamin Herrenschmidt struct pci_dn *pdn = pci_get_pdn(dev);
878184cd4a3SBenjamin Herrenschmidt struct pnv_ioda_pe *pe;
879184cd4a3SBenjamin Herrenschmidt
880184cd4a3SBenjamin Herrenschmidt if (!pdn) {
881184cd4a3SBenjamin Herrenschmidt pr_err("%s: Device tree node not associated properly\n",
882184cd4a3SBenjamin Herrenschmidt pci_name(dev));
883184cd4a3SBenjamin Herrenschmidt return NULL;
884184cd4a3SBenjamin Herrenschmidt }
885184cd4a3SBenjamin Herrenschmidt if (pdn->pe_number != IODA_INVALID_PE)
886184cd4a3SBenjamin Herrenschmidt return NULL;
887184cd4a3SBenjamin Herrenschmidt
888a4bc676eSOliver O'Halloran pe = pnv_ioda_alloc_pe(phb, 1);
8891e916772SGavin Shan if (!pe) {
890f2c2cbccSJoe Perches pr_warn("%s: Not enough PE# available, disabling device\n",
891184cd4a3SBenjamin Herrenschmidt pci_name(dev));
892184cd4a3SBenjamin Herrenschmidt return NULL;
893184cd4a3SBenjamin Herrenschmidt }
894184cd4a3SBenjamin Herrenschmidt
89505dd7da7SFrederic Barrat /* NOTE: We don't get a reference for the pointer in the PE
89605dd7da7SFrederic Barrat * data structure, both the device and PE structures should be
897562d1e20SChristoph Hellwig * destroyed at the same time.
898184cd4a3SBenjamin Herrenschmidt *
899184cd4a3SBenjamin Herrenschmidt * At some point we want to remove the PDN completely anyways
900184cd4a3SBenjamin Herrenschmidt */
9011e916772SGavin Shan pdn->pe_number = pe->pe_number;
9025d2aa710SAlistair Popple pe->flags = PNV_IODA_PE_DEV;
903184cd4a3SBenjamin Herrenschmidt pe->pdev = dev;
904184cd4a3SBenjamin Herrenschmidt pe->pbus = NULL;
905184cd4a3SBenjamin Herrenschmidt pe->mve_number = -1;
906184cd4a3SBenjamin Herrenschmidt pe->rid = dev->bus->number << 8 | pdn->devfn;
907f724385fSFrederic Barrat pe->device_count++;
908184cd4a3SBenjamin Herrenschmidt
909184cd4a3SBenjamin Herrenschmidt pe_info(pe, "Associated device to PE\n");
910184cd4a3SBenjamin Herrenschmidt
911184cd4a3SBenjamin Herrenschmidt if (pnv_ioda_configure_pe(phb, pe)) {
912184cd4a3SBenjamin Herrenschmidt /* XXX What do we do here ? */
9131e916772SGavin Shan pnv_ioda_free_pe(pe);
914184cd4a3SBenjamin Herrenschmidt pdn->pe_number = IODA_INVALID_PE;
915184cd4a3SBenjamin Herrenschmidt pe->pdev = NULL;
916184cd4a3SBenjamin Herrenschmidt return NULL;
917184cd4a3SBenjamin Herrenschmidt }
918184cd4a3SBenjamin Herrenschmidt
9191d4e89cfSAlexey Kardashevskiy /* Put PE to the list */
92080f1ff83SFrederic Barrat mutex_lock(&phb->ioda.pe_list_mutex);
9211d4e89cfSAlexey Kardashevskiy list_add_tail(&pe->list, &phb->ioda.pe_list);
92280f1ff83SFrederic Barrat mutex_unlock(&phb->ioda.pe_list_mutex);
923184cd4a3SBenjamin Herrenschmidt return pe;
924184cd4a3SBenjamin Herrenschmidt }
925184cd4a3SBenjamin Herrenschmidt
926fb446ad0SGavin Shan /*
927fb446ad0SGavin Shan * There're 2 types of PCI bus sensitive PEs: One that is compromised of
928fb446ad0SGavin Shan * single PCI bus. Another one that contains the primary PCI bus and its
929fb446ad0SGavin Shan * subordinate PCI devices and buses. The second type of PE is normally
930fb446ad0SGavin Shan * orgiriated by PCIe-to-PCI bridge or PLX switch downstream ports.
931fb446ad0SGavin Shan */
pnv_ioda_setup_bus_PE(struct pci_bus * bus,bool all)9321e916772SGavin Shan static struct pnv_ioda_pe *pnv_ioda_setup_bus_PE(struct pci_bus *bus, bool all)
933184cd4a3SBenjamin Herrenschmidt {
9345609ffddSOliver O'Halloran struct pnv_phb *phb = pci_bus_to_pnvhb(bus);
9351e916772SGavin Shan struct pnv_ioda_pe *pe = NULL;
936ccd1c191SGavin Shan unsigned int pe_num;
937ccd1c191SGavin Shan
938ccd1c191SGavin Shan /*
939ccd1c191SGavin Shan * In partial hotplug case, the PE instance might be still alive.
940ccd1c191SGavin Shan * We should reuse it instead of allocating a new one.
941ccd1c191SGavin Shan */
942ccd1c191SGavin Shan pe_num = phb->ioda.pe_rmap[bus->number << 8];
9436ae8aedfSOliver O'Halloran if (WARN_ON(pe_num != IODA_INVALID_PE)) {
944ccd1c191SGavin Shan pe = &phb->ioda.pe_array[pe_num];
945ccd1c191SGavin Shan return NULL;
946ccd1c191SGavin Shan }
947184cd4a3SBenjamin Herrenschmidt
94863803c39SGavin Shan /* PE number for root bus should have been reserved */
949718d249aSOliver O'Halloran if (pci_is_root_bus(bus))
95063803c39SGavin Shan pe = &phb->ioda.pe_array[phb->ioda.root_pe_idx];
95163803c39SGavin Shan
952262af557SGuo Chao /* Check if PE is determined by M64 */
953a25de7afSAlexey Kardashevskiy if (!pe)
954a25de7afSAlexey Kardashevskiy pe = pnv_ioda_pick_m64_pe(bus, all);
955262af557SGuo Chao
956262af557SGuo Chao /* The PE number isn't pinned by M64 */
9571e916772SGavin Shan if (!pe)
958a4bc676eSOliver O'Halloran pe = pnv_ioda_alloc_pe(phb, 1);
959262af557SGuo Chao
9601e916772SGavin Shan if (!pe) {
961f2c2cbccSJoe Perches pr_warn("%s: Not enough PE# available for PCI bus %04x:%02x\n",
962fb446ad0SGavin Shan __func__, pci_domain_nr(bus), bus->number);
9631e916772SGavin Shan return NULL;
964184cd4a3SBenjamin Herrenschmidt }
965184cd4a3SBenjamin Herrenschmidt
966262af557SGuo Chao pe->flags |= (all ? PNV_IODA_PE_BUS_ALL : PNV_IODA_PE_BUS);
967184cd4a3SBenjamin Herrenschmidt pe->pbus = bus;
968184cd4a3SBenjamin Herrenschmidt pe->pdev = NULL;
969184cd4a3SBenjamin Herrenschmidt pe->mve_number = -1;
970b918c62eSYinghai Lu pe->rid = bus->busn_res.start << 8;
971184cd4a3SBenjamin Herrenschmidt
972fb446ad0SGavin Shan if (all)
9731e496391SJoe Perches pe_info(pe, "Secondary bus %pad..%pad associated with PE#%x\n",
9741e496391SJoe Perches &bus->busn_res.start, &bus->busn_res.end,
9751e496391SJoe Perches pe->pe_number);
976fb446ad0SGavin Shan else
9771e496391SJoe Perches pe_info(pe, "Secondary bus %pad associated with PE#%x\n",
9781e496391SJoe Perches &bus->busn_res.start, pe->pe_number);
979184cd4a3SBenjamin Herrenschmidt
980184cd4a3SBenjamin Herrenschmidt if (pnv_ioda_configure_pe(phb, pe)) {
981184cd4a3SBenjamin Herrenschmidt /* XXX What do we do here ? */
9821e916772SGavin Shan pnv_ioda_free_pe(pe);
983184cd4a3SBenjamin Herrenschmidt pe->pbus = NULL;
9841e916772SGavin Shan return NULL;
985184cd4a3SBenjamin Herrenschmidt }
986184cd4a3SBenjamin Herrenschmidt
9877ebdf956SGavin Shan /* Put PE to the list */
9887ebdf956SGavin Shan list_add_tail(&pe->list, &phb->ioda.pe_list);
9891e916772SGavin Shan
9901e916772SGavin Shan return pe;
991184cd4a3SBenjamin Herrenschmidt }
992184cd4a3SBenjamin Herrenschmidt
pnv_pci_ioda_dma_dev_setup(struct pci_dev * pdev)9930a25d9c4SOliver O'Halloran static void pnv_pci_ioda_dma_dev_setup(struct pci_dev *pdev)
994184cd4a3SBenjamin Herrenschmidt {
9955609ffddSOliver O'Halloran struct pnv_phb *phb = pci_bus_to_pnvhb(pdev->bus);
996b72c1f65SBenjamin Herrenschmidt struct pci_dn *pdn = pci_get_pdn(pdev);
997959c9bddSGavin Shan struct pnv_ioda_pe *pe;
998184cd4a3SBenjamin Herrenschmidt
999dc3d8f85SOliver O'Halloran /* Check if the BDFN for this device is associated with a PE yet */
1000*fe8aa8e3SXiongfeng Wang pe = pnv_pci_bdfn_to_pe(phb, pci_dev_id(pdev));
1001dc3d8f85SOliver O'Halloran if (!pe) {
1002dc3d8f85SOliver O'Halloran /* VF PEs should be pre-configured in pnv_pci_sriov_enable() */
1003dc3d8f85SOliver O'Halloran if (WARN_ON(pdev->is_virtfn))
1004959c9bddSGavin Shan return;
1005184cd4a3SBenjamin Herrenschmidt
1006dc3d8f85SOliver O'Halloran pnv_pci_configure_bus(pdev->bus);
1007*fe8aa8e3SXiongfeng Wang pe = pnv_pci_bdfn_to_pe(phb, pci_dev_id(pdev));
1008dc3d8f85SOliver O'Halloran pci_info(pdev, "Configured PE#%x\n", pe ? pe->pe_number : 0xfffff);
1009dc3d8f85SOliver O'Halloran
1010dc3d8f85SOliver O'Halloran
1011dc3d8f85SOliver O'Halloran /*
1012dc3d8f85SOliver O'Halloran * If we can't setup the IODA PE something has gone horribly
1013dc3d8f85SOliver O'Halloran * wrong and we can't enable DMA for the device.
1014dc3d8f85SOliver O'Halloran */
1015dc3d8f85SOliver O'Halloran if (WARN_ON(!pe))
1016dc3d8f85SOliver O'Halloran return;
1017dc3d8f85SOliver O'Halloran } else {
1018dc3d8f85SOliver O'Halloran pci_info(pdev, "Added to existing PE#%x\n", pe->pe_number);
1019dc3d8f85SOliver O'Halloran }
1020dc3d8f85SOliver O'Halloran
102101e12629SOliver O'Halloran /*
102201e12629SOliver O'Halloran * We assume that bridges *probably* don't need to do any DMA so we can
102301e12629SOliver O'Halloran * skip allocating a TCE table, etc unless we get a non-bridge device.
102401e12629SOliver O'Halloran */
102501e12629SOliver O'Halloran if (!pe->dma_setup_done && !pci_is_bridge(pdev)) {
102601e12629SOliver O'Halloran switch (phb->type) {
102701e12629SOliver O'Halloran case PNV_PHB_IODA2:
102801e12629SOliver O'Halloran pnv_pci_ioda2_setup_dma_pe(phb, pe);
102901e12629SOliver O'Halloran break;
103001e12629SOliver O'Halloran default:
103101e12629SOliver O'Halloran pr_warn("%s: No DMA for PHB#%x (type %d)\n",
103201e12629SOliver O'Halloran __func__, phb->hose->global_number, phb->type);
103301e12629SOliver O'Halloran }
103401e12629SOliver O'Halloran }
103501e12629SOliver O'Halloran
1036dc3d8f85SOliver O'Halloran if (pdn)
1037dc3d8f85SOliver O'Halloran pdn->pe_number = pe->pe_number;
1038dc3d8f85SOliver O'Halloran pe->device_count++;
1039dc3d8f85SOliver O'Halloran
1040cd15b048SBenjamin Herrenschmidt WARN_ON(get_dma_ops(&pdev->dev) != &dma_iommu_ops);
10410617fc0cSChristoph Hellwig pdev->dev.archdata.dma_offset = pe->tce_bypass_base;
1042b348aa65SAlexey Kardashevskiy set_iommu_table_base(&pdev->dev, pe->table_group.tables[0]);
104384d8cc07SOliver O'Halloran
104484d8cc07SOliver O'Halloran /* PEs with a DMA weight of zero won't have a group */
104584d8cc07SOliver O'Halloran if (pe->table_group.group)
104684d8cc07SOliver O'Halloran iommu_add_device(&pe->table_group, &pdev->dev);
1047184cd4a3SBenjamin Herrenschmidt }
1048184cd4a3SBenjamin Herrenschmidt
10498e3f1b1dSRussell Currey /*
10508e3f1b1dSRussell Currey * Reconfigure TVE#0 to be usable as 64-bit DMA space.
10518e3f1b1dSRussell Currey *
10528e3f1b1dSRussell Currey * The first 4GB of virtual memory for a PE is reserved for 32-bit accesses.
10538e3f1b1dSRussell Currey * Devices can only access more than that if bit 59 of the PCI address is set
10548e3f1b1dSRussell Currey * by hardware, which indicates TVE#1 should be used instead of TVE#0.
10558e3f1b1dSRussell Currey * Many PCI devices are not capable of addressing that many bits, and as a
10568e3f1b1dSRussell Currey * result are limited to the 4GB of virtual memory made available to 32-bit
10578e3f1b1dSRussell Currey * devices in TVE#0.
10588e3f1b1dSRussell Currey *
10598e3f1b1dSRussell Currey * In order to work around this, reconfigure TVE#0 to be suitable for 64-bit
10608e3f1b1dSRussell Currey * devices by configuring the virtual memory past the first 4GB inaccessible
10618e3f1b1dSRussell Currey * by 64-bit DMAs. This should only be used by devices that want more than
10628e3f1b1dSRussell Currey * 4GB, and only on PEs that have no 32-bit devices.
10638e3f1b1dSRussell Currey *
10648e3f1b1dSRussell Currey * Currently this will only work on PHB3 (POWER8).
10658e3f1b1dSRussell Currey */
pnv_pci_ioda_dma_64bit_bypass(struct pnv_ioda_pe * pe)10668e3f1b1dSRussell Currey static int pnv_pci_ioda_dma_64bit_bypass(struct pnv_ioda_pe *pe)
10678e3f1b1dSRussell Currey {
10688e3f1b1dSRussell Currey u64 window_size, table_size, tce_count, addr;
10698e3f1b1dSRussell Currey struct page *table_pages;
10708e3f1b1dSRussell Currey u64 tce_order = 28; /* 256MB TCEs */
10718e3f1b1dSRussell Currey __be64 *tces;
10728e3f1b1dSRussell Currey s64 rc;
10738e3f1b1dSRussell Currey
10748e3f1b1dSRussell Currey /*
10758e3f1b1dSRussell Currey * Window size needs to be a power of two, but needs to account for
10768e3f1b1dSRussell Currey * shifting memory by the 4GB offset required to skip 32bit space.
10778e3f1b1dSRussell Currey */
10788e3f1b1dSRussell Currey window_size = roundup_pow_of_two(memory_hotplug_max() + (1ULL << 32));
10798e3f1b1dSRussell Currey tce_count = window_size >> tce_order;
10808e3f1b1dSRussell Currey table_size = tce_count << 3;
10818e3f1b1dSRussell Currey
10828e3f1b1dSRussell Currey if (table_size < PAGE_SIZE)
10838e3f1b1dSRussell Currey table_size = PAGE_SIZE;
10848e3f1b1dSRussell Currey
10858e3f1b1dSRussell Currey table_pages = alloc_pages_node(pe->phb->hose->node, GFP_KERNEL,
10868e3f1b1dSRussell Currey get_order(table_size));
10878e3f1b1dSRussell Currey if (!table_pages)
10888e3f1b1dSRussell Currey goto err;
10898e3f1b1dSRussell Currey
10908e3f1b1dSRussell Currey tces = page_address(table_pages);
10918e3f1b1dSRussell Currey if (!tces)
10928e3f1b1dSRussell Currey goto err;
10938e3f1b1dSRussell Currey
10948e3f1b1dSRussell Currey memset(tces, 0, table_size);
10958e3f1b1dSRussell Currey
10968e3f1b1dSRussell Currey for (addr = 0; addr < memory_hotplug_max(); addr += (1 << tce_order)) {
10978e3f1b1dSRussell Currey tces[(addr + (1ULL << 32)) >> tce_order] =
10988e3f1b1dSRussell Currey cpu_to_be64(addr | TCE_PCI_READ | TCE_PCI_WRITE);
10998e3f1b1dSRussell Currey }
11008e3f1b1dSRussell Currey
11018e3f1b1dSRussell Currey rc = opal_pci_map_pe_dma_window(pe->phb->opal_id,
11028e3f1b1dSRussell Currey pe->pe_number,
11038e3f1b1dSRussell Currey /* reconfigure window 0 */
11048e3f1b1dSRussell Currey (pe->pe_number << 1) + 0,
11058e3f1b1dSRussell Currey 1,
11068e3f1b1dSRussell Currey __pa(tces),
11078e3f1b1dSRussell Currey table_size,
11088e3f1b1dSRussell Currey 1 << tce_order);
11098e3f1b1dSRussell Currey if (rc == OPAL_SUCCESS) {
11108e3f1b1dSRussell Currey pe_info(pe, "Using 64-bit DMA iommu bypass (through TVE#0)\n");
11118e3f1b1dSRussell Currey return 0;
11128e3f1b1dSRussell Currey }
11138e3f1b1dSRussell Currey err:
11148e3f1b1dSRussell Currey pe_err(pe, "Error configuring 64-bit DMA bypass\n");
11158e3f1b1dSRussell Currey return -EIO;
11168e3f1b1dSRussell Currey }
11178e3f1b1dSRussell Currey
pnv_pci_ioda_iommu_bypass_supported(struct pci_dev * pdev,u64 dma_mask)11182d6ad41bSChristoph Hellwig static bool pnv_pci_ioda_iommu_bypass_supported(struct pci_dev *pdev,
11192d6ad41bSChristoph Hellwig u64 dma_mask)
1120cd15b048SBenjamin Herrenschmidt {
11215609ffddSOliver O'Halloran struct pnv_phb *phb = pci_bus_to_pnvhb(pdev->bus);
1122cd15b048SBenjamin Herrenschmidt struct pci_dn *pdn = pci_get_pdn(pdev);
1123cd15b048SBenjamin Herrenschmidt struct pnv_ioda_pe *pe;
1124cd15b048SBenjamin Herrenschmidt
1125cd15b048SBenjamin Herrenschmidt if (WARN_ON(!pdn || pdn->pe_number == IODA_INVALID_PE))
1126b511cdd1SAlexey Kardashevskiy return false;
1127cd15b048SBenjamin Herrenschmidt
1128cd15b048SBenjamin Herrenschmidt pe = &phb->ioda.pe_array[pdn->pe_number];
1129cd15b048SBenjamin Herrenschmidt if (pe->tce_bypass_enabled) {
11302d6ad41bSChristoph Hellwig u64 top = pe->tce_bypass_base + memblock_end_of_DRAM() - 1;
11312d6ad41bSChristoph Hellwig if (dma_mask >= top)
11322d6ad41bSChristoph Hellwig return true;
1133cd15b048SBenjamin Herrenschmidt }
1134cd15b048SBenjamin Herrenschmidt
11358e3f1b1dSRussell Currey /*
11368e3f1b1dSRussell Currey * If the device can't set the TCE bypass bit but still wants
11378e3f1b1dSRussell Currey * to access 4GB or more, on PHB3 we can reconfigure TVE#0 to
11388e3f1b1dSRussell Currey * bypass the 32-bit region and be usable for 64-bit DMAs.
11398e3f1b1dSRussell Currey * The device needs to be able to address all of this space.
11408e3f1b1dSRussell Currey */
11418e3f1b1dSRussell Currey if (dma_mask >> 32 &&
11428e3f1b1dSRussell Currey dma_mask > (memory_hotplug_max() + (1ULL << 32)) &&
1143661fcb45SChristoph Hellwig /* pe->pdev should be set if it's a single device, pe->pbus if not */
1144661fcb45SChristoph Hellwig (pe->device_count == 1 || !pe->pbus) &&
11458e3f1b1dSRussell Currey phb->model == PNV_PHB_MODEL_PHB3) {
11468e3f1b1dSRussell Currey /* Configure the bypass mode */
11472d6ad41bSChristoph Hellwig s64 rc = pnv_pci_ioda_dma_64bit_bypass(pe);
11488e3f1b1dSRussell Currey if (rc)
1149b511cdd1SAlexey Kardashevskiy return false;
11508e3f1b1dSRussell Currey /* 4GB offset bypasses 32-bit space */
11510617fc0cSChristoph Hellwig pdev->dev.archdata.dma_offset = (1ULL << 32);
11522d6ad41bSChristoph Hellwig return true;
1153cd15b048SBenjamin Herrenschmidt }
1154cd15b048SBenjamin Herrenschmidt
11552d6ad41bSChristoph Hellwig return false;
1156fe7e85c6SGavin Shan }
1157fe7e85c6SGavin Shan
pnv_ioda_get_inval_reg(struct pnv_phb * phb)1158cad32d9dSAlexey Kardashevskiy static inline __be64 __iomem *pnv_ioda_get_inval_reg(struct pnv_phb *phb)
1159fd141d1aSBenjamin Herrenschmidt {
1160cad32d9dSAlexey Kardashevskiy return phb->regs + 0x210;
1161fd141d1aSBenjamin Herrenschmidt }
1162fd141d1aSBenjamin Herrenschmidt
116305c6cfb9SAlexey Kardashevskiy #ifdef CONFIG_IOMMU_API
116435872480SAlexey Kardashevskiy /* Common for IODA1 and IODA2 */
pnv_ioda_tce_xchg_no_kill(struct iommu_table * tbl,long index,unsigned long * hpa,enum dma_data_direction * direction)116535872480SAlexey Kardashevskiy static int pnv_ioda_tce_xchg_no_kill(struct iommu_table *tbl, long index,
1166cad32d9dSAlexey Kardashevskiy unsigned long *hpa, enum dma_data_direction *direction)
116705c6cfb9SAlexey Kardashevskiy {
1168cad32d9dSAlexey Kardashevskiy return pnv_tce_xchg(tbl, index, hpa, direction);
1169a540aa56SAlexey Kardashevskiy }
117005c6cfb9SAlexey Kardashevskiy #endif
117105c6cfb9SAlexey Kardashevskiy
1172a34ab7c3SBenjamin Herrenschmidt #define PHB3_TCE_KILL_INVAL_ALL PPC_BIT(0)
1173a34ab7c3SBenjamin Herrenschmidt #define PHB3_TCE_KILL_INVAL_PE PPC_BIT(1)
1174a34ab7c3SBenjamin Herrenschmidt #define PHB3_TCE_KILL_INVAL_ONE PPC_BIT(2)
1175bef9253fSAlexey Kardashevskiy
pnv_pci_phb3_tce_invalidate_pe(struct pnv_ioda_pe * pe)1176a34ab7c3SBenjamin Herrenschmidt static inline void pnv_pci_phb3_tce_invalidate_pe(struct pnv_ioda_pe *pe)
11775780fb04SAlexey Kardashevskiy {
11785780fb04SAlexey Kardashevskiy /* 01xb - invalidate TCEs that match the specified PE# */
1179cad32d9dSAlexey Kardashevskiy __be64 __iomem *invalidate = pnv_ioda_get_inval_reg(pe->phb);
1180a34ab7c3SBenjamin Herrenschmidt unsigned long val = PHB3_TCE_KILL_INVAL_PE | (pe->pe_number & 0xFF);
11815780fb04SAlexey Kardashevskiy
11825780fb04SAlexey Kardashevskiy mb(); /* Ensure above stores are visible */
1183001ff2eeSMichael Ellerman __raw_writeq_be(val, invalidate);
11845780fb04SAlexey Kardashevskiy }
11855780fb04SAlexey Kardashevskiy
pnv_pci_phb3_tce_invalidate(struct pnv_ioda_pe * pe,unsigned shift,unsigned long index,unsigned long npages)1186cad32d9dSAlexey Kardashevskiy static void pnv_pci_phb3_tce_invalidate(struct pnv_ioda_pe *pe,
1187fd141d1aSBenjamin Herrenschmidt unsigned shift, unsigned long index,
1188fd141d1aSBenjamin Herrenschmidt unsigned long npages)
11894cce9550SGavin Shan {
1190cad32d9dSAlexey Kardashevskiy __be64 __iomem *invalidate = pnv_ioda_get_inval_reg(pe->phb);
11914cce9550SGavin Shan unsigned long start, end, inc;
11924cce9550SGavin Shan
11934cce9550SGavin Shan /* We'll invalidate DMA address in PE scope */
1194a34ab7c3SBenjamin Herrenschmidt start = PHB3_TCE_KILL_INVAL_ONE;
1195fd141d1aSBenjamin Herrenschmidt start |= (pe->pe_number & 0xFF);
11964cce9550SGavin Shan end = start;
11974cce9550SGavin Shan
11984cce9550SGavin Shan /* Figure out the start, end and step */
1199decbda25SAlexey Kardashevskiy start |= (index << shift);
1200decbda25SAlexey Kardashevskiy end |= ((index + npages - 1) << shift);
1201b0376c9bSAlexey Kardashevskiy inc = (0x1ull << shift);
12024cce9550SGavin Shan mb();
12034cce9550SGavin Shan
12044cce9550SGavin Shan while (start <= end) {
1205001ff2eeSMichael Ellerman __raw_writeq_be(start, invalidate);
12064cce9550SGavin Shan start += inc;
12074cce9550SGavin Shan }
12084cce9550SGavin Shan }
12094cce9550SGavin Shan
pnv_pci_ioda2_tce_invalidate_pe(struct pnv_ioda_pe * pe)1210f0228c41SBenjamin Herrenschmidt static inline void pnv_pci_ioda2_tce_invalidate_pe(struct pnv_ioda_pe *pe)
1211f0228c41SBenjamin Herrenschmidt {
1212f0228c41SBenjamin Herrenschmidt struct pnv_phb *phb = pe->phb;
1213f0228c41SBenjamin Herrenschmidt
1214f0228c41SBenjamin Herrenschmidt if (phb->model == PNV_PHB_MODEL_PHB3 && phb->regs)
1215f0228c41SBenjamin Herrenschmidt pnv_pci_phb3_tce_invalidate_pe(pe);
1216f0228c41SBenjamin Herrenschmidt else
1217f0228c41SBenjamin Herrenschmidt opal_pci_tce_kill(phb->opal_id, OPAL_PCI_TCE_KILL_PE,
1218f0228c41SBenjamin Herrenschmidt pe->pe_number, 0, 0, 0);
1219f0228c41SBenjamin Herrenschmidt }
1220f0228c41SBenjamin Herrenschmidt
pnv_pci_ioda2_tce_invalidate(struct iommu_table * tbl,unsigned long index,unsigned long npages)1221e57080f1SAlexey Kardashevskiy static void pnv_pci_ioda2_tce_invalidate(struct iommu_table *tbl,
1222cad32d9dSAlexey Kardashevskiy unsigned long index, unsigned long npages)
1223e57080f1SAlexey Kardashevskiy {
1224e57080f1SAlexey Kardashevskiy struct iommu_table_group_link *tgl;
1225e57080f1SAlexey Kardashevskiy
1226a540aa56SAlexey Kardashevskiy list_for_each_entry_lockless(tgl, &tbl->it_group_list, next) {
1227e57080f1SAlexey Kardashevskiy struct pnv_ioda_pe *pe = container_of(tgl->table_group,
1228e57080f1SAlexey Kardashevskiy struct pnv_ioda_pe, table_group);
1229f0228c41SBenjamin Herrenschmidt struct pnv_phb *phb = pe->phb;
1230f0228c41SBenjamin Herrenschmidt unsigned int shift = tbl->it_page_shift;
1231f0228c41SBenjamin Herrenschmidt
1232f0228c41SBenjamin Herrenschmidt if (phb->model == PNV_PHB_MODEL_PHB3 && phb->regs)
1233cad32d9dSAlexey Kardashevskiy pnv_pci_phb3_tce_invalidate(pe, shift,
123485674868SAlexey Kardashevskiy index, npages);
1235f0228c41SBenjamin Herrenschmidt else
1236f0228c41SBenjamin Herrenschmidt opal_pci_tce_kill(phb->opal_id,
1237f0228c41SBenjamin Herrenschmidt OPAL_PCI_TCE_KILL_PAGES,
1238f0228c41SBenjamin Herrenschmidt pe->pe_number, 1u << shift,
1239f0228c41SBenjamin Herrenschmidt index << shift, npages);
1240e57080f1SAlexey Kardashevskiy }
1241e57080f1SAlexey Kardashevskiy }
1242e57080f1SAlexey Kardashevskiy
pnv_ioda2_tce_build(struct iommu_table * tbl,long index,long npages,unsigned long uaddr,enum dma_data_direction direction,unsigned long attrs)1243decbda25SAlexey Kardashevskiy static int pnv_ioda2_tce_build(struct iommu_table *tbl, long index,
1244decbda25SAlexey Kardashevskiy long npages, unsigned long uaddr,
1245decbda25SAlexey Kardashevskiy enum dma_data_direction direction,
124600085f1eSKrzysztof Kozlowski unsigned long attrs)
12474cce9550SGavin Shan {
1248decbda25SAlexey Kardashevskiy int ret = pnv_tce_build(tbl, index, npages, uaddr, direction,
1249decbda25SAlexey Kardashevskiy attrs);
12504cce9550SGavin Shan
125108acce1cSBenjamin Herrenschmidt if (!ret)
1252cad32d9dSAlexey Kardashevskiy pnv_pci_ioda2_tce_invalidate(tbl, index, npages);
1253decbda25SAlexey Kardashevskiy
1254decbda25SAlexey Kardashevskiy return ret;
1255decbda25SAlexey Kardashevskiy }
1256decbda25SAlexey Kardashevskiy
pnv_ioda2_tce_free(struct iommu_table * tbl,long index,long npages)1257decbda25SAlexey Kardashevskiy static void pnv_ioda2_tce_free(struct iommu_table *tbl, long index,
1258decbda25SAlexey Kardashevskiy long npages)
1259decbda25SAlexey Kardashevskiy {
1260decbda25SAlexey Kardashevskiy pnv_tce_free(tbl, index, npages);
1261decbda25SAlexey Kardashevskiy
1262cad32d9dSAlexey Kardashevskiy pnv_pci_ioda2_tce_invalidate(tbl, index, npages);
12634cce9550SGavin Shan }
12644cce9550SGavin Shan
1265da004c36SAlexey Kardashevskiy static struct iommu_table_ops pnv_ioda2_iommu_ops = {
1266decbda25SAlexey Kardashevskiy .set = pnv_ioda2_tce_build,
126705c6cfb9SAlexey Kardashevskiy #ifdef CONFIG_IOMMU_API
126835872480SAlexey Kardashevskiy .xchg_no_kill = pnv_ioda_tce_xchg_no_kill,
126935872480SAlexey Kardashevskiy .tce_kill = pnv_pci_ioda2_tce_invalidate,
1270090bad39SAlexey Kardashevskiy .useraddrptr = pnv_tce_useraddrptr,
127105c6cfb9SAlexey Kardashevskiy #endif
1272decbda25SAlexey Kardashevskiy .clear = pnv_ioda2_tce_free,
1273da004c36SAlexey Kardashevskiy .get = pnv_tce_get,
1274da2bb0daSAlexey Kardashevskiy .free = pnv_pci_ioda2_table_free_pages,
1275da004c36SAlexey Kardashevskiy };
1276da004c36SAlexey Kardashevskiy
pnv_pci_ioda2_set_window(struct iommu_table_group * table_group,int num,struct iommu_table * tbl)127743cb60abSAlexey Kardashevskiy static long pnv_pci_ioda2_set_window(struct iommu_table_group *table_group,
127843cb60abSAlexey Kardashevskiy int num, struct iommu_table *tbl)
127943cb60abSAlexey Kardashevskiy {
128043cb60abSAlexey Kardashevskiy struct pnv_ioda_pe *pe = container_of(table_group, struct pnv_ioda_pe,
128143cb60abSAlexey Kardashevskiy table_group);
128243cb60abSAlexey Kardashevskiy struct pnv_phb *phb = pe->phb;
128343cb60abSAlexey Kardashevskiy int64_t rc;
1284bbb845c4SAlexey Kardashevskiy const unsigned long size = tbl->it_indirect_levels ?
1285bbb845c4SAlexey Kardashevskiy tbl->it_level_size : tbl->it_size;
128643cb60abSAlexey Kardashevskiy const __u64 start_addr = tbl->it_offset << tbl->it_page_shift;
128743cb60abSAlexey Kardashevskiy const __u64 win_size = tbl->it_size << tbl->it_page_shift;
128843cb60abSAlexey Kardashevskiy
12891e496391SJoe Perches pe_info(pe, "Setting up window#%d %llx..%llx pg=%lx\n",
12901e496391SJoe Perches num, start_addr, start_addr + win_size - 1,
129143cb60abSAlexey Kardashevskiy IOMMU_PAGE_SIZE(tbl));
129243cb60abSAlexey Kardashevskiy
129343cb60abSAlexey Kardashevskiy /*
129443cb60abSAlexey Kardashevskiy * Map TCE table through TVT. The TVE index is the PE number
129543cb60abSAlexey Kardashevskiy * shifted by 1 bit for 32-bits DMA space.
129643cb60abSAlexey Kardashevskiy */
129743cb60abSAlexey Kardashevskiy rc = opal_pci_map_pe_dma_window(phb->opal_id,
129843cb60abSAlexey Kardashevskiy pe->pe_number,
12994793d65dSAlexey Kardashevskiy (pe->pe_number << 1) + num,
1300bbb845c4SAlexey Kardashevskiy tbl->it_indirect_levels + 1,
130143cb60abSAlexey Kardashevskiy __pa(tbl->it_base),
1302bbb845c4SAlexey Kardashevskiy size << 3,
130343cb60abSAlexey Kardashevskiy IOMMU_PAGE_SIZE(tbl));
130443cb60abSAlexey Kardashevskiy if (rc) {
13051e496391SJoe Perches pe_err(pe, "Failed to configure TCE table, err %lld\n", rc);
130643cb60abSAlexey Kardashevskiy return rc;
130743cb60abSAlexey Kardashevskiy }
130843cb60abSAlexey Kardashevskiy
130943cb60abSAlexey Kardashevskiy pnv_pci_link_table_and_group(phb->hose->node, num,
131043cb60abSAlexey Kardashevskiy tbl, &pe->table_group);
1311ed7d9a1dSMichael Ellerman pnv_pci_ioda2_tce_invalidate_pe(pe);
131243cb60abSAlexey Kardashevskiy
131343cb60abSAlexey Kardashevskiy return 0;
131443cb60abSAlexey Kardashevskiy }
131543cb60abSAlexey Kardashevskiy
pnv_pci_ioda2_set_bypass(struct pnv_ioda_pe * pe,bool enable)1316c498a4f9SChristoph Hellwig static void pnv_pci_ioda2_set_bypass(struct pnv_ioda_pe *pe, bool enable)
1317cd15b048SBenjamin Herrenschmidt {
1318cd15b048SBenjamin Herrenschmidt uint16_t window_id = (pe->pe_number << 1 ) + 1;
1319cd15b048SBenjamin Herrenschmidt int64_t rc;
1320cd15b048SBenjamin Herrenschmidt
1321cd15b048SBenjamin Herrenschmidt pe_info(pe, "%sabling 64-bit DMA bypass\n", enable ? "En" : "Dis");
1322cd15b048SBenjamin Herrenschmidt if (enable) {
1323cd15b048SBenjamin Herrenschmidt phys_addr_t top = memblock_end_of_DRAM();
1324cd15b048SBenjamin Herrenschmidt
1325cd15b048SBenjamin Herrenschmidt top = roundup_pow_of_two(top);
1326cd15b048SBenjamin Herrenschmidt rc = opal_pci_map_pe_dma_window_real(pe->phb->opal_id,
1327cd15b048SBenjamin Herrenschmidt pe->pe_number,
1328cd15b048SBenjamin Herrenschmidt window_id,
1329cd15b048SBenjamin Herrenschmidt pe->tce_bypass_base,
1330cd15b048SBenjamin Herrenschmidt top);
1331cd15b048SBenjamin Herrenschmidt } else {
1332cd15b048SBenjamin Herrenschmidt rc = opal_pci_map_pe_dma_window_real(pe->phb->opal_id,
1333cd15b048SBenjamin Herrenschmidt pe->pe_number,
1334cd15b048SBenjamin Herrenschmidt window_id,
1335cd15b048SBenjamin Herrenschmidt pe->tce_bypass_base,
1336cd15b048SBenjamin Herrenschmidt 0);
1337cd15b048SBenjamin Herrenschmidt }
1338cd15b048SBenjamin Herrenschmidt if (rc)
1339cd15b048SBenjamin Herrenschmidt pe_err(pe, "OPAL error %lld configuring bypass window\n", rc);
1340cd15b048SBenjamin Herrenschmidt else
1341cd15b048SBenjamin Herrenschmidt pe->tce_bypass_enabled = enable;
1342cd15b048SBenjamin Herrenschmidt }
1343cd15b048SBenjamin Herrenschmidt
pnv_pci_ioda2_create_table(struct iommu_table_group * table_group,int num,__u32 page_shift,__u64 window_size,__u32 levels,bool alloc_userspace_copy,struct iommu_table ** ptbl)13444793d65dSAlexey Kardashevskiy static long pnv_pci_ioda2_create_table(struct iommu_table_group *table_group,
13454793d65dSAlexey Kardashevskiy int num, __u32 page_shift, __u64 window_size, __u32 levels,
1346090bad39SAlexey Kardashevskiy bool alloc_userspace_copy, struct iommu_table **ptbl)
13474793d65dSAlexey Kardashevskiy {
13484793d65dSAlexey Kardashevskiy struct pnv_ioda_pe *pe = container_of(table_group, struct pnv_ioda_pe,
13494793d65dSAlexey Kardashevskiy table_group);
13504793d65dSAlexey Kardashevskiy int nid = pe->phb->hose->node;
13514793d65dSAlexey Kardashevskiy __u64 bus_offset = num ? pe->tce_bypass_base : table_group->tce32_start;
13524793d65dSAlexey Kardashevskiy long ret;
13534793d65dSAlexey Kardashevskiy struct iommu_table *tbl;
13544793d65dSAlexey Kardashevskiy
13554793d65dSAlexey Kardashevskiy tbl = pnv_pci_table_alloc(nid);
13564793d65dSAlexey Kardashevskiy if (!tbl)
13574793d65dSAlexey Kardashevskiy return -ENOMEM;
13584793d65dSAlexey Kardashevskiy
135911edf116SAlexey Kardashevskiy tbl->it_ops = &pnv_ioda2_iommu_ops;
136011edf116SAlexey Kardashevskiy
13614793d65dSAlexey Kardashevskiy ret = pnv_pci_ioda2_table_alloc_pages(nid,
13624793d65dSAlexey Kardashevskiy bus_offset, page_shift, window_size,
1363090bad39SAlexey Kardashevskiy levels, alloc_userspace_copy, tbl);
13644793d65dSAlexey Kardashevskiy if (ret) {
1365e5afdf9dSAlexey Kardashevskiy iommu_tce_table_put(tbl);
13664793d65dSAlexey Kardashevskiy return ret;
13674793d65dSAlexey Kardashevskiy }
13684793d65dSAlexey Kardashevskiy
13694793d65dSAlexey Kardashevskiy *ptbl = tbl;
13704793d65dSAlexey Kardashevskiy
13714793d65dSAlexey Kardashevskiy return 0;
13724793d65dSAlexey Kardashevskiy }
13734793d65dSAlexey Kardashevskiy
pnv_pci_ioda2_setup_default_config(struct pnv_ioda_pe * pe)137446d3e1e1SAlexey Kardashevskiy static long pnv_pci_ioda2_setup_default_config(struct pnv_ioda_pe *pe)
137546d3e1e1SAlexey Kardashevskiy {
137646d3e1e1SAlexey Kardashevskiy struct iommu_table *tbl = NULL;
137746d3e1e1SAlexey Kardashevskiy long rc;
1378201ed7f3SAlexey Kardashevskiy unsigned long res_start, res_end;
137946d3e1e1SAlexey Kardashevskiy
1380bb005455SNishanth Aravamudan /*
1381fa144869SNishanth Aravamudan * crashkernel= specifies the kdump kernel's maximum memory at
1382fa144869SNishanth Aravamudan * some offset and there is no guaranteed the result is a power
1383fa144869SNishanth Aravamudan * of 2, which will cause errors later.
1384fa144869SNishanth Aravamudan */
1385fa144869SNishanth Aravamudan const u64 max_memory = __rounddown_pow_of_two(memory_hotplug_max());
1386fa144869SNishanth Aravamudan
1387fa144869SNishanth Aravamudan /*
1388bb005455SNishanth Aravamudan * In memory constrained environments, e.g. kdump kernel, the
1389bb005455SNishanth Aravamudan * DMA window can be larger than available memory, which will
1390bb005455SNishanth Aravamudan * cause errors later.
1391bb005455SNishanth Aravamudan */
139223baf831SKirill A. Shutemov const u64 maxblock = 1UL << (PAGE_SHIFT + MAX_ORDER);
1393bb005455SNishanth Aravamudan
1394201ed7f3SAlexey Kardashevskiy /*
1395201ed7f3SAlexey Kardashevskiy * We create the default window as big as we can. The constraint is
1396201ed7f3SAlexey Kardashevskiy * the max order of allocation possible. The TCE table is likely to
1397201ed7f3SAlexey Kardashevskiy * end up being multilevel and with on-demand allocation in place,
1398201ed7f3SAlexey Kardashevskiy * the initial use is not going to be huge as the default window aims
1399201ed7f3SAlexey Kardashevskiy * to support crippled devices (i.e. not fully 64bit DMAble) only.
1400201ed7f3SAlexey Kardashevskiy */
1401201ed7f3SAlexey Kardashevskiy /* iommu_table::it_map uses 1 bit per IOMMU page, hence 8 */
1402201ed7f3SAlexey Kardashevskiy const u64 window_size = min((maxblock * 8) << PAGE_SHIFT, max_memory);
1403201ed7f3SAlexey Kardashevskiy /* Each TCE level cannot exceed maxblock so go multilevel if needed */
1404201ed7f3SAlexey Kardashevskiy unsigned long tces_order = ilog2(window_size >> PAGE_SHIFT);
1405201ed7f3SAlexey Kardashevskiy unsigned long tcelevel_order = ilog2(maxblock >> 3);
1406201ed7f3SAlexey Kardashevskiy unsigned int levels = tces_order / tcelevel_order;
1407201ed7f3SAlexey Kardashevskiy
1408201ed7f3SAlexey Kardashevskiy if (tces_order % tcelevel_order)
1409201ed7f3SAlexey Kardashevskiy levels += 1;
1410201ed7f3SAlexey Kardashevskiy /*
1411201ed7f3SAlexey Kardashevskiy * We try to stick to default levels (which is >1 at the moment) in
1412201ed7f3SAlexey Kardashevskiy * order to save memory by relying on on-demain TCE level allocation.
1413201ed7f3SAlexey Kardashevskiy */
1414201ed7f3SAlexey Kardashevskiy levels = max_t(unsigned int, levels, POWERNV_IOMMU_DEFAULT_LEVELS);
1415201ed7f3SAlexey Kardashevskiy
1416201ed7f3SAlexey Kardashevskiy rc = pnv_pci_ioda2_create_table(&pe->table_group, 0, PAGE_SHIFT,
1417201ed7f3SAlexey Kardashevskiy window_size, levels, false, &tbl);
141846d3e1e1SAlexey Kardashevskiy if (rc) {
141946d3e1e1SAlexey Kardashevskiy pe_err(pe, "Failed to create 32-bit TCE table, err %ld",
142046d3e1e1SAlexey Kardashevskiy rc);
142146d3e1e1SAlexey Kardashevskiy return rc;
142246d3e1e1SAlexey Kardashevskiy }
142346d3e1e1SAlexey Kardashevskiy
1424201ed7f3SAlexey Kardashevskiy /* We use top part of 32bit space for MMIO so exclude it from DMA */
1425201ed7f3SAlexey Kardashevskiy res_start = 0;
1426201ed7f3SAlexey Kardashevskiy res_end = 0;
1427201ed7f3SAlexey Kardashevskiy if (window_size > pe->phb->ioda.m32_pci_base) {
1428201ed7f3SAlexey Kardashevskiy res_start = pe->phb->ioda.m32_pci_base >> tbl->it_page_shift;
1429201ed7f3SAlexey Kardashevskiy res_end = min(window_size, SZ_4G) >> tbl->it_page_shift;
1430201ed7f3SAlexey Kardashevskiy }
143146d3e1e1SAlexey Kardashevskiy
1432d73b46c3SAlexey Kardashevskiy tbl->it_index = (pe->phb->hose->global_number << 16) | pe->pe_number;
14334be518d8SAlexey Kardashevskiy if (iommu_init_table(tbl, pe->phb->hose->node, res_start, res_end))
143446d3e1e1SAlexey Kardashevskiy rc = pnv_pci_ioda2_set_window(&pe->table_group, 0, tbl);
14354be518d8SAlexey Kardashevskiy else
14364be518d8SAlexey Kardashevskiy rc = -ENOMEM;
143746d3e1e1SAlexey Kardashevskiy if (rc) {
14384be518d8SAlexey Kardashevskiy pe_err(pe, "Failed to configure 32-bit TCE table, err %ld\n", rc);
1439e5afdf9dSAlexey Kardashevskiy iommu_tce_table_put(tbl);
14404be518d8SAlexey Kardashevskiy tbl = NULL; /* This clears iommu_table_base below */
144146d3e1e1SAlexey Kardashevskiy }
144246d3e1e1SAlexey Kardashevskiy if (!pnv_iommu_bypass_disabled)
144346d3e1e1SAlexey Kardashevskiy pnv_pci_ioda2_set_bypass(pe, true);
144446d3e1e1SAlexey Kardashevskiy
14455636427dSAlexey Kardashevskiy /*
14465636427dSAlexey Kardashevskiy * Set table base for the case of IOMMU DMA use. Usually this is done
14475636427dSAlexey Kardashevskiy * from dma_dev_setup() which is not called when a device is returned
14485636427dSAlexey Kardashevskiy * from VFIO so do it here.
14495636427dSAlexey Kardashevskiy */
14505636427dSAlexey Kardashevskiy if (pe->pdev)
14515636427dSAlexey Kardashevskiy set_iommu_table_base(&pe->pdev->dev, tbl);
14525636427dSAlexey Kardashevskiy
145346d3e1e1SAlexey Kardashevskiy return 0;
145446d3e1e1SAlexey Kardashevskiy }
145546d3e1e1SAlexey Kardashevskiy
pnv_pci_ioda2_unset_window(struct iommu_table_group * table_group,int num)1456b5926430SAlexey Kardashevskiy static long pnv_pci_ioda2_unset_window(struct iommu_table_group *table_group,
1457b5926430SAlexey Kardashevskiy int num)
1458b5926430SAlexey Kardashevskiy {
1459b5926430SAlexey Kardashevskiy struct pnv_ioda_pe *pe = container_of(table_group, struct pnv_ioda_pe,
1460b5926430SAlexey Kardashevskiy table_group);
1461b5926430SAlexey Kardashevskiy struct pnv_phb *phb = pe->phb;
1462b5926430SAlexey Kardashevskiy long ret;
1463b5926430SAlexey Kardashevskiy
1464b5926430SAlexey Kardashevskiy pe_info(pe, "Removing DMA window #%d\n", num);
1465b5926430SAlexey Kardashevskiy
1466b5926430SAlexey Kardashevskiy ret = opal_pci_map_pe_dma_window(phb->opal_id, pe->pe_number,
1467b5926430SAlexey Kardashevskiy (pe->pe_number << 1) + num,
1468b5926430SAlexey Kardashevskiy 0/* levels */, 0/* table address */,
1469b5926430SAlexey Kardashevskiy 0/* table size */, 0/* page size */);
1470b5926430SAlexey Kardashevskiy if (ret)
1471b5926430SAlexey Kardashevskiy pe_warn(pe, "Unmapping failed, ret = %ld\n", ret);
1472b5926430SAlexey Kardashevskiy else
1473ed7d9a1dSMichael Ellerman pnv_pci_ioda2_tce_invalidate_pe(pe);
1474b5926430SAlexey Kardashevskiy
1475b5926430SAlexey Kardashevskiy pnv_pci_unlink_table_and_group(table_group->tables[num], table_group);
1476b5926430SAlexey Kardashevskiy
1477b5926430SAlexey Kardashevskiy return ret;
1478b5926430SAlexey Kardashevskiy }
1479b5926430SAlexey Kardashevskiy
1480f87a8864SAlexey Kardashevskiy #ifdef CONFIG_IOMMU_API
pnv_pci_ioda2_get_table_size(__u32 page_shift,__u64 window_size,__u32 levels)14810bd97167SAlexey Kardashevskiy unsigned long pnv_pci_ioda2_get_table_size(__u32 page_shift,
148200547193SAlexey Kardashevskiy __u64 window_size, __u32 levels)
148300547193SAlexey Kardashevskiy {
148400547193SAlexey Kardashevskiy unsigned long bytes = 0;
148500547193SAlexey Kardashevskiy const unsigned window_shift = ilog2(window_size);
148600547193SAlexey Kardashevskiy unsigned entries_shift = window_shift - page_shift;
148700547193SAlexey Kardashevskiy unsigned table_shift = entries_shift + 3;
148800547193SAlexey Kardashevskiy unsigned long tce_table_size = max(0x1000UL, 1UL << table_shift);
148900547193SAlexey Kardashevskiy unsigned long direct_table_size;
149000547193SAlexey Kardashevskiy
149100547193SAlexey Kardashevskiy if (!levels || (levels > POWERNV_IOMMU_MAX_LEVELS) ||
149200547193SAlexey Kardashevskiy !is_power_of_2(window_size))
149300547193SAlexey Kardashevskiy return 0;
149400547193SAlexey Kardashevskiy
149500547193SAlexey Kardashevskiy /* Calculate a direct table size from window_size and levels */
149600547193SAlexey Kardashevskiy entries_shift = (entries_shift + levels - 1) / levels;
149700547193SAlexey Kardashevskiy table_shift = entries_shift + 3;
149800547193SAlexey Kardashevskiy table_shift = max_t(unsigned, table_shift, PAGE_SHIFT);
149900547193SAlexey Kardashevskiy direct_table_size = 1UL << table_shift;
150000547193SAlexey Kardashevskiy
150100547193SAlexey Kardashevskiy for ( ; levels; --levels) {
1502b7115316SChristophe Leroy bytes += ALIGN(tce_table_size, direct_table_size);
150300547193SAlexey Kardashevskiy
150400547193SAlexey Kardashevskiy tce_table_size /= direct_table_size;
150500547193SAlexey Kardashevskiy tce_table_size <<= 3;
1506e49a6a21SAlexey Kardashevskiy tce_table_size = max_t(unsigned long,
1507e49a6a21SAlexey Kardashevskiy tce_table_size, direct_table_size);
150800547193SAlexey Kardashevskiy }
150900547193SAlexey Kardashevskiy
1510090bad39SAlexey Kardashevskiy return bytes + bytes; /* one for HW table, one for userspace copy */
1511090bad39SAlexey Kardashevskiy }
1512090bad39SAlexey Kardashevskiy
pnv_pci_ioda2_create_table_userspace(struct iommu_table_group * table_group,int num,__u32 page_shift,__u64 window_size,__u32 levels,struct iommu_table ** ptbl)1513090bad39SAlexey Kardashevskiy static long pnv_pci_ioda2_create_table_userspace(
1514090bad39SAlexey Kardashevskiy struct iommu_table_group *table_group,
1515090bad39SAlexey Kardashevskiy int num, __u32 page_shift, __u64 window_size, __u32 levels,
1516090bad39SAlexey Kardashevskiy struct iommu_table **ptbl)
1517090bad39SAlexey Kardashevskiy {
151811f5acceSAlexey Kardashevskiy long ret = pnv_pci_ioda2_create_table(table_group,
1519090bad39SAlexey Kardashevskiy num, page_shift, window_size, levels, true, ptbl);
152011f5acceSAlexey Kardashevskiy
152111f5acceSAlexey Kardashevskiy if (!ret)
152211f5acceSAlexey Kardashevskiy (*ptbl)->it_allocated_size = pnv_pci_ioda2_get_table_size(
152311f5acceSAlexey Kardashevskiy page_shift, window_size, levels);
152411f5acceSAlexey Kardashevskiy return ret;
152500547193SAlexey Kardashevskiy }
152600547193SAlexey Kardashevskiy
pnv_ioda_setup_bus_dma(struct pnv_ioda_pe * pe,struct pci_bus * bus)1527e3417faeSOliver O'Halloran static void pnv_ioda_setup_bus_dma(struct pnv_ioda_pe *pe, struct pci_bus *bus)
1528e3417faeSOliver O'Halloran {
1529e3417faeSOliver O'Halloran struct pci_dev *dev;
1530e3417faeSOliver O'Halloran
1531e3417faeSOliver O'Halloran list_for_each_entry(dev, &bus->devices, bus_list) {
1532e3417faeSOliver O'Halloran set_iommu_table_base(&dev->dev, pe->table_group.tables[0]);
1533e3417faeSOliver O'Halloran dev->dev.archdata.dma_offset = pe->tce_bypass_base;
1534e3417faeSOliver O'Halloran
1535e3417faeSOliver O'Halloran if ((pe->flags & PNV_IODA_PE_BUS_ALL) && dev->subordinate)
1536e3417faeSOliver O'Halloran pnv_ioda_setup_bus_dma(pe, dev->subordinate);
1537e3417faeSOliver O'Halloran }
1538e3417faeSOliver O'Halloran }
1539e3417faeSOliver O'Halloran
pnv_ioda2_take_ownership(struct iommu_table_group * table_group)15409d67c943SAlexey Kardashevskiy static long pnv_ioda2_take_ownership(struct iommu_table_group *table_group)
1541cd15b048SBenjamin Herrenschmidt {
1542f87a8864SAlexey Kardashevskiy struct pnv_ioda_pe *pe = container_of(table_group, struct pnv_ioda_pe,
1543f87a8864SAlexey Kardashevskiy table_group);
154446d3e1e1SAlexey Kardashevskiy /* Store @tbl as pnv_pci_ioda2_unset_window() resets it */
154546d3e1e1SAlexey Kardashevskiy struct iommu_table *tbl = pe->table_group.tables[0];
1546cd15b048SBenjamin Herrenschmidt
1547a9409044SAlexey Kardashevskiy /*
1548a9409044SAlexey Kardashevskiy * iommu_ops transfers the ownership per a device and we mode
1549a9409044SAlexey Kardashevskiy * the group ownership with the first device in the group.
1550a9409044SAlexey Kardashevskiy */
1551a9409044SAlexey Kardashevskiy if (!tbl)
1552a9409044SAlexey Kardashevskiy return 0;
1553a9409044SAlexey Kardashevskiy
1554f87a8864SAlexey Kardashevskiy pnv_pci_ioda2_set_bypass(pe, false);
155546d3e1e1SAlexey Kardashevskiy pnv_pci_ioda2_unset_window(&pe->table_group, 0);
1556db08e1d5SAlexey Kardashevskiy if (pe->pbus)
15575eada8a3SAlexey Kardashevskiy pnv_ioda_setup_bus_dma(pe, pe->pbus);
15585636427dSAlexey Kardashevskiy else if (pe->pdev)
15595636427dSAlexey Kardashevskiy set_iommu_table_base(&pe->pdev->dev, NULL);
1560e5afdf9dSAlexey Kardashevskiy iommu_tce_table_put(tbl);
15619d67c943SAlexey Kardashevskiy
15629d67c943SAlexey Kardashevskiy return 0;
1563cd15b048SBenjamin Herrenschmidt }
1564cd15b048SBenjamin Herrenschmidt
pnv_ioda2_release_ownership(struct iommu_table_group * table_group)1565f87a8864SAlexey Kardashevskiy static void pnv_ioda2_release_ownership(struct iommu_table_group *table_group)
1566f87a8864SAlexey Kardashevskiy {
1567f87a8864SAlexey Kardashevskiy struct pnv_ioda_pe *pe = container_of(table_group, struct pnv_ioda_pe,
1568f87a8864SAlexey Kardashevskiy table_group);
1569f87a8864SAlexey Kardashevskiy
1570a9409044SAlexey Kardashevskiy /* See the comment about iommu_ops above */
1571a9409044SAlexey Kardashevskiy if (pe->table_group.tables[0])
1572a9409044SAlexey Kardashevskiy return;
157346d3e1e1SAlexey Kardashevskiy pnv_pci_ioda2_setup_default_config(pe);
1574db08e1d5SAlexey Kardashevskiy if (pe->pbus)
15755eada8a3SAlexey Kardashevskiy pnv_ioda_setup_bus_dma(pe, pe->pbus);
1576f87a8864SAlexey Kardashevskiy }
1577f87a8864SAlexey Kardashevskiy
1578f87a8864SAlexey Kardashevskiy static struct iommu_table_group_ops pnv_pci_ioda2_ops = {
157900547193SAlexey Kardashevskiy .get_table_size = pnv_pci_ioda2_get_table_size,
1580090bad39SAlexey Kardashevskiy .create_table = pnv_pci_ioda2_create_table_userspace,
15814793d65dSAlexey Kardashevskiy .set_window = pnv_pci_ioda2_set_window,
15824793d65dSAlexey Kardashevskiy .unset_window = pnv_pci_ioda2_unset_window,
1583f87a8864SAlexey Kardashevskiy .take_ownership = pnv_ioda2_take_ownership,
1584f87a8864SAlexey Kardashevskiy .release_ownership = pnv_ioda2_release_ownership,
1585f87a8864SAlexey Kardashevskiy };
1586f87a8864SAlexey Kardashevskiy #endif
1587f87a8864SAlexey Kardashevskiy
pnv_pci_ioda2_setup_dma_pe(struct pnv_phb * phb,struct pnv_ioda_pe * pe)158837b59ef0SOliver O'Halloran void pnv_pci_ioda2_setup_dma_pe(struct pnv_phb *phb,
1589373f5657SGavin Shan struct pnv_ioda_pe *pe)
1590373f5657SGavin Shan {
1591373f5657SGavin Shan int64_t rc;
1592373f5657SGavin Shan
1593f87a8864SAlexey Kardashevskiy /* TVE #1 is selected by PCI address bit 59 */
1594f87a8864SAlexey Kardashevskiy pe->tce_bypass_base = 1ull << 59;
1595f87a8864SAlexey Kardashevskiy
1596373f5657SGavin Shan /* The PE will reserve all possible 32-bits space */
1597373f5657SGavin Shan pe_info(pe, "Setting up 32-bit TCE table at 0..%08x\n",
1598aca6913fSAlexey Kardashevskiy phb->ioda.m32_pci_base);
1599373f5657SGavin Shan
1600e5aad1e6SAlexey Kardashevskiy /* Setup linux iommu table */
16014793d65dSAlexey Kardashevskiy pe->table_group.tce32_start = 0;
16024793d65dSAlexey Kardashevskiy pe->table_group.tce32_size = phb->ioda.m32_pci_base;
16034793d65dSAlexey Kardashevskiy pe->table_group.max_dynamic_windows_supported =
16044793d65dSAlexey Kardashevskiy IOMMU_TABLE_GROUP_MAX_TABLES;
16054793d65dSAlexey Kardashevskiy pe->table_group.max_levels = POWERNV_IOMMU_MAX_LEVELS;
16067ef73cd3SAlexey Kardashevskiy pe->table_group.pgsizes = pnv_ioda_parse_tce_sizes(phb);
1607e5aad1e6SAlexey Kardashevskiy
160846d3e1e1SAlexey Kardashevskiy rc = pnv_pci_ioda2_setup_default_config(pe);
1609801846d1SGavin Shan if (rc)
161046d3e1e1SAlexey Kardashevskiy return;
161146d3e1e1SAlexey Kardashevskiy
16129b9408c5SOliver O'Halloran #ifdef CONFIG_IOMMU_API
16139b9408c5SOliver O'Halloran pe->table_group.ops = &pnv_pci_ioda2_ops;
16149b9408c5SOliver O'Halloran iommu_register_group(&pe->table_group, phb->hose->global_number,
16159b9408c5SOliver O'Halloran pe->pe_number);
16169b9408c5SOliver O'Halloran #endif
161701e12629SOliver O'Halloran pe->dma_setup_done = true;
1618373f5657SGavin Shan }
1619373f5657SGavin Shan
1620c325712bSCédric Le Goater /*
1621c325712bSCédric Le Goater * Called from KVM in real mode to EOI passthru interrupts. The ICP
1622c325712bSCédric Le Goater * EOI is handled directly in KVM in kvmppc_deliver_irq_passthru().
1623c325712bSCédric Le Goater *
1624c325712bSCédric Le Goater * The IRQ data is mapped in the PCI-MSI domain and the EOI OPAL call
1625c325712bSCédric Le Goater * needs an HW IRQ number mapped in the XICS IRQ domain. The HW IRQ
1626c325712bSCédric Le Goater * numbers of the in-the-middle MSI domain are vector numbers and it's
1627c325712bSCédric Le Goater * good enough for OPAL. Use that.
1628c325712bSCédric Le Goater */
pnv_opal_pci_msi_eoi(struct irq_data * d)1629c325712bSCédric Le Goater int64_t pnv_opal_pci_msi_eoi(struct irq_data *d)
1630137436c9SGavin Shan {
1631c325712bSCédric Le Goater struct pci_controller *hose = irq_data_get_irq_chip_data(d->parent_data);
1632c325712bSCédric Le Goater struct pnv_phb *phb = hose->private_data;
1633137436c9SGavin Shan
1634c325712bSCédric Le Goater return opal_pci_msi_eoi(phb->opal_id, d->parent_data->hwirq);
16354ee11c1aSSuresh Warrier }
16364ee11c1aSSuresh Warrier
16375cd69651SCédric Le Goater /*
16385cd69651SCédric Le Goater * The IRQ data is mapped in the XICS domain, with OPAL HW IRQ numbers
16395cd69651SCédric Le Goater */
pnv_ioda2_msi_eoi(struct irq_data * d)16404ee11c1aSSuresh Warrier static void pnv_ioda2_msi_eoi(struct irq_data *d)
16414ee11c1aSSuresh Warrier {
16424ee11c1aSSuresh Warrier int64_t rc;
16434ee11c1aSSuresh Warrier unsigned int hw_irq = (unsigned int)irqd_to_hwirq(d);
16445cd69651SCédric Le Goater struct pci_controller *hose = irq_data_get_irq_chip_data(d);
16455cd69651SCédric Le Goater struct pnv_phb *phb = hose->private_data;
16464ee11c1aSSuresh Warrier
16475cd69651SCédric Le Goater rc = opal_pci_msi_eoi(phb->opal_id, hw_irq);
1648137436c9SGavin Shan WARN_ON_ONCE(rc);
1649137436c9SGavin Shan
1650137436c9SGavin Shan icp_native_eoi(d);
1651137436c9SGavin Shan }
1652137436c9SGavin Shan
16535cd69651SCédric Le Goater /* P8/CXL only */
pnv_set_msi_irq_chip(struct pnv_phb * phb,unsigned int virq)1654f456834aSIan Munsie void pnv_set_msi_irq_chip(struct pnv_phb *phb, unsigned int virq)
1655fd9a1c26SIan Munsie {
1656fd9a1c26SIan Munsie struct irq_data *idata;
1657fd9a1c26SIan Munsie struct irq_chip *ichip;
1658fd9a1c26SIan Munsie
1659fb111334SBenjamin Herrenschmidt /* The MSI EOI OPAL call is only needed on PHB3 */
1660fb111334SBenjamin Herrenschmidt if (phb->model != PNV_PHB_MODEL_PHB3)
1661fd9a1c26SIan Munsie return;
1662fd9a1c26SIan Munsie
1663fd9a1c26SIan Munsie if (!phb->ioda.irq_chip_init) {
1664fd9a1c26SIan Munsie /*
1665fd9a1c26SIan Munsie * First time we setup an MSI IRQ, we need to setup the
1666fd9a1c26SIan Munsie * corresponding IRQ chip to route correctly.
1667fd9a1c26SIan Munsie */
1668fd9a1c26SIan Munsie idata = irq_get_irq_data(virq);
1669fd9a1c26SIan Munsie ichip = irq_data_get_irq_chip(idata);
1670fd9a1c26SIan Munsie phb->ioda.irq_chip_init = 1;
1671fd9a1c26SIan Munsie phb->ioda.irq_chip = *ichip;
1672fd9a1c26SIan Munsie phb->ioda.irq_chip.irq_eoi = pnv_ioda2_msi_eoi;
1673fd9a1c26SIan Munsie }
1674fd9a1c26SIan Munsie irq_set_chip(virq, &phb->ioda.irq_chip);
16755cd69651SCédric Le Goater irq_set_chip_data(virq, phb->hose);
1676fd9a1c26SIan Munsie }
1677fd9a1c26SIan Munsie
1678ba418a02SCédric Le Goater static struct irq_chip pnv_pci_msi_irq_chip;
1679ba418a02SCédric Le Goater
16804ee11c1aSSuresh Warrier /*
16814ee11c1aSSuresh Warrier * Returns true iff chip is something that we could call
16824ee11c1aSSuresh Warrier * pnv_opal_pci_msi_eoi for.
16834ee11c1aSSuresh Warrier */
is_pnv_opal_msi(struct irq_chip * chip)16844ee11c1aSSuresh Warrier bool is_pnv_opal_msi(struct irq_chip *chip)
16854ee11c1aSSuresh Warrier {
1686f1a377f8SCédric Le Goater return chip == &pnv_pci_msi_irq_chip;
16874ee11c1aSSuresh Warrier }
16884ee11c1aSSuresh Warrier EXPORT_SYMBOL_GPL(is_pnv_opal_msi);
16894ee11c1aSSuresh Warrier
__pnv_pci_ioda_msi_setup(struct pnv_phb * phb,struct pci_dev * dev,unsigned int xive_num,unsigned int is_64,struct msi_msg * msg)16902c50d7e9SCédric Le Goater static int __pnv_pci_ioda_msi_setup(struct pnv_phb *phb, struct pci_dev *dev,
16912c50d7e9SCédric Le Goater unsigned int xive_num,
1692137436c9SGavin Shan unsigned int is_64, struct msi_msg *msg)
1693184cd4a3SBenjamin Herrenschmidt {
1694184cd4a3SBenjamin Herrenschmidt struct pnv_ioda_pe *pe = pnv_ioda_get_pe(dev);
16953a1a4661SBenjamin Herrenschmidt __be32 data;
1696184cd4a3SBenjamin Herrenschmidt int rc;
1697184cd4a3SBenjamin Herrenschmidt
16982c50d7e9SCédric Le Goater dev_dbg(&dev->dev, "%s: setup %s-bit MSI for vector #%d\n", __func__,
16992c50d7e9SCédric Le Goater is_64 ? "64" : "32", xive_num);
17002c50d7e9SCédric Le Goater
1701184cd4a3SBenjamin Herrenschmidt /* No PE assigned ? bail out ... no MSI for you ! */
1702184cd4a3SBenjamin Herrenschmidt if (pe == NULL)
1703184cd4a3SBenjamin Herrenschmidt return -ENXIO;
1704184cd4a3SBenjamin Herrenschmidt
1705184cd4a3SBenjamin Herrenschmidt /* Check if we have an MVE */
1706184cd4a3SBenjamin Herrenschmidt if (pe->mve_number < 0)
1707184cd4a3SBenjamin Herrenschmidt return -ENXIO;
1708184cd4a3SBenjamin Herrenschmidt
1709b72c1f65SBenjamin Herrenschmidt /* Force 32-bit MSI on some broken devices */
171036074381SBenjamin Herrenschmidt if (dev->no_64bit_msi)
1711b72c1f65SBenjamin Herrenschmidt is_64 = 0;
1712b72c1f65SBenjamin Herrenschmidt
1713184cd4a3SBenjamin Herrenschmidt /* Assign XIVE to PE */
1714184cd4a3SBenjamin Herrenschmidt rc = opal_pci_set_xive_pe(phb->opal_id, pe->pe_number, xive_num);
1715184cd4a3SBenjamin Herrenschmidt if (rc) {
1716184cd4a3SBenjamin Herrenschmidt pr_warn("%s: OPAL error %d setting XIVE %d PE\n",
1717184cd4a3SBenjamin Herrenschmidt pci_name(dev), rc, xive_num);
1718184cd4a3SBenjamin Herrenschmidt return -EIO;
1719184cd4a3SBenjamin Herrenschmidt }
1720184cd4a3SBenjamin Herrenschmidt
1721184cd4a3SBenjamin Herrenschmidt if (is_64) {
17223a1a4661SBenjamin Herrenschmidt __be64 addr64;
17233a1a4661SBenjamin Herrenschmidt
1724184cd4a3SBenjamin Herrenschmidt rc = opal_get_msi_64(phb->opal_id, pe->mve_number, xive_num, 1,
1725184cd4a3SBenjamin Herrenschmidt &addr64, &data);
1726184cd4a3SBenjamin Herrenschmidt if (rc) {
1727184cd4a3SBenjamin Herrenschmidt pr_warn("%s: OPAL error %d getting 64-bit MSI data\n",
1728184cd4a3SBenjamin Herrenschmidt pci_name(dev), rc);
1729184cd4a3SBenjamin Herrenschmidt return -EIO;
1730184cd4a3SBenjamin Herrenschmidt }
17313a1a4661SBenjamin Herrenschmidt msg->address_hi = be64_to_cpu(addr64) >> 32;
17323a1a4661SBenjamin Herrenschmidt msg->address_lo = be64_to_cpu(addr64) & 0xfffffffful;
1733184cd4a3SBenjamin Herrenschmidt } else {
17343a1a4661SBenjamin Herrenschmidt __be32 addr32;
17353a1a4661SBenjamin Herrenschmidt
1736184cd4a3SBenjamin Herrenschmidt rc = opal_get_msi_32(phb->opal_id, pe->mve_number, xive_num, 1,
1737184cd4a3SBenjamin Herrenschmidt &addr32, &data);
1738184cd4a3SBenjamin Herrenschmidt if (rc) {
1739184cd4a3SBenjamin Herrenschmidt pr_warn("%s: OPAL error %d getting 32-bit MSI data\n",
1740184cd4a3SBenjamin Herrenschmidt pci_name(dev), rc);
1741184cd4a3SBenjamin Herrenschmidt return -EIO;
1742184cd4a3SBenjamin Herrenschmidt }
1743184cd4a3SBenjamin Herrenschmidt msg->address_hi = 0;
17443a1a4661SBenjamin Herrenschmidt msg->address_lo = be32_to_cpu(addr32);
1745184cd4a3SBenjamin Herrenschmidt }
17463a1a4661SBenjamin Herrenschmidt msg->data = be32_to_cpu(data);
1747184cd4a3SBenjamin Herrenschmidt
17482c50d7e9SCédric Le Goater return 0;
17492c50d7e9SCédric Le Goater }
17502c50d7e9SCédric Le Goater
17510fcfe224SCédric Le Goater /*
17520fcfe224SCédric Le Goater * The msi_free() op is called before irq_domain_free_irqs_top() when
17530fcfe224SCédric Le Goater * the handler data is still available. Use that to clear the XIVE
17540fcfe224SCédric Le Goater * controller.
17550fcfe224SCédric Le Goater */
pnv_msi_ops_msi_free(struct irq_domain * domain,struct msi_domain_info * info,unsigned int irq)17560fcfe224SCédric Le Goater static void pnv_msi_ops_msi_free(struct irq_domain *domain,
17570fcfe224SCédric Le Goater struct msi_domain_info *info,
17580fcfe224SCédric Le Goater unsigned int irq)
17590fcfe224SCédric Le Goater {
17600fcfe224SCédric Le Goater if (xive_enabled())
17610fcfe224SCédric Le Goater xive_irq_free_data(irq);
17620fcfe224SCédric Le Goater }
17630fcfe224SCédric Le Goater
17640fcfe224SCédric Le Goater static struct msi_domain_ops pnv_pci_msi_domain_ops = {
17650fcfe224SCédric Le Goater .msi_free = pnv_msi_ops_msi_free,
17660fcfe224SCédric Le Goater };
17670fcfe224SCédric Le Goater
pnv_msi_shutdown(struct irq_data * d)17680fcfe224SCédric Le Goater static void pnv_msi_shutdown(struct irq_data *d)
17690fcfe224SCédric Le Goater {
17700fcfe224SCédric Le Goater d = d->parent_data;
17710fcfe224SCédric Le Goater if (d->chip->irq_shutdown)
17720fcfe224SCédric Le Goater d->chip->irq_shutdown(d);
17730fcfe224SCédric Le Goater }
17740fcfe224SCédric Le Goater
pnv_msi_mask(struct irq_data * d)17750fcfe224SCédric Le Goater static void pnv_msi_mask(struct irq_data *d)
17760fcfe224SCédric Le Goater {
17770fcfe224SCédric Le Goater pci_msi_mask_irq(d);
17780fcfe224SCédric Le Goater irq_chip_mask_parent(d);
17790fcfe224SCédric Le Goater }
17800fcfe224SCédric Le Goater
pnv_msi_unmask(struct irq_data * d)17810fcfe224SCédric Le Goater static void pnv_msi_unmask(struct irq_data *d)
17820fcfe224SCédric Le Goater {
17830fcfe224SCédric Le Goater pci_msi_unmask_irq(d);
17840fcfe224SCédric Le Goater irq_chip_unmask_parent(d);
17850fcfe224SCédric Le Goater }
17860fcfe224SCédric Le Goater
17870fcfe224SCédric Le Goater static struct irq_chip pnv_pci_msi_irq_chip = {
17880fcfe224SCédric Le Goater .name = "PNV-PCI-MSI",
17890fcfe224SCédric Le Goater .irq_shutdown = pnv_msi_shutdown,
17900fcfe224SCédric Le Goater .irq_mask = pnv_msi_mask,
17910fcfe224SCédric Le Goater .irq_unmask = pnv_msi_unmask,
17920fcfe224SCédric Le Goater .irq_eoi = irq_chip_eoi_parent,
17930fcfe224SCédric Le Goater };
17940fcfe224SCédric Le Goater
17950fcfe224SCédric Le Goater static struct msi_domain_info pnv_msi_domain_info = {
17960fcfe224SCédric Le Goater .flags = (MSI_FLAG_USE_DEF_DOM_OPS | MSI_FLAG_USE_DEF_CHIP_OPS |
17970fcfe224SCédric Le Goater MSI_FLAG_MULTI_PCI_MSI | MSI_FLAG_PCI_MSIX),
17980fcfe224SCédric Le Goater .ops = &pnv_pci_msi_domain_ops,
17990fcfe224SCédric Le Goater .chip = &pnv_pci_msi_irq_chip,
18000fcfe224SCédric Le Goater };
18010fcfe224SCédric Le Goater
pnv_msi_compose_msg(struct irq_data * d,struct msi_msg * msg)18020fcfe224SCédric Le Goater static void pnv_msi_compose_msg(struct irq_data *d, struct msi_msg *msg)
18030fcfe224SCédric Le Goater {
18040fcfe224SCédric Le Goater struct msi_desc *entry = irq_data_get_msi_desc(d);
18050fcfe224SCédric Le Goater struct pci_dev *pdev = msi_desc_to_pci_dev(entry);
18060fcfe224SCédric Le Goater struct pci_controller *hose = irq_data_get_irq_chip_data(d);
18070fcfe224SCédric Le Goater struct pnv_phb *phb = hose->private_data;
18080fcfe224SCédric Le Goater int rc;
18090fcfe224SCédric Le Goater
18100fcfe224SCédric Le Goater rc = __pnv_pci_ioda_msi_setup(phb, pdev, d->hwirq,
1811e58f2259SThomas Gleixner entry->pci.msi_attrib.is_64, msg);
18120fcfe224SCédric Le Goater if (rc)
18130fcfe224SCédric Le Goater dev_err(&pdev->dev, "Failed to setup %s-bit MSI #%ld : %d\n",
1814e58f2259SThomas Gleixner entry->pci.msi_attrib.is_64 ? "64" : "32", d->hwirq, rc);
18150fcfe224SCédric Le Goater }
18160fcfe224SCédric Le Goater
1817bbb25af8SCédric Le Goater /*
1818bbb25af8SCédric Le Goater * The IRQ data is mapped in the MSI domain in which HW IRQ numbers
1819bbb25af8SCédric Le Goater * correspond to vector numbers.
1820bbb25af8SCédric Le Goater */
pnv_msi_eoi(struct irq_data * d)1821bbb25af8SCédric Le Goater static void pnv_msi_eoi(struct irq_data *d)
1822bbb25af8SCédric Le Goater {
1823bbb25af8SCédric Le Goater struct pci_controller *hose = irq_data_get_irq_chip_data(d);
1824bbb25af8SCédric Le Goater struct pnv_phb *phb = hose->private_data;
1825bbb25af8SCédric Le Goater
1826bbb25af8SCédric Le Goater if (phb->model == PNV_PHB_MODEL_PHB3) {
1827bbb25af8SCédric Le Goater /*
1828bbb25af8SCédric Le Goater * The EOI OPAL call takes an OPAL HW IRQ number but
1829bbb25af8SCédric Le Goater * since it is translated into a vector number in
1830bbb25af8SCédric Le Goater * OPAL, use that directly.
1831bbb25af8SCédric Le Goater */
1832bbb25af8SCédric Le Goater WARN_ON_ONCE(opal_pci_msi_eoi(phb->opal_id, d->hwirq));
1833bbb25af8SCédric Le Goater }
1834bbb25af8SCédric Le Goater
1835bbb25af8SCédric Le Goater irq_chip_eoi_parent(d);
1836bbb25af8SCédric Le Goater }
1837bbb25af8SCédric Le Goater
18380fcfe224SCédric Le Goater static struct irq_chip pnv_msi_irq_chip = {
18390fcfe224SCédric Le Goater .name = "PNV-MSI",
18400fcfe224SCédric Le Goater .irq_shutdown = pnv_msi_shutdown,
18410fcfe224SCédric Le Goater .irq_mask = irq_chip_mask_parent,
18420fcfe224SCédric Le Goater .irq_unmask = irq_chip_unmask_parent,
1843bbb25af8SCédric Le Goater .irq_eoi = pnv_msi_eoi,
18440fcfe224SCédric Le Goater .irq_set_affinity = irq_chip_set_affinity_parent,
18450fcfe224SCédric Le Goater .irq_compose_msi_msg = pnv_msi_compose_msg,
18460fcfe224SCédric Le Goater };
18470fcfe224SCédric Le Goater
pnv_irq_parent_domain_alloc(struct irq_domain * domain,unsigned int virq,int hwirq)18480fcfe224SCédric Le Goater static int pnv_irq_parent_domain_alloc(struct irq_domain *domain,
18490fcfe224SCédric Le Goater unsigned int virq, int hwirq)
18500fcfe224SCédric Le Goater {
18510fcfe224SCédric Le Goater struct irq_fwspec parent_fwspec;
18520fcfe224SCédric Le Goater int ret;
18530fcfe224SCédric Le Goater
18540fcfe224SCédric Le Goater parent_fwspec.fwnode = domain->parent->fwnode;
18550fcfe224SCédric Le Goater parent_fwspec.param_count = 2;
18560fcfe224SCédric Le Goater parent_fwspec.param[0] = hwirq;
18570fcfe224SCédric Le Goater parent_fwspec.param[1] = IRQ_TYPE_EDGE_RISING;
18580fcfe224SCédric Le Goater
18590fcfe224SCédric Le Goater ret = irq_domain_alloc_irqs_parent(domain, virq, 1, &parent_fwspec);
18600fcfe224SCédric Le Goater if (ret)
18610fcfe224SCédric Le Goater return ret;
18620fcfe224SCédric Le Goater
18630fcfe224SCédric Le Goater return 0;
18640fcfe224SCédric Le Goater }
18650fcfe224SCédric Le Goater
pnv_irq_domain_alloc(struct irq_domain * domain,unsigned int virq,unsigned int nr_irqs,void * arg)18660fcfe224SCédric Le Goater static int pnv_irq_domain_alloc(struct irq_domain *domain, unsigned int virq,
18670fcfe224SCédric Le Goater unsigned int nr_irqs, void *arg)
18680fcfe224SCédric Le Goater {
18690fcfe224SCédric Le Goater struct pci_controller *hose = domain->host_data;
18700fcfe224SCédric Le Goater struct pnv_phb *phb = hose->private_data;
18710fcfe224SCédric Le Goater msi_alloc_info_t *info = arg;
18720fcfe224SCédric Le Goater struct pci_dev *pdev = msi_desc_to_pci_dev(info->desc);
18730fcfe224SCédric Le Goater int hwirq;
18740fcfe224SCédric Le Goater int i, ret;
18750fcfe224SCédric Le Goater
18760fcfe224SCédric Le Goater hwirq = msi_bitmap_alloc_hwirqs(&phb->msi_bmp, nr_irqs);
18770fcfe224SCédric Le Goater if (hwirq < 0) {
18780fcfe224SCédric Le Goater dev_warn(&pdev->dev, "failed to find a free MSI\n");
18790fcfe224SCédric Le Goater return -ENOSPC;
18800fcfe224SCédric Le Goater }
18810fcfe224SCédric Le Goater
18820fcfe224SCédric Le Goater dev_dbg(&pdev->dev, "%s bridge %pOF %d/%x #%d\n", __func__,
18830fcfe224SCédric Le Goater hose->dn, virq, hwirq, nr_irqs);
18840fcfe224SCédric Le Goater
18850fcfe224SCédric Le Goater for (i = 0; i < nr_irqs; i++) {
18860fcfe224SCédric Le Goater ret = pnv_irq_parent_domain_alloc(domain, virq + i,
18870fcfe224SCédric Le Goater phb->msi_base + hwirq + i);
18880fcfe224SCédric Le Goater if (ret)
18890fcfe224SCédric Le Goater goto out;
18900fcfe224SCédric Le Goater
18910fcfe224SCédric Le Goater irq_domain_set_hwirq_and_chip(domain, virq + i, hwirq + i,
18920fcfe224SCédric Le Goater &pnv_msi_irq_chip, hose);
18930fcfe224SCédric Le Goater }
18940fcfe224SCédric Le Goater
18950fcfe224SCédric Le Goater return 0;
18960fcfe224SCédric Le Goater
18970fcfe224SCédric Le Goater out:
18980fcfe224SCédric Le Goater irq_domain_free_irqs_parent(domain, virq, i - 1);
18990fcfe224SCédric Le Goater msi_bitmap_free_hwirqs(&phb->msi_bmp, hwirq, nr_irqs);
19000fcfe224SCédric Le Goater return ret;
19010fcfe224SCédric Le Goater }
19020fcfe224SCédric Le Goater
pnv_irq_domain_free(struct irq_domain * domain,unsigned int virq,unsigned int nr_irqs)19030fcfe224SCédric Le Goater static void pnv_irq_domain_free(struct irq_domain *domain, unsigned int virq,
19040fcfe224SCédric Le Goater unsigned int nr_irqs)
19050fcfe224SCédric Le Goater {
19060fcfe224SCédric Le Goater struct irq_data *d = irq_domain_get_irq_data(domain, virq);
19070fcfe224SCédric Le Goater struct pci_controller *hose = irq_data_get_irq_chip_data(d);
19080fcfe224SCédric Le Goater struct pnv_phb *phb = hose->private_data;
19090fcfe224SCédric Le Goater
19100fcfe224SCédric Le Goater pr_debug("%s bridge %pOF %d/%lx #%d\n", __func__, hose->dn,
19110fcfe224SCédric Le Goater virq, d->hwirq, nr_irqs);
19120fcfe224SCédric Le Goater
19130fcfe224SCédric Le Goater msi_bitmap_free_hwirqs(&phb->msi_bmp, d->hwirq, nr_irqs);
19140fcfe224SCédric Le Goater /* XIVE domain is cleared through ->msi_free() */
19150fcfe224SCédric Le Goater }
19160fcfe224SCédric Le Goater
19170fcfe224SCédric Le Goater static const struct irq_domain_ops pnv_irq_domain_ops = {
19180fcfe224SCédric Le Goater .alloc = pnv_irq_domain_alloc,
19190fcfe224SCédric Le Goater .free = pnv_irq_domain_free,
19200fcfe224SCédric Le Goater };
19210fcfe224SCédric Le Goater
pnv_msi_allocate_domains(struct pci_controller * hose,unsigned int count)1922e5913db1SNick Child static int __init pnv_msi_allocate_domains(struct pci_controller *hose, unsigned int count)
19230fcfe224SCédric Le Goater {
19240fcfe224SCédric Le Goater struct pnv_phb *phb = hose->private_data;
19250fcfe224SCédric Le Goater struct irq_domain *parent = irq_get_default_host();
19260fcfe224SCédric Le Goater
19270fcfe224SCédric Le Goater hose->fwnode = irq_domain_alloc_named_id_fwnode("PNV-MSI", phb->opal_id);
19280fcfe224SCédric Le Goater if (!hose->fwnode)
19290fcfe224SCédric Le Goater return -ENOMEM;
19300fcfe224SCédric Le Goater
19310fcfe224SCédric Le Goater hose->dev_domain = irq_domain_create_hierarchy(parent, 0, count,
19320fcfe224SCédric Le Goater hose->fwnode,
19330fcfe224SCédric Le Goater &pnv_irq_domain_ops, hose);
19340fcfe224SCédric Le Goater if (!hose->dev_domain) {
19350fcfe224SCédric Le Goater pr_err("PCI: failed to create IRQ domain bridge %pOF (domain %d)\n",
19360fcfe224SCédric Le Goater hose->dn, hose->global_number);
19370fcfe224SCédric Le Goater irq_domain_free_fwnode(hose->fwnode);
19380fcfe224SCédric Le Goater return -ENOMEM;
19390fcfe224SCédric Le Goater }
19400fcfe224SCédric Le Goater
19410fcfe224SCédric Le Goater hose->msi_domain = pci_msi_create_irq_domain(of_node_to_fwnode(hose->dn),
19420fcfe224SCédric Le Goater &pnv_msi_domain_info,
19430fcfe224SCédric Le Goater hose->dev_domain);
19440fcfe224SCédric Le Goater if (!hose->msi_domain) {
19450fcfe224SCédric Le Goater pr_err("PCI: failed to create MSI IRQ domain bridge %pOF (domain %d)\n",
19460fcfe224SCédric Le Goater hose->dn, hose->global_number);
19470fcfe224SCédric Le Goater irq_domain_free_fwnode(hose->fwnode);
19480fcfe224SCédric Le Goater irq_domain_remove(hose->dev_domain);
19490fcfe224SCédric Le Goater return -ENOMEM;
19500fcfe224SCédric Le Goater }
19510fcfe224SCédric Le Goater
19520fcfe224SCédric Le Goater return 0;
19530fcfe224SCédric Le Goater }
19540fcfe224SCédric Le Goater
pnv_pci_init_ioda_msis(struct pnv_phb * phb)1955e5913db1SNick Child static void __init pnv_pci_init_ioda_msis(struct pnv_phb *phb)
1956184cd4a3SBenjamin Herrenschmidt {
1957fb1b55d6SGavin Shan unsigned int count;
1958184cd4a3SBenjamin Herrenschmidt const __be32 *prop = of_get_property(phb->hose->dn,
1959184cd4a3SBenjamin Herrenschmidt "ibm,opal-msi-ranges", NULL);
1960184cd4a3SBenjamin Herrenschmidt if (!prop) {
1961184cd4a3SBenjamin Herrenschmidt /* BML Fallback */
1962184cd4a3SBenjamin Herrenschmidt prop = of_get_property(phb->hose->dn, "msi-ranges", NULL);
1963184cd4a3SBenjamin Herrenschmidt }
1964184cd4a3SBenjamin Herrenschmidt if (!prop)
1965184cd4a3SBenjamin Herrenschmidt return;
1966184cd4a3SBenjamin Herrenschmidt
1967184cd4a3SBenjamin Herrenschmidt phb->msi_base = be32_to_cpup(prop);
1968fb1b55d6SGavin Shan count = be32_to_cpup(prop + 1);
1969fb1b55d6SGavin Shan if (msi_bitmap_alloc(&phb->msi_bmp, count, phb->hose->dn)) {
1970184cd4a3SBenjamin Herrenschmidt pr_err("PCI %d: Failed to allocate MSI bitmap !\n",
1971184cd4a3SBenjamin Herrenschmidt phb->hose->global_number);
1972184cd4a3SBenjamin Herrenschmidt return;
1973184cd4a3SBenjamin Herrenschmidt }
1974fb1b55d6SGavin Shan
1975184cd4a3SBenjamin Herrenschmidt pr_info(" Allocated bitmap for %d MSIs (base IRQ 0x%x)\n",
1976fb1b55d6SGavin Shan count, phb->msi_base);
19770fcfe224SCédric Le Goater
19780fcfe224SCédric Le Goater pnv_msi_allocate_domains(phb->hose, count);
1979184cd4a3SBenjamin Herrenschmidt }
1980184cd4a3SBenjamin Herrenschmidt
pnv_ioda_setup_pe_res(struct pnv_ioda_pe * pe,struct resource * res)198123e79425SGavin Shan static void pnv_ioda_setup_pe_res(struct pnv_ioda_pe *pe,
198223e79425SGavin Shan struct resource *res)
198311685becSGavin Shan {
198423e79425SGavin Shan struct pnv_phb *phb = pe->phb;
198511685becSGavin Shan struct pci_bus_region region;
198623e79425SGavin Shan int index;
198723e79425SGavin Shan int64_t rc;
198811685becSGavin Shan
1989e64e7105SFrederic Barrat if (!res || !res->flags || res->start > res->end ||
1990e64e7105SFrederic Barrat res->flags & IORESOURCE_UNSET)
199123e79425SGavin Shan return;
199211685becSGavin Shan
199311685becSGavin Shan if (res->flags & IORESOURCE_IO) {
199411685becSGavin Shan region.start = res->start - phb->ioda.io_pci_base;
199511685becSGavin Shan region.end = res->end - phb->ioda.io_pci_base;
199611685becSGavin Shan index = region.start / phb->ioda.io_segsize;
199711685becSGavin Shan
199892b8f137SGavin Shan while (index < phb->ioda.total_pe_num &&
199911685becSGavin Shan region.start <= region.end) {
200011685becSGavin Shan phb->ioda.io_segmap[index] = pe->pe_number;
200111685becSGavin Shan rc = opal_pci_map_pe_mmio_window(phb->opal_id,
200211685becSGavin Shan pe->pe_number, OPAL_IO_WINDOW_TYPE, 0, index);
200311685becSGavin Shan if (rc != OPAL_SUCCESS) {
20041f52f176SRussell Currey pr_err("%s: Error %lld mapping IO segment#%d to PE#%x\n",
200511685becSGavin Shan __func__, rc, index, pe->pe_number);
200611685becSGavin Shan break;
200711685becSGavin Shan }
200811685becSGavin Shan
200911685becSGavin Shan region.start += phb->ioda.io_segsize;
201011685becSGavin Shan index++;
201111685becSGavin Shan }
2012027fa02fSGavin Shan } else if ((res->flags & IORESOURCE_MEM) &&
20135958d19aSBenjamin Herrenschmidt !pnv_pci_is_m64(phb, res)) {
201411685becSGavin Shan region.start = res->start -
201523e79425SGavin Shan phb->hose->mem_offset[0] -
201611685becSGavin Shan phb->ioda.m32_pci_base;
201711685becSGavin Shan region.end = res->end -
201823e79425SGavin Shan phb->hose->mem_offset[0] -
201911685becSGavin Shan phb->ioda.m32_pci_base;
202011685becSGavin Shan index = region.start / phb->ioda.m32_segsize;
202111685becSGavin Shan
202292b8f137SGavin Shan while (index < phb->ioda.total_pe_num &&
202311685becSGavin Shan region.start <= region.end) {
202411685becSGavin Shan phb->ioda.m32_segmap[index] = pe->pe_number;
202511685becSGavin Shan rc = opal_pci_map_pe_mmio_window(phb->opal_id,
202611685becSGavin Shan pe->pe_number, OPAL_M32_WINDOW_TYPE, 0, index);
202711685becSGavin Shan if (rc != OPAL_SUCCESS) {
20281f52f176SRussell Currey pr_err("%s: Error %lld mapping M32 segment#%d to PE#%x",
202911685becSGavin Shan __func__, rc, index, pe->pe_number);
203011685becSGavin Shan break;
203111685becSGavin Shan }
203211685becSGavin Shan
203311685becSGavin Shan region.start += phb->ioda.m32_segsize;
203411685becSGavin Shan index++;
203511685becSGavin Shan }
203611685becSGavin Shan }
203711685becSGavin Shan }
203823e79425SGavin Shan
203923e79425SGavin Shan /*
204023e79425SGavin Shan * This function is supposed to be called on basis of PE from top
204187c78b61SMichael Ellerman * to bottom style. So the I/O or MMIO segment assigned to
204203671057SMasahiro Yamada * parent PE could be overridden by its child PEs if necessary.
204323e79425SGavin Shan */
pnv_ioda_setup_pe_seg(struct pnv_ioda_pe * pe)204423e79425SGavin Shan static void pnv_ioda_setup_pe_seg(struct pnv_ioda_pe *pe)
204523e79425SGavin Shan {
204669d733e7SGavin Shan struct pci_dev *pdev;
204723e79425SGavin Shan int i;
204823e79425SGavin Shan
204923e79425SGavin Shan /*
205023e79425SGavin Shan * NOTE: We only care PCI bus based PE for now. For PCI
205123e79425SGavin Shan * device based PE, for example SRIOV sensitive VF should
205223e79425SGavin Shan * be figured out later.
205323e79425SGavin Shan */
205423e79425SGavin Shan BUG_ON(!(pe->flags & (PNV_IODA_PE_BUS | PNV_IODA_PE_BUS_ALL)));
205523e79425SGavin Shan
205669d733e7SGavin Shan list_for_each_entry(pdev, &pe->pbus->devices, bus_list) {
205769d733e7SGavin Shan for (i = 0; i <= PCI_ROM_RESOURCE; i++)
205869d733e7SGavin Shan pnv_ioda_setup_pe_res(pe, &pdev->resource[i]);
205969d733e7SGavin Shan
206069d733e7SGavin Shan /*
206169d733e7SGavin Shan * If the PE contains all subordinate PCI buses, the
206269d733e7SGavin Shan * windows of the child bridges should be mapped to
206369d733e7SGavin Shan * the PE as well.
206469d733e7SGavin Shan */
206569d733e7SGavin Shan if (!(pe->flags & PNV_IODA_PE_BUS_ALL) || !pci_is_bridge(pdev))
206669d733e7SGavin Shan continue;
206769d733e7SGavin Shan for (i = 0; i < PCI_BRIDGE_RESOURCE_NUM; i++)
206869d733e7SGavin Shan pnv_ioda_setup_pe_res(pe,
206969d733e7SGavin Shan &pdev->resource[PCI_BRIDGE_RESOURCES + i]);
207069d733e7SGavin Shan }
207111685becSGavin Shan }
207211685becSGavin Shan
207398b665daSRussell Currey #ifdef CONFIG_DEBUG_FS
pnv_pci_diag_data_set(void * data,u64 val)207498b665daSRussell Currey static int pnv_pci_diag_data_set(void *data, u64 val)
207598b665daSRussell Currey {
207622ba7289SOliver O'Halloran struct pnv_phb *phb = data;
207798b665daSRussell Currey s64 ret;
207898b665daSRussell Currey
207998b665daSRussell Currey /* Retrieve the diag data from firmware */
20805cb1f8fdSRussell Currey ret = opal_pci_get_phb_diag_data2(phb->opal_id, phb->diag_data,
20815cb1f8fdSRussell Currey phb->diag_data_size);
208298b665daSRussell Currey if (ret != OPAL_SUCCESS)
208398b665daSRussell Currey return -EIO;
208498b665daSRussell Currey
208598b665daSRussell Currey /* Print the diag data to the kernel log */
20865cb1f8fdSRussell Currey pnv_pci_dump_phb_diag_data(phb->hose, phb->diag_data);
208798b665daSRussell Currey return 0;
208898b665daSRussell Currey }
208998b665daSRussell Currey
2090bfa2325eSYueHaibing DEFINE_DEBUGFS_ATTRIBUTE(pnv_pci_diag_data_fops, NULL, pnv_pci_diag_data_set,
2091bfa2325eSYueHaibing "%llu\n");
209298b665daSRussell Currey
pnv_pci_ioda_pe_dump(void * data,u64 val)209318697d2bSOliver O'Halloran static int pnv_pci_ioda_pe_dump(void *data, u64 val)
209418697d2bSOliver O'Halloran {
209518697d2bSOliver O'Halloran struct pnv_phb *phb = data;
209618697d2bSOliver O'Halloran int pe_num;
209718697d2bSOliver O'Halloran
209818697d2bSOliver O'Halloran for (pe_num = 0; pe_num < phb->ioda.total_pe_num; pe_num++) {
209918697d2bSOliver O'Halloran struct pnv_ioda_pe *pe = &phb->ioda.pe_array[pe_num];
210018697d2bSOliver O'Halloran
210118697d2bSOliver O'Halloran if (!test_bit(pe_num, phb->ioda.pe_alloc))
210218697d2bSOliver O'Halloran continue;
210318697d2bSOliver O'Halloran
210418697d2bSOliver O'Halloran pe_warn(pe, "rid: %04x dev count: %2d flags: %s%s%s%s%s%s\n",
210518697d2bSOliver O'Halloran pe->rid, pe->device_count,
210618697d2bSOliver O'Halloran (pe->flags & PNV_IODA_PE_DEV) ? "dev " : "",
210718697d2bSOliver O'Halloran (pe->flags & PNV_IODA_PE_BUS) ? "bus " : "",
210818697d2bSOliver O'Halloran (pe->flags & PNV_IODA_PE_BUS_ALL) ? "all " : "",
210918697d2bSOliver O'Halloran (pe->flags & PNV_IODA_PE_MASTER) ? "master " : "",
211018697d2bSOliver O'Halloran (pe->flags & PNV_IODA_PE_SLAVE) ? "slave " : "",
211118697d2bSOliver O'Halloran (pe->flags & PNV_IODA_PE_VF) ? "vf " : "");
211218697d2bSOliver O'Halloran }
211318697d2bSOliver O'Halloran
211418697d2bSOliver O'Halloran return 0;
211518697d2bSOliver O'Halloran }
211618697d2bSOliver O'Halloran
211718697d2bSOliver O'Halloran DEFINE_DEBUGFS_ATTRIBUTE(pnv_pci_ioda_pe_dump_fops, NULL,
211818697d2bSOliver O'Halloran pnv_pci_ioda_pe_dump, "%llu\n");
211918697d2bSOliver O'Halloran
212098b665daSRussell Currey #endif /* CONFIG_DEBUG_FS */
212198b665daSRussell Currey
pnv_pci_ioda_create_dbgfs(void)212237c367f2SGavin Shan static void pnv_pci_ioda_create_dbgfs(void)
212337c367f2SGavin Shan {
212437c367f2SGavin Shan #ifdef CONFIG_DEBUG_FS
212537c367f2SGavin Shan struct pci_controller *hose, *tmp;
212637c367f2SGavin Shan struct pnv_phb *phb;
212737c367f2SGavin Shan char name[16];
212837c367f2SGavin Shan
212937c367f2SGavin Shan list_for_each_entry_safe(hose, tmp, &hose_list, list_node) {
213037c367f2SGavin Shan phb = hose->private_data;
213137c367f2SGavin Shan
213237c367f2SGavin Shan sprintf(name, "PCI%04x", hose->global_number);
2133dbf77fedSAneesh Kumar K.V phb->dbgfs = debugfs_create_dir(name, arch_debugfs_dir);
213498b665daSRussell Currey
2135bfa2325eSYueHaibing debugfs_create_file_unsafe("dump_diag_regs", 0200, phb->dbgfs,
213622ba7289SOliver O'Halloran phb, &pnv_pci_diag_data_fops);
213718697d2bSOliver O'Halloran debugfs_create_file_unsafe("dump_ioda_pe_state", 0200, phb->dbgfs,
213818697d2bSOliver O'Halloran phb, &pnv_pci_ioda_pe_dump_fops);
213937c367f2SGavin Shan }
214037c367f2SGavin Shan #endif /* CONFIG_DEBUG_FS */
214137c367f2SGavin Shan }
214237c367f2SGavin Shan
pnv_pci_enable_bridge(struct pci_bus * bus)2143db217319SBenjamin Herrenschmidt static void pnv_pci_enable_bridge(struct pci_bus *bus)
2144db217319SBenjamin Herrenschmidt {
2145db217319SBenjamin Herrenschmidt struct pci_dev *dev = bus->self;
2146db217319SBenjamin Herrenschmidt struct pci_bus *child;
2147db217319SBenjamin Herrenschmidt
2148db217319SBenjamin Herrenschmidt /* Empty bus ? bail */
2149db217319SBenjamin Herrenschmidt if (list_empty(&bus->devices))
2150db217319SBenjamin Herrenschmidt return;
2151db217319SBenjamin Herrenschmidt
2152db217319SBenjamin Herrenschmidt /*
2153db217319SBenjamin Herrenschmidt * If there's a bridge associated with that bus enable it. This works
2154db217319SBenjamin Herrenschmidt * around races in the generic code if the enabling is done during
2155db217319SBenjamin Herrenschmidt * parallel probing. This can be removed once those races have been
2156db217319SBenjamin Herrenschmidt * fixed.
2157db217319SBenjamin Herrenschmidt */
2158db217319SBenjamin Herrenschmidt if (dev) {
2159db217319SBenjamin Herrenschmidt int rc = pci_enable_device(dev);
2160db217319SBenjamin Herrenschmidt if (rc)
2161db217319SBenjamin Herrenschmidt pci_err(dev, "Error enabling bridge (%d)\n", rc);
2162db217319SBenjamin Herrenschmidt pci_set_master(dev);
2163db217319SBenjamin Herrenschmidt }
2164db217319SBenjamin Herrenschmidt
2165db217319SBenjamin Herrenschmidt /* Perform the same to child busses */
2166db217319SBenjamin Herrenschmidt list_for_each_entry(child, &bus->children, node)
2167db217319SBenjamin Herrenschmidt pnv_pci_enable_bridge(child);
2168db217319SBenjamin Herrenschmidt }
2169db217319SBenjamin Herrenschmidt
pnv_pci_enable_bridges(void)2170db217319SBenjamin Herrenschmidt static void pnv_pci_enable_bridges(void)
2171db217319SBenjamin Herrenschmidt {
2172db217319SBenjamin Herrenschmidt struct pci_controller *hose;
2173db217319SBenjamin Herrenschmidt
2174db217319SBenjamin Herrenschmidt list_for_each_entry(hose, &hose_list, list_node)
2175db217319SBenjamin Herrenschmidt pnv_pci_enable_bridge(hose->bus);
2176db217319SBenjamin Herrenschmidt }
2177db217319SBenjamin Herrenschmidt
pnv_pci_ioda_fixup(void)2178cad5cef6SGreg Kroah-Hartman static void pnv_pci_ioda_fixup(void)
2179fb446ad0SGavin Shan {
218037c367f2SGavin Shan pnv_pci_ioda_create_dbgfs();
218137c367f2SGavin Shan
2182db217319SBenjamin Herrenschmidt pnv_pci_enable_bridges();
2183db217319SBenjamin Herrenschmidt
2184e9cc17d4SGavin Shan #ifdef CONFIG_EEH
2185b9fde58dSBenjamin Herrenschmidt pnv_eeh_post_init();
2186e9cc17d4SGavin Shan #endif
2187fb446ad0SGavin Shan }
2188fb446ad0SGavin Shan
2189271fd03aSGavin Shan /*
2190271fd03aSGavin Shan * Returns the alignment for I/O or memory windows for P2P
2191271fd03aSGavin Shan * bridges. That actually depends on how PEs are segmented.
2192271fd03aSGavin Shan * For now, we return I/O or M32 segment size for PE sensitive
2193271fd03aSGavin Shan * P2P bridges. Otherwise, the default values (4KiB for I/O,
2194271fd03aSGavin Shan * 1MiB for memory) will be returned.
2195271fd03aSGavin Shan *
2196271fd03aSGavin Shan * The current PCI bus might be put into one PE, which was
2197271fd03aSGavin Shan * create against the parent PCI bridge. For that case, we
2198271fd03aSGavin Shan * needn't enlarge the alignment so that we can save some
2199271fd03aSGavin Shan * resources.
2200271fd03aSGavin Shan */
pnv_pci_window_alignment(struct pci_bus * bus,unsigned long type)2201271fd03aSGavin Shan static resource_size_t pnv_pci_window_alignment(struct pci_bus *bus,
2202271fd03aSGavin Shan unsigned long type)
2203271fd03aSGavin Shan {
22045609ffddSOliver O'Halloran struct pnv_phb *phb = pci_bus_to_pnvhb(bus);
2205271fd03aSGavin Shan int num_pci_bridges = 0;
22065609ffddSOliver O'Halloran struct pci_dev *bridge;
2207271fd03aSGavin Shan
2208271fd03aSGavin Shan bridge = bus->self;
2209271fd03aSGavin Shan while (bridge) {
2210271fd03aSGavin Shan if (pci_pcie_type(bridge) == PCI_EXP_TYPE_PCI_BRIDGE) {
2211271fd03aSGavin Shan num_pci_bridges++;
2212271fd03aSGavin Shan if (num_pci_bridges >= 2)
2213271fd03aSGavin Shan return 1;
2214271fd03aSGavin Shan }
2215271fd03aSGavin Shan
2216271fd03aSGavin Shan bridge = bridge->bus->self;
2217271fd03aSGavin Shan }
2218271fd03aSGavin Shan
22195958d19aSBenjamin Herrenschmidt /*
22205958d19aSBenjamin Herrenschmidt * We fall back to M32 if M64 isn't supported. We enforce the M64
22215958d19aSBenjamin Herrenschmidt * alignment for any 64-bit resource, PCIe doesn't care and
22225958d19aSBenjamin Herrenschmidt * bridges only do 64-bit prefetchable anyway.
22235958d19aSBenjamin Herrenschmidt */
2224b79331a5SRussell Currey if (phb->ioda.m64_segsize && pnv_pci_is_m64_flags(type))
2225262af557SGuo Chao return phb->ioda.m64_segsize;
2226271fd03aSGavin Shan if (type & IORESOURCE_MEM)
2227271fd03aSGavin Shan return phb->ioda.m32_segsize;
2228271fd03aSGavin Shan
2229271fd03aSGavin Shan return phb->ioda.io_segsize;
2230271fd03aSGavin Shan }
2231271fd03aSGavin Shan
223240e2a47eSGavin Shan /*
223340e2a47eSGavin Shan * We are updating root port or the upstream port of the
223440e2a47eSGavin Shan * bridge behind the root port with PHB's windows in order
223540e2a47eSGavin Shan * to accommodate the changes on required resources during
223640e2a47eSGavin Shan * PCI (slot) hotplug, which is connected to either root
223740e2a47eSGavin Shan * port or the downstream ports of PCIe switch behind the
223840e2a47eSGavin Shan * root port.
223940e2a47eSGavin Shan */
pnv_pci_fixup_bridge_resources(struct pci_bus * bus,unsigned long type)224040e2a47eSGavin Shan static void pnv_pci_fixup_bridge_resources(struct pci_bus *bus,
224140e2a47eSGavin Shan unsigned long type)
224240e2a47eSGavin Shan {
224340e2a47eSGavin Shan struct pci_controller *hose = pci_bus_to_host(bus);
224440e2a47eSGavin Shan struct pnv_phb *phb = hose->private_data;
224540e2a47eSGavin Shan struct pci_dev *bridge = bus->self;
224640e2a47eSGavin Shan struct resource *r, *w;
224740e2a47eSGavin Shan bool msi_region = false;
224840e2a47eSGavin Shan int i;
224940e2a47eSGavin Shan
225040e2a47eSGavin Shan /* Check if we need apply fixup to the bridge's windows */
225140e2a47eSGavin Shan if (!pci_is_root_bus(bridge->bus) &&
225240e2a47eSGavin Shan !pci_is_root_bus(bridge->bus->self->bus))
225340e2a47eSGavin Shan return;
225440e2a47eSGavin Shan
225540e2a47eSGavin Shan /* Fixup the resources */
225640e2a47eSGavin Shan for (i = 0; i < PCI_BRIDGE_RESOURCE_NUM; i++) {
225740e2a47eSGavin Shan r = &bridge->resource[PCI_BRIDGE_RESOURCES + i];
225840e2a47eSGavin Shan if (!r->flags || !r->parent)
225940e2a47eSGavin Shan continue;
226040e2a47eSGavin Shan
226140e2a47eSGavin Shan w = NULL;
226240e2a47eSGavin Shan if (r->flags & type & IORESOURCE_IO)
226340e2a47eSGavin Shan w = &hose->io_resource;
22645958d19aSBenjamin Herrenschmidt else if (pnv_pci_is_m64(phb, r) &&
226540e2a47eSGavin Shan (type & IORESOURCE_PREFETCH) &&
226640e2a47eSGavin Shan phb->ioda.m64_segsize)
226740e2a47eSGavin Shan w = &hose->mem_resources[1];
226840e2a47eSGavin Shan else if (r->flags & type & IORESOURCE_MEM) {
226940e2a47eSGavin Shan w = &hose->mem_resources[0];
227040e2a47eSGavin Shan msi_region = true;
227140e2a47eSGavin Shan }
227240e2a47eSGavin Shan
227340e2a47eSGavin Shan r->start = w->start;
227440e2a47eSGavin Shan r->end = w->end;
227540e2a47eSGavin Shan
227640e2a47eSGavin Shan /* The 64KB 32-bits MSI region shouldn't be included in
227740e2a47eSGavin Shan * the 32-bits bridge window. Otherwise, we can see strange
227840e2a47eSGavin Shan * issues. One of them is EEH error observed on Garrison.
227940e2a47eSGavin Shan *
228040e2a47eSGavin Shan * Exclude top 1MB region which is the minimal alignment of
228140e2a47eSGavin Shan * 32-bits bridge window.
228240e2a47eSGavin Shan */
228340e2a47eSGavin Shan if (msi_region) {
228440e2a47eSGavin Shan r->end += 0x10000;
228540e2a47eSGavin Shan r->end -= 0x100000;
228640e2a47eSGavin Shan }
228740e2a47eSGavin Shan }
228840e2a47eSGavin Shan }
228940e2a47eSGavin Shan
pnv_pci_configure_bus(struct pci_bus * bus)2290dc3d8f85SOliver O'Halloran static void pnv_pci_configure_bus(struct pci_bus *bus)
2291ccd1c191SGavin Shan {
2292ccd1c191SGavin Shan struct pci_dev *bridge = bus->self;
2293ccd1c191SGavin Shan struct pnv_ioda_pe *pe;
2294dc3d8f85SOliver O'Halloran bool all = (bridge && pci_pcie_type(bridge) == PCI_EXP_TYPE_PCI_BRIDGE);
2295ccd1c191SGavin Shan
2296dc3d8f85SOliver O'Halloran dev_info(&bus->dev, "Configuring PE for bus\n");
229740e2a47eSGavin Shan
2298ccd1c191SGavin Shan /* Don't assign PE to PCI bus, which doesn't have subordinate devices */
22996ae8aedfSOliver O'Halloran if (WARN_ON(list_empty(&bus->devices)))
2300ccd1c191SGavin Shan return;
2301ccd1c191SGavin Shan
2302ccd1c191SGavin Shan /* Reserve PEs according to used M64 resources */
2303a25de7afSAlexey Kardashevskiy pnv_ioda_reserve_m64_pe(bus, NULL, all);
2304ccd1c191SGavin Shan
2305ccd1c191SGavin Shan /*
2306ccd1c191SGavin Shan * Assign PE. We might run here because of partial hotplug.
2307ccd1c191SGavin Shan * For the case, we just pick up the existing PE and should
2308ccd1c191SGavin Shan * not allocate resources again.
2309ccd1c191SGavin Shan */
2310ccd1c191SGavin Shan pe = pnv_ioda_setup_bus_PE(bus, all);
2311ccd1c191SGavin Shan if (!pe)
2312ccd1c191SGavin Shan return;
2313ccd1c191SGavin Shan
2314ccd1c191SGavin Shan pnv_ioda_setup_pe_seg(pe);
2315ccd1c191SGavin Shan }
2316ccd1c191SGavin Shan
pnv_pci_default_alignment(void)231738274637SYongji Xie static resource_size_t pnv_pci_default_alignment(void)
231838274637SYongji Xie {
231938274637SYongji Xie return PAGE_SIZE;
232038274637SYongji Xie }
232138274637SYongji Xie
2322184cd4a3SBenjamin Herrenschmidt /* Prevent enabling devices for which we couldn't properly
2323184cd4a3SBenjamin Herrenschmidt * assign a PE
2324184cd4a3SBenjamin Herrenschmidt */
pnv_pci_enable_device_hook(struct pci_dev * dev)23258bf6b91aSAlastair D'Silva static bool pnv_pci_enable_device_hook(struct pci_dev *dev)
2326184cd4a3SBenjamin Herrenschmidt {
2327db1266c8SGavin Shan struct pci_dn *pdn;
2328184cd4a3SBenjamin Herrenschmidt
2329b72c1f65SBenjamin Herrenschmidt pdn = pci_get_pdn(dev);
23306c58b1b4SOliver O'Halloran if (!pdn || pdn->pe_number == IODA_INVALID_PE) {
23316c58b1b4SOliver O'Halloran pci_err(dev, "pci_enable_device() blocked, no PE assigned.\n");
2332c88c2a18SDaniel Axtens return false;
23336c58b1b4SOliver O'Halloran }
2334db1266c8SGavin Shan
2335c88c2a18SDaniel Axtens return true;
2336184cd4a3SBenjamin Herrenschmidt }
2337184cd4a3SBenjamin Herrenschmidt
pnv_ocapi_enable_device_hook(struct pci_dev * dev)2338c1a2feadSFrederic Barrat static bool pnv_ocapi_enable_device_hook(struct pci_dev *dev)
2339c1a2feadSFrederic Barrat {
2340c1a2feadSFrederic Barrat struct pci_dn *pdn;
2341c1a2feadSFrederic Barrat struct pnv_ioda_pe *pe;
2342c1a2feadSFrederic Barrat
2343c1a2feadSFrederic Barrat pdn = pci_get_pdn(dev);
2344c1a2feadSFrederic Barrat if (!pdn)
2345c1a2feadSFrederic Barrat return false;
2346c1a2feadSFrederic Barrat
2347c1a2feadSFrederic Barrat if (pdn->pe_number == IODA_INVALID_PE) {
2348c1a2feadSFrederic Barrat pe = pnv_ioda_setup_dev_PE(dev);
2349c1a2feadSFrederic Barrat if (!pe)
2350c1a2feadSFrederic Barrat return false;
2351c1a2feadSFrederic Barrat }
2352c1a2feadSFrederic Barrat return true;
2353c1a2feadSFrederic Barrat }
2354c1a2feadSFrederic Barrat
pnv_pci_ioda2_release_pe_dma(struct pnv_ioda_pe * pe)235537b59ef0SOliver O'Halloran void pnv_pci_ioda2_release_pe_dma(struct pnv_ioda_pe *pe)
2356c5f7700bSGavin Shan {
2357c5f7700bSGavin Shan struct iommu_table *tbl = pe->table_group.tables[0];
2358c5f7700bSGavin Shan int64_t rc;
2359c5f7700bSGavin Shan
2360e17a7c0eSFrederic Barrat if (!pe->dma_setup_done)
2361c5f7700bSGavin Shan return;
2362c5f7700bSGavin Shan
2363c5f7700bSGavin Shan rc = pnv_pci_ioda2_unset_window(&pe->table_group, 0);
2364c5f7700bSGavin Shan if (rc)
23651e496391SJoe Perches pe_warn(pe, "OPAL error %lld release DMA window\n", rc);
2366c5f7700bSGavin Shan
2367c5f7700bSGavin Shan pnv_pci_ioda2_set_bypass(pe, false);
2368c5f7700bSGavin Shan if (pe->table_group.group) {
2369c5f7700bSGavin Shan iommu_group_put(pe->table_group.group);
2370c5f7700bSGavin Shan WARN_ON(pe->table_group.group);
2371c5f7700bSGavin Shan }
2372c5f7700bSGavin Shan
2373e5afdf9dSAlexey Kardashevskiy iommu_tce_table_put(tbl);
2374c5f7700bSGavin Shan }
2375c5f7700bSGavin Shan
pnv_ioda_free_pe_seg(struct pnv_ioda_pe * pe,unsigned short win,unsigned int * map)2376c5f7700bSGavin Shan static void pnv_ioda_free_pe_seg(struct pnv_ioda_pe *pe,
2377c5f7700bSGavin Shan unsigned short win,
2378c5f7700bSGavin Shan unsigned int *map)
2379c5f7700bSGavin Shan {
2380c5f7700bSGavin Shan struct pnv_phb *phb = pe->phb;
2381c5f7700bSGavin Shan int idx;
2382c5f7700bSGavin Shan int64_t rc;
2383c5f7700bSGavin Shan
2384c5f7700bSGavin Shan for (idx = 0; idx < phb->ioda.total_pe_num; idx++) {
2385c5f7700bSGavin Shan if (map[idx] != pe->pe_number)
2386c5f7700bSGavin Shan continue;
2387c5f7700bSGavin Shan
2388c5f7700bSGavin Shan rc = opal_pci_map_pe_mmio_window(phb->opal_id,
2389c5f7700bSGavin Shan phb->ioda.reserved_pe_idx, win, 0, idx);
2390c5f7700bSGavin Shan
2391c5f7700bSGavin Shan if (rc != OPAL_SUCCESS)
23921e496391SJoe Perches pe_warn(pe, "Error %lld unmapping (%d) segment#%d\n",
2393c5f7700bSGavin Shan rc, win, idx);
2394c5f7700bSGavin Shan
2395c5f7700bSGavin Shan map[idx] = IODA_INVALID_PE;
2396c5f7700bSGavin Shan }
2397c5f7700bSGavin Shan }
2398c5f7700bSGavin Shan
pnv_ioda_release_pe_seg(struct pnv_ioda_pe * pe)2399c5f7700bSGavin Shan static void pnv_ioda_release_pe_seg(struct pnv_ioda_pe *pe)
2400c5f7700bSGavin Shan {
2401c5f7700bSGavin Shan struct pnv_phb *phb = pe->phb;
2402c5f7700bSGavin Shan
24035ac129cdSJoel Stanley if (phb->type == PNV_PHB_IODA2) {
2404c5f7700bSGavin Shan pnv_ioda_free_pe_seg(pe, OPAL_M32_WINDOW_TYPE,
2405c5f7700bSGavin Shan phb->ioda.m32_segmap);
2406c5f7700bSGavin Shan }
2407c5f7700bSGavin Shan }
2408c5f7700bSGavin Shan
pnv_ioda_release_pe(struct pnv_ioda_pe * pe)2409c5f7700bSGavin Shan static void pnv_ioda_release_pe(struct pnv_ioda_pe *pe)
2410c5f7700bSGavin Shan {
2411c5f7700bSGavin Shan struct pnv_phb *phb = pe->phb;
2412c5f7700bSGavin Shan struct pnv_ioda_pe *slave, *tmp;
2413c5f7700bSGavin Shan
2414e5500ab6SOliver O'Halloran pe_info(pe, "Releasing PE\n");
2415e5500ab6SOliver O'Halloran
241680f1ff83SFrederic Barrat mutex_lock(&phb->ioda.pe_list_mutex);
2417c5f7700bSGavin Shan list_del(&pe->list);
241880f1ff83SFrederic Barrat mutex_unlock(&phb->ioda.pe_list_mutex);
241980f1ff83SFrederic Barrat
2420c5f7700bSGavin Shan switch (phb->type) {
2421c5f7700bSGavin Shan case PNV_PHB_IODA2:
2422c5f7700bSGavin Shan pnv_pci_ioda2_release_pe_dma(pe);
2423c5f7700bSGavin Shan break;
2424f724385fSFrederic Barrat case PNV_PHB_NPU_OCAPI:
2425f724385fSFrederic Barrat break;
2426c5f7700bSGavin Shan default:
2427c5f7700bSGavin Shan WARN_ON(1);
2428c5f7700bSGavin Shan }
2429c5f7700bSGavin Shan
2430c5f7700bSGavin Shan pnv_ioda_release_pe_seg(pe);
2431c5f7700bSGavin Shan pnv_ioda_deconfigure_pe(pe->phb, pe);
2432b314427aSGavin Shan
2433b314427aSGavin Shan /* Release slave PEs in the compound PE */
2434b314427aSGavin Shan if (pe->flags & PNV_IODA_PE_MASTER) {
2435b314427aSGavin Shan list_for_each_entry_safe(slave, tmp, &pe->slaves, list) {
2436b314427aSGavin Shan list_del(&slave->list);
2437b314427aSGavin Shan pnv_ioda_free_pe(slave);
2438b314427aSGavin Shan }
2439b314427aSGavin Shan }
2440b314427aSGavin Shan
24416eaed166SGavin Shan /*
24426eaed166SGavin Shan * The PE for root bus can be removed because of hotplug in EEH
24436eaed166SGavin Shan * recovery for fenced PHB error. We need to mark the PE dead so
24446eaed166SGavin Shan * that it can be populated again in PCI hot add path. The PE
24456eaed166SGavin Shan * shouldn't be destroyed as it's the global reserved resource.
24466eaed166SGavin Shan */
2447718d249aSOliver O'Halloran if (phb->ioda.root_pe_idx == pe->pe_number)
2448718d249aSOliver O'Halloran return;
2449718d249aSOliver O'Halloran
2450c5f7700bSGavin Shan pnv_ioda_free_pe(pe);
2451c5f7700bSGavin Shan }
2452c5f7700bSGavin Shan
pnv_pci_release_device(struct pci_dev * pdev)2453c5f7700bSGavin Shan static void pnv_pci_release_device(struct pci_dev *pdev)
2454c5f7700bSGavin Shan {
24555609ffddSOliver O'Halloran struct pnv_phb *phb = pci_bus_to_pnvhb(pdev->bus);
2456c5f7700bSGavin Shan struct pci_dn *pdn = pci_get_pdn(pdev);
2457c5f7700bSGavin Shan struct pnv_ioda_pe *pe;
2458c5f7700bSGavin Shan
245937b59ef0SOliver O'Halloran /* The VF PE state is torn down when sriov_disable() is called */
2460c5f7700bSGavin Shan if (pdev->is_virtfn)
2461c5f7700bSGavin Shan return;
2462c5f7700bSGavin Shan
2463c5f7700bSGavin Shan if (!pdn || pdn->pe_number == IODA_INVALID_PE)
2464c5f7700bSGavin Shan return;
2465c5f7700bSGavin Shan
246637b59ef0SOliver O'Halloran #ifdef CONFIG_PCI_IOV
246737b59ef0SOliver O'Halloran /*
246837b59ef0SOliver O'Halloran * FIXME: Try move this to sriov_disable(). It's here since we allocate
246937b59ef0SOliver O'Halloran * the iov state at probe time since we need to fiddle with the IOV
247037b59ef0SOliver O'Halloran * resources.
247137b59ef0SOliver O'Halloran */
247237b59ef0SOliver O'Halloran if (pdev->is_physfn)
247337b59ef0SOliver O'Halloran kfree(pdev->dev.archdata.iov_data);
247437b59ef0SOliver O'Halloran #endif
247537b59ef0SOliver O'Halloran
247629bf282dSGavin Shan /*
247729bf282dSGavin Shan * PCI hotplug can happen as part of EEH error recovery. The @pdn
247829bf282dSGavin Shan * isn't removed and added afterwards in this scenario. We should
247929bf282dSGavin Shan * set the PE number in @pdn to an invalid one. Otherwise, the PE's
248029bf282dSGavin Shan * device count is decreased on removing devices while failing to
248129bf282dSGavin Shan * be increased on adding devices. It leads to unbalanced PE's device
248229bf282dSGavin Shan * count and eventually make normal PCI hotplug path broken.
248329bf282dSGavin Shan */
2484c5f7700bSGavin Shan pe = &phb->ioda.pe_array[pdn->pe_number];
248529bf282dSGavin Shan pdn->pe_number = IODA_INVALID_PE;
248629bf282dSGavin Shan
2487c5f7700bSGavin Shan WARN_ON(--pe->device_count < 0);
2488c5f7700bSGavin Shan if (pe->device_count == 0)
2489c5f7700bSGavin Shan pnv_ioda_release_pe(pe);
2490c5f7700bSGavin Shan }
2491c5f7700bSGavin Shan
pnv_pci_ioda_shutdown(struct pci_controller * hose)24927a8e6bbfSMichael Neuling static void pnv_pci_ioda_shutdown(struct pci_controller *hose)
249373ed148aSBenjamin Herrenschmidt {
24947a8e6bbfSMichael Neuling struct pnv_phb *phb = hose->private_data;
24957a8e6bbfSMichael Neuling
2496d1a85eeeSGavin Shan opal_pci_reset(phb->opal_id, OPAL_RESET_PCI_IODA_TABLE,
249773ed148aSBenjamin Herrenschmidt OPAL_ASSERT_RESET);
249873ed148aSBenjamin Herrenschmidt }
249973ed148aSBenjamin Herrenschmidt
pnv_pci_ioda_dma_bus_setup(struct pci_bus * bus)2500946743d0SOliver O'Halloran static void pnv_pci_ioda_dma_bus_setup(struct pci_bus *bus)
2501946743d0SOliver O'Halloran {
25025609ffddSOliver O'Halloran struct pnv_phb *phb = pci_bus_to_pnvhb(bus);
2503946743d0SOliver O'Halloran struct pnv_ioda_pe *pe;
2504946743d0SOliver O'Halloran
2505946743d0SOliver O'Halloran list_for_each_entry(pe, &phb->ioda.pe_list, list) {
2506946743d0SOliver O'Halloran if (!(pe->flags & (PNV_IODA_PE_BUS | PNV_IODA_PE_BUS_ALL)))
2507946743d0SOliver O'Halloran continue;
2508946743d0SOliver O'Halloran
2509946743d0SOliver O'Halloran if (!pe->pbus)
2510946743d0SOliver O'Halloran continue;
2511946743d0SOliver O'Halloran
2512946743d0SOliver O'Halloran if (bus->number == ((pe->rid >> 8) & 0xFF)) {
2513946743d0SOliver O'Halloran pe->pbus = bus;
2514946743d0SOliver O'Halloran break;
2515946743d0SOliver O'Halloran }
2516946743d0SOliver O'Halloran }
2517946743d0SOliver O'Halloran }
2518946743d0SOliver O'Halloran
2519a9409044SAlexey Kardashevskiy #ifdef CONFIG_IOMMU_API
pnv_pci_device_group(struct pci_controller * hose,struct pci_dev * pdev)2520a9409044SAlexey Kardashevskiy static struct iommu_group *pnv_pci_device_group(struct pci_controller *hose,
2521a9409044SAlexey Kardashevskiy struct pci_dev *pdev)
2522a9409044SAlexey Kardashevskiy {
2523a9409044SAlexey Kardashevskiy struct pnv_phb *phb = hose->private_data;
2524a9409044SAlexey Kardashevskiy struct pnv_ioda_pe *pe;
2525a9409044SAlexey Kardashevskiy
2526a9409044SAlexey Kardashevskiy if (WARN_ON(!phb))
2527a9409044SAlexey Kardashevskiy return ERR_PTR(-ENODEV);
2528a9409044SAlexey Kardashevskiy
2529*fe8aa8e3SXiongfeng Wang pe = pnv_pci_bdfn_to_pe(phb, pci_dev_id(pdev));
2530a9409044SAlexey Kardashevskiy if (!pe)
2531a9409044SAlexey Kardashevskiy return ERR_PTR(-ENODEV);
2532a9409044SAlexey Kardashevskiy
2533a9409044SAlexey Kardashevskiy if (!pe->table_group.group)
2534a9409044SAlexey Kardashevskiy return ERR_PTR(-ENODEV);
2535a9409044SAlexey Kardashevskiy
2536a9409044SAlexey Kardashevskiy return iommu_group_ref_get(pe->table_group.group);
2537a9409044SAlexey Kardashevskiy }
2538a9409044SAlexey Kardashevskiy #endif
2539a9409044SAlexey Kardashevskiy
254092ae0353SDaniel Axtens static const struct pci_controller_ops pnv_pci_ioda_controller_ops = {
25410a25d9c4SOliver O'Halloran .dma_dev_setup = pnv_pci_ioda_dma_dev_setup,
2542946743d0SOliver O'Halloran .dma_bus_setup = pnv_pci_ioda_dma_bus_setup,
25432d6ad41bSChristoph Hellwig .iommu_bypass_supported = pnv_pci_ioda_iommu_bypass_supported,
254492ae0353SDaniel Axtens .enable_device_hook = pnv_pci_enable_device_hook,
2545c5f7700bSGavin Shan .release_device = pnv_pci_release_device,
254692ae0353SDaniel Axtens .window_alignment = pnv_pci_window_alignment,
2547dc3d8f85SOliver O'Halloran .setup_bridge = pnv_pci_fixup_bridge_resources,
254892ae0353SDaniel Axtens .reset_secondary_bus = pnv_pci_reset_secondary_bus,
25497a8e6bbfSMichael Neuling .shutdown = pnv_pci_ioda_shutdown,
2550a9409044SAlexey Kardashevskiy #ifdef CONFIG_IOMMU_API
2551a9409044SAlexey Kardashevskiy .device_group = pnv_pci_device_group,
2552a9409044SAlexey Kardashevskiy #endif
255392ae0353SDaniel Axtens };
255492ae0353SDaniel Axtens
25557f2c39e9SFrederic Barrat static const struct pci_controller_ops pnv_npu_ocapi_ioda_controller_ops = {
2556c1a2feadSFrederic Barrat .enable_device_hook = pnv_ocapi_enable_device_hook,
2557f724385fSFrederic Barrat .release_device = pnv_pci_release_device,
25587f2c39e9SFrederic Barrat .window_alignment = pnv_pci_window_alignment,
25597f2c39e9SFrederic Barrat .reset_secondary_bus = pnv_pci_reset_secondary_bus,
25607f2c39e9SFrederic Barrat .shutdown = pnv_pci_ioda_shutdown,
25617f2c39e9SFrederic Barrat };
25627f2c39e9SFrederic Barrat
pnv_pci_init_ioda_phb(struct device_node * np,u64 hub_id,int ioda_type)2563e51df2c1SAnton Blanchard static void __init pnv_pci_init_ioda_phb(struct device_node *np,
2564e9cc17d4SGavin Shan u64 hub_id, int ioda_type)
2565184cd4a3SBenjamin Herrenschmidt {
2566184cd4a3SBenjamin Herrenschmidt struct pci_controller *hose;
2567184cd4a3SBenjamin Herrenschmidt struct pnv_phb *phb;
25682b923ed1SGavin Shan unsigned long size, m64map_off, m32map_off, pemap_off;
2569718d249aSOliver O'Halloran struct pnv_ioda_pe *root_pe;
2570fd141d1aSBenjamin Herrenschmidt struct resource r;
2571c681b93cSAlistair Popple const __be64 *prop64;
25723a1a4661SBenjamin Herrenschmidt const __be32 *prop32;
2573f1b7cc3eSGavin Shan int len;
25743fa23ff8SGavin Shan unsigned int segno;
2575184cd4a3SBenjamin Herrenschmidt u64 phb_id;
2576184cd4a3SBenjamin Herrenschmidt void *aux;
2577184cd4a3SBenjamin Herrenschmidt long rc;
2578184cd4a3SBenjamin Herrenschmidt
257908a45b32SBenjamin Herrenschmidt if (!of_device_is_available(np))
258008a45b32SBenjamin Herrenschmidt return;
258108a45b32SBenjamin Herrenschmidt
2582b7c670d6SRob Herring pr_info("Initializing %s PHB (%pOF)\n", pnv_phb_names[ioda_type], np);
2583184cd4a3SBenjamin Herrenschmidt
2584184cd4a3SBenjamin Herrenschmidt prop64 = of_get_property(np, "ibm,opal-phbid", NULL);
2585184cd4a3SBenjamin Herrenschmidt if (!prop64) {
2586184cd4a3SBenjamin Herrenschmidt pr_err(" Missing \"ibm,opal-phbid\" property !\n");
2587184cd4a3SBenjamin Herrenschmidt return;
2588184cd4a3SBenjamin Herrenschmidt }
2589184cd4a3SBenjamin Herrenschmidt phb_id = be64_to_cpup(prop64);
2590184cd4a3SBenjamin Herrenschmidt pr_debug(" PHB-ID : 0x%016llx\n", phb_id);
2591184cd4a3SBenjamin Herrenschmidt
2592dea6f4c6SMichael Ellerman phb = kzalloc(sizeof(*phb), GFP_KERNEL);
25938a7f97b9SMike Rapoport if (!phb)
25948a7f97b9SMike Rapoport panic("%s: Failed to allocate %zu bytes\n", __func__,
25958a7f97b9SMike Rapoport sizeof(*phb));
259658d714ecSGavin Shan
259758d714ecSGavin Shan /* Allocate PCI controller */
2598184cd4a3SBenjamin Herrenschmidt phb->hose = hose = pcibios_alloc_controller(np);
259958d714ecSGavin Shan if (!phb->hose) {
2600b7c670d6SRob Herring pr_err(" Can't allocate PCI controller for %pOF\n",
2601b7c670d6SRob Herring np);
26024421cca0SMike Rapoport memblock_free(phb, sizeof(struct pnv_phb));
2603184cd4a3SBenjamin Herrenschmidt return;
2604184cd4a3SBenjamin Herrenschmidt }
2605184cd4a3SBenjamin Herrenschmidt
2606184cd4a3SBenjamin Herrenschmidt spin_lock_init(&phb->lock);
2607f1b7cc3eSGavin Shan prop32 = of_get_property(np, "bus-range", &len);
2608f1b7cc3eSGavin Shan if (prop32 && len == 8) {
26093a1a4661SBenjamin Herrenschmidt hose->first_busno = be32_to_cpu(prop32[0]);
26103a1a4661SBenjamin Herrenschmidt hose->last_busno = be32_to_cpu(prop32[1]);
2611f1b7cc3eSGavin Shan } else {
2612b7c670d6SRob Herring pr_warn(" Broken <bus-range> on %pOF\n", np);
2613184cd4a3SBenjamin Herrenschmidt hose->first_busno = 0;
2614184cd4a3SBenjamin Herrenschmidt hose->last_busno = 0xff;
2615f1b7cc3eSGavin Shan }
2616184cd4a3SBenjamin Herrenschmidt hose->private_data = phb;
2617e9cc17d4SGavin Shan phb->hub_id = hub_id;
2618184cd4a3SBenjamin Herrenschmidt phb->opal_id = phb_id;
2619aa0c033fSGavin Shan phb->type = ioda_type;
2620781a868fSWei Yang mutex_init(&phb->ioda.pe_alloc_mutex);
2621184cd4a3SBenjamin Herrenschmidt
2622cee72d5bSBenjamin Herrenschmidt /* Detect specific models for error handling */
2623cee72d5bSBenjamin Herrenschmidt if (of_device_is_compatible(np, "ibm,p7ioc-pciex"))
2624cee72d5bSBenjamin Herrenschmidt phb->model = PNV_PHB_MODEL_P7IOC;
2625f3d40c25SBenjamin Herrenschmidt else if (of_device_is_compatible(np, "ibm,power8-pciex"))
2626aa0c033fSGavin Shan phb->model = PNV_PHB_MODEL_PHB3;
2627cee72d5bSBenjamin Herrenschmidt else
2628cee72d5bSBenjamin Herrenschmidt phb->model = PNV_PHB_MODEL_UNKNOWN;
2629cee72d5bSBenjamin Herrenschmidt
26305cb1f8fdSRussell Currey /* Initialize diagnostic data buffer */
26315cb1f8fdSRussell Currey prop32 = of_get_property(np, "ibm,phb-diag-data-size", NULL);
26325cb1f8fdSRussell Currey if (prop32)
26335cb1f8fdSRussell Currey phb->diag_data_size = be32_to_cpup(prop32);
26345cb1f8fdSRussell Currey else
26355cb1f8fdSRussell Currey phb->diag_data_size = PNV_PCI_DIAG_BUF_SIZE;
26365cb1f8fdSRussell Currey
2637dea6f4c6SMichael Ellerman phb->diag_data = kzalloc(phb->diag_data_size, GFP_KERNEL);
26388a7f97b9SMike Rapoport if (!phb->diag_data)
26398a7f97b9SMike Rapoport panic("%s: Failed to allocate %u bytes\n", __func__,
26408a7f97b9SMike Rapoport phb->diag_data_size);
26415cb1f8fdSRussell Currey
2642aa0c033fSGavin Shan /* Parse 32-bit and IO ranges (if any) */
26432f1ec02eSGavin Shan pci_process_bridge_OF_ranges(hose, np, !hose->global_number);
2644184cd4a3SBenjamin Herrenschmidt
2645aa0c033fSGavin Shan /* Get registers */
2646fd141d1aSBenjamin Herrenschmidt if (!of_address_to_resource(np, 0, &r)) {
2647fd141d1aSBenjamin Herrenschmidt phb->regs_phys = r.start;
2648fd141d1aSBenjamin Herrenschmidt phb->regs = ioremap(r.start, resource_size(&r));
2649184cd4a3SBenjamin Herrenschmidt if (phb->regs == NULL)
2650184cd4a3SBenjamin Herrenschmidt pr_err(" Failed to map registers !\n");
2651fd141d1aSBenjamin Herrenschmidt }
2652577c8c88SGavin Shan
2653184cd4a3SBenjamin Herrenschmidt /* Initialize more IODA stuff */
265492b8f137SGavin Shan phb->ioda.total_pe_num = 1;
265536954dc7SGavin Shan prop32 = of_get_property(np, "ibm,opal-num-pes", NULL);
265636954dc7SGavin Shan if (prop32)
265792b8f137SGavin Shan phb->ioda.total_pe_num = be32_to_cpup(prop32);
265836954dc7SGavin Shan prop32 = of_get_property(np, "ibm,opal-reserved-pe", NULL);
265936954dc7SGavin Shan if (prop32)
266092b8f137SGavin Shan phb->ioda.reserved_pe_idx = be32_to_cpup(prop32);
2661262af557SGuo Chao
2662c127562aSGavin Shan /* Invalidate RID to PE# mapping */
2663c127562aSGavin Shan for (segno = 0; segno < ARRAY_SIZE(phb->ioda.pe_rmap); segno++)
2664c127562aSGavin Shan phb->ioda.pe_rmap[segno] = IODA_INVALID_PE;
2665c127562aSGavin Shan
2666262af557SGuo Chao /* Parse 64-bit MMIO range */
2667262af557SGuo Chao pnv_ioda_parse_m64_window(phb);
2668262af557SGuo Chao
2669184cd4a3SBenjamin Herrenschmidt phb->ioda.m32_size = resource_size(&hose->mem_resources[0]);
2670aa0c033fSGavin Shan /* FW Has already off top 64k of M32 space (MSI space) */
2671184cd4a3SBenjamin Herrenschmidt phb->ioda.m32_size += 0x10000;
2672184cd4a3SBenjamin Herrenschmidt
267392b8f137SGavin Shan phb->ioda.m32_segsize = phb->ioda.m32_size / phb->ioda.total_pe_num;
26743fd47f06SBenjamin Herrenschmidt phb->ioda.m32_pci_base = hose->mem_resources[0].start - hose->mem_offset[0];
2675184cd4a3SBenjamin Herrenschmidt phb->ioda.io_size = hose->pci_io_size;
267692b8f137SGavin Shan phb->ioda.io_segsize = phb->ioda.io_size / phb->ioda.total_pe_num;
2677184cd4a3SBenjamin Herrenschmidt phb->ioda.io_pci_base = 0; /* XXX calculate this ? */
2678184cd4a3SBenjamin Herrenschmidt
2679c35d2a8cSGavin Shan /* Allocate aux data & arrays. We don't have IO ports on PHB3 */
2680b7115316SChristophe Leroy size = ALIGN(max_t(unsigned, phb->ioda.total_pe_num, 8) / 8,
268192a86756SAlexey Kardashevskiy sizeof(unsigned long));
268293289d8cSGavin Shan m64map_off = size;
268393289d8cSGavin Shan size += phb->ioda.total_pe_num * sizeof(phb->ioda.m64_segmap[0]);
2684184cd4a3SBenjamin Herrenschmidt m32map_off = size;
268592b8f137SGavin Shan size += phb->ioda.total_pe_num * sizeof(phb->ioda.m32_segmap[0]);
2686184cd4a3SBenjamin Herrenschmidt pemap_off = size;
268792b8f137SGavin Shan size += phb->ioda.total_pe_num * sizeof(struct pnv_ioda_pe);
2688dea6f4c6SMichael Ellerman aux = kzalloc(size, GFP_KERNEL);
26898a7f97b9SMike Rapoport if (!aux)
26908a7f97b9SMike Rapoport panic("%s: Failed to allocate %lu bytes\n", __func__, size);
2691fbbefb32SOliver O'Halloran
2692184cd4a3SBenjamin Herrenschmidt phb->ioda.pe_alloc = aux;
269393289d8cSGavin Shan phb->ioda.m64_segmap = aux + m64map_off;
2694184cd4a3SBenjamin Herrenschmidt phb->ioda.m32_segmap = aux + m32map_off;
269593289d8cSGavin Shan for (segno = 0; segno < phb->ioda.total_pe_num; segno++) {
269693289d8cSGavin Shan phb->ioda.m64_segmap[segno] = IODA_INVALID_PE;
26973fa23ff8SGavin Shan phb->ioda.m32_segmap[segno] = IODA_INVALID_PE;
269893289d8cSGavin Shan }
2699184cd4a3SBenjamin Herrenschmidt phb->ioda.pe_array = aux + pemap_off;
270063803c39SGavin Shan
270163803c39SGavin Shan /*
270263803c39SGavin Shan * Choose PE number for root bus, which shouldn't have
270363803c39SGavin Shan * M64 resources consumed by its child devices. To pick
270463803c39SGavin Shan * the PE number adjacent to the reserved one if possible.
270563803c39SGavin Shan */
270663803c39SGavin Shan pnv_ioda_reserve_pe(phb, phb->ioda.reserved_pe_idx);
270763803c39SGavin Shan if (phb->ioda.reserved_pe_idx == 0) {
270863803c39SGavin Shan phb->ioda.root_pe_idx = 1;
270963803c39SGavin Shan pnv_ioda_reserve_pe(phb, phb->ioda.root_pe_idx);
271063803c39SGavin Shan } else if (phb->ioda.reserved_pe_idx == (phb->ioda.total_pe_num - 1)) {
271163803c39SGavin Shan phb->ioda.root_pe_idx = phb->ioda.reserved_pe_idx - 1;
271263803c39SGavin Shan pnv_ioda_reserve_pe(phb, phb->ioda.root_pe_idx);
271363803c39SGavin Shan } else {
2714718d249aSOliver O'Halloran /* otherwise just allocate one */
2715a4bc676eSOliver O'Halloran root_pe = pnv_ioda_alloc_pe(phb, 1);
2716718d249aSOliver O'Halloran phb->ioda.root_pe_idx = root_pe->pe_number;
271763803c39SGavin Shan }
2718184cd4a3SBenjamin Herrenschmidt
2719184cd4a3SBenjamin Herrenschmidt INIT_LIST_HEAD(&phb->ioda.pe_list);
2720781a868fSWei Yang mutex_init(&phb->ioda.pe_list_mutex);
2721184cd4a3SBenjamin Herrenschmidt
2722aa0c033fSGavin Shan #if 0 /* We should really do that ... */
2723184cd4a3SBenjamin Herrenschmidt rc = opal_pci_set_phb_mem_window(opal->phb_id,
2724184cd4a3SBenjamin Herrenschmidt window_type,
2725184cd4a3SBenjamin Herrenschmidt window_num,
2726184cd4a3SBenjamin Herrenschmidt starting_real_address,
2727184cd4a3SBenjamin Herrenschmidt starting_pci_address,
2728184cd4a3SBenjamin Herrenschmidt segment_size);
2729184cd4a3SBenjamin Herrenschmidt #endif
2730184cd4a3SBenjamin Herrenschmidt
2731262af557SGuo Chao pr_info(" %03d (%03d) PE's M32: 0x%x [segment=0x%x]\n",
273292b8f137SGavin Shan phb->ioda.total_pe_num, phb->ioda.reserved_pe_idx,
2733262af557SGuo Chao phb->ioda.m32_size, phb->ioda.m32_segsize);
2734262af557SGuo Chao if (phb->ioda.m64_size)
2735262af557SGuo Chao pr_info(" M64: 0x%lx [segment=0x%lx]\n",
2736262af557SGuo Chao phb->ioda.m64_size, phb->ioda.m64_segsize);
2737262af557SGuo Chao if (phb->ioda.io_size)
2738262af557SGuo Chao pr_info(" IO: 0x%x [segment=0x%x]\n",
2739184cd4a3SBenjamin Herrenschmidt phb->ioda.io_size, phb->ioda.io_segsize);
2740184cd4a3SBenjamin Herrenschmidt
2741262af557SGuo Chao
2742184cd4a3SBenjamin Herrenschmidt phb->hose->ops = &pnv_pci_ops;
274349dec922SGavin Shan phb->get_pe_state = pnv_ioda_get_pe_state;
274449dec922SGavin Shan phb->freeze_pe = pnv_ioda_freeze_pe;
274549dec922SGavin Shan phb->unfreeze_pe = pnv_ioda_unfreeze_pe;
2746184cd4a3SBenjamin Herrenschmidt
2747184cd4a3SBenjamin Herrenschmidt /* Setup MSI support */
2748184cd4a3SBenjamin Herrenschmidt pnv_pci_init_ioda_msis(phb);
2749184cd4a3SBenjamin Herrenschmidt
2750c40a4210SGavin Shan /*
2751c40a4210SGavin Shan * We pass the PCI probe flag PCI_REASSIGN_ALL_RSRC here
2752c40a4210SGavin Shan * to let the PCI core do resource assignment. It's supposed
2753c40a4210SGavin Shan * that the PCI core will do correct I/O and MMIO alignment
2754c40a4210SGavin Shan * for the P2P bridge bars so that each PCI bus (excluding
2755c40a4210SGavin Shan * the child P2P bridges) can form individual PE.
2756184cd4a3SBenjamin Herrenschmidt */
2757fb446ad0SGavin Shan ppc_md.pcibios_fixup = pnv_pci_ioda_fixup;
27585d2aa710SAlistair Popple
27597f2c39e9SFrederic Barrat switch (phb->type) {
27607f2c39e9SFrederic Barrat case PNV_PHB_NPU_OCAPI:
27617f2c39e9SFrederic Barrat hose->controller_ops = pnv_npu_ocapi_ioda_controller_ops;
27627f2c39e9SFrederic Barrat break;
27637f2c39e9SFrederic Barrat default:
276492ae0353SDaniel Axtens hose->controller_ops = pnv_pci_ioda_controller_ops;
2765f9f83456SAlexey Kardashevskiy }
2766ad30cb99SMichael Ellerman
276738274637SYongji Xie ppc_md.pcibios_default_alignment = pnv_pci_default_alignment;
276838274637SYongji Xie
27696e628c7dSWei Yang #ifdef CONFIG_PCI_IOV
2770965c94f3SOliver O'Halloran ppc_md.pcibios_fixup_sriov = pnv_pci_ioda_fixup_iov;
27715350ab3fSWei Yang ppc_md.pcibios_iov_resource_alignment = pnv_pci_iov_resource_alignment;
2772988fc3baSBryant G. Ly ppc_md.pcibios_sriov_enable = pnv_pcibios_sriov_enable;
2773988fc3baSBryant G. Ly ppc_md.pcibios_sriov_disable = pnv_pcibios_sriov_disable;
2774ad30cb99SMichael Ellerman #endif
2775ad30cb99SMichael Ellerman
2776c40a4210SGavin Shan pci_add_flags(PCI_REASSIGN_ALL_RSRC);
2777184cd4a3SBenjamin Herrenschmidt
2778184cd4a3SBenjamin Herrenschmidt /* Reset IODA tables to a clean state */
2779d1a85eeeSGavin Shan rc = opal_pci_reset(phb_id, OPAL_RESET_PCI_IODA_TABLE, OPAL_ASSERT_RESET);
2780184cd4a3SBenjamin Herrenschmidt if (rc)
2781f2c2cbccSJoe Perches pr_warn(" OPAL Error %ld performing IODA table reset !\n", rc);
2782361f2a2aSGavin Shan
27836060e9eaSAndrew Donnellan /*
27846060e9eaSAndrew Donnellan * If we're running in kdump kernel, the previous kernel never
2785361f2a2aSGavin Shan * shutdown PCI devices correctly. We already got IODA table
2786361f2a2aSGavin Shan * cleaned out. So we have to issue PHB reset to stop all PCI
278745baee14SGuilherme G. Piccoli * transactions from previous kernel. The ppc_pci_reset_phbs
2788b174b4fbSOliver O'Halloran * kernel parameter will force this reset too. Additionally,
2789b174b4fbSOliver O'Halloran * if the IODA reset above failed then use a bigger hammer.
2790b174b4fbSOliver O'Halloran * This can happen if we get a PHB fatal error in very early
2791b174b4fbSOliver O'Halloran * boot.
2792361f2a2aSGavin Shan */
2793b174b4fbSOliver O'Halloran if (is_kdump_kernel() || pci_reset_phbs || rc) {
2794361f2a2aSGavin Shan pr_info(" Issue PHB reset ...\n");
2795cadf364dSGavin Shan pnv_eeh_phb_reset(hose, EEH_RESET_FUNDAMENTAL);
2796cadf364dSGavin Shan pnv_eeh_phb_reset(hose, EEH_RESET_DEACTIVATE);
2797361f2a2aSGavin Shan }
2798262af557SGuo Chao
27999e9e8935SGavin Shan /* Remove M64 resource if we can't configure it successfully */
28009e9e8935SGavin Shan if (!phb->init_m64 || phb->init_m64(phb))
2801262af557SGuo Chao hose->mem_resources[1].flags = 0;
2802fbbefb32SOliver O'Halloran
2803fbbefb32SOliver O'Halloran /* create pci_dn's for DT nodes under this PHB */
2804fbbefb32SOliver O'Halloran pci_devs_phb_init_dynamic(hose);
2805184cd4a3SBenjamin Herrenschmidt }
2806184cd4a3SBenjamin Herrenschmidt
pnv_pci_init_ioda2_phb(struct device_node * np)280767975005SBjorn Helgaas void __init pnv_pci_init_ioda2_phb(struct device_node *np)
2808aa0c033fSGavin Shan {
2809e9cc17d4SGavin Shan pnv_pci_init_ioda_phb(np, 0, PNV_PHB_IODA2);
2810aa0c033fSGavin Shan }
2811aa0c033fSGavin Shan
pnv_pci_init_npu2_opencapi_phb(struct device_node * np)28127f2c39e9SFrederic Barrat void __init pnv_pci_init_npu2_opencapi_phb(struct device_node *np)
28137f2c39e9SFrederic Barrat {
28147f2c39e9SFrederic Barrat pnv_pci_init_ioda_phb(np, 0, PNV_PHB_NPU_OCAPI);
28155d2aa710SAlistair Popple }
28165d2aa710SAlistair Popple
pnv_npu2_opencapi_cfg_size_fixup(struct pci_dev * dev)2817228c2f41SAndrew Donnellan static void pnv_npu2_opencapi_cfg_size_fixup(struct pci_dev *dev)
2818228c2f41SAndrew Donnellan {
28195609ffddSOliver O'Halloran struct pnv_phb *phb = pci_bus_to_pnvhb(dev->bus);
2820228c2f41SAndrew Donnellan
2821228c2f41SAndrew Donnellan if (!machine_is(powernv))
2822228c2f41SAndrew Donnellan return;
2823228c2f41SAndrew Donnellan
2824228c2f41SAndrew Donnellan if (phb->type == PNV_PHB_NPU_OCAPI)
2825228c2f41SAndrew Donnellan dev->cfg_size = PCI_CFG_SPACE_EXP_SIZE;
2826228c2f41SAndrew Donnellan }
2827228c2f41SAndrew Donnellan DECLARE_PCI_FIXUP_EARLY(PCI_ANY_ID, PCI_ANY_ID, pnv_npu2_opencapi_cfg_size_fixup);
2828