1184cd4a3SBenjamin Herrenschmidt /* 2184cd4a3SBenjamin Herrenschmidt * Support PCI/PCIe on PowerNV platforms 3184cd4a3SBenjamin Herrenschmidt * 4184cd4a3SBenjamin Herrenschmidt * Copyright 2011 Benjamin Herrenschmidt, IBM Corp. 5184cd4a3SBenjamin Herrenschmidt * 6184cd4a3SBenjamin Herrenschmidt * This program is free software; you can redistribute it and/or 7184cd4a3SBenjamin Herrenschmidt * modify it under the terms of the GNU General Public License 8184cd4a3SBenjamin Herrenschmidt * as published by the Free Software Foundation; either version 9184cd4a3SBenjamin Herrenschmidt * 2 of the License, or (at your option) any later version. 10184cd4a3SBenjamin Herrenschmidt */ 11184cd4a3SBenjamin Herrenschmidt 12cee72d5bSBenjamin Herrenschmidt #undef DEBUG 13184cd4a3SBenjamin Herrenschmidt 14184cd4a3SBenjamin Herrenschmidt #include <linux/kernel.h> 15184cd4a3SBenjamin Herrenschmidt #include <linux/pci.h> 16361f2a2aSGavin Shan #include <linux/crash_dump.h> 1737c367f2SGavin Shan #include <linux/debugfs.h> 18184cd4a3SBenjamin Herrenschmidt #include <linux/delay.h> 19184cd4a3SBenjamin Herrenschmidt #include <linux/string.h> 20184cd4a3SBenjamin Herrenschmidt #include <linux/init.h> 21184cd4a3SBenjamin Herrenschmidt #include <linux/bootmem.h> 22184cd4a3SBenjamin Herrenschmidt #include <linux/irq.h> 23184cd4a3SBenjamin Herrenschmidt #include <linux/io.h> 24184cd4a3SBenjamin Herrenschmidt #include <linux/msi.h> 25cd15b048SBenjamin Herrenschmidt #include <linux/memblock.h> 26ac9a5889SAlexey Kardashevskiy #include <linux/iommu.h> 27e57080f1SAlexey Kardashevskiy #include <linux/rculist.h> 284793d65dSAlexey Kardashevskiy #include <linux/sizes.h> 29184cd4a3SBenjamin Herrenschmidt 30184cd4a3SBenjamin Herrenschmidt #include <asm/sections.h> 31184cd4a3SBenjamin Herrenschmidt #include <asm/io.h> 32184cd4a3SBenjamin Herrenschmidt #include <asm/prom.h> 33184cd4a3SBenjamin Herrenschmidt #include <asm/pci-bridge.h> 34184cd4a3SBenjamin Herrenschmidt #include <asm/machdep.h> 35fb1b55d6SGavin Shan #include <asm/msi_bitmap.h> 36184cd4a3SBenjamin Herrenschmidt #include <asm/ppc-pci.h> 37184cd4a3SBenjamin Herrenschmidt #include <asm/opal.h> 38184cd4a3SBenjamin Herrenschmidt #include <asm/iommu.h> 39184cd4a3SBenjamin Herrenschmidt #include <asm/tce.h> 40137436c9SGavin Shan #include <asm/xics.h> 4137c367f2SGavin Shan #include <asm/debug.h> 42262af557SGuo Chao #include <asm/firmware.h> 4380c49c7eSIan Munsie #include <asm/pnv-pci.h> 44aca6913fSAlexey Kardashevskiy #include <asm/mmzone.h> 4580c49c7eSIan Munsie 46ec249dd8SMichael Neuling #include <misc/cxl-base.h> 47184cd4a3SBenjamin Herrenschmidt 48184cd4a3SBenjamin Herrenschmidt #include "powernv.h" 49184cd4a3SBenjamin Herrenschmidt #include "pci.h" 50184cd4a3SBenjamin Herrenschmidt 5199451551SGavin Shan #define PNV_IODA1_M64_NUM 16 /* Number of M64 BARs */ 5299451551SGavin Shan #define PNV_IODA1_M64_SEGS 8 /* Segments per M64 BAR */ 53acce971cSGavin Shan #define PNV_IODA1_DMA32_SEGSIZE 0x10000000 54781a868fSWei Yang 55bbb845c4SAlexey Kardashevskiy #define POWERNV_IOMMU_DEFAULT_LEVELS 1 56bbb845c4SAlexey Kardashevskiy #define POWERNV_IOMMU_MAX_LEVELS 5 57bbb845c4SAlexey Kardashevskiy 589497a1c1SGavin Shan static const char * const pnv_phb_names[] = { "IODA1", "IODA2", "NPU" }; 59aca6913fSAlexey Kardashevskiy static void pnv_pci_ioda2_table_free_pages(struct iommu_table *tbl); 60aca6913fSAlexey Kardashevskiy 617d623e42SAlexey Kardashevskiy void pe_level_printk(const struct pnv_ioda_pe *pe, const char *level, 626d31c2faSJoe Perches const char *fmt, ...) 636d31c2faSJoe Perches { 646d31c2faSJoe Perches struct va_format vaf; 656d31c2faSJoe Perches va_list args; 666d31c2faSJoe Perches char pfix[32]; 67184cd4a3SBenjamin Herrenschmidt 686d31c2faSJoe Perches va_start(args, fmt); 696d31c2faSJoe Perches 706d31c2faSJoe Perches vaf.fmt = fmt; 716d31c2faSJoe Perches vaf.va = &args; 726d31c2faSJoe Perches 73781a868fSWei Yang if (pe->flags & PNV_IODA_PE_DEV) 746d31c2faSJoe Perches strlcpy(pfix, dev_name(&pe->pdev->dev), sizeof(pfix)); 75781a868fSWei Yang else if (pe->flags & (PNV_IODA_PE_BUS | PNV_IODA_PE_BUS_ALL)) 766d31c2faSJoe Perches sprintf(pfix, "%04x:%02x ", 776d31c2faSJoe Perches pci_domain_nr(pe->pbus), pe->pbus->number); 78781a868fSWei Yang #ifdef CONFIG_PCI_IOV 79781a868fSWei Yang else if (pe->flags & PNV_IODA_PE_VF) 80781a868fSWei Yang sprintf(pfix, "%04x:%02x:%2x.%d", 81781a868fSWei Yang pci_domain_nr(pe->parent_dev->bus), 82781a868fSWei Yang (pe->rid & 0xff00) >> 8, 83781a868fSWei Yang PCI_SLOT(pe->rid), PCI_FUNC(pe->rid)); 84781a868fSWei Yang #endif /* CONFIG_PCI_IOV*/ 856d31c2faSJoe Perches 866d31c2faSJoe Perches printk("%spci %s: [PE# %.3d] %pV", 876d31c2faSJoe Perches level, pfix, pe->pe_number, &vaf); 886d31c2faSJoe Perches 896d31c2faSJoe Perches va_end(args); 906d31c2faSJoe Perches } 916d31c2faSJoe Perches 924e287840SThadeu Lima de Souza Cascardo static bool pnv_iommu_bypass_disabled __read_mostly; 934e287840SThadeu Lima de Souza Cascardo 944e287840SThadeu Lima de Souza Cascardo static int __init iommu_setup(char *str) 954e287840SThadeu Lima de Souza Cascardo { 964e287840SThadeu Lima de Souza Cascardo if (!str) 974e287840SThadeu Lima de Souza Cascardo return -EINVAL; 984e287840SThadeu Lima de Souza Cascardo 994e287840SThadeu Lima de Souza Cascardo while (*str) { 1004e287840SThadeu Lima de Souza Cascardo if (!strncmp(str, "nobypass", 8)) { 1014e287840SThadeu Lima de Souza Cascardo pnv_iommu_bypass_disabled = true; 1024e287840SThadeu Lima de Souza Cascardo pr_info("PowerNV: IOMMU bypass window disabled.\n"); 1034e287840SThadeu Lima de Souza Cascardo break; 1044e287840SThadeu Lima de Souza Cascardo } 1054e287840SThadeu Lima de Souza Cascardo str += strcspn(str, ","); 1064e287840SThadeu Lima de Souza Cascardo if (*str == ',') 1074e287840SThadeu Lima de Souza Cascardo str++; 1084e287840SThadeu Lima de Souza Cascardo } 1094e287840SThadeu Lima de Souza Cascardo 1104e287840SThadeu Lima de Souza Cascardo return 0; 1114e287840SThadeu Lima de Souza Cascardo } 1124e287840SThadeu Lima de Souza Cascardo early_param("iommu", iommu_setup); 1134e287840SThadeu Lima de Souza Cascardo 114262af557SGuo Chao static inline bool pnv_pci_is_mem_pref_64(unsigned long flags) 115262af557SGuo Chao { 116262af557SGuo Chao return ((flags & (IORESOURCE_MEM_64 | IORESOURCE_PREFETCH)) == 117262af557SGuo Chao (IORESOURCE_MEM_64 | IORESOURCE_PREFETCH)); 118262af557SGuo Chao } 119262af557SGuo Chao 1201e916772SGavin Shan static struct pnv_ioda_pe *pnv_ioda_init_pe(struct pnv_phb *phb, int pe_no) 1211e916772SGavin Shan { 1221e916772SGavin Shan phb->ioda.pe_array[pe_no].phb = phb; 1231e916772SGavin Shan phb->ioda.pe_array[pe_no].pe_number = pe_no; 1241e916772SGavin Shan 1251e916772SGavin Shan return &phb->ioda.pe_array[pe_no]; 1261e916772SGavin Shan } 1271e916772SGavin Shan 1284b82ab18SGavin Shan static void pnv_ioda_reserve_pe(struct pnv_phb *phb, int pe_no) 1294b82ab18SGavin Shan { 13092b8f137SGavin Shan if (!(pe_no >= 0 && pe_no < phb->ioda.total_pe_num)) { 1314b82ab18SGavin Shan pr_warn("%s: Invalid PE %d on PHB#%x\n", 1324b82ab18SGavin Shan __func__, pe_no, phb->hose->global_number); 1334b82ab18SGavin Shan return; 1344b82ab18SGavin Shan } 1354b82ab18SGavin Shan 136e9dc4d7fSGavin Shan if (test_and_set_bit(pe_no, phb->ioda.pe_alloc)) 137e9dc4d7fSGavin Shan pr_debug("%s: PE %d was reserved on PHB#%x\n", 1384b82ab18SGavin Shan __func__, pe_no, phb->hose->global_number); 1394b82ab18SGavin Shan 1401e916772SGavin Shan pnv_ioda_init_pe(phb, pe_no); 1414b82ab18SGavin Shan } 1424b82ab18SGavin Shan 1431e916772SGavin Shan static struct pnv_ioda_pe *pnv_ioda_alloc_pe(struct pnv_phb *phb) 144184cd4a3SBenjamin Herrenschmidt { 1459fcd6f4aSGavin Shan unsigned long pe = phb->ioda.total_pe_num - 1; 146184cd4a3SBenjamin Herrenschmidt 1479fcd6f4aSGavin Shan for (pe = phb->ioda.total_pe_num - 1; pe >= 0; pe--) { 1489fcd6f4aSGavin Shan if (!test_and_set_bit(pe, phb->ioda.pe_alloc)) 1491e916772SGavin Shan return pnv_ioda_init_pe(phb, pe); 150184cd4a3SBenjamin Herrenschmidt } 151184cd4a3SBenjamin Herrenschmidt 1529fcd6f4aSGavin Shan return NULL; 1539fcd6f4aSGavin Shan } 1549fcd6f4aSGavin Shan 1551e916772SGavin Shan static void pnv_ioda_free_pe(struct pnv_ioda_pe *pe) 156184cd4a3SBenjamin Herrenschmidt { 1571e916772SGavin Shan struct pnv_phb *phb = pe->phb; 158184cd4a3SBenjamin Herrenschmidt 1591e916772SGavin Shan WARN_ON(pe->pdev); 1601e916772SGavin Shan 1611e916772SGavin Shan memset(pe, 0, sizeof(struct pnv_ioda_pe)); 1621e916772SGavin Shan clear_bit(pe->pe_number, phb->ioda.pe_alloc); 163184cd4a3SBenjamin Herrenschmidt } 164184cd4a3SBenjamin Herrenschmidt 165262af557SGuo Chao /* The default M64 BAR is shared by all PEs */ 166262af557SGuo Chao static int pnv_ioda2_init_m64(struct pnv_phb *phb) 167262af557SGuo Chao { 168262af557SGuo Chao const char *desc; 169262af557SGuo Chao struct resource *r; 170262af557SGuo Chao s64 rc; 171262af557SGuo Chao 172262af557SGuo Chao /* Configure the default M64 BAR */ 173262af557SGuo Chao rc = opal_pci_set_phb_mem_window(phb->opal_id, 174262af557SGuo Chao OPAL_M64_WINDOW_TYPE, 175262af557SGuo Chao phb->ioda.m64_bar_idx, 176262af557SGuo Chao phb->ioda.m64_base, 177262af557SGuo Chao 0, /* unused */ 178262af557SGuo Chao phb->ioda.m64_size); 179262af557SGuo Chao if (rc != OPAL_SUCCESS) { 180262af557SGuo Chao desc = "configuring"; 181262af557SGuo Chao goto fail; 182262af557SGuo Chao } 183262af557SGuo Chao 184262af557SGuo Chao /* Enable the default M64 BAR */ 185262af557SGuo Chao rc = opal_pci_phb_mmio_enable(phb->opal_id, 186262af557SGuo Chao OPAL_M64_WINDOW_TYPE, 187262af557SGuo Chao phb->ioda.m64_bar_idx, 188262af557SGuo Chao OPAL_ENABLE_M64_SPLIT); 189262af557SGuo Chao if (rc != OPAL_SUCCESS) { 190262af557SGuo Chao desc = "enabling"; 191262af557SGuo Chao goto fail; 192262af557SGuo Chao } 193262af557SGuo Chao 194262af557SGuo Chao /* Mark the M64 BAR assigned */ 195262af557SGuo Chao set_bit(phb->ioda.m64_bar_idx, &phb->ioda.m64_bar_alloc); 196262af557SGuo Chao 197262af557SGuo Chao /* 19863803c39SGavin Shan * Exclude the segments for reserved and root bus PE, which 19963803c39SGavin Shan * are first or last two PEs. 200262af557SGuo Chao */ 201262af557SGuo Chao r = &phb->hose->mem_resources[1]; 20292b8f137SGavin Shan if (phb->ioda.reserved_pe_idx == 0) 20363803c39SGavin Shan r->start += (2 * phb->ioda.m64_segsize); 20492b8f137SGavin Shan else if (phb->ioda.reserved_pe_idx == (phb->ioda.total_pe_num - 1)) 20563803c39SGavin Shan r->end -= (2 * phb->ioda.m64_segsize); 206262af557SGuo Chao else 207262af557SGuo Chao pr_warn(" Cannot strip M64 segment for reserved PE#%d\n", 20892b8f137SGavin Shan phb->ioda.reserved_pe_idx); 209262af557SGuo Chao 210262af557SGuo Chao return 0; 211262af557SGuo Chao 212262af557SGuo Chao fail: 213262af557SGuo Chao pr_warn(" Failure %lld %s M64 BAR#%d\n", 214262af557SGuo Chao rc, desc, phb->ioda.m64_bar_idx); 215262af557SGuo Chao opal_pci_phb_mmio_enable(phb->opal_id, 216262af557SGuo Chao OPAL_M64_WINDOW_TYPE, 217262af557SGuo Chao phb->ioda.m64_bar_idx, 218262af557SGuo Chao OPAL_DISABLE_M64); 219262af557SGuo Chao return -EIO; 220262af557SGuo Chao } 221262af557SGuo Chao 222c430670aSGavin Shan static void pnv_ioda_reserve_dev_m64_pe(struct pci_dev *pdev, 22396a2f92bSGavin Shan unsigned long *pe_bitmap) 224262af557SGuo Chao { 22596a2f92bSGavin Shan struct pci_controller *hose = pci_bus_to_host(pdev->bus); 22696a2f92bSGavin Shan struct pnv_phb *phb = hose->private_data; 227262af557SGuo Chao struct resource *r; 22896a2f92bSGavin Shan resource_size_t base, sgsz, start, end; 22996a2f92bSGavin Shan int segno, i; 230262af557SGuo Chao 23196a2f92bSGavin Shan base = phb->ioda.m64_base; 23296a2f92bSGavin Shan sgsz = phb->ioda.m64_segsize; 23396a2f92bSGavin Shan for (i = 0; i <= PCI_ROM_RESOURCE; i++) { 23496a2f92bSGavin Shan r = &pdev->resource[i]; 23596a2f92bSGavin Shan if (!r->parent || !pnv_pci_is_mem_pref_64(r->flags)) 236262af557SGuo Chao continue; 237262af557SGuo Chao 23896a2f92bSGavin Shan start = _ALIGN_DOWN(r->start - base, sgsz); 23996a2f92bSGavin Shan end = _ALIGN_UP(r->end - base, sgsz); 24096a2f92bSGavin Shan for (segno = start / sgsz; segno < end / sgsz; segno++) { 24196a2f92bSGavin Shan if (pe_bitmap) 24296a2f92bSGavin Shan set_bit(segno, pe_bitmap); 24396a2f92bSGavin Shan else 24496a2f92bSGavin Shan pnv_ioda_reserve_pe(phb, segno); 245262af557SGuo Chao } 246262af557SGuo Chao } 247262af557SGuo Chao } 248262af557SGuo Chao 24999451551SGavin Shan static int pnv_ioda1_init_m64(struct pnv_phb *phb) 25099451551SGavin Shan { 25199451551SGavin Shan struct resource *r; 25299451551SGavin Shan int index; 25399451551SGavin Shan 25499451551SGavin Shan /* 25599451551SGavin Shan * There are 16 M64 BARs, each of which has 8 segments. So 25699451551SGavin Shan * there are as many M64 segments as the maximum number of 25799451551SGavin Shan * PEs, which is 128. 25899451551SGavin Shan */ 25999451551SGavin Shan for (index = 0; index < PNV_IODA1_M64_NUM; index++) { 26099451551SGavin Shan unsigned long base, segsz = phb->ioda.m64_segsize; 26199451551SGavin Shan int64_t rc; 26299451551SGavin Shan 26399451551SGavin Shan base = phb->ioda.m64_base + 26499451551SGavin Shan index * PNV_IODA1_M64_SEGS * segsz; 26599451551SGavin Shan rc = opal_pci_set_phb_mem_window(phb->opal_id, 26699451551SGavin Shan OPAL_M64_WINDOW_TYPE, index, base, 0, 26799451551SGavin Shan PNV_IODA1_M64_SEGS * segsz); 26899451551SGavin Shan if (rc != OPAL_SUCCESS) { 26999451551SGavin Shan pr_warn(" Error %lld setting M64 PHB#%d-BAR#%d\n", 27099451551SGavin Shan rc, phb->hose->global_number, index); 27199451551SGavin Shan goto fail; 27299451551SGavin Shan } 27399451551SGavin Shan 27499451551SGavin Shan rc = opal_pci_phb_mmio_enable(phb->opal_id, 27599451551SGavin Shan OPAL_M64_WINDOW_TYPE, index, 27699451551SGavin Shan OPAL_ENABLE_M64_SPLIT); 27799451551SGavin Shan if (rc != OPAL_SUCCESS) { 27899451551SGavin Shan pr_warn(" Error %lld enabling M64 PHB#%d-BAR#%d\n", 27999451551SGavin Shan rc, phb->hose->global_number, index); 28099451551SGavin Shan goto fail; 28199451551SGavin Shan } 28299451551SGavin Shan } 28399451551SGavin Shan 28499451551SGavin Shan /* 28563803c39SGavin Shan * Exclude the segments for reserved and root bus PE, which 28663803c39SGavin Shan * are first or last two PEs. 28799451551SGavin Shan */ 28899451551SGavin Shan r = &phb->hose->mem_resources[1]; 28999451551SGavin Shan if (phb->ioda.reserved_pe_idx == 0) 29063803c39SGavin Shan r->start += (2 * phb->ioda.m64_segsize); 29199451551SGavin Shan else if (phb->ioda.reserved_pe_idx == (phb->ioda.total_pe_num - 1)) 29263803c39SGavin Shan r->end -= (2 * phb->ioda.m64_segsize); 29399451551SGavin Shan else 29499451551SGavin Shan WARN(1, "Wrong reserved PE#%d on PHB#%d\n", 29599451551SGavin Shan phb->ioda.reserved_pe_idx, phb->hose->global_number); 29699451551SGavin Shan 29799451551SGavin Shan return 0; 29899451551SGavin Shan 29999451551SGavin Shan fail: 30099451551SGavin Shan for ( ; index >= 0; index--) 30199451551SGavin Shan opal_pci_phb_mmio_enable(phb->opal_id, 30299451551SGavin Shan OPAL_M64_WINDOW_TYPE, index, OPAL_DISABLE_M64); 30399451551SGavin Shan 30499451551SGavin Shan return -EIO; 30599451551SGavin Shan } 30699451551SGavin Shan 307c430670aSGavin Shan static void pnv_ioda_reserve_m64_pe(struct pci_bus *bus, 30896a2f92bSGavin Shan unsigned long *pe_bitmap, 30996a2f92bSGavin Shan bool all) 310262af557SGuo Chao { 311262af557SGuo Chao struct pci_dev *pdev; 31296a2f92bSGavin Shan 31396a2f92bSGavin Shan list_for_each_entry(pdev, &bus->devices, bus_list) { 314c430670aSGavin Shan pnv_ioda_reserve_dev_m64_pe(pdev, pe_bitmap); 31596a2f92bSGavin Shan 31696a2f92bSGavin Shan if (all && pdev->subordinate) 317c430670aSGavin Shan pnv_ioda_reserve_m64_pe(pdev->subordinate, 31896a2f92bSGavin Shan pe_bitmap, all); 31996a2f92bSGavin Shan } 32096a2f92bSGavin Shan } 32196a2f92bSGavin Shan 3221e916772SGavin Shan static struct pnv_ioda_pe *pnv_ioda_pick_m64_pe(struct pci_bus *bus, bool all) 323262af557SGuo Chao { 32426ba248dSGavin Shan struct pci_controller *hose = pci_bus_to_host(bus); 32526ba248dSGavin Shan struct pnv_phb *phb = hose->private_data; 326262af557SGuo Chao struct pnv_ioda_pe *master_pe, *pe; 327262af557SGuo Chao unsigned long size, *pe_alloc; 32826ba248dSGavin Shan int i; 329262af557SGuo Chao 330262af557SGuo Chao /* Root bus shouldn't use M64 */ 331262af557SGuo Chao if (pci_is_root_bus(bus)) 3321e916772SGavin Shan return NULL; 333262af557SGuo Chao 334262af557SGuo Chao /* Allocate bitmap */ 33592b8f137SGavin Shan size = _ALIGN_UP(phb->ioda.total_pe_num / 8, sizeof(unsigned long)); 336262af557SGuo Chao pe_alloc = kzalloc(size, GFP_KERNEL); 337262af557SGuo Chao if (!pe_alloc) { 338262af557SGuo Chao pr_warn("%s: Out of memory !\n", 339262af557SGuo Chao __func__); 3401e916772SGavin Shan return NULL; 341262af557SGuo Chao } 342262af557SGuo Chao 34326ba248dSGavin Shan /* Figure out reserved PE numbers by the PE */ 344c430670aSGavin Shan pnv_ioda_reserve_m64_pe(bus, pe_alloc, all); 345262af557SGuo Chao 346262af557SGuo Chao /* 347262af557SGuo Chao * the current bus might not own M64 window and that's all 348262af557SGuo Chao * contributed by its child buses. For the case, we needn't 349262af557SGuo Chao * pick M64 dependent PE#. 350262af557SGuo Chao */ 35192b8f137SGavin Shan if (bitmap_empty(pe_alloc, phb->ioda.total_pe_num)) { 352262af557SGuo Chao kfree(pe_alloc); 3531e916772SGavin Shan return NULL; 354262af557SGuo Chao } 355262af557SGuo Chao 356262af557SGuo Chao /* 357262af557SGuo Chao * Figure out the master PE and put all slave PEs to master 358262af557SGuo Chao * PE's list to form compound PE. 359262af557SGuo Chao */ 360262af557SGuo Chao master_pe = NULL; 361262af557SGuo Chao i = -1; 36292b8f137SGavin Shan while ((i = find_next_bit(pe_alloc, phb->ioda.total_pe_num, i + 1)) < 36392b8f137SGavin Shan phb->ioda.total_pe_num) { 364262af557SGuo Chao pe = &phb->ioda.pe_array[i]; 365262af557SGuo Chao 36693289d8cSGavin Shan phb->ioda.m64_segmap[pe->pe_number] = pe->pe_number; 367262af557SGuo Chao if (!master_pe) { 368262af557SGuo Chao pe->flags |= PNV_IODA_PE_MASTER; 369262af557SGuo Chao INIT_LIST_HEAD(&pe->slaves); 370262af557SGuo Chao master_pe = pe; 371262af557SGuo Chao } else { 372262af557SGuo Chao pe->flags |= PNV_IODA_PE_SLAVE; 373262af557SGuo Chao pe->master = master_pe; 374262af557SGuo Chao list_add_tail(&pe->list, &master_pe->slaves); 375262af557SGuo Chao } 37699451551SGavin Shan 37799451551SGavin Shan /* 37899451551SGavin Shan * P7IOC supports M64DT, which helps mapping M64 segment 37999451551SGavin Shan * to one particular PE#. However, PHB3 has fixed mapping 38099451551SGavin Shan * between M64 segment and PE#. In order to have same logic 38199451551SGavin Shan * for P7IOC and PHB3, we enforce fixed mapping between M64 38299451551SGavin Shan * segment and PE# on P7IOC. 38399451551SGavin Shan */ 38499451551SGavin Shan if (phb->type == PNV_PHB_IODA1) { 38599451551SGavin Shan int64_t rc; 38699451551SGavin Shan 38799451551SGavin Shan rc = opal_pci_map_pe_mmio_window(phb->opal_id, 38899451551SGavin Shan pe->pe_number, OPAL_M64_WINDOW_TYPE, 38999451551SGavin Shan pe->pe_number / PNV_IODA1_M64_SEGS, 39099451551SGavin Shan pe->pe_number % PNV_IODA1_M64_SEGS); 39199451551SGavin Shan if (rc != OPAL_SUCCESS) 39299451551SGavin Shan pr_warn("%s: Error %lld mapping M64 for PHB#%d-PE#%d\n", 39399451551SGavin Shan __func__, rc, phb->hose->global_number, 39499451551SGavin Shan pe->pe_number); 39599451551SGavin Shan } 396262af557SGuo Chao } 397262af557SGuo Chao 398262af557SGuo Chao kfree(pe_alloc); 3991e916772SGavin Shan return master_pe; 400262af557SGuo Chao } 401262af557SGuo Chao 402262af557SGuo Chao static void __init pnv_ioda_parse_m64_window(struct pnv_phb *phb) 403262af557SGuo Chao { 404262af557SGuo Chao struct pci_controller *hose = phb->hose; 405262af557SGuo Chao struct device_node *dn = hose->dn; 406262af557SGuo Chao struct resource *res; 407262af557SGuo Chao const u32 *r; 408262af557SGuo Chao u64 pci_addr; 409262af557SGuo Chao 41099451551SGavin Shan if (phb->type != PNV_PHB_IODA1 && phb->type != PNV_PHB_IODA2) { 4111665c4a8SGavin Shan pr_info(" Not support M64 window\n"); 4121665c4a8SGavin Shan return; 4131665c4a8SGavin Shan } 4141665c4a8SGavin Shan 415e4d54f71SStewart Smith if (!firmware_has_feature(FW_FEATURE_OPAL)) { 416262af557SGuo Chao pr_info(" Firmware too old to support M64 window\n"); 417262af557SGuo Chao return; 418262af557SGuo Chao } 419262af557SGuo Chao 420262af557SGuo Chao r = of_get_property(dn, "ibm,opal-m64-window", NULL); 421262af557SGuo Chao if (!r) { 422262af557SGuo Chao pr_info(" No <ibm,opal-m64-window> on %s\n", 423262af557SGuo Chao dn->full_name); 424262af557SGuo Chao return; 425262af557SGuo Chao } 426262af557SGuo Chao 427262af557SGuo Chao res = &hose->mem_resources[1]; 428e80c4e7cSGavin Shan res->name = dn->full_name; 429262af557SGuo Chao res->start = of_translate_address(dn, r + 2); 430262af557SGuo Chao res->end = res->start + of_read_number(r + 4, 2) - 1; 431262af557SGuo Chao res->flags = (IORESOURCE_MEM | IORESOURCE_MEM_64 | IORESOURCE_PREFETCH); 432262af557SGuo Chao pci_addr = of_read_number(r, 2); 433262af557SGuo Chao hose->mem_offset[1] = res->start - pci_addr; 434262af557SGuo Chao 435262af557SGuo Chao phb->ioda.m64_size = resource_size(res); 43692b8f137SGavin Shan phb->ioda.m64_segsize = phb->ioda.m64_size / phb->ioda.total_pe_num; 437262af557SGuo Chao phb->ioda.m64_base = pci_addr; 438262af557SGuo Chao 439e9863e68SWei Yang pr_info(" MEM64 0x%016llx..0x%016llx -> 0x%016llx\n", 440e9863e68SWei Yang res->start, res->end, pci_addr); 441e9863e68SWei Yang 442262af557SGuo Chao /* Use last M64 BAR to cover M64 window */ 443262af557SGuo Chao phb->ioda.m64_bar_idx = 15; 44499451551SGavin Shan if (phb->type == PNV_PHB_IODA1) 44599451551SGavin Shan phb->init_m64 = pnv_ioda1_init_m64; 44699451551SGavin Shan else 447262af557SGuo Chao phb->init_m64 = pnv_ioda2_init_m64; 448c430670aSGavin Shan phb->reserve_m64_pe = pnv_ioda_reserve_m64_pe; 449c430670aSGavin Shan phb->pick_m64_pe = pnv_ioda_pick_m64_pe; 450262af557SGuo Chao } 451262af557SGuo Chao 45249dec922SGavin Shan static void pnv_ioda_freeze_pe(struct pnv_phb *phb, int pe_no) 45349dec922SGavin Shan { 45449dec922SGavin Shan struct pnv_ioda_pe *pe = &phb->ioda.pe_array[pe_no]; 45549dec922SGavin Shan struct pnv_ioda_pe *slave; 45649dec922SGavin Shan s64 rc; 45749dec922SGavin Shan 45849dec922SGavin Shan /* Fetch master PE */ 45949dec922SGavin Shan if (pe->flags & PNV_IODA_PE_SLAVE) { 46049dec922SGavin Shan pe = pe->master; 461ec8e4e9dSGavin Shan if (WARN_ON(!pe || !(pe->flags & PNV_IODA_PE_MASTER))) 462ec8e4e9dSGavin Shan return; 463ec8e4e9dSGavin Shan 46449dec922SGavin Shan pe_no = pe->pe_number; 46549dec922SGavin Shan } 46649dec922SGavin Shan 46749dec922SGavin Shan /* Freeze master PE */ 46849dec922SGavin Shan rc = opal_pci_eeh_freeze_set(phb->opal_id, 46949dec922SGavin Shan pe_no, 47049dec922SGavin Shan OPAL_EEH_ACTION_SET_FREEZE_ALL); 47149dec922SGavin Shan if (rc != OPAL_SUCCESS) { 47249dec922SGavin Shan pr_warn("%s: Failure %lld freezing PHB#%x-PE#%x\n", 47349dec922SGavin Shan __func__, rc, phb->hose->global_number, pe_no); 47449dec922SGavin Shan return; 47549dec922SGavin Shan } 47649dec922SGavin Shan 47749dec922SGavin Shan /* Freeze slave PEs */ 47849dec922SGavin Shan if (!(pe->flags & PNV_IODA_PE_MASTER)) 47949dec922SGavin Shan return; 48049dec922SGavin Shan 48149dec922SGavin Shan list_for_each_entry(slave, &pe->slaves, list) { 48249dec922SGavin Shan rc = opal_pci_eeh_freeze_set(phb->opal_id, 48349dec922SGavin Shan slave->pe_number, 48449dec922SGavin Shan OPAL_EEH_ACTION_SET_FREEZE_ALL); 48549dec922SGavin Shan if (rc != OPAL_SUCCESS) 48649dec922SGavin Shan pr_warn("%s: Failure %lld freezing PHB#%x-PE#%x\n", 48749dec922SGavin Shan __func__, rc, phb->hose->global_number, 48849dec922SGavin Shan slave->pe_number); 48949dec922SGavin Shan } 49049dec922SGavin Shan } 49149dec922SGavin Shan 492e51df2c1SAnton Blanchard static int pnv_ioda_unfreeze_pe(struct pnv_phb *phb, int pe_no, int opt) 49349dec922SGavin Shan { 49449dec922SGavin Shan struct pnv_ioda_pe *pe, *slave; 49549dec922SGavin Shan s64 rc; 49649dec922SGavin Shan 49749dec922SGavin Shan /* Find master PE */ 49849dec922SGavin Shan pe = &phb->ioda.pe_array[pe_no]; 49949dec922SGavin Shan if (pe->flags & PNV_IODA_PE_SLAVE) { 50049dec922SGavin Shan pe = pe->master; 50149dec922SGavin Shan WARN_ON(!pe || !(pe->flags & PNV_IODA_PE_MASTER)); 50249dec922SGavin Shan pe_no = pe->pe_number; 50349dec922SGavin Shan } 50449dec922SGavin Shan 50549dec922SGavin Shan /* Clear frozen state for master PE */ 50649dec922SGavin Shan rc = opal_pci_eeh_freeze_clear(phb->opal_id, pe_no, opt); 50749dec922SGavin Shan if (rc != OPAL_SUCCESS) { 50849dec922SGavin Shan pr_warn("%s: Failure %lld clear %d on PHB#%x-PE#%x\n", 50949dec922SGavin Shan __func__, rc, opt, phb->hose->global_number, pe_no); 51049dec922SGavin Shan return -EIO; 51149dec922SGavin Shan } 51249dec922SGavin Shan 51349dec922SGavin Shan if (!(pe->flags & PNV_IODA_PE_MASTER)) 51449dec922SGavin Shan return 0; 51549dec922SGavin Shan 51649dec922SGavin Shan /* Clear frozen state for slave PEs */ 51749dec922SGavin Shan list_for_each_entry(slave, &pe->slaves, list) { 51849dec922SGavin Shan rc = opal_pci_eeh_freeze_clear(phb->opal_id, 51949dec922SGavin Shan slave->pe_number, 52049dec922SGavin Shan opt); 52149dec922SGavin Shan if (rc != OPAL_SUCCESS) { 52249dec922SGavin Shan pr_warn("%s: Failure %lld clear %d on PHB#%x-PE#%x\n", 52349dec922SGavin Shan __func__, rc, opt, phb->hose->global_number, 52449dec922SGavin Shan slave->pe_number); 52549dec922SGavin Shan return -EIO; 52649dec922SGavin Shan } 52749dec922SGavin Shan } 52849dec922SGavin Shan 52949dec922SGavin Shan return 0; 53049dec922SGavin Shan } 53149dec922SGavin Shan 53249dec922SGavin Shan static int pnv_ioda_get_pe_state(struct pnv_phb *phb, int pe_no) 53349dec922SGavin Shan { 53449dec922SGavin Shan struct pnv_ioda_pe *slave, *pe; 53549dec922SGavin Shan u8 fstate, state; 53649dec922SGavin Shan __be16 pcierr; 53749dec922SGavin Shan s64 rc; 53849dec922SGavin Shan 53949dec922SGavin Shan /* Sanity check on PE number */ 54092b8f137SGavin Shan if (pe_no < 0 || pe_no >= phb->ioda.total_pe_num) 54149dec922SGavin Shan return OPAL_EEH_STOPPED_PERM_UNAVAIL; 54249dec922SGavin Shan 54349dec922SGavin Shan /* 54449dec922SGavin Shan * Fetch the master PE and the PE instance might be 54549dec922SGavin Shan * not initialized yet. 54649dec922SGavin Shan */ 54749dec922SGavin Shan pe = &phb->ioda.pe_array[pe_no]; 54849dec922SGavin Shan if (pe->flags & PNV_IODA_PE_SLAVE) { 54949dec922SGavin Shan pe = pe->master; 55049dec922SGavin Shan WARN_ON(!pe || !(pe->flags & PNV_IODA_PE_MASTER)); 55149dec922SGavin Shan pe_no = pe->pe_number; 55249dec922SGavin Shan } 55349dec922SGavin Shan 55449dec922SGavin Shan /* Check the master PE */ 55549dec922SGavin Shan rc = opal_pci_eeh_freeze_status(phb->opal_id, pe_no, 55649dec922SGavin Shan &state, &pcierr, NULL); 55749dec922SGavin Shan if (rc != OPAL_SUCCESS) { 55849dec922SGavin Shan pr_warn("%s: Failure %lld getting " 55949dec922SGavin Shan "PHB#%x-PE#%x state\n", 56049dec922SGavin Shan __func__, rc, 56149dec922SGavin Shan phb->hose->global_number, pe_no); 56249dec922SGavin Shan return OPAL_EEH_STOPPED_TEMP_UNAVAIL; 56349dec922SGavin Shan } 56449dec922SGavin Shan 56549dec922SGavin Shan /* Check the slave PE */ 56649dec922SGavin Shan if (!(pe->flags & PNV_IODA_PE_MASTER)) 56749dec922SGavin Shan return state; 56849dec922SGavin Shan 56949dec922SGavin Shan list_for_each_entry(slave, &pe->slaves, list) { 57049dec922SGavin Shan rc = opal_pci_eeh_freeze_status(phb->opal_id, 57149dec922SGavin Shan slave->pe_number, 57249dec922SGavin Shan &fstate, 57349dec922SGavin Shan &pcierr, 57449dec922SGavin Shan NULL); 57549dec922SGavin Shan if (rc != OPAL_SUCCESS) { 57649dec922SGavin Shan pr_warn("%s: Failure %lld getting " 57749dec922SGavin Shan "PHB#%x-PE#%x state\n", 57849dec922SGavin Shan __func__, rc, 57949dec922SGavin Shan phb->hose->global_number, slave->pe_number); 58049dec922SGavin Shan return OPAL_EEH_STOPPED_TEMP_UNAVAIL; 58149dec922SGavin Shan } 58249dec922SGavin Shan 58349dec922SGavin Shan /* 58449dec922SGavin Shan * Override the result based on the ascending 58549dec922SGavin Shan * priority. 58649dec922SGavin Shan */ 58749dec922SGavin Shan if (fstate > state) 58849dec922SGavin Shan state = fstate; 58949dec922SGavin Shan } 59049dec922SGavin Shan 59149dec922SGavin Shan return state; 59249dec922SGavin Shan } 59349dec922SGavin Shan 594184cd4a3SBenjamin Herrenschmidt /* Currently those 2 are only used when MSIs are enabled, this will change 595184cd4a3SBenjamin Herrenschmidt * but in the meantime, we need to protect them to avoid warnings 596184cd4a3SBenjamin Herrenschmidt */ 597184cd4a3SBenjamin Herrenschmidt #ifdef CONFIG_PCI_MSI 598f456834aSIan Munsie struct pnv_ioda_pe *pnv_ioda_get_pe(struct pci_dev *dev) 599184cd4a3SBenjamin Herrenschmidt { 600184cd4a3SBenjamin Herrenschmidt struct pci_controller *hose = pci_bus_to_host(dev->bus); 601184cd4a3SBenjamin Herrenschmidt struct pnv_phb *phb = hose->private_data; 602b72c1f65SBenjamin Herrenschmidt struct pci_dn *pdn = pci_get_pdn(dev); 603184cd4a3SBenjamin Herrenschmidt 604184cd4a3SBenjamin Herrenschmidt if (!pdn) 605184cd4a3SBenjamin Herrenschmidt return NULL; 606184cd4a3SBenjamin Herrenschmidt if (pdn->pe_number == IODA_INVALID_PE) 607184cd4a3SBenjamin Herrenschmidt return NULL; 608184cd4a3SBenjamin Herrenschmidt return &phb->ioda.pe_array[pdn->pe_number]; 609184cd4a3SBenjamin Herrenschmidt } 610184cd4a3SBenjamin Herrenschmidt #endif /* CONFIG_PCI_MSI */ 611184cd4a3SBenjamin Herrenschmidt 612b131a842SGavin Shan static int pnv_ioda_set_one_peltv(struct pnv_phb *phb, 613b131a842SGavin Shan struct pnv_ioda_pe *parent, 614b131a842SGavin Shan struct pnv_ioda_pe *child, 615b131a842SGavin Shan bool is_add) 616b131a842SGavin Shan { 617b131a842SGavin Shan const char *desc = is_add ? "adding" : "removing"; 618b131a842SGavin Shan uint8_t op = is_add ? OPAL_ADD_PE_TO_DOMAIN : 619b131a842SGavin Shan OPAL_REMOVE_PE_FROM_DOMAIN; 620b131a842SGavin Shan struct pnv_ioda_pe *slave; 621b131a842SGavin Shan long rc; 622b131a842SGavin Shan 623b131a842SGavin Shan /* Parent PE affects child PE */ 624b131a842SGavin Shan rc = opal_pci_set_peltv(phb->opal_id, parent->pe_number, 625b131a842SGavin Shan child->pe_number, op); 626b131a842SGavin Shan if (rc != OPAL_SUCCESS) { 627b131a842SGavin Shan pe_warn(child, "OPAL error %ld %s to parent PELTV\n", 628b131a842SGavin Shan rc, desc); 629b131a842SGavin Shan return -ENXIO; 630b131a842SGavin Shan } 631b131a842SGavin Shan 632b131a842SGavin Shan if (!(child->flags & PNV_IODA_PE_MASTER)) 633b131a842SGavin Shan return 0; 634b131a842SGavin Shan 635b131a842SGavin Shan /* Compound case: parent PE affects slave PEs */ 636b131a842SGavin Shan list_for_each_entry(slave, &child->slaves, list) { 637b131a842SGavin Shan rc = opal_pci_set_peltv(phb->opal_id, parent->pe_number, 638b131a842SGavin Shan slave->pe_number, op); 639b131a842SGavin Shan if (rc != OPAL_SUCCESS) { 640b131a842SGavin Shan pe_warn(slave, "OPAL error %ld %s to parent PELTV\n", 641b131a842SGavin Shan rc, desc); 642b131a842SGavin Shan return -ENXIO; 643b131a842SGavin Shan } 644b131a842SGavin Shan } 645b131a842SGavin Shan 646b131a842SGavin Shan return 0; 647b131a842SGavin Shan } 648b131a842SGavin Shan 649b131a842SGavin Shan static int pnv_ioda_set_peltv(struct pnv_phb *phb, 650b131a842SGavin Shan struct pnv_ioda_pe *pe, 651b131a842SGavin Shan bool is_add) 652b131a842SGavin Shan { 653b131a842SGavin Shan struct pnv_ioda_pe *slave; 654781a868fSWei Yang struct pci_dev *pdev = NULL; 655b131a842SGavin Shan int ret; 656b131a842SGavin Shan 657b131a842SGavin Shan /* 658b131a842SGavin Shan * Clear PE frozen state. If it's master PE, we need 659b131a842SGavin Shan * clear slave PE frozen state as well. 660b131a842SGavin Shan */ 661b131a842SGavin Shan if (is_add) { 662b131a842SGavin Shan opal_pci_eeh_freeze_clear(phb->opal_id, pe->pe_number, 663b131a842SGavin Shan OPAL_EEH_ACTION_CLEAR_FREEZE_ALL); 664b131a842SGavin Shan if (pe->flags & PNV_IODA_PE_MASTER) { 665b131a842SGavin Shan list_for_each_entry(slave, &pe->slaves, list) 666b131a842SGavin Shan opal_pci_eeh_freeze_clear(phb->opal_id, 667b131a842SGavin Shan slave->pe_number, 668b131a842SGavin Shan OPAL_EEH_ACTION_CLEAR_FREEZE_ALL); 669b131a842SGavin Shan } 670b131a842SGavin Shan } 671b131a842SGavin Shan 672b131a842SGavin Shan /* 673b131a842SGavin Shan * Associate PE in PELT. We need add the PE into the 674b131a842SGavin Shan * corresponding PELT-V as well. Otherwise, the error 675b131a842SGavin Shan * originated from the PE might contribute to other 676b131a842SGavin Shan * PEs. 677b131a842SGavin Shan */ 678b131a842SGavin Shan ret = pnv_ioda_set_one_peltv(phb, pe, pe, is_add); 679b131a842SGavin Shan if (ret) 680b131a842SGavin Shan return ret; 681b131a842SGavin Shan 682b131a842SGavin Shan /* For compound PEs, any one affects all of them */ 683b131a842SGavin Shan if (pe->flags & PNV_IODA_PE_MASTER) { 684b131a842SGavin Shan list_for_each_entry(slave, &pe->slaves, list) { 685b131a842SGavin Shan ret = pnv_ioda_set_one_peltv(phb, slave, pe, is_add); 686b131a842SGavin Shan if (ret) 687b131a842SGavin Shan return ret; 688b131a842SGavin Shan } 689b131a842SGavin Shan } 690b131a842SGavin Shan 691b131a842SGavin Shan if (pe->flags & (PNV_IODA_PE_BUS_ALL | PNV_IODA_PE_BUS)) 692b131a842SGavin Shan pdev = pe->pbus->self; 693781a868fSWei Yang else if (pe->flags & PNV_IODA_PE_DEV) 694b131a842SGavin Shan pdev = pe->pdev->bus->self; 695781a868fSWei Yang #ifdef CONFIG_PCI_IOV 696781a868fSWei Yang else if (pe->flags & PNV_IODA_PE_VF) 697283e2d8aSGavin Shan pdev = pe->parent_dev; 698781a868fSWei Yang #endif /* CONFIG_PCI_IOV */ 699b131a842SGavin Shan while (pdev) { 700b131a842SGavin Shan struct pci_dn *pdn = pci_get_pdn(pdev); 701b131a842SGavin Shan struct pnv_ioda_pe *parent; 702b131a842SGavin Shan 703b131a842SGavin Shan if (pdn && pdn->pe_number != IODA_INVALID_PE) { 704b131a842SGavin Shan parent = &phb->ioda.pe_array[pdn->pe_number]; 705b131a842SGavin Shan ret = pnv_ioda_set_one_peltv(phb, parent, pe, is_add); 706b131a842SGavin Shan if (ret) 707b131a842SGavin Shan return ret; 708b131a842SGavin Shan } 709b131a842SGavin Shan 710b131a842SGavin Shan pdev = pdev->bus->self; 711b131a842SGavin Shan } 712b131a842SGavin Shan 713b131a842SGavin Shan return 0; 714b131a842SGavin Shan } 715b131a842SGavin Shan 716781a868fSWei Yang static int pnv_ioda_deconfigure_pe(struct pnv_phb *phb, struct pnv_ioda_pe *pe) 717781a868fSWei Yang { 718781a868fSWei Yang struct pci_dev *parent; 719781a868fSWei Yang uint8_t bcomp, dcomp, fcomp; 720781a868fSWei Yang int64_t rc; 721781a868fSWei Yang long rid_end, rid; 722781a868fSWei Yang 723781a868fSWei Yang /* Currently, we just deconfigure VF PE. Bus PE will always there.*/ 724781a868fSWei Yang if (pe->pbus) { 725781a868fSWei Yang int count; 726781a868fSWei Yang 727781a868fSWei Yang dcomp = OPAL_IGNORE_RID_DEVICE_NUMBER; 728781a868fSWei Yang fcomp = OPAL_IGNORE_RID_FUNCTION_NUMBER; 729781a868fSWei Yang parent = pe->pbus->self; 730781a868fSWei Yang if (pe->flags & PNV_IODA_PE_BUS_ALL) 731781a868fSWei Yang count = pe->pbus->busn_res.end - pe->pbus->busn_res.start + 1; 732781a868fSWei Yang else 733781a868fSWei Yang count = 1; 734781a868fSWei Yang 735781a868fSWei Yang switch(count) { 736781a868fSWei Yang case 1: bcomp = OpalPciBusAll; break; 737781a868fSWei Yang case 2: bcomp = OpalPciBus7Bits; break; 738781a868fSWei Yang case 4: bcomp = OpalPciBus6Bits; break; 739781a868fSWei Yang case 8: bcomp = OpalPciBus5Bits; break; 740781a868fSWei Yang case 16: bcomp = OpalPciBus4Bits; break; 741781a868fSWei Yang case 32: bcomp = OpalPciBus3Bits; break; 742781a868fSWei Yang default: 743781a868fSWei Yang dev_err(&pe->pbus->dev, "Number of subordinate buses %d unsupported\n", 744781a868fSWei Yang count); 745781a868fSWei Yang /* Do an exact match only */ 746781a868fSWei Yang bcomp = OpalPciBusAll; 747781a868fSWei Yang } 748781a868fSWei Yang rid_end = pe->rid + (count << 8); 749781a868fSWei Yang } else { 75093e01a50SGavin Shan #ifdef CONFIG_PCI_IOV 751781a868fSWei Yang if (pe->flags & PNV_IODA_PE_VF) 752781a868fSWei Yang parent = pe->parent_dev; 753781a868fSWei Yang else 75493e01a50SGavin Shan #endif 755781a868fSWei Yang parent = pe->pdev->bus->self; 756781a868fSWei Yang bcomp = OpalPciBusAll; 757781a868fSWei Yang dcomp = OPAL_COMPARE_RID_DEVICE_NUMBER; 758781a868fSWei Yang fcomp = OPAL_COMPARE_RID_FUNCTION_NUMBER; 759781a868fSWei Yang rid_end = pe->rid + 1; 760781a868fSWei Yang } 761781a868fSWei Yang 762781a868fSWei Yang /* Clear the reverse map */ 763781a868fSWei Yang for (rid = pe->rid; rid < rid_end; rid++) 764c127562aSGavin Shan phb->ioda.pe_rmap[rid] = IODA_INVALID_PE; 765781a868fSWei Yang 766781a868fSWei Yang /* Release from all parents PELT-V */ 767781a868fSWei Yang while (parent) { 768781a868fSWei Yang struct pci_dn *pdn = pci_get_pdn(parent); 769781a868fSWei Yang if (pdn && pdn->pe_number != IODA_INVALID_PE) { 770781a868fSWei Yang rc = opal_pci_set_peltv(phb->opal_id, pdn->pe_number, 771781a868fSWei Yang pe->pe_number, OPAL_REMOVE_PE_FROM_DOMAIN); 772781a868fSWei Yang /* XXX What to do in case of error ? */ 773781a868fSWei Yang } 774781a868fSWei Yang parent = parent->bus->self; 775781a868fSWei Yang } 776781a868fSWei Yang 777f951e510SGavin Shan opal_pci_eeh_freeze_clear(phb->opal_id, pe->pe_number, 778781a868fSWei Yang OPAL_EEH_ACTION_CLEAR_FREEZE_ALL); 779781a868fSWei Yang 780781a868fSWei Yang /* Disassociate PE in PELT */ 781781a868fSWei Yang rc = opal_pci_set_peltv(phb->opal_id, pe->pe_number, 782781a868fSWei Yang pe->pe_number, OPAL_REMOVE_PE_FROM_DOMAIN); 783781a868fSWei Yang if (rc) 784781a868fSWei Yang pe_warn(pe, "OPAL error %ld remove self from PELTV\n", rc); 785781a868fSWei Yang rc = opal_pci_set_pe(phb->opal_id, pe->pe_number, pe->rid, 786781a868fSWei Yang bcomp, dcomp, fcomp, OPAL_UNMAP_PE); 787781a868fSWei Yang if (rc) 788781a868fSWei Yang pe_err(pe, "OPAL error %ld trying to setup PELT table\n", rc); 789781a868fSWei Yang 790781a868fSWei Yang pe->pbus = NULL; 791781a868fSWei Yang pe->pdev = NULL; 79293e01a50SGavin Shan #ifdef CONFIG_PCI_IOV 793781a868fSWei Yang pe->parent_dev = NULL; 79493e01a50SGavin Shan #endif 795781a868fSWei Yang 796781a868fSWei Yang return 0; 797781a868fSWei Yang } 798781a868fSWei Yang 799cad5cef6SGreg Kroah-Hartman static int pnv_ioda_configure_pe(struct pnv_phb *phb, struct pnv_ioda_pe *pe) 800184cd4a3SBenjamin Herrenschmidt { 801184cd4a3SBenjamin Herrenschmidt struct pci_dev *parent; 802184cd4a3SBenjamin Herrenschmidt uint8_t bcomp, dcomp, fcomp; 803184cd4a3SBenjamin Herrenschmidt long rc, rid_end, rid; 804184cd4a3SBenjamin Herrenschmidt 805184cd4a3SBenjamin Herrenschmidt /* Bus validation ? */ 806184cd4a3SBenjamin Herrenschmidt if (pe->pbus) { 807184cd4a3SBenjamin Herrenschmidt int count; 808184cd4a3SBenjamin Herrenschmidt 809184cd4a3SBenjamin Herrenschmidt dcomp = OPAL_IGNORE_RID_DEVICE_NUMBER; 810184cd4a3SBenjamin Herrenschmidt fcomp = OPAL_IGNORE_RID_FUNCTION_NUMBER; 811184cd4a3SBenjamin Herrenschmidt parent = pe->pbus->self; 812fb446ad0SGavin Shan if (pe->flags & PNV_IODA_PE_BUS_ALL) 813b918c62eSYinghai Lu count = pe->pbus->busn_res.end - pe->pbus->busn_res.start + 1; 814fb446ad0SGavin Shan else 815fb446ad0SGavin Shan count = 1; 816fb446ad0SGavin Shan 817184cd4a3SBenjamin Herrenschmidt switch(count) { 818184cd4a3SBenjamin Herrenschmidt case 1: bcomp = OpalPciBusAll; break; 819184cd4a3SBenjamin Herrenschmidt case 2: bcomp = OpalPciBus7Bits; break; 820184cd4a3SBenjamin Herrenschmidt case 4: bcomp = OpalPciBus6Bits; break; 821184cd4a3SBenjamin Herrenschmidt case 8: bcomp = OpalPciBus5Bits; break; 822184cd4a3SBenjamin Herrenschmidt case 16: bcomp = OpalPciBus4Bits; break; 823184cd4a3SBenjamin Herrenschmidt case 32: bcomp = OpalPciBus3Bits; break; 824184cd4a3SBenjamin Herrenschmidt default: 825781a868fSWei Yang dev_err(&pe->pbus->dev, "Number of subordinate buses %d unsupported\n", 826781a868fSWei Yang count); 827184cd4a3SBenjamin Herrenschmidt /* Do an exact match only */ 828184cd4a3SBenjamin Herrenschmidt bcomp = OpalPciBusAll; 829184cd4a3SBenjamin Herrenschmidt } 830184cd4a3SBenjamin Herrenschmidt rid_end = pe->rid + (count << 8); 831184cd4a3SBenjamin Herrenschmidt } else { 832781a868fSWei Yang #ifdef CONFIG_PCI_IOV 833781a868fSWei Yang if (pe->flags & PNV_IODA_PE_VF) 834781a868fSWei Yang parent = pe->parent_dev; 835781a868fSWei Yang else 836781a868fSWei Yang #endif /* CONFIG_PCI_IOV */ 837184cd4a3SBenjamin Herrenschmidt parent = pe->pdev->bus->self; 838184cd4a3SBenjamin Herrenschmidt bcomp = OpalPciBusAll; 839184cd4a3SBenjamin Herrenschmidt dcomp = OPAL_COMPARE_RID_DEVICE_NUMBER; 840184cd4a3SBenjamin Herrenschmidt fcomp = OPAL_COMPARE_RID_FUNCTION_NUMBER; 841184cd4a3SBenjamin Herrenschmidt rid_end = pe->rid + 1; 842184cd4a3SBenjamin Herrenschmidt } 843184cd4a3SBenjamin Herrenschmidt 844631ad691SGavin Shan /* 845631ad691SGavin Shan * Associate PE in PELT. We need add the PE into the 846631ad691SGavin Shan * corresponding PELT-V as well. Otherwise, the error 847631ad691SGavin Shan * originated from the PE might contribute to other 848631ad691SGavin Shan * PEs. 849631ad691SGavin Shan */ 850184cd4a3SBenjamin Herrenschmidt rc = opal_pci_set_pe(phb->opal_id, pe->pe_number, pe->rid, 851184cd4a3SBenjamin Herrenschmidt bcomp, dcomp, fcomp, OPAL_MAP_PE); 852184cd4a3SBenjamin Herrenschmidt if (rc) { 853184cd4a3SBenjamin Herrenschmidt pe_err(pe, "OPAL error %ld trying to setup PELT table\n", rc); 854184cd4a3SBenjamin Herrenschmidt return -ENXIO; 855184cd4a3SBenjamin Herrenschmidt } 856631ad691SGavin Shan 8575d2aa710SAlistair Popple /* 8585d2aa710SAlistair Popple * Configure PELTV. NPUs don't have a PELTV table so skip 8595d2aa710SAlistair Popple * configuration on them. 8605d2aa710SAlistair Popple */ 8615d2aa710SAlistair Popple if (phb->type != PNV_PHB_NPU) 862b131a842SGavin Shan pnv_ioda_set_peltv(phb, pe, true); 863184cd4a3SBenjamin Herrenschmidt 864184cd4a3SBenjamin Herrenschmidt /* Setup reverse map */ 865184cd4a3SBenjamin Herrenschmidt for (rid = pe->rid; rid < rid_end; rid++) 866184cd4a3SBenjamin Herrenschmidt phb->ioda.pe_rmap[rid] = pe->pe_number; 867184cd4a3SBenjamin Herrenschmidt 868184cd4a3SBenjamin Herrenschmidt /* Setup one MVTs on IODA1 */ 8694773f76bSGavin Shan if (phb->type != PNV_PHB_IODA1) { 8704773f76bSGavin Shan pe->mve_number = 0; 8714773f76bSGavin Shan goto out; 8724773f76bSGavin Shan } 8734773f76bSGavin Shan 874184cd4a3SBenjamin Herrenschmidt pe->mve_number = pe->pe_number; 8754773f76bSGavin Shan rc = opal_pci_set_mve(phb->opal_id, pe->mve_number, pe->pe_number); 8764773f76bSGavin Shan if (rc != OPAL_SUCCESS) { 877184cd4a3SBenjamin Herrenschmidt pe_err(pe, "OPAL error %ld setting up MVE %d\n", 878184cd4a3SBenjamin Herrenschmidt rc, pe->mve_number); 879184cd4a3SBenjamin Herrenschmidt pe->mve_number = -1; 880184cd4a3SBenjamin Herrenschmidt } else { 881184cd4a3SBenjamin Herrenschmidt rc = opal_pci_set_mve_enable(phb->opal_id, 882cee72d5bSBenjamin Herrenschmidt pe->mve_number, OPAL_ENABLE_MVE); 883184cd4a3SBenjamin Herrenschmidt if (rc) { 884184cd4a3SBenjamin Herrenschmidt pe_err(pe, "OPAL error %ld enabling MVE %d\n", 885184cd4a3SBenjamin Herrenschmidt rc, pe->mve_number); 886184cd4a3SBenjamin Herrenschmidt pe->mve_number = -1; 887184cd4a3SBenjamin Herrenschmidt } 888184cd4a3SBenjamin Herrenschmidt } 889184cd4a3SBenjamin Herrenschmidt 8904773f76bSGavin Shan out: 891184cd4a3SBenjamin Herrenschmidt return 0; 892184cd4a3SBenjamin Herrenschmidt } 893184cd4a3SBenjamin Herrenschmidt 894781a868fSWei Yang #ifdef CONFIG_PCI_IOV 895781a868fSWei Yang static int pnv_pci_vf_resource_shift(struct pci_dev *dev, int offset) 896781a868fSWei Yang { 897781a868fSWei Yang struct pci_dn *pdn = pci_get_pdn(dev); 898781a868fSWei Yang int i; 899781a868fSWei Yang struct resource *res, res2; 900781a868fSWei Yang resource_size_t size; 901781a868fSWei Yang u16 num_vfs; 902781a868fSWei Yang 903781a868fSWei Yang if (!dev->is_physfn) 904781a868fSWei Yang return -EINVAL; 905781a868fSWei Yang 906781a868fSWei Yang /* 907781a868fSWei Yang * "offset" is in VFs. The M64 windows are sized so that when they 908781a868fSWei Yang * are segmented, each segment is the same size as the IOV BAR. 909781a868fSWei Yang * Each segment is in a separate PE, and the high order bits of the 910781a868fSWei Yang * address are the PE number. Therefore, each VF's BAR is in a 911781a868fSWei Yang * separate PE, and changing the IOV BAR start address changes the 912781a868fSWei Yang * range of PEs the VFs are in. 913781a868fSWei Yang */ 914781a868fSWei Yang num_vfs = pdn->num_vfs; 915781a868fSWei Yang for (i = 0; i < PCI_SRIOV_NUM_BARS; i++) { 916781a868fSWei Yang res = &dev->resource[i + PCI_IOV_RESOURCES]; 917781a868fSWei Yang if (!res->flags || !res->parent) 918781a868fSWei Yang continue; 919781a868fSWei Yang 920781a868fSWei Yang /* 921781a868fSWei Yang * The actual IOV BAR range is determined by the start address 922781a868fSWei Yang * and the actual size for num_vfs VFs BAR. This check is to 923781a868fSWei Yang * make sure that after shifting, the range will not overlap 924781a868fSWei Yang * with another device. 925781a868fSWei Yang */ 926781a868fSWei Yang size = pci_iov_resource_size(dev, i + PCI_IOV_RESOURCES); 927781a868fSWei Yang res2.flags = res->flags; 928781a868fSWei Yang res2.start = res->start + (size * offset); 929781a868fSWei Yang res2.end = res2.start + (size * num_vfs) - 1; 930781a868fSWei Yang 931781a868fSWei Yang if (res2.end > res->end) { 932781a868fSWei Yang dev_err(&dev->dev, "VF BAR%d: %pR would extend past %pR (trying to enable %d VFs shifted by %d)\n", 933781a868fSWei Yang i, &res2, res, num_vfs, offset); 934781a868fSWei Yang return -EBUSY; 935781a868fSWei Yang } 936781a868fSWei Yang } 937781a868fSWei Yang 938781a868fSWei Yang /* 939781a868fSWei Yang * After doing so, there would be a "hole" in the /proc/iomem when 940781a868fSWei Yang * offset is a positive value. It looks like the device return some 941781a868fSWei Yang * mmio back to the system, which actually no one could use it. 942781a868fSWei Yang */ 943781a868fSWei Yang for (i = 0; i < PCI_SRIOV_NUM_BARS; i++) { 944781a868fSWei Yang res = &dev->resource[i + PCI_IOV_RESOURCES]; 945781a868fSWei Yang if (!res->flags || !res->parent) 946781a868fSWei Yang continue; 947781a868fSWei Yang 948781a868fSWei Yang size = pci_iov_resource_size(dev, i + PCI_IOV_RESOURCES); 949781a868fSWei Yang res2 = *res; 950781a868fSWei Yang res->start += size * offset; 951781a868fSWei Yang 95274703cc4SWei Yang dev_info(&dev->dev, "VF BAR%d: %pR shifted to %pR (%sabling %d VFs shifted by %d)\n", 95374703cc4SWei Yang i, &res2, res, (offset > 0) ? "En" : "Dis", 95474703cc4SWei Yang num_vfs, offset); 955781a868fSWei Yang pci_update_resource(dev, i + PCI_IOV_RESOURCES); 956781a868fSWei Yang } 957781a868fSWei Yang return 0; 958781a868fSWei Yang } 959781a868fSWei Yang #endif /* CONFIG_PCI_IOV */ 960781a868fSWei Yang 961cad5cef6SGreg Kroah-Hartman static struct pnv_ioda_pe *pnv_ioda_setup_dev_PE(struct pci_dev *dev) 962184cd4a3SBenjamin Herrenschmidt { 963184cd4a3SBenjamin Herrenschmidt struct pci_controller *hose = pci_bus_to_host(dev->bus); 964184cd4a3SBenjamin Herrenschmidt struct pnv_phb *phb = hose->private_data; 965b72c1f65SBenjamin Herrenschmidt struct pci_dn *pdn = pci_get_pdn(dev); 966184cd4a3SBenjamin Herrenschmidt struct pnv_ioda_pe *pe; 967184cd4a3SBenjamin Herrenschmidt 968184cd4a3SBenjamin Herrenschmidt if (!pdn) { 969184cd4a3SBenjamin Herrenschmidt pr_err("%s: Device tree node not associated properly\n", 970184cd4a3SBenjamin Herrenschmidt pci_name(dev)); 971184cd4a3SBenjamin Herrenschmidt return NULL; 972184cd4a3SBenjamin Herrenschmidt } 973184cd4a3SBenjamin Herrenschmidt if (pdn->pe_number != IODA_INVALID_PE) 974184cd4a3SBenjamin Herrenschmidt return NULL; 975184cd4a3SBenjamin Herrenschmidt 9761e916772SGavin Shan pe = pnv_ioda_alloc_pe(phb); 9771e916772SGavin Shan if (!pe) { 978184cd4a3SBenjamin Herrenschmidt pr_warning("%s: Not enough PE# available, disabling device\n", 979184cd4a3SBenjamin Herrenschmidt pci_name(dev)); 980184cd4a3SBenjamin Herrenschmidt return NULL; 981184cd4a3SBenjamin Herrenschmidt } 982184cd4a3SBenjamin Herrenschmidt 983184cd4a3SBenjamin Herrenschmidt /* NOTE: We get only one ref to the pci_dev for the pdn, not for the 984184cd4a3SBenjamin Herrenschmidt * pointer in the PE data structure, both should be destroyed at the 985184cd4a3SBenjamin Herrenschmidt * same time. However, this needs to be looked at more closely again 986184cd4a3SBenjamin Herrenschmidt * once we actually start removing things (Hotplug, SR-IOV, ...) 987184cd4a3SBenjamin Herrenschmidt * 988184cd4a3SBenjamin Herrenschmidt * At some point we want to remove the PDN completely anyways 989184cd4a3SBenjamin Herrenschmidt */ 990184cd4a3SBenjamin Herrenschmidt pci_dev_get(dev); 991184cd4a3SBenjamin Herrenschmidt pdn->pcidev = dev; 9921e916772SGavin Shan pdn->pe_number = pe->pe_number; 9935d2aa710SAlistair Popple pe->flags = PNV_IODA_PE_DEV; 994184cd4a3SBenjamin Herrenschmidt pe->pdev = dev; 995184cd4a3SBenjamin Herrenschmidt pe->pbus = NULL; 996184cd4a3SBenjamin Herrenschmidt pe->mve_number = -1; 997184cd4a3SBenjamin Herrenschmidt pe->rid = dev->bus->number << 8 | pdn->devfn; 998184cd4a3SBenjamin Herrenschmidt 999184cd4a3SBenjamin Herrenschmidt pe_info(pe, "Associated device to PE\n"); 1000184cd4a3SBenjamin Herrenschmidt 1001184cd4a3SBenjamin Herrenschmidt if (pnv_ioda_configure_pe(phb, pe)) { 1002184cd4a3SBenjamin Herrenschmidt /* XXX What do we do here ? */ 10031e916772SGavin Shan pnv_ioda_free_pe(pe); 1004184cd4a3SBenjamin Herrenschmidt pdn->pe_number = IODA_INVALID_PE; 1005184cd4a3SBenjamin Herrenschmidt pe->pdev = NULL; 1006184cd4a3SBenjamin Herrenschmidt pci_dev_put(dev); 1007184cd4a3SBenjamin Herrenschmidt return NULL; 1008184cd4a3SBenjamin Herrenschmidt } 1009184cd4a3SBenjamin Herrenschmidt 10101d4e89cfSAlexey Kardashevskiy /* Put PE to the list */ 10111d4e89cfSAlexey Kardashevskiy list_add_tail(&pe->list, &phb->ioda.pe_list); 10121d4e89cfSAlexey Kardashevskiy 1013184cd4a3SBenjamin Herrenschmidt return pe; 1014184cd4a3SBenjamin Herrenschmidt } 1015184cd4a3SBenjamin Herrenschmidt 1016184cd4a3SBenjamin Herrenschmidt static void pnv_ioda_setup_same_PE(struct pci_bus *bus, struct pnv_ioda_pe *pe) 1017184cd4a3SBenjamin Herrenschmidt { 1018184cd4a3SBenjamin Herrenschmidt struct pci_dev *dev; 1019184cd4a3SBenjamin Herrenschmidt 1020184cd4a3SBenjamin Herrenschmidt list_for_each_entry(dev, &bus->devices, bus_list) { 1021b72c1f65SBenjamin Herrenschmidt struct pci_dn *pdn = pci_get_pdn(dev); 1022184cd4a3SBenjamin Herrenschmidt 1023184cd4a3SBenjamin Herrenschmidt if (pdn == NULL) { 1024184cd4a3SBenjamin Herrenschmidt pr_warn("%s: No device node associated with device !\n", 1025184cd4a3SBenjamin Herrenschmidt pci_name(dev)); 1026184cd4a3SBenjamin Herrenschmidt continue; 1027184cd4a3SBenjamin Herrenschmidt } 1028ccd1c191SGavin Shan 1029ccd1c191SGavin Shan /* 1030ccd1c191SGavin Shan * In partial hotplug case, the PCI device might be still 1031ccd1c191SGavin Shan * associated with the PE and needn't attach it to the PE 1032ccd1c191SGavin Shan * again. 1033ccd1c191SGavin Shan */ 1034ccd1c191SGavin Shan if (pdn->pe_number != IODA_INVALID_PE) 1035ccd1c191SGavin Shan continue; 1036ccd1c191SGavin Shan 1037c5f7700bSGavin Shan pe->device_count++; 103894973b24SAlistair Popple pdn->pcidev = dev; 1039184cd4a3SBenjamin Herrenschmidt pdn->pe_number = pe->pe_number; 1040fb446ad0SGavin Shan if ((pe->flags & PNV_IODA_PE_BUS_ALL) && dev->subordinate) 1041184cd4a3SBenjamin Herrenschmidt pnv_ioda_setup_same_PE(dev->subordinate, pe); 1042184cd4a3SBenjamin Herrenschmidt } 1043184cd4a3SBenjamin Herrenschmidt } 1044184cd4a3SBenjamin Herrenschmidt 1045fb446ad0SGavin Shan /* 1046fb446ad0SGavin Shan * There're 2 types of PCI bus sensitive PEs: One that is compromised of 1047fb446ad0SGavin Shan * single PCI bus. Another one that contains the primary PCI bus and its 1048fb446ad0SGavin Shan * subordinate PCI devices and buses. The second type of PE is normally 1049fb446ad0SGavin Shan * orgiriated by PCIe-to-PCI bridge or PLX switch downstream ports. 1050fb446ad0SGavin Shan */ 10511e916772SGavin Shan static struct pnv_ioda_pe *pnv_ioda_setup_bus_PE(struct pci_bus *bus, bool all) 1052184cd4a3SBenjamin Herrenschmidt { 1053fb446ad0SGavin Shan struct pci_controller *hose = pci_bus_to_host(bus); 1054184cd4a3SBenjamin Herrenschmidt struct pnv_phb *phb = hose->private_data; 10551e916772SGavin Shan struct pnv_ioda_pe *pe = NULL; 1056ccd1c191SGavin Shan unsigned int pe_num; 1057ccd1c191SGavin Shan 1058ccd1c191SGavin Shan /* 1059ccd1c191SGavin Shan * In partial hotplug case, the PE instance might be still alive. 1060ccd1c191SGavin Shan * We should reuse it instead of allocating a new one. 1061ccd1c191SGavin Shan */ 1062ccd1c191SGavin Shan pe_num = phb->ioda.pe_rmap[bus->number << 8]; 1063ccd1c191SGavin Shan if (pe_num != IODA_INVALID_PE) { 1064ccd1c191SGavin Shan pe = &phb->ioda.pe_array[pe_num]; 1065ccd1c191SGavin Shan pnv_ioda_setup_same_PE(bus, pe); 1066ccd1c191SGavin Shan return NULL; 1067ccd1c191SGavin Shan } 1068184cd4a3SBenjamin Herrenschmidt 106963803c39SGavin Shan /* PE number for root bus should have been reserved */ 107063803c39SGavin Shan if (pci_is_root_bus(bus) && 107163803c39SGavin Shan phb->ioda.root_pe_idx != IODA_INVALID_PE) 107263803c39SGavin Shan pe = &phb->ioda.pe_array[phb->ioda.root_pe_idx]; 107363803c39SGavin Shan 1074262af557SGuo Chao /* Check if PE is determined by M64 */ 107563803c39SGavin Shan if (!pe && phb->pick_m64_pe) 10761e916772SGavin Shan pe = phb->pick_m64_pe(bus, all); 1077262af557SGuo Chao 1078262af557SGuo Chao /* The PE number isn't pinned by M64 */ 10791e916772SGavin Shan if (!pe) 10801e916772SGavin Shan pe = pnv_ioda_alloc_pe(phb); 1081262af557SGuo Chao 10821e916772SGavin Shan if (!pe) { 1083fb446ad0SGavin Shan pr_warning("%s: Not enough PE# available for PCI bus %04x:%02x\n", 1084fb446ad0SGavin Shan __func__, pci_domain_nr(bus), bus->number); 10851e916772SGavin Shan return NULL; 1086184cd4a3SBenjamin Herrenschmidt } 1087184cd4a3SBenjamin Herrenschmidt 1088262af557SGuo Chao pe->flags |= (all ? PNV_IODA_PE_BUS_ALL : PNV_IODA_PE_BUS); 1089184cd4a3SBenjamin Herrenschmidt pe->pbus = bus; 1090184cd4a3SBenjamin Herrenschmidt pe->pdev = NULL; 1091184cd4a3SBenjamin Herrenschmidt pe->mve_number = -1; 1092b918c62eSYinghai Lu pe->rid = bus->busn_res.start << 8; 1093184cd4a3SBenjamin Herrenschmidt 1094fb446ad0SGavin Shan if (all) 1095fb446ad0SGavin Shan pe_info(pe, "Secondary bus %d..%d associated with PE#%d\n", 10961e916772SGavin Shan bus->busn_res.start, bus->busn_res.end, pe->pe_number); 1097fb446ad0SGavin Shan else 1098fb446ad0SGavin Shan pe_info(pe, "Secondary bus %d associated with PE#%d\n", 10991e916772SGavin Shan bus->busn_res.start, pe->pe_number); 1100184cd4a3SBenjamin Herrenschmidt 1101184cd4a3SBenjamin Herrenschmidt if (pnv_ioda_configure_pe(phb, pe)) { 1102184cd4a3SBenjamin Herrenschmidt /* XXX What do we do here ? */ 11031e916772SGavin Shan pnv_ioda_free_pe(pe); 1104184cd4a3SBenjamin Herrenschmidt pe->pbus = NULL; 11051e916772SGavin Shan return NULL; 1106184cd4a3SBenjamin Herrenschmidt } 1107184cd4a3SBenjamin Herrenschmidt 1108184cd4a3SBenjamin Herrenschmidt /* Associate it with all child devices */ 1109184cd4a3SBenjamin Herrenschmidt pnv_ioda_setup_same_PE(bus, pe); 1110184cd4a3SBenjamin Herrenschmidt 11117ebdf956SGavin Shan /* Put PE to the list */ 11127ebdf956SGavin Shan list_add_tail(&pe->list, &phb->ioda.pe_list); 11131e916772SGavin Shan 11141e916772SGavin Shan return pe; 1115184cd4a3SBenjamin Herrenschmidt } 1116184cd4a3SBenjamin Herrenschmidt 1117b521549aSAlistair Popple static struct pnv_ioda_pe *pnv_ioda_setup_npu_PE(struct pci_dev *npu_pdev) 11185d2aa710SAlistair Popple { 1119b521549aSAlistair Popple int pe_num, found_pe = false, rc; 1120b521549aSAlistair Popple long rid; 1121b521549aSAlistair Popple struct pnv_ioda_pe *pe; 1122b521549aSAlistair Popple struct pci_dev *gpu_pdev; 1123b521549aSAlistair Popple struct pci_dn *npu_pdn; 1124b521549aSAlistair Popple struct pci_controller *hose = pci_bus_to_host(npu_pdev->bus); 1125b521549aSAlistair Popple struct pnv_phb *phb = hose->private_data; 1126b521549aSAlistair Popple 1127b521549aSAlistair Popple /* 1128b521549aSAlistair Popple * Due to a hardware errata PE#0 on the NPU is reserved for 1129b521549aSAlistair Popple * error handling. This means we only have three PEs remaining 1130b521549aSAlistair Popple * which need to be assigned to four links, implying some 1131b521549aSAlistair Popple * links must share PEs. 1132b521549aSAlistair Popple * 1133b521549aSAlistair Popple * To achieve this we assign PEs such that NPUs linking the 1134b521549aSAlistair Popple * same GPU get assigned the same PE. 1135b521549aSAlistair Popple */ 1136b521549aSAlistair Popple gpu_pdev = pnv_pci_get_gpu_dev(npu_pdev); 113792b8f137SGavin Shan for (pe_num = 0; pe_num < phb->ioda.total_pe_num; pe_num++) { 1138b521549aSAlistair Popple pe = &phb->ioda.pe_array[pe_num]; 1139b521549aSAlistair Popple if (!pe->pdev) 1140b521549aSAlistair Popple continue; 1141b521549aSAlistair Popple 1142b521549aSAlistair Popple if (pnv_pci_get_gpu_dev(pe->pdev) == gpu_pdev) { 1143b521549aSAlistair Popple /* 1144b521549aSAlistair Popple * This device has the same peer GPU so should 1145b521549aSAlistair Popple * be assigned the same PE as the existing 1146b521549aSAlistair Popple * peer NPU. 1147b521549aSAlistair Popple */ 1148b521549aSAlistair Popple dev_info(&npu_pdev->dev, 1149b521549aSAlistair Popple "Associating to existing PE %d\n", pe_num); 1150b521549aSAlistair Popple pci_dev_get(npu_pdev); 1151b521549aSAlistair Popple npu_pdn = pci_get_pdn(npu_pdev); 1152b521549aSAlistair Popple rid = npu_pdev->bus->number << 8 | npu_pdn->devfn; 1153b521549aSAlistair Popple npu_pdn->pcidev = npu_pdev; 1154b521549aSAlistair Popple npu_pdn->pe_number = pe_num; 1155b521549aSAlistair Popple phb->ioda.pe_rmap[rid] = pe->pe_number; 1156b521549aSAlistair Popple 1157b521549aSAlistair Popple /* Map the PE to this link */ 1158b521549aSAlistair Popple rc = opal_pci_set_pe(phb->opal_id, pe_num, rid, 1159b521549aSAlistair Popple OpalPciBusAll, 1160b521549aSAlistair Popple OPAL_COMPARE_RID_DEVICE_NUMBER, 1161b521549aSAlistair Popple OPAL_COMPARE_RID_FUNCTION_NUMBER, 1162b521549aSAlistair Popple OPAL_MAP_PE); 1163b521549aSAlistair Popple WARN_ON(rc != OPAL_SUCCESS); 1164b521549aSAlistair Popple found_pe = true; 1165b521549aSAlistair Popple break; 1166b521549aSAlistair Popple } 1167b521549aSAlistair Popple } 1168b521549aSAlistair Popple 1169b521549aSAlistair Popple if (!found_pe) 1170b521549aSAlistair Popple /* 1171b521549aSAlistair Popple * Could not find an existing PE so allocate a new 1172b521549aSAlistair Popple * one. 1173b521549aSAlistair Popple */ 1174b521549aSAlistair Popple return pnv_ioda_setup_dev_PE(npu_pdev); 1175b521549aSAlistair Popple else 1176b521549aSAlistair Popple return pe; 1177b521549aSAlistair Popple } 1178b521549aSAlistair Popple 1179b521549aSAlistair Popple static void pnv_ioda_setup_npu_PEs(struct pci_bus *bus) 1180b521549aSAlistair Popple { 11815d2aa710SAlistair Popple struct pci_dev *pdev; 11825d2aa710SAlistair Popple 11835d2aa710SAlistair Popple list_for_each_entry(pdev, &bus->devices, bus_list) 1184b521549aSAlistair Popple pnv_ioda_setup_npu_PE(pdev); 11855d2aa710SAlistair Popple } 11865d2aa710SAlistair Popple 1187cad5cef6SGreg Kroah-Hartman static void pnv_pci_ioda_setup_PEs(void) 1188fb446ad0SGavin Shan { 1189fb446ad0SGavin Shan struct pci_controller *hose, *tmp; 1190262af557SGuo Chao struct pnv_phb *phb; 1191fb446ad0SGavin Shan 1192fb446ad0SGavin Shan list_for_each_entry_safe(hose, tmp, &hose_list, list_node) { 1193262af557SGuo Chao phb = hose->private_data; 119408f48f32SAlistair Popple if (phb->type == PNV_PHB_NPU) { 119508f48f32SAlistair Popple /* PE#0 is needed for error reporting */ 119608f48f32SAlistair Popple pnv_ioda_reserve_pe(phb, 0); 1197b521549aSAlistair Popple pnv_ioda_setup_npu_PEs(hose->bus); 1198ccd1c191SGavin Shan } 1199fb446ad0SGavin Shan } 1200fb446ad0SGavin Shan } 1201184cd4a3SBenjamin Herrenschmidt 1202a8b2f828SGavin Shan #ifdef CONFIG_PCI_IOV 1203ee8222feSWei Yang static int pnv_pci_vf_release_m64(struct pci_dev *pdev, u16 num_vfs) 1204781a868fSWei Yang { 1205781a868fSWei Yang struct pci_bus *bus; 1206781a868fSWei Yang struct pci_controller *hose; 1207781a868fSWei Yang struct pnv_phb *phb; 1208781a868fSWei Yang struct pci_dn *pdn; 120902639b0eSWei Yang int i, j; 1210ee8222feSWei Yang int m64_bars; 1211781a868fSWei Yang 1212781a868fSWei Yang bus = pdev->bus; 1213781a868fSWei Yang hose = pci_bus_to_host(bus); 1214781a868fSWei Yang phb = hose->private_data; 1215781a868fSWei Yang pdn = pci_get_pdn(pdev); 1216781a868fSWei Yang 1217ee8222feSWei Yang if (pdn->m64_single_mode) 1218ee8222feSWei Yang m64_bars = num_vfs; 1219ee8222feSWei Yang else 1220ee8222feSWei Yang m64_bars = 1; 1221ee8222feSWei Yang 122202639b0eSWei Yang for (i = 0; i < PCI_SRIOV_NUM_BARS; i++) 1223ee8222feSWei Yang for (j = 0; j < m64_bars; j++) { 1224ee8222feSWei Yang if (pdn->m64_map[j][i] == IODA_INVALID_M64) 1225781a868fSWei Yang continue; 1226781a868fSWei Yang opal_pci_phb_mmio_enable(phb->opal_id, 1227ee8222feSWei Yang OPAL_M64_WINDOW_TYPE, pdn->m64_map[j][i], 0); 1228ee8222feSWei Yang clear_bit(pdn->m64_map[j][i], &phb->ioda.m64_bar_alloc); 1229ee8222feSWei Yang pdn->m64_map[j][i] = IODA_INVALID_M64; 1230781a868fSWei Yang } 1231781a868fSWei Yang 1232ee8222feSWei Yang kfree(pdn->m64_map); 1233781a868fSWei Yang return 0; 1234781a868fSWei Yang } 1235781a868fSWei Yang 123602639b0eSWei Yang static int pnv_pci_vf_assign_m64(struct pci_dev *pdev, u16 num_vfs) 1237781a868fSWei Yang { 1238781a868fSWei Yang struct pci_bus *bus; 1239781a868fSWei Yang struct pci_controller *hose; 1240781a868fSWei Yang struct pnv_phb *phb; 1241781a868fSWei Yang struct pci_dn *pdn; 1242781a868fSWei Yang unsigned int win; 1243781a868fSWei Yang struct resource *res; 124402639b0eSWei Yang int i, j; 1245781a868fSWei Yang int64_t rc; 124602639b0eSWei Yang int total_vfs; 124702639b0eSWei Yang resource_size_t size, start; 124802639b0eSWei Yang int pe_num; 1249ee8222feSWei Yang int m64_bars; 1250781a868fSWei Yang 1251781a868fSWei Yang bus = pdev->bus; 1252781a868fSWei Yang hose = pci_bus_to_host(bus); 1253781a868fSWei Yang phb = hose->private_data; 1254781a868fSWei Yang pdn = pci_get_pdn(pdev); 125502639b0eSWei Yang total_vfs = pci_sriov_get_totalvfs(pdev); 1256781a868fSWei Yang 1257ee8222feSWei Yang if (pdn->m64_single_mode) 1258ee8222feSWei Yang m64_bars = num_vfs; 1259ee8222feSWei Yang else 1260ee8222feSWei Yang m64_bars = 1; 126102639b0eSWei Yang 1262ee8222feSWei Yang pdn->m64_map = kmalloc(sizeof(*pdn->m64_map) * m64_bars, GFP_KERNEL); 1263ee8222feSWei Yang if (!pdn->m64_map) 1264ee8222feSWei Yang return -ENOMEM; 1265ee8222feSWei Yang /* Initialize the m64_map to IODA_INVALID_M64 */ 1266ee8222feSWei Yang for (i = 0; i < m64_bars ; i++) 1267ee8222feSWei Yang for (j = 0; j < PCI_SRIOV_NUM_BARS; j++) 1268ee8222feSWei Yang pdn->m64_map[i][j] = IODA_INVALID_M64; 1269ee8222feSWei Yang 1270781a868fSWei Yang 1271781a868fSWei Yang for (i = 0; i < PCI_SRIOV_NUM_BARS; i++) { 1272781a868fSWei Yang res = &pdev->resource[i + PCI_IOV_RESOURCES]; 1273781a868fSWei Yang if (!res->flags || !res->parent) 1274781a868fSWei Yang continue; 1275781a868fSWei Yang 1276ee8222feSWei Yang for (j = 0; j < m64_bars; j++) { 1277781a868fSWei Yang do { 1278781a868fSWei Yang win = find_next_zero_bit(&phb->ioda.m64_bar_alloc, 1279781a868fSWei Yang phb->ioda.m64_bar_idx + 1, 0); 1280781a868fSWei Yang 1281781a868fSWei Yang if (win >= phb->ioda.m64_bar_idx + 1) 1282781a868fSWei Yang goto m64_failed; 1283781a868fSWei Yang } while (test_and_set_bit(win, &phb->ioda.m64_bar_alloc)); 1284781a868fSWei Yang 1285ee8222feSWei Yang pdn->m64_map[j][i] = win; 128602639b0eSWei Yang 1287ee8222feSWei Yang if (pdn->m64_single_mode) { 128802639b0eSWei Yang size = pci_iov_resource_size(pdev, 128902639b0eSWei Yang PCI_IOV_RESOURCES + i); 129002639b0eSWei Yang start = res->start + size * j; 129102639b0eSWei Yang } else { 129202639b0eSWei Yang size = resource_size(res); 129302639b0eSWei Yang start = res->start; 129402639b0eSWei Yang } 1295781a868fSWei Yang 1296781a868fSWei Yang /* Map the M64 here */ 1297ee8222feSWei Yang if (pdn->m64_single_mode) { 1298be283eebSWei Yang pe_num = pdn->pe_num_map[j]; 129902639b0eSWei Yang rc = opal_pci_map_pe_mmio_window(phb->opal_id, 130002639b0eSWei Yang pe_num, OPAL_M64_WINDOW_TYPE, 1301ee8222feSWei Yang pdn->m64_map[j][i], 0); 130202639b0eSWei Yang } 130302639b0eSWei Yang 1304781a868fSWei Yang rc = opal_pci_set_phb_mem_window(phb->opal_id, 1305781a868fSWei Yang OPAL_M64_WINDOW_TYPE, 1306ee8222feSWei Yang pdn->m64_map[j][i], 130702639b0eSWei Yang start, 1308781a868fSWei Yang 0, /* unused */ 130902639b0eSWei Yang size); 131002639b0eSWei Yang 131102639b0eSWei Yang 1312781a868fSWei Yang if (rc != OPAL_SUCCESS) { 1313781a868fSWei Yang dev_err(&pdev->dev, "Failed to map M64 window #%d: %lld\n", 1314781a868fSWei Yang win, rc); 1315781a868fSWei Yang goto m64_failed; 1316781a868fSWei Yang } 1317781a868fSWei Yang 1318ee8222feSWei Yang if (pdn->m64_single_mode) 1319781a868fSWei Yang rc = opal_pci_phb_mmio_enable(phb->opal_id, 1320ee8222feSWei Yang OPAL_M64_WINDOW_TYPE, pdn->m64_map[j][i], 2); 132102639b0eSWei Yang else 132202639b0eSWei Yang rc = opal_pci_phb_mmio_enable(phb->opal_id, 1323ee8222feSWei Yang OPAL_M64_WINDOW_TYPE, pdn->m64_map[j][i], 1); 132402639b0eSWei Yang 1325781a868fSWei Yang if (rc != OPAL_SUCCESS) { 1326781a868fSWei Yang dev_err(&pdev->dev, "Failed to enable M64 window #%d: %llx\n", 1327781a868fSWei Yang win, rc); 1328781a868fSWei Yang goto m64_failed; 1329781a868fSWei Yang } 1330781a868fSWei Yang } 133102639b0eSWei Yang } 1332781a868fSWei Yang return 0; 1333781a868fSWei Yang 1334781a868fSWei Yang m64_failed: 1335ee8222feSWei Yang pnv_pci_vf_release_m64(pdev, num_vfs); 1336781a868fSWei Yang return -EBUSY; 1337781a868fSWei Yang } 1338781a868fSWei Yang 1339c035e37bSAlexey Kardashevskiy static long pnv_pci_ioda2_unset_window(struct iommu_table_group *table_group, 1340c035e37bSAlexey Kardashevskiy int num); 1341c035e37bSAlexey Kardashevskiy static void pnv_pci_ioda2_set_bypass(struct pnv_ioda_pe *pe, bool enable); 1342c035e37bSAlexey Kardashevskiy 1343781a868fSWei Yang static void pnv_pci_ioda2_release_dma_pe(struct pci_dev *dev, struct pnv_ioda_pe *pe) 1344781a868fSWei Yang { 1345781a868fSWei Yang struct iommu_table *tbl; 1346781a868fSWei Yang int64_t rc; 1347781a868fSWei Yang 1348b348aa65SAlexey Kardashevskiy tbl = pe->table_group.tables[0]; 1349c035e37bSAlexey Kardashevskiy rc = pnv_pci_ioda2_unset_window(&pe->table_group, 0); 1350781a868fSWei Yang if (rc) 1351781a868fSWei Yang pe_warn(pe, "OPAL error %ld release DMA window\n", rc); 1352781a868fSWei Yang 1353c035e37bSAlexey Kardashevskiy pnv_pci_ioda2_set_bypass(pe, false); 13540eaf4defSAlexey Kardashevskiy if (pe->table_group.group) { 13550eaf4defSAlexey Kardashevskiy iommu_group_put(pe->table_group.group); 13560eaf4defSAlexey Kardashevskiy BUG_ON(pe->table_group.group); 1357ac9a5889SAlexey Kardashevskiy } 1358aca6913fSAlexey Kardashevskiy pnv_pci_ioda2_table_free_pages(tbl); 1359781a868fSWei Yang iommu_free_table(tbl, of_node_full_name(dev->dev.of_node)); 1360781a868fSWei Yang } 1361781a868fSWei Yang 1362ee8222feSWei Yang static void pnv_ioda_release_vf_PE(struct pci_dev *pdev) 1363781a868fSWei Yang { 1364781a868fSWei Yang struct pci_bus *bus; 1365781a868fSWei Yang struct pci_controller *hose; 1366781a868fSWei Yang struct pnv_phb *phb; 1367781a868fSWei Yang struct pnv_ioda_pe *pe, *pe_n; 1368781a868fSWei Yang struct pci_dn *pdn; 1369781a868fSWei Yang 1370781a868fSWei Yang bus = pdev->bus; 1371781a868fSWei Yang hose = pci_bus_to_host(bus); 1372781a868fSWei Yang phb = hose->private_data; 137302639b0eSWei Yang pdn = pci_get_pdn(pdev); 1374781a868fSWei Yang 1375781a868fSWei Yang if (!pdev->is_physfn) 1376781a868fSWei Yang return; 1377781a868fSWei Yang 1378781a868fSWei Yang list_for_each_entry_safe(pe, pe_n, &phb->ioda.pe_list, list) { 1379781a868fSWei Yang if (pe->parent_dev != pdev) 1380781a868fSWei Yang continue; 1381781a868fSWei Yang 1382781a868fSWei Yang pnv_pci_ioda2_release_dma_pe(pdev, pe); 1383781a868fSWei Yang 1384781a868fSWei Yang /* Remove from list */ 1385781a868fSWei Yang mutex_lock(&phb->ioda.pe_list_mutex); 1386781a868fSWei Yang list_del(&pe->list); 1387781a868fSWei Yang mutex_unlock(&phb->ioda.pe_list_mutex); 1388781a868fSWei Yang 1389781a868fSWei Yang pnv_ioda_deconfigure_pe(phb, pe); 1390781a868fSWei Yang 13911e916772SGavin Shan pnv_ioda_free_pe(pe); 1392781a868fSWei Yang } 1393781a868fSWei Yang } 1394781a868fSWei Yang 1395781a868fSWei Yang void pnv_pci_sriov_disable(struct pci_dev *pdev) 1396781a868fSWei Yang { 1397781a868fSWei Yang struct pci_bus *bus; 1398781a868fSWei Yang struct pci_controller *hose; 1399781a868fSWei Yang struct pnv_phb *phb; 14001e916772SGavin Shan struct pnv_ioda_pe *pe; 1401781a868fSWei Yang struct pci_dn *pdn; 1402781a868fSWei Yang struct pci_sriov *iov; 1403be283eebSWei Yang u16 num_vfs, i; 1404781a868fSWei Yang 1405781a868fSWei Yang bus = pdev->bus; 1406781a868fSWei Yang hose = pci_bus_to_host(bus); 1407781a868fSWei Yang phb = hose->private_data; 1408781a868fSWei Yang pdn = pci_get_pdn(pdev); 1409781a868fSWei Yang iov = pdev->sriov; 1410781a868fSWei Yang num_vfs = pdn->num_vfs; 1411781a868fSWei Yang 1412781a868fSWei Yang /* Release VF PEs */ 1413ee8222feSWei Yang pnv_ioda_release_vf_PE(pdev); 1414781a868fSWei Yang 1415781a868fSWei Yang if (phb->type == PNV_PHB_IODA2) { 1416ee8222feSWei Yang if (!pdn->m64_single_mode) 1417be283eebSWei Yang pnv_pci_vf_resource_shift(pdev, -*pdn->pe_num_map); 1418781a868fSWei Yang 1419781a868fSWei Yang /* Release M64 windows */ 1420ee8222feSWei Yang pnv_pci_vf_release_m64(pdev, num_vfs); 1421781a868fSWei Yang 1422781a868fSWei Yang /* Release PE numbers */ 1423be283eebSWei Yang if (pdn->m64_single_mode) { 1424be283eebSWei Yang for (i = 0; i < num_vfs; i++) { 14251e916772SGavin Shan if (pdn->pe_num_map[i] == IODA_INVALID_PE) 14261e916772SGavin Shan continue; 14271e916772SGavin Shan 14281e916772SGavin Shan pe = &phb->ioda.pe_array[pdn->pe_num_map[i]]; 14291e916772SGavin Shan pnv_ioda_free_pe(pe); 1430be283eebSWei Yang } 1431be283eebSWei Yang } else 1432be283eebSWei Yang bitmap_clear(phb->ioda.pe_alloc, *pdn->pe_num_map, num_vfs); 1433be283eebSWei Yang /* Releasing pe_num_map */ 1434be283eebSWei Yang kfree(pdn->pe_num_map); 1435781a868fSWei Yang } 1436781a868fSWei Yang } 1437781a868fSWei Yang 1438781a868fSWei Yang static void pnv_pci_ioda2_setup_dma_pe(struct pnv_phb *phb, 1439781a868fSWei Yang struct pnv_ioda_pe *pe); 1440781a868fSWei Yang static void pnv_ioda_setup_vf_PE(struct pci_dev *pdev, u16 num_vfs) 1441781a868fSWei Yang { 1442781a868fSWei Yang struct pci_bus *bus; 1443781a868fSWei Yang struct pci_controller *hose; 1444781a868fSWei Yang struct pnv_phb *phb; 1445781a868fSWei Yang struct pnv_ioda_pe *pe; 1446781a868fSWei Yang int pe_num; 1447781a868fSWei Yang u16 vf_index; 1448781a868fSWei Yang struct pci_dn *pdn; 1449781a868fSWei Yang 1450781a868fSWei Yang bus = pdev->bus; 1451781a868fSWei Yang hose = pci_bus_to_host(bus); 1452781a868fSWei Yang phb = hose->private_data; 1453781a868fSWei Yang pdn = pci_get_pdn(pdev); 1454781a868fSWei Yang 1455781a868fSWei Yang if (!pdev->is_physfn) 1456781a868fSWei Yang return; 1457781a868fSWei Yang 1458781a868fSWei Yang /* Reserve PE for each VF */ 1459781a868fSWei Yang for (vf_index = 0; vf_index < num_vfs; vf_index++) { 1460be283eebSWei Yang if (pdn->m64_single_mode) 1461be283eebSWei Yang pe_num = pdn->pe_num_map[vf_index]; 1462be283eebSWei Yang else 1463be283eebSWei Yang pe_num = *pdn->pe_num_map + vf_index; 1464781a868fSWei Yang 1465781a868fSWei Yang pe = &phb->ioda.pe_array[pe_num]; 1466781a868fSWei Yang pe->pe_number = pe_num; 1467781a868fSWei Yang pe->phb = phb; 1468781a868fSWei Yang pe->flags = PNV_IODA_PE_VF; 1469781a868fSWei Yang pe->pbus = NULL; 1470781a868fSWei Yang pe->parent_dev = pdev; 1471781a868fSWei Yang pe->mve_number = -1; 1472781a868fSWei Yang pe->rid = (pci_iov_virtfn_bus(pdev, vf_index) << 8) | 1473781a868fSWei Yang pci_iov_virtfn_devfn(pdev, vf_index); 1474781a868fSWei Yang 1475781a868fSWei Yang pe_info(pe, "VF %04d:%02d:%02d.%d associated with PE#%d\n", 1476781a868fSWei Yang hose->global_number, pdev->bus->number, 1477781a868fSWei Yang PCI_SLOT(pci_iov_virtfn_devfn(pdev, vf_index)), 1478781a868fSWei Yang PCI_FUNC(pci_iov_virtfn_devfn(pdev, vf_index)), pe_num); 1479781a868fSWei Yang 1480781a868fSWei Yang if (pnv_ioda_configure_pe(phb, pe)) { 1481781a868fSWei Yang /* XXX What do we do here ? */ 14821e916772SGavin Shan pnv_ioda_free_pe(pe); 1483781a868fSWei Yang pe->pdev = NULL; 1484781a868fSWei Yang continue; 1485781a868fSWei Yang } 1486781a868fSWei Yang 1487781a868fSWei Yang /* Put PE to the list */ 1488781a868fSWei Yang mutex_lock(&phb->ioda.pe_list_mutex); 1489781a868fSWei Yang list_add_tail(&pe->list, &phb->ioda.pe_list); 1490781a868fSWei Yang mutex_unlock(&phb->ioda.pe_list_mutex); 1491781a868fSWei Yang 1492781a868fSWei Yang pnv_pci_ioda2_setup_dma_pe(phb, pe); 1493781a868fSWei Yang } 1494781a868fSWei Yang } 1495781a868fSWei Yang 1496781a868fSWei Yang int pnv_pci_sriov_enable(struct pci_dev *pdev, u16 num_vfs) 1497781a868fSWei Yang { 1498781a868fSWei Yang struct pci_bus *bus; 1499781a868fSWei Yang struct pci_controller *hose; 1500781a868fSWei Yang struct pnv_phb *phb; 15011e916772SGavin Shan struct pnv_ioda_pe *pe; 1502781a868fSWei Yang struct pci_dn *pdn; 1503781a868fSWei Yang int ret; 1504be283eebSWei Yang u16 i; 1505781a868fSWei Yang 1506781a868fSWei Yang bus = pdev->bus; 1507781a868fSWei Yang hose = pci_bus_to_host(bus); 1508781a868fSWei Yang phb = hose->private_data; 1509781a868fSWei Yang pdn = pci_get_pdn(pdev); 1510781a868fSWei Yang 1511781a868fSWei Yang if (phb->type == PNV_PHB_IODA2) { 1512b0331854SWei Yang if (!pdn->vfs_expanded) { 1513b0331854SWei Yang dev_info(&pdev->dev, "don't support this SRIOV device" 1514b0331854SWei Yang " with non 64bit-prefetchable IOV BAR\n"); 1515b0331854SWei Yang return -ENOSPC; 1516b0331854SWei Yang } 1517b0331854SWei Yang 1518ee8222feSWei Yang /* 1519ee8222feSWei Yang * When M64 BARs functions in Single PE mode, the number of VFs 1520ee8222feSWei Yang * could be enabled must be less than the number of M64 BARs. 1521ee8222feSWei Yang */ 1522ee8222feSWei Yang if (pdn->m64_single_mode && num_vfs > phb->ioda.m64_bar_idx) { 1523ee8222feSWei Yang dev_info(&pdev->dev, "Not enough M64 BAR for VFs\n"); 1524ee8222feSWei Yang return -EBUSY; 1525ee8222feSWei Yang } 1526ee8222feSWei Yang 1527be283eebSWei Yang /* Allocating pe_num_map */ 1528be283eebSWei Yang if (pdn->m64_single_mode) 1529be283eebSWei Yang pdn->pe_num_map = kmalloc(sizeof(*pdn->pe_num_map) * num_vfs, 1530be283eebSWei Yang GFP_KERNEL); 1531be283eebSWei Yang else 1532be283eebSWei Yang pdn->pe_num_map = kmalloc(sizeof(*pdn->pe_num_map), GFP_KERNEL); 1533be283eebSWei Yang 1534be283eebSWei Yang if (!pdn->pe_num_map) 1535be283eebSWei Yang return -ENOMEM; 1536be283eebSWei Yang 1537be283eebSWei Yang if (pdn->m64_single_mode) 1538be283eebSWei Yang for (i = 0; i < num_vfs; i++) 1539be283eebSWei Yang pdn->pe_num_map[i] = IODA_INVALID_PE; 1540be283eebSWei Yang 1541781a868fSWei Yang /* Calculate available PE for required VFs */ 1542be283eebSWei Yang if (pdn->m64_single_mode) { 1543be283eebSWei Yang for (i = 0; i < num_vfs; i++) { 15441e916772SGavin Shan pe = pnv_ioda_alloc_pe(phb); 15451e916772SGavin Shan if (!pe) { 1546be283eebSWei Yang ret = -EBUSY; 1547be283eebSWei Yang goto m64_failed; 1548be283eebSWei Yang } 15491e916772SGavin Shan 15501e916772SGavin Shan pdn->pe_num_map[i] = pe->pe_number; 1551be283eebSWei Yang } 1552be283eebSWei Yang } else { 1553781a868fSWei Yang mutex_lock(&phb->ioda.pe_alloc_mutex); 1554be283eebSWei Yang *pdn->pe_num_map = bitmap_find_next_zero_area( 155592b8f137SGavin Shan phb->ioda.pe_alloc, phb->ioda.total_pe_num, 1556781a868fSWei Yang 0, num_vfs, 0); 155792b8f137SGavin Shan if (*pdn->pe_num_map >= phb->ioda.total_pe_num) { 1558781a868fSWei Yang mutex_unlock(&phb->ioda.pe_alloc_mutex); 1559781a868fSWei Yang dev_info(&pdev->dev, "Failed to enable VF%d\n", num_vfs); 1560be283eebSWei Yang kfree(pdn->pe_num_map); 1561781a868fSWei Yang return -EBUSY; 1562781a868fSWei Yang } 1563be283eebSWei Yang bitmap_set(phb->ioda.pe_alloc, *pdn->pe_num_map, num_vfs); 1564781a868fSWei Yang mutex_unlock(&phb->ioda.pe_alloc_mutex); 1565be283eebSWei Yang } 1566be283eebSWei Yang pdn->num_vfs = num_vfs; 1567781a868fSWei Yang 1568781a868fSWei Yang /* Assign M64 window accordingly */ 156902639b0eSWei Yang ret = pnv_pci_vf_assign_m64(pdev, num_vfs); 1570781a868fSWei Yang if (ret) { 1571781a868fSWei Yang dev_info(&pdev->dev, "Not enough M64 window resources\n"); 1572781a868fSWei Yang goto m64_failed; 1573781a868fSWei Yang } 1574781a868fSWei Yang 1575781a868fSWei Yang /* 1576781a868fSWei Yang * When using one M64 BAR to map one IOV BAR, we need to shift 1577781a868fSWei Yang * the IOV BAR according to the PE# allocated to the VFs. 1578781a868fSWei Yang * Otherwise, the PE# for the VF will conflict with others. 1579781a868fSWei Yang */ 1580ee8222feSWei Yang if (!pdn->m64_single_mode) { 1581be283eebSWei Yang ret = pnv_pci_vf_resource_shift(pdev, *pdn->pe_num_map); 1582781a868fSWei Yang if (ret) 1583781a868fSWei Yang goto m64_failed; 1584781a868fSWei Yang } 158502639b0eSWei Yang } 1586781a868fSWei Yang 1587781a868fSWei Yang /* Setup VF PEs */ 1588781a868fSWei Yang pnv_ioda_setup_vf_PE(pdev, num_vfs); 1589781a868fSWei Yang 1590781a868fSWei Yang return 0; 1591781a868fSWei Yang 1592781a868fSWei Yang m64_failed: 1593be283eebSWei Yang if (pdn->m64_single_mode) { 1594be283eebSWei Yang for (i = 0; i < num_vfs; i++) { 15951e916772SGavin Shan if (pdn->pe_num_map[i] == IODA_INVALID_PE) 15961e916772SGavin Shan continue; 15971e916772SGavin Shan 15981e916772SGavin Shan pe = &phb->ioda.pe_array[pdn->pe_num_map[i]]; 15991e916772SGavin Shan pnv_ioda_free_pe(pe); 1600be283eebSWei Yang } 1601be283eebSWei Yang } else 1602be283eebSWei Yang bitmap_clear(phb->ioda.pe_alloc, *pdn->pe_num_map, num_vfs); 1603be283eebSWei Yang 1604be283eebSWei Yang /* Releasing pe_num_map */ 1605be283eebSWei Yang kfree(pdn->pe_num_map); 1606781a868fSWei Yang 1607781a868fSWei Yang return ret; 1608781a868fSWei Yang } 1609781a868fSWei Yang 1610a8b2f828SGavin Shan int pcibios_sriov_disable(struct pci_dev *pdev) 1611a8b2f828SGavin Shan { 1612781a868fSWei Yang pnv_pci_sriov_disable(pdev); 1613781a868fSWei Yang 1614a8b2f828SGavin Shan /* Release PCI data */ 1615a8b2f828SGavin Shan remove_dev_pci_data(pdev); 1616a8b2f828SGavin Shan return 0; 1617a8b2f828SGavin Shan } 1618a8b2f828SGavin Shan 1619a8b2f828SGavin Shan int pcibios_sriov_enable(struct pci_dev *pdev, u16 num_vfs) 1620a8b2f828SGavin Shan { 1621a8b2f828SGavin Shan /* Allocate PCI data */ 1622a8b2f828SGavin Shan add_dev_pci_data(pdev); 1623781a868fSWei Yang 1624ee8222feSWei Yang return pnv_pci_sriov_enable(pdev, num_vfs); 1625a8b2f828SGavin Shan } 1626a8b2f828SGavin Shan #endif /* CONFIG_PCI_IOV */ 1627a8b2f828SGavin Shan 1628959c9bddSGavin Shan static void pnv_pci_ioda_dma_dev_setup(struct pnv_phb *phb, struct pci_dev *pdev) 1629184cd4a3SBenjamin Herrenschmidt { 1630b72c1f65SBenjamin Herrenschmidt struct pci_dn *pdn = pci_get_pdn(pdev); 1631959c9bddSGavin Shan struct pnv_ioda_pe *pe; 1632184cd4a3SBenjamin Herrenschmidt 1633959c9bddSGavin Shan /* 1634959c9bddSGavin Shan * The function can be called while the PE# 1635959c9bddSGavin Shan * hasn't been assigned. Do nothing for the 1636959c9bddSGavin Shan * case. 1637959c9bddSGavin Shan */ 1638959c9bddSGavin Shan if (!pdn || pdn->pe_number == IODA_INVALID_PE) 1639959c9bddSGavin Shan return; 1640184cd4a3SBenjamin Herrenschmidt 1641959c9bddSGavin Shan pe = &phb->ioda.pe_array[pdn->pe_number]; 1642cd15b048SBenjamin Herrenschmidt WARN_ON(get_dma_ops(&pdev->dev) != &dma_iommu_ops); 16430e1ffef0SAlexey Kardashevskiy set_dma_offset(&pdev->dev, pe->tce_bypass_base); 1644b348aa65SAlexey Kardashevskiy set_iommu_table_base(&pdev->dev, pe->table_group.tables[0]); 16454617082eSAlexey Kardashevskiy /* 16464617082eSAlexey Kardashevskiy * Note: iommu_add_device() will fail here as 16474617082eSAlexey Kardashevskiy * for physical PE: the device is already added by now; 16484617082eSAlexey Kardashevskiy * for virtual PE: sysfs entries are not ready yet and 16494617082eSAlexey Kardashevskiy * tce_iommu_bus_notifier will add the device to a group later. 16504617082eSAlexey Kardashevskiy */ 1651184cd4a3SBenjamin Herrenschmidt } 1652184cd4a3SBenjamin Herrenschmidt 1653763d2d8dSDaniel Axtens static int pnv_pci_ioda_dma_set_mask(struct pci_dev *pdev, u64 dma_mask) 1654cd15b048SBenjamin Herrenschmidt { 1655763d2d8dSDaniel Axtens struct pci_controller *hose = pci_bus_to_host(pdev->bus); 1656763d2d8dSDaniel Axtens struct pnv_phb *phb = hose->private_data; 1657cd15b048SBenjamin Herrenschmidt struct pci_dn *pdn = pci_get_pdn(pdev); 1658cd15b048SBenjamin Herrenschmidt struct pnv_ioda_pe *pe; 1659cd15b048SBenjamin Herrenschmidt uint64_t top; 1660cd15b048SBenjamin Herrenschmidt bool bypass = false; 1661cd15b048SBenjamin Herrenschmidt 1662cd15b048SBenjamin Herrenschmidt if (WARN_ON(!pdn || pdn->pe_number == IODA_INVALID_PE)) 1663cd15b048SBenjamin Herrenschmidt return -ENODEV;; 1664cd15b048SBenjamin Herrenschmidt 1665cd15b048SBenjamin Herrenschmidt pe = &phb->ioda.pe_array[pdn->pe_number]; 1666cd15b048SBenjamin Herrenschmidt if (pe->tce_bypass_enabled) { 1667cd15b048SBenjamin Herrenschmidt top = pe->tce_bypass_base + memblock_end_of_DRAM() - 1; 1668cd15b048SBenjamin Herrenschmidt bypass = (dma_mask >= top); 1669cd15b048SBenjamin Herrenschmidt } 1670cd15b048SBenjamin Herrenschmidt 1671cd15b048SBenjamin Herrenschmidt if (bypass) { 1672cd15b048SBenjamin Herrenschmidt dev_info(&pdev->dev, "Using 64-bit DMA iommu bypass\n"); 1673cd15b048SBenjamin Herrenschmidt set_dma_ops(&pdev->dev, &dma_direct_ops); 1674cd15b048SBenjamin Herrenschmidt } else { 1675cd15b048SBenjamin Herrenschmidt dev_info(&pdev->dev, "Using 32-bit DMA via iommu\n"); 1676cd15b048SBenjamin Herrenschmidt set_dma_ops(&pdev->dev, &dma_iommu_ops); 1677cd15b048SBenjamin Herrenschmidt } 1678a32305bfSBrian W Hart *pdev->dev.dma_mask = dma_mask; 16795d2aa710SAlistair Popple 16805d2aa710SAlistair Popple /* Update peer npu devices */ 1681f9f83456SAlexey Kardashevskiy pnv_npu_try_dma_set_bypass(pdev, bypass); 16825d2aa710SAlistair Popple 1683cd15b048SBenjamin Herrenschmidt return 0; 1684cd15b048SBenjamin Herrenschmidt } 1685cd15b048SBenjamin Herrenschmidt 168653522982SAndrew Donnellan static u64 pnv_pci_ioda_dma_get_required_mask(struct pci_dev *pdev) 1687fe7e85c6SGavin Shan { 168853522982SAndrew Donnellan struct pci_controller *hose = pci_bus_to_host(pdev->bus); 168953522982SAndrew Donnellan struct pnv_phb *phb = hose->private_data; 1690fe7e85c6SGavin Shan struct pci_dn *pdn = pci_get_pdn(pdev); 1691fe7e85c6SGavin Shan struct pnv_ioda_pe *pe; 1692fe7e85c6SGavin Shan u64 end, mask; 1693fe7e85c6SGavin Shan 1694fe7e85c6SGavin Shan if (WARN_ON(!pdn || pdn->pe_number == IODA_INVALID_PE)) 1695fe7e85c6SGavin Shan return 0; 1696fe7e85c6SGavin Shan 1697fe7e85c6SGavin Shan pe = &phb->ioda.pe_array[pdn->pe_number]; 1698fe7e85c6SGavin Shan if (!pe->tce_bypass_enabled) 1699fe7e85c6SGavin Shan return __dma_get_required_mask(&pdev->dev); 1700fe7e85c6SGavin Shan 1701fe7e85c6SGavin Shan 1702fe7e85c6SGavin Shan end = pe->tce_bypass_base + memblock_end_of_DRAM(); 1703fe7e85c6SGavin Shan mask = 1ULL << (fls64(end) - 1); 1704fe7e85c6SGavin Shan mask += mask - 1; 1705fe7e85c6SGavin Shan 1706fe7e85c6SGavin Shan return mask; 1707fe7e85c6SGavin Shan } 1708fe7e85c6SGavin Shan 1709dff4a39eSGavin Shan static void pnv_ioda_setup_bus_dma(struct pnv_ioda_pe *pe, 1710ea30e99eSAlexey Kardashevskiy struct pci_bus *bus) 171174251fe2SBenjamin Herrenschmidt { 171274251fe2SBenjamin Herrenschmidt struct pci_dev *dev; 171374251fe2SBenjamin Herrenschmidt 171474251fe2SBenjamin Herrenschmidt list_for_each_entry(dev, &bus->devices, bus_list) { 1715b348aa65SAlexey Kardashevskiy set_iommu_table_base(&dev->dev, pe->table_group.tables[0]); 1716e91c2511SBenjamin Herrenschmidt set_dma_offset(&dev->dev, pe->tce_bypass_base); 17174617082eSAlexey Kardashevskiy iommu_add_device(&dev->dev); 1718dff4a39eSGavin Shan 17195c89a87dSAlexey Kardashevskiy if ((pe->flags & PNV_IODA_PE_BUS_ALL) && dev->subordinate) 1720ea30e99eSAlexey Kardashevskiy pnv_ioda_setup_bus_dma(pe, dev->subordinate); 172174251fe2SBenjamin Herrenschmidt } 172274251fe2SBenjamin Herrenschmidt } 172374251fe2SBenjamin Herrenschmidt 1724fd141d1aSBenjamin Herrenschmidt static inline __be64 __iomem *pnv_ioda_get_inval_reg(struct pnv_phb *phb, 1725fd141d1aSBenjamin Herrenschmidt bool real_mode) 1726fd141d1aSBenjamin Herrenschmidt { 1727fd141d1aSBenjamin Herrenschmidt return real_mode ? (__be64 __iomem *)(phb->regs_phys + 0x210) : 1728fd141d1aSBenjamin Herrenschmidt (phb->regs + 0x210); 1729fd141d1aSBenjamin Herrenschmidt } 1730fd141d1aSBenjamin Herrenschmidt 1731a34ab7c3SBenjamin Herrenschmidt static void pnv_pci_p7ioc_tce_invalidate(struct iommu_table *tbl, 1732decbda25SAlexey Kardashevskiy unsigned long index, unsigned long npages, bool rm) 17334cce9550SGavin Shan { 17340eaf4defSAlexey Kardashevskiy struct iommu_table_group_link *tgl = list_first_entry_or_null( 17350eaf4defSAlexey Kardashevskiy &tbl->it_group_list, struct iommu_table_group_link, 17360eaf4defSAlexey Kardashevskiy next); 17370eaf4defSAlexey Kardashevskiy struct pnv_ioda_pe *pe = container_of(tgl->table_group, 1738b348aa65SAlexey Kardashevskiy struct pnv_ioda_pe, table_group); 1739fd141d1aSBenjamin Herrenschmidt __be64 __iomem *invalidate = pnv_ioda_get_inval_reg(pe->phb, rm); 17404cce9550SGavin Shan unsigned long start, end, inc; 17414cce9550SGavin Shan 1742decbda25SAlexey Kardashevskiy start = __pa(((__be64 *)tbl->it_base) + index - tbl->it_offset); 1743decbda25SAlexey Kardashevskiy end = __pa(((__be64 *)tbl->it_base) + index - tbl->it_offset + 1744decbda25SAlexey Kardashevskiy npages - 1); 17454cce9550SGavin Shan 17464cce9550SGavin Shan /* p7ioc-style invalidation, 2 TCEs per write */ 17474cce9550SGavin Shan start |= (1ull << 63); 17484cce9550SGavin Shan end |= (1ull << 63); 17494cce9550SGavin Shan inc = 16; 17504cce9550SGavin Shan end |= inc - 1; /* round up end to be different than start */ 17514cce9550SGavin Shan 17524cce9550SGavin Shan mb(); /* Ensure above stores are visible */ 17534cce9550SGavin Shan while (start <= end) { 17548e0a1611SAlexey Kardashevskiy if (rm) 17553ad26e5cSBenjamin Herrenschmidt __raw_rm_writeq(cpu_to_be64(start), invalidate); 17568e0a1611SAlexey Kardashevskiy else 17573a1a4661SBenjamin Herrenschmidt __raw_writeq(cpu_to_be64(start), invalidate); 17584cce9550SGavin Shan start += inc; 17594cce9550SGavin Shan } 17604cce9550SGavin Shan 17614cce9550SGavin Shan /* 17624cce9550SGavin Shan * The iommu layer will do another mb() for us on build() 17634cce9550SGavin Shan * and we don't care on free() 17644cce9550SGavin Shan */ 17654cce9550SGavin Shan } 17664cce9550SGavin Shan 1767decbda25SAlexey Kardashevskiy static int pnv_ioda1_tce_build(struct iommu_table *tbl, long index, 1768decbda25SAlexey Kardashevskiy long npages, unsigned long uaddr, 1769decbda25SAlexey Kardashevskiy enum dma_data_direction direction, 1770decbda25SAlexey Kardashevskiy struct dma_attrs *attrs) 1771decbda25SAlexey Kardashevskiy { 1772decbda25SAlexey Kardashevskiy int ret = pnv_tce_build(tbl, index, npages, uaddr, direction, 1773decbda25SAlexey Kardashevskiy attrs); 1774decbda25SAlexey Kardashevskiy 177508acce1cSBenjamin Herrenschmidt if (!ret) 1776a34ab7c3SBenjamin Herrenschmidt pnv_pci_p7ioc_tce_invalidate(tbl, index, npages, false); 1777decbda25SAlexey Kardashevskiy 1778decbda25SAlexey Kardashevskiy return ret; 1779decbda25SAlexey Kardashevskiy } 1780decbda25SAlexey Kardashevskiy 178105c6cfb9SAlexey Kardashevskiy #ifdef CONFIG_IOMMU_API 178205c6cfb9SAlexey Kardashevskiy static int pnv_ioda1_tce_xchg(struct iommu_table *tbl, long index, 178305c6cfb9SAlexey Kardashevskiy unsigned long *hpa, enum dma_data_direction *direction) 178405c6cfb9SAlexey Kardashevskiy { 178505c6cfb9SAlexey Kardashevskiy long ret = pnv_tce_xchg(tbl, index, hpa, direction); 178605c6cfb9SAlexey Kardashevskiy 178708acce1cSBenjamin Herrenschmidt if (!ret) 1788a34ab7c3SBenjamin Herrenschmidt pnv_pci_p7ioc_tce_invalidate(tbl, index, 1, false); 178905c6cfb9SAlexey Kardashevskiy 179005c6cfb9SAlexey Kardashevskiy return ret; 179105c6cfb9SAlexey Kardashevskiy } 179205c6cfb9SAlexey Kardashevskiy #endif 179305c6cfb9SAlexey Kardashevskiy 1794decbda25SAlexey Kardashevskiy static void pnv_ioda1_tce_free(struct iommu_table *tbl, long index, 1795decbda25SAlexey Kardashevskiy long npages) 1796decbda25SAlexey Kardashevskiy { 1797decbda25SAlexey Kardashevskiy pnv_tce_free(tbl, index, npages); 1798decbda25SAlexey Kardashevskiy 1799a34ab7c3SBenjamin Herrenschmidt pnv_pci_p7ioc_tce_invalidate(tbl, index, npages, false); 1800decbda25SAlexey Kardashevskiy } 1801decbda25SAlexey Kardashevskiy 1802da004c36SAlexey Kardashevskiy static struct iommu_table_ops pnv_ioda1_iommu_ops = { 1803decbda25SAlexey Kardashevskiy .set = pnv_ioda1_tce_build, 180405c6cfb9SAlexey Kardashevskiy #ifdef CONFIG_IOMMU_API 180505c6cfb9SAlexey Kardashevskiy .exchange = pnv_ioda1_tce_xchg, 180605c6cfb9SAlexey Kardashevskiy #endif 1807decbda25SAlexey Kardashevskiy .clear = pnv_ioda1_tce_free, 1808da004c36SAlexey Kardashevskiy .get = pnv_tce_get, 1809da004c36SAlexey Kardashevskiy }; 1810da004c36SAlexey Kardashevskiy 1811a34ab7c3SBenjamin Herrenschmidt #define PHB3_TCE_KILL_INVAL_ALL PPC_BIT(0) 1812a34ab7c3SBenjamin Herrenschmidt #define PHB3_TCE_KILL_INVAL_PE PPC_BIT(1) 1813a34ab7c3SBenjamin Herrenschmidt #define PHB3_TCE_KILL_INVAL_ONE PPC_BIT(2) 1814bef9253fSAlexey Kardashevskiy 1815a34ab7c3SBenjamin Herrenschmidt void pnv_pci_phb3_tce_invalidate_entire(struct pnv_phb *phb, bool rm) 18160bbcdb43SAlexey Kardashevskiy { 1817fd141d1aSBenjamin Herrenschmidt __be64 __iomem *invalidate = pnv_ioda_get_inval_reg(phb, rm); 1818a34ab7c3SBenjamin Herrenschmidt const unsigned long val = PHB3_TCE_KILL_INVAL_ALL; 18190bbcdb43SAlexey Kardashevskiy 18200bbcdb43SAlexey Kardashevskiy mb(); /* Ensure previous TCE table stores are visible */ 18210bbcdb43SAlexey Kardashevskiy if (rm) 1822fd141d1aSBenjamin Herrenschmidt __raw_rm_writeq(cpu_to_be64(val), invalidate); 18230bbcdb43SAlexey Kardashevskiy else 1824fd141d1aSBenjamin Herrenschmidt __raw_writeq(cpu_to_be64(val), invalidate); 18250bbcdb43SAlexey Kardashevskiy } 18260bbcdb43SAlexey Kardashevskiy 1827a34ab7c3SBenjamin Herrenschmidt static inline void pnv_pci_phb3_tce_invalidate_pe(struct pnv_ioda_pe *pe) 18285780fb04SAlexey Kardashevskiy { 18295780fb04SAlexey Kardashevskiy /* 01xb - invalidate TCEs that match the specified PE# */ 1830fd141d1aSBenjamin Herrenschmidt __be64 __iomem *invalidate = pnv_ioda_get_inval_reg(pe->phb, false); 1831a34ab7c3SBenjamin Herrenschmidt unsigned long val = PHB3_TCE_KILL_INVAL_PE | (pe->pe_number & 0xFF); 18325780fb04SAlexey Kardashevskiy 18335780fb04SAlexey Kardashevskiy mb(); /* Ensure above stores are visible */ 1834fd141d1aSBenjamin Herrenschmidt __raw_writeq(cpu_to_be64(val), invalidate); 18355780fb04SAlexey Kardashevskiy } 18365780fb04SAlexey Kardashevskiy 1837fd141d1aSBenjamin Herrenschmidt static void pnv_pci_phb3_tce_invalidate(struct pnv_ioda_pe *pe, bool rm, 1838fd141d1aSBenjamin Herrenschmidt unsigned shift, unsigned long index, 1839fd141d1aSBenjamin Herrenschmidt unsigned long npages) 18404cce9550SGavin Shan { 1841fd141d1aSBenjamin Herrenschmidt __be64 __iomem *invalidate = pnv_ioda_get_inval_reg(pe->phb, false); 18424cce9550SGavin Shan unsigned long start, end, inc; 18434cce9550SGavin Shan 18444cce9550SGavin Shan /* We'll invalidate DMA address in PE scope */ 1845a34ab7c3SBenjamin Herrenschmidt start = PHB3_TCE_KILL_INVAL_ONE; 1846fd141d1aSBenjamin Herrenschmidt start |= (pe->pe_number & 0xFF); 18474cce9550SGavin Shan end = start; 18484cce9550SGavin Shan 18494cce9550SGavin Shan /* Figure out the start, end and step */ 1850decbda25SAlexey Kardashevskiy start |= (index << shift); 1851decbda25SAlexey Kardashevskiy end |= ((index + npages - 1) << shift); 1852b0376c9bSAlexey Kardashevskiy inc = (0x1ull << shift); 18534cce9550SGavin Shan mb(); 18544cce9550SGavin Shan 18554cce9550SGavin Shan while (start <= end) { 18568e0a1611SAlexey Kardashevskiy if (rm) 18573ad26e5cSBenjamin Herrenschmidt __raw_rm_writeq(cpu_to_be64(start), invalidate); 18588e0a1611SAlexey Kardashevskiy else 18593a1a4661SBenjamin Herrenschmidt __raw_writeq(cpu_to_be64(start), invalidate); 18604cce9550SGavin Shan start += inc; 18614cce9550SGavin Shan } 18624cce9550SGavin Shan } 18634cce9550SGavin Shan 1864e57080f1SAlexey Kardashevskiy static void pnv_pci_ioda2_tce_invalidate(struct iommu_table *tbl, 1865e57080f1SAlexey Kardashevskiy unsigned long index, unsigned long npages, bool rm) 1866e57080f1SAlexey Kardashevskiy { 1867e57080f1SAlexey Kardashevskiy struct iommu_table_group_link *tgl; 1868e57080f1SAlexey Kardashevskiy 1869e57080f1SAlexey Kardashevskiy list_for_each_entry_rcu(tgl, &tbl->it_group_list, next) { 1870e57080f1SAlexey Kardashevskiy struct pnv_ioda_pe *pe = container_of(tgl->table_group, 1871e57080f1SAlexey Kardashevskiy struct pnv_ioda_pe, table_group); 187285674868SAlexey Kardashevskiy if (pe->phb->type == PNV_PHB_NPU) { 18730bbcdb43SAlexey Kardashevskiy /* 18740bbcdb43SAlexey Kardashevskiy * The NVLink hardware does not support TCE kill 18750bbcdb43SAlexey Kardashevskiy * per TCE entry so we have to invalidate 18760bbcdb43SAlexey Kardashevskiy * the entire cache for it. 18770bbcdb43SAlexey Kardashevskiy */ 1878a34ab7c3SBenjamin Herrenschmidt pnv_pci_phb3_tce_invalidate_entire(pe->phb, rm); 18795d2aa710SAlistair Popple continue; 18805d2aa710SAlistair Popple } 1881fd141d1aSBenjamin Herrenschmidt pnv_pci_phb3_tce_invalidate(pe, rm, tbl->it_page_shift, 188285674868SAlexey Kardashevskiy index, npages); 1883e57080f1SAlexey Kardashevskiy } 1884e57080f1SAlexey Kardashevskiy } 1885e57080f1SAlexey Kardashevskiy 1886decbda25SAlexey Kardashevskiy static int pnv_ioda2_tce_build(struct iommu_table *tbl, long index, 1887decbda25SAlexey Kardashevskiy long npages, unsigned long uaddr, 1888decbda25SAlexey Kardashevskiy enum dma_data_direction direction, 1889decbda25SAlexey Kardashevskiy struct dma_attrs *attrs) 18904cce9550SGavin Shan { 1891decbda25SAlexey Kardashevskiy int ret = pnv_tce_build(tbl, index, npages, uaddr, direction, 1892decbda25SAlexey Kardashevskiy attrs); 18934cce9550SGavin Shan 189408acce1cSBenjamin Herrenschmidt if (!ret) 1895decbda25SAlexey Kardashevskiy pnv_pci_ioda2_tce_invalidate(tbl, index, npages, false); 1896decbda25SAlexey Kardashevskiy 1897decbda25SAlexey Kardashevskiy return ret; 1898decbda25SAlexey Kardashevskiy } 1899decbda25SAlexey Kardashevskiy 190005c6cfb9SAlexey Kardashevskiy #ifdef CONFIG_IOMMU_API 190105c6cfb9SAlexey Kardashevskiy static int pnv_ioda2_tce_xchg(struct iommu_table *tbl, long index, 190205c6cfb9SAlexey Kardashevskiy unsigned long *hpa, enum dma_data_direction *direction) 190305c6cfb9SAlexey Kardashevskiy { 190405c6cfb9SAlexey Kardashevskiy long ret = pnv_tce_xchg(tbl, index, hpa, direction); 190505c6cfb9SAlexey Kardashevskiy 190608acce1cSBenjamin Herrenschmidt if (!ret) 190705c6cfb9SAlexey Kardashevskiy pnv_pci_ioda2_tce_invalidate(tbl, index, 1, false); 190805c6cfb9SAlexey Kardashevskiy 190905c6cfb9SAlexey Kardashevskiy return ret; 191005c6cfb9SAlexey Kardashevskiy } 191105c6cfb9SAlexey Kardashevskiy #endif 191205c6cfb9SAlexey Kardashevskiy 1913decbda25SAlexey Kardashevskiy static void pnv_ioda2_tce_free(struct iommu_table *tbl, long index, 1914decbda25SAlexey Kardashevskiy long npages) 1915decbda25SAlexey Kardashevskiy { 1916decbda25SAlexey Kardashevskiy pnv_tce_free(tbl, index, npages); 1917decbda25SAlexey Kardashevskiy 1918decbda25SAlexey Kardashevskiy pnv_pci_ioda2_tce_invalidate(tbl, index, npages, false); 19194cce9550SGavin Shan } 19204cce9550SGavin Shan 19214793d65dSAlexey Kardashevskiy static void pnv_ioda2_table_free(struct iommu_table *tbl) 19224793d65dSAlexey Kardashevskiy { 19234793d65dSAlexey Kardashevskiy pnv_pci_ioda2_table_free_pages(tbl); 19244793d65dSAlexey Kardashevskiy iommu_free_table(tbl, "pnv"); 19254793d65dSAlexey Kardashevskiy } 19264793d65dSAlexey Kardashevskiy 1927da004c36SAlexey Kardashevskiy static struct iommu_table_ops pnv_ioda2_iommu_ops = { 1928decbda25SAlexey Kardashevskiy .set = pnv_ioda2_tce_build, 192905c6cfb9SAlexey Kardashevskiy #ifdef CONFIG_IOMMU_API 193005c6cfb9SAlexey Kardashevskiy .exchange = pnv_ioda2_tce_xchg, 193105c6cfb9SAlexey Kardashevskiy #endif 1932decbda25SAlexey Kardashevskiy .clear = pnv_ioda2_tce_free, 1933da004c36SAlexey Kardashevskiy .get = pnv_tce_get, 19344793d65dSAlexey Kardashevskiy .free = pnv_ioda2_table_free, 1935da004c36SAlexey Kardashevskiy }; 1936da004c36SAlexey Kardashevskiy 1937801846d1SGavin Shan static int pnv_pci_ioda_dev_dma_weight(struct pci_dev *dev, void *data) 1938801846d1SGavin Shan { 1939801846d1SGavin Shan unsigned int *weight = (unsigned int *)data; 1940801846d1SGavin Shan 1941801846d1SGavin Shan /* This is quite simplistic. The "base" weight of a device 1942801846d1SGavin Shan * is 10. 0 means no DMA is to be accounted for it. 1943801846d1SGavin Shan */ 1944801846d1SGavin Shan if (dev->hdr_type != PCI_HEADER_TYPE_NORMAL) 1945801846d1SGavin Shan return 0; 1946801846d1SGavin Shan 1947801846d1SGavin Shan if (dev->class == PCI_CLASS_SERIAL_USB_UHCI || 1948801846d1SGavin Shan dev->class == PCI_CLASS_SERIAL_USB_OHCI || 1949801846d1SGavin Shan dev->class == PCI_CLASS_SERIAL_USB_EHCI) 1950801846d1SGavin Shan *weight += 3; 1951801846d1SGavin Shan else if ((dev->class >> 8) == PCI_CLASS_STORAGE_RAID) 1952801846d1SGavin Shan *weight += 15; 1953801846d1SGavin Shan else 1954801846d1SGavin Shan *weight += 10; 1955801846d1SGavin Shan 1956801846d1SGavin Shan return 0; 1957801846d1SGavin Shan } 1958801846d1SGavin Shan 1959801846d1SGavin Shan static unsigned int pnv_pci_ioda_pe_dma_weight(struct pnv_ioda_pe *pe) 1960801846d1SGavin Shan { 1961801846d1SGavin Shan unsigned int weight = 0; 1962801846d1SGavin Shan 1963801846d1SGavin Shan /* SRIOV VF has same DMA32 weight as its PF */ 1964801846d1SGavin Shan #ifdef CONFIG_PCI_IOV 1965801846d1SGavin Shan if ((pe->flags & PNV_IODA_PE_VF) && pe->parent_dev) { 1966801846d1SGavin Shan pnv_pci_ioda_dev_dma_weight(pe->parent_dev, &weight); 1967801846d1SGavin Shan return weight; 1968801846d1SGavin Shan } 1969801846d1SGavin Shan #endif 1970801846d1SGavin Shan 1971801846d1SGavin Shan if ((pe->flags & PNV_IODA_PE_DEV) && pe->pdev) { 1972801846d1SGavin Shan pnv_pci_ioda_dev_dma_weight(pe->pdev, &weight); 1973801846d1SGavin Shan } else if ((pe->flags & PNV_IODA_PE_BUS) && pe->pbus) { 1974801846d1SGavin Shan struct pci_dev *pdev; 1975801846d1SGavin Shan 1976801846d1SGavin Shan list_for_each_entry(pdev, &pe->pbus->devices, bus_list) 1977801846d1SGavin Shan pnv_pci_ioda_dev_dma_weight(pdev, &weight); 1978801846d1SGavin Shan } else if ((pe->flags & PNV_IODA_PE_BUS_ALL) && pe->pbus) { 1979801846d1SGavin Shan pci_walk_bus(pe->pbus, pnv_pci_ioda_dev_dma_weight, &weight); 1980801846d1SGavin Shan } 1981801846d1SGavin Shan 1982801846d1SGavin Shan return weight; 1983801846d1SGavin Shan } 1984801846d1SGavin Shan 1985b30d936fSGavin Shan static void pnv_pci_ioda1_setup_dma_pe(struct pnv_phb *phb, 19862b923ed1SGavin Shan struct pnv_ioda_pe *pe) 1987184cd4a3SBenjamin Herrenschmidt { 1988184cd4a3SBenjamin Herrenschmidt 1989184cd4a3SBenjamin Herrenschmidt struct page *tce_mem = NULL; 1990184cd4a3SBenjamin Herrenschmidt struct iommu_table *tbl; 19912b923ed1SGavin Shan unsigned int weight, total_weight = 0; 19922b923ed1SGavin Shan unsigned int tce32_segsz, base, segs, avail, i; 1993184cd4a3SBenjamin Herrenschmidt int64_t rc; 1994184cd4a3SBenjamin Herrenschmidt void *addr; 1995184cd4a3SBenjamin Herrenschmidt 1996184cd4a3SBenjamin Herrenschmidt /* XXX FIXME: Handle 64-bit only DMA devices */ 1997184cd4a3SBenjamin Herrenschmidt /* XXX FIXME: Provide 64-bit DMA facilities & non-4K TCE tables etc.. */ 1998184cd4a3SBenjamin Herrenschmidt /* XXX FIXME: Allocate multi-level tables on PHB3 */ 19992b923ed1SGavin Shan weight = pnv_pci_ioda_pe_dma_weight(pe); 20002b923ed1SGavin Shan if (!weight) 20012b923ed1SGavin Shan return; 2002184cd4a3SBenjamin Herrenschmidt 20032b923ed1SGavin Shan pci_walk_bus(phb->hose->bus, pnv_pci_ioda_dev_dma_weight, 20042b923ed1SGavin Shan &total_weight); 20052b923ed1SGavin Shan segs = (weight * phb->ioda.dma32_count) / total_weight; 20062b923ed1SGavin Shan if (!segs) 20072b923ed1SGavin Shan segs = 1; 20082b923ed1SGavin Shan 20092b923ed1SGavin Shan /* 20102b923ed1SGavin Shan * Allocate contiguous DMA32 segments. We begin with the expected 20112b923ed1SGavin Shan * number of segments. With one more attempt, the number of DMA32 20122b923ed1SGavin Shan * segments to be allocated is decreased by one until one segment 20132b923ed1SGavin Shan * is allocated successfully. 20142b923ed1SGavin Shan */ 20152b923ed1SGavin Shan do { 20162b923ed1SGavin Shan for (base = 0; base <= phb->ioda.dma32_count - segs; base++) { 20172b923ed1SGavin Shan for (avail = 0, i = base; i < base + segs; i++) { 20182b923ed1SGavin Shan if (phb->ioda.dma32_segmap[i] == 20192b923ed1SGavin Shan IODA_INVALID_PE) 20202b923ed1SGavin Shan avail++; 20212b923ed1SGavin Shan } 20222b923ed1SGavin Shan 20232b923ed1SGavin Shan if (avail == segs) 20242b923ed1SGavin Shan goto found; 20252b923ed1SGavin Shan } 20262b923ed1SGavin Shan } while (--segs); 20272b923ed1SGavin Shan 20282b923ed1SGavin Shan if (!segs) { 20292b923ed1SGavin Shan pe_warn(pe, "No available DMA32 segments\n"); 20302b923ed1SGavin Shan return; 20312b923ed1SGavin Shan } 20322b923ed1SGavin Shan 20332b923ed1SGavin Shan found: 20340eaf4defSAlexey Kardashevskiy tbl = pnv_pci_table_alloc(phb->hose->node); 2035b348aa65SAlexey Kardashevskiy iommu_register_group(&pe->table_group, phb->hose->global_number, 2036b348aa65SAlexey Kardashevskiy pe->pe_number); 20370eaf4defSAlexey Kardashevskiy pnv_pci_link_table_and_group(phb->hose->node, 0, tbl, &pe->table_group); 2038c5773822SAlexey Kardashevskiy 2039184cd4a3SBenjamin Herrenschmidt /* Grab a 32-bit TCE table */ 20402b923ed1SGavin Shan pe_info(pe, "DMA weight %d (%d), assigned (%d) %d DMA32 segments\n", 20412b923ed1SGavin Shan weight, total_weight, base, segs); 2042184cd4a3SBenjamin Herrenschmidt pe_info(pe, " Setting up 32-bit TCE table at %08x..%08x\n", 2043acce971cSGavin Shan base * PNV_IODA1_DMA32_SEGSIZE, 2044acce971cSGavin Shan (base + segs) * PNV_IODA1_DMA32_SEGSIZE - 1); 2045184cd4a3SBenjamin Herrenschmidt 2046184cd4a3SBenjamin Herrenschmidt /* XXX Currently, we allocate one big contiguous table for the 2047184cd4a3SBenjamin Herrenschmidt * TCEs. We only really need one chunk per 256M of TCE space 2048184cd4a3SBenjamin Herrenschmidt * (ie per segment) but that's an optimization for later, it 2049184cd4a3SBenjamin Herrenschmidt * requires some added smarts with our get/put_tce implementation 2050acce971cSGavin Shan * 2051acce971cSGavin Shan * Each TCE page is 4KB in size and each TCE entry occupies 8 2052acce971cSGavin Shan * bytes 2053184cd4a3SBenjamin Herrenschmidt */ 2054acce971cSGavin Shan tce32_segsz = PNV_IODA1_DMA32_SEGSIZE >> (IOMMU_PAGE_SHIFT_4K - 3); 2055184cd4a3SBenjamin Herrenschmidt tce_mem = alloc_pages_node(phb->hose->node, GFP_KERNEL, 2056acce971cSGavin Shan get_order(tce32_segsz * segs)); 2057184cd4a3SBenjamin Herrenschmidt if (!tce_mem) { 2058184cd4a3SBenjamin Herrenschmidt pe_err(pe, " Failed to allocate a 32-bit TCE memory\n"); 2059184cd4a3SBenjamin Herrenschmidt goto fail; 2060184cd4a3SBenjamin Herrenschmidt } 2061184cd4a3SBenjamin Herrenschmidt addr = page_address(tce_mem); 2062acce971cSGavin Shan memset(addr, 0, tce32_segsz * segs); 2063184cd4a3SBenjamin Herrenschmidt 2064184cd4a3SBenjamin Herrenschmidt /* Configure HW */ 2065184cd4a3SBenjamin Herrenschmidt for (i = 0; i < segs; i++) { 2066184cd4a3SBenjamin Herrenschmidt rc = opal_pci_map_pe_dma_window(phb->opal_id, 2067184cd4a3SBenjamin Herrenschmidt pe->pe_number, 2068184cd4a3SBenjamin Herrenschmidt base + i, 1, 2069acce971cSGavin Shan __pa(addr) + tce32_segsz * i, 2070acce971cSGavin Shan tce32_segsz, IOMMU_PAGE_SIZE_4K); 2071184cd4a3SBenjamin Herrenschmidt if (rc) { 2072184cd4a3SBenjamin Herrenschmidt pe_err(pe, " Failed to configure 32-bit TCE table," 2073184cd4a3SBenjamin Herrenschmidt " err %ld\n", rc); 2074184cd4a3SBenjamin Herrenschmidt goto fail; 2075184cd4a3SBenjamin Herrenschmidt } 2076184cd4a3SBenjamin Herrenschmidt } 2077184cd4a3SBenjamin Herrenschmidt 20782b923ed1SGavin Shan /* Setup DMA32 segment mapping */ 20792b923ed1SGavin Shan for (i = base; i < base + segs; i++) 20802b923ed1SGavin Shan phb->ioda.dma32_segmap[i] = pe->pe_number; 20812b923ed1SGavin Shan 2082184cd4a3SBenjamin Herrenschmidt /* Setup linux iommu table */ 2083acce971cSGavin Shan pnv_pci_setup_iommu_table(tbl, addr, tce32_segsz * segs, 2084acce971cSGavin Shan base * PNV_IODA1_DMA32_SEGSIZE, 2085acce971cSGavin Shan IOMMU_PAGE_SHIFT_4K); 2086184cd4a3SBenjamin Herrenschmidt 2087da004c36SAlexey Kardashevskiy tbl->it_ops = &pnv_ioda1_iommu_ops; 20884793d65dSAlexey Kardashevskiy pe->table_group.tce32_start = tbl->it_offset << tbl->it_page_shift; 20894793d65dSAlexey Kardashevskiy pe->table_group.tce32_size = tbl->it_size << tbl->it_page_shift; 2090184cd4a3SBenjamin Herrenschmidt iommu_init_table(tbl, phb->hose->node); 2091184cd4a3SBenjamin Herrenschmidt 2092781a868fSWei Yang if (pe->flags & PNV_IODA_PE_DEV) { 20934617082eSAlexey Kardashevskiy /* 20944617082eSAlexey Kardashevskiy * Setting table base here only for carrying iommu_group 20954617082eSAlexey Kardashevskiy * further down to let iommu_add_device() do the job. 20964617082eSAlexey Kardashevskiy * pnv_pci_ioda_dma_dev_setup will override it later anyway. 20974617082eSAlexey Kardashevskiy */ 20984617082eSAlexey Kardashevskiy set_iommu_table_base(&pe->pdev->dev, tbl); 20994617082eSAlexey Kardashevskiy iommu_add_device(&pe->pdev->dev); 2100c5773822SAlexey Kardashevskiy } else if (pe->flags & (PNV_IODA_PE_BUS | PNV_IODA_PE_BUS_ALL)) 2101ea30e99eSAlexey Kardashevskiy pnv_ioda_setup_bus_dma(pe, pe->pbus); 210274251fe2SBenjamin Herrenschmidt 2103184cd4a3SBenjamin Herrenschmidt return; 2104184cd4a3SBenjamin Herrenschmidt fail: 2105184cd4a3SBenjamin Herrenschmidt /* XXX Failure: Try to fallback to 64-bit only ? */ 2106184cd4a3SBenjamin Herrenschmidt if (tce_mem) 2107acce971cSGavin Shan __free_pages(tce_mem, get_order(tce32_segsz * segs)); 21080eaf4defSAlexey Kardashevskiy if (tbl) { 21090eaf4defSAlexey Kardashevskiy pnv_pci_unlink_table_and_group(tbl, &pe->table_group); 21100eaf4defSAlexey Kardashevskiy iommu_free_table(tbl, "pnv"); 21110eaf4defSAlexey Kardashevskiy } 2112184cd4a3SBenjamin Herrenschmidt } 2113184cd4a3SBenjamin Herrenschmidt 211443cb60abSAlexey Kardashevskiy static long pnv_pci_ioda2_set_window(struct iommu_table_group *table_group, 211543cb60abSAlexey Kardashevskiy int num, struct iommu_table *tbl) 211643cb60abSAlexey Kardashevskiy { 211743cb60abSAlexey Kardashevskiy struct pnv_ioda_pe *pe = container_of(table_group, struct pnv_ioda_pe, 211843cb60abSAlexey Kardashevskiy table_group); 211943cb60abSAlexey Kardashevskiy struct pnv_phb *phb = pe->phb; 212043cb60abSAlexey Kardashevskiy int64_t rc; 2121bbb845c4SAlexey Kardashevskiy const unsigned long size = tbl->it_indirect_levels ? 2122bbb845c4SAlexey Kardashevskiy tbl->it_level_size : tbl->it_size; 212343cb60abSAlexey Kardashevskiy const __u64 start_addr = tbl->it_offset << tbl->it_page_shift; 212443cb60abSAlexey Kardashevskiy const __u64 win_size = tbl->it_size << tbl->it_page_shift; 212543cb60abSAlexey Kardashevskiy 21264793d65dSAlexey Kardashevskiy pe_info(pe, "Setting up window#%d %llx..%llx pg=%x\n", num, 212743cb60abSAlexey Kardashevskiy start_addr, start_addr + win_size - 1, 212843cb60abSAlexey Kardashevskiy IOMMU_PAGE_SIZE(tbl)); 212943cb60abSAlexey Kardashevskiy 213043cb60abSAlexey Kardashevskiy /* 213143cb60abSAlexey Kardashevskiy * Map TCE table through TVT. The TVE index is the PE number 213243cb60abSAlexey Kardashevskiy * shifted by 1 bit for 32-bits DMA space. 213343cb60abSAlexey Kardashevskiy */ 213443cb60abSAlexey Kardashevskiy rc = opal_pci_map_pe_dma_window(phb->opal_id, 213543cb60abSAlexey Kardashevskiy pe->pe_number, 21364793d65dSAlexey Kardashevskiy (pe->pe_number << 1) + num, 2137bbb845c4SAlexey Kardashevskiy tbl->it_indirect_levels + 1, 213843cb60abSAlexey Kardashevskiy __pa(tbl->it_base), 2139bbb845c4SAlexey Kardashevskiy size << 3, 214043cb60abSAlexey Kardashevskiy IOMMU_PAGE_SIZE(tbl)); 214143cb60abSAlexey Kardashevskiy if (rc) { 214243cb60abSAlexey Kardashevskiy pe_err(pe, "Failed to configure TCE table, err %ld\n", rc); 214343cb60abSAlexey Kardashevskiy return rc; 214443cb60abSAlexey Kardashevskiy } 214543cb60abSAlexey Kardashevskiy 214643cb60abSAlexey Kardashevskiy pnv_pci_link_table_and_group(phb->hose->node, num, 214743cb60abSAlexey Kardashevskiy tbl, &pe->table_group); 2148a34ab7c3SBenjamin Herrenschmidt pnv_pci_phb3_tce_invalidate_pe(pe); 214943cb60abSAlexey Kardashevskiy 215043cb60abSAlexey Kardashevskiy return 0; 215143cb60abSAlexey Kardashevskiy } 215243cb60abSAlexey Kardashevskiy 2153f87a8864SAlexey Kardashevskiy static void pnv_pci_ioda2_set_bypass(struct pnv_ioda_pe *pe, bool enable) 2154cd15b048SBenjamin Herrenschmidt { 2155cd15b048SBenjamin Herrenschmidt uint16_t window_id = (pe->pe_number << 1 ) + 1; 2156cd15b048SBenjamin Herrenschmidt int64_t rc; 2157cd15b048SBenjamin Herrenschmidt 2158cd15b048SBenjamin Herrenschmidt pe_info(pe, "%sabling 64-bit DMA bypass\n", enable ? "En" : "Dis"); 2159cd15b048SBenjamin Herrenschmidt if (enable) { 2160cd15b048SBenjamin Herrenschmidt phys_addr_t top = memblock_end_of_DRAM(); 2161cd15b048SBenjamin Herrenschmidt 2162cd15b048SBenjamin Herrenschmidt top = roundup_pow_of_two(top); 2163cd15b048SBenjamin Herrenschmidt rc = opal_pci_map_pe_dma_window_real(pe->phb->opal_id, 2164cd15b048SBenjamin Herrenschmidt pe->pe_number, 2165cd15b048SBenjamin Herrenschmidt window_id, 2166cd15b048SBenjamin Herrenschmidt pe->tce_bypass_base, 2167cd15b048SBenjamin Herrenschmidt top); 2168cd15b048SBenjamin Herrenschmidt } else { 2169cd15b048SBenjamin Herrenschmidt rc = opal_pci_map_pe_dma_window_real(pe->phb->opal_id, 2170cd15b048SBenjamin Herrenschmidt pe->pe_number, 2171cd15b048SBenjamin Herrenschmidt window_id, 2172cd15b048SBenjamin Herrenschmidt pe->tce_bypass_base, 2173cd15b048SBenjamin Herrenschmidt 0); 2174cd15b048SBenjamin Herrenschmidt } 2175cd15b048SBenjamin Herrenschmidt if (rc) 2176cd15b048SBenjamin Herrenschmidt pe_err(pe, "OPAL error %lld configuring bypass window\n", rc); 2177cd15b048SBenjamin Herrenschmidt else 2178cd15b048SBenjamin Herrenschmidt pe->tce_bypass_enabled = enable; 2179cd15b048SBenjamin Herrenschmidt } 2180cd15b048SBenjamin Herrenschmidt 21814793d65dSAlexey Kardashevskiy static long pnv_pci_ioda2_table_alloc_pages(int nid, __u64 bus_offset, 21824793d65dSAlexey Kardashevskiy __u32 page_shift, __u64 window_size, __u32 levels, 21834793d65dSAlexey Kardashevskiy struct iommu_table *tbl); 21844793d65dSAlexey Kardashevskiy 21854793d65dSAlexey Kardashevskiy static long pnv_pci_ioda2_create_table(struct iommu_table_group *table_group, 21864793d65dSAlexey Kardashevskiy int num, __u32 page_shift, __u64 window_size, __u32 levels, 21874793d65dSAlexey Kardashevskiy struct iommu_table **ptbl) 21884793d65dSAlexey Kardashevskiy { 21894793d65dSAlexey Kardashevskiy struct pnv_ioda_pe *pe = container_of(table_group, struct pnv_ioda_pe, 21904793d65dSAlexey Kardashevskiy table_group); 21914793d65dSAlexey Kardashevskiy int nid = pe->phb->hose->node; 21924793d65dSAlexey Kardashevskiy __u64 bus_offset = num ? pe->tce_bypass_base : table_group->tce32_start; 21934793d65dSAlexey Kardashevskiy long ret; 21944793d65dSAlexey Kardashevskiy struct iommu_table *tbl; 21954793d65dSAlexey Kardashevskiy 21964793d65dSAlexey Kardashevskiy tbl = pnv_pci_table_alloc(nid); 21974793d65dSAlexey Kardashevskiy if (!tbl) 21984793d65dSAlexey Kardashevskiy return -ENOMEM; 21994793d65dSAlexey Kardashevskiy 22004793d65dSAlexey Kardashevskiy ret = pnv_pci_ioda2_table_alloc_pages(nid, 22014793d65dSAlexey Kardashevskiy bus_offset, page_shift, window_size, 22024793d65dSAlexey Kardashevskiy levels, tbl); 22034793d65dSAlexey Kardashevskiy if (ret) { 22044793d65dSAlexey Kardashevskiy iommu_free_table(tbl, "pnv"); 22054793d65dSAlexey Kardashevskiy return ret; 22064793d65dSAlexey Kardashevskiy } 22074793d65dSAlexey Kardashevskiy 22084793d65dSAlexey Kardashevskiy tbl->it_ops = &pnv_ioda2_iommu_ops; 22094793d65dSAlexey Kardashevskiy 22104793d65dSAlexey Kardashevskiy *ptbl = tbl; 22114793d65dSAlexey Kardashevskiy 22124793d65dSAlexey Kardashevskiy return 0; 22134793d65dSAlexey Kardashevskiy } 22144793d65dSAlexey Kardashevskiy 221546d3e1e1SAlexey Kardashevskiy static long pnv_pci_ioda2_setup_default_config(struct pnv_ioda_pe *pe) 221646d3e1e1SAlexey Kardashevskiy { 221746d3e1e1SAlexey Kardashevskiy struct iommu_table *tbl = NULL; 221846d3e1e1SAlexey Kardashevskiy long rc; 221946d3e1e1SAlexey Kardashevskiy 2220bb005455SNishanth Aravamudan /* 2221fa144869SNishanth Aravamudan * crashkernel= specifies the kdump kernel's maximum memory at 2222fa144869SNishanth Aravamudan * some offset and there is no guaranteed the result is a power 2223fa144869SNishanth Aravamudan * of 2, which will cause errors later. 2224fa144869SNishanth Aravamudan */ 2225fa144869SNishanth Aravamudan const u64 max_memory = __rounddown_pow_of_two(memory_hotplug_max()); 2226fa144869SNishanth Aravamudan 2227fa144869SNishanth Aravamudan /* 2228bb005455SNishanth Aravamudan * In memory constrained environments, e.g. kdump kernel, the 2229bb005455SNishanth Aravamudan * DMA window can be larger than available memory, which will 2230bb005455SNishanth Aravamudan * cause errors later. 2231bb005455SNishanth Aravamudan */ 2232fa144869SNishanth Aravamudan const u64 window_size = min((u64)pe->table_group.tce32_size, max_memory); 2233bb005455SNishanth Aravamudan 223446d3e1e1SAlexey Kardashevskiy rc = pnv_pci_ioda2_create_table(&pe->table_group, 0, 223546d3e1e1SAlexey Kardashevskiy IOMMU_PAGE_SHIFT_4K, 2236bb005455SNishanth Aravamudan window_size, 223746d3e1e1SAlexey Kardashevskiy POWERNV_IOMMU_DEFAULT_LEVELS, &tbl); 223846d3e1e1SAlexey Kardashevskiy if (rc) { 223946d3e1e1SAlexey Kardashevskiy pe_err(pe, "Failed to create 32-bit TCE table, err %ld", 224046d3e1e1SAlexey Kardashevskiy rc); 224146d3e1e1SAlexey Kardashevskiy return rc; 224246d3e1e1SAlexey Kardashevskiy } 224346d3e1e1SAlexey Kardashevskiy 224446d3e1e1SAlexey Kardashevskiy iommu_init_table(tbl, pe->phb->hose->node); 224546d3e1e1SAlexey Kardashevskiy 224646d3e1e1SAlexey Kardashevskiy rc = pnv_pci_ioda2_set_window(&pe->table_group, 0, tbl); 224746d3e1e1SAlexey Kardashevskiy if (rc) { 224846d3e1e1SAlexey Kardashevskiy pe_err(pe, "Failed to configure 32-bit TCE table, err %ld\n", 224946d3e1e1SAlexey Kardashevskiy rc); 225046d3e1e1SAlexey Kardashevskiy pnv_ioda2_table_free(tbl); 225146d3e1e1SAlexey Kardashevskiy return rc; 225246d3e1e1SAlexey Kardashevskiy } 225346d3e1e1SAlexey Kardashevskiy 225446d3e1e1SAlexey Kardashevskiy if (!pnv_iommu_bypass_disabled) 225546d3e1e1SAlexey Kardashevskiy pnv_pci_ioda2_set_bypass(pe, true); 225646d3e1e1SAlexey Kardashevskiy 225746d3e1e1SAlexey Kardashevskiy /* 225846d3e1e1SAlexey Kardashevskiy * Setting table base here only for carrying iommu_group 225946d3e1e1SAlexey Kardashevskiy * further down to let iommu_add_device() do the job. 226046d3e1e1SAlexey Kardashevskiy * pnv_pci_ioda_dma_dev_setup will override it later anyway. 226146d3e1e1SAlexey Kardashevskiy */ 226246d3e1e1SAlexey Kardashevskiy if (pe->flags & PNV_IODA_PE_DEV) 226346d3e1e1SAlexey Kardashevskiy set_iommu_table_base(&pe->pdev->dev, tbl); 226446d3e1e1SAlexey Kardashevskiy 226546d3e1e1SAlexey Kardashevskiy return 0; 226646d3e1e1SAlexey Kardashevskiy } 226746d3e1e1SAlexey Kardashevskiy 2268b5926430SAlexey Kardashevskiy #if defined(CONFIG_IOMMU_API) || defined(CONFIG_PCI_IOV) 2269b5926430SAlexey Kardashevskiy static long pnv_pci_ioda2_unset_window(struct iommu_table_group *table_group, 2270b5926430SAlexey Kardashevskiy int num) 2271b5926430SAlexey Kardashevskiy { 2272b5926430SAlexey Kardashevskiy struct pnv_ioda_pe *pe = container_of(table_group, struct pnv_ioda_pe, 2273b5926430SAlexey Kardashevskiy table_group); 2274b5926430SAlexey Kardashevskiy struct pnv_phb *phb = pe->phb; 2275b5926430SAlexey Kardashevskiy long ret; 2276b5926430SAlexey Kardashevskiy 2277b5926430SAlexey Kardashevskiy pe_info(pe, "Removing DMA window #%d\n", num); 2278b5926430SAlexey Kardashevskiy 2279b5926430SAlexey Kardashevskiy ret = opal_pci_map_pe_dma_window(phb->opal_id, pe->pe_number, 2280b5926430SAlexey Kardashevskiy (pe->pe_number << 1) + num, 2281b5926430SAlexey Kardashevskiy 0/* levels */, 0/* table address */, 2282b5926430SAlexey Kardashevskiy 0/* table size */, 0/* page size */); 2283b5926430SAlexey Kardashevskiy if (ret) 2284b5926430SAlexey Kardashevskiy pe_warn(pe, "Unmapping failed, ret = %ld\n", ret); 2285b5926430SAlexey Kardashevskiy else 2286a34ab7c3SBenjamin Herrenschmidt pnv_pci_phb3_tce_invalidate_pe(pe); 2287b5926430SAlexey Kardashevskiy 2288b5926430SAlexey Kardashevskiy pnv_pci_unlink_table_and_group(table_group->tables[num], table_group); 2289b5926430SAlexey Kardashevskiy 2290b5926430SAlexey Kardashevskiy return ret; 2291b5926430SAlexey Kardashevskiy } 2292b5926430SAlexey Kardashevskiy #endif 2293b5926430SAlexey Kardashevskiy 2294f87a8864SAlexey Kardashevskiy #ifdef CONFIG_IOMMU_API 229500547193SAlexey Kardashevskiy static unsigned long pnv_pci_ioda2_get_table_size(__u32 page_shift, 229600547193SAlexey Kardashevskiy __u64 window_size, __u32 levels) 229700547193SAlexey Kardashevskiy { 229800547193SAlexey Kardashevskiy unsigned long bytes = 0; 229900547193SAlexey Kardashevskiy const unsigned window_shift = ilog2(window_size); 230000547193SAlexey Kardashevskiy unsigned entries_shift = window_shift - page_shift; 230100547193SAlexey Kardashevskiy unsigned table_shift = entries_shift + 3; 230200547193SAlexey Kardashevskiy unsigned long tce_table_size = max(0x1000UL, 1UL << table_shift); 230300547193SAlexey Kardashevskiy unsigned long direct_table_size; 230400547193SAlexey Kardashevskiy 230500547193SAlexey Kardashevskiy if (!levels || (levels > POWERNV_IOMMU_MAX_LEVELS) || 230600547193SAlexey Kardashevskiy (window_size > memory_hotplug_max()) || 230700547193SAlexey Kardashevskiy !is_power_of_2(window_size)) 230800547193SAlexey Kardashevskiy return 0; 230900547193SAlexey Kardashevskiy 231000547193SAlexey Kardashevskiy /* Calculate a direct table size from window_size and levels */ 231100547193SAlexey Kardashevskiy entries_shift = (entries_shift + levels - 1) / levels; 231200547193SAlexey Kardashevskiy table_shift = entries_shift + 3; 231300547193SAlexey Kardashevskiy table_shift = max_t(unsigned, table_shift, PAGE_SHIFT); 231400547193SAlexey Kardashevskiy direct_table_size = 1UL << table_shift; 231500547193SAlexey Kardashevskiy 231600547193SAlexey Kardashevskiy for ( ; levels; --levels) { 231700547193SAlexey Kardashevskiy bytes += _ALIGN_UP(tce_table_size, direct_table_size); 231800547193SAlexey Kardashevskiy 231900547193SAlexey Kardashevskiy tce_table_size /= direct_table_size; 232000547193SAlexey Kardashevskiy tce_table_size <<= 3; 232100547193SAlexey Kardashevskiy tce_table_size = _ALIGN_UP(tce_table_size, direct_table_size); 232200547193SAlexey Kardashevskiy } 232300547193SAlexey Kardashevskiy 232400547193SAlexey Kardashevskiy return bytes; 232500547193SAlexey Kardashevskiy } 232600547193SAlexey Kardashevskiy 2327f87a8864SAlexey Kardashevskiy static void pnv_ioda2_take_ownership(struct iommu_table_group *table_group) 2328cd15b048SBenjamin Herrenschmidt { 2329f87a8864SAlexey Kardashevskiy struct pnv_ioda_pe *pe = container_of(table_group, struct pnv_ioda_pe, 2330f87a8864SAlexey Kardashevskiy table_group); 233146d3e1e1SAlexey Kardashevskiy /* Store @tbl as pnv_pci_ioda2_unset_window() resets it */ 233246d3e1e1SAlexey Kardashevskiy struct iommu_table *tbl = pe->table_group.tables[0]; 2333cd15b048SBenjamin Herrenschmidt 2334f87a8864SAlexey Kardashevskiy pnv_pci_ioda2_set_bypass(pe, false); 233546d3e1e1SAlexey Kardashevskiy pnv_pci_ioda2_unset_window(&pe->table_group, 0); 233646d3e1e1SAlexey Kardashevskiy pnv_ioda2_table_free(tbl); 2337cd15b048SBenjamin Herrenschmidt } 2338cd15b048SBenjamin Herrenschmidt 2339f87a8864SAlexey Kardashevskiy static void pnv_ioda2_release_ownership(struct iommu_table_group *table_group) 2340f87a8864SAlexey Kardashevskiy { 2341f87a8864SAlexey Kardashevskiy struct pnv_ioda_pe *pe = container_of(table_group, struct pnv_ioda_pe, 2342f87a8864SAlexey Kardashevskiy table_group); 2343f87a8864SAlexey Kardashevskiy 234446d3e1e1SAlexey Kardashevskiy pnv_pci_ioda2_setup_default_config(pe); 2345f87a8864SAlexey Kardashevskiy } 2346f87a8864SAlexey Kardashevskiy 2347f87a8864SAlexey Kardashevskiy static struct iommu_table_group_ops pnv_pci_ioda2_ops = { 234800547193SAlexey Kardashevskiy .get_table_size = pnv_pci_ioda2_get_table_size, 23494793d65dSAlexey Kardashevskiy .create_table = pnv_pci_ioda2_create_table, 23504793d65dSAlexey Kardashevskiy .set_window = pnv_pci_ioda2_set_window, 23514793d65dSAlexey Kardashevskiy .unset_window = pnv_pci_ioda2_unset_window, 2352f87a8864SAlexey Kardashevskiy .take_ownership = pnv_ioda2_take_ownership, 2353f87a8864SAlexey Kardashevskiy .release_ownership = pnv_ioda2_release_ownership, 2354f87a8864SAlexey Kardashevskiy }; 2355b5cb9ab1SAlexey Kardashevskiy 2356b5cb9ab1SAlexey Kardashevskiy static int gpe_table_group_to_npe_cb(struct device *dev, void *opaque) 2357b5cb9ab1SAlexey Kardashevskiy { 2358b5cb9ab1SAlexey Kardashevskiy struct pci_controller *hose; 2359b5cb9ab1SAlexey Kardashevskiy struct pnv_phb *phb; 2360b5cb9ab1SAlexey Kardashevskiy struct pnv_ioda_pe **ptmppe = opaque; 2361b5cb9ab1SAlexey Kardashevskiy struct pci_dev *pdev = container_of(dev, struct pci_dev, dev); 2362b5cb9ab1SAlexey Kardashevskiy struct pci_dn *pdn = pci_get_pdn(pdev); 2363b5cb9ab1SAlexey Kardashevskiy 2364b5cb9ab1SAlexey Kardashevskiy if (!pdn || pdn->pe_number == IODA_INVALID_PE) 2365b5cb9ab1SAlexey Kardashevskiy return 0; 2366b5cb9ab1SAlexey Kardashevskiy 2367b5cb9ab1SAlexey Kardashevskiy hose = pci_bus_to_host(pdev->bus); 2368b5cb9ab1SAlexey Kardashevskiy phb = hose->private_data; 2369b5cb9ab1SAlexey Kardashevskiy if (phb->type != PNV_PHB_NPU) 2370b5cb9ab1SAlexey Kardashevskiy return 0; 2371b5cb9ab1SAlexey Kardashevskiy 2372b5cb9ab1SAlexey Kardashevskiy *ptmppe = &phb->ioda.pe_array[pdn->pe_number]; 2373b5cb9ab1SAlexey Kardashevskiy 2374b5cb9ab1SAlexey Kardashevskiy return 1; 2375b5cb9ab1SAlexey Kardashevskiy } 2376b5cb9ab1SAlexey Kardashevskiy 2377b5cb9ab1SAlexey Kardashevskiy /* 2378b5cb9ab1SAlexey Kardashevskiy * This returns PE of associated NPU. 2379b5cb9ab1SAlexey Kardashevskiy * This assumes that NPU is in the same IOMMU group with GPU and there is 2380b5cb9ab1SAlexey Kardashevskiy * no other PEs. 2381b5cb9ab1SAlexey Kardashevskiy */ 2382b5cb9ab1SAlexey Kardashevskiy static struct pnv_ioda_pe *gpe_table_group_to_npe( 2383b5cb9ab1SAlexey Kardashevskiy struct iommu_table_group *table_group) 2384b5cb9ab1SAlexey Kardashevskiy { 2385b5cb9ab1SAlexey Kardashevskiy struct pnv_ioda_pe *npe = NULL; 2386b5cb9ab1SAlexey Kardashevskiy int ret = iommu_group_for_each_dev(table_group->group, &npe, 2387b5cb9ab1SAlexey Kardashevskiy gpe_table_group_to_npe_cb); 2388b5cb9ab1SAlexey Kardashevskiy 2389b5cb9ab1SAlexey Kardashevskiy BUG_ON(!ret || !npe); 2390b5cb9ab1SAlexey Kardashevskiy 2391b5cb9ab1SAlexey Kardashevskiy return npe; 2392b5cb9ab1SAlexey Kardashevskiy } 2393b5cb9ab1SAlexey Kardashevskiy 2394b5cb9ab1SAlexey Kardashevskiy static long pnv_pci_ioda2_npu_set_window(struct iommu_table_group *table_group, 2395b5cb9ab1SAlexey Kardashevskiy int num, struct iommu_table *tbl) 2396b5cb9ab1SAlexey Kardashevskiy { 2397b5cb9ab1SAlexey Kardashevskiy long ret = pnv_pci_ioda2_set_window(table_group, num, tbl); 2398b5cb9ab1SAlexey Kardashevskiy 2399b5cb9ab1SAlexey Kardashevskiy if (ret) 2400b5cb9ab1SAlexey Kardashevskiy return ret; 2401b5cb9ab1SAlexey Kardashevskiy 2402b5cb9ab1SAlexey Kardashevskiy ret = pnv_npu_set_window(gpe_table_group_to_npe(table_group), num, tbl); 2403b5cb9ab1SAlexey Kardashevskiy if (ret) 2404b5cb9ab1SAlexey Kardashevskiy pnv_pci_ioda2_unset_window(table_group, num); 2405b5cb9ab1SAlexey Kardashevskiy 2406b5cb9ab1SAlexey Kardashevskiy return ret; 2407b5cb9ab1SAlexey Kardashevskiy } 2408b5cb9ab1SAlexey Kardashevskiy 2409b5cb9ab1SAlexey Kardashevskiy static long pnv_pci_ioda2_npu_unset_window( 2410b5cb9ab1SAlexey Kardashevskiy struct iommu_table_group *table_group, 2411b5cb9ab1SAlexey Kardashevskiy int num) 2412b5cb9ab1SAlexey Kardashevskiy { 2413b5cb9ab1SAlexey Kardashevskiy long ret = pnv_pci_ioda2_unset_window(table_group, num); 2414b5cb9ab1SAlexey Kardashevskiy 2415b5cb9ab1SAlexey Kardashevskiy if (ret) 2416b5cb9ab1SAlexey Kardashevskiy return ret; 2417b5cb9ab1SAlexey Kardashevskiy 2418b5cb9ab1SAlexey Kardashevskiy return pnv_npu_unset_window(gpe_table_group_to_npe(table_group), num); 2419b5cb9ab1SAlexey Kardashevskiy } 2420b5cb9ab1SAlexey Kardashevskiy 2421b5cb9ab1SAlexey Kardashevskiy static void pnv_ioda2_npu_take_ownership(struct iommu_table_group *table_group) 2422b5cb9ab1SAlexey Kardashevskiy { 2423b5cb9ab1SAlexey Kardashevskiy /* 2424b5cb9ab1SAlexey Kardashevskiy * Detach NPU first as pnv_ioda2_take_ownership() will destroy 2425b5cb9ab1SAlexey Kardashevskiy * the iommu_table if 32bit DMA is enabled. 2426b5cb9ab1SAlexey Kardashevskiy */ 2427b5cb9ab1SAlexey Kardashevskiy pnv_npu_take_ownership(gpe_table_group_to_npe(table_group)); 2428b5cb9ab1SAlexey Kardashevskiy pnv_ioda2_take_ownership(table_group); 2429b5cb9ab1SAlexey Kardashevskiy } 2430b5cb9ab1SAlexey Kardashevskiy 2431b5cb9ab1SAlexey Kardashevskiy static struct iommu_table_group_ops pnv_pci_ioda2_npu_ops = { 2432b5cb9ab1SAlexey Kardashevskiy .get_table_size = pnv_pci_ioda2_get_table_size, 2433b5cb9ab1SAlexey Kardashevskiy .create_table = pnv_pci_ioda2_create_table, 2434b5cb9ab1SAlexey Kardashevskiy .set_window = pnv_pci_ioda2_npu_set_window, 2435b5cb9ab1SAlexey Kardashevskiy .unset_window = pnv_pci_ioda2_npu_unset_window, 2436b5cb9ab1SAlexey Kardashevskiy .take_ownership = pnv_ioda2_npu_take_ownership, 2437b5cb9ab1SAlexey Kardashevskiy .release_ownership = pnv_ioda2_release_ownership, 2438b5cb9ab1SAlexey Kardashevskiy }; 2439b5cb9ab1SAlexey Kardashevskiy 2440b5cb9ab1SAlexey Kardashevskiy static void pnv_pci_ioda_setup_iommu_api(void) 2441b5cb9ab1SAlexey Kardashevskiy { 2442b5cb9ab1SAlexey Kardashevskiy struct pci_controller *hose, *tmp; 2443b5cb9ab1SAlexey Kardashevskiy struct pnv_phb *phb; 2444b5cb9ab1SAlexey Kardashevskiy struct pnv_ioda_pe *pe, *gpe; 2445b5cb9ab1SAlexey Kardashevskiy 2446b5cb9ab1SAlexey Kardashevskiy /* 2447b5cb9ab1SAlexey Kardashevskiy * Now we have all PHBs discovered, time to add NPU devices to 2448b5cb9ab1SAlexey Kardashevskiy * the corresponding IOMMU groups. 2449b5cb9ab1SAlexey Kardashevskiy */ 2450b5cb9ab1SAlexey Kardashevskiy list_for_each_entry_safe(hose, tmp, &hose_list, list_node) { 2451b5cb9ab1SAlexey Kardashevskiy phb = hose->private_data; 2452b5cb9ab1SAlexey Kardashevskiy 2453b5cb9ab1SAlexey Kardashevskiy if (phb->type != PNV_PHB_NPU) 2454b5cb9ab1SAlexey Kardashevskiy continue; 2455b5cb9ab1SAlexey Kardashevskiy 2456b5cb9ab1SAlexey Kardashevskiy list_for_each_entry(pe, &phb->ioda.pe_list, list) { 2457b5cb9ab1SAlexey Kardashevskiy gpe = pnv_pci_npu_setup_iommu(pe); 2458b5cb9ab1SAlexey Kardashevskiy if (gpe) 2459b5cb9ab1SAlexey Kardashevskiy gpe->table_group.ops = &pnv_pci_ioda2_npu_ops; 2460b5cb9ab1SAlexey Kardashevskiy } 2461b5cb9ab1SAlexey Kardashevskiy } 2462b5cb9ab1SAlexey Kardashevskiy } 2463b5cb9ab1SAlexey Kardashevskiy #else /* !CONFIG_IOMMU_API */ 2464b5cb9ab1SAlexey Kardashevskiy static void pnv_pci_ioda_setup_iommu_api(void) { }; 2465f87a8864SAlexey Kardashevskiy #endif 2466f87a8864SAlexey Kardashevskiy 2467bbb845c4SAlexey Kardashevskiy static __be64 *pnv_pci_ioda2_table_do_alloc_pages(int nid, unsigned shift, 2468bbb845c4SAlexey Kardashevskiy unsigned levels, unsigned long limit, 24693ba3a73eSAlexey Kardashevskiy unsigned long *current_offset, unsigned long *total_allocated) 2470aca6913fSAlexey Kardashevskiy { 2471aca6913fSAlexey Kardashevskiy struct page *tce_mem = NULL; 2472bbb845c4SAlexey Kardashevskiy __be64 *addr, *tmp; 2473aca6913fSAlexey Kardashevskiy unsigned order = max_t(unsigned, shift, PAGE_SHIFT) - PAGE_SHIFT; 2474bbb845c4SAlexey Kardashevskiy unsigned long allocated = 1UL << (order + PAGE_SHIFT); 2475bbb845c4SAlexey Kardashevskiy unsigned entries = 1UL << (shift - 3); 2476bbb845c4SAlexey Kardashevskiy long i; 2477aca6913fSAlexey Kardashevskiy 2478aca6913fSAlexey Kardashevskiy tce_mem = alloc_pages_node(nid, GFP_KERNEL, order); 2479aca6913fSAlexey Kardashevskiy if (!tce_mem) { 2480aca6913fSAlexey Kardashevskiy pr_err("Failed to allocate a TCE memory, order=%d\n", order); 2481aca6913fSAlexey Kardashevskiy return NULL; 2482aca6913fSAlexey Kardashevskiy } 2483aca6913fSAlexey Kardashevskiy addr = page_address(tce_mem); 2484bbb845c4SAlexey Kardashevskiy memset(addr, 0, allocated); 24853ba3a73eSAlexey Kardashevskiy *total_allocated += allocated; 2486bbb845c4SAlexey Kardashevskiy 2487bbb845c4SAlexey Kardashevskiy --levels; 2488bbb845c4SAlexey Kardashevskiy if (!levels) { 2489bbb845c4SAlexey Kardashevskiy *current_offset += allocated; 2490bbb845c4SAlexey Kardashevskiy return addr; 2491bbb845c4SAlexey Kardashevskiy } 2492bbb845c4SAlexey Kardashevskiy 2493bbb845c4SAlexey Kardashevskiy for (i = 0; i < entries; ++i) { 2494bbb845c4SAlexey Kardashevskiy tmp = pnv_pci_ioda2_table_do_alloc_pages(nid, shift, 24953ba3a73eSAlexey Kardashevskiy levels, limit, current_offset, total_allocated); 2496bbb845c4SAlexey Kardashevskiy if (!tmp) 2497bbb845c4SAlexey Kardashevskiy break; 2498bbb845c4SAlexey Kardashevskiy 2499bbb845c4SAlexey Kardashevskiy addr[i] = cpu_to_be64(__pa(tmp) | 2500bbb845c4SAlexey Kardashevskiy TCE_PCI_READ | TCE_PCI_WRITE); 2501bbb845c4SAlexey Kardashevskiy 2502bbb845c4SAlexey Kardashevskiy if (*current_offset >= limit) 2503bbb845c4SAlexey Kardashevskiy break; 2504bbb845c4SAlexey Kardashevskiy } 2505aca6913fSAlexey Kardashevskiy 2506aca6913fSAlexey Kardashevskiy return addr; 2507aca6913fSAlexey Kardashevskiy } 2508aca6913fSAlexey Kardashevskiy 2509bbb845c4SAlexey Kardashevskiy static void pnv_pci_ioda2_table_do_free_pages(__be64 *addr, 2510bbb845c4SAlexey Kardashevskiy unsigned long size, unsigned level); 2511bbb845c4SAlexey Kardashevskiy 2512aca6913fSAlexey Kardashevskiy static long pnv_pci_ioda2_table_alloc_pages(int nid, __u64 bus_offset, 2513bbb845c4SAlexey Kardashevskiy __u32 page_shift, __u64 window_size, __u32 levels, 2514bbb845c4SAlexey Kardashevskiy struct iommu_table *tbl) 2515aca6913fSAlexey Kardashevskiy { 2516aca6913fSAlexey Kardashevskiy void *addr; 25173ba3a73eSAlexey Kardashevskiy unsigned long offset = 0, level_shift, total_allocated = 0; 2518aca6913fSAlexey Kardashevskiy const unsigned window_shift = ilog2(window_size); 2519aca6913fSAlexey Kardashevskiy unsigned entries_shift = window_shift - page_shift; 2520aca6913fSAlexey Kardashevskiy unsigned table_shift = max_t(unsigned, entries_shift + 3, PAGE_SHIFT); 2521aca6913fSAlexey Kardashevskiy const unsigned long tce_table_size = 1UL << table_shift; 2522aca6913fSAlexey Kardashevskiy 2523bbb845c4SAlexey Kardashevskiy if (!levels || (levels > POWERNV_IOMMU_MAX_LEVELS)) 2524bbb845c4SAlexey Kardashevskiy return -EINVAL; 2525bbb845c4SAlexey Kardashevskiy 2526aca6913fSAlexey Kardashevskiy if ((window_size > memory_hotplug_max()) || !is_power_of_2(window_size)) 2527aca6913fSAlexey Kardashevskiy return -EINVAL; 2528aca6913fSAlexey Kardashevskiy 2529bbb845c4SAlexey Kardashevskiy /* Adjust direct table size from window_size and levels */ 2530bbb845c4SAlexey Kardashevskiy entries_shift = (entries_shift + levels - 1) / levels; 2531bbb845c4SAlexey Kardashevskiy level_shift = entries_shift + 3; 2532bbb845c4SAlexey Kardashevskiy level_shift = max_t(unsigned, level_shift, PAGE_SHIFT); 2533bbb845c4SAlexey Kardashevskiy 2534aca6913fSAlexey Kardashevskiy /* Allocate TCE table */ 2535bbb845c4SAlexey Kardashevskiy addr = pnv_pci_ioda2_table_do_alloc_pages(nid, level_shift, 25363ba3a73eSAlexey Kardashevskiy levels, tce_table_size, &offset, &total_allocated); 2537bbb845c4SAlexey Kardashevskiy 2538bbb845c4SAlexey Kardashevskiy /* addr==NULL means that the first level allocation failed */ 2539aca6913fSAlexey Kardashevskiy if (!addr) 2540aca6913fSAlexey Kardashevskiy return -ENOMEM; 2541aca6913fSAlexey Kardashevskiy 2542bbb845c4SAlexey Kardashevskiy /* 2543bbb845c4SAlexey Kardashevskiy * First level was allocated but some lower level failed as 2544bbb845c4SAlexey Kardashevskiy * we did not allocate as much as we wanted, 2545bbb845c4SAlexey Kardashevskiy * release partially allocated table. 2546bbb845c4SAlexey Kardashevskiy */ 2547bbb845c4SAlexey Kardashevskiy if (offset < tce_table_size) { 2548bbb845c4SAlexey Kardashevskiy pnv_pci_ioda2_table_do_free_pages(addr, 2549bbb845c4SAlexey Kardashevskiy 1ULL << (level_shift - 3), levels - 1); 2550bbb845c4SAlexey Kardashevskiy return -ENOMEM; 2551bbb845c4SAlexey Kardashevskiy } 2552bbb845c4SAlexey Kardashevskiy 2553aca6913fSAlexey Kardashevskiy /* Setup linux iommu table */ 2554aca6913fSAlexey Kardashevskiy pnv_pci_setup_iommu_table(tbl, addr, tce_table_size, bus_offset, 2555aca6913fSAlexey Kardashevskiy page_shift); 2556bbb845c4SAlexey Kardashevskiy tbl->it_level_size = 1ULL << (level_shift - 3); 2557bbb845c4SAlexey Kardashevskiy tbl->it_indirect_levels = levels - 1; 25583ba3a73eSAlexey Kardashevskiy tbl->it_allocated_size = total_allocated; 2559aca6913fSAlexey Kardashevskiy 2560aca6913fSAlexey Kardashevskiy pr_devel("Created TCE table: ws=%08llx ts=%lx @%08llx\n", 2561aca6913fSAlexey Kardashevskiy window_size, tce_table_size, bus_offset); 2562aca6913fSAlexey Kardashevskiy 2563aca6913fSAlexey Kardashevskiy return 0; 2564aca6913fSAlexey Kardashevskiy } 2565aca6913fSAlexey Kardashevskiy 2566bbb845c4SAlexey Kardashevskiy static void pnv_pci_ioda2_table_do_free_pages(__be64 *addr, 2567bbb845c4SAlexey Kardashevskiy unsigned long size, unsigned level) 2568bbb845c4SAlexey Kardashevskiy { 2569bbb845c4SAlexey Kardashevskiy const unsigned long addr_ul = (unsigned long) addr & 2570bbb845c4SAlexey Kardashevskiy ~(TCE_PCI_READ | TCE_PCI_WRITE); 2571bbb845c4SAlexey Kardashevskiy 2572bbb845c4SAlexey Kardashevskiy if (level) { 2573bbb845c4SAlexey Kardashevskiy long i; 2574bbb845c4SAlexey Kardashevskiy u64 *tmp = (u64 *) addr_ul; 2575bbb845c4SAlexey Kardashevskiy 2576bbb845c4SAlexey Kardashevskiy for (i = 0; i < size; ++i) { 2577bbb845c4SAlexey Kardashevskiy unsigned long hpa = be64_to_cpu(tmp[i]); 2578bbb845c4SAlexey Kardashevskiy 2579bbb845c4SAlexey Kardashevskiy if (!(hpa & (TCE_PCI_READ | TCE_PCI_WRITE))) 2580bbb845c4SAlexey Kardashevskiy continue; 2581bbb845c4SAlexey Kardashevskiy 2582bbb845c4SAlexey Kardashevskiy pnv_pci_ioda2_table_do_free_pages(__va(hpa), size, 2583bbb845c4SAlexey Kardashevskiy level - 1); 2584bbb845c4SAlexey Kardashevskiy } 2585bbb845c4SAlexey Kardashevskiy } 2586bbb845c4SAlexey Kardashevskiy 2587bbb845c4SAlexey Kardashevskiy free_pages(addr_ul, get_order(size << 3)); 2588bbb845c4SAlexey Kardashevskiy } 2589bbb845c4SAlexey Kardashevskiy 2590aca6913fSAlexey Kardashevskiy static void pnv_pci_ioda2_table_free_pages(struct iommu_table *tbl) 2591aca6913fSAlexey Kardashevskiy { 2592bbb845c4SAlexey Kardashevskiy const unsigned long size = tbl->it_indirect_levels ? 2593bbb845c4SAlexey Kardashevskiy tbl->it_level_size : tbl->it_size; 2594bbb845c4SAlexey Kardashevskiy 2595aca6913fSAlexey Kardashevskiy if (!tbl->it_size) 2596aca6913fSAlexey Kardashevskiy return; 2597aca6913fSAlexey Kardashevskiy 2598bbb845c4SAlexey Kardashevskiy pnv_pci_ioda2_table_do_free_pages((__be64 *)tbl->it_base, size, 2599bbb845c4SAlexey Kardashevskiy tbl->it_indirect_levels); 2600aca6913fSAlexey Kardashevskiy } 2601aca6913fSAlexey Kardashevskiy 2602373f5657SGavin Shan static void pnv_pci_ioda2_setup_dma_pe(struct pnv_phb *phb, 2603373f5657SGavin Shan struct pnv_ioda_pe *pe) 2604373f5657SGavin Shan { 2605373f5657SGavin Shan int64_t rc; 2606373f5657SGavin Shan 2607ccd1c191SGavin Shan if (!pnv_pci_ioda_pe_dma_weight(pe)) 2608ccd1c191SGavin Shan return; 2609ccd1c191SGavin Shan 2610f87a8864SAlexey Kardashevskiy /* TVE #1 is selected by PCI address bit 59 */ 2611f87a8864SAlexey Kardashevskiy pe->tce_bypass_base = 1ull << 59; 2612f87a8864SAlexey Kardashevskiy 2613b348aa65SAlexey Kardashevskiy iommu_register_group(&pe->table_group, phb->hose->global_number, 2614b348aa65SAlexey Kardashevskiy pe->pe_number); 2615c5773822SAlexey Kardashevskiy 2616373f5657SGavin Shan /* The PE will reserve all possible 32-bits space */ 2617373f5657SGavin Shan pe_info(pe, "Setting up 32-bit TCE table at 0..%08x\n", 2618aca6913fSAlexey Kardashevskiy phb->ioda.m32_pci_base); 2619373f5657SGavin Shan 2620e5aad1e6SAlexey Kardashevskiy /* Setup linux iommu table */ 26214793d65dSAlexey Kardashevskiy pe->table_group.tce32_start = 0; 26224793d65dSAlexey Kardashevskiy pe->table_group.tce32_size = phb->ioda.m32_pci_base; 26234793d65dSAlexey Kardashevskiy pe->table_group.max_dynamic_windows_supported = 26244793d65dSAlexey Kardashevskiy IOMMU_TABLE_GROUP_MAX_TABLES; 26254793d65dSAlexey Kardashevskiy pe->table_group.max_levels = POWERNV_IOMMU_MAX_LEVELS; 26264793d65dSAlexey Kardashevskiy pe->table_group.pgsizes = SZ_4K | SZ_64K | SZ_16M; 2627e5aad1e6SAlexey Kardashevskiy #ifdef CONFIG_IOMMU_API 2628e5aad1e6SAlexey Kardashevskiy pe->table_group.ops = &pnv_pci_ioda2_ops; 2629e5aad1e6SAlexey Kardashevskiy #endif 2630e5aad1e6SAlexey Kardashevskiy 263146d3e1e1SAlexey Kardashevskiy rc = pnv_pci_ioda2_setup_default_config(pe); 2632801846d1SGavin Shan if (rc) 263346d3e1e1SAlexey Kardashevskiy return; 263446d3e1e1SAlexey Kardashevskiy 263546d3e1e1SAlexey Kardashevskiy if (pe->flags & PNV_IODA_PE_DEV) 263646d3e1e1SAlexey Kardashevskiy iommu_add_device(&pe->pdev->dev); 263746d3e1e1SAlexey Kardashevskiy else if (pe->flags & (PNV_IODA_PE_BUS | PNV_IODA_PE_BUS_ALL)) 263846d3e1e1SAlexey Kardashevskiy pnv_ioda_setup_bus_dma(pe, pe->pbus); 2639373f5657SGavin Shan } 2640373f5657SGavin Shan 2641184cd4a3SBenjamin Herrenschmidt #ifdef CONFIG_PCI_MSI 2642137436c9SGavin Shan static void pnv_ioda2_msi_eoi(struct irq_data *d) 2643137436c9SGavin Shan { 2644137436c9SGavin Shan unsigned int hw_irq = (unsigned int)irqd_to_hwirq(d); 2645137436c9SGavin Shan struct irq_chip *chip = irq_data_get_irq_chip(d); 2646137436c9SGavin Shan struct pnv_phb *phb = container_of(chip, struct pnv_phb, 2647137436c9SGavin Shan ioda.irq_chip); 2648137436c9SGavin Shan int64_t rc; 2649137436c9SGavin Shan 2650137436c9SGavin Shan rc = opal_pci_msi_eoi(phb->opal_id, hw_irq); 2651137436c9SGavin Shan WARN_ON_ONCE(rc); 2652137436c9SGavin Shan 2653137436c9SGavin Shan icp_native_eoi(d); 2654137436c9SGavin Shan } 2655137436c9SGavin Shan 2656fd9a1c26SIan Munsie 2657f456834aSIan Munsie void pnv_set_msi_irq_chip(struct pnv_phb *phb, unsigned int virq) 2658fd9a1c26SIan Munsie { 2659fd9a1c26SIan Munsie struct irq_data *idata; 2660fd9a1c26SIan Munsie struct irq_chip *ichip; 2661fd9a1c26SIan Munsie 2662fb111334SBenjamin Herrenschmidt /* The MSI EOI OPAL call is only needed on PHB3 */ 2663fb111334SBenjamin Herrenschmidt if (phb->model != PNV_PHB_MODEL_PHB3) 2664fd9a1c26SIan Munsie return; 2665fd9a1c26SIan Munsie 2666fd9a1c26SIan Munsie if (!phb->ioda.irq_chip_init) { 2667fd9a1c26SIan Munsie /* 2668fd9a1c26SIan Munsie * First time we setup an MSI IRQ, we need to setup the 2669fd9a1c26SIan Munsie * corresponding IRQ chip to route correctly. 2670fd9a1c26SIan Munsie */ 2671fd9a1c26SIan Munsie idata = irq_get_irq_data(virq); 2672fd9a1c26SIan Munsie ichip = irq_data_get_irq_chip(idata); 2673fd9a1c26SIan Munsie phb->ioda.irq_chip_init = 1; 2674fd9a1c26SIan Munsie phb->ioda.irq_chip = *ichip; 2675fd9a1c26SIan Munsie phb->ioda.irq_chip.irq_eoi = pnv_ioda2_msi_eoi; 2676fd9a1c26SIan Munsie } 2677fd9a1c26SIan Munsie irq_set_chip(virq, &phb->ioda.irq_chip); 2678fd9a1c26SIan Munsie } 2679fd9a1c26SIan Munsie 2680184cd4a3SBenjamin Herrenschmidt static int pnv_pci_ioda_msi_setup(struct pnv_phb *phb, struct pci_dev *dev, 2681137436c9SGavin Shan unsigned int hwirq, unsigned int virq, 2682137436c9SGavin Shan unsigned int is_64, struct msi_msg *msg) 2683184cd4a3SBenjamin Herrenschmidt { 2684184cd4a3SBenjamin Herrenschmidt struct pnv_ioda_pe *pe = pnv_ioda_get_pe(dev); 2685184cd4a3SBenjamin Herrenschmidt unsigned int xive_num = hwirq - phb->msi_base; 26863a1a4661SBenjamin Herrenschmidt __be32 data; 2687184cd4a3SBenjamin Herrenschmidt int rc; 2688184cd4a3SBenjamin Herrenschmidt 2689184cd4a3SBenjamin Herrenschmidt /* No PE assigned ? bail out ... no MSI for you ! */ 2690184cd4a3SBenjamin Herrenschmidt if (pe == NULL) 2691184cd4a3SBenjamin Herrenschmidt return -ENXIO; 2692184cd4a3SBenjamin Herrenschmidt 2693184cd4a3SBenjamin Herrenschmidt /* Check if we have an MVE */ 2694184cd4a3SBenjamin Herrenschmidt if (pe->mve_number < 0) 2695184cd4a3SBenjamin Herrenschmidt return -ENXIO; 2696184cd4a3SBenjamin Herrenschmidt 2697b72c1f65SBenjamin Herrenschmidt /* Force 32-bit MSI on some broken devices */ 269836074381SBenjamin Herrenschmidt if (dev->no_64bit_msi) 2699b72c1f65SBenjamin Herrenschmidt is_64 = 0; 2700b72c1f65SBenjamin Herrenschmidt 2701184cd4a3SBenjamin Herrenschmidt /* Assign XIVE to PE */ 2702184cd4a3SBenjamin Herrenschmidt rc = opal_pci_set_xive_pe(phb->opal_id, pe->pe_number, xive_num); 2703184cd4a3SBenjamin Herrenschmidt if (rc) { 2704184cd4a3SBenjamin Herrenschmidt pr_warn("%s: OPAL error %d setting XIVE %d PE\n", 2705184cd4a3SBenjamin Herrenschmidt pci_name(dev), rc, xive_num); 2706184cd4a3SBenjamin Herrenschmidt return -EIO; 2707184cd4a3SBenjamin Herrenschmidt } 2708184cd4a3SBenjamin Herrenschmidt 2709184cd4a3SBenjamin Herrenschmidt if (is_64) { 27103a1a4661SBenjamin Herrenschmidt __be64 addr64; 27113a1a4661SBenjamin Herrenschmidt 2712184cd4a3SBenjamin Herrenschmidt rc = opal_get_msi_64(phb->opal_id, pe->mve_number, xive_num, 1, 2713184cd4a3SBenjamin Herrenschmidt &addr64, &data); 2714184cd4a3SBenjamin Herrenschmidt if (rc) { 2715184cd4a3SBenjamin Herrenschmidt pr_warn("%s: OPAL error %d getting 64-bit MSI data\n", 2716184cd4a3SBenjamin Herrenschmidt pci_name(dev), rc); 2717184cd4a3SBenjamin Herrenschmidt return -EIO; 2718184cd4a3SBenjamin Herrenschmidt } 27193a1a4661SBenjamin Herrenschmidt msg->address_hi = be64_to_cpu(addr64) >> 32; 27203a1a4661SBenjamin Herrenschmidt msg->address_lo = be64_to_cpu(addr64) & 0xfffffffful; 2721184cd4a3SBenjamin Herrenschmidt } else { 27223a1a4661SBenjamin Herrenschmidt __be32 addr32; 27233a1a4661SBenjamin Herrenschmidt 2724184cd4a3SBenjamin Herrenschmidt rc = opal_get_msi_32(phb->opal_id, pe->mve_number, xive_num, 1, 2725184cd4a3SBenjamin Herrenschmidt &addr32, &data); 2726184cd4a3SBenjamin Herrenschmidt if (rc) { 2727184cd4a3SBenjamin Herrenschmidt pr_warn("%s: OPAL error %d getting 32-bit MSI data\n", 2728184cd4a3SBenjamin Herrenschmidt pci_name(dev), rc); 2729184cd4a3SBenjamin Herrenschmidt return -EIO; 2730184cd4a3SBenjamin Herrenschmidt } 2731184cd4a3SBenjamin Herrenschmidt msg->address_hi = 0; 27323a1a4661SBenjamin Herrenschmidt msg->address_lo = be32_to_cpu(addr32); 2733184cd4a3SBenjamin Herrenschmidt } 27343a1a4661SBenjamin Herrenschmidt msg->data = be32_to_cpu(data); 2735184cd4a3SBenjamin Herrenschmidt 2736f456834aSIan Munsie pnv_set_msi_irq_chip(phb, virq); 2737137436c9SGavin Shan 2738184cd4a3SBenjamin Herrenschmidt pr_devel("%s: %s-bit MSI on hwirq %x (xive #%d)," 2739184cd4a3SBenjamin Herrenschmidt " address=%x_%08x data=%x PE# %d\n", 2740184cd4a3SBenjamin Herrenschmidt pci_name(dev), is_64 ? "64" : "32", hwirq, xive_num, 2741184cd4a3SBenjamin Herrenschmidt msg->address_hi, msg->address_lo, data, pe->pe_number); 2742184cd4a3SBenjamin Herrenschmidt 2743184cd4a3SBenjamin Herrenschmidt return 0; 2744184cd4a3SBenjamin Herrenschmidt } 2745184cd4a3SBenjamin Herrenschmidt 2746184cd4a3SBenjamin Herrenschmidt static void pnv_pci_init_ioda_msis(struct pnv_phb *phb) 2747184cd4a3SBenjamin Herrenschmidt { 2748fb1b55d6SGavin Shan unsigned int count; 2749184cd4a3SBenjamin Herrenschmidt const __be32 *prop = of_get_property(phb->hose->dn, 2750184cd4a3SBenjamin Herrenschmidt "ibm,opal-msi-ranges", NULL); 2751184cd4a3SBenjamin Herrenschmidt if (!prop) { 2752184cd4a3SBenjamin Herrenschmidt /* BML Fallback */ 2753184cd4a3SBenjamin Herrenschmidt prop = of_get_property(phb->hose->dn, "msi-ranges", NULL); 2754184cd4a3SBenjamin Herrenschmidt } 2755184cd4a3SBenjamin Herrenschmidt if (!prop) 2756184cd4a3SBenjamin Herrenschmidt return; 2757184cd4a3SBenjamin Herrenschmidt 2758184cd4a3SBenjamin Herrenschmidt phb->msi_base = be32_to_cpup(prop); 2759fb1b55d6SGavin Shan count = be32_to_cpup(prop + 1); 2760fb1b55d6SGavin Shan if (msi_bitmap_alloc(&phb->msi_bmp, count, phb->hose->dn)) { 2761184cd4a3SBenjamin Herrenschmidt pr_err("PCI %d: Failed to allocate MSI bitmap !\n", 2762184cd4a3SBenjamin Herrenschmidt phb->hose->global_number); 2763184cd4a3SBenjamin Herrenschmidt return; 2764184cd4a3SBenjamin Herrenschmidt } 2765fb1b55d6SGavin Shan 2766184cd4a3SBenjamin Herrenschmidt phb->msi_setup = pnv_pci_ioda_msi_setup; 2767184cd4a3SBenjamin Herrenschmidt phb->msi32_support = 1; 2768184cd4a3SBenjamin Herrenschmidt pr_info(" Allocated bitmap for %d MSIs (base IRQ 0x%x)\n", 2769fb1b55d6SGavin Shan count, phb->msi_base); 2770184cd4a3SBenjamin Herrenschmidt } 2771184cd4a3SBenjamin Herrenschmidt #else 2772184cd4a3SBenjamin Herrenschmidt static void pnv_pci_init_ioda_msis(struct pnv_phb *phb) { } 2773184cd4a3SBenjamin Herrenschmidt #endif /* CONFIG_PCI_MSI */ 2774184cd4a3SBenjamin Herrenschmidt 27756e628c7dSWei Yang #ifdef CONFIG_PCI_IOV 27766e628c7dSWei Yang static void pnv_pci_ioda_fixup_iov_resources(struct pci_dev *pdev) 27776e628c7dSWei Yang { 2778f2dd0afeSWei Yang struct pci_controller *hose = pci_bus_to_host(pdev->bus); 2779f2dd0afeSWei Yang struct pnv_phb *phb = hose->private_data; 2780f2dd0afeSWei Yang const resource_size_t gate = phb->ioda.m64_segsize >> 2; 27816e628c7dSWei Yang struct resource *res; 27826e628c7dSWei Yang int i; 2783dfcc8d45SWei Yang resource_size_t size, total_vf_bar_sz; 27846e628c7dSWei Yang struct pci_dn *pdn; 27855b88ec22SWei Yang int mul, total_vfs; 27866e628c7dSWei Yang 27876e628c7dSWei Yang if (!pdev->is_physfn || pdev->is_added) 27886e628c7dSWei Yang return; 27896e628c7dSWei Yang 27906e628c7dSWei Yang pdn = pci_get_pdn(pdev); 27916e628c7dSWei Yang pdn->vfs_expanded = 0; 2792ee8222feSWei Yang pdn->m64_single_mode = false; 27936e628c7dSWei Yang 27945b88ec22SWei Yang total_vfs = pci_sriov_get_totalvfs(pdev); 279592b8f137SGavin Shan mul = phb->ioda.total_pe_num; 2796dfcc8d45SWei Yang total_vf_bar_sz = 0; 27975b88ec22SWei Yang 27985b88ec22SWei Yang for (i = 0; i < PCI_SRIOV_NUM_BARS; i++) { 27995b88ec22SWei Yang res = &pdev->resource[i + PCI_IOV_RESOURCES]; 28005b88ec22SWei Yang if (!res->flags || res->parent) 28015b88ec22SWei Yang continue; 28025b88ec22SWei Yang if (!pnv_pci_is_mem_pref_64(res->flags)) { 2803b0331854SWei Yang dev_warn(&pdev->dev, "Don't support SR-IOV with" 2804b0331854SWei Yang " non M64 VF BAR%d: %pR. \n", 28055b88ec22SWei Yang i, res); 2806b0331854SWei Yang goto truncate_iov; 28075b88ec22SWei Yang } 28085b88ec22SWei Yang 2809dfcc8d45SWei Yang total_vf_bar_sz += pci_iov_resource_size(pdev, 2810dfcc8d45SWei Yang i + PCI_IOV_RESOURCES); 28115b88ec22SWei Yang 2812f2dd0afeSWei Yang /* 2813f2dd0afeSWei Yang * If bigger than quarter of M64 segment size, just round up 2814f2dd0afeSWei Yang * power of two. 2815f2dd0afeSWei Yang * 2816f2dd0afeSWei Yang * Generally, one M64 BAR maps one IOV BAR. To avoid conflict 2817f2dd0afeSWei Yang * with other devices, IOV BAR size is expanded to be 2818f2dd0afeSWei Yang * (total_pe * VF_BAR_size). When VF_BAR_size is half of M64 2819f2dd0afeSWei Yang * segment size , the expanded size would equal to half of the 2820f2dd0afeSWei Yang * whole M64 space size, which will exhaust the M64 Space and 2821f2dd0afeSWei Yang * limit the system flexibility. This is a design decision to 2822f2dd0afeSWei Yang * set the boundary to quarter of the M64 segment size. 2823f2dd0afeSWei Yang */ 2824dfcc8d45SWei Yang if (total_vf_bar_sz > gate) { 28255b88ec22SWei Yang mul = roundup_pow_of_two(total_vfs); 2826dfcc8d45SWei Yang dev_info(&pdev->dev, 2827dfcc8d45SWei Yang "VF BAR Total IOV size %llx > %llx, roundup to %d VFs\n", 2828dfcc8d45SWei Yang total_vf_bar_sz, gate, mul); 2829ee8222feSWei Yang pdn->m64_single_mode = true; 28305b88ec22SWei Yang break; 28315b88ec22SWei Yang } 28325b88ec22SWei Yang } 28335b88ec22SWei Yang 28346e628c7dSWei Yang for (i = 0; i < PCI_SRIOV_NUM_BARS; i++) { 28356e628c7dSWei Yang res = &pdev->resource[i + PCI_IOV_RESOURCES]; 28366e628c7dSWei Yang if (!res->flags || res->parent) 28376e628c7dSWei Yang continue; 28386e628c7dSWei Yang 28396e628c7dSWei Yang size = pci_iov_resource_size(pdev, i + PCI_IOV_RESOURCES); 2840ee8222feSWei Yang /* 2841ee8222feSWei Yang * On PHB3, the minimum size alignment of M64 BAR in single 2842ee8222feSWei Yang * mode is 32MB. 2843ee8222feSWei Yang */ 2844ee8222feSWei Yang if (pdn->m64_single_mode && (size < SZ_32M)) 2845ee8222feSWei Yang goto truncate_iov; 2846ee8222feSWei Yang dev_dbg(&pdev->dev, " Fixing VF BAR%d: %pR to\n", i, res); 28475b88ec22SWei Yang res->end = res->start + size * mul - 1; 28486e628c7dSWei Yang dev_dbg(&pdev->dev, " %pR\n", res); 28496e628c7dSWei Yang dev_info(&pdev->dev, "VF BAR%d: %pR (expanded to %d VFs for PE alignment)", 28505b88ec22SWei Yang i, res, mul); 28516e628c7dSWei Yang } 28525b88ec22SWei Yang pdn->vfs_expanded = mul; 2853b0331854SWei Yang 2854b0331854SWei Yang return; 2855b0331854SWei Yang 2856b0331854SWei Yang truncate_iov: 2857b0331854SWei Yang /* To save MMIO space, IOV BAR is truncated. */ 2858b0331854SWei Yang for (i = 0; i < PCI_SRIOV_NUM_BARS; i++) { 2859b0331854SWei Yang res = &pdev->resource[i + PCI_IOV_RESOURCES]; 2860b0331854SWei Yang res->flags = 0; 2861b0331854SWei Yang res->end = res->start - 1; 2862b0331854SWei Yang } 28636e628c7dSWei Yang } 28646e628c7dSWei Yang #endif /* CONFIG_PCI_IOV */ 28656e628c7dSWei Yang 286623e79425SGavin Shan static void pnv_ioda_setup_pe_res(struct pnv_ioda_pe *pe, 286723e79425SGavin Shan struct resource *res) 286811685becSGavin Shan { 286923e79425SGavin Shan struct pnv_phb *phb = pe->phb; 287011685becSGavin Shan struct pci_bus_region region; 287123e79425SGavin Shan int index; 287223e79425SGavin Shan int64_t rc; 287311685becSGavin Shan 287423e79425SGavin Shan if (!res || !res->flags || res->start > res->end) 287523e79425SGavin Shan return; 287611685becSGavin Shan 287711685becSGavin Shan if (res->flags & IORESOURCE_IO) { 287811685becSGavin Shan region.start = res->start - phb->ioda.io_pci_base; 287911685becSGavin Shan region.end = res->end - phb->ioda.io_pci_base; 288011685becSGavin Shan index = region.start / phb->ioda.io_segsize; 288111685becSGavin Shan 288292b8f137SGavin Shan while (index < phb->ioda.total_pe_num && 288311685becSGavin Shan region.start <= region.end) { 288411685becSGavin Shan phb->ioda.io_segmap[index] = pe->pe_number; 288511685becSGavin Shan rc = opal_pci_map_pe_mmio_window(phb->opal_id, 288611685becSGavin Shan pe->pe_number, OPAL_IO_WINDOW_TYPE, 0, index); 288711685becSGavin Shan if (rc != OPAL_SUCCESS) { 288823e79425SGavin Shan pr_err("%s: Error %lld mapping IO segment#%d to PE#%d\n", 288911685becSGavin Shan __func__, rc, index, pe->pe_number); 289011685becSGavin Shan break; 289111685becSGavin Shan } 289211685becSGavin Shan 289311685becSGavin Shan region.start += phb->ioda.io_segsize; 289411685becSGavin Shan index++; 289511685becSGavin Shan } 2896027fa02fSGavin Shan } else if ((res->flags & IORESOURCE_MEM) && 2897027fa02fSGavin Shan !pnv_pci_is_mem_pref_64(res->flags)) { 289811685becSGavin Shan region.start = res->start - 289923e79425SGavin Shan phb->hose->mem_offset[0] - 290011685becSGavin Shan phb->ioda.m32_pci_base; 290111685becSGavin Shan region.end = res->end - 290223e79425SGavin Shan phb->hose->mem_offset[0] - 290311685becSGavin Shan phb->ioda.m32_pci_base; 290411685becSGavin Shan index = region.start / phb->ioda.m32_segsize; 290511685becSGavin Shan 290692b8f137SGavin Shan while (index < phb->ioda.total_pe_num && 290711685becSGavin Shan region.start <= region.end) { 290811685becSGavin Shan phb->ioda.m32_segmap[index] = pe->pe_number; 290911685becSGavin Shan rc = opal_pci_map_pe_mmio_window(phb->opal_id, 291011685becSGavin Shan pe->pe_number, OPAL_M32_WINDOW_TYPE, 0, index); 291111685becSGavin Shan if (rc != OPAL_SUCCESS) { 291223e79425SGavin Shan pr_err("%s: Error %lld mapping M32 segment#%d to PE#%d", 291311685becSGavin Shan __func__, rc, index, pe->pe_number); 291411685becSGavin Shan break; 291511685becSGavin Shan } 291611685becSGavin Shan 291711685becSGavin Shan region.start += phb->ioda.m32_segsize; 291811685becSGavin Shan index++; 291911685becSGavin Shan } 292011685becSGavin Shan } 292111685becSGavin Shan } 292223e79425SGavin Shan 292323e79425SGavin Shan /* 292423e79425SGavin Shan * This function is supposed to be called on basis of PE from top 292523e79425SGavin Shan * to bottom style. So the the I/O or MMIO segment assigned to 292623e79425SGavin Shan * parent PE could be overrided by its child PEs if necessary. 292723e79425SGavin Shan */ 292823e79425SGavin Shan static void pnv_ioda_setup_pe_seg(struct pnv_ioda_pe *pe) 292923e79425SGavin Shan { 293069d733e7SGavin Shan struct pci_dev *pdev; 293123e79425SGavin Shan int i; 293223e79425SGavin Shan 293323e79425SGavin Shan /* 293423e79425SGavin Shan * NOTE: We only care PCI bus based PE for now. For PCI 293523e79425SGavin Shan * device based PE, for example SRIOV sensitive VF should 293623e79425SGavin Shan * be figured out later. 293723e79425SGavin Shan */ 293823e79425SGavin Shan BUG_ON(!(pe->flags & (PNV_IODA_PE_BUS | PNV_IODA_PE_BUS_ALL))); 293923e79425SGavin Shan 294069d733e7SGavin Shan list_for_each_entry(pdev, &pe->pbus->devices, bus_list) { 294169d733e7SGavin Shan for (i = 0; i <= PCI_ROM_RESOURCE; i++) 294269d733e7SGavin Shan pnv_ioda_setup_pe_res(pe, &pdev->resource[i]); 294369d733e7SGavin Shan 294469d733e7SGavin Shan /* 294569d733e7SGavin Shan * If the PE contains all subordinate PCI buses, the 294669d733e7SGavin Shan * windows of the child bridges should be mapped to 294769d733e7SGavin Shan * the PE as well. 294869d733e7SGavin Shan */ 294969d733e7SGavin Shan if (!(pe->flags & PNV_IODA_PE_BUS_ALL) || !pci_is_bridge(pdev)) 295069d733e7SGavin Shan continue; 295169d733e7SGavin Shan for (i = 0; i < PCI_BRIDGE_RESOURCE_NUM; i++) 295269d733e7SGavin Shan pnv_ioda_setup_pe_res(pe, 295369d733e7SGavin Shan &pdev->resource[PCI_BRIDGE_RESOURCES + i]); 295469d733e7SGavin Shan } 295511685becSGavin Shan } 295611685becSGavin Shan 295737c367f2SGavin Shan static void pnv_pci_ioda_create_dbgfs(void) 295837c367f2SGavin Shan { 295937c367f2SGavin Shan #ifdef CONFIG_DEBUG_FS 296037c367f2SGavin Shan struct pci_controller *hose, *tmp; 296137c367f2SGavin Shan struct pnv_phb *phb; 296237c367f2SGavin Shan char name[16]; 296337c367f2SGavin Shan 296437c367f2SGavin Shan list_for_each_entry_safe(hose, tmp, &hose_list, list_node) { 296537c367f2SGavin Shan phb = hose->private_data; 296637c367f2SGavin Shan 2967ccd1c191SGavin Shan /* Notify initialization of PHB done */ 2968ccd1c191SGavin Shan phb->initialized = 1; 2969ccd1c191SGavin Shan 297037c367f2SGavin Shan sprintf(name, "PCI%04x", hose->global_number); 297137c367f2SGavin Shan phb->dbgfs = debugfs_create_dir(name, powerpc_debugfs_root); 297237c367f2SGavin Shan if (!phb->dbgfs) 297337c367f2SGavin Shan pr_warning("%s: Error on creating debugfs on PHB#%x\n", 297437c367f2SGavin Shan __func__, hose->global_number); 297537c367f2SGavin Shan } 297637c367f2SGavin Shan #endif /* CONFIG_DEBUG_FS */ 297737c367f2SGavin Shan } 297837c367f2SGavin Shan 2979cad5cef6SGreg Kroah-Hartman static void pnv_pci_ioda_fixup(void) 2980fb446ad0SGavin Shan { 2981fb446ad0SGavin Shan pnv_pci_ioda_setup_PEs(); 2982ccd1c191SGavin Shan pnv_pci_ioda_setup_iommu_api(); 298337c367f2SGavin Shan pnv_pci_ioda_create_dbgfs(); 298437c367f2SGavin Shan 2985e9cc17d4SGavin Shan #ifdef CONFIG_EEH 2986e9cc17d4SGavin Shan eeh_init(); 2987dadcd6d6SMike Qiu eeh_addr_cache_build(); 2988e9cc17d4SGavin Shan #endif 2989fb446ad0SGavin Shan } 2990fb446ad0SGavin Shan 2991271fd03aSGavin Shan /* 2992271fd03aSGavin Shan * Returns the alignment for I/O or memory windows for P2P 2993271fd03aSGavin Shan * bridges. That actually depends on how PEs are segmented. 2994271fd03aSGavin Shan * For now, we return I/O or M32 segment size for PE sensitive 2995271fd03aSGavin Shan * P2P bridges. Otherwise, the default values (4KiB for I/O, 2996271fd03aSGavin Shan * 1MiB for memory) will be returned. 2997271fd03aSGavin Shan * 2998271fd03aSGavin Shan * The current PCI bus might be put into one PE, which was 2999271fd03aSGavin Shan * create against the parent PCI bridge. For that case, we 3000271fd03aSGavin Shan * needn't enlarge the alignment so that we can save some 3001271fd03aSGavin Shan * resources. 3002271fd03aSGavin Shan */ 3003271fd03aSGavin Shan static resource_size_t pnv_pci_window_alignment(struct pci_bus *bus, 3004271fd03aSGavin Shan unsigned long type) 3005271fd03aSGavin Shan { 3006271fd03aSGavin Shan struct pci_dev *bridge; 3007271fd03aSGavin Shan struct pci_controller *hose = pci_bus_to_host(bus); 3008271fd03aSGavin Shan struct pnv_phb *phb = hose->private_data; 3009271fd03aSGavin Shan int num_pci_bridges = 0; 3010271fd03aSGavin Shan 3011271fd03aSGavin Shan bridge = bus->self; 3012271fd03aSGavin Shan while (bridge) { 3013271fd03aSGavin Shan if (pci_pcie_type(bridge) == PCI_EXP_TYPE_PCI_BRIDGE) { 3014271fd03aSGavin Shan num_pci_bridges++; 3015271fd03aSGavin Shan if (num_pci_bridges >= 2) 3016271fd03aSGavin Shan return 1; 3017271fd03aSGavin Shan } 3018271fd03aSGavin Shan 3019271fd03aSGavin Shan bridge = bridge->bus->self; 3020271fd03aSGavin Shan } 3021271fd03aSGavin Shan 3022262af557SGuo Chao /* We fail back to M32 if M64 isn't supported */ 3023262af557SGuo Chao if (phb->ioda.m64_segsize && 3024262af557SGuo Chao pnv_pci_is_mem_pref_64(type)) 3025262af557SGuo Chao return phb->ioda.m64_segsize; 3026271fd03aSGavin Shan if (type & IORESOURCE_MEM) 3027271fd03aSGavin Shan return phb->ioda.m32_segsize; 3028271fd03aSGavin Shan 3029271fd03aSGavin Shan return phb->ioda.io_segsize; 3030271fd03aSGavin Shan } 3031271fd03aSGavin Shan 303240e2a47eSGavin Shan /* 303340e2a47eSGavin Shan * We are updating root port or the upstream port of the 303440e2a47eSGavin Shan * bridge behind the root port with PHB's windows in order 303540e2a47eSGavin Shan * to accommodate the changes on required resources during 303640e2a47eSGavin Shan * PCI (slot) hotplug, which is connected to either root 303740e2a47eSGavin Shan * port or the downstream ports of PCIe switch behind the 303840e2a47eSGavin Shan * root port. 303940e2a47eSGavin Shan */ 304040e2a47eSGavin Shan static void pnv_pci_fixup_bridge_resources(struct pci_bus *bus, 304140e2a47eSGavin Shan unsigned long type) 304240e2a47eSGavin Shan { 304340e2a47eSGavin Shan struct pci_controller *hose = pci_bus_to_host(bus); 304440e2a47eSGavin Shan struct pnv_phb *phb = hose->private_data; 304540e2a47eSGavin Shan struct pci_dev *bridge = bus->self; 304640e2a47eSGavin Shan struct resource *r, *w; 304740e2a47eSGavin Shan bool msi_region = false; 304840e2a47eSGavin Shan int i; 304940e2a47eSGavin Shan 305040e2a47eSGavin Shan /* Check if we need apply fixup to the bridge's windows */ 305140e2a47eSGavin Shan if (!pci_is_root_bus(bridge->bus) && 305240e2a47eSGavin Shan !pci_is_root_bus(bridge->bus->self->bus)) 305340e2a47eSGavin Shan return; 305440e2a47eSGavin Shan 305540e2a47eSGavin Shan /* Fixup the resources */ 305640e2a47eSGavin Shan for (i = 0; i < PCI_BRIDGE_RESOURCE_NUM; i++) { 305740e2a47eSGavin Shan r = &bridge->resource[PCI_BRIDGE_RESOURCES + i]; 305840e2a47eSGavin Shan if (!r->flags || !r->parent) 305940e2a47eSGavin Shan continue; 306040e2a47eSGavin Shan 306140e2a47eSGavin Shan w = NULL; 306240e2a47eSGavin Shan if (r->flags & type & IORESOURCE_IO) 306340e2a47eSGavin Shan w = &hose->io_resource; 306440e2a47eSGavin Shan else if (pnv_pci_is_mem_pref_64(r->flags) && 306540e2a47eSGavin Shan (type & IORESOURCE_PREFETCH) && 306640e2a47eSGavin Shan phb->ioda.m64_segsize) 306740e2a47eSGavin Shan w = &hose->mem_resources[1]; 306840e2a47eSGavin Shan else if (r->flags & type & IORESOURCE_MEM) { 306940e2a47eSGavin Shan w = &hose->mem_resources[0]; 307040e2a47eSGavin Shan msi_region = true; 307140e2a47eSGavin Shan } 307240e2a47eSGavin Shan 307340e2a47eSGavin Shan r->start = w->start; 307440e2a47eSGavin Shan r->end = w->end; 307540e2a47eSGavin Shan 307640e2a47eSGavin Shan /* The 64KB 32-bits MSI region shouldn't be included in 307740e2a47eSGavin Shan * the 32-bits bridge window. Otherwise, we can see strange 307840e2a47eSGavin Shan * issues. One of them is EEH error observed on Garrison. 307940e2a47eSGavin Shan * 308040e2a47eSGavin Shan * Exclude top 1MB region which is the minimal alignment of 308140e2a47eSGavin Shan * 32-bits bridge window. 308240e2a47eSGavin Shan */ 308340e2a47eSGavin Shan if (msi_region) { 308440e2a47eSGavin Shan r->end += 0x10000; 308540e2a47eSGavin Shan r->end -= 0x100000; 308640e2a47eSGavin Shan } 308740e2a47eSGavin Shan } 308840e2a47eSGavin Shan } 308940e2a47eSGavin Shan 3090ccd1c191SGavin Shan static void pnv_pci_setup_bridge(struct pci_bus *bus, unsigned long type) 3091ccd1c191SGavin Shan { 3092ccd1c191SGavin Shan struct pci_controller *hose = pci_bus_to_host(bus); 3093ccd1c191SGavin Shan struct pnv_phb *phb = hose->private_data; 3094ccd1c191SGavin Shan struct pci_dev *bridge = bus->self; 3095ccd1c191SGavin Shan struct pnv_ioda_pe *pe; 3096ccd1c191SGavin Shan bool all = (pci_pcie_type(bridge) == PCI_EXP_TYPE_PCI_BRIDGE); 3097ccd1c191SGavin Shan 309840e2a47eSGavin Shan /* Extend bridge's windows if necessary */ 309940e2a47eSGavin Shan pnv_pci_fixup_bridge_resources(bus, type); 310040e2a47eSGavin Shan 310163803c39SGavin Shan /* The PE for root bus should be realized before any one else */ 310263803c39SGavin Shan if (!phb->ioda.root_pe_populated) { 310363803c39SGavin Shan pe = pnv_ioda_setup_bus_PE(phb->hose->bus, false); 310463803c39SGavin Shan if (pe) { 310563803c39SGavin Shan phb->ioda.root_pe_idx = pe->pe_number; 310663803c39SGavin Shan phb->ioda.root_pe_populated = true; 310763803c39SGavin Shan } 310863803c39SGavin Shan } 310963803c39SGavin Shan 3110ccd1c191SGavin Shan /* Don't assign PE to PCI bus, which doesn't have subordinate devices */ 3111ccd1c191SGavin Shan if (list_empty(&bus->devices)) 3112ccd1c191SGavin Shan return; 3113ccd1c191SGavin Shan 3114ccd1c191SGavin Shan /* Reserve PEs according to used M64 resources */ 3115ccd1c191SGavin Shan if (phb->reserve_m64_pe) 3116ccd1c191SGavin Shan phb->reserve_m64_pe(bus, NULL, all); 3117ccd1c191SGavin Shan 3118ccd1c191SGavin Shan /* 3119ccd1c191SGavin Shan * Assign PE. We might run here because of partial hotplug. 3120ccd1c191SGavin Shan * For the case, we just pick up the existing PE and should 3121ccd1c191SGavin Shan * not allocate resources again. 3122ccd1c191SGavin Shan */ 3123ccd1c191SGavin Shan pe = pnv_ioda_setup_bus_PE(bus, all); 3124ccd1c191SGavin Shan if (!pe) 3125ccd1c191SGavin Shan return; 3126ccd1c191SGavin Shan 3127ccd1c191SGavin Shan pnv_ioda_setup_pe_seg(pe); 3128ccd1c191SGavin Shan switch (phb->type) { 3129ccd1c191SGavin Shan case PNV_PHB_IODA1: 3130ccd1c191SGavin Shan pnv_pci_ioda1_setup_dma_pe(phb, pe); 3131ccd1c191SGavin Shan break; 3132ccd1c191SGavin Shan case PNV_PHB_IODA2: 3133ccd1c191SGavin Shan pnv_pci_ioda2_setup_dma_pe(phb, pe); 3134ccd1c191SGavin Shan break; 3135ccd1c191SGavin Shan default: 3136ccd1c191SGavin Shan pr_warn("%s: No DMA for PHB#%d (type %d)\n", 3137ccd1c191SGavin Shan __func__, phb->hose->global_number, phb->type); 3138ccd1c191SGavin Shan } 3139ccd1c191SGavin Shan } 3140ccd1c191SGavin Shan 31415350ab3fSWei Yang #ifdef CONFIG_PCI_IOV 31425350ab3fSWei Yang static resource_size_t pnv_pci_iov_resource_alignment(struct pci_dev *pdev, 31435350ab3fSWei Yang int resno) 31445350ab3fSWei Yang { 3145ee8222feSWei Yang struct pci_controller *hose = pci_bus_to_host(pdev->bus); 3146ee8222feSWei Yang struct pnv_phb *phb = hose->private_data; 31475350ab3fSWei Yang struct pci_dn *pdn = pci_get_pdn(pdev); 31487fbe7a93SWei Yang resource_size_t align; 31495350ab3fSWei Yang 31507fbe7a93SWei Yang /* 31517fbe7a93SWei Yang * On PowerNV platform, IOV BAR is mapped by M64 BAR to enable the 31527fbe7a93SWei Yang * SR-IOV. While from hardware perspective, the range mapped by M64 31537fbe7a93SWei Yang * BAR should be size aligned. 31547fbe7a93SWei Yang * 3155ee8222feSWei Yang * When IOV BAR is mapped with M64 BAR in Single PE mode, the extra 3156ee8222feSWei Yang * powernv-specific hardware restriction is gone. But if just use the 3157ee8222feSWei Yang * VF BAR size as the alignment, PF BAR / VF BAR may be allocated with 3158ee8222feSWei Yang * in one segment of M64 #15, which introduces the PE conflict between 3159ee8222feSWei Yang * PF and VF. Based on this, the minimum alignment of an IOV BAR is 3160ee8222feSWei Yang * m64_segsize. 3161ee8222feSWei Yang * 31627fbe7a93SWei Yang * This function returns the total IOV BAR size if M64 BAR is in 31637fbe7a93SWei Yang * Shared PE mode or just VF BAR size if not. 3164ee8222feSWei Yang * If the M64 BAR is in Single PE mode, return the VF BAR size or 3165ee8222feSWei Yang * M64 segment size if IOV BAR size is less. 31667fbe7a93SWei Yang */ 31675350ab3fSWei Yang align = pci_iov_resource_size(pdev, resno); 31687fbe7a93SWei Yang if (!pdn->vfs_expanded) 31695350ab3fSWei Yang return align; 3170ee8222feSWei Yang if (pdn->m64_single_mode) 3171ee8222feSWei Yang return max(align, (resource_size_t)phb->ioda.m64_segsize); 31727fbe7a93SWei Yang 31737fbe7a93SWei Yang return pdn->vfs_expanded * align; 31745350ab3fSWei Yang } 31755350ab3fSWei Yang #endif /* CONFIG_PCI_IOV */ 31765350ab3fSWei Yang 3177184cd4a3SBenjamin Herrenschmidt /* Prevent enabling devices for which we couldn't properly 3178184cd4a3SBenjamin Herrenschmidt * assign a PE 3179184cd4a3SBenjamin Herrenschmidt */ 31804361b034SIan Munsie bool pnv_pci_enable_device_hook(struct pci_dev *dev) 3181184cd4a3SBenjamin Herrenschmidt { 3182db1266c8SGavin Shan struct pci_controller *hose = pci_bus_to_host(dev->bus); 3183db1266c8SGavin Shan struct pnv_phb *phb = hose->private_data; 3184db1266c8SGavin Shan struct pci_dn *pdn; 3185184cd4a3SBenjamin Herrenschmidt 3186db1266c8SGavin Shan /* The function is probably called while the PEs have 3187db1266c8SGavin Shan * not be created yet. For example, resource reassignment 3188db1266c8SGavin Shan * during PCI probe period. We just skip the check if 3189db1266c8SGavin Shan * PEs isn't ready. 3190db1266c8SGavin Shan */ 3191db1266c8SGavin Shan if (!phb->initialized) 3192c88c2a18SDaniel Axtens return true; 3193db1266c8SGavin Shan 3194b72c1f65SBenjamin Herrenschmidt pdn = pci_get_pdn(dev); 3195184cd4a3SBenjamin Herrenschmidt if (!pdn || pdn->pe_number == IODA_INVALID_PE) 3196c88c2a18SDaniel Axtens return false; 3197db1266c8SGavin Shan 3198c88c2a18SDaniel Axtens return true; 3199184cd4a3SBenjamin Herrenschmidt } 3200184cd4a3SBenjamin Herrenschmidt 3201c5f7700bSGavin Shan static long pnv_pci_ioda1_unset_window(struct iommu_table_group *table_group, 3202c5f7700bSGavin Shan int num) 3203c5f7700bSGavin Shan { 3204c5f7700bSGavin Shan struct pnv_ioda_pe *pe = container_of(table_group, 3205c5f7700bSGavin Shan struct pnv_ioda_pe, table_group); 3206c5f7700bSGavin Shan struct pnv_phb *phb = pe->phb; 3207c5f7700bSGavin Shan unsigned int idx; 3208c5f7700bSGavin Shan long rc; 3209c5f7700bSGavin Shan 3210c5f7700bSGavin Shan pe_info(pe, "Removing DMA window #%d\n", num); 3211c5f7700bSGavin Shan for (idx = 0; idx < phb->ioda.dma32_count; idx++) { 3212c5f7700bSGavin Shan if (phb->ioda.dma32_segmap[idx] != pe->pe_number) 3213c5f7700bSGavin Shan continue; 3214c5f7700bSGavin Shan 3215c5f7700bSGavin Shan rc = opal_pci_map_pe_dma_window(phb->opal_id, pe->pe_number, 3216c5f7700bSGavin Shan idx, 0, 0ul, 0ul, 0ul); 3217c5f7700bSGavin Shan if (rc != OPAL_SUCCESS) { 3218c5f7700bSGavin Shan pe_warn(pe, "Failure %ld unmapping DMA32 segment#%d\n", 3219c5f7700bSGavin Shan rc, idx); 3220c5f7700bSGavin Shan return rc; 3221c5f7700bSGavin Shan } 3222c5f7700bSGavin Shan 3223c5f7700bSGavin Shan phb->ioda.dma32_segmap[idx] = IODA_INVALID_PE; 3224c5f7700bSGavin Shan } 3225c5f7700bSGavin Shan 3226c5f7700bSGavin Shan pnv_pci_unlink_table_and_group(table_group->tables[num], table_group); 3227c5f7700bSGavin Shan return OPAL_SUCCESS; 3228c5f7700bSGavin Shan } 3229c5f7700bSGavin Shan 3230c5f7700bSGavin Shan static void pnv_pci_ioda1_release_pe_dma(struct pnv_ioda_pe *pe) 3231c5f7700bSGavin Shan { 3232c5f7700bSGavin Shan unsigned int weight = pnv_pci_ioda_pe_dma_weight(pe); 3233c5f7700bSGavin Shan struct iommu_table *tbl = pe->table_group.tables[0]; 3234c5f7700bSGavin Shan int64_t rc; 3235c5f7700bSGavin Shan 3236c5f7700bSGavin Shan if (!weight) 3237c5f7700bSGavin Shan return; 3238c5f7700bSGavin Shan 3239c5f7700bSGavin Shan rc = pnv_pci_ioda1_unset_window(&pe->table_group, 0); 3240c5f7700bSGavin Shan if (rc != OPAL_SUCCESS) 3241c5f7700bSGavin Shan return; 3242c5f7700bSGavin Shan 3243a34ab7c3SBenjamin Herrenschmidt pnv_pci_p7ioc_tce_invalidate(tbl, tbl->it_offset, tbl->it_size, false); 3244c5f7700bSGavin Shan if (pe->table_group.group) { 3245c5f7700bSGavin Shan iommu_group_put(pe->table_group.group); 3246c5f7700bSGavin Shan WARN_ON(pe->table_group.group); 3247c5f7700bSGavin Shan } 3248c5f7700bSGavin Shan 3249c5f7700bSGavin Shan free_pages(tbl->it_base, get_order(tbl->it_size << 3)); 3250c5f7700bSGavin Shan iommu_free_table(tbl, "pnv"); 3251c5f7700bSGavin Shan } 3252c5f7700bSGavin Shan 3253c5f7700bSGavin Shan static void pnv_pci_ioda2_release_pe_dma(struct pnv_ioda_pe *pe) 3254c5f7700bSGavin Shan { 3255c5f7700bSGavin Shan struct iommu_table *tbl = pe->table_group.tables[0]; 3256c5f7700bSGavin Shan unsigned int weight = pnv_pci_ioda_pe_dma_weight(pe); 3257c5f7700bSGavin Shan #ifdef CONFIG_IOMMU_API 3258c5f7700bSGavin Shan int64_t rc; 3259c5f7700bSGavin Shan #endif 3260c5f7700bSGavin Shan 3261c5f7700bSGavin Shan if (!weight) 3262c5f7700bSGavin Shan return; 3263c5f7700bSGavin Shan 3264c5f7700bSGavin Shan #ifdef CONFIG_IOMMU_API 3265c5f7700bSGavin Shan rc = pnv_pci_ioda2_unset_window(&pe->table_group, 0); 3266c5f7700bSGavin Shan if (rc) 3267c5f7700bSGavin Shan pe_warn(pe, "OPAL error %ld release DMA window\n", rc); 3268c5f7700bSGavin Shan #endif 3269c5f7700bSGavin Shan 3270c5f7700bSGavin Shan pnv_pci_ioda2_set_bypass(pe, false); 3271c5f7700bSGavin Shan if (pe->table_group.group) { 3272c5f7700bSGavin Shan iommu_group_put(pe->table_group.group); 3273c5f7700bSGavin Shan WARN_ON(pe->table_group.group); 3274c5f7700bSGavin Shan } 3275c5f7700bSGavin Shan 3276c5f7700bSGavin Shan pnv_pci_ioda2_table_free_pages(tbl); 3277c5f7700bSGavin Shan iommu_free_table(tbl, "pnv"); 3278c5f7700bSGavin Shan } 3279c5f7700bSGavin Shan 3280c5f7700bSGavin Shan static void pnv_ioda_free_pe_seg(struct pnv_ioda_pe *pe, 3281c5f7700bSGavin Shan unsigned short win, 3282c5f7700bSGavin Shan unsigned int *map) 3283c5f7700bSGavin Shan { 3284c5f7700bSGavin Shan struct pnv_phb *phb = pe->phb; 3285c5f7700bSGavin Shan int idx; 3286c5f7700bSGavin Shan int64_t rc; 3287c5f7700bSGavin Shan 3288c5f7700bSGavin Shan for (idx = 0; idx < phb->ioda.total_pe_num; idx++) { 3289c5f7700bSGavin Shan if (map[idx] != pe->pe_number) 3290c5f7700bSGavin Shan continue; 3291c5f7700bSGavin Shan 3292c5f7700bSGavin Shan if (win == OPAL_M64_WINDOW_TYPE) 3293c5f7700bSGavin Shan rc = opal_pci_map_pe_mmio_window(phb->opal_id, 3294c5f7700bSGavin Shan phb->ioda.reserved_pe_idx, win, 3295c5f7700bSGavin Shan idx / PNV_IODA1_M64_SEGS, 3296c5f7700bSGavin Shan idx % PNV_IODA1_M64_SEGS); 3297c5f7700bSGavin Shan else 3298c5f7700bSGavin Shan rc = opal_pci_map_pe_mmio_window(phb->opal_id, 3299c5f7700bSGavin Shan phb->ioda.reserved_pe_idx, win, 0, idx); 3300c5f7700bSGavin Shan 3301c5f7700bSGavin Shan if (rc != OPAL_SUCCESS) 3302c5f7700bSGavin Shan pe_warn(pe, "Error %ld unmapping (%d) segment#%d\n", 3303c5f7700bSGavin Shan rc, win, idx); 3304c5f7700bSGavin Shan 3305c5f7700bSGavin Shan map[idx] = IODA_INVALID_PE; 3306c5f7700bSGavin Shan } 3307c5f7700bSGavin Shan } 3308c5f7700bSGavin Shan 3309c5f7700bSGavin Shan static void pnv_ioda_release_pe_seg(struct pnv_ioda_pe *pe) 3310c5f7700bSGavin Shan { 3311c5f7700bSGavin Shan struct pnv_phb *phb = pe->phb; 3312c5f7700bSGavin Shan 3313c5f7700bSGavin Shan if (phb->type == PNV_PHB_IODA1) { 3314c5f7700bSGavin Shan pnv_ioda_free_pe_seg(pe, OPAL_IO_WINDOW_TYPE, 3315c5f7700bSGavin Shan phb->ioda.io_segmap); 3316c5f7700bSGavin Shan pnv_ioda_free_pe_seg(pe, OPAL_M32_WINDOW_TYPE, 3317c5f7700bSGavin Shan phb->ioda.m32_segmap); 3318c5f7700bSGavin Shan pnv_ioda_free_pe_seg(pe, OPAL_M64_WINDOW_TYPE, 3319c5f7700bSGavin Shan phb->ioda.m64_segmap); 3320c5f7700bSGavin Shan } else if (phb->type == PNV_PHB_IODA2) { 3321c5f7700bSGavin Shan pnv_ioda_free_pe_seg(pe, OPAL_M32_WINDOW_TYPE, 3322c5f7700bSGavin Shan phb->ioda.m32_segmap); 3323c5f7700bSGavin Shan } 3324c5f7700bSGavin Shan } 3325c5f7700bSGavin Shan 3326c5f7700bSGavin Shan static void pnv_ioda_release_pe(struct pnv_ioda_pe *pe) 3327c5f7700bSGavin Shan { 3328c5f7700bSGavin Shan struct pnv_phb *phb = pe->phb; 3329c5f7700bSGavin Shan struct pnv_ioda_pe *slave, *tmp; 3330c5f7700bSGavin Shan 3331c5f7700bSGavin Shan /* Release slave PEs in compound PE */ 3332c5f7700bSGavin Shan if (pe->flags & PNV_IODA_PE_MASTER) { 3333c5f7700bSGavin Shan list_for_each_entry_safe(slave, tmp, &pe->slaves, list) 3334c5f7700bSGavin Shan pnv_ioda_release_pe(slave); 3335c5f7700bSGavin Shan } 3336c5f7700bSGavin Shan 3337c5f7700bSGavin Shan list_del(&pe->list); 3338c5f7700bSGavin Shan switch (phb->type) { 3339c5f7700bSGavin Shan case PNV_PHB_IODA1: 3340c5f7700bSGavin Shan pnv_pci_ioda1_release_pe_dma(pe); 3341c5f7700bSGavin Shan break; 3342c5f7700bSGavin Shan case PNV_PHB_IODA2: 3343c5f7700bSGavin Shan pnv_pci_ioda2_release_pe_dma(pe); 3344c5f7700bSGavin Shan break; 3345c5f7700bSGavin Shan default: 3346c5f7700bSGavin Shan WARN_ON(1); 3347c5f7700bSGavin Shan } 3348c5f7700bSGavin Shan 3349c5f7700bSGavin Shan pnv_ioda_release_pe_seg(pe); 3350c5f7700bSGavin Shan pnv_ioda_deconfigure_pe(pe->phb, pe); 3351c5f7700bSGavin Shan pnv_ioda_free_pe(pe); 3352c5f7700bSGavin Shan } 3353c5f7700bSGavin Shan 3354c5f7700bSGavin Shan static void pnv_pci_release_device(struct pci_dev *pdev) 3355c5f7700bSGavin Shan { 3356c5f7700bSGavin Shan struct pci_controller *hose = pci_bus_to_host(pdev->bus); 3357c5f7700bSGavin Shan struct pnv_phb *phb = hose->private_data; 3358c5f7700bSGavin Shan struct pci_dn *pdn = pci_get_pdn(pdev); 3359c5f7700bSGavin Shan struct pnv_ioda_pe *pe; 3360c5f7700bSGavin Shan 3361c5f7700bSGavin Shan if (pdev->is_virtfn) 3362c5f7700bSGavin Shan return; 3363c5f7700bSGavin Shan 3364c5f7700bSGavin Shan if (!pdn || pdn->pe_number == IODA_INVALID_PE) 3365c5f7700bSGavin Shan return; 3366c5f7700bSGavin Shan 3367c5f7700bSGavin Shan pe = &phb->ioda.pe_array[pdn->pe_number]; 3368c5f7700bSGavin Shan WARN_ON(--pe->device_count < 0); 3369c5f7700bSGavin Shan if (pe->device_count == 0) 3370c5f7700bSGavin Shan pnv_ioda_release_pe(pe); 3371c5f7700bSGavin Shan } 3372c5f7700bSGavin Shan 33737a8e6bbfSMichael Neuling static void pnv_pci_ioda_shutdown(struct pci_controller *hose) 337473ed148aSBenjamin Herrenschmidt { 33757a8e6bbfSMichael Neuling struct pnv_phb *phb = hose->private_data; 33767a8e6bbfSMichael Neuling 3377d1a85eeeSGavin Shan opal_pci_reset(phb->opal_id, OPAL_RESET_PCI_IODA_TABLE, 337873ed148aSBenjamin Herrenschmidt OPAL_ASSERT_RESET); 337973ed148aSBenjamin Herrenschmidt } 338073ed148aSBenjamin Herrenschmidt 338192ae0353SDaniel Axtens static const struct pci_controller_ops pnv_pci_ioda_controller_ops = { 338292ae0353SDaniel Axtens .dma_dev_setup = pnv_pci_dma_dev_setup, 33831bc74f1cSGavin Shan .dma_bus_setup = pnv_pci_dma_bus_setup, 338492ae0353SDaniel Axtens #ifdef CONFIG_PCI_MSI 338592ae0353SDaniel Axtens .setup_msi_irqs = pnv_setup_msi_irqs, 338692ae0353SDaniel Axtens .teardown_msi_irqs = pnv_teardown_msi_irqs, 338792ae0353SDaniel Axtens #endif 338892ae0353SDaniel Axtens .enable_device_hook = pnv_pci_enable_device_hook, 3389c5f7700bSGavin Shan .release_device = pnv_pci_release_device, 339092ae0353SDaniel Axtens .window_alignment = pnv_pci_window_alignment, 3391ccd1c191SGavin Shan .setup_bridge = pnv_pci_setup_bridge, 339292ae0353SDaniel Axtens .reset_secondary_bus = pnv_pci_reset_secondary_bus, 3393763d2d8dSDaniel Axtens .dma_set_mask = pnv_pci_ioda_dma_set_mask, 339453522982SAndrew Donnellan .dma_get_required_mask = pnv_pci_ioda_dma_get_required_mask, 33957a8e6bbfSMichael Neuling .shutdown = pnv_pci_ioda_shutdown, 339692ae0353SDaniel Axtens }; 339792ae0353SDaniel Axtens 3398f9f83456SAlexey Kardashevskiy static int pnv_npu_dma_set_mask(struct pci_dev *npdev, u64 dma_mask) 3399f9f83456SAlexey Kardashevskiy { 3400f9f83456SAlexey Kardashevskiy dev_err_once(&npdev->dev, 3401f9f83456SAlexey Kardashevskiy "%s operation unsupported for NVLink devices\n", 3402f9f83456SAlexey Kardashevskiy __func__); 3403f9f83456SAlexey Kardashevskiy return -EPERM; 3404f9f83456SAlexey Kardashevskiy } 3405f9f83456SAlexey Kardashevskiy 34065d2aa710SAlistair Popple static const struct pci_controller_ops pnv_npu_ioda_controller_ops = { 34075d2aa710SAlistair Popple .dma_dev_setup = pnv_pci_dma_dev_setup, 34085d2aa710SAlistair Popple #ifdef CONFIG_PCI_MSI 34095d2aa710SAlistair Popple .setup_msi_irqs = pnv_setup_msi_irqs, 34105d2aa710SAlistair Popple .teardown_msi_irqs = pnv_teardown_msi_irqs, 34115d2aa710SAlistair Popple #endif 34125d2aa710SAlistair Popple .enable_device_hook = pnv_pci_enable_device_hook, 34135d2aa710SAlistair Popple .window_alignment = pnv_pci_window_alignment, 34145d2aa710SAlistair Popple .reset_secondary_bus = pnv_pci_reset_secondary_bus, 34155d2aa710SAlistair Popple .dma_set_mask = pnv_npu_dma_set_mask, 34165d2aa710SAlistair Popple .shutdown = pnv_pci_ioda_shutdown, 34175d2aa710SAlistair Popple }; 34185d2aa710SAlistair Popple 34194361b034SIan Munsie #ifdef CONFIG_CXL_BASE 34204361b034SIan Munsie const struct pci_controller_ops pnv_cxl_cx4_ioda_controller_ops = { 34214361b034SIan Munsie .dma_dev_setup = pnv_pci_dma_dev_setup, 34224361b034SIan Munsie .dma_bus_setup = pnv_pci_dma_bus_setup, 3423a2f67d5eSIan Munsie #ifdef CONFIG_PCI_MSI 3424a2f67d5eSIan Munsie .setup_msi_irqs = pnv_cxl_cx4_setup_msi_irqs, 3425a2f67d5eSIan Munsie .teardown_msi_irqs = pnv_cxl_cx4_teardown_msi_irqs, 3426a2f67d5eSIan Munsie #endif 34274361b034SIan Munsie .enable_device_hook = pnv_cxl_enable_device_hook, 34284361b034SIan Munsie .disable_device = pnv_cxl_disable_device, 34294361b034SIan Munsie .release_device = pnv_pci_release_device, 34304361b034SIan Munsie .window_alignment = pnv_pci_window_alignment, 34314361b034SIan Munsie .setup_bridge = pnv_pci_setup_bridge, 34324361b034SIan Munsie .reset_secondary_bus = pnv_pci_reset_secondary_bus, 34334361b034SIan Munsie .dma_set_mask = pnv_pci_ioda_dma_set_mask, 34344361b034SIan Munsie .dma_get_required_mask = pnv_pci_ioda_dma_get_required_mask, 34354361b034SIan Munsie .shutdown = pnv_pci_ioda_shutdown, 34364361b034SIan Munsie }; 34374361b034SIan Munsie #endif 34384361b034SIan Munsie 3439e51df2c1SAnton Blanchard static void __init pnv_pci_init_ioda_phb(struct device_node *np, 3440e9cc17d4SGavin Shan u64 hub_id, int ioda_type) 3441184cd4a3SBenjamin Herrenschmidt { 3442184cd4a3SBenjamin Herrenschmidt struct pci_controller *hose; 3443184cd4a3SBenjamin Herrenschmidt struct pnv_phb *phb; 34442b923ed1SGavin Shan unsigned long size, m64map_off, m32map_off, pemap_off; 34452b923ed1SGavin Shan unsigned long iomap_off = 0, dma32map_off = 0; 3446fd141d1aSBenjamin Herrenschmidt struct resource r; 3447c681b93cSAlistair Popple const __be64 *prop64; 34483a1a4661SBenjamin Herrenschmidt const __be32 *prop32; 3449f1b7cc3eSGavin Shan int len; 34503fa23ff8SGavin Shan unsigned int segno; 3451184cd4a3SBenjamin Herrenschmidt u64 phb_id; 3452184cd4a3SBenjamin Herrenschmidt void *aux; 3453184cd4a3SBenjamin Herrenschmidt long rc; 3454184cd4a3SBenjamin Herrenschmidt 34559497a1c1SGavin Shan pr_info("Initializing %s PHB (%s)\n", 34569497a1c1SGavin Shan pnv_phb_names[ioda_type], of_node_full_name(np)); 3457184cd4a3SBenjamin Herrenschmidt 3458184cd4a3SBenjamin Herrenschmidt prop64 = of_get_property(np, "ibm,opal-phbid", NULL); 3459184cd4a3SBenjamin Herrenschmidt if (!prop64) { 3460184cd4a3SBenjamin Herrenschmidt pr_err(" Missing \"ibm,opal-phbid\" property !\n"); 3461184cd4a3SBenjamin Herrenschmidt return; 3462184cd4a3SBenjamin Herrenschmidt } 3463184cd4a3SBenjamin Herrenschmidt phb_id = be64_to_cpup(prop64); 3464184cd4a3SBenjamin Herrenschmidt pr_debug(" PHB-ID : 0x%016llx\n", phb_id); 3465184cd4a3SBenjamin Herrenschmidt 3466e39f223fSMichael Ellerman phb = memblock_virt_alloc(sizeof(struct pnv_phb), 0); 346758d714ecSGavin Shan 346858d714ecSGavin Shan /* Allocate PCI controller */ 3469184cd4a3SBenjamin Herrenschmidt phb->hose = hose = pcibios_alloc_controller(np); 347058d714ecSGavin Shan if (!phb->hose) { 347158d714ecSGavin Shan pr_err(" Can't allocate PCI controller for %s\n", 3472184cd4a3SBenjamin Herrenschmidt np->full_name); 3473e39f223fSMichael Ellerman memblock_free(__pa(phb), sizeof(struct pnv_phb)); 3474184cd4a3SBenjamin Herrenschmidt return; 3475184cd4a3SBenjamin Herrenschmidt } 3476184cd4a3SBenjamin Herrenschmidt 3477184cd4a3SBenjamin Herrenschmidt spin_lock_init(&phb->lock); 3478f1b7cc3eSGavin Shan prop32 = of_get_property(np, "bus-range", &len); 3479f1b7cc3eSGavin Shan if (prop32 && len == 8) { 34803a1a4661SBenjamin Herrenschmidt hose->first_busno = be32_to_cpu(prop32[0]); 34813a1a4661SBenjamin Herrenschmidt hose->last_busno = be32_to_cpu(prop32[1]); 3482f1b7cc3eSGavin Shan } else { 3483f1b7cc3eSGavin Shan pr_warn(" Broken <bus-range> on %s\n", np->full_name); 3484184cd4a3SBenjamin Herrenschmidt hose->first_busno = 0; 3485184cd4a3SBenjamin Herrenschmidt hose->last_busno = 0xff; 3486f1b7cc3eSGavin Shan } 3487184cd4a3SBenjamin Herrenschmidt hose->private_data = phb; 3488e9cc17d4SGavin Shan phb->hub_id = hub_id; 3489184cd4a3SBenjamin Herrenschmidt phb->opal_id = phb_id; 3490aa0c033fSGavin Shan phb->type = ioda_type; 3491781a868fSWei Yang mutex_init(&phb->ioda.pe_alloc_mutex); 3492184cd4a3SBenjamin Herrenschmidt 3493cee72d5bSBenjamin Herrenschmidt /* Detect specific models for error handling */ 3494cee72d5bSBenjamin Herrenschmidt if (of_device_is_compatible(np, "ibm,p7ioc-pciex")) 3495cee72d5bSBenjamin Herrenschmidt phb->model = PNV_PHB_MODEL_P7IOC; 3496f3d40c25SBenjamin Herrenschmidt else if (of_device_is_compatible(np, "ibm,power8-pciex")) 3497aa0c033fSGavin Shan phb->model = PNV_PHB_MODEL_PHB3; 34985d2aa710SAlistair Popple else if (of_device_is_compatible(np, "ibm,power8-npu-pciex")) 34995d2aa710SAlistair Popple phb->model = PNV_PHB_MODEL_NPU; 3500cee72d5bSBenjamin Herrenschmidt else 3501cee72d5bSBenjamin Herrenschmidt phb->model = PNV_PHB_MODEL_UNKNOWN; 3502cee72d5bSBenjamin Herrenschmidt 3503aa0c033fSGavin Shan /* Parse 32-bit and IO ranges (if any) */ 35042f1ec02eSGavin Shan pci_process_bridge_OF_ranges(hose, np, !hose->global_number); 3505184cd4a3SBenjamin Herrenschmidt 3506aa0c033fSGavin Shan /* Get registers */ 3507fd141d1aSBenjamin Herrenschmidt if (!of_address_to_resource(np, 0, &r)) { 3508fd141d1aSBenjamin Herrenschmidt phb->regs_phys = r.start; 3509fd141d1aSBenjamin Herrenschmidt phb->regs = ioremap(r.start, resource_size(&r)); 3510184cd4a3SBenjamin Herrenschmidt if (phb->regs == NULL) 3511184cd4a3SBenjamin Herrenschmidt pr_err(" Failed to map registers !\n"); 3512fd141d1aSBenjamin Herrenschmidt } 3513577c8c88SGavin Shan 3514184cd4a3SBenjamin Herrenschmidt /* Initialize more IODA stuff */ 351592b8f137SGavin Shan phb->ioda.total_pe_num = 1; 351636954dc7SGavin Shan prop32 = of_get_property(np, "ibm,opal-num-pes", NULL); 351736954dc7SGavin Shan if (prop32) 351892b8f137SGavin Shan phb->ioda.total_pe_num = be32_to_cpup(prop32); 351936954dc7SGavin Shan prop32 = of_get_property(np, "ibm,opal-reserved-pe", NULL); 352036954dc7SGavin Shan if (prop32) 352192b8f137SGavin Shan phb->ioda.reserved_pe_idx = be32_to_cpup(prop32); 3522262af557SGuo Chao 3523c127562aSGavin Shan /* Invalidate RID to PE# mapping */ 3524c127562aSGavin Shan for (segno = 0; segno < ARRAY_SIZE(phb->ioda.pe_rmap); segno++) 3525c127562aSGavin Shan phb->ioda.pe_rmap[segno] = IODA_INVALID_PE; 3526c127562aSGavin Shan 3527262af557SGuo Chao /* Parse 64-bit MMIO range */ 3528262af557SGuo Chao pnv_ioda_parse_m64_window(phb); 3529262af557SGuo Chao 3530184cd4a3SBenjamin Herrenschmidt phb->ioda.m32_size = resource_size(&hose->mem_resources[0]); 3531aa0c033fSGavin Shan /* FW Has already off top 64k of M32 space (MSI space) */ 3532184cd4a3SBenjamin Herrenschmidt phb->ioda.m32_size += 0x10000; 3533184cd4a3SBenjamin Herrenschmidt 353492b8f137SGavin Shan phb->ioda.m32_segsize = phb->ioda.m32_size / phb->ioda.total_pe_num; 35353fd47f06SBenjamin Herrenschmidt phb->ioda.m32_pci_base = hose->mem_resources[0].start - hose->mem_offset[0]; 3536184cd4a3SBenjamin Herrenschmidt phb->ioda.io_size = hose->pci_io_size; 353792b8f137SGavin Shan phb->ioda.io_segsize = phb->ioda.io_size / phb->ioda.total_pe_num; 3538184cd4a3SBenjamin Herrenschmidt phb->ioda.io_pci_base = 0; /* XXX calculate this ? */ 3539184cd4a3SBenjamin Herrenschmidt 35402b923ed1SGavin Shan /* Calculate how many 32-bit TCE segments we have */ 35412b923ed1SGavin Shan phb->ioda.dma32_count = phb->ioda.m32_pci_base / 35422b923ed1SGavin Shan PNV_IODA1_DMA32_SEGSIZE; 35432b923ed1SGavin Shan 3544c35d2a8cSGavin Shan /* Allocate aux data & arrays. We don't have IO ports on PHB3 */ 354592a86756SAlexey Kardashevskiy size = _ALIGN_UP(max_t(unsigned, phb->ioda.total_pe_num, 8) / 8, 354692a86756SAlexey Kardashevskiy sizeof(unsigned long)); 354793289d8cSGavin Shan m64map_off = size; 354893289d8cSGavin Shan size += phb->ioda.total_pe_num * sizeof(phb->ioda.m64_segmap[0]); 3549184cd4a3SBenjamin Herrenschmidt m32map_off = size; 355092b8f137SGavin Shan size += phb->ioda.total_pe_num * sizeof(phb->ioda.m32_segmap[0]); 3551c35d2a8cSGavin Shan if (phb->type == PNV_PHB_IODA1) { 3552c35d2a8cSGavin Shan iomap_off = size; 355392b8f137SGavin Shan size += phb->ioda.total_pe_num * sizeof(phb->ioda.io_segmap[0]); 35542b923ed1SGavin Shan dma32map_off = size; 35552b923ed1SGavin Shan size += phb->ioda.dma32_count * 35562b923ed1SGavin Shan sizeof(phb->ioda.dma32_segmap[0]); 3557c35d2a8cSGavin Shan } 3558184cd4a3SBenjamin Herrenschmidt pemap_off = size; 355992b8f137SGavin Shan size += phb->ioda.total_pe_num * sizeof(struct pnv_ioda_pe); 3560e39f223fSMichael Ellerman aux = memblock_virt_alloc(size, 0); 3561184cd4a3SBenjamin Herrenschmidt phb->ioda.pe_alloc = aux; 356293289d8cSGavin Shan phb->ioda.m64_segmap = aux + m64map_off; 3563184cd4a3SBenjamin Herrenschmidt phb->ioda.m32_segmap = aux + m32map_off; 356493289d8cSGavin Shan for (segno = 0; segno < phb->ioda.total_pe_num; segno++) { 356593289d8cSGavin Shan phb->ioda.m64_segmap[segno] = IODA_INVALID_PE; 35663fa23ff8SGavin Shan phb->ioda.m32_segmap[segno] = IODA_INVALID_PE; 356793289d8cSGavin Shan } 35683fa23ff8SGavin Shan if (phb->type == PNV_PHB_IODA1) { 3569184cd4a3SBenjamin Herrenschmidt phb->ioda.io_segmap = aux + iomap_off; 35703fa23ff8SGavin Shan for (segno = 0; segno < phb->ioda.total_pe_num; segno++) 35713fa23ff8SGavin Shan phb->ioda.io_segmap[segno] = IODA_INVALID_PE; 35722b923ed1SGavin Shan 35732b923ed1SGavin Shan phb->ioda.dma32_segmap = aux + dma32map_off; 35742b923ed1SGavin Shan for (segno = 0; segno < phb->ioda.dma32_count; segno++) 35752b923ed1SGavin Shan phb->ioda.dma32_segmap[segno] = IODA_INVALID_PE; 35763fa23ff8SGavin Shan } 3577184cd4a3SBenjamin Herrenschmidt phb->ioda.pe_array = aux + pemap_off; 357863803c39SGavin Shan 357963803c39SGavin Shan /* 358063803c39SGavin Shan * Choose PE number for root bus, which shouldn't have 358163803c39SGavin Shan * M64 resources consumed by its child devices. To pick 358263803c39SGavin Shan * the PE number adjacent to the reserved one if possible. 358363803c39SGavin Shan */ 358463803c39SGavin Shan pnv_ioda_reserve_pe(phb, phb->ioda.reserved_pe_idx); 358563803c39SGavin Shan if (phb->ioda.reserved_pe_idx == 0) { 358663803c39SGavin Shan phb->ioda.root_pe_idx = 1; 358763803c39SGavin Shan pnv_ioda_reserve_pe(phb, phb->ioda.root_pe_idx); 358863803c39SGavin Shan } else if (phb->ioda.reserved_pe_idx == (phb->ioda.total_pe_num - 1)) { 358963803c39SGavin Shan phb->ioda.root_pe_idx = phb->ioda.reserved_pe_idx - 1; 359063803c39SGavin Shan pnv_ioda_reserve_pe(phb, phb->ioda.root_pe_idx); 359163803c39SGavin Shan } else { 359263803c39SGavin Shan phb->ioda.root_pe_idx = IODA_INVALID_PE; 359363803c39SGavin Shan } 3594184cd4a3SBenjamin Herrenschmidt 3595184cd4a3SBenjamin Herrenschmidt INIT_LIST_HEAD(&phb->ioda.pe_list); 3596781a868fSWei Yang mutex_init(&phb->ioda.pe_list_mutex); 3597184cd4a3SBenjamin Herrenschmidt 3598184cd4a3SBenjamin Herrenschmidt /* Calculate how many 32-bit TCE segments we have */ 35992b923ed1SGavin Shan phb->ioda.dma32_count = phb->ioda.m32_pci_base / 3600acce971cSGavin Shan PNV_IODA1_DMA32_SEGSIZE; 3601184cd4a3SBenjamin Herrenschmidt 3602aa0c033fSGavin Shan #if 0 /* We should really do that ... */ 3603184cd4a3SBenjamin Herrenschmidt rc = opal_pci_set_phb_mem_window(opal->phb_id, 3604184cd4a3SBenjamin Herrenschmidt window_type, 3605184cd4a3SBenjamin Herrenschmidt window_num, 3606184cd4a3SBenjamin Herrenschmidt starting_real_address, 3607184cd4a3SBenjamin Herrenschmidt starting_pci_address, 3608184cd4a3SBenjamin Herrenschmidt segment_size); 3609184cd4a3SBenjamin Herrenschmidt #endif 3610184cd4a3SBenjamin Herrenschmidt 3611262af557SGuo Chao pr_info(" %03d (%03d) PE's M32: 0x%x [segment=0x%x]\n", 361292b8f137SGavin Shan phb->ioda.total_pe_num, phb->ioda.reserved_pe_idx, 3613262af557SGuo Chao phb->ioda.m32_size, phb->ioda.m32_segsize); 3614262af557SGuo Chao if (phb->ioda.m64_size) 3615262af557SGuo Chao pr_info(" M64: 0x%lx [segment=0x%lx]\n", 3616262af557SGuo Chao phb->ioda.m64_size, phb->ioda.m64_segsize); 3617262af557SGuo Chao if (phb->ioda.io_size) 3618262af557SGuo Chao pr_info(" IO: 0x%x [segment=0x%x]\n", 3619184cd4a3SBenjamin Herrenschmidt phb->ioda.io_size, phb->ioda.io_segsize); 3620184cd4a3SBenjamin Herrenschmidt 3621262af557SGuo Chao 3622184cd4a3SBenjamin Herrenschmidt phb->hose->ops = &pnv_pci_ops; 362349dec922SGavin Shan phb->get_pe_state = pnv_ioda_get_pe_state; 362449dec922SGavin Shan phb->freeze_pe = pnv_ioda_freeze_pe; 362549dec922SGavin Shan phb->unfreeze_pe = pnv_ioda_unfreeze_pe; 3626184cd4a3SBenjamin Herrenschmidt 3627184cd4a3SBenjamin Herrenschmidt /* Setup MSI support */ 3628184cd4a3SBenjamin Herrenschmidt pnv_pci_init_ioda_msis(phb); 3629184cd4a3SBenjamin Herrenschmidt 3630c40a4210SGavin Shan /* 3631c40a4210SGavin Shan * We pass the PCI probe flag PCI_REASSIGN_ALL_RSRC here 3632c40a4210SGavin Shan * to let the PCI core do resource assignment. It's supposed 3633c40a4210SGavin Shan * that the PCI core will do correct I/O and MMIO alignment 3634c40a4210SGavin Shan * for the P2P bridge bars so that each PCI bus (excluding 3635c40a4210SGavin Shan * the child P2P bridges) can form individual PE. 3636184cd4a3SBenjamin Herrenschmidt */ 3637fb446ad0SGavin Shan ppc_md.pcibios_fixup = pnv_pci_ioda_fixup; 36385d2aa710SAlistair Popple 3639f9f83456SAlexey Kardashevskiy if (phb->type == PNV_PHB_NPU) { 36405d2aa710SAlistair Popple hose->controller_ops = pnv_npu_ioda_controller_ops; 3641f9f83456SAlexey Kardashevskiy } else { 3642f9f83456SAlexey Kardashevskiy phb->dma_dev_setup = pnv_pci_ioda_dma_dev_setup; 364392ae0353SDaniel Axtens hose->controller_ops = pnv_pci_ioda_controller_ops; 3644f9f83456SAlexey Kardashevskiy } 3645ad30cb99SMichael Ellerman 36466e628c7dSWei Yang #ifdef CONFIG_PCI_IOV 36476e628c7dSWei Yang ppc_md.pcibios_fixup_sriov = pnv_pci_ioda_fixup_iov_resources; 36485350ab3fSWei Yang ppc_md.pcibios_iov_resource_alignment = pnv_pci_iov_resource_alignment; 3649ad30cb99SMichael Ellerman #endif 3650ad30cb99SMichael Ellerman 3651c40a4210SGavin Shan pci_add_flags(PCI_REASSIGN_ALL_RSRC); 3652184cd4a3SBenjamin Herrenschmidt 3653184cd4a3SBenjamin Herrenschmidt /* Reset IODA tables to a clean state */ 3654d1a85eeeSGavin Shan rc = opal_pci_reset(phb_id, OPAL_RESET_PCI_IODA_TABLE, OPAL_ASSERT_RESET); 3655184cd4a3SBenjamin Herrenschmidt if (rc) 3656f11fe552SBenjamin Herrenschmidt pr_warning(" OPAL Error %ld performing IODA table reset !\n", rc); 3657361f2a2aSGavin Shan 3658361f2a2aSGavin Shan /* If we're running in kdump kerenl, the previous kerenl never 3659361f2a2aSGavin Shan * shutdown PCI devices correctly. We already got IODA table 3660361f2a2aSGavin Shan * cleaned out. So we have to issue PHB reset to stop all PCI 3661361f2a2aSGavin Shan * transactions from previous kerenl. 3662361f2a2aSGavin Shan */ 3663361f2a2aSGavin Shan if (is_kdump_kernel()) { 3664361f2a2aSGavin Shan pr_info(" Issue PHB reset ...\n"); 3665cadf364dSGavin Shan pnv_eeh_phb_reset(hose, EEH_RESET_FUNDAMENTAL); 3666cadf364dSGavin Shan pnv_eeh_phb_reset(hose, EEH_RESET_DEACTIVATE); 3667361f2a2aSGavin Shan } 3668262af557SGuo Chao 36699e9e8935SGavin Shan /* Remove M64 resource if we can't configure it successfully */ 36709e9e8935SGavin Shan if (!phb->init_m64 || phb->init_m64(phb)) 3671262af557SGuo Chao hose->mem_resources[1].flags = 0; 3672184cd4a3SBenjamin Herrenschmidt } 3673184cd4a3SBenjamin Herrenschmidt 367467975005SBjorn Helgaas void __init pnv_pci_init_ioda2_phb(struct device_node *np) 3675aa0c033fSGavin Shan { 3676e9cc17d4SGavin Shan pnv_pci_init_ioda_phb(np, 0, PNV_PHB_IODA2); 3677aa0c033fSGavin Shan } 3678aa0c033fSGavin Shan 36795d2aa710SAlistair Popple void __init pnv_pci_init_npu_phb(struct device_node *np) 36805d2aa710SAlistair Popple { 36815d2aa710SAlistair Popple pnv_pci_init_ioda_phb(np, 0, PNV_PHB_NPU); 36825d2aa710SAlistair Popple } 36835d2aa710SAlistair Popple 3684184cd4a3SBenjamin Herrenschmidt void __init pnv_pci_init_ioda_hub(struct device_node *np) 3685184cd4a3SBenjamin Herrenschmidt { 3686184cd4a3SBenjamin Herrenschmidt struct device_node *phbn; 3687c681b93cSAlistair Popple const __be64 *prop64; 3688184cd4a3SBenjamin Herrenschmidt u64 hub_id; 3689184cd4a3SBenjamin Herrenschmidt 3690184cd4a3SBenjamin Herrenschmidt pr_info("Probing IODA IO-Hub %s\n", np->full_name); 3691184cd4a3SBenjamin Herrenschmidt 3692184cd4a3SBenjamin Herrenschmidt prop64 = of_get_property(np, "ibm,opal-hubid", NULL); 3693184cd4a3SBenjamin Herrenschmidt if (!prop64) { 3694184cd4a3SBenjamin Herrenschmidt pr_err(" Missing \"ibm,opal-hubid\" property !\n"); 3695184cd4a3SBenjamin Herrenschmidt return; 3696184cd4a3SBenjamin Herrenschmidt } 3697184cd4a3SBenjamin Herrenschmidt hub_id = be64_to_cpup(prop64); 3698184cd4a3SBenjamin Herrenschmidt pr_devel(" HUB-ID : 0x%016llx\n", hub_id); 3699184cd4a3SBenjamin Herrenschmidt 3700184cd4a3SBenjamin Herrenschmidt /* Count child PHBs */ 3701184cd4a3SBenjamin Herrenschmidt for_each_child_of_node(np, phbn) { 3702184cd4a3SBenjamin Herrenschmidt /* Look for IODA1 PHBs */ 3703184cd4a3SBenjamin Herrenschmidt if (of_device_is_compatible(phbn, "ibm,ioda-phb")) 3704e9cc17d4SGavin Shan pnv_pci_init_ioda_phb(phbn, hub_id, PNV_PHB_IODA1); 3705184cd4a3SBenjamin Herrenschmidt } 3706184cd4a3SBenjamin Herrenschmidt } 3707