1184cd4a3SBenjamin Herrenschmidt /* 2184cd4a3SBenjamin Herrenschmidt * Support PCI/PCIe on PowerNV platforms 3184cd4a3SBenjamin Herrenschmidt * 4184cd4a3SBenjamin Herrenschmidt * Copyright 2011 Benjamin Herrenschmidt, IBM Corp. 5184cd4a3SBenjamin Herrenschmidt * 6184cd4a3SBenjamin Herrenschmidt * This program is free software; you can redistribute it and/or 7184cd4a3SBenjamin Herrenschmidt * modify it under the terms of the GNU General Public License 8184cd4a3SBenjamin Herrenschmidt * as published by the Free Software Foundation; either version 9184cd4a3SBenjamin Herrenschmidt * 2 of the License, or (at your option) any later version. 10184cd4a3SBenjamin Herrenschmidt */ 11184cd4a3SBenjamin Herrenschmidt 12cee72d5bSBenjamin Herrenschmidt #undef DEBUG 13184cd4a3SBenjamin Herrenschmidt 14184cd4a3SBenjamin Herrenschmidt #include <linux/kernel.h> 15184cd4a3SBenjamin Herrenschmidt #include <linux/pci.h> 16361f2a2aSGavin Shan #include <linux/crash_dump.h> 1737c367f2SGavin Shan #include <linux/debugfs.h> 18184cd4a3SBenjamin Herrenschmidt #include <linux/delay.h> 19184cd4a3SBenjamin Herrenschmidt #include <linux/string.h> 20184cd4a3SBenjamin Herrenschmidt #include <linux/init.h> 21184cd4a3SBenjamin Herrenschmidt #include <linux/bootmem.h> 22184cd4a3SBenjamin Herrenschmidt #include <linux/irq.h> 23184cd4a3SBenjamin Herrenschmidt #include <linux/io.h> 24184cd4a3SBenjamin Herrenschmidt #include <linux/msi.h> 25cd15b048SBenjamin Herrenschmidt #include <linux/memblock.h> 26ac9a5889SAlexey Kardashevskiy #include <linux/iommu.h> 27e57080f1SAlexey Kardashevskiy #include <linux/rculist.h> 284793d65dSAlexey Kardashevskiy #include <linux/sizes.h> 29184cd4a3SBenjamin Herrenschmidt 30184cd4a3SBenjamin Herrenschmidt #include <asm/sections.h> 31184cd4a3SBenjamin Herrenschmidt #include <asm/io.h> 32184cd4a3SBenjamin Herrenschmidt #include <asm/prom.h> 33184cd4a3SBenjamin Herrenschmidt #include <asm/pci-bridge.h> 34184cd4a3SBenjamin Herrenschmidt #include <asm/machdep.h> 35fb1b55d6SGavin Shan #include <asm/msi_bitmap.h> 36184cd4a3SBenjamin Herrenschmidt #include <asm/ppc-pci.h> 37184cd4a3SBenjamin Herrenschmidt #include <asm/opal.h> 38184cd4a3SBenjamin Herrenschmidt #include <asm/iommu.h> 39184cd4a3SBenjamin Herrenschmidt #include <asm/tce.h> 40137436c9SGavin Shan #include <asm/xics.h> 4137c367f2SGavin Shan #include <asm/debug.h> 42262af557SGuo Chao #include <asm/firmware.h> 4380c49c7eSIan Munsie #include <asm/pnv-pci.h> 44aca6913fSAlexey Kardashevskiy #include <asm/mmzone.h> 4580c49c7eSIan Munsie 46ec249dd8SMichael Neuling #include <misc/cxl-base.h> 47184cd4a3SBenjamin Herrenschmidt 48184cd4a3SBenjamin Herrenschmidt #include "powernv.h" 49184cd4a3SBenjamin Herrenschmidt #include "pci.h" 50184cd4a3SBenjamin Herrenschmidt 5199451551SGavin Shan #define PNV_IODA1_M64_NUM 16 /* Number of M64 BARs */ 5299451551SGavin Shan #define PNV_IODA1_M64_SEGS 8 /* Segments per M64 BAR */ 53acce971cSGavin Shan #define PNV_IODA1_DMA32_SEGSIZE 0x10000000 54781a868fSWei Yang 55bbb845c4SAlexey Kardashevskiy #define POWERNV_IOMMU_DEFAULT_LEVELS 1 56bbb845c4SAlexey Kardashevskiy #define POWERNV_IOMMU_MAX_LEVELS 5 57bbb845c4SAlexey Kardashevskiy 58aca6913fSAlexey Kardashevskiy static void pnv_pci_ioda2_table_free_pages(struct iommu_table *tbl); 59aca6913fSAlexey Kardashevskiy 606d31c2faSJoe Perches static void pe_level_printk(const struct pnv_ioda_pe *pe, const char *level, 616d31c2faSJoe Perches const char *fmt, ...) 626d31c2faSJoe Perches { 636d31c2faSJoe Perches struct va_format vaf; 646d31c2faSJoe Perches va_list args; 656d31c2faSJoe Perches char pfix[32]; 66184cd4a3SBenjamin Herrenschmidt 676d31c2faSJoe Perches va_start(args, fmt); 686d31c2faSJoe Perches 696d31c2faSJoe Perches vaf.fmt = fmt; 706d31c2faSJoe Perches vaf.va = &args; 716d31c2faSJoe Perches 72781a868fSWei Yang if (pe->flags & PNV_IODA_PE_DEV) 736d31c2faSJoe Perches strlcpy(pfix, dev_name(&pe->pdev->dev), sizeof(pfix)); 74781a868fSWei Yang else if (pe->flags & (PNV_IODA_PE_BUS | PNV_IODA_PE_BUS_ALL)) 756d31c2faSJoe Perches sprintf(pfix, "%04x:%02x ", 766d31c2faSJoe Perches pci_domain_nr(pe->pbus), pe->pbus->number); 77781a868fSWei Yang #ifdef CONFIG_PCI_IOV 78781a868fSWei Yang else if (pe->flags & PNV_IODA_PE_VF) 79781a868fSWei Yang sprintf(pfix, "%04x:%02x:%2x.%d", 80781a868fSWei Yang pci_domain_nr(pe->parent_dev->bus), 81781a868fSWei Yang (pe->rid & 0xff00) >> 8, 82781a868fSWei Yang PCI_SLOT(pe->rid), PCI_FUNC(pe->rid)); 83781a868fSWei Yang #endif /* CONFIG_PCI_IOV*/ 846d31c2faSJoe Perches 856d31c2faSJoe Perches printk("%spci %s: [PE# %.3d] %pV", 866d31c2faSJoe Perches level, pfix, pe->pe_number, &vaf); 876d31c2faSJoe Perches 886d31c2faSJoe Perches va_end(args); 896d31c2faSJoe Perches } 906d31c2faSJoe Perches 916d31c2faSJoe Perches #define pe_err(pe, fmt, ...) \ 926d31c2faSJoe Perches pe_level_printk(pe, KERN_ERR, fmt, ##__VA_ARGS__) 936d31c2faSJoe Perches #define pe_warn(pe, fmt, ...) \ 946d31c2faSJoe Perches pe_level_printk(pe, KERN_WARNING, fmt, ##__VA_ARGS__) 956d31c2faSJoe Perches #define pe_info(pe, fmt, ...) \ 966d31c2faSJoe Perches pe_level_printk(pe, KERN_INFO, fmt, ##__VA_ARGS__) 97184cd4a3SBenjamin Herrenschmidt 984e287840SThadeu Lima de Souza Cascardo static bool pnv_iommu_bypass_disabled __read_mostly; 994e287840SThadeu Lima de Souza Cascardo 1004e287840SThadeu Lima de Souza Cascardo static int __init iommu_setup(char *str) 1014e287840SThadeu Lima de Souza Cascardo { 1024e287840SThadeu Lima de Souza Cascardo if (!str) 1034e287840SThadeu Lima de Souza Cascardo return -EINVAL; 1044e287840SThadeu Lima de Souza Cascardo 1054e287840SThadeu Lima de Souza Cascardo while (*str) { 1064e287840SThadeu Lima de Souza Cascardo if (!strncmp(str, "nobypass", 8)) { 1074e287840SThadeu Lima de Souza Cascardo pnv_iommu_bypass_disabled = true; 1084e287840SThadeu Lima de Souza Cascardo pr_info("PowerNV: IOMMU bypass window disabled.\n"); 1094e287840SThadeu Lima de Souza Cascardo break; 1104e287840SThadeu Lima de Souza Cascardo } 1114e287840SThadeu Lima de Souza Cascardo str += strcspn(str, ","); 1124e287840SThadeu Lima de Souza Cascardo if (*str == ',') 1134e287840SThadeu Lima de Souza Cascardo str++; 1144e287840SThadeu Lima de Souza Cascardo } 1154e287840SThadeu Lima de Souza Cascardo 1164e287840SThadeu Lima de Souza Cascardo return 0; 1174e287840SThadeu Lima de Souza Cascardo } 1184e287840SThadeu Lima de Souza Cascardo early_param("iommu", iommu_setup); 1194e287840SThadeu Lima de Souza Cascardo 120262af557SGuo Chao static inline bool pnv_pci_is_mem_pref_64(unsigned long flags) 121262af557SGuo Chao { 122262af557SGuo Chao return ((flags & (IORESOURCE_MEM_64 | IORESOURCE_PREFETCH)) == 123262af557SGuo Chao (IORESOURCE_MEM_64 | IORESOURCE_PREFETCH)); 124262af557SGuo Chao } 125262af557SGuo Chao 1261e916772SGavin Shan static struct pnv_ioda_pe *pnv_ioda_init_pe(struct pnv_phb *phb, int pe_no) 1271e916772SGavin Shan { 1281e916772SGavin Shan phb->ioda.pe_array[pe_no].phb = phb; 1291e916772SGavin Shan phb->ioda.pe_array[pe_no].pe_number = pe_no; 1301e916772SGavin Shan 1311e916772SGavin Shan return &phb->ioda.pe_array[pe_no]; 1321e916772SGavin Shan } 1331e916772SGavin Shan 1344b82ab18SGavin Shan static void pnv_ioda_reserve_pe(struct pnv_phb *phb, int pe_no) 1354b82ab18SGavin Shan { 13692b8f137SGavin Shan if (!(pe_no >= 0 && pe_no < phb->ioda.total_pe_num)) { 1374b82ab18SGavin Shan pr_warn("%s: Invalid PE %d on PHB#%x\n", 1384b82ab18SGavin Shan __func__, pe_no, phb->hose->global_number); 1394b82ab18SGavin Shan return; 1404b82ab18SGavin Shan } 1414b82ab18SGavin Shan 142e9dc4d7fSGavin Shan if (test_and_set_bit(pe_no, phb->ioda.pe_alloc)) 143e9dc4d7fSGavin Shan pr_debug("%s: PE %d was reserved on PHB#%x\n", 1444b82ab18SGavin Shan __func__, pe_no, phb->hose->global_number); 1454b82ab18SGavin Shan 1461e916772SGavin Shan pnv_ioda_init_pe(phb, pe_no); 1474b82ab18SGavin Shan } 1484b82ab18SGavin Shan 1491e916772SGavin Shan static struct pnv_ioda_pe *pnv_ioda_alloc_pe(struct pnv_phb *phb) 150184cd4a3SBenjamin Herrenschmidt { 151184cd4a3SBenjamin Herrenschmidt unsigned long pe; 152184cd4a3SBenjamin Herrenschmidt 153184cd4a3SBenjamin Herrenschmidt do { 154184cd4a3SBenjamin Herrenschmidt pe = find_next_zero_bit(phb->ioda.pe_alloc, 15592b8f137SGavin Shan phb->ioda.total_pe_num, 0); 15692b8f137SGavin Shan if (pe >= phb->ioda.total_pe_num) 1571e916772SGavin Shan return NULL; 158184cd4a3SBenjamin Herrenschmidt } while(test_and_set_bit(pe, phb->ioda.pe_alloc)); 159184cd4a3SBenjamin Herrenschmidt 1601e916772SGavin Shan return pnv_ioda_init_pe(phb, pe); 161184cd4a3SBenjamin Herrenschmidt } 162184cd4a3SBenjamin Herrenschmidt 1631e916772SGavin Shan static void pnv_ioda_free_pe(struct pnv_ioda_pe *pe) 164184cd4a3SBenjamin Herrenschmidt { 1651e916772SGavin Shan struct pnv_phb *phb = pe->phb; 166184cd4a3SBenjamin Herrenschmidt 1671e916772SGavin Shan WARN_ON(pe->pdev); 1681e916772SGavin Shan 1691e916772SGavin Shan memset(pe, 0, sizeof(struct pnv_ioda_pe)); 1701e916772SGavin Shan clear_bit(pe->pe_number, phb->ioda.pe_alloc); 171184cd4a3SBenjamin Herrenschmidt } 172184cd4a3SBenjamin Herrenschmidt 173262af557SGuo Chao /* The default M64 BAR is shared by all PEs */ 174262af557SGuo Chao static int pnv_ioda2_init_m64(struct pnv_phb *phb) 175262af557SGuo Chao { 176262af557SGuo Chao const char *desc; 177262af557SGuo Chao struct resource *r; 178262af557SGuo Chao s64 rc; 179262af557SGuo Chao 180262af557SGuo Chao /* Configure the default M64 BAR */ 181262af557SGuo Chao rc = opal_pci_set_phb_mem_window(phb->opal_id, 182262af557SGuo Chao OPAL_M64_WINDOW_TYPE, 183262af557SGuo Chao phb->ioda.m64_bar_idx, 184262af557SGuo Chao phb->ioda.m64_base, 185262af557SGuo Chao 0, /* unused */ 186262af557SGuo Chao phb->ioda.m64_size); 187262af557SGuo Chao if (rc != OPAL_SUCCESS) { 188262af557SGuo Chao desc = "configuring"; 189262af557SGuo Chao goto fail; 190262af557SGuo Chao } 191262af557SGuo Chao 192262af557SGuo Chao /* Enable the default M64 BAR */ 193262af557SGuo Chao rc = opal_pci_phb_mmio_enable(phb->opal_id, 194262af557SGuo Chao OPAL_M64_WINDOW_TYPE, 195262af557SGuo Chao phb->ioda.m64_bar_idx, 196262af557SGuo Chao OPAL_ENABLE_M64_SPLIT); 197262af557SGuo Chao if (rc != OPAL_SUCCESS) { 198262af557SGuo Chao desc = "enabling"; 199262af557SGuo Chao goto fail; 200262af557SGuo Chao } 201262af557SGuo Chao 202262af557SGuo Chao /* Mark the M64 BAR assigned */ 203262af557SGuo Chao set_bit(phb->ioda.m64_bar_idx, &phb->ioda.m64_bar_alloc); 204262af557SGuo Chao 205262af557SGuo Chao /* 206262af557SGuo Chao * Strip off the segment used by the reserved PE, which is 207262af557SGuo Chao * expected to be 0 or last one of PE capabicity. 208262af557SGuo Chao */ 209262af557SGuo Chao r = &phb->hose->mem_resources[1]; 21092b8f137SGavin Shan if (phb->ioda.reserved_pe_idx == 0) 211262af557SGuo Chao r->start += phb->ioda.m64_segsize; 21292b8f137SGavin Shan else if (phb->ioda.reserved_pe_idx == (phb->ioda.total_pe_num - 1)) 213262af557SGuo Chao r->end -= phb->ioda.m64_segsize; 214262af557SGuo Chao else 215262af557SGuo Chao pr_warn(" Cannot strip M64 segment for reserved PE#%d\n", 21692b8f137SGavin Shan phb->ioda.reserved_pe_idx); 217262af557SGuo Chao 218262af557SGuo Chao return 0; 219262af557SGuo Chao 220262af557SGuo Chao fail: 221262af557SGuo Chao pr_warn(" Failure %lld %s M64 BAR#%d\n", 222262af557SGuo Chao rc, desc, phb->ioda.m64_bar_idx); 223262af557SGuo Chao opal_pci_phb_mmio_enable(phb->opal_id, 224262af557SGuo Chao OPAL_M64_WINDOW_TYPE, 225262af557SGuo Chao phb->ioda.m64_bar_idx, 226262af557SGuo Chao OPAL_DISABLE_M64); 227262af557SGuo Chao return -EIO; 228262af557SGuo Chao } 229262af557SGuo Chao 230c430670aSGavin Shan static void pnv_ioda_reserve_dev_m64_pe(struct pci_dev *pdev, 23196a2f92bSGavin Shan unsigned long *pe_bitmap) 232262af557SGuo Chao { 23396a2f92bSGavin Shan struct pci_controller *hose = pci_bus_to_host(pdev->bus); 23496a2f92bSGavin Shan struct pnv_phb *phb = hose->private_data; 235262af557SGuo Chao struct resource *r; 23696a2f92bSGavin Shan resource_size_t base, sgsz, start, end; 23796a2f92bSGavin Shan int segno, i; 238262af557SGuo Chao 23996a2f92bSGavin Shan base = phb->ioda.m64_base; 24096a2f92bSGavin Shan sgsz = phb->ioda.m64_segsize; 24196a2f92bSGavin Shan for (i = 0; i <= PCI_ROM_RESOURCE; i++) { 24296a2f92bSGavin Shan r = &pdev->resource[i]; 24396a2f92bSGavin Shan if (!r->parent || !pnv_pci_is_mem_pref_64(r->flags)) 244262af557SGuo Chao continue; 245262af557SGuo Chao 24696a2f92bSGavin Shan start = _ALIGN_DOWN(r->start - base, sgsz); 24796a2f92bSGavin Shan end = _ALIGN_UP(r->end - base, sgsz); 24896a2f92bSGavin Shan for (segno = start / sgsz; segno < end / sgsz; segno++) { 24996a2f92bSGavin Shan if (pe_bitmap) 25096a2f92bSGavin Shan set_bit(segno, pe_bitmap); 25196a2f92bSGavin Shan else 25296a2f92bSGavin Shan pnv_ioda_reserve_pe(phb, segno); 253262af557SGuo Chao } 254262af557SGuo Chao } 255262af557SGuo Chao } 256262af557SGuo Chao 25799451551SGavin Shan static int pnv_ioda1_init_m64(struct pnv_phb *phb) 25899451551SGavin Shan { 25999451551SGavin Shan struct resource *r; 26099451551SGavin Shan int index; 26199451551SGavin Shan 26299451551SGavin Shan /* 26399451551SGavin Shan * There are 16 M64 BARs, each of which has 8 segments. So 26499451551SGavin Shan * there are as many M64 segments as the maximum number of 26599451551SGavin Shan * PEs, which is 128. 26699451551SGavin Shan */ 26799451551SGavin Shan for (index = 0; index < PNV_IODA1_M64_NUM; index++) { 26899451551SGavin Shan unsigned long base, segsz = phb->ioda.m64_segsize; 26999451551SGavin Shan int64_t rc; 27099451551SGavin Shan 27199451551SGavin Shan base = phb->ioda.m64_base + 27299451551SGavin Shan index * PNV_IODA1_M64_SEGS * segsz; 27399451551SGavin Shan rc = opal_pci_set_phb_mem_window(phb->opal_id, 27499451551SGavin Shan OPAL_M64_WINDOW_TYPE, index, base, 0, 27599451551SGavin Shan PNV_IODA1_M64_SEGS * segsz); 27699451551SGavin Shan if (rc != OPAL_SUCCESS) { 27799451551SGavin Shan pr_warn(" Error %lld setting M64 PHB#%d-BAR#%d\n", 27899451551SGavin Shan rc, phb->hose->global_number, index); 27999451551SGavin Shan goto fail; 28099451551SGavin Shan } 28199451551SGavin Shan 28299451551SGavin Shan rc = opal_pci_phb_mmio_enable(phb->opal_id, 28399451551SGavin Shan OPAL_M64_WINDOW_TYPE, index, 28499451551SGavin Shan OPAL_ENABLE_M64_SPLIT); 28599451551SGavin Shan if (rc != OPAL_SUCCESS) { 28699451551SGavin Shan pr_warn(" Error %lld enabling M64 PHB#%d-BAR#%d\n", 28799451551SGavin Shan rc, phb->hose->global_number, index); 28899451551SGavin Shan goto fail; 28999451551SGavin Shan } 29099451551SGavin Shan } 29199451551SGavin Shan 29299451551SGavin Shan /* 29399451551SGavin Shan * Exclude the segment used by the reserved PE, which 29499451551SGavin Shan * is expected to be 0 or last supported PE#. 29599451551SGavin Shan */ 29699451551SGavin Shan r = &phb->hose->mem_resources[1]; 29799451551SGavin Shan if (phb->ioda.reserved_pe_idx == 0) 29899451551SGavin Shan r->start += phb->ioda.m64_segsize; 29999451551SGavin Shan else if (phb->ioda.reserved_pe_idx == (phb->ioda.total_pe_num - 1)) 30099451551SGavin Shan r->end -= phb->ioda.m64_segsize; 30199451551SGavin Shan else 30299451551SGavin Shan WARN(1, "Wrong reserved PE#%d on PHB#%d\n", 30399451551SGavin Shan phb->ioda.reserved_pe_idx, phb->hose->global_number); 30499451551SGavin Shan 30599451551SGavin Shan return 0; 30699451551SGavin Shan 30799451551SGavin Shan fail: 30899451551SGavin Shan for ( ; index >= 0; index--) 30999451551SGavin Shan opal_pci_phb_mmio_enable(phb->opal_id, 31099451551SGavin Shan OPAL_M64_WINDOW_TYPE, index, OPAL_DISABLE_M64); 31199451551SGavin Shan 31299451551SGavin Shan return -EIO; 31399451551SGavin Shan } 31499451551SGavin Shan 315c430670aSGavin Shan static void pnv_ioda_reserve_m64_pe(struct pci_bus *bus, 31696a2f92bSGavin Shan unsigned long *pe_bitmap, 31796a2f92bSGavin Shan bool all) 318262af557SGuo Chao { 319262af557SGuo Chao struct pci_dev *pdev; 32096a2f92bSGavin Shan 32196a2f92bSGavin Shan list_for_each_entry(pdev, &bus->devices, bus_list) { 322c430670aSGavin Shan pnv_ioda_reserve_dev_m64_pe(pdev, pe_bitmap); 32396a2f92bSGavin Shan 32496a2f92bSGavin Shan if (all && pdev->subordinate) 325c430670aSGavin Shan pnv_ioda_reserve_m64_pe(pdev->subordinate, 32696a2f92bSGavin Shan pe_bitmap, all); 32796a2f92bSGavin Shan } 32896a2f92bSGavin Shan } 32996a2f92bSGavin Shan 3301e916772SGavin Shan static struct pnv_ioda_pe *pnv_ioda_pick_m64_pe(struct pci_bus *bus, bool all) 331262af557SGuo Chao { 33226ba248dSGavin Shan struct pci_controller *hose = pci_bus_to_host(bus); 33326ba248dSGavin Shan struct pnv_phb *phb = hose->private_data; 334262af557SGuo Chao struct pnv_ioda_pe *master_pe, *pe; 335262af557SGuo Chao unsigned long size, *pe_alloc; 33626ba248dSGavin Shan int i; 337262af557SGuo Chao 338262af557SGuo Chao /* Root bus shouldn't use M64 */ 339262af557SGuo Chao if (pci_is_root_bus(bus)) 3401e916772SGavin Shan return NULL; 341262af557SGuo Chao 342262af557SGuo Chao /* Allocate bitmap */ 34392b8f137SGavin Shan size = _ALIGN_UP(phb->ioda.total_pe_num / 8, sizeof(unsigned long)); 344262af557SGuo Chao pe_alloc = kzalloc(size, GFP_KERNEL); 345262af557SGuo Chao if (!pe_alloc) { 346262af557SGuo Chao pr_warn("%s: Out of memory !\n", 347262af557SGuo Chao __func__); 3481e916772SGavin Shan return NULL; 349262af557SGuo Chao } 350262af557SGuo Chao 35126ba248dSGavin Shan /* Figure out reserved PE numbers by the PE */ 352c430670aSGavin Shan pnv_ioda_reserve_m64_pe(bus, pe_alloc, all); 353262af557SGuo Chao 354262af557SGuo Chao /* 355262af557SGuo Chao * the current bus might not own M64 window and that's all 356262af557SGuo Chao * contributed by its child buses. For the case, we needn't 357262af557SGuo Chao * pick M64 dependent PE#. 358262af557SGuo Chao */ 35992b8f137SGavin Shan if (bitmap_empty(pe_alloc, phb->ioda.total_pe_num)) { 360262af557SGuo Chao kfree(pe_alloc); 3611e916772SGavin Shan return NULL; 362262af557SGuo Chao } 363262af557SGuo Chao 364262af557SGuo Chao /* 365262af557SGuo Chao * Figure out the master PE and put all slave PEs to master 366262af557SGuo Chao * PE's list to form compound PE. 367262af557SGuo Chao */ 368262af557SGuo Chao master_pe = NULL; 369262af557SGuo Chao i = -1; 37092b8f137SGavin Shan while ((i = find_next_bit(pe_alloc, phb->ioda.total_pe_num, i + 1)) < 37192b8f137SGavin Shan phb->ioda.total_pe_num) { 372262af557SGuo Chao pe = &phb->ioda.pe_array[i]; 373262af557SGuo Chao 37493289d8cSGavin Shan phb->ioda.m64_segmap[pe->pe_number] = pe->pe_number; 375262af557SGuo Chao if (!master_pe) { 376262af557SGuo Chao pe->flags |= PNV_IODA_PE_MASTER; 377262af557SGuo Chao INIT_LIST_HEAD(&pe->slaves); 378262af557SGuo Chao master_pe = pe; 379262af557SGuo Chao } else { 380262af557SGuo Chao pe->flags |= PNV_IODA_PE_SLAVE; 381262af557SGuo Chao pe->master = master_pe; 382262af557SGuo Chao list_add_tail(&pe->list, &master_pe->slaves); 383262af557SGuo Chao } 38499451551SGavin Shan 38599451551SGavin Shan /* 38699451551SGavin Shan * P7IOC supports M64DT, which helps mapping M64 segment 38799451551SGavin Shan * to one particular PE#. However, PHB3 has fixed mapping 38899451551SGavin Shan * between M64 segment and PE#. In order to have same logic 38999451551SGavin Shan * for P7IOC and PHB3, we enforce fixed mapping between M64 39099451551SGavin Shan * segment and PE# on P7IOC. 39199451551SGavin Shan */ 39299451551SGavin Shan if (phb->type == PNV_PHB_IODA1) { 39399451551SGavin Shan int64_t rc; 39499451551SGavin Shan 39599451551SGavin Shan rc = opal_pci_map_pe_mmio_window(phb->opal_id, 39699451551SGavin Shan pe->pe_number, OPAL_M64_WINDOW_TYPE, 39799451551SGavin Shan pe->pe_number / PNV_IODA1_M64_SEGS, 39899451551SGavin Shan pe->pe_number % PNV_IODA1_M64_SEGS); 39999451551SGavin Shan if (rc != OPAL_SUCCESS) 40099451551SGavin Shan pr_warn("%s: Error %lld mapping M64 for PHB#%d-PE#%d\n", 40199451551SGavin Shan __func__, rc, phb->hose->global_number, 40299451551SGavin Shan pe->pe_number); 40399451551SGavin Shan } 404262af557SGuo Chao } 405262af557SGuo Chao 406262af557SGuo Chao kfree(pe_alloc); 4071e916772SGavin Shan return master_pe; 408262af557SGuo Chao } 409262af557SGuo Chao 410262af557SGuo Chao static void __init pnv_ioda_parse_m64_window(struct pnv_phb *phb) 411262af557SGuo Chao { 412262af557SGuo Chao struct pci_controller *hose = phb->hose; 413262af557SGuo Chao struct device_node *dn = hose->dn; 414262af557SGuo Chao struct resource *res; 415262af557SGuo Chao const u32 *r; 416262af557SGuo Chao u64 pci_addr; 417262af557SGuo Chao 41899451551SGavin Shan if (phb->type != PNV_PHB_IODA1 && phb->type != PNV_PHB_IODA2) { 4191665c4a8SGavin Shan pr_info(" Not support M64 window\n"); 4201665c4a8SGavin Shan return; 4211665c4a8SGavin Shan } 4221665c4a8SGavin Shan 423e4d54f71SStewart Smith if (!firmware_has_feature(FW_FEATURE_OPAL)) { 424262af557SGuo Chao pr_info(" Firmware too old to support M64 window\n"); 425262af557SGuo Chao return; 426262af557SGuo Chao } 427262af557SGuo Chao 428262af557SGuo Chao r = of_get_property(dn, "ibm,opal-m64-window", NULL); 429262af557SGuo Chao if (!r) { 430262af557SGuo Chao pr_info(" No <ibm,opal-m64-window> on %s\n", 431262af557SGuo Chao dn->full_name); 432262af557SGuo Chao return; 433262af557SGuo Chao } 434262af557SGuo Chao 435262af557SGuo Chao res = &hose->mem_resources[1]; 436e80c4e7cSGavin Shan res->name = dn->full_name; 437262af557SGuo Chao res->start = of_translate_address(dn, r + 2); 438262af557SGuo Chao res->end = res->start + of_read_number(r + 4, 2) - 1; 439262af557SGuo Chao res->flags = (IORESOURCE_MEM | IORESOURCE_MEM_64 | IORESOURCE_PREFETCH); 440262af557SGuo Chao pci_addr = of_read_number(r, 2); 441262af557SGuo Chao hose->mem_offset[1] = res->start - pci_addr; 442262af557SGuo Chao 443262af557SGuo Chao phb->ioda.m64_size = resource_size(res); 44492b8f137SGavin Shan phb->ioda.m64_segsize = phb->ioda.m64_size / phb->ioda.total_pe_num; 445262af557SGuo Chao phb->ioda.m64_base = pci_addr; 446262af557SGuo Chao 447e9863e68SWei Yang pr_info(" MEM64 0x%016llx..0x%016llx -> 0x%016llx\n", 448e9863e68SWei Yang res->start, res->end, pci_addr); 449e9863e68SWei Yang 450262af557SGuo Chao /* Use last M64 BAR to cover M64 window */ 451262af557SGuo Chao phb->ioda.m64_bar_idx = 15; 45299451551SGavin Shan if (phb->type == PNV_PHB_IODA1) 45399451551SGavin Shan phb->init_m64 = pnv_ioda1_init_m64; 45499451551SGavin Shan else 455262af557SGuo Chao phb->init_m64 = pnv_ioda2_init_m64; 456c430670aSGavin Shan phb->reserve_m64_pe = pnv_ioda_reserve_m64_pe; 457c430670aSGavin Shan phb->pick_m64_pe = pnv_ioda_pick_m64_pe; 458262af557SGuo Chao } 459262af557SGuo Chao 46049dec922SGavin Shan static void pnv_ioda_freeze_pe(struct pnv_phb *phb, int pe_no) 46149dec922SGavin Shan { 46249dec922SGavin Shan struct pnv_ioda_pe *pe = &phb->ioda.pe_array[pe_no]; 46349dec922SGavin Shan struct pnv_ioda_pe *slave; 46449dec922SGavin Shan s64 rc; 46549dec922SGavin Shan 46649dec922SGavin Shan /* Fetch master PE */ 46749dec922SGavin Shan if (pe->flags & PNV_IODA_PE_SLAVE) { 46849dec922SGavin Shan pe = pe->master; 469ec8e4e9dSGavin Shan if (WARN_ON(!pe || !(pe->flags & PNV_IODA_PE_MASTER))) 470ec8e4e9dSGavin Shan return; 471ec8e4e9dSGavin Shan 47249dec922SGavin Shan pe_no = pe->pe_number; 47349dec922SGavin Shan } 47449dec922SGavin Shan 47549dec922SGavin Shan /* Freeze master PE */ 47649dec922SGavin Shan rc = opal_pci_eeh_freeze_set(phb->opal_id, 47749dec922SGavin Shan pe_no, 47849dec922SGavin Shan OPAL_EEH_ACTION_SET_FREEZE_ALL); 47949dec922SGavin Shan if (rc != OPAL_SUCCESS) { 48049dec922SGavin Shan pr_warn("%s: Failure %lld freezing PHB#%x-PE#%x\n", 48149dec922SGavin Shan __func__, rc, phb->hose->global_number, pe_no); 48249dec922SGavin Shan return; 48349dec922SGavin Shan } 48449dec922SGavin Shan 48549dec922SGavin Shan /* Freeze slave PEs */ 48649dec922SGavin Shan if (!(pe->flags & PNV_IODA_PE_MASTER)) 48749dec922SGavin Shan return; 48849dec922SGavin Shan 48949dec922SGavin Shan list_for_each_entry(slave, &pe->slaves, list) { 49049dec922SGavin Shan rc = opal_pci_eeh_freeze_set(phb->opal_id, 49149dec922SGavin Shan slave->pe_number, 49249dec922SGavin Shan OPAL_EEH_ACTION_SET_FREEZE_ALL); 49349dec922SGavin Shan if (rc != OPAL_SUCCESS) 49449dec922SGavin Shan pr_warn("%s: Failure %lld freezing PHB#%x-PE#%x\n", 49549dec922SGavin Shan __func__, rc, phb->hose->global_number, 49649dec922SGavin Shan slave->pe_number); 49749dec922SGavin Shan } 49849dec922SGavin Shan } 49949dec922SGavin Shan 500e51df2c1SAnton Blanchard static int pnv_ioda_unfreeze_pe(struct pnv_phb *phb, int pe_no, int opt) 50149dec922SGavin Shan { 50249dec922SGavin Shan struct pnv_ioda_pe *pe, *slave; 50349dec922SGavin Shan s64 rc; 50449dec922SGavin Shan 50549dec922SGavin Shan /* Find master PE */ 50649dec922SGavin Shan pe = &phb->ioda.pe_array[pe_no]; 50749dec922SGavin Shan if (pe->flags & PNV_IODA_PE_SLAVE) { 50849dec922SGavin Shan pe = pe->master; 50949dec922SGavin Shan WARN_ON(!pe || !(pe->flags & PNV_IODA_PE_MASTER)); 51049dec922SGavin Shan pe_no = pe->pe_number; 51149dec922SGavin Shan } 51249dec922SGavin Shan 51349dec922SGavin Shan /* Clear frozen state for master PE */ 51449dec922SGavin Shan rc = opal_pci_eeh_freeze_clear(phb->opal_id, pe_no, opt); 51549dec922SGavin Shan if (rc != OPAL_SUCCESS) { 51649dec922SGavin Shan pr_warn("%s: Failure %lld clear %d on PHB#%x-PE#%x\n", 51749dec922SGavin Shan __func__, rc, opt, phb->hose->global_number, pe_no); 51849dec922SGavin Shan return -EIO; 51949dec922SGavin Shan } 52049dec922SGavin Shan 52149dec922SGavin Shan if (!(pe->flags & PNV_IODA_PE_MASTER)) 52249dec922SGavin Shan return 0; 52349dec922SGavin Shan 52449dec922SGavin Shan /* Clear frozen state for slave PEs */ 52549dec922SGavin Shan list_for_each_entry(slave, &pe->slaves, list) { 52649dec922SGavin Shan rc = opal_pci_eeh_freeze_clear(phb->opal_id, 52749dec922SGavin Shan slave->pe_number, 52849dec922SGavin Shan opt); 52949dec922SGavin Shan if (rc != OPAL_SUCCESS) { 53049dec922SGavin Shan pr_warn("%s: Failure %lld clear %d on PHB#%x-PE#%x\n", 53149dec922SGavin Shan __func__, rc, opt, phb->hose->global_number, 53249dec922SGavin Shan slave->pe_number); 53349dec922SGavin Shan return -EIO; 53449dec922SGavin Shan } 53549dec922SGavin Shan } 53649dec922SGavin Shan 53749dec922SGavin Shan return 0; 53849dec922SGavin Shan } 53949dec922SGavin Shan 54049dec922SGavin Shan static int pnv_ioda_get_pe_state(struct pnv_phb *phb, int pe_no) 54149dec922SGavin Shan { 54249dec922SGavin Shan struct pnv_ioda_pe *slave, *pe; 54349dec922SGavin Shan u8 fstate, state; 54449dec922SGavin Shan __be16 pcierr; 54549dec922SGavin Shan s64 rc; 54649dec922SGavin Shan 54749dec922SGavin Shan /* Sanity check on PE number */ 54892b8f137SGavin Shan if (pe_no < 0 || pe_no >= phb->ioda.total_pe_num) 54949dec922SGavin Shan return OPAL_EEH_STOPPED_PERM_UNAVAIL; 55049dec922SGavin Shan 55149dec922SGavin Shan /* 55249dec922SGavin Shan * Fetch the master PE and the PE instance might be 55349dec922SGavin Shan * not initialized yet. 55449dec922SGavin Shan */ 55549dec922SGavin Shan pe = &phb->ioda.pe_array[pe_no]; 55649dec922SGavin Shan if (pe->flags & PNV_IODA_PE_SLAVE) { 55749dec922SGavin Shan pe = pe->master; 55849dec922SGavin Shan WARN_ON(!pe || !(pe->flags & PNV_IODA_PE_MASTER)); 55949dec922SGavin Shan pe_no = pe->pe_number; 56049dec922SGavin Shan } 56149dec922SGavin Shan 56249dec922SGavin Shan /* Check the master PE */ 56349dec922SGavin Shan rc = opal_pci_eeh_freeze_status(phb->opal_id, pe_no, 56449dec922SGavin Shan &state, &pcierr, NULL); 56549dec922SGavin Shan if (rc != OPAL_SUCCESS) { 56649dec922SGavin Shan pr_warn("%s: Failure %lld getting " 56749dec922SGavin Shan "PHB#%x-PE#%x state\n", 56849dec922SGavin Shan __func__, rc, 56949dec922SGavin Shan phb->hose->global_number, pe_no); 57049dec922SGavin Shan return OPAL_EEH_STOPPED_TEMP_UNAVAIL; 57149dec922SGavin Shan } 57249dec922SGavin Shan 57349dec922SGavin Shan /* Check the slave PE */ 57449dec922SGavin Shan if (!(pe->flags & PNV_IODA_PE_MASTER)) 57549dec922SGavin Shan return state; 57649dec922SGavin Shan 57749dec922SGavin Shan list_for_each_entry(slave, &pe->slaves, list) { 57849dec922SGavin Shan rc = opal_pci_eeh_freeze_status(phb->opal_id, 57949dec922SGavin Shan slave->pe_number, 58049dec922SGavin Shan &fstate, 58149dec922SGavin Shan &pcierr, 58249dec922SGavin Shan NULL); 58349dec922SGavin Shan if (rc != OPAL_SUCCESS) { 58449dec922SGavin Shan pr_warn("%s: Failure %lld getting " 58549dec922SGavin Shan "PHB#%x-PE#%x state\n", 58649dec922SGavin Shan __func__, rc, 58749dec922SGavin Shan phb->hose->global_number, slave->pe_number); 58849dec922SGavin Shan return OPAL_EEH_STOPPED_TEMP_UNAVAIL; 58949dec922SGavin Shan } 59049dec922SGavin Shan 59149dec922SGavin Shan /* 59249dec922SGavin Shan * Override the result based on the ascending 59349dec922SGavin Shan * priority. 59449dec922SGavin Shan */ 59549dec922SGavin Shan if (fstate > state) 59649dec922SGavin Shan state = fstate; 59749dec922SGavin Shan } 59849dec922SGavin Shan 59949dec922SGavin Shan return state; 60049dec922SGavin Shan } 60149dec922SGavin Shan 602184cd4a3SBenjamin Herrenschmidt /* Currently those 2 are only used when MSIs are enabled, this will change 603184cd4a3SBenjamin Herrenschmidt * but in the meantime, we need to protect them to avoid warnings 604184cd4a3SBenjamin Herrenschmidt */ 605184cd4a3SBenjamin Herrenschmidt #ifdef CONFIG_PCI_MSI 606cad5cef6SGreg Kroah-Hartman static struct pnv_ioda_pe *pnv_ioda_get_pe(struct pci_dev *dev) 607184cd4a3SBenjamin Herrenschmidt { 608184cd4a3SBenjamin Herrenschmidt struct pci_controller *hose = pci_bus_to_host(dev->bus); 609184cd4a3SBenjamin Herrenschmidt struct pnv_phb *phb = hose->private_data; 610b72c1f65SBenjamin Herrenschmidt struct pci_dn *pdn = pci_get_pdn(dev); 611184cd4a3SBenjamin Herrenschmidt 612184cd4a3SBenjamin Herrenschmidt if (!pdn) 613184cd4a3SBenjamin Herrenschmidt return NULL; 614184cd4a3SBenjamin Herrenschmidt if (pdn->pe_number == IODA_INVALID_PE) 615184cd4a3SBenjamin Herrenschmidt return NULL; 616184cd4a3SBenjamin Herrenschmidt return &phb->ioda.pe_array[pdn->pe_number]; 617184cd4a3SBenjamin Herrenschmidt } 618184cd4a3SBenjamin Herrenschmidt #endif /* CONFIG_PCI_MSI */ 619184cd4a3SBenjamin Herrenschmidt 620b131a842SGavin Shan static int pnv_ioda_set_one_peltv(struct pnv_phb *phb, 621b131a842SGavin Shan struct pnv_ioda_pe *parent, 622b131a842SGavin Shan struct pnv_ioda_pe *child, 623b131a842SGavin Shan bool is_add) 624b131a842SGavin Shan { 625b131a842SGavin Shan const char *desc = is_add ? "adding" : "removing"; 626b131a842SGavin Shan uint8_t op = is_add ? OPAL_ADD_PE_TO_DOMAIN : 627b131a842SGavin Shan OPAL_REMOVE_PE_FROM_DOMAIN; 628b131a842SGavin Shan struct pnv_ioda_pe *slave; 629b131a842SGavin Shan long rc; 630b131a842SGavin Shan 631b131a842SGavin Shan /* Parent PE affects child PE */ 632b131a842SGavin Shan rc = opal_pci_set_peltv(phb->opal_id, parent->pe_number, 633b131a842SGavin Shan child->pe_number, op); 634b131a842SGavin Shan if (rc != OPAL_SUCCESS) { 635b131a842SGavin Shan pe_warn(child, "OPAL error %ld %s to parent PELTV\n", 636b131a842SGavin Shan rc, desc); 637b131a842SGavin Shan return -ENXIO; 638b131a842SGavin Shan } 639b131a842SGavin Shan 640b131a842SGavin Shan if (!(child->flags & PNV_IODA_PE_MASTER)) 641b131a842SGavin Shan return 0; 642b131a842SGavin Shan 643b131a842SGavin Shan /* Compound case: parent PE affects slave PEs */ 644b131a842SGavin Shan list_for_each_entry(slave, &child->slaves, list) { 645b131a842SGavin Shan rc = opal_pci_set_peltv(phb->opal_id, parent->pe_number, 646b131a842SGavin Shan slave->pe_number, op); 647b131a842SGavin Shan if (rc != OPAL_SUCCESS) { 648b131a842SGavin Shan pe_warn(slave, "OPAL error %ld %s to parent PELTV\n", 649b131a842SGavin Shan rc, desc); 650b131a842SGavin Shan return -ENXIO; 651b131a842SGavin Shan } 652b131a842SGavin Shan } 653b131a842SGavin Shan 654b131a842SGavin Shan return 0; 655b131a842SGavin Shan } 656b131a842SGavin Shan 657b131a842SGavin Shan static int pnv_ioda_set_peltv(struct pnv_phb *phb, 658b131a842SGavin Shan struct pnv_ioda_pe *pe, 659b131a842SGavin Shan bool is_add) 660b131a842SGavin Shan { 661b131a842SGavin Shan struct pnv_ioda_pe *slave; 662781a868fSWei Yang struct pci_dev *pdev = NULL; 663b131a842SGavin Shan int ret; 664b131a842SGavin Shan 665b131a842SGavin Shan /* 666b131a842SGavin Shan * Clear PE frozen state. If it's master PE, we need 667b131a842SGavin Shan * clear slave PE frozen state as well. 668b131a842SGavin Shan */ 669b131a842SGavin Shan if (is_add) { 670b131a842SGavin Shan opal_pci_eeh_freeze_clear(phb->opal_id, pe->pe_number, 671b131a842SGavin Shan OPAL_EEH_ACTION_CLEAR_FREEZE_ALL); 672b131a842SGavin Shan if (pe->flags & PNV_IODA_PE_MASTER) { 673b131a842SGavin Shan list_for_each_entry(slave, &pe->slaves, list) 674b131a842SGavin Shan opal_pci_eeh_freeze_clear(phb->opal_id, 675b131a842SGavin Shan slave->pe_number, 676b131a842SGavin Shan OPAL_EEH_ACTION_CLEAR_FREEZE_ALL); 677b131a842SGavin Shan } 678b131a842SGavin Shan } 679b131a842SGavin Shan 680b131a842SGavin Shan /* 681b131a842SGavin Shan * Associate PE in PELT. We need add the PE into the 682b131a842SGavin Shan * corresponding PELT-V as well. Otherwise, the error 683b131a842SGavin Shan * originated from the PE might contribute to other 684b131a842SGavin Shan * PEs. 685b131a842SGavin Shan */ 686b131a842SGavin Shan ret = pnv_ioda_set_one_peltv(phb, pe, pe, is_add); 687b131a842SGavin Shan if (ret) 688b131a842SGavin Shan return ret; 689b131a842SGavin Shan 690b131a842SGavin Shan /* For compound PEs, any one affects all of them */ 691b131a842SGavin Shan if (pe->flags & PNV_IODA_PE_MASTER) { 692b131a842SGavin Shan list_for_each_entry(slave, &pe->slaves, list) { 693b131a842SGavin Shan ret = pnv_ioda_set_one_peltv(phb, slave, pe, is_add); 694b131a842SGavin Shan if (ret) 695b131a842SGavin Shan return ret; 696b131a842SGavin Shan } 697b131a842SGavin Shan } 698b131a842SGavin Shan 699b131a842SGavin Shan if (pe->flags & (PNV_IODA_PE_BUS_ALL | PNV_IODA_PE_BUS)) 700b131a842SGavin Shan pdev = pe->pbus->self; 701781a868fSWei Yang else if (pe->flags & PNV_IODA_PE_DEV) 702b131a842SGavin Shan pdev = pe->pdev->bus->self; 703781a868fSWei Yang #ifdef CONFIG_PCI_IOV 704781a868fSWei Yang else if (pe->flags & PNV_IODA_PE_VF) 705283e2d8aSGavin Shan pdev = pe->parent_dev; 706781a868fSWei Yang #endif /* CONFIG_PCI_IOV */ 707b131a842SGavin Shan while (pdev) { 708b131a842SGavin Shan struct pci_dn *pdn = pci_get_pdn(pdev); 709b131a842SGavin Shan struct pnv_ioda_pe *parent; 710b131a842SGavin Shan 711b131a842SGavin Shan if (pdn && pdn->pe_number != IODA_INVALID_PE) { 712b131a842SGavin Shan parent = &phb->ioda.pe_array[pdn->pe_number]; 713b131a842SGavin Shan ret = pnv_ioda_set_one_peltv(phb, parent, pe, is_add); 714b131a842SGavin Shan if (ret) 715b131a842SGavin Shan return ret; 716b131a842SGavin Shan } 717b131a842SGavin Shan 718b131a842SGavin Shan pdev = pdev->bus->self; 719b131a842SGavin Shan } 720b131a842SGavin Shan 721b131a842SGavin Shan return 0; 722b131a842SGavin Shan } 723b131a842SGavin Shan 724781a868fSWei Yang #ifdef CONFIG_PCI_IOV 725781a868fSWei Yang static int pnv_ioda_deconfigure_pe(struct pnv_phb *phb, struct pnv_ioda_pe *pe) 726781a868fSWei Yang { 727781a868fSWei Yang struct pci_dev *parent; 728781a868fSWei Yang uint8_t bcomp, dcomp, fcomp; 729781a868fSWei Yang int64_t rc; 730781a868fSWei Yang long rid_end, rid; 731781a868fSWei Yang 732781a868fSWei Yang /* Currently, we just deconfigure VF PE. Bus PE will always there.*/ 733781a868fSWei Yang if (pe->pbus) { 734781a868fSWei Yang int count; 735781a868fSWei Yang 736781a868fSWei Yang dcomp = OPAL_IGNORE_RID_DEVICE_NUMBER; 737781a868fSWei Yang fcomp = OPAL_IGNORE_RID_FUNCTION_NUMBER; 738781a868fSWei Yang parent = pe->pbus->self; 739781a868fSWei Yang if (pe->flags & PNV_IODA_PE_BUS_ALL) 740781a868fSWei Yang count = pe->pbus->busn_res.end - pe->pbus->busn_res.start + 1; 741781a868fSWei Yang else 742781a868fSWei Yang count = 1; 743781a868fSWei Yang 744781a868fSWei Yang switch(count) { 745781a868fSWei Yang case 1: bcomp = OpalPciBusAll; break; 746781a868fSWei Yang case 2: bcomp = OpalPciBus7Bits; break; 747781a868fSWei Yang case 4: bcomp = OpalPciBus6Bits; break; 748781a868fSWei Yang case 8: bcomp = OpalPciBus5Bits; break; 749781a868fSWei Yang case 16: bcomp = OpalPciBus4Bits; break; 750781a868fSWei Yang case 32: bcomp = OpalPciBus3Bits; break; 751781a868fSWei Yang default: 752781a868fSWei Yang dev_err(&pe->pbus->dev, "Number of subordinate buses %d unsupported\n", 753781a868fSWei Yang count); 754781a868fSWei Yang /* Do an exact match only */ 755781a868fSWei Yang bcomp = OpalPciBusAll; 756781a868fSWei Yang } 757781a868fSWei Yang rid_end = pe->rid + (count << 8); 758781a868fSWei Yang } else { 759781a868fSWei Yang if (pe->flags & PNV_IODA_PE_VF) 760781a868fSWei Yang parent = pe->parent_dev; 761781a868fSWei Yang else 762781a868fSWei Yang parent = pe->pdev->bus->self; 763781a868fSWei Yang bcomp = OpalPciBusAll; 764781a868fSWei Yang dcomp = OPAL_COMPARE_RID_DEVICE_NUMBER; 765781a868fSWei Yang fcomp = OPAL_COMPARE_RID_FUNCTION_NUMBER; 766781a868fSWei Yang rid_end = pe->rid + 1; 767781a868fSWei Yang } 768781a868fSWei Yang 769781a868fSWei Yang /* Clear the reverse map */ 770781a868fSWei Yang for (rid = pe->rid; rid < rid_end; rid++) 771781a868fSWei Yang phb->ioda.pe_rmap[rid] = 0; 772781a868fSWei Yang 773781a868fSWei Yang /* Release from all parents PELT-V */ 774781a868fSWei Yang while (parent) { 775781a868fSWei Yang struct pci_dn *pdn = pci_get_pdn(parent); 776781a868fSWei Yang if (pdn && pdn->pe_number != IODA_INVALID_PE) { 777781a868fSWei Yang rc = opal_pci_set_peltv(phb->opal_id, pdn->pe_number, 778781a868fSWei Yang pe->pe_number, OPAL_REMOVE_PE_FROM_DOMAIN); 779781a868fSWei Yang /* XXX What to do in case of error ? */ 780781a868fSWei Yang } 781781a868fSWei Yang parent = parent->bus->self; 782781a868fSWei Yang } 783781a868fSWei Yang 784f951e510SGavin Shan opal_pci_eeh_freeze_clear(phb->opal_id, pe->pe_number, 785781a868fSWei Yang OPAL_EEH_ACTION_CLEAR_FREEZE_ALL); 786781a868fSWei Yang 787781a868fSWei Yang /* Disassociate PE in PELT */ 788781a868fSWei Yang rc = opal_pci_set_peltv(phb->opal_id, pe->pe_number, 789781a868fSWei Yang pe->pe_number, OPAL_REMOVE_PE_FROM_DOMAIN); 790781a868fSWei Yang if (rc) 791781a868fSWei Yang pe_warn(pe, "OPAL error %ld remove self from PELTV\n", rc); 792781a868fSWei Yang rc = opal_pci_set_pe(phb->opal_id, pe->pe_number, pe->rid, 793781a868fSWei Yang bcomp, dcomp, fcomp, OPAL_UNMAP_PE); 794781a868fSWei Yang if (rc) 795781a868fSWei Yang pe_err(pe, "OPAL error %ld trying to setup PELT table\n", rc); 796781a868fSWei Yang 797781a868fSWei Yang pe->pbus = NULL; 798781a868fSWei Yang pe->pdev = NULL; 799781a868fSWei Yang pe->parent_dev = NULL; 800781a868fSWei Yang 801781a868fSWei Yang return 0; 802781a868fSWei Yang } 803781a868fSWei Yang #endif /* CONFIG_PCI_IOV */ 804781a868fSWei Yang 805cad5cef6SGreg Kroah-Hartman static int pnv_ioda_configure_pe(struct pnv_phb *phb, struct pnv_ioda_pe *pe) 806184cd4a3SBenjamin Herrenschmidt { 807184cd4a3SBenjamin Herrenschmidt struct pci_dev *parent; 808184cd4a3SBenjamin Herrenschmidt uint8_t bcomp, dcomp, fcomp; 809184cd4a3SBenjamin Herrenschmidt long rc, rid_end, rid; 810184cd4a3SBenjamin Herrenschmidt 811184cd4a3SBenjamin Herrenschmidt /* Bus validation ? */ 812184cd4a3SBenjamin Herrenschmidt if (pe->pbus) { 813184cd4a3SBenjamin Herrenschmidt int count; 814184cd4a3SBenjamin Herrenschmidt 815184cd4a3SBenjamin Herrenschmidt dcomp = OPAL_IGNORE_RID_DEVICE_NUMBER; 816184cd4a3SBenjamin Herrenschmidt fcomp = OPAL_IGNORE_RID_FUNCTION_NUMBER; 817184cd4a3SBenjamin Herrenschmidt parent = pe->pbus->self; 818fb446ad0SGavin Shan if (pe->flags & PNV_IODA_PE_BUS_ALL) 819b918c62eSYinghai Lu count = pe->pbus->busn_res.end - pe->pbus->busn_res.start + 1; 820fb446ad0SGavin Shan else 821fb446ad0SGavin Shan count = 1; 822fb446ad0SGavin Shan 823184cd4a3SBenjamin Herrenschmidt switch(count) { 824184cd4a3SBenjamin Herrenschmidt case 1: bcomp = OpalPciBusAll; break; 825184cd4a3SBenjamin Herrenschmidt case 2: bcomp = OpalPciBus7Bits; break; 826184cd4a3SBenjamin Herrenschmidt case 4: bcomp = OpalPciBus6Bits; break; 827184cd4a3SBenjamin Herrenschmidt case 8: bcomp = OpalPciBus5Bits; break; 828184cd4a3SBenjamin Herrenschmidt case 16: bcomp = OpalPciBus4Bits; break; 829184cd4a3SBenjamin Herrenschmidt case 32: bcomp = OpalPciBus3Bits; break; 830184cd4a3SBenjamin Herrenschmidt default: 831781a868fSWei Yang dev_err(&pe->pbus->dev, "Number of subordinate buses %d unsupported\n", 832781a868fSWei Yang count); 833184cd4a3SBenjamin Herrenschmidt /* Do an exact match only */ 834184cd4a3SBenjamin Herrenschmidt bcomp = OpalPciBusAll; 835184cd4a3SBenjamin Herrenschmidt } 836184cd4a3SBenjamin Herrenschmidt rid_end = pe->rid + (count << 8); 837184cd4a3SBenjamin Herrenschmidt } else { 838781a868fSWei Yang #ifdef CONFIG_PCI_IOV 839781a868fSWei Yang if (pe->flags & PNV_IODA_PE_VF) 840781a868fSWei Yang parent = pe->parent_dev; 841781a868fSWei Yang else 842781a868fSWei Yang #endif /* CONFIG_PCI_IOV */ 843184cd4a3SBenjamin Herrenschmidt parent = pe->pdev->bus->self; 844184cd4a3SBenjamin Herrenschmidt bcomp = OpalPciBusAll; 845184cd4a3SBenjamin Herrenschmidt dcomp = OPAL_COMPARE_RID_DEVICE_NUMBER; 846184cd4a3SBenjamin Herrenschmidt fcomp = OPAL_COMPARE_RID_FUNCTION_NUMBER; 847184cd4a3SBenjamin Herrenschmidt rid_end = pe->rid + 1; 848184cd4a3SBenjamin Herrenschmidt } 849184cd4a3SBenjamin Herrenschmidt 850631ad691SGavin Shan /* 851631ad691SGavin Shan * Associate PE in PELT. We need add the PE into the 852631ad691SGavin Shan * corresponding PELT-V as well. Otherwise, the error 853631ad691SGavin Shan * originated from the PE might contribute to other 854631ad691SGavin Shan * PEs. 855631ad691SGavin Shan */ 856184cd4a3SBenjamin Herrenschmidt rc = opal_pci_set_pe(phb->opal_id, pe->pe_number, pe->rid, 857184cd4a3SBenjamin Herrenschmidt bcomp, dcomp, fcomp, OPAL_MAP_PE); 858184cd4a3SBenjamin Herrenschmidt if (rc) { 859184cd4a3SBenjamin Herrenschmidt pe_err(pe, "OPAL error %ld trying to setup PELT table\n", rc); 860184cd4a3SBenjamin Herrenschmidt return -ENXIO; 861184cd4a3SBenjamin Herrenschmidt } 862631ad691SGavin Shan 8635d2aa710SAlistair Popple /* 8645d2aa710SAlistair Popple * Configure PELTV. NPUs don't have a PELTV table so skip 8655d2aa710SAlistair Popple * configuration on them. 8665d2aa710SAlistair Popple */ 8675d2aa710SAlistair Popple if (phb->type != PNV_PHB_NPU) 868b131a842SGavin Shan pnv_ioda_set_peltv(phb, pe, true); 869184cd4a3SBenjamin Herrenschmidt 870184cd4a3SBenjamin Herrenschmidt /* Setup reverse map */ 871184cd4a3SBenjamin Herrenschmidt for (rid = pe->rid; rid < rid_end; rid++) 872184cd4a3SBenjamin Herrenschmidt phb->ioda.pe_rmap[rid] = pe->pe_number; 873184cd4a3SBenjamin Herrenschmidt 874184cd4a3SBenjamin Herrenschmidt /* Setup one MVTs on IODA1 */ 8754773f76bSGavin Shan if (phb->type != PNV_PHB_IODA1) { 8764773f76bSGavin Shan pe->mve_number = 0; 8774773f76bSGavin Shan goto out; 8784773f76bSGavin Shan } 8794773f76bSGavin Shan 880184cd4a3SBenjamin Herrenschmidt pe->mve_number = pe->pe_number; 8814773f76bSGavin Shan rc = opal_pci_set_mve(phb->opal_id, pe->mve_number, pe->pe_number); 8824773f76bSGavin Shan if (rc != OPAL_SUCCESS) { 883184cd4a3SBenjamin Herrenschmidt pe_err(pe, "OPAL error %ld setting up MVE %d\n", 884184cd4a3SBenjamin Herrenschmidt rc, pe->mve_number); 885184cd4a3SBenjamin Herrenschmidt pe->mve_number = -1; 886184cd4a3SBenjamin Herrenschmidt } else { 887184cd4a3SBenjamin Herrenschmidt rc = opal_pci_set_mve_enable(phb->opal_id, 888cee72d5bSBenjamin Herrenschmidt pe->mve_number, OPAL_ENABLE_MVE); 889184cd4a3SBenjamin Herrenschmidt if (rc) { 890184cd4a3SBenjamin Herrenschmidt pe_err(pe, "OPAL error %ld enabling MVE %d\n", 891184cd4a3SBenjamin Herrenschmidt rc, pe->mve_number); 892184cd4a3SBenjamin Herrenschmidt pe->mve_number = -1; 893184cd4a3SBenjamin Herrenschmidt } 894184cd4a3SBenjamin Herrenschmidt } 895184cd4a3SBenjamin Herrenschmidt 8964773f76bSGavin Shan out: 897184cd4a3SBenjamin Herrenschmidt return 0; 898184cd4a3SBenjamin Herrenschmidt } 899184cd4a3SBenjamin Herrenschmidt 900781a868fSWei Yang #ifdef CONFIG_PCI_IOV 901781a868fSWei Yang static int pnv_pci_vf_resource_shift(struct pci_dev *dev, int offset) 902781a868fSWei Yang { 903781a868fSWei Yang struct pci_dn *pdn = pci_get_pdn(dev); 904781a868fSWei Yang int i; 905781a868fSWei Yang struct resource *res, res2; 906781a868fSWei Yang resource_size_t size; 907781a868fSWei Yang u16 num_vfs; 908781a868fSWei Yang 909781a868fSWei Yang if (!dev->is_physfn) 910781a868fSWei Yang return -EINVAL; 911781a868fSWei Yang 912781a868fSWei Yang /* 913781a868fSWei Yang * "offset" is in VFs. The M64 windows are sized so that when they 914781a868fSWei Yang * are segmented, each segment is the same size as the IOV BAR. 915781a868fSWei Yang * Each segment is in a separate PE, and the high order bits of the 916781a868fSWei Yang * address are the PE number. Therefore, each VF's BAR is in a 917781a868fSWei Yang * separate PE, and changing the IOV BAR start address changes the 918781a868fSWei Yang * range of PEs the VFs are in. 919781a868fSWei Yang */ 920781a868fSWei Yang num_vfs = pdn->num_vfs; 921781a868fSWei Yang for (i = 0; i < PCI_SRIOV_NUM_BARS; i++) { 922781a868fSWei Yang res = &dev->resource[i + PCI_IOV_RESOURCES]; 923781a868fSWei Yang if (!res->flags || !res->parent) 924781a868fSWei Yang continue; 925781a868fSWei Yang 926781a868fSWei Yang /* 927781a868fSWei Yang * The actual IOV BAR range is determined by the start address 928781a868fSWei Yang * and the actual size for num_vfs VFs BAR. This check is to 929781a868fSWei Yang * make sure that after shifting, the range will not overlap 930781a868fSWei Yang * with another device. 931781a868fSWei Yang */ 932781a868fSWei Yang size = pci_iov_resource_size(dev, i + PCI_IOV_RESOURCES); 933781a868fSWei Yang res2.flags = res->flags; 934781a868fSWei Yang res2.start = res->start + (size * offset); 935781a868fSWei Yang res2.end = res2.start + (size * num_vfs) - 1; 936781a868fSWei Yang 937781a868fSWei Yang if (res2.end > res->end) { 938781a868fSWei Yang dev_err(&dev->dev, "VF BAR%d: %pR would extend past %pR (trying to enable %d VFs shifted by %d)\n", 939781a868fSWei Yang i, &res2, res, num_vfs, offset); 940781a868fSWei Yang return -EBUSY; 941781a868fSWei Yang } 942781a868fSWei Yang } 943781a868fSWei Yang 944781a868fSWei Yang /* 945781a868fSWei Yang * After doing so, there would be a "hole" in the /proc/iomem when 946781a868fSWei Yang * offset is a positive value. It looks like the device return some 947781a868fSWei Yang * mmio back to the system, which actually no one could use it. 948781a868fSWei Yang */ 949781a868fSWei Yang for (i = 0; i < PCI_SRIOV_NUM_BARS; i++) { 950781a868fSWei Yang res = &dev->resource[i + PCI_IOV_RESOURCES]; 951781a868fSWei Yang if (!res->flags || !res->parent) 952781a868fSWei Yang continue; 953781a868fSWei Yang 954781a868fSWei Yang size = pci_iov_resource_size(dev, i + PCI_IOV_RESOURCES); 955781a868fSWei Yang res2 = *res; 956781a868fSWei Yang res->start += size * offset; 957781a868fSWei Yang 95874703cc4SWei Yang dev_info(&dev->dev, "VF BAR%d: %pR shifted to %pR (%sabling %d VFs shifted by %d)\n", 95974703cc4SWei Yang i, &res2, res, (offset > 0) ? "En" : "Dis", 96074703cc4SWei Yang num_vfs, offset); 961781a868fSWei Yang pci_update_resource(dev, i + PCI_IOV_RESOURCES); 962781a868fSWei Yang } 963781a868fSWei Yang return 0; 964781a868fSWei Yang } 965781a868fSWei Yang #endif /* CONFIG_PCI_IOV */ 966781a868fSWei Yang 967cad5cef6SGreg Kroah-Hartman static struct pnv_ioda_pe *pnv_ioda_setup_dev_PE(struct pci_dev *dev) 968184cd4a3SBenjamin Herrenschmidt { 969184cd4a3SBenjamin Herrenschmidt struct pci_controller *hose = pci_bus_to_host(dev->bus); 970184cd4a3SBenjamin Herrenschmidt struct pnv_phb *phb = hose->private_data; 971b72c1f65SBenjamin Herrenschmidt struct pci_dn *pdn = pci_get_pdn(dev); 972184cd4a3SBenjamin Herrenschmidt struct pnv_ioda_pe *pe; 973184cd4a3SBenjamin Herrenschmidt 974184cd4a3SBenjamin Herrenschmidt if (!pdn) { 975184cd4a3SBenjamin Herrenschmidt pr_err("%s: Device tree node not associated properly\n", 976184cd4a3SBenjamin Herrenschmidt pci_name(dev)); 977184cd4a3SBenjamin Herrenschmidt return NULL; 978184cd4a3SBenjamin Herrenschmidt } 979184cd4a3SBenjamin Herrenschmidt if (pdn->pe_number != IODA_INVALID_PE) 980184cd4a3SBenjamin Herrenschmidt return NULL; 981184cd4a3SBenjamin Herrenschmidt 9821e916772SGavin Shan pe = pnv_ioda_alloc_pe(phb); 9831e916772SGavin Shan if (!pe) { 984184cd4a3SBenjamin Herrenschmidt pr_warning("%s: Not enough PE# available, disabling device\n", 985184cd4a3SBenjamin Herrenschmidt pci_name(dev)); 986184cd4a3SBenjamin Herrenschmidt return NULL; 987184cd4a3SBenjamin Herrenschmidt } 988184cd4a3SBenjamin Herrenschmidt 989184cd4a3SBenjamin Herrenschmidt /* NOTE: We get only one ref to the pci_dev for the pdn, not for the 990184cd4a3SBenjamin Herrenschmidt * pointer in the PE data structure, both should be destroyed at the 991184cd4a3SBenjamin Herrenschmidt * same time. However, this needs to be looked at more closely again 992184cd4a3SBenjamin Herrenschmidt * once we actually start removing things (Hotplug, SR-IOV, ...) 993184cd4a3SBenjamin Herrenschmidt * 994184cd4a3SBenjamin Herrenschmidt * At some point we want to remove the PDN completely anyways 995184cd4a3SBenjamin Herrenschmidt */ 996184cd4a3SBenjamin Herrenschmidt pci_dev_get(dev); 997184cd4a3SBenjamin Herrenschmidt pdn->pcidev = dev; 9981e916772SGavin Shan pdn->pe_number = pe->pe_number; 9995d2aa710SAlistair Popple pe->flags = PNV_IODA_PE_DEV; 1000184cd4a3SBenjamin Herrenschmidt pe->pdev = dev; 1001184cd4a3SBenjamin Herrenschmidt pe->pbus = NULL; 1002184cd4a3SBenjamin Herrenschmidt pe->mve_number = -1; 1003184cd4a3SBenjamin Herrenschmidt pe->rid = dev->bus->number << 8 | pdn->devfn; 1004184cd4a3SBenjamin Herrenschmidt 1005184cd4a3SBenjamin Herrenschmidt pe_info(pe, "Associated device to PE\n"); 1006184cd4a3SBenjamin Herrenschmidt 1007184cd4a3SBenjamin Herrenschmidt if (pnv_ioda_configure_pe(phb, pe)) { 1008184cd4a3SBenjamin Herrenschmidt /* XXX What do we do here ? */ 10091e916772SGavin Shan pnv_ioda_free_pe(pe); 1010184cd4a3SBenjamin Herrenschmidt pdn->pe_number = IODA_INVALID_PE; 1011184cd4a3SBenjamin Herrenschmidt pe->pdev = NULL; 1012184cd4a3SBenjamin Herrenschmidt pci_dev_put(dev); 1013184cd4a3SBenjamin Herrenschmidt return NULL; 1014184cd4a3SBenjamin Herrenschmidt } 1015184cd4a3SBenjamin Herrenschmidt 1016184cd4a3SBenjamin Herrenschmidt return pe; 1017184cd4a3SBenjamin Herrenschmidt } 1018184cd4a3SBenjamin Herrenschmidt 1019184cd4a3SBenjamin Herrenschmidt static void pnv_ioda_setup_same_PE(struct pci_bus *bus, struct pnv_ioda_pe *pe) 1020184cd4a3SBenjamin Herrenschmidt { 1021184cd4a3SBenjamin Herrenschmidt struct pci_dev *dev; 1022184cd4a3SBenjamin Herrenschmidt 1023184cd4a3SBenjamin Herrenschmidt list_for_each_entry(dev, &bus->devices, bus_list) { 1024b72c1f65SBenjamin Herrenschmidt struct pci_dn *pdn = pci_get_pdn(dev); 1025184cd4a3SBenjamin Herrenschmidt 1026184cd4a3SBenjamin Herrenschmidt if (pdn == NULL) { 1027184cd4a3SBenjamin Herrenschmidt pr_warn("%s: No device node associated with device !\n", 1028184cd4a3SBenjamin Herrenschmidt pci_name(dev)); 1029184cd4a3SBenjamin Herrenschmidt continue; 1030184cd4a3SBenjamin Herrenschmidt } 103194973b24SAlistair Popple pdn->pcidev = dev; 1032184cd4a3SBenjamin Herrenschmidt pdn->pe_number = pe->pe_number; 1033fb446ad0SGavin Shan if ((pe->flags & PNV_IODA_PE_BUS_ALL) && dev->subordinate) 1034184cd4a3SBenjamin Herrenschmidt pnv_ioda_setup_same_PE(dev->subordinate, pe); 1035184cd4a3SBenjamin Herrenschmidt } 1036184cd4a3SBenjamin Herrenschmidt } 1037184cd4a3SBenjamin Herrenschmidt 1038fb446ad0SGavin Shan /* 1039fb446ad0SGavin Shan * There're 2 types of PCI bus sensitive PEs: One that is compromised of 1040fb446ad0SGavin Shan * single PCI bus. Another one that contains the primary PCI bus and its 1041fb446ad0SGavin Shan * subordinate PCI devices and buses. The second type of PE is normally 1042fb446ad0SGavin Shan * orgiriated by PCIe-to-PCI bridge or PLX switch downstream ports. 1043fb446ad0SGavin Shan */ 10441e916772SGavin Shan static struct pnv_ioda_pe *pnv_ioda_setup_bus_PE(struct pci_bus *bus, bool all) 1045184cd4a3SBenjamin Herrenschmidt { 1046fb446ad0SGavin Shan struct pci_controller *hose = pci_bus_to_host(bus); 1047184cd4a3SBenjamin Herrenschmidt struct pnv_phb *phb = hose->private_data; 10481e916772SGavin Shan struct pnv_ioda_pe *pe = NULL; 1049184cd4a3SBenjamin Herrenschmidt 1050262af557SGuo Chao /* Check if PE is determined by M64 */ 1051262af557SGuo Chao if (phb->pick_m64_pe) 10521e916772SGavin Shan pe = phb->pick_m64_pe(bus, all); 1053262af557SGuo Chao 1054262af557SGuo Chao /* The PE number isn't pinned by M64 */ 10551e916772SGavin Shan if (!pe) 10561e916772SGavin Shan pe = pnv_ioda_alloc_pe(phb); 1057262af557SGuo Chao 10581e916772SGavin Shan if (!pe) { 1059fb446ad0SGavin Shan pr_warning("%s: Not enough PE# available for PCI bus %04x:%02x\n", 1060fb446ad0SGavin Shan __func__, pci_domain_nr(bus), bus->number); 10611e916772SGavin Shan return NULL; 1062184cd4a3SBenjamin Herrenschmidt } 1063184cd4a3SBenjamin Herrenschmidt 1064262af557SGuo Chao pe->flags |= (all ? PNV_IODA_PE_BUS_ALL : PNV_IODA_PE_BUS); 1065184cd4a3SBenjamin Herrenschmidt pe->pbus = bus; 1066184cd4a3SBenjamin Herrenschmidt pe->pdev = NULL; 1067184cd4a3SBenjamin Herrenschmidt pe->mve_number = -1; 1068b918c62eSYinghai Lu pe->rid = bus->busn_res.start << 8; 1069184cd4a3SBenjamin Herrenschmidt 1070fb446ad0SGavin Shan if (all) 1071fb446ad0SGavin Shan pe_info(pe, "Secondary bus %d..%d associated with PE#%d\n", 10721e916772SGavin Shan bus->busn_res.start, bus->busn_res.end, pe->pe_number); 1073fb446ad0SGavin Shan else 1074fb446ad0SGavin Shan pe_info(pe, "Secondary bus %d associated with PE#%d\n", 10751e916772SGavin Shan bus->busn_res.start, pe->pe_number); 1076184cd4a3SBenjamin Herrenschmidt 1077184cd4a3SBenjamin Herrenschmidt if (pnv_ioda_configure_pe(phb, pe)) { 1078184cd4a3SBenjamin Herrenschmidt /* XXX What do we do here ? */ 10791e916772SGavin Shan pnv_ioda_free_pe(pe); 1080184cd4a3SBenjamin Herrenschmidt pe->pbus = NULL; 10811e916772SGavin Shan return NULL; 1082184cd4a3SBenjamin Herrenschmidt } 1083184cd4a3SBenjamin Herrenschmidt 1084184cd4a3SBenjamin Herrenschmidt /* Associate it with all child devices */ 1085184cd4a3SBenjamin Herrenschmidt pnv_ioda_setup_same_PE(bus, pe); 1086184cd4a3SBenjamin Herrenschmidt 10877ebdf956SGavin Shan /* Put PE to the list */ 10887ebdf956SGavin Shan list_add_tail(&pe->list, &phb->ioda.pe_list); 10891e916772SGavin Shan 10901e916772SGavin Shan return pe; 1091184cd4a3SBenjamin Herrenschmidt } 1092184cd4a3SBenjamin Herrenschmidt 1093b521549aSAlistair Popple static struct pnv_ioda_pe *pnv_ioda_setup_npu_PE(struct pci_dev *npu_pdev) 10945d2aa710SAlistair Popple { 1095b521549aSAlistair Popple int pe_num, found_pe = false, rc; 1096b521549aSAlistair Popple long rid; 1097b521549aSAlistair Popple struct pnv_ioda_pe *pe; 1098b521549aSAlistair Popple struct pci_dev *gpu_pdev; 1099b521549aSAlistair Popple struct pci_dn *npu_pdn; 1100b521549aSAlistair Popple struct pci_controller *hose = pci_bus_to_host(npu_pdev->bus); 1101b521549aSAlistair Popple struct pnv_phb *phb = hose->private_data; 1102b521549aSAlistair Popple 1103b521549aSAlistair Popple /* 1104b521549aSAlistair Popple * Due to a hardware errata PE#0 on the NPU is reserved for 1105b521549aSAlistair Popple * error handling. This means we only have three PEs remaining 1106b521549aSAlistair Popple * which need to be assigned to four links, implying some 1107b521549aSAlistair Popple * links must share PEs. 1108b521549aSAlistair Popple * 1109b521549aSAlistair Popple * To achieve this we assign PEs such that NPUs linking the 1110b521549aSAlistair Popple * same GPU get assigned the same PE. 1111b521549aSAlistair Popple */ 1112b521549aSAlistair Popple gpu_pdev = pnv_pci_get_gpu_dev(npu_pdev); 111392b8f137SGavin Shan for (pe_num = 0; pe_num < phb->ioda.total_pe_num; pe_num++) { 1114b521549aSAlistair Popple pe = &phb->ioda.pe_array[pe_num]; 1115b521549aSAlistair Popple if (!pe->pdev) 1116b521549aSAlistair Popple continue; 1117b521549aSAlistair Popple 1118b521549aSAlistair Popple if (pnv_pci_get_gpu_dev(pe->pdev) == gpu_pdev) { 1119b521549aSAlistair Popple /* 1120b521549aSAlistair Popple * This device has the same peer GPU so should 1121b521549aSAlistair Popple * be assigned the same PE as the existing 1122b521549aSAlistair Popple * peer NPU. 1123b521549aSAlistair Popple */ 1124b521549aSAlistair Popple dev_info(&npu_pdev->dev, 1125b521549aSAlistair Popple "Associating to existing PE %d\n", pe_num); 1126b521549aSAlistair Popple pci_dev_get(npu_pdev); 1127b521549aSAlistair Popple npu_pdn = pci_get_pdn(npu_pdev); 1128b521549aSAlistair Popple rid = npu_pdev->bus->number << 8 | npu_pdn->devfn; 1129b521549aSAlistair Popple npu_pdn->pcidev = npu_pdev; 1130b521549aSAlistair Popple npu_pdn->pe_number = pe_num; 1131b521549aSAlistair Popple phb->ioda.pe_rmap[rid] = pe->pe_number; 1132b521549aSAlistair Popple 1133b521549aSAlistair Popple /* Map the PE to this link */ 1134b521549aSAlistair Popple rc = opal_pci_set_pe(phb->opal_id, pe_num, rid, 1135b521549aSAlistair Popple OpalPciBusAll, 1136b521549aSAlistair Popple OPAL_COMPARE_RID_DEVICE_NUMBER, 1137b521549aSAlistair Popple OPAL_COMPARE_RID_FUNCTION_NUMBER, 1138b521549aSAlistair Popple OPAL_MAP_PE); 1139b521549aSAlistair Popple WARN_ON(rc != OPAL_SUCCESS); 1140b521549aSAlistair Popple found_pe = true; 1141b521549aSAlistair Popple break; 1142b521549aSAlistair Popple } 1143b521549aSAlistair Popple } 1144b521549aSAlistair Popple 1145b521549aSAlistair Popple if (!found_pe) 1146b521549aSAlistair Popple /* 1147b521549aSAlistair Popple * Could not find an existing PE so allocate a new 1148b521549aSAlistair Popple * one. 1149b521549aSAlistair Popple */ 1150b521549aSAlistair Popple return pnv_ioda_setup_dev_PE(npu_pdev); 1151b521549aSAlistair Popple else 1152b521549aSAlistair Popple return pe; 1153b521549aSAlistair Popple } 1154b521549aSAlistair Popple 1155b521549aSAlistair Popple static void pnv_ioda_setup_npu_PEs(struct pci_bus *bus) 1156b521549aSAlistair Popple { 11575d2aa710SAlistair Popple struct pci_dev *pdev; 11585d2aa710SAlistair Popple 11595d2aa710SAlistair Popple list_for_each_entry(pdev, &bus->devices, bus_list) 1160b521549aSAlistair Popple pnv_ioda_setup_npu_PE(pdev); 11615d2aa710SAlistair Popple } 11625d2aa710SAlistair Popple 1163cad5cef6SGreg Kroah-Hartman static void pnv_ioda_setup_PEs(struct pci_bus *bus) 1164184cd4a3SBenjamin Herrenschmidt { 1165184cd4a3SBenjamin Herrenschmidt struct pci_dev *dev; 1166fb446ad0SGavin Shan 1167d1203852SGavin Shan pnv_ioda_setup_bus_PE(bus, false); 1168184cd4a3SBenjamin Herrenschmidt 1169184cd4a3SBenjamin Herrenschmidt list_for_each_entry(dev, &bus->devices, bus_list) { 1170fb446ad0SGavin Shan if (dev->subordinate) { 117162f87c0eSYijing Wang if (pci_pcie_type(dev) == PCI_EXP_TYPE_PCI_BRIDGE) 1172d1203852SGavin Shan pnv_ioda_setup_bus_PE(dev->subordinate, true); 1173fb446ad0SGavin Shan else 1174184cd4a3SBenjamin Herrenschmidt pnv_ioda_setup_PEs(dev->subordinate); 1175184cd4a3SBenjamin Herrenschmidt } 1176184cd4a3SBenjamin Herrenschmidt } 1177fb446ad0SGavin Shan } 1178fb446ad0SGavin Shan 1179fb446ad0SGavin Shan /* 1180fb446ad0SGavin Shan * Configure PEs so that the downstream PCI buses and devices 1181fb446ad0SGavin Shan * could have their associated PE#. Unfortunately, we didn't 1182fb446ad0SGavin Shan * figure out the way to identify the PLX bridge yet. So we 1183fb446ad0SGavin Shan * simply put the PCI bus and the subordinate behind the root 1184fb446ad0SGavin Shan * port to PE# here. The game rule here is expected to be changed 1185fb446ad0SGavin Shan * as soon as we can detected PLX bridge correctly. 1186fb446ad0SGavin Shan */ 1187cad5cef6SGreg Kroah-Hartman static void pnv_pci_ioda_setup_PEs(void) 1188fb446ad0SGavin Shan { 1189fb446ad0SGavin Shan struct pci_controller *hose, *tmp; 1190262af557SGuo Chao struct pnv_phb *phb; 1191fb446ad0SGavin Shan 1192fb446ad0SGavin Shan list_for_each_entry_safe(hose, tmp, &hose_list, list_node) { 1193262af557SGuo Chao phb = hose->private_data; 1194262af557SGuo Chao 1195262af557SGuo Chao /* M64 layout might affect PE allocation */ 11965ef73567SGavin Shan if (phb->reserve_m64_pe) 119796a2f92bSGavin Shan phb->reserve_m64_pe(hose->bus, NULL, true); 1198262af557SGuo Chao 11995d2aa710SAlistair Popple /* 12005d2aa710SAlistair Popple * On NPU PHB, we expect separate PEs for individual PCI 12015d2aa710SAlistair Popple * functions. PCI bus dependent PEs are required for the 12025d2aa710SAlistair Popple * remaining types of PHBs. 12035d2aa710SAlistair Popple */ 120408f48f32SAlistair Popple if (phb->type == PNV_PHB_NPU) { 120508f48f32SAlistair Popple /* PE#0 is needed for error reporting */ 120608f48f32SAlistair Popple pnv_ioda_reserve_pe(phb, 0); 1207b521549aSAlistair Popple pnv_ioda_setup_npu_PEs(hose->bus); 120808f48f32SAlistair Popple } else 1209fb446ad0SGavin Shan pnv_ioda_setup_PEs(hose->bus); 1210fb446ad0SGavin Shan } 1211fb446ad0SGavin Shan } 1212184cd4a3SBenjamin Herrenschmidt 1213a8b2f828SGavin Shan #ifdef CONFIG_PCI_IOV 1214ee8222feSWei Yang static int pnv_pci_vf_release_m64(struct pci_dev *pdev, u16 num_vfs) 1215781a868fSWei Yang { 1216781a868fSWei Yang struct pci_bus *bus; 1217781a868fSWei Yang struct pci_controller *hose; 1218781a868fSWei Yang struct pnv_phb *phb; 1219781a868fSWei Yang struct pci_dn *pdn; 122002639b0eSWei Yang int i, j; 1221ee8222feSWei Yang int m64_bars; 1222781a868fSWei Yang 1223781a868fSWei Yang bus = pdev->bus; 1224781a868fSWei Yang hose = pci_bus_to_host(bus); 1225781a868fSWei Yang phb = hose->private_data; 1226781a868fSWei Yang pdn = pci_get_pdn(pdev); 1227781a868fSWei Yang 1228ee8222feSWei Yang if (pdn->m64_single_mode) 1229ee8222feSWei Yang m64_bars = num_vfs; 1230ee8222feSWei Yang else 1231ee8222feSWei Yang m64_bars = 1; 1232ee8222feSWei Yang 123302639b0eSWei Yang for (i = 0; i < PCI_SRIOV_NUM_BARS; i++) 1234ee8222feSWei Yang for (j = 0; j < m64_bars; j++) { 1235ee8222feSWei Yang if (pdn->m64_map[j][i] == IODA_INVALID_M64) 1236781a868fSWei Yang continue; 1237781a868fSWei Yang opal_pci_phb_mmio_enable(phb->opal_id, 1238ee8222feSWei Yang OPAL_M64_WINDOW_TYPE, pdn->m64_map[j][i], 0); 1239ee8222feSWei Yang clear_bit(pdn->m64_map[j][i], &phb->ioda.m64_bar_alloc); 1240ee8222feSWei Yang pdn->m64_map[j][i] = IODA_INVALID_M64; 1241781a868fSWei Yang } 1242781a868fSWei Yang 1243ee8222feSWei Yang kfree(pdn->m64_map); 1244781a868fSWei Yang return 0; 1245781a868fSWei Yang } 1246781a868fSWei Yang 124702639b0eSWei Yang static int pnv_pci_vf_assign_m64(struct pci_dev *pdev, u16 num_vfs) 1248781a868fSWei Yang { 1249781a868fSWei Yang struct pci_bus *bus; 1250781a868fSWei Yang struct pci_controller *hose; 1251781a868fSWei Yang struct pnv_phb *phb; 1252781a868fSWei Yang struct pci_dn *pdn; 1253781a868fSWei Yang unsigned int win; 1254781a868fSWei Yang struct resource *res; 125502639b0eSWei Yang int i, j; 1256781a868fSWei Yang int64_t rc; 125702639b0eSWei Yang int total_vfs; 125802639b0eSWei Yang resource_size_t size, start; 125902639b0eSWei Yang int pe_num; 1260ee8222feSWei Yang int m64_bars; 1261781a868fSWei Yang 1262781a868fSWei Yang bus = pdev->bus; 1263781a868fSWei Yang hose = pci_bus_to_host(bus); 1264781a868fSWei Yang phb = hose->private_data; 1265781a868fSWei Yang pdn = pci_get_pdn(pdev); 126602639b0eSWei Yang total_vfs = pci_sriov_get_totalvfs(pdev); 1267781a868fSWei Yang 1268ee8222feSWei Yang if (pdn->m64_single_mode) 1269ee8222feSWei Yang m64_bars = num_vfs; 1270ee8222feSWei Yang else 1271ee8222feSWei Yang m64_bars = 1; 127202639b0eSWei Yang 1273ee8222feSWei Yang pdn->m64_map = kmalloc(sizeof(*pdn->m64_map) * m64_bars, GFP_KERNEL); 1274ee8222feSWei Yang if (!pdn->m64_map) 1275ee8222feSWei Yang return -ENOMEM; 1276ee8222feSWei Yang /* Initialize the m64_map to IODA_INVALID_M64 */ 1277ee8222feSWei Yang for (i = 0; i < m64_bars ; i++) 1278ee8222feSWei Yang for (j = 0; j < PCI_SRIOV_NUM_BARS; j++) 1279ee8222feSWei Yang pdn->m64_map[i][j] = IODA_INVALID_M64; 1280ee8222feSWei Yang 1281781a868fSWei Yang 1282781a868fSWei Yang for (i = 0; i < PCI_SRIOV_NUM_BARS; i++) { 1283781a868fSWei Yang res = &pdev->resource[i + PCI_IOV_RESOURCES]; 1284781a868fSWei Yang if (!res->flags || !res->parent) 1285781a868fSWei Yang continue; 1286781a868fSWei Yang 1287ee8222feSWei Yang for (j = 0; j < m64_bars; j++) { 1288781a868fSWei Yang do { 1289781a868fSWei Yang win = find_next_zero_bit(&phb->ioda.m64_bar_alloc, 1290781a868fSWei Yang phb->ioda.m64_bar_idx + 1, 0); 1291781a868fSWei Yang 1292781a868fSWei Yang if (win >= phb->ioda.m64_bar_idx + 1) 1293781a868fSWei Yang goto m64_failed; 1294781a868fSWei Yang } while (test_and_set_bit(win, &phb->ioda.m64_bar_alloc)); 1295781a868fSWei Yang 1296ee8222feSWei Yang pdn->m64_map[j][i] = win; 129702639b0eSWei Yang 1298ee8222feSWei Yang if (pdn->m64_single_mode) { 129902639b0eSWei Yang size = pci_iov_resource_size(pdev, 130002639b0eSWei Yang PCI_IOV_RESOURCES + i); 130102639b0eSWei Yang start = res->start + size * j; 130202639b0eSWei Yang } else { 130302639b0eSWei Yang size = resource_size(res); 130402639b0eSWei Yang start = res->start; 130502639b0eSWei Yang } 1306781a868fSWei Yang 1307781a868fSWei Yang /* Map the M64 here */ 1308ee8222feSWei Yang if (pdn->m64_single_mode) { 1309be283eebSWei Yang pe_num = pdn->pe_num_map[j]; 131002639b0eSWei Yang rc = opal_pci_map_pe_mmio_window(phb->opal_id, 131102639b0eSWei Yang pe_num, OPAL_M64_WINDOW_TYPE, 1312ee8222feSWei Yang pdn->m64_map[j][i], 0); 131302639b0eSWei Yang } 131402639b0eSWei Yang 1315781a868fSWei Yang rc = opal_pci_set_phb_mem_window(phb->opal_id, 1316781a868fSWei Yang OPAL_M64_WINDOW_TYPE, 1317ee8222feSWei Yang pdn->m64_map[j][i], 131802639b0eSWei Yang start, 1319781a868fSWei Yang 0, /* unused */ 132002639b0eSWei Yang size); 132102639b0eSWei Yang 132202639b0eSWei Yang 1323781a868fSWei Yang if (rc != OPAL_SUCCESS) { 1324781a868fSWei Yang dev_err(&pdev->dev, "Failed to map M64 window #%d: %lld\n", 1325781a868fSWei Yang win, rc); 1326781a868fSWei Yang goto m64_failed; 1327781a868fSWei Yang } 1328781a868fSWei Yang 1329ee8222feSWei Yang if (pdn->m64_single_mode) 1330781a868fSWei Yang rc = opal_pci_phb_mmio_enable(phb->opal_id, 1331ee8222feSWei Yang OPAL_M64_WINDOW_TYPE, pdn->m64_map[j][i], 2); 133202639b0eSWei Yang else 133302639b0eSWei Yang rc = opal_pci_phb_mmio_enable(phb->opal_id, 1334ee8222feSWei Yang OPAL_M64_WINDOW_TYPE, pdn->m64_map[j][i], 1); 133502639b0eSWei Yang 1336781a868fSWei Yang if (rc != OPAL_SUCCESS) { 1337781a868fSWei Yang dev_err(&pdev->dev, "Failed to enable M64 window #%d: %llx\n", 1338781a868fSWei Yang win, rc); 1339781a868fSWei Yang goto m64_failed; 1340781a868fSWei Yang } 1341781a868fSWei Yang } 134202639b0eSWei Yang } 1343781a868fSWei Yang return 0; 1344781a868fSWei Yang 1345781a868fSWei Yang m64_failed: 1346ee8222feSWei Yang pnv_pci_vf_release_m64(pdev, num_vfs); 1347781a868fSWei Yang return -EBUSY; 1348781a868fSWei Yang } 1349781a868fSWei Yang 1350c035e37bSAlexey Kardashevskiy static long pnv_pci_ioda2_unset_window(struct iommu_table_group *table_group, 1351c035e37bSAlexey Kardashevskiy int num); 1352c035e37bSAlexey Kardashevskiy static void pnv_pci_ioda2_set_bypass(struct pnv_ioda_pe *pe, bool enable); 1353c035e37bSAlexey Kardashevskiy 1354781a868fSWei Yang static void pnv_pci_ioda2_release_dma_pe(struct pci_dev *dev, struct pnv_ioda_pe *pe) 1355781a868fSWei Yang { 1356781a868fSWei Yang struct iommu_table *tbl; 1357781a868fSWei Yang int64_t rc; 1358781a868fSWei Yang 1359b348aa65SAlexey Kardashevskiy tbl = pe->table_group.tables[0]; 1360c035e37bSAlexey Kardashevskiy rc = pnv_pci_ioda2_unset_window(&pe->table_group, 0); 1361781a868fSWei Yang if (rc) 1362781a868fSWei Yang pe_warn(pe, "OPAL error %ld release DMA window\n", rc); 1363781a868fSWei Yang 1364c035e37bSAlexey Kardashevskiy pnv_pci_ioda2_set_bypass(pe, false); 13650eaf4defSAlexey Kardashevskiy if (pe->table_group.group) { 13660eaf4defSAlexey Kardashevskiy iommu_group_put(pe->table_group.group); 13670eaf4defSAlexey Kardashevskiy BUG_ON(pe->table_group.group); 1368ac9a5889SAlexey Kardashevskiy } 1369aca6913fSAlexey Kardashevskiy pnv_pci_ioda2_table_free_pages(tbl); 1370781a868fSWei Yang iommu_free_table(tbl, of_node_full_name(dev->dev.of_node)); 1371781a868fSWei Yang } 1372781a868fSWei Yang 1373ee8222feSWei Yang static void pnv_ioda_release_vf_PE(struct pci_dev *pdev) 1374781a868fSWei Yang { 1375781a868fSWei Yang struct pci_bus *bus; 1376781a868fSWei Yang struct pci_controller *hose; 1377781a868fSWei Yang struct pnv_phb *phb; 1378781a868fSWei Yang struct pnv_ioda_pe *pe, *pe_n; 1379781a868fSWei Yang struct pci_dn *pdn; 1380781a868fSWei Yang 1381781a868fSWei Yang bus = pdev->bus; 1382781a868fSWei Yang hose = pci_bus_to_host(bus); 1383781a868fSWei Yang phb = hose->private_data; 138402639b0eSWei Yang pdn = pci_get_pdn(pdev); 1385781a868fSWei Yang 1386781a868fSWei Yang if (!pdev->is_physfn) 1387781a868fSWei Yang return; 1388781a868fSWei Yang 1389781a868fSWei Yang list_for_each_entry_safe(pe, pe_n, &phb->ioda.pe_list, list) { 1390781a868fSWei Yang if (pe->parent_dev != pdev) 1391781a868fSWei Yang continue; 1392781a868fSWei Yang 1393781a868fSWei Yang pnv_pci_ioda2_release_dma_pe(pdev, pe); 1394781a868fSWei Yang 1395781a868fSWei Yang /* Remove from list */ 1396781a868fSWei Yang mutex_lock(&phb->ioda.pe_list_mutex); 1397781a868fSWei Yang list_del(&pe->list); 1398781a868fSWei Yang mutex_unlock(&phb->ioda.pe_list_mutex); 1399781a868fSWei Yang 1400781a868fSWei Yang pnv_ioda_deconfigure_pe(phb, pe); 1401781a868fSWei Yang 14021e916772SGavin Shan pnv_ioda_free_pe(pe); 1403781a868fSWei Yang } 1404781a868fSWei Yang } 1405781a868fSWei Yang 1406781a868fSWei Yang void pnv_pci_sriov_disable(struct pci_dev *pdev) 1407781a868fSWei Yang { 1408781a868fSWei Yang struct pci_bus *bus; 1409781a868fSWei Yang struct pci_controller *hose; 1410781a868fSWei Yang struct pnv_phb *phb; 14111e916772SGavin Shan struct pnv_ioda_pe *pe; 1412781a868fSWei Yang struct pci_dn *pdn; 1413781a868fSWei Yang struct pci_sriov *iov; 1414be283eebSWei Yang u16 num_vfs, i; 1415781a868fSWei Yang 1416781a868fSWei Yang bus = pdev->bus; 1417781a868fSWei Yang hose = pci_bus_to_host(bus); 1418781a868fSWei Yang phb = hose->private_data; 1419781a868fSWei Yang pdn = pci_get_pdn(pdev); 1420781a868fSWei Yang iov = pdev->sriov; 1421781a868fSWei Yang num_vfs = pdn->num_vfs; 1422781a868fSWei Yang 1423781a868fSWei Yang /* Release VF PEs */ 1424ee8222feSWei Yang pnv_ioda_release_vf_PE(pdev); 1425781a868fSWei Yang 1426781a868fSWei Yang if (phb->type == PNV_PHB_IODA2) { 1427ee8222feSWei Yang if (!pdn->m64_single_mode) 1428be283eebSWei Yang pnv_pci_vf_resource_shift(pdev, -*pdn->pe_num_map); 1429781a868fSWei Yang 1430781a868fSWei Yang /* Release M64 windows */ 1431ee8222feSWei Yang pnv_pci_vf_release_m64(pdev, num_vfs); 1432781a868fSWei Yang 1433781a868fSWei Yang /* Release PE numbers */ 1434be283eebSWei Yang if (pdn->m64_single_mode) { 1435be283eebSWei Yang for (i = 0; i < num_vfs; i++) { 14361e916772SGavin Shan if (pdn->pe_num_map[i] == IODA_INVALID_PE) 14371e916772SGavin Shan continue; 14381e916772SGavin Shan 14391e916772SGavin Shan pe = &phb->ioda.pe_array[pdn->pe_num_map[i]]; 14401e916772SGavin Shan pnv_ioda_free_pe(pe); 1441be283eebSWei Yang } 1442be283eebSWei Yang } else 1443be283eebSWei Yang bitmap_clear(phb->ioda.pe_alloc, *pdn->pe_num_map, num_vfs); 1444be283eebSWei Yang /* Releasing pe_num_map */ 1445be283eebSWei Yang kfree(pdn->pe_num_map); 1446781a868fSWei Yang } 1447781a868fSWei Yang } 1448781a868fSWei Yang 1449781a868fSWei Yang static void pnv_pci_ioda2_setup_dma_pe(struct pnv_phb *phb, 1450781a868fSWei Yang struct pnv_ioda_pe *pe); 1451781a868fSWei Yang static void pnv_ioda_setup_vf_PE(struct pci_dev *pdev, u16 num_vfs) 1452781a868fSWei Yang { 1453781a868fSWei Yang struct pci_bus *bus; 1454781a868fSWei Yang struct pci_controller *hose; 1455781a868fSWei Yang struct pnv_phb *phb; 1456781a868fSWei Yang struct pnv_ioda_pe *pe; 1457781a868fSWei Yang int pe_num; 1458781a868fSWei Yang u16 vf_index; 1459781a868fSWei Yang struct pci_dn *pdn; 1460781a868fSWei Yang 1461781a868fSWei Yang bus = pdev->bus; 1462781a868fSWei Yang hose = pci_bus_to_host(bus); 1463781a868fSWei Yang phb = hose->private_data; 1464781a868fSWei Yang pdn = pci_get_pdn(pdev); 1465781a868fSWei Yang 1466781a868fSWei Yang if (!pdev->is_physfn) 1467781a868fSWei Yang return; 1468781a868fSWei Yang 1469781a868fSWei Yang /* Reserve PE for each VF */ 1470781a868fSWei Yang for (vf_index = 0; vf_index < num_vfs; vf_index++) { 1471be283eebSWei Yang if (pdn->m64_single_mode) 1472be283eebSWei Yang pe_num = pdn->pe_num_map[vf_index]; 1473be283eebSWei Yang else 1474be283eebSWei Yang pe_num = *pdn->pe_num_map + vf_index; 1475781a868fSWei Yang 1476781a868fSWei Yang pe = &phb->ioda.pe_array[pe_num]; 1477781a868fSWei Yang pe->pe_number = pe_num; 1478781a868fSWei Yang pe->phb = phb; 1479781a868fSWei Yang pe->flags = PNV_IODA_PE_VF; 1480781a868fSWei Yang pe->pbus = NULL; 1481781a868fSWei Yang pe->parent_dev = pdev; 1482781a868fSWei Yang pe->mve_number = -1; 1483781a868fSWei Yang pe->rid = (pci_iov_virtfn_bus(pdev, vf_index) << 8) | 1484781a868fSWei Yang pci_iov_virtfn_devfn(pdev, vf_index); 1485781a868fSWei Yang 1486781a868fSWei Yang pe_info(pe, "VF %04d:%02d:%02d.%d associated with PE#%d\n", 1487781a868fSWei Yang hose->global_number, pdev->bus->number, 1488781a868fSWei Yang PCI_SLOT(pci_iov_virtfn_devfn(pdev, vf_index)), 1489781a868fSWei Yang PCI_FUNC(pci_iov_virtfn_devfn(pdev, vf_index)), pe_num); 1490781a868fSWei Yang 1491781a868fSWei Yang if (pnv_ioda_configure_pe(phb, pe)) { 1492781a868fSWei Yang /* XXX What do we do here ? */ 14931e916772SGavin Shan pnv_ioda_free_pe(pe); 1494781a868fSWei Yang pe->pdev = NULL; 1495781a868fSWei Yang continue; 1496781a868fSWei Yang } 1497781a868fSWei Yang 1498781a868fSWei Yang /* Put PE to the list */ 1499781a868fSWei Yang mutex_lock(&phb->ioda.pe_list_mutex); 1500781a868fSWei Yang list_add_tail(&pe->list, &phb->ioda.pe_list); 1501781a868fSWei Yang mutex_unlock(&phb->ioda.pe_list_mutex); 1502781a868fSWei Yang 1503781a868fSWei Yang pnv_pci_ioda2_setup_dma_pe(phb, pe); 1504781a868fSWei Yang } 1505781a868fSWei Yang } 1506781a868fSWei Yang 1507781a868fSWei Yang int pnv_pci_sriov_enable(struct pci_dev *pdev, u16 num_vfs) 1508781a868fSWei Yang { 1509781a868fSWei Yang struct pci_bus *bus; 1510781a868fSWei Yang struct pci_controller *hose; 1511781a868fSWei Yang struct pnv_phb *phb; 15121e916772SGavin Shan struct pnv_ioda_pe *pe; 1513781a868fSWei Yang struct pci_dn *pdn; 1514781a868fSWei Yang int ret; 1515be283eebSWei Yang u16 i; 1516781a868fSWei Yang 1517781a868fSWei Yang bus = pdev->bus; 1518781a868fSWei Yang hose = pci_bus_to_host(bus); 1519781a868fSWei Yang phb = hose->private_data; 1520781a868fSWei Yang pdn = pci_get_pdn(pdev); 1521781a868fSWei Yang 1522781a868fSWei Yang if (phb->type == PNV_PHB_IODA2) { 1523b0331854SWei Yang if (!pdn->vfs_expanded) { 1524b0331854SWei Yang dev_info(&pdev->dev, "don't support this SRIOV device" 1525b0331854SWei Yang " with non 64bit-prefetchable IOV BAR\n"); 1526b0331854SWei Yang return -ENOSPC; 1527b0331854SWei Yang } 1528b0331854SWei Yang 1529ee8222feSWei Yang /* 1530ee8222feSWei Yang * When M64 BARs functions in Single PE mode, the number of VFs 1531ee8222feSWei Yang * could be enabled must be less than the number of M64 BARs. 1532ee8222feSWei Yang */ 1533ee8222feSWei Yang if (pdn->m64_single_mode && num_vfs > phb->ioda.m64_bar_idx) { 1534ee8222feSWei Yang dev_info(&pdev->dev, "Not enough M64 BAR for VFs\n"); 1535ee8222feSWei Yang return -EBUSY; 1536ee8222feSWei Yang } 1537ee8222feSWei Yang 1538be283eebSWei Yang /* Allocating pe_num_map */ 1539be283eebSWei Yang if (pdn->m64_single_mode) 1540be283eebSWei Yang pdn->pe_num_map = kmalloc(sizeof(*pdn->pe_num_map) * num_vfs, 1541be283eebSWei Yang GFP_KERNEL); 1542be283eebSWei Yang else 1543be283eebSWei Yang pdn->pe_num_map = kmalloc(sizeof(*pdn->pe_num_map), GFP_KERNEL); 1544be283eebSWei Yang 1545be283eebSWei Yang if (!pdn->pe_num_map) 1546be283eebSWei Yang return -ENOMEM; 1547be283eebSWei Yang 1548be283eebSWei Yang if (pdn->m64_single_mode) 1549be283eebSWei Yang for (i = 0; i < num_vfs; i++) 1550be283eebSWei Yang pdn->pe_num_map[i] = IODA_INVALID_PE; 1551be283eebSWei Yang 1552781a868fSWei Yang /* Calculate available PE for required VFs */ 1553be283eebSWei Yang if (pdn->m64_single_mode) { 1554be283eebSWei Yang for (i = 0; i < num_vfs; i++) { 15551e916772SGavin Shan pe = pnv_ioda_alloc_pe(phb); 15561e916772SGavin Shan if (!pe) { 1557be283eebSWei Yang ret = -EBUSY; 1558be283eebSWei Yang goto m64_failed; 1559be283eebSWei Yang } 15601e916772SGavin Shan 15611e916772SGavin Shan pdn->pe_num_map[i] = pe->pe_number; 1562be283eebSWei Yang } 1563be283eebSWei Yang } else { 1564781a868fSWei Yang mutex_lock(&phb->ioda.pe_alloc_mutex); 1565be283eebSWei Yang *pdn->pe_num_map = bitmap_find_next_zero_area( 156692b8f137SGavin Shan phb->ioda.pe_alloc, phb->ioda.total_pe_num, 1567781a868fSWei Yang 0, num_vfs, 0); 156892b8f137SGavin Shan if (*pdn->pe_num_map >= phb->ioda.total_pe_num) { 1569781a868fSWei Yang mutex_unlock(&phb->ioda.pe_alloc_mutex); 1570781a868fSWei Yang dev_info(&pdev->dev, "Failed to enable VF%d\n", num_vfs); 1571be283eebSWei Yang kfree(pdn->pe_num_map); 1572781a868fSWei Yang return -EBUSY; 1573781a868fSWei Yang } 1574be283eebSWei Yang bitmap_set(phb->ioda.pe_alloc, *pdn->pe_num_map, num_vfs); 1575781a868fSWei Yang mutex_unlock(&phb->ioda.pe_alloc_mutex); 1576be283eebSWei Yang } 1577be283eebSWei Yang pdn->num_vfs = num_vfs; 1578781a868fSWei Yang 1579781a868fSWei Yang /* Assign M64 window accordingly */ 158002639b0eSWei Yang ret = pnv_pci_vf_assign_m64(pdev, num_vfs); 1581781a868fSWei Yang if (ret) { 1582781a868fSWei Yang dev_info(&pdev->dev, "Not enough M64 window resources\n"); 1583781a868fSWei Yang goto m64_failed; 1584781a868fSWei Yang } 1585781a868fSWei Yang 1586781a868fSWei Yang /* 1587781a868fSWei Yang * When using one M64 BAR to map one IOV BAR, we need to shift 1588781a868fSWei Yang * the IOV BAR according to the PE# allocated to the VFs. 1589781a868fSWei Yang * Otherwise, the PE# for the VF will conflict with others. 1590781a868fSWei Yang */ 1591ee8222feSWei Yang if (!pdn->m64_single_mode) { 1592be283eebSWei Yang ret = pnv_pci_vf_resource_shift(pdev, *pdn->pe_num_map); 1593781a868fSWei Yang if (ret) 1594781a868fSWei Yang goto m64_failed; 1595781a868fSWei Yang } 159602639b0eSWei Yang } 1597781a868fSWei Yang 1598781a868fSWei Yang /* Setup VF PEs */ 1599781a868fSWei Yang pnv_ioda_setup_vf_PE(pdev, num_vfs); 1600781a868fSWei Yang 1601781a868fSWei Yang return 0; 1602781a868fSWei Yang 1603781a868fSWei Yang m64_failed: 1604be283eebSWei Yang if (pdn->m64_single_mode) { 1605be283eebSWei Yang for (i = 0; i < num_vfs; i++) { 16061e916772SGavin Shan if (pdn->pe_num_map[i] == IODA_INVALID_PE) 16071e916772SGavin Shan continue; 16081e916772SGavin Shan 16091e916772SGavin Shan pe = &phb->ioda.pe_array[pdn->pe_num_map[i]]; 16101e916772SGavin Shan pnv_ioda_free_pe(pe); 1611be283eebSWei Yang } 1612be283eebSWei Yang } else 1613be283eebSWei Yang bitmap_clear(phb->ioda.pe_alloc, *pdn->pe_num_map, num_vfs); 1614be283eebSWei Yang 1615be283eebSWei Yang /* Releasing pe_num_map */ 1616be283eebSWei Yang kfree(pdn->pe_num_map); 1617781a868fSWei Yang 1618781a868fSWei Yang return ret; 1619781a868fSWei Yang } 1620781a868fSWei Yang 1621a8b2f828SGavin Shan int pcibios_sriov_disable(struct pci_dev *pdev) 1622a8b2f828SGavin Shan { 1623781a868fSWei Yang pnv_pci_sriov_disable(pdev); 1624781a868fSWei Yang 1625a8b2f828SGavin Shan /* Release PCI data */ 1626a8b2f828SGavin Shan remove_dev_pci_data(pdev); 1627a8b2f828SGavin Shan return 0; 1628a8b2f828SGavin Shan } 1629a8b2f828SGavin Shan 1630a8b2f828SGavin Shan int pcibios_sriov_enable(struct pci_dev *pdev, u16 num_vfs) 1631a8b2f828SGavin Shan { 1632a8b2f828SGavin Shan /* Allocate PCI data */ 1633a8b2f828SGavin Shan add_dev_pci_data(pdev); 1634781a868fSWei Yang 1635ee8222feSWei Yang return pnv_pci_sriov_enable(pdev, num_vfs); 1636a8b2f828SGavin Shan } 1637a8b2f828SGavin Shan #endif /* CONFIG_PCI_IOV */ 1638a8b2f828SGavin Shan 1639959c9bddSGavin Shan static void pnv_pci_ioda_dma_dev_setup(struct pnv_phb *phb, struct pci_dev *pdev) 1640184cd4a3SBenjamin Herrenschmidt { 1641b72c1f65SBenjamin Herrenschmidt struct pci_dn *pdn = pci_get_pdn(pdev); 1642959c9bddSGavin Shan struct pnv_ioda_pe *pe; 1643184cd4a3SBenjamin Herrenschmidt 1644959c9bddSGavin Shan /* 1645959c9bddSGavin Shan * The function can be called while the PE# 1646959c9bddSGavin Shan * hasn't been assigned. Do nothing for the 1647959c9bddSGavin Shan * case. 1648959c9bddSGavin Shan */ 1649959c9bddSGavin Shan if (!pdn || pdn->pe_number == IODA_INVALID_PE) 1650959c9bddSGavin Shan return; 1651184cd4a3SBenjamin Herrenschmidt 1652959c9bddSGavin Shan pe = &phb->ioda.pe_array[pdn->pe_number]; 1653cd15b048SBenjamin Herrenschmidt WARN_ON(get_dma_ops(&pdev->dev) != &dma_iommu_ops); 16540e1ffef0SAlexey Kardashevskiy set_dma_offset(&pdev->dev, pe->tce_bypass_base); 1655b348aa65SAlexey Kardashevskiy set_iommu_table_base(&pdev->dev, pe->table_group.tables[0]); 16564617082eSAlexey Kardashevskiy /* 16574617082eSAlexey Kardashevskiy * Note: iommu_add_device() will fail here as 16584617082eSAlexey Kardashevskiy * for physical PE: the device is already added by now; 16594617082eSAlexey Kardashevskiy * for virtual PE: sysfs entries are not ready yet and 16604617082eSAlexey Kardashevskiy * tce_iommu_bus_notifier will add the device to a group later. 16614617082eSAlexey Kardashevskiy */ 1662184cd4a3SBenjamin Herrenschmidt } 1663184cd4a3SBenjamin Herrenschmidt 1664763d2d8dSDaniel Axtens static int pnv_pci_ioda_dma_set_mask(struct pci_dev *pdev, u64 dma_mask) 1665cd15b048SBenjamin Herrenschmidt { 1666763d2d8dSDaniel Axtens struct pci_controller *hose = pci_bus_to_host(pdev->bus); 1667763d2d8dSDaniel Axtens struct pnv_phb *phb = hose->private_data; 1668cd15b048SBenjamin Herrenschmidt struct pci_dn *pdn = pci_get_pdn(pdev); 1669cd15b048SBenjamin Herrenschmidt struct pnv_ioda_pe *pe; 1670cd15b048SBenjamin Herrenschmidt uint64_t top; 1671cd15b048SBenjamin Herrenschmidt bool bypass = false; 1672cd15b048SBenjamin Herrenschmidt 1673cd15b048SBenjamin Herrenschmidt if (WARN_ON(!pdn || pdn->pe_number == IODA_INVALID_PE)) 1674cd15b048SBenjamin Herrenschmidt return -ENODEV;; 1675cd15b048SBenjamin Herrenschmidt 1676cd15b048SBenjamin Herrenschmidt pe = &phb->ioda.pe_array[pdn->pe_number]; 1677cd15b048SBenjamin Herrenschmidt if (pe->tce_bypass_enabled) { 1678cd15b048SBenjamin Herrenschmidt top = pe->tce_bypass_base + memblock_end_of_DRAM() - 1; 1679cd15b048SBenjamin Herrenschmidt bypass = (dma_mask >= top); 1680cd15b048SBenjamin Herrenschmidt } 1681cd15b048SBenjamin Herrenschmidt 1682cd15b048SBenjamin Herrenschmidt if (bypass) { 1683cd15b048SBenjamin Herrenschmidt dev_info(&pdev->dev, "Using 64-bit DMA iommu bypass\n"); 1684cd15b048SBenjamin Herrenschmidt set_dma_ops(&pdev->dev, &dma_direct_ops); 1685cd15b048SBenjamin Herrenschmidt } else { 1686cd15b048SBenjamin Herrenschmidt dev_info(&pdev->dev, "Using 32-bit DMA via iommu\n"); 1687cd15b048SBenjamin Herrenschmidt set_dma_ops(&pdev->dev, &dma_iommu_ops); 1688cd15b048SBenjamin Herrenschmidt } 1689a32305bfSBrian W Hart *pdev->dev.dma_mask = dma_mask; 16905d2aa710SAlistair Popple 16915d2aa710SAlistair Popple /* Update peer npu devices */ 1692f9f83456SAlexey Kardashevskiy pnv_npu_try_dma_set_bypass(pdev, bypass); 16935d2aa710SAlistair Popple 1694cd15b048SBenjamin Herrenschmidt return 0; 1695cd15b048SBenjamin Herrenschmidt } 1696cd15b048SBenjamin Herrenschmidt 169753522982SAndrew Donnellan static u64 pnv_pci_ioda_dma_get_required_mask(struct pci_dev *pdev) 1698fe7e85c6SGavin Shan { 169953522982SAndrew Donnellan struct pci_controller *hose = pci_bus_to_host(pdev->bus); 170053522982SAndrew Donnellan struct pnv_phb *phb = hose->private_data; 1701fe7e85c6SGavin Shan struct pci_dn *pdn = pci_get_pdn(pdev); 1702fe7e85c6SGavin Shan struct pnv_ioda_pe *pe; 1703fe7e85c6SGavin Shan u64 end, mask; 1704fe7e85c6SGavin Shan 1705fe7e85c6SGavin Shan if (WARN_ON(!pdn || pdn->pe_number == IODA_INVALID_PE)) 1706fe7e85c6SGavin Shan return 0; 1707fe7e85c6SGavin Shan 1708fe7e85c6SGavin Shan pe = &phb->ioda.pe_array[pdn->pe_number]; 1709fe7e85c6SGavin Shan if (!pe->tce_bypass_enabled) 1710fe7e85c6SGavin Shan return __dma_get_required_mask(&pdev->dev); 1711fe7e85c6SGavin Shan 1712fe7e85c6SGavin Shan 1713fe7e85c6SGavin Shan end = pe->tce_bypass_base + memblock_end_of_DRAM(); 1714fe7e85c6SGavin Shan mask = 1ULL << (fls64(end) - 1); 1715fe7e85c6SGavin Shan mask += mask - 1; 1716fe7e85c6SGavin Shan 1717fe7e85c6SGavin Shan return mask; 1718fe7e85c6SGavin Shan } 1719fe7e85c6SGavin Shan 1720dff4a39eSGavin Shan static void pnv_ioda_setup_bus_dma(struct pnv_ioda_pe *pe, 1721ea30e99eSAlexey Kardashevskiy struct pci_bus *bus) 172274251fe2SBenjamin Herrenschmidt { 172374251fe2SBenjamin Herrenschmidt struct pci_dev *dev; 172474251fe2SBenjamin Herrenschmidt 172574251fe2SBenjamin Herrenschmidt list_for_each_entry(dev, &bus->devices, bus_list) { 1726b348aa65SAlexey Kardashevskiy set_iommu_table_base(&dev->dev, pe->table_group.tables[0]); 1727e91c2511SBenjamin Herrenschmidt set_dma_offset(&dev->dev, pe->tce_bypass_base); 17284617082eSAlexey Kardashevskiy iommu_add_device(&dev->dev); 1729dff4a39eSGavin Shan 17305c89a87dSAlexey Kardashevskiy if ((pe->flags & PNV_IODA_PE_BUS_ALL) && dev->subordinate) 1731ea30e99eSAlexey Kardashevskiy pnv_ioda_setup_bus_dma(pe, dev->subordinate); 173274251fe2SBenjamin Herrenschmidt } 173374251fe2SBenjamin Herrenschmidt } 173474251fe2SBenjamin Herrenschmidt 1735decbda25SAlexey Kardashevskiy static void pnv_pci_ioda1_tce_invalidate(struct iommu_table *tbl, 1736decbda25SAlexey Kardashevskiy unsigned long index, unsigned long npages, bool rm) 17374cce9550SGavin Shan { 17380eaf4defSAlexey Kardashevskiy struct iommu_table_group_link *tgl = list_first_entry_or_null( 17390eaf4defSAlexey Kardashevskiy &tbl->it_group_list, struct iommu_table_group_link, 17400eaf4defSAlexey Kardashevskiy next); 17410eaf4defSAlexey Kardashevskiy struct pnv_ioda_pe *pe = container_of(tgl->table_group, 1742b348aa65SAlexey Kardashevskiy struct pnv_ioda_pe, table_group); 17433ad26e5cSBenjamin Herrenschmidt __be64 __iomem *invalidate = rm ? 17445780fb04SAlexey Kardashevskiy (__be64 __iomem *)pe->phb->ioda.tce_inval_reg_phys : 17455780fb04SAlexey Kardashevskiy pe->phb->ioda.tce_inval_reg; 17464cce9550SGavin Shan unsigned long start, end, inc; 1747b0376c9bSAlexey Kardashevskiy const unsigned shift = tbl->it_page_shift; 17484cce9550SGavin Shan 1749decbda25SAlexey Kardashevskiy start = __pa(((__be64 *)tbl->it_base) + index - tbl->it_offset); 1750decbda25SAlexey Kardashevskiy end = __pa(((__be64 *)tbl->it_base) + index - tbl->it_offset + 1751decbda25SAlexey Kardashevskiy npages - 1); 17524cce9550SGavin Shan 17534cce9550SGavin Shan /* BML uses this case for p6/p7/galaxy2: Shift addr and put in node */ 17544cce9550SGavin Shan if (tbl->it_busno) { 1755b0376c9bSAlexey Kardashevskiy start <<= shift; 1756b0376c9bSAlexey Kardashevskiy end <<= shift; 1757b0376c9bSAlexey Kardashevskiy inc = 128ull << shift; 17584cce9550SGavin Shan start |= tbl->it_busno; 17594cce9550SGavin Shan end |= tbl->it_busno; 17604cce9550SGavin Shan } else if (tbl->it_type & TCE_PCI_SWINV_PAIR) { 17614cce9550SGavin Shan /* p7ioc-style invalidation, 2 TCEs per write */ 17624cce9550SGavin Shan start |= (1ull << 63); 17634cce9550SGavin Shan end |= (1ull << 63); 17644cce9550SGavin Shan inc = 16; 17654cce9550SGavin Shan } else { 17664cce9550SGavin Shan /* Default (older HW) */ 17674cce9550SGavin Shan inc = 128; 17684cce9550SGavin Shan } 17694cce9550SGavin Shan 17704cce9550SGavin Shan end |= inc - 1; /* round up end to be different than start */ 17714cce9550SGavin Shan 17724cce9550SGavin Shan mb(); /* Ensure above stores are visible */ 17734cce9550SGavin Shan while (start <= end) { 17748e0a1611SAlexey Kardashevskiy if (rm) 17753ad26e5cSBenjamin Herrenschmidt __raw_rm_writeq(cpu_to_be64(start), invalidate); 17768e0a1611SAlexey Kardashevskiy else 17773a1a4661SBenjamin Herrenschmidt __raw_writeq(cpu_to_be64(start), invalidate); 17784cce9550SGavin Shan start += inc; 17794cce9550SGavin Shan } 17804cce9550SGavin Shan 17814cce9550SGavin Shan /* 17824cce9550SGavin Shan * The iommu layer will do another mb() for us on build() 17834cce9550SGavin Shan * and we don't care on free() 17844cce9550SGavin Shan */ 17854cce9550SGavin Shan } 17864cce9550SGavin Shan 1787decbda25SAlexey Kardashevskiy static int pnv_ioda1_tce_build(struct iommu_table *tbl, long index, 1788decbda25SAlexey Kardashevskiy long npages, unsigned long uaddr, 1789decbda25SAlexey Kardashevskiy enum dma_data_direction direction, 1790decbda25SAlexey Kardashevskiy struct dma_attrs *attrs) 1791decbda25SAlexey Kardashevskiy { 1792decbda25SAlexey Kardashevskiy int ret = pnv_tce_build(tbl, index, npages, uaddr, direction, 1793decbda25SAlexey Kardashevskiy attrs); 1794decbda25SAlexey Kardashevskiy 1795decbda25SAlexey Kardashevskiy if (!ret && (tbl->it_type & TCE_PCI_SWINV_CREATE)) 1796decbda25SAlexey Kardashevskiy pnv_pci_ioda1_tce_invalidate(tbl, index, npages, false); 1797decbda25SAlexey Kardashevskiy 1798decbda25SAlexey Kardashevskiy return ret; 1799decbda25SAlexey Kardashevskiy } 1800decbda25SAlexey Kardashevskiy 180105c6cfb9SAlexey Kardashevskiy #ifdef CONFIG_IOMMU_API 180205c6cfb9SAlexey Kardashevskiy static int pnv_ioda1_tce_xchg(struct iommu_table *tbl, long index, 180305c6cfb9SAlexey Kardashevskiy unsigned long *hpa, enum dma_data_direction *direction) 180405c6cfb9SAlexey Kardashevskiy { 180505c6cfb9SAlexey Kardashevskiy long ret = pnv_tce_xchg(tbl, index, hpa, direction); 180605c6cfb9SAlexey Kardashevskiy 180705c6cfb9SAlexey Kardashevskiy if (!ret && (tbl->it_type & 180805c6cfb9SAlexey Kardashevskiy (TCE_PCI_SWINV_CREATE | TCE_PCI_SWINV_FREE))) 180905c6cfb9SAlexey Kardashevskiy pnv_pci_ioda1_tce_invalidate(tbl, index, 1, false); 181005c6cfb9SAlexey Kardashevskiy 181105c6cfb9SAlexey Kardashevskiy return ret; 181205c6cfb9SAlexey Kardashevskiy } 181305c6cfb9SAlexey Kardashevskiy #endif 181405c6cfb9SAlexey Kardashevskiy 1815decbda25SAlexey Kardashevskiy static void pnv_ioda1_tce_free(struct iommu_table *tbl, long index, 1816decbda25SAlexey Kardashevskiy long npages) 1817decbda25SAlexey Kardashevskiy { 1818decbda25SAlexey Kardashevskiy pnv_tce_free(tbl, index, npages); 1819decbda25SAlexey Kardashevskiy 1820decbda25SAlexey Kardashevskiy if (tbl->it_type & TCE_PCI_SWINV_FREE) 1821decbda25SAlexey Kardashevskiy pnv_pci_ioda1_tce_invalidate(tbl, index, npages, false); 1822decbda25SAlexey Kardashevskiy } 1823decbda25SAlexey Kardashevskiy 1824da004c36SAlexey Kardashevskiy static struct iommu_table_ops pnv_ioda1_iommu_ops = { 1825decbda25SAlexey Kardashevskiy .set = pnv_ioda1_tce_build, 182605c6cfb9SAlexey Kardashevskiy #ifdef CONFIG_IOMMU_API 182705c6cfb9SAlexey Kardashevskiy .exchange = pnv_ioda1_tce_xchg, 182805c6cfb9SAlexey Kardashevskiy #endif 1829decbda25SAlexey Kardashevskiy .clear = pnv_ioda1_tce_free, 1830da004c36SAlexey Kardashevskiy .get = pnv_tce_get, 1831da004c36SAlexey Kardashevskiy }; 1832da004c36SAlexey Kardashevskiy 18330bbcdb43SAlexey Kardashevskiy #define TCE_KILL_INVAL_ALL PPC_BIT(0) 1834bef9253fSAlexey Kardashevskiy #define TCE_KILL_INVAL_PE PPC_BIT(1) 1835bef9253fSAlexey Kardashevskiy #define TCE_KILL_INVAL_TCE PPC_BIT(2) 1836bef9253fSAlexey Kardashevskiy 18370bbcdb43SAlexey Kardashevskiy void pnv_pci_ioda2_tce_invalidate_entire(struct pnv_phb *phb, bool rm) 18380bbcdb43SAlexey Kardashevskiy { 18390bbcdb43SAlexey Kardashevskiy const unsigned long val = TCE_KILL_INVAL_ALL; 18400bbcdb43SAlexey Kardashevskiy 18410bbcdb43SAlexey Kardashevskiy mb(); /* Ensure previous TCE table stores are visible */ 18420bbcdb43SAlexey Kardashevskiy if (rm) 18430bbcdb43SAlexey Kardashevskiy __raw_rm_writeq(cpu_to_be64(val), 18440bbcdb43SAlexey Kardashevskiy (__be64 __iomem *) 18450bbcdb43SAlexey Kardashevskiy phb->ioda.tce_inval_reg_phys); 18460bbcdb43SAlexey Kardashevskiy else 18470bbcdb43SAlexey Kardashevskiy __raw_writeq(cpu_to_be64(val), phb->ioda.tce_inval_reg); 18480bbcdb43SAlexey Kardashevskiy } 18490bbcdb43SAlexey Kardashevskiy 1850a7cf13caSAlexey Kardashevskiy static inline void pnv_pci_ioda2_tce_invalidate_pe(struct pnv_ioda_pe *pe) 18515780fb04SAlexey Kardashevskiy { 18525780fb04SAlexey Kardashevskiy /* 01xb - invalidate TCEs that match the specified PE# */ 1853bef9253fSAlexey Kardashevskiy unsigned long val = TCE_KILL_INVAL_PE | (pe->pe_number & 0xFF); 18545780fb04SAlexey Kardashevskiy struct pnv_phb *phb = pe->phb; 18555d2aa710SAlistair Popple struct pnv_ioda_pe *npe; 18565d2aa710SAlistair Popple int i; 18575780fb04SAlexey Kardashevskiy 18585780fb04SAlexey Kardashevskiy if (!phb->ioda.tce_inval_reg) 18595780fb04SAlexey Kardashevskiy return; 18605780fb04SAlexey Kardashevskiy 18615780fb04SAlexey Kardashevskiy mb(); /* Ensure above stores are visible */ 18625780fb04SAlexey Kardashevskiy __raw_writeq(cpu_to_be64(val), phb->ioda.tce_inval_reg); 18635d2aa710SAlistair Popple 18645d2aa710SAlistair Popple if (pe->flags & PNV_IODA_PE_PEER) 18655d2aa710SAlistair Popple for (i = 0; i < PNV_IODA_MAX_PEER_PES; i++) { 18665d2aa710SAlistair Popple npe = pe->peers[i]; 18675d2aa710SAlistair Popple if (!npe || npe->phb->type != PNV_PHB_NPU) 18685d2aa710SAlistair Popple continue; 18695d2aa710SAlistair Popple 18700bbcdb43SAlexey Kardashevskiy pnv_pci_ioda2_tce_invalidate_entire(npe->phb, false); 18715d2aa710SAlistair Popple } 18725780fb04SAlexey Kardashevskiy } 18735780fb04SAlexey Kardashevskiy 1874e57080f1SAlexey Kardashevskiy static void pnv_pci_ioda2_do_tce_invalidate(unsigned pe_number, bool rm, 1875e57080f1SAlexey Kardashevskiy __be64 __iomem *invalidate, unsigned shift, 1876e57080f1SAlexey Kardashevskiy unsigned long index, unsigned long npages) 18774cce9550SGavin Shan { 18784cce9550SGavin Shan unsigned long start, end, inc; 18794cce9550SGavin Shan 18804cce9550SGavin Shan /* We'll invalidate DMA address in PE scope */ 1881bef9253fSAlexey Kardashevskiy start = TCE_KILL_INVAL_TCE; 1882e57080f1SAlexey Kardashevskiy start |= (pe_number & 0xFF); 18834cce9550SGavin Shan end = start; 18844cce9550SGavin Shan 18854cce9550SGavin Shan /* Figure out the start, end and step */ 1886decbda25SAlexey Kardashevskiy start |= (index << shift); 1887decbda25SAlexey Kardashevskiy end |= ((index + npages - 1) << shift); 1888b0376c9bSAlexey Kardashevskiy inc = (0x1ull << shift); 18894cce9550SGavin Shan mb(); 18904cce9550SGavin Shan 18914cce9550SGavin Shan while (start <= end) { 18928e0a1611SAlexey Kardashevskiy if (rm) 18933ad26e5cSBenjamin Herrenschmidt __raw_rm_writeq(cpu_to_be64(start), invalidate); 18948e0a1611SAlexey Kardashevskiy else 18953a1a4661SBenjamin Herrenschmidt __raw_writeq(cpu_to_be64(start), invalidate); 18964cce9550SGavin Shan start += inc; 18974cce9550SGavin Shan } 18984cce9550SGavin Shan } 18994cce9550SGavin Shan 1900e57080f1SAlexey Kardashevskiy static void pnv_pci_ioda2_tce_invalidate(struct iommu_table *tbl, 1901e57080f1SAlexey Kardashevskiy unsigned long index, unsigned long npages, bool rm) 1902e57080f1SAlexey Kardashevskiy { 1903e57080f1SAlexey Kardashevskiy struct iommu_table_group_link *tgl; 1904e57080f1SAlexey Kardashevskiy 1905e57080f1SAlexey Kardashevskiy list_for_each_entry_rcu(tgl, &tbl->it_group_list, next) { 19065d2aa710SAlistair Popple struct pnv_ioda_pe *npe; 1907e57080f1SAlexey Kardashevskiy struct pnv_ioda_pe *pe = container_of(tgl->table_group, 1908e57080f1SAlexey Kardashevskiy struct pnv_ioda_pe, table_group); 1909e57080f1SAlexey Kardashevskiy __be64 __iomem *invalidate = rm ? 1910e57080f1SAlexey Kardashevskiy (__be64 __iomem *)pe->phb->ioda.tce_inval_reg_phys : 1911e57080f1SAlexey Kardashevskiy pe->phb->ioda.tce_inval_reg; 19125d2aa710SAlistair Popple int i; 1913e57080f1SAlexey Kardashevskiy 1914e57080f1SAlexey Kardashevskiy pnv_pci_ioda2_do_tce_invalidate(pe->pe_number, rm, 1915e57080f1SAlexey Kardashevskiy invalidate, tbl->it_page_shift, 1916e57080f1SAlexey Kardashevskiy index, npages); 19175d2aa710SAlistair Popple 19185d2aa710SAlistair Popple if (pe->flags & PNV_IODA_PE_PEER) 19190bbcdb43SAlexey Kardashevskiy /* 19200bbcdb43SAlexey Kardashevskiy * The NVLink hardware does not support TCE kill 19210bbcdb43SAlexey Kardashevskiy * per TCE entry so we have to invalidate 19220bbcdb43SAlexey Kardashevskiy * the entire cache for it. 19230bbcdb43SAlexey Kardashevskiy */ 19245d2aa710SAlistair Popple for (i = 0; i < PNV_IODA_MAX_PEER_PES; i++) { 19255d2aa710SAlistair Popple npe = pe->peers[i]; 19260bbcdb43SAlexey Kardashevskiy if (!npe || npe->phb->type != PNV_PHB_NPU || 19270bbcdb43SAlexey Kardashevskiy !npe->phb->ioda.tce_inval_reg) 19285d2aa710SAlistair Popple continue; 19295d2aa710SAlistair Popple 19300bbcdb43SAlexey Kardashevskiy pnv_pci_ioda2_tce_invalidate_entire(npe->phb, 19310bbcdb43SAlexey Kardashevskiy rm); 19325d2aa710SAlistair Popple } 1933e57080f1SAlexey Kardashevskiy } 1934e57080f1SAlexey Kardashevskiy } 1935e57080f1SAlexey Kardashevskiy 1936decbda25SAlexey Kardashevskiy static int pnv_ioda2_tce_build(struct iommu_table *tbl, long index, 1937decbda25SAlexey Kardashevskiy long npages, unsigned long uaddr, 1938decbda25SAlexey Kardashevskiy enum dma_data_direction direction, 1939decbda25SAlexey Kardashevskiy struct dma_attrs *attrs) 19404cce9550SGavin Shan { 1941decbda25SAlexey Kardashevskiy int ret = pnv_tce_build(tbl, index, npages, uaddr, direction, 1942decbda25SAlexey Kardashevskiy attrs); 19434cce9550SGavin Shan 1944decbda25SAlexey Kardashevskiy if (!ret && (tbl->it_type & TCE_PCI_SWINV_CREATE)) 1945decbda25SAlexey Kardashevskiy pnv_pci_ioda2_tce_invalidate(tbl, index, npages, false); 1946decbda25SAlexey Kardashevskiy 1947decbda25SAlexey Kardashevskiy return ret; 1948decbda25SAlexey Kardashevskiy } 1949decbda25SAlexey Kardashevskiy 195005c6cfb9SAlexey Kardashevskiy #ifdef CONFIG_IOMMU_API 195105c6cfb9SAlexey Kardashevskiy static int pnv_ioda2_tce_xchg(struct iommu_table *tbl, long index, 195205c6cfb9SAlexey Kardashevskiy unsigned long *hpa, enum dma_data_direction *direction) 195305c6cfb9SAlexey Kardashevskiy { 195405c6cfb9SAlexey Kardashevskiy long ret = pnv_tce_xchg(tbl, index, hpa, direction); 195505c6cfb9SAlexey Kardashevskiy 195605c6cfb9SAlexey Kardashevskiy if (!ret && (tbl->it_type & 195705c6cfb9SAlexey Kardashevskiy (TCE_PCI_SWINV_CREATE | TCE_PCI_SWINV_FREE))) 195805c6cfb9SAlexey Kardashevskiy pnv_pci_ioda2_tce_invalidate(tbl, index, 1, false); 195905c6cfb9SAlexey Kardashevskiy 196005c6cfb9SAlexey Kardashevskiy return ret; 196105c6cfb9SAlexey Kardashevskiy } 196205c6cfb9SAlexey Kardashevskiy #endif 196305c6cfb9SAlexey Kardashevskiy 1964decbda25SAlexey Kardashevskiy static void pnv_ioda2_tce_free(struct iommu_table *tbl, long index, 1965decbda25SAlexey Kardashevskiy long npages) 1966decbda25SAlexey Kardashevskiy { 1967decbda25SAlexey Kardashevskiy pnv_tce_free(tbl, index, npages); 1968decbda25SAlexey Kardashevskiy 1969decbda25SAlexey Kardashevskiy if (tbl->it_type & TCE_PCI_SWINV_FREE) 1970decbda25SAlexey Kardashevskiy pnv_pci_ioda2_tce_invalidate(tbl, index, npages, false); 19714cce9550SGavin Shan } 19724cce9550SGavin Shan 19734793d65dSAlexey Kardashevskiy static void pnv_ioda2_table_free(struct iommu_table *tbl) 19744793d65dSAlexey Kardashevskiy { 19754793d65dSAlexey Kardashevskiy pnv_pci_ioda2_table_free_pages(tbl); 19764793d65dSAlexey Kardashevskiy iommu_free_table(tbl, "pnv"); 19774793d65dSAlexey Kardashevskiy } 19784793d65dSAlexey Kardashevskiy 1979da004c36SAlexey Kardashevskiy static struct iommu_table_ops pnv_ioda2_iommu_ops = { 1980decbda25SAlexey Kardashevskiy .set = pnv_ioda2_tce_build, 198105c6cfb9SAlexey Kardashevskiy #ifdef CONFIG_IOMMU_API 198205c6cfb9SAlexey Kardashevskiy .exchange = pnv_ioda2_tce_xchg, 198305c6cfb9SAlexey Kardashevskiy #endif 1984decbda25SAlexey Kardashevskiy .clear = pnv_ioda2_tce_free, 1985da004c36SAlexey Kardashevskiy .get = pnv_tce_get, 19864793d65dSAlexey Kardashevskiy .free = pnv_ioda2_table_free, 1987da004c36SAlexey Kardashevskiy }; 1988da004c36SAlexey Kardashevskiy 1989801846d1SGavin Shan static int pnv_pci_ioda_dev_dma_weight(struct pci_dev *dev, void *data) 1990801846d1SGavin Shan { 1991801846d1SGavin Shan unsigned int *weight = (unsigned int *)data; 1992801846d1SGavin Shan 1993801846d1SGavin Shan /* This is quite simplistic. The "base" weight of a device 1994801846d1SGavin Shan * is 10. 0 means no DMA is to be accounted for it. 1995801846d1SGavin Shan */ 1996801846d1SGavin Shan if (dev->hdr_type != PCI_HEADER_TYPE_NORMAL) 1997801846d1SGavin Shan return 0; 1998801846d1SGavin Shan 1999801846d1SGavin Shan if (dev->class == PCI_CLASS_SERIAL_USB_UHCI || 2000801846d1SGavin Shan dev->class == PCI_CLASS_SERIAL_USB_OHCI || 2001801846d1SGavin Shan dev->class == PCI_CLASS_SERIAL_USB_EHCI) 2002801846d1SGavin Shan *weight += 3; 2003801846d1SGavin Shan else if ((dev->class >> 8) == PCI_CLASS_STORAGE_RAID) 2004801846d1SGavin Shan *weight += 15; 2005801846d1SGavin Shan else 2006801846d1SGavin Shan *weight += 10; 2007801846d1SGavin Shan 2008801846d1SGavin Shan return 0; 2009801846d1SGavin Shan } 2010801846d1SGavin Shan 2011801846d1SGavin Shan static unsigned int pnv_pci_ioda_pe_dma_weight(struct pnv_ioda_pe *pe) 2012801846d1SGavin Shan { 2013801846d1SGavin Shan unsigned int weight = 0; 2014801846d1SGavin Shan 2015801846d1SGavin Shan /* SRIOV VF has same DMA32 weight as its PF */ 2016801846d1SGavin Shan #ifdef CONFIG_PCI_IOV 2017801846d1SGavin Shan if ((pe->flags & PNV_IODA_PE_VF) && pe->parent_dev) { 2018801846d1SGavin Shan pnv_pci_ioda_dev_dma_weight(pe->parent_dev, &weight); 2019801846d1SGavin Shan return weight; 2020801846d1SGavin Shan } 2021801846d1SGavin Shan #endif 2022801846d1SGavin Shan 2023801846d1SGavin Shan if ((pe->flags & PNV_IODA_PE_DEV) && pe->pdev) { 2024801846d1SGavin Shan pnv_pci_ioda_dev_dma_weight(pe->pdev, &weight); 2025801846d1SGavin Shan } else if ((pe->flags & PNV_IODA_PE_BUS) && pe->pbus) { 2026801846d1SGavin Shan struct pci_dev *pdev; 2027801846d1SGavin Shan 2028801846d1SGavin Shan list_for_each_entry(pdev, &pe->pbus->devices, bus_list) 2029801846d1SGavin Shan pnv_pci_ioda_dev_dma_weight(pdev, &weight); 2030801846d1SGavin Shan } else if ((pe->flags & PNV_IODA_PE_BUS_ALL) && pe->pbus) { 2031801846d1SGavin Shan pci_walk_bus(pe->pbus, pnv_pci_ioda_dev_dma_weight, &weight); 2032801846d1SGavin Shan } 2033801846d1SGavin Shan 2034801846d1SGavin Shan return weight; 2035801846d1SGavin Shan } 2036801846d1SGavin Shan 2037b30d936fSGavin Shan static void pnv_pci_ioda1_setup_dma_pe(struct pnv_phb *phb, 20382b923ed1SGavin Shan struct pnv_ioda_pe *pe) 2039184cd4a3SBenjamin Herrenschmidt { 2040184cd4a3SBenjamin Herrenschmidt 2041184cd4a3SBenjamin Herrenschmidt struct page *tce_mem = NULL; 2042184cd4a3SBenjamin Herrenschmidt struct iommu_table *tbl; 20432b923ed1SGavin Shan unsigned int weight, total_weight = 0; 20442b923ed1SGavin Shan unsigned int tce32_segsz, base, segs, avail, i; 2045184cd4a3SBenjamin Herrenschmidt int64_t rc; 2046184cd4a3SBenjamin Herrenschmidt void *addr; 2047184cd4a3SBenjamin Herrenschmidt 2048184cd4a3SBenjamin Herrenschmidt /* XXX FIXME: Handle 64-bit only DMA devices */ 2049184cd4a3SBenjamin Herrenschmidt /* XXX FIXME: Provide 64-bit DMA facilities & non-4K TCE tables etc.. */ 2050184cd4a3SBenjamin Herrenschmidt /* XXX FIXME: Allocate multi-level tables on PHB3 */ 20512b923ed1SGavin Shan weight = pnv_pci_ioda_pe_dma_weight(pe); 20522b923ed1SGavin Shan if (!weight) 20532b923ed1SGavin Shan return; 2054184cd4a3SBenjamin Herrenschmidt 20552b923ed1SGavin Shan pci_walk_bus(phb->hose->bus, pnv_pci_ioda_dev_dma_weight, 20562b923ed1SGavin Shan &total_weight); 20572b923ed1SGavin Shan segs = (weight * phb->ioda.dma32_count) / total_weight; 20582b923ed1SGavin Shan if (!segs) 20592b923ed1SGavin Shan segs = 1; 20602b923ed1SGavin Shan 20612b923ed1SGavin Shan /* 20622b923ed1SGavin Shan * Allocate contiguous DMA32 segments. We begin with the expected 20632b923ed1SGavin Shan * number of segments. With one more attempt, the number of DMA32 20642b923ed1SGavin Shan * segments to be allocated is decreased by one until one segment 20652b923ed1SGavin Shan * is allocated successfully. 20662b923ed1SGavin Shan */ 20672b923ed1SGavin Shan do { 20682b923ed1SGavin Shan for (base = 0; base <= phb->ioda.dma32_count - segs; base++) { 20692b923ed1SGavin Shan for (avail = 0, i = base; i < base + segs; i++) { 20702b923ed1SGavin Shan if (phb->ioda.dma32_segmap[i] == 20712b923ed1SGavin Shan IODA_INVALID_PE) 20722b923ed1SGavin Shan avail++; 20732b923ed1SGavin Shan } 20742b923ed1SGavin Shan 20752b923ed1SGavin Shan if (avail == segs) 20762b923ed1SGavin Shan goto found; 20772b923ed1SGavin Shan } 20782b923ed1SGavin Shan } while (--segs); 20792b923ed1SGavin Shan 20802b923ed1SGavin Shan if (!segs) { 20812b923ed1SGavin Shan pe_warn(pe, "No available DMA32 segments\n"); 20822b923ed1SGavin Shan return; 20832b923ed1SGavin Shan } 20842b923ed1SGavin Shan 20852b923ed1SGavin Shan found: 20860eaf4defSAlexey Kardashevskiy tbl = pnv_pci_table_alloc(phb->hose->node); 2087b348aa65SAlexey Kardashevskiy iommu_register_group(&pe->table_group, phb->hose->global_number, 2088b348aa65SAlexey Kardashevskiy pe->pe_number); 20890eaf4defSAlexey Kardashevskiy pnv_pci_link_table_and_group(phb->hose->node, 0, tbl, &pe->table_group); 2090c5773822SAlexey Kardashevskiy 2091184cd4a3SBenjamin Herrenschmidt /* Grab a 32-bit TCE table */ 20922b923ed1SGavin Shan pe_info(pe, "DMA weight %d (%d), assigned (%d) %d DMA32 segments\n", 20932b923ed1SGavin Shan weight, total_weight, base, segs); 2094184cd4a3SBenjamin Herrenschmidt pe_info(pe, " Setting up 32-bit TCE table at %08x..%08x\n", 2095acce971cSGavin Shan base * PNV_IODA1_DMA32_SEGSIZE, 2096acce971cSGavin Shan (base + segs) * PNV_IODA1_DMA32_SEGSIZE - 1); 2097184cd4a3SBenjamin Herrenschmidt 2098184cd4a3SBenjamin Herrenschmidt /* XXX Currently, we allocate one big contiguous table for the 2099184cd4a3SBenjamin Herrenschmidt * TCEs. We only really need one chunk per 256M of TCE space 2100184cd4a3SBenjamin Herrenschmidt * (ie per segment) but that's an optimization for later, it 2101184cd4a3SBenjamin Herrenschmidt * requires some added smarts with our get/put_tce implementation 2102acce971cSGavin Shan * 2103acce971cSGavin Shan * Each TCE page is 4KB in size and each TCE entry occupies 8 2104acce971cSGavin Shan * bytes 2105184cd4a3SBenjamin Herrenschmidt */ 2106acce971cSGavin Shan tce32_segsz = PNV_IODA1_DMA32_SEGSIZE >> (IOMMU_PAGE_SHIFT_4K - 3); 2107184cd4a3SBenjamin Herrenschmidt tce_mem = alloc_pages_node(phb->hose->node, GFP_KERNEL, 2108acce971cSGavin Shan get_order(tce32_segsz * segs)); 2109184cd4a3SBenjamin Herrenschmidt if (!tce_mem) { 2110184cd4a3SBenjamin Herrenschmidt pe_err(pe, " Failed to allocate a 32-bit TCE memory\n"); 2111184cd4a3SBenjamin Herrenschmidt goto fail; 2112184cd4a3SBenjamin Herrenschmidt } 2113184cd4a3SBenjamin Herrenschmidt addr = page_address(tce_mem); 2114acce971cSGavin Shan memset(addr, 0, tce32_segsz * segs); 2115184cd4a3SBenjamin Herrenschmidt 2116184cd4a3SBenjamin Herrenschmidt /* Configure HW */ 2117184cd4a3SBenjamin Herrenschmidt for (i = 0; i < segs; i++) { 2118184cd4a3SBenjamin Herrenschmidt rc = opal_pci_map_pe_dma_window(phb->opal_id, 2119184cd4a3SBenjamin Herrenschmidt pe->pe_number, 2120184cd4a3SBenjamin Herrenschmidt base + i, 1, 2121acce971cSGavin Shan __pa(addr) + tce32_segsz * i, 2122acce971cSGavin Shan tce32_segsz, IOMMU_PAGE_SIZE_4K); 2123184cd4a3SBenjamin Herrenschmidt if (rc) { 2124184cd4a3SBenjamin Herrenschmidt pe_err(pe, " Failed to configure 32-bit TCE table," 2125184cd4a3SBenjamin Herrenschmidt " err %ld\n", rc); 2126184cd4a3SBenjamin Herrenschmidt goto fail; 2127184cd4a3SBenjamin Herrenschmidt } 2128184cd4a3SBenjamin Herrenschmidt } 2129184cd4a3SBenjamin Herrenschmidt 21302b923ed1SGavin Shan /* Setup DMA32 segment mapping */ 21312b923ed1SGavin Shan for (i = base; i < base + segs; i++) 21322b923ed1SGavin Shan phb->ioda.dma32_segmap[i] = pe->pe_number; 21332b923ed1SGavin Shan 2134184cd4a3SBenjamin Herrenschmidt /* Setup linux iommu table */ 2135acce971cSGavin Shan pnv_pci_setup_iommu_table(tbl, addr, tce32_segsz * segs, 2136acce971cSGavin Shan base * PNV_IODA1_DMA32_SEGSIZE, 2137acce971cSGavin Shan IOMMU_PAGE_SHIFT_4K); 2138184cd4a3SBenjamin Herrenschmidt 2139184cd4a3SBenjamin Herrenschmidt /* OPAL variant of P7IOC SW invalidated TCEs */ 21405780fb04SAlexey Kardashevskiy if (phb->ioda.tce_inval_reg) 214165fd766bSGavin Shan tbl->it_type |= (TCE_PCI_SWINV_CREATE | 214265fd766bSGavin Shan TCE_PCI_SWINV_FREE | 214365fd766bSGavin Shan TCE_PCI_SWINV_PAIR); 21445780fb04SAlexey Kardashevskiy 2145da004c36SAlexey Kardashevskiy tbl->it_ops = &pnv_ioda1_iommu_ops; 21464793d65dSAlexey Kardashevskiy pe->table_group.tce32_start = tbl->it_offset << tbl->it_page_shift; 21474793d65dSAlexey Kardashevskiy pe->table_group.tce32_size = tbl->it_size << tbl->it_page_shift; 2148184cd4a3SBenjamin Herrenschmidt iommu_init_table(tbl, phb->hose->node); 2149184cd4a3SBenjamin Herrenschmidt 2150781a868fSWei Yang if (pe->flags & PNV_IODA_PE_DEV) { 21514617082eSAlexey Kardashevskiy /* 21524617082eSAlexey Kardashevskiy * Setting table base here only for carrying iommu_group 21534617082eSAlexey Kardashevskiy * further down to let iommu_add_device() do the job. 21544617082eSAlexey Kardashevskiy * pnv_pci_ioda_dma_dev_setup will override it later anyway. 21554617082eSAlexey Kardashevskiy */ 21564617082eSAlexey Kardashevskiy set_iommu_table_base(&pe->pdev->dev, tbl); 21574617082eSAlexey Kardashevskiy iommu_add_device(&pe->pdev->dev); 2158c5773822SAlexey Kardashevskiy } else if (pe->flags & (PNV_IODA_PE_BUS | PNV_IODA_PE_BUS_ALL)) 2159ea30e99eSAlexey Kardashevskiy pnv_ioda_setup_bus_dma(pe, pe->pbus); 216074251fe2SBenjamin Herrenschmidt 2161184cd4a3SBenjamin Herrenschmidt return; 2162184cd4a3SBenjamin Herrenschmidt fail: 2163184cd4a3SBenjamin Herrenschmidt /* XXX Failure: Try to fallback to 64-bit only ? */ 2164184cd4a3SBenjamin Herrenschmidt if (tce_mem) 2165acce971cSGavin Shan __free_pages(tce_mem, get_order(tce32_segsz * segs)); 21660eaf4defSAlexey Kardashevskiy if (tbl) { 21670eaf4defSAlexey Kardashevskiy pnv_pci_unlink_table_and_group(tbl, &pe->table_group); 21680eaf4defSAlexey Kardashevskiy iommu_free_table(tbl, "pnv"); 21690eaf4defSAlexey Kardashevskiy } 2170184cd4a3SBenjamin Herrenschmidt } 2171184cd4a3SBenjamin Herrenschmidt 217243cb60abSAlexey Kardashevskiy static long pnv_pci_ioda2_set_window(struct iommu_table_group *table_group, 217343cb60abSAlexey Kardashevskiy int num, struct iommu_table *tbl) 217443cb60abSAlexey Kardashevskiy { 217543cb60abSAlexey Kardashevskiy struct pnv_ioda_pe *pe = container_of(table_group, struct pnv_ioda_pe, 217643cb60abSAlexey Kardashevskiy table_group); 217743cb60abSAlexey Kardashevskiy struct pnv_phb *phb = pe->phb; 217843cb60abSAlexey Kardashevskiy int64_t rc; 2179bbb845c4SAlexey Kardashevskiy const unsigned long size = tbl->it_indirect_levels ? 2180bbb845c4SAlexey Kardashevskiy tbl->it_level_size : tbl->it_size; 218143cb60abSAlexey Kardashevskiy const __u64 start_addr = tbl->it_offset << tbl->it_page_shift; 218243cb60abSAlexey Kardashevskiy const __u64 win_size = tbl->it_size << tbl->it_page_shift; 218343cb60abSAlexey Kardashevskiy 21844793d65dSAlexey Kardashevskiy pe_info(pe, "Setting up window#%d %llx..%llx pg=%x\n", num, 218543cb60abSAlexey Kardashevskiy start_addr, start_addr + win_size - 1, 218643cb60abSAlexey Kardashevskiy IOMMU_PAGE_SIZE(tbl)); 218743cb60abSAlexey Kardashevskiy 218843cb60abSAlexey Kardashevskiy /* 218943cb60abSAlexey Kardashevskiy * Map TCE table through TVT. The TVE index is the PE number 219043cb60abSAlexey Kardashevskiy * shifted by 1 bit for 32-bits DMA space. 219143cb60abSAlexey Kardashevskiy */ 219243cb60abSAlexey Kardashevskiy rc = opal_pci_map_pe_dma_window(phb->opal_id, 219343cb60abSAlexey Kardashevskiy pe->pe_number, 21944793d65dSAlexey Kardashevskiy (pe->pe_number << 1) + num, 2195bbb845c4SAlexey Kardashevskiy tbl->it_indirect_levels + 1, 219643cb60abSAlexey Kardashevskiy __pa(tbl->it_base), 2197bbb845c4SAlexey Kardashevskiy size << 3, 219843cb60abSAlexey Kardashevskiy IOMMU_PAGE_SIZE(tbl)); 219943cb60abSAlexey Kardashevskiy if (rc) { 220043cb60abSAlexey Kardashevskiy pe_err(pe, "Failed to configure TCE table, err %ld\n", rc); 220143cb60abSAlexey Kardashevskiy return rc; 220243cb60abSAlexey Kardashevskiy } 220343cb60abSAlexey Kardashevskiy 220443cb60abSAlexey Kardashevskiy pnv_pci_link_table_and_group(phb->hose->node, num, 220543cb60abSAlexey Kardashevskiy tbl, &pe->table_group); 2206a7cf13caSAlexey Kardashevskiy pnv_pci_ioda2_tce_invalidate_pe(pe); 220743cb60abSAlexey Kardashevskiy 220843cb60abSAlexey Kardashevskiy return 0; 220943cb60abSAlexey Kardashevskiy } 221043cb60abSAlexey Kardashevskiy 2211f87a8864SAlexey Kardashevskiy static void pnv_pci_ioda2_set_bypass(struct pnv_ioda_pe *pe, bool enable) 2212cd15b048SBenjamin Herrenschmidt { 2213cd15b048SBenjamin Herrenschmidt uint16_t window_id = (pe->pe_number << 1 ) + 1; 2214cd15b048SBenjamin Herrenschmidt int64_t rc; 2215cd15b048SBenjamin Herrenschmidt 2216cd15b048SBenjamin Herrenschmidt pe_info(pe, "%sabling 64-bit DMA bypass\n", enable ? "En" : "Dis"); 2217cd15b048SBenjamin Herrenschmidt if (enable) { 2218cd15b048SBenjamin Herrenschmidt phys_addr_t top = memblock_end_of_DRAM(); 2219cd15b048SBenjamin Herrenschmidt 2220cd15b048SBenjamin Herrenschmidt top = roundup_pow_of_two(top); 2221cd15b048SBenjamin Herrenschmidt rc = opal_pci_map_pe_dma_window_real(pe->phb->opal_id, 2222cd15b048SBenjamin Herrenschmidt pe->pe_number, 2223cd15b048SBenjamin Herrenschmidt window_id, 2224cd15b048SBenjamin Herrenschmidt pe->tce_bypass_base, 2225cd15b048SBenjamin Herrenschmidt top); 2226cd15b048SBenjamin Herrenschmidt } else { 2227cd15b048SBenjamin Herrenschmidt rc = opal_pci_map_pe_dma_window_real(pe->phb->opal_id, 2228cd15b048SBenjamin Herrenschmidt pe->pe_number, 2229cd15b048SBenjamin Herrenschmidt window_id, 2230cd15b048SBenjamin Herrenschmidt pe->tce_bypass_base, 2231cd15b048SBenjamin Herrenschmidt 0); 2232cd15b048SBenjamin Herrenschmidt } 2233cd15b048SBenjamin Herrenschmidt if (rc) 2234cd15b048SBenjamin Herrenschmidt pe_err(pe, "OPAL error %lld configuring bypass window\n", rc); 2235cd15b048SBenjamin Herrenschmidt else 2236cd15b048SBenjamin Herrenschmidt pe->tce_bypass_enabled = enable; 2237cd15b048SBenjamin Herrenschmidt } 2238cd15b048SBenjamin Herrenschmidt 22394793d65dSAlexey Kardashevskiy static long pnv_pci_ioda2_table_alloc_pages(int nid, __u64 bus_offset, 22404793d65dSAlexey Kardashevskiy __u32 page_shift, __u64 window_size, __u32 levels, 22414793d65dSAlexey Kardashevskiy struct iommu_table *tbl); 22424793d65dSAlexey Kardashevskiy 22434793d65dSAlexey Kardashevskiy static long pnv_pci_ioda2_create_table(struct iommu_table_group *table_group, 22444793d65dSAlexey Kardashevskiy int num, __u32 page_shift, __u64 window_size, __u32 levels, 22454793d65dSAlexey Kardashevskiy struct iommu_table **ptbl) 22464793d65dSAlexey Kardashevskiy { 22474793d65dSAlexey Kardashevskiy struct pnv_ioda_pe *pe = container_of(table_group, struct pnv_ioda_pe, 22484793d65dSAlexey Kardashevskiy table_group); 22494793d65dSAlexey Kardashevskiy int nid = pe->phb->hose->node; 22504793d65dSAlexey Kardashevskiy __u64 bus_offset = num ? pe->tce_bypass_base : table_group->tce32_start; 22514793d65dSAlexey Kardashevskiy long ret; 22524793d65dSAlexey Kardashevskiy struct iommu_table *tbl; 22534793d65dSAlexey Kardashevskiy 22544793d65dSAlexey Kardashevskiy tbl = pnv_pci_table_alloc(nid); 22554793d65dSAlexey Kardashevskiy if (!tbl) 22564793d65dSAlexey Kardashevskiy return -ENOMEM; 22574793d65dSAlexey Kardashevskiy 22584793d65dSAlexey Kardashevskiy ret = pnv_pci_ioda2_table_alloc_pages(nid, 22594793d65dSAlexey Kardashevskiy bus_offset, page_shift, window_size, 22604793d65dSAlexey Kardashevskiy levels, tbl); 22614793d65dSAlexey Kardashevskiy if (ret) { 22624793d65dSAlexey Kardashevskiy iommu_free_table(tbl, "pnv"); 22634793d65dSAlexey Kardashevskiy return ret; 22644793d65dSAlexey Kardashevskiy } 22654793d65dSAlexey Kardashevskiy 22664793d65dSAlexey Kardashevskiy tbl->it_ops = &pnv_ioda2_iommu_ops; 22674793d65dSAlexey Kardashevskiy if (pe->phb->ioda.tce_inval_reg) 22684793d65dSAlexey Kardashevskiy tbl->it_type |= (TCE_PCI_SWINV_CREATE | TCE_PCI_SWINV_FREE); 22694793d65dSAlexey Kardashevskiy 22704793d65dSAlexey Kardashevskiy *ptbl = tbl; 22714793d65dSAlexey Kardashevskiy 22724793d65dSAlexey Kardashevskiy return 0; 22734793d65dSAlexey Kardashevskiy } 22744793d65dSAlexey Kardashevskiy 227546d3e1e1SAlexey Kardashevskiy static long pnv_pci_ioda2_setup_default_config(struct pnv_ioda_pe *pe) 227646d3e1e1SAlexey Kardashevskiy { 227746d3e1e1SAlexey Kardashevskiy struct iommu_table *tbl = NULL; 227846d3e1e1SAlexey Kardashevskiy long rc; 227946d3e1e1SAlexey Kardashevskiy 2280bb005455SNishanth Aravamudan /* 2281fa144869SNishanth Aravamudan * crashkernel= specifies the kdump kernel's maximum memory at 2282fa144869SNishanth Aravamudan * some offset and there is no guaranteed the result is a power 2283fa144869SNishanth Aravamudan * of 2, which will cause errors later. 2284fa144869SNishanth Aravamudan */ 2285fa144869SNishanth Aravamudan const u64 max_memory = __rounddown_pow_of_two(memory_hotplug_max()); 2286fa144869SNishanth Aravamudan 2287fa144869SNishanth Aravamudan /* 2288bb005455SNishanth Aravamudan * In memory constrained environments, e.g. kdump kernel, the 2289bb005455SNishanth Aravamudan * DMA window can be larger than available memory, which will 2290bb005455SNishanth Aravamudan * cause errors later. 2291bb005455SNishanth Aravamudan */ 2292fa144869SNishanth Aravamudan const u64 window_size = min((u64)pe->table_group.tce32_size, max_memory); 2293bb005455SNishanth Aravamudan 229446d3e1e1SAlexey Kardashevskiy rc = pnv_pci_ioda2_create_table(&pe->table_group, 0, 229546d3e1e1SAlexey Kardashevskiy IOMMU_PAGE_SHIFT_4K, 2296bb005455SNishanth Aravamudan window_size, 229746d3e1e1SAlexey Kardashevskiy POWERNV_IOMMU_DEFAULT_LEVELS, &tbl); 229846d3e1e1SAlexey Kardashevskiy if (rc) { 229946d3e1e1SAlexey Kardashevskiy pe_err(pe, "Failed to create 32-bit TCE table, err %ld", 230046d3e1e1SAlexey Kardashevskiy rc); 230146d3e1e1SAlexey Kardashevskiy return rc; 230246d3e1e1SAlexey Kardashevskiy } 230346d3e1e1SAlexey Kardashevskiy 230446d3e1e1SAlexey Kardashevskiy iommu_init_table(tbl, pe->phb->hose->node); 230546d3e1e1SAlexey Kardashevskiy 230646d3e1e1SAlexey Kardashevskiy rc = pnv_pci_ioda2_set_window(&pe->table_group, 0, tbl); 230746d3e1e1SAlexey Kardashevskiy if (rc) { 230846d3e1e1SAlexey Kardashevskiy pe_err(pe, "Failed to configure 32-bit TCE table, err %ld\n", 230946d3e1e1SAlexey Kardashevskiy rc); 231046d3e1e1SAlexey Kardashevskiy pnv_ioda2_table_free(tbl); 231146d3e1e1SAlexey Kardashevskiy return rc; 231246d3e1e1SAlexey Kardashevskiy } 231346d3e1e1SAlexey Kardashevskiy 231446d3e1e1SAlexey Kardashevskiy if (!pnv_iommu_bypass_disabled) 231546d3e1e1SAlexey Kardashevskiy pnv_pci_ioda2_set_bypass(pe, true); 231646d3e1e1SAlexey Kardashevskiy 231746d3e1e1SAlexey Kardashevskiy /* OPAL variant of PHB3 invalidated TCEs */ 231846d3e1e1SAlexey Kardashevskiy if (pe->phb->ioda.tce_inval_reg) 231946d3e1e1SAlexey Kardashevskiy tbl->it_type |= (TCE_PCI_SWINV_CREATE | TCE_PCI_SWINV_FREE); 232046d3e1e1SAlexey Kardashevskiy 232146d3e1e1SAlexey Kardashevskiy /* 232246d3e1e1SAlexey Kardashevskiy * Setting table base here only for carrying iommu_group 232346d3e1e1SAlexey Kardashevskiy * further down to let iommu_add_device() do the job. 232446d3e1e1SAlexey Kardashevskiy * pnv_pci_ioda_dma_dev_setup will override it later anyway. 232546d3e1e1SAlexey Kardashevskiy */ 232646d3e1e1SAlexey Kardashevskiy if (pe->flags & PNV_IODA_PE_DEV) 232746d3e1e1SAlexey Kardashevskiy set_iommu_table_base(&pe->pdev->dev, tbl); 232846d3e1e1SAlexey Kardashevskiy 232946d3e1e1SAlexey Kardashevskiy return 0; 233046d3e1e1SAlexey Kardashevskiy } 233146d3e1e1SAlexey Kardashevskiy 2332b5926430SAlexey Kardashevskiy #if defined(CONFIG_IOMMU_API) || defined(CONFIG_PCI_IOV) 2333b5926430SAlexey Kardashevskiy static long pnv_pci_ioda2_unset_window(struct iommu_table_group *table_group, 2334b5926430SAlexey Kardashevskiy int num) 2335b5926430SAlexey Kardashevskiy { 2336b5926430SAlexey Kardashevskiy struct pnv_ioda_pe *pe = container_of(table_group, struct pnv_ioda_pe, 2337b5926430SAlexey Kardashevskiy table_group); 2338b5926430SAlexey Kardashevskiy struct pnv_phb *phb = pe->phb; 2339b5926430SAlexey Kardashevskiy long ret; 2340b5926430SAlexey Kardashevskiy 2341b5926430SAlexey Kardashevskiy pe_info(pe, "Removing DMA window #%d\n", num); 2342b5926430SAlexey Kardashevskiy 2343b5926430SAlexey Kardashevskiy ret = opal_pci_map_pe_dma_window(phb->opal_id, pe->pe_number, 2344b5926430SAlexey Kardashevskiy (pe->pe_number << 1) + num, 2345b5926430SAlexey Kardashevskiy 0/* levels */, 0/* table address */, 2346b5926430SAlexey Kardashevskiy 0/* table size */, 0/* page size */); 2347b5926430SAlexey Kardashevskiy if (ret) 2348b5926430SAlexey Kardashevskiy pe_warn(pe, "Unmapping failed, ret = %ld\n", ret); 2349b5926430SAlexey Kardashevskiy else 2350a7cf13caSAlexey Kardashevskiy pnv_pci_ioda2_tce_invalidate_pe(pe); 2351b5926430SAlexey Kardashevskiy 2352b5926430SAlexey Kardashevskiy pnv_pci_unlink_table_and_group(table_group->tables[num], table_group); 2353b5926430SAlexey Kardashevskiy 2354b5926430SAlexey Kardashevskiy return ret; 2355b5926430SAlexey Kardashevskiy } 2356b5926430SAlexey Kardashevskiy #endif 2357b5926430SAlexey Kardashevskiy 2358f87a8864SAlexey Kardashevskiy #ifdef CONFIG_IOMMU_API 235900547193SAlexey Kardashevskiy static unsigned long pnv_pci_ioda2_get_table_size(__u32 page_shift, 236000547193SAlexey Kardashevskiy __u64 window_size, __u32 levels) 236100547193SAlexey Kardashevskiy { 236200547193SAlexey Kardashevskiy unsigned long bytes = 0; 236300547193SAlexey Kardashevskiy const unsigned window_shift = ilog2(window_size); 236400547193SAlexey Kardashevskiy unsigned entries_shift = window_shift - page_shift; 236500547193SAlexey Kardashevskiy unsigned table_shift = entries_shift + 3; 236600547193SAlexey Kardashevskiy unsigned long tce_table_size = max(0x1000UL, 1UL << table_shift); 236700547193SAlexey Kardashevskiy unsigned long direct_table_size; 236800547193SAlexey Kardashevskiy 236900547193SAlexey Kardashevskiy if (!levels || (levels > POWERNV_IOMMU_MAX_LEVELS) || 237000547193SAlexey Kardashevskiy (window_size > memory_hotplug_max()) || 237100547193SAlexey Kardashevskiy !is_power_of_2(window_size)) 237200547193SAlexey Kardashevskiy return 0; 237300547193SAlexey Kardashevskiy 237400547193SAlexey Kardashevskiy /* Calculate a direct table size from window_size and levels */ 237500547193SAlexey Kardashevskiy entries_shift = (entries_shift + levels - 1) / levels; 237600547193SAlexey Kardashevskiy table_shift = entries_shift + 3; 237700547193SAlexey Kardashevskiy table_shift = max_t(unsigned, table_shift, PAGE_SHIFT); 237800547193SAlexey Kardashevskiy direct_table_size = 1UL << table_shift; 237900547193SAlexey Kardashevskiy 238000547193SAlexey Kardashevskiy for ( ; levels; --levels) { 238100547193SAlexey Kardashevskiy bytes += _ALIGN_UP(tce_table_size, direct_table_size); 238200547193SAlexey Kardashevskiy 238300547193SAlexey Kardashevskiy tce_table_size /= direct_table_size; 238400547193SAlexey Kardashevskiy tce_table_size <<= 3; 238500547193SAlexey Kardashevskiy tce_table_size = _ALIGN_UP(tce_table_size, direct_table_size); 238600547193SAlexey Kardashevskiy } 238700547193SAlexey Kardashevskiy 238800547193SAlexey Kardashevskiy return bytes; 238900547193SAlexey Kardashevskiy } 239000547193SAlexey Kardashevskiy 2391f87a8864SAlexey Kardashevskiy static void pnv_ioda2_take_ownership(struct iommu_table_group *table_group) 2392cd15b048SBenjamin Herrenschmidt { 2393f87a8864SAlexey Kardashevskiy struct pnv_ioda_pe *pe = container_of(table_group, struct pnv_ioda_pe, 2394f87a8864SAlexey Kardashevskiy table_group); 239546d3e1e1SAlexey Kardashevskiy /* Store @tbl as pnv_pci_ioda2_unset_window() resets it */ 239646d3e1e1SAlexey Kardashevskiy struct iommu_table *tbl = pe->table_group.tables[0]; 2397cd15b048SBenjamin Herrenschmidt 2398f87a8864SAlexey Kardashevskiy pnv_pci_ioda2_set_bypass(pe, false); 239946d3e1e1SAlexey Kardashevskiy pnv_pci_ioda2_unset_window(&pe->table_group, 0); 240046d3e1e1SAlexey Kardashevskiy pnv_ioda2_table_free(tbl); 2401cd15b048SBenjamin Herrenschmidt } 2402cd15b048SBenjamin Herrenschmidt 2403f87a8864SAlexey Kardashevskiy static void pnv_ioda2_release_ownership(struct iommu_table_group *table_group) 2404f87a8864SAlexey Kardashevskiy { 2405f87a8864SAlexey Kardashevskiy struct pnv_ioda_pe *pe = container_of(table_group, struct pnv_ioda_pe, 2406f87a8864SAlexey Kardashevskiy table_group); 2407f87a8864SAlexey Kardashevskiy 240846d3e1e1SAlexey Kardashevskiy pnv_pci_ioda2_setup_default_config(pe); 2409f87a8864SAlexey Kardashevskiy } 2410f87a8864SAlexey Kardashevskiy 2411f87a8864SAlexey Kardashevskiy static struct iommu_table_group_ops pnv_pci_ioda2_ops = { 241200547193SAlexey Kardashevskiy .get_table_size = pnv_pci_ioda2_get_table_size, 24134793d65dSAlexey Kardashevskiy .create_table = pnv_pci_ioda2_create_table, 24144793d65dSAlexey Kardashevskiy .set_window = pnv_pci_ioda2_set_window, 24154793d65dSAlexey Kardashevskiy .unset_window = pnv_pci_ioda2_unset_window, 2416f87a8864SAlexey Kardashevskiy .take_ownership = pnv_ioda2_take_ownership, 2417f87a8864SAlexey Kardashevskiy .release_ownership = pnv_ioda2_release_ownership, 2418f87a8864SAlexey Kardashevskiy }; 2419f87a8864SAlexey Kardashevskiy #endif 2420f87a8864SAlexey Kardashevskiy 24215780fb04SAlexey Kardashevskiy static void pnv_pci_ioda_setup_opal_tce_kill(struct pnv_phb *phb) 24225780fb04SAlexey Kardashevskiy { 24235780fb04SAlexey Kardashevskiy const __be64 *swinvp; 24245780fb04SAlexey Kardashevskiy 24255780fb04SAlexey Kardashevskiy /* OPAL variant of PHB3 invalidated TCEs */ 24265780fb04SAlexey Kardashevskiy swinvp = of_get_property(phb->hose->dn, "ibm,opal-tce-kill", NULL); 24275780fb04SAlexey Kardashevskiy if (!swinvp) 24285780fb04SAlexey Kardashevskiy return; 24295780fb04SAlexey Kardashevskiy 24305780fb04SAlexey Kardashevskiy phb->ioda.tce_inval_reg_phys = be64_to_cpup(swinvp); 24315780fb04SAlexey Kardashevskiy phb->ioda.tce_inval_reg = ioremap(phb->ioda.tce_inval_reg_phys, 8); 24325780fb04SAlexey Kardashevskiy } 24335780fb04SAlexey Kardashevskiy 2434bbb845c4SAlexey Kardashevskiy static __be64 *pnv_pci_ioda2_table_do_alloc_pages(int nid, unsigned shift, 2435bbb845c4SAlexey Kardashevskiy unsigned levels, unsigned long limit, 24363ba3a73eSAlexey Kardashevskiy unsigned long *current_offset, unsigned long *total_allocated) 2437aca6913fSAlexey Kardashevskiy { 2438aca6913fSAlexey Kardashevskiy struct page *tce_mem = NULL; 2439bbb845c4SAlexey Kardashevskiy __be64 *addr, *tmp; 2440aca6913fSAlexey Kardashevskiy unsigned order = max_t(unsigned, shift, PAGE_SHIFT) - PAGE_SHIFT; 2441bbb845c4SAlexey Kardashevskiy unsigned long allocated = 1UL << (order + PAGE_SHIFT); 2442bbb845c4SAlexey Kardashevskiy unsigned entries = 1UL << (shift - 3); 2443bbb845c4SAlexey Kardashevskiy long i; 2444aca6913fSAlexey Kardashevskiy 2445aca6913fSAlexey Kardashevskiy tce_mem = alloc_pages_node(nid, GFP_KERNEL, order); 2446aca6913fSAlexey Kardashevskiy if (!tce_mem) { 2447aca6913fSAlexey Kardashevskiy pr_err("Failed to allocate a TCE memory, order=%d\n", order); 2448aca6913fSAlexey Kardashevskiy return NULL; 2449aca6913fSAlexey Kardashevskiy } 2450aca6913fSAlexey Kardashevskiy addr = page_address(tce_mem); 2451bbb845c4SAlexey Kardashevskiy memset(addr, 0, allocated); 24523ba3a73eSAlexey Kardashevskiy *total_allocated += allocated; 2453bbb845c4SAlexey Kardashevskiy 2454bbb845c4SAlexey Kardashevskiy --levels; 2455bbb845c4SAlexey Kardashevskiy if (!levels) { 2456bbb845c4SAlexey Kardashevskiy *current_offset += allocated; 2457bbb845c4SAlexey Kardashevskiy return addr; 2458bbb845c4SAlexey Kardashevskiy } 2459bbb845c4SAlexey Kardashevskiy 2460bbb845c4SAlexey Kardashevskiy for (i = 0; i < entries; ++i) { 2461bbb845c4SAlexey Kardashevskiy tmp = pnv_pci_ioda2_table_do_alloc_pages(nid, shift, 24623ba3a73eSAlexey Kardashevskiy levels, limit, current_offset, total_allocated); 2463bbb845c4SAlexey Kardashevskiy if (!tmp) 2464bbb845c4SAlexey Kardashevskiy break; 2465bbb845c4SAlexey Kardashevskiy 2466bbb845c4SAlexey Kardashevskiy addr[i] = cpu_to_be64(__pa(tmp) | 2467bbb845c4SAlexey Kardashevskiy TCE_PCI_READ | TCE_PCI_WRITE); 2468bbb845c4SAlexey Kardashevskiy 2469bbb845c4SAlexey Kardashevskiy if (*current_offset >= limit) 2470bbb845c4SAlexey Kardashevskiy break; 2471bbb845c4SAlexey Kardashevskiy } 2472aca6913fSAlexey Kardashevskiy 2473aca6913fSAlexey Kardashevskiy return addr; 2474aca6913fSAlexey Kardashevskiy } 2475aca6913fSAlexey Kardashevskiy 2476bbb845c4SAlexey Kardashevskiy static void pnv_pci_ioda2_table_do_free_pages(__be64 *addr, 2477bbb845c4SAlexey Kardashevskiy unsigned long size, unsigned level); 2478bbb845c4SAlexey Kardashevskiy 2479aca6913fSAlexey Kardashevskiy static long pnv_pci_ioda2_table_alloc_pages(int nid, __u64 bus_offset, 2480bbb845c4SAlexey Kardashevskiy __u32 page_shift, __u64 window_size, __u32 levels, 2481bbb845c4SAlexey Kardashevskiy struct iommu_table *tbl) 2482aca6913fSAlexey Kardashevskiy { 2483aca6913fSAlexey Kardashevskiy void *addr; 24843ba3a73eSAlexey Kardashevskiy unsigned long offset = 0, level_shift, total_allocated = 0; 2485aca6913fSAlexey Kardashevskiy const unsigned window_shift = ilog2(window_size); 2486aca6913fSAlexey Kardashevskiy unsigned entries_shift = window_shift - page_shift; 2487aca6913fSAlexey Kardashevskiy unsigned table_shift = max_t(unsigned, entries_shift + 3, PAGE_SHIFT); 2488aca6913fSAlexey Kardashevskiy const unsigned long tce_table_size = 1UL << table_shift; 2489aca6913fSAlexey Kardashevskiy 2490bbb845c4SAlexey Kardashevskiy if (!levels || (levels > POWERNV_IOMMU_MAX_LEVELS)) 2491bbb845c4SAlexey Kardashevskiy return -EINVAL; 2492bbb845c4SAlexey Kardashevskiy 2493aca6913fSAlexey Kardashevskiy if ((window_size > memory_hotplug_max()) || !is_power_of_2(window_size)) 2494aca6913fSAlexey Kardashevskiy return -EINVAL; 2495aca6913fSAlexey Kardashevskiy 2496bbb845c4SAlexey Kardashevskiy /* Adjust direct table size from window_size and levels */ 2497bbb845c4SAlexey Kardashevskiy entries_shift = (entries_shift + levels - 1) / levels; 2498bbb845c4SAlexey Kardashevskiy level_shift = entries_shift + 3; 2499bbb845c4SAlexey Kardashevskiy level_shift = max_t(unsigned, level_shift, PAGE_SHIFT); 2500bbb845c4SAlexey Kardashevskiy 2501aca6913fSAlexey Kardashevskiy /* Allocate TCE table */ 2502bbb845c4SAlexey Kardashevskiy addr = pnv_pci_ioda2_table_do_alloc_pages(nid, level_shift, 25033ba3a73eSAlexey Kardashevskiy levels, tce_table_size, &offset, &total_allocated); 2504bbb845c4SAlexey Kardashevskiy 2505bbb845c4SAlexey Kardashevskiy /* addr==NULL means that the first level allocation failed */ 2506aca6913fSAlexey Kardashevskiy if (!addr) 2507aca6913fSAlexey Kardashevskiy return -ENOMEM; 2508aca6913fSAlexey Kardashevskiy 2509bbb845c4SAlexey Kardashevskiy /* 2510bbb845c4SAlexey Kardashevskiy * First level was allocated but some lower level failed as 2511bbb845c4SAlexey Kardashevskiy * we did not allocate as much as we wanted, 2512bbb845c4SAlexey Kardashevskiy * release partially allocated table. 2513bbb845c4SAlexey Kardashevskiy */ 2514bbb845c4SAlexey Kardashevskiy if (offset < tce_table_size) { 2515bbb845c4SAlexey Kardashevskiy pnv_pci_ioda2_table_do_free_pages(addr, 2516bbb845c4SAlexey Kardashevskiy 1ULL << (level_shift - 3), levels - 1); 2517bbb845c4SAlexey Kardashevskiy return -ENOMEM; 2518bbb845c4SAlexey Kardashevskiy } 2519bbb845c4SAlexey Kardashevskiy 2520aca6913fSAlexey Kardashevskiy /* Setup linux iommu table */ 2521aca6913fSAlexey Kardashevskiy pnv_pci_setup_iommu_table(tbl, addr, tce_table_size, bus_offset, 2522aca6913fSAlexey Kardashevskiy page_shift); 2523bbb845c4SAlexey Kardashevskiy tbl->it_level_size = 1ULL << (level_shift - 3); 2524bbb845c4SAlexey Kardashevskiy tbl->it_indirect_levels = levels - 1; 25253ba3a73eSAlexey Kardashevskiy tbl->it_allocated_size = total_allocated; 2526aca6913fSAlexey Kardashevskiy 2527aca6913fSAlexey Kardashevskiy pr_devel("Created TCE table: ws=%08llx ts=%lx @%08llx\n", 2528aca6913fSAlexey Kardashevskiy window_size, tce_table_size, bus_offset); 2529aca6913fSAlexey Kardashevskiy 2530aca6913fSAlexey Kardashevskiy return 0; 2531aca6913fSAlexey Kardashevskiy } 2532aca6913fSAlexey Kardashevskiy 2533bbb845c4SAlexey Kardashevskiy static void pnv_pci_ioda2_table_do_free_pages(__be64 *addr, 2534bbb845c4SAlexey Kardashevskiy unsigned long size, unsigned level) 2535bbb845c4SAlexey Kardashevskiy { 2536bbb845c4SAlexey Kardashevskiy const unsigned long addr_ul = (unsigned long) addr & 2537bbb845c4SAlexey Kardashevskiy ~(TCE_PCI_READ | TCE_PCI_WRITE); 2538bbb845c4SAlexey Kardashevskiy 2539bbb845c4SAlexey Kardashevskiy if (level) { 2540bbb845c4SAlexey Kardashevskiy long i; 2541bbb845c4SAlexey Kardashevskiy u64 *tmp = (u64 *) addr_ul; 2542bbb845c4SAlexey Kardashevskiy 2543bbb845c4SAlexey Kardashevskiy for (i = 0; i < size; ++i) { 2544bbb845c4SAlexey Kardashevskiy unsigned long hpa = be64_to_cpu(tmp[i]); 2545bbb845c4SAlexey Kardashevskiy 2546bbb845c4SAlexey Kardashevskiy if (!(hpa & (TCE_PCI_READ | TCE_PCI_WRITE))) 2547bbb845c4SAlexey Kardashevskiy continue; 2548bbb845c4SAlexey Kardashevskiy 2549bbb845c4SAlexey Kardashevskiy pnv_pci_ioda2_table_do_free_pages(__va(hpa), size, 2550bbb845c4SAlexey Kardashevskiy level - 1); 2551bbb845c4SAlexey Kardashevskiy } 2552bbb845c4SAlexey Kardashevskiy } 2553bbb845c4SAlexey Kardashevskiy 2554bbb845c4SAlexey Kardashevskiy free_pages(addr_ul, get_order(size << 3)); 2555bbb845c4SAlexey Kardashevskiy } 2556bbb845c4SAlexey Kardashevskiy 2557aca6913fSAlexey Kardashevskiy static void pnv_pci_ioda2_table_free_pages(struct iommu_table *tbl) 2558aca6913fSAlexey Kardashevskiy { 2559bbb845c4SAlexey Kardashevskiy const unsigned long size = tbl->it_indirect_levels ? 2560bbb845c4SAlexey Kardashevskiy tbl->it_level_size : tbl->it_size; 2561bbb845c4SAlexey Kardashevskiy 2562aca6913fSAlexey Kardashevskiy if (!tbl->it_size) 2563aca6913fSAlexey Kardashevskiy return; 2564aca6913fSAlexey Kardashevskiy 2565bbb845c4SAlexey Kardashevskiy pnv_pci_ioda2_table_do_free_pages((__be64 *)tbl->it_base, size, 2566bbb845c4SAlexey Kardashevskiy tbl->it_indirect_levels); 2567aca6913fSAlexey Kardashevskiy } 2568aca6913fSAlexey Kardashevskiy 2569373f5657SGavin Shan static void pnv_pci_ioda2_setup_dma_pe(struct pnv_phb *phb, 2570373f5657SGavin Shan struct pnv_ioda_pe *pe) 2571373f5657SGavin Shan { 2572373f5657SGavin Shan int64_t rc; 2573373f5657SGavin Shan 2574f87a8864SAlexey Kardashevskiy /* TVE #1 is selected by PCI address bit 59 */ 2575f87a8864SAlexey Kardashevskiy pe->tce_bypass_base = 1ull << 59; 2576f87a8864SAlexey Kardashevskiy 2577b348aa65SAlexey Kardashevskiy iommu_register_group(&pe->table_group, phb->hose->global_number, 2578b348aa65SAlexey Kardashevskiy pe->pe_number); 2579c5773822SAlexey Kardashevskiy 2580373f5657SGavin Shan /* The PE will reserve all possible 32-bits space */ 2581373f5657SGavin Shan pe_info(pe, "Setting up 32-bit TCE table at 0..%08x\n", 2582aca6913fSAlexey Kardashevskiy phb->ioda.m32_pci_base); 2583373f5657SGavin Shan 2584e5aad1e6SAlexey Kardashevskiy /* Setup linux iommu table */ 25854793d65dSAlexey Kardashevskiy pe->table_group.tce32_start = 0; 25864793d65dSAlexey Kardashevskiy pe->table_group.tce32_size = phb->ioda.m32_pci_base; 25874793d65dSAlexey Kardashevskiy pe->table_group.max_dynamic_windows_supported = 25884793d65dSAlexey Kardashevskiy IOMMU_TABLE_GROUP_MAX_TABLES; 25894793d65dSAlexey Kardashevskiy pe->table_group.max_levels = POWERNV_IOMMU_MAX_LEVELS; 25904793d65dSAlexey Kardashevskiy pe->table_group.pgsizes = SZ_4K | SZ_64K | SZ_16M; 2591e5aad1e6SAlexey Kardashevskiy #ifdef CONFIG_IOMMU_API 2592e5aad1e6SAlexey Kardashevskiy pe->table_group.ops = &pnv_pci_ioda2_ops; 2593e5aad1e6SAlexey Kardashevskiy #endif 2594e5aad1e6SAlexey Kardashevskiy 259546d3e1e1SAlexey Kardashevskiy rc = pnv_pci_ioda2_setup_default_config(pe); 2596801846d1SGavin Shan if (rc) 259746d3e1e1SAlexey Kardashevskiy return; 259846d3e1e1SAlexey Kardashevskiy 259946d3e1e1SAlexey Kardashevskiy if (pe->flags & PNV_IODA_PE_DEV) 260046d3e1e1SAlexey Kardashevskiy iommu_add_device(&pe->pdev->dev); 260146d3e1e1SAlexey Kardashevskiy else if (pe->flags & (PNV_IODA_PE_BUS | PNV_IODA_PE_BUS_ALL)) 260246d3e1e1SAlexey Kardashevskiy pnv_ioda_setup_bus_dma(pe, pe->pbus); 2603373f5657SGavin Shan } 2604373f5657SGavin Shan 2605cad5cef6SGreg Kroah-Hartman static void pnv_ioda_setup_dma(struct pnv_phb *phb) 2606184cd4a3SBenjamin Herrenschmidt { 2607184cd4a3SBenjamin Herrenschmidt struct pci_controller *hose = phb->hose; 2608184cd4a3SBenjamin Herrenschmidt struct pnv_ioda_pe *pe; 26092b923ed1SGavin Shan unsigned int weight; 2610801846d1SGavin Shan 2611184cd4a3SBenjamin Herrenschmidt /* If we have more PE# than segments available, hand out one 2612184cd4a3SBenjamin Herrenschmidt * per PE until we run out and let the rest fail. If not, 2613184cd4a3SBenjamin Herrenschmidt * then we assign at least one segment per PE, plus more based 2614184cd4a3SBenjamin Herrenschmidt * on the amount of devices under that PE 2615184cd4a3SBenjamin Herrenschmidt */ 26162b923ed1SGavin Shan pr_info("PCI: Domain %04x has %d available 32-bit DMA segments\n", 26172b923ed1SGavin Shan hose->global_number, phb->ioda.dma32_count); 2618184cd4a3SBenjamin Herrenschmidt 26195780fb04SAlexey Kardashevskiy pnv_pci_ioda_setup_opal_tce_kill(phb); 26205780fb04SAlexey Kardashevskiy 26212b923ed1SGavin Shan /* Walk our PE list and configure their DMA segments */ 2622801846d1SGavin Shan list_for_each_entry(pe, &phb->ioda.pe_list, list) { 2623801846d1SGavin Shan weight = pnv_pci_ioda_pe_dma_weight(pe); 2624801846d1SGavin Shan if (!weight) 2625184cd4a3SBenjamin Herrenschmidt continue; 2626801846d1SGavin Shan 2627373f5657SGavin Shan /* 2628373f5657SGavin Shan * For IODA2 compliant PHB3, we needn't care about the weight. 2629373f5657SGavin Shan * The all available 32-bits DMA space will be assigned to 2630373f5657SGavin Shan * the specific PE. 2631373f5657SGavin Shan */ 2632373f5657SGavin Shan if (phb->type == PNV_PHB_IODA1) { 26332b923ed1SGavin Shan pnv_pci_ioda1_setup_dma_pe(phb, pe); 26345d2aa710SAlistair Popple } else if (phb->type == PNV_PHB_IODA2) { 2635373f5657SGavin Shan pe_info(pe, "Assign DMA32 space\n"); 2636373f5657SGavin Shan pnv_pci_ioda2_setup_dma_pe(phb, pe); 26375d2aa710SAlistair Popple } else if (phb->type == PNV_PHB_NPU) { 26385d2aa710SAlistair Popple /* 26395d2aa710SAlistair Popple * We initialise the DMA space for an NPU PHB 26405d2aa710SAlistair Popple * after setup of the PHB is complete as we 26415d2aa710SAlistair Popple * point the NPU TVT to the the same location 26425d2aa710SAlistair Popple * as the PHB3 TVT. 26435d2aa710SAlistair Popple */ 2644373f5657SGavin Shan } 2645184cd4a3SBenjamin Herrenschmidt } 2646184cd4a3SBenjamin Herrenschmidt } 2647184cd4a3SBenjamin Herrenschmidt 2648184cd4a3SBenjamin Herrenschmidt #ifdef CONFIG_PCI_MSI 2649137436c9SGavin Shan static void pnv_ioda2_msi_eoi(struct irq_data *d) 2650137436c9SGavin Shan { 2651137436c9SGavin Shan unsigned int hw_irq = (unsigned int)irqd_to_hwirq(d); 2652137436c9SGavin Shan struct irq_chip *chip = irq_data_get_irq_chip(d); 2653137436c9SGavin Shan struct pnv_phb *phb = container_of(chip, struct pnv_phb, 2654137436c9SGavin Shan ioda.irq_chip); 2655137436c9SGavin Shan int64_t rc; 2656137436c9SGavin Shan 2657137436c9SGavin Shan rc = opal_pci_msi_eoi(phb->opal_id, hw_irq); 2658137436c9SGavin Shan WARN_ON_ONCE(rc); 2659137436c9SGavin Shan 2660137436c9SGavin Shan icp_native_eoi(d); 2661137436c9SGavin Shan } 2662137436c9SGavin Shan 2663fd9a1c26SIan Munsie 2664fd9a1c26SIan Munsie static void set_msi_irq_chip(struct pnv_phb *phb, unsigned int virq) 2665fd9a1c26SIan Munsie { 2666fd9a1c26SIan Munsie struct irq_data *idata; 2667fd9a1c26SIan Munsie struct irq_chip *ichip; 2668fd9a1c26SIan Munsie 2669fd9a1c26SIan Munsie if (phb->type != PNV_PHB_IODA2) 2670fd9a1c26SIan Munsie return; 2671fd9a1c26SIan Munsie 2672fd9a1c26SIan Munsie if (!phb->ioda.irq_chip_init) { 2673fd9a1c26SIan Munsie /* 2674fd9a1c26SIan Munsie * First time we setup an MSI IRQ, we need to setup the 2675fd9a1c26SIan Munsie * corresponding IRQ chip to route correctly. 2676fd9a1c26SIan Munsie */ 2677fd9a1c26SIan Munsie idata = irq_get_irq_data(virq); 2678fd9a1c26SIan Munsie ichip = irq_data_get_irq_chip(idata); 2679fd9a1c26SIan Munsie phb->ioda.irq_chip_init = 1; 2680fd9a1c26SIan Munsie phb->ioda.irq_chip = *ichip; 2681fd9a1c26SIan Munsie phb->ioda.irq_chip.irq_eoi = pnv_ioda2_msi_eoi; 2682fd9a1c26SIan Munsie } 2683fd9a1c26SIan Munsie irq_set_chip(virq, &phb->ioda.irq_chip); 2684fd9a1c26SIan Munsie } 2685fd9a1c26SIan Munsie 268680c49c7eSIan Munsie #ifdef CONFIG_CXL_BASE 268780c49c7eSIan Munsie 26886f963ec2SRyan Grimm struct device_node *pnv_pci_get_phb_node(struct pci_dev *dev) 268980c49c7eSIan Munsie { 269080c49c7eSIan Munsie struct pci_controller *hose = pci_bus_to_host(dev->bus); 269180c49c7eSIan Munsie 26926f963ec2SRyan Grimm return of_node_get(hose->dn); 269380c49c7eSIan Munsie } 26946f963ec2SRyan Grimm EXPORT_SYMBOL(pnv_pci_get_phb_node); 269580c49c7eSIan Munsie 26961212aa1cSRyan Grimm int pnv_phb_to_cxl_mode(struct pci_dev *dev, uint64_t mode) 269780c49c7eSIan Munsie { 269880c49c7eSIan Munsie struct pci_controller *hose = pci_bus_to_host(dev->bus); 269980c49c7eSIan Munsie struct pnv_phb *phb = hose->private_data; 270080c49c7eSIan Munsie struct pnv_ioda_pe *pe; 270180c49c7eSIan Munsie int rc; 270280c49c7eSIan Munsie 270380c49c7eSIan Munsie pe = pnv_ioda_get_pe(dev); 270480c49c7eSIan Munsie if (!pe) 270580c49c7eSIan Munsie return -ENODEV; 270680c49c7eSIan Munsie 270780c49c7eSIan Munsie pe_info(pe, "Switching PHB to CXL\n"); 270880c49c7eSIan Munsie 27091212aa1cSRyan Grimm rc = opal_pci_set_phb_cxl_mode(phb->opal_id, mode, pe->pe_number); 271080c49c7eSIan Munsie if (rc) 271180c49c7eSIan Munsie dev_err(&dev->dev, "opal_pci_set_phb_cxl_mode failed: %i\n", rc); 271280c49c7eSIan Munsie 271380c49c7eSIan Munsie return rc; 271480c49c7eSIan Munsie } 27151212aa1cSRyan Grimm EXPORT_SYMBOL(pnv_phb_to_cxl_mode); 271680c49c7eSIan Munsie 271780c49c7eSIan Munsie /* Find PHB for cxl dev and allocate MSI hwirqs? 271880c49c7eSIan Munsie * Returns the absolute hardware IRQ number 271980c49c7eSIan Munsie */ 272080c49c7eSIan Munsie int pnv_cxl_alloc_hwirqs(struct pci_dev *dev, int num) 272180c49c7eSIan Munsie { 272280c49c7eSIan Munsie struct pci_controller *hose = pci_bus_to_host(dev->bus); 272380c49c7eSIan Munsie struct pnv_phb *phb = hose->private_data; 272480c49c7eSIan Munsie int hwirq = msi_bitmap_alloc_hwirqs(&phb->msi_bmp, num); 272580c49c7eSIan Munsie 272680c49c7eSIan Munsie if (hwirq < 0) { 272780c49c7eSIan Munsie dev_warn(&dev->dev, "Failed to find a free MSI\n"); 272880c49c7eSIan Munsie return -ENOSPC; 272980c49c7eSIan Munsie } 273080c49c7eSIan Munsie 273180c49c7eSIan Munsie return phb->msi_base + hwirq; 273280c49c7eSIan Munsie } 273380c49c7eSIan Munsie EXPORT_SYMBOL(pnv_cxl_alloc_hwirqs); 273480c49c7eSIan Munsie 273580c49c7eSIan Munsie void pnv_cxl_release_hwirqs(struct pci_dev *dev, int hwirq, int num) 273680c49c7eSIan Munsie { 273780c49c7eSIan Munsie struct pci_controller *hose = pci_bus_to_host(dev->bus); 273880c49c7eSIan Munsie struct pnv_phb *phb = hose->private_data; 273980c49c7eSIan Munsie 274080c49c7eSIan Munsie msi_bitmap_free_hwirqs(&phb->msi_bmp, hwirq - phb->msi_base, num); 274180c49c7eSIan Munsie } 274280c49c7eSIan Munsie EXPORT_SYMBOL(pnv_cxl_release_hwirqs); 274380c49c7eSIan Munsie 274480c49c7eSIan Munsie void pnv_cxl_release_hwirq_ranges(struct cxl_irq_ranges *irqs, 274580c49c7eSIan Munsie struct pci_dev *dev) 274680c49c7eSIan Munsie { 274780c49c7eSIan Munsie struct pci_controller *hose = pci_bus_to_host(dev->bus); 274880c49c7eSIan Munsie struct pnv_phb *phb = hose->private_data; 274980c49c7eSIan Munsie int i, hwirq; 275080c49c7eSIan Munsie 275180c49c7eSIan Munsie for (i = 1; i < CXL_IRQ_RANGES; i++) { 275280c49c7eSIan Munsie if (!irqs->range[i]) 275380c49c7eSIan Munsie continue; 275480c49c7eSIan Munsie pr_devel("cxl release irq range 0x%x: offset: 0x%lx limit: %ld\n", 275580c49c7eSIan Munsie i, irqs->offset[i], 275680c49c7eSIan Munsie irqs->range[i]); 275780c49c7eSIan Munsie hwirq = irqs->offset[i] - phb->msi_base; 275880c49c7eSIan Munsie msi_bitmap_free_hwirqs(&phb->msi_bmp, hwirq, 275980c49c7eSIan Munsie irqs->range[i]); 276080c49c7eSIan Munsie } 276180c49c7eSIan Munsie } 276280c49c7eSIan Munsie EXPORT_SYMBOL(pnv_cxl_release_hwirq_ranges); 276380c49c7eSIan Munsie 276480c49c7eSIan Munsie int pnv_cxl_alloc_hwirq_ranges(struct cxl_irq_ranges *irqs, 276580c49c7eSIan Munsie struct pci_dev *dev, int num) 276680c49c7eSIan Munsie { 276780c49c7eSIan Munsie struct pci_controller *hose = pci_bus_to_host(dev->bus); 276880c49c7eSIan Munsie struct pnv_phb *phb = hose->private_data; 276980c49c7eSIan Munsie int i, hwirq, try; 277080c49c7eSIan Munsie 277180c49c7eSIan Munsie memset(irqs, 0, sizeof(struct cxl_irq_ranges)); 277280c49c7eSIan Munsie 277380c49c7eSIan Munsie /* 0 is reserved for the multiplexed PSL DSI interrupt */ 277480c49c7eSIan Munsie for (i = 1; i < CXL_IRQ_RANGES && num; i++) { 277580c49c7eSIan Munsie try = num; 277680c49c7eSIan Munsie while (try) { 277780c49c7eSIan Munsie hwirq = msi_bitmap_alloc_hwirqs(&phb->msi_bmp, try); 277880c49c7eSIan Munsie if (hwirq >= 0) 277980c49c7eSIan Munsie break; 278080c49c7eSIan Munsie try /= 2; 278180c49c7eSIan Munsie } 278280c49c7eSIan Munsie if (!try) 278380c49c7eSIan Munsie goto fail; 278480c49c7eSIan Munsie 278580c49c7eSIan Munsie irqs->offset[i] = phb->msi_base + hwirq; 278680c49c7eSIan Munsie irqs->range[i] = try; 278780c49c7eSIan Munsie pr_devel("cxl alloc irq range 0x%x: offset: 0x%lx limit: %li\n", 278880c49c7eSIan Munsie i, irqs->offset[i], irqs->range[i]); 278980c49c7eSIan Munsie num -= try; 279080c49c7eSIan Munsie } 279180c49c7eSIan Munsie if (num) 279280c49c7eSIan Munsie goto fail; 279380c49c7eSIan Munsie 279480c49c7eSIan Munsie return 0; 279580c49c7eSIan Munsie fail: 279680c49c7eSIan Munsie pnv_cxl_release_hwirq_ranges(irqs, dev); 279780c49c7eSIan Munsie return -ENOSPC; 279880c49c7eSIan Munsie } 279980c49c7eSIan Munsie EXPORT_SYMBOL(pnv_cxl_alloc_hwirq_ranges); 280080c49c7eSIan Munsie 280180c49c7eSIan Munsie int pnv_cxl_get_irq_count(struct pci_dev *dev) 280280c49c7eSIan Munsie { 280380c49c7eSIan Munsie struct pci_controller *hose = pci_bus_to_host(dev->bus); 280480c49c7eSIan Munsie struct pnv_phb *phb = hose->private_data; 280580c49c7eSIan Munsie 280680c49c7eSIan Munsie return phb->msi_bmp.irq_count; 280780c49c7eSIan Munsie } 280880c49c7eSIan Munsie EXPORT_SYMBOL(pnv_cxl_get_irq_count); 280980c49c7eSIan Munsie 281080c49c7eSIan Munsie int pnv_cxl_ioda_msi_setup(struct pci_dev *dev, unsigned int hwirq, 281180c49c7eSIan Munsie unsigned int virq) 281280c49c7eSIan Munsie { 281380c49c7eSIan Munsie struct pci_controller *hose = pci_bus_to_host(dev->bus); 281480c49c7eSIan Munsie struct pnv_phb *phb = hose->private_data; 281580c49c7eSIan Munsie unsigned int xive_num = hwirq - phb->msi_base; 281680c49c7eSIan Munsie struct pnv_ioda_pe *pe; 281780c49c7eSIan Munsie int rc; 281880c49c7eSIan Munsie 281980c49c7eSIan Munsie if (!(pe = pnv_ioda_get_pe(dev))) 282080c49c7eSIan Munsie return -ENODEV; 282180c49c7eSIan Munsie 282280c49c7eSIan Munsie /* Assign XIVE to PE */ 282380c49c7eSIan Munsie rc = opal_pci_set_xive_pe(phb->opal_id, pe->pe_number, xive_num); 282480c49c7eSIan Munsie if (rc) { 282580c49c7eSIan Munsie pe_warn(pe, "%s: OPAL error %d setting msi_base 0x%x " 282680c49c7eSIan Munsie "hwirq 0x%x XIVE 0x%x PE\n", 282780c49c7eSIan Munsie pci_name(dev), rc, phb->msi_base, hwirq, xive_num); 282880c49c7eSIan Munsie return -EIO; 282980c49c7eSIan Munsie } 283080c49c7eSIan Munsie set_msi_irq_chip(phb, virq); 283180c49c7eSIan Munsie 283280c49c7eSIan Munsie return 0; 283380c49c7eSIan Munsie } 283480c49c7eSIan Munsie EXPORT_SYMBOL(pnv_cxl_ioda_msi_setup); 283580c49c7eSIan Munsie #endif 283680c49c7eSIan Munsie 2837184cd4a3SBenjamin Herrenschmidt static int pnv_pci_ioda_msi_setup(struct pnv_phb *phb, struct pci_dev *dev, 2838137436c9SGavin Shan unsigned int hwirq, unsigned int virq, 2839137436c9SGavin Shan unsigned int is_64, struct msi_msg *msg) 2840184cd4a3SBenjamin Herrenschmidt { 2841184cd4a3SBenjamin Herrenschmidt struct pnv_ioda_pe *pe = pnv_ioda_get_pe(dev); 2842184cd4a3SBenjamin Herrenschmidt unsigned int xive_num = hwirq - phb->msi_base; 28433a1a4661SBenjamin Herrenschmidt __be32 data; 2844184cd4a3SBenjamin Herrenschmidt int rc; 2845184cd4a3SBenjamin Herrenschmidt 2846184cd4a3SBenjamin Herrenschmidt /* No PE assigned ? bail out ... no MSI for you ! */ 2847184cd4a3SBenjamin Herrenschmidt if (pe == NULL) 2848184cd4a3SBenjamin Herrenschmidt return -ENXIO; 2849184cd4a3SBenjamin Herrenschmidt 2850184cd4a3SBenjamin Herrenschmidt /* Check if we have an MVE */ 2851184cd4a3SBenjamin Herrenschmidt if (pe->mve_number < 0) 2852184cd4a3SBenjamin Herrenschmidt return -ENXIO; 2853184cd4a3SBenjamin Herrenschmidt 2854b72c1f65SBenjamin Herrenschmidt /* Force 32-bit MSI on some broken devices */ 285536074381SBenjamin Herrenschmidt if (dev->no_64bit_msi) 2856b72c1f65SBenjamin Herrenschmidt is_64 = 0; 2857b72c1f65SBenjamin Herrenschmidt 2858184cd4a3SBenjamin Herrenschmidt /* Assign XIVE to PE */ 2859184cd4a3SBenjamin Herrenschmidt rc = opal_pci_set_xive_pe(phb->opal_id, pe->pe_number, xive_num); 2860184cd4a3SBenjamin Herrenschmidt if (rc) { 2861184cd4a3SBenjamin Herrenschmidt pr_warn("%s: OPAL error %d setting XIVE %d PE\n", 2862184cd4a3SBenjamin Herrenschmidt pci_name(dev), rc, xive_num); 2863184cd4a3SBenjamin Herrenschmidt return -EIO; 2864184cd4a3SBenjamin Herrenschmidt } 2865184cd4a3SBenjamin Herrenschmidt 2866184cd4a3SBenjamin Herrenschmidt if (is_64) { 28673a1a4661SBenjamin Herrenschmidt __be64 addr64; 28683a1a4661SBenjamin Herrenschmidt 2869184cd4a3SBenjamin Herrenschmidt rc = opal_get_msi_64(phb->opal_id, pe->mve_number, xive_num, 1, 2870184cd4a3SBenjamin Herrenschmidt &addr64, &data); 2871184cd4a3SBenjamin Herrenschmidt if (rc) { 2872184cd4a3SBenjamin Herrenschmidt pr_warn("%s: OPAL error %d getting 64-bit MSI data\n", 2873184cd4a3SBenjamin Herrenschmidt pci_name(dev), rc); 2874184cd4a3SBenjamin Herrenschmidt return -EIO; 2875184cd4a3SBenjamin Herrenschmidt } 28763a1a4661SBenjamin Herrenschmidt msg->address_hi = be64_to_cpu(addr64) >> 32; 28773a1a4661SBenjamin Herrenschmidt msg->address_lo = be64_to_cpu(addr64) & 0xfffffffful; 2878184cd4a3SBenjamin Herrenschmidt } else { 28793a1a4661SBenjamin Herrenschmidt __be32 addr32; 28803a1a4661SBenjamin Herrenschmidt 2881184cd4a3SBenjamin Herrenschmidt rc = opal_get_msi_32(phb->opal_id, pe->mve_number, xive_num, 1, 2882184cd4a3SBenjamin Herrenschmidt &addr32, &data); 2883184cd4a3SBenjamin Herrenschmidt if (rc) { 2884184cd4a3SBenjamin Herrenschmidt pr_warn("%s: OPAL error %d getting 32-bit MSI data\n", 2885184cd4a3SBenjamin Herrenschmidt pci_name(dev), rc); 2886184cd4a3SBenjamin Herrenschmidt return -EIO; 2887184cd4a3SBenjamin Herrenschmidt } 2888184cd4a3SBenjamin Herrenschmidt msg->address_hi = 0; 28893a1a4661SBenjamin Herrenschmidt msg->address_lo = be32_to_cpu(addr32); 2890184cd4a3SBenjamin Herrenschmidt } 28913a1a4661SBenjamin Herrenschmidt msg->data = be32_to_cpu(data); 2892184cd4a3SBenjamin Herrenschmidt 2893fd9a1c26SIan Munsie set_msi_irq_chip(phb, virq); 2894137436c9SGavin Shan 2895184cd4a3SBenjamin Herrenschmidt pr_devel("%s: %s-bit MSI on hwirq %x (xive #%d)," 2896184cd4a3SBenjamin Herrenschmidt " address=%x_%08x data=%x PE# %d\n", 2897184cd4a3SBenjamin Herrenschmidt pci_name(dev), is_64 ? "64" : "32", hwirq, xive_num, 2898184cd4a3SBenjamin Herrenschmidt msg->address_hi, msg->address_lo, data, pe->pe_number); 2899184cd4a3SBenjamin Herrenschmidt 2900184cd4a3SBenjamin Herrenschmidt return 0; 2901184cd4a3SBenjamin Herrenschmidt } 2902184cd4a3SBenjamin Herrenschmidt 2903184cd4a3SBenjamin Herrenschmidt static void pnv_pci_init_ioda_msis(struct pnv_phb *phb) 2904184cd4a3SBenjamin Herrenschmidt { 2905fb1b55d6SGavin Shan unsigned int count; 2906184cd4a3SBenjamin Herrenschmidt const __be32 *prop = of_get_property(phb->hose->dn, 2907184cd4a3SBenjamin Herrenschmidt "ibm,opal-msi-ranges", NULL); 2908184cd4a3SBenjamin Herrenschmidt if (!prop) { 2909184cd4a3SBenjamin Herrenschmidt /* BML Fallback */ 2910184cd4a3SBenjamin Herrenschmidt prop = of_get_property(phb->hose->dn, "msi-ranges", NULL); 2911184cd4a3SBenjamin Herrenschmidt } 2912184cd4a3SBenjamin Herrenschmidt if (!prop) 2913184cd4a3SBenjamin Herrenschmidt return; 2914184cd4a3SBenjamin Herrenschmidt 2915184cd4a3SBenjamin Herrenschmidt phb->msi_base = be32_to_cpup(prop); 2916fb1b55d6SGavin Shan count = be32_to_cpup(prop + 1); 2917fb1b55d6SGavin Shan if (msi_bitmap_alloc(&phb->msi_bmp, count, phb->hose->dn)) { 2918184cd4a3SBenjamin Herrenschmidt pr_err("PCI %d: Failed to allocate MSI bitmap !\n", 2919184cd4a3SBenjamin Herrenschmidt phb->hose->global_number); 2920184cd4a3SBenjamin Herrenschmidt return; 2921184cd4a3SBenjamin Herrenschmidt } 2922fb1b55d6SGavin Shan 2923184cd4a3SBenjamin Herrenschmidt phb->msi_setup = pnv_pci_ioda_msi_setup; 2924184cd4a3SBenjamin Herrenschmidt phb->msi32_support = 1; 2925184cd4a3SBenjamin Herrenschmidt pr_info(" Allocated bitmap for %d MSIs (base IRQ 0x%x)\n", 2926fb1b55d6SGavin Shan count, phb->msi_base); 2927184cd4a3SBenjamin Herrenschmidt } 2928184cd4a3SBenjamin Herrenschmidt #else 2929184cd4a3SBenjamin Herrenschmidt static void pnv_pci_init_ioda_msis(struct pnv_phb *phb) { } 2930184cd4a3SBenjamin Herrenschmidt #endif /* CONFIG_PCI_MSI */ 2931184cd4a3SBenjamin Herrenschmidt 29326e628c7dSWei Yang #ifdef CONFIG_PCI_IOV 29336e628c7dSWei Yang static void pnv_pci_ioda_fixup_iov_resources(struct pci_dev *pdev) 29346e628c7dSWei Yang { 2935f2dd0afeSWei Yang struct pci_controller *hose = pci_bus_to_host(pdev->bus); 2936f2dd0afeSWei Yang struct pnv_phb *phb = hose->private_data; 2937f2dd0afeSWei Yang const resource_size_t gate = phb->ioda.m64_segsize >> 2; 29386e628c7dSWei Yang struct resource *res; 29396e628c7dSWei Yang int i; 2940dfcc8d45SWei Yang resource_size_t size, total_vf_bar_sz; 29416e628c7dSWei Yang struct pci_dn *pdn; 29425b88ec22SWei Yang int mul, total_vfs; 29436e628c7dSWei Yang 29446e628c7dSWei Yang if (!pdev->is_physfn || pdev->is_added) 29456e628c7dSWei Yang return; 29466e628c7dSWei Yang 29476e628c7dSWei Yang pdn = pci_get_pdn(pdev); 29486e628c7dSWei Yang pdn->vfs_expanded = 0; 2949ee8222feSWei Yang pdn->m64_single_mode = false; 29506e628c7dSWei Yang 29515b88ec22SWei Yang total_vfs = pci_sriov_get_totalvfs(pdev); 295292b8f137SGavin Shan mul = phb->ioda.total_pe_num; 2953dfcc8d45SWei Yang total_vf_bar_sz = 0; 29545b88ec22SWei Yang 29555b88ec22SWei Yang for (i = 0; i < PCI_SRIOV_NUM_BARS; i++) { 29565b88ec22SWei Yang res = &pdev->resource[i + PCI_IOV_RESOURCES]; 29575b88ec22SWei Yang if (!res->flags || res->parent) 29585b88ec22SWei Yang continue; 29595b88ec22SWei Yang if (!pnv_pci_is_mem_pref_64(res->flags)) { 2960b0331854SWei Yang dev_warn(&pdev->dev, "Don't support SR-IOV with" 2961b0331854SWei Yang " non M64 VF BAR%d: %pR. \n", 29625b88ec22SWei Yang i, res); 2963b0331854SWei Yang goto truncate_iov; 29645b88ec22SWei Yang } 29655b88ec22SWei Yang 2966dfcc8d45SWei Yang total_vf_bar_sz += pci_iov_resource_size(pdev, 2967dfcc8d45SWei Yang i + PCI_IOV_RESOURCES); 29685b88ec22SWei Yang 2969f2dd0afeSWei Yang /* 2970f2dd0afeSWei Yang * If bigger than quarter of M64 segment size, just round up 2971f2dd0afeSWei Yang * power of two. 2972f2dd0afeSWei Yang * 2973f2dd0afeSWei Yang * Generally, one M64 BAR maps one IOV BAR. To avoid conflict 2974f2dd0afeSWei Yang * with other devices, IOV BAR size is expanded to be 2975f2dd0afeSWei Yang * (total_pe * VF_BAR_size). When VF_BAR_size is half of M64 2976f2dd0afeSWei Yang * segment size , the expanded size would equal to half of the 2977f2dd0afeSWei Yang * whole M64 space size, which will exhaust the M64 Space and 2978f2dd0afeSWei Yang * limit the system flexibility. This is a design decision to 2979f2dd0afeSWei Yang * set the boundary to quarter of the M64 segment size. 2980f2dd0afeSWei Yang */ 2981dfcc8d45SWei Yang if (total_vf_bar_sz > gate) { 29825b88ec22SWei Yang mul = roundup_pow_of_two(total_vfs); 2983dfcc8d45SWei Yang dev_info(&pdev->dev, 2984dfcc8d45SWei Yang "VF BAR Total IOV size %llx > %llx, roundup to %d VFs\n", 2985dfcc8d45SWei Yang total_vf_bar_sz, gate, mul); 2986ee8222feSWei Yang pdn->m64_single_mode = true; 29875b88ec22SWei Yang break; 29885b88ec22SWei Yang } 29895b88ec22SWei Yang } 29905b88ec22SWei Yang 29916e628c7dSWei Yang for (i = 0; i < PCI_SRIOV_NUM_BARS; i++) { 29926e628c7dSWei Yang res = &pdev->resource[i + PCI_IOV_RESOURCES]; 29936e628c7dSWei Yang if (!res->flags || res->parent) 29946e628c7dSWei Yang continue; 29956e628c7dSWei Yang 29966e628c7dSWei Yang size = pci_iov_resource_size(pdev, i + PCI_IOV_RESOURCES); 2997ee8222feSWei Yang /* 2998ee8222feSWei Yang * On PHB3, the minimum size alignment of M64 BAR in single 2999ee8222feSWei Yang * mode is 32MB. 3000ee8222feSWei Yang */ 3001ee8222feSWei Yang if (pdn->m64_single_mode && (size < SZ_32M)) 3002ee8222feSWei Yang goto truncate_iov; 3003ee8222feSWei Yang dev_dbg(&pdev->dev, " Fixing VF BAR%d: %pR to\n", i, res); 30045b88ec22SWei Yang res->end = res->start + size * mul - 1; 30056e628c7dSWei Yang dev_dbg(&pdev->dev, " %pR\n", res); 30066e628c7dSWei Yang dev_info(&pdev->dev, "VF BAR%d: %pR (expanded to %d VFs for PE alignment)", 30075b88ec22SWei Yang i, res, mul); 30086e628c7dSWei Yang } 30095b88ec22SWei Yang pdn->vfs_expanded = mul; 3010b0331854SWei Yang 3011b0331854SWei Yang return; 3012b0331854SWei Yang 3013b0331854SWei Yang truncate_iov: 3014b0331854SWei Yang /* To save MMIO space, IOV BAR is truncated. */ 3015b0331854SWei Yang for (i = 0; i < PCI_SRIOV_NUM_BARS; i++) { 3016b0331854SWei Yang res = &pdev->resource[i + PCI_IOV_RESOURCES]; 3017b0331854SWei Yang res->flags = 0; 3018b0331854SWei Yang res->end = res->start - 1; 3019b0331854SWei Yang } 30206e628c7dSWei Yang } 30216e628c7dSWei Yang #endif /* CONFIG_PCI_IOV */ 30226e628c7dSWei Yang 302323e79425SGavin Shan static void pnv_ioda_setup_pe_res(struct pnv_ioda_pe *pe, 302423e79425SGavin Shan struct resource *res) 302511685becSGavin Shan { 302623e79425SGavin Shan struct pnv_phb *phb = pe->phb; 302711685becSGavin Shan struct pci_bus_region region; 302823e79425SGavin Shan int index; 302923e79425SGavin Shan int64_t rc; 303011685becSGavin Shan 303123e79425SGavin Shan if (!res || !res->flags || res->start > res->end) 303223e79425SGavin Shan return; 303311685becSGavin Shan 303411685becSGavin Shan if (res->flags & IORESOURCE_IO) { 303511685becSGavin Shan region.start = res->start - phb->ioda.io_pci_base; 303611685becSGavin Shan region.end = res->end - phb->ioda.io_pci_base; 303711685becSGavin Shan index = region.start / phb->ioda.io_segsize; 303811685becSGavin Shan 303992b8f137SGavin Shan while (index < phb->ioda.total_pe_num && 304011685becSGavin Shan region.start <= region.end) { 304111685becSGavin Shan phb->ioda.io_segmap[index] = pe->pe_number; 304211685becSGavin Shan rc = opal_pci_map_pe_mmio_window(phb->opal_id, 304311685becSGavin Shan pe->pe_number, OPAL_IO_WINDOW_TYPE, 0, index); 304411685becSGavin Shan if (rc != OPAL_SUCCESS) { 304523e79425SGavin Shan pr_err("%s: Error %lld mapping IO segment#%d to PE#%d\n", 304611685becSGavin Shan __func__, rc, index, pe->pe_number); 304711685becSGavin Shan break; 304811685becSGavin Shan } 304911685becSGavin Shan 305011685becSGavin Shan region.start += phb->ioda.io_segsize; 305111685becSGavin Shan index++; 305211685becSGavin Shan } 3053027fa02fSGavin Shan } else if ((res->flags & IORESOURCE_MEM) && 3054027fa02fSGavin Shan !pnv_pci_is_mem_pref_64(res->flags)) { 305511685becSGavin Shan region.start = res->start - 305623e79425SGavin Shan phb->hose->mem_offset[0] - 305711685becSGavin Shan phb->ioda.m32_pci_base; 305811685becSGavin Shan region.end = res->end - 305923e79425SGavin Shan phb->hose->mem_offset[0] - 306011685becSGavin Shan phb->ioda.m32_pci_base; 306111685becSGavin Shan index = region.start / phb->ioda.m32_segsize; 306211685becSGavin Shan 306392b8f137SGavin Shan while (index < phb->ioda.total_pe_num && 306411685becSGavin Shan region.start <= region.end) { 306511685becSGavin Shan phb->ioda.m32_segmap[index] = pe->pe_number; 306611685becSGavin Shan rc = opal_pci_map_pe_mmio_window(phb->opal_id, 306711685becSGavin Shan pe->pe_number, OPAL_M32_WINDOW_TYPE, 0, index); 306811685becSGavin Shan if (rc != OPAL_SUCCESS) { 306923e79425SGavin Shan pr_err("%s: Error %lld mapping M32 segment#%d to PE#%d", 307011685becSGavin Shan __func__, rc, index, pe->pe_number); 307111685becSGavin Shan break; 307211685becSGavin Shan } 307311685becSGavin Shan 307411685becSGavin Shan region.start += phb->ioda.m32_segsize; 307511685becSGavin Shan index++; 307611685becSGavin Shan } 307711685becSGavin Shan } 307811685becSGavin Shan } 307923e79425SGavin Shan 308023e79425SGavin Shan /* 308123e79425SGavin Shan * This function is supposed to be called on basis of PE from top 308223e79425SGavin Shan * to bottom style. So the the I/O or MMIO segment assigned to 308323e79425SGavin Shan * parent PE could be overrided by its child PEs if necessary. 308423e79425SGavin Shan */ 308523e79425SGavin Shan static void pnv_ioda_setup_pe_seg(struct pnv_ioda_pe *pe) 308623e79425SGavin Shan { 308769d733e7SGavin Shan struct pci_dev *pdev; 308823e79425SGavin Shan int i; 308923e79425SGavin Shan 309023e79425SGavin Shan /* 309123e79425SGavin Shan * NOTE: We only care PCI bus based PE for now. For PCI 309223e79425SGavin Shan * device based PE, for example SRIOV sensitive VF should 309323e79425SGavin Shan * be figured out later. 309423e79425SGavin Shan */ 309523e79425SGavin Shan BUG_ON(!(pe->flags & (PNV_IODA_PE_BUS | PNV_IODA_PE_BUS_ALL))); 309623e79425SGavin Shan 309769d733e7SGavin Shan list_for_each_entry(pdev, &pe->pbus->devices, bus_list) { 309869d733e7SGavin Shan for (i = 0; i <= PCI_ROM_RESOURCE; i++) 309969d733e7SGavin Shan pnv_ioda_setup_pe_res(pe, &pdev->resource[i]); 310069d733e7SGavin Shan 310169d733e7SGavin Shan /* 310269d733e7SGavin Shan * If the PE contains all subordinate PCI buses, the 310369d733e7SGavin Shan * windows of the child bridges should be mapped to 310469d733e7SGavin Shan * the PE as well. 310569d733e7SGavin Shan */ 310669d733e7SGavin Shan if (!(pe->flags & PNV_IODA_PE_BUS_ALL) || !pci_is_bridge(pdev)) 310769d733e7SGavin Shan continue; 310869d733e7SGavin Shan for (i = 0; i < PCI_BRIDGE_RESOURCE_NUM; i++) 310969d733e7SGavin Shan pnv_ioda_setup_pe_res(pe, 311069d733e7SGavin Shan &pdev->resource[PCI_BRIDGE_RESOURCES + i]); 311169d733e7SGavin Shan } 311211685becSGavin Shan } 311311685becSGavin Shan 3114cad5cef6SGreg Kroah-Hartman static void pnv_pci_ioda_setup_seg(void) 311511685becSGavin Shan { 311611685becSGavin Shan struct pci_controller *tmp, *hose; 311711685becSGavin Shan struct pnv_phb *phb; 311811685becSGavin Shan struct pnv_ioda_pe *pe; 311911685becSGavin Shan 312011685becSGavin Shan list_for_each_entry_safe(hose, tmp, &hose_list, list_node) { 312111685becSGavin Shan phb = hose->private_data; 31225d2aa710SAlistair Popple 31235d2aa710SAlistair Popple /* NPU PHB does not support IO or MMIO segmentation */ 31245d2aa710SAlistair Popple if (phb->type == PNV_PHB_NPU) 31255d2aa710SAlistair Popple continue; 31265d2aa710SAlistair Popple 312711685becSGavin Shan list_for_each_entry(pe, &phb->ioda.pe_list, list) { 312823e79425SGavin Shan pnv_ioda_setup_pe_seg(pe); 312911685becSGavin Shan } 313011685becSGavin Shan } 313111685becSGavin Shan } 313211685becSGavin Shan 3133cad5cef6SGreg Kroah-Hartman static void pnv_pci_ioda_setup_DMA(void) 313413395c48SGavin Shan { 313513395c48SGavin Shan struct pci_controller *hose, *tmp; 3136db1266c8SGavin Shan struct pnv_phb *phb; 313713395c48SGavin Shan 313813395c48SGavin Shan list_for_each_entry_safe(hose, tmp, &hose_list, list_node) { 313913395c48SGavin Shan pnv_ioda_setup_dma(hose->private_data); 3140db1266c8SGavin Shan 3141db1266c8SGavin Shan /* Mark the PHB initialization done */ 3142db1266c8SGavin Shan phb = hose->private_data; 3143db1266c8SGavin Shan phb->initialized = 1; 314413395c48SGavin Shan } 314513395c48SGavin Shan } 314613395c48SGavin Shan 314737c367f2SGavin Shan static void pnv_pci_ioda_create_dbgfs(void) 314837c367f2SGavin Shan { 314937c367f2SGavin Shan #ifdef CONFIG_DEBUG_FS 315037c367f2SGavin Shan struct pci_controller *hose, *tmp; 315137c367f2SGavin Shan struct pnv_phb *phb; 315237c367f2SGavin Shan char name[16]; 315337c367f2SGavin Shan 315437c367f2SGavin Shan list_for_each_entry_safe(hose, tmp, &hose_list, list_node) { 315537c367f2SGavin Shan phb = hose->private_data; 315637c367f2SGavin Shan 315737c367f2SGavin Shan sprintf(name, "PCI%04x", hose->global_number); 315837c367f2SGavin Shan phb->dbgfs = debugfs_create_dir(name, powerpc_debugfs_root); 315937c367f2SGavin Shan if (!phb->dbgfs) 316037c367f2SGavin Shan pr_warning("%s: Error on creating debugfs on PHB#%x\n", 316137c367f2SGavin Shan __func__, hose->global_number); 316237c367f2SGavin Shan } 316337c367f2SGavin Shan #endif /* CONFIG_DEBUG_FS */ 316437c367f2SGavin Shan } 316537c367f2SGavin Shan 31665d2aa710SAlistair Popple static void pnv_npu_ioda_fixup(void) 31675d2aa710SAlistair Popple { 31685d2aa710SAlistair Popple bool enable_bypass; 31695d2aa710SAlistair Popple struct pci_controller *hose, *tmp; 31705d2aa710SAlistair Popple struct pnv_phb *phb; 31715d2aa710SAlistair Popple struct pnv_ioda_pe *pe; 3172801846d1SGavin Shan unsigned int weight; 31735d2aa710SAlistair Popple 31745d2aa710SAlistair Popple list_for_each_entry_safe(hose, tmp, &hose_list, list_node) { 31755d2aa710SAlistair Popple phb = hose->private_data; 31765d2aa710SAlistair Popple if (phb->type != PNV_PHB_NPU) 31775d2aa710SAlistair Popple continue; 31785d2aa710SAlistair Popple 3179801846d1SGavin Shan list_for_each_entry(pe, &phb->ioda.pe_list, list) { 3180801846d1SGavin Shan weight = pnv_pci_ioda_pe_dma_weight(pe); 3181801846d1SGavin Shan if (WARN_ON(!weight)) 3182801846d1SGavin Shan continue; 3183801846d1SGavin Shan 31845d2aa710SAlistair Popple enable_bypass = dma_get_mask(&pe->pdev->dev) == 31855d2aa710SAlistair Popple DMA_BIT_MASK(64); 31865d2aa710SAlistair Popple pnv_npu_init_dma_pe(pe); 31875d2aa710SAlistair Popple } 31885d2aa710SAlistair Popple } 31895d2aa710SAlistair Popple } 31905d2aa710SAlistair Popple 3191cad5cef6SGreg Kroah-Hartman static void pnv_pci_ioda_fixup(void) 3192fb446ad0SGavin Shan { 3193fb446ad0SGavin Shan pnv_pci_ioda_setup_PEs(); 319411685becSGavin Shan pnv_pci_ioda_setup_seg(); 319513395c48SGavin Shan pnv_pci_ioda_setup_DMA(); 3196e9cc17d4SGavin Shan 319737c367f2SGavin Shan pnv_pci_ioda_create_dbgfs(); 319837c367f2SGavin Shan 3199e9cc17d4SGavin Shan #ifdef CONFIG_EEH 3200e9cc17d4SGavin Shan eeh_init(); 3201dadcd6d6SMike Qiu eeh_addr_cache_build(); 3202e9cc17d4SGavin Shan #endif 32035d2aa710SAlistair Popple 32045d2aa710SAlistair Popple /* Link NPU IODA tables to their PCI devices. */ 32055d2aa710SAlistair Popple pnv_npu_ioda_fixup(); 3206fb446ad0SGavin Shan } 3207fb446ad0SGavin Shan 3208271fd03aSGavin Shan /* 3209271fd03aSGavin Shan * Returns the alignment for I/O or memory windows for P2P 3210271fd03aSGavin Shan * bridges. That actually depends on how PEs are segmented. 3211271fd03aSGavin Shan * For now, we return I/O or M32 segment size for PE sensitive 3212271fd03aSGavin Shan * P2P bridges. Otherwise, the default values (4KiB for I/O, 3213271fd03aSGavin Shan * 1MiB for memory) will be returned. 3214271fd03aSGavin Shan * 3215271fd03aSGavin Shan * The current PCI bus might be put into one PE, which was 3216271fd03aSGavin Shan * create against the parent PCI bridge. For that case, we 3217271fd03aSGavin Shan * needn't enlarge the alignment so that we can save some 3218271fd03aSGavin Shan * resources. 3219271fd03aSGavin Shan */ 3220271fd03aSGavin Shan static resource_size_t pnv_pci_window_alignment(struct pci_bus *bus, 3221271fd03aSGavin Shan unsigned long type) 3222271fd03aSGavin Shan { 3223271fd03aSGavin Shan struct pci_dev *bridge; 3224271fd03aSGavin Shan struct pci_controller *hose = pci_bus_to_host(bus); 3225271fd03aSGavin Shan struct pnv_phb *phb = hose->private_data; 3226271fd03aSGavin Shan int num_pci_bridges = 0; 3227271fd03aSGavin Shan 3228271fd03aSGavin Shan bridge = bus->self; 3229271fd03aSGavin Shan while (bridge) { 3230271fd03aSGavin Shan if (pci_pcie_type(bridge) == PCI_EXP_TYPE_PCI_BRIDGE) { 3231271fd03aSGavin Shan num_pci_bridges++; 3232271fd03aSGavin Shan if (num_pci_bridges >= 2) 3233271fd03aSGavin Shan return 1; 3234271fd03aSGavin Shan } 3235271fd03aSGavin Shan 3236271fd03aSGavin Shan bridge = bridge->bus->self; 3237271fd03aSGavin Shan } 3238271fd03aSGavin Shan 3239262af557SGuo Chao /* We fail back to M32 if M64 isn't supported */ 3240262af557SGuo Chao if (phb->ioda.m64_segsize && 3241262af557SGuo Chao pnv_pci_is_mem_pref_64(type)) 3242262af557SGuo Chao return phb->ioda.m64_segsize; 3243271fd03aSGavin Shan if (type & IORESOURCE_MEM) 3244271fd03aSGavin Shan return phb->ioda.m32_segsize; 3245271fd03aSGavin Shan 3246271fd03aSGavin Shan return phb->ioda.io_segsize; 3247271fd03aSGavin Shan } 3248271fd03aSGavin Shan 32495350ab3fSWei Yang #ifdef CONFIG_PCI_IOV 32505350ab3fSWei Yang static resource_size_t pnv_pci_iov_resource_alignment(struct pci_dev *pdev, 32515350ab3fSWei Yang int resno) 32525350ab3fSWei Yang { 3253ee8222feSWei Yang struct pci_controller *hose = pci_bus_to_host(pdev->bus); 3254ee8222feSWei Yang struct pnv_phb *phb = hose->private_data; 32555350ab3fSWei Yang struct pci_dn *pdn = pci_get_pdn(pdev); 32567fbe7a93SWei Yang resource_size_t align; 32575350ab3fSWei Yang 32587fbe7a93SWei Yang /* 32597fbe7a93SWei Yang * On PowerNV platform, IOV BAR is mapped by M64 BAR to enable the 32607fbe7a93SWei Yang * SR-IOV. While from hardware perspective, the range mapped by M64 32617fbe7a93SWei Yang * BAR should be size aligned. 32627fbe7a93SWei Yang * 3263ee8222feSWei Yang * When IOV BAR is mapped with M64 BAR in Single PE mode, the extra 3264ee8222feSWei Yang * powernv-specific hardware restriction is gone. But if just use the 3265ee8222feSWei Yang * VF BAR size as the alignment, PF BAR / VF BAR may be allocated with 3266ee8222feSWei Yang * in one segment of M64 #15, which introduces the PE conflict between 3267ee8222feSWei Yang * PF and VF. Based on this, the minimum alignment of an IOV BAR is 3268ee8222feSWei Yang * m64_segsize. 3269ee8222feSWei Yang * 32707fbe7a93SWei Yang * This function returns the total IOV BAR size if M64 BAR is in 32717fbe7a93SWei Yang * Shared PE mode or just VF BAR size if not. 3272ee8222feSWei Yang * If the M64 BAR is in Single PE mode, return the VF BAR size or 3273ee8222feSWei Yang * M64 segment size if IOV BAR size is less. 32747fbe7a93SWei Yang */ 32755350ab3fSWei Yang align = pci_iov_resource_size(pdev, resno); 32767fbe7a93SWei Yang if (!pdn->vfs_expanded) 32775350ab3fSWei Yang return align; 3278ee8222feSWei Yang if (pdn->m64_single_mode) 3279ee8222feSWei Yang return max(align, (resource_size_t)phb->ioda.m64_segsize); 32807fbe7a93SWei Yang 32817fbe7a93SWei Yang return pdn->vfs_expanded * align; 32825350ab3fSWei Yang } 32835350ab3fSWei Yang #endif /* CONFIG_PCI_IOV */ 32845350ab3fSWei Yang 3285184cd4a3SBenjamin Herrenschmidt /* Prevent enabling devices for which we couldn't properly 3286184cd4a3SBenjamin Herrenschmidt * assign a PE 3287184cd4a3SBenjamin Herrenschmidt */ 3288c88c2a18SDaniel Axtens static bool pnv_pci_enable_device_hook(struct pci_dev *dev) 3289184cd4a3SBenjamin Herrenschmidt { 3290db1266c8SGavin Shan struct pci_controller *hose = pci_bus_to_host(dev->bus); 3291db1266c8SGavin Shan struct pnv_phb *phb = hose->private_data; 3292db1266c8SGavin Shan struct pci_dn *pdn; 3293184cd4a3SBenjamin Herrenschmidt 3294db1266c8SGavin Shan /* The function is probably called while the PEs have 3295db1266c8SGavin Shan * not be created yet. For example, resource reassignment 3296db1266c8SGavin Shan * during PCI probe period. We just skip the check if 3297db1266c8SGavin Shan * PEs isn't ready. 3298db1266c8SGavin Shan */ 3299db1266c8SGavin Shan if (!phb->initialized) 3300c88c2a18SDaniel Axtens return true; 3301db1266c8SGavin Shan 3302b72c1f65SBenjamin Herrenschmidt pdn = pci_get_pdn(dev); 3303184cd4a3SBenjamin Herrenschmidt if (!pdn || pdn->pe_number == IODA_INVALID_PE) 3304c88c2a18SDaniel Axtens return false; 3305db1266c8SGavin Shan 3306c88c2a18SDaniel Axtens return true; 3307184cd4a3SBenjamin Herrenschmidt } 3308184cd4a3SBenjamin Herrenschmidt 33097a8e6bbfSMichael Neuling static void pnv_pci_ioda_shutdown(struct pci_controller *hose) 331073ed148aSBenjamin Herrenschmidt { 33117a8e6bbfSMichael Neuling struct pnv_phb *phb = hose->private_data; 33127a8e6bbfSMichael Neuling 3313d1a85eeeSGavin Shan opal_pci_reset(phb->opal_id, OPAL_RESET_PCI_IODA_TABLE, 331473ed148aSBenjamin Herrenschmidt OPAL_ASSERT_RESET); 331573ed148aSBenjamin Herrenschmidt } 331673ed148aSBenjamin Herrenschmidt 331792ae0353SDaniel Axtens static const struct pci_controller_ops pnv_pci_ioda_controller_ops = { 331892ae0353SDaniel Axtens .dma_dev_setup = pnv_pci_dma_dev_setup, 33191bc74f1cSGavin Shan .dma_bus_setup = pnv_pci_dma_bus_setup, 332092ae0353SDaniel Axtens #ifdef CONFIG_PCI_MSI 332192ae0353SDaniel Axtens .setup_msi_irqs = pnv_setup_msi_irqs, 332292ae0353SDaniel Axtens .teardown_msi_irqs = pnv_teardown_msi_irqs, 332392ae0353SDaniel Axtens #endif 332492ae0353SDaniel Axtens .enable_device_hook = pnv_pci_enable_device_hook, 332592ae0353SDaniel Axtens .window_alignment = pnv_pci_window_alignment, 332692ae0353SDaniel Axtens .reset_secondary_bus = pnv_pci_reset_secondary_bus, 3327763d2d8dSDaniel Axtens .dma_set_mask = pnv_pci_ioda_dma_set_mask, 332853522982SAndrew Donnellan .dma_get_required_mask = pnv_pci_ioda_dma_get_required_mask, 33297a8e6bbfSMichael Neuling .shutdown = pnv_pci_ioda_shutdown, 333092ae0353SDaniel Axtens }; 333192ae0353SDaniel Axtens 3332f9f83456SAlexey Kardashevskiy static int pnv_npu_dma_set_mask(struct pci_dev *npdev, u64 dma_mask) 3333f9f83456SAlexey Kardashevskiy { 3334f9f83456SAlexey Kardashevskiy dev_err_once(&npdev->dev, 3335f9f83456SAlexey Kardashevskiy "%s operation unsupported for NVLink devices\n", 3336f9f83456SAlexey Kardashevskiy __func__); 3337f9f83456SAlexey Kardashevskiy return -EPERM; 3338f9f83456SAlexey Kardashevskiy } 3339f9f83456SAlexey Kardashevskiy 33405d2aa710SAlistair Popple static const struct pci_controller_ops pnv_npu_ioda_controller_ops = { 33415d2aa710SAlistair Popple .dma_dev_setup = pnv_pci_dma_dev_setup, 33425d2aa710SAlistair Popple #ifdef CONFIG_PCI_MSI 33435d2aa710SAlistair Popple .setup_msi_irqs = pnv_setup_msi_irqs, 33445d2aa710SAlistair Popple .teardown_msi_irqs = pnv_teardown_msi_irqs, 33455d2aa710SAlistair Popple #endif 33465d2aa710SAlistair Popple .enable_device_hook = pnv_pci_enable_device_hook, 33475d2aa710SAlistair Popple .window_alignment = pnv_pci_window_alignment, 33485d2aa710SAlistair Popple .reset_secondary_bus = pnv_pci_reset_secondary_bus, 33495d2aa710SAlistair Popple .dma_set_mask = pnv_npu_dma_set_mask, 33505d2aa710SAlistair Popple .shutdown = pnv_pci_ioda_shutdown, 33515d2aa710SAlistair Popple }; 33525d2aa710SAlistair Popple 3353e51df2c1SAnton Blanchard static void __init pnv_pci_init_ioda_phb(struct device_node *np, 3354e9cc17d4SGavin Shan u64 hub_id, int ioda_type) 3355184cd4a3SBenjamin Herrenschmidt { 3356184cd4a3SBenjamin Herrenschmidt struct pci_controller *hose; 3357184cd4a3SBenjamin Herrenschmidt struct pnv_phb *phb; 33582b923ed1SGavin Shan unsigned long size, m64map_off, m32map_off, pemap_off; 33592b923ed1SGavin Shan unsigned long iomap_off = 0, dma32map_off = 0; 3360c681b93cSAlistair Popple const __be64 *prop64; 33613a1a4661SBenjamin Herrenschmidt const __be32 *prop32; 3362f1b7cc3eSGavin Shan int len; 33633fa23ff8SGavin Shan unsigned int segno; 3364184cd4a3SBenjamin Herrenschmidt u64 phb_id; 3365184cd4a3SBenjamin Herrenschmidt void *aux; 3366184cd4a3SBenjamin Herrenschmidt long rc; 3367184cd4a3SBenjamin Herrenschmidt 3368aa0c033fSGavin Shan pr_info("Initializing IODA%d OPAL PHB %s\n", ioda_type, np->full_name); 3369184cd4a3SBenjamin Herrenschmidt 3370184cd4a3SBenjamin Herrenschmidt prop64 = of_get_property(np, "ibm,opal-phbid", NULL); 3371184cd4a3SBenjamin Herrenschmidt if (!prop64) { 3372184cd4a3SBenjamin Herrenschmidt pr_err(" Missing \"ibm,opal-phbid\" property !\n"); 3373184cd4a3SBenjamin Herrenschmidt return; 3374184cd4a3SBenjamin Herrenschmidt } 3375184cd4a3SBenjamin Herrenschmidt phb_id = be64_to_cpup(prop64); 3376184cd4a3SBenjamin Herrenschmidt pr_debug(" PHB-ID : 0x%016llx\n", phb_id); 3377184cd4a3SBenjamin Herrenschmidt 3378e39f223fSMichael Ellerman phb = memblock_virt_alloc(sizeof(struct pnv_phb), 0); 337958d714ecSGavin Shan 338058d714ecSGavin Shan /* Allocate PCI controller */ 3381184cd4a3SBenjamin Herrenschmidt phb->hose = hose = pcibios_alloc_controller(np); 338258d714ecSGavin Shan if (!phb->hose) { 338358d714ecSGavin Shan pr_err(" Can't allocate PCI controller for %s\n", 3384184cd4a3SBenjamin Herrenschmidt np->full_name); 3385e39f223fSMichael Ellerman memblock_free(__pa(phb), sizeof(struct pnv_phb)); 3386184cd4a3SBenjamin Herrenschmidt return; 3387184cd4a3SBenjamin Herrenschmidt } 3388184cd4a3SBenjamin Herrenschmidt 3389184cd4a3SBenjamin Herrenschmidt spin_lock_init(&phb->lock); 3390f1b7cc3eSGavin Shan prop32 = of_get_property(np, "bus-range", &len); 3391f1b7cc3eSGavin Shan if (prop32 && len == 8) { 33923a1a4661SBenjamin Herrenschmidt hose->first_busno = be32_to_cpu(prop32[0]); 33933a1a4661SBenjamin Herrenschmidt hose->last_busno = be32_to_cpu(prop32[1]); 3394f1b7cc3eSGavin Shan } else { 3395f1b7cc3eSGavin Shan pr_warn(" Broken <bus-range> on %s\n", np->full_name); 3396184cd4a3SBenjamin Herrenschmidt hose->first_busno = 0; 3397184cd4a3SBenjamin Herrenschmidt hose->last_busno = 0xff; 3398f1b7cc3eSGavin Shan } 3399184cd4a3SBenjamin Herrenschmidt hose->private_data = phb; 3400e9cc17d4SGavin Shan phb->hub_id = hub_id; 3401184cd4a3SBenjamin Herrenschmidt phb->opal_id = phb_id; 3402aa0c033fSGavin Shan phb->type = ioda_type; 3403781a868fSWei Yang mutex_init(&phb->ioda.pe_alloc_mutex); 3404184cd4a3SBenjamin Herrenschmidt 3405cee72d5bSBenjamin Herrenschmidt /* Detect specific models for error handling */ 3406cee72d5bSBenjamin Herrenschmidt if (of_device_is_compatible(np, "ibm,p7ioc-pciex")) 3407cee72d5bSBenjamin Herrenschmidt phb->model = PNV_PHB_MODEL_P7IOC; 3408f3d40c25SBenjamin Herrenschmidt else if (of_device_is_compatible(np, "ibm,power8-pciex")) 3409aa0c033fSGavin Shan phb->model = PNV_PHB_MODEL_PHB3; 34105d2aa710SAlistair Popple else if (of_device_is_compatible(np, "ibm,power8-npu-pciex")) 34115d2aa710SAlistair Popple phb->model = PNV_PHB_MODEL_NPU; 3412cee72d5bSBenjamin Herrenschmidt else 3413cee72d5bSBenjamin Herrenschmidt phb->model = PNV_PHB_MODEL_UNKNOWN; 3414cee72d5bSBenjamin Herrenschmidt 3415aa0c033fSGavin Shan /* Parse 32-bit and IO ranges (if any) */ 34162f1ec02eSGavin Shan pci_process_bridge_OF_ranges(hose, np, !hose->global_number); 3417184cd4a3SBenjamin Herrenschmidt 3418aa0c033fSGavin Shan /* Get registers */ 3419184cd4a3SBenjamin Herrenschmidt phb->regs = of_iomap(np, 0); 3420184cd4a3SBenjamin Herrenschmidt if (phb->regs == NULL) 3421184cd4a3SBenjamin Herrenschmidt pr_err(" Failed to map registers !\n"); 3422184cd4a3SBenjamin Herrenschmidt 3423184cd4a3SBenjamin Herrenschmidt /* Initialize more IODA stuff */ 342492b8f137SGavin Shan phb->ioda.total_pe_num = 1; 342536954dc7SGavin Shan prop32 = of_get_property(np, "ibm,opal-num-pes", NULL); 342636954dc7SGavin Shan if (prop32) 342792b8f137SGavin Shan phb->ioda.total_pe_num = be32_to_cpup(prop32); 342836954dc7SGavin Shan prop32 = of_get_property(np, "ibm,opal-reserved-pe", NULL); 342936954dc7SGavin Shan if (prop32) 343092b8f137SGavin Shan phb->ioda.reserved_pe_idx = be32_to_cpup(prop32); 3431262af557SGuo Chao 3432262af557SGuo Chao /* Parse 64-bit MMIO range */ 3433262af557SGuo Chao pnv_ioda_parse_m64_window(phb); 3434262af557SGuo Chao 3435184cd4a3SBenjamin Herrenschmidt phb->ioda.m32_size = resource_size(&hose->mem_resources[0]); 3436aa0c033fSGavin Shan /* FW Has already off top 64k of M32 space (MSI space) */ 3437184cd4a3SBenjamin Herrenschmidt phb->ioda.m32_size += 0x10000; 3438184cd4a3SBenjamin Herrenschmidt 343992b8f137SGavin Shan phb->ioda.m32_segsize = phb->ioda.m32_size / phb->ioda.total_pe_num; 34403fd47f06SBenjamin Herrenschmidt phb->ioda.m32_pci_base = hose->mem_resources[0].start - hose->mem_offset[0]; 3441184cd4a3SBenjamin Herrenschmidt phb->ioda.io_size = hose->pci_io_size; 344292b8f137SGavin Shan phb->ioda.io_segsize = phb->ioda.io_size / phb->ioda.total_pe_num; 3443184cd4a3SBenjamin Herrenschmidt phb->ioda.io_pci_base = 0; /* XXX calculate this ? */ 3444184cd4a3SBenjamin Herrenschmidt 34452b923ed1SGavin Shan /* Calculate how many 32-bit TCE segments we have */ 34462b923ed1SGavin Shan phb->ioda.dma32_count = phb->ioda.m32_pci_base / 34472b923ed1SGavin Shan PNV_IODA1_DMA32_SEGSIZE; 34482b923ed1SGavin Shan 3449c35d2a8cSGavin Shan /* Allocate aux data & arrays. We don't have IO ports on PHB3 */ 345092b8f137SGavin Shan size = _ALIGN_UP(phb->ioda.total_pe_num / 8, sizeof(unsigned long)); 345193289d8cSGavin Shan m64map_off = size; 345293289d8cSGavin Shan size += phb->ioda.total_pe_num * sizeof(phb->ioda.m64_segmap[0]); 3453184cd4a3SBenjamin Herrenschmidt m32map_off = size; 345492b8f137SGavin Shan size += phb->ioda.total_pe_num * sizeof(phb->ioda.m32_segmap[0]); 3455c35d2a8cSGavin Shan if (phb->type == PNV_PHB_IODA1) { 3456c35d2a8cSGavin Shan iomap_off = size; 345792b8f137SGavin Shan size += phb->ioda.total_pe_num * sizeof(phb->ioda.io_segmap[0]); 34582b923ed1SGavin Shan dma32map_off = size; 34592b923ed1SGavin Shan size += phb->ioda.dma32_count * 34602b923ed1SGavin Shan sizeof(phb->ioda.dma32_segmap[0]); 3461c35d2a8cSGavin Shan } 3462184cd4a3SBenjamin Herrenschmidt pemap_off = size; 346392b8f137SGavin Shan size += phb->ioda.total_pe_num * sizeof(struct pnv_ioda_pe); 3464e39f223fSMichael Ellerman aux = memblock_virt_alloc(size, 0); 3465184cd4a3SBenjamin Herrenschmidt phb->ioda.pe_alloc = aux; 346693289d8cSGavin Shan phb->ioda.m64_segmap = aux + m64map_off; 3467184cd4a3SBenjamin Herrenschmidt phb->ioda.m32_segmap = aux + m32map_off; 346893289d8cSGavin Shan for (segno = 0; segno < phb->ioda.total_pe_num; segno++) { 346993289d8cSGavin Shan phb->ioda.m64_segmap[segno] = IODA_INVALID_PE; 34703fa23ff8SGavin Shan phb->ioda.m32_segmap[segno] = IODA_INVALID_PE; 347193289d8cSGavin Shan } 34723fa23ff8SGavin Shan if (phb->type == PNV_PHB_IODA1) { 3473184cd4a3SBenjamin Herrenschmidt phb->ioda.io_segmap = aux + iomap_off; 34743fa23ff8SGavin Shan for (segno = 0; segno < phb->ioda.total_pe_num; segno++) 34753fa23ff8SGavin Shan phb->ioda.io_segmap[segno] = IODA_INVALID_PE; 34762b923ed1SGavin Shan 34772b923ed1SGavin Shan phb->ioda.dma32_segmap = aux + dma32map_off; 34782b923ed1SGavin Shan for (segno = 0; segno < phb->ioda.dma32_count; segno++) 34792b923ed1SGavin Shan phb->ioda.dma32_segmap[segno] = IODA_INVALID_PE; 34803fa23ff8SGavin Shan } 3481184cd4a3SBenjamin Herrenschmidt phb->ioda.pe_array = aux + pemap_off; 348292b8f137SGavin Shan set_bit(phb->ioda.reserved_pe_idx, phb->ioda.pe_alloc); 3483184cd4a3SBenjamin Herrenschmidt 3484184cd4a3SBenjamin Herrenschmidt INIT_LIST_HEAD(&phb->ioda.pe_list); 3485781a868fSWei Yang mutex_init(&phb->ioda.pe_list_mutex); 3486184cd4a3SBenjamin Herrenschmidt 3487184cd4a3SBenjamin Herrenschmidt /* Calculate how many 32-bit TCE segments we have */ 34882b923ed1SGavin Shan phb->ioda.dma32_count = phb->ioda.m32_pci_base / 3489acce971cSGavin Shan PNV_IODA1_DMA32_SEGSIZE; 3490184cd4a3SBenjamin Herrenschmidt 3491aa0c033fSGavin Shan #if 0 /* We should really do that ... */ 3492184cd4a3SBenjamin Herrenschmidt rc = opal_pci_set_phb_mem_window(opal->phb_id, 3493184cd4a3SBenjamin Herrenschmidt window_type, 3494184cd4a3SBenjamin Herrenschmidt window_num, 3495184cd4a3SBenjamin Herrenschmidt starting_real_address, 3496184cd4a3SBenjamin Herrenschmidt starting_pci_address, 3497184cd4a3SBenjamin Herrenschmidt segment_size); 3498184cd4a3SBenjamin Herrenschmidt #endif 3499184cd4a3SBenjamin Herrenschmidt 3500262af557SGuo Chao pr_info(" %03d (%03d) PE's M32: 0x%x [segment=0x%x]\n", 350192b8f137SGavin Shan phb->ioda.total_pe_num, phb->ioda.reserved_pe_idx, 3502262af557SGuo Chao phb->ioda.m32_size, phb->ioda.m32_segsize); 3503262af557SGuo Chao if (phb->ioda.m64_size) 3504262af557SGuo Chao pr_info(" M64: 0x%lx [segment=0x%lx]\n", 3505262af557SGuo Chao phb->ioda.m64_size, phb->ioda.m64_segsize); 3506262af557SGuo Chao if (phb->ioda.io_size) 3507262af557SGuo Chao pr_info(" IO: 0x%x [segment=0x%x]\n", 3508184cd4a3SBenjamin Herrenschmidt phb->ioda.io_size, phb->ioda.io_segsize); 3509184cd4a3SBenjamin Herrenschmidt 3510262af557SGuo Chao 3511184cd4a3SBenjamin Herrenschmidt phb->hose->ops = &pnv_pci_ops; 351249dec922SGavin Shan phb->get_pe_state = pnv_ioda_get_pe_state; 351349dec922SGavin Shan phb->freeze_pe = pnv_ioda_freeze_pe; 351449dec922SGavin Shan phb->unfreeze_pe = pnv_ioda_unfreeze_pe; 3515184cd4a3SBenjamin Herrenschmidt 3516184cd4a3SBenjamin Herrenschmidt /* Setup MSI support */ 3517184cd4a3SBenjamin Herrenschmidt pnv_pci_init_ioda_msis(phb); 3518184cd4a3SBenjamin Herrenschmidt 3519c40a4210SGavin Shan /* 3520c40a4210SGavin Shan * We pass the PCI probe flag PCI_REASSIGN_ALL_RSRC here 3521c40a4210SGavin Shan * to let the PCI core do resource assignment. It's supposed 3522c40a4210SGavin Shan * that the PCI core will do correct I/O and MMIO alignment 3523c40a4210SGavin Shan * for the P2P bridge bars so that each PCI bus (excluding 3524c40a4210SGavin Shan * the child P2P bridges) can form individual PE. 3525184cd4a3SBenjamin Herrenschmidt */ 3526fb446ad0SGavin Shan ppc_md.pcibios_fixup = pnv_pci_ioda_fixup; 35275d2aa710SAlistair Popple 3528f9f83456SAlexey Kardashevskiy if (phb->type == PNV_PHB_NPU) { 35295d2aa710SAlistair Popple hose->controller_ops = pnv_npu_ioda_controller_ops; 3530f9f83456SAlexey Kardashevskiy } else { 3531f9f83456SAlexey Kardashevskiy phb->dma_dev_setup = pnv_pci_ioda_dma_dev_setup; 353292ae0353SDaniel Axtens hose->controller_ops = pnv_pci_ioda_controller_ops; 3533f9f83456SAlexey Kardashevskiy } 3534ad30cb99SMichael Ellerman 35356e628c7dSWei Yang #ifdef CONFIG_PCI_IOV 35366e628c7dSWei Yang ppc_md.pcibios_fixup_sriov = pnv_pci_ioda_fixup_iov_resources; 35375350ab3fSWei Yang ppc_md.pcibios_iov_resource_alignment = pnv_pci_iov_resource_alignment; 3538ad30cb99SMichael Ellerman #endif 3539ad30cb99SMichael Ellerman 3540c40a4210SGavin Shan pci_add_flags(PCI_REASSIGN_ALL_RSRC); 3541184cd4a3SBenjamin Herrenschmidt 3542184cd4a3SBenjamin Herrenschmidt /* Reset IODA tables to a clean state */ 3543d1a85eeeSGavin Shan rc = opal_pci_reset(phb_id, OPAL_RESET_PCI_IODA_TABLE, OPAL_ASSERT_RESET); 3544184cd4a3SBenjamin Herrenschmidt if (rc) 3545f11fe552SBenjamin Herrenschmidt pr_warning(" OPAL Error %ld performing IODA table reset !\n", rc); 3546361f2a2aSGavin Shan 3547361f2a2aSGavin Shan /* If we're running in kdump kerenl, the previous kerenl never 3548361f2a2aSGavin Shan * shutdown PCI devices correctly. We already got IODA table 3549361f2a2aSGavin Shan * cleaned out. So we have to issue PHB reset to stop all PCI 3550361f2a2aSGavin Shan * transactions from previous kerenl. 3551361f2a2aSGavin Shan */ 3552361f2a2aSGavin Shan if (is_kdump_kernel()) { 3553361f2a2aSGavin Shan pr_info(" Issue PHB reset ...\n"); 3554cadf364dSGavin Shan pnv_eeh_phb_reset(hose, EEH_RESET_FUNDAMENTAL); 3555cadf364dSGavin Shan pnv_eeh_phb_reset(hose, EEH_RESET_DEACTIVATE); 3556361f2a2aSGavin Shan } 3557262af557SGuo Chao 35589e9e8935SGavin Shan /* Remove M64 resource if we can't configure it successfully */ 35599e9e8935SGavin Shan if (!phb->init_m64 || phb->init_m64(phb)) 3560262af557SGuo Chao hose->mem_resources[1].flags = 0; 3561184cd4a3SBenjamin Herrenschmidt } 3562184cd4a3SBenjamin Herrenschmidt 356367975005SBjorn Helgaas void __init pnv_pci_init_ioda2_phb(struct device_node *np) 3564aa0c033fSGavin Shan { 3565e9cc17d4SGavin Shan pnv_pci_init_ioda_phb(np, 0, PNV_PHB_IODA2); 3566aa0c033fSGavin Shan } 3567aa0c033fSGavin Shan 35685d2aa710SAlistair Popple void __init pnv_pci_init_npu_phb(struct device_node *np) 35695d2aa710SAlistair Popple { 35705d2aa710SAlistair Popple pnv_pci_init_ioda_phb(np, 0, PNV_PHB_NPU); 35715d2aa710SAlistair Popple } 35725d2aa710SAlistair Popple 3573184cd4a3SBenjamin Herrenschmidt void __init pnv_pci_init_ioda_hub(struct device_node *np) 3574184cd4a3SBenjamin Herrenschmidt { 3575184cd4a3SBenjamin Herrenschmidt struct device_node *phbn; 3576c681b93cSAlistair Popple const __be64 *prop64; 3577184cd4a3SBenjamin Herrenschmidt u64 hub_id; 3578184cd4a3SBenjamin Herrenschmidt 3579184cd4a3SBenjamin Herrenschmidt pr_info("Probing IODA IO-Hub %s\n", np->full_name); 3580184cd4a3SBenjamin Herrenschmidt 3581184cd4a3SBenjamin Herrenschmidt prop64 = of_get_property(np, "ibm,opal-hubid", NULL); 3582184cd4a3SBenjamin Herrenschmidt if (!prop64) { 3583184cd4a3SBenjamin Herrenschmidt pr_err(" Missing \"ibm,opal-hubid\" property !\n"); 3584184cd4a3SBenjamin Herrenschmidt return; 3585184cd4a3SBenjamin Herrenschmidt } 3586184cd4a3SBenjamin Herrenschmidt hub_id = be64_to_cpup(prop64); 3587184cd4a3SBenjamin Herrenschmidt pr_devel(" HUB-ID : 0x%016llx\n", hub_id); 3588184cd4a3SBenjamin Herrenschmidt 3589184cd4a3SBenjamin Herrenschmidt /* Count child PHBs */ 3590184cd4a3SBenjamin Herrenschmidt for_each_child_of_node(np, phbn) { 3591184cd4a3SBenjamin Herrenschmidt /* Look for IODA1 PHBs */ 3592184cd4a3SBenjamin Herrenschmidt if (of_device_is_compatible(phbn, "ibm,ioda-phb")) 3593e9cc17d4SGavin Shan pnv_pci_init_ioda_phb(phbn, hub_id, PNV_PHB_IODA1); 3594184cd4a3SBenjamin Herrenschmidt } 3595184cd4a3SBenjamin Herrenschmidt } 3596