1184cd4a3SBenjamin Herrenschmidt /* 2184cd4a3SBenjamin Herrenschmidt * Support PCI/PCIe on PowerNV platforms 3184cd4a3SBenjamin Herrenschmidt * 4184cd4a3SBenjamin Herrenschmidt * Copyright 2011 Benjamin Herrenschmidt, IBM Corp. 5184cd4a3SBenjamin Herrenschmidt * 6184cd4a3SBenjamin Herrenschmidt * This program is free software; you can redistribute it and/or 7184cd4a3SBenjamin Herrenschmidt * modify it under the terms of the GNU General Public License 8184cd4a3SBenjamin Herrenschmidt * as published by the Free Software Foundation; either version 9184cd4a3SBenjamin Herrenschmidt * 2 of the License, or (at your option) any later version. 10184cd4a3SBenjamin Herrenschmidt */ 11184cd4a3SBenjamin Herrenschmidt 12cee72d5bSBenjamin Herrenschmidt #undef DEBUG 13184cd4a3SBenjamin Herrenschmidt 14184cd4a3SBenjamin Herrenschmidt #include <linux/kernel.h> 15184cd4a3SBenjamin Herrenschmidt #include <linux/pci.h> 16361f2a2aSGavin Shan #include <linux/crash_dump.h> 17184cd4a3SBenjamin Herrenschmidt #include <linux/delay.h> 18184cd4a3SBenjamin Herrenschmidt #include <linux/string.h> 19184cd4a3SBenjamin Herrenschmidt #include <linux/init.h> 20184cd4a3SBenjamin Herrenschmidt #include <linux/bootmem.h> 21184cd4a3SBenjamin Herrenschmidt #include <linux/irq.h> 22184cd4a3SBenjamin Herrenschmidt #include <linux/io.h> 23184cd4a3SBenjamin Herrenschmidt #include <linux/msi.h> 24cd15b048SBenjamin Herrenschmidt #include <linux/memblock.h> 25ac9a5889SAlexey Kardashevskiy #include <linux/iommu.h> 26e57080f1SAlexey Kardashevskiy #include <linux/rculist.h> 274793d65dSAlexey Kardashevskiy #include <linux/sizes.h> 28184cd4a3SBenjamin Herrenschmidt 29184cd4a3SBenjamin Herrenschmidt #include <asm/sections.h> 30184cd4a3SBenjamin Herrenschmidt #include <asm/io.h> 31184cd4a3SBenjamin Herrenschmidt #include <asm/prom.h> 32184cd4a3SBenjamin Herrenschmidt #include <asm/pci-bridge.h> 33184cd4a3SBenjamin Herrenschmidt #include <asm/machdep.h> 34fb1b55d6SGavin Shan #include <asm/msi_bitmap.h> 35184cd4a3SBenjamin Herrenschmidt #include <asm/ppc-pci.h> 36184cd4a3SBenjamin Herrenschmidt #include <asm/opal.h> 37184cd4a3SBenjamin Herrenschmidt #include <asm/iommu.h> 38184cd4a3SBenjamin Herrenschmidt #include <asm/tce.h> 39137436c9SGavin Shan #include <asm/xics.h> 407644d581SMichael Ellerman #include <asm/debugfs.h> 41262af557SGuo Chao #include <asm/firmware.h> 4280c49c7eSIan Munsie #include <asm/pnv-pci.h> 43aca6913fSAlexey Kardashevskiy #include <asm/mmzone.h> 4480c49c7eSIan Munsie 45ec249dd8SMichael Neuling #include <misc/cxl-base.h> 46184cd4a3SBenjamin Herrenschmidt 47184cd4a3SBenjamin Herrenschmidt #include "powernv.h" 48184cd4a3SBenjamin Herrenschmidt #include "pci.h" 49184cd4a3SBenjamin Herrenschmidt 5099451551SGavin Shan #define PNV_IODA1_M64_NUM 16 /* Number of M64 BARs */ 5199451551SGavin Shan #define PNV_IODA1_M64_SEGS 8 /* Segments per M64 BAR */ 52acce971cSGavin Shan #define PNV_IODA1_DMA32_SEGSIZE 0x10000000 53781a868fSWei Yang 54bbb845c4SAlexey Kardashevskiy #define POWERNV_IOMMU_DEFAULT_LEVELS 1 55bbb845c4SAlexey Kardashevskiy #define POWERNV_IOMMU_MAX_LEVELS 5 56bbb845c4SAlexey Kardashevskiy 579497a1c1SGavin Shan static const char * const pnv_phb_names[] = { "IODA1", "IODA2", "NPU" }; 58aca6913fSAlexey Kardashevskiy static void pnv_pci_ioda2_table_free_pages(struct iommu_table *tbl); 59aca6913fSAlexey Kardashevskiy 607d623e42SAlexey Kardashevskiy void pe_level_printk(const struct pnv_ioda_pe *pe, const char *level, 616d31c2faSJoe Perches const char *fmt, ...) 626d31c2faSJoe Perches { 636d31c2faSJoe Perches struct va_format vaf; 646d31c2faSJoe Perches va_list args; 656d31c2faSJoe Perches char pfix[32]; 66184cd4a3SBenjamin Herrenschmidt 676d31c2faSJoe Perches va_start(args, fmt); 686d31c2faSJoe Perches 696d31c2faSJoe Perches vaf.fmt = fmt; 706d31c2faSJoe Perches vaf.va = &args; 716d31c2faSJoe Perches 72781a868fSWei Yang if (pe->flags & PNV_IODA_PE_DEV) 736d31c2faSJoe Perches strlcpy(pfix, dev_name(&pe->pdev->dev), sizeof(pfix)); 74781a868fSWei Yang else if (pe->flags & (PNV_IODA_PE_BUS | PNV_IODA_PE_BUS_ALL)) 756d31c2faSJoe Perches sprintf(pfix, "%04x:%02x ", 766d31c2faSJoe Perches pci_domain_nr(pe->pbus), pe->pbus->number); 77781a868fSWei Yang #ifdef CONFIG_PCI_IOV 78781a868fSWei Yang else if (pe->flags & PNV_IODA_PE_VF) 79781a868fSWei Yang sprintf(pfix, "%04x:%02x:%2x.%d", 80781a868fSWei Yang pci_domain_nr(pe->parent_dev->bus), 81781a868fSWei Yang (pe->rid & 0xff00) >> 8, 82781a868fSWei Yang PCI_SLOT(pe->rid), PCI_FUNC(pe->rid)); 83781a868fSWei Yang #endif /* CONFIG_PCI_IOV*/ 846d31c2faSJoe Perches 851f52f176SRussell Currey printk("%spci %s: [PE# %.2x] %pV", 866d31c2faSJoe Perches level, pfix, pe->pe_number, &vaf); 876d31c2faSJoe Perches 886d31c2faSJoe Perches va_end(args); 896d31c2faSJoe Perches } 906d31c2faSJoe Perches 914e287840SThadeu Lima de Souza Cascardo static bool pnv_iommu_bypass_disabled __read_mostly; 924e287840SThadeu Lima de Souza Cascardo 934e287840SThadeu Lima de Souza Cascardo static int __init iommu_setup(char *str) 944e287840SThadeu Lima de Souza Cascardo { 954e287840SThadeu Lima de Souza Cascardo if (!str) 964e287840SThadeu Lima de Souza Cascardo return -EINVAL; 974e287840SThadeu Lima de Souza Cascardo 984e287840SThadeu Lima de Souza Cascardo while (*str) { 994e287840SThadeu Lima de Souza Cascardo if (!strncmp(str, "nobypass", 8)) { 1004e287840SThadeu Lima de Souza Cascardo pnv_iommu_bypass_disabled = true; 1014e287840SThadeu Lima de Souza Cascardo pr_info("PowerNV: IOMMU bypass window disabled.\n"); 1024e287840SThadeu Lima de Souza Cascardo break; 1034e287840SThadeu Lima de Souza Cascardo } 1044e287840SThadeu Lima de Souza Cascardo str += strcspn(str, ","); 1054e287840SThadeu Lima de Souza Cascardo if (*str == ',') 1064e287840SThadeu Lima de Souza Cascardo str++; 1074e287840SThadeu Lima de Souza Cascardo } 1084e287840SThadeu Lima de Souza Cascardo 1094e287840SThadeu Lima de Souza Cascardo return 0; 1104e287840SThadeu Lima de Souza Cascardo } 1114e287840SThadeu Lima de Souza Cascardo early_param("iommu", iommu_setup); 1124e287840SThadeu Lima de Souza Cascardo 1135958d19aSBenjamin Herrenschmidt static inline bool pnv_pci_is_m64(struct pnv_phb *phb, struct resource *r) 114262af557SGuo Chao { 1155958d19aSBenjamin Herrenschmidt /* 1165958d19aSBenjamin Herrenschmidt * WARNING: We cannot rely on the resource flags. The Linux PCI 1175958d19aSBenjamin Herrenschmidt * allocation code sometimes decides to put a 64-bit prefetchable 1185958d19aSBenjamin Herrenschmidt * BAR in the 32-bit window, so we have to compare the addresses. 1195958d19aSBenjamin Herrenschmidt * 1205958d19aSBenjamin Herrenschmidt * For simplicity we only test resource start. 1215958d19aSBenjamin Herrenschmidt */ 1225958d19aSBenjamin Herrenschmidt return (r->start >= phb->ioda.m64_base && 1235958d19aSBenjamin Herrenschmidt r->start < (phb->ioda.m64_base + phb->ioda.m64_size)); 124262af557SGuo Chao } 125262af557SGuo Chao 126b79331a5SRussell Currey static inline bool pnv_pci_is_m64_flags(unsigned long resource_flags) 127b79331a5SRussell Currey { 128b79331a5SRussell Currey unsigned long flags = (IORESOURCE_MEM_64 | IORESOURCE_PREFETCH); 129b79331a5SRussell Currey 130b79331a5SRussell Currey return (resource_flags & flags) == flags; 131b79331a5SRussell Currey } 132b79331a5SRussell Currey 1331e916772SGavin Shan static struct pnv_ioda_pe *pnv_ioda_init_pe(struct pnv_phb *phb, int pe_no) 1341e916772SGavin Shan { 135313483ddSGavin Shan s64 rc; 136313483ddSGavin Shan 1371e916772SGavin Shan phb->ioda.pe_array[pe_no].phb = phb; 1381e916772SGavin Shan phb->ioda.pe_array[pe_no].pe_number = pe_no; 1391e916772SGavin Shan 140313483ddSGavin Shan /* 141313483ddSGavin Shan * Clear the PE frozen state as it might be put into frozen state 142313483ddSGavin Shan * in the last PCI remove path. It's not harmful to do so when the 143313483ddSGavin Shan * PE is already in unfrozen state. 144313483ddSGavin Shan */ 145313483ddSGavin Shan rc = opal_pci_eeh_freeze_clear(phb->opal_id, pe_no, 146313483ddSGavin Shan OPAL_EEH_ACTION_CLEAR_FREEZE_ALL); 147d4791db5SRussell Currey if (rc != OPAL_SUCCESS && rc != OPAL_UNSUPPORTED) 1481f52f176SRussell Currey pr_warn("%s: Error %lld unfreezing PHB#%x-PE#%x\n", 149313483ddSGavin Shan __func__, rc, phb->hose->global_number, pe_no); 150313483ddSGavin Shan 1511e916772SGavin Shan return &phb->ioda.pe_array[pe_no]; 1521e916772SGavin Shan } 1531e916772SGavin Shan 1544b82ab18SGavin Shan static void pnv_ioda_reserve_pe(struct pnv_phb *phb, int pe_no) 1554b82ab18SGavin Shan { 15692b8f137SGavin Shan if (!(pe_no >= 0 && pe_no < phb->ioda.total_pe_num)) { 1571f52f176SRussell Currey pr_warn("%s: Invalid PE %x on PHB#%x\n", 1584b82ab18SGavin Shan __func__, pe_no, phb->hose->global_number); 1594b82ab18SGavin Shan return; 1604b82ab18SGavin Shan } 1614b82ab18SGavin Shan 162e9dc4d7fSGavin Shan if (test_and_set_bit(pe_no, phb->ioda.pe_alloc)) 1631f52f176SRussell Currey pr_debug("%s: PE %x was reserved on PHB#%x\n", 1644b82ab18SGavin Shan __func__, pe_no, phb->hose->global_number); 1654b82ab18SGavin Shan 1661e916772SGavin Shan pnv_ioda_init_pe(phb, pe_no); 1674b82ab18SGavin Shan } 1684b82ab18SGavin Shan 1691e916772SGavin Shan static struct pnv_ioda_pe *pnv_ioda_alloc_pe(struct pnv_phb *phb) 170184cd4a3SBenjamin Herrenschmidt { 17160964816SAndrzej Hajda long pe; 172184cd4a3SBenjamin Herrenschmidt 1739fcd6f4aSGavin Shan for (pe = phb->ioda.total_pe_num - 1; pe >= 0; pe--) { 1749fcd6f4aSGavin Shan if (!test_and_set_bit(pe, phb->ioda.pe_alloc)) 1751e916772SGavin Shan return pnv_ioda_init_pe(phb, pe); 176184cd4a3SBenjamin Herrenschmidt } 177184cd4a3SBenjamin Herrenschmidt 1789fcd6f4aSGavin Shan return NULL; 1799fcd6f4aSGavin Shan } 1809fcd6f4aSGavin Shan 1811e916772SGavin Shan static void pnv_ioda_free_pe(struct pnv_ioda_pe *pe) 182184cd4a3SBenjamin Herrenschmidt { 1831e916772SGavin Shan struct pnv_phb *phb = pe->phb; 184caa58f80SGavin Shan unsigned int pe_num = pe->pe_number; 185184cd4a3SBenjamin Herrenschmidt 1861e916772SGavin Shan WARN_ON(pe->pdev); 1871e916772SGavin Shan 1881e916772SGavin Shan memset(pe, 0, sizeof(struct pnv_ioda_pe)); 189caa58f80SGavin Shan clear_bit(pe_num, phb->ioda.pe_alloc); 190184cd4a3SBenjamin Herrenschmidt } 191184cd4a3SBenjamin Herrenschmidt 192262af557SGuo Chao /* The default M64 BAR is shared by all PEs */ 193262af557SGuo Chao static int pnv_ioda2_init_m64(struct pnv_phb *phb) 194262af557SGuo Chao { 195262af557SGuo Chao const char *desc; 196262af557SGuo Chao struct resource *r; 197262af557SGuo Chao s64 rc; 198262af557SGuo Chao 199262af557SGuo Chao /* Configure the default M64 BAR */ 200262af557SGuo Chao rc = opal_pci_set_phb_mem_window(phb->opal_id, 201262af557SGuo Chao OPAL_M64_WINDOW_TYPE, 202262af557SGuo Chao phb->ioda.m64_bar_idx, 203262af557SGuo Chao phb->ioda.m64_base, 204262af557SGuo Chao 0, /* unused */ 205262af557SGuo Chao phb->ioda.m64_size); 206262af557SGuo Chao if (rc != OPAL_SUCCESS) { 207262af557SGuo Chao desc = "configuring"; 208262af557SGuo Chao goto fail; 209262af557SGuo Chao } 210262af557SGuo Chao 211262af557SGuo Chao /* Enable the default M64 BAR */ 212262af557SGuo Chao rc = opal_pci_phb_mmio_enable(phb->opal_id, 213262af557SGuo Chao OPAL_M64_WINDOW_TYPE, 214262af557SGuo Chao phb->ioda.m64_bar_idx, 215262af557SGuo Chao OPAL_ENABLE_M64_SPLIT); 216262af557SGuo Chao if (rc != OPAL_SUCCESS) { 217262af557SGuo Chao desc = "enabling"; 218262af557SGuo Chao goto fail; 219262af557SGuo Chao } 220262af557SGuo Chao 221262af557SGuo Chao /* 22263803c39SGavin Shan * Exclude the segments for reserved and root bus PE, which 22363803c39SGavin Shan * are first or last two PEs. 224262af557SGuo Chao */ 225262af557SGuo Chao r = &phb->hose->mem_resources[1]; 22692b8f137SGavin Shan if (phb->ioda.reserved_pe_idx == 0) 22763803c39SGavin Shan r->start += (2 * phb->ioda.m64_segsize); 22892b8f137SGavin Shan else if (phb->ioda.reserved_pe_idx == (phb->ioda.total_pe_num - 1)) 22963803c39SGavin Shan r->end -= (2 * phb->ioda.m64_segsize); 230262af557SGuo Chao else 2311f52f176SRussell Currey pr_warn(" Cannot strip M64 segment for reserved PE#%x\n", 23292b8f137SGavin Shan phb->ioda.reserved_pe_idx); 233262af557SGuo Chao 234262af557SGuo Chao return 0; 235262af557SGuo Chao 236262af557SGuo Chao fail: 237262af557SGuo Chao pr_warn(" Failure %lld %s M64 BAR#%d\n", 238262af557SGuo Chao rc, desc, phb->ioda.m64_bar_idx); 239262af557SGuo Chao opal_pci_phb_mmio_enable(phb->opal_id, 240262af557SGuo Chao OPAL_M64_WINDOW_TYPE, 241262af557SGuo Chao phb->ioda.m64_bar_idx, 242262af557SGuo Chao OPAL_DISABLE_M64); 243262af557SGuo Chao return -EIO; 244262af557SGuo Chao } 245262af557SGuo Chao 246c430670aSGavin Shan static void pnv_ioda_reserve_dev_m64_pe(struct pci_dev *pdev, 24796a2f92bSGavin Shan unsigned long *pe_bitmap) 248262af557SGuo Chao { 24996a2f92bSGavin Shan struct pci_controller *hose = pci_bus_to_host(pdev->bus); 25096a2f92bSGavin Shan struct pnv_phb *phb = hose->private_data; 251262af557SGuo Chao struct resource *r; 25296a2f92bSGavin Shan resource_size_t base, sgsz, start, end; 25396a2f92bSGavin Shan int segno, i; 254262af557SGuo Chao 25596a2f92bSGavin Shan base = phb->ioda.m64_base; 25696a2f92bSGavin Shan sgsz = phb->ioda.m64_segsize; 25796a2f92bSGavin Shan for (i = 0; i <= PCI_ROM_RESOURCE; i++) { 25896a2f92bSGavin Shan r = &pdev->resource[i]; 2595958d19aSBenjamin Herrenschmidt if (!r->parent || !pnv_pci_is_m64(phb, r)) 260262af557SGuo Chao continue; 261262af557SGuo Chao 26296a2f92bSGavin Shan start = _ALIGN_DOWN(r->start - base, sgsz); 26396a2f92bSGavin Shan end = _ALIGN_UP(r->end - base, sgsz); 26496a2f92bSGavin Shan for (segno = start / sgsz; segno < end / sgsz; segno++) { 26596a2f92bSGavin Shan if (pe_bitmap) 26696a2f92bSGavin Shan set_bit(segno, pe_bitmap); 26796a2f92bSGavin Shan else 26896a2f92bSGavin Shan pnv_ioda_reserve_pe(phb, segno); 269262af557SGuo Chao } 270262af557SGuo Chao } 271262af557SGuo Chao } 272262af557SGuo Chao 27399451551SGavin Shan static int pnv_ioda1_init_m64(struct pnv_phb *phb) 27499451551SGavin Shan { 27599451551SGavin Shan struct resource *r; 27699451551SGavin Shan int index; 27799451551SGavin Shan 27899451551SGavin Shan /* 27999451551SGavin Shan * There are 16 M64 BARs, each of which has 8 segments. So 28099451551SGavin Shan * there are as many M64 segments as the maximum number of 28199451551SGavin Shan * PEs, which is 128. 28299451551SGavin Shan */ 28399451551SGavin Shan for (index = 0; index < PNV_IODA1_M64_NUM; index++) { 28499451551SGavin Shan unsigned long base, segsz = phb->ioda.m64_segsize; 28599451551SGavin Shan int64_t rc; 28699451551SGavin Shan 28799451551SGavin Shan base = phb->ioda.m64_base + 28899451551SGavin Shan index * PNV_IODA1_M64_SEGS * segsz; 28999451551SGavin Shan rc = opal_pci_set_phb_mem_window(phb->opal_id, 29099451551SGavin Shan OPAL_M64_WINDOW_TYPE, index, base, 0, 29199451551SGavin Shan PNV_IODA1_M64_SEGS * segsz); 29299451551SGavin Shan if (rc != OPAL_SUCCESS) { 2931f52f176SRussell Currey pr_warn(" Error %lld setting M64 PHB#%x-BAR#%d\n", 29499451551SGavin Shan rc, phb->hose->global_number, index); 29599451551SGavin Shan goto fail; 29699451551SGavin Shan } 29799451551SGavin Shan 29899451551SGavin Shan rc = opal_pci_phb_mmio_enable(phb->opal_id, 29999451551SGavin Shan OPAL_M64_WINDOW_TYPE, index, 30099451551SGavin Shan OPAL_ENABLE_M64_SPLIT); 30199451551SGavin Shan if (rc != OPAL_SUCCESS) { 3021f52f176SRussell Currey pr_warn(" Error %lld enabling M64 PHB#%x-BAR#%d\n", 30399451551SGavin Shan rc, phb->hose->global_number, index); 30499451551SGavin Shan goto fail; 30599451551SGavin Shan } 30699451551SGavin Shan } 30799451551SGavin Shan 30899451551SGavin Shan /* 30963803c39SGavin Shan * Exclude the segments for reserved and root bus PE, which 31063803c39SGavin Shan * are first or last two PEs. 31199451551SGavin Shan */ 31299451551SGavin Shan r = &phb->hose->mem_resources[1]; 31399451551SGavin Shan if (phb->ioda.reserved_pe_idx == 0) 31463803c39SGavin Shan r->start += (2 * phb->ioda.m64_segsize); 31599451551SGavin Shan else if (phb->ioda.reserved_pe_idx == (phb->ioda.total_pe_num - 1)) 31663803c39SGavin Shan r->end -= (2 * phb->ioda.m64_segsize); 31799451551SGavin Shan else 3181f52f176SRussell Currey WARN(1, "Wrong reserved PE#%x on PHB#%x\n", 31999451551SGavin Shan phb->ioda.reserved_pe_idx, phb->hose->global_number); 32099451551SGavin Shan 32199451551SGavin Shan return 0; 32299451551SGavin Shan 32399451551SGavin Shan fail: 32499451551SGavin Shan for ( ; index >= 0; index--) 32599451551SGavin Shan opal_pci_phb_mmio_enable(phb->opal_id, 32699451551SGavin Shan OPAL_M64_WINDOW_TYPE, index, OPAL_DISABLE_M64); 32799451551SGavin Shan 32899451551SGavin Shan return -EIO; 32999451551SGavin Shan } 33099451551SGavin Shan 331c430670aSGavin Shan static void pnv_ioda_reserve_m64_pe(struct pci_bus *bus, 33296a2f92bSGavin Shan unsigned long *pe_bitmap, 33396a2f92bSGavin Shan bool all) 334262af557SGuo Chao { 335262af557SGuo Chao struct pci_dev *pdev; 33696a2f92bSGavin Shan 33796a2f92bSGavin Shan list_for_each_entry(pdev, &bus->devices, bus_list) { 338c430670aSGavin Shan pnv_ioda_reserve_dev_m64_pe(pdev, pe_bitmap); 33996a2f92bSGavin Shan 34096a2f92bSGavin Shan if (all && pdev->subordinate) 341c430670aSGavin Shan pnv_ioda_reserve_m64_pe(pdev->subordinate, 34296a2f92bSGavin Shan pe_bitmap, all); 34396a2f92bSGavin Shan } 34496a2f92bSGavin Shan } 34596a2f92bSGavin Shan 3461e916772SGavin Shan static struct pnv_ioda_pe *pnv_ioda_pick_m64_pe(struct pci_bus *bus, bool all) 347262af557SGuo Chao { 34826ba248dSGavin Shan struct pci_controller *hose = pci_bus_to_host(bus); 34926ba248dSGavin Shan struct pnv_phb *phb = hose->private_data; 350262af557SGuo Chao struct pnv_ioda_pe *master_pe, *pe; 351262af557SGuo Chao unsigned long size, *pe_alloc; 35226ba248dSGavin Shan int i; 353262af557SGuo Chao 354262af557SGuo Chao /* Root bus shouldn't use M64 */ 355262af557SGuo Chao if (pci_is_root_bus(bus)) 3561e916772SGavin Shan return NULL; 357262af557SGuo Chao 358262af557SGuo Chao /* Allocate bitmap */ 35992b8f137SGavin Shan size = _ALIGN_UP(phb->ioda.total_pe_num / 8, sizeof(unsigned long)); 360262af557SGuo Chao pe_alloc = kzalloc(size, GFP_KERNEL); 361262af557SGuo Chao if (!pe_alloc) { 362262af557SGuo Chao pr_warn("%s: Out of memory !\n", 363262af557SGuo Chao __func__); 3641e916772SGavin Shan return NULL; 365262af557SGuo Chao } 366262af557SGuo Chao 36726ba248dSGavin Shan /* Figure out reserved PE numbers by the PE */ 368c430670aSGavin Shan pnv_ioda_reserve_m64_pe(bus, pe_alloc, all); 369262af557SGuo Chao 370262af557SGuo Chao /* 371262af557SGuo Chao * the current bus might not own M64 window and that's all 372262af557SGuo Chao * contributed by its child buses. For the case, we needn't 373262af557SGuo Chao * pick M64 dependent PE#. 374262af557SGuo Chao */ 37592b8f137SGavin Shan if (bitmap_empty(pe_alloc, phb->ioda.total_pe_num)) { 376262af557SGuo Chao kfree(pe_alloc); 3771e916772SGavin Shan return NULL; 378262af557SGuo Chao } 379262af557SGuo Chao 380262af557SGuo Chao /* 381262af557SGuo Chao * Figure out the master PE and put all slave PEs to master 382262af557SGuo Chao * PE's list to form compound PE. 383262af557SGuo Chao */ 384262af557SGuo Chao master_pe = NULL; 385262af557SGuo Chao i = -1; 38692b8f137SGavin Shan while ((i = find_next_bit(pe_alloc, phb->ioda.total_pe_num, i + 1)) < 38792b8f137SGavin Shan phb->ioda.total_pe_num) { 388262af557SGuo Chao pe = &phb->ioda.pe_array[i]; 389262af557SGuo Chao 39093289d8cSGavin Shan phb->ioda.m64_segmap[pe->pe_number] = pe->pe_number; 391262af557SGuo Chao if (!master_pe) { 392262af557SGuo Chao pe->flags |= PNV_IODA_PE_MASTER; 393262af557SGuo Chao INIT_LIST_HEAD(&pe->slaves); 394262af557SGuo Chao master_pe = pe; 395262af557SGuo Chao } else { 396262af557SGuo Chao pe->flags |= PNV_IODA_PE_SLAVE; 397262af557SGuo Chao pe->master = master_pe; 398262af557SGuo Chao list_add_tail(&pe->list, &master_pe->slaves); 399262af557SGuo Chao } 40099451551SGavin Shan 40199451551SGavin Shan /* 40299451551SGavin Shan * P7IOC supports M64DT, which helps mapping M64 segment 40399451551SGavin Shan * to one particular PE#. However, PHB3 has fixed mapping 40499451551SGavin Shan * between M64 segment and PE#. In order to have same logic 40599451551SGavin Shan * for P7IOC and PHB3, we enforce fixed mapping between M64 40699451551SGavin Shan * segment and PE# on P7IOC. 40799451551SGavin Shan */ 40899451551SGavin Shan if (phb->type == PNV_PHB_IODA1) { 40999451551SGavin Shan int64_t rc; 41099451551SGavin Shan 41199451551SGavin Shan rc = opal_pci_map_pe_mmio_window(phb->opal_id, 41299451551SGavin Shan pe->pe_number, OPAL_M64_WINDOW_TYPE, 41399451551SGavin Shan pe->pe_number / PNV_IODA1_M64_SEGS, 41499451551SGavin Shan pe->pe_number % PNV_IODA1_M64_SEGS); 41599451551SGavin Shan if (rc != OPAL_SUCCESS) 4161f52f176SRussell Currey pr_warn("%s: Error %lld mapping M64 for PHB#%x-PE#%x\n", 41799451551SGavin Shan __func__, rc, phb->hose->global_number, 41899451551SGavin Shan pe->pe_number); 41999451551SGavin Shan } 420262af557SGuo Chao } 421262af557SGuo Chao 422262af557SGuo Chao kfree(pe_alloc); 4231e916772SGavin Shan return master_pe; 424262af557SGuo Chao } 425262af557SGuo Chao 426262af557SGuo Chao static void __init pnv_ioda_parse_m64_window(struct pnv_phb *phb) 427262af557SGuo Chao { 428262af557SGuo Chao struct pci_controller *hose = phb->hose; 429262af557SGuo Chao struct device_node *dn = hose->dn; 430262af557SGuo Chao struct resource *res; 431a1339fafSBenjamin Herrenschmidt u32 m64_range[2], i; 4320e7736c6SGavin Shan const __be32 *r; 433262af557SGuo Chao u64 pci_addr; 434262af557SGuo Chao 43599451551SGavin Shan if (phb->type != PNV_PHB_IODA1 && phb->type != PNV_PHB_IODA2) { 4361665c4a8SGavin Shan pr_info(" Not support M64 window\n"); 4371665c4a8SGavin Shan return; 4381665c4a8SGavin Shan } 4391665c4a8SGavin Shan 440e4d54f71SStewart Smith if (!firmware_has_feature(FW_FEATURE_OPAL)) { 441262af557SGuo Chao pr_info(" Firmware too old to support M64 window\n"); 442262af557SGuo Chao return; 443262af557SGuo Chao } 444262af557SGuo Chao 445262af557SGuo Chao r = of_get_property(dn, "ibm,opal-m64-window", NULL); 446262af557SGuo Chao if (!r) { 447b7c670d6SRob Herring pr_info(" No <ibm,opal-m64-window> on %pOF\n", 448b7c670d6SRob Herring dn); 449262af557SGuo Chao return; 450262af557SGuo Chao } 451262af557SGuo Chao 452a1339fafSBenjamin Herrenschmidt /* 453a1339fafSBenjamin Herrenschmidt * Find the available M64 BAR range and pickup the last one for 454a1339fafSBenjamin Herrenschmidt * covering the whole 64-bits space. We support only one range. 455a1339fafSBenjamin Herrenschmidt */ 456a1339fafSBenjamin Herrenschmidt if (of_property_read_u32_array(dn, "ibm,opal-available-m64-ranges", 457a1339fafSBenjamin Herrenschmidt m64_range, 2)) { 458a1339fafSBenjamin Herrenschmidt /* In absence of the property, assume 0..15 */ 459a1339fafSBenjamin Herrenschmidt m64_range[0] = 0; 460a1339fafSBenjamin Herrenschmidt m64_range[1] = 16; 461a1339fafSBenjamin Herrenschmidt } 462a1339fafSBenjamin Herrenschmidt /* We only support 64 bits in our allocator */ 463a1339fafSBenjamin Herrenschmidt if (m64_range[1] > 63) { 464a1339fafSBenjamin Herrenschmidt pr_warn("%s: Limiting M64 range to 63 (from %d) on PHB#%x\n", 465a1339fafSBenjamin Herrenschmidt __func__, m64_range[1], phb->hose->global_number); 466a1339fafSBenjamin Herrenschmidt m64_range[1] = 63; 467a1339fafSBenjamin Herrenschmidt } 468a1339fafSBenjamin Herrenschmidt /* Empty range, no m64 */ 469a1339fafSBenjamin Herrenschmidt if (m64_range[1] <= m64_range[0]) { 470a1339fafSBenjamin Herrenschmidt pr_warn("%s: M64 empty, disabling M64 usage on PHB#%x\n", 471a1339fafSBenjamin Herrenschmidt __func__, phb->hose->global_number); 472a1339fafSBenjamin Herrenschmidt return; 473a1339fafSBenjamin Herrenschmidt } 474a1339fafSBenjamin Herrenschmidt 475a1339fafSBenjamin Herrenschmidt /* Configure M64 informations */ 476262af557SGuo Chao res = &hose->mem_resources[1]; 477e80c4e7cSGavin Shan res->name = dn->full_name; 478262af557SGuo Chao res->start = of_translate_address(dn, r + 2); 479262af557SGuo Chao res->end = res->start + of_read_number(r + 4, 2) - 1; 480262af557SGuo Chao res->flags = (IORESOURCE_MEM | IORESOURCE_MEM_64 | IORESOURCE_PREFETCH); 481262af557SGuo Chao pci_addr = of_read_number(r, 2); 482262af557SGuo Chao hose->mem_offset[1] = res->start - pci_addr; 483262af557SGuo Chao 484262af557SGuo Chao phb->ioda.m64_size = resource_size(res); 48592b8f137SGavin Shan phb->ioda.m64_segsize = phb->ioda.m64_size / phb->ioda.total_pe_num; 486262af557SGuo Chao phb->ioda.m64_base = pci_addr; 487262af557SGuo Chao 488a1339fafSBenjamin Herrenschmidt /* This lines up nicely with the display from processing OF ranges */ 489a1339fafSBenjamin Herrenschmidt pr_info(" MEM 0x%016llx..0x%016llx -> 0x%016llx (M64 #%d..%d)\n", 490a1339fafSBenjamin Herrenschmidt res->start, res->end, pci_addr, m64_range[0], 491a1339fafSBenjamin Herrenschmidt m64_range[0] + m64_range[1] - 1); 492a1339fafSBenjamin Herrenschmidt 493a1339fafSBenjamin Herrenschmidt /* Mark all M64 used up by default */ 494a1339fafSBenjamin Herrenschmidt phb->ioda.m64_bar_alloc = (unsigned long)-1; 495e9863e68SWei Yang 496262af557SGuo Chao /* Use last M64 BAR to cover M64 window */ 497a1339fafSBenjamin Herrenschmidt m64_range[1]--; 498a1339fafSBenjamin Herrenschmidt phb->ioda.m64_bar_idx = m64_range[0] + m64_range[1]; 499a1339fafSBenjamin Herrenschmidt 500a1339fafSBenjamin Herrenschmidt pr_info(" Using M64 #%d as default window\n", phb->ioda.m64_bar_idx); 501a1339fafSBenjamin Herrenschmidt 502a1339fafSBenjamin Herrenschmidt /* Mark remaining ones free */ 503a1339fafSBenjamin Herrenschmidt for (i = m64_range[0]; i < m64_range[1]; i++) 504a1339fafSBenjamin Herrenschmidt clear_bit(i, &phb->ioda.m64_bar_alloc); 505a1339fafSBenjamin Herrenschmidt 506a1339fafSBenjamin Herrenschmidt /* 507a1339fafSBenjamin Herrenschmidt * Setup init functions for M64 based on IODA version, IODA3 uses 508a1339fafSBenjamin Herrenschmidt * the IODA2 code. 509a1339fafSBenjamin Herrenschmidt */ 51099451551SGavin Shan if (phb->type == PNV_PHB_IODA1) 51199451551SGavin Shan phb->init_m64 = pnv_ioda1_init_m64; 51299451551SGavin Shan else 513262af557SGuo Chao phb->init_m64 = pnv_ioda2_init_m64; 514c430670aSGavin Shan phb->reserve_m64_pe = pnv_ioda_reserve_m64_pe; 515c430670aSGavin Shan phb->pick_m64_pe = pnv_ioda_pick_m64_pe; 516262af557SGuo Chao } 517262af557SGuo Chao 51849dec922SGavin Shan static void pnv_ioda_freeze_pe(struct pnv_phb *phb, int pe_no) 51949dec922SGavin Shan { 52049dec922SGavin Shan struct pnv_ioda_pe *pe = &phb->ioda.pe_array[pe_no]; 52149dec922SGavin Shan struct pnv_ioda_pe *slave; 52249dec922SGavin Shan s64 rc; 52349dec922SGavin Shan 52449dec922SGavin Shan /* Fetch master PE */ 52549dec922SGavin Shan if (pe->flags & PNV_IODA_PE_SLAVE) { 52649dec922SGavin Shan pe = pe->master; 527ec8e4e9dSGavin Shan if (WARN_ON(!pe || !(pe->flags & PNV_IODA_PE_MASTER))) 528ec8e4e9dSGavin Shan return; 529ec8e4e9dSGavin Shan 53049dec922SGavin Shan pe_no = pe->pe_number; 53149dec922SGavin Shan } 53249dec922SGavin Shan 53349dec922SGavin Shan /* Freeze master PE */ 53449dec922SGavin Shan rc = opal_pci_eeh_freeze_set(phb->opal_id, 53549dec922SGavin Shan pe_no, 53649dec922SGavin Shan OPAL_EEH_ACTION_SET_FREEZE_ALL); 53749dec922SGavin Shan if (rc != OPAL_SUCCESS) { 53849dec922SGavin Shan pr_warn("%s: Failure %lld freezing PHB#%x-PE#%x\n", 53949dec922SGavin Shan __func__, rc, phb->hose->global_number, pe_no); 54049dec922SGavin Shan return; 54149dec922SGavin Shan } 54249dec922SGavin Shan 54349dec922SGavin Shan /* Freeze slave PEs */ 54449dec922SGavin Shan if (!(pe->flags & PNV_IODA_PE_MASTER)) 54549dec922SGavin Shan return; 54649dec922SGavin Shan 54749dec922SGavin Shan list_for_each_entry(slave, &pe->slaves, list) { 54849dec922SGavin Shan rc = opal_pci_eeh_freeze_set(phb->opal_id, 54949dec922SGavin Shan slave->pe_number, 55049dec922SGavin Shan OPAL_EEH_ACTION_SET_FREEZE_ALL); 55149dec922SGavin Shan if (rc != OPAL_SUCCESS) 55249dec922SGavin Shan pr_warn("%s: Failure %lld freezing PHB#%x-PE#%x\n", 55349dec922SGavin Shan __func__, rc, phb->hose->global_number, 55449dec922SGavin Shan slave->pe_number); 55549dec922SGavin Shan } 55649dec922SGavin Shan } 55749dec922SGavin Shan 558e51df2c1SAnton Blanchard static int pnv_ioda_unfreeze_pe(struct pnv_phb *phb, int pe_no, int opt) 55949dec922SGavin Shan { 56049dec922SGavin Shan struct pnv_ioda_pe *pe, *slave; 56149dec922SGavin Shan s64 rc; 56249dec922SGavin Shan 56349dec922SGavin Shan /* Find master PE */ 56449dec922SGavin Shan pe = &phb->ioda.pe_array[pe_no]; 56549dec922SGavin Shan if (pe->flags & PNV_IODA_PE_SLAVE) { 56649dec922SGavin Shan pe = pe->master; 56749dec922SGavin Shan WARN_ON(!pe || !(pe->flags & PNV_IODA_PE_MASTER)); 56849dec922SGavin Shan pe_no = pe->pe_number; 56949dec922SGavin Shan } 57049dec922SGavin Shan 57149dec922SGavin Shan /* Clear frozen state for master PE */ 57249dec922SGavin Shan rc = opal_pci_eeh_freeze_clear(phb->opal_id, pe_no, opt); 57349dec922SGavin Shan if (rc != OPAL_SUCCESS) { 57449dec922SGavin Shan pr_warn("%s: Failure %lld clear %d on PHB#%x-PE#%x\n", 57549dec922SGavin Shan __func__, rc, opt, phb->hose->global_number, pe_no); 57649dec922SGavin Shan return -EIO; 57749dec922SGavin Shan } 57849dec922SGavin Shan 57949dec922SGavin Shan if (!(pe->flags & PNV_IODA_PE_MASTER)) 58049dec922SGavin Shan return 0; 58149dec922SGavin Shan 58249dec922SGavin Shan /* Clear frozen state for slave PEs */ 58349dec922SGavin Shan list_for_each_entry(slave, &pe->slaves, list) { 58449dec922SGavin Shan rc = opal_pci_eeh_freeze_clear(phb->opal_id, 58549dec922SGavin Shan slave->pe_number, 58649dec922SGavin Shan opt); 58749dec922SGavin Shan if (rc != OPAL_SUCCESS) { 58849dec922SGavin Shan pr_warn("%s: Failure %lld clear %d on PHB#%x-PE#%x\n", 58949dec922SGavin Shan __func__, rc, opt, phb->hose->global_number, 59049dec922SGavin Shan slave->pe_number); 59149dec922SGavin Shan return -EIO; 59249dec922SGavin Shan } 59349dec922SGavin Shan } 59449dec922SGavin Shan 59549dec922SGavin Shan return 0; 59649dec922SGavin Shan } 59749dec922SGavin Shan 59849dec922SGavin Shan static int pnv_ioda_get_pe_state(struct pnv_phb *phb, int pe_no) 59949dec922SGavin Shan { 60049dec922SGavin Shan struct pnv_ioda_pe *slave, *pe; 60149dec922SGavin Shan u8 fstate, state; 60249dec922SGavin Shan __be16 pcierr; 60349dec922SGavin Shan s64 rc; 60449dec922SGavin Shan 60549dec922SGavin Shan /* Sanity check on PE number */ 60692b8f137SGavin Shan if (pe_no < 0 || pe_no >= phb->ioda.total_pe_num) 60749dec922SGavin Shan return OPAL_EEH_STOPPED_PERM_UNAVAIL; 60849dec922SGavin Shan 60949dec922SGavin Shan /* 61049dec922SGavin Shan * Fetch the master PE and the PE instance might be 61149dec922SGavin Shan * not initialized yet. 61249dec922SGavin Shan */ 61349dec922SGavin Shan pe = &phb->ioda.pe_array[pe_no]; 61449dec922SGavin Shan if (pe->flags & PNV_IODA_PE_SLAVE) { 61549dec922SGavin Shan pe = pe->master; 61649dec922SGavin Shan WARN_ON(!pe || !(pe->flags & PNV_IODA_PE_MASTER)); 61749dec922SGavin Shan pe_no = pe->pe_number; 61849dec922SGavin Shan } 61949dec922SGavin Shan 62049dec922SGavin Shan /* Check the master PE */ 62149dec922SGavin Shan rc = opal_pci_eeh_freeze_status(phb->opal_id, pe_no, 62249dec922SGavin Shan &state, &pcierr, NULL); 62349dec922SGavin Shan if (rc != OPAL_SUCCESS) { 62449dec922SGavin Shan pr_warn("%s: Failure %lld getting " 62549dec922SGavin Shan "PHB#%x-PE#%x state\n", 62649dec922SGavin Shan __func__, rc, 62749dec922SGavin Shan phb->hose->global_number, pe_no); 62849dec922SGavin Shan return OPAL_EEH_STOPPED_TEMP_UNAVAIL; 62949dec922SGavin Shan } 63049dec922SGavin Shan 63149dec922SGavin Shan /* Check the slave PE */ 63249dec922SGavin Shan if (!(pe->flags & PNV_IODA_PE_MASTER)) 63349dec922SGavin Shan return state; 63449dec922SGavin Shan 63549dec922SGavin Shan list_for_each_entry(slave, &pe->slaves, list) { 63649dec922SGavin Shan rc = opal_pci_eeh_freeze_status(phb->opal_id, 63749dec922SGavin Shan slave->pe_number, 63849dec922SGavin Shan &fstate, 63949dec922SGavin Shan &pcierr, 64049dec922SGavin Shan NULL); 64149dec922SGavin Shan if (rc != OPAL_SUCCESS) { 64249dec922SGavin Shan pr_warn("%s: Failure %lld getting " 64349dec922SGavin Shan "PHB#%x-PE#%x state\n", 64449dec922SGavin Shan __func__, rc, 64549dec922SGavin Shan phb->hose->global_number, slave->pe_number); 64649dec922SGavin Shan return OPAL_EEH_STOPPED_TEMP_UNAVAIL; 64749dec922SGavin Shan } 64849dec922SGavin Shan 64949dec922SGavin Shan /* 65049dec922SGavin Shan * Override the result based on the ascending 65149dec922SGavin Shan * priority. 65249dec922SGavin Shan */ 65349dec922SGavin Shan if (fstate > state) 65449dec922SGavin Shan state = fstate; 65549dec922SGavin Shan } 65649dec922SGavin Shan 65749dec922SGavin Shan return state; 65849dec922SGavin Shan } 65949dec922SGavin Shan 660184cd4a3SBenjamin Herrenschmidt /* Currently those 2 are only used when MSIs are enabled, this will change 661184cd4a3SBenjamin Herrenschmidt * but in the meantime, we need to protect them to avoid warnings 662184cd4a3SBenjamin Herrenschmidt */ 663184cd4a3SBenjamin Herrenschmidt #ifdef CONFIG_PCI_MSI 664f456834aSIan Munsie struct pnv_ioda_pe *pnv_ioda_get_pe(struct pci_dev *dev) 665184cd4a3SBenjamin Herrenschmidt { 666184cd4a3SBenjamin Herrenschmidt struct pci_controller *hose = pci_bus_to_host(dev->bus); 667184cd4a3SBenjamin Herrenschmidt struct pnv_phb *phb = hose->private_data; 668b72c1f65SBenjamin Herrenschmidt struct pci_dn *pdn = pci_get_pdn(dev); 669184cd4a3SBenjamin Herrenschmidt 670184cd4a3SBenjamin Herrenschmidt if (!pdn) 671184cd4a3SBenjamin Herrenschmidt return NULL; 672184cd4a3SBenjamin Herrenschmidt if (pdn->pe_number == IODA_INVALID_PE) 673184cd4a3SBenjamin Herrenschmidt return NULL; 674184cd4a3SBenjamin Herrenschmidt return &phb->ioda.pe_array[pdn->pe_number]; 675184cd4a3SBenjamin Herrenschmidt } 676184cd4a3SBenjamin Herrenschmidt #endif /* CONFIG_PCI_MSI */ 677184cd4a3SBenjamin Herrenschmidt 678b131a842SGavin Shan static int pnv_ioda_set_one_peltv(struct pnv_phb *phb, 679b131a842SGavin Shan struct pnv_ioda_pe *parent, 680b131a842SGavin Shan struct pnv_ioda_pe *child, 681b131a842SGavin Shan bool is_add) 682b131a842SGavin Shan { 683b131a842SGavin Shan const char *desc = is_add ? "adding" : "removing"; 684b131a842SGavin Shan uint8_t op = is_add ? OPAL_ADD_PE_TO_DOMAIN : 685b131a842SGavin Shan OPAL_REMOVE_PE_FROM_DOMAIN; 686b131a842SGavin Shan struct pnv_ioda_pe *slave; 687b131a842SGavin Shan long rc; 688b131a842SGavin Shan 689b131a842SGavin Shan /* Parent PE affects child PE */ 690b131a842SGavin Shan rc = opal_pci_set_peltv(phb->opal_id, parent->pe_number, 691b131a842SGavin Shan child->pe_number, op); 692b131a842SGavin Shan if (rc != OPAL_SUCCESS) { 693b131a842SGavin Shan pe_warn(child, "OPAL error %ld %s to parent PELTV\n", 694b131a842SGavin Shan rc, desc); 695b131a842SGavin Shan return -ENXIO; 696b131a842SGavin Shan } 697b131a842SGavin Shan 698b131a842SGavin Shan if (!(child->flags & PNV_IODA_PE_MASTER)) 699b131a842SGavin Shan return 0; 700b131a842SGavin Shan 701b131a842SGavin Shan /* Compound case: parent PE affects slave PEs */ 702b131a842SGavin Shan list_for_each_entry(slave, &child->slaves, list) { 703b131a842SGavin Shan rc = opal_pci_set_peltv(phb->opal_id, parent->pe_number, 704b131a842SGavin Shan slave->pe_number, op); 705b131a842SGavin Shan if (rc != OPAL_SUCCESS) { 706b131a842SGavin Shan pe_warn(slave, "OPAL error %ld %s to parent PELTV\n", 707b131a842SGavin Shan rc, desc); 708b131a842SGavin Shan return -ENXIO; 709b131a842SGavin Shan } 710b131a842SGavin Shan } 711b131a842SGavin Shan 712b131a842SGavin Shan return 0; 713b131a842SGavin Shan } 714b131a842SGavin Shan 715b131a842SGavin Shan static int pnv_ioda_set_peltv(struct pnv_phb *phb, 716b131a842SGavin Shan struct pnv_ioda_pe *pe, 717b131a842SGavin Shan bool is_add) 718b131a842SGavin Shan { 719b131a842SGavin Shan struct pnv_ioda_pe *slave; 720781a868fSWei Yang struct pci_dev *pdev = NULL; 721b131a842SGavin Shan int ret; 722b131a842SGavin Shan 723b131a842SGavin Shan /* 724b131a842SGavin Shan * Clear PE frozen state. If it's master PE, we need 725b131a842SGavin Shan * clear slave PE frozen state as well. 726b131a842SGavin Shan */ 727b131a842SGavin Shan if (is_add) { 728b131a842SGavin Shan opal_pci_eeh_freeze_clear(phb->opal_id, pe->pe_number, 729b131a842SGavin Shan OPAL_EEH_ACTION_CLEAR_FREEZE_ALL); 730b131a842SGavin Shan if (pe->flags & PNV_IODA_PE_MASTER) { 731b131a842SGavin Shan list_for_each_entry(slave, &pe->slaves, list) 732b131a842SGavin Shan opal_pci_eeh_freeze_clear(phb->opal_id, 733b131a842SGavin Shan slave->pe_number, 734b131a842SGavin Shan OPAL_EEH_ACTION_CLEAR_FREEZE_ALL); 735b131a842SGavin Shan } 736b131a842SGavin Shan } 737b131a842SGavin Shan 738b131a842SGavin Shan /* 739b131a842SGavin Shan * Associate PE in PELT. We need add the PE into the 740b131a842SGavin Shan * corresponding PELT-V as well. Otherwise, the error 741b131a842SGavin Shan * originated from the PE might contribute to other 742b131a842SGavin Shan * PEs. 743b131a842SGavin Shan */ 744b131a842SGavin Shan ret = pnv_ioda_set_one_peltv(phb, pe, pe, is_add); 745b131a842SGavin Shan if (ret) 746b131a842SGavin Shan return ret; 747b131a842SGavin Shan 748b131a842SGavin Shan /* For compound PEs, any one affects all of them */ 749b131a842SGavin Shan if (pe->flags & PNV_IODA_PE_MASTER) { 750b131a842SGavin Shan list_for_each_entry(slave, &pe->slaves, list) { 751b131a842SGavin Shan ret = pnv_ioda_set_one_peltv(phb, slave, pe, is_add); 752b131a842SGavin Shan if (ret) 753b131a842SGavin Shan return ret; 754b131a842SGavin Shan } 755b131a842SGavin Shan } 756b131a842SGavin Shan 757b131a842SGavin Shan if (pe->flags & (PNV_IODA_PE_BUS_ALL | PNV_IODA_PE_BUS)) 758b131a842SGavin Shan pdev = pe->pbus->self; 759781a868fSWei Yang else if (pe->flags & PNV_IODA_PE_DEV) 760b131a842SGavin Shan pdev = pe->pdev->bus->self; 761781a868fSWei Yang #ifdef CONFIG_PCI_IOV 762781a868fSWei Yang else if (pe->flags & PNV_IODA_PE_VF) 763283e2d8aSGavin Shan pdev = pe->parent_dev; 764781a868fSWei Yang #endif /* CONFIG_PCI_IOV */ 765b131a842SGavin Shan while (pdev) { 766b131a842SGavin Shan struct pci_dn *pdn = pci_get_pdn(pdev); 767b131a842SGavin Shan struct pnv_ioda_pe *parent; 768b131a842SGavin Shan 769b131a842SGavin Shan if (pdn && pdn->pe_number != IODA_INVALID_PE) { 770b131a842SGavin Shan parent = &phb->ioda.pe_array[pdn->pe_number]; 771b131a842SGavin Shan ret = pnv_ioda_set_one_peltv(phb, parent, pe, is_add); 772b131a842SGavin Shan if (ret) 773b131a842SGavin Shan return ret; 774b131a842SGavin Shan } 775b131a842SGavin Shan 776b131a842SGavin Shan pdev = pdev->bus->self; 777b131a842SGavin Shan } 778b131a842SGavin Shan 779b131a842SGavin Shan return 0; 780b131a842SGavin Shan } 781b131a842SGavin Shan 782781a868fSWei Yang static int pnv_ioda_deconfigure_pe(struct pnv_phb *phb, struct pnv_ioda_pe *pe) 783781a868fSWei Yang { 784781a868fSWei Yang struct pci_dev *parent; 785781a868fSWei Yang uint8_t bcomp, dcomp, fcomp; 786781a868fSWei Yang int64_t rc; 787781a868fSWei Yang long rid_end, rid; 788781a868fSWei Yang 789781a868fSWei Yang /* Currently, we just deconfigure VF PE. Bus PE will always there.*/ 790781a868fSWei Yang if (pe->pbus) { 791781a868fSWei Yang int count; 792781a868fSWei Yang 793781a868fSWei Yang dcomp = OPAL_IGNORE_RID_DEVICE_NUMBER; 794781a868fSWei Yang fcomp = OPAL_IGNORE_RID_FUNCTION_NUMBER; 795781a868fSWei Yang parent = pe->pbus->self; 796781a868fSWei Yang if (pe->flags & PNV_IODA_PE_BUS_ALL) 797781a868fSWei Yang count = pe->pbus->busn_res.end - pe->pbus->busn_res.start + 1; 798781a868fSWei Yang else 799781a868fSWei Yang count = 1; 800781a868fSWei Yang 801781a868fSWei Yang switch(count) { 802781a868fSWei Yang case 1: bcomp = OpalPciBusAll; break; 803781a868fSWei Yang case 2: bcomp = OpalPciBus7Bits; break; 804781a868fSWei Yang case 4: bcomp = OpalPciBus6Bits; break; 805781a868fSWei Yang case 8: bcomp = OpalPciBus5Bits; break; 806781a868fSWei Yang case 16: bcomp = OpalPciBus4Bits; break; 807781a868fSWei Yang case 32: bcomp = OpalPciBus3Bits; break; 808781a868fSWei Yang default: 809781a868fSWei Yang dev_err(&pe->pbus->dev, "Number of subordinate buses %d unsupported\n", 810781a868fSWei Yang count); 811781a868fSWei Yang /* Do an exact match only */ 812781a868fSWei Yang bcomp = OpalPciBusAll; 813781a868fSWei Yang } 814781a868fSWei Yang rid_end = pe->rid + (count << 8); 815781a868fSWei Yang } else { 81693e01a50SGavin Shan #ifdef CONFIG_PCI_IOV 817781a868fSWei Yang if (pe->flags & PNV_IODA_PE_VF) 818781a868fSWei Yang parent = pe->parent_dev; 819781a868fSWei Yang else 82093e01a50SGavin Shan #endif 821781a868fSWei Yang parent = pe->pdev->bus->self; 822781a868fSWei Yang bcomp = OpalPciBusAll; 823781a868fSWei Yang dcomp = OPAL_COMPARE_RID_DEVICE_NUMBER; 824781a868fSWei Yang fcomp = OPAL_COMPARE_RID_FUNCTION_NUMBER; 825781a868fSWei Yang rid_end = pe->rid + 1; 826781a868fSWei Yang } 827781a868fSWei Yang 828781a868fSWei Yang /* Clear the reverse map */ 829781a868fSWei Yang for (rid = pe->rid; rid < rid_end; rid++) 830c127562aSGavin Shan phb->ioda.pe_rmap[rid] = IODA_INVALID_PE; 831781a868fSWei Yang 832781a868fSWei Yang /* Release from all parents PELT-V */ 833781a868fSWei Yang while (parent) { 834781a868fSWei Yang struct pci_dn *pdn = pci_get_pdn(parent); 835781a868fSWei Yang if (pdn && pdn->pe_number != IODA_INVALID_PE) { 836781a868fSWei Yang rc = opal_pci_set_peltv(phb->opal_id, pdn->pe_number, 837781a868fSWei Yang pe->pe_number, OPAL_REMOVE_PE_FROM_DOMAIN); 838781a868fSWei Yang /* XXX What to do in case of error ? */ 839781a868fSWei Yang } 840781a868fSWei Yang parent = parent->bus->self; 841781a868fSWei Yang } 842781a868fSWei Yang 843f951e510SGavin Shan opal_pci_eeh_freeze_clear(phb->opal_id, pe->pe_number, 844781a868fSWei Yang OPAL_EEH_ACTION_CLEAR_FREEZE_ALL); 845781a868fSWei Yang 846781a868fSWei Yang /* Disassociate PE in PELT */ 847781a868fSWei Yang rc = opal_pci_set_peltv(phb->opal_id, pe->pe_number, 848781a868fSWei Yang pe->pe_number, OPAL_REMOVE_PE_FROM_DOMAIN); 849781a868fSWei Yang if (rc) 850781a868fSWei Yang pe_warn(pe, "OPAL error %ld remove self from PELTV\n", rc); 851781a868fSWei Yang rc = opal_pci_set_pe(phb->opal_id, pe->pe_number, pe->rid, 852781a868fSWei Yang bcomp, dcomp, fcomp, OPAL_UNMAP_PE); 853781a868fSWei Yang if (rc) 854781a868fSWei Yang pe_err(pe, "OPAL error %ld trying to setup PELT table\n", rc); 855781a868fSWei Yang 856781a868fSWei Yang pe->pbus = NULL; 857781a868fSWei Yang pe->pdev = NULL; 85893e01a50SGavin Shan #ifdef CONFIG_PCI_IOV 859781a868fSWei Yang pe->parent_dev = NULL; 86093e01a50SGavin Shan #endif 861781a868fSWei Yang 862781a868fSWei Yang return 0; 863781a868fSWei Yang } 864781a868fSWei Yang 865cad5cef6SGreg Kroah-Hartman static int pnv_ioda_configure_pe(struct pnv_phb *phb, struct pnv_ioda_pe *pe) 866184cd4a3SBenjamin Herrenschmidt { 867184cd4a3SBenjamin Herrenschmidt struct pci_dev *parent; 868184cd4a3SBenjamin Herrenschmidt uint8_t bcomp, dcomp, fcomp; 869184cd4a3SBenjamin Herrenschmidt long rc, rid_end, rid; 870184cd4a3SBenjamin Herrenschmidt 871184cd4a3SBenjamin Herrenschmidt /* Bus validation ? */ 872184cd4a3SBenjamin Herrenschmidt if (pe->pbus) { 873184cd4a3SBenjamin Herrenschmidt int count; 874184cd4a3SBenjamin Herrenschmidt 875184cd4a3SBenjamin Herrenschmidt dcomp = OPAL_IGNORE_RID_DEVICE_NUMBER; 876184cd4a3SBenjamin Herrenschmidt fcomp = OPAL_IGNORE_RID_FUNCTION_NUMBER; 877184cd4a3SBenjamin Herrenschmidt parent = pe->pbus->self; 878fb446ad0SGavin Shan if (pe->flags & PNV_IODA_PE_BUS_ALL) 879b918c62eSYinghai Lu count = pe->pbus->busn_res.end - pe->pbus->busn_res.start + 1; 880fb446ad0SGavin Shan else 881fb446ad0SGavin Shan count = 1; 882fb446ad0SGavin Shan 883184cd4a3SBenjamin Herrenschmidt switch(count) { 884184cd4a3SBenjamin Herrenschmidt case 1: bcomp = OpalPciBusAll; break; 885184cd4a3SBenjamin Herrenschmidt case 2: bcomp = OpalPciBus7Bits; break; 886184cd4a3SBenjamin Herrenschmidt case 4: bcomp = OpalPciBus6Bits; break; 887184cd4a3SBenjamin Herrenschmidt case 8: bcomp = OpalPciBus5Bits; break; 888184cd4a3SBenjamin Herrenschmidt case 16: bcomp = OpalPciBus4Bits; break; 889184cd4a3SBenjamin Herrenschmidt case 32: bcomp = OpalPciBus3Bits; break; 890184cd4a3SBenjamin Herrenschmidt default: 891781a868fSWei Yang dev_err(&pe->pbus->dev, "Number of subordinate buses %d unsupported\n", 892781a868fSWei Yang count); 893184cd4a3SBenjamin Herrenschmidt /* Do an exact match only */ 894184cd4a3SBenjamin Herrenschmidt bcomp = OpalPciBusAll; 895184cd4a3SBenjamin Herrenschmidt } 896184cd4a3SBenjamin Herrenschmidt rid_end = pe->rid + (count << 8); 897184cd4a3SBenjamin Herrenschmidt } else { 898781a868fSWei Yang #ifdef CONFIG_PCI_IOV 899781a868fSWei Yang if (pe->flags & PNV_IODA_PE_VF) 900781a868fSWei Yang parent = pe->parent_dev; 901781a868fSWei Yang else 902781a868fSWei Yang #endif /* CONFIG_PCI_IOV */ 903184cd4a3SBenjamin Herrenschmidt parent = pe->pdev->bus->self; 904184cd4a3SBenjamin Herrenschmidt bcomp = OpalPciBusAll; 905184cd4a3SBenjamin Herrenschmidt dcomp = OPAL_COMPARE_RID_DEVICE_NUMBER; 906184cd4a3SBenjamin Herrenschmidt fcomp = OPAL_COMPARE_RID_FUNCTION_NUMBER; 907184cd4a3SBenjamin Herrenschmidt rid_end = pe->rid + 1; 908184cd4a3SBenjamin Herrenschmidt } 909184cd4a3SBenjamin Herrenschmidt 910631ad691SGavin Shan /* 911631ad691SGavin Shan * Associate PE in PELT. We need add the PE into the 912631ad691SGavin Shan * corresponding PELT-V as well. Otherwise, the error 913631ad691SGavin Shan * originated from the PE might contribute to other 914631ad691SGavin Shan * PEs. 915631ad691SGavin Shan */ 916184cd4a3SBenjamin Herrenschmidt rc = opal_pci_set_pe(phb->opal_id, pe->pe_number, pe->rid, 917184cd4a3SBenjamin Herrenschmidt bcomp, dcomp, fcomp, OPAL_MAP_PE); 918184cd4a3SBenjamin Herrenschmidt if (rc) { 919184cd4a3SBenjamin Herrenschmidt pe_err(pe, "OPAL error %ld trying to setup PELT table\n", rc); 920184cd4a3SBenjamin Herrenschmidt return -ENXIO; 921184cd4a3SBenjamin Herrenschmidt } 922631ad691SGavin Shan 9235d2aa710SAlistair Popple /* 9245d2aa710SAlistair Popple * Configure PELTV. NPUs don't have a PELTV table so skip 9255d2aa710SAlistair Popple * configuration on them. 9265d2aa710SAlistair Popple */ 9275d2aa710SAlistair Popple if (phb->type != PNV_PHB_NPU) 928b131a842SGavin Shan pnv_ioda_set_peltv(phb, pe, true); 929184cd4a3SBenjamin Herrenschmidt 930184cd4a3SBenjamin Herrenschmidt /* Setup reverse map */ 931184cd4a3SBenjamin Herrenschmidt for (rid = pe->rid; rid < rid_end; rid++) 932184cd4a3SBenjamin Herrenschmidt phb->ioda.pe_rmap[rid] = pe->pe_number; 933184cd4a3SBenjamin Herrenschmidt 934184cd4a3SBenjamin Herrenschmidt /* Setup one MVTs on IODA1 */ 9354773f76bSGavin Shan if (phb->type != PNV_PHB_IODA1) { 9364773f76bSGavin Shan pe->mve_number = 0; 9374773f76bSGavin Shan goto out; 9384773f76bSGavin Shan } 9394773f76bSGavin Shan 940184cd4a3SBenjamin Herrenschmidt pe->mve_number = pe->pe_number; 9414773f76bSGavin Shan rc = opal_pci_set_mve(phb->opal_id, pe->mve_number, pe->pe_number); 9424773f76bSGavin Shan if (rc != OPAL_SUCCESS) { 9431f52f176SRussell Currey pe_err(pe, "OPAL error %ld setting up MVE %x\n", 944184cd4a3SBenjamin Herrenschmidt rc, pe->mve_number); 945184cd4a3SBenjamin Herrenschmidt pe->mve_number = -1; 946184cd4a3SBenjamin Herrenschmidt } else { 947184cd4a3SBenjamin Herrenschmidt rc = opal_pci_set_mve_enable(phb->opal_id, 948cee72d5bSBenjamin Herrenschmidt pe->mve_number, OPAL_ENABLE_MVE); 949184cd4a3SBenjamin Herrenschmidt if (rc) { 9501f52f176SRussell Currey pe_err(pe, "OPAL error %ld enabling MVE %x\n", 951184cd4a3SBenjamin Herrenschmidt rc, pe->mve_number); 952184cd4a3SBenjamin Herrenschmidt pe->mve_number = -1; 953184cd4a3SBenjamin Herrenschmidt } 954184cd4a3SBenjamin Herrenschmidt } 955184cd4a3SBenjamin Herrenschmidt 9564773f76bSGavin Shan out: 957184cd4a3SBenjamin Herrenschmidt return 0; 958184cd4a3SBenjamin Herrenschmidt } 959184cd4a3SBenjamin Herrenschmidt 960781a868fSWei Yang #ifdef CONFIG_PCI_IOV 961781a868fSWei Yang static int pnv_pci_vf_resource_shift(struct pci_dev *dev, int offset) 962781a868fSWei Yang { 963781a868fSWei Yang struct pci_dn *pdn = pci_get_pdn(dev); 964781a868fSWei Yang int i; 965781a868fSWei Yang struct resource *res, res2; 966781a868fSWei Yang resource_size_t size; 967781a868fSWei Yang u16 num_vfs; 968781a868fSWei Yang 969781a868fSWei Yang if (!dev->is_physfn) 970781a868fSWei Yang return -EINVAL; 971781a868fSWei Yang 972781a868fSWei Yang /* 973781a868fSWei Yang * "offset" is in VFs. The M64 windows are sized so that when they 974781a868fSWei Yang * are segmented, each segment is the same size as the IOV BAR. 975781a868fSWei Yang * Each segment is in a separate PE, and the high order bits of the 976781a868fSWei Yang * address are the PE number. Therefore, each VF's BAR is in a 977781a868fSWei Yang * separate PE, and changing the IOV BAR start address changes the 978781a868fSWei Yang * range of PEs the VFs are in. 979781a868fSWei Yang */ 980781a868fSWei Yang num_vfs = pdn->num_vfs; 981781a868fSWei Yang for (i = 0; i < PCI_SRIOV_NUM_BARS; i++) { 982781a868fSWei Yang res = &dev->resource[i + PCI_IOV_RESOURCES]; 983781a868fSWei Yang if (!res->flags || !res->parent) 984781a868fSWei Yang continue; 985781a868fSWei Yang 986781a868fSWei Yang /* 987781a868fSWei Yang * The actual IOV BAR range is determined by the start address 988781a868fSWei Yang * and the actual size for num_vfs VFs BAR. This check is to 989781a868fSWei Yang * make sure that after shifting, the range will not overlap 990781a868fSWei Yang * with another device. 991781a868fSWei Yang */ 992781a868fSWei Yang size = pci_iov_resource_size(dev, i + PCI_IOV_RESOURCES); 993781a868fSWei Yang res2.flags = res->flags; 994781a868fSWei Yang res2.start = res->start + (size * offset); 995781a868fSWei Yang res2.end = res2.start + (size * num_vfs) - 1; 996781a868fSWei Yang 997781a868fSWei Yang if (res2.end > res->end) { 998781a868fSWei Yang dev_err(&dev->dev, "VF BAR%d: %pR would extend past %pR (trying to enable %d VFs shifted by %d)\n", 999781a868fSWei Yang i, &res2, res, num_vfs, offset); 1000781a868fSWei Yang return -EBUSY; 1001781a868fSWei Yang } 1002781a868fSWei Yang } 1003781a868fSWei Yang 1004781a868fSWei Yang /* 1005d6f934fdSAlexey Kardashevskiy * Since M64 BAR shares segments among all possible 256 PEs, 1006d6f934fdSAlexey Kardashevskiy * we have to shift the beginning of PF IOV BAR to make it start from 1007d6f934fdSAlexey Kardashevskiy * the segment which belongs to the PE number assigned to the first VF. 1008d6f934fdSAlexey Kardashevskiy * This creates a "hole" in the /proc/iomem which could be used for 1009d6f934fdSAlexey Kardashevskiy * allocating other resources so we reserve this area below and 1010d6f934fdSAlexey Kardashevskiy * release when IOV is released. 1011781a868fSWei Yang */ 1012781a868fSWei Yang for (i = 0; i < PCI_SRIOV_NUM_BARS; i++) { 1013781a868fSWei Yang res = &dev->resource[i + PCI_IOV_RESOURCES]; 1014781a868fSWei Yang if (!res->flags || !res->parent) 1015781a868fSWei Yang continue; 1016781a868fSWei Yang 1017781a868fSWei Yang size = pci_iov_resource_size(dev, i + PCI_IOV_RESOURCES); 1018781a868fSWei Yang res2 = *res; 1019781a868fSWei Yang res->start += size * offset; 1020781a868fSWei Yang 102174703cc4SWei Yang dev_info(&dev->dev, "VF BAR%d: %pR shifted to %pR (%sabling %d VFs shifted by %d)\n", 102274703cc4SWei Yang i, &res2, res, (offset > 0) ? "En" : "Dis", 102374703cc4SWei Yang num_vfs, offset); 1024d6f934fdSAlexey Kardashevskiy 1025d6f934fdSAlexey Kardashevskiy if (offset < 0) { 1026d6f934fdSAlexey Kardashevskiy devm_release_resource(&dev->dev, &pdn->holes[i]); 1027d6f934fdSAlexey Kardashevskiy memset(&pdn->holes[i], 0, sizeof(pdn->holes[i])); 1028d6f934fdSAlexey Kardashevskiy } 1029d6f934fdSAlexey Kardashevskiy 1030781a868fSWei Yang pci_update_resource(dev, i + PCI_IOV_RESOURCES); 1031d6f934fdSAlexey Kardashevskiy 1032d6f934fdSAlexey Kardashevskiy if (offset > 0) { 1033d6f934fdSAlexey Kardashevskiy pdn->holes[i].start = res2.start; 1034d6f934fdSAlexey Kardashevskiy pdn->holes[i].end = res2.start + size * offset - 1; 1035d6f934fdSAlexey Kardashevskiy pdn->holes[i].flags = IORESOURCE_BUS; 1036d6f934fdSAlexey Kardashevskiy pdn->holes[i].name = "pnv_iov_reserved"; 1037d6f934fdSAlexey Kardashevskiy devm_request_resource(&dev->dev, res->parent, 1038d6f934fdSAlexey Kardashevskiy &pdn->holes[i]); 1039d6f934fdSAlexey Kardashevskiy } 1040781a868fSWei Yang } 1041781a868fSWei Yang return 0; 1042781a868fSWei Yang } 1043781a868fSWei Yang #endif /* CONFIG_PCI_IOV */ 1044781a868fSWei Yang 1045cad5cef6SGreg Kroah-Hartman static struct pnv_ioda_pe *pnv_ioda_setup_dev_PE(struct pci_dev *dev) 1046184cd4a3SBenjamin Herrenschmidt { 1047184cd4a3SBenjamin Herrenschmidt struct pci_controller *hose = pci_bus_to_host(dev->bus); 1048184cd4a3SBenjamin Herrenschmidt struct pnv_phb *phb = hose->private_data; 1049b72c1f65SBenjamin Herrenschmidt struct pci_dn *pdn = pci_get_pdn(dev); 1050184cd4a3SBenjamin Herrenschmidt struct pnv_ioda_pe *pe; 1051184cd4a3SBenjamin Herrenschmidt 1052184cd4a3SBenjamin Herrenschmidt if (!pdn) { 1053184cd4a3SBenjamin Herrenschmidt pr_err("%s: Device tree node not associated properly\n", 1054184cd4a3SBenjamin Herrenschmidt pci_name(dev)); 1055184cd4a3SBenjamin Herrenschmidt return NULL; 1056184cd4a3SBenjamin Herrenschmidt } 1057184cd4a3SBenjamin Herrenschmidt if (pdn->pe_number != IODA_INVALID_PE) 1058184cd4a3SBenjamin Herrenschmidt return NULL; 1059184cd4a3SBenjamin Herrenschmidt 10601e916772SGavin Shan pe = pnv_ioda_alloc_pe(phb); 10611e916772SGavin Shan if (!pe) { 1062f2c2cbccSJoe Perches pr_warn("%s: Not enough PE# available, disabling device\n", 1063184cd4a3SBenjamin Herrenschmidt pci_name(dev)); 1064184cd4a3SBenjamin Herrenschmidt return NULL; 1065184cd4a3SBenjamin Herrenschmidt } 1066184cd4a3SBenjamin Herrenschmidt 1067184cd4a3SBenjamin Herrenschmidt /* NOTE: We get only one ref to the pci_dev for the pdn, not for the 1068184cd4a3SBenjamin Herrenschmidt * pointer in the PE data structure, both should be destroyed at the 1069184cd4a3SBenjamin Herrenschmidt * same time. However, this needs to be looked at more closely again 1070184cd4a3SBenjamin Herrenschmidt * once we actually start removing things (Hotplug, SR-IOV, ...) 1071184cd4a3SBenjamin Herrenschmidt * 1072184cd4a3SBenjamin Herrenschmidt * At some point we want to remove the PDN completely anyways 1073184cd4a3SBenjamin Herrenschmidt */ 1074184cd4a3SBenjamin Herrenschmidt pci_dev_get(dev); 1075184cd4a3SBenjamin Herrenschmidt pdn->pcidev = dev; 10761e916772SGavin Shan pdn->pe_number = pe->pe_number; 10775d2aa710SAlistair Popple pe->flags = PNV_IODA_PE_DEV; 1078184cd4a3SBenjamin Herrenschmidt pe->pdev = dev; 1079184cd4a3SBenjamin Herrenschmidt pe->pbus = NULL; 1080184cd4a3SBenjamin Herrenschmidt pe->mve_number = -1; 1081184cd4a3SBenjamin Herrenschmidt pe->rid = dev->bus->number << 8 | pdn->devfn; 1082184cd4a3SBenjamin Herrenschmidt 1083184cd4a3SBenjamin Herrenschmidt pe_info(pe, "Associated device to PE\n"); 1084184cd4a3SBenjamin Herrenschmidt 1085184cd4a3SBenjamin Herrenschmidt if (pnv_ioda_configure_pe(phb, pe)) { 1086184cd4a3SBenjamin Herrenschmidt /* XXX What do we do here ? */ 10871e916772SGavin Shan pnv_ioda_free_pe(pe); 1088184cd4a3SBenjamin Herrenschmidt pdn->pe_number = IODA_INVALID_PE; 1089184cd4a3SBenjamin Herrenschmidt pe->pdev = NULL; 1090184cd4a3SBenjamin Herrenschmidt pci_dev_put(dev); 1091184cd4a3SBenjamin Herrenschmidt return NULL; 1092184cd4a3SBenjamin Herrenschmidt } 1093184cd4a3SBenjamin Herrenschmidt 10941d4e89cfSAlexey Kardashevskiy /* Put PE to the list */ 10951d4e89cfSAlexey Kardashevskiy list_add_tail(&pe->list, &phb->ioda.pe_list); 10961d4e89cfSAlexey Kardashevskiy 1097184cd4a3SBenjamin Herrenschmidt return pe; 1098184cd4a3SBenjamin Herrenschmidt } 1099184cd4a3SBenjamin Herrenschmidt 1100184cd4a3SBenjamin Herrenschmidt static void pnv_ioda_setup_same_PE(struct pci_bus *bus, struct pnv_ioda_pe *pe) 1101184cd4a3SBenjamin Herrenschmidt { 1102184cd4a3SBenjamin Herrenschmidt struct pci_dev *dev; 1103184cd4a3SBenjamin Herrenschmidt 1104184cd4a3SBenjamin Herrenschmidt list_for_each_entry(dev, &bus->devices, bus_list) { 1105b72c1f65SBenjamin Herrenschmidt struct pci_dn *pdn = pci_get_pdn(dev); 1106184cd4a3SBenjamin Herrenschmidt 1107184cd4a3SBenjamin Herrenschmidt if (pdn == NULL) { 1108184cd4a3SBenjamin Herrenschmidt pr_warn("%s: No device node associated with device !\n", 1109184cd4a3SBenjamin Herrenschmidt pci_name(dev)); 1110184cd4a3SBenjamin Herrenschmidt continue; 1111184cd4a3SBenjamin Herrenschmidt } 1112ccd1c191SGavin Shan 1113ccd1c191SGavin Shan /* 1114ccd1c191SGavin Shan * In partial hotplug case, the PCI device might be still 1115ccd1c191SGavin Shan * associated with the PE and needn't attach it to the PE 1116ccd1c191SGavin Shan * again. 1117ccd1c191SGavin Shan */ 1118ccd1c191SGavin Shan if (pdn->pe_number != IODA_INVALID_PE) 1119ccd1c191SGavin Shan continue; 1120ccd1c191SGavin Shan 1121c5f7700bSGavin Shan pe->device_count++; 112294973b24SAlistair Popple pdn->pcidev = dev; 1123184cd4a3SBenjamin Herrenschmidt pdn->pe_number = pe->pe_number; 1124fb446ad0SGavin Shan if ((pe->flags & PNV_IODA_PE_BUS_ALL) && dev->subordinate) 1125184cd4a3SBenjamin Herrenschmidt pnv_ioda_setup_same_PE(dev->subordinate, pe); 1126184cd4a3SBenjamin Herrenschmidt } 1127184cd4a3SBenjamin Herrenschmidt } 1128184cd4a3SBenjamin Herrenschmidt 1129fb446ad0SGavin Shan /* 1130fb446ad0SGavin Shan * There're 2 types of PCI bus sensitive PEs: One that is compromised of 1131fb446ad0SGavin Shan * single PCI bus. Another one that contains the primary PCI bus and its 1132fb446ad0SGavin Shan * subordinate PCI devices and buses. The second type of PE is normally 1133fb446ad0SGavin Shan * orgiriated by PCIe-to-PCI bridge or PLX switch downstream ports. 1134fb446ad0SGavin Shan */ 11351e916772SGavin Shan static struct pnv_ioda_pe *pnv_ioda_setup_bus_PE(struct pci_bus *bus, bool all) 1136184cd4a3SBenjamin Herrenschmidt { 1137fb446ad0SGavin Shan struct pci_controller *hose = pci_bus_to_host(bus); 1138184cd4a3SBenjamin Herrenschmidt struct pnv_phb *phb = hose->private_data; 11391e916772SGavin Shan struct pnv_ioda_pe *pe = NULL; 1140ccd1c191SGavin Shan unsigned int pe_num; 1141ccd1c191SGavin Shan 1142ccd1c191SGavin Shan /* 1143ccd1c191SGavin Shan * In partial hotplug case, the PE instance might be still alive. 1144ccd1c191SGavin Shan * We should reuse it instead of allocating a new one. 1145ccd1c191SGavin Shan */ 1146ccd1c191SGavin Shan pe_num = phb->ioda.pe_rmap[bus->number << 8]; 1147ccd1c191SGavin Shan if (pe_num != IODA_INVALID_PE) { 1148ccd1c191SGavin Shan pe = &phb->ioda.pe_array[pe_num]; 1149ccd1c191SGavin Shan pnv_ioda_setup_same_PE(bus, pe); 1150ccd1c191SGavin Shan return NULL; 1151ccd1c191SGavin Shan } 1152184cd4a3SBenjamin Herrenschmidt 115363803c39SGavin Shan /* PE number for root bus should have been reserved */ 115463803c39SGavin Shan if (pci_is_root_bus(bus) && 115563803c39SGavin Shan phb->ioda.root_pe_idx != IODA_INVALID_PE) 115663803c39SGavin Shan pe = &phb->ioda.pe_array[phb->ioda.root_pe_idx]; 115763803c39SGavin Shan 1158262af557SGuo Chao /* Check if PE is determined by M64 */ 115963803c39SGavin Shan if (!pe && phb->pick_m64_pe) 11601e916772SGavin Shan pe = phb->pick_m64_pe(bus, all); 1161262af557SGuo Chao 1162262af557SGuo Chao /* The PE number isn't pinned by M64 */ 11631e916772SGavin Shan if (!pe) 11641e916772SGavin Shan pe = pnv_ioda_alloc_pe(phb); 1165262af557SGuo Chao 11661e916772SGavin Shan if (!pe) { 1167f2c2cbccSJoe Perches pr_warn("%s: Not enough PE# available for PCI bus %04x:%02x\n", 1168fb446ad0SGavin Shan __func__, pci_domain_nr(bus), bus->number); 11691e916772SGavin Shan return NULL; 1170184cd4a3SBenjamin Herrenschmidt } 1171184cd4a3SBenjamin Herrenschmidt 1172262af557SGuo Chao pe->flags |= (all ? PNV_IODA_PE_BUS_ALL : PNV_IODA_PE_BUS); 1173184cd4a3SBenjamin Herrenschmidt pe->pbus = bus; 1174184cd4a3SBenjamin Herrenschmidt pe->pdev = NULL; 1175184cd4a3SBenjamin Herrenschmidt pe->mve_number = -1; 1176b918c62eSYinghai Lu pe->rid = bus->busn_res.start << 8; 1177184cd4a3SBenjamin Herrenschmidt 1178fb446ad0SGavin Shan if (all) 11791f52f176SRussell Currey pe_info(pe, "Secondary bus %d..%d associated with PE#%x\n", 11801e916772SGavin Shan bus->busn_res.start, bus->busn_res.end, pe->pe_number); 1181fb446ad0SGavin Shan else 11821f52f176SRussell Currey pe_info(pe, "Secondary bus %d associated with PE#%x\n", 11831e916772SGavin Shan bus->busn_res.start, pe->pe_number); 1184184cd4a3SBenjamin Herrenschmidt 1185184cd4a3SBenjamin Herrenschmidt if (pnv_ioda_configure_pe(phb, pe)) { 1186184cd4a3SBenjamin Herrenschmidt /* XXX What do we do here ? */ 11871e916772SGavin Shan pnv_ioda_free_pe(pe); 1188184cd4a3SBenjamin Herrenschmidt pe->pbus = NULL; 11891e916772SGavin Shan return NULL; 1190184cd4a3SBenjamin Herrenschmidt } 1191184cd4a3SBenjamin Herrenschmidt 1192184cd4a3SBenjamin Herrenschmidt /* Associate it with all child devices */ 1193184cd4a3SBenjamin Herrenschmidt pnv_ioda_setup_same_PE(bus, pe); 1194184cd4a3SBenjamin Herrenschmidt 11957ebdf956SGavin Shan /* Put PE to the list */ 11967ebdf956SGavin Shan list_add_tail(&pe->list, &phb->ioda.pe_list); 11971e916772SGavin Shan 11981e916772SGavin Shan return pe; 1199184cd4a3SBenjamin Herrenschmidt } 1200184cd4a3SBenjamin Herrenschmidt 1201b521549aSAlistair Popple static struct pnv_ioda_pe *pnv_ioda_setup_npu_PE(struct pci_dev *npu_pdev) 12025d2aa710SAlistair Popple { 1203b521549aSAlistair Popple int pe_num, found_pe = false, rc; 1204b521549aSAlistair Popple long rid; 1205b521549aSAlistair Popple struct pnv_ioda_pe *pe; 1206b521549aSAlistair Popple struct pci_dev *gpu_pdev; 1207b521549aSAlistair Popple struct pci_dn *npu_pdn; 1208b521549aSAlistair Popple struct pci_controller *hose = pci_bus_to_host(npu_pdev->bus); 1209b521549aSAlistair Popple struct pnv_phb *phb = hose->private_data; 1210b521549aSAlistair Popple 1211b521549aSAlistair Popple /* 1212b521549aSAlistair Popple * Due to a hardware errata PE#0 on the NPU is reserved for 1213b521549aSAlistair Popple * error handling. This means we only have three PEs remaining 1214b521549aSAlistair Popple * which need to be assigned to four links, implying some 1215b521549aSAlistair Popple * links must share PEs. 1216b521549aSAlistair Popple * 1217b521549aSAlistair Popple * To achieve this we assign PEs such that NPUs linking the 1218b521549aSAlistair Popple * same GPU get assigned the same PE. 1219b521549aSAlistair Popple */ 1220b521549aSAlistair Popple gpu_pdev = pnv_pci_get_gpu_dev(npu_pdev); 122192b8f137SGavin Shan for (pe_num = 0; pe_num < phb->ioda.total_pe_num; pe_num++) { 1222b521549aSAlistair Popple pe = &phb->ioda.pe_array[pe_num]; 1223b521549aSAlistair Popple if (!pe->pdev) 1224b521549aSAlistair Popple continue; 1225b521549aSAlistair Popple 1226b521549aSAlistair Popple if (pnv_pci_get_gpu_dev(pe->pdev) == gpu_pdev) { 1227b521549aSAlistair Popple /* 1228b521549aSAlistair Popple * This device has the same peer GPU so should 1229b521549aSAlistair Popple * be assigned the same PE as the existing 1230b521549aSAlistair Popple * peer NPU. 1231b521549aSAlistair Popple */ 1232b521549aSAlistair Popple dev_info(&npu_pdev->dev, 12331f52f176SRussell Currey "Associating to existing PE %x\n", pe_num); 1234b521549aSAlistair Popple pci_dev_get(npu_pdev); 1235b521549aSAlistair Popple npu_pdn = pci_get_pdn(npu_pdev); 1236b521549aSAlistair Popple rid = npu_pdev->bus->number << 8 | npu_pdn->devfn; 1237b521549aSAlistair Popple npu_pdn->pcidev = npu_pdev; 1238b521549aSAlistair Popple npu_pdn->pe_number = pe_num; 1239b521549aSAlistair Popple phb->ioda.pe_rmap[rid] = pe->pe_number; 1240b521549aSAlistair Popple 1241b521549aSAlistair Popple /* Map the PE to this link */ 1242b521549aSAlistair Popple rc = opal_pci_set_pe(phb->opal_id, pe_num, rid, 1243b521549aSAlistair Popple OpalPciBusAll, 1244b521549aSAlistair Popple OPAL_COMPARE_RID_DEVICE_NUMBER, 1245b521549aSAlistair Popple OPAL_COMPARE_RID_FUNCTION_NUMBER, 1246b521549aSAlistair Popple OPAL_MAP_PE); 1247b521549aSAlistair Popple WARN_ON(rc != OPAL_SUCCESS); 1248b521549aSAlistair Popple found_pe = true; 1249b521549aSAlistair Popple break; 1250b521549aSAlistair Popple } 1251b521549aSAlistair Popple } 1252b521549aSAlistair Popple 1253b521549aSAlistair Popple if (!found_pe) 1254b521549aSAlistair Popple /* 1255b521549aSAlistair Popple * Could not find an existing PE so allocate a new 1256b521549aSAlistair Popple * one. 1257b521549aSAlistair Popple */ 1258b521549aSAlistair Popple return pnv_ioda_setup_dev_PE(npu_pdev); 1259b521549aSAlistair Popple else 1260b521549aSAlistair Popple return pe; 1261b521549aSAlistair Popple } 1262b521549aSAlistair Popple 1263b521549aSAlistair Popple static void pnv_ioda_setup_npu_PEs(struct pci_bus *bus) 1264b521549aSAlistair Popple { 12655d2aa710SAlistair Popple struct pci_dev *pdev; 12665d2aa710SAlistair Popple 12675d2aa710SAlistair Popple list_for_each_entry(pdev, &bus->devices, bus_list) 1268b521549aSAlistair Popple pnv_ioda_setup_npu_PE(pdev); 12695d2aa710SAlistair Popple } 12705d2aa710SAlistair Popple 1271cad5cef6SGreg Kroah-Hartman static void pnv_pci_ioda_setup_PEs(void) 1272fb446ad0SGavin Shan { 1273fb446ad0SGavin Shan struct pci_controller *hose, *tmp; 1274262af557SGuo Chao struct pnv_phb *phb; 1275fb446ad0SGavin Shan 1276fb446ad0SGavin Shan list_for_each_entry_safe(hose, tmp, &hose_list, list_node) { 1277262af557SGuo Chao phb = hose->private_data; 127808f48f32SAlistair Popple if (phb->type == PNV_PHB_NPU) { 127908f48f32SAlistair Popple /* PE#0 is needed for error reporting */ 128008f48f32SAlistair Popple pnv_ioda_reserve_pe(phb, 0); 1281b521549aSAlistair Popple pnv_ioda_setup_npu_PEs(hose->bus); 12821ab66d1fSAlistair Popple if (phb->model == PNV_PHB_MODEL_NPU2) 12831ab66d1fSAlistair Popple pnv_npu2_init(phb); 1284ccd1c191SGavin Shan } 1285fb446ad0SGavin Shan } 1286fb446ad0SGavin Shan } 1287184cd4a3SBenjamin Herrenschmidt 1288a8b2f828SGavin Shan #ifdef CONFIG_PCI_IOV 1289ee8222feSWei Yang static int pnv_pci_vf_release_m64(struct pci_dev *pdev, u16 num_vfs) 1290781a868fSWei Yang { 1291781a868fSWei Yang struct pci_bus *bus; 1292781a868fSWei Yang struct pci_controller *hose; 1293781a868fSWei Yang struct pnv_phb *phb; 1294781a868fSWei Yang struct pci_dn *pdn; 129502639b0eSWei Yang int i, j; 1296ee8222feSWei Yang int m64_bars; 1297781a868fSWei Yang 1298781a868fSWei Yang bus = pdev->bus; 1299781a868fSWei Yang hose = pci_bus_to_host(bus); 1300781a868fSWei Yang phb = hose->private_data; 1301781a868fSWei Yang pdn = pci_get_pdn(pdev); 1302781a868fSWei Yang 1303ee8222feSWei Yang if (pdn->m64_single_mode) 1304ee8222feSWei Yang m64_bars = num_vfs; 1305ee8222feSWei Yang else 1306ee8222feSWei Yang m64_bars = 1; 1307ee8222feSWei Yang 130802639b0eSWei Yang for (i = 0; i < PCI_SRIOV_NUM_BARS; i++) 1309ee8222feSWei Yang for (j = 0; j < m64_bars; j++) { 1310ee8222feSWei Yang if (pdn->m64_map[j][i] == IODA_INVALID_M64) 1311781a868fSWei Yang continue; 1312781a868fSWei Yang opal_pci_phb_mmio_enable(phb->opal_id, 1313ee8222feSWei Yang OPAL_M64_WINDOW_TYPE, pdn->m64_map[j][i], 0); 1314ee8222feSWei Yang clear_bit(pdn->m64_map[j][i], &phb->ioda.m64_bar_alloc); 1315ee8222feSWei Yang pdn->m64_map[j][i] = IODA_INVALID_M64; 1316781a868fSWei Yang } 1317781a868fSWei Yang 1318ee8222feSWei Yang kfree(pdn->m64_map); 1319781a868fSWei Yang return 0; 1320781a868fSWei Yang } 1321781a868fSWei Yang 132202639b0eSWei Yang static int pnv_pci_vf_assign_m64(struct pci_dev *pdev, u16 num_vfs) 1323781a868fSWei Yang { 1324781a868fSWei Yang struct pci_bus *bus; 1325781a868fSWei Yang struct pci_controller *hose; 1326781a868fSWei Yang struct pnv_phb *phb; 1327781a868fSWei Yang struct pci_dn *pdn; 1328781a868fSWei Yang unsigned int win; 1329781a868fSWei Yang struct resource *res; 133002639b0eSWei Yang int i, j; 1331781a868fSWei Yang int64_t rc; 133202639b0eSWei Yang int total_vfs; 133302639b0eSWei Yang resource_size_t size, start; 133402639b0eSWei Yang int pe_num; 1335ee8222feSWei Yang int m64_bars; 1336781a868fSWei Yang 1337781a868fSWei Yang bus = pdev->bus; 1338781a868fSWei Yang hose = pci_bus_to_host(bus); 1339781a868fSWei Yang phb = hose->private_data; 1340781a868fSWei Yang pdn = pci_get_pdn(pdev); 134102639b0eSWei Yang total_vfs = pci_sriov_get_totalvfs(pdev); 1342781a868fSWei Yang 1343ee8222feSWei Yang if (pdn->m64_single_mode) 1344ee8222feSWei Yang m64_bars = num_vfs; 1345ee8222feSWei Yang else 1346ee8222feSWei Yang m64_bars = 1; 134702639b0eSWei Yang 1348fb37e128SMarkus Elfring pdn->m64_map = kmalloc_array(m64_bars, 1349fb37e128SMarkus Elfring sizeof(*pdn->m64_map), 1350fb37e128SMarkus Elfring GFP_KERNEL); 1351ee8222feSWei Yang if (!pdn->m64_map) 1352ee8222feSWei Yang return -ENOMEM; 1353ee8222feSWei Yang /* Initialize the m64_map to IODA_INVALID_M64 */ 1354ee8222feSWei Yang for (i = 0; i < m64_bars ; i++) 1355ee8222feSWei Yang for (j = 0; j < PCI_SRIOV_NUM_BARS; j++) 1356ee8222feSWei Yang pdn->m64_map[i][j] = IODA_INVALID_M64; 1357ee8222feSWei Yang 1358781a868fSWei Yang 1359781a868fSWei Yang for (i = 0; i < PCI_SRIOV_NUM_BARS; i++) { 1360781a868fSWei Yang res = &pdev->resource[i + PCI_IOV_RESOURCES]; 1361781a868fSWei Yang if (!res->flags || !res->parent) 1362781a868fSWei Yang continue; 1363781a868fSWei Yang 1364ee8222feSWei Yang for (j = 0; j < m64_bars; j++) { 1365781a868fSWei Yang do { 1366781a868fSWei Yang win = find_next_zero_bit(&phb->ioda.m64_bar_alloc, 1367781a868fSWei Yang phb->ioda.m64_bar_idx + 1, 0); 1368781a868fSWei Yang 1369781a868fSWei Yang if (win >= phb->ioda.m64_bar_idx + 1) 1370781a868fSWei Yang goto m64_failed; 1371781a868fSWei Yang } while (test_and_set_bit(win, &phb->ioda.m64_bar_alloc)); 1372781a868fSWei Yang 1373ee8222feSWei Yang pdn->m64_map[j][i] = win; 137402639b0eSWei Yang 1375ee8222feSWei Yang if (pdn->m64_single_mode) { 137602639b0eSWei Yang size = pci_iov_resource_size(pdev, 137702639b0eSWei Yang PCI_IOV_RESOURCES + i); 137802639b0eSWei Yang start = res->start + size * j; 137902639b0eSWei Yang } else { 138002639b0eSWei Yang size = resource_size(res); 138102639b0eSWei Yang start = res->start; 138202639b0eSWei Yang } 1383781a868fSWei Yang 1384781a868fSWei Yang /* Map the M64 here */ 1385ee8222feSWei Yang if (pdn->m64_single_mode) { 1386be283eebSWei Yang pe_num = pdn->pe_num_map[j]; 138702639b0eSWei Yang rc = opal_pci_map_pe_mmio_window(phb->opal_id, 138802639b0eSWei Yang pe_num, OPAL_M64_WINDOW_TYPE, 1389ee8222feSWei Yang pdn->m64_map[j][i], 0); 139002639b0eSWei Yang } 139102639b0eSWei Yang 1392781a868fSWei Yang rc = opal_pci_set_phb_mem_window(phb->opal_id, 1393781a868fSWei Yang OPAL_M64_WINDOW_TYPE, 1394ee8222feSWei Yang pdn->m64_map[j][i], 139502639b0eSWei Yang start, 1396781a868fSWei Yang 0, /* unused */ 139702639b0eSWei Yang size); 139802639b0eSWei Yang 139902639b0eSWei Yang 1400781a868fSWei Yang if (rc != OPAL_SUCCESS) { 1401781a868fSWei Yang dev_err(&pdev->dev, "Failed to map M64 window #%d: %lld\n", 1402781a868fSWei Yang win, rc); 1403781a868fSWei Yang goto m64_failed; 1404781a868fSWei Yang } 1405781a868fSWei Yang 1406ee8222feSWei Yang if (pdn->m64_single_mode) 1407781a868fSWei Yang rc = opal_pci_phb_mmio_enable(phb->opal_id, 1408ee8222feSWei Yang OPAL_M64_WINDOW_TYPE, pdn->m64_map[j][i], 2); 140902639b0eSWei Yang else 141002639b0eSWei Yang rc = opal_pci_phb_mmio_enable(phb->opal_id, 1411ee8222feSWei Yang OPAL_M64_WINDOW_TYPE, pdn->m64_map[j][i], 1); 141202639b0eSWei Yang 1413781a868fSWei Yang if (rc != OPAL_SUCCESS) { 1414781a868fSWei Yang dev_err(&pdev->dev, "Failed to enable M64 window #%d: %llx\n", 1415781a868fSWei Yang win, rc); 1416781a868fSWei Yang goto m64_failed; 1417781a868fSWei Yang } 1418781a868fSWei Yang } 141902639b0eSWei Yang } 1420781a868fSWei Yang return 0; 1421781a868fSWei Yang 1422781a868fSWei Yang m64_failed: 1423ee8222feSWei Yang pnv_pci_vf_release_m64(pdev, num_vfs); 1424781a868fSWei Yang return -EBUSY; 1425781a868fSWei Yang } 1426781a868fSWei Yang 1427c035e37bSAlexey Kardashevskiy static long pnv_pci_ioda2_unset_window(struct iommu_table_group *table_group, 1428c035e37bSAlexey Kardashevskiy int num); 1429c035e37bSAlexey Kardashevskiy 1430781a868fSWei Yang static void pnv_pci_ioda2_release_dma_pe(struct pci_dev *dev, struct pnv_ioda_pe *pe) 1431781a868fSWei Yang { 1432781a868fSWei Yang struct iommu_table *tbl; 1433781a868fSWei Yang int64_t rc; 1434781a868fSWei Yang 1435b348aa65SAlexey Kardashevskiy tbl = pe->table_group.tables[0]; 1436c035e37bSAlexey Kardashevskiy rc = pnv_pci_ioda2_unset_window(&pe->table_group, 0); 1437781a868fSWei Yang if (rc) 1438781a868fSWei Yang pe_warn(pe, "OPAL error %ld release DMA window\n", rc); 1439781a868fSWei Yang 1440c035e37bSAlexey Kardashevskiy pnv_pci_ioda2_set_bypass(pe, false); 14410eaf4defSAlexey Kardashevskiy if (pe->table_group.group) { 14420eaf4defSAlexey Kardashevskiy iommu_group_put(pe->table_group.group); 14430eaf4defSAlexey Kardashevskiy BUG_ON(pe->table_group.group); 1444ac9a5889SAlexey Kardashevskiy } 1445e5afdf9dSAlexey Kardashevskiy iommu_tce_table_put(tbl); 1446781a868fSWei Yang } 1447781a868fSWei Yang 1448ee8222feSWei Yang static void pnv_ioda_release_vf_PE(struct pci_dev *pdev) 1449781a868fSWei Yang { 1450781a868fSWei Yang struct pci_bus *bus; 1451781a868fSWei Yang struct pci_controller *hose; 1452781a868fSWei Yang struct pnv_phb *phb; 1453781a868fSWei Yang struct pnv_ioda_pe *pe, *pe_n; 1454781a868fSWei Yang struct pci_dn *pdn; 1455781a868fSWei Yang 1456781a868fSWei Yang bus = pdev->bus; 1457781a868fSWei Yang hose = pci_bus_to_host(bus); 1458781a868fSWei Yang phb = hose->private_data; 145902639b0eSWei Yang pdn = pci_get_pdn(pdev); 1460781a868fSWei Yang 1461781a868fSWei Yang if (!pdev->is_physfn) 1462781a868fSWei Yang return; 1463781a868fSWei Yang 1464781a868fSWei Yang list_for_each_entry_safe(pe, pe_n, &phb->ioda.pe_list, list) { 1465781a868fSWei Yang if (pe->parent_dev != pdev) 1466781a868fSWei Yang continue; 1467781a868fSWei Yang 1468781a868fSWei Yang pnv_pci_ioda2_release_dma_pe(pdev, pe); 1469781a868fSWei Yang 1470781a868fSWei Yang /* Remove from list */ 1471781a868fSWei Yang mutex_lock(&phb->ioda.pe_list_mutex); 1472781a868fSWei Yang list_del(&pe->list); 1473781a868fSWei Yang mutex_unlock(&phb->ioda.pe_list_mutex); 1474781a868fSWei Yang 1475781a868fSWei Yang pnv_ioda_deconfigure_pe(phb, pe); 1476781a868fSWei Yang 14771e916772SGavin Shan pnv_ioda_free_pe(pe); 1478781a868fSWei Yang } 1479781a868fSWei Yang } 1480781a868fSWei Yang 1481781a868fSWei Yang void pnv_pci_sriov_disable(struct pci_dev *pdev) 1482781a868fSWei Yang { 1483781a868fSWei Yang struct pci_bus *bus; 1484781a868fSWei Yang struct pci_controller *hose; 1485781a868fSWei Yang struct pnv_phb *phb; 14861e916772SGavin Shan struct pnv_ioda_pe *pe; 1487781a868fSWei Yang struct pci_dn *pdn; 1488be283eebSWei Yang u16 num_vfs, i; 1489781a868fSWei Yang 1490781a868fSWei Yang bus = pdev->bus; 1491781a868fSWei Yang hose = pci_bus_to_host(bus); 1492781a868fSWei Yang phb = hose->private_data; 1493781a868fSWei Yang pdn = pci_get_pdn(pdev); 1494781a868fSWei Yang num_vfs = pdn->num_vfs; 1495781a868fSWei Yang 1496781a868fSWei Yang /* Release VF PEs */ 1497ee8222feSWei Yang pnv_ioda_release_vf_PE(pdev); 1498781a868fSWei Yang 1499781a868fSWei Yang if (phb->type == PNV_PHB_IODA2) { 1500ee8222feSWei Yang if (!pdn->m64_single_mode) 1501be283eebSWei Yang pnv_pci_vf_resource_shift(pdev, -*pdn->pe_num_map); 1502781a868fSWei Yang 1503781a868fSWei Yang /* Release M64 windows */ 1504ee8222feSWei Yang pnv_pci_vf_release_m64(pdev, num_vfs); 1505781a868fSWei Yang 1506781a868fSWei Yang /* Release PE numbers */ 1507be283eebSWei Yang if (pdn->m64_single_mode) { 1508be283eebSWei Yang for (i = 0; i < num_vfs; i++) { 15091e916772SGavin Shan if (pdn->pe_num_map[i] == IODA_INVALID_PE) 15101e916772SGavin Shan continue; 15111e916772SGavin Shan 15121e916772SGavin Shan pe = &phb->ioda.pe_array[pdn->pe_num_map[i]]; 15131e916772SGavin Shan pnv_ioda_free_pe(pe); 1514be283eebSWei Yang } 1515be283eebSWei Yang } else 1516be283eebSWei Yang bitmap_clear(phb->ioda.pe_alloc, *pdn->pe_num_map, num_vfs); 1517be283eebSWei Yang /* Releasing pe_num_map */ 1518be283eebSWei Yang kfree(pdn->pe_num_map); 1519781a868fSWei Yang } 1520781a868fSWei Yang } 1521781a868fSWei Yang 1522781a868fSWei Yang static void pnv_pci_ioda2_setup_dma_pe(struct pnv_phb *phb, 1523781a868fSWei Yang struct pnv_ioda_pe *pe); 1524781a868fSWei Yang static void pnv_ioda_setup_vf_PE(struct pci_dev *pdev, u16 num_vfs) 1525781a868fSWei Yang { 1526781a868fSWei Yang struct pci_bus *bus; 1527781a868fSWei Yang struct pci_controller *hose; 1528781a868fSWei Yang struct pnv_phb *phb; 1529781a868fSWei Yang struct pnv_ioda_pe *pe; 1530781a868fSWei Yang int pe_num; 1531781a868fSWei Yang u16 vf_index; 1532781a868fSWei Yang struct pci_dn *pdn; 1533781a868fSWei Yang 1534781a868fSWei Yang bus = pdev->bus; 1535781a868fSWei Yang hose = pci_bus_to_host(bus); 1536781a868fSWei Yang phb = hose->private_data; 1537781a868fSWei Yang pdn = pci_get_pdn(pdev); 1538781a868fSWei Yang 1539781a868fSWei Yang if (!pdev->is_physfn) 1540781a868fSWei Yang return; 1541781a868fSWei Yang 1542781a868fSWei Yang /* Reserve PE for each VF */ 1543781a868fSWei Yang for (vf_index = 0; vf_index < num_vfs; vf_index++) { 1544be283eebSWei Yang if (pdn->m64_single_mode) 1545be283eebSWei Yang pe_num = pdn->pe_num_map[vf_index]; 1546be283eebSWei Yang else 1547be283eebSWei Yang pe_num = *pdn->pe_num_map + vf_index; 1548781a868fSWei Yang 1549781a868fSWei Yang pe = &phb->ioda.pe_array[pe_num]; 1550781a868fSWei Yang pe->pe_number = pe_num; 1551781a868fSWei Yang pe->phb = phb; 1552781a868fSWei Yang pe->flags = PNV_IODA_PE_VF; 1553781a868fSWei Yang pe->pbus = NULL; 1554781a868fSWei Yang pe->parent_dev = pdev; 1555781a868fSWei Yang pe->mve_number = -1; 1556781a868fSWei Yang pe->rid = (pci_iov_virtfn_bus(pdev, vf_index) << 8) | 1557781a868fSWei Yang pci_iov_virtfn_devfn(pdev, vf_index); 1558781a868fSWei Yang 15591f52f176SRussell Currey pe_info(pe, "VF %04d:%02d:%02d.%d associated with PE#%x\n", 1560781a868fSWei Yang hose->global_number, pdev->bus->number, 1561781a868fSWei Yang PCI_SLOT(pci_iov_virtfn_devfn(pdev, vf_index)), 1562781a868fSWei Yang PCI_FUNC(pci_iov_virtfn_devfn(pdev, vf_index)), pe_num); 1563781a868fSWei Yang 1564781a868fSWei Yang if (pnv_ioda_configure_pe(phb, pe)) { 1565781a868fSWei Yang /* XXX What do we do here ? */ 15661e916772SGavin Shan pnv_ioda_free_pe(pe); 1567781a868fSWei Yang pe->pdev = NULL; 1568781a868fSWei Yang continue; 1569781a868fSWei Yang } 1570781a868fSWei Yang 1571781a868fSWei Yang /* Put PE to the list */ 1572781a868fSWei Yang mutex_lock(&phb->ioda.pe_list_mutex); 1573781a868fSWei Yang list_add_tail(&pe->list, &phb->ioda.pe_list); 1574781a868fSWei Yang mutex_unlock(&phb->ioda.pe_list_mutex); 1575781a868fSWei Yang 1576781a868fSWei Yang pnv_pci_ioda2_setup_dma_pe(phb, pe); 1577781a868fSWei Yang } 1578781a868fSWei Yang } 1579781a868fSWei Yang 1580781a868fSWei Yang int pnv_pci_sriov_enable(struct pci_dev *pdev, u16 num_vfs) 1581781a868fSWei Yang { 1582781a868fSWei Yang struct pci_bus *bus; 1583781a868fSWei Yang struct pci_controller *hose; 1584781a868fSWei Yang struct pnv_phb *phb; 15851e916772SGavin Shan struct pnv_ioda_pe *pe; 1586781a868fSWei Yang struct pci_dn *pdn; 1587781a868fSWei Yang int ret; 1588be283eebSWei Yang u16 i; 1589781a868fSWei Yang 1590781a868fSWei Yang bus = pdev->bus; 1591781a868fSWei Yang hose = pci_bus_to_host(bus); 1592781a868fSWei Yang phb = hose->private_data; 1593781a868fSWei Yang pdn = pci_get_pdn(pdev); 1594781a868fSWei Yang 1595781a868fSWei Yang if (phb->type == PNV_PHB_IODA2) { 1596b0331854SWei Yang if (!pdn->vfs_expanded) { 1597b0331854SWei Yang dev_info(&pdev->dev, "don't support this SRIOV device" 1598b0331854SWei Yang " with non 64bit-prefetchable IOV BAR\n"); 1599b0331854SWei Yang return -ENOSPC; 1600b0331854SWei Yang } 1601b0331854SWei Yang 1602ee8222feSWei Yang /* 1603ee8222feSWei Yang * When M64 BARs functions in Single PE mode, the number of VFs 1604ee8222feSWei Yang * could be enabled must be less than the number of M64 BARs. 1605ee8222feSWei Yang */ 1606ee8222feSWei Yang if (pdn->m64_single_mode && num_vfs > phb->ioda.m64_bar_idx) { 1607ee8222feSWei Yang dev_info(&pdev->dev, "Not enough M64 BAR for VFs\n"); 1608ee8222feSWei Yang return -EBUSY; 1609ee8222feSWei Yang } 1610ee8222feSWei Yang 1611be283eebSWei Yang /* Allocating pe_num_map */ 1612be283eebSWei Yang if (pdn->m64_single_mode) 1613fb37e128SMarkus Elfring pdn->pe_num_map = kmalloc_array(num_vfs, 1614fb37e128SMarkus Elfring sizeof(*pdn->pe_num_map), 1615be283eebSWei Yang GFP_KERNEL); 1616be283eebSWei Yang else 1617be283eebSWei Yang pdn->pe_num_map = kmalloc(sizeof(*pdn->pe_num_map), GFP_KERNEL); 1618be283eebSWei Yang 1619be283eebSWei Yang if (!pdn->pe_num_map) 1620be283eebSWei Yang return -ENOMEM; 1621be283eebSWei Yang 1622be283eebSWei Yang if (pdn->m64_single_mode) 1623be283eebSWei Yang for (i = 0; i < num_vfs; i++) 1624be283eebSWei Yang pdn->pe_num_map[i] = IODA_INVALID_PE; 1625be283eebSWei Yang 1626781a868fSWei Yang /* Calculate available PE for required VFs */ 1627be283eebSWei Yang if (pdn->m64_single_mode) { 1628be283eebSWei Yang for (i = 0; i < num_vfs; i++) { 16291e916772SGavin Shan pe = pnv_ioda_alloc_pe(phb); 16301e916772SGavin Shan if (!pe) { 1631be283eebSWei Yang ret = -EBUSY; 1632be283eebSWei Yang goto m64_failed; 1633be283eebSWei Yang } 16341e916772SGavin Shan 16351e916772SGavin Shan pdn->pe_num_map[i] = pe->pe_number; 1636be283eebSWei Yang } 1637be283eebSWei Yang } else { 1638781a868fSWei Yang mutex_lock(&phb->ioda.pe_alloc_mutex); 1639be283eebSWei Yang *pdn->pe_num_map = bitmap_find_next_zero_area( 164092b8f137SGavin Shan phb->ioda.pe_alloc, phb->ioda.total_pe_num, 1641781a868fSWei Yang 0, num_vfs, 0); 164292b8f137SGavin Shan if (*pdn->pe_num_map >= phb->ioda.total_pe_num) { 1643781a868fSWei Yang mutex_unlock(&phb->ioda.pe_alloc_mutex); 1644781a868fSWei Yang dev_info(&pdev->dev, "Failed to enable VF%d\n", num_vfs); 1645be283eebSWei Yang kfree(pdn->pe_num_map); 1646781a868fSWei Yang return -EBUSY; 1647781a868fSWei Yang } 1648be283eebSWei Yang bitmap_set(phb->ioda.pe_alloc, *pdn->pe_num_map, num_vfs); 1649781a868fSWei Yang mutex_unlock(&phb->ioda.pe_alloc_mutex); 1650be283eebSWei Yang } 1651be283eebSWei Yang pdn->num_vfs = num_vfs; 1652781a868fSWei Yang 1653781a868fSWei Yang /* Assign M64 window accordingly */ 165402639b0eSWei Yang ret = pnv_pci_vf_assign_m64(pdev, num_vfs); 1655781a868fSWei Yang if (ret) { 1656781a868fSWei Yang dev_info(&pdev->dev, "Not enough M64 window resources\n"); 1657781a868fSWei Yang goto m64_failed; 1658781a868fSWei Yang } 1659781a868fSWei Yang 1660781a868fSWei Yang /* 1661781a868fSWei Yang * When using one M64 BAR to map one IOV BAR, we need to shift 1662781a868fSWei Yang * the IOV BAR according to the PE# allocated to the VFs. 1663781a868fSWei Yang * Otherwise, the PE# for the VF will conflict with others. 1664781a868fSWei Yang */ 1665ee8222feSWei Yang if (!pdn->m64_single_mode) { 1666be283eebSWei Yang ret = pnv_pci_vf_resource_shift(pdev, *pdn->pe_num_map); 1667781a868fSWei Yang if (ret) 1668781a868fSWei Yang goto m64_failed; 1669781a868fSWei Yang } 167002639b0eSWei Yang } 1671781a868fSWei Yang 1672781a868fSWei Yang /* Setup VF PEs */ 1673781a868fSWei Yang pnv_ioda_setup_vf_PE(pdev, num_vfs); 1674781a868fSWei Yang 1675781a868fSWei Yang return 0; 1676781a868fSWei Yang 1677781a868fSWei Yang m64_failed: 1678be283eebSWei Yang if (pdn->m64_single_mode) { 1679be283eebSWei Yang for (i = 0; i < num_vfs; i++) { 16801e916772SGavin Shan if (pdn->pe_num_map[i] == IODA_INVALID_PE) 16811e916772SGavin Shan continue; 16821e916772SGavin Shan 16831e916772SGavin Shan pe = &phb->ioda.pe_array[pdn->pe_num_map[i]]; 16841e916772SGavin Shan pnv_ioda_free_pe(pe); 1685be283eebSWei Yang } 1686be283eebSWei Yang } else 1687be283eebSWei Yang bitmap_clear(phb->ioda.pe_alloc, *pdn->pe_num_map, num_vfs); 1688be283eebSWei Yang 1689be283eebSWei Yang /* Releasing pe_num_map */ 1690be283eebSWei Yang kfree(pdn->pe_num_map); 1691781a868fSWei Yang 1692781a868fSWei Yang return ret; 1693781a868fSWei Yang } 1694781a868fSWei Yang 1695a8b2f828SGavin Shan int pcibios_sriov_disable(struct pci_dev *pdev) 1696a8b2f828SGavin Shan { 1697781a868fSWei Yang pnv_pci_sriov_disable(pdev); 1698781a868fSWei Yang 1699a8b2f828SGavin Shan /* Release PCI data */ 1700a8b2f828SGavin Shan remove_dev_pci_data(pdev); 1701a8b2f828SGavin Shan return 0; 1702a8b2f828SGavin Shan } 1703a8b2f828SGavin Shan 1704a8b2f828SGavin Shan int pcibios_sriov_enable(struct pci_dev *pdev, u16 num_vfs) 1705a8b2f828SGavin Shan { 1706a8b2f828SGavin Shan /* Allocate PCI data */ 1707a8b2f828SGavin Shan add_dev_pci_data(pdev); 1708781a868fSWei Yang 1709ee8222feSWei Yang return pnv_pci_sriov_enable(pdev, num_vfs); 1710a8b2f828SGavin Shan } 1711a8b2f828SGavin Shan #endif /* CONFIG_PCI_IOV */ 1712a8b2f828SGavin Shan 1713959c9bddSGavin Shan static void pnv_pci_ioda_dma_dev_setup(struct pnv_phb *phb, struct pci_dev *pdev) 1714184cd4a3SBenjamin Herrenschmidt { 1715b72c1f65SBenjamin Herrenschmidt struct pci_dn *pdn = pci_get_pdn(pdev); 1716959c9bddSGavin Shan struct pnv_ioda_pe *pe; 1717184cd4a3SBenjamin Herrenschmidt 1718959c9bddSGavin Shan /* 1719959c9bddSGavin Shan * The function can be called while the PE# 1720959c9bddSGavin Shan * hasn't been assigned. Do nothing for the 1721959c9bddSGavin Shan * case. 1722959c9bddSGavin Shan */ 1723959c9bddSGavin Shan if (!pdn || pdn->pe_number == IODA_INVALID_PE) 1724959c9bddSGavin Shan return; 1725184cd4a3SBenjamin Herrenschmidt 1726959c9bddSGavin Shan pe = &phb->ioda.pe_array[pdn->pe_number]; 1727cd15b048SBenjamin Herrenschmidt WARN_ON(get_dma_ops(&pdev->dev) != &dma_iommu_ops); 17280e1ffef0SAlexey Kardashevskiy set_dma_offset(&pdev->dev, pe->tce_bypass_base); 1729b348aa65SAlexey Kardashevskiy set_iommu_table_base(&pdev->dev, pe->table_group.tables[0]); 17304617082eSAlexey Kardashevskiy /* 17314617082eSAlexey Kardashevskiy * Note: iommu_add_device() will fail here as 17324617082eSAlexey Kardashevskiy * for physical PE: the device is already added by now; 17334617082eSAlexey Kardashevskiy * for virtual PE: sysfs entries are not ready yet and 17344617082eSAlexey Kardashevskiy * tce_iommu_bus_notifier will add the device to a group later. 17354617082eSAlexey Kardashevskiy */ 1736184cd4a3SBenjamin Herrenschmidt } 1737184cd4a3SBenjamin Herrenschmidt 1738a0f98629SRussell Currey static bool pnv_pci_ioda_pe_single_vendor(struct pnv_ioda_pe *pe) 1739a0f98629SRussell Currey { 1740a0f98629SRussell Currey unsigned short vendor = 0; 1741a0f98629SRussell Currey struct pci_dev *pdev; 1742a0f98629SRussell Currey 1743a0f98629SRussell Currey if (pe->device_count == 1) 1744a0f98629SRussell Currey return true; 1745a0f98629SRussell Currey 1746a0f98629SRussell Currey /* pe->pdev should be set if it's a single device, pe->pbus if not */ 1747a0f98629SRussell Currey if (!pe->pbus) 1748a0f98629SRussell Currey return true; 1749a0f98629SRussell Currey 1750a0f98629SRussell Currey list_for_each_entry(pdev, &pe->pbus->devices, bus_list) { 1751a0f98629SRussell Currey if (!vendor) { 1752a0f98629SRussell Currey vendor = pdev->vendor; 1753a0f98629SRussell Currey continue; 1754a0f98629SRussell Currey } 1755a0f98629SRussell Currey 1756a0f98629SRussell Currey if (pdev->vendor != vendor) 1757a0f98629SRussell Currey return false; 1758a0f98629SRussell Currey } 1759a0f98629SRussell Currey 1760a0f98629SRussell Currey return true; 1761a0f98629SRussell Currey } 1762a0f98629SRussell Currey 17638e3f1b1dSRussell Currey /* 17648e3f1b1dSRussell Currey * Reconfigure TVE#0 to be usable as 64-bit DMA space. 17658e3f1b1dSRussell Currey * 17668e3f1b1dSRussell Currey * The first 4GB of virtual memory for a PE is reserved for 32-bit accesses. 17678e3f1b1dSRussell Currey * Devices can only access more than that if bit 59 of the PCI address is set 17688e3f1b1dSRussell Currey * by hardware, which indicates TVE#1 should be used instead of TVE#0. 17698e3f1b1dSRussell Currey * Many PCI devices are not capable of addressing that many bits, and as a 17708e3f1b1dSRussell Currey * result are limited to the 4GB of virtual memory made available to 32-bit 17718e3f1b1dSRussell Currey * devices in TVE#0. 17728e3f1b1dSRussell Currey * 17738e3f1b1dSRussell Currey * In order to work around this, reconfigure TVE#0 to be suitable for 64-bit 17748e3f1b1dSRussell Currey * devices by configuring the virtual memory past the first 4GB inaccessible 17758e3f1b1dSRussell Currey * by 64-bit DMAs. This should only be used by devices that want more than 17768e3f1b1dSRussell Currey * 4GB, and only on PEs that have no 32-bit devices. 17778e3f1b1dSRussell Currey * 17788e3f1b1dSRussell Currey * Currently this will only work on PHB3 (POWER8). 17798e3f1b1dSRussell Currey */ 17808e3f1b1dSRussell Currey static int pnv_pci_ioda_dma_64bit_bypass(struct pnv_ioda_pe *pe) 17818e3f1b1dSRussell Currey { 17828e3f1b1dSRussell Currey u64 window_size, table_size, tce_count, addr; 17838e3f1b1dSRussell Currey struct page *table_pages; 17848e3f1b1dSRussell Currey u64 tce_order = 28; /* 256MB TCEs */ 17858e3f1b1dSRussell Currey __be64 *tces; 17868e3f1b1dSRussell Currey s64 rc; 17878e3f1b1dSRussell Currey 17888e3f1b1dSRussell Currey /* 17898e3f1b1dSRussell Currey * Window size needs to be a power of two, but needs to account for 17908e3f1b1dSRussell Currey * shifting memory by the 4GB offset required to skip 32bit space. 17918e3f1b1dSRussell Currey */ 17928e3f1b1dSRussell Currey window_size = roundup_pow_of_two(memory_hotplug_max() + (1ULL << 32)); 17938e3f1b1dSRussell Currey tce_count = window_size >> tce_order; 17948e3f1b1dSRussell Currey table_size = tce_count << 3; 17958e3f1b1dSRussell Currey 17968e3f1b1dSRussell Currey if (table_size < PAGE_SIZE) 17978e3f1b1dSRussell Currey table_size = PAGE_SIZE; 17988e3f1b1dSRussell Currey 17998e3f1b1dSRussell Currey table_pages = alloc_pages_node(pe->phb->hose->node, GFP_KERNEL, 18008e3f1b1dSRussell Currey get_order(table_size)); 18018e3f1b1dSRussell Currey if (!table_pages) 18028e3f1b1dSRussell Currey goto err; 18038e3f1b1dSRussell Currey 18048e3f1b1dSRussell Currey tces = page_address(table_pages); 18058e3f1b1dSRussell Currey if (!tces) 18068e3f1b1dSRussell Currey goto err; 18078e3f1b1dSRussell Currey 18088e3f1b1dSRussell Currey memset(tces, 0, table_size); 18098e3f1b1dSRussell Currey 18108e3f1b1dSRussell Currey for (addr = 0; addr < memory_hotplug_max(); addr += (1 << tce_order)) { 18118e3f1b1dSRussell Currey tces[(addr + (1ULL << 32)) >> tce_order] = 18128e3f1b1dSRussell Currey cpu_to_be64(addr | TCE_PCI_READ | TCE_PCI_WRITE); 18138e3f1b1dSRussell Currey } 18148e3f1b1dSRussell Currey 18158e3f1b1dSRussell Currey rc = opal_pci_map_pe_dma_window(pe->phb->opal_id, 18168e3f1b1dSRussell Currey pe->pe_number, 18178e3f1b1dSRussell Currey /* reconfigure window 0 */ 18188e3f1b1dSRussell Currey (pe->pe_number << 1) + 0, 18198e3f1b1dSRussell Currey 1, 18208e3f1b1dSRussell Currey __pa(tces), 18218e3f1b1dSRussell Currey table_size, 18228e3f1b1dSRussell Currey 1 << tce_order); 18238e3f1b1dSRussell Currey if (rc == OPAL_SUCCESS) { 18248e3f1b1dSRussell Currey pe_info(pe, "Using 64-bit DMA iommu bypass (through TVE#0)\n"); 18258e3f1b1dSRussell Currey return 0; 18268e3f1b1dSRussell Currey } 18278e3f1b1dSRussell Currey err: 18288e3f1b1dSRussell Currey pe_err(pe, "Error configuring 64-bit DMA bypass\n"); 18298e3f1b1dSRussell Currey return -EIO; 18308e3f1b1dSRussell Currey } 18318e3f1b1dSRussell Currey 1832763d2d8dSDaniel Axtens static int pnv_pci_ioda_dma_set_mask(struct pci_dev *pdev, u64 dma_mask) 1833cd15b048SBenjamin Herrenschmidt { 1834763d2d8dSDaniel Axtens struct pci_controller *hose = pci_bus_to_host(pdev->bus); 1835763d2d8dSDaniel Axtens struct pnv_phb *phb = hose->private_data; 1836cd15b048SBenjamin Herrenschmidt struct pci_dn *pdn = pci_get_pdn(pdev); 1837cd15b048SBenjamin Herrenschmidt struct pnv_ioda_pe *pe; 1838cd15b048SBenjamin Herrenschmidt uint64_t top; 1839cd15b048SBenjamin Herrenschmidt bool bypass = false; 18408e3f1b1dSRussell Currey s64 rc; 1841cd15b048SBenjamin Herrenschmidt 1842cd15b048SBenjamin Herrenschmidt if (WARN_ON(!pdn || pdn->pe_number == IODA_INVALID_PE)) 1843cd15b048SBenjamin Herrenschmidt return -ENODEV;; 1844cd15b048SBenjamin Herrenschmidt 1845cd15b048SBenjamin Herrenschmidt pe = &phb->ioda.pe_array[pdn->pe_number]; 1846cd15b048SBenjamin Herrenschmidt if (pe->tce_bypass_enabled) { 1847cd15b048SBenjamin Herrenschmidt top = pe->tce_bypass_base + memblock_end_of_DRAM() - 1; 1848cd15b048SBenjamin Herrenschmidt bypass = (dma_mask >= top); 1849cd15b048SBenjamin Herrenschmidt } 1850cd15b048SBenjamin Herrenschmidt 1851cd15b048SBenjamin Herrenschmidt if (bypass) { 1852cd15b048SBenjamin Herrenschmidt dev_info(&pdev->dev, "Using 64-bit DMA iommu bypass\n"); 1853cd15b048SBenjamin Herrenschmidt set_dma_ops(&pdev->dev, &dma_direct_ops); 1854cd15b048SBenjamin Herrenschmidt } else { 18558e3f1b1dSRussell Currey /* 18568e3f1b1dSRussell Currey * If the device can't set the TCE bypass bit but still wants 18578e3f1b1dSRussell Currey * to access 4GB or more, on PHB3 we can reconfigure TVE#0 to 18588e3f1b1dSRussell Currey * bypass the 32-bit region and be usable for 64-bit DMAs. 18598e3f1b1dSRussell Currey * The device needs to be able to address all of this space. 18608e3f1b1dSRussell Currey */ 18618e3f1b1dSRussell Currey if (dma_mask >> 32 && 18628e3f1b1dSRussell Currey dma_mask > (memory_hotplug_max() + (1ULL << 32)) && 18638e3f1b1dSRussell Currey pnv_pci_ioda_pe_single_vendor(pe) && 18648e3f1b1dSRussell Currey phb->model == PNV_PHB_MODEL_PHB3) { 18658e3f1b1dSRussell Currey /* Configure the bypass mode */ 18668e3f1b1dSRussell Currey rc = pnv_pci_ioda_dma_64bit_bypass(pe); 18678e3f1b1dSRussell Currey if (rc) 18688e3f1b1dSRussell Currey return rc; 18698e3f1b1dSRussell Currey /* 4GB offset bypasses 32-bit space */ 18708e3f1b1dSRussell Currey set_dma_offset(&pdev->dev, (1ULL << 32)); 18718e3f1b1dSRussell Currey set_dma_ops(&pdev->dev, &dma_direct_ops); 1872253fd51eSAlistair Popple } else if (dma_mask >> 32 && dma_mask != DMA_BIT_MASK(64)) { 1873253fd51eSAlistair Popple /* 1874253fd51eSAlistair Popple * Fail the request if a DMA mask between 32 and 64 bits 1875253fd51eSAlistair Popple * was requested but couldn't be fulfilled. Ideally we 1876253fd51eSAlistair Popple * would do this for 64-bits but historically we have 1877253fd51eSAlistair Popple * always fallen back to 32-bits. 1878253fd51eSAlistair Popple */ 1879253fd51eSAlistair Popple return -ENOMEM; 18808e3f1b1dSRussell Currey } else { 1881cd15b048SBenjamin Herrenschmidt dev_info(&pdev->dev, "Using 32-bit DMA via iommu\n"); 1882cd15b048SBenjamin Herrenschmidt set_dma_ops(&pdev->dev, &dma_iommu_ops); 1883cd15b048SBenjamin Herrenschmidt } 18848e3f1b1dSRussell Currey } 1885a32305bfSBrian W Hart *pdev->dev.dma_mask = dma_mask; 18865d2aa710SAlistair Popple 18875d2aa710SAlistair Popple /* Update peer npu devices */ 1888f9f83456SAlexey Kardashevskiy pnv_npu_try_dma_set_bypass(pdev, bypass); 18895d2aa710SAlistair Popple 1890cd15b048SBenjamin Herrenschmidt return 0; 1891cd15b048SBenjamin Herrenschmidt } 1892cd15b048SBenjamin Herrenschmidt 189353522982SAndrew Donnellan static u64 pnv_pci_ioda_dma_get_required_mask(struct pci_dev *pdev) 1894fe7e85c6SGavin Shan { 189553522982SAndrew Donnellan struct pci_controller *hose = pci_bus_to_host(pdev->bus); 189653522982SAndrew Donnellan struct pnv_phb *phb = hose->private_data; 1897fe7e85c6SGavin Shan struct pci_dn *pdn = pci_get_pdn(pdev); 1898fe7e85c6SGavin Shan struct pnv_ioda_pe *pe; 1899fe7e85c6SGavin Shan u64 end, mask; 1900fe7e85c6SGavin Shan 1901fe7e85c6SGavin Shan if (WARN_ON(!pdn || pdn->pe_number == IODA_INVALID_PE)) 1902fe7e85c6SGavin Shan return 0; 1903fe7e85c6SGavin Shan 1904fe7e85c6SGavin Shan pe = &phb->ioda.pe_array[pdn->pe_number]; 1905fe7e85c6SGavin Shan if (!pe->tce_bypass_enabled) 1906fe7e85c6SGavin Shan return __dma_get_required_mask(&pdev->dev); 1907fe7e85c6SGavin Shan 1908fe7e85c6SGavin Shan 1909fe7e85c6SGavin Shan end = pe->tce_bypass_base + memblock_end_of_DRAM(); 1910fe7e85c6SGavin Shan mask = 1ULL << (fls64(end) - 1); 1911fe7e85c6SGavin Shan mask += mask - 1; 1912fe7e85c6SGavin Shan 1913fe7e85c6SGavin Shan return mask; 1914fe7e85c6SGavin Shan } 1915fe7e85c6SGavin Shan 1916dff4a39eSGavin Shan static void pnv_ioda_setup_bus_dma(struct pnv_ioda_pe *pe, 1917db08e1d5SAlexey Kardashevskiy struct pci_bus *bus, 1918db08e1d5SAlexey Kardashevskiy bool add_to_group) 191974251fe2SBenjamin Herrenschmidt { 192074251fe2SBenjamin Herrenschmidt struct pci_dev *dev; 192174251fe2SBenjamin Herrenschmidt 192274251fe2SBenjamin Herrenschmidt list_for_each_entry(dev, &bus->devices, bus_list) { 1923b348aa65SAlexey Kardashevskiy set_iommu_table_base(&dev->dev, pe->table_group.tables[0]); 1924e91c2511SBenjamin Herrenschmidt set_dma_offset(&dev->dev, pe->tce_bypass_base); 1925db08e1d5SAlexey Kardashevskiy if (add_to_group) 19264617082eSAlexey Kardashevskiy iommu_add_device(&dev->dev); 1927dff4a39eSGavin Shan 19285c89a87dSAlexey Kardashevskiy if ((pe->flags & PNV_IODA_PE_BUS_ALL) && dev->subordinate) 1929db08e1d5SAlexey Kardashevskiy pnv_ioda_setup_bus_dma(pe, dev->subordinate, 1930db08e1d5SAlexey Kardashevskiy add_to_group); 193174251fe2SBenjamin Herrenschmidt } 193274251fe2SBenjamin Herrenschmidt } 193374251fe2SBenjamin Herrenschmidt 1934fd141d1aSBenjamin Herrenschmidt static inline __be64 __iomem *pnv_ioda_get_inval_reg(struct pnv_phb *phb, 1935fd141d1aSBenjamin Herrenschmidt bool real_mode) 1936fd141d1aSBenjamin Herrenschmidt { 1937fd141d1aSBenjamin Herrenschmidt return real_mode ? (__be64 __iomem *)(phb->regs_phys + 0x210) : 1938fd141d1aSBenjamin Herrenschmidt (phb->regs + 0x210); 1939fd141d1aSBenjamin Herrenschmidt } 1940fd141d1aSBenjamin Herrenschmidt 1941a34ab7c3SBenjamin Herrenschmidt static void pnv_pci_p7ioc_tce_invalidate(struct iommu_table *tbl, 1942decbda25SAlexey Kardashevskiy unsigned long index, unsigned long npages, bool rm) 19434cce9550SGavin Shan { 19440eaf4defSAlexey Kardashevskiy struct iommu_table_group_link *tgl = list_first_entry_or_null( 19450eaf4defSAlexey Kardashevskiy &tbl->it_group_list, struct iommu_table_group_link, 19460eaf4defSAlexey Kardashevskiy next); 19470eaf4defSAlexey Kardashevskiy struct pnv_ioda_pe *pe = container_of(tgl->table_group, 1948b348aa65SAlexey Kardashevskiy struct pnv_ioda_pe, table_group); 1949fd141d1aSBenjamin Herrenschmidt __be64 __iomem *invalidate = pnv_ioda_get_inval_reg(pe->phb, rm); 19504cce9550SGavin Shan unsigned long start, end, inc; 19514cce9550SGavin Shan 1952decbda25SAlexey Kardashevskiy start = __pa(((__be64 *)tbl->it_base) + index - tbl->it_offset); 1953decbda25SAlexey Kardashevskiy end = __pa(((__be64 *)tbl->it_base) + index - tbl->it_offset + 1954decbda25SAlexey Kardashevskiy npages - 1); 19554cce9550SGavin Shan 19564cce9550SGavin Shan /* p7ioc-style invalidation, 2 TCEs per write */ 19574cce9550SGavin Shan start |= (1ull << 63); 19584cce9550SGavin Shan end |= (1ull << 63); 19594cce9550SGavin Shan inc = 16; 19604cce9550SGavin Shan end |= inc - 1; /* round up end to be different than start */ 19614cce9550SGavin Shan 19624cce9550SGavin Shan mb(); /* Ensure above stores are visible */ 19634cce9550SGavin Shan while (start <= end) { 19648e0a1611SAlexey Kardashevskiy if (rm) 19653ad26e5cSBenjamin Herrenschmidt __raw_rm_writeq(cpu_to_be64(start), invalidate); 19668e0a1611SAlexey Kardashevskiy else 19673a1a4661SBenjamin Herrenschmidt __raw_writeq(cpu_to_be64(start), invalidate); 19684cce9550SGavin Shan start += inc; 19694cce9550SGavin Shan } 19704cce9550SGavin Shan 19714cce9550SGavin Shan /* 19724cce9550SGavin Shan * The iommu layer will do another mb() for us on build() 19734cce9550SGavin Shan * and we don't care on free() 19744cce9550SGavin Shan */ 19754cce9550SGavin Shan } 19764cce9550SGavin Shan 1977decbda25SAlexey Kardashevskiy static int pnv_ioda1_tce_build(struct iommu_table *tbl, long index, 1978decbda25SAlexey Kardashevskiy long npages, unsigned long uaddr, 1979decbda25SAlexey Kardashevskiy enum dma_data_direction direction, 198000085f1eSKrzysztof Kozlowski unsigned long attrs) 1981decbda25SAlexey Kardashevskiy { 1982decbda25SAlexey Kardashevskiy int ret = pnv_tce_build(tbl, index, npages, uaddr, direction, 1983decbda25SAlexey Kardashevskiy attrs); 1984decbda25SAlexey Kardashevskiy 198508acce1cSBenjamin Herrenschmidt if (!ret) 1986a34ab7c3SBenjamin Herrenschmidt pnv_pci_p7ioc_tce_invalidate(tbl, index, npages, false); 1987decbda25SAlexey Kardashevskiy 1988decbda25SAlexey Kardashevskiy return ret; 1989decbda25SAlexey Kardashevskiy } 1990decbda25SAlexey Kardashevskiy 199105c6cfb9SAlexey Kardashevskiy #ifdef CONFIG_IOMMU_API 199205c6cfb9SAlexey Kardashevskiy static int pnv_ioda1_tce_xchg(struct iommu_table *tbl, long index, 199305c6cfb9SAlexey Kardashevskiy unsigned long *hpa, enum dma_data_direction *direction) 199405c6cfb9SAlexey Kardashevskiy { 199505c6cfb9SAlexey Kardashevskiy long ret = pnv_tce_xchg(tbl, index, hpa, direction); 199605c6cfb9SAlexey Kardashevskiy 199708acce1cSBenjamin Herrenschmidt if (!ret) 1998a34ab7c3SBenjamin Herrenschmidt pnv_pci_p7ioc_tce_invalidate(tbl, index, 1, false); 199905c6cfb9SAlexey Kardashevskiy 200005c6cfb9SAlexey Kardashevskiy return ret; 200105c6cfb9SAlexey Kardashevskiy } 2002a540aa56SAlexey Kardashevskiy 2003a540aa56SAlexey Kardashevskiy static int pnv_ioda1_tce_xchg_rm(struct iommu_table *tbl, long index, 2004a540aa56SAlexey Kardashevskiy unsigned long *hpa, enum dma_data_direction *direction) 2005a540aa56SAlexey Kardashevskiy { 2006a540aa56SAlexey Kardashevskiy long ret = pnv_tce_xchg(tbl, index, hpa, direction); 2007a540aa56SAlexey Kardashevskiy 2008a540aa56SAlexey Kardashevskiy if (!ret) 2009a540aa56SAlexey Kardashevskiy pnv_pci_p7ioc_tce_invalidate(tbl, index, 1, true); 2010a540aa56SAlexey Kardashevskiy 2011a540aa56SAlexey Kardashevskiy return ret; 2012a540aa56SAlexey Kardashevskiy } 201305c6cfb9SAlexey Kardashevskiy #endif 201405c6cfb9SAlexey Kardashevskiy 2015decbda25SAlexey Kardashevskiy static void pnv_ioda1_tce_free(struct iommu_table *tbl, long index, 2016decbda25SAlexey Kardashevskiy long npages) 2017decbda25SAlexey Kardashevskiy { 2018decbda25SAlexey Kardashevskiy pnv_tce_free(tbl, index, npages); 2019decbda25SAlexey Kardashevskiy 2020a34ab7c3SBenjamin Herrenschmidt pnv_pci_p7ioc_tce_invalidate(tbl, index, npages, false); 2021decbda25SAlexey Kardashevskiy } 2022decbda25SAlexey Kardashevskiy 2023da004c36SAlexey Kardashevskiy static struct iommu_table_ops pnv_ioda1_iommu_ops = { 2024decbda25SAlexey Kardashevskiy .set = pnv_ioda1_tce_build, 202505c6cfb9SAlexey Kardashevskiy #ifdef CONFIG_IOMMU_API 202605c6cfb9SAlexey Kardashevskiy .exchange = pnv_ioda1_tce_xchg, 2027a540aa56SAlexey Kardashevskiy .exchange_rm = pnv_ioda1_tce_xchg_rm, 202805c6cfb9SAlexey Kardashevskiy #endif 2029decbda25SAlexey Kardashevskiy .clear = pnv_ioda1_tce_free, 2030da004c36SAlexey Kardashevskiy .get = pnv_tce_get, 2031da004c36SAlexey Kardashevskiy }; 2032da004c36SAlexey Kardashevskiy 2033a34ab7c3SBenjamin Herrenschmidt #define PHB3_TCE_KILL_INVAL_ALL PPC_BIT(0) 2034a34ab7c3SBenjamin Herrenschmidt #define PHB3_TCE_KILL_INVAL_PE PPC_BIT(1) 2035a34ab7c3SBenjamin Herrenschmidt #define PHB3_TCE_KILL_INVAL_ONE PPC_BIT(2) 2036bef9253fSAlexey Kardashevskiy 20376b3d12a9SAlistair Popple static void pnv_pci_phb3_tce_invalidate_entire(struct pnv_phb *phb, bool rm) 20380bbcdb43SAlexey Kardashevskiy { 2039fd141d1aSBenjamin Herrenschmidt __be64 __iomem *invalidate = pnv_ioda_get_inval_reg(phb, rm); 2040a34ab7c3SBenjamin Herrenschmidt const unsigned long val = PHB3_TCE_KILL_INVAL_ALL; 20410bbcdb43SAlexey Kardashevskiy 20420bbcdb43SAlexey Kardashevskiy mb(); /* Ensure previous TCE table stores are visible */ 20430bbcdb43SAlexey Kardashevskiy if (rm) 2044fd141d1aSBenjamin Herrenschmidt __raw_rm_writeq(cpu_to_be64(val), invalidate); 20450bbcdb43SAlexey Kardashevskiy else 2046fd141d1aSBenjamin Herrenschmidt __raw_writeq(cpu_to_be64(val), invalidate); 20470bbcdb43SAlexey Kardashevskiy } 20480bbcdb43SAlexey Kardashevskiy 2049a34ab7c3SBenjamin Herrenschmidt static inline void pnv_pci_phb3_tce_invalidate_pe(struct pnv_ioda_pe *pe) 20505780fb04SAlexey Kardashevskiy { 20515780fb04SAlexey Kardashevskiy /* 01xb - invalidate TCEs that match the specified PE# */ 2052fd141d1aSBenjamin Herrenschmidt __be64 __iomem *invalidate = pnv_ioda_get_inval_reg(pe->phb, false); 2053a34ab7c3SBenjamin Herrenschmidt unsigned long val = PHB3_TCE_KILL_INVAL_PE | (pe->pe_number & 0xFF); 20545780fb04SAlexey Kardashevskiy 20555780fb04SAlexey Kardashevskiy mb(); /* Ensure above stores are visible */ 2056fd141d1aSBenjamin Herrenschmidt __raw_writeq(cpu_to_be64(val), invalidate); 20575780fb04SAlexey Kardashevskiy } 20585780fb04SAlexey Kardashevskiy 2059fd141d1aSBenjamin Herrenschmidt static void pnv_pci_phb3_tce_invalidate(struct pnv_ioda_pe *pe, bool rm, 2060fd141d1aSBenjamin Herrenschmidt unsigned shift, unsigned long index, 2061fd141d1aSBenjamin Herrenschmidt unsigned long npages) 20624cce9550SGavin Shan { 20634d902195SAlexey Kardashevskiy __be64 __iomem *invalidate = pnv_ioda_get_inval_reg(pe->phb, rm); 20644cce9550SGavin Shan unsigned long start, end, inc; 20654cce9550SGavin Shan 20664cce9550SGavin Shan /* We'll invalidate DMA address in PE scope */ 2067a34ab7c3SBenjamin Herrenschmidt start = PHB3_TCE_KILL_INVAL_ONE; 2068fd141d1aSBenjamin Herrenschmidt start |= (pe->pe_number & 0xFF); 20694cce9550SGavin Shan end = start; 20704cce9550SGavin Shan 20714cce9550SGavin Shan /* Figure out the start, end and step */ 2072decbda25SAlexey Kardashevskiy start |= (index << shift); 2073decbda25SAlexey Kardashevskiy end |= ((index + npages - 1) << shift); 2074b0376c9bSAlexey Kardashevskiy inc = (0x1ull << shift); 20754cce9550SGavin Shan mb(); 20764cce9550SGavin Shan 20774cce9550SGavin Shan while (start <= end) { 20788e0a1611SAlexey Kardashevskiy if (rm) 20793ad26e5cSBenjamin Herrenschmidt __raw_rm_writeq(cpu_to_be64(start), invalidate); 20808e0a1611SAlexey Kardashevskiy else 20813a1a4661SBenjamin Herrenschmidt __raw_writeq(cpu_to_be64(start), invalidate); 20824cce9550SGavin Shan start += inc; 20834cce9550SGavin Shan } 20844cce9550SGavin Shan } 20854cce9550SGavin Shan 2086f0228c41SBenjamin Herrenschmidt static inline void pnv_pci_ioda2_tce_invalidate_pe(struct pnv_ioda_pe *pe) 2087f0228c41SBenjamin Herrenschmidt { 2088f0228c41SBenjamin Herrenschmidt struct pnv_phb *phb = pe->phb; 2089f0228c41SBenjamin Herrenschmidt 2090f0228c41SBenjamin Herrenschmidt if (phb->model == PNV_PHB_MODEL_PHB3 && phb->regs) 2091f0228c41SBenjamin Herrenschmidt pnv_pci_phb3_tce_invalidate_pe(pe); 2092f0228c41SBenjamin Herrenschmidt else 2093f0228c41SBenjamin Herrenschmidt opal_pci_tce_kill(phb->opal_id, OPAL_PCI_TCE_KILL_PE, 2094f0228c41SBenjamin Herrenschmidt pe->pe_number, 0, 0, 0); 2095f0228c41SBenjamin Herrenschmidt } 2096f0228c41SBenjamin Herrenschmidt 2097e57080f1SAlexey Kardashevskiy static void pnv_pci_ioda2_tce_invalidate(struct iommu_table *tbl, 2098e57080f1SAlexey Kardashevskiy unsigned long index, unsigned long npages, bool rm) 2099e57080f1SAlexey Kardashevskiy { 2100e57080f1SAlexey Kardashevskiy struct iommu_table_group_link *tgl; 2101e57080f1SAlexey Kardashevskiy 2102a540aa56SAlexey Kardashevskiy list_for_each_entry_lockless(tgl, &tbl->it_group_list, next) { 2103e57080f1SAlexey Kardashevskiy struct pnv_ioda_pe *pe = container_of(tgl->table_group, 2104e57080f1SAlexey Kardashevskiy struct pnv_ioda_pe, table_group); 2105f0228c41SBenjamin Herrenschmidt struct pnv_phb *phb = pe->phb; 2106f0228c41SBenjamin Herrenschmidt unsigned int shift = tbl->it_page_shift; 2107f0228c41SBenjamin Herrenschmidt 2108616badd2SAlistair Popple /* 2109616badd2SAlistair Popple * NVLink1 can use the TCE kill register directly as 2110616badd2SAlistair Popple * it's the same as PHB3. NVLink2 is different and 2111616badd2SAlistair Popple * should go via the OPAL call. 2112616badd2SAlistair Popple */ 2113616badd2SAlistair Popple if (phb->model == PNV_PHB_MODEL_NPU) { 21140bbcdb43SAlexey Kardashevskiy /* 21150bbcdb43SAlexey Kardashevskiy * The NVLink hardware does not support TCE kill 21160bbcdb43SAlexey Kardashevskiy * per TCE entry so we have to invalidate 21170bbcdb43SAlexey Kardashevskiy * the entire cache for it. 21180bbcdb43SAlexey Kardashevskiy */ 2119f0228c41SBenjamin Herrenschmidt pnv_pci_phb3_tce_invalidate_entire(phb, rm); 21205d2aa710SAlistair Popple continue; 21215d2aa710SAlistair Popple } 2122f0228c41SBenjamin Herrenschmidt if (phb->model == PNV_PHB_MODEL_PHB3 && phb->regs) 2123f0228c41SBenjamin Herrenschmidt pnv_pci_phb3_tce_invalidate(pe, rm, shift, 212485674868SAlexey Kardashevskiy index, npages); 2125f0228c41SBenjamin Herrenschmidt else 2126f0228c41SBenjamin Herrenschmidt opal_pci_tce_kill(phb->opal_id, 2127f0228c41SBenjamin Herrenschmidt OPAL_PCI_TCE_KILL_PAGES, 2128f0228c41SBenjamin Herrenschmidt pe->pe_number, 1u << shift, 2129f0228c41SBenjamin Herrenschmidt index << shift, npages); 2130e57080f1SAlexey Kardashevskiy } 2131e57080f1SAlexey Kardashevskiy } 2132e57080f1SAlexey Kardashevskiy 21336b3d12a9SAlistair Popple void pnv_pci_ioda2_tce_invalidate_entire(struct pnv_phb *phb, bool rm) 21346b3d12a9SAlistair Popple { 21356b3d12a9SAlistair Popple if (phb->model == PNV_PHB_MODEL_NPU || phb->model == PNV_PHB_MODEL_PHB3) 21366b3d12a9SAlistair Popple pnv_pci_phb3_tce_invalidate_entire(phb, rm); 21376b3d12a9SAlistair Popple else 21386b3d12a9SAlistair Popple opal_pci_tce_kill(phb->opal_id, OPAL_PCI_TCE_KILL, 0, 0, 0, 0); 21396b3d12a9SAlistair Popple } 21406b3d12a9SAlistair Popple 2141decbda25SAlexey Kardashevskiy static int pnv_ioda2_tce_build(struct iommu_table *tbl, long index, 2142decbda25SAlexey Kardashevskiy long npages, unsigned long uaddr, 2143decbda25SAlexey Kardashevskiy enum dma_data_direction direction, 214400085f1eSKrzysztof Kozlowski unsigned long attrs) 21454cce9550SGavin Shan { 2146decbda25SAlexey Kardashevskiy int ret = pnv_tce_build(tbl, index, npages, uaddr, direction, 2147decbda25SAlexey Kardashevskiy attrs); 21484cce9550SGavin Shan 214908acce1cSBenjamin Herrenschmidt if (!ret) 2150decbda25SAlexey Kardashevskiy pnv_pci_ioda2_tce_invalidate(tbl, index, npages, false); 2151decbda25SAlexey Kardashevskiy 2152decbda25SAlexey Kardashevskiy return ret; 2153decbda25SAlexey Kardashevskiy } 2154decbda25SAlexey Kardashevskiy 215505c6cfb9SAlexey Kardashevskiy #ifdef CONFIG_IOMMU_API 215605c6cfb9SAlexey Kardashevskiy static int pnv_ioda2_tce_xchg(struct iommu_table *tbl, long index, 215705c6cfb9SAlexey Kardashevskiy unsigned long *hpa, enum dma_data_direction *direction) 215805c6cfb9SAlexey Kardashevskiy { 215905c6cfb9SAlexey Kardashevskiy long ret = pnv_tce_xchg(tbl, index, hpa, direction); 216005c6cfb9SAlexey Kardashevskiy 216108acce1cSBenjamin Herrenschmidt if (!ret) 216205c6cfb9SAlexey Kardashevskiy pnv_pci_ioda2_tce_invalidate(tbl, index, 1, false); 216305c6cfb9SAlexey Kardashevskiy 216405c6cfb9SAlexey Kardashevskiy return ret; 216505c6cfb9SAlexey Kardashevskiy } 2166a540aa56SAlexey Kardashevskiy 2167a540aa56SAlexey Kardashevskiy static int pnv_ioda2_tce_xchg_rm(struct iommu_table *tbl, long index, 2168a540aa56SAlexey Kardashevskiy unsigned long *hpa, enum dma_data_direction *direction) 2169a540aa56SAlexey Kardashevskiy { 2170a540aa56SAlexey Kardashevskiy long ret = pnv_tce_xchg(tbl, index, hpa, direction); 2171a540aa56SAlexey Kardashevskiy 2172a540aa56SAlexey Kardashevskiy if (!ret) 2173a540aa56SAlexey Kardashevskiy pnv_pci_ioda2_tce_invalidate(tbl, index, 1, true); 2174a540aa56SAlexey Kardashevskiy 2175a540aa56SAlexey Kardashevskiy return ret; 2176a540aa56SAlexey Kardashevskiy } 217705c6cfb9SAlexey Kardashevskiy #endif 217805c6cfb9SAlexey Kardashevskiy 2179decbda25SAlexey Kardashevskiy static void pnv_ioda2_tce_free(struct iommu_table *tbl, long index, 2180decbda25SAlexey Kardashevskiy long npages) 2181decbda25SAlexey Kardashevskiy { 2182decbda25SAlexey Kardashevskiy pnv_tce_free(tbl, index, npages); 2183decbda25SAlexey Kardashevskiy 2184decbda25SAlexey Kardashevskiy pnv_pci_ioda2_tce_invalidate(tbl, index, npages, false); 21854cce9550SGavin Shan } 21864cce9550SGavin Shan 21874793d65dSAlexey Kardashevskiy static void pnv_ioda2_table_free(struct iommu_table *tbl) 21884793d65dSAlexey Kardashevskiy { 21894793d65dSAlexey Kardashevskiy pnv_pci_ioda2_table_free_pages(tbl); 21904793d65dSAlexey Kardashevskiy } 21914793d65dSAlexey Kardashevskiy 2192da004c36SAlexey Kardashevskiy static struct iommu_table_ops pnv_ioda2_iommu_ops = { 2193decbda25SAlexey Kardashevskiy .set = pnv_ioda2_tce_build, 219405c6cfb9SAlexey Kardashevskiy #ifdef CONFIG_IOMMU_API 219505c6cfb9SAlexey Kardashevskiy .exchange = pnv_ioda2_tce_xchg, 2196a540aa56SAlexey Kardashevskiy .exchange_rm = pnv_ioda2_tce_xchg_rm, 219705c6cfb9SAlexey Kardashevskiy #endif 2198decbda25SAlexey Kardashevskiy .clear = pnv_ioda2_tce_free, 2199da004c36SAlexey Kardashevskiy .get = pnv_tce_get, 22004793d65dSAlexey Kardashevskiy .free = pnv_ioda2_table_free, 2201da004c36SAlexey Kardashevskiy }; 2202da004c36SAlexey Kardashevskiy 2203801846d1SGavin Shan static int pnv_pci_ioda_dev_dma_weight(struct pci_dev *dev, void *data) 2204801846d1SGavin Shan { 2205801846d1SGavin Shan unsigned int *weight = (unsigned int *)data; 2206801846d1SGavin Shan 2207801846d1SGavin Shan /* This is quite simplistic. The "base" weight of a device 2208801846d1SGavin Shan * is 10. 0 means no DMA is to be accounted for it. 2209801846d1SGavin Shan */ 2210801846d1SGavin Shan if (dev->hdr_type != PCI_HEADER_TYPE_NORMAL) 2211801846d1SGavin Shan return 0; 2212801846d1SGavin Shan 2213801846d1SGavin Shan if (dev->class == PCI_CLASS_SERIAL_USB_UHCI || 2214801846d1SGavin Shan dev->class == PCI_CLASS_SERIAL_USB_OHCI || 2215801846d1SGavin Shan dev->class == PCI_CLASS_SERIAL_USB_EHCI) 2216801846d1SGavin Shan *weight += 3; 2217801846d1SGavin Shan else if ((dev->class >> 8) == PCI_CLASS_STORAGE_RAID) 2218801846d1SGavin Shan *weight += 15; 2219801846d1SGavin Shan else 2220801846d1SGavin Shan *weight += 10; 2221801846d1SGavin Shan 2222801846d1SGavin Shan return 0; 2223801846d1SGavin Shan } 2224801846d1SGavin Shan 2225801846d1SGavin Shan static unsigned int pnv_pci_ioda_pe_dma_weight(struct pnv_ioda_pe *pe) 2226801846d1SGavin Shan { 2227801846d1SGavin Shan unsigned int weight = 0; 2228801846d1SGavin Shan 2229801846d1SGavin Shan /* SRIOV VF has same DMA32 weight as its PF */ 2230801846d1SGavin Shan #ifdef CONFIG_PCI_IOV 2231801846d1SGavin Shan if ((pe->flags & PNV_IODA_PE_VF) && pe->parent_dev) { 2232801846d1SGavin Shan pnv_pci_ioda_dev_dma_weight(pe->parent_dev, &weight); 2233801846d1SGavin Shan return weight; 2234801846d1SGavin Shan } 2235801846d1SGavin Shan #endif 2236801846d1SGavin Shan 2237801846d1SGavin Shan if ((pe->flags & PNV_IODA_PE_DEV) && pe->pdev) { 2238801846d1SGavin Shan pnv_pci_ioda_dev_dma_weight(pe->pdev, &weight); 2239801846d1SGavin Shan } else if ((pe->flags & PNV_IODA_PE_BUS) && pe->pbus) { 2240801846d1SGavin Shan struct pci_dev *pdev; 2241801846d1SGavin Shan 2242801846d1SGavin Shan list_for_each_entry(pdev, &pe->pbus->devices, bus_list) 2243801846d1SGavin Shan pnv_pci_ioda_dev_dma_weight(pdev, &weight); 2244801846d1SGavin Shan } else if ((pe->flags & PNV_IODA_PE_BUS_ALL) && pe->pbus) { 2245801846d1SGavin Shan pci_walk_bus(pe->pbus, pnv_pci_ioda_dev_dma_weight, &weight); 2246801846d1SGavin Shan } 2247801846d1SGavin Shan 2248801846d1SGavin Shan return weight; 2249801846d1SGavin Shan } 2250801846d1SGavin Shan 2251b30d936fSGavin Shan static void pnv_pci_ioda1_setup_dma_pe(struct pnv_phb *phb, 22522b923ed1SGavin Shan struct pnv_ioda_pe *pe) 2253184cd4a3SBenjamin Herrenschmidt { 2254184cd4a3SBenjamin Herrenschmidt 2255184cd4a3SBenjamin Herrenschmidt struct page *tce_mem = NULL; 2256184cd4a3SBenjamin Herrenschmidt struct iommu_table *tbl; 22572b923ed1SGavin Shan unsigned int weight, total_weight = 0; 22582b923ed1SGavin Shan unsigned int tce32_segsz, base, segs, avail, i; 2259184cd4a3SBenjamin Herrenschmidt int64_t rc; 2260184cd4a3SBenjamin Herrenschmidt void *addr; 2261184cd4a3SBenjamin Herrenschmidt 2262184cd4a3SBenjamin Herrenschmidt /* XXX FIXME: Handle 64-bit only DMA devices */ 2263184cd4a3SBenjamin Herrenschmidt /* XXX FIXME: Provide 64-bit DMA facilities & non-4K TCE tables etc.. */ 2264184cd4a3SBenjamin Herrenschmidt /* XXX FIXME: Allocate multi-level tables on PHB3 */ 22652b923ed1SGavin Shan weight = pnv_pci_ioda_pe_dma_weight(pe); 22662b923ed1SGavin Shan if (!weight) 22672b923ed1SGavin Shan return; 2268184cd4a3SBenjamin Herrenschmidt 22692b923ed1SGavin Shan pci_walk_bus(phb->hose->bus, pnv_pci_ioda_dev_dma_weight, 22702b923ed1SGavin Shan &total_weight); 22712b923ed1SGavin Shan segs = (weight * phb->ioda.dma32_count) / total_weight; 22722b923ed1SGavin Shan if (!segs) 22732b923ed1SGavin Shan segs = 1; 22742b923ed1SGavin Shan 22752b923ed1SGavin Shan /* 22762b923ed1SGavin Shan * Allocate contiguous DMA32 segments. We begin with the expected 22772b923ed1SGavin Shan * number of segments. With one more attempt, the number of DMA32 22782b923ed1SGavin Shan * segments to be allocated is decreased by one until one segment 22792b923ed1SGavin Shan * is allocated successfully. 22802b923ed1SGavin Shan */ 22812b923ed1SGavin Shan do { 22822b923ed1SGavin Shan for (base = 0; base <= phb->ioda.dma32_count - segs; base++) { 22832b923ed1SGavin Shan for (avail = 0, i = base; i < base + segs; i++) { 22842b923ed1SGavin Shan if (phb->ioda.dma32_segmap[i] == 22852b923ed1SGavin Shan IODA_INVALID_PE) 22862b923ed1SGavin Shan avail++; 22872b923ed1SGavin Shan } 22882b923ed1SGavin Shan 22892b923ed1SGavin Shan if (avail == segs) 22902b923ed1SGavin Shan goto found; 22912b923ed1SGavin Shan } 22922b923ed1SGavin Shan } while (--segs); 22932b923ed1SGavin Shan 22942b923ed1SGavin Shan if (!segs) { 22952b923ed1SGavin Shan pe_warn(pe, "No available DMA32 segments\n"); 22962b923ed1SGavin Shan return; 22972b923ed1SGavin Shan } 22982b923ed1SGavin Shan 22992b923ed1SGavin Shan found: 23000eaf4defSAlexey Kardashevskiy tbl = pnv_pci_table_alloc(phb->hose->node); 230182eae1afSAlexey Kardashevskiy if (WARN_ON(!tbl)) 230282eae1afSAlexey Kardashevskiy return; 230382eae1afSAlexey Kardashevskiy 2304b348aa65SAlexey Kardashevskiy iommu_register_group(&pe->table_group, phb->hose->global_number, 2305b348aa65SAlexey Kardashevskiy pe->pe_number); 23060eaf4defSAlexey Kardashevskiy pnv_pci_link_table_and_group(phb->hose->node, 0, tbl, &pe->table_group); 2307c5773822SAlexey Kardashevskiy 2308184cd4a3SBenjamin Herrenschmidt /* Grab a 32-bit TCE table */ 23092b923ed1SGavin Shan pe_info(pe, "DMA weight %d (%d), assigned (%d) %d DMA32 segments\n", 23102b923ed1SGavin Shan weight, total_weight, base, segs); 2311184cd4a3SBenjamin Herrenschmidt pe_info(pe, " Setting up 32-bit TCE table at %08x..%08x\n", 2312acce971cSGavin Shan base * PNV_IODA1_DMA32_SEGSIZE, 2313acce971cSGavin Shan (base + segs) * PNV_IODA1_DMA32_SEGSIZE - 1); 2314184cd4a3SBenjamin Herrenschmidt 2315184cd4a3SBenjamin Herrenschmidt /* XXX Currently, we allocate one big contiguous table for the 2316184cd4a3SBenjamin Herrenschmidt * TCEs. We only really need one chunk per 256M of TCE space 2317184cd4a3SBenjamin Herrenschmidt * (ie per segment) but that's an optimization for later, it 2318184cd4a3SBenjamin Herrenschmidt * requires some added smarts with our get/put_tce implementation 2319acce971cSGavin Shan * 2320acce971cSGavin Shan * Each TCE page is 4KB in size and each TCE entry occupies 8 2321acce971cSGavin Shan * bytes 2322184cd4a3SBenjamin Herrenschmidt */ 2323acce971cSGavin Shan tce32_segsz = PNV_IODA1_DMA32_SEGSIZE >> (IOMMU_PAGE_SHIFT_4K - 3); 2324184cd4a3SBenjamin Herrenschmidt tce_mem = alloc_pages_node(phb->hose->node, GFP_KERNEL, 2325acce971cSGavin Shan get_order(tce32_segsz * segs)); 2326184cd4a3SBenjamin Herrenschmidt if (!tce_mem) { 2327184cd4a3SBenjamin Herrenschmidt pe_err(pe, " Failed to allocate a 32-bit TCE memory\n"); 2328184cd4a3SBenjamin Herrenschmidt goto fail; 2329184cd4a3SBenjamin Herrenschmidt } 2330184cd4a3SBenjamin Herrenschmidt addr = page_address(tce_mem); 2331acce971cSGavin Shan memset(addr, 0, tce32_segsz * segs); 2332184cd4a3SBenjamin Herrenschmidt 2333184cd4a3SBenjamin Herrenschmidt /* Configure HW */ 2334184cd4a3SBenjamin Herrenschmidt for (i = 0; i < segs; i++) { 2335184cd4a3SBenjamin Herrenschmidt rc = opal_pci_map_pe_dma_window(phb->opal_id, 2336184cd4a3SBenjamin Herrenschmidt pe->pe_number, 2337184cd4a3SBenjamin Herrenschmidt base + i, 1, 2338acce971cSGavin Shan __pa(addr) + tce32_segsz * i, 2339acce971cSGavin Shan tce32_segsz, IOMMU_PAGE_SIZE_4K); 2340184cd4a3SBenjamin Herrenschmidt if (rc) { 2341184cd4a3SBenjamin Herrenschmidt pe_err(pe, " Failed to configure 32-bit TCE table," 2342184cd4a3SBenjamin Herrenschmidt " err %ld\n", rc); 2343184cd4a3SBenjamin Herrenschmidt goto fail; 2344184cd4a3SBenjamin Herrenschmidt } 2345184cd4a3SBenjamin Herrenschmidt } 2346184cd4a3SBenjamin Herrenschmidt 23472b923ed1SGavin Shan /* Setup DMA32 segment mapping */ 23482b923ed1SGavin Shan for (i = base; i < base + segs; i++) 23492b923ed1SGavin Shan phb->ioda.dma32_segmap[i] = pe->pe_number; 23502b923ed1SGavin Shan 2351184cd4a3SBenjamin Herrenschmidt /* Setup linux iommu table */ 2352acce971cSGavin Shan pnv_pci_setup_iommu_table(tbl, addr, tce32_segsz * segs, 2353acce971cSGavin Shan base * PNV_IODA1_DMA32_SEGSIZE, 2354acce971cSGavin Shan IOMMU_PAGE_SHIFT_4K); 2355184cd4a3SBenjamin Herrenschmidt 2356da004c36SAlexey Kardashevskiy tbl->it_ops = &pnv_ioda1_iommu_ops; 23574793d65dSAlexey Kardashevskiy pe->table_group.tce32_start = tbl->it_offset << tbl->it_page_shift; 23584793d65dSAlexey Kardashevskiy pe->table_group.tce32_size = tbl->it_size << tbl->it_page_shift; 2359184cd4a3SBenjamin Herrenschmidt iommu_init_table(tbl, phb->hose->node); 2360184cd4a3SBenjamin Herrenschmidt 2361781a868fSWei Yang if (pe->flags & PNV_IODA_PE_DEV) { 23624617082eSAlexey Kardashevskiy /* 23634617082eSAlexey Kardashevskiy * Setting table base here only for carrying iommu_group 23644617082eSAlexey Kardashevskiy * further down to let iommu_add_device() do the job. 23654617082eSAlexey Kardashevskiy * pnv_pci_ioda_dma_dev_setup will override it later anyway. 23664617082eSAlexey Kardashevskiy */ 23674617082eSAlexey Kardashevskiy set_iommu_table_base(&pe->pdev->dev, tbl); 23684617082eSAlexey Kardashevskiy iommu_add_device(&pe->pdev->dev); 2369c5773822SAlexey Kardashevskiy } else if (pe->flags & (PNV_IODA_PE_BUS | PNV_IODA_PE_BUS_ALL)) 2370db08e1d5SAlexey Kardashevskiy pnv_ioda_setup_bus_dma(pe, pe->pbus, true); 237174251fe2SBenjamin Herrenschmidt 2372184cd4a3SBenjamin Herrenschmidt return; 2373184cd4a3SBenjamin Herrenschmidt fail: 2374184cd4a3SBenjamin Herrenschmidt /* XXX Failure: Try to fallback to 64-bit only ? */ 2375184cd4a3SBenjamin Herrenschmidt if (tce_mem) 2376acce971cSGavin Shan __free_pages(tce_mem, get_order(tce32_segsz * segs)); 23770eaf4defSAlexey Kardashevskiy if (tbl) { 23780eaf4defSAlexey Kardashevskiy pnv_pci_unlink_table_and_group(tbl, &pe->table_group); 2379e5afdf9dSAlexey Kardashevskiy iommu_tce_table_put(tbl); 23800eaf4defSAlexey Kardashevskiy } 2381184cd4a3SBenjamin Herrenschmidt } 2382184cd4a3SBenjamin Herrenschmidt 238343cb60abSAlexey Kardashevskiy static long pnv_pci_ioda2_set_window(struct iommu_table_group *table_group, 238443cb60abSAlexey Kardashevskiy int num, struct iommu_table *tbl) 238543cb60abSAlexey Kardashevskiy { 238643cb60abSAlexey Kardashevskiy struct pnv_ioda_pe *pe = container_of(table_group, struct pnv_ioda_pe, 238743cb60abSAlexey Kardashevskiy table_group); 238843cb60abSAlexey Kardashevskiy struct pnv_phb *phb = pe->phb; 238943cb60abSAlexey Kardashevskiy int64_t rc; 2390bbb845c4SAlexey Kardashevskiy const unsigned long size = tbl->it_indirect_levels ? 2391bbb845c4SAlexey Kardashevskiy tbl->it_level_size : tbl->it_size; 239243cb60abSAlexey Kardashevskiy const __u64 start_addr = tbl->it_offset << tbl->it_page_shift; 239343cb60abSAlexey Kardashevskiy const __u64 win_size = tbl->it_size << tbl->it_page_shift; 239443cb60abSAlexey Kardashevskiy 23954793d65dSAlexey Kardashevskiy pe_info(pe, "Setting up window#%d %llx..%llx pg=%x\n", num, 239643cb60abSAlexey Kardashevskiy start_addr, start_addr + win_size - 1, 239743cb60abSAlexey Kardashevskiy IOMMU_PAGE_SIZE(tbl)); 239843cb60abSAlexey Kardashevskiy 239943cb60abSAlexey Kardashevskiy /* 240043cb60abSAlexey Kardashevskiy * Map TCE table through TVT. The TVE index is the PE number 240143cb60abSAlexey Kardashevskiy * shifted by 1 bit for 32-bits DMA space. 240243cb60abSAlexey Kardashevskiy */ 240343cb60abSAlexey Kardashevskiy rc = opal_pci_map_pe_dma_window(phb->opal_id, 240443cb60abSAlexey Kardashevskiy pe->pe_number, 24054793d65dSAlexey Kardashevskiy (pe->pe_number << 1) + num, 2406bbb845c4SAlexey Kardashevskiy tbl->it_indirect_levels + 1, 240743cb60abSAlexey Kardashevskiy __pa(tbl->it_base), 2408bbb845c4SAlexey Kardashevskiy size << 3, 240943cb60abSAlexey Kardashevskiy IOMMU_PAGE_SIZE(tbl)); 241043cb60abSAlexey Kardashevskiy if (rc) { 241143cb60abSAlexey Kardashevskiy pe_err(pe, "Failed to configure TCE table, err %ld\n", rc); 241243cb60abSAlexey Kardashevskiy return rc; 241343cb60abSAlexey Kardashevskiy } 241443cb60abSAlexey Kardashevskiy 241543cb60abSAlexey Kardashevskiy pnv_pci_link_table_and_group(phb->hose->node, num, 241643cb60abSAlexey Kardashevskiy tbl, &pe->table_group); 2417ed7d9a1dSMichael Ellerman pnv_pci_ioda2_tce_invalidate_pe(pe); 241843cb60abSAlexey Kardashevskiy 241943cb60abSAlexey Kardashevskiy return 0; 242043cb60abSAlexey Kardashevskiy } 242143cb60abSAlexey Kardashevskiy 242225529100SFrederic Barrat void pnv_pci_ioda2_set_bypass(struct pnv_ioda_pe *pe, bool enable) 2423cd15b048SBenjamin Herrenschmidt { 2424cd15b048SBenjamin Herrenschmidt uint16_t window_id = (pe->pe_number << 1 ) + 1; 2425cd15b048SBenjamin Herrenschmidt int64_t rc; 2426cd15b048SBenjamin Herrenschmidt 2427cd15b048SBenjamin Herrenschmidt pe_info(pe, "%sabling 64-bit DMA bypass\n", enable ? "En" : "Dis"); 2428cd15b048SBenjamin Herrenschmidt if (enable) { 2429cd15b048SBenjamin Herrenschmidt phys_addr_t top = memblock_end_of_DRAM(); 2430cd15b048SBenjamin Herrenschmidt 2431cd15b048SBenjamin Herrenschmidt top = roundup_pow_of_two(top); 2432cd15b048SBenjamin Herrenschmidt rc = opal_pci_map_pe_dma_window_real(pe->phb->opal_id, 2433cd15b048SBenjamin Herrenschmidt pe->pe_number, 2434cd15b048SBenjamin Herrenschmidt window_id, 2435cd15b048SBenjamin Herrenschmidt pe->tce_bypass_base, 2436cd15b048SBenjamin Herrenschmidt top); 2437cd15b048SBenjamin Herrenschmidt } else { 2438cd15b048SBenjamin Herrenschmidt rc = opal_pci_map_pe_dma_window_real(pe->phb->opal_id, 2439cd15b048SBenjamin Herrenschmidt pe->pe_number, 2440cd15b048SBenjamin Herrenschmidt window_id, 2441cd15b048SBenjamin Herrenschmidt pe->tce_bypass_base, 2442cd15b048SBenjamin Herrenschmidt 0); 2443cd15b048SBenjamin Herrenschmidt } 2444cd15b048SBenjamin Herrenschmidt if (rc) 2445cd15b048SBenjamin Herrenschmidt pe_err(pe, "OPAL error %lld configuring bypass window\n", rc); 2446cd15b048SBenjamin Herrenschmidt else 2447cd15b048SBenjamin Herrenschmidt pe->tce_bypass_enabled = enable; 2448cd15b048SBenjamin Herrenschmidt } 2449cd15b048SBenjamin Herrenschmidt 24504793d65dSAlexey Kardashevskiy static long pnv_pci_ioda2_table_alloc_pages(int nid, __u64 bus_offset, 24514793d65dSAlexey Kardashevskiy __u32 page_shift, __u64 window_size, __u32 levels, 24524793d65dSAlexey Kardashevskiy struct iommu_table *tbl); 24534793d65dSAlexey Kardashevskiy 24544793d65dSAlexey Kardashevskiy static long pnv_pci_ioda2_create_table(struct iommu_table_group *table_group, 24554793d65dSAlexey Kardashevskiy int num, __u32 page_shift, __u64 window_size, __u32 levels, 24564793d65dSAlexey Kardashevskiy struct iommu_table **ptbl) 24574793d65dSAlexey Kardashevskiy { 24584793d65dSAlexey Kardashevskiy struct pnv_ioda_pe *pe = container_of(table_group, struct pnv_ioda_pe, 24594793d65dSAlexey Kardashevskiy table_group); 24604793d65dSAlexey Kardashevskiy int nid = pe->phb->hose->node; 24614793d65dSAlexey Kardashevskiy __u64 bus_offset = num ? pe->tce_bypass_base : table_group->tce32_start; 24624793d65dSAlexey Kardashevskiy long ret; 24634793d65dSAlexey Kardashevskiy struct iommu_table *tbl; 24644793d65dSAlexey Kardashevskiy 24654793d65dSAlexey Kardashevskiy tbl = pnv_pci_table_alloc(nid); 24664793d65dSAlexey Kardashevskiy if (!tbl) 24674793d65dSAlexey Kardashevskiy return -ENOMEM; 24684793d65dSAlexey Kardashevskiy 246911edf116SAlexey Kardashevskiy tbl->it_ops = &pnv_ioda2_iommu_ops; 247011edf116SAlexey Kardashevskiy 24714793d65dSAlexey Kardashevskiy ret = pnv_pci_ioda2_table_alloc_pages(nid, 24724793d65dSAlexey Kardashevskiy bus_offset, page_shift, window_size, 24734793d65dSAlexey Kardashevskiy levels, tbl); 24744793d65dSAlexey Kardashevskiy if (ret) { 2475e5afdf9dSAlexey Kardashevskiy iommu_tce_table_put(tbl); 24764793d65dSAlexey Kardashevskiy return ret; 24774793d65dSAlexey Kardashevskiy } 24784793d65dSAlexey Kardashevskiy 24794793d65dSAlexey Kardashevskiy *ptbl = tbl; 24804793d65dSAlexey Kardashevskiy 24814793d65dSAlexey Kardashevskiy return 0; 24824793d65dSAlexey Kardashevskiy } 24834793d65dSAlexey Kardashevskiy 248446d3e1e1SAlexey Kardashevskiy static long pnv_pci_ioda2_setup_default_config(struct pnv_ioda_pe *pe) 248546d3e1e1SAlexey Kardashevskiy { 248646d3e1e1SAlexey Kardashevskiy struct iommu_table *tbl = NULL; 248746d3e1e1SAlexey Kardashevskiy long rc; 248846d3e1e1SAlexey Kardashevskiy 2489bb005455SNishanth Aravamudan /* 2490fa144869SNishanth Aravamudan * crashkernel= specifies the kdump kernel's maximum memory at 2491fa144869SNishanth Aravamudan * some offset and there is no guaranteed the result is a power 2492fa144869SNishanth Aravamudan * of 2, which will cause errors later. 2493fa144869SNishanth Aravamudan */ 2494fa144869SNishanth Aravamudan const u64 max_memory = __rounddown_pow_of_two(memory_hotplug_max()); 2495fa144869SNishanth Aravamudan 2496fa144869SNishanth Aravamudan /* 2497bb005455SNishanth Aravamudan * In memory constrained environments, e.g. kdump kernel, the 2498bb005455SNishanth Aravamudan * DMA window can be larger than available memory, which will 2499bb005455SNishanth Aravamudan * cause errors later. 2500bb005455SNishanth Aravamudan */ 2501fa144869SNishanth Aravamudan const u64 window_size = min((u64)pe->table_group.tce32_size, max_memory); 2502bb005455SNishanth Aravamudan 250346d3e1e1SAlexey Kardashevskiy rc = pnv_pci_ioda2_create_table(&pe->table_group, 0, 250446d3e1e1SAlexey Kardashevskiy IOMMU_PAGE_SHIFT_4K, 2505bb005455SNishanth Aravamudan window_size, 250646d3e1e1SAlexey Kardashevskiy POWERNV_IOMMU_DEFAULT_LEVELS, &tbl); 250746d3e1e1SAlexey Kardashevskiy if (rc) { 250846d3e1e1SAlexey Kardashevskiy pe_err(pe, "Failed to create 32-bit TCE table, err %ld", 250946d3e1e1SAlexey Kardashevskiy rc); 251046d3e1e1SAlexey Kardashevskiy return rc; 251146d3e1e1SAlexey Kardashevskiy } 251246d3e1e1SAlexey Kardashevskiy 251346d3e1e1SAlexey Kardashevskiy iommu_init_table(tbl, pe->phb->hose->node); 251446d3e1e1SAlexey Kardashevskiy 251546d3e1e1SAlexey Kardashevskiy rc = pnv_pci_ioda2_set_window(&pe->table_group, 0, tbl); 251646d3e1e1SAlexey Kardashevskiy if (rc) { 251746d3e1e1SAlexey Kardashevskiy pe_err(pe, "Failed to configure 32-bit TCE table, err %ld\n", 251846d3e1e1SAlexey Kardashevskiy rc); 2519e5afdf9dSAlexey Kardashevskiy iommu_tce_table_put(tbl); 252046d3e1e1SAlexey Kardashevskiy return rc; 252146d3e1e1SAlexey Kardashevskiy } 252246d3e1e1SAlexey Kardashevskiy 252346d3e1e1SAlexey Kardashevskiy if (!pnv_iommu_bypass_disabled) 252446d3e1e1SAlexey Kardashevskiy pnv_pci_ioda2_set_bypass(pe, true); 252546d3e1e1SAlexey Kardashevskiy 252646d3e1e1SAlexey Kardashevskiy /* 252746d3e1e1SAlexey Kardashevskiy * Setting table base here only for carrying iommu_group 252846d3e1e1SAlexey Kardashevskiy * further down to let iommu_add_device() do the job. 252946d3e1e1SAlexey Kardashevskiy * pnv_pci_ioda_dma_dev_setup will override it later anyway. 253046d3e1e1SAlexey Kardashevskiy */ 253146d3e1e1SAlexey Kardashevskiy if (pe->flags & PNV_IODA_PE_DEV) 253246d3e1e1SAlexey Kardashevskiy set_iommu_table_base(&pe->pdev->dev, tbl); 253346d3e1e1SAlexey Kardashevskiy 253446d3e1e1SAlexey Kardashevskiy return 0; 253546d3e1e1SAlexey Kardashevskiy } 253646d3e1e1SAlexey Kardashevskiy 2537b5926430SAlexey Kardashevskiy #if defined(CONFIG_IOMMU_API) || defined(CONFIG_PCI_IOV) 2538b5926430SAlexey Kardashevskiy static long pnv_pci_ioda2_unset_window(struct iommu_table_group *table_group, 2539b5926430SAlexey Kardashevskiy int num) 2540b5926430SAlexey Kardashevskiy { 2541b5926430SAlexey Kardashevskiy struct pnv_ioda_pe *pe = container_of(table_group, struct pnv_ioda_pe, 2542b5926430SAlexey Kardashevskiy table_group); 2543b5926430SAlexey Kardashevskiy struct pnv_phb *phb = pe->phb; 2544b5926430SAlexey Kardashevskiy long ret; 2545b5926430SAlexey Kardashevskiy 2546b5926430SAlexey Kardashevskiy pe_info(pe, "Removing DMA window #%d\n", num); 2547b5926430SAlexey Kardashevskiy 2548b5926430SAlexey Kardashevskiy ret = opal_pci_map_pe_dma_window(phb->opal_id, pe->pe_number, 2549b5926430SAlexey Kardashevskiy (pe->pe_number << 1) + num, 2550b5926430SAlexey Kardashevskiy 0/* levels */, 0/* table address */, 2551b5926430SAlexey Kardashevskiy 0/* table size */, 0/* page size */); 2552b5926430SAlexey Kardashevskiy if (ret) 2553b5926430SAlexey Kardashevskiy pe_warn(pe, "Unmapping failed, ret = %ld\n", ret); 2554b5926430SAlexey Kardashevskiy else 2555ed7d9a1dSMichael Ellerman pnv_pci_ioda2_tce_invalidate_pe(pe); 2556b5926430SAlexey Kardashevskiy 2557b5926430SAlexey Kardashevskiy pnv_pci_unlink_table_and_group(table_group->tables[num], table_group); 2558b5926430SAlexey Kardashevskiy 2559b5926430SAlexey Kardashevskiy return ret; 2560b5926430SAlexey Kardashevskiy } 2561b5926430SAlexey Kardashevskiy #endif 2562b5926430SAlexey Kardashevskiy 2563f87a8864SAlexey Kardashevskiy #ifdef CONFIG_IOMMU_API 256400547193SAlexey Kardashevskiy static unsigned long pnv_pci_ioda2_get_table_size(__u32 page_shift, 256500547193SAlexey Kardashevskiy __u64 window_size, __u32 levels) 256600547193SAlexey Kardashevskiy { 256700547193SAlexey Kardashevskiy unsigned long bytes = 0; 256800547193SAlexey Kardashevskiy const unsigned window_shift = ilog2(window_size); 256900547193SAlexey Kardashevskiy unsigned entries_shift = window_shift - page_shift; 257000547193SAlexey Kardashevskiy unsigned table_shift = entries_shift + 3; 257100547193SAlexey Kardashevskiy unsigned long tce_table_size = max(0x1000UL, 1UL << table_shift); 257200547193SAlexey Kardashevskiy unsigned long direct_table_size; 257300547193SAlexey Kardashevskiy 257400547193SAlexey Kardashevskiy if (!levels || (levels > POWERNV_IOMMU_MAX_LEVELS) || 257500547193SAlexey Kardashevskiy (window_size > memory_hotplug_max()) || 257600547193SAlexey Kardashevskiy !is_power_of_2(window_size)) 257700547193SAlexey Kardashevskiy return 0; 257800547193SAlexey Kardashevskiy 257900547193SAlexey Kardashevskiy /* Calculate a direct table size from window_size and levels */ 258000547193SAlexey Kardashevskiy entries_shift = (entries_shift + levels - 1) / levels; 258100547193SAlexey Kardashevskiy table_shift = entries_shift + 3; 258200547193SAlexey Kardashevskiy table_shift = max_t(unsigned, table_shift, PAGE_SHIFT); 258300547193SAlexey Kardashevskiy direct_table_size = 1UL << table_shift; 258400547193SAlexey Kardashevskiy 258500547193SAlexey Kardashevskiy for ( ; levels; --levels) { 258600547193SAlexey Kardashevskiy bytes += _ALIGN_UP(tce_table_size, direct_table_size); 258700547193SAlexey Kardashevskiy 258800547193SAlexey Kardashevskiy tce_table_size /= direct_table_size; 258900547193SAlexey Kardashevskiy tce_table_size <<= 3; 2590e49a6a21SAlexey Kardashevskiy tce_table_size = max_t(unsigned long, 2591e49a6a21SAlexey Kardashevskiy tce_table_size, direct_table_size); 259200547193SAlexey Kardashevskiy } 259300547193SAlexey Kardashevskiy 259400547193SAlexey Kardashevskiy return bytes; 259500547193SAlexey Kardashevskiy } 259600547193SAlexey Kardashevskiy 2597f87a8864SAlexey Kardashevskiy static void pnv_ioda2_take_ownership(struct iommu_table_group *table_group) 2598cd15b048SBenjamin Herrenschmidt { 2599f87a8864SAlexey Kardashevskiy struct pnv_ioda_pe *pe = container_of(table_group, struct pnv_ioda_pe, 2600f87a8864SAlexey Kardashevskiy table_group); 260146d3e1e1SAlexey Kardashevskiy /* Store @tbl as pnv_pci_ioda2_unset_window() resets it */ 260246d3e1e1SAlexey Kardashevskiy struct iommu_table *tbl = pe->table_group.tables[0]; 2603cd15b048SBenjamin Herrenschmidt 2604f87a8864SAlexey Kardashevskiy pnv_pci_ioda2_set_bypass(pe, false); 260546d3e1e1SAlexey Kardashevskiy pnv_pci_ioda2_unset_window(&pe->table_group, 0); 2606db08e1d5SAlexey Kardashevskiy if (pe->pbus) 2607db08e1d5SAlexey Kardashevskiy pnv_ioda_setup_bus_dma(pe, pe->pbus, false); 2608e5afdf9dSAlexey Kardashevskiy iommu_tce_table_put(tbl); 2609cd15b048SBenjamin Herrenschmidt } 2610cd15b048SBenjamin Herrenschmidt 2611f87a8864SAlexey Kardashevskiy static void pnv_ioda2_release_ownership(struct iommu_table_group *table_group) 2612f87a8864SAlexey Kardashevskiy { 2613f87a8864SAlexey Kardashevskiy struct pnv_ioda_pe *pe = container_of(table_group, struct pnv_ioda_pe, 2614f87a8864SAlexey Kardashevskiy table_group); 2615f87a8864SAlexey Kardashevskiy 261646d3e1e1SAlexey Kardashevskiy pnv_pci_ioda2_setup_default_config(pe); 2617db08e1d5SAlexey Kardashevskiy if (pe->pbus) 2618db08e1d5SAlexey Kardashevskiy pnv_ioda_setup_bus_dma(pe, pe->pbus, false); 2619f87a8864SAlexey Kardashevskiy } 2620f87a8864SAlexey Kardashevskiy 2621f87a8864SAlexey Kardashevskiy static struct iommu_table_group_ops pnv_pci_ioda2_ops = { 262200547193SAlexey Kardashevskiy .get_table_size = pnv_pci_ioda2_get_table_size, 26234793d65dSAlexey Kardashevskiy .create_table = pnv_pci_ioda2_create_table, 26244793d65dSAlexey Kardashevskiy .set_window = pnv_pci_ioda2_set_window, 26254793d65dSAlexey Kardashevskiy .unset_window = pnv_pci_ioda2_unset_window, 2626f87a8864SAlexey Kardashevskiy .take_ownership = pnv_ioda2_take_ownership, 2627f87a8864SAlexey Kardashevskiy .release_ownership = pnv_ioda2_release_ownership, 2628f87a8864SAlexey Kardashevskiy }; 2629b5cb9ab1SAlexey Kardashevskiy 2630b5cb9ab1SAlexey Kardashevskiy static int gpe_table_group_to_npe_cb(struct device *dev, void *opaque) 2631b5cb9ab1SAlexey Kardashevskiy { 2632b5cb9ab1SAlexey Kardashevskiy struct pci_controller *hose; 2633b5cb9ab1SAlexey Kardashevskiy struct pnv_phb *phb; 2634b5cb9ab1SAlexey Kardashevskiy struct pnv_ioda_pe **ptmppe = opaque; 2635b5cb9ab1SAlexey Kardashevskiy struct pci_dev *pdev = container_of(dev, struct pci_dev, dev); 2636b5cb9ab1SAlexey Kardashevskiy struct pci_dn *pdn = pci_get_pdn(pdev); 2637b5cb9ab1SAlexey Kardashevskiy 2638b5cb9ab1SAlexey Kardashevskiy if (!pdn || pdn->pe_number == IODA_INVALID_PE) 2639b5cb9ab1SAlexey Kardashevskiy return 0; 2640b5cb9ab1SAlexey Kardashevskiy 2641b5cb9ab1SAlexey Kardashevskiy hose = pci_bus_to_host(pdev->bus); 2642b5cb9ab1SAlexey Kardashevskiy phb = hose->private_data; 2643b5cb9ab1SAlexey Kardashevskiy if (phb->type != PNV_PHB_NPU) 2644b5cb9ab1SAlexey Kardashevskiy return 0; 2645b5cb9ab1SAlexey Kardashevskiy 2646b5cb9ab1SAlexey Kardashevskiy *ptmppe = &phb->ioda.pe_array[pdn->pe_number]; 2647b5cb9ab1SAlexey Kardashevskiy 2648b5cb9ab1SAlexey Kardashevskiy return 1; 2649b5cb9ab1SAlexey Kardashevskiy } 2650b5cb9ab1SAlexey Kardashevskiy 2651b5cb9ab1SAlexey Kardashevskiy /* 2652b5cb9ab1SAlexey Kardashevskiy * This returns PE of associated NPU. 2653b5cb9ab1SAlexey Kardashevskiy * This assumes that NPU is in the same IOMMU group with GPU and there is 2654b5cb9ab1SAlexey Kardashevskiy * no other PEs. 2655b5cb9ab1SAlexey Kardashevskiy */ 2656b5cb9ab1SAlexey Kardashevskiy static struct pnv_ioda_pe *gpe_table_group_to_npe( 2657b5cb9ab1SAlexey Kardashevskiy struct iommu_table_group *table_group) 2658b5cb9ab1SAlexey Kardashevskiy { 2659b5cb9ab1SAlexey Kardashevskiy struct pnv_ioda_pe *npe = NULL; 2660b5cb9ab1SAlexey Kardashevskiy int ret = iommu_group_for_each_dev(table_group->group, &npe, 2661b5cb9ab1SAlexey Kardashevskiy gpe_table_group_to_npe_cb); 2662b5cb9ab1SAlexey Kardashevskiy 2663b5cb9ab1SAlexey Kardashevskiy BUG_ON(!ret || !npe); 2664b5cb9ab1SAlexey Kardashevskiy 2665b5cb9ab1SAlexey Kardashevskiy return npe; 2666b5cb9ab1SAlexey Kardashevskiy } 2667b5cb9ab1SAlexey Kardashevskiy 2668b5cb9ab1SAlexey Kardashevskiy static long pnv_pci_ioda2_npu_set_window(struct iommu_table_group *table_group, 2669b5cb9ab1SAlexey Kardashevskiy int num, struct iommu_table *tbl) 2670b5cb9ab1SAlexey Kardashevskiy { 2671b5cb9ab1SAlexey Kardashevskiy long ret = pnv_pci_ioda2_set_window(table_group, num, tbl); 2672b5cb9ab1SAlexey Kardashevskiy 2673b5cb9ab1SAlexey Kardashevskiy if (ret) 2674b5cb9ab1SAlexey Kardashevskiy return ret; 2675b5cb9ab1SAlexey Kardashevskiy 2676b5cb9ab1SAlexey Kardashevskiy ret = pnv_npu_set_window(gpe_table_group_to_npe(table_group), num, tbl); 2677b5cb9ab1SAlexey Kardashevskiy if (ret) 2678b5cb9ab1SAlexey Kardashevskiy pnv_pci_ioda2_unset_window(table_group, num); 2679b5cb9ab1SAlexey Kardashevskiy 2680b5cb9ab1SAlexey Kardashevskiy return ret; 2681b5cb9ab1SAlexey Kardashevskiy } 2682b5cb9ab1SAlexey Kardashevskiy 2683b5cb9ab1SAlexey Kardashevskiy static long pnv_pci_ioda2_npu_unset_window( 2684b5cb9ab1SAlexey Kardashevskiy struct iommu_table_group *table_group, 2685b5cb9ab1SAlexey Kardashevskiy int num) 2686b5cb9ab1SAlexey Kardashevskiy { 2687b5cb9ab1SAlexey Kardashevskiy long ret = pnv_pci_ioda2_unset_window(table_group, num); 2688b5cb9ab1SAlexey Kardashevskiy 2689b5cb9ab1SAlexey Kardashevskiy if (ret) 2690b5cb9ab1SAlexey Kardashevskiy return ret; 2691b5cb9ab1SAlexey Kardashevskiy 2692b5cb9ab1SAlexey Kardashevskiy return pnv_npu_unset_window(gpe_table_group_to_npe(table_group), num); 2693b5cb9ab1SAlexey Kardashevskiy } 2694b5cb9ab1SAlexey Kardashevskiy 2695b5cb9ab1SAlexey Kardashevskiy static void pnv_ioda2_npu_take_ownership(struct iommu_table_group *table_group) 2696b5cb9ab1SAlexey Kardashevskiy { 2697b5cb9ab1SAlexey Kardashevskiy /* 2698b5cb9ab1SAlexey Kardashevskiy * Detach NPU first as pnv_ioda2_take_ownership() will destroy 2699b5cb9ab1SAlexey Kardashevskiy * the iommu_table if 32bit DMA is enabled. 2700b5cb9ab1SAlexey Kardashevskiy */ 2701b5cb9ab1SAlexey Kardashevskiy pnv_npu_take_ownership(gpe_table_group_to_npe(table_group)); 2702b5cb9ab1SAlexey Kardashevskiy pnv_ioda2_take_ownership(table_group); 2703b5cb9ab1SAlexey Kardashevskiy } 2704b5cb9ab1SAlexey Kardashevskiy 2705b5cb9ab1SAlexey Kardashevskiy static struct iommu_table_group_ops pnv_pci_ioda2_npu_ops = { 2706b5cb9ab1SAlexey Kardashevskiy .get_table_size = pnv_pci_ioda2_get_table_size, 2707b5cb9ab1SAlexey Kardashevskiy .create_table = pnv_pci_ioda2_create_table, 2708b5cb9ab1SAlexey Kardashevskiy .set_window = pnv_pci_ioda2_npu_set_window, 2709b5cb9ab1SAlexey Kardashevskiy .unset_window = pnv_pci_ioda2_npu_unset_window, 2710b5cb9ab1SAlexey Kardashevskiy .take_ownership = pnv_ioda2_npu_take_ownership, 2711b5cb9ab1SAlexey Kardashevskiy .release_ownership = pnv_ioda2_release_ownership, 2712b5cb9ab1SAlexey Kardashevskiy }; 2713b5cb9ab1SAlexey Kardashevskiy 2714b5cb9ab1SAlexey Kardashevskiy static void pnv_pci_ioda_setup_iommu_api(void) 2715b5cb9ab1SAlexey Kardashevskiy { 2716b5cb9ab1SAlexey Kardashevskiy struct pci_controller *hose, *tmp; 2717b5cb9ab1SAlexey Kardashevskiy struct pnv_phb *phb; 2718b5cb9ab1SAlexey Kardashevskiy struct pnv_ioda_pe *pe, *gpe; 2719b5cb9ab1SAlexey Kardashevskiy 2720b5cb9ab1SAlexey Kardashevskiy /* 2721b5cb9ab1SAlexey Kardashevskiy * Now we have all PHBs discovered, time to add NPU devices to 2722b5cb9ab1SAlexey Kardashevskiy * the corresponding IOMMU groups. 2723b5cb9ab1SAlexey Kardashevskiy */ 2724b5cb9ab1SAlexey Kardashevskiy list_for_each_entry_safe(hose, tmp, &hose_list, list_node) { 2725b5cb9ab1SAlexey Kardashevskiy phb = hose->private_data; 2726b5cb9ab1SAlexey Kardashevskiy 2727b5cb9ab1SAlexey Kardashevskiy if (phb->type != PNV_PHB_NPU) 2728b5cb9ab1SAlexey Kardashevskiy continue; 2729b5cb9ab1SAlexey Kardashevskiy 2730b5cb9ab1SAlexey Kardashevskiy list_for_each_entry(pe, &phb->ioda.pe_list, list) { 2731b5cb9ab1SAlexey Kardashevskiy gpe = pnv_pci_npu_setup_iommu(pe); 2732b5cb9ab1SAlexey Kardashevskiy if (gpe) 2733b5cb9ab1SAlexey Kardashevskiy gpe->table_group.ops = &pnv_pci_ioda2_npu_ops; 2734b5cb9ab1SAlexey Kardashevskiy } 2735b5cb9ab1SAlexey Kardashevskiy } 2736b5cb9ab1SAlexey Kardashevskiy } 2737b5cb9ab1SAlexey Kardashevskiy #else /* !CONFIG_IOMMU_API */ 2738b5cb9ab1SAlexey Kardashevskiy static void pnv_pci_ioda_setup_iommu_api(void) { }; 2739f87a8864SAlexey Kardashevskiy #endif 2740f87a8864SAlexey Kardashevskiy 2741bbb845c4SAlexey Kardashevskiy static __be64 *pnv_pci_ioda2_table_do_alloc_pages(int nid, unsigned shift, 2742bbb845c4SAlexey Kardashevskiy unsigned levels, unsigned long limit, 27433ba3a73eSAlexey Kardashevskiy unsigned long *current_offset, unsigned long *total_allocated) 2744aca6913fSAlexey Kardashevskiy { 2745aca6913fSAlexey Kardashevskiy struct page *tce_mem = NULL; 2746bbb845c4SAlexey Kardashevskiy __be64 *addr, *tmp; 2747aca6913fSAlexey Kardashevskiy unsigned order = max_t(unsigned, shift, PAGE_SHIFT) - PAGE_SHIFT; 2748bbb845c4SAlexey Kardashevskiy unsigned long allocated = 1UL << (order + PAGE_SHIFT); 2749bbb845c4SAlexey Kardashevskiy unsigned entries = 1UL << (shift - 3); 2750bbb845c4SAlexey Kardashevskiy long i; 2751aca6913fSAlexey Kardashevskiy 2752aca6913fSAlexey Kardashevskiy tce_mem = alloc_pages_node(nid, GFP_KERNEL, order); 2753aca6913fSAlexey Kardashevskiy if (!tce_mem) { 2754aca6913fSAlexey Kardashevskiy pr_err("Failed to allocate a TCE memory, order=%d\n", order); 2755aca6913fSAlexey Kardashevskiy return NULL; 2756aca6913fSAlexey Kardashevskiy } 2757aca6913fSAlexey Kardashevskiy addr = page_address(tce_mem); 2758bbb845c4SAlexey Kardashevskiy memset(addr, 0, allocated); 27593ba3a73eSAlexey Kardashevskiy *total_allocated += allocated; 2760bbb845c4SAlexey Kardashevskiy 2761bbb845c4SAlexey Kardashevskiy --levels; 2762bbb845c4SAlexey Kardashevskiy if (!levels) { 2763bbb845c4SAlexey Kardashevskiy *current_offset += allocated; 2764bbb845c4SAlexey Kardashevskiy return addr; 2765bbb845c4SAlexey Kardashevskiy } 2766bbb845c4SAlexey Kardashevskiy 2767bbb845c4SAlexey Kardashevskiy for (i = 0; i < entries; ++i) { 2768bbb845c4SAlexey Kardashevskiy tmp = pnv_pci_ioda2_table_do_alloc_pages(nid, shift, 27693ba3a73eSAlexey Kardashevskiy levels, limit, current_offset, total_allocated); 2770bbb845c4SAlexey Kardashevskiy if (!tmp) 2771bbb845c4SAlexey Kardashevskiy break; 2772bbb845c4SAlexey Kardashevskiy 2773bbb845c4SAlexey Kardashevskiy addr[i] = cpu_to_be64(__pa(tmp) | 2774bbb845c4SAlexey Kardashevskiy TCE_PCI_READ | TCE_PCI_WRITE); 2775bbb845c4SAlexey Kardashevskiy 2776bbb845c4SAlexey Kardashevskiy if (*current_offset >= limit) 2777bbb845c4SAlexey Kardashevskiy break; 2778bbb845c4SAlexey Kardashevskiy } 2779aca6913fSAlexey Kardashevskiy 2780aca6913fSAlexey Kardashevskiy return addr; 2781aca6913fSAlexey Kardashevskiy } 2782aca6913fSAlexey Kardashevskiy 2783bbb845c4SAlexey Kardashevskiy static void pnv_pci_ioda2_table_do_free_pages(__be64 *addr, 2784bbb845c4SAlexey Kardashevskiy unsigned long size, unsigned level); 2785bbb845c4SAlexey Kardashevskiy 2786aca6913fSAlexey Kardashevskiy static long pnv_pci_ioda2_table_alloc_pages(int nid, __u64 bus_offset, 2787bbb845c4SAlexey Kardashevskiy __u32 page_shift, __u64 window_size, __u32 levels, 2788bbb845c4SAlexey Kardashevskiy struct iommu_table *tbl) 2789aca6913fSAlexey Kardashevskiy { 2790aca6913fSAlexey Kardashevskiy void *addr; 27913ba3a73eSAlexey Kardashevskiy unsigned long offset = 0, level_shift, total_allocated = 0; 2792aca6913fSAlexey Kardashevskiy const unsigned window_shift = ilog2(window_size); 2793aca6913fSAlexey Kardashevskiy unsigned entries_shift = window_shift - page_shift; 2794aca6913fSAlexey Kardashevskiy unsigned table_shift = max_t(unsigned, entries_shift + 3, PAGE_SHIFT); 2795aca6913fSAlexey Kardashevskiy const unsigned long tce_table_size = 1UL << table_shift; 2796aca6913fSAlexey Kardashevskiy 2797bbb845c4SAlexey Kardashevskiy if (!levels || (levels > POWERNV_IOMMU_MAX_LEVELS)) 2798bbb845c4SAlexey Kardashevskiy return -EINVAL; 2799bbb845c4SAlexey Kardashevskiy 28009003a249SAlexey Kardashevskiy if (!is_power_of_2(window_size)) 2801aca6913fSAlexey Kardashevskiy return -EINVAL; 2802aca6913fSAlexey Kardashevskiy 2803bbb845c4SAlexey Kardashevskiy /* Adjust direct table size from window_size and levels */ 2804bbb845c4SAlexey Kardashevskiy entries_shift = (entries_shift + levels - 1) / levels; 2805bbb845c4SAlexey Kardashevskiy level_shift = entries_shift + 3; 2806bbb845c4SAlexey Kardashevskiy level_shift = max_t(unsigned, level_shift, PAGE_SHIFT); 2807bbb845c4SAlexey Kardashevskiy 28087aafac11SAlexey Kardashevskiy if ((level_shift - 3) * levels + page_shift >= 60) 28097aafac11SAlexey Kardashevskiy return -EINVAL; 28107aafac11SAlexey Kardashevskiy 2811aca6913fSAlexey Kardashevskiy /* Allocate TCE table */ 2812bbb845c4SAlexey Kardashevskiy addr = pnv_pci_ioda2_table_do_alloc_pages(nid, level_shift, 28133ba3a73eSAlexey Kardashevskiy levels, tce_table_size, &offset, &total_allocated); 2814bbb845c4SAlexey Kardashevskiy 2815bbb845c4SAlexey Kardashevskiy /* addr==NULL means that the first level allocation failed */ 2816aca6913fSAlexey Kardashevskiy if (!addr) 2817aca6913fSAlexey Kardashevskiy return -ENOMEM; 2818aca6913fSAlexey Kardashevskiy 2819bbb845c4SAlexey Kardashevskiy /* 2820bbb845c4SAlexey Kardashevskiy * First level was allocated but some lower level failed as 2821bbb845c4SAlexey Kardashevskiy * we did not allocate as much as we wanted, 2822bbb845c4SAlexey Kardashevskiy * release partially allocated table. 2823bbb845c4SAlexey Kardashevskiy */ 2824bbb845c4SAlexey Kardashevskiy if (offset < tce_table_size) { 2825bbb845c4SAlexey Kardashevskiy pnv_pci_ioda2_table_do_free_pages(addr, 2826bbb845c4SAlexey Kardashevskiy 1ULL << (level_shift - 3), levels - 1); 2827bbb845c4SAlexey Kardashevskiy return -ENOMEM; 2828bbb845c4SAlexey Kardashevskiy } 2829bbb845c4SAlexey Kardashevskiy 2830aca6913fSAlexey Kardashevskiy /* Setup linux iommu table */ 2831aca6913fSAlexey Kardashevskiy pnv_pci_setup_iommu_table(tbl, addr, tce_table_size, bus_offset, 2832aca6913fSAlexey Kardashevskiy page_shift); 2833bbb845c4SAlexey Kardashevskiy tbl->it_level_size = 1ULL << (level_shift - 3); 2834bbb845c4SAlexey Kardashevskiy tbl->it_indirect_levels = levels - 1; 28353ba3a73eSAlexey Kardashevskiy tbl->it_allocated_size = total_allocated; 2836aca6913fSAlexey Kardashevskiy 2837aca6913fSAlexey Kardashevskiy pr_devel("Created TCE table: ws=%08llx ts=%lx @%08llx\n", 2838aca6913fSAlexey Kardashevskiy window_size, tce_table_size, bus_offset); 2839aca6913fSAlexey Kardashevskiy 2840aca6913fSAlexey Kardashevskiy return 0; 2841aca6913fSAlexey Kardashevskiy } 2842aca6913fSAlexey Kardashevskiy 2843bbb845c4SAlexey Kardashevskiy static void pnv_pci_ioda2_table_do_free_pages(__be64 *addr, 2844bbb845c4SAlexey Kardashevskiy unsigned long size, unsigned level) 2845bbb845c4SAlexey Kardashevskiy { 2846bbb845c4SAlexey Kardashevskiy const unsigned long addr_ul = (unsigned long) addr & 2847bbb845c4SAlexey Kardashevskiy ~(TCE_PCI_READ | TCE_PCI_WRITE); 2848bbb845c4SAlexey Kardashevskiy 2849bbb845c4SAlexey Kardashevskiy if (level) { 2850bbb845c4SAlexey Kardashevskiy long i; 2851bbb845c4SAlexey Kardashevskiy u64 *tmp = (u64 *) addr_ul; 2852bbb845c4SAlexey Kardashevskiy 2853bbb845c4SAlexey Kardashevskiy for (i = 0; i < size; ++i) { 2854bbb845c4SAlexey Kardashevskiy unsigned long hpa = be64_to_cpu(tmp[i]); 2855bbb845c4SAlexey Kardashevskiy 2856bbb845c4SAlexey Kardashevskiy if (!(hpa & (TCE_PCI_READ | TCE_PCI_WRITE))) 2857bbb845c4SAlexey Kardashevskiy continue; 2858bbb845c4SAlexey Kardashevskiy 2859bbb845c4SAlexey Kardashevskiy pnv_pci_ioda2_table_do_free_pages(__va(hpa), size, 2860bbb845c4SAlexey Kardashevskiy level - 1); 2861bbb845c4SAlexey Kardashevskiy } 2862bbb845c4SAlexey Kardashevskiy } 2863bbb845c4SAlexey Kardashevskiy 2864bbb845c4SAlexey Kardashevskiy free_pages(addr_ul, get_order(size << 3)); 2865bbb845c4SAlexey Kardashevskiy } 2866bbb845c4SAlexey Kardashevskiy 2867aca6913fSAlexey Kardashevskiy static void pnv_pci_ioda2_table_free_pages(struct iommu_table *tbl) 2868aca6913fSAlexey Kardashevskiy { 2869bbb845c4SAlexey Kardashevskiy const unsigned long size = tbl->it_indirect_levels ? 2870bbb845c4SAlexey Kardashevskiy tbl->it_level_size : tbl->it_size; 2871bbb845c4SAlexey Kardashevskiy 2872aca6913fSAlexey Kardashevskiy if (!tbl->it_size) 2873aca6913fSAlexey Kardashevskiy return; 2874aca6913fSAlexey Kardashevskiy 2875bbb845c4SAlexey Kardashevskiy pnv_pci_ioda2_table_do_free_pages((__be64 *)tbl->it_base, size, 2876bbb845c4SAlexey Kardashevskiy tbl->it_indirect_levels); 2877aca6913fSAlexey Kardashevskiy } 2878aca6913fSAlexey Kardashevskiy 2879373f5657SGavin Shan static void pnv_pci_ioda2_setup_dma_pe(struct pnv_phb *phb, 2880373f5657SGavin Shan struct pnv_ioda_pe *pe) 2881373f5657SGavin Shan { 2882373f5657SGavin Shan int64_t rc; 2883373f5657SGavin Shan 2884ccd1c191SGavin Shan if (!pnv_pci_ioda_pe_dma_weight(pe)) 2885ccd1c191SGavin Shan return; 2886ccd1c191SGavin Shan 2887f87a8864SAlexey Kardashevskiy /* TVE #1 is selected by PCI address bit 59 */ 2888f87a8864SAlexey Kardashevskiy pe->tce_bypass_base = 1ull << 59; 2889f87a8864SAlexey Kardashevskiy 2890b348aa65SAlexey Kardashevskiy iommu_register_group(&pe->table_group, phb->hose->global_number, 2891b348aa65SAlexey Kardashevskiy pe->pe_number); 2892c5773822SAlexey Kardashevskiy 2893373f5657SGavin Shan /* The PE will reserve all possible 32-bits space */ 2894373f5657SGavin Shan pe_info(pe, "Setting up 32-bit TCE table at 0..%08x\n", 2895aca6913fSAlexey Kardashevskiy phb->ioda.m32_pci_base); 2896373f5657SGavin Shan 2897e5aad1e6SAlexey Kardashevskiy /* Setup linux iommu table */ 28984793d65dSAlexey Kardashevskiy pe->table_group.tce32_start = 0; 28994793d65dSAlexey Kardashevskiy pe->table_group.tce32_size = phb->ioda.m32_pci_base; 29004793d65dSAlexey Kardashevskiy pe->table_group.max_dynamic_windows_supported = 29014793d65dSAlexey Kardashevskiy IOMMU_TABLE_GROUP_MAX_TABLES; 29024793d65dSAlexey Kardashevskiy pe->table_group.max_levels = POWERNV_IOMMU_MAX_LEVELS; 29034793d65dSAlexey Kardashevskiy pe->table_group.pgsizes = SZ_4K | SZ_64K | SZ_16M; 2904e5aad1e6SAlexey Kardashevskiy #ifdef CONFIG_IOMMU_API 2905e5aad1e6SAlexey Kardashevskiy pe->table_group.ops = &pnv_pci_ioda2_ops; 2906e5aad1e6SAlexey Kardashevskiy #endif 2907e5aad1e6SAlexey Kardashevskiy 290846d3e1e1SAlexey Kardashevskiy rc = pnv_pci_ioda2_setup_default_config(pe); 2909801846d1SGavin Shan if (rc) 291046d3e1e1SAlexey Kardashevskiy return; 291146d3e1e1SAlexey Kardashevskiy 291220f13b95SAlexey Kardashevskiy if (pe->flags & (PNV_IODA_PE_BUS | PNV_IODA_PE_BUS_ALL)) 2913db08e1d5SAlexey Kardashevskiy pnv_ioda_setup_bus_dma(pe, pe->pbus, true); 2914373f5657SGavin Shan } 2915373f5657SGavin Shan 2916184cd4a3SBenjamin Herrenschmidt #ifdef CONFIG_PCI_MSI 29174ee11c1aSSuresh Warrier int64_t pnv_opal_pci_msi_eoi(struct irq_chip *chip, unsigned int hw_irq) 2918137436c9SGavin Shan { 2919137436c9SGavin Shan struct pnv_phb *phb = container_of(chip, struct pnv_phb, 2920137436c9SGavin Shan ioda.irq_chip); 2921137436c9SGavin Shan 29224ee11c1aSSuresh Warrier return opal_pci_msi_eoi(phb->opal_id, hw_irq); 29234ee11c1aSSuresh Warrier } 29244ee11c1aSSuresh Warrier 29254ee11c1aSSuresh Warrier static void pnv_ioda2_msi_eoi(struct irq_data *d) 29264ee11c1aSSuresh Warrier { 29274ee11c1aSSuresh Warrier int64_t rc; 29284ee11c1aSSuresh Warrier unsigned int hw_irq = (unsigned int)irqd_to_hwirq(d); 29294ee11c1aSSuresh Warrier struct irq_chip *chip = irq_data_get_irq_chip(d); 29304ee11c1aSSuresh Warrier 29314ee11c1aSSuresh Warrier rc = pnv_opal_pci_msi_eoi(chip, hw_irq); 2932137436c9SGavin Shan WARN_ON_ONCE(rc); 2933137436c9SGavin Shan 2934137436c9SGavin Shan icp_native_eoi(d); 2935137436c9SGavin Shan } 2936137436c9SGavin Shan 2937fd9a1c26SIan Munsie 2938f456834aSIan Munsie void pnv_set_msi_irq_chip(struct pnv_phb *phb, unsigned int virq) 2939fd9a1c26SIan Munsie { 2940fd9a1c26SIan Munsie struct irq_data *idata; 2941fd9a1c26SIan Munsie struct irq_chip *ichip; 2942fd9a1c26SIan Munsie 2943fb111334SBenjamin Herrenschmidt /* The MSI EOI OPAL call is only needed on PHB3 */ 2944fb111334SBenjamin Herrenschmidt if (phb->model != PNV_PHB_MODEL_PHB3) 2945fd9a1c26SIan Munsie return; 2946fd9a1c26SIan Munsie 2947fd9a1c26SIan Munsie if (!phb->ioda.irq_chip_init) { 2948fd9a1c26SIan Munsie /* 2949fd9a1c26SIan Munsie * First time we setup an MSI IRQ, we need to setup the 2950fd9a1c26SIan Munsie * corresponding IRQ chip to route correctly. 2951fd9a1c26SIan Munsie */ 2952fd9a1c26SIan Munsie idata = irq_get_irq_data(virq); 2953fd9a1c26SIan Munsie ichip = irq_data_get_irq_chip(idata); 2954fd9a1c26SIan Munsie phb->ioda.irq_chip_init = 1; 2955fd9a1c26SIan Munsie phb->ioda.irq_chip = *ichip; 2956fd9a1c26SIan Munsie phb->ioda.irq_chip.irq_eoi = pnv_ioda2_msi_eoi; 2957fd9a1c26SIan Munsie } 2958fd9a1c26SIan Munsie irq_set_chip(virq, &phb->ioda.irq_chip); 2959fd9a1c26SIan Munsie } 2960fd9a1c26SIan Munsie 29614ee11c1aSSuresh Warrier /* 29624ee11c1aSSuresh Warrier * Returns true iff chip is something that we could call 29634ee11c1aSSuresh Warrier * pnv_opal_pci_msi_eoi for. 29644ee11c1aSSuresh Warrier */ 29654ee11c1aSSuresh Warrier bool is_pnv_opal_msi(struct irq_chip *chip) 29664ee11c1aSSuresh Warrier { 29674ee11c1aSSuresh Warrier return chip->irq_eoi == pnv_ioda2_msi_eoi; 29684ee11c1aSSuresh Warrier } 29694ee11c1aSSuresh Warrier EXPORT_SYMBOL_GPL(is_pnv_opal_msi); 29704ee11c1aSSuresh Warrier 2971184cd4a3SBenjamin Herrenschmidt static int pnv_pci_ioda_msi_setup(struct pnv_phb *phb, struct pci_dev *dev, 2972137436c9SGavin Shan unsigned int hwirq, unsigned int virq, 2973137436c9SGavin Shan unsigned int is_64, struct msi_msg *msg) 2974184cd4a3SBenjamin Herrenschmidt { 2975184cd4a3SBenjamin Herrenschmidt struct pnv_ioda_pe *pe = pnv_ioda_get_pe(dev); 2976184cd4a3SBenjamin Herrenschmidt unsigned int xive_num = hwirq - phb->msi_base; 29773a1a4661SBenjamin Herrenschmidt __be32 data; 2978184cd4a3SBenjamin Herrenschmidt int rc; 2979184cd4a3SBenjamin Herrenschmidt 2980184cd4a3SBenjamin Herrenschmidt /* No PE assigned ? bail out ... no MSI for you ! */ 2981184cd4a3SBenjamin Herrenschmidt if (pe == NULL) 2982184cd4a3SBenjamin Herrenschmidt return -ENXIO; 2983184cd4a3SBenjamin Herrenschmidt 2984184cd4a3SBenjamin Herrenschmidt /* Check if we have an MVE */ 2985184cd4a3SBenjamin Herrenschmidt if (pe->mve_number < 0) 2986184cd4a3SBenjamin Herrenschmidt return -ENXIO; 2987184cd4a3SBenjamin Herrenschmidt 2988b72c1f65SBenjamin Herrenschmidt /* Force 32-bit MSI on some broken devices */ 298936074381SBenjamin Herrenschmidt if (dev->no_64bit_msi) 2990b72c1f65SBenjamin Herrenschmidt is_64 = 0; 2991b72c1f65SBenjamin Herrenschmidt 2992184cd4a3SBenjamin Herrenschmidt /* Assign XIVE to PE */ 2993184cd4a3SBenjamin Herrenschmidt rc = opal_pci_set_xive_pe(phb->opal_id, pe->pe_number, xive_num); 2994184cd4a3SBenjamin Herrenschmidt if (rc) { 2995184cd4a3SBenjamin Herrenschmidt pr_warn("%s: OPAL error %d setting XIVE %d PE\n", 2996184cd4a3SBenjamin Herrenschmidt pci_name(dev), rc, xive_num); 2997184cd4a3SBenjamin Herrenschmidt return -EIO; 2998184cd4a3SBenjamin Herrenschmidt } 2999184cd4a3SBenjamin Herrenschmidt 3000184cd4a3SBenjamin Herrenschmidt if (is_64) { 30013a1a4661SBenjamin Herrenschmidt __be64 addr64; 30023a1a4661SBenjamin Herrenschmidt 3003184cd4a3SBenjamin Herrenschmidt rc = opal_get_msi_64(phb->opal_id, pe->mve_number, xive_num, 1, 3004184cd4a3SBenjamin Herrenschmidt &addr64, &data); 3005184cd4a3SBenjamin Herrenschmidt if (rc) { 3006184cd4a3SBenjamin Herrenschmidt pr_warn("%s: OPAL error %d getting 64-bit MSI data\n", 3007184cd4a3SBenjamin Herrenschmidt pci_name(dev), rc); 3008184cd4a3SBenjamin Herrenschmidt return -EIO; 3009184cd4a3SBenjamin Herrenschmidt } 30103a1a4661SBenjamin Herrenschmidt msg->address_hi = be64_to_cpu(addr64) >> 32; 30113a1a4661SBenjamin Herrenschmidt msg->address_lo = be64_to_cpu(addr64) & 0xfffffffful; 3012184cd4a3SBenjamin Herrenschmidt } else { 30133a1a4661SBenjamin Herrenschmidt __be32 addr32; 30143a1a4661SBenjamin Herrenschmidt 3015184cd4a3SBenjamin Herrenschmidt rc = opal_get_msi_32(phb->opal_id, pe->mve_number, xive_num, 1, 3016184cd4a3SBenjamin Herrenschmidt &addr32, &data); 3017184cd4a3SBenjamin Herrenschmidt if (rc) { 3018184cd4a3SBenjamin Herrenschmidt pr_warn("%s: OPAL error %d getting 32-bit MSI data\n", 3019184cd4a3SBenjamin Herrenschmidt pci_name(dev), rc); 3020184cd4a3SBenjamin Herrenschmidt return -EIO; 3021184cd4a3SBenjamin Herrenschmidt } 3022184cd4a3SBenjamin Herrenschmidt msg->address_hi = 0; 30233a1a4661SBenjamin Herrenschmidt msg->address_lo = be32_to_cpu(addr32); 3024184cd4a3SBenjamin Herrenschmidt } 30253a1a4661SBenjamin Herrenschmidt msg->data = be32_to_cpu(data); 3026184cd4a3SBenjamin Herrenschmidt 3027f456834aSIan Munsie pnv_set_msi_irq_chip(phb, virq); 3028137436c9SGavin Shan 3029184cd4a3SBenjamin Herrenschmidt pr_devel("%s: %s-bit MSI on hwirq %x (xive #%d)," 30301f52f176SRussell Currey " address=%x_%08x data=%x PE# %x\n", 3031184cd4a3SBenjamin Herrenschmidt pci_name(dev), is_64 ? "64" : "32", hwirq, xive_num, 3032184cd4a3SBenjamin Herrenschmidt msg->address_hi, msg->address_lo, data, pe->pe_number); 3033184cd4a3SBenjamin Herrenschmidt 3034184cd4a3SBenjamin Herrenschmidt return 0; 3035184cd4a3SBenjamin Herrenschmidt } 3036184cd4a3SBenjamin Herrenschmidt 3037184cd4a3SBenjamin Herrenschmidt static void pnv_pci_init_ioda_msis(struct pnv_phb *phb) 3038184cd4a3SBenjamin Herrenschmidt { 3039fb1b55d6SGavin Shan unsigned int count; 3040184cd4a3SBenjamin Herrenschmidt const __be32 *prop = of_get_property(phb->hose->dn, 3041184cd4a3SBenjamin Herrenschmidt "ibm,opal-msi-ranges", NULL); 3042184cd4a3SBenjamin Herrenschmidt if (!prop) { 3043184cd4a3SBenjamin Herrenschmidt /* BML Fallback */ 3044184cd4a3SBenjamin Herrenschmidt prop = of_get_property(phb->hose->dn, "msi-ranges", NULL); 3045184cd4a3SBenjamin Herrenschmidt } 3046184cd4a3SBenjamin Herrenschmidt if (!prop) 3047184cd4a3SBenjamin Herrenschmidt return; 3048184cd4a3SBenjamin Herrenschmidt 3049184cd4a3SBenjamin Herrenschmidt phb->msi_base = be32_to_cpup(prop); 3050fb1b55d6SGavin Shan count = be32_to_cpup(prop + 1); 3051fb1b55d6SGavin Shan if (msi_bitmap_alloc(&phb->msi_bmp, count, phb->hose->dn)) { 3052184cd4a3SBenjamin Herrenschmidt pr_err("PCI %d: Failed to allocate MSI bitmap !\n", 3053184cd4a3SBenjamin Herrenschmidt phb->hose->global_number); 3054184cd4a3SBenjamin Herrenschmidt return; 3055184cd4a3SBenjamin Herrenschmidt } 3056fb1b55d6SGavin Shan 3057184cd4a3SBenjamin Herrenschmidt phb->msi_setup = pnv_pci_ioda_msi_setup; 3058184cd4a3SBenjamin Herrenschmidt phb->msi32_support = 1; 3059184cd4a3SBenjamin Herrenschmidt pr_info(" Allocated bitmap for %d MSIs (base IRQ 0x%x)\n", 3060fb1b55d6SGavin Shan count, phb->msi_base); 3061184cd4a3SBenjamin Herrenschmidt } 3062184cd4a3SBenjamin Herrenschmidt #else 3063184cd4a3SBenjamin Herrenschmidt static void pnv_pci_init_ioda_msis(struct pnv_phb *phb) { } 3064184cd4a3SBenjamin Herrenschmidt #endif /* CONFIG_PCI_MSI */ 3065184cd4a3SBenjamin Herrenschmidt 30666e628c7dSWei Yang #ifdef CONFIG_PCI_IOV 30676e628c7dSWei Yang static void pnv_pci_ioda_fixup_iov_resources(struct pci_dev *pdev) 30686e628c7dSWei Yang { 3069f2dd0afeSWei Yang struct pci_controller *hose = pci_bus_to_host(pdev->bus); 3070f2dd0afeSWei Yang struct pnv_phb *phb = hose->private_data; 3071f2dd0afeSWei Yang const resource_size_t gate = phb->ioda.m64_segsize >> 2; 30726e628c7dSWei Yang struct resource *res; 30736e628c7dSWei Yang int i; 3074dfcc8d45SWei Yang resource_size_t size, total_vf_bar_sz; 30756e628c7dSWei Yang struct pci_dn *pdn; 30765b88ec22SWei Yang int mul, total_vfs; 30776e628c7dSWei Yang 30786e628c7dSWei Yang if (!pdev->is_physfn || pdev->is_added) 30796e628c7dSWei Yang return; 30806e628c7dSWei Yang 30816e628c7dSWei Yang pdn = pci_get_pdn(pdev); 30826e628c7dSWei Yang pdn->vfs_expanded = 0; 3083ee8222feSWei Yang pdn->m64_single_mode = false; 30846e628c7dSWei Yang 30855b88ec22SWei Yang total_vfs = pci_sriov_get_totalvfs(pdev); 308692b8f137SGavin Shan mul = phb->ioda.total_pe_num; 3087dfcc8d45SWei Yang total_vf_bar_sz = 0; 30885b88ec22SWei Yang 30895b88ec22SWei Yang for (i = 0; i < PCI_SRIOV_NUM_BARS; i++) { 30905b88ec22SWei Yang res = &pdev->resource[i + PCI_IOV_RESOURCES]; 30915b88ec22SWei Yang if (!res->flags || res->parent) 30925b88ec22SWei Yang continue; 3093b79331a5SRussell Currey if (!pnv_pci_is_m64_flags(res->flags)) { 3094b0331854SWei Yang dev_warn(&pdev->dev, "Don't support SR-IOV with" 3095b0331854SWei Yang " non M64 VF BAR%d: %pR. \n", 30965b88ec22SWei Yang i, res); 3097b0331854SWei Yang goto truncate_iov; 30985b88ec22SWei Yang } 30995b88ec22SWei Yang 3100dfcc8d45SWei Yang total_vf_bar_sz += pci_iov_resource_size(pdev, 3101dfcc8d45SWei Yang i + PCI_IOV_RESOURCES); 31025b88ec22SWei Yang 3103f2dd0afeSWei Yang /* 3104f2dd0afeSWei Yang * If bigger than quarter of M64 segment size, just round up 3105f2dd0afeSWei Yang * power of two. 3106f2dd0afeSWei Yang * 3107f2dd0afeSWei Yang * Generally, one M64 BAR maps one IOV BAR. To avoid conflict 3108f2dd0afeSWei Yang * with other devices, IOV BAR size is expanded to be 3109f2dd0afeSWei Yang * (total_pe * VF_BAR_size). When VF_BAR_size is half of M64 3110f2dd0afeSWei Yang * segment size , the expanded size would equal to half of the 3111f2dd0afeSWei Yang * whole M64 space size, which will exhaust the M64 Space and 3112f2dd0afeSWei Yang * limit the system flexibility. This is a design decision to 3113f2dd0afeSWei Yang * set the boundary to quarter of the M64 segment size. 3114f2dd0afeSWei Yang */ 3115dfcc8d45SWei Yang if (total_vf_bar_sz > gate) { 31165b88ec22SWei Yang mul = roundup_pow_of_two(total_vfs); 3117dfcc8d45SWei Yang dev_info(&pdev->dev, 3118dfcc8d45SWei Yang "VF BAR Total IOV size %llx > %llx, roundup to %d VFs\n", 3119dfcc8d45SWei Yang total_vf_bar_sz, gate, mul); 3120ee8222feSWei Yang pdn->m64_single_mode = true; 31215b88ec22SWei Yang break; 31225b88ec22SWei Yang } 31235b88ec22SWei Yang } 31245b88ec22SWei Yang 31256e628c7dSWei Yang for (i = 0; i < PCI_SRIOV_NUM_BARS; i++) { 31266e628c7dSWei Yang res = &pdev->resource[i + PCI_IOV_RESOURCES]; 31276e628c7dSWei Yang if (!res->flags || res->parent) 31286e628c7dSWei Yang continue; 31296e628c7dSWei Yang 31306e628c7dSWei Yang size = pci_iov_resource_size(pdev, i + PCI_IOV_RESOURCES); 3131ee8222feSWei Yang /* 3132ee8222feSWei Yang * On PHB3, the minimum size alignment of M64 BAR in single 3133ee8222feSWei Yang * mode is 32MB. 3134ee8222feSWei Yang */ 3135ee8222feSWei Yang if (pdn->m64_single_mode && (size < SZ_32M)) 3136ee8222feSWei Yang goto truncate_iov; 3137ee8222feSWei Yang dev_dbg(&pdev->dev, " Fixing VF BAR%d: %pR to\n", i, res); 31385b88ec22SWei Yang res->end = res->start + size * mul - 1; 31396e628c7dSWei Yang dev_dbg(&pdev->dev, " %pR\n", res); 31406e628c7dSWei Yang dev_info(&pdev->dev, "VF BAR%d: %pR (expanded to %d VFs for PE alignment)", 31415b88ec22SWei Yang i, res, mul); 31426e628c7dSWei Yang } 31435b88ec22SWei Yang pdn->vfs_expanded = mul; 3144b0331854SWei Yang 3145b0331854SWei Yang return; 3146b0331854SWei Yang 3147b0331854SWei Yang truncate_iov: 3148b0331854SWei Yang /* To save MMIO space, IOV BAR is truncated. */ 3149b0331854SWei Yang for (i = 0; i < PCI_SRIOV_NUM_BARS; i++) { 3150b0331854SWei Yang res = &pdev->resource[i + PCI_IOV_RESOURCES]; 3151b0331854SWei Yang res->flags = 0; 3152b0331854SWei Yang res->end = res->start - 1; 3153b0331854SWei Yang } 31546e628c7dSWei Yang } 31556e628c7dSWei Yang #endif /* CONFIG_PCI_IOV */ 31566e628c7dSWei Yang 315723e79425SGavin Shan static void pnv_ioda_setup_pe_res(struct pnv_ioda_pe *pe, 315823e79425SGavin Shan struct resource *res) 315911685becSGavin Shan { 316023e79425SGavin Shan struct pnv_phb *phb = pe->phb; 316111685becSGavin Shan struct pci_bus_region region; 316223e79425SGavin Shan int index; 316323e79425SGavin Shan int64_t rc; 316411685becSGavin Shan 316523e79425SGavin Shan if (!res || !res->flags || res->start > res->end) 316623e79425SGavin Shan return; 316711685becSGavin Shan 316811685becSGavin Shan if (res->flags & IORESOURCE_IO) { 316911685becSGavin Shan region.start = res->start - phb->ioda.io_pci_base; 317011685becSGavin Shan region.end = res->end - phb->ioda.io_pci_base; 317111685becSGavin Shan index = region.start / phb->ioda.io_segsize; 317211685becSGavin Shan 317392b8f137SGavin Shan while (index < phb->ioda.total_pe_num && 317411685becSGavin Shan region.start <= region.end) { 317511685becSGavin Shan phb->ioda.io_segmap[index] = pe->pe_number; 317611685becSGavin Shan rc = opal_pci_map_pe_mmio_window(phb->opal_id, 317711685becSGavin Shan pe->pe_number, OPAL_IO_WINDOW_TYPE, 0, index); 317811685becSGavin Shan if (rc != OPAL_SUCCESS) { 31791f52f176SRussell Currey pr_err("%s: Error %lld mapping IO segment#%d to PE#%x\n", 318011685becSGavin Shan __func__, rc, index, pe->pe_number); 318111685becSGavin Shan break; 318211685becSGavin Shan } 318311685becSGavin Shan 318411685becSGavin Shan region.start += phb->ioda.io_segsize; 318511685becSGavin Shan index++; 318611685becSGavin Shan } 3187027fa02fSGavin Shan } else if ((res->flags & IORESOURCE_MEM) && 31885958d19aSBenjamin Herrenschmidt !pnv_pci_is_m64(phb, res)) { 318911685becSGavin Shan region.start = res->start - 319023e79425SGavin Shan phb->hose->mem_offset[0] - 319111685becSGavin Shan phb->ioda.m32_pci_base; 319211685becSGavin Shan region.end = res->end - 319323e79425SGavin Shan phb->hose->mem_offset[0] - 319411685becSGavin Shan phb->ioda.m32_pci_base; 319511685becSGavin Shan index = region.start / phb->ioda.m32_segsize; 319611685becSGavin Shan 319792b8f137SGavin Shan while (index < phb->ioda.total_pe_num && 319811685becSGavin Shan region.start <= region.end) { 319911685becSGavin Shan phb->ioda.m32_segmap[index] = pe->pe_number; 320011685becSGavin Shan rc = opal_pci_map_pe_mmio_window(phb->opal_id, 320111685becSGavin Shan pe->pe_number, OPAL_M32_WINDOW_TYPE, 0, index); 320211685becSGavin Shan if (rc != OPAL_SUCCESS) { 32031f52f176SRussell Currey pr_err("%s: Error %lld mapping M32 segment#%d to PE#%x", 320411685becSGavin Shan __func__, rc, index, pe->pe_number); 320511685becSGavin Shan break; 320611685becSGavin Shan } 320711685becSGavin Shan 320811685becSGavin Shan region.start += phb->ioda.m32_segsize; 320911685becSGavin Shan index++; 321011685becSGavin Shan } 321111685becSGavin Shan } 321211685becSGavin Shan } 321323e79425SGavin Shan 321423e79425SGavin Shan /* 321523e79425SGavin Shan * This function is supposed to be called on basis of PE from top 321623e79425SGavin Shan * to bottom style. So the the I/O or MMIO segment assigned to 321703671057SMasahiro Yamada * parent PE could be overridden by its child PEs if necessary. 321823e79425SGavin Shan */ 321923e79425SGavin Shan static void pnv_ioda_setup_pe_seg(struct pnv_ioda_pe *pe) 322023e79425SGavin Shan { 322169d733e7SGavin Shan struct pci_dev *pdev; 322223e79425SGavin Shan int i; 322323e79425SGavin Shan 322423e79425SGavin Shan /* 322523e79425SGavin Shan * NOTE: We only care PCI bus based PE for now. For PCI 322623e79425SGavin Shan * device based PE, for example SRIOV sensitive VF should 322723e79425SGavin Shan * be figured out later. 322823e79425SGavin Shan */ 322923e79425SGavin Shan BUG_ON(!(pe->flags & (PNV_IODA_PE_BUS | PNV_IODA_PE_BUS_ALL))); 323023e79425SGavin Shan 323169d733e7SGavin Shan list_for_each_entry(pdev, &pe->pbus->devices, bus_list) { 323269d733e7SGavin Shan for (i = 0; i <= PCI_ROM_RESOURCE; i++) 323369d733e7SGavin Shan pnv_ioda_setup_pe_res(pe, &pdev->resource[i]); 323469d733e7SGavin Shan 323569d733e7SGavin Shan /* 323669d733e7SGavin Shan * If the PE contains all subordinate PCI buses, the 323769d733e7SGavin Shan * windows of the child bridges should be mapped to 323869d733e7SGavin Shan * the PE as well. 323969d733e7SGavin Shan */ 324069d733e7SGavin Shan if (!(pe->flags & PNV_IODA_PE_BUS_ALL) || !pci_is_bridge(pdev)) 324169d733e7SGavin Shan continue; 324269d733e7SGavin Shan for (i = 0; i < PCI_BRIDGE_RESOURCE_NUM; i++) 324369d733e7SGavin Shan pnv_ioda_setup_pe_res(pe, 324469d733e7SGavin Shan &pdev->resource[PCI_BRIDGE_RESOURCES + i]); 324569d733e7SGavin Shan } 324611685becSGavin Shan } 324711685becSGavin Shan 324898b665daSRussell Currey #ifdef CONFIG_DEBUG_FS 324998b665daSRussell Currey static int pnv_pci_diag_data_set(void *data, u64 val) 325098b665daSRussell Currey { 325198b665daSRussell Currey struct pci_controller *hose; 325298b665daSRussell Currey struct pnv_phb *phb; 325398b665daSRussell Currey s64 ret; 325498b665daSRussell Currey 325598b665daSRussell Currey if (val != 1ULL) 325698b665daSRussell Currey return -EINVAL; 325798b665daSRussell Currey 325898b665daSRussell Currey hose = (struct pci_controller *)data; 325998b665daSRussell Currey if (!hose || !hose->private_data) 326098b665daSRussell Currey return -ENODEV; 326198b665daSRussell Currey 326298b665daSRussell Currey phb = hose->private_data; 326398b665daSRussell Currey 326498b665daSRussell Currey /* Retrieve the diag data from firmware */ 32655cb1f8fdSRussell Currey ret = opal_pci_get_phb_diag_data2(phb->opal_id, phb->diag_data, 32665cb1f8fdSRussell Currey phb->diag_data_size); 326798b665daSRussell Currey if (ret != OPAL_SUCCESS) 326898b665daSRussell Currey return -EIO; 326998b665daSRussell Currey 327098b665daSRussell Currey /* Print the diag data to the kernel log */ 32715cb1f8fdSRussell Currey pnv_pci_dump_phb_diag_data(phb->hose, phb->diag_data); 327298b665daSRussell Currey return 0; 327398b665daSRussell Currey } 327498b665daSRussell Currey 327598b665daSRussell Currey DEFINE_SIMPLE_ATTRIBUTE(pnv_pci_diag_data_fops, NULL, 327698b665daSRussell Currey pnv_pci_diag_data_set, "%llu\n"); 327798b665daSRussell Currey 327898b665daSRussell Currey #endif /* CONFIG_DEBUG_FS */ 327998b665daSRussell Currey 328037c367f2SGavin Shan static void pnv_pci_ioda_create_dbgfs(void) 328137c367f2SGavin Shan { 328237c367f2SGavin Shan #ifdef CONFIG_DEBUG_FS 328337c367f2SGavin Shan struct pci_controller *hose, *tmp; 328437c367f2SGavin Shan struct pnv_phb *phb; 328537c367f2SGavin Shan char name[16]; 328637c367f2SGavin Shan 328737c367f2SGavin Shan list_for_each_entry_safe(hose, tmp, &hose_list, list_node) { 328837c367f2SGavin Shan phb = hose->private_data; 328937c367f2SGavin Shan 3290ccd1c191SGavin Shan /* Notify initialization of PHB done */ 3291ccd1c191SGavin Shan phb->initialized = 1; 3292ccd1c191SGavin Shan 329337c367f2SGavin Shan sprintf(name, "PCI%04x", hose->global_number); 329437c367f2SGavin Shan phb->dbgfs = debugfs_create_dir(name, powerpc_debugfs_root); 329598b665daSRussell Currey if (!phb->dbgfs) { 3296f2c2cbccSJoe Perches pr_warn("%s: Error on creating debugfs on PHB#%x\n", 329737c367f2SGavin Shan __func__, hose->global_number); 329898b665daSRussell Currey continue; 329998b665daSRussell Currey } 330098b665daSRussell Currey 330198b665daSRussell Currey debugfs_create_file("dump_diag_regs", 0200, phb->dbgfs, hose, 330298b665daSRussell Currey &pnv_pci_diag_data_fops); 330337c367f2SGavin Shan } 330437c367f2SGavin Shan #endif /* CONFIG_DEBUG_FS */ 330537c367f2SGavin Shan } 330637c367f2SGavin Shan 3307cad5cef6SGreg Kroah-Hartman static void pnv_pci_ioda_fixup(void) 3308fb446ad0SGavin Shan { 3309fb446ad0SGavin Shan pnv_pci_ioda_setup_PEs(); 3310ccd1c191SGavin Shan pnv_pci_ioda_setup_iommu_api(); 331137c367f2SGavin Shan pnv_pci_ioda_create_dbgfs(); 331237c367f2SGavin Shan 3313e9cc17d4SGavin Shan #ifdef CONFIG_EEH 3314b9fde58dSBenjamin Herrenschmidt pnv_eeh_post_init(); 3315e9cc17d4SGavin Shan #endif 3316fb446ad0SGavin Shan } 3317fb446ad0SGavin Shan 3318271fd03aSGavin Shan /* 3319271fd03aSGavin Shan * Returns the alignment for I/O or memory windows for P2P 3320271fd03aSGavin Shan * bridges. That actually depends on how PEs are segmented. 3321271fd03aSGavin Shan * For now, we return I/O or M32 segment size for PE sensitive 3322271fd03aSGavin Shan * P2P bridges. Otherwise, the default values (4KiB for I/O, 3323271fd03aSGavin Shan * 1MiB for memory) will be returned. 3324271fd03aSGavin Shan * 3325271fd03aSGavin Shan * The current PCI bus might be put into one PE, which was 3326271fd03aSGavin Shan * create against the parent PCI bridge. For that case, we 3327271fd03aSGavin Shan * needn't enlarge the alignment so that we can save some 3328271fd03aSGavin Shan * resources. 3329271fd03aSGavin Shan */ 3330271fd03aSGavin Shan static resource_size_t pnv_pci_window_alignment(struct pci_bus *bus, 3331271fd03aSGavin Shan unsigned long type) 3332271fd03aSGavin Shan { 3333271fd03aSGavin Shan struct pci_dev *bridge; 3334271fd03aSGavin Shan struct pci_controller *hose = pci_bus_to_host(bus); 3335271fd03aSGavin Shan struct pnv_phb *phb = hose->private_data; 3336271fd03aSGavin Shan int num_pci_bridges = 0; 3337271fd03aSGavin Shan 3338271fd03aSGavin Shan bridge = bus->self; 3339271fd03aSGavin Shan while (bridge) { 3340271fd03aSGavin Shan if (pci_pcie_type(bridge) == PCI_EXP_TYPE_PCI_BRIDGE) { 3341271fd03aSGavin Shan num_pci_bridges++; 3342271fd03aSGavin Shan if (num_pci_bridges >= 2) 3343271fd03aSGavin Shan return 1; 3344271fd03aSGavin Shan } 3345271fd03aSGavin Shan 3346271fd03aSGavin Shan bridge = bridge->bus->self; 3347271fd03aSGavin Shan } 3348271fd03aSGavin Shan 33495958d19aSBenjamin Herrenschmidt /* 33505958d19aSBenjamin Herrenschmidt * We fall back to M32 if M64 isn't supported. We enforce the M64 33515958d19aSBenjamin Herrenschmidt * alignment for any 64-bit resource, PCIe doesn't care and 33525958d19aSBenjamin Herrenschmidt * bridges only do 64-bit prefetchable anyway. 33535958d19aSBenjamin Herrenschmidt */ 3354b79331a5SRussell Currey if (phb->ioda.m64_segsize && pnv_pci_is_m64_flags(type)) 3355262af557SGuo Chao return phb->ioda.m64_segsize; 3356271fd03aSGavin Shan if (type & IORESOURCE_MEM) 3357271fd03aSGavin Shan return phb->ioda.m32_segsize; 3358271fd03aSGavin Shan 3359271fd03aSGavin Shan return phb->ioda.io_segsize; 3360271fd03aSGavin Shan } 3361271fd03aSGavin Shan 336240e2a47eSGavin Shan /* 336340e2a47eSGavin Shan * We are updating root port or the upstream port of the 336440e2a47eSGavin Shan * bridge behind the root port with PHB's windows in order 336540e2a47eSGavin Shan * to accommodate the changes on required resources during 336640e2a47eSGavin Shan * PCI (slot) hotplug, which is connected to either root 336740e2a47eSGavin Shan * port or the downstream ports of PCIe switch behind the 336840e2a47eSGavin Shan * root port. 336940e2a47eSGavin Shan */ 337040e2a47eSGavin Shan static void pnv_pci_fixup_bridge_resources(struct pci_bus *bus, 337140e2a47eSGavin Shan unsigned long type) 337240e2a47eSGavin Shan { 337340e2a47eSGavin Shan struct pci_controller *hose = pci_bus_to_host(bus); 337440e2a47eSGavin Shan struct pnv_phb *phb = hose->private_data; 337540e2a47eSGavin Shan struct pci_dev *bridge = bus->self; 337640e2a47eSGavin Shan struct resource *r, *w; 337740e2a47eSGavin Shan bool msi_region = false; 337840e2a47eSGavin Shan int i; 337940e2a47eSGavin Shan 338040e2a47eSGavin Shan /* Check if we need apply fixup to the bridge's windows */ 338140e2a47eSGavin Shan if (!pci_is_root_bus(bridge->bus) && 338240e2a47eSGavin Shan !pci_is_root_bus(bridge->bus->self->bus)) 338340e2a47eSGavin Shan return; 338440e2a47eSGavin Shan 338540e2a47eSGavin Shan /* Fixup the resources */ 338640e2a47eSGavin Shan for (i = 0; i < PCI_BRIDGE_RESOURCE_NUM; i++) { 338740e2a47eSGavin Shan r = &bridge->resource[PCI_BRIDGE_RESOURCES + i]; 338840e2a47eSGavin Shan if (!r->flags || !r->parent) 338940e2a47eSGavin Shan continue; 339040e2a47eSGavin Shan 339140e2a47eSGavin Shan w = NULL; 339240e2a47eSGavin Shan if (r->flags & type & IORESOURCE_IO) 339340e2a47eSGavin Shan w = &hose->io_resource; 33945958d19aSBenjamin Herrenschmidt else if (pnv_pci_is_m64(phb, r) && 339540e2a47eSGavin Shan (type & IORESOURCE_PREFETCH) && 339640e2a47eSGavin Shan phb->ioda.m64_segsize) 339740e2a47eSGavin Shan w = &hose->mem_resources[1]; 339840e2a47eSGavin Shan else if (r->flags & type & IORESOURCE_MEM) { 339940e2a47eSGavin Shan w = &hose->mem_resources[0]; 340040e2a47eSGavin Shan msi_region = true; 340140e2a47eSGavin Shan } 340240e2a47eSGavin Shan 340340e2a47eSGavin Shan r->start = w->start; 340440e2a47eSGavin Shan r->end = w->end; 340540e2a47eSGavin Shan 340640e2a47eSGavin Shan /* The 64KB 32-bits MSI region shouldn't be included in 340740e2a47eSGavin Shan * the 32-bits bridge window. Otherwise, we can see strange 340840e2a47eSGavin Shan * issues. One of them is EEH error observed on Garrison. 340940e2a47eSGavin Shan * 341040e2a47eSGavin Shan * Exclude top 1MB region which is the minimal alignment of 341140e2a47eSGavin Shan * 32-bits bridge window. 341240e2a47eSGavin Shan */ 341340e2a47eSGavin Shan if (msi_region) { 341440e2a47eSGavin Shan r->end += 0x10000; 341540e2a47eSGavin Shan r->end -= 0x100000; 341640e2a47eSGavin Shan } 341740e2a47eSGavin Shan } 341840e2a47eSGavin Shan } 341940e2a47eSGavin Shan 3420ccd1c191SGavin Shan static void pnv_pci_setup_bridge(struct pci_bus *bus, unsigned long type) 3421ccd1c191SGavin Shan { 3422ccd1c191SGavin Shan struct pci_controller *hose = pci_bus_to_host(bus); 3423ccd1c191SGavin Shan struct pnv_phb *phb = hose->private_data; 3424ccd1c191SGavin Shan struct pci_dev *bridge = bus->self; 3425ccd1c191SGavin Shan struct pnv_ioda_pe *pe; 3426ccd1c191SGavin Shan bool all = (pci_pcie_type(bridge) == PCI_EXP_TYPE_PCI_BRIDGE); 3427ccd1c191SGavin Shan 342840e2a47eSGavin Shan /* Extend bridge's windows if necessary */ 342940e2a47eSGavin Shan pnv_pci_fixup_bridge_resources(bus, type); 343040e2a47eSGavin Shan 343163803c39SGavin Shan /* The PE for root bus should be realized before any one else */ 343263803c39SGavin Shan if (!phb->ioda.root_pe_populated) { 343363803c39SGavin Shan pe = pnv_ioda_setup_bus_PE(phb->hose->bus, false); 343463803c39SGavin Shan if (pe) { 343563803c39SGavin Shan phb->ioda.root_pe_idx = pe->pe_number; 343663803c39SGavin Shan phb->ioda.root_pe_populated = true; 343763803c39SGavin Shan } 343863803c39SGavin Shan } 343963803c39SGavin Shan 3440ccd1c191SGavin Shan /* Don't assign PE to PCI bus, which doesn't have subordinate devices */ 3441ccd1c191SGavin Shan if (list_empty(&bus->devices)) 3442ccd1c191SGavin Shan return; 3443ccd1c191SGavin Shan 3444ccd1c191SGavin Shan /* Reserve PEs according to used M64 resources */ 3445ccd1c191SGavin Shan if (phb->reserve_m64_pe) 3446ccd1c191SGavin Shan phb->reserve_m64_pe(bus, NULL, all); 3447ccd1c191SGavin Shan 3448ccd1c191SGavin Shan /* 3449ccd1c191SGavin Shan * Assign PE. We might run here because of partial hotplug. 3450ccd1c191SGavin Shan * For the case, we just pick up the existing PE and should 3451ccd1c191SGavin Shan * not allocate resources again. 3452ccd1c191SGavin Shan */ 3453ccd1c191SGavin Shan pe = pnv_ioda_setup_bus_PE(bus, all); 3454ccd1c191SGavin Shan if (!pe) 3455ccd1c191SGavin Shan return; 3456ccd1c191SGavin Shan 3457ccd1c191SGavin Shan pnv_ioda_setup_pe_seg(pe); 3458ccd1c191SGavin Shan switch (phb->type) { 3459ccd1c191SGavin Shan case PNV_PHB_IODA1: 3460ccd1c191SGavin Shan pnv_pci_ioda1_setup_dma_pe(phb, pe); 3461ccd1c191SGavin Shan break; 3462ccd1c191SGavin Shan case PNV_PHB_IODA2: 3463ccd1c191SGavin Shan pnv_pci_ioda2_setup_dma_pe(phb, pe); 3464ccd1c191SGavin Shan break; 3465ccd1c191SGavin Shan default: 34661f52f176SRussell Currey pr_warn("%s: No DMA for PHB#%x (type %d)\n", 3467ccd1c191SGavin Shan __func__, phb->hose->global_number, phb->type); 3468ccd1c191SGavin Shan } 3469ccd1c191SGavin Shan } 3470ccd1c191SGavin Shan 347138274637SYongji Xie static resource_size_t pnv_pci_default_alignment(void) 347238274637SYongji Xie { 347338274637SYongji Xie return PAGE_SIZE; 347438274637SYongji Xie } 347538274637SYongji Xie 34765350ab3fSWei Yang #ifdef CONFIG_PCI_IOV 34775350ab3fSWei Yang static resource_size_t pnv_pci_iov_resource_alignment(struct pci_dev *pdev, 34785350ab3fSWei Yang int resno) 34795350ab3fSWei Yang { 3480ee8222feSWei Yang struct pci_controller *hose = pci_bus_to_host(pdev->bus); 3481ee8222feSWei Yang struct pnv_phb *phb = hose->private_data; 34825350ab3fSWei Yang struct pci_dn *pdn = pci_get_pdn(pdev); 34837fbe7a93SWei Yang resource_size_t align; 34845350ab3fSWei Yang 34857fbe7a93SWei Yang /* 34867fbe7a93SWei Yang * On PowerNV platform, IOV BAR is mapped by M64 BAR to enable the 34877fbe7a93SWei Yang * SR-IOV. While from hardware perspective, the range mapped by M64 34887fbe7a93SWei Yang * BAR should be size aligned. 34897fbe7a93SWei Yang * 3490ee8222feSWei Yang * When IOV BAR is mapped with M64 BAR in Single PE mode, the extra 3491ee8222feSWei Yang * powernv-specific hardware restriction is gone. But if just use the 3492ee8222feSWei Yang * VF BAR size as the alignment, PF BAR / VF BAR may be allocated with 3493ee8222feSWei Yang * in one segment of M64 #15, which introduces the PE conflict between 3494ee8222feSWei Yang * PF and VF. Based on this, the minimum alignment of an IOV BAR is 3495ee8222feSWei Yang * m64_segsize. 3496ee8222feSWei Yang * 34977fbe7a93SWei Yang * This function returns the total IOV BAR size if M64 BAR is in 34987fbe7a93SWei Yang * Shared PE mode or just VF BAR size if not. 3499ee8222feSWei Yang * If the M64 BAR is in Single PE mode, return the VF BAR size or 3500ee8222feSWei Yang * M64 segment size if IOV BAR size is less. 35017fbe7a93SWei Yang */ 35025350ab3fSWei Yang align = pci_iov_resource_size(pdev, resno); 35037fbe7a93SWei Yang if (!pdn->vfs_expanded) 35045350ab3fSWei Yang return align; 3505ee8222feSWei Yang if (pdn->m64_single_mode) 3506ee8222feSWei Yang return max(align, (resource_size_t)phb->ioda.m64_segsize); 35077fbe7a93SWei Yang 35087fbe7a93SWei Yang return pdn->vfs_expanded * align; 35095350ab3fSWei Yang } 35105350ab3fSWei Yang #endif /* CONFIG_PCI_IOV */ 35115350ab3fSWei Yang 3512184cd4a3SBenjamin Herrenschmidt /* Prevent enabling devices for which we couldn't properly 3513184cd4a3SBenjamin Herrenschmidt * assign a PE 3514184cd4a3SBenjamin Herrenschmidt */ 35154361b034SIan Munsie bool pnv_pci_enable_device_hook(struct pci_dev *dev) 3516184cd4a3SBenjamin Herrenschmidt { 3517db1266c8SGavin Shan struct pci_controller *hose = pci_bus_to_host(dev->bus); 3518db1266c8SGavin Shan struct pnv_phb *phb = hose->private_data; 3519db1266c8SGavin Shan struct pci_dn *pdn; 3520184cd4a3SBenjamin Herrenschmidt 3521db1266c8SGavin Shan /* The function is probably called while the PEs have 3522db1266c8SGavin Shan * not be created yet. For example, resource reassignment 3523db1266c8SGavin Shan * during PCI probe period. We just skip the check if 3524db1266c8SGavin Shan * PEs isn't ready. 3525db1266c8SGavin Shan */ 3526db1266c8SGavin Shan if (!phb->initialized) 3527c88c2a18SDaniel Axtens return true; 3528db1266c8SGavin Shan 3529b72c1f65SBenjamin Herrenschmidt pdn = pci_get_pdn(dev); 3530184cd4a3SBenjamin Herrenschmidt if (!pdn || pdn->pe_number == IODA_INVALID_PE) 3531c88c2a18SDaniel Axtens return false; 3532db1266c8SGavin Shan 3533c88c2a18SDaniel Axtens return true; 3534184cd4a3SBenjamin Herrenschmidt } 3535184cd4a3SBenjamin Herrenschmidt 3536c5f7700bSGavin Shan static long pnv_pci_ioda1_unset_window(struct iommu_table_group *table_group, 3537c5f7700bSGavin Shan int num) 3538c5f7700bSGavin Shan { 3539c5f7700bSGavin Shan struct pnv_ioda_pe *pe = container_of(table_group, 3540c5f7700bSGavin Shan struct pnv_ioda_pe, table_group); 3541c5f7700bSGavin Shan struct pnv_phb *phb = pe->phb; 3542c5f7700bSGavin Shan unsigned int idx; 3543c5f7700bSGavin Shan long rc; 3544c5f7700bSGavin Shan 3545c5f7700bSGavin Shan pe_info(pe, "Removing DMA window #%d\n", num); 3546c5f7700bSGavin Shan for (idx = 0; idx < phb->ioda.dma32_count; idx++) { 3547c5f7700bSGavin Shan if (phb->ioda.dma32_segmap[idx] != pe->pe_number) 3548c5f7700bSGavin Shan continue; 3549c5f7700bSGavin Shan 3550c5f7700bSGavin Shan rc = opal_pci_map_pe_dma_window(phb->opal_id, pe->pe_number, 3551c5f7700bSGavin Shan idx, 0, 0ul, 0ul, 0ul); 3552c5f7700bSGavin Shan if (rc != OPAL_SUCCESS) { 3553c5f7700bSGavin Shan pe_warn(pe, "Failure %ld unmapping DMA32 segment#%d\n", 3554c5f7700bSGavin Shan rc, idx); 3555c5f7700bSGavin Shan return rc; 3556c5f7700bSGavin Shan } 3557c5f7700bSGavin Shan 3558c5f7700bSGavin Shan phb->ioda.dma32_segmap[idx] = IODA_INVALID_PE; 3559c5f7700bSGavin Shan } 3560c5f7700bSGavin Shan 3561c5f7700bSGavin Shan pnv_pci_unlink_table_and_group(table_group->tables[num], table_group); 3562c5f7700bSGavin Shan return OPAL_SUCCESS; 3563c5f7700bSGavin Shan } 3564c5f7700bSGavin Shan 3565c5f7700bSGavin Shan static void pnv_pci_ioda1_release_pe_dma(struct pnv_ioda_pe *pe) 3566c5f7700bSGavin Shan { 3567c5f7700bSGavin Shan unsigned int weight = pnv_pci_ioda_pe_dma_weight(pe); 3568c5f7700bSGavin Shan struct iommu_table *tbl = pe->table_group.tables[0]; 3569c5f7700bSGavin Shan int64_t rc; 3570c5f7700bSGavin Shan 3571c5f7700bSGavin Shan if (!weight) 3572c5f7700bSGavin Shan return; 3573c5f7700bSGavin Shan 3574c5f7700bSGavin Shan rc = pnv_pci_ioda1_unset_window(&pe->table_group, 0); 3575c5f7700bSGavin Shan if (rc != OPAL_SUCCESS) 3576c5f7700bSGavin Shan return; 3577c5f7700bSGavin Shan 3578a34ab7c3SBenjamin Herrenschmidt pnv_pci_p7ioc_tce_invalidate(tbl, tbl->it_offset, tbl->it_size, false); 3579c5f7700bSGavin Shan if (pe->table_group.group) { 3580c5f7700bSGavin Shan iommu_group_put(pe->table_group.group); 3581c5f7700bSGavin Shan WARN_ON(pe->table_group.group); 3582c5f7700bSGavin Shan } 3583c5f7700bSGavin Shan 3584c5f7700bSGavin Shan free_pages(tbl->it_base, get_order(tbl->it_size << 3)); 3585e5afdf9dSAlexey Kardashevskiy iommu_tce_table_put(tbl); 3586c5f7700bSGavin Shan } 3587c5f7700bSGavin Shan 3588c5f7700bSGavin Shan static void pnv_pci_ioda2_release_pe_dma(struct pnv_ioda_pe *pe) 3589c5f7700bSGavin Shan { 3590c5f7700bSGavin Shan struct iommu_table *tbl = pe->table_group.tables[0]; 3591c5f7700bSGavin Shan unsigned int weight = pnv_pci_ioda_pe_dma_weight(pe); 3592c5f7700bSGavin Shan #ifdef CONFIG_IOMMU_API 3593c5f7700bSGavin Shan int64_t rc; 3594c5f7700bSGavin Shan #endif 3595c5f7700bSGavin Shan 3596c5f7700bSGavin Shan if (!weight) 3597c5f7700bSGavin Shan return; 3598c5f7700bSGavin Shan 3599c5f7700bSGavin Shan #ifdef CONFIG_IOMMU_API 3600c5f7700bSGavin Shan rc = pnv_pci_ioda2_unset_window(&pe->table_group, 0); 3601c5f7700bSGavin Shan if (rc) 3602c5f7700bSGavin Shan pe_warn(pe, "OPAL error %ld release DMA window\n", rc); 3603c5f7700bSGavin Shan #endif 3604c5f7700bSGavin Shan 3605c5f7700bSGavin Shan pnv_pci_ioda2_set_bypass(pe, false); 3606c5f7700bSGavin Shan if (pe->table_group.group) { 3607c5f7700bSGavin Shan iommu_group_put(pe->table_group.group); 3608c5f7700bSGavin Shan WARN_ON(pe->table_group.group); 3609c5f7700bSGavin Shan } 3610c5f7700bSGavin Shan 3611c5f7700bSGavin Shan pnv_pci_ioda2_table_free_pages(tbl); 3612e5afdf9dSAlexey Kardashevskiy iommu_tce_table_put(tbl); 3613c5f7700bSGavin Shan } 3614c5f7700bSGavin Shan 3615c5f7700bSGavin Shan static void pnv_ioda_free_pe_seg(struct pnv_ioda_pe *pe, 3616c5f7700bSGavin Shan unsigned short win, 3617c5f7700bSGavin Shan unsigned int *map) 3618c5f7700bSGavin Shan { 3619c5f7700bSGavin Shan struct pnv_phb *phb = pe->phb; 3620c5f7700bSGavin Shan int idx; 3621c5f7700bSGavin Shan int64_t rc; 3622c5f7700bSGavin Shan 3623c5f7700bSGavin Shan for (idx = 0; idx < phb->ioda.total_pe_num; idx++) { 3624c5f7700bSGavin Shan if (map[idx] != pe->pe_number) 3625c5f7700bSGavin Shan continue; 3626c5f7700bSGavin Shan 3627c5f7700bSGavin Shan if (win == OPAL_M64_WINDOW_TYPE) 3628c5f7700bSGavin Shan rc = opal_pci_map_pe_mmio_window(phb->opal_id, 3629c5f7700bSGavin Shan phb->ioda.reserved_pe_idx, win, 3630c5f7700bSGavin Shan idx / PNV_IODA1_M64_SEGS, 3631c5f7700bSGavin Shan idx % PNV_IODA1_M64_SEGS); 3632c5f7700bSGavin Shan else 3633c5f7700bSGavin Shan rc = opal_pci_map_pe_mmio_window(phb->opal_id, 3634c5f7700bSGavin Shan phb->ioda.reserved_pe_idx, win, 0, idx); 3635c5f7700bSGavin Shan 3636c5f7700bSGavin Shan if (rc != OPAL_SUCCESS) 3637c5f7700bSGavin Shan pe_warn(pe, "Error %ld unmapping (%d) segment#%d\n", 3638c5f7700bSGavin Shan rc, win, idx); 3639c5f7700bSGavin Shan 3640c5f7700bSGavin Shan map[idx] = IODA_INVALID_PE; 3641c5f7700bSGavin Shan } 3642c5f7700bSGavin Shan } 3643c5f7700bSGavin Shan 3644c5f7700bSGavin Shan static void pnv_ioda_release_pe_seg(struct pnv_ioda_pe *pe) 3645c5f7700bSGavin Shan { 3646c5f7700bSGavin Shan struct pnv_phb *phb = pe->phb; 3647c5f7700bSGavin Shan 3648c5f7700bSGavin Shan if (phb->type == PNV_PHB_IODA1) { 3649c5f7700bSGavin Shan pnv_ioda_free_pe_seg(pe, OPAL_IO_WINDOW_TYPE, 3650c5f7700bSGavin Shan phb->ioda.io_segmap); 3651c5f7700bSGavin Shan pnv_ioda_free_pe_seg(pe, OPAL_M32_WINDOW_TYPE, 3652c5f7700bSGavin Shan phb->ioda.m32_segmap); 3653c5f7700bSGavin Shan pnv_ioda_free_pe_seg(pe, OPAL_M64_WINDOW_TYPE, 3654c5f7700bSGavin Shan phb->ioda.m64_segmap); 3655c5f7700bSGavin Shan } else if (phb->type == PNV_PHB_IODA2) { 3656c5f7700bSGavin Shan pnv_ioda_free_pe_seg(pe, OPAL_M32_WINDOW_TYPE, 3657c5f7700bSGavin Shan phb->ioda.m32_segmap); 3658c5f7700bSGavin Shan } 3659c5f7700bSGavin Shan } 3660c5f7700bSGavin Shan 3661c5f7700bSGavin Shan static void pnv_ioda_release_pe(struct pnv_ioda_pe *pe) 3662c5f7700bSGavin Shan { 3663c5f7700bSGavin Shan struct pnv_phb *phb = pe->phb; 3664c5f7700bSGavin Shan struct pnv_ioda_pe *slave, *tmp; 3665c5f7700bSGavin Shan 3666c5f7700bSGavin Shan list_del(&pe->list); 3667c5f7700bSGavin Shan switch (phb->type) { 3668c5f7700bSGavin Shan case PNV_PHB_IODA1: 3669c5f7700bSGavin Shan pnv_pci_ioda1_release_pe_dma(pe); 3670c5f7700bSGavin Shan break; 3671c5f7700bSGavin Shan case PNV_PHB_IODA2: 3672c5f7700bSGavin Shan pnv_pci_ioda2_release_pe_dma(pe); 3673c5f7700bSGavin Shan break; 3674c5f7700bSGavin Shan default: 3675c5f7700bSGavin Shan WARN_ON(1); 3676c5f7700bSGavin Shan } 3677c5f7700bSGavin Shan 3678c5f7700bSGavin Shan pnv_ioda_release_pe_seg(pe); 3679c5f7700bSGavin Shan pnv_ioda_deconfigure_pe(pe->phb, pe); 3680b314427aSGavin Shan 3681b314427aSGavin Shan /* Release slave PEs in the compound PE */ 3682b314427aSGavin Shan if (pe->flags & PNV_IODA_PE_MASTER) { 3683b314427aSGavin Shan list_for_each_entry_safe(slave, tmp, &pe->slaves, list) { 3684b314427aSGavin Shan list_del(&slave->list); 3685b314427aSGavin Shan pnv_ioda_free_pe(slave); 3686b314427aSGavin Shan } 3687b314427aSGavin Shan } 3688b314427aSGavin Shan 36896eaed166SGavin Shan /* 36906eaed166SGavin Shan * The PE for root bus can be removed because of hotplug in EEH 36916eaed166SGavin Shan * recovery for fenced PHB error. We need to mark the PE dead so 36926eaed166SGavin Shan * that it can be populated again in PCI hot add path. The PE 36936eaed166SGavin Shan * shouldn't be destroyed as it's the global reserved resource. 36946eaed166SGavin Shan */ 36956eaed166SGavin Shan if (phb->ioda.root_pe_populated && 36966eaed166SGavin Shan phb->ioda.root_pe_idx == pe->pe_number) 36976eaed166SGavin Shan phb->ioda.root_pe_populated = false; 36986eaed166SGavin Shan else 3699c5f7700bSGavin Shan pnv_ioda_free_pe(pe); 3700c5f7700bSGavin Shan } 3701c5f7700bSGavin Shan 3702c5f7700bSGavin Shan static void pnv_pci_release_device(struct pci_dev *pdev) 3703c5f7700bSGavin Shan { 3704c5f7700bSGavin Shan struct pci_controller *hose = pci_bus_to_host(pdev->bus); 3705c5f7700bSGavin Shan struct pnv_phb *phb = hose->private_data; 3706c5f7700bSGavin Shan struct pci_dn *pdn = pci_get_pdn(pdev); 3707c5f7700bSGavin Shan struct pnv_ioda_pe *pe; 3708c5f7700bSGavin Shan 3709c5f7700bSGavin Shan if (pdev->is_virtfn) 3710c5f7700bSGavin Shan return; 3711c5f7700bSGavin Shan 3712c5f7700bSGavin Shan if (!pdn || pdn->pe_number == IODA_INVALID_PE) 3713c5f7700bSGavin Shan return; 3714c5f7700bSGavin Shan 371529bf282dSGavin Shan /* 371629bf282dSGavin Shan * PCI hotplug can happen as part of EEH error recovery. The @pdn 371729bf282dSGavin Shan * isn't removed and added afterwards in this scenario. We should 371829bf282dSGavin Shan * set the PE number in @pdn to an invalid one. Otherwise, the PE's 371929bf282dSGavin Shan * device count is decreased on removing devices while failing to 372029bf282dSGavin Shan * be increased on adding devices. It leads to unbalanced PE's device 372129bf282dSGavin Shan * count and eventually make normal PCI hotplug path broken. 372229bf282dSGavin Shan */ 3723c5f7700bSGavin Shan pe = &phb->ioda.pe_array[pdn->pe_number]; 372429bf282dSGavin Shan pdn->pe_number = IODA_INVALID_PE; 372529bf282dSGavin Shan 3726c5f7700bSGavin Shan WARN_ON(--pe->device_count < 0); 3727c5f7700bSGavin Shan if (pe->device_count == 0) 3728c5f7700bSGavin Shan pnv_ioda_release_pe(pe); 3729c5f7700bSGavin Shan } 3730c5f7700bSGavin Shan 37317a8e6bbfSMichael Neuling static void pnv_pci_ioda_shutdown(struct pci_controller *hose) 373273ed148aSBenjamin Herrenschmidt { 37337a8e6bbfSMichael Neuling struct pnv_phb *phb = hose->private_data; 37347a8e6bbfSMichael Neuling 3735d1a85eeeSGavin Shan opal_pci_reset(phb->opal_id, OPAL_RESET_PCI_IODA_TABLE, 373673ed148aSBenjamin Herrenschmidt OPAL_ASSERT_RESET); 373773ed148aSBenjamin Herrenschmidt } 373873ed148aSBenjamin Herrenschmidt 373992ae0353SDaniel Axtens static const struct pci_controller_ops pnv_pci_ioda_controller_ops = { 374092ae0353SDaniel Axtens .dma_dev_setup = pnv_pci_dma_dev_setup, 37411bc74f1cSGavin Shan .dma_bus_setup = pnv_pci_dma_bus_setup, 374292ae0353SDaniel Axtens #ifdef CONFIG_PCI_MSI 374392ae0353SDaniel Axtens .setup_msi_irqs = pnv_setup_msi_irqs, 374492ae0353SDaniel Axtens .teardown_msi_irqs = pnv_teardown_msi_irqs, 374592ae0353SDaniel Axtens #endif 374692ae0353SDaniel Axtens .enable_device_hook = pnv_pci_enable_device_hook, 3747c5f7700bSGavin Shan .release_device = pnv_pci_release_device, 374892ae0353SDaniel Axtens .window_alignment = pnv_pci_window_alignment, 3749ccd1c191SGavin Shan .setup_bridge = pnv_pci_setup_bridge, 375092ae0353SDaniel Axtens .reset_secondary_bus = pnv_pci_reset_secondary_bus, 3751763d2d8dSDaniel Axtens .dma_set_mask = pnv_pci_ioda_dma_set_mask, 375253522982SAndrew Donnellan .dma_get_required_mask = pnv_pci_ioda_dma_get_required_mask, 37537a8e6bbfSMichael Neuling .shutdown = pnv_pci_ioda_shutdown, 375492ae0353SDaniel Axtens }; 375592ae0353SDaniel Axtens 3756f9f83456SAlexey Kardashevskiy static int pnv_npu_dma_set_mask(struct pci_dev *npdev, u64 dma_mask) 3757f9f83456SAlexey Kardashevskiy { 3758f9f83456SAlexey Kardashevskiy dev_err_once(&npdev->dev, 3759f9f83456SAlexey Kardashevskiy "%s operation unsupported for NVLink devices\n", 3760f9f83456SAlexey Kardashevskiy __func__); 3761f9f83456SAlexey Kardashevskiy return -EPERM; 3762f9f83456SAlexey Kardashevskiy } 3763f9f83456SAlexey Kardashevskiy 37645d2aa710SAlistair Popple static const struct pci_controller_ops pnv_npu_ioda_controller_ops = { 37655d2aa710SAlistair Popple .dma_dev_setup = pnv_pci_dma_dev_setup, 37665d2aa710SAlistair Popple #ifdef CONFIG_PCI_MSI 37675d2aa710SAlistair Popple .setup_msi_irqs = pnv_setup_msi_irqs, 37685d2aa710SAlistair Popple .teardown_msi_irqs = pnv_teardown_msi_irqs, 37695d2aa710SAlistair Popple #endif 37705d2aa710SAlistair Popple .enable_device_hook = pnv_pci_enable_device_hook, 37715d2aa710SAlistair Popple .window_alignment = pnv_pci_window_alignment, 37725d2aa710SAlistair Popple .reset_secondary_bus = pnv_pci_reset_secondary_bus, 37735d2aa710SAlistair Popple .dma_set_mask = pnv_npu_dma_set_mask, 37745d2aa710SAlistair Popple .shutdown = pnv_pci_ioda_shutdown, 37755d2aa710SAlistair Popple }; 37765d2aa710SAlistair Popple 37774361b034SIan Munsie #ifdef CONFIG_CXL_BASE 37784361b034SIan Munsie const struct pci_controller_ops pnv_cxl_cx4_ioda_controller_ops = { 37794361b034SIan Munsie .dma_dev_setup = pnv_pci_dma_dev_setup, 37804361b034SIan Munsie .dma_bus_setup = pnv_pci_dma_bus_setup, 3781a2f67d5eSIan Munsie #ifdef CONFIG_PCI_MSI 3782a2f67d5eSIan Munsie .setup_msi_irqs = pnv_cxl_cx4_setup_msi_irqs, 3783a2f67d5eSIan Munsie .teardown_msi_irqs = pnv_cxl_cx4_teardown_msi_irqs, 3784a2f67d5eSIan Munsie #endif 37854361b034SIan Munsie .enable_device_hook = pnv_cxl_enable_device_hook, 37864361b034SIan Munsie .disable_device = pnv_cxl_disable_device, 37874361b034SIan Munsie .release_device = pnv_pci_release_device, 37884361b034SIan Munsie .window_alignment = pnv_pci_window_alignment, 37894361b034SIan Munsie .setup_bridge = pnv_pci_setup_bridge, 37904361b034SIan Munsie .reset_secondary_bus = pnv_pci_reset_secondary_bus, 37914361b034SIan Munsie .dma_set_mask = pnv_pci_ioda_dma_set_mask, 37924361b034SIan Munsie .dma_get_required_mask = pnv_pci_ioda_dma_get_required_mask, 37934361b034SIan Munsie .shutdown = pnv_pci_ioda_shutdown, 37944361b034SIan Munsie }; 37954361b034SIan Munsie #endif 37964361b034SIan Munsie 3797e51df2c1SAnton Blanchard static void __init pnv_pci_init_ioda_phb(struct device_node *np, 3798e9cc17d4SGavin Shan u64 hub_id, int ioda_type) 3799184cd4a3SBenjamin Herrenschmidt { 3800184cd4a3SBenjamin Herrenschmidt struct pci_controller *hose; 3801184cd4a3SBenjamin Herrenschmidt struct pnv_phb *phb; 38022b923ed1SGavin Shan unsigned long size, m64map_off, m32map_off, pemap_off; 38032b923ed1SGavin Shan unsigned long iomap_off = 0, dma32map_off = 0; 3804fd141d1aSBenjamin Herrenschmidt struct resource r; 3805c681b93cSAlistair Popple const __be64 *prop64; 38063a1a4661SBenjamin Herrenschmidt const __be32 *prop32; 3807f1b7cc3eSGavin Shan int len; 38083fa23ff8SGavin Shan unsigned int segno; 3809184cd4a3SBenjamin Herrenschmidt u64 phb_id; 3810184cd4a3SBenjamin Herrenschmidt void *aux; 3811184cd4a3SBenjamin Herrenschmidt long rc; 3812184cd4a3SBenjamin Herrenschmidt 381308a45b32SBenjamin Herrenschmidt if (!of_device_is_available(np)) 381408a45b32SBenjamin Herrenschmidt return; 381508a45b32SBenjamin Herrenschmidt 3816b7c670d6SRob Herring pr_info("Initializing %s PHB (%pOF)\n", pnv_phb_names[ioda_type], np); 3817184cd4a3SBenjamin Herrenschmidt 3818184cd4a3SBenjamin Herrenschmidt prop64 = of_get_property(np, "ibm,opal-phbid", NULL); 3819184cd4a3SBenjamin Herrenschmidt if (!prop64) { 3820184cd4a3SBenjamin Herrenschmidt pr_err(" Missing \"ibm,opal-phbid\" property !\n"); 3821184cd4a3SBenjamin Herrenschmidt return; 3822184cd4a3SBenjamin Herrenschmidt } 3823184cd4a3SBenjamin Herrenschmidt phb_id = be64_to_cpup(prop64); 3824184cd4a3SBenjamin Herrenschmidt pr_debug(" PHB-ID : 0x%016llx\n", phb_id); 3825184cd4a3SBenjamin Herrenschmidt 3826e39f223fSMichael Ellerman phb = memblock_virt_alloc(sizeof(struct pnv_phb), 0); 382758d714ecSGavin Shan 382858d714ecSGavin Shan /* Allocate PCI controller */ 3829184cd4a3SBenjamin Herrenschmidt phb->hose = hose = pcibios_alloc_controller(np); 383058d714ecSGavin Shan if (!phb->hose) { 3831b7c670d6SRob Herring pr_err(" Can't allocate PCI controller for %pOF\n", 3832b7c670d6SRob Herring np); 3833e39f223fSMichael Ellerman memblock_free(__pa(phb), sizeof(struct pnv_phb)); 3834184cd4a3SBenjamin Herrenschmidt return; 3835184cd4a3SBenjamin Herrenschmidt } 3836184cd4a3SBenjamin Herrenschmidt 3837184cd4a3SBenjamin Herrenschmidt spin_lock_init(&phb->lock); 3838f1b7cc3eSGavin Shan prop32 = of_get_property(np, "bus-range", &len); 3839f1b7cc3eSGavin Shan if (prop32 && len == 8) { 38403a1a4661SBenjamin Herrenschmidt hose->first_busno = be32_to_cpu(prop32[0]); 38413a1a4661SBenjamin Herrenschmidt hose->last_busno = be32_to_cpu(prop32[1]); 3842f1b7cc3eSGavin Shan } else { 3843b7c670d6SRob Herring pr_warn(" Broken <bus-range> on %pOF\n", np); 3844184cd4a3SBenjamin Herrenschmidt hose->first_busno = 0; 3845184cd4a3SBenjamin Herrenschmidt hose->last_busno = 0xff; 3846f1b7cc3eSGavin Shan } 3847184cd4a3SBenjamin Herrenschmidt hose->private_data = phb; 3848e9cc17d4SGavin Shan phb->hub_id = hub_id; 3849184cd4a3SBenjamin Herrenschmidt phb->opal_id = phb_id; 3850aa0c033fSGavin Shan phb->type = ioda_type; 3851781a868fSWei Yang mutex_init(&phb->ioda.pe_alloc_mutex); 3852184cd4a3SBenjamin Herrenschmidt 3853cee72d5bSBenjamin Herrenschmidt /* Detect specific models for error handling */ 3854cee72d5bSBenjamin Herrenschmidt if (of_device_is_compatible(np, "ibm,p7ioc-pciex")) 3855cee72d5bSBenjamin Herrenschmidt phb->model = PNV_PHB_MODEL_P7IOC; 3856f3d40c25SBenjamin Herrenschmidt else if (of_device_is_compatible(np, "ibm,power8-pciex")) 3857aa0c033fSGavin Shan phb->model = PNV_PHB_MODEL_PHB3; 38585d2aa710SAlistair Popple else if (of_device_is_compatible(np, "ibm,power8-npu-pciex")) 38595d2aa710SAlistair Popple phb->model = PNV_PHB_MODEL_NPU; 3860616badd2SAlistair Popple else if (of_device_is_compatible(np, "ibm,power9-npu-pciex")) 3861616badd2SAlistair Popple phb->model = PNV_PHB_MODEL_NPU2; 3862cee72d5bSBenjamin Herrenschmidt else 3863cee72d5bSBenjamin Herrenschmidt phb->model = PNV_PHB_MODEL_UNKNOWN; 3864cee72d5bSBenjamin Herrenschmidt 38655cb1f8fdSRussell Currey /* Initialize diagnostic data buffer */ 38665cb1f8fdSRussell Currey prop32 = of_get_property(np, "ibm,phb-diag-data-size", NULL); 38675cb1f8fdSRussell Currey if (prop32) 38685cb1f8fdSRussell Currey phb->diag_data_size = be32_to_cpup(prop32); 38695cb1f8fdSRussell Currey else 38705cb1f8fdSRussell Currey phb->diag_data_size = PNV_PCI_DIAG_BUF_SIZE; 38715cb1f8fdSRussell Currey 38725cb1f8fdSRussell Currey phb->diag_data = memblock_virt_alloc(phb->diag_data_size, 0); 38735cb1f8fdSRussell Currey 3874aa0c033fSGavin Shan /* Parse 32-bit and IO ranges (if any) */ 38752f1ec02eSGavin Shan pci_process_bridge_OF_ranges(hose, np, !hose->global_number); 3876184cd4a3SBenjamin Herrenschmidt 3877aa0c033fSGavin Shan /* Get registers */ 3878fd141d1aSBenjamin Herrenschmidt if (!of_address_to_resource(np, 0, &r)) { 3879fd141d1aSBenjamin Herrenschmidt phb->regs_phys = r.start; 3880fd141d1aSBenjamin Herrenschmidt phb->regs = ioremap(r.start, resource_size(&r)); 3881184cd4a3SBenjamin Herrenschmidt if (phb->regs == NULL) 3882184cd4a3SBenjamin Herrenschmidt pr_err(" Failed to map registers !\n"); 3883fd141d1aSBenjamin Herrenschmidt } 3884577c8c88SGavin Shan 3885184cd4a3SBenjamin Herrenschmidt /* Initialize more IODA stuff */ 388692b8f137SGavin Shan phb->ioda.total_pe_num = 1; 388736954dc7SGavin Shan prop32 = of_get_property(np, "ibm,opal-num-pes", NULL); 388836954dc7SGavin Shan if (prop32) 388992b8f137SGavin Shan phb->ioda.total_pe_num = be32_to_cpup(prop32); 389036954dc7SGavin Shan prop32 = of_get_property(np, "ibm,opal-reserved-pe", NULL); 389136954dc7SGavin Shan if (prop32) 389292b8f137SGavin Shan phb->ioda.reserved_pe_idx = be32_to_cpup(prop32); 3893262af557SGuo Chao 3894c127562aSGavin Shan /* Invalidate RID to PE# mapping */ 3895c127562aSGavin Shan for (segno = 0; segno < ARRAY_SIZE(phb->ioda.pe_rmap); segno++) 3896c127562aSGavin Shan phb->ioda.pe_rmap[segno] = IODA_INVALID_PE; 3897c127562aSGavin Shan 3898262af557SGuo Chao /* Parse 64-bit MMIO range */ 3899262af557SGuo Chao pnv_ioda_parse_m64_window(phb); 3900262af557SGuo Chao 3901184cd4a3SBenjamin Herrenschmidt phb->ioda.m32_size = resource_size(&hose->mem_resources[0]); 3902aa0c033fSGavin Shan /* FW Has already off top 64k of M32 space (MSI space) */ 3903184cd4a3SBenjamin Herrenschmidt phb->ioda.m32_size += 0x10000; 3904184cd4a3SBenjamin Herrenschmidt 390592b8f137SGavin Shan phb->ioda.m32_segsize = phb->ioda.m32_size / phb->ioda.total_pe_num; 39063fd47f06SBenjamin Herrenschmidt phb->ioda.m32_pci_base = hose->mem_resources[0].start - hose->mem_offset[0]; 3907184cd4a3SBenjamin Herrenschmidt phb->ioda.io_size = hose->pci_io_size; 390892b8f137SGavin Shan phb->ioda.io_segsize = phb->ioda.io_size / phb->ioda.total_pe_num; 3909184cd4a3SBenjamin Herrenschmidt phb->ioda.io_pci_base = 0; /* XXX calculate this ? */ 3910184cd4a3SBenjamin Herrenschmidt 39112b923ed1SGavin Shan /* Calculate how many 32-bit TCE segments we have */ 39122b923ed1SGavin Shan phb->ioda.dma32_count = phb->ioda.m32_pci_base / 39132b923ed1SGavin Shan PNV_IODA1_DMA32_SEGSIZE; 39142b923ed1SGavin Shan 3915c35d2a8cSGavin Shan /* Allocate aux data & arrays. We don't have IO ports on PHB3 */ 391692a86756SAlexey Kardashevskiy size = _ALIGN_UP(max_t(unsigned, phb->ioda.total_pe_num, 8) / 8, 391792a86756SAlexey Kardashevskiy sizeof(unsigned long)); 391893289d8cSGavin Shan m64map_off = size; 391993289d8cSGavin Shan size += phb->ioda.total_pe_num * sizeof(phb->ioda.m64_segmap[0]); 3920184cd4a3SBenjamin Herrenschmidt m32map_off = size; 392192b8f137SGavin Shan size += phb->ioda.total_pe_num * sizeof(phb->ioda.m32_segmap[0]); 3922c35d2a8cSGavin Shan if (phb->type == PNV_PHB_IODA1) { 3923c35d2a8cSGavin Shan iomap_off = size; 392492b8f137SGavin Shan size += phb->ioda.total_pe_num * sizeof(phb->ioda.io_segmap[0]); 39252b923ed1SGavin Shan dma32map_off = size; 39262b923ed1SGavin Shan size += phb->ioda.dma32_count * 39272b923ed1SGavin Shan sizeof(phb->ioda.dma32_segmap[0]); 3928c35d2a8cSGavin Shan } 3929184cd4a3SBenjamin Herrenschmidt pemap_off = size; 393092b8f137SGavin Shan size += phb->ioda.total_pe_num * sizeof(struct pnv_ioda_pe); 3931e39f223fSMichael Ellerman aux = memblock_virt_alloc(size, 0); 3932184cd4a3SBenjamin Herrenschmidt phb->ioda.pe_alloc = aux; 393393289d8cSGavin Shan phb->ioda.m64_segmap = aux + m64map_off; 3934184cd4a3SBenjamin Herrenschmidt phb->ioda.m32_segmap = aux + m32map_off; 393593289d8cSGavin Shan for (segno = 0; segno < phb->ioda.total_pe_num; segno++) { 393693289d8cSGavin Shan phb->ioda.m64_segmap[segno] = IODA_INVALID_PE; 39373fa23ff8SGavin Shan phb->ioda.m32_segmap[segno] = IODA_INVALID_PE; 393893289d8cSGavin Shan } 39393fa23ff8SGavin Shan if (phb->type == PNV_PHB_IODA1) { 3940184cd4a3SBenjamin Herrenschmidt phb->ioda.io_segmap = aux + iomap_off; 39413fa23ff8SGavin Shan for (segno = 0; segno < phb->ioda.total_pe_num; segno++) 39423fa23ff8SGavin Shan phb->ioda.io_segmap[segno] = IODA_INVALID_PE; 39432b923ed1SGavin Shan 39442b923ed1SGavin Shan phb->ioda.dma32_segmap = aux + dma32map_off; 39452b923ed1SGavin Shan for (segno = 0; segno < phb->ioda.dma32_count; segno++) 39462b923ed1SGavin Shan phb->ioda.dma32_segmap[segno] = IODA_INVALID_PE; 39473fa23ff8SGavin Shan } 3948184cd4a3SBenjamin Herrenschmidt phb->ioda.pe_array = aux + pemap_off; 394963803c39SGavin Shan 395063803c39SGavin Shan /* 395163803c39SGavin Shan * Choose PE number for root bus, which shouldn't have 395263803c39SGavin Shan * M64 resources consumed by its child devices. To pick 395363803c39SGavin Shan * the PE number adjacent to the reserved one if possible. 395463803c39SGavin Shan */ 395563803c39SGavin Shan pnv_ioda_reserve_pe(phb, phb->ioda.reserved_pe_idx); 395663803c39SGavin Shan if (phb->ioda.reserved_pe_idx == 0) { 395763803c39SGavin Shan phb->ioda.root_pe_idx = 1; 395863803c39SGavin Shan pnv_ioda_reserve_pe(phb, phb->ioda.root_pe_idx); 395963803c39SGavin Shan } else if (phb->ioda.reserved_pe_idx == (phb->ioda.total_pe_num - 1)) { 396063803c39SGavin Shan phb->ioda.root_pe_idx = phb->ioda.reserved_pe_idx - 1; 396163803c39SGavin Shan pnv_ioda_reserve_pe(phb, phb->ioda.root_pe_idx); 396263803c39SGavin Shan } else { 396363803c39SGavin Shan phb->ioda.root_pe_idx = IODA_INVALID_PE; 396463803c39SGavin Shan } 3965184cd4a3SBenjamin Herrenschmidt 3966184cd4a3SBenjamin Herrenschmidt INIT_LIST_HEAD(&phb->ioda.pe_list); 3967781a868fSWei Yang mutex_init(&phb->ioda.pe_list_mutex); 3968184cd4a3SBenjamin Herrenschmidt 3969184cd4a3SBenjamin Herrenschmidt /* Calculate how many 32-bit TCE segments we have */ 39702b923ed1SGavin Shan phb->ioda.dma32_count = phb->ioda.m32_pci_base / 3971acce971cSGavin Shan PNV_IODA1_DMA32_SEGSIZE; 3972184cd4a3SBenjamin Herrenschmidt 3973aa0c033fSGavin Shan #if 0 /* We should really do that ... */ 3974184cd4a3SBenjamin Herrenschmidt rc = opal_pci_set_phb_mem_window(opal->phb_id, 3975184cd4a3SBenjamin Herrenschmidt window_type, 3976184cd4a3SBenjamin Herrenschmidt window_num, 3977184cd4a3SBenjamin Herrenschmidt starting_real_address, 3978184cd4a3SBenjamin Herrenschmidt starting_pci_address, 3979184cd4a3SBenjamin Herrenschmidt segment_size); 3980184cd4a3SBenjamin Herrenschmidt #endif 3981184cd4a3SBenjamin Herrenschmidt 3982262af557SGuo Chao pr_info(" %03d (%03d) PE's M32: 0x%x [segment=0x%x]\n", 398392b8f137SGavin Shan phb->ioda.total_pe_num, phb->ioda.reserved_pe_idx, 3984262af557SGuo Chao phb->ioda.m32_size, phb->ioda.m32_segsize); 3985262af557SGuo Chao if (phb->ioda.m64_size) 3986262af557SGuo Chao pr_info(" M64: 0x%lx [segment=0x%lx]\n", 3987262af557SGuo Chao phb->ioda.m64_size, phb->ioda.m64_segsize); 3988262af557SGuo Chao if (phb->ioda.io_size) 3989262af557SGuo Chao pr_info(" IO: 0x%x [segment=0x%x]\n", 3990184cd4a3SBenjamin Herrenschmidt phb->ioda.io_size, phb->ioda.io_segsize); 3991184cd4a3SBenjamin Herrenschmidt 3992262af557SGuo Chao 3993184cd4a3SBenjamin Herrenschmidt phb->hose->ops = &pnv_pci_ops; 399449dec922SGavin Shan phb->get_pe_state = pnv_ioda_get_pe_state; 399549dec922SGavin Shan phb->freeze_pe = pnv_ioda_freeze_pe; 399649dec922SGavin Shan phb->unfreeze_pe = pnv_ioda_unfreeze_pe; 3997184cd4a3SBenjamin Herrenschmidt 3998184cd4a3SBenjamin Herrenschmidt /* Setup MSI support */ 3999184cd4a3SBenjamin Herrenschmidt pnv_pci_init_ioda_msis(phb); 4000184cd4a3SBenjamin Herrenschmidt 4001c40a4210SGavin Shan /* 4002c40a4210SGavin Shan * We pass the PCI probe flag PCI_REASSIGN_ALL_RSRC here 4003c40a4210SGavin Shan * to let the PCI core do resource assignment. It's supposed 4004c40a4210SGavin Shan * that the PCI core will do correct I/O and MMIO alignment 4005c40a4210SGavin Shan * for the P2P bridge bars so that each PCI bus (excluding 4006c40a4210SGavin Shan * the child P2P bridges) can form individual PE. 4007184cd4a3SBenjamin Herrenschmidt */ 4008fb446ad0SGavin Shan ppc_md.pcibios_fixup = pnv_pci_ioda_fixup; 40095d2aa710SAlistair Popple 4010f9f83456SAlexey Kardashevskiy if (phb->type == PNV_PHB_NPU) { 40115d2aa710SAlistair Popple hose->controller_ops = pnv_npu_ioda_controller_ops; 4012f9f83456SAlexey Kardashevskiy } else { 4013f9f83456SAlexey Kardashevskiy phb->dma_dev_setup = pnv_pci_ioda_dma_dev_setup; 401492ae0353SDaniel Axtens hose->controller_ops = pnv_pci_ioda_controller_ops; 4015f9f83456SAlexey Kardashevskiy } 4016ad30cb99SMichael Ellerman 401738274637SYongji Xie ppc_md.pcibios_default_alignment = pnv_pci_default_alignment; 401838274637SYongji Xie 40196e628c7dSWei Yang #ifdef CONFIG_PCI_IOV 40206e628c7dSWei Yang ppc_md.pcibios_fixup_sriov = pnv_pci_ioda_fixup_iov_resources; 40215350ab3fSWei Yang ppc_md.pcibios_iov_resource_alignment = pnv_pci_iov_resource_alignment; 4022ad30cb99SMichael Ellerman #endif 4023ad30cb99SMichael Ellerman 4024c40a4210SGavin Shan pci_add_flags(PCI_REASSIGN_ALL_RSRC); 4025184cd4a3SBenjamin Herrenschmidt 4026184cd4a3SBenjamin Herrenschmidt /* Reset IODA tables to a clean state */ 4027d1a85eeeSGavin Shan rc = opal_pci_reset(phb_id, OPAL_RESET_PCI_IODA_TABLE, OPAL_ASSERT_RESET); 4028184cd4a3SBenjamin Herrenschmidt if (rc) 4029f2c2cbccSJoe Perches pr_warn(" OPAL Error %ld performing IODA table reset !\n", rc); 4030361f2a2aSGavin Shan 40316060e9eaSAndrew Donnellan /* 40326060e9eaSAndrew Donnellan * If we're running in kdump kernel, the previous kernel never 4033361f2a2aSGavin Shan * shutdown PCI devices correctly. We already got IODA table 4034361f2a2aSGavin Shan * cleaned out. So we have to issue PHB reset to stop all PCI 40356060e9eaSAndrew Donnellan * transactions from previous kernel. 4036361f2a2aSGavin Shan */ 4037361f2a2aSGavin Shan if (is_kdump_kernel()) { 4038361f2a2aSGavin Shan pr_info(" Issue PHB reset ...\n"); 4039cadf364dSGavin Shan pnv_eeh_phb_reset(hose, EEH_RESET_FUNDAMENTAL); 4040cadf364dSGavin Shan pnv_eeh_phb_reset(hose, EEH_RESET_DEACTIVATE); 4041361f2a2aSGavin Shan } 4042262af557SGuo Chao 40439e9e8935SGavin Shan /* Remove M64 resource if we can't configure it successfully */ 40449e9e8935SGavin Shan if (!phb->init_m64 || phb->init_m64(phb)) 4045262af557SGuo Chao hose->mem_resources[1].flags = 0; 4046184cd4a3SBenjamin Herrenschmidt } 4047184cd4a3SBenjamin Herrenschmidt 404867975005SBjorn Helgaas void __init pnv_pci_init_ioda2_phb(struct device_node *np) 4049aa0c033fSGavin Shan { 4050e9cc17d4SGavin Shan pnv_pci_init_ioda_phb(np, 0, PNV_PHB_IODA2); 4051aa0c033fSGavin Shan } 4052aa0c033fSGavin Shan 40535d2aa710SAlistair Popple void __init pnv_pci_init_npu_phb(struct device_node *np) 40545d2aa710SAlistair Popple { 40555d2aa710SAlistair Popple pnv_pci_init_ioda_phb(np, 0, PNV_PHB_NPU); 40565d2aa710SAlistair Popple } 40575d2aa710SAlistair Popple 4058184cd4a3SBenjamin Herrenschmidt void __init pnv_pci_init_ioda_hub(struct device_node *np) 4059184cd4a3SBenjamin Herrenschmidt { 4060184cd4a3SBenjamin Herrenschmidt struct device_node *phbn; 4061c681b93cSAlistair Popple const __be64 *prop64; 4062184cd4a3SBenjamin Herrenschmidt u64 hub_id; 4063184cd4a3SBenjamin Herrenschmidt 4064b7c670d6SRob Herring pr_info("Probing IODA IO-Hub %pOF\n", np); 4065184cd4a3SBenjamin Herrenschmidt 4066184cd4a3SBenjamin Herrenschmidt prop64 = of_get_property(np, "ibm,opal-hubid", NULL); 4067184cd4a3SBenjamin Herrenschmidt if (!prop64) { 4068184cd4a3SBenjamin Herrenschmidt pr_err(" Missing \"ibm,opal-hubid\" property !\n"); 4069184cd4a3SBenjamin Herrenschmidt return; 4070184cd4a3SBenjamin Herrenschmidt } 4071184cd4a3SBenjamin Herrenschmidt hub_id = be64_to_cpup(prop64); 4072184cd4a3SBenjamin Herrenschmidt pr_devel(" HUB-ID : 0x%016llx\n", hub_id); 4073184cd4a3SBenjamin Herrenschmidt 4074184cd4a3SBenjamin Herrenschmidt /* Count child PHBs */ 4075184cd4a3SBenjamin Herrenschmidt for_each_child_of_node(np, phbn) { 4076184cd4a3SBenjamin Herrenschmidt /* Look for IODA1 PHBs */ 4077184cd4a3SBenjamin Herrenschmidt if (of_device_is_compatible(phbn, "ibm,ioda-phb")) 4078e9cc17d4SGavin Shan pnv_pci_init_ioda_phb(phbn, hub_id, PNV_PHB_IODA1); 4079184cd4a3SBenjamin Herrenschmidt } 4080184cd4a3SBenjamin Herrenschmidt } 4081