1184cd4a3SBenjamin Herrenschmidt /* 2184cd4a3SBenjamin Herrenschmidt * Support PCI/PCIe on PowerNV platforms 3184cd4a3SBenjamin Herrenschmidt * 4184cd4a3SBenjamin Herrenschmidt * Copyright 2011 Benjamin Herrenschmidt, IBM Corp. 5184cd4a3SBenjamin Herrenschmidt * 6184cd4a3SBenjamin Herrenschmidt * This program is free software; you can redistribute it and/or 7184cd4a3SBenjamin Herrenschmidt * modify it under the terms of the GNU General Public License 8184cd4a3SBenjamin Herrenschmidt * as published by the Free Software Foundation; either version 9184cd4a3SBenjamin Herrenschmidt * 2 of the License, or (at your option) any later version. 10184cd4a3SBenjamin Herrenschmidt */ 11184cd4a3SBenjamin Herrenschmidt 12cee72d5bSBenjamin Herrenschmidt #undef DEBUG 13184cd4a3SBenjamin Herrenschmidt 14184cd4a3SBenjamin Herrenschmidt #include <linux/kernel.h> 15184cd4a3SBenjamin Herrenschmidt #include <linux/pci.h> 16361f2a2aSGavin Shan #include <linux/crash_dump.h> 1737c367f2SGavin Shan #include <linux/debugfs.h> 18184cd4a3SBenjamin Herrenschmidt #include <linux/delay.h> 19184cd4a3SBenjamin Herrenschmidt #include <linux/string.h> 20184cd4a3SBenjamin Herrenschmidt #include <linux/init.h> 21184cd4a3SBenjamin Herrenschmidt #include <linux/bootmem.h> 22184cd4a3SBenjamin Herrenschmidt #include <linux/irq.h> 23184cd4a3SBenjamin Herrenschmidt #include <linux/io.h> 24184cd4a3SBenjamin Herrenschmidt #include <linux/msi.h> 25cd15b048SBenjamin Herrenschmidt #include <linux/memblock.h> 26184cd4a3SBenjamin Herrenschmidt 27184cd4a3SBenjamin Herrenschmidt #include <asm/sections.h> 28184cd4a3SBenjamin Herrenschmidt #include <asm/io.h> 29184cd4a3SBenjamin Herrenschmidt #include <asm/prom.h> 30184cd4a3SBenjamin Herrenschmidt #include <asm/pci-bridge.h> 31184cd4a3SBenjamin Herrenschmidt #include <asm/machdep.h> 32fb1b55d6SGavin Shan #include <asm/msi_bitmap.h> 33184cd4a3SBenjamin Herrenschmidt #include <asm/ppc-pci.h> 34184cd4a3SBenjamin Herrenschmidt #include <asm/opal.h> 35184cd4a3SBenjamin Herrenschmidt #include <asm/iommu.h> 36184cd4a3SBenjamin Herrenschmidt #include <asm/tce.h> 37137436c9SGavin Shan #include <asm/xics.h> 3837c367f2SGavin Shan #include <asm/debug.h> 39262af557SGuo Chao #include <asm/firmware.h> 4080c49c7eSIan Munsie #include <asm/pnv-pci.h> 4180c49c7eSIan Munsie 4280c49c7eSIan Munsie #include <misc/cxl.h> 43184cd4a3SBenjamin Herrenschmidt 44184cd4a3SBenjamin Herrenschmidt #include "powernv.h" 45184cd4a3SBenjamin Herrenschmidt #include "pci.h" 46184cd4a3SBenjamin Herrenschmidt 476d31c2faSJoe Perches static void pe_level_printk(const struct pnv_ioda_pe *pe, const char *level, 486d31c2faSJoe Perches const char *fmt, ...) 496d31c2faSJoe Perches { 506d31c2faSJoe Perches struct va_format vaf; 516d31c2faSJoe Perches va_list args; 526d31c2faSJoe Perches char pfix[32]; 53184cd4a3SBenjamin Herrenschmidt 546d31c2faSJoe Perches va_start(args, fmt); 556d31c2faSJoe Perches 566d31c2faSJoe Perches vaf.fmt = fmt; 576d31c2faSJoe Perches vaf.va = &args; 586d31c2faSJoe Perches 596d31c2faSJoe Perches if (pe->pdev) 606d31c2faSJoe Perches strlcpy(pfix, dev_name(&pe->pdev->dev), sizeof(pfix)); 616d31c2faSJoe Perches else 626d31c2faSJoe Perches sprintf(pfix, "%04x:%02x ", 636d31c2faSJoe Perches pci_domain_nr(pe->pbus), pe->pbus->number); 646d31c2faSJoe Perches 656d31c2faSJoe Perches printk("%spci %s: [PE# %.3d] %pV", 666d31c2faSJoe Perches level, pfix, pe->pe_number, &vaf); 676d31c2faSJoe Perches 686d31c2faSJoe Perches va_end(args); 696d31c2faSJoe Perches } 706d31c2faSJoe Perches 716d31c2faSJoe Perches #define pe_err(pe, fmt, ...) \ 726d31c2faSJoe Perches pe_level_printk(pe, KERN_ERR, fmt, ##__VA_ARGS__) 736d31c2faSJoe Perches #define pe_warn(pe, fmt, ...) \ 746d31c2faSJoe Perches pe_level_printk(pe, KERN_WARNING, fmt, ##__VA_ARGS__) 756d31c2faSJoe Perches #define pe_info(pe, fmt, ...) \ 766d31c2faSJoe Perches pe_level_printk(pe, KERN_INFO, fmt, ##__VA_ARGS__) 77184cd4a3SBenjamin Herrenschmidt 788e0a1611SAlexey Kardashevskiy /* 798e0a1611SAlexey Kardashevskiy * stdcix is only supposed to be used in hypervisor real mode as per 808e0a1611SAlexey Kardashevskiy * the architecture spec 818e0a1611SAlexey Kardashevskiy */ 828e0a1611SAlexey Kardashevskiy static inline void __raw_rm_writeq(u64 val, volatile void __iomem *paddr) 838e0a1611SAlexey Kardashevskiy { 848e0a1611SAlexey Kardashevskiy __asm__ __volatile__("stdcix %0,0,%1" 858e0a1611SAlexey Kardashevskiy : : "r" (val), "r" (paddr) : "memory"); 868e0a1611SAlexey Kardashevskiy } 878e0a1611SAlexey Kardashevskiy 88262af557SGuo Chao static inline bool pnv_pci_is_mem_pref_64(unsigned long flags) 89262af557SGuo Chao { 90262af557SGuo Chao return ((flags & (IORESOURCE_MEM_64 | IORESOURCE_PREFETCH)) == 91262af557SGuo Chao (IORESOURCE_MEM_64 | IORESOURCE_PREFETCH)); 92262af557SGuo Chao } 93262af557SGuo Chao 944b82ab18SGavin Shan static void pnv_ioda_reserve_pe(struct pnv_phb *phb, int pe_no) 954b82ab18SGavin Shan { 964b82ab18SGavin Shan if (!(pe_no >= 0 && pe_no < phb->ioda.total_pe)) { 974b82ab18SGavin Shan pr_warn("%s: Invalid PE %d on PHB#%x\n", 984b82ab18SGavin Shan __func__, pe_no, phb->hose->global_number); 994b82ab18SGavin Shan return; 1004b82ab18SGavin Shan } 1014b82ab18SGavin Shan 1024b82ab18SGavin Shan if (test_and_set_bit(pe_no, phb->ioda.pe_alloc)) { 1034b82ab18SGavin Shan pr_warn("%s: PE %d was assigned on PHB#%x\n", 1044b82ab18SGavin Shan __func__, pe_no, phb->hose->global_number); 1054b82ab18SGavin Shan return; 1064b82ab18SGavin Shan } 1074b82ab18SGavin Shan 1084b82ab18SGavin Shan phb->ioda.pe_array[pe_no].phb = phb; 1094b82ab18SGavin Shan phb->ioda.pe_array[pe_no].pe_number = pe_no; 1104b82ab18SGavin Shan } 1114b82ab18SGavin Shan 112cad5cef6SGreg Kroah-Hartman static int pnv_ioda_alloc_pe(struct pnv_phb *phb) 113184cd4a3SBenjamin Herrenschmidt { 114184cd4a3SBenjamin Herrenschmidt unsigned long pe; 115184cd4a3SBenjamin Herrenschmidt 116184cd4a3SBenjamin Herrenschmidt do { 117184cd4a3SBenjamin Herrenschmidt pe = find_next_zero_bit(phb->ioda.pe_alloc, 118184cd4a3SBenjamin Herrenschmidt phb->ioda.total_pe, 0); 119184cd4a3SBenjamin Herrenschmidt if (pe >= phb->ioda.total_pe) 120184cd4a3SBenjamin Herrenschmidt return IODA_INVALID_PE; 121184cd4a3SBenjamin Herrenschmidt } while(test_and_set_bit(pe, phb->ioda.pe_alloc)); 122184cd4a3SBenjamin Herrenschmidt 1234cce9550SGavin Shan phb->ioda.pe_array[pe].phb = phb; 124184cd4a3SBenjamin Herrenschmidt phb->ioda.pe_array[pe].pe_number = pe; 125184cd4a3SBenjamin Herrenschmidt return pe; 126184cd4a3SBenjamin Herrenschmidt } 127184cd4a3SBenjamin Herrenschmidt 128cad5cef6SGreg Kroah-Hartman static void pnv_ioda_free_pe(struct pnv_phb *phb, int pe) 129184cd4a3SBenjamin Herrenschmidt { 130184cd4a3SBenjamin Herrenschmidt WARN_ON(phb->ioda.pe_array[pe].pdev); 131184cd4a3SBenjamin Herrenschmidt 132184cd4a3SBenjamin Herrenschmidt memset(&phb->ioda.pe_array[pe], 0, sizeof(struct pnv_ioda_pe)); 133184cd4a3SBenjamin Herrenschmidt clear_bit(pe, phb->ioda.pe_alloc); 134184cd4a3SBenjamin Herrenschmidt } 135184cd4a3SBenjamin Herrenschmidt 136262af557SGuo Chao /* The default M64 BAR is shared by all PEs */ 137262af557SGuo Chao static int pnv_ioda2_init_m64(struct pnv_phb *phb) 138262af557SGuo Chao { 139262af557SGuo Chao const char *desc; 140262af557SGuo Chao struct resource *r; 141262af557SGuo Chao s64 rc; 142262af557SGuo Chao 143262af557SGuo Chao /* Configure the default M64 BAR */ 144262af557SGuo Chao rc = opal_pci_set_phb_mem_window(phb->opal_id, 145262af557SGuo Chao OPAL_M64_WINDOW_TYPE, 146262af557SGuo Chao phb->ioda.m64_bar_idx, 147262af557SGuo Chao phb->ioda.m64_base, 148262af557SGuo Chao 0, /* unused */ 149262af557SGuo Chao phb->ioda.m64_size); 150262af557SGuo Chao if (rc != OPAL_SUCCESS) { 151262af557SGuo Chao desc = "configuring"; 152262af557SGuo Chao goto fail; 153262af557SGuo Chao } 154262af557SGuo Chao 155262af557SGuo Chao /* Enable the default M64 BAR */ 156262af557SGuo Chao rc = opal_pci_phb_mmio_enable(phb->opal_id, 157262af557SGuo Chao OPAL_M64_WINDOW_TYPE, 158262af557SGuo Chao phb->ioda.m64_bar_idx, 159262af557SGuo Chao OPAL_ENABLE_M64_SPLIT); 160262af557SGuo Chao if (rc != OPAL_SUCCESS) { 161262af557SGuo Chao desc = "enabling"; 162262af557SGuo Chao goto fail; 163262af557SGuo Chao } 164262af557SGuo Chao 165262af557SGuo Chao /* Mark the M64 BAR assigned */ 166262af557SGuo Chao set_bit(phb->ioda.m64_bar_idx, &phb->ioda.m64_bar_alloc); 167262af557SGuo Chao 168262af557SGuo Chao /* 169262af557SGuo Chao * Strip off the segment used by the reserved PE, which is 170262af557SGuo Chao * expected to be 0 or last one of PE capabicity. 171262af557SGuo Chao */ 172262af557SGuo Chao r = &phb->hose->mem_resources[1]; 173262af557SGuo Chao if (phb->ioda.reserved_pe == 0) 174262af557SGuo Chao r->start += phb->ioda.m64_segsize; 175262af557SGuo Chao else if (phb->ioda.reserved_pe == (phb->ioda.total_pe - 1)) 176262af557SGuo Chao r->end -= phb->ioda.m64_segsize; 177262af557SGuo Chao else 178262af557SGuo Chao pr_warn(" Cannot strip M64 segment for reserved PE#%d\n", 179262af557SGuo Chao phb->ioda.reserved_pe); 180262af557SGuo Chao 181262af557SGuo Chao return 0; 182262af557SGuo Chao 183262af557SGuo Chao fail: 184262af557SGuo Chao pr_warn(" Failure %lld %s M64 BAR#%d\n", 185262af557SGuo Chao rc, desc, phb->ioda.m64_bar_idx); 186262af557SGuo Chao opal_pci_phb_mmio_enable(phb->opal_id, 187262af557SGuo Chao OPAL_M64_WINDOW_TYPE, 188262af557SGuo Chao phb->ioda.m64_bar_idx, 189262af557SGuo Chao OPAL_DISABLE_M64); 190262af557SGuo Chao return -EIO; 191262af557SGuo Chao } 192262af557SGuo Chao 1935ef73567SGavin Shan static void pnv_ioda2_reserve_m64_pe(struct pnv_phb *phb) 194262af557SGuo Chao { 195262af557SGuo Chao resource_size_t sgsz = phb->ioda.m64_segsize; 196262af557SGuo Chao struct pci_dev *pdev; 197262af557SGuo Chao struct resource *r; 198262af557SGuo Chao int base, step, i; 199262af557SGuo Chao 200262af557SGuo Chao /* 201262af557SGuo Chao * Root bus always has full M64 range and root port has 202262af557SGuo Chao * M64 range used in reality. So we're checking root port 203262af557SGuo Chao * instead of root bus. 204262af557SGuo Chao */ 205262af557SGuo Chao list_for_each_entry(pdev, &phb->hose->bus->devices, bus_list) { 2064b82ab18SGavin Shan for (i = 0; i < PCI_BRIDGE_RESOURCE_NUM; i++) { 2074b82ab18SGavin Shan r = &pdev->resource[PCI_BRIDGE_RESOURCES + i]; 208262af557SGuo Chao if (!r->parent || 209262af557SGuo Chao !pnv_pci_is_mem_pref_64(r->flags)) 210262af557SGuo Chao continue; 211262af557SGuo Chao 212262af557SGuo Chao base = (r->start - phb->ioda.m64_base) / sgsz; 213262af557SGuo Chao for (step = 0; step < resource_size(r) / sgsz; step++) 2144b82ab18SGavin Shan pnv_ioda_reserve_pe(phb, base + step); 215262af557SGuo Chao } 216262af557SGuo Chao } 217262af557SGuo Chao } 218262af557SGuo Chao 219262af557SGuo Chao static int pnv_ioda2_pick_m64_pe(struct pnv_phb *phb, 220262af557SGuo Chao struct pci_bus *bus, int all) 221262af557SGuo Chao { 222262af557SGuo Chao resource_size_t segsz = phb->ioda.m64_segsize; 223262af557SGuo Chao struct pci_dev *pdev; 224262af557SGuo Chao struct resource *r; 225262af557SGuo Chao struct pnv_ioda_pe *master_pe, *pe; 226262af557SGuo Chao unsigned long size, *pe_alloc; 227262af557SGuo Chao bool found; 228262af557SGuo Chao int start, i, j; 229262af557SGuo Chao 230262af557SGuo Chao /* Root bus shouldn't use M64 */ 231262af557SGuo Chao if (pci_is_root_bus(bus)) 232262af557SGuo Chao return IODA_INVALID_PE; 233262af557SGuo Chao 234262af557SGuo Chao /* We support only one M64 window on each bus */ 235262af557SGuo Chao found = false; 236262af557SGuo Chao pci_bus_for_each_resource(bus, r, i) { 237262af557SGuo Chao if (r && r->parent && 238262af557SGuo Chao pnv_pci_is_mem_pref_64(r->flags)) { 239262af557SGuo Chao found = true; 240262af557SGuo Chao break; 241262af557SGuo Chao } 242262af557SGuo Chao } 243262af557SGuo Chao 244262af557SGuo Chao /* No M64 window found ? */ 245262af557SGuo Chao if (!found) 246262af557SGuo Chao return IODA_INVALID_PE; 247262af557SGuo Chao 248262af557SGuo Chao /* Allocate bitmap */ 249262af557SGuo Chao size = _ALIGN_UP(phb->ioda.total_pe / 8, sizeof(unsigned long)); 250262af557SGuo Chao pe_alloc = kzalloc(size, GFP_KERNEL); 251262af557SGuo Chao if (!pe_alloc) { 252262af557SGuo Chao pr_warn("%s: Out of memory !\n", 253262af557SGuo Chao __func__); 254262af557SGuo Chao return IODA_INVALID_PE; 255262af557SGuo Chao } 256262af557SGuo Chao 257262af557SGuo Chao /* 258262af557SGuo Chao * Figure out reserved PE numbers by the PE 259262af557SGuo Chao * the its child PEs. 260262af557SGuo Chao */ 261262af557SGuo Chao start = (r->start - phb->ioda.m64_base) / segsz; 262262af557SGuo Chao for (i = 0; i < resource_size(r) / segsz; i++) 263262af557SGuo Chao set_bit(start + i, pe_alloc); 264262af557SGuo Chao 265262af557SGuo Chao if (all) 266262af557SGuo Chao goto done; 267262af557SGuo Chao 268262af557SGuo Chao /* 269262af557SGuo Chao * If the PE doesn't cover all subordinate buses, 270262af557SGuo Chao * we need subtract from reserved PEs for children. 271262af557SGuo Chao */ 272262af557SGuo Chao list_for_each_entry(pdev, &bus->devices, bus_list) { 273262af557SGuo Chao if (!pdev->subordinate) 274262af557SGuo Chao continue; 275262af557SGuo Chao 276262af557SGuo Chao pci_bus_for_each_resource(pdev->subordinate, r, i) { 277262af557SGuo Chao if (!r || !r->parent || 278262af557SGuo Chao !pnv_pci_is_mem_pref_64(r->flags)) 279262af557SGuo Chao continue; 280262af557SGuo Chao 281262af557SGuo Chao start = (r->start - phb->ioda.m64_base) / segsz; 282262af557SGuo Chao for (j = 0; j < resource_size(r) / segsz ; j++) 283262af557SGuo Chao clear_bit(start + j, pe_alloc); 284262af557SGuo Chao } 285262af557SGuo Chao } 286262af557SGuo Chao 287262af557SGuo Chao /* 288262af557SGuo Chao * the current bus might not own M64 window and that's all 289262af557SGuo Chao * contributed by its child buses. For the case, we needn't 290262af557SGuo Chao * pick M64 dependent PE#. 291262af557SGuo Chao */ 292262af557SGuo Chao if (bitmap_empty(pe_alloc, phb->ioda.total_pe)) { 293262af557SGuo Chao kfree(pe_alloc); 294262af557SGuo Chao return IODA_INVALID_PE; 295262af557SGuo Chao } 296262af557SGuo Chao 297262af557SGuo Chao /* 298262af557SGuo Chao * Figure out the master PE and put all slave PEs to master 299262af557SGuo Chao * PE's list to form compound PE. 300262af557SGuo Chao */ 301262af557SGuo Chao done: 302262af557SGuo Chao master_pe = NULL; 303262af557SGuo Chao i = -1; 304262af557SGuo Chao while ((i = find_next_bit(pe_alloc, phb->ioda.total_pe, i + 1)) < 305262af557SGuo Chao phb->ioda.total_pe) { 306262af557SGuo Chao pe = &phb->ioda.pe_array[i]; 307262af557SGuo Chao 308262af557SGuo Chao if (!master_pe) { 309262af557SGuo Chao pe->flags |= PNV_IODA_PE_MASTER; 310262af557SGuo Chao INIT_LIST_HEAD(&pe->slaves); 311262af557SGuo Chao master_pe = pe; 312262af557SGuo Chao } else { 313262af557SGuo Chao pe->flags |= PNV_IODA_PE_SLAVE; 314262af557SGuo Chao pe->master = master_pe; 315262af557SGuo Chao list_add_tail(&pe->list, &master_pe->slaves); 316262af557SGuo Chao } 317262af557SGuo Chao } 318262af557SGuo Chao 319262af557SGuo Chao kfree(pe_alloc); 320262af557SGuo Chao return master_pe->pe_number; 321262af557SGuo Chao } 322262af557SGuo Chao 323262af557SGuo Chao static void __init pnv_ioda_parse_m64_window(struct pnv_phb *phb) 324262af557SGuo Chao { 325262af557SGuo Chao struct pci_controller *hose = phb->hose; 326262af557SGuo Chao struct device_node *dn = hose->dn; 327262af557SGuo Chao struct resource *res; 328262af557SGuo Chao const u32 *r; 329262af557SGuo Chao u64 pci_addr; 330262af557SGuo Chao 3311665c4a8SGavin Shan /* FIXME: Support M64 for P7IOC */ 3321665c4a8SGavin Shan if (phb->type != PNV_PHB_IODA2) { 3331665c4a8SGavin Shan pr_info(" Not support M64 window\n"); 3341665c4a8SGavin Shan return; 3351665c4a8SGavin Shan } 3361665c4a8SGavin Shan 337262af557SGuo Chao if (!firmware_has_feature(FW_FEATURE_OPALv3)) { 338262af557SGuo Chao pr_info(" Firmware too old to support M64 window\n"); 339262af557SGuo Chao return; 340262af557SGuo Chao } 341262af557SGuo Chao 342262af557SGuo Chao r = of_get_property(dn, "ibm,opal-m64-window", NULL); 343262af557SGuo Chao if (!r) { 344262af557SGuo Chao pr_info(" No <ibm,opal-m64-window> on %s\n", 345262af557SGuo Chao dn->full_name); 346262af557SGuo Chao return; 347262af557SGuo Chao } 348262af557SGuo Chao 349262af557SGuo Chao res = &hose->mem_resources[1]; 350262af557SGuo Chao res->start = of_translate_address(dn, r + 2); 351262af557SGuo Chao res->end = res->start + of_read_number(r + 4, 2) - 1; 352262af557SGuo Chao res->flags = (IORESOURCE_MEM | IORESOURCE_MEM_64 | IORESOURCE_PREFETCH); 353262af557SGuo Chao pci_addr = of_read_number(r, 2); 354262af557SGuo Chao hose->mem_offset[1] = res->start - pci_addr; 355262af557SGuo Chao 356262af557SGuo Chao phb->ioda.m64_size = resource_size(res); 357262af557SGuo Chao phb->ioda.m64_segsize = phb->ioda.m64_size / phb->ioda.total_pe; 358262af557SGuo Chao phb->ioda.m64_base = pci_addr; 359262af557SGuo Chao 360e9863e68SWei Yang pr_info(" MEM64 0x%016llx..0x%016llx -> 0x%016llx\n", 361e9863e68SWei Yang res->start, res->end, pci_addr); 362e9863e68SWei Yang 363262af557SGuo Chao /* Use last M64 BAR to cover M64 window */ 364262af557SGuo Chao phb->ioda.m64_bar_idx = 15; 365262af557SGuo Chao phb->init_m64 = pnv_ioda2_init_m64; 3665ef73567SGavin Shan phb->reserve_m64_pe = pnv_ioda2_reserve_m64_pe; 367262af557SGuo Chao phb->pick_m64_pe = pnv_ioda2_pick_m64_pe; 368262af557SGuo Chao } 369262af557SGuo Chao 37049dec922SGavin Shan static void pnv_ioda_freeze_pe(struct pnv_phb *phb, int pe_no) 37149dec922SGavin Shan { 37249dec922SGavin Shan struct pnv_ioda_pe *pe = &phb->ioda.pe_array[pe_no]; 37349dec922SGavin Shan struct pnv_ioda_pe *slave; 37449dec922SGavin Shan s64 rc; 37549dec922SGavin Shan 37649dec922SGavin Shan /* Fetch master PE */ 37749dec922SGavin Shan if (pe->flags & PNV_IODA_PE_SLAVE) { 37849dec922SGavin Shan pe = pe->master; 379ec8e4e9dSGavin Shan if (WARN_ON(!pe || !(pe->flags & PNV_IODA_PE_MASTER))) 380ec8e4e9dSGavin Shan return; 381ec8e4e9dSGavin Shan 38249dec922SGavin Shan pe_no = pe->pe_number; 38349dec922SGavin Shan } 38449dec922SGavin Shan 38549dec922SGavin Shan /* Freeze master PE */ 38649dec922SGavin Shan rc = opal_pci_eeh_freeze_set(phb->opal_id, 38749dec922SGavin Shan pe_no, 38849dec922SGavin Shan OPAL_EEH_ACTION_SET_FREEZE_ALL); 38949dec922SGavin Shan if (rc != OPAL_SUCCESS) { 39049dec922SGavin Shan pr_warn("%s: Failure %lld freezing PHB#%x-PE#%x\n", 39149dec922SGavin Shan __func__, rc, phb->hose->global_number, pe_no); 39249dec922SGavin Shan return; 39349dec922SGavin Shan } 39449dec922SGavin Shan 39549dec922SGavin Shan /* Freeze slave PEs */ 39649dec922SGavin Shan if (!(pe->flags & PNV_IODA_PE_MASTER)) 39749dec922SGavin Shan return; 39849dec922SGavin Shan 39949dec922SGavin Shan list_for_each_entry(slave, &pe->slaves, list) { 40049dec922SGavin Shan rc = opal_pci_eeh_freeze_set(phb->opal_id, 40149dec922SGavin Shan slave->pe_number, 40249dec922SGavin Shan OPAL_EEH_ACTION_SET_FREEZE_ALL); 40349dec922SGavin Shan if (rc != OPAL_SUCCESS) 40449dec922SGavin Shan pr_warn("%s: Failure %lld freezing PHB#%x-PE#%x\n", 40549dec922SGavin Shan __func__, rc, phb->hose->global_number, 40649dec922SGavin Shan slave->pe_number); 40749dec922SGavin Shan } 40849dec922SGavin Shan } 40949dec922SGavin Shan 410e51df2c1SAnton Blanchard static int pnv_ioda_unfreeze_pe(struct pnv_phb *phb, int pe_no, int opt) 41149dec922SGavin Shan { 41249dec922SGavin Shan struct pnv_ioda_pe *pe, *slave; 41349dec922SGavin Shan s64 rc; 41449dec922SGavin Shan 41549dec922SGavin Shan /* Find master PE */ 41649dec922SGavin Shan pe = &phb->ioda.pe_array[pe_no]; 41749dec922SGavin Shan if (pe->flags & PNV_IODA_PE_SLAVE) { 41849dec922SGavin Shan pe = pe->master; 41949dec922SGavin Shan WARN_ON(!pe || !(pe->flags & PNV_IODA_PE_MASTER)); 42049dec922SGavin Shan pe_no = pe->pe_number; 42149dec922SGavin Shan } 42249dec922SGavin Shan 42349dec922SGavin Shan /* Clear frozen state for master PE */ 42449dec922SGavin Shan rc = opal_pci_eeh_freeze_clear(phb->opal_id, pe_no, opt); 42549dec922SGavin Shan if (rc != OPAL_SUCCESS) { 42649dec922SGavin Shan pr_warn("%s: Failure %lld clear %d on PHB#%x-PE#%x\n", 42749dec922SGavin Shan __func__, rc, opt, phb->hose->global_number, pe_no); 42849dec922SGavin Shan return -EIO; 42949dec922SGavin Shan } 43049dec922SGavin Shan 43149dec922SGavin Shan if (!(pe->flags & PNV_IODA_PE_MASTER)) 43249dec922SGavin Shan return 0; 43349dec922SGavin Shan 43449dec922SGavin Shan /* Clear frozen state for slave PEs */ 43549dec922SGavin Shan list_for_each_entry(slave, &pe->slaves, list) { 43649dec922SGavin Shan rc = opal_pci_eeh_freeze_clear(phb->opal_id, 43749dec922SGavin Shan slave->pe_number, 43849dec922SGavin Shan opt); 43949dec922SGavin Shan if (rc != OPAL_SUCCESS) { 44049dec922SGavin Shan pr_warn("%s: Failure %lld clear %d on PHB#%x-PE#%x\n", 44149dec922SGavin Shan __func__, rc, opt, phb->hose->global_number, 44249dec922SGavin Shan slave->pe_number); 44349dec922SGavin Shan return -EIO; 44449dec922SGavin Shan } 44549dec922SGavin Shan } 44649dec922SGavin Shan 44749dec922SGavin Shan return 0; 44849dec922SGavin Shan } 44949dec922SGavin Shan 45049dec922SGavin Shan static int pnv_ioda_get_pe_state(struct pnv_phb *phb, int pe_no) 45149dec922SGavin Shan { 45249dec922SGavin Shan struct pnv_ioda_pe *slave, *pe; 45349dec922SGavin Shan u8 fstate, state; 45449dec922SGavin Shan __be16 pcierr; 45549dec922SGavin Shan s64 rc; 45649dec922SGavin Shan 45749dec922SGavin Shan /* Sanity check on PE number */ 45849dec922SGavin Shan if (pe_no < 0 || pe_no >= phb->ioda.total_pe) 45949dec922SGavin Shan return OPAL_EEH_STOPPED_PERM_UNAVAIL; 46049dec922SGavin Shan 46149dec922SGavin Shan /* 46249dec922SGavin Shan * Fetch the master PE and the PE instance might be 46349dec922SGavin Shan * not initialized yet. 46449dec922SGavin Shan */ 46549dec922SGavin Shan pe = &phb->ioda.pe_array[pe_no]; 46649dec922SGavin Shan if (pe->flags & PNV_IODA_PE_SLAVE) { 46749dec922SGavin Shan pe = pe->master; 46849dec922SGavin Shan WARN_ON(!pe || !(pe->flags & PNV_IODA_PE_MASTER)); 46949dec922SGavin Shan pe_no = pe->pe_number; 47049dec922SGavin Shan } 47149dec922SGavin Shan 47249dec922SGavin Shan /* Check the master PE */ 47349dec922SGavin Shan rc = opal_pci_eeh_freeze_status(phb->opal_id, pe_no, 47449dec922SGavin Shan &state, &pcierr, NULL); 47549dec922SGavin Shan if (rc != OPAL_SUCCESS) { 47649dec922SGavin Shan pr_warn("%s: Failure %lld getting " 47749dec922SGavin Shan "PHB#%x-PE#%x state\n", 47849dec922SGavin Shan __func__, rc, 47949dec922SGavin Shan phb->hose->global_number, pe_no); 48049dec922SGavin Shan return OPAL_EEH_STOPPED_TEMP_UNAVAIL; 48149dec922SGavin Shan } 48249dec922SGavin Shan 48349dec922SGavin Shan /* Check the slave PE */ 48449dec922SGavin Shan if (!(pe->flags & PNV_IODA_PE_MASTER)) 48549dec922SGavin Shan return state; 48649dec922SGavin Shan 48749dec922SGavin Shan list_for_each_entry(slave, &pe->slaves, list) { 48849dec922SGavin Shan rc = opal_pci_eeh_freeze_status(phb->opal_id, 48949dec922SGavin Shan slave->pe_number, 49049dec922SGavin Shan &fstate, 49149dec922SGavin Shan &pcierr, 49249dec922SGavin Shan NULL); 49349dec922SGavin Shan if (rc != OPAL_SUCCESS) { 49449dec922SGavin Shan pr_warn("%s: Failure %lld getting " 49549dec922SGavin Shan "PHB#%x-PE#%x state\n", 49649dec922SGavin Shan __func__, rc, 49749dec922SGavin Shan phb->hose->global_number, slave->pe_number); 49849dec922SGavin Shan return OPAL_EEH_STOPPED_TEMP_UNAVAIL; 49949dec922SGavin Shan } 50049dec922SGavin Shan 50149dec922SGavin Shan /* 50249dec922SGavin Shan * Override the result based on the ascending 50349dec922SGavin Shan * priority. 50449dec922SGavin Shan */ 50549dec922SGavin Shan if (fstate > state) 50649dec922SGavin Shan state = fstate; 50749dec922SGavin Shan } 50849dec922SGavin Shan 50949dec922SGavin Shan return state; 51049dec922SGavin Shan } 51149dec922SGavin Shan 512184cd4a3SBenjamin Herrenschmidt /* Currently those 2 are only used when MSIs are enabled, this will change 513184cd4a3SBenjamin Herrenschmidt * but in the meantime, we need to protect them to avoid warnings 514184cd4a3SBenjamin Herrenschmidt */ 515184cd4a3SBenjamin Herrenschmidt #ifdef CONFIG_PCI_MSI 516cad5cef6SGreg Kroah-Hartman static struct pnv_ioda_pe *pnv_ioda_get_pe(struct pci_dev *dev) 517184cd4a3SBenjamin Herrenschmidt { 518184cd4a3SBenjamin Herrenschmidt struct pci_controller *hose = pci_bus_to_host(dev->bus); 519184cd4a3SBenjamin Herrenschmidt struct pnv_phb *phb = hose->private_data; 520b72c1f65SBenjamin Herrenschmidt struct pci_dn *pdn = pci_get_pdn(dev); 521184cd4a3SBenjamin Herrenschmidt 522184cd4a3SBenjamin Herrenschmidt if (!pdn) 523184cd4a3SBenjamin Herrenschmidt return NULL; 524184cd4a3SBenjamin Herrenschmidt if (pdn->pe_number == IODA_INVALID_PE) 525184cd4a3SBenjamin Herrenschmidt return NULL; 526184cd4a3SBenjamin Herrenschmidt return &phb->ioda.pe_array[pdn->pe_number]; 527184cd4a3SBenjamin Herrenschmidt } 528184cd4a3SBenjamin Herrenschmidt #endif /* CONFIG_PCI_MSI */ 529184cd4a3SBenjamin Herrenschmidt 530b131a842SGavin Shan static int pnv_ioda_set_one_peltv(struct pnv_phb *phb, 531b131a842SGavin Shan struct pnv_ioda_pe *parent, 532b131a842SGavin Shan struct pnv_ioda_pe *child, 533b131a842SGavin Shan bool is_add) 534b131a842SGavin Shan { 535b131a842SGavin Shan const char *desc = is_add ? "adding" : "removing"; 536b131a842SGavin Shan uint8_t op = is_add ? OPAL_ADD_PE_TO_DOMAIN : 537b131a842SGavin Shan OPAL_REMOVE_PE_FROM_DOMAIN; 538b131a842SGavin Shan struct pnv_ioda_pe *slave; 539b131a842SGavin Shan long rc; 540b131a842SGavin Shan 541b131a842SGavin Shan /* Parent PE affects child PE */ 542b131a842SGavin Shan rc = opal_pci_set_peltv(phb->opal_id, parent->pe_number, 543b131a842SGavin Shan child->pe_number, op); 544b131a842SGavin Shan if (rc != OPAL_SUCCESS) { 545b131a842SGavin Shan pe_warn(child, "OPAL error %ld %s to parent PELTV\n", 546b131a842SGavin Shan rc, desc); 547b131a842SGavin Shan return -ENXIO; 548b131a842SGavin Shan } 549b131a842SGavin Shan 550b131a842SGavin Shan if (!(child->flags & PNV_IODA_PE_MASTER)) 551b131a842SGavin Shan return 0; 552b131a842SGavin Shan 553b131a842SGavin Shan /* Compound case: parent PE affects slave PEs */ 554b131a842SGavin Shan list_for_each_entry(slave, &child->slaves, list) { 555b131a842SGavin Shan rc = opal_pci_set_peltv(phb->opal_id, parent->pe_number, 556b131a842SGavin Shan slave->pe_number, op); 557b131a842SGavin Shan if (rc != OPAL_SUCCESS) { 558b131a842SGavin Shan pe_warn(slave, "OPAL error %ld %s to parent PELTV\n", 559b131a842SGavin Shan rc, desc); 560b131a842SGavin Shan return -ENXIO; 561b131a842SGavin Shan } 562b131a842SGavin Shan } 563b131a842SGavin Shan 564b131a842SGavin Shan return 0; 565b131a842SGavin Shan } 566b131a842SGavin Shan 567b131a842SGavin Shan static int pnv_ioda_set_peltv(struct pnv_phb *phb, 568b131a842SGavin Shan struct pnv_ioda_pe *pe, 569b131a842SGavin Shan bool is_add) 570b131a842SGavin Shan { 571b131a842SGavin Shan struct pnv_ioda_pe *slave; 572b131a842SGavin Shan struct pci_dev *pdev; 573b131a842SGavin Shan int ret; 574b131a842SGavin Shan 575b131a842SGavin Shan /* 576b131a842SGavin Shan * Clear PE frozen state. If it's master PE, we need 577b131a842SGavin Shan * clear slave PE frozen state as well. 578b131a842SGavin Shan */ 579b131a842SGavin Shan if (is_add) { 580b131a842SGavin Shan opal_pci_eeh_freeze_clear(phb->opal_id, pe->pe_number, 581b131a842SGavin Shan OPAL_EEH_ACTION_CLEAR_FREEZE_ALL); 582b131a842SGavin Shan if (pe->flags & PNV_IODA_PE_MASTER) { 583b131a842SGavin Shan list_for_each_entry(slave, &pe->slaves, list) 584b131a842SGavin Shan opal_pci_eeh_freeze_clear(phb->opal_id, 585b131a842SGavin Shan slave->pe_number, 586b131a842SGavin Shan OPAL_EEH_ACTION_CLEAR_FREEZE_ALL); 587b131a842SGavin Shan } 588b131a842SGavin Shan } 589b131a842SGavin Shan 590b131a842SGavin Shan /* 591b131a842SGavin Shan * Associate PE in PELT. We need add the PE into the 592b131a842SGavin Shan * corresponding PELT-V as well. Otherwise, the error 593b131a842SGavin Shan * originated from the PE might contribute to other 594b131a842SGavin Shan * PEs. 595b131a842SGavin Shan */ 596b131a842SGavin Shan ret = pnv_ioda_set_one_peltv(phb, pe, pe, is_add); 597b131a842SGavin Shan if (ret) 598b131a842SGavin Shan return ret; 599b131a842SGavin Shan 600b131a842SGavin Shan /* For compound PEs, any one affects all of them */ 601b131a842SGavin Shan if (pe->flags & PNV_IODA_PE_MASTER) { 602b131a842SGavin Shan list_for_each_entry(slave, &pe->slaves, list) { 603b131a842SGavin Shan ret = pnv_ioda_set_one_peltv(phb, slave, pe, is_add); 604b131a842SGavin Shan if (ret) 605b131a842SGavin Shan return ret; 606b131a842SGavin Shan } 607b131a842SGavin Shan } 608b131a842SGavin Shan 609b131a842SGavin Shan if (pe->flags & (PNV_IODA_PE_BUS_ALL | PNV_IODA_PE_BUS)) 610b131a842SGavin Shan pdev = pe->pbus->self; 611b131a842SGavin Shan else 612b131a842SGavin Shan pdev = pe->pdev->bus->self; 613b131a842SGavin Shan while (pdev) { 614b131a842SGavin Shan struct pci_dn *pdn = pci_get_pdn(pdev); 615b131a842SGavin Shan struct pnv_ioda_pe *parent; 616b131a842SGavin Shan 617b131a842SGavin Shan if (pdn && pdn->pe_number != IODA_INVALID_PE) { 618b131a842SGavin Shan parent = &phb->ioda.pe_array[pdn->pe_number]; 619b131a842SGavin Shan ret = pnv_ioda_set_one_peltv(phb, parent, pe, is_add); 620b131a842SGavin Shan if (ret) 621b131a842SGavin Shan return ret; 622b131a842SGavin Shan } 623b131a842SGavin Shan 624b131a842SGavin Shan pdev = pdev->bus->self; 625b131a842SGavin Shan } 626b131a842SGavin Shan 627b131a842SGavin Shan return 0; 628b131a842SGavin Shan } 629b131a842SGavin Shan 630cad5cef6SGreg Kroah-Hartman static int pnv_ioda_configure_pe(struct pnv_phb *phb, struct pnv_ioda_pe *pe) 631184cd4a3SBenjamin Herrenschmidt { 632184cd4a3SBenjamin Herrenschmidt struct pci_dev *parent; 633184cd4a3SBenjamin Herrenschmidt uint8_t bcomp, dcomp, fcomp; 634184cd4a3SBenjamin Herrenschmidt long rc, rid_end, rid; 635184cd4a3SBenjamin Herrenschmidt 636184cd4a3SBenjamin Herrenschmidt /* Bus validation ? */ 637184cd4a3SBenjamin Herrenschmidt if (pe->pbus) { 638184cd4a3SBenjamin Herrenschmidt int count; 639184cd4a3SBenjamin Herrenschmidt 640184cd4a3SBenjamin Herrenschmidt dcomp = OPAL_IGNORE_RID_DEVICE_NUMBER; 641184cd4a3SBenjamin Herrenschmidt fcomp = OPAL_IGNORE_RID_FUNCTION_NUMBER; 642184cd4a3SBenjamin Herrenschmidt parent = pe->pbus->self; 643fb446ad0SGavin Shan if (pe->flags & PNV_IODA_PE_BUS_ALL) 644b918c62eSYinghai Lu count = pe->pbus->busn_res.end - pe->pbus->busn_res.start + 1; 645fb446ad0SGavin Shan else 646fb446ad0SGavin Shan count = 1; 647fb446ad0SGavin Shan 648184cd4a3SBenjamin Herrenschmidt switch(count) { 649184cd4a3SBenjamin Herrenschmidt case 1: bcomp = OpalPciBusAll; break; 650184cd4a3SBenjamin Herrenschmidt case 2: bcomp = OpalPciBus7Bits; break; 651184cd4a3SBenjamin Herrenschmidt case 4: bcomp = OpalPciBus6Bits; break; 652184cd4a3SBenjamin Herrenschmidt case 8: bcomp = OpalPciBus5Bits; break; 653184cd4a3SBenjamin Herrenschmidt case 16: bcomp = OpalPciBus4Bits; break; 654184cd4a3SBenjamin Herrenschmidt case 32: bcomp = OpalPciBus3Bits; break; 655184cd4a3SBenjamin Herrenschmidt default: 656184cd4a3SBenjamin Herrenschmidt pr_err("%s: Number of subordinate busses %d" 657184cd4a3SBenjamin Herrenschmidt " unsupported\n", 658184cd4a3SBenjamin Herrenschmidt pci_name(pe->pbus->self), count); 659184cd4a3SBenjamin Herrenschmidt /* Do an exact match only */ 660184cd4a3SBenjamin Herrenschmidt bcomp = OpalPciBusAll; 661184cd4a3SBenjamin Herrenschmidt } 662184cd4a3SBenjamin Herrenschmidt rid_end = pe->rid + (count << 8); 663184cd4a3SBenjamin Herrenschmidt } else { 664184cd4a3SBenjamin Herrenschmidt parent = pe->pdev->bus->self; 665184cd4a3SBenjamin Herrenschmidt bcomp = OpalPciBusAll; 666184cd4a3SBenjamin Herrenschmidt dcomp = OPAL_COMPARE_RID_DEVICE_NUMBER; 667184cd4a3SBenjamin Herrenschmidt fcomp = OPAL_COMPARE_RID_FUNCTION_NUMBER; 668184cd4a3SBenjamin Herrenschmidt rid_end = pe->rid + 1; 669184cd4a3SBenjamin Herrenschmidt } 670184cd4a3SBenjamin Herrenschmidt 671631ad691SGavin Shan /* 672631ad691SGavin Shan * Associate PE in PELT. We need add the PE into the 673631ad691SGavin Shan * corresponding PELT-V as well. Otherwise, the error 674631ad691SGavin Shan * originated from the PE might contribute to other 675631ad691SGavin Shan * PEs. 676631ad691SGavin Shan */ 677184cd4a3SBenjamin Herrenschmidt rc = opal_pci_set_pe(phb->opal_id, pe->pe_number, pe->rid, 678184cd4a3SBenjamin Herrenschmidt bcomp, dcomp, fcomp, OPAL_MAP_PE); 679184cd4a3SBenjamin Herrenschmidt if (rc) { 680184cd4a3SBenjamin Herrenschmidt pe_err(pe, "OPAL error %ld trying to setup PELT table\n", rc); 681184cd4a3SBenjamin Herrenschmidt return -ENXIO; 682184cd4a3SBenjamin Herrenschmidt } 683631ad691SGavin Shan 684b131a842SGavin Shan /* Configure PELTV */ 685b131a842SGavin Shan pnv_ioda_set_peltv(phb, pe, true); 686184cd4a3SBenjamin Herrenschmidt 687184cd4a3SBenjamin Herrenschmidt /* Setup reverse map */ 688184cd4a3SBenjamin Herrenschmidt for (rid = pe->rid; rid < rid_end; rid++) 689184cd4a3SBenjamin Herrenschmidt phb->ioda.pe_rmap[rid] = pe->pe_number; 690184cd4a3SBenjamin Herrenschmidt 691184cd4a3SBenjamin Herrenschmidt /* Setup one MVTs on IODA1 */ 6924773f76bSGavin Shan if (phb->type != PNV_PHB_IODA1) { 6934773f76bSGavin Shan pe->mve_number = 0; 6944773f76bSGavin Shan goto out; 6954773f76bSGavin Shan } 6964773f76bSGavin Shan 697184cd4a3SBenjamin Herrenschmidt pe->mve_number = pe->pe_number; 6984773f76bSGavin Shan rc = opal_pci_set_mve(phb->opal_id, pe->mve_number, pe->pe_number); 6994773f76bSGavin Shan if (rc != OPAL_SUCCESS) { 700184cd4a3SBenjamin Herrenschmidt pe_err(pe, "OPAL error %ld setting up MVE %d\n", 701184cd4a3SBenjamin Herrenschmidt rc, pe->mve_number); 702184cd4a3SBenjamin Herrenschmidt pe->mve_number = -1; 703184cd4a3SBenjamin Herrenschmidt } else { 704184cd4a3SBenjamin Herrenschmidt rc = opal_pci_set_mve_enable(phb->opal_id, 705cee72d5bSBenjamin Herrenschmidt pe->mve_number, OPAL_ENABLE_MVE); 706184cd4a3SBenjamin Herrenschmidt if (rc) { 707184cd4a3SBenjamin Herrenschmidt pe_err(pe, "OPAL error %ld enabling MVE %d\n", 708184cd4a3SBenjamin Herrenschmidt rc, pe->mve_number); 709184cd4a3SBenjamin Herrenschmidt pe->mve_number = -1; 710184cd4a3SBenjamin Herrenschmidt } 711184cd4a3SBenjamin Herrenschmidt } 712184cd4a3SBenjamin Herrenschmidt 7134773f76bSGavin Shan out: 714184cd4a3SBenjamin Herrenschmidt return 0; 715184cd4a3SBenjamin Herrenschmidt } 716184cd4a3SBenjamin Herrenschmidt 717cad5cef6SGreg Kroah-Hartman static void pnv_ioda_link_pe_by_weight(struct pnv_phb *phb, 718184cd4a3SBenjamin Herrenschmidt struct pnv_ioda_pe *pe) 719184cd4a3SBenjamin Herrenschmidt { 720184cd4a3SBenjamin Herrenschmidt struct pnv_ioda_pe *lpe; 721184cd4a3SBenjamin Herrenschmidt 7227ebdf956SGavin Shan list_for_each_entry(lpe, &phb->ioda.pe_dma_list, dma_link) { 723184cd4a3SBenjamin Herrenschmidt if (lpe->dma_weight < pe->dma_weight) { 7247ebdf956SGavin Shan list_add_tail(&pe->dma_link, &lpe->dma_link); 725184cd4a3SBenjamin Herrenschmidt return; 726184cd4a3SBenjamin Herrenschmidt } 727184cd4a3SBenjamin Herrenschmidt } 7287ebdf956SGavin Shan list_add_tail(&pe->dma_link, &phb->ioda.pe_dma_list); 729184cd4a3SBenjamin Herrenschmidt } 730184cd4a3SBenjamin Herrenschmidt 731184cd4a3SBenjamin Herrenschmidt static unsigned int pnv_ioda_dma_weight(struct pci_dev *dev) 732184cd4a3SBenjamin Herrenschmidt { 733184cd4a3SBenjamin Herrenschmidt /* This is quite simplistic. The "base" weight of a device 734184cd4a3SBenjamin Herrenschmidt * is 10. 0 means no DMA is to be accounted for it. 735184cd4a3SBenjamin Herrenschmidt */ 736184cd4a3SBenjamin Herrenschmidt 737184cd4a3SBenjamin Herrenschmidt /* If it's a bridge, no DMA */ 738184cd4a3SBenjamin Herrenschmidt if (dev->hdr_type != PCI_HEADER_TYPE_NORMAL) 739184cd4a3SBenjamin Herrenschmidt return 0; 740184cd4a3SBenjamin Herrenschmidt 741184cd4a3SBenjamin Herrenschmidt /* Reduce the weight of slow USB controllers */ 742184cd4a3SBenjamin Herrenschmidt if (dev->class == PCI_CLASS_SERIAL_USB_UHCI || 743184cd4a3SBenjamin Herrenschmidt dev->class == PCI_CLASS_SERIAL_USB_OHCI || 744184cd4a3SBenjamin Herrenschmidt dev->class == PCI_CLASS_SERIAL_USB_EHCI) 745184cd4a3SBenjamin Herrenschmidt return 3; 746184cd4a3SBenjamin Herrenschmidt 747184cd4a3SBenjamin Herrenschmidt /* Increase the weight of RAID (includes Obsidian) */ 748184cd4a3SBenjamin Herrenschmidt if ((dev->class >> 8) == PCI_CLASS_STORAGE_RAID) 749184cd4a3SBenjamin Herrenschmidt return 15; 750184cd4a3SBenjamin Herrenschmidt 751184cd4a3SBenjamin Herrenschmidt /* Default */ 752184cd4a3SBenjamin Herrenschmidt return 10; 753184cd4a3SBenjamin Herrenschmidt } 754184cd4a3SBenjamin Herrenschmidt 755fb446ad0SGavin Shan #if 0 756cad5cef6SGreg Kroah-Hartman static struct pnv_ioda_pe *pnv_ioda_setup_dev_PE(struct pci_dev *dev) 757184cd4a3SBenjamin Herrenschmidt { 758184cd4a3SBenjamin Herrenschmidt struct pci_controller *hose = pci_bus_to_host(dev->bus); 759184cd4a3SBenjamin Herrenschmidt struct pnv_phb *phb = hose->private_data; 760b72c1f65SBenjamin Herrenschmidt struct pci_dn *pdn = pci_get_pdn(dev); 761184cd4a3SBenjamin Herrenschmidt struct pnv_ioda_pe *pe; 762184cd4a3SBenjamin Herrenschmidt int pe_num; 763184cd4a3SBenjamin Herrenschmidt 764184cd4a3SBenjamin Herrenschmidt if (!pdn) { 765184cd4a3SBenjamin Herrenschmidt pr_err("%s: Device tree node not associated properly\n", 766184cd4a3SBenjamin Herrenschmidt pci_name(dev)); 767184cd4a3SBenjamin Herrenschmidt return NULL; 768184cd4a3SBenjamin Herrenschmidt } 769184cd4a3SBenjamin Herrenschmidt if (pdn->pe_number != IODA_INVALID_PE) 770184cd4a3SBenjamin Herrenschmidt return NULL; 771184cd4a3SBenjamin Herrenschmidt 772184cd4a3SBenjamin Herrenschmidt /* PE#0 has been pre-set */ 773184cd4a3SBenjamin Herrenschmidt if (dev->bus->number == 0) 774184cd4a3SBenjamin Herrenschmidt pe_num = 0; 775184cd4a3SBenjamin Herrenschmidt else 776184cd4a3SBenjamin Herrenschmidt pe_num = pnv_ioda_alloc_pe(phb); 777184cd4a3SBenjamin Herrenschmidt if (pe_num == IODA_INVALID_PE) { 778184cd4a3SBenjamin Herrenschmidt pr_warning("%s: Not enough PE# available, disabling device\n", 779184cd4a3SBenjamin Herrenschmidt pci_name(dev)); 780184cd4a3SBenjamin Herrenschmidt return NULL; 781184cd4a3SBenjamin Herrenschmidt } 782184cd4a3SBenjamin Herrenschmidt 783184cd4a3SBenjamin Herrenschmidt /* NOTE: We get only one ref to the pci_dev for the pdn, not for the 784184cd4a3SBenjamin Herrenschmidt * pointer in the PE data structure, both should be destroyed at the 785184cd4a3SBenjamin Herrenschmidt * same time. However, this needs to be looked at more closely again 786184cd4a3SBenjamin Herrenschmidt * once we actually start removing things (Hotplug, SR-IOV, ...) 787184cd4a3SBenjamin Herrenschmidt * 788184cd4a3SBenjamin Herrenschmidt * At some point we want to remove the PDN completely anyways 789184cd4a3SBenjamin Herrenschmidt */ 790184cd4a3SBenjamin Herrenschmidt pe = &phb->ioda.pe_array[pe_num]; 791184cd4a3SBenjamin Herrenschmidt pci_dev_get(dev); 792184cd4a3SBenjamin Herrenschmidt pdn->pcidev = dev; 793184cd4a3SBenjamin Herrenschmidt pdn->pe_number = pe_num; 794184cd4a3SBenjamin Herrenschmidt pe->pdev = dev; 795184cd4a3SBenjamin Herrenschmidt pe->pbus = NULL; 796184cd4a3SBenjamin Herrenschmidt pe->tce32_seg = -1; 797184cd4a3SBenjamin Herrenschmidt pe->mve_number = -1; 798184cd4a3SBenjamin Herrenschmidt pe->rid = dev->bus->number << 8 | pdn->devfn; 799184cd4a3SBenjamin Herrenschmidt 800184cd4a3SBenjamin Herrenschmidt pe_info(pe, "Associated device to PE\n"); 801184cd4a3SBenjamin Herrenschmidt 802184cd4a3SBenjamin Herrenschmidt if (pnv_ioda_configure_pe(phb, pe)) { 803184cd4a3SBenjamin Herrenschmidt /* XXX What do we do here ? */ 804184cd4a3SBenjamin Herrenschmidt if (pe_num) 805184cd4a3SBenjamin Herrenschmidt pnv_ioda_free_pe(phb, pe_num); 806184cd4a3SBenjamin Herrenschmidt pdn->pe_number = IODA_INVALID_PE; 807184cd4a3SBenjamin Herrenschmidt pe->pdev = NULL; 808184cd4a3SBenjamin Herrenschmidt pci_dev_put(dev); 809184cd4a3SBenjamin Herrenschmidt return NULL; 810184cd4a3SBenjamin Herrenschmidt } 811184cd4a3SBenjamin Herrenschmidt 812184cd4a3SBenjamin Herrenschmidt /* Assign a DMA weight to the device */ 813184cd4a3SBenjamin Herrenschmidt pe->dma_weight = pnv_ioda_dma_weight(dev); 814184cd4a3SBenjamin Herrenschmidt if (pe->dma_weight != 0) { 815184cd4a3SBenjamin Herrenschmidt phb->ioda.dma_weight += pe->dma_weight; 816184cd4a3SBenjamin Herrenschmidt phb->ioda.dma_pe_count++; 817184cd4a3SBenjamin Herrenschmidt } 818184cd4a3SBenjamin Herrenschmidt 819184cd4a3SBenjamin Herrenschmidt /* Link the PE */ 820184cd4a3SBenjamin Herrenschmidt pnv_ioda_link_pe_by_weight(phb, pe); 821184cd4a3SBenjamin Herrenschmidt 822184cd4a3SBenjamin Herrenschmidt return pe; 823184cd4a3SBenjamin Herrenschmidt } 824fb446ad0SGavin Shan #endif /* Useful for SRIOV case */ 825184cd4a3SBenjamin Herrenschmidt 826184cd4a3SBenjamin Herrenschmidt static void pnv_ioda_setup_same_PE(struct pci_bus *bus, struct pnv_ioda_pe *pe) 827184cd4a3SBenjamin Herrenschmidt { 828184cd4a3SBenjamin Herrenschmidt struct pci_dev *dev; 829184cd4a3SBenjamin Herrenschmidt 830184cd4a3SBenjamin Herrenschmidt list_for_each_entry(dev, &bus->devices, bus_list) { 831b72c1f65SBenjamin Herrenschmidt struct pci_dn *pdn = pci_get_pdn(dev); 832184cd4a3SBenjamin Herrenschmidt 833184cd4a3SBenjamin Herrenschmidt if (pdn == NULL) { 834184cd4a3SBenjamin Herrenschmidt pr_warn("%s: No device node associated with device !\n", 835184cd4a3SBenjamin Herrenschmidt pci_name(dev)); 836184cd4a3SBenjamin Herrenschmidt continue; 837184cd4a3SBenjamin Herrenschmidt } 838184cd4a3SBenjamin Herrenschmidt pdn->pcidev = dev; 839184cd4a3SBenjamin Herrenschmidt pdn->pe_number = pe->pe_number; 840184cd4a3SBenjamin Herrenschmidt pe->dma_weight += pnv_ioda_dma_weight(dev); 841fb446ad0SGavin Shan if ((pe->flags & PNV_IODA_PE_BUS_ALL) && dev->subordinate) 842184cd4a3SBenjamin Herrenschmidt pnv_ioda_setup_same_PE(dev->subordinate, pe); 843184cd4a3SBenjamin Herrenschmidt } 844184cd4a3SBenjamin Herrenschmidt } 845184cd4a3SBenjamin Herrenschmidt 846fb446ad0SGavin Shan /* 847fb446ad0SGavin Shan * There're 2 types of PCI bus sensitive PEs: One that is compromised of 848fb446ad0SGavin Shan * single PCI bus. Another one that contains the primary PCI bus and its 849fb446ad0SGavin Shan * subordinate PCI devices and buses. The second type of PE is normally 850fb446ad0SGavin Shan * orgiriated by PCIe-to-PCI bridge or PLX switch downstream ports. 851fb446ad0SGavin Shan */ 852cad5cef6SGreg Kroah-Hartman static void pnv_ioda_setup_bus_PE(struct pci_bus *bus, int all) 853184cd4a3SBenjamin Herrenschmidt { 854fb446ad0SGavin Shan struct pci_controller *hose = pci_bus_to_host(bus); 855184cd4a3SBenjamin Herrenschmidt struct pnv_phb *phb = hose->private_data; 856184cd4a3SBenjamin Herrenschmidt struct pnv_ioda_pe *pe; 857262af557SGuo Chao int pe_num = IODA_INVALID_PE; 858184cd4a3SBenjamin Herrenschmidt 859262af557SGuo Chao /* Check if PE is determined by M64 */ 860262af557SGuo Chao if (phb->pick_m64_pe) 861262af557SGuo Chao pe_num = phb->pick_m64_pe(phb, bus, all); 862262af557SGuo Chao 863262af557SGuo Chao /* The PE number isn't pinned by M64 */ 864262af557SGuo Chao if (pe_num == IODA_INVALID_PE) 865184cd4a3SBenjamin Herrenschmidt pe_num = pnv_ioda_alloc_pe(phb); 866262af557SGuo Chao 867184cd4a3SBenjamin Herrenschmidt if (pe_num == IODA_INVALID_PE) { 868fb446ad0SGavin Shan pr_warning("%s: Not enough PE# available for PCI bus %04x:%02x\n", 869fb446ad0SGavin Shan __func__, pci_domain_nr(bus), bus->number); 870184cd4a3SBenjamin Herrenschmidt return; 871184cd4a3SBenjamin Herrenschmidt } 872184cd4a3SBenjamin Herrenschmidt 873184cd4a3SBenjamin Herrenschmidt pe = &phb->ioda.pe_array[pe_num]; 874262af557SGuo Chao pe->flags |= (all ? PNV_IODA_PE_BUS_ALL : PNV_IODA_PE_BUS); 875184cd4a3SBenjamin Herrenschmidt pe->pbus = bus; 876184cd4a3SBenjamin Herrenschmidt pe->pdev = NULL; 877184cd4a3SBenjamin Herrenschmidt pe->tce32_seg = -1; 878184cd4a3SBenjamin Herrenschmidt pe->mve_number = -1; 879b918c62eSYinghai Lu pe->rid = bus->busn_res.start << 8; 880184cd4a3SBenjamin Herrenschmidt pe->dma_weight = 0; 881184cd4a3SBenjamin Herrenschmidt 882fb446ad0SGavin Shan if (all) 883fb446ad0SGavin Shan pe_info(pe, "Secondary bus %d..%d associated with PE#%d\n", 884fb446ad0SGavin Shan bus->busn_res.start, bus->busn_res.end, pe_num); 885fb446ad0SGavin Shan else 886fb446ad0SGavin Shan pe_info(pe, "Secondary bus %d associated with PE#%d\n", 887fb446ad0SGavin Shan bus->busn_res.start, pe_num); 888184cd4a3SBenjamin Herrenschmidt 889184cd4a3SBenjamin Herrenschmidt if (pnv_ioda_configure_pe(phb, pe)) { 890184cd4a3SBenjamin Herrenschmidt /* XXX What do we do here ? */ 891184cd4a3SBenjamin Herrenschmidt if (pe_num) 892184cd4a3SBenjamin Herrenschmidt pnv_ioda_free_pe(phb, pe_num); 893184cd4a3SBenjamin Herrenschmidt pe->pbus = NULL; 894184cd4a3SBenjamin Herrenschmidt return; 895184cd4a3SBenjamin Herrenschmidt } 896184cd4a3SBenjamin Herrenschmidt 897184cd4a3SBenjamin Herrenschmidt /* Associate it with all child devices */ 898184cd4a3SBenjamin Herrenschmidt pnv_ioda_setup_same_PE(bus, pe); 899184cd4a3SBenjamin Herrenschmidt 9007ebdf956SGavin Shan /* Put PE to the list */ 9017ebdf956SGavin Shan list_add_tail(&pe->list, &phb->ioda.pe_list); 9027ebdf956SGavin Shan 903184cd4a3SBenjamin Herrenschmidt /* Account for one DMA PE if at least one DMA capable device exist 904184cd4a3SBenjamin Herrenschmidt * below the bridge 905184cd4a3SBenjamin Herrenschmidt */ 906184cd4a3SBenjamin Herrenschmidt if (pe->dma_weight != 0) { 907184cd4a3SBenjamin Herrenschmidt phb->ioda.dma_weight += pe->dma_weight; 908184cd4a3SBenjamin Herrenschmidt phb->ioda.dma_pe_count++; 909184cd4a3SBenjamin Herrenschmidt } 910184cd4a3SBenjamin Herrenschmidt 911184cd4a3SBenjamin Herrenschmidt /* Link the PE */ 912184cd4a3SBenjamin Herrenschmidt pnv_ioda_link_pe_by_weight(phb, pe); 913184cd4a3SBenjamin Herrenschmidt } 914184cd4a3SBenjamin Herrenschmidt 915cad5cef6SGreg Kroah-Hartman static void pnv_ioda_setup_PEs(struct pci_bus *bus) 916184cd4a3SBenjamin Herrenschmidt { 917184cd4a3SBenjamin Herrenschmidt struct pci_dev *dev; 918fb446ad0SGavin Shan 919fb446ad0SGavin Shan pnv_ioda_setup_bus_PE(bus, 0); 920184cd4a3SBenjamin Herrenschmidt 921184cd4a3SBenjamin Herrenschmidt list_for_each_entry(dev, &bus->devices, bus_list) { 922fb446ad0SGavin Shan if (dev->subordinate) { 92362f87c0eSYijing Wang if (pci_pcie_type(dev) == PCI_EXP_TYPE_PCI_BRIDGE) 924fb446ad0SGavin Shan pnv_ioda_setup_bus_PE(dev->subordinate, 1); 925fb446ad0SGavin Shan else 926184cd4a3SBenjamin Herrenschmidt pnv_ioda_setup_PEs(dev->subordinate); 927184cd4a3SBenjamin Herrenschmidt } 928184cd4a3SBenjamin Herrenschmidt } 929fb446ad0SGavin Shan } 930fb446ad0SGavin Shan 931fb446ad0SGavin Shan /* 932fb446ad0SGavin Shan * Configure PEs so that the downstream PCI buses and devices 933fb446ad0SGavin Shan * could have their associated PE#. Unfortunately, we didn't 934fb446ad0SGavin Shan * figure out the way to identify the PLX bridge yet. So we 935fb446ad0SGavin Shan * simply put the PCI bus and the subordinate behind the root 936fb446ad0SGavin Shan * port to PE# here. The game rule here is expected to be changed 937fb446ad0SGavin Shan * as soon as we can detected PLX bridge correctly. 938fb446ad0SGavin Shan */ 939cad5cef6SGreg Kroah-Hartman static void pnv_pci_ioda_setup_PEs(void) 940fb446ad0SGavin Shan { 941fb446ad0SGavin Shan struct pci_controller *hose, *tmp; 942262af557SGuo Chao struct pnv_phb *phb; 943fb446ad0SGavin Shan 944fb446ad0SGavin Shan list_for_each_entry_safe(hose, tmp, &hose_list, list_node) { 945262af557SGuo Chao phb = hose->private_data; 946262af557SGuo Chao 947262af557SGuo Chao /* M64 layout might affect PE allocation */ 9485ef73567SGavin Shan if (phb->reserve_m64_pe) 9495ef73567SGavin Shan phb->reserve_m64_pe(phb); 950262af557SGuo Chao 951fb446ad0SGavin Shan pnv_ioda_setup_PEs(hose->bus); 952fb446ad0SGavin Shan } 953fb446ad0SGavin Shan } 954184cd4a3SBenjamin Herrenschmidt 955959c9bddSGavin Shan static void pnv_pci_ioda_dma_dev_setup(struct pnv_phb *phb, struct pci_dev *pdev) 956184cd4a3SBenjamin Herrenschmidt { 957b72c1f65SBenjamin Herrenschmidt struct pci_dn *pdn = pci_get_pdn(pdev); 958959c9bddSGavin Shan struct pnv_ioda_pe *pe; 959184cd4a3SBenjamin Herrenschmidt 960959c9bddSGavin Shan /* 961959c9bddSGavin Shan * The function can be called while the PE# 962959c9bddSGavin Shan * hasn't been assigned. Do nothing for the 963959c9bddSGavin Shan * case. 964959c9bddSGavin Shan */ 965959c9bddSGavin Shan if (!pdn || pdn->pe_number == IODA_INVALID_PE) 966959c9bddSGavin Shan return; 967184cd4a3SBenjamin Herrenschmidt 968959c9bddSGavin Shan pe = &phb->ioda.pe_array[pdn->pe_number]; 969cd15b048SBenjamin Herrenschmidt WARN_ON(get_dma_ops(&pdev->dev) != &dma_iommu_ops); 970763fe0adSGavin Shan set_iommu_table_base_and_group(&pdev->dev, &pe->tce32_table); 971184cd4a3SBenjamin Herrenschmidt } 972184cd4a3SBenjamin Herrenschmidt 973cd15b048SBenjamin Herrenschmidt static int pnv_pci_ioda_dma_set_mask(struct pnv_phb *phb, 974cd15b048SBenjamin Herrenschmidt struct pci_dev *pdev, u64 dma_mask) 975cd15b048SBenjamin Herrenschmidt { 976cd15b048SBenjamin Herrenschmidt struct pci_dn *pdn = pci_get_pdn(pdev); 977cd15b048SBenjamin Herrenschmidt struct pnv_ioda_pe *pe; 978cd15b048SBenjamin Herrenschmidt uint64_t top; 979cd15b048SBenjamin Herrenschmidt bool bypass = false; 980cd15b048SBenjamin Herrenschmidt 981cd15b048SBenjamin Herrenschmidt if (WARN_ON(!pdn || pdn->pe_number == IODA_INVALID_PE)) 982cd15b048SBenjamin Herrenschmidt return -ENODEV;; 983cd15b048SBenjamin Herrenschmidt 984cd15b048SBenjamin Herrenschmidt pe = &phb->ioda.pe_array[pdn->pe_number]; 985cd15b048SBenjamin Herrenschmidt if (pe->tce_bypass_enabled) { 986cd15b048SBenjamin Herrenschmidt top = pe->tce_bypass_base + memblock_end_of_DRAM() - 1; 987cd15b048SBenjamin Herrenschmidt bypass = (dma_mask >= top); 988cd15b048SBenjamin Herrenschmidt } 989cd15b048SBenjamin Herrenschmidt 990cd15b048SBenjamin Herrenschmidt if (bypass) { 991cd15b048SBenjamin Herrenschmidt dev_info(&pdev->dev, "Using 64-bit DMA iommu bypass\n"); 992cd15b048SBenjamin Herrenschmidt set_dma_ops(&pdev->dev, &dma_direct_ops); 993cd15b048SBenjamin Herrenschmidt set_dma_offset(&pdev->dev, pe->tce_bypass_base); 994cd15b048SBenjamin Herrenschmidt } else { 995cd15b048SBenjamin Herrenschmidt dev_info(&pdev->dev, "Using 32-bit DMA via iommu\n"); 996cd15b048SBenjamin Herrenschmidt set_dma_ops(&pdev->dev, &dma_iommu_ops); 997cd15b048SBenjamin Herrenschmidt set_iommu_table_base(&pdev->dev, &pe->tce32_table); 998cd15b048SBenjamin Herrenschmidt } 999a32305bfSBrian W Hart *pdev->dev.dma_mask = dma_mask; 1000cd15b048SBenjamin Herrenschmidt return 0; 1001cd15b048SBenjamin Herrenschmidt } 1002cd15b048SBenjamin Herrenschmidt 1003fe7e85c6SGavin Shan static u64 pnv_pci_ioda_dma_get_required_mask(struct pnv_phb *phb, 1004fe7e85c6SGavin Shan struct pci_dev *pdev) 1005fe7e85c6SGavin Shan { 1006fe7e85c6SGavin Shan struct pci_dn *pdn = pci_get_pdn(pdev); 1007fe7e85c6SGavin Shan struct pnv_ioda_pe *pe; 1008fe7e85c6SGavin Shan u64 end, mask; 1009fe7e85c6SGavin Shan 1010fe7e85c6SGavin Shan if (WARN_ON(!pdn || pdn->pe_number == IODA_INVALID_PE)) 1011fe7e85c6SGavin Shan return 0; 1012fe7e85c6SGavin Shan 1013fe7e85c6SGavin Shan pe = &phb->ioda.pe_array[pdn->pe_number]; 1014fe7e85c6SGavin Shan if (!pe->tce_bypass_enabled) 1015fe7e85c6SGavin Shan return __dma_get_required_mask(&pdev->dev); 1016fe7e85c6SGavin Shan 1017fe7e85c6SGavin Shan 1018fe7e85c6SGavin Shan end = pe->tce_bypass_base + memblock_end_of_DRAM(); 1019fe7e85c6SGavin Shan mask = 1ULL << (fls64(end) - 1); 1020fe7e85c6SGavin Shan mask += mask - 1; 1021fe7e85c6SGavin Shan 1022fe7e85c6SGavin Shan return mask; 1023fe7e85c6SGavin Shan } 1024fe7e85c6SGavin Shan 1025dff4a39eSGavin Shan static void pnv_ioda_setup_bus_dma(struct pnv_ioda_pe *pe, 1026dff4a39eSGavin Shan struct pci_bus *bus, 1027dff4a39eSGavin Shan bool add_to_iommu_group) 102874251fe2SBenjamin Herrenschmidt { 102974251fe2SBenjamin Herrenschmidt struct pci_dev *dev; 103074251fe2SBenjamin Herrenschmidt 103174251fe2SBenjamin Herrenschmidt list_for_each_entry(dev, &bus->devices, bus_list) { 1032dff4a39eSGavin Shan if (add_to_iommu_group) 1033dff4a39eSGavin Shan set_iommu_table_base_and_group(&dev->dev, 1034dff4a39eSGavin Shan &pe->tce32_table); 1035dff4a39eSGavin Shan else 1036dff4a39eSGavin Shan set_iommu_table_base(&dev->dev, &pe->tce32_table); 1037dff4a39eSGavin Shan 103874251fe2SBenjamin Herrenschmidt if (dev->subordinate) 1039dff4a39eSGavin Shan pnv_ioda_setup_bus_dma(pe, dev->subordinate, 1040dff4a39eSGavin Shan add_to_iommu_group); 104174251fe2SBenjamin Herrenschmidt } 104274251fe2SBenjamin Herrenschmidt } 104374251fe2SBenjamin Herrenschmidt 10448e0a1611SAlexey Kardashevskiy static void pnv_pci_ioda1_tce_invalidate(struct pnv_ioda_pe *pe, 10458e0a1611SAlexey Kardashevskiy struct iommu_table *tbl, 10463ad26e5cSBenjamin Herrenschmidt __be64 *startp, __be64 *endp, bool rm) 10474cce9550SGavin Shan { 10483ad26e5cSBenjamin Herrenschmidt __be64 __iomem *invalidate = rm ? 10493ad26e5cSBenjamin Herrenschmidt (__be64 __iomem *)pe->tce_inval_reg_phys : 10503ad26e5cSBenjamin Herrenschmidt (__be64 __iomem *)tbl->it_index; 10514cce9550SGavin Shan unsigned long start, end, inc; 1052b0376c9bSAlexey Kardashevskiy const unsigned shift = tbl->it_page_shift; 10534cce9550SGavin Shan 10544cce9550SGavin Shan start = __pa(startp); 10554cce9550SGavin Shan end = __pa(endp); 10564cce9550SGavin Shan 10574cce9550SGavin Shan /* BML uses this case for p6/p7/galaxy2: Shift addr and put in node */ 10584cce9550SGavin Shan if (tbl->it_busno) { 1059b0376c9bSAlexey Kardashevskiy start <<= shift; 1060b0376c9bSAlexey Kardashevskiy end <<= shift; 1061b0376c9bSAlexey Kardashevskiy inc = 128ull << shift; 10624cce9550SGavin Shan start |= tbl->it_busno; 10634cce9550SGavin Shan end |= tbl->it_busno; 10644cce9550SGavin Shan } else if (tbl->it_type & TCE_PCI_SWINV_PAIR) { 10654cce9550SGavin Shan /* p7ioc-style invalidation, 2 TCEs per write */ 10664cce9550SGavin Shan start |= (1ull << 63); 10674cce9550SGavin Shan end |= (1ull << 63); 10684cce9550SGavin Shan inc = 16; 10694cce9550SGavin Shan } else { 10704cce9550SGavin Shan /* Default (older HW) */ 10714cce9550SGavin Shan inc = 128; 10724cce9550SGavin Shan } 10734cce9550SGavin Shan 10744cce9550SGavin Shan end |= inc - 1; /* round up end to be different than start */ 10754cce9550SGavin Shan 10764cce9550SGavin Shan mb(); /* Ensure above stores are visible */ 10774cce9550SGavin Shan while (start <= end) { 10788e0a1611SAlexey Kardashevskiy if (rm) 10793ad26e5cSBenjamin Herrenschmidt __raw_rm_writeq(cpu_to_be64(start), invalidate); 10808e0a1611SAlexey Kardashevskiy else 10813a1a4661SBenjamin Herrenschmidt __raw_writeq(cpu_to_be64(start), invalidate); 10824cce9550SGavin Shan start += inc; 10834cce9550SGavin Shan } 10844cce9550SGavin Shan 10854cce9550SGavin Shan /* 10864cce9550SGavin Shan * The iommu layer will do another mb() for us on build() 10874cce9550SGavin Shan * and we don't care on free() 10884cce9550SGavin Shan */ 10894cce9550SGavin Shan } 10904cce9550SGavin Shan 10914cce9550SGavin Shan static void pnv_pci_ioda2_tce_invalidate(struct pnv_ioda_pe *pe, 10924cce9550SGavin Shan struct iommu_table *tbl, 10933ad26e5cSBenjamin Herrenschmidt __be64 *startp, __be64 *endp, bool rm) 10944cce9550SGavin Shan { 10954cce9550SGavin Shan unsigned long start, end, inc; 10963ad26e5cSBenjamin Herrenschmidt __be64 __iomem *invalidate = rm ? 10973ad26e5cSBenjamin Herrenschmidt (__be64 __iomem *)pe->tce_inval_reg_phys : 10983ad26e5cSBenjamin Herrenschmidt (__be64 __iomem *)tbl->it_index; 1099b0376c9bSAlexey Kardashevskiy const unsigned shift = tbl->it_page_shift; 11004cce9550SGavin Shan 11014cce9550SGavin Shan /* We'll invalidate DMA address in PE scope */ 1102b0376c9bSAlexey Kardashevskiy start = 0x2ull << 60; 11034cce9550SGavin Shan start |= (pe->pe_number & 0xFF); 11044cce9550SGavin Shan end = start; 11054cce9550SGavin Shan 11064cce9550SGavin Shan /* Figure out the start, end and step */ 11074cce9550SGavin Shan inc = tbl->it_offset + (((u64)startp - tbl->it_base) / sizeof(u64)); 1108b0376c9bSAlexey Kardashevskiy start |= (inc << shift); 11094cce9550SGavin Shan inc = tbl->it_offset + (((u64)endp - tbl->it_base) / sizeof(u64)); 1110b0376c9bSAlexey Kardashevskiy end |= (inc << shift); 1111b0376c9bSAlexey Kardashevskiy inc = (0x1ull << shift); 11124cce9550SGavin Shan mb(); 11134cce9550SGavin Shan 11144cce9550SGavin Shan while (start <= end) { 11158e0a1611SAlexey Kardashevskiy if (rm) 11163ad26e5cSBenjamin Herrenschmidt __raw_rm_writeq(cpu_to_be64(start), invalidate); 11178e0a1611SAlexey Kardashevskiy else 11183a1a4661SBenjamin Herrenschmidt __raw_writeq(cpu_to_be64(start), invalidate); 11194cce9550SGavin Shan start += inc; 11204cce9550SGavin Shan } 11214cce9550SGavin Shan } 11224cce9550SGavin Shan 11234cce9550SGavin Shan void pnv_pci_ioda_tce_invalidate(struct iommu_table *tbl, 11243ad26e5cSBenjamin Herrenschmidt __be64 *startp, __be64 *endp, bool rm) 11254cce9550SGavin Shan { 11264cce9550SGavin Shan struct pnv_ioda_pe *pe = container_of(tbl, struct pnv_ioda_pe, 11274cce9550SGavin Shan tce32_table); 11284cce9550SGavin Shan struct pnv_phb *phb = pe->phb; 11294cce9550SGavin Shan 11304cce9550SGavin Shan if (phb->type == PNV_PHB_IODA1) 11318e0a1611SAlexey Kardashevskiy pnv_pci_ioda1_tce_invalidate(pe, tbl, startp, endp, rm); 11324cce9550SGavin Shan else 11338e0a1611SAlexey Kardashevskiy pnv_pci_ioda2_tce_invalidate(pe, tbl, startp, endp, rm); 11344cce9550SGavin Shan } 11354cce9550SGavin Shan 1136cad5cef6SGreg Kroah-Hartman static void pnv_pci_ioda_setup_dma_pe(struct pnv_phb *phb, 1137cad5cef6SGreg Kroah-Hartman struct pnv_ioda_pe *pe, unsigned int base, 1138184cd4a3SBenjamin Herrenschmidt unsigned int segs) 1139184cd4a3SBenjamin Herrenschmidt { 1140184cd4a3SBenjamin Herrenschmidt 1141184cd4a3SBenjamin Herrenschmidt struct page *tce_mem = NULL; 1142184cd4a3SBenjamin Herrenschmidt const __be64 *swinvp; 1143184cd4a3SBenjamin Herrenschmidt struct iommu_table *tbl; 1144184cd4a3SBenjamin Herrenschmidt unsigned int i; 1145184cd4a3SBenjamin Herrenschmidt int64_t rc; 1146184cd4a3SBenjamin Herrenschmidt void *addr; 1147184cd4a3SBenjamin Herrenschmidt 1148184cd4a3SBenjamin Herrenschmidt /* 256M DMA window, 4K TCE pages, 8 bytes TCE */ 1149184cd4a3SBenjamin Herrenschmidt #define TCE32_TABLE_SIZE ((0x10000000 / 0x1000) * 8) 1150184cd4a3SBenjamin Herrenschmidt 1151184cd4a3SBenjamin Herrenschmidt /* XXX FIXME: Handle 64-bit only DMA devices */ 1152184cd4a3SBenjamin Herrenschmidt /* XXX FIXME: Provide 64-bit DMA facilities & non-4K TCE tables etc.. */ 1153184cd4a3SBenjamin Herrenschmidt /* XXX FIXME: Allocate multi-level tables on PHB3 */ 1154184cd4a3SBenjamin Herrenschmidt 1155184cd4a3SBenjamin Herrenschmidt /* We shouldn't already have a 32-bit DMA associated */ 1156184cd4a3SBenjamin Herrenschmidt if (WARN_ON(pe->tce32_seg >= 0)) 1157184cd4a3SBenjamin Herrenschmidt return; 1158184cd4a3SBenjamin Herrenschmidt 1159184cd4a3SBenjamin Herrenschmidt /* Grab a 32-bit TCE table */ 1160184cd4a3SBenjamin Herrenschmidt pe->tce32_seg = base; 1161184cd4a3SBenjamin Herrenschmidt pe_info(pe, " Setting up 32-bit TCE table at %08x..%08x\n", 1162184cd4a3SBenjamin Herrenschmidt (base << 28), ((base + segs) << 28) - 1); 1163184cd4a3SBenjamin Herrenschmidt 1164184cd4a3SBenjamin Herrenschmidt /* XXX Currently, we allocate one big contiguous table for the 1165184cd4a3SBenjamin Herrenschmidt * TCEs. We only really need one chunk per 256M of TCE space 1166184cd4a3SBenjamin Herrenschmidt * (ie per segment) but that's an optimization for later, it 1167184cd4a3SBenjamin Herrenschmidt * requires some added smarts with our get/put_tce implementation 1168184cd4a3SBenjamin Herrenschmidt */ 1169184cd4a3SBenjamin Herrenschmidt tce_mem = alloc_pages_node(phb->hose->node, GFP_KERNEL, 1170184cd4a3SBenjamin Herrenschmidt get_order(TCE32_TABLE_SIZE * segs)); 1171184cd4a3SBenjamin Herrenschmidt if (!tce_mem) { 1172184cd4a3SBenjamin Herrenschmidt pe_err(pe, " Failed to allocate a 32-bit TCE memory\n"); 1173184cd4a3SBenjamin Herrenschmidt goto fail; 1174184cd4a3SBenjamin Herrenschmidt } 1175184cd4a3SBenjamin Herrenschmidt addr = page_address(tce_mem); 1176184cd4a3SBenjamin Herrenschmidt memset(addr, 0, TCE32_TABLE_SIZE * segs); 1177184cd4a3SBenjamin Herrenschmidt 1178184cd4a3SBenjamin Herrenschmidt /* Configure HW */ 1179184cd4a3SBenjamin Herrenschmidt for (i = 0; i < segs; i++) { 1180184cd4a3SBenjamin Herrenschmidt rc = opal_pci_map_pe_dma_window(phb->opal_id, 1181184cd4a3SBenjamin Herrenschmidt pe->pe_number, 1182184cd4a3SBenjamin Herrenschmidt base + i, 1, 1183184cd4a3SBenjamin Herrenschmidt __pa(addr) + TCE32_TABLE_SIZE * i, 1184184cd4a3SBenjamin Herrenschmidt TCE32_TABLE_SIZE, 0x1000); 1185184cd4a3SBenjamin Herrenschmidt if (rc) { 1186184cd4a3SBenjamin Herrenschmidt pe_err(pe, " Failed to configure 32-bit TCE table," 1187184cd4a3SBenjamin Herrenschmidt " err %ld\n", rc); 1188184cd4a3SBenjamin Herrenschmidt goto fail; 1189184cd4a3SBenjamin Herrenschmidt } 1190184cd4a3SBenjamin Herrenschmidt } 1191184cd4a3SBenjamin Herrenschmidt 1192184cd4a3SBenjamin Herrenschmidt /* Setup linux iommu table */ 1193184cd4a3SBenjamin Herrenschmidt tbl = &pe->tce32_table; 1194184cd4a3SBenjamin Herrenschmidt pnv_pci_setup_iommu_table(tbl, addr, TCE32_TABLE_SIZE * segs, 11958fa5d454SAlexey Kardashevskiy base << 28, IOMMU_PAGE_SHIFT_4K); 1196184cd4a3SBenjamin Herrenschmidt 1197184cd4a3SBenjamin Herrenschmidt /* OPAL variant of P7IOC SW invalidated TCEs */ 1198184cd4a3SBenjamin Herrenschmidt swinvp = of_get_property(phb->hose->dn, "ibm,opal-tce-kill", NULL); 1199184cd4a3SBenjamin Herrenschmidt if (swinvp) { 1200184cd4a3SBenjamin Herrenschmidt /* We need a couple more fields -- an address and a data 1201184cd4a3SBenjamin Herrenschmidt * to or. Since the bus is only printed out on table free 1202184cd4a3SBenjamin Herrenschmidt * errors, and on the first pass the data will be a relative 1203184cd4a3SBenjamin Herrenschmidt * bus number, print that out instead. 1204184cd4a3SBenjamin Herrenschmidt */ 12058e0a1611SAlexey Kardashevskiy pe->tce_inval_reg_phys = be64_to_cpup(swinvp); 12068e0a1611SAlexey Kardashevskiy tbl->it_index = (unsigned long)ioremap(pe->tce_inval_reg_phys, 12078e0a1611SAlexey Kardashevskiy 8); 120865fd766bSGavin Shan tbl->it_type |= (TCE_PCI_SWINV_CREATE | 120965fd766bSGavin Shan TCE_PCI_SWINV_FREE | 121065fd766bSGavin Shan TCE_PCI_SWINV_PAIR); 1211184cd4a3SBenjamin Herrenschmidt } 1212184cd4a3SBenjamin Herrenschmidt iommu_init_table(tbl, phb->hose->node); 1213e9bc03feSGavin Shan iommu_register_group(tbl, phb->hose->global_number, pe->pe_number); 1214184cd4a3SBenjamin Herrenschmidt 121574251fe2SBenjamin Herrenschmidt if (pe->pdev) 1216d905c5dfSAlexey Kardashevskiy set_iommu_table_base_and_group(&pe->pdev->dev, tbl); 121774251fe2SBenjamin Herrenschmidt else 1218dff4a39eSGavin Shan pnv_ioda_setup_bus_dma(pe, pe->pbus, true); 121974251fe2SBenjamin Herrenschmidt 1220184cd4a3SBenjamin Herrenschmidt return; 1221184cd4a3SBenjamin Herrenschmidt fail: 1222184cd4a3SBenjamin Herrenschmidt /* XXX Failure: Try to fallback to 64-bit only ? */ 1223184cd4a3SBenjamin Herrenschmidt if (pe->tce32_seg >= 0) 1224184cd4a3SBenjamin Herrenschmidt pe->tce32_seg = -1; 1225184cd4a3SBenjamin Herrenschmidt if (tce_mem) 1226184cd4a3SBenjamin Herrenschmidt __free_pages(tce_mem, get_order(TCE32_TABLE_SIZE * segs)); 1227184cd4a3SBenjamin Herrenschmidt } 1228184cd4a3SBenjamin Herrenschmidt 1229cd15b048SBenjamin Herrenschmidt static void pnv_pci_ioda2_set_bypass(struct iommu_table *tbl, bool enable) 1230cd15b048SBenjamin Herrenschmidt { 1231cd15b048SBenjamin Herrenschmidt struct pnv_ioda_pe *pe = container_of(tbl, struct pnv_ioda_pe, 1232cd15b048SBenjamin Herrenschmidt tce32_table); 1233cd15b048SBenjamin Herrenschmidt uint16_t window_id = (pe->pe_number << 1 ) + 1; 1234cd15b048SBenjamin Herrenschmidt int64_t rc; 1235cd15b048SBenjamin Herrenschmidt 1236cd15b048SBenjamin Herrenschmidt pe_info(pe, "%sabling 64-bit DMA bypass\n", enable ? "En" : "Dis"); 1237cd15b048SBenjamin Herrenschmidt if (enable) { 1238cd15b048SBenjamin Herrenschmidt phys_addr_t top = memblock_end_of_DRAM(); 1239cd15b048SBenjamin Herrenschmidt 1240cd15b048SBenjamin Herrenschmidt top = roundup_pow_of_two(top); 1241cd15b048SBenjamin Herrenschmidt rc = opal_pci_map_pe_dma_window_real(pe->phb->opal_id, 1242cd15b048SBenjamin Herrenschmidt pe->pe_number, 1243cd15b048SBenjamin Herrenschmidt window_id, 1244cd15b048SBenjamin Herrenschmidt pe->tce_bypass_base, 1245cd15b048SBenjamin Herrenschmidt top); 1246cd15b048SBenjamin Herrenschmidt } else { 1247cd15b048SBenjamin Herrenschmidt rc = opal_pci_map_pe_dma_window_real(pe->phb->opal_id, 1248cd15b048SBenjamin Herrenschmidt pe->pe_number, 1249cd15b048SBenjamin Herrenschmidt window_id, 1250cd15b048SBenjamin Herrenschmidt pe->tce_bypass_base, 1251cd15b048SBenjamin Herrenschmidt 0); 1252cd15b048SBenjamin Herrenschmidt 1253cd15b048SBenjamin Herrenschmidt /* 1254dff4a39eSGavin Shan * EEH needs the mapping between IOMMU table and group 1255dff4a39eSGavin Shan * of those VFIO/KVM pass-through devices. We can postpone 1256dff4a39eSGavin Shan * resetting DMA ops until the DMA mask is configured in 1257dff4a39eSGavin Shan * host side. 1258cd15b048SBenjamin Herrenschmidt */ 1259dff4a39eSGavin Shan if (pe->pdev) 1260dff4a39eSGavin Shan set_iommu_table_base(&pe->pdev->dev, tbl); 1261dff4a39eSGavin Shan else 1262dff4a39eSGavin Shan pnv_ioda_setup_bus_dma(pe, pe->pbus, false); 1263cd15b048SBenjamin Herrenschmidt } 1264cd15b048SBenjamin Herrenschmidt if (rc) 1265cd15b048SBenjamin Herrenschmidt pe_err(pe, "OPAL error %lld configuring bypass window\n", rc); 1266cd15b048SBenjamin Herrenschmidt else 1267cd15b048SBenjamin Herrenschmidt pe->tce_bypass_enabled = enable; 1268cd15b048SBenjamin Herrenschmidt } 1269cd15b048SBenjamin Herrenschmidt 1270cd15b048SBenjamin Herrenschmidt static void pnv_pci_ioda2_setup_bypass_pe(struct pnv_phb *phb, 1271cd15b048SBenjamin Herrenschmidt struct pnv_ioda_pe *pe) 1272cd15b048SBenjamin Herrenschmidt { 1273cd15b048SBenjamin Herrenschmidt /* TVE #1 is selected by PCI address bit 59 */ 1274cd15b048SBenjamin Herrenschmidt pe->tce_bypass_base = 1ull << 59; 1275cd15b048SBenjamin Herrenschmidt 1276cd15b048SBenjamin Herrenschmidt /* Install set_bypass callback for VFIO */ 1277cd15b048SBenjamin Herrenschmidt pe->tce32_table.set_bypass = pnv_pci_ioda2_set_bypass; 1278cd15b048SBenjamin Herrenschmidt 1279cd15b048SBenjamin Herrenschmidt /* Enable bypass by default */ 1280cd15b048SBenjamin Herrenschmidt pnv_pci_ioda2_set_bypass(&pe->tce32_table, true); 1281cd15b048SBenjamin Herrenschmidt } 1282cd15b048SBenjamin Herrenschmidt 1283373f5657SGavin Shan static void pnv_pci_ioda2_setup_dma_pe(struct pnv_phb *phb, 1284373f5657SGavin Shan struct pnv_ioda_pe *pe) 1285373f5657SGavin Shan { 1286373f5657SGavin Shan struct page *tce_mem = NULL; 1287373f5657SGavin Shan void *addr; 1288373f5657SGavin Shan const __be64 *swinvp; 1289373f5657SGavin Shan struct iommu_table *tbl; 1290373f5657SGavin Shan unsigned int tce_table_size, end; 1291373f5657SGavin Shan int64_t rc; 1292373f5657SGavin Shan 1293373f5657SGavin Shan /* We shouldn't already have a 32-bit DMA associated */ 1294373f5657SGavin Shan if (WARN_ON(pe->tce32_seg >= 0)) 1295373f5657SGavin Shan return; 1296373f5657SGavin Shan 1297373f5657SGavin Shan /* The PE will reserve all possible 32-bits space */ 1298373f5657SGavin Shan pe->tce32_seg = 0; 1299373f5657SGavin Shan end = (1 << ilog2(phb->ioda.m32_pci_base)); 1300373f5657SGavin Shan tce_table_size = (end / 0x1000) * 8; 1301373f5657SGavin Shan pe_info(pe, "Setting up 32-bit TCE table at 0..%08x\n", 1302373f5657SGavin Shan end); 1303373f5657SGavin Shan 1304373f5657SGavin Shan /* Allocate TCE table */ 1305373f5657SGavin Shan tce_mem = alloc_pages_node(phb->hose->node, GFP_KERNEL, 1306373f5657SGavin Shan get_order(tce_table_size)); 1307373f5657SGavin Shan if (!tce_mem) { 1308373f5657SGavin Shan pe_err(pe, "Failed to allocate a 32-bit TCE memory\n"); 1309373f5657SGavin Shan goto fail; 1310373f5657SGavin Shan } 1311373f5657SGavin Shan addr = page_address(tce_mem); 1312373f5657SGavin Shan memset(addr, 0, tce_table_size); 1313373f5657SGavin Shan 1314373f5657SGavin Shan /* 1315373f5657SGavin Shan * Map TCE table through TVT. The TVE index is the PE number 1316373f5657SGavin Shan * shifted by 1 bit for 32-bits DMA space. 1317373f5657SGavin Shan */ 1318373f5657SGavin Shan rc = opal_pci_map_pe_dma_window(phb->opal_id, pe->pe_number, 1319373f5657SGavin Shan pe->pe_number << 1, 1, __pa(addr), 1320373f5657SGavin Shan tce_table_size, 0x1000); 1321373f5657SGavin Shan if (rc) { 1322373f5657SGavin Shan pe_err(pe, "Failed to configure 32-bit TCE table," 1323373f5657SGavin Shan " err %ld\n", rc); 1324373f5657SGavin Shan goto fail; 1325373f5657SGavin Shan } 1326373f5657SGavin Shan 1327373f5657SGavin Shan /* Setup linux iommu table */ 1328373f5657SGavin Shan tbl = &pe->tce32_table; 13298fa5d454SAlexey Kardashevskiy pnv_pci_setup_iommu_table(tbl, addr, tce_table_size, 0, 13308fa5d454SAlexey Kardashevskiy IOMMU_PAGE_SHIFT_4K); 1331373f5657SGavin Shan 1332373f5657SGavin Shan /* OPAL variant of PHB3 invalidated TCEs */ 1333373f5657SGavin Shan swinvp = of_get_property(phb->hose->dn, "ibm,opal-tce-kill", NULL); 1334373f5657SGavin Shan if (swinvp) { 1335373f5657SGavin Shan /* We need a couple more fields -- an address and a data 1336373f5657SGavin Shan * to or. Since the bus is only printed out on table free 1337373f5657SGavin Shan * errors, and on the first pass the data will be a relative 1338373f5657SGavin Shan * bus number, print that out instead. 1339373f5657SGavin Shan */ 13408e0a1611SAlexey Kardashevskiy pe->tce_inval_reg_phys = be64_to_cpup(swinvp); 13418e0a1611SAlexey Kardashevskiy tbl->it_index = (unsigned long)ioremap(pe->tce_inval_reg_phys, 13428e0a1611SAlexey Kardashevskiy 8); 134365fd766bSGavin Shan tbl->it_type |= (TCE_PCI_SWINV_CREATE | TCE_PCI_SWINV_FREE); 1344373f5657SGavin Shan } 1345373f5657SGavin Shan iommu_init_table(tbl, phb->hose->node); 1346e9bc03feSGavin Shan iommu_register_group(tbl, phb->hose->global_number, pe->pe_number); 1347373f5657SGavin Shan 134874251fe2SBenjamin Herrenschmidt if (pe->pdev) 1349d905c5dfSAlexey Kardashevskiy set_iommu_table_base_and_group(&pe->pdev->dev, tbl); 135074251fe2SBenjamin Herrenschmidt else 1351dff4a39eSGavin Shan pnv_ioda_setup_bus_dma(pe, pe->pbus, true); 135274251fe2SBenjamin Herrenschmidt 1353cd15b048SBenjamin Herrenschmidt /* Also create a bypass window */ 1354cd15b048SBenjamin Herrenschmidt pnv_pci_ioda2_setup_bypass_pe(phb, pe); 1355373f5657SGavin Shan return; 1356373f5657SGavin Shan fail: 1357373f5657SGavin Shan if (pe->tce32_seg >= 0) 1358373f5657SGavin Shan pe->tce32_seg = -1; 1359373f5657SGavin Shan if (tce_mem) 1360373f5657SGavin Shan __free_pages(tce_mem, get_order(tce_table_size)); 1361373f5657SGavin Shan } 1362373f5657SGavin Shan 1363cad5cef6SGreg Kroah-Hartman static void pnv_ioda_setup_dma(struct pnv_phb *phb) 1364184cd4a3SBenjamin Herrenschmidt { 1365184cd4a3SBenjamin Herrenschmidt struct pci_controller *hose = phb->hose; 1366184cd4a3SBenjamin Herrenschmidt unsigned int residual, remaining, segs, tw, base; 1367184cd4a3SBenjamin Herrenschmidt struct pnv_ioda_pe *pe; 1368184cd4a3SBenjamin Herrenschmidt 1369184cd4a3SBenjamin Herrenschmidt /* If we have more PE# than segments available, hand out one 1370184cd4a3SBenjamin Herrenschmidt * per PE until we run out and let the rest fail. If not, 1371184cd4a3SBenjamin Herrenschmidt * then we assign at least one segment per PE, plus more based 1372184cd4a3SBenjamin Herrenschmidt * on the amount of devices under that PE 1373184cd4a3SBenjamin Herrenschmidt */ 1374184cd4a3SBenjamin Herrenschmidt if (phb->ioda.dma_pe_count > phb->ioda.tce32_count) 1375184cd4a3SBenjamin Herrenschmidt residual = 0; 1376184cd4a3SBenjamin Herrenschmidt else 1377184cd4a3SBenjamin Herrenschmidt residual = phb->ioda.tce32_count - 1378184cd4a3SBenjamin Herrenschmidt phb->ioda.dma_pe_count; 1379184cd4a3SBenjamin Herrenschmidt 1380184cd4a3SBenjamin Herrenschmidt pr_info("PCI: Domain %04x has %ld available 32-bit DMA segments\n", 1381184cd4a3SBenjamin Herrenschmidt hose->global_number, phb->ioda.tce32_count); 1382184cd4a3SBenjamin Herrenschmidt pr_info("PCI: %d PE# for a total weight of %d\n", 1383184cd4a3SBenjamin Herrenschmidt phb->ioda.dma_pe_count, phb->ioda.dma_weight); 1384184cd4a3SBenjamin Herrenschmidt 1385184cd4a3SBenjamin Herrenschmidt /* Walk our PE list and configure their DMA segments, hand them 1386184cd4a3SBenjamin Herrenschmidt * out one base segment plus any residual segments based on 1387184cd4a3SBenjamin Herrenschmidt * weight 1388184cd4a3SBenjamin Herrenschmidt */ 1389184cd4a3SBenjamin Herrenschmidt remaining = phb->ioda.tce32_count; 1390184cd4a3SBenjamin Herrenschmidt tw = phb->ioda.dma_weight; 1391184cd4a3SBenjamin Herrenschmidt base = 0; 13927ebdf956SGavin Shan list_for_each_entry(pe, &phb->ioda.pe_dma_list, dma_link) { 1393184cd4a3SBenjamin Herrenschmidt if (!pe->dma_weight) 1394184cd4a3SBenjamin Herrenschmidt continue; 1395184cd4a3SBenjamin Herrenschmidt if (!remaining) { 1396184cd4a3SBenjamin Herrenschmidt pe_warn(pe, "No DMA32 resources available\n"); 1397184cd4a3SBenjamin Herrenschmidt continue; 1398184cd4a3SBenjamin Herrenschmidt } 1399184cd4a3SBenjamin Herrenschmidt segs = 1; 1400184cd4a3SBenjamin Herrenschmidt if (residual) { 1401184cd4a3SBenjamin Herrenschmidt segs += ((pe->dma_weight * residual) + (tw / 2)) / tw; 1402184cd4a3SBenjamin Herrenschmidt if (segs > remaining) 1403184cd4a3SBenjamin Herrenschmidt segs = remaining; 1404184cd4a3SBenjamin Herrenschmidt } 1405373f5657SGavin Shan 1406373f5657SGavin Shan /* 1407373f5657SGavin Shan * For IODA2 compliant PHB3, we needn't care about the weight. 1408373f5657SGavin Shan * The all available 32-bits DMA space will be assigned to 1409373f5657SGavin Shan * the specific PE. 1410373f5657SGavin Shan */ 1411373f5657SGavin Shan if (phb->type == PNV_PHB_IODA1) { 1412184cd4a3SBenjamin Herrenschmidt pe_info(pe, "DMA weight %d, assigned %d DMA32 segments\n", 1413184cd4a3SBenjamin Herrenschmidt pe->dma_weight, segs); 1414184cd4a3SBenjamin Herrenschmidt pnv_pci_ioda_setup_dma_pe(phb, pe, base, segs); 1415373f5657SGavin Shan } else { 1416373f5657SGavin Shan pe_info(pe, "Assign DMA32 space\n"); 1417373f5657SGavin Shan segs = 0; 1418373f5657SGavin Shan pnv_pci_ioda2_setup_dma_pe(phb, pe); 1419373f5657SGavin Shan } 1420373f5657SGavin Shan 1421184cd4a3SBenjamin Herrenschmidt remaining -= segs; 1422184cd4a3SBenjamin Herrenschmidt base += segs; 1423184cd4a3SBenjamin Herrenschmidt } 1424184cd4a3SBenjamin Herrenschmidt } 1425184cd4a3SBenjamin Herrenschmidt 1426184cd4a3SBenjamin Herrenschmidt #ifdef CONFIG_PCI_MSI 1427137436c9SGavin Shan static void pnv_ioda2_msi_eoi(struct irq_data *d) 1428137436c9SGavin Shan { 1429137436c9SGavin Shan unsigned int hw_irq = (unsigned int)irqd_to_hwirq(d); 1430137436c9SGavin Shan struct irq_chip *chip = irq_data_get_irq_chip(d); 1431137436c9SGavin Shan struct pnv_phb *phb = container_of(chip, struct pnv_phb, 1432137436c9SGavin Shan ioda.irq_chip); 1433137436c9SGavin Shan int64_t rc; 1434137436c9SGavin Shan 1435137436c9SGavin Shan rc = opal_pci_msi_eoi(phb->opal_id, hw_irq); 1436137436c9SGavin Shan WARN_ON_ONCE(rc); 1437137436c9SGavin Shan 1438137436c9SGavin Shan icp_native_eoi(d); 1439137436c9SGavin Shan } 1440137436c9SGavin Shan 1441fd9a1c26SIan Munsie 1442fd9a1c26SIan Munsie static void set_msi_irq_chip(struct pnv_phb *phb, unsigned int virq) 1443fd9a1c26SIan Munsie { 1444fd9a1c26SIan Munsie struct irq_data *idata; 1445fd9a1c26SIan Munsie struct irq_chip *ichip; 1446fd9a1c26SIan Munsie 1447fd9a1c26SIan Munsie if (phb->type != PNV_PHB_IODA2) 1448fd9a1c26SIan Munsie return; 1449fd9a1c26SIan Munsie 1450fd9a1c26SIan Munsie if (!phb->ioda.irq_chip_init) { 1451fd9a1c26SIan Munsie /* 1452fd9a1c26SIan Munsie * First time we setup an MSI IRQ, we need to setup the 1453fd9a1c26SIan Munsie * corresponding IRQ chip to route correctly. 1454fd9a1c26SIan Munsie */ 1455fd9a1c26SIan Munsie idata = irq_get_irq_data(virq); 1456fd9a1c26SIan Munsie ichip = irq_data_get_irq_chip(idata); 1457fd9a1c26SIan Munsie phb->ioda.irq_chip_init = 1; 1458fd9a1c26SIan Munsie phb->ioda.irq_chip = *ichip; 1459fd9a1c26SIan Munsie phb->ioda.irq_chip.irq_eoi = pnv_ioda2_msi_eoi; 1460fd9a1c26SIan Munsie } 1461fd9a1c26SIan Munsie irq_set_chip(virq, &phb->ioda.irq_chip); 1462fd9a1c26SIan Munsie } 1463fd9a1c26SIan Munsie 146480c49c7eSIan Munsie #ifdef CONFIG_CXL_BASE 146580c49c7eSIan Munsie 146680c49c7eSIan Munsie struct device_node *pnv_pci_to_phb_node(struct pci_dev *dev) 146780c49c7eSIan Munsie { 146880c49c7eSIan Munsie struct pci_controller *hose = pci_bus_to_host(dev->bus); 146980c49c7eSIan Munsie 147080c49c7eSIan Munsie return hose->dn; 147180c49c7eSIan Munsie } 147280c49c7eSIan Munsie EXPORT_SYMBOL(pnv_pci_to_phb_node); 147380c49c7eSIan Munsie 14741212aa1cSRyan Grimm int pnv_phb_to_cxl_mode(struct pci_dev *dev, uint64_t mode) 147580c49c7eSIan Munsie { 147680c49c7eSIan Munsie struct pci_controller *hose = pci_bus_to_host(dev->bus); 147780c49c7eSIan Munsie struct pnv_phb *phb = hose->private_data; 147880c49c7eSIan Munsie struct pnv_ioda_pe *pe; 147980c49c7eSIan Munsie int rc; 148080c49c7eSIan Munsie 148180c49c7eSIan Munsie pe = pnv_ioda_get_pe(dev); 148280c49c7eSIan Munsie if (!pe) 148380c49c7eSIan Munsie return -ENODEV; 148480c49c7eSIan Munsie 148580c49c7eSIan Munsie pe_info(pe, "Switching PHB to CXL\n"); 148680c49c7eSIan Munsie 14871212aa1cSRyan Grimm rc = opal_pci_set_phb_cxl_mode(phb->opal_id, mode, pe->pe_number); 148880c49c7eSIan Munsie if (rc) 148980c49c7eSIan Munsie dev_err(&dev->dev, "opal_pci_set_phb_cxl_mode failed: %i\n", rc); 149080c49c7eSIan Munsie 149180c49c7eSIan Munsie return rc; 149280c49c7eSIan Munsie } 14931212aa1cSRyan Grimm EXPORT_SYMBOL(pnv_phb_to_cxl_mode); 149480c49c7eSIan Munsie 149580c49c7eSIan Munsie /* Find PHB for cxl dev and allocate MSI hwirqs? 149680c49c7eSIan Munsie * Returns the absolute hardware IRQ number 149780c49c7eSIan Munsie */ 149880c49c7eSIan Munsie int pnv_cxl_alloc_hwirqs(struct pci_dev *dev, int num) 149980c49c7eSIan Munsie { 150080c49c7eSIan Munsie struct pci_controller *hose = pci_bus_to_host(dev->bus); 150180c49c7eSIan Munsie struct pnv_phb *phb = hose->private_data; 150280c49c7eSIan Munsie int hwirq = msi_bitmap_alloc_hwirqs(&phb->msi_bmp, num); 150380c49c7eSIan Munsie 150480c49c7eSIan Munsie if (hwirq < 0) { 150580c49c7eSIan Munsie dev_warn(&dev->dev, "Failed to find a free MSI\n"); 150680c49c7eSIan Munsie return -ENOSPC; 150780c49c7eSIan Munsie } 150880c49c7eSIan Munsie 150980c49c7eSIan Munsie return phb->msi_base + hwirq; 151080c49c7eSIan Munsie } 151180c49c7eSIan Munsie EXPORT_SYMBOL(pnv_cxl_alloc_hwirqs); 151280c49c7eSIan Munsie 151380c49c7eSIan Munsie void pnv_cxl_release_hwirqs(struct pci_dev *dev, int hwirq, int num) 151480c49c7eSIan Munsie { 151580c49c7eSIan Munsie struct pci_controller *hose = pci_bus_to_host(dev->bus); 151680c49c7eSIan Munsie struct pnv_phb *phb = hose->private_data; 151780c49c7eSIan Munsie 151880c49c7eSIan Munsie msi_bitmap_free_hwirqs(&phb->msi_bmp, hwirq - phb->msi_base, num); 151980c49c7eSIan Munsie } 152080c49c7eSIan Munsie EXPORT_SYMBOL(pnv_cxl_release_hwirqs); 152180c49c7eSIan Munsie 152280c49c7eSIan Munsie void pnv_cxl_release_hwirq_ranges(struct cxl_irq_ranges *irqs, 152380c49c7eSIan Munsie struct pci_dev *dev) 152480c49c7eSIan Munsie { 152580c49c7eSIan Munsie struct pci_controller *hose = pci_bus_to_host(dev->bus); 152680c49c7eSIan Munsie struct pnv_phb *phb = hose->private_data; 152780c49c7eSIan Munsie int i, hwirq; 152880c49c7eSIan Munsie 152980c49c7eSIan Munsie for (i = 1; i < CXL_IRQ_RANGES; i++) { 153080c49c7eSIan Munsie if (!irqs->range[i]) 153180c49c7eSIan Munsie continue; 153280c49c7eSIan Munsie pr_devel("cxl release irq range 0x%x: offset: 0x%lx limit: %ld\n", 153380c49c7eSIan Munsie i, irqs->offset[i], 153480c49c7eSIan Munsie irqs->range[i]); 153580c49c7eSIan Munsie hwirq = irqs->offset[i] - phb->msi_base; 153680c49c7eSIan Munsie msi_bitmap_free_hwirqs(&phb->msi_bmp, hwirq, 153780c49c7eSIan Munsie irqs->range[i]); 153880c49c7eSIan Munsie } 153980c49c7eSIan Munsie } 154080c49c7eSIan Munsie EXPORT_SYMBOL(pnv_cxl_release_hwirq_ranges); 154180c49c7eSIan Munsie 154280c49c7eSIan Munsie int pnv_cxl_alloc_hwirq_ranges(struct cxl_irq_ranges *irqs, 154380c49c7eSIan Munsie struct pci_dev *dev, int num) 154480c49c7eSIan Munsie { 154580c49c7eSIan Munsie struct pci_controller *hose = pci_bus_to_host(dev->bus); 154680c49c7eSIan Munsie struct pnv_phb *phb = hose->private_data; 154780c49c7eSIan Munsie int i, hwirq, try; 154880c49c7eSIan Munsie 154980c49c7eSIan Munsie memset(irqs, 0, sizeof(struct cxl_irq_ranges)); 155080c49c7eSIan Munsie 155180c49c7eSIan Munsie /* 0 is reserved for the multiplexed PSL DSI interrupt */ 155280c49c7eSIan Munsie for (i = 1; i < CXL_IRQ_RANGES && num; i++) { 155380c49c7eSIan Munsie try = num; 155480c49c7eSIan Munsie while (try) { 155580c49c7eSIan Munsie hwirq = msi_bitmap_alloc_hwirqs(&phb->msi_bmp, try); 155680c49c7eSIan Munsie if (hwirq >= 0) 155780c49c7eSIan Munsie break; 155880c49c7eSIan Munsie try /= 2; 155980c49c7eSIan Munsie } 156080c49c7eSIan Munsie if (!try) 156180c49c7eSIan Munsie goto fail; 156280c49c7eSIan Munsie 156380c49c7eSIan Munsie irqs->offset[i] = phb->msi_base + hwirq; 156480c49c7eSIan Munsie irqs->range[i] = try; 156580c49c7eSIan Munsie pr_devel("cxl alloc irq range 0x%x: offset: 0x%lx limit: %li\n", 156680c49c7eSIan Munsie i, irqs->offset[i], irqs->range[i]); 156780c49c7eSIan Munsie num -= try; 156880c49c7eSIan Munsie } 156980c49c7eSIan Munsie if (num) 157080c49c7eSIan Munsie goto fail; 157180c49c7eSIan Munsie 157280c49c7eSIan Munsie return 0; 157380c49c7eSIan Munsie fail: 157480c49c7eSIan Munsie pnv_cxl_release_hwirq_ranges(irqs, dev); 157580c49c7eSIan Munsie return -ENOSPC; 157680c49c7eSIan Munsie } 157780c49c7eSIan Munsie EXPORT_SYMBOL(pnv_cxl_alloc_hwirq_ranges); 157880c49c7eSIan Munsie 157980c49c7eSIan Munsie int pnv_cxl_get_irq_count(struct pci_dev *dev) 158080c49c7eSIan Munsie { 158180c49c7eSIan Munsie struct pci_controller *hose = pci_bus_to_host(dev->bus); 158280c49c7eSIan Munsie struct pnv_phb *phb = hose->private_data; 158380c49c7eSIan Munsie 158480c49c7eSIan Munsie return phb->msi_bmp.irq_count; 158580c49c7eSIan Munsie } 158680c49c7eSIan Munsie EXPORT_SYMBOL(pnv_cxl_get_irq_count); 158780c49c7eSIan Munsie 158880c49c7eSIan Munsie int pnv_cxl_ioda_msi_setup(struct pci_dev *dev, unsigned int hwirq, 158980c49c7eSIan Munsie unsigned int virq) 159080c49c7eSIan Munsie { 159180c49c7eSIan Munsie struct pci_controller *hose = pci_bus_to_host(dev->bus); 159280c49c7eSIan Munsie struct pnv_phb *phb = hose->private_data; 159380c49c7eSIan Munsie unsigned int xive_num = hwirq - phb->msi_base; 159480c49c7eSIan Munsie struct pnv_ioda_pe *pe; 159580c49c7eSIan Munsie int rc; 159680c49c7eSIan Munsie 159780c49c7eSIan Munsie if (!(pe = pnv_ioda_get_pe(dev))) 159880c49c7eSIan Munsie return -ENODEV; 159980c49c7eSIan Munsie 160080c49c7eSIan Munsie /* Assign XIVE to PE */ 160180c49c7eSIan Munsie rc = opal_pci_set_xive_pe(phb->opal_id, pe->pe_number, xive_num); 160280c49c7eSIan Munsie if (rc) { 160380c49c7eSIan Munsie pe_warn(pe, "%s: OPAL error %d setting msi_base 0x%x " 160480c49c7eSIan Munsie "hwirq 0x%x XIVE 0x%x PE\n", 160580c49c7eSIan Munsie pci_name(dev), rc, phb->msi_base, hwirq, xive_num); 160680c49c7eSIan Munsie return -EIO; 160780c49c7eSIan Munsie } 160880c49c7eSIan Munsie set_msi_irq_chip(phb, virq); 160980c49c7eSIan Munsie 161080c49c7eSIan Munsie return 0; 161180c49c7eSIan Munsie } 161280c49c7eSIan Munsie EXPORT_SYMBOL(pnv_cxl_ioda_msi_setup); 161380c49c7eSIan Munsie #endif 161480c49c7eSIan Munsie 1615184cd4a3SBenjamin Herrenschmidt static int pnv_pci_ioda_msi_setup(struct pnv_phb *phb, struct pci_dev *dev, 1616137436c9SGavin Shan unsigned int hwirq, unsigned int virq, 1617137436c9SGavin Shan unsigned int is_64, struct msi_msg *msg) 1618184cd4a3SBenjamin Herrenschmidt { 1619184cd4a3SBenjamin Herrenschmidt struct pnv_ioda_pe *pe = pnv_ioda_get_pe(dev); 1620184cd4a3SBenjamin Herrenschmidt unsigned int xive_num = hwirq - phb->msi_base; 16213a1a4661SBenjamin Herrenschmidt __be32 data; 1622184cd4a3SBenjamin Herrenschmidt int rc; 1623184cd4a3SBenjamin Herrenschmidt 1624184cd4a3SBenjamin Herrenschmidt /* No PE assigned ? bail out ... no MSI for you ! */ 1625184cd4a3SBenjamin Herrenschmidt if (pe == NULL) 1626184cd4a3SBenjamin Herrenschmidt return -ENXIO; 1627184cd4a3SBenjamin Herrenschmidt 1628184cd4a3SBenjamin Herrenschmidt /* Check if we have an MVE */ 1629184cd4a3SBenjamin Herrenschmidt if (pe->mve_number < 0) 1630184cd4a3SBenjamin Herrenschmidt return -ENXIO; 1631184cd4a3SBenjamin Herrenschmidt 1632b72c1f65SBenjamin Herrenschmidt /* Force 32-bit MSI on some broken devices */ 163336074381SBenjamin Herrenschmidt if (dev->no_64bit_msi) 1634b72c1f65SBenjamin Herrenschmidt is_64 = 0; 1635b72c1f65SBenjamin Herrenschmidt 1636184cd4a3SBenjamin Herrenschmidt /* Assign XIVE to PE */ 1637184cd4a3SBenjamin Herrenschmidt rc = opal_pci_set_xive_pe(phb->opal_id, pe->pe_number, xive_num); 1638184cd4a3SBenjamin Herrenschmidt if (rc) { 1639184cd4a3SBenjamin Herrenschmidt pr_warn("%s: OPAL error %d setting XIVE %d PE\n", 1640184cd4a3SBenjamin Herrenschmidt pci_name(dev), rc, xive_num); 1641184cd4a3SBenjamin Herrenschmidt return -EIO; 1642184cd4a3SBenjamin Herrenschmidt } 1643184cd4a3SBenjamin Herrenschmidt 1644184cd4a3SBenjamin Herrenschmidt if (is_64) { 16453a1a4661SBenjamin Herrenschmidt __be64 addr64; 16463a1a4661SBenjamin Herrenschmidt 1647184cd4a3SBenjamin Herrenschmidt rc = opal_get_msi_64(phb->opal_id, pe->mve_number, xive_num, 1, 1648184cd4a3SBenjamin Herrenschmidt &addr64, &data); 1649184cd4a3SBenjamin Herrenschmidt if (rc) { 1650184cd4a3SBenjamin Herrenschmidt pr_warn("%s: OPAL error %d getting 64-bit MSI data\n", 1651184cd4a3SBenjamin Herrenschmidt pci_name(dev), rc); 1652184cd4a3SBenjamin Herrenschmidt return -EIO; 1653184cd4a3SBenjamin Herrenschmidt } 16543a1a4661SBenjamin Herrenschmidt msg->address_hi = be64_to_cpu(addr64) >> 32; 16553a1a4661SBenjamin Herrenschmidt msg->address_lo = be64_to_cpu(addr64) & 0xfffffffful; 1656184cd4a3SBenjamin Herrenschmidt } else { 16573a1a4661SBenjamin Herrenschmidt __be32 addr32; 16583a1a4661SBenjamin Herrenschmidt 1659184cd4a3SBenjamin Herrenschmidt rc = opal_get_msi_32(phb->opal_id, pe->mve_number, xive_num, 1, 1660184cd4a3SBenjamin Herrenschmidt &addr32, &data); 1661184cd4a3SBenjamin Herrenschmidt if (rc) { 1662184cd4a3SBenjamin Herrenschmidt pr_warn("%s: OPAL error %d getting 32-bit MSI data\n", 1663184cd4a3SBenjamin Herrenschmidt pci_name(dev), rc); 1664184cd4a3SBenjamin Herrenschmidt return -EIO; 1665184cd4a3SBenjamin Herrenschmidt } 1666184cd4a3SBenjamin Herrenschmidt msg->address_hi = 0; 16673a1a4661SBenjamin Herrenschmidt msg->address_lo = be32_to_cpu(addr32); 1668184cd4a3SBenjamin Herrenschmidt } 16693a1a4661SBenjamin Herrenschmidt msg->data = be32_to_cpu(data); 1670184cd4a3SBenjamin Herrenschmidt 1671fd9a1c26SIan Munsie set_msi_irq_chip(phb, virq); 1672137436c9SGavin Shan 1673184cd4a3SBenjamin Herrenschmidt pr_devel("%s: %s-bit MSI on hwirq %x (xive #%d)," 1674184cd4a3SBenjamin Herrenschmidt " address=%x_%08x data=%x PE# %d\n", 1675184cd4a3SBenjamin Herrenschmidt pci_name(dev), is_64 ? "64" : "32", hwirq, xive_num, 1676184cd4a3SBenjamin Herrenschmidt msg->address_hi, msg->address_lo, data, pe->pe_number); 1677184cd4a3SBenjamin Herrenschmidt 1678184cd4a3SBenjamin Herrenschmidt return 0; 1679184cd4a3SBenjamin Herrenschmidt } 1680184cd4a3SBenjamin Herrenschmidt 1681184cd4a3SBenjamin Herrenschmidt static void pnv_pci_init_ioda_msis(struct pnv_phb *phb) 1682184cd4a3SBenjamin Herrenschmidt { 1683fb1b55d6SGavin Shan unsigned int count; 1684184cd4a3SBenjamin Herrenschmidt const __be32 *prop = of_get_property(phb->hose->dn, 1685184cd4a3SBenjamin Herrenschmidt "ibm,opal-msi-ranges", NULL); 1686184cd4a3SBenjamin Herrenschmidt if (!prop) { 1687184cd4a3SBenjamin Herrenschmidt /* BML Fallback */ 1688184cd4a3SBenjamin Herrenschmidt prop = of_get_property(phb->hose->dn, "msi-ranges", NULL); 1689184cd4a3SBenjamin Herrenschmidt } 1690184cd4a3SBenjamin Herrenschmidt if (!prop) 1691184cd4a3SBenjamin Herrenschmidt return; 1692184cd4a3SBenjamin Herrenschmidt 1693184cd4a3SBenjamin Herrenschmidt phb->msi_base = be32_to_cpup(prop); 1694fb1b55d6SGavin Shan count = be32_to_cpup(prop + 1); 1695fb1b55d6SGavin Shan if (msi_bitmap_alloc(&phb->msi_bmp, count, phb->hose->dn)) { 1696184cd4a3SBenjamin Herrenschmidt pr_err("PCI %d: Failed to allocate MSI bitmap !\n", 1697184cd4a3SBenjamin Herrenschmidt phb->hose->global_number); 1698184cd4a3SBenjamin Herrenschmidt return; 1699184cd4a3SBenjamin Herrenschmidt } 1700fb1b55d6SGavin Shan 1701184cd4a3SBenjamin Herrenschmidt phb->msi_setup = pnv_pci_ioda_msi_setup; 1702184cd4a3SBenjamin Herrenschmidt phb->msi32_support = 1; 1703184cd4a3SBenjamin Herrenschmidt pr_info(" Allocated bitmap for %d MSIs (base IRQ 0x%x)\n", 1704fb1b55d6SGavin Shan count, phb->msi_base); 1705184cd4a3SBenjamin Herrenschmidt } 1706184cd4a3SBenjamin Herrenschmidt #else 1707184cd4a3SBenjamin Herrenschmidt static void pnv_pci_init_ioda_msis(struct pnv_phb *phb) { } 1708184cd4a3SBenjamin Herrenschmidt #endif /* CONFIG_PCI_MSI */ 1709184cd4a3SBenjamin Herrenschmidt 171011685becSGavin Shan /* 171111685becSGavin Shan * This function is supposed to be called on basis of PE from top 171211685becSGavin Shan * to bottom style. So the the I/O or MMIO segment assigned to 171311685becSGavin Shan * parent PE could be overrided by its child PEs if necessary. 171411685becSGavin Shan */ 1715cad5cef6SGreg Kroah-Hartman static void pnv_ioda_setup_pe_seg(struct pci_controller *hose, 171611685becSGavin Shan struct pnv_ioda_pe *pe) 171711685becSGavin Shan { 171811685becSGavin Shan struct pnv_phb *phb = hose->private_data; 171911685becSGavin Shan struct pci_bus_region region; 172011685becSGavin Shan struct resource *res; 172111685becSGavin Shan int i, index; 172211685becSGavin Shan int rc; 172311685becSGavin Shan 172411685becSGavin Shan /* 172511685becSGavin Shan * NOTE: We only care PCI bus based PE for now. For PCI 172611685becSGavin Shan * device based PE, for example SRIOV sensitive VF should 172711685becSGavin Shan * be figured out later. 172811685becSGavin Shan */ 172911685becSGavin Shan BUG_ON(!(pe->flags & (PNV_IODA_PE_BUS | PNV_IODA_PE_BUS_ALL))); 173011685becSGavin Shan 173111685becSGavin Shan pci_bus_for_each_resource(pe->pbus, res, i) { 173211685becSGavin Shan if (!res || !res->flags || 173311685becSGavin Shan res->start > res->end) 173411685becSGavin Shan continue; 173511685becSGavin Shan 173611685becSGavin Shan if (res->flags & IORESOURCE_IO) { 173711685becSGavin Shan region.start = res->start - phb->ioda.io_pci_base; 173811685becSGavin Shan region.end = res->end - phb->ioda.io_pci_base; 173911685becSGavin Shan index = region.start / phb->ioda.io_segsize; 174011685becSGavin Shan 174111685becSGavin Shan while (index < phb->ioda.total_pe && 174211685becSGavin Shan region.start <= region.end) { 174311685becSGavin Shan phb->ioda.io_segmap[index] = pe->pe_number; 174411685becSGavin Shan rc = opal_pci_map_pe_mmio_window(phb->opal_id, 174511685becSGavin Shan pe->pe_number, OPAL_IO_WINDOW_TYPE, 0, index); 174611685becSGavin Shan if (rc != OPAL_SUCCESS) { 174711685becSGavin Shan pr_err("%s: OPAL error %d when mapping IO " 174811685becSGavin Shan "segment #%d to PE#%d\n", 174911685becSGavin Shan __func__, rc, index, pe->pe_number); 175011685becSGavin Shan break; 175111685becSGavin Shan } 175211685becSGavin Shan 175311685becSGavin Shan region.start += phb->ioda.io_segsize; 175411685becSGavin Shan index++; 175511685becSGavin Shan } 175611685becSGavin Shan } else if (res->flags & IORESOURCE_MEM) { 175711685becSGavin Shan region.start = res->start - 17583fd47f06SBenjamin Herrenschmidt hose->mem_offset[0] - 175911685becSGavin Shan phb->ioda.m32_pci_base; 176011685becSGavin Shan region.end = res->end - 17613fd47f06SBenjamin Herrenschmidt hose->mem_offset[0] - 176211685becSGavin Shan phb->ioda.m32_pci_base; 176311685becSGavin Shan index = region.start / phb->ioda.m32_segsize; 176411685becSGavin Shan 176511685becSGavin Shan while (index < phb->ioda.total_pe && 176611685becSGavin Shan region.start <= region.end) { 176711685becSGavin Shan phb->ioda.m32_segmap[index] = pe->pe_number; 176811685becSGavin Shan rc = opal_pci_map_pe_mmio_window(phb->opal_id, 176911685becSGavin Shan pe->pe_number, OPAL_M32_WINDOW_TYPE, 0, index); 177011685becSGavin Shan if (rc != OPAL_SUCCESS) { 177111685becSGavin Shan pr_err("%s: OPAL error %d when mapping M32 " 177211685becSGavin Shan "segment#%d to PE#%d", 177311685becSGavin Shan __func__, rc, index, pe->pe_number); 177411685becSGavin Shan break; 177511685becSGavin Shan } 177611685becSGavin Shan 177711685becSGavin Shan region.start += phb->ioda.m32_segsize; 177811685becSGavin Shan index++; 177911685becSGavin Shan } 178011685becSGavin Shan } 178111685becSGavin Shan } 178211685becSGavin Shan } 178311685becSGavin Shan 1784cad5cef6SGreg Kroah-Hartman static void pnv_pci_ioda_setup_seg(void) 178511685becSGavin Shan { 178611685becSGavin Shan struct pci_controller *tmp, *hose; 178711685becSGavin Shan struct pnv_phb *phb; 178811685becSGavin Shan struct pnv_ioda_pe *pe; 178911685becSGavin Shan 179011685becSGavin Shan list_for_each_entry_safe(hose, tmp, &hose_list, list_node) { 179111685becSGavin Shan phb = hose->private_data; 179211685becSGavin Shan list_for_each_entry(pe, &phb->ioda.pe_list, list) { 179311685becSGavin Shan pnv_ioda_setup_pe_seg(hose, pe); 179411685becSGavin Shan } 179511685becSGavin Shan } 179611685becSGavin Shan } 179711685becSGavin Shan 1798cad5cef6SGreg Kroah-Hartman static void pnv_pci_ioda_setup_DMA(void) 179913395c48SGavin Shan { 180013395c48SGavin Shan struct pci_controller *hose, *tmp; 1801db1266c8SGavin Shan struct pnv_phb *phb; 180213395c48SGavin Shan 180313395c48SGavin Shan list_for_each_entry_safe(hose, tmp, &hose_list, list_node) { 180413395c48SGavin Shan pnv_ioda_setup_dma(hose->private_data); 1805db1266c8SGavin Shan 1806db1266c8SGavin Shan /* Mark the PHB initialization done */ 1807db1266c8SGavin Shan phb = hose->private_data; 1808db1266c8SGavin Shan phb->initialized = 1; 180913395c48SGavin Shan } 181013395c48SGavin Shan } 181113395c48SGavin Shan 181237c367f2SGavin Shan static void pnv_pci_ioda_create_dbgfs(void) 181337c367f2SGavin Shan { 181437c367f2SGavin Shan #ifdef CONFIG_DEBUG_FS 181537c367f2SGavin Shan struct pci_controller *hose, *tmp; 181637c367f2SGavin Shan struct pnv_phb *phb; 181737c367f2SGavin Shan char name[16]; 181837c367f2SGavin Shan 181937c367f2SGavin Shan list_for_each_entry_safe(hose, tmp, &hose_list, list_node) { 182037c367f2SGavin Shan phb = hose->private_data; 182137c367f2SGavin Shan 182237c367f2SGavin Shan sprintf(name, "PCI%04x", hose->global_number); 182337c367f2SGavin Shan phb->dbgfs = debugfs_create_dir(name, powerpc_debugfs_root); 182437c367f2SGavin Shan if (!phb->dbgfs) 182537c367f2SGavin Shan pr_warning("%s: Error on creating debugfs on PHB#%x\n", 182637c367f2SGavin Shan __func__, hose->global_number); 182737c367f2SGavin Shan } 182837c367f2SGavin Shan #endif /* CONFIG_DEBUG_FS */ 182937c367f2SGavin Shan } 183037c367f2SGavin Shan 1831cad5cef6SGreg Kroah-Hartman static void pnv_pci_ioda_fixup(void) 1832fb446ad0SGavin Shan { 1833fb446ad0SGavin Shan pnv_pci_ioda_setup_PEs(); 183411685becSGavin Shan pnv_pci_ioda_setup_seg(); 183513395c48SGavin Shan pnv_pci_ioda_setup_DMA(); 1836e9cc17d4SGavin Shan 183737c367f2SGavin Shan pnv_pci_ioda_create_dbgfs(); 183837c367f2SGavin Shan 1839e9cc17d4SGavin Shan #ifdef CONFIG_EEH 1840e9cc17d4SGavin Shan eeh_init(); 1841dadcd6d6SMike Qiu eeh_addr_cache_build(); 1842e9cc17d4SGavin Shan #endif 1843fb446ad0SGavin Shan } 1844fb446ad0SGavin Shan 1845271fd03aSGavin Shan /* 1846271fd03aSGavin Shan * Returns the alignment for I/O or memory windows for P2P 1847271fd03aSGavin Shan * bridges. That actually depends on how PEs are segmented. 1848271fd03aSGavin Shan * For now, we return I/O or M32 segment size for PE sensitive 1849271fd03aSGavin Shan * P2P bridges. Otherwise, the default values (4KiB for I/O, 1850271fd03aSGavin Shan * 1MiB for memory) will be returned. 1851271fd03aSGavin Shan * 1852271fd03aSGavin Shan * The current PCI bus might be put into one PE, which was 1853271fd03aSGavin Shan * create against the parent PCI bridge. For that case, we 1854271fd03aSGavin Shan * needn't enlarge the alignment so that we can save some 1855271fd03aSGavin Shan * resources. 1856271fd03aSGavin Shan */ 1857271fd03aSGavin Shan static resource_size_t pnv_pci_window_alignment(struct pci_bus *bus, 1858271fd03aSGavin Shan unsigned long type) 1859271fd03aSGavin Shan { 1860271fd03aSGavin Shan struct pci_dev *bridge; 1861271fd03aSGavin Shan struct pci_controller *hose = pci_bus_to_host(bus); 1862271fd03aSGavin Shan struct pnv_phb *phb = hose->private_data; 1863271fd03aSGavin Shan int num_pci_bridges = 0; 1864271fd03aSGavin Shan 1865271fd03aSGavin Shan bridge = bus->self; 1866271fd03aSGavin Shan while (bridge) { 1867271fd03aSGavin Shan if (pci_pcie_type(bridge) == PCI_EXP_TYPE_PCI_BRIDGE) { 1868271fd03aSGavin Shan num_pci_bridges++; 1869271fd03aSGavin Shan if (num_pci_bridges >= 2) 1870271fd03aSGavin Shan return 1; 1871271fd03aSGavin Shan } 1872271fd03aSGavin Shan 1873271fd03aSGavin Shan bridge = bridge->bus->self; 1874271fd03aSGavin Shan } 1875271fd03aSGavin Shan 1876262af557SGuo Chao /* We fail back to M32 if M64 isn't supported */ 1877262af557SGuo Chao if (phb->ioda.m64_segsize && 1878262af557SGuo Chao pnv_pci_is_mem_pref_64(type)) 1879262af557SGuo Chao return phb->ioda.m64_segsize; 1880271fd03aSGavin Shan if (type & IORESOURCE_MEM) 1881271fd03aSGavin Shan return phb->ioda.m32_segsize; 1882271fd03aSGavin Shan 1883271fd03aSGavin Shan return phb->ioda.io_segsize; 1884271fd03aSGavin Shan } 1885271fd03aSGavin Shan 1886184cd4a3SBenjamin Herrenschmidt /* Prevent enabling devices for which we couldn't properly 1887184cd4a3SBenjamin Herrenschmidt * assign a PE 1888184cd4a3SBenjamin Herrenschmidt */ 1889cad5cef6SGreg Kroah-Hartman static int pnv_pci_enable_device_hook(struct pci_dev *dev) 1890184cd4a3SBenjamin Herrenschmidt { 1891db1266c8SGavin Shan struct pci_controller *hose = pci_bus_to_host(dev->bus); 1892db1266c8SGavin Shan struct pnv_phb *phb = hose->private_data; 1893db1266c8SGavin Shan struct pci_dn *pdn; 1894184cd4a3SBenjamin Herrenschmidt 1895db1266c8SGavin Shan /* The function is probably called while the PEs have 1896db1266c8SGavin Shan * not be created yet. For example, resource reassignment 1897db1266c8SGavin Shan * during PCI probe period. We just skip the check if 1898db1266c8SGavin Shan * PEs isn't ready. 1899db1266c8SGavin Shan */ 1900db1266c8SGavin Shan if (!phb->initialized) 1901db1266c8SGavin Shan return 0; 1902db1266c8SGavin Shan 1903b72c1f65SBenjamin Herrenschmidt pdn = pci_get_pdn(dev); 1904184cd4a3SBenjamin Herrenschmidt if (!pdn || pdn->pe_number == IODA_INVALID_PE) 1905184cd4a3SBenjamin Herrenschmidt return -EINVAL; 1906db1266c8SGavin Shan 1907184cd4a3SBenjamin Herrenschmidt return 0; 1908184cd4a3SBenjamin Herrenschmidt } 1909184cd4a3SBenjamin Herrenschmidt 1910184cd4a3SBenjamin Herrenschmidt static u32 pnv_ioda_bdfn_to_pe(struct pnv_phb *phb, struct pci_bus *bus, 1911184cd4a3SBenjamin Herrenschmidt u32 devfn) 1912184cd4a3SBenjamin Herrenschmidt { 1913184cd4a3SBenjamin Herrenschmidt return phb->ioda.pe_rmap[(bus->number << 8) | devfn]; 1914184cd4a3SBenjamin Herrenschmidt } 1915184cd4a3SBenjamin Herrenschmidt 191673ed148aSBenjamin Herrenschmidt static void pnv_pci_ioda_shutdown(struct pnv_phb *phb) 191773ed148aSBenjamin Herrenschmidt { 1918d1a85eeeSGavin Shan opal_pci_reset(phb->opal_id, OPAL_RESET_PCI_IODA_TABLE, 191973ed148aSBenjamin Herrenschmidt OPAL_ASSERT_RESET); 192073ed148aSBenjamin Herrenschmidt } 192173ed148aSBenjamin Herrenschmidt 1922e51df2c1SAnton Blanchard static void __init pnv_pci_init_ioda_phb(struct device_node *np, 1923e9cc17d4SGavin Shan u64 hub_id, int ioda_type) 1924184cd4a3SBenjamin Herrenschmidt { 1925184cd4a3SBenjamin Herrenschmidt struct pci_controller *hose; 1926184cd4a3SBenjamin Herrenschmidt struct pnv_phb *phb; 19278184616fSGavin Shan unsigned long size, m32map_off, pemap_off, iomap_off = 0; 1928c681b93cSAlistair Popple const __be64 *prop64; 19293a1a4661SBenjamin Herrenschmidt const __be32 *prop32; 1930f1b7cc3eSGavin Shan int len; 1931184cd4a3SBenjamin Herrenschmidt u64 phb_id; 1932184cd4a3SBenjamin Herrenschmidt void *aux; 1933184cd4a3SBenjamin Herrenschmidt long rc; 1934184cd4a3SBenjamin Herrenschmidt 1935aa0c033fSGavin Shan pr_info("Initializing IODA%d OPAL PHB %s\n", ioda_type, np->full_name); 1936184cd4a3SBenjamin Herrenschmidt 1937184cd4a3SBenjamin Herrenschmidt prop64 = of_get_property(np, "ibm,opal-phbid", NULL); 1938184cd4a3SBenjamin Herrenschmidt if (!prop64) { 1939184cd4a3SBenjamin Herrenschmidt pr_err(" Missing \"ibm,opal-phbid\" property !\n"); 1940184cd4a3SBenjamin Herrenschmidt return; 1941184cd4a3SBenjamin Herrenschmidt } 1942184cd4a3SBenjamin Herrenschmidt phb_id = be64_to_cpup(prop64); 1943184cd4a3SBenjamin Herrenschmidt pr_debug(" PHB-ID : 0x%016llx\n", phb_id); 1944184cd4a3SBenjamin Herrenschmidt 1945e39f223fSMichael Ellerman phb = memblock_virt_alloc(sizeof(struct pnv_phb), 0); 194658d714ecSGavin Shan 194758d714ecSGavin Shan /* Allocate PCI controller */ 1948184cd4a3SBenjamin Herrenschmidt phb->hose = hose = pcibios_alloc_controller(np); 194958d714ecSGavin Shan if (!phb->hose) { 195058d714ecSGavin Shan pr_err(" Can't allocate PCI controller for %s\n", 1951184cd4a3SBenjamin Herrenschmidt np->full_name); 1952e39f223fSMichael Ellerman memblock_free(__pa(phb), sizeof(struct pnv_phb)); 1953184cd4a3SBenjamin Herrenschmidt return; 1954184cd4a3SBenjamin Herrenschmidt } 1955184cd4a3SBenjamin Herrenschmidt 1956184cd4a3SBenjamin Herrenschmidt spin_lock_init(&phb->lock); 1957f1b7cc3eSGavin Shan prop32 = of_get_property(np, "bus-range", &len); 1958f1b7cc3eSGavin Shan if (prop32 && len == 8) { 19593a1a4661SBenjamin Herrenschmidt hose->first_busno = be32_to_cpu(prop32[0]); 19603a1a4661SBenjamin Herrenschmidt hose->last_busno = be32_to_cpu(prop32[1]); 1961f1b7cc3eSGavin Shan } else { 1962f1b7cc3eSGavin Shan pr_warn(" Broken <bus-range> on %s\n", np->full_name); 1963184cd4a3SBenjamin Herrenschmidt hose->first_busno = 0; 1964184cd4a3SBenjamin Herrenschmidt hose->last_busno = 0xff; 1965f1b7cc3eSGavin Shan } 1966184cd4a3SBenjamin Herrenschmidt hose->private_data = phb; 1967e9cc17d4SGavin Shan phb->hub_id = hub_id; 1968184cd4a3SBenjamin Herrenschmidt phb->opal_id = phb_id; 1969aa0c033fSGavin Shan phb->type = ioda_type; 1970184cd4a3SBenjamin Herrenschmidt 1971cee72d5bSBenjamin Herrenschmidt /* Detect specific models for error handling */ 1972cee72d5bSBenjamin Herrenschmidt if (of_device_is_compatible(np, "ibm,p7ioc-pciex")) 1973cee72d5bSBenjamin Herrenschmidt phb->model = PNV_PHB_MODEL_P7IOC; 1974f3d40c25SBenjamin Herrenschmidt else if (of_device_is_compatible(np, "ibm,power8-pciex")) 1975aa0c033fSGavin Shan phb->model = PNV_PHB_MODEL_PHB3; 1976cee72d5bSBenjamin Herrenschmidt else 1977cee72d5bSBenjamin Herrenschmidt phb->model = PNV_PHB_MODEL_UNKNOWN; 1978cee72d5bSBenjamin Herrenschmidt 1979aa0c033fSGavin Shan /* Parse 32-bit and IO ranges (if any) */ 19802f1ec02eSGavin Shan pci_process_bridge_OF_ranges(hose, np, !hose->global_number); 1981184cd4a3SBenjamin Herrenschmidt 1982aa0c033fSGavin Shan /* Get registers */ 1983184cd4a3SBenjamin Herrenschmidt phb->regs = of_iomap(np, 0); 1984184cd4a3SBenjamin Herrenschmidt if (phb->regs == NULL) 1985184cd4a3SBenjamin Herrenschmidt pr_err(" Failed to map registers !\n"); 1986184cd4a3SBenjamin Herrenschmidt 1987184cd4a3SBenjamin Herrenschmidt /* Initialize more IODA stuff */ 1988aa0c033fSGavin Shan phb->ioda.total_pe = 1; 198936954dc7SGavin Shan prop32 = of_get_property(np, "ibm,opal-num-pes", NULL); 199036954dc7SGavin Shan if (prop32) 19913a1a4661SBenjamin Herrenschmidt phb->ioda.total_pe = be32_to_cpup(prop32); 199236954dc7SGavin Shan prop32 = of_get_property(np, "ibm,opal-reserved-pe", NULL); 199336954dc7SGavin Shan if (prop32) 199436954dc7SGavin Shan phb->ioda.reserved_pe = be32_to_cpup(prop32); 1995262af557SGuo Chao 1996262af557SGuo Chao /* Parse 64-bit MMIO range */ 1997262af557SGuo Chao pnv_ioda_parse_m64_window(phb); 1998262af557SGuo Chao 1999184cd4a3SBenjamin Herrenschmidt phb->ioda.m32_size = resource_size(&hose->mem_resources[0]); 2000aa0c033fSGavin Shan /* FW Has already off top 64k of M32 space (MSI space) */ 2001184cd4a3SBenjamin Herrenschmidt phb->ioda.m32_size += 0x10000; 2002184cd4a3SBenjamin Herrenschmidt 2003184cd4a3SBenjamin Herrenschmidt phb->ioda.m32_segsize = phb->ioda.m32_size / phb->ioda.total_pe; 20043fd47f06SBenjamin Herrenschmidt phb->ioda.m32_pci_base = hose->mem_resources[0].start - hose->mem_offset[0]; 2005184cd4a3SBenjamin Herrenschmidt phb->ioda.io_size = hose->pci_io_size; 2006184cd4a3SBenjamin Herrenschmidt phb->ioda.io_segsize = phb->ioda.io_size / phb->ioda.total_pe; 2007184cd4a3SBenjamin Herrenschmidt phb->ioda.io_pci_base = 0; /* XXX calculate this ? */ 2008184cd4a3SBenjamin Herrenschmidt 2009c35d2a8cSGavin Shan /* Allocate aux data & arrays. We don't have IO ports on PHB3 */ 2010184cd4a3SBenjamin Herrenschmidt size = _ALIGN_UP(phb->ioda.total_pe / 8, sizeof(unsigned long)); 2011184cd4a3SBenjamin Herrenschmidt m32map_off = size; 2012e47747f4SGavin Shan size += phb->ioda.total_pe * sizeof(phb->ioda.m32_segmap[0]); 2013c35d2a8cSGavin Shan if (phb->type == PNV_PHB_IODA1) { 2014c35d2a8cSGavin Shan iomap_off = size; 2015e47747f4SGavin Shan size += phb->ioda.total_pe * sizeof(phb->ioda.io_segmap[0]); 2016c35d2a8cSGavin Shan } 2017184cd4a3SBenjamin Herrenschmidt pemap_off = size; 2018184cd4a3SBenjamin Herrenschmidt size += phb->ioda.total_pe * sizeof(struct pnv_ioda_pe); 2019e39f223fSMichael Ellerman aux = memblock_virt_alloc(size, 0); 2020184cd4a3SBenjamin Herrenschmidt phb->ioda.pe_alloc = aux; 2021184cd4a3SBenjamin Herrenschmidt phb->ioda.m32_segmap = aux + m32map_off; 2022c35d2a8cSGavin Shan if (phb->type == PNV_PHB_IODA1) 2023184cd4a3SBenjamin Herrenschmidt phb->ioda.io_segmap = aux + iomap_off; 2024184cd4a3SBenjamin Herrenschmidt phb->ioda.pe_array = aux + pemap_off; 202536954dc7SGavin Shan set_bit(phb->ioda.reserved_pe, phb->ioda.pe_alloc); 2026184cd4a3SBenjamin Herrenschmidt 20277ebdf956SGavin Shan INIT_LIST_HEAD(&phb->ioda.pe_dma_list); 2028184cd4a3SBenjamin Herrenschmidt INIT_LIST_HEAD(&phb->ioda.pe_list); 2029184cd4a3SBenjamin Herrenschmidt 2030184cd4a3SBenjamin Herrenschmidt /* Calculate how many 32-bit TCE segments we have */ 2031184cd4a3SBenjamin Herrenschmidt phb->ioda.tce32_count = phb->ioda.m32_pci_base >> 28; 2032184cd4a3SBenjamin Herrenschmidt 2033aa0c033fSGavin Shan #if 0 /* We should really do that ... */ 2034184cd4a3SBenjamin Herrenschmidt rc = opal_pci_set_phb_mem_window(opal->phb_id, 2035184cd4a3SBenjamin Herrenschmidt window_type, 2036184cd4a3SBenjamin Herrenschmidt window_num, 2037184cd4a3SBenjamin Herrenschmidt starting_real_address, 2038184cd4a3SBenjamin Herrenschmidt starting_pci_address, 2039184cd4a3SBenjamin Herrenschmidt segment_size); 2040184cd4a3SBenjamin Herrenschmidt #endif 2041184cd4a3SBenjamin Herrenschmidt 2042262af557SGuo Chao pr_info(" %03d (%03d) PE's M32: 0x%x [segment=0x%x]\n", 2043262af557SGuo Chao phb->ioda.total_pe, phb->ioda.reserved_pe, 2044262af557SGuo Chao phb->ioda.m32_size, phb->ioda.m32_segsize); 2045262af557SGuo Chao if (phb->ioda.m64_size) 2046262af557SGuo Chao pr_info(" M64: 0x%lx [segment=0x%lx]\n", 2047262af557SGuo Chao phb->ioda.m64_size, phb->ioda.m64_segsize); 2048262af557SGuo Chao if (phb->ioda.io_size) 2049262af557SGuo Chao pr_info(" IO: 0x%x [segment=0x%x]\n", 2050184cd4a3SBenjamin Herrenschmidt phb->ioda.io_size, phb->ioda.io_segsize); 2051184cd4a3SBenjamin Herrenschmidt 2052262af557SGuo Chao 2053184cd4a3SBenjamin Herrenschmidt phb->hose->ops = &pnv_pci_ops; 205449dec922SGavin Shan phb->get_pe_state = pnv_ioda_get_pe_state; 205549dec922SGavin Shan phb->freeze_pe = pnv_ioda_freeze_pe; 205649dec922SGavin Shan phb->unfreeze_pe = pnv_ioda_unfreeze_pe; 2057e9cc17d4SGavin Shan #ifdef CONFIG_EEH 2058e9cc17d4SGavin Shan phb->eeh_ops = &ioda_eeh_ops; 2059e9cc17d4SGavin Shan #endif 2060184cd4a3SBenjamin Herrenschmidt 2061184cd4a3SBenjamin Herrenschmidt /* Setup RID -> PE mapping function */ 2062184cd4a3SBenjamin Herrenschmidt phb->bdfn_to_pe = pnv_ioda_bdfn_to_pe; 2063184cd4a3SBenjamin Herrenschmidt 2064184cd4a3SBenjamin Herrenschmidt /* Setup TCEs */ 2065184cd4a3SBenjamin Herrenschmidt phb->dma_dev_setup = pnv_pci_ioda_dma_dev_setup; 2066cd15b048SBenjamin Herrenschmidt phb->dma_set_mask = pnv_pci_ioda_dma_set_mask; 2067fe7e85c6SGavin Shan phb->dma_get_required_mask = pnv_pci_ioda_dma_get_required_mask; 2068184cd4a3SBenjamin Herrenschmidt 206973ed148aSBenjamin Herrenschmidt /* Setup shutdown function for kexec */ 207073ed148aSBenjamin Herrenschmidt phb->shutdown = pnv_pci_ioda_shutdown; 207173ed148aSBenjamin Herrenschmidt 2072184cd4a3SBenjamin Herrenschmidt /* Setup MSI support */ 2073184cd4a3SBenjamin Herrenschmidt pnv_pci_init_ioda_msis(phb); 2074184cd4a3SBenjamin Herrenschmidt 2075c40a4210SGavin Shan /* 2076c40a4210SGavin Shan * We pass the PCI probe flag PCI_REASSIGN_ALL_RSRC here 2077c40a4210SGavin Shan * to let the PCI core do resource assignment. It's supposed 2078c40a4210SGavin Shan * that the PCI core will do correct I/O and MMIO alignment 2079c40a4210SGavin Shan * for the P2P bridge bars so that each PCI bus (excluding 2080c40a4210SGavin Shan * the child P2P bridges) can form individual PE. 2081184cd4a3SBenjamin Herrenschmidt */ 2082fb446ad0SGavin Shan ppc_md.pcibios_fixup = pnv_pci_ioda_fixup; 2083184cd4a3SBenjamin Herrenschmidt ppc_md.pcibios_enable_device_hook = pnv_pci_enable_device_hook; 2084271fd03aSGavin Shan ppc_md.pcibios_window_alignment = pnv_pci_window_alignment; 2085d92a208dSGavin Shan ppc_md.pcibios_reset_secondary_bus = pnv_pci_reset_secondary_bus; 2086c40a4210SGavin Shan pci_add_flags(PCI_REASSIGN_ALL_RSRC); 2087184cd4a3SBenjamin Herrenschmidt 2088184cd4a3SBenjamin Herrenschmidt /* Reset IODA tables to a clean state */ 2089d1a85eeeSGavin Shan rc = opal_pci_reset(phb_id, OPAL_RESET_PCI_IODA_TABLE, OPAL_ASSERT_RESET); 2090184cd4a3SBenjamin Herrenschmidt if (rc) 2091f11fe552SBenjamin Herrenschmidt pr_warning(" OPAL Error %ld performing IODA table reset !\n", rc); 2092361f2a2aSGavin Shan 2093361f2a2aSGavin Shan /* If we're running in kdump kerenl, the previous kerenl never 2094361f2a2aSGavin Shan * shutdown PCI devices correctly. We already got IODA table 2095361f2a2aSGavin Shan * cleaned out. So we have to issue PHB reset to stop all PCI 2096361f2a2aSGavin Shan * transactions from previous kerenl. 2097361f2a2aSGavin Shan */ 2098361f2a2aSGavin Shan if (is_kdump_kernel()) { 2099361f2a2aSGavin Shan pr_info(" Issue PHB reset ...\n"); 2100361f2a2aSGavin Shan ioda_eeh_phb_reset(hose, EEH_RESET_FUNDAMENTAL); 2101360d88a9SGavin Shan ioda_eeh_phb_reset(hose, EEH_RESET_DEACTIVATE); 2102361f2a2aSGavin Shan } 2103262af557SGuo Chao 21049e9e8935SGavin Shan /* Remove M64 resource if we can't configure it successfully */ 21059e9e8935SGavin Shan if (!phb->init_m64 || phb->init_m64(phb)) 2106262af557SGuo Chao hose->mem_resources[1].flags = 0; 2107184cd4a3SBenjamin Herrenschmidt } 2108184cd4a3SBenjamin Herrenschmidt 210967975005SBjorn Helgaas void __init pnv_pci_init_ioda2_phb(struct device_node *np) 2110aa0c033fSGavin Shan { 2111e9cc17d4SGavin Shan pnv_pci_init_ioda_phb(np, 0, PNV_PHB_IODA2); 2112aa0c033fSGavin Shan } 2113aa0c033fSGavin Shan 2114184cd4a3SBenjamin Herrenschmidt void __init pnv_pci_init_ioda_hub(struct device_node *np) 2115184cd4a3SBenjamin Herrenschmidt { 2116184cd4a3SBenjamin Herrenschmidt struct device_node *phbn; 2117c681b93cSAlistair Popple const __be64 *prop64; 2118184cd4a3SBenjamin Herrenschmidt u64 hub_id; 2119184cd4a3SBenjamin Herrenschmidt 2120184cd4a3SBenjamin Herrenschmidt pr_info("Probing IODA IO-Hub %s\n", np->full_name); 2121184cd4a3SBenjamin Herrenschmidt 2122184cd4a3SBenjamin Herrenschmidt prop64 = of_get_property(np, "ibm,opal-hubid", NULL); 2123184cd4a3SBenjamin Herrenschmidt if (!prop64) { 2124184cd4a3SBenjamin Herrenschmidt pr_err(" Missing \"ibm,opal-hubid\" property !\n"); 2125184cd4a3SBenjamin Herrenschmidt return; 2126184cd4a3SBenjamin Herrenschmidt } 2127184cd4a3SBenjamin Herrenschmidt hub_id = be64_to_cpup(prop64); 2128184cd4a3SBenjamin Herrenschmidt pr_devel(" HUB-ID : 0x%016llx\n", hub_id); 2129184cd4a3SBenjamin Herrenschmidt 2130184cd4a3SBenjamin Herrenschmidt /* Count child PHBs */ 2131184cd4a3SBenjamin Herrenschmidt for_each_child_of_node(np, phbn) { 2132184cd4a3SBenjamin Herrenschmidt /* Look for IODA1 PHBs */ 2133184cd4a3SBenjamin Herrenschmidt if (of_device_is_compatible(phbn, "ibm,ioda-phb")) 2134e9cc17d4SGavin Shan pnv_pci_init_ioda_phb(phbn, hub_id, PNV_PHB_IODA1); 2135184cd4a3SBenjamin Herrenschmidt } 2136184cd4a3SBenjamin Herrenschmidt } 2137