1184cd4a3SBenjamin Herrenschmidt /* 2184cd4a3SBenjamin Herrenschmidt * Support PCI/PCIe on PowerNV platforms 3184cd4a3SBenjamin Herrenschmidt * 4184cd4a3SBenjamin Herrenschmidt * Copyright 2011 Benjamin Herrenschmidt, IBM Corp. 5184cd4a3SBenjamin Herrenschmidt * 6184cd4a3SBenjamin Herrenschmidt * This program is free software; you can redistribute it and/or 7184cd4a3SBenjamin Herrenschmidt * modify it under the terms of the GNU General Public License 8184cd4a3SBenjamin Herrenschmidt * as published by the Free Software Foundation; either version 9184cd4a3SBenjamin Herrenschmidt * 2 of the License, or (at your option) any later version. 10184cd4a3SBenjamin Herrenschmidt */ 11184cd4a3SBenjamin Herrenschmidt 12cee72d5bSBenjamin Herrenschmidt #undef DEBUG 13184cd4a3SBenjamin Herrenschmidt 14184cd4a3SBenjamin Herrenschmidt #include <linux/kernel.h> 15184cd4a3SBenjamin Herrenschmidt #include <linux/pci.h> 16361f2a2aSGavin Shan #include <linux/crash_dump.h> 1737c367f2SGavin Shan #include <linux/debugfs.h> 18184cd4a3SBenjamin Herrenschmidt #include <linux/delay.h> 19184cd4a3SBenjamin Herrenschmidt #include <linux/string.h> 20184cd4a3SBenjamin Herrenschmidt #include <linux/init.h> 21184cd4a3SBenjamin Herrenschmidt #include <linux/bootmem.h> 22184cd4a3SBenjamin Herrenschmidt #include <linux/irq.h> 23184cd4a3SBenjamin Herrenschmidt #include <linux/io.h> 24184cd4a3SBenjamin Herrenschmidt #include <linux/msi.h> 25cd15b048SBenjamin Herrenschmidt #include <linux/memblock.h> 26ac9a5889SAlexey Kardashevskiy #include <linux/iommu.h> 27e57080f1SAlexey Kardashevskiy #include <linux/rculist.h> 284793d65dSAlexey Kardashevskiy #include <linux/sizes.h> 29184cd4a3SBenjamin Herrenschmidt 30184cd4a3SBenjamin Herrenschmidt #include <asm/sections.h> 31184cd4a3SBenjamin Herrenschmidt #include <asm/io.h> 32184cd4a3SBenjamin Herrenschmidt #include <asm/prom.h> 33184cd4a3SBenjamin Herrenschmidt #include <asm/pci-bridge.h> 34184cd4a3SBenjamin Herrenschmidt #include <asm/machdep.h> 35fb1b55d6SGavin Shan #include <asm/msi_bitmap.h> 36184cd4a3SBenjamin Herrenschmidt #include <asm/ppc-pci.h> 37184cd4a3SBenjamin Herrenschmidt #include <asm/opal.h> 38184cd4a3SBenjamin Herrenschmidt #include <asm/iommu.h> 39184cd4a3SBenjamin Herrenschmidt #include <asm/tce.h> 40137436c9SGavin Shan #include <asm/xics.h> 4137c367f2SGavin Shan #include <asm/debug.h> 42262af557SGuo Chao #include <asm/firmware.h> 4380c49c7eSIan Munsie #include <asm/pnv-pci.h> 44aca6913fSAlexey Kardashevskiy #include <asm/mmzone.h> 4580c49c7eSIan Munsie 46ec249dd8SMichael Neuling #include <misc/cxl-base.h> 47184cd4a3SBenjamin Herrenschmidt 48184cd4a3SBenjamin Herrenschmidt #include "powernv.h" 49184cd4a3SBenjamin Herrenschmidt #include "pci.h" 50184cd4a3SBenjamin Herrenschmidt 51781a868fSWei Yang /* 256M DMA window, 4K TCE pages, 8 bytes TCE */ 52781a868fSWei Yang #define TCE32_TABLE_SIZE ((0x10000000 / 0x1000) * 8) 53781a868fSWei Yang 54bbb845c4SAlexey Kardashevskiy #define POWERNV_IOMMU_DEFAULT_LEVELS 1 55bbb845c4SAlexey Kardashevskiy #define POWERNV_IOMMU_MAX_LEVELS 5 56bbb845c4SAlexey Kardashevskiy 57aca6913fSAlexey Kardashevskiy static void pnv_pci_ioda2_table_free_pages(struct iommu_table *tbl); 58aca6913fSAlexey Kardashevskiy 596d31c2faSJoe Perches static void pe_level_printk(const struct pnv_ioda_pe *pe, const char *level, 606d31c2faSJoe Perches const char *fmt, ...) 616d31c2faSJoe Perches { 626d31c2faSJoe Perches struct va_format vaf; 636d31c2faSJoe Perches va_list args; 646d31c2faSJoe Perches char pfix[32]; 65184cd4a3SBenjamin Herrenschmidt 666d31c2faSJoe Perches va_start(args, fmt); 676d31c2faSJoe Perches 686d31c2faSJoe Perches vaf.fmt = fmt; 696d31c2faSJoe Perches vaf.va = &args; 706d31c2faSJoe Perches 71781a868fSWei Yang if (pe->flags & PNV_IODA_PE_DEV) 726d31c2faSJoe Perches strlcpy(pfix, dev_name(&pe->pdev->dev), sizeof(pfix)); 73781a868fSWei Yang else if (pe->flags & (PNV_IODA_PE_BUS | PNV_IODA_PE_BUS_ALL)) 746d31c2faSJoe Perches sprintf(pfix, "%04x:%02x ", 756d31c2faSJoe Perches pci_domain_nr(pe->pbus), pe->pbus->number); 76781a868fSWei Yang #ifdef CONFIG_PCI_IOV 77781a868fSWei Yang else if (pe->flags & PNV_IODA_PE_VF) 78781a868fSWei Yang sprintf(pfix, "%04x:%02x:%2x.%d", 79781a868fSWei Yang pci_domain_nr(pe->parent_dev->bus), 80781a868fSWei Yang (pe->rid & 0xff00) >> 8, 81781a868fSWei Yang PCI_SLOT(pe->rid), PCI_FUNC(pe->rid)); 82781a868fSWei Yang #endif /* CONFIG_PCI_IOV*/ 836d31c2faSJoe Perches 846d31c2faSJoe Perches printk("%spci %s: [PE# %.3d] %pV", 856d31c2faSJoe Perches level, pfix, pe->pe_number, &vaf); 866d31c2faSJoe Perches 876d31c2faSJoe Perches va_end(args); 886d31c2faSJoe Perches } 896d31c2faSJoe Perches 906d31c2faSJoe Perches #define pe_err(pe, fmt, ...) \ 916d31c2faSJoe Perches pe_level_printk(pe, KERN_ERR, fmt, ##__VA_ARGS__) 926d31c2faSJoe Perches #define pe_warn(pe, fmt, ...) \ 936d31c2faSJoe Perches pe_level_printk(pe, KERN_WARNING, fmt, ##__VA_ARGS__) 946d31c2faSJoe Perches #define pe_info(pe, fmt, ...) \ 956d31c2faSJoe Perches pe_level_printk(pe, KERN_INFO, fmt, ##__VA_ARGS__) 96184cd4a3SBenjamin Herrenschmidt 974e287840SThadeu Lima de Souza Cascardo static bool pnv_iommu_bypass_disabled __read_mostly; 984e287840SThadeu Lima de Souza Cascardo 994e287840SThadeu Lima de Souza Cascardo static int __init iommu_setup(char *str) 1004e287840SThadeu Lima de Souza Cascardo { 1014e287840SThadeu Lima de Souza Cascardo if (!str) 1024e287840SThadeu Lima de Souza Cascardo return -EINVAL; 1034e287840SThadeu Lima de Souza Cascardo 1044e287840SThadeu Lima de Souza Cascardo while (*str) { 1054e287840SThadeu Lima de Souza Cascardo if (!strncmp(str, "nobypass", 8)) { 1064e287840SThadeu Lima de Souza Cascardo pnv_iommu_bypass_disabled = true; 1074e287840SThadeu Lima de Souza Cascardo pr_info("PowerNV: IOMMU bypass window disabled.\n"); 1084e287840SThadeu Lima de Souza Cascardo break; 1094e287840SThadeu Lima de Souza Cascardo } 1104e287840SThadeu Lima de Souza Cascardo str += strcspn(str, ","); 1114e287840SThadeu Lima de Souza Cascardo if (*str == ',') 1124e287840SThadeu Lima de Souza Cascardo str++; 1134e287840SThadeu Lima de Souza Cascardo } 1144e287840SThadeu Lima de Souza Cascardo 1154e287840SThadeu Lima de Souza Cascardo return 0; 1164e287840SThadeu Lima de Souza Cascardo } 1174e287840SThadeu Lima de Souza Cascardo early_param("iommu", iommu_setup); 1184e287840SThadeu Lima de Souza Cascardo 1198e0a1611SAlexey Kardashevskiy /* 1208e0a1611SAlexey Kardashevskiy * stdcix is only supposed to be used in hypervisor real mode as per 1218e0a1611SAlexey Kardashevskiy * the architecture spec 1228e0a1611SAlexey Kardashevskiy */ 1238e0a1611SAlexey Kardashevskiy static inline void __raw_rm_writeq(u64 val, volatile void __iomem *paddr) 1248e0a1611SAlexey Kardashevskiy { 1258e0a1611SAlexey Kardashevskiy __asm__ __volatile__("stdcix %0,0,%1" 1268e0a1611SAlexey Kardashevskiy : : "r" (val), "r" (paddr) : "memory"); 1278e0a1611SAlexey Kardashevskiy } 1288e0a1611SAlexey Kardashevskiy 129262af557SGuo Chao static inline bool pnv_pci_is_mem_pref_64(unsigned long flags) 130262af557SGuo Chao { 131262af557SGuo Chao return ((flags & (IORESOURCE_MEM_64 | IORESOURCE_PREFETCH)) == 132262af557SGuo Chao (IORESOURCE_MEM_64 | IORESOURCE_PREFETCH)); 133262af557SGuo Chao } 134262af557SGuo Chao 1354b82ab18SGavin Shan static void pnv_ioda_reserve_pe(struct pnv_phb *phb, int pe_no) 1364b82ab18SGavin Shan { 1374b82ab18SGavin Shan if (!(pe_no >= 0 && pe_no < phb->ioda.total_pe)) { 1384b82ab18SGavin Shan pr_warn("%s: Invalid PE %d on PHB#%x\n", 1394b82ab18SGavin Shan __func__, pe_no, phb->hose->global_number); 1404b82ab18SGavin Shan return; 1414b82ab18SGavin Shan } 1424b82ab18SGavin Shan 143e9dc4d7fSGavin Shan if (test_and_set_bit(pe_no, phb->ioda.pe_alloc)) 144e9dc4d7fSGavin Shan pr_debug("%s: PE %d was reserved on PHB#%x\n", 1454b82ab18SGavin Shan __func__, pe_no, phb->hose->global_number); 1464b82ab18SGavin Shan 1474b82ab18SGavin Shan phb->ioda.pe_array[pe_no].phb = phb; 1484b82ab18SGavin Shan phb->ioda.pe_array[pe_no].pe_number = pe_no; 1494b82ab18SGavin Shan } 1504b82ab18SGavin Shan 151cad5cef6SGreg Kroah-Hartman static int pnv_ioda_alloc_pe(struct pnv_phb *phb) 152184cd4a3SBenjamin Herrenschmidt { 153184cd4a3SBenjamin Herrenschmidt unsigned long pe; 154184cd4a3SBenjamin Herrenschmidt 155184cd4a3SBenjamin Herrenschmidt do { 156184cd4a3SBenjamin Herrenschmidt pe = find_next_zero_bit(phb->ioda.pe_alloc, 157184cd4a3SBenjamin Herrenschmidt phb->ioda.total_pe, 0); 158184cd4a3SBenjamin Herrenschmidt if (pe >= phb->ioda.total_pe) 159184cd4a3SBenjamin Herrenschmidt return IODA_INVALID_PE; 160184cd4a3SBenjamin Herrenschmidt } while(test_and_set_bit(pe, phb->ioda.pe_alloc)); 161184cd4a3SBenjamin Herrenschmidt 1624cce9550SGavin Shan phb->ioda.pe_array[pe].phb = phb; 163184cd4a3SBenjamin Herrenschmidt phb->ioda.pe_array[pe].pe_number = pe; 164184cd4a3SBenjamin Herrenschmidt return pe; 165184cd4a3SBenjamin Herrenschmidt } 166184cd4a3SBenjamin Herrenschmidt 167cad5cef6SGreg Kroah-Hartman static void pnv_ioda_free_pe(struct pnv_phb *phb, int pe) 168184cd4a3SBenjamin Herrenschmidt { 169184cd4a3SBenjamin Herrenschmidt WARN_ON(phb->ioda.pe_array[pe].pdev); 170184cd4a3SBenjamin Herrenschmidt 171184cd4a3SBenjamin Herrenschmidt memset(&phb->ioda.pe_array[pe], 0, sizeof(struct pnv_ioda_pe)); 172184cd4a3SBenjamin Herrenschmidt clear_bit(pe, phb->ioda.pe_alloc); 173184cd4a3SBenjamin Herrenschmidt } 174184cd4a3SBenjamin Herrenschmidt 175262af557SGuo Chao /* The default M64 BAR is shared by all PEs */ 176262af557SGuo Chao static int pnv_ioda2_init_m64(struct pnv_phb *phb) 177262af557SGuo Chao { 178262af557SGuo Chao const char *desc; 179262af557SGuo Chao struct resource *r; 180262af557SGuo Chao s64 rc; 181262af557SGuo Chao 182262af557SGuo Chao /* Configure the default M64 BAR */ 183262af557SGuo Chao rc = opal_pci_set_phb_mem_window(phb->opal_id, 184262af557SGuo Chao OPAL_M64_WINDOW_TYPE, 185262af557SGuo Chao phb->ioda.m64_bar_idx, 186262af557SGuo Chao phb->ioda.m64_base, 187262af557SGuo Chao 0, /* unused */ 188262af557SGuo Chao phb->ioda.m64_size); 189262af557SGuo Chao if (rc != OPAL_SUCCESS) { 190262af557SGuo Chao desc = "configuring"; 191262af557SGuo Chao goto fail; 192262af557SGuo Chao } 193262af557SGuo Chao 194262af557SGuo Chao /* Enable the default M64 BAR */ 195262af557SGuo Chao rc = opal_pci_phb_mmio_enable(phb->opal_id, 196262af557SGuo Chao OPAL_M64_WINDOW_TYPE, 197262af557SGuo Chao phb->ioda.m64_bar_idx, 198262af557SGuo Chao OPAL_ENABLE_M64_SPLIT); 199262af557SGuo Chao if (rc != OPAL_SUCCESS) { 200262af557SGuo Chao desc = "enabling"; 201262af557SGuo Chao goto fail; 202262af557SGuo Chao } 203262af557SGuo Chao 204262af557SGuo Chao /* Mark the M64 BAR assigned */ 205262af557SGuo Chao set_bit(phb->ioda.m64_bar_idx, &phb->ioda.m64_bar_alloc); 206262af557SGuo Chao 207262af557SGuo Chao /* 208262af557SGuo Chao * Strip off the segment used by the reserved PE, which is 209262af557SGuo Chao * expected to be 0 or last one of PE capabicity. 210262af557SGuo Chao */ 211262af557SGuo Chao r = &phb->hose->mem_resources[1]; 212262af557SGuo Chao if (phb->ioda.reserved_pe == 0) 213262af557SGuo Chao r->start += phb->ioda.m64_segsize; 214262af557SGuo Chao else if (phb->ioda.reserved_pe == (phb->ioda.total_pe - 1)) 215262af557SGuo Chao r->end -= phb->ioda.m64_segsize; 216262af557SGuo Chao else 217262af557SGuo Chao pr_warn(" Cannot strip M64 segment for reserved PE#%d\n", 218262af557SGuo Chao phb->ioda.reserved_pe); 219262af557SGuo Chao 220262af557SGuo Chao return 0; 221262af557SGuo Chao 222262af557SGuo Chao fail: 223262af557SGuo Chao pr_warn(" Failure %lld %s M64 BAR#%d\n", 224262af557SGuo Chao rc, desc, phb->ioda.m64_bar_idx); 225262af557SGuo Chao opal_pci_phb_mmio_enable(phb->opal_id, 226262af557SGuo Chao OPAL_M64_WINDOW_TYPE, 227262af557SGuo Chao phb->ioda.m64_bar_idx, 228262af557SGuo Chao OPAL_DISABLE_M64); 229262af557SGuo Chao return -EIO; 230262af557SGuo Chao } 231262af557SGuo Chao 23296a2f92bSGavin Shan static void pnv_ioda2_reserve_dev_m64_pe(struct pci_dev *pdev, 23396a2f92bSGavin Shan unsigned long *pe_bitmap) 234262af557SGuo Chao { 23596a2f92bSGavin Shan struct pci_controller *hose = pci_bus_to_host(pdev->bus); 23696a2f92bSGavin Shan struct pnv_phb *phb = hose->private_data; 237262af557SGuo Chao struct resource *r; 23896a2f92bSGavin Shan resource_size_t base, sgsz, start, end; 23996a2f92bSGavin Shan int segno, i; 240262af557SGuo Chao 24196a2f92bSGavin Shan base = phb->ioda.m64_base; 24296a2f92bSGavin Shan sgsz = phb->ioda.m64_segsize; 24396a2f92bSGavin Shan for (i = 0; i <= PCI_ROM_RESOURCE; i++) { 24496a2f92bSGavin Shan r = &pdev->resource[i]; 24596a2f92bSGavin Shan if (!r->parent || !pnv_pci_is_mem_pref_64(r->flags)) 246262af557SGuo Chao continue; 247262af557SGuo Chao 24896a2f92bSGavin Shan start = _ALIGN_DOWN(r->start - base, sgsz); 24996a2f92bSGavin Shan end = _ALIGN_UP(r->end - base, sgsz); 25096a2f92bSGavin Shan for (segno = start / sgsz; segno < end / sgsz; segno++) { 25196a2f92bSGavin Shan if (pe_bitmap) 25296a2f92bSGavin Shan set_bit(segno, pe_bitmap); 25396a2f92bSGavin Shan else 25496a2f92bSGavin Shan pnv_ioda_reserve_pe(phb, segno); 255262af557SGuo Chao } 256262af557SGuo Chao } 257262af557SGuo Chao } 258262af557SGuo Chao 25996a2f92bSGavin Shan static void pnv_ioda2_reserve_m64_pe(struct pci_bus *bus, 26096a2f92bSGavin Shan unsigned long *pe_bitmap, 26196a2f92bSGavin Shan bool all) 262262af557SGuo Chao { 263262af557SGuo Chao struct pci_dev *pdev; 26496a2f92bSGavin Shan 26596a2f92bSGavin Shan list_for_each_entry(pdev, &bus->devices, bus_list) { 26696a2f92bSGavin Shan pnv_ioda2_reserve_dev_m64_pe(pdev, pe_bitmap); 26796a2f92bSGavin Shan 26896a2f92bSGavin Shan if (all && pdev->subordinate) 26996a2f92bSGavin Shan pnv_ioda2_reserve_m64_pe(pdev->subordinate, 27096a2f92bSGavin Shan pe_bitmap, all); 27196a2f92bSGavin Shan } 27296a2f92bSGavin Shan } 27396a2f92bSGavin Shan 27426ba248dSGavin Shan static int pnv_ioda2_pick_m64_pe(struct pci_bus *bus, bool all) 275262af557SGuo Chao { 27626ba248dSGavin Shan struct pci_controller *hose = pci_bus_to_host(bus); 27726ba248dSGavin Shan struct pnv_phb *phb = hose->private_data; 278262af557SGuo Chao struct pnv_ioda_pe *master_pe, *pe; 279262af557SGuo Chao unsigned long size, *pe_alloc; 28026ba248dSGavin Shan int i; 281262af557SGuo Chao 282262af557SGuo Chao /* Root bus shouldn't use M64 */ 283262af557SGuo Chao if (pci_is_root_bus(bus)) 284262af557SGuo Chao return IODA_INVALID_PE; 285262af557SGuo Chao 286262af557SGuo Chao /* Allocate bitmap */ 287262af557SGuo Chao size = _ALIGN_UP(phb->ioda.total_pe / 8, sizeof(unsigned long)); 288262af557SGuo Chao pe_alloc = kzalloc(size, GFP_KERNEL); 289262af557SGuo Chao if (!pe_alloc) { 290262af557SGuo Chao pr_warn("%s: Out of memory !\n", 291262af557SGuo Chao __func__); 292262af557SGuo Chao return IODA_INVALID_PE; 293262af557SGuo Chao } 294262af557SGuo Chao 29526ba248dSGavin Shan /* Figure out reserved PE numbers by the PE */ 29626ba248dSGavin Shan pnv_ioda2_reserve_m64_pe(bus, pe_alloc, all); 297262af557SGuo Chao 298262af557SGuo Chao /* 299262af557SGuo Chao * the current bus might not own M64 window and that's all 300262af557SGuo Chao * contributed by its child buses. For the case, we needn't 301262af557SGuo Chao * pick M64 dependent PE#. 302262af557SGuo Chao */ 303262af557SGuo Chao if (bitmap_empty(pe_alloc, phb->ioda.total_pe)) { 304262af557SGuo Chao kfree(pe_alloc); 305262af557SGuo Chao return IODA_INVALID_PE; 306262af557SGuo Chao } 307262af557SGuo Chao 308262af557SGuo Chao /* 309262af557SGuo Chao * Figure out the master PE and put all slave PEs to master 310262af557SGuo Chao * PE's list to form compound PE. 311262af557SGuo Chao */ 312262af557SGuo Chao master_pe = NULL; 313262af557SGuo Chao i = -1; 314262af557SGuo Chao while ((i = find_next_bit(pe_alloc, phb->ioda.total_pe, i + 1)) < 315262af557SGuo Chao phb->ioda.total_pe) { 316262af557SGuo Chao pe = &phb->ioda.pe_array[i]; 317262af557SGuo Chao 318262af557SGuo Chao if (!master_pe) { 319262af557SGuo Chao pe->flags |= PNV_IODA_PE_MASTER; 320262af557SGuo Chao INIT_LIST_HEAD(&pe->slaves); 321262af557SGuo Chao master_pe = pe; 322262af557SGuo Chao } else { 323262af557SGuo Chao pe->flags |= PNV_IODA_PE_SLAVE; 324262af557SGuo Chao pe->master = master_pe; 325262af557SGuo Chao list_add_tail(&pe->list, &master_pe->slaves); 326262af557SGuo Chao } 327262af557SGuo Chao } 328262af557SGuo Chao 329262af557SGuo Chao kfree(pe_alloc); 330262af557SGuo Chao return master_pe->pe_number; 331262af557SGuo Chao } 332262af557SGuo Chao 333262af557SGuo Chao static void __init pnv_ioda_parse_m64_window(struct pnv_phb *phb) 334262af557SGuo Chao { 335262af557SGuo Chao struct pci_controller *hose = phb->hose; 336262af557SGuo Chao struct device_node *dn = hose->dn; 337262af557SGuo Chao struct resource *res; 338262af557SGuo Chao const u32 *r; 339262af557SGuo Chao u64 pci_addr; 340262af557SGuo Chao 3411665c4a8SGavin Shan /* FIXME: Support M64 for P7IOC */ 3421665c4a8SGavin Shan if (phb->type != PNV_PHB_IODA2) { 3431665c4a8SGavin Shan pr_info(" Not support M64 window\n"); 3441665c4a8SGavin Shan return; 3451665c4a8SGavin Shan } 3461665c4a8SGavin Shan 347e4d54f71SStewart Smith if (!firmware_has_feature(FW_FEATURE_OPAL)) { 348262af557SGuo Chao pr_info(" Firmware too old to support M64 window\n"); 349262af557SGuo Chao return; 350262af557SGuo Chao } 351262af557SGuo Chao 352262af557SGuo Chao r = of_get_property(dn, "ibm,opal-m64-window", NULL); 353262af557SGuo Chao if (!r) { 354262af557SGuo Chao pr_info(" No <ibm,opal-m64-window> on %s\n", 355262af557SGuo Chao dn->full_name); 356262af557SGuo Chao return; 357262af557SGuo Chao } 358262af557SGuo Chao 359262af557SGuo Chao res = &hose->mem_resources[1]; 360e80c4e7cSGavin Shan res->name = dn->full_name; 361262af557SGuo Chao res->start = of_translate_address(dn, r + 2); 362262af557SGuo Chao res->end = res->start + of_read_number(r + 4, 2) - 1; 363262af557SGuo Chao res->flags = (IORESOURCE_MEM | IORESOURCE_MEM_64 | IORESOURCE_PREFETCH); 364262af557SGuo Chao pci_addr = of_read_number(r, 2); 365262af557SGuo Chao hose->mem_offset[1] = res->start - pci_addr; 366262af557SGuo Chao 367262af557SGuo Chao phb->ioda.m64_size = resource_size(res); 368262af557SGuo Chao phb->ioda.m64_segsize = phb->ioda.m64_size / phb->ioda.total_pe; 369262af557SGuo Chao phb->ioda.m64_base = pci_addr; 370262af557SGuo Chao 371e9863e68SWei Yang pr_info(" MEM64 0x%016llx..0x%016llx -> 0x%016llx\n", 372e9863e68SWei Yang res->start, res->end, pci_addr); 373e9863e68SWei Yang 374262af557SGuo Chao /* Use last M64 BAR to cover M64 window */ 375262af557SGuo Chao phb->ioda.m64_bar_idx = 15; 376262af557SGuo Chao phb->init_m64 = pnv_ioda2_init_m64; 3775ef73567SGavin Shan phb->reserve_m64_pe = pnv_ioda2_reserve_m64_pe; 378262af557SGuo Chao phb->pick_m64_pe = pnv_ioda2_pick_m64_pe; 379262af557SGuo Chao } 380262af557SGuo Chao 38149dec922SGavin Shan static void pnv_ioda_freeze_pe(struct pnv_phb *phb, int pe_no) 38249dec922SGavin Shan { 38349dec922SGavin Shan struct pnv_ioda_pe *pe = &phb->ioda.pe_array[pe_no]; 38449dec922SGavin Shan struct pnv_ioda_pe *slave; 38549dec922SGavin Shan s64 rc; 38649dec922SGavin Shan 38749dec922SGavin Shan /* Fetch master PE */ 38849dec922SGavin Shan if (pe->flags & PNV_IODA_PE_SLAVE) { 38949dec922SGavin Shan pe = pe->master; 390ec8e4e9dSGavin Shan if (WARN_ON(!pe || !(pe->flags & PNV_IODA_PE_MASTER))) 391ec8e4e9dSGavin Shan return; 392ec8e4e9dSGavin Shan 39349dec922SGavin Shan pe_no = pe->pe_number; 39449dec922SGavin Shan } 39549dec922SGavin Shan 39649dec922SGavin Shan /* Freeze master PE */ 39749dec922SGavin Shan rc = opal_pci_eeh_freeze_set(phb->opal_id, 39849dec922SGavin Shan pe_no, 39949dec922SGavin Shan OPAL_EEH_ACTION_SET_FREEZE_ALL); 40049dec922SGavin Shan if (rc != OPAL_SUCCESS) { 40149dec922SGavin Shan pr_warn("%s: Failure %lld freezing PHB#%x-PE#%x\n", 40249dec922SGavin Shan __func__, rc, phb->hose->global_number, pe_no); 40349dec922SGavin Shan return; 40449dec922SGavin Shan } 40549dec922SGavin Shan 40649dec922SGavin Shan /* Freeze slave PEs */ 40749dec922SGavin Shan if (!(pe->flags & PNV_IODA_PE_MASTER)) 40849dec922SGavin Shan return; 40949dec922SGavin Shan 41049dec922SGavin Shan list_for_each_entry(slave, &pe->slaves, list) { 41149dec922SGavin Shan rc = opal_pci_eeh_freeze_set(phb->opal_id, 41249dec922SGavin Shan slave->pe_number, 41349dec922SGavin Shan OPAL_EEH_ACTION_SET_FREEZE_ALL); 41449dec922SGavin Shan if (rc != OPAL_SUCCESS) 41549dec922SGavin Shan pr_warn("%s: Failure %lld freezing PHB#%x-PE#%x\n", 41649dec922SGavin Shan __func__, rc, phb->hose->global_number, 41749dec922SGavin Shan slave->pe_number); 41849dec922SGavin Shan } 41949dec922SGavin Shan } 42049dec922SGavin Shan 421e51df2c1SAnton Blanchard static int pnv_ioda_unfreeze_pe(struct pnv_phb *phb, int pe_no, int opt) 42249dec922SGavin Shan { 42349dec922SGavin Shan struct pnv_ioda_pe *pe, *slave; 42449dec922SGavin Shan s64 rc; 42549dec922SGavin Shan 42649dec922SGavin Shan /* Find master PE */ 42749dec922SGavin Shan pe = &phb->ioda.pe_array[pe_no]; 42849dec922SGavin Shan if (pe->flags & PNV_IODA_PE_SLAVE) { 42949dec922SGavin Shan pe = pe->master; 43049dec922SGavin Shan WARN_ON(!pe || !(pe->flags & PNV_IODA_PE_MASTER)); 43149dec922SGavin Shan pe_no = pe->pe_number; 43249dec922SGavin Shan } 43349dec922SGavin Shan 43449dec922SGavin Shan /* Clear frozen state for master PE */ 43549dec922SGavin Shan rc = opal_pci_eeh_freeze_clear(phb->opal_id, pe_no, opt); 43649dec922SGavin Shan if (rc != OPAL_SUCCESS) { 43749dec922SGavin Shan pr_warn("%s: Failure %lld clear %d on PHB#%x-PE#%x\n", 43849dec922SGavin Shan __func__, rc, opt, phb->hose->global_number, pe_no); 43949dec922SGavin Shan return -EIO; 44049dec922SGavin Shan } 44149dec922SGavin Shan 44249dec922SGavin Shan if (!(pe->flags & PNV_IODA_PE_MASTER)) 44349dec922SGavin Shan return 0; 44449dec922SGavin Shan 44549dec922SGavin Shan /* Clear frozen state for slave PEs */ 44649dec922SGavin Shan list_for_each_entry(slave, &pe->slaves, list) { 44749dec922SGavin Shan rc = opal_pci_eeh_freeze_clear(phb->opal_id, 44849dec922SGavin Shan slave->pe_number, 44949dec922SGavin Shan opt); 45049dec922SGavin Shan if (rc != OPAL_SUCCESS) { 45149dec922SGavin Shan pr_warn("%s: Failure %lld clear %d on PHB#%x-PE#%x\n", 45249dec922SGavin Shan __func__, rc, opt, phb->hose->global_number, 45349dec922SGavin Shan slave->pe_number); 45449dec922SGavin Shan return -EIO; 45549dec922SGavin Shan } 45649dec922SGavin Shan } 45749dec922SGavin Shan 45849dec922SGavin Shan return 0; 45949dec922SGavin Shan } 46049dec922SGavin Shan 46149dec922SGavin Shan static int pnv_ioda_get_pe_state(struct pnv_phb *phb, int pe_no) 46249dec922SGavin Shan { 46349dec922SGavin Shan struct pnv_ioda_pe *slave, *pe; 46449dec922SGavin Shan u8 fstate, state; 46549dec922SGavin Shan __be16 pcierr; 46649dec922SGavin Shan s64 rc; 46749dec922SGavin Shan 46849dec922SGavin Shan /* Sanity check on PE number */ 46949dec922SGavin Shan if (pe_no < 0 || pe_no >= phb->ioda.total_pe) 47049dec922SGavin Shan return OPAL_EEH_STOPPED_PERM_UNAVAIL; 47149dec922SGavin Shan 47249dec922SGavin Shan /* 47349dec922SGavin Shan * Fetch the master PE and the PE instance might be 47449dec922SGavin Shan * not initialized yet. 47549dec922SGavin Shan */ 47649dec922SGavin Shan pe = &phb->ioda.pe_array[pe_no]; 47749dec922SGavin Shan if (pe->flags & PNV_IODA_PE_SLAVE) { 47849dec922SGavin Shan pe = pe->master; 47949dec922SGavin Shan WARN_ON(!pe || !(pe->flags & PNV_IODA_PE_MASTER)); 48049dec922SGavin Shan pe_no = pe->pe_number; 48149dec922SGavin Shan } 48249dec922SGavin Shan 48349dec922SGavin Shan /* Check the master PE */ 48449dec922SGavin Shan rc = opal_pci_eeh_freeze_status(phb->opal_id, pe_no, 48549dec922SGavin Shan &state, &pcierr, NULL); 48649dec922SGavin Shan if (rc != OPAL_SUCCESS) { 48749dec922SGavin Shan pr_warn("%s: Failure %lld getting " 48849dec922SGavin Shan "PHB#%x-PE#%x state\n", 48949dec922SGavin Shan __func__, rc, 49049dec922SGavin Shan phb->hose->global_number, pe_no); 49149dec922SGavin Shan return OPAL_EEH_STOPPED_TEMP_UNAVAIL; 49249dec922SGavin Shan } 49349dec922SGavin Shan 49449dec922SGavin Shan /* Check the slave PE */ 49549dec922SGavin Shan if (!(pe->flags & PNV_IODA_PE_MASTER)) 49649dec922SGavin Shan return state; 49749dec922SGavin Shan 49849dec922SGavin Shan list_for_each_entry(slave, &pe->slaves, list) { 49949dec922SGavin Shan rc = opal_pci_eeh_freeze_status(phb->opal_id, 50049dec922SGavin Shan slave->pe_number, 50149dec922SGavin Shan &fstate, 50249dec922SGavin Shan &pcierr, 50349dec922SGavin Shan NULL); 50449dec922SGavin Shan if (rc != OPAL_SUCCESS) { 50549dec922SGavin Shan pr_warn("%s: Failure %lld getting " 50649dec922SGavin Shan "PHB#%x-PE#%x state\n", 50749dec922SGavin Shan __func__, rc, 50849dec922SGavin Shan phb->hose->global_number, slave->pe_number); 50949dec922SGavin Shan return OPAL_EEH_STOPPED_TEMP_UNAVAIL; 51049dec922SGavin Shan } 51149dec922SGavin Shan 51249dec922SGavin Shan /* 51349dec922SGavin Shan * Override the result based on the ascending 51449dec922SGavin Shan * priority. 51549dec922SGavin Shan */ 51649dec922SGavin Shan if (fstate > state) 51749dec922SGavin Shan state = fstate; 51849dec922SGavin Shan } 51949dec922SGavin Shan 52049dec922SGavin Shan return state; 52149dec922SGavin Shan } 52249dec922SGavin Shan 523184cd4a3SBenjamin Herrenschmidt /* Currently those 2 are only used when MSIs are enabled, this will change 524184cd4a3SBenjamin Herrenschmidt * but in the meantime, we need to protect them to avoid warnings 525184cd4a3SBenjamin Herrenschmidt */ 526184cd4a3SBenjamin Herrenschmidt #ifdef CONFIG_PCI_MSI 527cad5cef6SGreg Kroah-Hartman static struct pnv_ioda_pe *pnv_ioda_get_pe(struct pci_dev *dev) 528184cd4a3SBenjamin Herrenschmidt { 529184cd4a3SBenjamin Herrenschmidt struct pci_controller *hose = pci_bus_to_host(dev->bus); 530184cd4a3SBenjamin Herrenschmidt struct pnv_phb *phb = hose->private_data; 531b72c1f65SBenjamin Herrenschmidt struct pci_dn *pdn = pci_get_pdn(dev); 532184cd4a3SBenjamin Herrenschmidt 533184cd4a3SBenjamin Herrenschmidt if (!pdn) 534184cd4a3SBenjamin Herrenschmidt return NULL; 535184cd4a3SBenjamin Herrenschmidt if (pdn->pe_number == IODA_INVALID_PE) 536184cd4a3SBenjamin Herrenschmidt return NULL; 537184cd4a3SBenjamin Herrenschmidt return &phb->ioda.pe_array[pdn->pe_number]; 538184cd4a3SBenjamin Herrenschmidt } 539184cd4a3SBenjamin Herrenschmidt #endif /* CONFIG_PCI_MSI */ 540184cd4a3SBenjamin Herrenschmidt 541b131a842SGavin Shan static int pnv_ioda_set_one_peltv(struct pnv_phb *phb, 542b131a842SGavin Shan struct pnv_ioda_pe *parent, 543b131a842SGavin Shan struct pnv_ioda_pe *child, 544b131a842SGavin Shan bool is_add) 545b131a842SGavin Shan { 546b131a842SGavin Shan const char *desc = is_add ? "adding" : "removing"; 547b131a842SGavin Shan uint8_t op = is_add ? OPAL_ADD_PE_TO_DOMAIN : 548b131a842SGavin Shan OPAL_REMOVE_PE_FROM_DOMAIN; 549b131a842SGavin Shan struct pnv_ioda_pe *slave; 550b131a842SGavin Shan long rc; 551b131a842SGavin Shan 552b131a842SGavin Shan /* Parent PE affects child PE */ 553b131a842SGavin Shan rc = opal_pci_set_peltv(phb->opal_id, parent->pe_number, 554b131a842SGavin Shan child->pe_number, op); 555b131a842SGavin Shan if (rc != OPAL_SUCCESS) { 556b131a842SGavin Shan pe_warn(child, "OPAL error %ld %s to parent PELTV\n", 557b131a842SGavin Shan rc, desc); 558b131a842SGavin Shan return -ENXIO; 559b131a842SGavin Shan } 560b131a842SGavin Shan 561b131a842SGavin Shan if (!(child->flags & PNV_IODA_PE_MASTER)) 562b131a842SGavin Shan return 0; 563b131a842SGavin Shan 564b131a842SGavin Shan /* Compound case: parent PE affects slave PEs */ 565b131a842SGavin Shan list_for_each_entry(slave, &child->slaves, list) { 566b131a842SGavin Shan rc = opal_pci_set_peltv(phb->opal_id, parent->pe_number, 567b131a842SGavin Shan slave->pe_number, op); 568b131a842SGavin Shan if (rc != OPAL_SUCCESS) { 569b131a842SGavin Shan pe_warn(slave, "OPAL error %ld %s to parent PELTV\n", 570b131a842SGavin Shan rc, desc); 571b131a842SGavin Shan return -ENXIO; 572b131a842SGavin Shan } 573b131a842SGavin Shan } 574b131a842SGavin Shan 575b131a842SGavin Shan return 0; 576b131a842SGavin Shan } 577b131a842SGavin Shan 578b131a842SGavin Shan static int pnv_ioda_set_peltv(struct pnv_phb *phb, 579b131a842SGavin Shan struct pnv_ioda_pe *pe, 580b131a842SGavin Shan bool is_add) 581b131a842SGavin Shan { 582b131a842SGavin Shan struct pnv_ioda_pe *slave; 583781a868fSWei Yang struct pci_dev *pdev = NULL; 584b131a842SGavin Shan int ret; 585b131a842SGavin Shan 586b131a842SGavin Shan /* 587b131a842SGavin Shan * Clear PE frozen state. If it's master PE, we need 588b131a842SGavin Shan * clear slave PE frozen state as well. 589b131a842SGavin Shan */ 590b131a842SGavin Shan if (is_add) { 591b131a842SGavin Shan opal_pci_eeh_freeze_clear(phb->opal_id, pe->pe_number, 592b131a842SGavin Shan OPAL_EEH_ACTION_CLEAR_FREEZE_ALL); 593b131a842SGavin Shan if (pe->flags & PNV_IODA_PE_MASTER) { 594b131a842SGavin Shan list_for_each_entry(slave, &pe->slaves, list) 595b131a842SGavin Shan opal_pci_eeh_freeze_clear(phb->opal_id, 596b131a842SGavin Shan slave->pe_number, 597b131a842SGavin Shan OPAL_EEH_ACTION_CLEAR_FREEZE_ALL); 598b131a842SGavin Shan } 599b131a842SGavin Shan } 600b131a842SGavin Shan 601b131a842SGavin Shan /* 602b131a842SGavin Shan * Associate PE in PELT. We need add the PE into the 603b131a842SGavin Shan * corresponding PELT-V as well. Otherwise, the error 604b131a842SGavin Shan * originated from the PE might contribute to other 605b131a842SGavin Shan * PEs. 606b131a842SGavin Shan */ 607b131a842SGavin Shan ret = pnv_ioda_set_one_peltv(phb, pe, pe, is_add); 608b131a842SGavin Shan if (ret) 609b131a842SGavin Shan return ret; 610b131a842SGavin Shan 611b131a842SGavin Shan /* For compound PEs, any one affects all of them */ 612b131a842SGavin Shan if (pe->flags & PNV_IODA_PE_MASTER) { 613b131a842SGavin Shan list_for_each_entry(slave, &pe->slaves, list) { 614b131a842SGavin Shan ret = pnv_ioda_set_one_peltv(phb, slave, pe, is_add); 615b131a842SGavin Shan if (ret) 616b131a842SGavin Shan return ret; 617b131a842SGavin Shan } 618b131a842SGavin Shan } 619b131a842SGavin Shan 620b131a842SGavin Shan if (pe->flags & (PNV_IODA_PE_BUS_ALL | PNV_IODA_PE_BUS)) 621b131a842SGavin Shan pdev = pe->pbus->self; 622781a868fSWei Yang else if (pe->flags & PNV_IODA_PE_DEV) 623b131a842SGavin Shan pdev = pe->pdev->bus->self; 624781a868fSWei Yang #ifdef CONFIG_PCI_IOV 625781a868fSWei Yang else if (pe->flags & PNV_IODA_PE_VF) 626283e2d8aSGavin Shan pdev = pe->parent_dev; 627781a868fSWei Yang #endif /* CONFIG_PCI_IOV */ 628b131a842SGavin Shan while (pdev) { 629b131a842SGavin Shan struct pci_dn *pdn = pci_get_pdn(pdev); 630b131a842SGavin Shan struct pnv_ioda_pe *parent; 631b131a842SGavin Shan 632b131a842SGavin Shan if (pdn && pdn->pe_number != IODA_INVALID_PE) { 633b131a842SGavin Shan parent = &phb->ioda.pe_array[pdn->pe_number]; 634b131a842SGavin Shan ret = pnv_ioda_set_one_peltv(phb, parent, pe, is_add); 635b131a842SGavin Shan if (ret) 636b131a842SGavin Shan return ret; 637b131a842SGavin Shan } 638b131a842SGavin Shan 639b131a842SGavin Shan pdev = pdev->bus->self; 640b131a842SGavin Shan } 641b131a842SGavin Shan 642b131a842SGavin Shan return 0; 643b131a842SGavin Shan } 644b131a842SGavin Shan 645781a868fSWei Yang #ifdef CONFIG_PCI_IOV 646781a868fSWei Yang static int pnv_ioda_deconfigure_pe(struct pnv_phb *phb, struct pnv_ioda_pe *pe) 647781a868fSWei Yang { 648781a868fSWei Yang struct pci_dev *parent; 649781a868fSWei Yang uint8_t bcomp, dcomp, fcomp; 650781a868fSWei Yang int64_t rc; 651781a868fSWei Yang long rid_end, rid; 652781a868fSWei Yang 653781a868fSWei Yang /* Currently, we just deconfigure VF PE. Bus PE will always there.*/ 654781a868fSWei Yang if (pe->pbus) { 655781a868fSWei Yang int count; 656781a868fSWei Yang 657781a868fSWei Yang dcomp = OPAL_IGNORE_RID_DEVICE_NUMBER; 658781a868fSWei Yang fcomp = OPAL_IGNORE_RID_FUNCTION_NUMBER; 659781a868fSWei Yang parent = pe->pbus->self; 660781a868fSWei Yang if (pe->flags & PNV_IODA_PE_BUS_ALL) 661781a868fSWei Yang count = pe->pbus->busn_res.end - pe->pbus->busn_res.start + 1; 662781a868fSWei Yang else 663781a868fSWei Yang count = 1; 664781a868fSWei Yang 665781a868fSWei Yang switch(count) { 666781a868fSWei Yang case 1: bcomp = OpalPciBusAll; break; 667781a868fSWei Yang case 2: bcomp = OpalPciBus7Bits; break; 668781a868fSWei Yang case 4: bcomp = OpalPciBus6Bits; break; 669781a868fSWei Yang case 8: bcomp = OpalPciBus5Bits; break; 670781a868fSWei Yang case 16: bcomp = OpalPciBus4Bits; break; 671781a868fSWei Yang case 32: bcomp = OpalPciBus3Bits; break; 672781a868fSWei Yang default: 673781a868fSWei Yang dev_err(&pe->pbus->dev, "Number of subordinate buses %d unsupported\n", 674781a868fSWei Yang count); 675781a868fSWei Yang /* Do an exact match only */ 676781a868fSWei Yang bcomp = OpalPciBusAll; 677781a868fSWei Yang } 678781a868fSWei Yang rid_end = pe->rid + (count << 8); 679781a868fSWei Yang } else { 680781a868fSWei Yang if (pe->flags & PNV_IODA_PE_VF) 681781a868fSWei Yang parent = pe->parent_dev; 682781a868fSWei Yang else 683781a868fSWei Yang parent = pe->pdev->bus->self; 684781a868fSWei Yang bcomp = OpalPciBusAll; 685781a868fSWei Yang dcomp = OPAL_COMPARE_RID_DEVICE_NUMBER; 686781a868fSWei Yang fcomp = OPAL_COMPARE_RID_FUNCTION_NUMBER; 687781a868fSWei Yang rid_end = pe->rid + 1; 688781a868fSWei Yang } 689781a868fSWei Yang 690781a868fSWei Yang /* Clear the reverse map */ 691781a868fSWei Yang for (rid = pe->rid; rid < rid_end; rid++) 692781a868fSWei Yang phb->ioda.pe_rmap[rid] = 0; 693781a868fSWei Yang 694781a868fSWei Yang /* Release from all parents PELT-V */ 695781a868fSWei Yang while (parent) { 696781a868fSWei Yang struct pci_dn *pdn = pci_get_pdn(parent); 697781a868fSWei Yang if (pdn && pdn->pe_number != IODA_INVALID_PE) { 698781a868fSWei Yang rc = opal_pci_set_peltv(phb->opal_id, pdn->pe_number, 699781a868fSWei Yang pe->pe_number, OPAL_REMOVE_PE_FROM_DOMAIN); 700781a868fSWei Yang /* XXX What to do in case of error ? */ 701781a868fSWei Yang } 702781a868fSWei Yang parent = parent->bus->self; 703781a868fSWei Yang } 704781a868fSWei Yang 705f951e510SGavin Shan opal_pci_eeh_freeze_clear(phb->opal_id, pe->pe_number, 706781a868fSWei Yang OPAL_EEH_ACTION_CLEAR_FREEZE_ALL); 707781a868fSWei Yang 708781a868fSWei Yang /* Disassociate PE in PELT */ 709781a868fSWei Yang rc = opal_pci_set_peltv(phb->opal_id, pe->pe_number, 710781a868fSWei Yang pe->pe_number, OPAL_REMOVE_PE_FROM_DOMAIN); 711781a868fSWei Yang if (rc) 712781a868fSWei Yang pe_warn(pe, "OPAL error %ld remove self from PELTV\n", rc); 713781a868fSWei Yang rc = opal_pci_set_pe(phb->opal_id, pe->pe_number, pe->rid, 714781a868fSWei Yang bcomp, dcomp, fcomp, OPAL_UNMAP_PE); 715781a868fSWei Yang if (rc) 716781a868fSWei Yang pe_err(pe, "OPAL error %ld trying to setup PELT table\n", rc); 717781a868fSWei Yang 718781a868fSWei Yang pe->pbus = NULL; 719781a868fSWei Yang pe->pdev = NULL; 720781a868fSWei Yang pe->parent_dev = NULL; 721781a868fSWei Yang 722781a868fSWei Yang return 0; 723781a868fSWei Yang } 724781a868fSWei Yang #endif /* CONFIG_PCI_IOV */ 725781a868fSWei Yang 726cad5cef6SGreg Kroah-Hartman static int pnv_ioda_configure_pe(struct pnv_phb *phb, struct pnv_ioda_pe *pe) 727184cd4a3SBenjamin Herrenschmidt { 728184cd4a3SBenjamin Herrenschmidt struct pci_dev *parent; 729184cd4a3SBenjamin Herrenschmidt uint8_t bcomp, dcomp, fcomp; 730184cd4a3SBenjamin Herrenschmidt long rc, rid_end, rid; 731184cd4a3SBenjamin Herrenschmidt 732184cd4a3SBenjamin Herrenschmidt /* Bus validation ? */ 733184cd4a3SBenjamin Herrenschmidt if (pe->pbus) { 734184cd4a3SBenjamin Herrenschmidt int count; 735184cd4a3SBenjamin Herrenschmidt 736184cd4a3SBenjamin Herrenschmidt dcomp = OPAL_IGNORE_RID_DEVICE_NUMBER; 737184cd4a3SBenjamin Herrenschmidt fcomp = OPAL_IGNORE_RID_FUNCTION_NUMBER; 738184cd4a3SBenjamin Herrenschmidt parent = pe->pbus->self; 739fb446ad0SGavin Shan if (pe->flags & PNV_IODA_PE_BUS_ALL) 740b918c62eSYinghai Lu count = pe->pbus->busn_res.end - pe->pbus->busn_res.start + 1; 741fb446ad0SGavin Shan else 742fb446ad0SGavin Shan count = 1; 743fb446ad0SGavin Shan 744184cd4a3SBenjamin Herrenschmidt switch(count) { 745184cd4a3SBenjamin Herrenschmidt case 1: bcomp = OpalPciBusAll; break; 746184cd4a3SBenjamin Herrenschmidt case 2: bcomp = OpalPciBus7Bits; break; 747184cd4a3SBenjamin Herrenschmidt case 4: bcomp = OpalPciBus6Bits; break; 748184cd4a3SBenjamin Herrenschmidt case 8: bcomp = OpalPciBus5Bits; break; 749184cd4a3SBenjamin Herrenschmidt case 16: bcomp = OpalPciBus4Bits; break; 750184cd4a3SBenjamin Herrenschmidt case 32: bcomp = OpalPciBus3Bits; break; 751184cd4a3SBenjamin Herrenschmidt default: 752781a868fSWei Yang dev_err(&pe->pbus->dev, "Number of subordinate buses %d unsupported\n", 753781a868fSWei Yang count); 754184cd4a3SBenjamin Herrenschmidt /* Do an exact match only */ 755184cd4a3SBenjamin Herrenschmidt bcomp = OpalPciBusAll; 756184cd4a3SBenjamin Herrenschmidt } 757184cd4a3SBenjamin Herrenschmidt rid_end = pe->rid + (count << 8); 758184cd4a3SBenjamin Herrenschmidt } else { 759781a868fSWei Yang #ifdef CONFIG_PCI_IOV 760781a868fSWei Yang if (pe->flags & PNV_IODA_PE_VF) 761781a868fSWei Yang parent = pe->parent_dev; 762781a868fSWei Yang else 763781a868fSWei Yang #endif /* CONFIG_PCI_IOV */ 764184cd4a3SBenjamin Herrenschmidt parent = pe->pdev->bus->self; 765184cd4a3SBenjamin Herrenschmidt bcomp = OpalPciBusAll; 766184cd4a3SBenjamin Herrenschmidt dcomp = OPAL_COMPARE_RID_DEVICE_NUMBER; 767184cd4a3SBenjamin Herrenschmidt fcomp = OPAL_COMPARE_RID_FUNCTION_NUMBER; 768184cd4a3SBenjamin Herrenschmidt rid_end = pe->rid + 1; 769184cd4a3SBenjamin Herrenschmidt } 770184cd4a3SBenjamin Herrenschmidt 771631ad691SGavin Shan /* 772631ad691SGavin Shan * Associate PE in PELT. We need add the PE into the 773631ad691SGavin Shan * corresponding PELT-V as well. Otherwise, the error 774631ad691SGavin Shan * originated from the PE might contribute to other 775631ad691SGavin Shan * PEs. 776631ad691SGavin Shan */ 777184cd4a3SBenjamin Herrenschmidt rc = opal_pci_set_pe(phb->opal_id, pe->pe_number, pe->rid, 778184cd4a3SBenjamin Herrenschmidt bcomp, dcomp, fcomp, OPAL_MAP_PE); 779184cd4a3SBenjamin Herrenschmidt if (rc) { 780184cd4a3SBenjamin Herrenschmidt pe_err(pe, "OPAL error %ld trying to setup PELT table\n", rc); 781184cd4a3SBenjamin Herrenschmidt return -ENXIO; 782184cd4a3SBenjamin Herrenschmidt } 783631ad691SGavin Shan 784b131a842SGavin Shan /* Configure PELTV */ 785b131a842SGavin Shan pnv_ioda_set_peltv(phb, pe, true); 786184cd4a3SBenjamin Herrenschmidt 787184cd4a3SBenjamin Herrenschmidt /* Setup reverse map */ 788184cd4a3SBenjamin Herrenschmidt for (rid = pe->rid; rid < rid_end; rid++) 789184cd4a3SBenjamin Herrenschmidt phb->ioda.pe_rmap[rid] = pe->pe_number; 790184cd4a3SBenjamin Herrenschmidt 791184cd4a3SBenjamin Herrenschmidt /* Setup one MVTs on IODA1 */ 7924773f76bSGavin Shan if (phb->type != PNV_PHB_IODA1) { 7934773f76bSGavin Shan pe->mve_number = 0; 7944773f76bSGavin Shan goto out; 7954773f76bSGavin Shan } 7964773f76bSGavin Shan 797184cd4a3SBenjamin Herrenschmidt pe->mve_number = pe->pe_number; 7984773f76bSGavin Shan rc = opal_pci_set_mve(phb->opal_id, pe->mve_number, pe->pe_number); 7994773f76bSGavin Shan if (rc != OPAL_SUCCESS) { 800184cd4a3SBenjamin Herrenschmidt pe_err(pe, "OPAL error %ld setting up MVE %d\n", 801184cd4a3SBenjamin Herrenschmidt rc, pe->mve_number); 802184cd4a3SBenjamin Herrenschmidt pe->mve_number = -1; 803184cd4a3SBenjamin Herrenschmidt } else { 804184cd4a3SBenjamin Herrenschmidt rc = opal_pci_set_mve_enable(phb->opal_id, 805cee72d5bSBenjamin Herrenschmidt pe->mve_number, OPAL_ENABLE_MVE); 806184cd4a3SBenjamin Herrenschmidt if (rc) { 807184cd4a3SBenjamin Herrenschmidt pe_err(pe, "OPAL error %ld enabling MVE %d\n", 808184cd4a3SBenjamin Herrenschmidt rc, pe->mve_number); 809184cd4a3SBenjamin Herrenschmidt pe->mve_number = -1; 810184cd4a3SBenjamin Herrenschmidt } 811184cd4a3SBenjamin Herrenschmidt } 812184cd4a3SBenjamin Herrenschmidt 8134773f76bSGavin Shan out: 814184cd4a3SBenjamin Herrenschmidt return 0; 815184cd4a3SBenjamin Herrenschmidt } 816184cd4a3SBenjamin Herrenschmidt 817cad5cef6SGreg Kroah-Hartman static void pnv_ioda_link_pe_by_weight(struct pnv_phb *phb, 818184cd4a3SBenjamin Herrenschmidt struct pnv_ioda_pe *pe) 819184cd4a3SBenjamin Herrenschmidt { 820184cd4a3SBenjamin Herrenschmidt struct pnv_ioda_pe *lpe; 821184cd4a3SBenjamin Herrenschmidt 8227ebdf956SGavin Shan list_for_each_entry(lpe, &phb->ioda.pe_dma_list, dma_link) { 823184cd4a3SBenjamin Herrenschmidt if (lpe->dma_weight < pe->dma_weight) { 8247ebdf956SGavin Shan list_add_tail(&pe->dma_link, &lpe->dma_link); 825184cd4a3SBenjamin Herrenschmidt return; 826184cd4a3SBenjamin Herrenschmidt } 827184cd4a3SBenjamin Herrenschmidt } 8287ebdf956SGavin Shan list_add_tail(&pe->dma_link, &phb->ioda.pe_dma_list); 829184cd4a3SBenjamin Herrenschmidt } 830184cd4a3SBenjamin Herrenschmidt 831184cd4a3SBenjamin Herrenschmidt static unsigned int pnv_ioda_dma_weight(struct pci_dev *dev) 832184cd4a3SBenjamin Herrenschmidt { 833184cd4a3SBenjamin Herrenschmidt /* This is quite simplistic. The "base" weight of a device 834184cd4a3SBenjamin Herrenschmidt * is 10. 0 means no DMA is to be accounted for it. 835184cd4a3SBenjamin Herrenschmidt */ 836184cd4a3SBenjamin Herrenschmidt 837184cd4a3SBenjamin Herrenschmidt /* If it's a bridge, no DMA */ 838184cd4a3SBenjamin Herrenschmidt if (dev->hdr_type != PCI_HEADER_TYPE_NORMAL) 839184cd4a3SBenjamin Herrenschmidt return 0; 840184cd4a3SBenjamin Herrenschmidt 841184cd4a3SBenjamin Herrenschmidt /* Reduce the weight of slow USB controllers */ 842184cd4a3SBenjamin Herrenschmidt if (dev->class == PCI_CLASS_SERIAL_USB_UHCI || 843184cd4a3SBenjamin Herrenschmidt dev->class == PCI_CLASS_SERIAL_USB_OHCI || 844184cd4a3SBenjamin Herrenschmidt dev->class == PCI_CLASS_SERIAL_USB_EHCI) 845184cd4a3SBenjamin Herrenschmidt return 3; 846184cd4a3SBenjamin Herrenschmidt 847184cd4a3SBenjamin Herrenschmidt /* Increase the weight of RAID (includes Obsidian) */ 848184cd4a3SBenjamin Herrenschmidt if ((dev->class >> 8) == PCI_CLASS_STORAGE_RAID) 849184cd4a3SBenjamin Herrenschmidt return 15; 850184cd4a3SBenjamin Herrenschmidt 851184cd4a3SBenjamin Herrenschmidt /* Default */ 852184cd4a3SBenjamin Herrenschmidt return 10; 853184cd4a3SBenjamin Herrenschmidt } 854184cd4a3SBenjamin Herrenschmidt 855781a868fSWei Yang #ifdef CONFIG_PCI_IOV 856781a868fSWei Yang static int pnv_pci_vf_resource_shift(struct pci_dev *dev, int offset) 857781a868fSWei Yang { 858781a868fSWei Yang struct pci_dn *pdn = pci_get_pdn(dev); 859781a868fSWei Yang int i; 860781a868fSWei Yang struct resource *res, res2; 861781a868fSWei Yang resource_size_t size; 862781a868fSWei Yang u16 num_vfs; 863781a868fSWei Yang 864781a868fSWei Yang if (!dev->is_physfn) 865781a868fSWei Yang return -EINVAL; 866781a868fSWei Yang 867781a868fSWei Yang /* 868781a868fSWei Yang * "offset" is in VFs. The M64 windows are sized so that when they 869781a868fSWei Yang * are segmented, each segment is the same size as the IOV BAR. 870781a868fSWei Yang * Each segment is in a separate PE, and the high order bits of the 871781a868fSWei Yang * address are the PE number. Therefore, each VF's BAR is in a 872781a868fSWei Yang * separate PE, and changing the IOV BAR start address changes the 873781a868fSWei Yang * range of PEs the VFs are in. 874781a868fSWei Yang */ 875781a868fSWei Yang num_vfs = pdn->num_vfs; 876781a868fSWei Yang for (i = 0; i < PCI_SRIOV_NUM_BARS; i++) { 877781a868fSWei Yang res = &dev->resource[i + PCI_IOV_RESOURCES]; 878781a868fSWei Yang if (!res->flags || !res->parent) 879781a868fSWei Yang continue; 880781a868fSWei Yang 881781a868fSWei Yang if (!pnv_pci_is_mem_pref_64(res->flags)) 882781a868fSWei Yang continue; 883781a868fSWei Yang 884781a868fSWei Yang /* 885781a868fSWei Yang * The actual IOV BAR range is determined by the start address 886781a868fSWei Yang * and the actual size for num_vfs VFs BAR. This check is to 887781a868fSWei Yang * make sure that after shifting, the range will not overlap 888781a868fSWei Yang * with another device. 889781a868fSWei Yang */ 890781a868fSWei Yang size = pci_iov_resource_size(dev, i + PCI_IOV_RESOURCES); 891781a868fSWei Yang res2.flags = res->flags; 892781a868fSWei Yang res2.start = res->start + (size * offset); 893781a868fSWei Yang res2.end = res2.start + (size * num_vfs) - 1; 894781a868fSWei Yang 895781a868fSWei Yang if (res2.end > res->end) { 896781a868fSWei Yang dev_err(&dev->dev, "VF BAR%d: %pR would extend past %pR (trying to enable %d VFs shifted by %d)\n", 897781a868fSWei Yang i, &res2, res, num_vfs, offset); 898781a868fSWei Yang return -EBUSY; 899781a868fSWei Yang } 900781a868fSWei Yang } 901781a868fSWei Yang 902781a868fSWei Yang /* 903781a868fSWei Yang * After doing so, there would be a "hole" in the /proc/iomem when 904781a868fSWei Yang * offset is a positive value. It looks like the device return some 905781a868fSWei Yang * mmio back to the system, which actually no one could use it. 906781a868fSWei Yang */ 907781a868fSWei Yang for (i = 0; i < PCI_SRIOV_NUM_BARS; i++) { 908781a868fSWei Yang res = &dev->resource[i + PCI_IOV_RESOURCES]; 909781a868fSWei Yang if (!res->flags || !res->parent) 910781a868fSWei Yang continue; 911781a868fSWei Yang 912781a868fSWei Yang if (!pnv_pci_is_mem_pref_64(res->flags)) 913781a868fSWei Yang continue; 914781a868fSWei Yang 915781a868fSWei Yang size = pci_iov_resource_size(dev, i + PCI_IOV_RESOURCES); 916781a868fSWei Yang res2 = *res; 917781a868fSWei Yang res->start += size * offset; 918781a868fSWei Yang 91974703cc4SWei Yang dev_info(&dev->dev, "VF BAR%d: %pR shifted to %pR (%sabling %d VFs shifted by %d)\n", 92074703cc4SWei Yang i, &res2, res, (offset > 0) ? "En" : "Dis", 92174703cc4SWei Yang num_vfs, offset); 922781a868fSWei Yang pci_update_resource(dev, i + PCI_IOV_RESOURCES); 923781a868fSWei Yang } 924781a868fSWei Yang return 0; 925781a868fSWei Yang } 926781a868fSWei Yang #endif /* CONFIG_PCI_IOV */ 927781a868fSWei Yang 928fb446ad0SGavin Shan #if 0 929cad5cef6SGreg Kroah-Hartman static struct pnv_ioda_pe *pnv_ioda_setup_dev_PE(struct pci_dev *dev) 930184cd4a3SBenjamin Herrenschmidt { 931184cd4a3SBenjamin Herrenschmidt struct pci_controller *hose = pci_bus_to_host(dev->bus); 932184cd4a3SBenjamin Herrenschmidt struct pnv_phb *phb = hose->private_data; 933b72c1f65SBenjamin Herrenschmidt struct pci_dn *pdn = pci_get_pdn(dev); 934184cd4a3SBenjamin Herrenschmidt struct pnv_ioda_pe *pe; 935184cd4a3SBenjamin Herrenschmidt int pe_num; 936184cd4a3SBenjamin Herrenschmidt 937184cd4a3SBenjamin Herrenschmidt if (!pdn) { 938184cd4a3SBenjamin Herrenschmidt pr_err("%s: Device tree node not associated properly\n", 939184cd4a3SBenjamin Herrenschmidt pci_name(dev)); 940184cd4a3SBenjamin Herrenschmidt return NULL; 941184cd4a3SBenjamin Herrenschmidt } 942184cd4a3SBenjamin Herrenschmidt if (pdn->pe_number != IODA_INVALID_PE) 943184cd4a3SBenjamin Herrenschmidt return NULL; 944184cd4a3SBenjamin Herrenschmidt 945184cd4a3SBenjamin Herrenschmidt /* PE#0 has been pre-set */ 946184cd4a3SBenjamin Herrenschmidt if (dev->bus->number == 0) 947184cd4a3SBenjamin Herrenschmidt pe_num = 0; 948184cd4a3SBenjamin Herrenschmidt else 949184cd4a3SBenjamin Herrenschmidt pe_num = pnv_ioda_alloc_pe(phb); 950184cd4a3SBenjamin Herrenschmidt if (pe_num == IODA_INVALID_PE) { 951184cd4a3SBenjamin Herrenschmidt pr_warning("%s: Not enough PE# available, disabling device\n", 952184cd4a3SBenjamin Herrenschmidt pci_name(dev)); 953184cd4a3SBenjamin Herrenschmidt return NULL; 954184cd4a3SBenjamin Herrenschmidt } 955184cd4a3SBenjamin Herrenschmidt 956184cd4a3SBenjamin Herrenschmidt /* NOTE: We get only one ref to the pci_dev for the pdn, not for the 957184cd4a3SBenjamin Herrenschmidt * pointer in the PE data structure, both should be destroyed at the 958184cd4a3SBenjamin Herrenschmidt * same time. However, this needs to be looked at more closely again 959184cd4a3SBenjamin Herrenschmidt * once we actually start removing things (Hotplug, SR-IOV, ...) 960184cd4a3SBenjamin Herrenschmidt * 961184cd4a3SBenjamin Herrenschmidt * At some point we want to remove the PDN completely anyways 962184cd4a3SBenjamin Herrenschmidt */ 963184cd4a3SBenjamin Herrenschmidt pe = &phb->ioda.pe_array[pe_num]; 964184cd4a3SBenjamin Herrenschmidt pci_dev_get(dev); 965184cd4a3SBenjamin Herrenschmidt pdn->pcidev = dev; 966184cd4a3SBenjamin Herrenschmidt pdn->pe_number = pe_num; 967184cd4a3SBenjamin Herrenschmidt pe->pdev = dev; 968184cd4a3SBenjamin Herrenschmidt pe->pbus = NULL; 969184cd4a3SBenjamin Herrenschmidt pe->tce32_seg = -1; 970184cd4a3SBenjamin Herrenschmidt pe->mve_number = -1; 971184cd4a3SBenjamin Herrenschmidt pe->rid = dev->bus->number << 8 | pdn->devfn; 972184cd4a3SBenjamin Herrenschmidt 973184cd4a3SBenjamin Herrenschmidt pe_info(pe, "Associated device to PE\n"); 974184cd4a3SBenjamin Herrenschmidt 975184cd4a3SBenjamin Herrenschmidt if (pnv_ioda_configure_pe(phb, pe)) { 976184cd4a3SBenjamin Herrenschmidt /* XXX What do we do here ? */ 977184cd4a3SBenjamin Herrenschmidt if (pe_num) 978184cd4a3SBenjamin Herrenschmidt pnv_ioda_free_pe(phb, pe_num); 979184cd4a3SBenjamin Herrenschmidt pdn->pe_number = IODA_INVALID_PE; 980184cd4a3SBenjamin Herrenschmidt pe->pdev = NULL; 981184cd4a3SBenjamin Herrenschmidt pci_dev_put(dev); 982184cd4a3SBenjamin Herrenschmidt return NULL; 983184cd4a3SBenjamin Herrenschmidt } 984184cd4a3SBenjamin Herrenschmidt 985184cd4a3SBenjamin Herrenschmidt /* Assign a DMA weight to the device */ 986184cd4a3SBenjamin Herrenschmidt pe->dma_weight = pnv_ioda_dma_weight(dev); 987184cd4a3SBenjamin Herrenschmidt if (pe->dma_weight != 0) { 988184cd4a3SBenjamin Herrenschmidt phb->ioda.dma_weight += pe->dma_weight; 989184cd4a3SBenjamin Herrenschmidt phb->ioda.dma_pe_count++; 990184cd4a3SBenjamin Herrenschmidt } 991184cd4a3SBenjamin Herrenschmidt 992184cd4a3SBenjamin Herrenschmidt /* Link the PE */ 993184cd4a3SBenjamin Herrenschmidt pnv_ioda_link_pe_by_weight(phb, pe); 994184cd4a3SBenjamin Herrenschmidt 995184cd4a3SBenjamin Herrenschmidt return pe; 996184cd4a3SBenjamin Herrenschmidt } 997fb446ad0SGavin Shan #endif /* Useful for SRIOV case */ 998184cd4a3SBenjamin Herrenschmidt 999184cd4a3SBenjamin Herrenschmidt static void pnv_ioda_setup_same_PE(struct pci_bus *bus, struct pnv_ioda_pe *pe) 1000184cd4a3SBenjamin Herrenschmidt { 1001184cd4a3SBenjamin Herrenschmidt struct pci_dev *dev; 1002184cd4a3SBenjamin Herrenschmidt 1003184cd4a3SBenjamin Herrenschmidt list_for_each_entry(dev, &bus->devices, bus_list) { 1004b72c1f65SBenjamin Herrenschmidt struct pci_dn *pdn = pci_get_pdn(dev); 1005184cd4a3SBenjamin Herrenschmidt 1006184cd4a3SBenjamin Herrenschmidt if (pdn == NULL) { 1007184cd4a3SBenjamin Herrenschmidt pr_warn("%s: No device node associated with device !\n", 1008184cd4a3SBenjamin Herrenschmidt pci_name(dev)); 1009184cd4a3SBenjamin Herrenschmidt continue; 1010184cd4a3SBenjamin Herrenschmidt } 1011184cd4a3SBenjamin Herrenschmidt pdn->pe_number = pe->pe_number; 1012184cd4a3SBenjamin Herrenschmidt pe->dma_weight += pnv_ioda_dma_weight(dev); 1013fb446ad0SGavin Shan if ((pe->flags & PNV_IODA_PE_BUS_ALL) && dev->subordinate) 1014184cd4a3SBenjamin Herrenschmidt pnv_ioda_setup_same_PE(dev->subordinate, pe); 1015184cd4a3SBenjamin Herrenschmidt } 1016184cd4a3SBenjamin Herrenschmidt } 1017184cd4a3SBenjamin Herrenschmidt 1018fb446ad0SGavin Shan /* 1019fb446ad0SGavin Shan * There're 2 types of PCI bus sensitive PEs: One that is compromised of 1020fb446ad0SGavin Shan * single PCI bus. Another one that contains the primary PCI bus and its 1021fb446ad0SGavin Shan * subordinate PCI devices and buses. The second type of PE is normally 1022fb446ad0SGavin Shan * orgiriated by PCIe-to-PCI bridge or PLX switch downstream ports. 1023fb446ad0SGavin Shan */ 1024d1203852SGavin Shan static void pnv_ioda_setup_bus_PE(struct pci_bus *bus, bool all) 1025184cd4a3SBenjamin Herrenschmidt { 1026fb446ad0SGavin Shan struct pci_controller *hose = pci_bus_to_host(bus); 1027184cd4a3SBenjamin Herrenschmidt struct pnv_phb *phb = hose->private_data; 1028184cd4a3SBenjamin Herrenschmidt struct pnv_ioda_pe *pe; 1029262af557SGuo Chao int pe_num = IODA_INVALID_PE; 1030184cd4a3SBenjamin Herrenschmidt 1031262af557SGuo Chao /* Check if PE is determined by M64 */ 1032262af557SGuo Chao if (phb->pick_m64_pe) 103326ba248dSGavin Shan pe_num = phb->pick_m64_pe(bus, all); 1034262af557SGuo Chao 1035262af557SGuo Chao /* The PE number isn't pinned by M64 */ 1036262af557SGuo Chao if (pe_num == IODA_INVALID_PE) 1037184cd4a3SBenjamin Herrenschmidt pe_num = pnv_ioda_alloc_pe(phb); 1038262af557SGuo Chao 1039184cd4a3SBenjamin Herrenschmidt if (pe_num == IODA_INVALID_PE) { 1040fb446ad0SGavin Shan pr_warning("%s: Not enough PE# available for PCI bus %04x:%02x\n", 1041fb446ad0SGavin Shan __func__, pci_domain_nr(bus), bus->number); 1042184cd4a3SBenjamin Herrenschmidt return; 1043184cd4a3SBenjamin Herrenschmidt } 1044184cd4a3SBenjamin Herrenschmidt 1045184cd4a3SBenjamin Herrenschmidt pe = &phb->ioda.pe_array[pe_num]; 1046262af557SGuo Chao pe->flags |= (all ? PNV_IODA_PE_BUS_ALL : PNV_IODA_PE_BUS); 1047184cd4a3SBenjamin Herrenschmidt pe->pbus = bus; 1048184cd4a3SBenjamin Herrenschmidt pe->pdev = NULL; 1049184cd4a3SBenjamin Herrenschmidt pe->tce32_seg = -1; 1050184cd4a3SBenjamin Herrenschmidt pe->mve_number = -1; 1051b918c62eSYinghai Lu pe->rid = bus->busn_res.start << 8; 1052184cd4a3SBenjamin Herrenschmidt pe->dma_weight = 0; 1053184cd4a3SBenjamin Herrenschmidt 1054fb446ad0SGavin Shan if (all) 1055fb446ad0SGavin Shan pe_info(pe, "Secondary bus %d..%d associated with PE#%d\n", 1056fb446ad0SGavin Shan bus->busn_res.start, bus->busn_res.end, pe_num); 1057fb446ad0SGavin Shan else 1058fb446ad0SGavin Shan pe_info(pe, "Secondary bus %d associated with PE#%d\n", 1059fb446ad0SGavin Shan bus->busn_res.start, pe_num); 1060184cd4a3SBenjamin Herrenschmidt 1061184cd4a3SBenjamin Herrenschmidt if (pnv_ioda_configure_pe(phb, pe)) { 1062184cd4a3SBenjamin Herrenschmidt /* XXX What do we do here ? */ 1063184cd4a3SBenjamin Herrenschmidt if (pe_num) 1064184cd4a3SBenjamin Herrenschmidt pnv_ioda_free_pe(phb, pe_num); 1065184cd4a3SBenjamin Herrenschmidt pe->pbus = NULL; 1066184cd4a3SBenjamin Herrenschmidt return; 1067184cd4a3SBenjamin Herrenschmidt } 1068184cd4a3SBenjamin Herrenschmidt 1069184cd4a3SBenjamin Herrenschmidt /* Associate it with all child devices */ 1070184cd4a3SBenjamin Herrenschmidt pnv_ioda_setup_same_PE(bus, pe); 1071184cd4a3SBenjamin Herrenschmidt 10727ebdf956SGavin Shan /* Put PE to the list */ 10737ebdf956SGavin Shan list_add_tail(&pe->list, &phb->ioda.pe_list); 10747ebdf956SGavin Shan 1075184cd4a3SBenjamin Herrenschmidt /* Account for one DMA PE if at least one DMA capable device exist 1076184cd4a3SBenjamin Herrenschmidt * below the bridge 1077184cd4a3SBenjamin Herrenschmidt */ 1078184cd4a3SBenjamin Herrenschmidt if (pe->dma_weight != 0) { 1079184cd4a3SBenjamin Herrenschmidt phb->ioda.dma_weight += pe->dma_weight; 1080184cd4a3SBenjamin Herrenschmidt phb->ioda.dma_pe_count++; 1081184cd4a3SBenjamin Herrenschmidt } 1082184cd4a3SBenjamin Herrenschmidt 1083184cd4a3SBenjamin Herrenschmidt /* Link the PE */ 1084184cd4a3SBenjamin Herrenschmidt pnv_ioda_link_pe_by_weight(phb, pe); 1085184cd4a3SBenjamin Herrenschmidt } 1086184cd4a3SBenjamin Herrenschmidt 1087cad5cef6SGreg Kroah-Hartman static void pnv_ioda_setup_PEs(struct pci_bus *bus) 1088184cd4a3SBenjamin Herrenschmidt { 1089184cd4a3SBenjamin Herrenschmidt struct pci_dev *dev; 1090fb446ad0SGavin Shan 1091d1203852SGavin Shan pnv_ioda_setup_bus_PE(bus, false); 1092184cd4a3SBenjamin Herrenschmidt 1093184cd4a3SBenjamin Herrenschmidt list_for_each_entry(dev, &bus->devices, bus_list) { 1094fb446ad0SGavin Shan if (dev->subordinate) { 109562f87c0eSYijing Wang if (pci_pcie_type(dev) == PCI_EXP_TYPE_PCI_BRIDGE) 1096d1203852SGavin Shan pnv_ioda_setup_bus_PE(dev->subordinate, true); 1097fb446ad0SGavin Shan else 1098184cd4a3SBenjamin Herrenschmidt pnv_ioda_setup_PEs(dev->subordinate); 1099184cd4a3SBenjamin Herrenschmidt } 1100184cd4a3SBenjamin Herrenschmidt } 1101fb446ad0SGavin Shan } 1102fb446ad0SGavin Shan 1103fb446ad0SGavin Shan /* 1104fb446ad0SGavin Shan * Configure PEs so that the downstream PCI buses and devices 1105fb446ad0SGavin Shan * could have their associated PE#. Unfortunately, we didn't 1106fb446ad0SGavin Shan * figure out the way to identify the PLX bridge yet. So we 1107fb446ad0SGavin Shan * simply put the PCI bus and the subordinate behind the root 1108fb446ad0SGavin Shan * port to PE# here. The game rule here is expected to be changed 1109fb446ad0SGavin Shan * as soon as we can detected PLX bridge correctly. 1110fb446ad0SGavin Shan */ 1111cad5cef6SGreg Kroah-Hartman static void pnv_pci_ioda_setup_PEs(void) 1112fb446ad0SGavin Shan { 1113fb446ad0SGavin Shan struct pci_controller *hose, *tmp; 1114262af557SGuo Chao struct pnv_phb *phb; 1115fb446ad0SGavin Shan 1116fb446ad0SGavin Shan list_for_each_entry_safe(hose, tmp, &hose_list, list_node) { 1117262af557SGuo Chao phb = hose->private_data; 1118262af557SGuo Chao 1119262af557SGuo Chao /* M64 layout might affect PE allocation */ 11205ef73567SGavin Shan if (phb->reserve_m64_pe) 112196a2f92bSGavin Shan phb->reserve_m64_pe(hose->bus, NULL, true); 1122262af557SGuo Chao 1123fb446ad0SGavin Shan pnv_ioda_setup_PEs(hose->bus); 1124fb446ad0SGavin Shan } 1125fb446ad0SGavin Shan } 1126184cd4a3SBenjamin Herrenschmidt 1127a8b2f828SGavin Shan #ifdef CONFIG_PCI_IOV 1128781a868fSWei Yang static int pnv_pci_vf_release_m64(struct pci_dev *pdev) 1129781a868fSWei Yang { 1130781a868fSWei Yang struct pci_bus *bus; 1131781a868fSWei Yang struct pci_controller *hose; 1132781a868fSWei Yang struct pnv_phb *phb; 1133781a868fSWei Yang struct pci_dn *pdn; 113402639b0eSWei Yang int i, j; 1135781a868fSWei Yang 1136781a868fSWei Yang bus = pdev->bus; 1137781a868fSWei Yang hose = pci_bus_to_host(bus); 1138781a868fSWei Yang phb = hose->private_data; 1139781a868fSWei Yang pdn = pci_get_pdn(pdev); 1140781a868fSWei Yang 114102639b0eSWei Yang for (i = 0; i < PCI_SRIOV_NUM_BARS; i++) 114202639b0eSWei Yang for (j = 0; j < M64_PER_IOV; j++) { 114302639b0eSWei Yang if (pdn->m64_wins[i][j] == IODA_INVALID_M64) 1144781a868fSWei Yang continue; 1145781a868fSWei Yang opal_pci_phb_mmio_enable(phb->opal_id, 114602639b0eSWei Yang OPAL_M64_WINDOW_TYPE, pdn->m64_wins[i][j], 0); 114702639b0eSWei Yang clear_bit(pdn->m64_wins[i][j], &phb->ioda.m64_bar_alloc); 114802639b0eSWei Yang pdn->m64_wins[i][j] = IODA_INVALID_M64; 1149781a868fSWei Yang } 1150781a868fSWei Yang 1151781a868fSWei Yang return 0; 1152781a868fSWei Yang } 1153781a868fSWei Yang 115402639b0eSWei Yang static int pnv_pci_vf_assign_m64(struct pci_dev *pdev, u16 num_vfs) 1155781a868fSWei Yang { 1156781a868fSWei Yang struct pci_bus *bus; 1157781a868fSWei Yang struct pci_controller *hose; 1158781a868fSWei Yang struct pnv_phb *phb; 1159781a868fSWei Yang struct pci_dn *pdn; 1160781a868fSWei Yang unsigned int win; 1161781a868fSWei Yang struct resource *res; 116202639b0eSWei Yang int i, j; 1163781a868fSWei Yang int64_t rc; 116402639b0eSWei Yang int total_vfs; 116502639b0eSWei Yang resource_size_t size, start; 116602639b0eSWei Yang int pe_num; 116702639b0eSWei Yang int vf_groups; 116802639b0eSWei Yang int vf_per_group; 1169781a868fSWei Yang 1170781a868fSWei Yang bus = pdev->bus; 1171781a868fSWei Yang hose = pci_bus_to_host(bus); 1172781a868fSWei Yang phb = hose->private_data; 1173781a868fSWei Yang pdn = pci_get_pdn(pdev); 117402639b0eSWei Yang total_vfs = pci_sriov_get_totalvfs(pdev); 1175781a868fSWei Yang 1176781a868fSWei Yang /* Initialize the m64_wins to IODA_INVALID_M64 */ 1177781a868fSWei Yang for (i = 0; i < PCI_SRIOV_NUM_BARS; i++) 117802639b0eSWei Yang for (j = 0; j < M64_PER_IOV; j++) 117902639b0eSWei Yang pdn->m64_wins[i][j] = IODA_INVALID_M64; 118002639b0eSWei Yang 118102639b0eSWei Yang if (pdn->m64_per_iov == M64_PER_IOV) { 118202639b0eSWei Yang vf_groups = (num_vfs <= M64_PER_IOV) ? num_vfs: M64_PER_IOV; 118302639b0eSWei Yang vf_per_group = (num_vfs <= M64_PER_IOV)? 1: 118402639b0eSWei Yang roundup_pow_of_two(num_vfs) / pdn->m64_per_iov; 118502639b0eSWei Yang } else { 118602639b0eSWei Yang vf_groups = 1; 118702639b0eSWei Yang vf_per_group = 1; 118802639b0eSWei Yang } 1189781a868fSWei Yang 1190781a868fSWei Yang for (i = 0; i < PCI_SRIOV_NUM_BARS; i++) { 1191781a868fSWei Yang res = &pdev->resource[i + PCI_IOV_RESOURCES]; 1192781a868fSWei Yang if (!res->flags || !res->parent) 1193781a868fSWei Yang continue; 1194781a868fSWei Yang 1195781a868fSWei Yang if (!pnv_pci_is_mem_pref_64(res->flags)) 1196781a868fSWei Yang continue; 1197781a868fSWei Yang 119802639b0eSWei Yang for (j = 0; j < vf_groups; j++) { 1199781a868fSWei Yang do { 1200781a868fSWei Yang win = find_next_zero_bit(&phb->ioda.m64_bar_alloc, 1201781a868fSWei Yang phb->ioda.m64_bar_idx + 1, 0); 1202781a868fSWei Yang 1203781a868fSWei Yang if (win >= phb->ioda.m64_bar_idx + 1) 1204781a868fSWei Yang goto m64_failed; 1205781a868fSWei Yang } while (test_and_set_bit(win, &phb->ioda.m64_bar_alloc)); 1206781a868fSWei Yang 120702639b0eSWei Yang pdn->m64_wins[i][j] = win; 120802639b0eSWei Yang 120902639b0eSWei Yang if (pdn->m64_per_iov == M64_PER_IOV) { 121002639b0eSWei Yang size = pci_iov_resource_size(pdev, 121102639b0eSWei Yang PCI_IOV_RESOURCES + i); 121202639b0eSWei Yang size = size * vf_per_group; 121302639b0eSWei Yang start = res->start + size * j; 121402639b0eSWei Yang } else { 121502639b0eSWei Yang size = resource_size(res); 121602639b0eSWei Yang start = res->start; 121702639b0eSWei Yang } 1218781a868fSWei Yang 1219781a868fSWei Yang /* Map the M64 here */ 122002639b0eSWei Yang if (pdn->m64_per_iov == M64_PER_IOV) { 122102639b0eSWei Yang pe_num = pdn->offset + j; 122202639b0eSWei Yang rc = opal_pci_map_pe_mmio_window(phb->opal_id, 122302639b0eSWei Yang pe_num, OPAL_M64_WINDOW_TYPE, 122402639b0eSWei Yang pdn->m64_wins[i][j], 0); 122502639b0eSWei Yang } 122602639b0eSWei Yang 1227781a868fSWei Yang rc = opal_pci_set_phb_mem_window(phb->opal_id, 1228781a868fSWei Yang OPAL_M64_WINDOW_TYPE, 122902639b0eSWei Yang pdn->m64_wins[i][j], 123002639b0eSWei Yang start, 1231781a868fSWei Yang 0, /* unused */ 123202639b0eSWei Yang size); 123302639b0eSWei Yang 123402639b0eSWei Yang 1235781a868fSWei Yang if (rc != OPAL_SUCCESS) { 1236781a868fSWei Yang dev_err(&pdev->dev, "Failed to map M64 window #%d: %lld\n", 1237781a868fSWei Yang win, rc); 1238781a868fSWei Yang goto m64_failed; 1239781a868fSWei Yang } 1240781a868fSWei Yang 124102639b0eSWei Yang if (pdn->m64_per_iov == M64_PER_IOV) 1242781a868fSWei Yang rc = opal_pci_phb_mmio_enable(phb->opal_id, 124302639b0eSWei Yang OPAL_M64_WINDOW_TYPE, pdn->m64_wins[i][j], 2); 124402639b0eSWei Yang else 124502639b0eSWei Yang rc = opal_pci_phb_mmio_enable(phb->opal_id, 124602639b0eSWei Yang OPAL_M64_WINDOW_TYPE, pdn->m64_wins[i][j], 1); 124702639b0eSWei Yang 1248781a868fSWei Yang if (rc != OPAL_SUCCESS) { 1249781a868fSWei Yang dev_err(&pdev->dev, "Failed to enable M64 window #%d: %llx\n", 1250781a868fSWei Yang win, rc); 1251781a868fSWei Yang goto m64_failed; 1252781a868fSWei Yang } 1253781a868fSWei Yang } 125402639b0eSWei Yang } 1255781a868fSWei Yang return 0; 1256781a868fSWei Yang 1257781a868fSWei Yang m64_failed: 1258781a868fSWei Yang pnv_pci_vf_release_m64(pdev); 1259781a868fSWei Yang return -EBUSY; 1260781a868fSWei Yang } 1261781a868fSWei Yang 1262c035e37bSAlexey Kardashevskiy static long pnv_pci_ioda2_unset_window(struct iommu_table_group *table_group, 1263c035e37bSAlexey Kardashevskiy int num); 1264c035e37bSAlexey Kardashevskiy static void pnv_pci_ioda2_set_bypass(struct pnv_ioda_pe *pe, bool enable); 1265c035e37bSAlexey Kardashevskiy 1266781a868fSWei Yang static void pnv_pci_ioda2_release_dma_pe(struct pci_dev *dev, struct pnv_ioda_pe *pe) 1267781a868fSWei Yang { 1268781a868fSWei Yang struct iommu_table *tbl; 1269781a868fSWei Yang int64_t rc; 1270781a868fSWei Yang 1271b348aa65SAlexey Kardashevskiy tbl = pe->table_group.tables[0]; 1272c035e37bSAlexey Kardashevskiy rc = pnv_pci_ioda2_unset_window(&pe->table_group, 0); 1273781a868fSWei Yang if (rc) 1274781a868fSWei Yang pe_warn(pe, "OPAL error %ld release DMA window\n", rc); 1275781a868fSWei Yang 1276c035e37bSAlexey Kardashevskiy pnv_pci_ioda2_set_bypass(pe, false); 12770eaf4defSAlexey Kardashevskiy if (pe->table_group.group) { 12780eaf4defSAlexey Kardashevskiy iommu_group_put(pe->table_group.group); 12790eaf4defSAlexey Kardashevskiy BUG_ON(pe->table_group.group); 1280ac9a5889SAlexey Kardashevskiy } 1281aca6913fSAlexey Kardashevskiy pnv_pci_ioda2_table_free_pages(tbl); 1282781a868fSWei Yang iommu_free_table(tbl, of_node_full_name(dev->dev.of_node)); 1283781a868fSWei Yang } 1284781a868fSWei Yang 128502639b0eSWei Yang static void pnv_ioda_release_vf_PE(struct pci_dev *pdev, u16 num_vfs) 1286781a868fSWei Yang { 1287781a868fSWei Yang struct pci_bus *bus; 1288781a868fSWei Yang struct pci_controller *hose; 1289781a868fSWei Yang struct pnv_phb *phb; 1290781a868fSWei Yang struct pnv_ioda_pe *pe, *pe_n; 1291781a868fSWei Yang struct pci_dn *pdn; 129202639b0eSWei Yang u16 vf_index; 129302639b0eSWei Yang int64_t rc; 1294781a868fSWei Yang 1295781a868fSWei Yang bus = pdev->bus; 1296781a868fSWei Yang hose = pci_bus_to_host(bus); 1297781a868fSWei Yang phb = hose->private_data; 129802639b0eSWei Yang pdn = pci_get_pdn(pdev); 1299781a868fSWei Yang 1300781a868fSWei Yang if (!pdev->is_physfn) 1301781a868fSWei Yang return; 1302781a868fSWei Yang 130302639b0eSWei Yang if (pdn->m64_per_iov == M64_PER_IOV && num_vfs > M64_PER_IOV) { 130402639b0eSWei Yang int vf_group; 130502639b0eSWei Yang int vf_per_group; 130602639b0eSWei Yang int vf_index1; 130702639b0eSWei Yang 130802639b0eSWei Yang vf_per_group = roundup_pow_of_two(num_vfs) / pdn->m64_per_iov; 130902639b0eSWei Yang 131002639b0eSWei Yang for (vf_group = 0; vf_group < M64_PER_IOV; vf_group++) 131102639b0eSWei Yang for (vf_index = vf_group * vf_per_group; 131202639b0eSWei Yang vf_index < (vf_group + 1) * vf_per_group && 131302639b0eSWei Yang vf_index < num_vfs; 131402639b0eSWei Yang vf_index++) 131502639b0eSWei Yang for (vf_index1 = vf_group * vf_per_group; 131602639b0eSWei Yang vf_index1 < (vf_group + 1) * vf_per_group && 131702639b0eSWei Yang vf_index1 < num_vfs; 131802639b0eSWei Yang vf_index1++){ 131902639b0eSWei Yang 132002639b0eSWei Yang rc = opal_pci_set_peltv(phb->opal_id, 132102639b0eSWei Yang pdn->offset + vf_index, 132202639b0eSWei Yang pdn->offset + vf_index1, 132302639b0eSWei Yang OPAL_REMOVE_PE_FROM_DOMAIN); 132402639b0eSWei Yang 132502639b0eSWei Yang if (rc) 132602639b0eSWei Yang dev_warn(&pdev->dev, "%s: Failed to unlink same group PE#%d(%lld)\n", 132702639b0eSWei Yang __func__, 132802639b0eSWei Yang pdn->offset + vf_index1, rc); 132902639b0eSWei Yang } 133002639b0eSWei Yang } 133102639b0eSWei Yang 1332781a868fSWei Yang list_for_each_entry_safe(pe, pe_n, &phb->ioda.pe_list, list) { 1333781a868fSWei Yang if (pe->parent_dev != pdev) 1334781a868fSWei Yang continue; 1335781a868fSWei Yang 1336781a868fSWei Yang pnv_pci_ioda2_release_dma_pe(pdev, pe); 1337781a868fSWei Yang 1338781a868fSWei Yang /* Remove from list */ 1339781a868fSWei Yang mutex_lock(&phb->ioda.pe_list_mutex); 1340781a868fSWei Yang list_del(&pe->list); 1341781a868fSWei Yang mutex_unlock(&phb->ioda.pe_list_mutex); 1342781a868fSWei Yang 1343781a868fSWei Yang pnv_ioda_deconfigure_pe(phb, pe); 1344781a868fSWei Yang 1345781a868fSWei Yang pnv_ioda_free_pe(phb, pe->pe_number); 1346781a868fSWei Yang } 1347781a868fSWei Yang } 1348781a868fSWei Yang 1349781a868fSWei Yang void pnv_pci_sriov_disable(struct pci_dev *pdev) 1350781a868fSWei Yang { 1351781a868fSWei Yang struct pci_bus *bus; 1352781a868fSWei Yang struct pci_controller *hose; 1353781a868fSWei Yang struct pnv_phb *phb; 1354781a868fSWei Yang struct pci_dn *pdn; 1355781a868fSWei Yang struct pci_sriov *iov; 1356781a868fSWei Yang u16 num_vfs; 1357781a868fSWei Yang 1358781a868fSWei Yang bus = pdev->bus; 1359781a868fSWei Yang hose = pci_bus_to_host(bus); 1360781a868fSWei Yang phb = hose->private_data; 1361781a868fSWei Yang pdn = pci_get_pdn(pdev); 1362781a868fSWei Yang iov = pdev->sriov; 1363781a868fSWei Yang num_vfs = pdn->num_vfs; 1364781a868fSWei Yang 1365781a868fSWei Yang /* Release VF PEs */ 136602639b0eSWei Yang pnv_ioda_release_vf_PE(pdev, num_vfs); 1367781a868fSWei Yang 1368781a868fSWei Yang if (phb->type == PNV_PHB_IODA2) { 136902639b0eSWei Yang if (pdn->m64_per_iov == 1) 1370781a868fSWei Yang pnv_pci_vf_resource_shift(pdev, -pdn->offset); 1371781a868fSWei Yang 1372781a868fSWei Yang /* Release M64 windows */ 1373781a868fSWei Yang pnv_pci_vf_release_m64(pdev); 1374781a868fSWei Yang 1375781a868fSWei Yang /* Release PE numbers */ 1376781a868fSWei Yang bitmap_clear(phb->ioda.pe_alloc, pdn->offset, num_vfs); 1377781a868fSWei Yang pdn->offset = 0; 1378781a868fSWei Yang } 1379781a868fSWei Yang } 1380781a868fSWei Yang 1381781a868fSWei Yang static void pnv_pci_ioda2_setup_dma_pe(struct pnv_phb *phb, 1382781a868fSWei Yang struct pnv_ioda_pe *pe); 1383781a868fSWei Yang static void pnv_ioda_setup_vf_PE(struct pci_dev *pdev, u16 num_vfs) 1384781a868fSWei Yang { 1385781a868fSWei Yang struct pci_bus *bus; 1386781a868fSWei Yang struct pci_controller *hose; 1387781a868fSWei Yang struct pnv_phb *phb; 1388781a868fSWei Yang struct pnv_ioda_pe *pe; 1389781a868fSWei Yang int pe_num; 1390781a868fSWei Yang u16 vf_index; 1391781a868fSWei Yang struct pci_dn *pdn; 139202639b0eSWei Yang int64_t rc; 1393781a868fSWei Yang 1394781a868fSWei Yang bus = pdev->bus; 1395781a868fSWei Yang hose = pci_bus_to_host(bus); 1396781a868fSWei Yang phb = hose->private_data; 1397781a868fSWei Yang pdn = pci_get_pdn(pdev); 1398781a868fSWei Yang 1399781a868fSWei Yang if (!pdev->is_physfn) 1400781a868fSWei Yang return; 1401781a868fSWei Yang 1402781a868fSWei Yang /* Reserve PE for each VF */ 1403781a868fSWei Yang for (vf_index = 0; vf_index < num_vfs; vf_index++) { 1404781a868fSWei Yang pe_num = pdn->offset + vf_index; 1405781a868fSWei Yang 1406781a868fSWei Yang pe = &phb->ioda.pe_array[pe_num]; 1407781a868fSWei Yang pe->pe_number = pe_num; 1408781a868fSWei Yang pe->phb = phb; 1409781a868fSWei Yang pe->flags = PNV_IODA_PE_VF; 1410781a868fSWei Yang pe->pbus = NULL; 1411781a868fSWei Yang pe->parent_dev = pdev; 1412781a868fSWei Yang pe->tce32_seg = -1; 1413781a868fSWei Yang pe->mve_number = -1; 1414781a868fSWei Yang pe->rid = (pci_iov_virtfn_bus(pdev, vf_index) << 8) | 1415781a868fSWei Yang pci_iov_virtfn_devfn(pdev, vf_index); 1416781a868fSWei Yang 1417781a868fSWei Yang pe_info(pe, "VF %04d:%02d:%02d.%d associated with PE#%d\n", 1418781a868fSWei Yang hose->global_number, pdev->bus->number, 1419781a868fSWei Yang PCI_SLOT(pci_iov_virtfn_devfn(pdev, vf_index)), 1420781a868fSWei Yang PCI_FUNC(pci_iov_virtfn_devfn(pdev, vf_index)), pe_num); 1421781a868fSWei Yang 1422781a868fSWei Yang if (pnv_ioda_configure_pe(phb, pe)) { 1423781a868fSWei Yang /* XXX What do we do here ? */ 1424781a868fSWei Yang if (pe_num) 1425781a868fSWei Yang pnv_ioda_free_pe(phb, pe_num); 1426781a868fSWei Yang pe->pdev = NULL; 1427781a868fSWei Yang continue; 1428781a868fSWei Yang } 1429781a868fSWei Yang 1430781a868fSWei Yang /* Put PE to the list */ 1431781a868fSWei Yang mutex_lock(&phb->ioda.pe_list_mutex); 1432781a868fSWei Yang list_add_tail(&pe->list, &phb->ioda.pe_list); 1433781a868fSWei Yang mutex_unlock(&phb->ioda.pe_list_mutex); 1434781a868fSWei Yang 1435781a868fSWei Yang pnv_pci_ioda2_setup_dma_pe(phb, pe); 1436781a868fSWei Yang } 143702639b0eSWei Yang 143802639b0eSWei Yang if (pdn->m64_per_iov == M64_PER_IOV && num_vfs > M64_PER_IOV) { 143902639b0eSWei Yang int vf_group; 144002639b0eSWei Yang int vf_per_group; 144102639b0eSWei Yang int vf_index1; 144202639b0eSWei Yang 144302639b0eSWei Yang vf_per_group = roundup_pow_of_two(num_vfs) / pdn->m64_per_iov; 144402639b0eSWei Yang 144502639b0eSWei Yang for (vf_group = 0; vf_group < M64_PER_IOV; vf_group++) { 144602639b0eSWei Yang for (vf_index = vf_group * vf_per_group; 144702639b0eSWei Yang vf_index < (vf_group + 1) * vf_per_group && 144802639b0eSWei Yang vf_index < num_vfs; 144902639b0eSWei Yang vf_index++) { 145002639b0eSWei Yang for (vf_index1 = vf_group * vf_per_group; 145102639b0eSWei Yang vf_index1 < (vf_group + 1) * vf_per_group && 145202639b0eSWei Yang vf_index1 < num_vfs; 145302639b0eSWei Yang vf_index1++) { 145402639b0eSWei Yang 145502639b0eSWei Yang rc = opal_pci_set_peltv(phb->opal_id, 145602639b0eSWei Yang pdn->offset + vf_index, 145702639b0eSWei Yang pdn->offset + vf_index1, 145802639b0eSWei Yang OPAL_ADD_PE_TO_DOMAIN); 145902639b0eSWei Yang 146002639b0eSWei Yang if (rc) 146102639b0eSWei Yang dev_warn(&pdev->dev, "%s: Failed to link same group PE#%d(%lld)\n", 146202639b0eSWei Yang __func__, 146302639b0eSWei Yang pdn->offset + vf_index1, rc); 146402639b0eSWei Yang } 146502639b0eSWei Yang } 146602639b0eSWei Yang } 146702639b0eSWei Yang } 1468781a868fSWei Yang } 1469781a868fSWei Yang 1470781a868fSWei Yang int pnv_pci_sriov_enable(struct pci_dev *pdev, u16 num_vfs) 1471781a868fSWei Yang { 1472781a868fSWei Yang struct pci_bus *bus; 1473781a868fSWei Yang struct pci_controller *hose; 1474781a868fSWei Yang struct pnv_phb *phb; 1475781a868fSWei Yang struct pci_dn *pdn; 1476781a868fSWei Yang int ret; 1477781a868fSWei Yang 1478781a868fSWei Yang bus = pdev->bus; 1479781a868fSWei Yang hose = pci_bus_to_host(bus); 1480781a868fSWei Yang phb = hose->private_data; 1481781a868fSWei Yang pdn = pci_get_pdn(pdev); 1482781a868fSWei Yang 1483781a868fSWei Yang if (phb->type == PNV_PHB_IODA2) { 1484781a868fSWei Yang /* Calculate available PE for required VFs */ 1485781a868fSWei Yang mutex_lock(&phb->ioda.pe_alloc_mutex); 1486781a868fSWei Yang pdn->offset = bitmap_find_next_zero_area( 1487781a868fSWei Yang phb->ioda.pe_alloc, phb->ioda.total_pe, 1488781a868fSWei Yang 0, num_vfs, 0); 1489781a868fSWei Yang if (pdn->offset >= phb->ioda.total_pe) { 1490781a868fSWei Yang mutex_unlock(&phb->ioda.pe_alloc_mutex); 1491781a868fSWei Yang dev_info(&pdev->dev, "Failed to enable VF%d\n", num_vfs); 1492781a868fSWei Yang pdn->offset = 0; 1493781a868fSWei Yang return -EBUSY; 1494781a868fSWei Yang } 1495781a868fSWei Yang bitmap_set(phb->ioda.pe_alloc, pdn->offset, num_vfs); 1496781a868fSWei Yang pdn->num_vfs = num_vfs; 1497781a868fSWei Yang mutex_unlock(&phb->ioda.pe_alloc_mutex); 1498781a868fSWei Yang 1499781a868fSWei Yang /* Assign M64 window accordingly */ 150002639b0eSWei Yang ret = pnv_pci_vf_assign_m64(pdev, num_vfs); 1501781a868fSWei Yang if (ret) { 1502781a868fSWei Yang dev_info(&pdev->dev, "Not enough M64 window resources\n"); 1503781a868fSWei Yang goto m64_failed; 1504781a868fSWei Yang } 1505781a868fSWei Yang 1506781a868fSWei Yang /* 1507781a868fSWei Yang * When using one M64 BAR to map one IOV BAR, we need to shift 1508781a868fSWei Yang * the IOV BAR according to the PE# allocated to the VFs. 1509781a868fSWei Yang * Otherwise, the PE# for the VF will conflict with others. 1510781a868fSWei Yang */ 151102639b0eSWei Yang if (pdn->m64_per_iov == 1) { 1512781a868fSWei Yang ret = pnv_pci_vf_resource_shift(pdev, pdn->offset); 1513781a868fSWei Yang if (ret) 1514781a868fSWei Yang goto m64_failed; 1515781a868fSWei Yang } 151602639b0eSWei Yang } 1517781a868fSWei Yang 1518781a868fSWei Yang /* Setup VF PEs */ 1519781a868fSWei Yang pnv_ioda_setup_vf_PE(pdev, num_vfs); 1520781a868fSWei Yang 1521781a868fSWei Yang return 0; 1522781a868fSWei Yang 1523781a868fSWei Yang m64_failed: 1524781a868fSWei Yang bitmap_clear(phb->ioda.pe_alloc, pdn->offset, num_vfs); 1525781a868fSWei Yang pdn->offset = 0; 1526781a868fSWei Yang 1527781a868fSWei Yang return ret; 1528781a868fSWei Yang } 1529781a868fSWei Yang 1530a8b2f828SGavin Shan int pcibios_sriov_disable(struct pci_dev *pdev) 1531a8b2f828SGavin Shan { 1532781a868fSWei Yang pnv_pci_sriov_disable(pdev); 1533781a868fSWei Yang 1534a8b2f828SGavin Shan /* Release PCI data */ 1535a8b2f828SGavin Shan remove_dev_pci_data(pdev); 1536a8b2f828SGavin Shan return 0; 1537a8b2f828SGavin Shan } 1538a8b2f828SGavin Shan 1539a8b2f828SGavin Shan int pcibios_sriov_enable(struct pci_dev *pdev, u16 num_vfs) 1540a8b2f828SGavin Shan { 1541a8b2f828SGavin Shan /* Allocate PCI data */ 1542a8b2f828SGavin Shan add_dev_pci_data(pdev); 1543781a868fSWei Yang 1544781a868fSWei Yang pnv_pci_sriov_enable(pdev, num_vfs); 1545a8b2f828SGavin Shan return 0; 1546a8b2f828SGavin Shan } 1547a8b2f828SGavin Shan #endif /* CONFIG_PCI_IOV */ 1548a8b2f828SGavin Shan 1549959c9bddSGavin Shan static void pnv_pci_ioda_dma_dev_setup(struct pnv_phb *phb, struct pci_dev *pdev) 1550184cd4a3SBenjamin Herrenschmidt { 1551b72c1f65SBenjamin Herrenschmidt struct pci_dn *pdn = pci_get_pdn(pdev); 1552959c9bddSGavin Shan struct pnv_ioda_pe *pe; 1553184cd4a3SBenjamin Herrenschmidt 1554959c9bddSGavin Shan /* 1555959c9bddSGavin Shan * The function can be called while the PE# 1556959c9bddSGavin Shan * hasn't been assigned. Do nothing for the 1557959c9bddSGavin Shan * case. 1558959c9bddSGavin Shan */ 1559959c9bddSGavin Shan if (!pdn || pdn->pe_number == IODA_INVALID_PE) 1560959c9bddSGavin Shan return; 1561184cd4a3SBenjamin Herrenschmidt 1562959c9bddSGavin Shan pe = &phb->ioda.pe_array[pdn->pe_number]; 1563cd15b048SBenjamin Herrenschmidt WARN_ON(get_dma_ops(&pdev->dev) != &dma_iommu_ops); 15640e1ffef0SAlexey Kardashevskiy set_dma_offset(&pdev->dev, pe->tce_bypass_base); 1565b348aa65SAlexey Kardashevskiy set_iommu_table_base(&pdev->dev, pe->table_group.tables[0]); 15664617082eSAlexey Kardashevskiy /* 15674617082eSAlexey Kardashevskiy * Note: iommu_add_device() will fail here as 15684617082eSAlexey Kardashevskiy * for physical PE: the device is already added by now; 15694617082eSAlexey Kardashevskiy * for virtual PE: sysfs entries are not ready yet and 15704617082eSAlexey Kardashevskiy * tce_iommu_bus_notifier will add the device to a group later. 15714617082eSAlexey Kardashevskiy */ 1572184cd4a3SBenjamin Herrenschmidt } 1573184cd4a3SBenjamin Herrenschmidt 1574763d2d8dSDaniel Axtens static int pnv_pci_ioda_dma_set_mask(struct pci_dev *pdev, u64 dma_mask) 1575cd15b048SBenjamin Herrenschmidt { 1576763d2d8dSDaniel Axtens struct pci_controller *hose = pci_bus_to_host(pdev->bus); 1577763d2d8dSDaniel Axtens struct pnv_phb *phb = hose->private_data; 1578cd15b048SBenjamin Herrenschmidt struct pci_dn *pdn = pci_get_pdn(pdev); 1579cd15b048SBenjamin Herrenschmidt struct pnv_ioda_pe *pe; 1580cd15b048SBenjamin Herrenschmidt uint64_t top; 1581cd15b048SBenjamin Herrenschmidt bool bypass = false; 1582cd15b048SBenjamin Herrenschmidt 1583cd15b048SBenjamin Herrenschmidt if (WARN_ON(!pdn || pdn->pe_number == IODA_INVALID_PE)) 1584cd15b048SBenjamin Herrenschmidt return -ENODEV;; 1585cd15b048SBenjamin Herrenschmidt 1586cd15b048SBenjamin Herrenschmidt pe = &phb->ioda.pe_array[pdn->pe_number]; 1587cd15b048SBenjamin Herrenschmidt if (pe->tce_bypass_enabled) { 1588cd15b048SBenjamin Herrenschmidt top = pe->tce_bypass_base + memblock_end_of_DRAM() - 1; 1589cd15b048SBenjamin Herrenschmidt bypass = (dma_mask >= top); 1590cd15b048SBenjamin Herrenschmidt } 1591cd15b048SBenjamin Herrenschmidt 1592cd15b048SBenjamin Herrenschmidt if (bypass) { 1593cd15b048SBenjamin Herrenschmidt dev_info(&pdev->dev, "Using 64-bit DMA iommu bypass\n"); 1594cd15b048SBenjamin Herrenschmidt set_dma_ops(&pdev->dev, &dma_direct_ops); 1595cd15b048SBenjamin Herrenschmidt } else { 1596cd15b048SBenjamin Herrenschmidt dev_info(&pdev->dev, "Using 32-bit DMA via iommu\n"); 1597cd15b048SBenjamin Herrenschmidt set_dma_ops(&pdev->dev, &dma_iommu_ops); 1598cd15b048SBenjamin Herrenschmidt } 1599a32305bfSBrian W Hart *pdev->dev.dma_mask = dma_mask; 1600cd15b048SBenjamin Herrenschmidt return 0; 1601cd15b048SBenjamin Herrenschmidt } 1602cd15b048SBenjamin Herrenschmidt 160353522982SAndrew Donnellan static u64 pnv_pci_ioda_dma_get_required_mask(struct pci_dev *pdev) 1604fe7e85c6SGavin Shan { 160553522982SAndrew Donnellan struct pci_controller *hose = pci_bus_to_host(pdev->bus); 160653522982SAndrew Donnellan struct pnv_phb *phb = hose->private_data; 1607fe7e85c6SGavin Shan struct pci_dn *pdn = pci_get_pdn(pdev); 1608fe7e85c6SGavin Shan struct pnv_ioda_pe *pe; 1609fe7e85c6SGavin Shan u64 end, mask; 1610fe7e85c6SGavin Shan 1611fe7e85c6SGavin Shan if (WARN_ON(!pdn || pdn->pe_number == IODA_INVALID_PE)) 1612fe7e85c6SGavin Shan return 0; 1613fe7e85c6SGavin Shan 1614fe7e85c6SGavin Shan pe = &phb->ioda.pe_array[pdn->pe_number]; 1615fe7e85c6SGavin Shan if (!pe->tce_bypass_enabled) 1616fe7e85c6SGavin Shan return __dma_get_required_mask(&pdev->dev); 1617fe7e85c6SGavin Shan 1618fe7e85c6SGavin Shan 1619fe7e85c6SGavin Shan end = pe->tce_bypass_base + memblock_end_of_DRAM(); 1620fe7e85c6SGavin Shan mask = 1ULL << (fls64(end) - 1); 1621fe7e85c6SGavin Shan mask += mask - 1; 1622fe7e85c6SGavin Shan 1623fe7e85c6SGavin Shan return mask; 1624fe7e85c6SGavin Shan } 1625fe7e85c6SGavin Shan 1626dff4a39eSGavin Shan static void pnv_ioda_setup_bus_dma(struct pnv_ioda_pe *pe, 1627ea30e99eSAlexey Kardashevskiy struct pci_bus *bus) 162874251fe2SBenjamin Herrenschmidt { 162974251fe2SBenjamin Herrenschmidt struct pci_dev *dev; 163074251fe2SBenjamin Herrenschmidt 163174251fe2SBenjamin Herrenschmidt list_for_each_entry(dev, &bus->devices, bus_list) { 1632b348aa65SAlexey Kardashevskiy set_iommu_table_base(&dev->dev, pe->table_group.tables[0]); 1633e91c2511SBenjamin Herrenschmidt set_dma_offset(&dev->dev, pe->tce_bypass_base); 16344617082eSAlexey Kardashevskiy iommu_add_device(&dev->dev); 1635dff4a39eSGavin Shan 16365c89a87dSAlexey Kardashevskiy if ((pe->flags & PNV_IODA_PE_BUS_ALL) && dev->subordinate) 1637ea30e99eSAlexey Kardashevskiy pnv_ioda_setup_bus_dma(pe, dev->subordinate); 163874251fe2SBenjamin Herrenschmidt } 163974251fe2SBenjamin Herrenschmidt } 164074251fe2SBenjamin Herrenschmidt 1641decbda25SAlexey Kardashevskiy static void pnv_pci_ioda1_tce_invalidate(struct iommu_table *tbl, 1642decbda25SAlexey Kardashevskiy unsigned long index, unsigned long npages, bool rm) 16434cce9550SGavin Shan { 16440eaf4defSAlexey Kardashevskiy struct iommu_table_group_link *tgl = list_first_entry_or_null( 16450eaf4defSAlexey Kardashevskiy &tbl->it_group_list, struct iommu_table_group_link, 16460eaf4defSAlexey Kardashevskiy next); 16470eaf4defSAlexey Kardashevskiy struct pnv_ioda_pe *pe = container_of(tgl->table_group, 1648b348aa65SAlexey Kardashevskiy struct pnv_ioda_pe, table_group); 16493ad26e5cSBenjamin Herrenschmidt __be64 __iomem *invalidate = rm ? 16505780fb04SAlexey Kardashevskiy (__be64 __iomem *)pe->phb->ioda.tce_inval_reg_phys : 16515780fb04SAlexey Kardashevskiy pe->phb->ioda.tce_inval_reg; 16524cce9550SGavin Shan unsigned long start, end, inc; 1653b0376c9bSAlexey Kardashevskiy const unsigned shift = tbl->it_page_shift; 16544cce9550SGavin Shan 1655decbda25SAlexey Kardashevskiy start = __pa(((__be64 *)tbl->it_base) + index - tbl->it_offset); 1656decbda25SAlexey Kardashevskiy end = __pa(((__be64 *)tbl->it_base) + index - tbl->it_offset + 1657decbda25SAlexey Kardashevskiy npages - 1); 16584cce9550SGavin Shan 16594cce9550SGavin Shan /* BML uses this case for p6/p7/galaxy2: Shift addr and put in node */ 16604cce9550SGavin Shan if (tbl->it_busno) { 1661b0376c9bSAlexey Kardashevskiy start <<= shift; 1662b0376c9bSAlexey Kardashevskiy end <<= shift; 1663b0376c9bSAlexey Kardashevskiy inc = 128ull << shift; 16644cce9550SGavin Shan start |= tbl->it_busno; 16654cce9550SGavin Shan end |= tbl->it_busno; 16664cce9550SGavin Shan } else if (tbl->it_type & TCE_PCI_SWINV_PAIR) { 16674cce9550SGavin Shan /* p7ioc-style invalidation, 2 TCEs per write */ 16684cce9550SGavin Shan start |= (1ull << 63); 16694cce9550SGavin Shan end |= (1ull << 63); 16704cce9550SGavin Shan inc = 16; 16714cce9550SGavin Shan } else { 16724cce9550SGavin Shan /* Default (older HW) */ 16734cce9550SGavin Shan inc = 128; 16744cce9550SGavin Shan } 16754cce9550SGavin Shan 16764cce9550SGavin Shan end |= inc - 1; /* round up end to be different than start */ 16774cce9550SGavin Shan 16784cce9550SGavin Shan mb(); /* Ensure above stores are visible */ 16794cce9550SGavin Shan while (start <= end) { 16808e0a1611SAlexey Kardashevskiy if (rm) 16813ad26e5cSBenjamin Herrenschmidt __raw_rm_writeq(cpu_to_be64(start), invalidate); 16828e0a1611SAlexey Kardashevskiy else 16833a1a4661SBenjamin Herrenschmidt __raw_writeq(cpu_to_be64(start), invalidate); 16844cce9550SGavin Shan start += inc; 16854cce9550SGavin Shan } 16864cce9550SGavin Shan 16874cce9550SGavin Shan /* 16884cce9550SGavin Shan * The iommu layer will do another mb() for us on build() 16894cce9550SGavin Shan * and we don't care on free() 16904cce9550SGavin Shan */ 16914cce9550SGavin Shan } 16924cce9550SGavin Shan 1693decbda25SAlexey Kardashevskiy static int pnv_ioda1_tce_build(struct iommu_table *tbl, long index, 1694decbda25SAlexey Kardashevskiy long npages, unsigned long uaddr, 1695decbda25SAlexey Kardashevskiy enum dma_data_direction direction, 1696decbda25SAlexey Kardashevskiy struct dma_attrs *attrs) 1697decbda25SAlexey Kardashevskiy { 1698decbda25SAlexey Kardashevskiy int ret = pnv_tce_build(tbl, index, npages, uaddr, direction, 1699decbda25SAlexey Kardashevskiy attrs); 1700decbda25SAlexey Kardashevskiy 1701decbda25SAlexey Kardashevskiy if (!ret && (tbl->it_type & TCE_PCI_SWINV_CREATE)) 1702decbda25SAlexey Kardashevskiy pnv_pci_ioda1_tce_invalidate(tbl, index, npages, false); 1703decbda25SAlexey Kardashevskiy 1704decbda25SAlexey Kardashevskiy return ret; 1705decbda25SAlexey Kardashevskiy } 1706decbda25SAlexey Kardashevskiy 170705c6cfb9SAlexey Kardashevskiy #ifdef CONFIG_IOMMU_API 170805c6cfb9SAlexey Kardashevskiy static int pnv_ioda1_tce_xchg(struct iommu_table *tbl, long index, 170905c6cfb9SAlexey Kardashevskiy unsigned long *hpa, enum dma_data_direction *direction) 171005c6cfb9SAlexey Kardashevskiy { 171105c6cfb9SAlexey Kardashevskiy long ret = pnv_tce_xchg(tbl, index, hpa, direction); 171205c6cfb9SAlexey Kardashevskiy 171305c6cfb9SAlexey Kardashevskiy if (!ret && (tbl->it_type & 171405c6cfb9SAlexey Kardashevskiy (TCE_PCI_SWINV_CREATE | TCE_PCI_SWINV_FREE))) 171505c6cfb9SAlexey Kardashevskiy pnv_pci_ioda1_tce_invalidate(tbl, index, 1, false); 171605c6cfb9SAlexey Kardashevskiy 171705c6cfb9SAlexey Kardashevskiy return ret; 171805c6cfb9SAlexey Kardashevskiy } 171905c6cfb9SAlexey Kardashevskiy #endif 172005c6cfb9SAlexey Kardashevskiy 1721decbda25SAlexey Kardashevskiy static void pnv_ioda1_tce_free(struct iommu_table *tbl, long index, 1722decbda25SAlexey Kardashevskiy long npages) 1723decbda25SAlexey Kardashevskiy { 1724decbda25SAlexey Kardashevskiy pnv_tce_free(tbl, index, npages); 1725decbda25SAlexey Kardashevskiy 1726decbda25SAlexey Kardashevskiy if (tbl->it_type & TCE_PCI_SWINV_FREE) 1727decbda25SAlexey Kardashevskiy pnv_pci_ioda1_tce_invalidate(tbl, index, npages, false); 1728decbda25SAlexey Kardashevskiy } 1729decbda25SAlexey Kardashevskiy 1730da004c36SAlexey Kardashevskiy static struct iommu_table_ops pnv_ioda1_iommu_ops = { 1731decbda25SAlexey Kardashevskiy .set = pnv_ioda1_tce_build, 173205c6cfb9SAlexey Kardashevskiy #ifdef CONFIG_IOMMU_API 173305c6cfb9SAlexey Kardashevskiy .exchange = pnv_ioda1_tce_xchg, 173405c6cfb9SAlexey Kardashevskiy #endif 1735decbda25SAlexey Kardashevskiy .clear = pnv_ioda1_tce_free, 1736da004c36SAlexey Kardashevskiy .get = pnv_tce_get, 1737da004c36SAlexey Kardashevskiy }; 1738da004c36SAlexey Kardashevskiy 17395780fb04SAlexey Kardashevskiy static inline void pnv_pci_ioda2_tce_invalidate_entire(struct pnv_ioda_pe *pe) 17405780fb04SAlexey Kardashevskiy { 17415780fb04SAlexey Kardashevskiy /* 01xb - invalidate TCEs that match the specified PE# */ 17425780fb04SAlexey Kardashevskiy unsigned long val = (0x4ull << 60) | (pe->pe_number & 0xFF); 17435780fb04SAlexey Kardashevskiy struct pnv_phb *phb = pe->phb; 17445780fb04SAlexey Kardashevskiy 17455780fb04SAlexey Kardashevskiy if (!phb->ioda.tce_inval_reg) 17465780fb04SAlexey Kardashevskiy return; 17475780fb04SAlexey Kardashevskiy 17485780fb04SAlexey Kardashevskiy mb(); /* Ensure above stores are visible */ 17495780fb04SAlexey Kardashevskiy __raw_writeq(cpu_to_be64(val), phb->ioda.tce_inval_reg); 17505780fb04SAlexey Kardashevskiy } 17515780fb04SAlexey Kardashevskiy 1752e57080f1SAlexey Kardashevskiy static void pnv_pci_ioda2_do_tce_invalidate(unsigned pe_number, bool rm, 1753e57080f1SAlexey Kardashevskiy __be64 __iomem *invalidate, unsigned shift, 1754e57080f1SAlexey Kardashevskiy unsigned long index, unsigned long npages) 17554cce9550SGavin Shan { 17564cce9550SGavin Shan unsigned long start, end, inc; 17574cce9550SGavin Shan 17584cce9550SGavin Shan /* We'll invalidate DMA address in PE scope */ 1759b0376c9bSAlexey Kardashevskiy start = 0x2ull << 60; 1760e57080f1SAlexey Kardashevskiy start |= (pe_number & 0xFF); 17614cce9550SGavin Shan end = start; 17624cce9550SGavin Shan 17634cce9550SGavin Shan /* Figure out the start, end and step */ 1764decbda25SAlexey Kardashevskiy start |= (index << shift); 1765decbda25SAlexey Kardashevskiy end |= ((index + npages - 1) << shift); 1766b0376c9bSAlexey Kardashevskiy inc = (0x1ull << shift); 17674cce9550SGavin Shan mb(); 17684cce9550SGavin Shan 17694cce9550SGavin Shan while (start <= end) { 17708e0a1611SAlexey Kardashevskiy if (rm) 17713ad26e5cSBenjamin Herrenschmidt __raw_rm_writeq(cpu_to_be64(start), invalidate); 17728e0a1611SAlexey Kardashevskiy else 17733a1a4661SBenjamin Herrenschmidt __raw_writeq(cpu_to_be64(start), invalidate); 17744cce9550SGavin Shan start += inc; 17754cce9550SGavin Shan } 17764cce9550SGavin Shan } 17774cce9550SGavin Shan 1778e57080f1SAlexey Kardashevskiy static void pnv_pci_ioda2_tce_invalidate(struct iommu_table *tbl, 1779e57080f1SAlexey Kardashevskiy unsigned long index, unsigned long npages, bool rm) 1780e57080f1SAlexey Kardashevskiy { 1781e57080f1SAlexey Kardashevskiy struct iommu_table_group_link *tgl; 1782e57080f1SAlexey Kardashevskiy 1783e57080f1SAlexey Kardashevskiy list_for_each_entry_rcu(tgl, &tbl->it_group_list, next) { 1784e57080f1SAlexey Kardashevskiy struct pnv_ioda_pe *pe = container_of(tgl->table_group, 1785e57080f1SAlexey Kardashevskiy struct pnv_ioda_pe, table_group); 1786e57080f1SAlexey Kardashevskiy __be64 __iomem *invalidate = rm ? 1787e57080f1SAlexey Kardashevskiy (__be64 __iomem *)pe->phb->ioda.tce_inval_reg_phys : 1788e57080f1SAlexey Kardashevskiy pe->phb->ioda.tce_inval_reg; 1789e57080f1SAlexey Kardashevskiy 1790e57080f1SAlexey Kardashevskiy pnv_pci_ioda2_do_tce_invalidate(pe->pe_number, rm, 1791e57080f1SAlexey Kardashevskiy invalidate, tbl->it_page_shift, 1792e57080f1SAlexey Kardashevskiy index, npages); 1793e57080f1SAlexey Kardashevskiy } 1794e57080f1SAlexey Kardashevskiy } 1795e57080f1SAlexey Kardashevskiy 1796decbda25SAlexey Kardashevskiy static int pnv_ioda2_tce_build(struct iommu_table *tbl, long index, 1797decbda25SAlexey Kardashevskiy long npages, unsigned long uaddr, 1798decbda25SAlexey Kardashevskiy enum dma_data_direction direction, 1799decbda25SAlexey Kardashevskiy struct dma_attrs *attrs) 18004cce9550SGavin Shan { 1801decbda25SAlexey Kardashevskiy int ret = pnv_tce_build(tbl, index, npages, uaddr, direction, 1802decbda25SAlexey Kardashevskiy attrs); 18034cce9550SGavin Shan 1804decbda25SAlexey Kardashevskiy if (!ret && (tbl->it_type & TCE_PCI_SWINV_CREATE)) 1805decbda25SAlexey Kardashevskiy pnv_pci_ioda2_tce_invalidate(tbl, index, npages, false); 1806decbda25SAlexey Kardashevskiy 1807decbda25SAlexey Kardashevskiy return ret; 1808decbda25SAlexey Kardashevskiy } 1809decbda25SAlexey Kardashevskiy 181005c6cfb9SAlexey Kardashevskiy #ifdef CONFIG_IOMMU_API 181105c6cfb9SAlexey Kardashevskiy static int pnv_ioda2_tce_xchg(struct iommu_table *tbl, long index, 181205c6cfb9SAlexey Kardashevskiy unsigned long *hpa, enum dma_data_direction *direction) 181305c6cfb9SAlexey Kardashevskiy { 181405c6cfb9SAlexey Kardashevskiy long ret = pnv_tce_xchg(tbl, index, hpa, direction); 181505c6cfb9SAlexey Kardashevskiy 181605c6cfb9SAlexey Kardashevskiy if (!ret && (tbl->it_type & 181705c6cfb9SAlexey Kardashevskiy (TCE_PCI_SWINV_CREATE | TCE_PCI_SWINV_FREE))) 181805c6cfb9SAlexey Kardashevskiy pnv_pci_ioda2_tce_invalidate(tbl, index, 1, false); 181905c6cfb9SAlexey Kardashevskiy 182005c6cfb9SAlexey Kardashevskiy return ret; 182105c6cfb9SAlexey Kardashevskiy } 182205c6cfb9SAlexey Kardashevskiy #endif 182305c6cfb9SAlexey Kardashevskiy 1824decbda25SAlexey Kardashevskiy static void pnv_ioda2_tce_free(struct iommu_table *tbl, long index, 1825decbda25SAlexey Kardashevskiy long npages) 1826decbda25SAlexey Kardashevskiy { 1827decbda25SAlexey Kardashevskiy pnv_tce_free(tbl, index, npages); 1828decbda25SAlexey Kardashevskiy 1829decbda25SAlexey Kardashevskiy if (tbl->it_type & TCE_PCI_SWINV_FREE) 1830decbda25SAlexey Kardashevskiy pnv_pci_ioda2_tce_invalidate(tbl, index, npages, false); 18314cce9550SGavin Shan } 18324cce9550SGavin Shan 18334793d65dSAlexey Kardashevskiy static void pnv_ioda2_table_free(struct iommu_table *tbl) 18344793d65dSAlexey Kardashevskiy { 18354793d65dSAlexey Kardashevskiy pnv_pci_ioda2_table_free_pages(tbl); 18364793d65dSAlexey Kardashevskiy iommu_free_table(tbl, "pnv"); 18374793d65dSAlexey Kardashevskiy } 18384793d65dSAlexey Kardashevskiy 1839da004c36SAlexey Kardashevskiy static struct iommu_table_ops pnv_ioda2_iommu_ops = { 1840decbda25SAlexey Kardashevskiy .set = pnv_ioda2_tce_build, 184105c6cfb9SAlexey Kardashevskiy #ifdef CONFIG_IOMMU_API 184205c6cfb9SAlexey Kardashevskiy .exchange = pnv_ioda2_tce_xchg, 184305c6cfb9SAlexey Kardashevskiy #endif 1844decbda25SAlexey Kardashevskiy .clear = pnv_ioda2_tce_free, 1845da004c36SAlexey Kardashevskiy .get = pnv_tce_get, 18464793d65dSAlexey Kardashevskiy .free = pnv_ioda2_table_free, 1847da004c36SAlexey Kardashevskiy }; 1848da004c36SAlexey Kardashevskiy 1849cad5cef6SGreg Kroah-Hartman static void pnv_pci_ioda_setup_dma_pe(struct pnv_phb *phb, 1850cad5cef6SGreg Kroah-Hartman struct pnv_ioda_pe *pe, unsigned int base, 1851184cd4a3SBenjamin Herrenschmidt unsigned int segs) 1852184cd4a3SBenjamin Herrenschmidt { 1853184cd4a3SBenjamin Herrenschmidt 1854184cd4a3SBenjamin Herrenschmidt struct page *tce_mem = NULL; 1855184cd4a3SBenjamin Herrenschmidt struct iommu_table *tbl; 1856184cd4a3SBenjamin Herrenschmidt unsigned int i; 1857184cd4a3SBenjamin Herrenschmidt int64_t rc; 1858184cd4a3SBenjamin Herrenschmidt void *addr; 1859184cd4a3SBenjamin Herrenschmidt 1860184cd4a3SBenjamin Herrenschmidt /* XXX FIXME: Handle 64-bit only DMA devices */ 1861184cd4a3SBenjamin Herrenschmidt /* XXX FIXME: Provide 64-bit DMA facilities & non-4K TCE tables etc.. */ 1862184cd4a3SBenjamin Herrenschmidt /* XXX FIXME: Allocate multi-level tables on PHB3 */ 1863184cd4a3SBenjamin Herrenschmidt 1864184cd4a3SBenjamin Herrenschmidt /* We shouldn't already have a 32-bit DMA associated */ 1865184cd4a3SBenjamin Herrenschmidt if (WARN_ON(pe->tce32_seg >= 0)) 1866184cd4a3SBenjamin Herrenschmidt return; 1867184cd4a3SBenjamin Herrenschmidt 18680eaf4defSAlexey Kardashevskiy tbl = pnv_pci_table_alloc(phb->hose->node); 1869b348aa65SAlexey Kardashevskiy iommu_register_group(&pe->table_group, phb->hose->global_number, 1870b348aa65SAlexey Kardashevskiy pe->pe_number); 18710eaf4defSAlexey Kardashevskiy pnv_pci_link_table_and_group(phb->hose->node, 0, tbl, &pe->table_group); 1872c5773822SAlexey Kardashevskiy 1873184cd4a3SBenjamin Herrenschmidt /* Grab a 32-bit TCE table */ 1874184cd4a3SBenjamin Herrenschmidt pe->tce32_seg = base; 1875184cd4a3SBenjamin Herrenschmidt pe_info(pe, " Setting up 32-bit TCE table at %08x..%08x\n", 1876184cd4a3SBenjamin Herrenschmidt (base << 28), ((base + segs) << 28) - 1); 1877184cd4a3SBenjamin Herrenschmidt 1878184cd4a3SBenjamin Herrenschmidt /* XXX Currently, we allocate one big contiguous table for the 1879184cd4a3SBenjamin Herrenschmidt * TCEs. We only really need one chunk per 256M of TCE space 1880184cd4a3SBenjamin Herrenschmidt * (ie per segment) but that's an optimization for later, it 1881184cd4a3SBenjamin Herrenschmidt * requires some added smarts with our get/put_tce implementation 1882184cd4a3SBenjamin Herrenschmidt */ 1883184cd4a3SBenjamin Herrenschmidt tce_mem = alloc_pages_node(phb->hose->node, GFP_KERNEL, 1884184cd4a3SBenjamin Herrenschmidt get_order(TCE32_TABLE_SIZE * segs)); 1885184cd4a3SBenjamin Herrenschmidt if (!tce_mem) { 1886184cd4a3SBenjamin Herrenschmidt pe_err(pe, " Failed to allocate a 32-bit TCE memory\n"); 1887184cd4a3SBenjamin Herrenschmidt goto fail; 1888184cd4a3SBenjamin Herrenschmidt } 1889184cd4a3SBenjamin Herrenschmidt addr = page_address(tce_mem); 1890184cd4a3SBenjamin Herrenschmidt memset(addr, 0, TCE32_TABLE_SIZE * segs); 1891184cd4a3SBenjamin Herrenschmidt 1892184cd4a3SBenjamin Herrenschmidt /* Configure HW */ 1893184cd4a3SBenjamin Herrenschmidt for (i = 0; i < segs; i++) { 1894184cd4a3SBenjamin Herrenschmidt rc = opal_pci_map_pe_dma_window(phb->opal_id, 1895184cd4a3SBenjamin Herrenschmidt pe->pe_number, 1896184cd4a3SBenjamin Herrenschmidt base + i, 1, 1897184cd4a3SBenjamin Herrenschmidt __pa(addr) + TCE32_TABLE_SIZE * i, 1898184cd4a3SBenjamin Herrenschmidt TCE32_TABLE_SIZE, 0x1000); 1899184cd4a3SBenjamin Herrenschmidt if (rc) { 1900184cd4a3SBenjamin Herrenschmidt pe_err(pe, " Failed to configure 32-bit TCE table," 1901184cd4a3SBenjamin Herrenschmidt " err %ld\n", rc); 1902184cd4a3SBenjamin Herrenschmidt goto fail; 1903184cd4a3SBenjamin Herrenschmidt } 1904184cd4a3SBenjamin Herrenschmidt } 1905184cd4a3SBenjamin Herrenschmidt 1906184cd4a3SBenjamin Herrenschmidt /* Setup linux iommu table */ 1907184cd4a3SBenjamin Herrenschmidt pnv_pci_setup_iommu_table(tbl, addr, TCE32_TABLE_SIZE * segs, 19088fa5d454SAlexey Kardashevskiy base << 28, IOMMU_PAGE_SHIFT_4K); 1909184cd4a3SBenjamin Herrenschmidt 1910184cd4a3SBenjamin Herrenschmidt /* OPAL variant of P7IOC SW invalidated TCEs */ 19115780fb04SAlexey Kardashevskiy if (phb->ioda.tce_inval_reg) 191265fd766bSGavin Shan tbl->it_type |= (TCE_PCI_SWINV_CREATE | 191365fd766bSGavin Shan TCE_PCI_SWINV_FREE | 191465fd766bSGavin Shan TCE_PCI_SWINV_PAIR); 19155780fb04SAlexey Kardashevskiy 1916da004c36SAlexey Kardashevskiy tbl->it_ops = &pnv_ioda1_iommu_ops; 19174793d65dSAlexey Kardashevskiy pe->table_group.tce32_start = tbl->it_offset << tbl->it_page_shift; 19184793d65dSAlexey Kardashevskiy pe->table_group.tce32_size = tbl->it_size << tbl->it_page_shift; 1919184cd4a3SBenjamin Herrenschmidt iommu_init_table(tbl, phb->hose->node); 1920184cd4a3SBenjamin Herrenschmidt 1921781a868fSWei Yang if (pe->flags & PNV_IODA_PE_DEV) { 19224617082eSAlexey Kardashevskiy /* 19234617082eSAlexey Kardashevskiy * Setting table base here only for carrying iommu_group 19244617082eSAlexey Kardashevskiy * further down to let iommu_add_device() do the job. 19254617082eSAlexey Kardashevskiy * pnv_pci_ioda_dma_dev_setup will override it later anyway. 19264617082eSAlexey Kardashevskiy */ 19274617082eSAlexey Kardashevskiy set_iommu_table_base(&pe->pdev->dev, tbl); 19284617082eSAlexey Kardashevskiy iommu_add_device(&pe->pdev->dev); 1929c5773822SAlexey Kardashevskiy } else if (pe->flags & (PNV_IODA_PE_BUS | PNV_IODA_PE_BUS_ALL)) 1930ea30e99eSAlexey Kardashevskiy pnv_ioda_setup_bus_dma(pe, pe->pbus); 193174251fe2SBenjamin Herrenschmidt 1932184cd4a3SBenjamin Herrenschmidt return; 1933184cd4a3SBenjamin Herrenschmidt fail: 1934184cd4a3SBenjamin Herrenschmidt /* XXX Failure: Try to fallback to 64-bit only ? */ 1935184cd4a3SBenjamin Herrenschmidt if (pe->tce32_seg >= 0) 1936184cd4a3SBenjamin Herrenschmidt pe->tce32_seg = -1; 1937184cd4a3SBenjamin Herrenschmidt if (tce_mem) 1938184cd4a3SBenjamin Herrenschmidt __free_pages(tce_mem, get_order(TCE32_TABLE_SIZE * segs)); 19390eaf4defSAlexey Kardashevskiy if (tbl) { 19400eaf4defSAlexey Kardashevskiy pnv_pci_unlink_table_and_group(tbl, &pe->table_group); 19410eaf4defSAlexey Kardashevskiy iommu_free_table(tbl, "pnv"); 19420eaf4defSAlexey Kardashevskiy } 1943184cd4a3SBenjamin Herrenschmidt } 1944184cd4a3SBenjamin Herrenschmidt 194543cb60abSAlexey Kardashevskiy static long pnv_pci_ioda2_set_window(struct iommu_table_group *table_group, 194643cb60abSAlexey Kardashevskiy int num, struct iommu_table *tbl) 194743cb60abSAlexey Kardashevskiy { 194843cb60abSAlexey Kardashevskiy struct pnv_ioda_pe *pe = container_of(table_group, struct pnv_ioda_pe, 194943cb60abSAlexey Kardashevskiy table_group); 195043cb60abSAlexey Kardashevskiy struct pnv_phb *phb = pe->phb; 195143cb60abSAlexey Kardashevskiy int64_t rc; 1952bbb845c4SAlexey Kardashevskiy const unsigned long size = tbl->it_indirect_levels ? 1953bbb845c4SAlexey Kardashevskiy tbl->it_level_size : tbl->it_size; 195443cb60abSAlexey Kardashevskiy const __u64 start_addr = tbl->it_offset << tbl->it_page_shift; 195543cb60abSAlexey Kardashevskiy const __u64 win_size = tbl->it_size << tbl->it_page_shift; 195643cb60abSAlexey Kardashevskiy 19574793d65dSAlexey Kardashevskiy pe_info(pe, "Setting up window#%d %llx..%llx pg=%x\n", num, 195843cb60abSAlexey Kardashevskiy start_addr, start_addr + win_size - 1, 195943cb60abSAlexey Kardashevskiy IOMMU_PAGE_SIZE(tbl)); 196043cb60abSAlexey Kardashevskiy 196143cb60abSAlexey Kardashevskiy /* 196243cb60abSAlexey Kardashevskiy * Map TCE table through TVT. The TVE index is the PE number 196343cb60abSAlexey Kardashevskiy * shifted by 1 bit for 32-bits DMA space. 196443cb60abSAlexey Kardashevskiy */ 196543cb60abSAlexey Kardashevskiy rc = opal_pci_map_pe_dma_window(phb->opal_id, 196643cb60abSAlexey Kardashevskiy pe->pe_number, 19674793d65dSAlexey Kardashevskiy (pe->pe_number << 1) + num, 1968bbb845c4SAlexey Kardashevskiy tbl->it_indirect_levels + 1, 196943cb60abSAlexey Kardashevskiy __pa(tbl->it_base), 1970bbb845c4SAlexey Kardashevskiy size << 3, 197143cb60abSAlexey Kardashevskiy IOMMU_PAGE_SIZE(tbl)); 197243cb60abSAlexey Kardashevskiy if (rc) { 197343cb60abSAlexey Kardashevskiy pe_err(pe, "Failed to configure TCE table, err %ld\n", rc); 197443cb60abSAlexey Kardashevskiy return rc; 197543cb60abSAlexey Kardashevskiy } 197643cb60abSAlexey Kardashevskiy 197743cb60abSAlexey Kardashevskiy pnv_pci_link_table_and_group(phb->hose->node, num, 197843cb60abSAlexey Kardashevskiy tbl, &pe->table_group); 197943cb60abSAlexey Kardashevskiy pnv_pci_ioda2_tce_invalidate_entire(pe); 198043cb60abSAlexey Kardashevskiy 198143cb60abSAlexey Kardashevskiy return 0; 198243cb60abSAlexey Kardashevskiy } 198343cb60abSAlexey Kardashevskiy 1984f87a8864SAlexey Kardashevskiy static void pnv_pci_ioda2_set_bypass(struct pnv_ioda_pe *pe, bool enable) 1985cd15b048SBenjamin Herrenschmidt { 1986cd15b048SBenjamin Herrenschmidt uint16_t window_id = (pe->pe_number << 1 ) + 1; 1987cd15b048SBenjamin Herrenschmidt int64_t rc; 1988cd15b048SBenjamin Herrenschmidt 1989cd15b048SBenjamin Herrenschmidt pe_info(pe, "%sabling 64-bit DMA bypass\n", enable ? "En" : "Dis"); 1990cd15b048SBenjamin Herrenschmidt if (enable) { 1991cd15b048SBenjamin Herrenschmidt phys_addr_t top = memblock_end_of_DRAM(); 1992cd15b048SBenjamin Herrenschmidt 1993cd15b048SBenjamin Herrenschmidt top = roundup_pow_of_two(top); 1994cd15b048SBenjamin Herrenschmidt rc = opal_pci_map_pe_dma_window_real(pe->phb->opal_id, 1995cd15b048SBenjamin Herrenschmidt pe->pe_number, 1996cd15b048SBenjamin Herrenschmidt window_id, 1997cd15b048SBenjamin Herrenschmidt pe->tce_bypass_base, 1998cd15b048SBenjamin Herrenschmidt top); 1999cd15b048SBenjamin Herrenschmidt } else { 2000cd15b048SBenjamin Herrenschmidt rc = opal_pci_map_pe_dma_window_real(pe->phb->opal_id, 2001cd15b048SBenjamin Herrenschmidt pe->pe_number, 2002cd15b048SBenjamin Herrenschmidt window_id, 2003cd15b048SBenjamin Herrenschmidt pe->tce_bypass_base, 2004cd15b048SBenjamin Herrenschmidt 0); 2005cd15b048SBenjamin Herrenschmidt } 2006cd15b048SBenjamin Herrenschmidt if (rc) 2007cd15b048SBenjamin Herrenschmidt pe_err(pe, "OPAL error %lld configuring bypass window\n", rc); 2008cd15b048SBenjamin Herrenschmidt else 2009cd15b048SBenjamin Herrenschmidt pe->tce_bypass_enabled = enable; 2010cd15b048SBenjamin Herrenschmidt } 2011cd15b048SBenjamin Herrenschmidt 20124793d65dSAlexey Kardashevskiy static long pnv_pci_ioda2_table_alloc_pages(int nid, __u64 bus_offset, 20134793d65dSAlexey Kardashevskiy __u32 page_shift, __u64 window_size, __u32 levels, 20144793d65dSAlexey Kardashevskiy struct iommu_table *tbl); 20154793d65dSAlexey Kardashevskiy 20164793d65dSAlexey Kardashevskiy static long pnv_pci_ioda2_create_table(struct iommu_table_group *table_group, 20174793d65dSAlexey Kardashevskiy int num, __u32 page_shift, __u64 window_size, __u32 levels, 20184793d65dSAlexey Kardashevskiy struct iommu_table **ptbl) 20194793d65dSAlexey Kardashevskiy { 20204793d65dSAlexey Kardashevskiy struct pnv_ioda_pe *pe = container_of(table_group, struct pnv_ioda_pe, 20214793d65dSAlexey Kardashevskiy table_group); 20224793d65dSAlexey Kardashevskiy int nid = pe->phb->hose->node; 20234793d65dSAlexey Kardashevskiy __u64 bus_offset = num ? pe->tce_bypass_base : table_group->tce32_start; 20244793d65dSAlexey Kardashevskiy long ret; 20254793d65dSAlexey Kardashevskiy struct iommu_table *tbl; 20264793d65dSAlexey Kardashevskiy 20274793d65dSAlexey Kardashevskiy tbl = pnv_pci_table_alloc(nid); 20284793d65dSAlexey Kardashevskiy if (!tbl) 20294793d65dSAlexey Kardashevskiy return -ENOMEM; 20304793d65dSAlexey Kardashevskiy 20314793d65dSAlexey Kardashevskiy ret = pnv_pci_ioda2_table_alloc_pages(nid, 20324793d65dSAlexey Kardashevskiy bus_offset, page_shift, window_size, 20334793d65dSAlexey Kardashevskiy levels, tbl); 20344793d65dSAlexey Kardashevskiy if (ret) { 20354793d65dSAlexey Kardashevskiy iommu_free_table(tbl, "pnv"); 20364793d65dSAlexey Kardashevskiy return ret; 20374793d65dSAlexey Kardashevskiy } 20384793d65dSAlexey Kardashevskiy 20394793d65dSAlexey Kardashevskiy tbl->it_ops = &pnv_ioda2_iommu_ops; 20404793d65dSAlexey Kardashevskiy if (pe->phb->ioda.tce_inval_reg) 20414793d65dSAlexey Kardashevskiy tbl->it_type |= (TCE_PCI_SWINV_CREATE | TCE_PCI_SWINV_FREE); 20424793d65dSAlexey Kardashevskiy 20434793d65dSAlexey Kardashevskiy *ptbl = tbl; 20444793d65dSAlexey Kardashevskiy 20454793d65dSAlexey Kardashevskiy return 0; 20464793d65dSAlexey Kardashevskiy } 20474793d65dSAlexey Kardashevskiy 204846d3e1e1SAlexey Kardashevskiy static long pnv_pci_ioda2_setup_default_config(struct pnv_ioda_pe *pe) 204946d3e1e1SAlexey Kardashevskiy { 205046d3e1e1SAlexey Kardashevskiy struct iommu_table *tbl = NULL; 205146d3e1e1SAlexey Kardashevskiy long rc; 205246d3e1e1SAlexey Kardashevskiy 2053bb005455SNishanth Aravamudan /* 2054fa144869SNishanth Aravamudan * crashkernel= specifies the kdump kernel's maximum memory at 2055fa144869SNishanth Aravamudan * some offset and there is no guaranteed the result is a power 2056fa144869SNishanth Aravamudan * of 2, which will cause errors later. 2057fa144869SNishanth Aravamudan */ 2058fa144869SNishanth Aravamudan const u64 max_memory = __rounddown_pow_of_two(memory_hotplug_max()); 2059fa144869SNishanth Aravamudan 2060fa144869SNishanth Aravamudan /* 2061bb005455SNishanth Aravamudan * In memory constrained environments, e.g. kdump kernel, the 2062bb005455SNishanth Aravamudan * DMA window can be larger than available memory, which will 2063bb005455SNishanth Aravamudan * cause errors later. 2064bb005455SNishanth Aravamudan */ 2065fa144869SNishanth Aravamudan const u64 window_size = min((u64)pe->table_group.tce32_size, max_memory); 2066bb005455SNishanth Aravamudan 206746d3e1e1SAlexey Kardashevskiy rc = pnv_pci_ioda2_create_table(&pe->table_group, 0, 206846d3e1e1SAlexey Kardashevskiy IOMMU_PAGE_SHIFT_4K, 2069bb005455SNishanth Aravamudan window_size, 207046d3e1e1SAlexey Kardashevskiy POWERNV_IOMMU_DEFAULT_LEVELS, &tbl); 207146d3e1e1SAlexey Kardashevskiy if (rc) { 207246d3e1e1SAlexey Kardashevskiy pe_err(pe, "Failed to create 32-bit TCE table, err %ld", 207346d3e1e1SAlexey Kardashevskiy rc); 207446d3e1e1SAlexey Kardashevskiy return rc; 207546d3e1e1SAlexey Kardashevskiy } 207646d3e1e1SAlexey Kardashevskiy 207746d3e1e1SAlexey Kardashevskiy iommu_init_table(tbl, pe->phb->hose->node); 207846d3e1e1SAlexey Kardashevskiy 207946d3e1e1SAlexey Kardashevskiy rc = pnv_pci_ioda2_set_window(&pe->table_group, 0, tbl); 208046d3e1e1SAlexey Kardashevskiy if (rc) { 208146d3e1e1SAlexey Kardashevskiy pe_err(pe, "Failed to configure 32-bit TCE table, err %ld\n", 208246d3e1e1SAlexey Kardashevskiy rc); 208346d3e1e1SAlexey Kardashevskiy pnv_ioda2_table_free(tbl); 208446d3e1e1SAlexey Kardashevskiy return rc; 208546d3e1e1SAlexey Kardashevskiy } 208646d3e1e1SAlexey Kardashevskiy 208746d3e1e1SAlexey Kardashevskiy if (!pnv_iommu_bypass_disabled) 208846d3e1e1SAlexey Kardashevskiy pnv_pci_ioda2_set_bypass(pe, true); 208946d3e1e1SAlexey Kardashevskiy 209046d3e1e1SAlexey Kardashevskiy /* OPAL variant of PHB3 invalidated TCEs */ 209146d3e1e1SAlexey Kardashevskiy if (pe->phb->ioda.tce_inval_reg) 209246d3e1e1SAlexey Kardashevskiy tbl->it_type |= (TCE_PCI_SWINV_CREATE | TCE_PCI_SWINV_FREE); 209346d3e1e1SAlexey Kardashevskiy 209446d3e1e1SAlexey Kardashevskiy /* 209546d3e1e1SAlexey Kardashevskiy * Setting table base here only for carrying iommu_group 209646d3e1e1SAlexey Kardashevskiy * further down to let iommu_add_device() do the job. 209746d3e1e1SAlexey Kardashevskiy * pnv_pci_ioda_dma_dev_setup will override it later anyway. 209846d3e1e1SAlexey Kardashevskiy */ 209946d3e1e1SAlexey Kardashevskiy if (pe->flags & PNV_IODA_PE_DEV) 210046d3e1e1SAlexey Kardashevskiy set_iommu_table_base(&pe->pdev->dev, tbl); 210146d3e1e1SAlexey Kardashevskiy 210246d3e1e1SAlexey Kardashevskiy return 0; 210346d3e1e1SAlexey Kardashevskiy } 210446d3e1e1SAlexey Kardashevskiy 2105b5926430SAlexey Kardashevskiy #if defined(CONFIG_IOMMU_API) || defined(CONFIG_PCI_IOV) 2106b5926430SAlexey Kardashevskiy static long pnv_pci_ioda2_unset_window(struct iommu_table_group *table_group, 2107b5926430SAlexey Kardashevskiy int num) 2108b5926430SAlexey Kardashevskiy { 2109b5926430SAlexey Kardashevskiy struct pnv_ioda_pe *pe = container_of(table_group, struct pnv_ioda_pe, 2110b5926430SAlexey Kardashevskiy table_group); 2111b5926430SAlexey Kardashevskiy struct pnv_phb *phb = pe->phb; 2112b5926430SAlexey Kardashevskiy long ret; 2113b5926430SAlexey Kardashevskiy 2114b5926430SAlexey Kardashevskiy pe_info(pe, "Removing DMA window #%d\n", num); 2115b5926430SAlexey Kardashevskiy 2116b5926430SAlexey Kardashevskiy ret = opal_pci_map_pe_dma_window(phb->opal_id, pe->pe_number, 2117b5926430SAlexey Kardashevskiy (pe->pe_number << 1) + num, 2118b5926430SAlexey Kardashevskiy 0/* levels */, 0/* table address */, 2119b5926430SAlexey Kardashevskiy 0/* table size */, 0/* page size */); 2120b5926430SAlexey Kardashevskiy if (ret) 2121b5926430SAlexey Kardashevskiy pe_warn(pe, "Unmapping failed, ret = %ld\n", ret); 2122b5926430SAlexey Kardashevskiy else 2123b5926430SAlexey Kardashevskiy pnv_pci_ioda2_tce_invalidate_entire(pe); 2124b5926430SAlexey Kardashevskiy 2125b5926430SAlexey Kardashevskiy pnv_pci_unlink_table_and_group(table_group->tables[num], table_group); 2126b5926430SAlexey Kardashevskiy 2127b5926430SAlexey Kardashevskiy return ret; 2128b5926430SAlexey Kardashevskiy } 2129b5926430SAlexey Kardashevskiy #endif 2130b5926430SAlexey Kardashevskiy 2131f87a8864SAlexey Kardashevskiy #ifdef CONFIG_IOMMU_API 213200547193SAlexey Kardashevskiy static unsigned long pnv_pci_ioda2_get_table_size(__u32 page_shift, 213300547193SAlexey Kardashevskiy __u64 window_size, __u32 levels) 213400547193SAlexey Kardashevskiy { 213500547193SAlexey Kardashevskiy unsigned long bytes = 0; 213600547193SAlexey Kardashevskiy const unsigned window_shift = ilog2(window_size); 213700547193SAlexey Kardashevskiy unsigned entries_shift = window_shift - page_shift; 213800547193SAlexey Kardashevskiy unsigned table_shift = entries_shift + 3; 213900547193SAlexey Kardashevskiy unsigned long tce_table_size = max(0x1000UL, 1UL << table_shift); 214000547193SAlexey Kardashevskiy unsigned long direct_table_size; 214100547193SAlexey Kardashevskiy 214200547193SAlexey Kardashevskiy if (!levels || (levels > POWERNV_IOMMU_MAX_LEVELS) || 214300547193SAlexey Kardashevskiy (window_size > memory_hotplug_max()) || 214400547193SAlexey Kardashevskiy !is_power_of_2(window_size)) 214500547193SAlexey Kardashevskiy return 0; 214600547193SAlexey Kardashevskiy 214700547193SAlexey Kardashevskiy /* Calculate a direct table size from window_size and levels */ 214800547193SAlexey Kardashevskiy entries_shift = (entries_shift + levels - 1) / levels; 214900547193SAlexey Kardashevskiy table_shift = entries_shift + 3; 215000547193SAlexey Kardashevskiy table_shift = max_t(unsigned, table_shift, PAGE_SHIFT); 215100547193SAlexey Kardashevskiy direct_table_size = 1UL << table_shift; 215200547193SAlexey Kardashevskiy 215300547193SAlexey Kardashevskiy for ( ; levels; --levels) { 215400547193SAlexey Kardashevskiy bytes += _ALIGN_UP(tce_table_size, direct_table_size); 215500547193SAlexey Kardashevskiy 215600547193SAlexey Kardashevskiy tce_table_size /= direct_table_size; 215700547193SAlexey Kardashevskiy tce_table_size <<= 3; 215800547193SAlexey Kardashevskiy tce_table_size = _ALIGN_UP(tce_table_size, direct_table_size); 215900547193SAlexey Kardashevskiy } 216000547193SAlexey Kardashevskiy 216100547193SAlexey Kardashevskiy return bytes; 216200547193SAlexey Kardashevskiy } 216300547193SAlexey Kardashevskiy 2164f87a8864SAlexey Kardashevskiy static void pnv_ioda2_take_ownership(struct iommu_table_group *table_group) 2165cd15b048SBenjamin Herrenschmidt { 2166f87a8864SAlexey Kardashevskiy struct pnv_ioda_pe *pe = container_of(table_group, struct pnv_ioda_pe, 2167f87a8864SAlexey Kardashevskiy table_group); 216846d3e1e1SAlexey Kardashevskiy /* Store @tbl as pnv_pci_ioda2_unset_window() resets it */ 216946d3e1e1SAlexey Kardashevskiy struct iommu_table *tbl = pe->table_group.tables[0]; 2170cd15b048SBenjamin Herrenschmidt 2171f87a8864SAlexey Kardashevskiy pnv_pci_ioda2_set_bypass(pe, false); 217246d3e1e1SAlexey Kardashevskiy pnv_pci_ioda2_unset_window(&pe->table_group, 0); 217346d3e1e1SAlexey Kardashevskiy pnv_ioda2_table_free(tbl); 2174cd15b048SBenjamin Herrenschmidt } 2175cd15b048SBenjamin Herrenschmidt 2176f87a8864SAlexey Kardashevskiy static void pnv_ioda2_release_ownership(struct iommu_table_group *table_group) 2177f87a8864SAlexey Kardashevskiy { 2178f87a8864SAlexey Kardashevskiy struct pnv_ioda_pe *pe = container_of(table_group, struct pnv_ioda_pe, 2179f87a8864SAlexey Kardashevskiy table_group); 2180f87a8864SAlexey Kardashevskiy 218146d3e1e1SAlexey Kardashevskiy pnv_pci_ioda2_setup_default_config(pe); 2182f87a8864SAlexey Kardashevskiy } 2183f87a8864SAlexey Kardashevskiy 2184f87a8864SAlexey Kardashevskiy static struct iommu_table_group_ops pnv_pci_ioda2_ops = { 218500547193SAlexey Kardashevskiy .get_table_size = pnv_pci_ioda2_get_table_size, 21864793d65dSAlexey Kardashevskiy .create_table = pnv_pci_ioda2_create_table, 21874793d65dSAlexey Kardashevskiy .set_window = pnv_pci_ioda2_set_window, 21884793d65dSAlexey Kardashevskiy .unset_window = pnv_pci_ioda2_unset_window, 2189f87a8864SAlexey Kardashevskiy .take_ownership = pnv_ioda2_take_ownership, 2190f87a8864SAlexey Kardashevskiy .release_ownership = pnv_ioda2_release_ownership, 2191f87a8864SAlexey Kardashevskiy }; 2192f87a8864SAlexey Kardashevskiy #endif 2193f87a8864SAlexey Kardashevskiy 21945780fb04SAlexey Kardashevskiy static void pnv_pci_ioda_setup_opal_tce_kill(struct pnv_phb *phb) 21955780fb04SAlexey Kardashevskiy { 21965780fb04SAlexey Kardashevskiy const __be64 *swinvp; 21975780fb04SAlexey Kardashevskiy 21985780fb04SAlexey Kardashevskiy /* OPAL variant of PHB3 invalidated TCEs */ 21995780fb04SAlexey Kardashevskiy swinvp = of_get_property(phb->hose->dn, "ibm,opal-tce-kill", NULL); 22005780fb04SAlexey Kardashevskiy if (!swinvp) 22015780fb04SAlexey Kardashevskiy return; 22025780fb04SAlexey Kardashevskiy 22035780fb04SAlexey Kardashevskiy phb->ioda.tce_inval_reg_phys = be64_to_cpup(swinvp); 22045780fb04SAlexey Kardashevskiy phb->ioda.tce_inval_reg = ioremap(phb->ioda.tce_inval_reg_phys, 8); 22055780fb04SAlexey Kardashevskiy } 22065780fb04SAlexey Kardashevskiy 2207bbb845c4SAlexey Kardashevskiy static __be64 *pnv_pci_ioda2_table_do_alloc_pages(int nid, unsigned shift, 2208bbb845c4SAlexey Kardashevskiy unsigned levels, unsigned long limit, 22093ba3a73eSAlexey Kardashevskiy unsigned long *current_offset, unsigned long *total_allocated) 2210aca6913fSAlexey Kardashevskiy { 2211aca6913fSAlexey Kardashevskiy struct page *tce_mem = NULL; 2212bbb845c4SAlexey Kardashevskiy __be64 *addr, *tmp; 2213aca6913fSAlexey Kardashevskiy unsigned order = max_t(unsigned, shift, PAGE_SHIFT) - PAGE_SHIFT; 2214bbb845c4SAlexey Kardashevskiy unsigned long allocated = 1UL << (order + PAGE_SHIFT); 2215bbb845c4SAlexey Kardashevskiy unsigned entries = 1UL << (shift - 3); 2216bbb845c4SAlexey Kardashevskiy long i; 2217aca6913fSAlexey Kardashevskiy 2218aca6913fSAlexey Kardashevskiy tce_mem = alloc_pages_node(nid, GFP_KERNEL, order); 2219aca6913fSAlexey Kardashevskiy if (!tce_mem) { 2220aca6913fSAlexey Kardashevskiy pr_err("Failed to allocate a TCE memory, order=%d\n", order); 2221aca6913fSAlexey Kardashevskiy return NULL; 2222aca6913fSAlexey Kardashevskiy } 2223aca6913fSAlexey Kardashevskiy addr = page_address(tce_mem); 2224bbb845c4SAlexey Kardashevskiy memset(addr, 0, allocated); 22253ba3a73eSAlexey Kardashevskiy *total_allocated += allocated; 2226bbb845c4SAlexey Kardashevskiy 2227bbb845c4SAlexey Kardashevskiy --levels; 2228bbb845c4SAlexey Kardashevskiy if (!levels) { 2229bbb845c4SAlexey Kardashevskiy *current_offset += allocated; 2230bbb845c4SAlexey Kardashevskiy return addr; 2231bbb845c4SAlexey Kardashevskiy } 2232bbb845c4SAlexey Kardashevskiy 2233bbb845c4SAlexey Kardashevskiy for (i = 0; i < entries; ++i) { 2234bbb845c4SAlexey Kardashevskiy tmp = pnv_pci_ioda2_table_do_alloc_pages(nid, shift, 22353ba3a73eSAlexey Kardashevskiy levels, limit, current_offset, total_allocated); 2236bbb845c4SAlexey Kardashevskiy if (!tmp) 2237bbb845c4SAlexey Kardashevskiy break; 2238bbb845c4SAlexey Kardashevskiy 2239bbb845c4SAlexey Kardashevskiy addr[i] = cpu_to_be64(__pa(tmp) | 2240bbb845c4SAlexey Kardashevskiy TCE_PCI_READ | TCE_PCI_WRITE); 2241bbb845c4SAlexey Kardashevskiy 2242bbb845c4SAlexey Kardashevskiy if (*current_offset >= limit) 2243bbb845c4SAlexey Kardashevskiy break; 2244bbb845c4SAlexey Kardashevskiy } 2245aca6913fSAlexey Kardashevskiy 2246aca6913fSAlexey Kardashevskiy return addr; 2247aca6913fSAlexey Kardashevskiy } 2248aca6913fSAlexey Kardashevskiy 2249bbb845c4SAlexey Kardashevskiy static void pnv_pci_ioda2_table_do_free_pages(__be64 *addr, 2250bbb845c4SAlexey Kardashevskiy unsigned long size, unsigned level); 2251bbb845c4SAlexey Kardashevskiy 2252aca6913fSAlexey Kardashevskiy static long pnv_pci_ioda2_table_alloc_pages(int nid, __u64 bus_offset, 2253bbb845c4SAlexey Kardashevskiy __u32 page_shift, __u64 window_size, __u32 levels, 2254bbb845c4SAlexey Kardashevskiy struct iommu_table *tbl) 2255aca6913fSAlexey Kardashevskiy { 2256aca6913fSAlexey Kardashevskiy void *addr; 22573ba3a73eSAlexey Kardashevskiy unsigned long offset = 0, level_shift, total_allocated = 0; 2258aca6913fSAlexey Kardashevskiy const unsigned window_shift = ilog2(window_size); 2259aca6913fSAlexey Kardashevskiy unsigned entries_shift = window_shift - page_shift; 2260aca6913fSAlexey Kardashevskiy unsigned table_shift = max_t(unsigned, entries_shift + 3, PAGE_SHIFT); 2261aca6913fSAlexey Kardashevskiy const unsigned long tce_table_size = 1UL << table_shift; 2262aca6913fSAlexey Kardashevskiy 2263bbb845c4SAlexey Kardashevskiy if (!levels || (levels > POWERNV_IOMMU_MAX_LEVELS)) 2264bbb845c4SAlexey Kardashevskiy return -EINVAL; 2265bbb845c4SAlexey Kardashevskiy 2266aca6913fSAlexey Kardashevskiy if ((window_size > memory_hotplug_max()) || !is_power_of_2(window_size)) 2267aca6913fSAlexey Kardashevskiy return -EINVAL; 2268aca6913fSAlexey Kardashevskiy 2269bbb845c4SAlexey Kardashevskiy /* Adjust direct table size from window_size and levels */ 2270bbb845c4SAlexey Kardashevskiy entries_shift = (entries_shift + levels - 1) / levels; 2271bbb845c4SAlexey Kardashevskiy level_shift = entries_shift + 3; 2272bbb845c4SAlexey Kardashevskiy level_shift = max_t(unsigned, level_shift, PAGE_SHIFT); 2273bbb845c4SAlexey Kardashevskiy 2274aca6913fSAlexey Kardashevskiy /* Allocate TCE table */ 2275bbb845c4SAlexey Kardashevskiy addr = pnv_pci_ioda2_table_do_alloc_pages(nid, level_shift, 22763ba3a73eSAlexey Kardashevskiy levels, tce_table_size, &offset, &total_allocated); 2277bbb845c4SAlexey Kardashevskiy 2278bbb845c4SAlexey Kardashevskiy /* addr==NULL means that the first level allocation failed */ 2279aca6913fSAlexey Kardashevskiy if (!addr) 2280aca6913fSAlexey Kardashevskiy return -ENOMEM; 2281aca6913fSAlexey Kardashevskiy 2282bbb845c4SAlexey Kardashevskiy /* 2283bbb845c4SAlexey Kardashevskiy * First level was allocated but some lower level failed as 2284bbb845c4SAlexey Kardashevskiy * we did not allocate as much as we wanted, 2285bbb845c4SAlexey Kardashevskiy * release partially allocated table. 2286bbb845c4SAlexey Kardashevskiy */ 2287bbb845c4SAlexey Kardashevskiy if (offset < tce_table_size) { 2288bbb845c4SAlexey Kardashevskiy pnv_pci_ioda2_table_do_free_pages(addr, 2289bbb845c4SAlexey Kardashevskiy 1ULL << (level_shift - 3), levels - 1); 2290bbb845c4SAlexey Kardashevskiy return -ENOMEM; 2291bbb845c4SAlexey Kardashevskiy } 2292bbb845c4SAlexey Kardashevskiy 2293aca6913fSAlexey Kardashevskiy /* Setup linux iommu table */ 2294aca6913fSAlexey Kardashevskiy pnv_pci_setup_iommu_table(tbl, addr, tce_table_size, bus_offset, 2295aca6913fSAlexey Kardashevskiy page_shift); 2296bbb845c4SAlexey Kardashevskiy tbl->it_level_size = 1ULL << (level_shift - 3); 2297bbb845c4SAlexey Kardashevskiy tbl->it_indirect_levels = levels - 1; 22983ba3a73eSAlexey Kardashevskiy tbl->it_allocated_size = total_allocated; 2299aca6913fSAlexey Kardashevskiy 2300aca6913fSAlexey Kardashevskiy pr_devel("Created TCE table: ws=%08llx ts=%lx @%08llx\n", 2301aca6913fSAlexey Kardashevskiy window_size, tce_table_size, bus_offset); 2302aca6913fSAlexey Kardashevskiy 2303aca6913fSAlexey Kardashevskiy return 0; 2304aca6913fSAlexey Kardashevskiy } 2305aca6913fSAlexey Kardashevskiy 2306bbb845c4SAlexey Kardashevskiy static void pnv_pci_ioda2_table_do_free_pages(__be64 *addr, 2307bbb845c4SAlexey Kardashevskiy unsigned long size, unsigned level) 2308bbb845c4SAlexey Kardashevskiy { 2309bbb845c4SAlexey Kardashevskiy const unsigned long addr_ul = (unsigned long) addr & 2310bbb845c4SAlexey Kardashevskiy ~(TCE_PCI_READ | TCE_PCI_WRITE); 2311bbb845c4SAlexey Kardashevskiy 2312bbb845c4SAlexey Kardashevskiy if (level) { 2313bbb845c4SAlexey Kardashevskiy long i; 2314bbb845c4SAlexey Kardashevskiy u64 *tmp = (u64 *) addr_ul; 2315bbb845c4SAlexey Kardashevskiy 2316bbb845c4SAlexey Kardashevskiy for (i = 0; i < size; ++i) { 2317bbb845c4SAlexey Kardashevskiy unsigned long hpa = be64_to_cpu(tmp[i]); 2318bbb845c4SAlexey Kardashevskiy 2319bbb845c4SAlexey Kardashevskiy if (!(hpa & (TCE_PCI_READ | TCE_PCI_WRITE))) 2320bbb845c4SAlexey Kardashevskiy continue; 2321bbb845c4SAlexey Kardashevskiy 2322bbb845c4SAlexey Kardashevskiy pnv_pci_ioda2_table_do_free_pages(__va(hpa), size, 2323bbb845c4SAlexey Kardashevskiy level - 1); 2324bbb845c4SAlexey Kardashevskiy } 2325bbb845c4SAlexey Kardashevskiy } 2326bbb845c4SAlexey Kardashevskiy 2327bbb845c4SAlexey Kardashevskiy free_pages(addr_ul, get_order(size << 3)); 2328bbb845c4SAlexey Kardashevskiy } 2329bbb845c4SAlexey Kardashevskiy 2330aca6913fSAlexey Kardashevskiy static void pnv_pci_ioda2_table_free_pages(struct iommu_table *tbl) 2331aca6913fSAlexey Kardashevskiy { 2332bbb845c4SAlexey Kardashevskiy const unsigned long size = tbl->it_indirect_levels ? 2333bbb845c4SAlexey Kardashevskiy tbl->it_level_size : tbl->it_size; 2334bbb845c4SAlexey Kardashevskiy 2335aca6913fSAlexey Kardashevskiy if (!tbl->it_size) 2336aca6913fSAlexey Kardashevskiy return; 2337aca6913fSAlexey Kardashevskiy 2338bbb845c4SAlexey Kardashevskiy pnv_pci_ioda2_table_do_free_pages((__be64 *)tbl->it_base, size, 2339bbb845c4SAlexey Kardashevskiy tbl->it_indirect_levels); 2340aca6913fSAlexey Kardashevskiy } 2341aca6913fSAlexey Kardashevskiy 2342373f5657SGavin Shan static void pnv_pci_ioda2_setup_dma_pe(struct pnv_phb *phb, 2343373f5657SGavin Shan struct pnv_ioda_pe *pe) 2344373f5657SGavin Shan { 2345373f5657SGavin Shan int64_t rc; 2346373f5657SGavin Shan 2347373f5657SGavin Shan /* We shouldn't already have a 32-bit DMA associated */ 2348373f5657SGavin Shan if (WARN_ON(pe->tce32_seg >= 0)) 2349373f5657SGavin Shan return; 2350373f5657SGavin Shan 2351f87a8864SAlexey Kardashevskiy /* TVE #1 is selected by PCI address bit 59 */ 2352f87a8864SAlexey Kardashevskiy pe->tce_bypass_base = 1ull << 59; 2353f87a8864SAlexey Kardashevskiy 2354b348aa65SAlexey Kardashevskiy iommu_register_group(&pe->table_group, phb->hose->global_number, 2355b348aa65SAlexey Kardashevskiy pe->pe_number); 2356c5773822SAlexey Kardashevskiy 2357373f5657SGavin Shan /* The PE will reserve all possible 32-bits space */ 2358373f5657SGavin Shan pe->tce32_seg = 0; 2359373f5657SGavin Shan pe_info(pe, "Setting up 32-bit TCE table at 0..%08x\n", 2360aca6913fSAlexey Kardashevskiy phb->ioda.m32_pci_base); 2361373f5657SGavin Shan 2362e5aad1e6SAlexey Kardashevskiy /* Setup linux iommu table */ 23634793d65dSAlexey Kardashevskiy pe->table_group.tce32_start = 0; 23644793d65dSAlexey Kardashevskiy pe->table_group.tce32_size = phb->ioda.m32_pci_base; 23654793d65dSAlexey Kardashevskiy pe->table_group.max_dynamic_windows_supported = 23664793d65dSAlexey Kardashevskiy IOMMU_TABLE_GROUP_MAX_TABLES; 23674793d65dSAlexey Kardashevskiy pe->table_group.max_levels = POWERNV_IOMMU_MAX_LEVELS; 23684793d65dSAlexey Kardashevskiy pe->table_group.pgsizes = SZ_4K | SZ_64K | SZ_16M; 2369e5aad1e6SAlexey Kardashevskiy #ifdef CONFIG_IOMMU_API 2370e5aad1e6SAlexey Kardashevskiy pe->table_group.ops = &pnv_pci_ioda2_ops; 2371e5aad1e6SAlexey Kardashevskiy #endif 2372e5aad1e6SAlexey Kardashevskiy 237346d3e1e1SAlexey Kardashevskiy rc = pnv_pci_ioda2_setup_default_config(pe); 2374373f5657SGavin Shan if (rc) { 2375373f5657SGavin Shan if (pe->tce32_seg >= 0) 2376373f5657SGavin Shan pe->tce32_seg = -1; 237746d3e1e1SAlexey Kardashevskiy return; 23780eaf4defSAlexey Kardashevskiy } 237946d3e1e1SAlexey Kardashevskiy 238046d3e1e1SAlexey Kardashevskiy if (pe->flags & PNV_IODA_PE_DEV) 238146d3e1e1SAlexey Kardashevskiy iommu_add_device(&pe->pdev->dev); 238246d3e1e1SAlexey Kardashevskiy else if (pe->flags & (PNV_IODA_PE_BUS | PNV_IODA_PE_BUS_ALL)) 238346d3e1e1SAlexey Kardashevskiy pnv_ioda_setup_bus_dma(pe, pe->pbus); 2384373f5657SGavin Shan } 2385373f5657SGavin Shan 2386cad5cef6SGreg Kroah-Hartman static void pnv_ioda_setup_dma(struct pnv_phb *phb) 2387184cd4a3SBenjamin Herrenschmidt { 2388184cd4a3SBenjamin Herrenschmidt struct pci_controller *hose = phb->hose; 2389184cd4a3SBenjamin Herrenschmidt unsigned int residual, remaining, segs, tw, base; 2390184cd4a3SBenjamin Herrenschmidt struct pnv_ioda_pe *pe; 2391184cd4a3SBenjamin Herrenschmidt 2392184cd4a3SBenjamin Herrenschmidt /* If we have more PE# than segments available, hand out one 2393184cd4a3SBenjamin Herrenschmidt * per PE until we run out and let the rest fail. If not, 2394184cd4a3SBenjamin Herrenschmidt * then we assign at least one segment per PE, plus more based 2395184cd4a3SBenjamin Herrenschmidt * on the amount of devices under that PE 2396184cd4a3SBenjamin Herrenschmidt */ 2397184cd4a3SBenjamin Herrenschmidt if (phb->ioda.dma_pe_count > phb->ioda.tce32_count) 2398184cd4a3SBenjamin Herrenschmidt residual = 0; 2399184cd4a3SBenjamin Herrenschmidt else 2400184cd4a3SBenjamin Herrenschmidt residual = phb->ioda.tce32_count - 2401184cd4a3SBenjamin Herrenschmidt phb->ioda.dma_pe_count; 2402184cd4a3SBenjamin Herrenschmidt 2403184cd4a3SBenjamin Herrenschmidt pr_info("PCI: Domain %04x has %ld available 32-bit DMA segments\n", 2404184cd4a3SBenjamin Herrenschmidt hose->global_number, phb->ioda.tce32_count); 2405184cd4a3SBenjamin Herrenschmidt pr_info("PCI: %d PE# for a total weight of %d\n", 2406184cd4a3SBenjamin Herrenschmidt phb->ioda.dma_pe_count, phb->ioda.dma_weight); 2407184cd4a3SBenjamin Herrenschmidt 24085780fb04SAlexey Kardashevskiy pnv_pci_ioda_setup_opal_tce_kill(phb); 24095780fb04SAlexey Kardashevskiy 2410184cd4a3SBenjamin Herrenschmidt /* Walk our PE list and configure their DMA segments, hand them 2411184cd4a3SBenjamin Herrenschmidt * out one base segment plus any residual segments based on 2412184cd4a3SBenjamin Herrenschmidt * weight 2413184cd4a3SBenjamin Herrenschmidt */ 2414184cd4a3SBenjamin Herrenschmidt remaining = phb->ioda.tce32_count; 2415184cd4a3SBenjamin Herrenschmidt tw = phb->ioda.dma_weight; 2416184cd4a3SBenjamin Herrenschmidt base = 0; 24177ebdf956SGavin Shan list_for_each_entry(pe, &phb->ioda.pe_dma_list, dma_link) { 2418184cd4a3SBenjamin Herrenschmidt if (!pe->dma_weight) 2419184cd4a3SBenjamin Herrenschmidt continue; 2420184cd4a3SBenjamin Herrenschmidt if (!remaining) { 2421184cd4a3SBenjamin Herrenschmidt pe_warn(pe, "No DMA32 resources available\n"); 2422184cd4a3SBenjamin Herrenschmidt continue; 2423184cd4a3SBenjamin Herrenschmidt } 2424184cd4a3SBenjamin Herrenschmidt segs = 1; 2425184cd4a3SBenjamin Herrenschmidt if (residual) { 2426184cd4a3SBenjamin Herrenschmidt segs += ((pe->dma_weight * residual) + (tw / 2)) / tw; 2427184cd4a3SBenjamin Herrenschmidt if (segs > remaining) 2428184cd4a3SBenjamin Herrenschmidt segs = remaining; 2429184cd4a3SBenjamin Herrenschmidt } 2430373f5657SGavin Shan 2431373f5657SGavin Shan /* 2432373f5657SGavin Shan * For IODA2 compliant PHB3, we needn't care about the weight. 2433373f5657SGavin Shan * The all available 32-bits DMA space will be assigned to 2434373f5657SGavin Shan * the specific PE. 2435373f5657SGavin Shan */ 2436373f5657SGavin Shan if (phb->type == PNV_PHB_IODA1) { 2437184cd4a3SBenjamin Herrenschmidt pe_info(pe, "DMA weight %d, assigned %d DMA32 segments\n", 2438184cd4a3SBenjamin Herrenschmidt pe->dma_weight, segs); 2439184cd4a3SBenjamin Herrenschmidt pnv_pci_ioda_setup_dma_pe(phb, pe, base, segs); 2440373f5657SGavin Shan } else { 2441373f5657SGavin Shan pe_info(pe, "Assign DMA32 space\n"); 2442373f5657SGavin Shan segs = 0; 2443373f5657SGavin Shan pnv_pci_ioda2_setup_dma_pe(phb, pe); 2444373f5657SGavin Shan } 2445373f5657SGavin Shan 2446184cd4a3SBenjamin Herrenschmidt remaining -= segs; 2447184cd4a3SBenjamin Herrenschmidt base += segs; 2448184cd4a3SBenjamin Herrenschmidt } 2449184cd4a3SBenjamin Herrenschmidt } 2450184cd4a3SBenjamin Herrenschmidt 2451184cd4a3SBenjamin Herrenschmidt #ifdef CONFIG_PCI_MSI 2452137436c9SGavin Shan static void pnv_ioda2_msi_eoi(struct irq_data *d) 2453137436c9SGavin Shan { 2454137436c9SGavin Shan unsigned int hw_irq = (unsigned int)irqd_to_hwirq(d); 2455137436c9SGavin Shan struct irq_chip *chip = irq_data_get_irq_chip(d); 2456137436c9SGavin Shan struct pnv_phb *phb = container_of(chip, struct pnv_phb, 2457137436c9SGavin Shan ioda.irq_chip); 2458137436c9SGavin Shan int64_t rc; 2459137436c9SGavin Shan 2460137436c9SGavin Shan rc = opal_pci_msi_eoi(phb->opal_id, hw_irq); 2461137436c9SGavin Shan WARN_ON_ONCE(rc); 2462137436c9SGavin Shan 2463137436c9SGavin Shan icp_native_eoi(d); 2464137436c9SGavin Shan } 2465137436c9SGavin Shan 2466fd9a1c26SIan Munsie 2467fd9a1c26SIan Munsie static void set_msi_irq_chip(struct pnv_phb *phb, unsigned int virq) 2468fd9a1c26SIan Munsie { 2469fd9a1c26SIan Munsie struct irq_data *idata; 2470fd9a1c26SIan Munsie struct irq_chip *ichip; 2471fd9a1c26SIan Munsie 2472fd9a1c26SIan Munsie if (phb->type != PNV_PHB_IODA2) 2473fd9a1c26SIan Munsie return; 2474fd9a1c26SIan Munsie 2475fd9a1c26SIan Munsie if (!phb->ioda.irq_chip_init) { 2476fd9a1c26SIan Munsie /* 2477fd9a1c26SIan Munsie * First time we setup an MSI IRQ, we need to setup the 2478fd9a1c26SIan Munsie * corresponding IRQ chip to route correctly. 2479fd9a1c26SIan Munsie */ 2480fd9a1c26SIan Munsie idata = irq_get_irq_data(virq); 2481fd9a1c26SIan Munsie ichip = irq_data_get_irq_chip(idata); 2482fd9a1c26SIan Munsie phb->ioda.irq_chip_init = 1; 2483fd9a1c26SIan Munsie phb->ioda.irq_chip = *ichip; 2484fd9a1c26SIan Munsie phb->ioda.irq_chip.irq_eoi = pnv_ioda2_msi_eoi; 2485fd9a1c26SIan Munsie } 2486fd9a1c26SIan Munsie irq_set_chip(virq, &phb->ioda.irq_chip); 2487fd9a1c26SIan Munsie } 2488fd9a1c26SIan Munsie 248980c49c7eSIan Munsie #ifdef CONFIG_CXL_BASE 249080c49c7eSIan Munsie 24916f963ec2SRyan Grimm struct device_node *pnv_pci_get_phb_node(struct pci_dev *dev) 249280c49c7eSIan Munsie { 249380c49c7eSIan Munsie struct pci_controller *hose = pci_bus_to_host(dev->bus); 249480c49c7eSIan Munsie 24956f963ec2SRyan Grimm return of_node_get(hose->dn); 249680c49c7eSIan Munsie } 24976f963ec2SRyan Grimm EXPORT_SYMBOL(pnv_pci_get_phb_node); 249880c49c7eSIan Munsie 24991212aa1cSRyan Grimm int pnv_phb_to_cxl_mode(struct pci_dev *dev, uint64_t mode) 250080c49c7eSIan Munsie { 250180c49c7eSIan Munsie struct pci_controller *hose = pci_bus_to_host(dev->bus); 250280c49c7eSIan Munsie struct pnv_phb *phb = hose->private_data; 250380c49c7eSIan Munsie struct pnv_ioda_pe *pe; 250480c49c7eSIan Munsie int rc; 250580c49c7eSIan Munsie 250680c49c7eSIan Munsie pe = pnv_ioda_get_pe(dev); 250780c49c7eSIan Munsie if (!pe) 250880c49c7eSIan Munsie return -ENODEV; 250980c49c7eSIan Munsie 251080c49c7eSIan Munsie pe_info(pe, "Switching PHB to CXL\n"); 251180c49c7eSIan Munsie 25121212aa1cSRyan Grimm rc = opal_pci_set_phb_cxl_mode(phb->opal_id, mode, pe->pe_number); 251380c49c7eSIan Munsie if (rc) 251480c49c7eSIan Munsie dev_err(&dev->dev, "opal_pci_set_phb_cxl_mode failed: %i\n", rc); 251580c49c7eSIan Munsie 251680c49c7eSIan Munsie return rc; 251780c49c7eSIan Munsie } 25181212aa1cSRyan Grimm EXPORT_SYMBOL(pnv_phb_to_cxl_mode); 251980c49c7eSIan Munsie 252080c49c7eSIan Munsie /* Find PHB for cxl dev and allocate MSI hwirqs? 252180c49c7eSIan Munsie * Returns the absolute hardware IRQ number 252280c49c7eSIan Munsie */ 252380c49c7eSIan Munsie int pnv_cxl_alloc_hwirqs(struct pci_dev *dev, int num) 252480c49c7eSIan Munsie { 252580c49c7eSIan Munsie struct pci_controller *hose = pci_bus_to_host(dev->bus); 252680c49c7eSIan Munsie struct pnv_phb *phb = hose->private_data; 252780c49c7eSIan Munsie int hwirq = msi_bitmap_alloc_hwirqs(&phb->msi_bmp, num); 252880c49c7eSIan Munsie 252980c49c7eSIan Munsie if (hwirq < 0) { 253080c49c7eSIan Munsie dev_warn(&dev->dev, "Failed to find a free MSI\n"); 253180c49c7eSIan Munsie return -ENOSPC; 253280c49c7eSIan Munsie } 253380c49c7eSIan Munsie 253480c49c7eSIan Munsie return phb->msi_base + hwirq; 253580c49c7eSIan Munsie } 253680c49c7eSIan Munsie EXPORT_SYMBOL(pnv_cxl_alloc_hwirqs); 253780c49c7eSIan Munsie 253880c49c7eSIan Munsie void pnv_cxl_release_hwirqs(struct pci_dev *dev, int hwirq, int num) 253980c49c7eSIan Munsie { 254080c49c7eSIan Munsie struct pci_controller *hose = pci_bus_to_host(dev->bus); 254180c49c7eSIan Munsie struct pnv_phb *phb = hose->private_data; 254280c49c7eSIan Munsie 254380c49c7eSIan Munsie msi_bitmap_free_hwirqs(&phb->msi_bmp, hwirq - phb->msi_base, num); 254480c49c7eSIan Munsie } 254580c49c7eSIan Munsie EXPORT_SYMBOL(pnv_cxl_release_hwirqs); 254680c49c7eSIan Munsie 254780c49c7eSIan Munsie void pnv_cxl_release_hwirq_ranges(struct cxl_irq_ranges *irqs, 254880c49c7eSIan Munsie struct pci_dev *dev) 254980c49c7eSIan Munsie { 255080c49c7eSIan Munsie struct pci_controller *hose = pci_bus_to_host(dev->bus); 255180c49c7eSIan Munsie struct pnv_phb *phb = hose->private_data; 255280c49c7eSIan Munsie int i, hwirq; 255380c49c7eSIan Munsie 255480c49c7eSIan Munsie for (i = 1; i < CXL_IRQ_RANGES; i++) { 255580c49c7eSIan Munsie if (!irqs->range[i]) 255680c49c7eSIan Munsie continue; 255780c49c7eSIan Munsie pr_devel("cxl release irq range 0x%x: offset: 0x%lx limit: %ld\n", 255880c49c7eSIan Munsie i, irqs->offset[i], 255980c49c7eSIan Munsie irqs->range[i]); 256080c49c7eSIan Munsie hwirq = irqs->offset[i] - phb->msi_base; 256180c49c7eSIan Munsie msi_bitmap_free_hwirqs(&phb->msi_bmp, hwirq, 256280c49c7eSIan Munsie irqs->range[i]); 256380c49c7eSIan Munsie } 256480c49c7eSIan Munsie } 256580c49c7eSIan Munsie EXPORT_SYMBOL(pnv_cxl_release_hwirq_ranges); 256680c49c7eSIan Munsie 256780c49c7eSIan Munsie int pnv_cxl_alloc_hwirq_ranges(struct cxl_irq_ranges *irqs, 256880c49c7eSIan Munsie struct pci_dev *dev, int num) 256980c49c7eSIan Munsie { 257080c49c7eSIan Munsie struct pci_controller *hose = pci_bus_to_host(dev->bus); 257180c49c7eSIan Munsie struct pnv_phb *phb = hose->private_data; 257280c49c7eSIan Munsie int i, hwirq, try; 257380c49c7eSIan Munsie 257480c49c7eSIan Munsie memset(irqs, 0, sizeof(struct cxl_irq_ranges)); 257580c49c7eSIan Munsie 257680c49c7eSIan Munsie /* 0 is reserved for the multiplexed PSL DSI interrupt */ 257780c49c7eSIan Munsie for (i = 1; i < CXL_IRQ_RANGES && num; i++) { 257880c49c7eSIan Munsie try = num; 257980c49c7eSIan Munsie while (try) { 258080c49c7eSIan Munsie hwirq = msi_bitmap_alloc_hwirqs(&phb->msi_bmp, try); 258180c49c7eSIan Munsie if (hwirq >= 0) 258280c49c7eSIan Munsie break; 258380c49c7eSIan Munsie try /= 2; 258480c49c7eSIan Munsie } 258580c49c7eSIan Munsie if (!try) 258680c49c7eSIan Munsie goto fail; 258780c49c7eSIan Munsie 258880c49c7eSIan Munsie irqs->offset[i] = phb->msi_base + hwirq; 258980c49c7eSIan Munsie irqs->range[i] = try; 259080c49c7eSIan Munsie pr_devel("cxl alloc irq range 0x%x: offset: 0x%lx limit: %li\n", 259180c49c7eSIan Munsie i, irqs->offset[i], irqs->range[i]); 259280c49c7eSIan Munsie num -= try; 259380c49c7eSIan Munsie } 259480c49c7eSIan Munsie if (num) 259580c49c7eSIan Munsie goto fail; 259680c49c7eSIan Munsie 259780c49c7eSIan Munsie return 0; 259880c49c7eSIan Munsie fail: 259980c49c7eSIan Munsie pnv_cxl_release_hwirq_ranges(irqs, dev); 260080c49c7eSIan Munsie return -ENOSPC; 260180c49c7eSIan Munsie } 260280c49c7eSIan Munsie EXPORT_SYMBOL(pnv_cxl_alloc_hwirq_ranges); 260380c49c7eSIan Munsie 260480c49c7eSIan Munsie int pnv_cxl_get_irq_count(struct pci_dev *dev) 260580c49c7eSIan Munsie { 260680c49c7eSIan Munsie struct pci_controller *hose = pci_bus_to_host(dev->bus); 260780c49c7eSIan Munsie struct pnv_phb *phb = hose->private_data; 260880c49c7eSIan Munsie 260980c49c7eSIan Munsie return phb->msi_bmp.irq_count; 261080c49c7eSIan Munsie } 261180c49c7eSIan Munsie EXPORT_SYMBOL(pnv_cxl_get_irq_count); 261280c49c7eSIan Munsie 261380c49c7eSIan Munsie int pnv_cxl_ioda_msi_setup(struct pci_dev *dev, unsigned int hwirq, 261480c49c7eSIan Munsie unsigned int virq) 261580c49c7eSIan Munsie { 261680c49c7eSIan Munsie struct pci_controller *hose = pci_bus_to_host(dev->bus); 261780c49c7eSIan Munsie struct pnv_phb *phb = hose->private_data; 261880c49c7eSIan Munsie unsigned int xive_num = hwirq - phb->msi_base; 261980c49c7eSIan Munsie struct pnv_ioda_pe *pe; 262080c49c7eSIan Munsie int rc; 262180c49c7eSIan Munsie 262280c49c7eSIan Munsie if (!(pe = pnv_ioda_get_pe(dev))) 262380c49c7eSIan Munsie return -ENODEV; 262480c49c7eSIan Munsie 262580c49c7eSIan Munsie /* Assign XIVE to PE */ 262680c49c7eSIan Munsie rc = opal_pci_set_xive_pe(phb->opal_id, pe->pe_number, xive_num); 262780c49c7eSIan Munsie if (rc) { 262880c49c7eSIan Munsie pe_warn(pe, "%s: OPAL error %d setting msi_base 0x%x " 262980c49c7eSIan Munsie "hwirq 0x%x XIVE 0x%x PE\n", 263080c49c7eSIan Munsie pci_name(dev), rc, phb->msi_base, hwirq, xive_num); 263180c49c7eSIan Munsie return -EIO; 263280c49c7eSIan Munsie } 263380c49c7eSIan Munsie set_msi_irq_chip(phb, virq); 263480c49c7eSIan Munsie 263580c49c7eSIan Munsie return 0; 263680c49c7eSIan Munsie } 263780c49c7eSIan Munsie EXPORT_SYMBOL(pnv_cxl_ioda_msi_setup); 263880c49c7eSIan Munsie #endif 263980c49c7eSIan Munsie 2640184cd4a3SBenjamin Herrenschmidt static int pnv_pci_ioda_msi_setup(struct pnv_phb *phb, struct pci_dev *dev, 2641137436c9SGavin Shan unsigned int hwirq, unsigned int virq, 2642137436c9SGavin Shan unsigned int is_64, struct msi_msg *msg) 2643184cd4a3SBenjamin Herrenschmidt { 2644184cd4a3SBenjamin Herrenschmidt struct pnv_ioda_pe *pe = pnv_ioda_get_pe(dev); 2645184cd4a3SBenjamin Herrenschmidt unsigned int xive_num = hwirq - phb->msi_base; 26463a1a4661SBenjamin Herrenschmidt __be32 data; 2647184cd4a3SBenjamin Herrenschmidt int rc; 2648184cd4a3SBenjamin Herrenschmidt 2649184cd4a3SBenjamin Herrenschmidt /* No PE assigned ? bail out ... no MSI for you ! */ 2650184cd4a3SBenjamin Herrenschmidt if (pe == NULL) 2651184cd4a3SBenjamin Herrenschmidt return -ENXIO; 2652184cd4a3SBenjamin Herrenschmidt 2653184cd4a3SBenjamin Herrenschmidt /* Check if we have an MVE */ 2654184cd4a3SBenjamin Herrenschmidt if (pe->mve_number < 0) 2655184cd4a3SBenjamin Herrenschmidt return -ENXIO; 2656184cd4a3SBenjamin Herrenschmidt 2657b72c1f65SBenjamin Herrenschmidt /* Force 32-bit MSI on some broken devices */ 265836074381SBenjamin Herrenschmidt if (dev->no_64bit_msi) 2659b72c1f65SBenjamin Herrenschmidt is_64 = 0; 2660b72c1f65SBenjamin Herrenschmidt 2661184cd4a3SBenjamin Herrenschmidt /* Assign XIVE to PE */ 2662184cd4a3SBenjamin Herrenschmidt rc = opal_pci_set_xive_pe(phb->opal_id, pe->pe_number, xive_num); 2663184cd4a3SBenjamin Herrenschmidt if (rc) { 2664184cd4a3SBenjamin Herrenschmidt pr_warn("%s: OPAL error %d setting XIVE %d PE\n", 2665184cd4a3SBenjamin Herrenschmidt pci_name(dev), rc, xive_num); 2666184cd4a3SBenjamin Herrenschmidt return -EIO; 2667184cd4a3SBenjamin Herrenschmidt } 2668184cd4a3SBenjamin Herrenschmidt 2669184cd4a3SBenjamin Herrenschmidt if (is_64) { 26703a1a4661SBenjamin Herrenschmidt __be64 addr64; 26713a1a4661SBenjamin Herrenschmidt 2672184cd4a3SBenjamin Herrenschmidt rc = opal_get_msi_64(phb->opal_id, pe->mve_number, xive_num, 1, 2673184cd4a3SBenjamin Herrenschmidt &addr64, &data); 2674184cd4a3SBenjamin Herrenschmidt if (rc) { 2675184cd4a3SBenjamin Herrenschmidt pr_warn("%s: OPAL error %d getting 64-bit MSI data\n", 2676184cd4a3SBenjamin Herrenschmidt pci_name(dev), rc); 2677184cd4a3SBenjamin Herrenschmidt return -EIO; 2678184cd4a3SBenjamin Herrenschmidt } 26793a1a4661SBenjamin Herrenschmidt msg->address_hi = be64_to_cpu(addr64) >> 32; 26803a1a4661SBenjamin Herrenschmidt msg->address_lo = be64_to_cpu(addr64) & 0xfffffffful; 2681184cd4a3SBenjamin Herrenschmidt } else { 26823a1a4661SBenjamin Herrenschmidt __be32 addr32; 26833a1a4661SBenjamin Herrenschmidt 2684184cd4a3SBenjamin Herrenschmidt rc = opal_get_msi_32(phb->opal_id, pe->mve_number, xive_num, 1, 2685184cd4a3SBenjamin Herrenschmidt &addr32, &data); 2686184cd4a3SBenjamin Herrenschmidt if (rc) { 2687184cd4a3SBenjamin Herrenschmidt pr_warn("%s: OPAL error %d getting 32-bit MSI data\n", 2688184cd4a3SBenjamin Herrenschmidt pci_name(dev), rc); 2689184cd4a3SBenjamin Herrenschmidt return -EIO; 2690184cd4a3SBenjamin Herrenschmidt } 2691184cd4a3SBenjamin Herrenschmidt msg->address_hi = 0; 26923a1a4661SBenjamin Herrenschmidt msg->address_lo = be32_to_cpu(addr32); 2693184cd4a3SBenjamin Herrenschmidt } 26943a1a4661SBenjamin Herrenschmidt msg->data = be32_to_cpu(data); 2695184cd4a3SBenjamin Herrenschmidt 2696fd9a1c26SIan Munsie set_msi_irq_chip(phb, virq); 2697137436c9SGavin Shan 2698184cd4a3SBenjamin Herrenschmidt pr_devel("%s: %s-bit MSI on hwirq %x (xive #%d)," 2699184cd4a3SBenjamin Herrenschmidt " address=%x_%08x data=%x PE# %d\n", 2700184cd4a3SBenjamin Herrenschmidt pci_name(dev), is_64 ? "64" : "32", hwirq, xive_num, 2701184cd4a3SBenjamin Herrenschmidt msg->address_hi, msg->address_lo, data, pe->pe_number); 2702184cd4a3SBenjamin Herrenschmidt 2703184cd4a3SBenjamin Herrenschmidt return 0; 2704184cd4a3SBenjamin Herrenschmidt } 2705184cd4a3SBenjamin Herrenschmidt 2706184cd4a3SBenjamin Herrenschmidt static void pnv_pci_init_ioda_msis(struct pnv_phb *phb) 2707184cd4a3SBenjamin Herrenschmidt { 2708fb1b55d6SGavin Shan unsigned int count; 2709184cd4a3SBenjamin Herrenschmidt const __be32 *prop = of_get_property(phb->hose->dn, 2710184cd4a3SBenjamin Herrenschmidt "ibm,opal-msi-ranges", NULL); 2711184cd4a3SBenjamin Herrenschmidt if (!prop) { 2712184cd4a3SBenjamin Herrenschmidt /* BML Fallback */ 2713184cd4a3SBenjamin Herrenschmidt prop = of_get_property(phb->hose->dn, "msi-ranges", NULL); 2714184cd4a3SBenjamin Herrenschmidt } 2715184cd4a3SBenjamin Herrenschmidt if (!prop) 2716184cd4a3SBenjamin Herrenschmidt return; 2717184cd4a3SBenjamin Herrenschmidt 2718184cd4a3SBenjamin Herrenschmidt phb->msi_base = be32_to_cpup(prop); 2719fb1b55d6SGavin Shan count = be32_to_cpup(prop + 1); 2720fb1b55d6SGavin Shan if (msi_bitmap_alloc(&phb->msi_bmp, count, phb->hose->dn)) { 2721184cd4a3SBenjamin Herrenschmidt pr_err("PCI %d: Failed to allocate MSI bitmap !\n", 2722184cd4a3SBenjamin Herrenschmidt phb->hose->global_number); 2723184cd4a3SBenjamin Herrenschmidt return; 2724184cd4a3SBenjamin Herrenschmidt } 2725fb1b55d6SGavin Shan 2726184cd4a3SBenjamin Herrenschmidt phb->msi_setup = pnv_pci_ioda_msi_setup; 2727184cd4a3SBenjamin Herrenschmidt phb->msi32_support = 1; 2728184cd4a3SBenjamin Herrenschmidt pr_info(" Allocated bitmap for %d MSIs (base IRQ 0x%x)\n", 2729fb1b55d6SGavin Shan count, phb->msi_base); 2730184cd4a3SBenjamin Herrenschmidt } 2731184cd4a3SBenjamin Herrenschmidt #else 2732184cd4a3SBenjamin Herrenschmidt static void pnv_pci_init_ioda_msis(struct pnv_phb *phb) { } 2733184cd4a3SBenjamin Herrenschmidt #endif /* CONFIG_PCI_MSI */ 2734184cd4a3SBenjamin Herrenschmidt 27356e628c7dSWei Yang #ifdef CONFIG_PCI_IOV 27366e628c7dSWei Yang static void pnv_pci_ioda_fixup_iov_resources(struct pci_dev *pdev) 27376e628c7dSWei Yang { 27386e628c7dSWei Yang struct pci_controller *hose; 27396e628c7dSWei Yang struct pnv_phb *phb; 27406e628c7dSWei Yang struct resource *res; 27416e628c7dSWei Yang int i; 27426e628c7dSWei Yang resource_size_t size; 27436e628c7dSWei Yang struct pci_dn *pdn; 27445b88ec22SWei Yang int mul, total_vfs; 27456e628c7dSWei Yang 27466e628c7dSWei Yang if (!pdev->is_physfn || pdev->is_added) 27476e628c7dSWei Yang return; 27486e628c7dSWei Yang 27496e628c7dSWei Yang hose = pci_bus_to_host(pdev->bus); 27506e628c7dSWei Yang phb = hose->private_data; 27516e628c7dSWei Yang 27526e628c7dSWei Yang pdn = pci_get_pdn(pdev); 27536e628c7dSWei Yang pdn->vfs_expanded = 0; 27546e628c7dSWei Yang 27555b88ec22SWei Yang total_vfs = pci_sriov_get_totalvfs(pdev); 27565b88ec22SWei Yang pdn->m64_per_iov = 1; 27575b88ec22SWei Yang mul = phb->ioda.total_pe; 27585b88ec22SWei Yang 27595b88ec22SWei Yang for (i = 0; i < PCI_SRIOV_NUM_BARS; i++) { 27605b88ec22SWei Yang res = &pdev->resource[i + PCI_IOV_RESOURCES]; 27615b88ec22SWei Yang if (!res->flags || res->parent) 27625b88ec22SWei Yang continue; 27635b88ec22SWei Yang if (!pnv_pci_is_mem_pref_64(res->flags)) { 27645b88ec22SWei Yang dev_warn(&pdev->dev, " non M64 VF BAR%d: %pR\n", 27655b88ec22SWei Yang i, res); 27665b88ec22SWei Yang continue; 27675b88ec22SWei Yang } 27685b88ec22SWei Yang 27695b88ec22SWei Yang size = pci_iov_resource_size(pdev, i + PCI_IOV_RESOURCES); 27705b88ec22SWei Yang 27715b88ec22SWei Yang /* bigger than 64M */ 27725b88ec22SWei Yang if (size > (1 << 26)) { 27735b88ec22SWei Yang dev_info(&pdev->dev, "PowerNV: VF BAR%d: %pR IOV size is bigger than 64M, roundup power2\n", 27745b88ec22SWei Yang i, res); 27755b88ec22SWei Yang pdn->m64_per_iov = M64_PER_IOV; 27765b88ec22SWei Yang mul = roundup_pow_of_two(total_vfs); 27775b88ec22SWei Yang break; 27785b88ec22SWei Yang } 27795b88ec22SWei Yang } 27805b88ec22SWei Yang 27816e628c7dSWei Yang for (i = 0; i < PCI_SRIOV_NUM_BARS; i++) { 27826e628c7dSWei Yang res = &pdev->resource[i + PCI_IOV_RESOURCES]; 27836e628c7dSWei Yang if (!res->flags || res->parent) 27846e628c7dSWei Yang continue; 27856e628c7dSWei Yang if (!pnv_pci_is_mem_pref_64(res->flags)) { 27866e628c7dSWei Yang dev_warn(&pdev->dev, "Skipping expanding VF BAR%d: %pR\n", 27876e628c7dSWei Yang i, res); 27886e628c7dSWei Yang continue; 27896e628c7dSWei Yang } 27906e628c7dSWei Yang 27916e628c7dSWei Yang dev_dbg(&pdev->dev, " Fixing VF BAR%d: %pR to\n", i, res); 27926e628c7dSWei Yang size = pci_iov_resource_size(pdev, i + PCI_IOV_RESOURCES); 27935b88ec22SWei Yang res->end = res->start + size * mul - 1; 27946e628c7dSWei Yang dev_dbg(&pdev->dev, " %pR\n", res); 27956e628c7dSWei Yang dev_info(&pdev->dev, "VF BAR%d: %pR (expanded to %d VFs for PE alignment)", 27965b88ec22SWei Yang i, res, mul); 27976e628c7dSWei Yang } 27985b88ec22SWei Yang pdn->vfs_expanded = mul; 27996e628c7dSWei Yang } 28006e628c7dSWei Yang #endif /* CONFIG_PCI_IOV */ 28016e628c7dSWei Yang 280211685becSGavin Shan /* 280311685becSGavin Shan * This function is supposed to be called on basis of PE from top 280411685becSGavin Shan * to bottom style. So the the I/O or MMIO segment assigned to 280511685becSGavin Shan * parent PE could be overrided by its child PEs if necessary. 280611685becSGavin Shan */ 2807cad5cef6SGreg Kroah-Hartman static void pnv_ioda_setup_pe_seg(struct pci_controller *hose, 280811685becSGavin Shan struct pnv_ioda_pe *pe) 280911685becSGavin Shan { 281011685becSGavin Shan struct pnv_phb *phb = hose->private_data; 281111685becSGavin Shan struct pci_bus_region region; 281211685becSGavin Shan struct resource *res; 281311685becSGavin Shan int i, index; 281411685becSGavin Shan int rc; 281511685becSGavin Shan 281611685becSGavin Shan /* 281711685becSGavin Shan * NOTE: We only care PCI bus based PE for now. For PCI 281811685becSGavin Shan * device based PE, for example SRIOV sensitive VF should 281911685becSGavin Shan * be figured out later. 282011685becSGavin Shan */ 282111685becSGavin Shan BUG_ON(!(pe->flags & (PNV_IODA_PE_BUS | PNV_IODA_PE_BUS_ALL))); 282211685becSGavin Shan 282311685becSGavin Shan pci_bus_for_each_resource(pe->pbus, res, i) { 282411685becSGavin Shan if (!res || !res->flags || 282511685becSGavin Shan res->start > res->end) 282611685becSGavin Shan continue; 282711685becSGavin Shan 282811685becSGavin Shan if (res->flags & IORESOURCE_IO) { 282911685becSGavin Shan region.start = res->start - phb->ioda.io_pci_base; 283011685becSGavin Shan region.end = res->end - phb->ioda.io_pci_base; 283111685becSGavin Shan index = region.start / phb->ioda.io_segsize; 283211685becSGavin Shan 283311685becSGavin Shan while (index < phb->ioda.total_pe && 283411685becSGavin Shan region.start <= region.end) { 283511685becSGavin Shan phb->ioda.io_segmap[index] = pe->pe_number; 283611685becSGavin Shan rc = opal_pci_map_pe_mmio_window(phb->opal_id, 283711685becSGavin Shan pe->pe_number, OPAL_IO_WINDOW_TYPE, 0, index); 283811685becSGavin Shan if (rc != OPAL_SUCCESS) { 283911685becSGavin Shan pr_err("%s: OPAL error %d when mapping IO " 284011685becSGavin Shan "segment #%d to PE#%d\n", 284111685becSGavin Shan __func__, rc, index, pe->pe_number); 284211685becSGavin Shan break; 284311685becSGavin Shan } 284411685becSGavin Shan 284511685becSGavin Shan region.start += phb->ioda.io_segsize; 284611685becSGavin Shan index++; 284711685becSGavin Shan } 2848027fa02fSGavin Shan } else if ((res->flags & IORESOURCE_MEM) && 2849027fa02fSGavin Shan !pnv_pci_is_mem_pref_64(res->flags)) { 285011685becSGavin Shan region.start = res->start - 28513fd47f06SBenjamin Herrenschmidt hose->mem_offset[0] - 285211685becSGavin Shan phb->ioda.m32_pci_base; 285311685becSGavin Shan region.end = res->end - 28543fd47f06SBenjamin Herrenschmidt hose->mem_offset[0] - 285511685becSGavin Shan phb->ioda.m32_pci_base; 285611685becSGavin Shan index = region.start / phb->ioda.m32_segsize; 285711685becSGavin Shan 285811685becSGavin Shan while (index < phb->ioda.total_pe && 285911685becSGavin Shan region.start <= region.end) { 286011685becSGavin Shan phb->ioda.m32_segmap[index] = pe->pe_number; 286111685becSGavin Shan rc = opal_pci_map_pe_mmio_window(phb->opal_id, 286211685becSGavin Shan pe->pe_number, OPAL_M32_WINDOW_TYPE, 0, index); 286311685becSGavin Shan if (rc != OPAL_SUCCESS) { 286411685becSGavin Shan pr_err("%s: OPAL error %d when mapping M32 " 286511685becSGavin Shan "segment#%d to PE#%d", 286611685becSGavin Shan __func__, rc, index, pe->pe_number); 286711685becSGavin Shan break; 286811685becSGavin Shan } 286911685becSGavin Shan 287011685becSGavin Shan region.start += phb->ioda.m32_segsize; 287111685becSGavin Shan index++; 287211685becSGavin Shan } 287311685becSGavin Shan } 287411685becSGavin Shan } 287511685becSGavin Shan } 287611685becSGavin Shan 2877cad5cef6SGreg Kroah-Hartman static void pnv_pci_ioda_setup_seg(void) 287811685becSGavin Shan { 287911685becSGavin Shan struct pci_controller *tmp, *hose; 288011685becSGavin Shan struct pnv_phb *phb; 288111685becSGavin Shan struct pnv_ioda_pe *pe; 288211685becSGavin Shan 288311685becSGavin Shan list_for_each_entry_safe(hose, tmp, &hose_list, list_node) { 288411685becSGavin Shan phb = hose->private_data; 288511685becSGavin Shan list_for_each_entry(pe, &phb->ioda.pe_list, list) { 288611685becSGavin Shan pnv_ioda_setup_pe_seg(hose, pe); 288711685becSGavin Shan } 288811685becSGavin Shan } 288911685becSGavin Shan } 289011685becSGavin Shan 2891cad5cef6SGreg Kroah-Hartman static void pnv_pci_ioda_setup_DMA(void) 289213395c48SGavin Shan { 289313395c48SGavin Shan struct pci_controller *hose, *tmp; 2894db1266c8SGavin Shan struct pnv_phb *phb; 289513395c48SGavin Shan 289613395c48SGavin Shan list_for_each_entry_safe(hose, tmp, &hose_list, list_node) { 289713395c48SGavin Shan pnv_ioda_setup_dma(hose->private_data); 2898db1266c8SGavin Shan 2899db1266c8SGavin Shan /* Mark the PHB initialization done */ 2900db1266c8SGavin Shan phb = hose->private_data; 2901db1266c8SGavin Shan phb->initialized = 1; 290213395c48SGavin Shan } 290313395c48SGavin Shan } 290413395c48SGavin Shan 290537c367f2SGavin Shan static void pnv_pci_ioda_create_dbgfs(void) 290637c367f2SGavin Shan { 290737c367f2SGavin Shan #ifdef CONFIG_DEBUG_FS 290837c367f2SGavin Shan struct pci_controller *hose, *tmp; 290937c367f2SGavin Shan struct pnv_phb *phb; 291037c367f2SGavin Shan char name[16]; 291137c367f2SGavin Shan 291237c367f2SGavin Shan list_for_each_entry_safe(hose, tmp, &hose_list, list_node) { 291337c367f2SGavin Shan phb = hose->private_data; 291437c367f2SGavin Shan 291537c367f2SGavin Shan sprintf(name, "PCI%04x", hose->global_number); 291637c367f2SGavin Shan phb->dbgfs = debugfs_create_dir(name, powerpc_debugfs_root); 291737c367f2SGavin Shan if (!phb->dbgfs) 291837c367f2SGavin Shan pr_warning("%s: Error on creating debugfs on PHB#%x\n", 291937c367f2SGavin Shan __func__, hose->global_number); 292037c367f2SGavin Shan } 292137c367f2SGavin Shan #endif /* CONFIG_DEBUG_FS */ 292237c367f2SGavin Shan } 292337c367f2SGavin Shan 2924cad5cef6SGreg Kroah-Hartman static void pnv_pci_ioda_fixup(void) 2925fb446ad0SGavin Shan { 2926fb446ad0SGavin Shan pnv_pci_ioda_setup_PEs(); 292711685becSGavin Shan pnv_pci_ioda_setup_seg(); 292813395c48SGavin Shan pnv_pci_ioda_setup_DMA(); 2929e9cc17d4SGavin Shan 293037c367f2SGavin Shan pnv_pci_ioda_create_dbgfs(); 293137c367f2SGavin Shan 2932e9cc17d4SGavin Shan #ifdef CONFIG_EEH 2933e9cc17d4SGavin Shan eeh_init(); 2934dadcd6d6SMike Qiu eeh_addr_cache_build(); 2935e9cc17d4SGavin Shan #endif 2936fb446ad0SGavin Shan } 2937fb446ad0SGavin Shan 2938271fd03aSGavin Shan /* 2939271fd03aSGavin Shan * Returns the alignment for I/O or memory windows for P2P 2940271fd03aSGavin Shan * bridges. That actually depends on how PEs are segmented. 2941271fd03aSGavin Shan * For now, we return I/O or M32 segment size for PE sensitive 2942271fd03aSGavin Shan * P2P bridges. Otherwise, the default values (4KiB for I/O, 2943271fd03aSGavin Shan * 1MiB for memory) will be returned. 2944271fd03aSGavin Shan * 2945271fd03aSGavin Shan * The current PCI bus might be put into one PE, which was 2946271fd03aSGavin Shan * create against the parent PCI bridge. For that case, we 2947271fd03aSGavin Shan * needn't enlarge the alignment so that we can save some 2948271fd03aSGavin Shan * resources. 2949271fd03aSGavin Shan */ 2950271fd03aSGavin Shan static resource_size_t pnv_pci_window_alignment(struct pci_bus *bus, 2951271fd03aSGavin Shan unsigned long type) 2952271fd03aSGavin Shan { 2953271fd03aSGavin Shan struct pci_dev *bridge; 2954271fd03aSGavin Shan struct pci_controller *hose = pci_bus_to_host(bus); 2955271fd03aSGavin Shan struct pnv_phb *phb = hose->private_data; 2956271fd03aSGavin Shan int num_pci_bridges = 0; 2957271fd03aSGavin Shan 2958271fd03aSGavin Shan bridge = bus->self; 2959271fd03aSGavin Shan while (bridge) { 2960271fd03aSGavin Shan if (pci_pcie_type(bridge) == PCI_EXP_TYPE_PCI_BRIDGE) { 2961271fd03aSGavin Shan num_pci_bridges++; 2962271fd03aSGavin Shan if (num_pci_bridges >= 2) 2963271fd03aSGavin Shan return 1; 2964271fd03aSGavin Shan } 2965271fd03aSGavin Shan 2966271fd03aSGavin Shan bridge = bridge->bus->self; 2967271fd03aSGavin Shan } 2968271fd03aSGavin Shan 2969262af557SGuo Chao /* We fail back to M32 if M64 isn't supported */ 2970262af557SGuo Chao if (phb->ioda.m64_segsize && 2971262af557SGuo Chao pnv_pci_is_mem_pref_64(type)) 2972262af557SGuo Chao return phb->ioda.m64_segsize; 2973271fd03aSGavin Shan if (type & IORESOURCE_MEM) 2974271fd03aSGavin Shan return phb->ioda.m32_segsize; 2975271fd03aSGavin Shan 2976271fd03aSGavin Shan return phb->ioda.io_segsize; 2977271fd03aSGavin Shan } 2978271fd03aSGavin Shan 29795350ab3fSWei Yang #ifdef CONFIG_PCI_IOV 29805350ab3fSWei Yang static resource_size_t pnv_pci_iov_resource_alignment(struct pci_dev *pdev, 29815350ab3fSWei Yang int resno) 29825350ab3fSWei Yang { 29835350ab3fSWei Yang struct pci_dn *pdn = pci_get_pdn(pdev); 29845350ab3fSWei Yang resource_size_t align, iov_align; 29855350ab3fSWei Yang 29865350ab3fSWei Yang iov_align = resource_size(&pdev->resource[resno]); 29875350ab3fSWei Yang if (iov_align) 29885350ab3fSWei Yang return iov_align; 29895350ab3fSWei Yang 29905350ab3fSWei Yang align = pci_iov_resource_size(pdev, resno); 29915350ab3fSWei Yang if (pdn->vfs_expanded) 29925350ab3fSWei Yang return pdn->vfs_expanded * align; 29935350ab3fSWei Yang 29945350ab3fSWei Yang return align; 29955350ab3fSWei Yang } 29965350ab3fSWei Yang #endif /* CONFIG_PCI_IOV */ 29975350ab3fSWei Yang 2998184cd4a3SBenjamin Herrenschmidt /* Prevent enabling devices for which we couldn't properly 2999184cd4a3SBenjamin Herrenschmidt * assign a PE 3000184cd4a3SBenjamin Herrenschmidt */ 3001c88c2a18SDaniel Axtens static bool pnv_pci_enable_device_hook(struct pci_dev *dev) 3002184cd4a3SBenjamin Herrenschmidt { 3003db1266c8SGavin Shan struct pci_controller *hose = pci_bus_to_host(dev->bus); 3004db1266c8SGavin Shan struct pnv_phb *phb = hose->private_data; 3005db1266c8SGavin Shan struct pci_dn *pdn; 3006184cd4a3SBenjamin Herrenschmidt 3007db1266c8SGavin Shan /* The function is probably called while the PEs have 3008db1266c8SGavin Shan * not be created yet. For example, resource reassignment 3009db1266c8SGavin Shan * during PCI probe period. We just skip the check if 3010db1266c8SGavin Shan * PEs isn't ready. 3011db1266c8SGavin Shan */ 3012db1266c8SGavin Shan if (!phb->initialized) 3013c88c2a18SDaniel Axtens return true; 3014db1266c8SGavin Shan 3015b72c1f65SBenjamin Herrenschmidt pdn = pci_get_pdn(dev); 3016184cd4a3SBenjamin Herrenschmidt if (!pdn || pdn->pe_number == IODA_INVALID_PE) 3017c88c2a18SDaniel Axtens return false; 3018db1266c8SGavin Shan 3019c88c2a18SDaniel Axtens return true; 3020184cd4a3SBenjamin Herrenschmidt } 3021184cd4a3SBenjamin Herrenschmidt 3022184cd4a3SBenjamin Herrenschmidt static u32 pnv_ioda_bdfn_to_pe(struct pnv_phb *phb, struct pci_bus *bus, 3023184cd4a3SBenjamin Herrenschmidt u32 devfn) 3024184cd4a3SBenjamin Herrenschmidt { 3025184cd4a3SBenjamin Herrenschmidt return phb->ioda.pe_rmap[(bus->number << 8) | devfn]; 3026184cd4a3SBenjamin Herrenschmidt } 3027184cd4a3SBenjamin Herrenschmidt 30287a8e6bbfSMichael Neuling static void pnv_pci_ioda_shutdown(struct pci_controller *hose) 302973ed148aSBenjamin Herrenschmidt { 30307a8e6bbfSMichael Neuling struct pnv_phb *phb = hose->private_data; 30317a8e6bbfSMichael Neuling 3032d1a85eeeSGavin Shan opal_pci_reset(phb->opal_id, OPAL_RESET_PCI_IODA_TABLE, 303373ed148aSBenjamin Herrenschmidt OPAL_ASSERT_RESET); 303473ed148aSBenjamin Herrenschmidt } 303573ed148aSBenjamin Herrenschmidt 303692ae0353SDaniel Axtens static const struct pci_controller_ops pnv_pci_ioda_controller_ops = { 303792ae0353SDaniel Axtens .dma_dev_setup = pnv_pci_dma_dev_setup, 303892ae0353SDaniel Axtens #ifdef CONFIG_PCI_MSI 303992ae0353SDaniel Axtens .setup_msi_irqs = pnv_setup_msi_irqs, 304092ae0353SDaniel Axtens .teardown_msi_irqs = pnv_teardown_msi_irqs, 304192ae0353SDaniel Axtens #endif 304292ae0353SDaniel Axtens .enable_device_hook = pnv_pci_enable_device_hook, 304392ae0353SDaniel Axtens .window_alignment = pnv_pci_window_alignment, 304492ae0353SDaniel Axtens .reset_secondary_bus = pnv_pci_reset_secondary_bus, 3045763d2d8dSDaniel Axtens .dma_set_mask = pnv_pci_ioda_dma_set_mask, 304653522982SAndrew Donnellan .dma_get_required_mask = pnv_pci_ioda_dma_get_required_mask, 30477a8e6bbfSMichael Neuling .shutdown = pnv_pci_ioda_shutdown, 304892ae0353SDaniel Axtens }; 304992ae0353SDaniel Axtens 3050e51df2c1SAnton Blanchard static void __init pnv_pci_init_ioda_phb(struct device_node *np, 3051e9cc17d4SGavin Shan u64 hub_id, int ioda_type) 3052184cd4a3SBenjamin Herrenschmidt { 3053184cd4a3SBenjamin Herrenschmidt struct pci_controller *hose; 3054184cd4a3SBenjamin Herrenschmidt struct pnv_phb *phb; 30558184616fSGavin Shan unsigned long size, m32map_off, pemap_off, iomap_off = 0; 3056c681b93cSAlistair Popple const __be64 *prop64; 30573a1a4661SBenjamin Herrenschmidt const __be32 *prop32; 3058f1b7cc3eSGavin Shan int len; 3059184cd4a3SBenjamin Herrenschmidt u64 phb_id; 3060184cd4a3SBenjamin Herrenschmidt void *aux; 3061184cd4a3SBenjamin Herrenschmidt long rc; 3062184cd4a3SBenjamin Herrenschmidt 3063aa0c033fSGavin Shan pr_info("Initializing IODA%d OPAL PHB %s\n", ioda_type, np->full_name); 3064184cd4a3SBenjamin Herrenschmidt 3065184cd4a3SBenjamin Herrenschmidt prop64 = of_get_property(np, "ibm,opal-phbid", NULL); 3066184cd4a3SBenjamin Herrenschmidt if (!prop64) { 3067184cd4a3SBenjamin Herrenschmidt pr_err(" Missing \"ibm,opal-phbid\" property !\n"); 3068184cd4a3SBenjamin Herrenschmidt return; 3069184cd4a3SBenjamin Herrenschmidt } 3070184cd4a3SBenjamin Herrenschmidt phb_id = be64_to_cpup(prop64); 3071184cd4a3SBenjamin Herrenschmidt pr_debug(" PHB-ID : 0x%016llx\n", phb_id); 3072184cd4a3SBenjamin Herrenschmidt 3073e39f223fSMichael Ellerman phb = memblock_virt_alloc(sizeof(struct pnv_phb), 0); 307458d714ecSGavin Shan 307558d714ecSGavin Shan /* Allocate PCI controller */ 3076184cd4a3SBenjamin Herrenschmidt phb->hose = hose = pcibios_alloc_controller(np); 307758d714ecSGavin Shan if (!phb->hose) { 307858d714ecSGavin Shan pr_err(" Can't allocate PCI controller for %s\n", 3079184cd4a3SBenjamin Herrenschmidt np->full_name); 3080e39f223fSMichael Ellerman memblock_free(__pa(phb), sizeof(struct pnv_phb)); 3081184cd4a3SBenjamin Herrenschmidt return; 3082184cd4a3SBenjamin Herrenschmidt } 3083184cd4a3SBenjamin Herrenschmidt 3084184cd4a3SBenjamin Herrenschmidt spin_lock_init(&phb->lock); 3085f1b7cc3eSGavin Shan prop32 = of_get_property(np, "bus-range", &len); 3086f1b7cc3eSGavin Shan if (prop32 && len == 8) { 30873a1a4661SBenjamin Herrenschmidt hose->first_busno = be32_to_cpu(prop32[0]); 30883a1a4661SBenjamin Herrenschmidt hose->last_busno = be32_to_cpu(prop32[1]); 3089f1b7cc3eSGavin Shan } else { 3090f1b7cc3eSGavin Shan pr_warn(" Broken <bus-range> on %s\n", np->full_name); 3091184cd4a3SBenjamin Herrenschmidt hose->first_busno = 0; 3092184cd4a3SBenjamin Herrenschmidt hose->last_busno = 0xff; 3093f1b7cc3eSGavin Shan } 3094184cd4a3SBenjamin Herrenschmidt hose->private_data = phb; 3095e9cc17d4SGavin Shan phb->hub_id = hub_id; 3096184cd4a3SBenjamin Herrenschmidt phb->opal_id = phb_id; 3097aa0c033fSGavin Shan phb->type = ioda_type; 3098781a868fSWei Yang mutex_init(&phb->ioda.pe_alloc_mutex); 3099184cd4a3SBenjamin Herrenschmidt 3100cee72d5bSBenjamin Herrenschmidt /* Detect specific models for error handling */ 3101cee72d5bSBenjamin Herrenschmidt if (of_device_is_compatible(np, "ibm,p7ioc-pciex")) 3102cee72d5bSBenjamin Herrenschmidt phb->model = PNV_PHB_MODEL_P7IOC; 3103f3d40c25SBenjamin Herrenschmidt else if (of_device_is_compatible(np, "ibm,power8-pciex")) 3104aa0c033fSGavin Shan phb->model = PNV_PHB_MODEL_PHB3; 3105cee72d5bSBenjamin Herrenschmidt else 3106cee72d5bSBenjamin Herrenschmidt phb->model = PNV_PHB_MODEL_UNKNOWN; 3107cee72d5bSBenjamin Herrenschmidt 3108aa0c033fSGavin Shan /* Parse 32-bit and IO ranges (if any) */ 31092f1ec02eSGavin Shan pci_process_bridge_OF_ranges(hose, np, !hose->global_number); 3110184cd4a3SBenjamin Herrenschmidt 3111aa0c033fSGavin Shan /* Get registers */ 3112184cd4a3SBenjamin Herrenschmidt phb->regs = of_iomap(np, 0); 3113184cd4a3SBenjamin Herrenschmidt if (phb->regs == NULL) 3114184cd4a3SBenjamin Herrenschmidt pr_err(" Failed to map registers !\n"); 3115184cd4a3SBenjamin Herrenschmidt 3116184cd4a3SBenjamin Herrenschmidt /* Initialize more IODA stuff */ 3117aa0c033fSGavin Shan phb->ioda.total_pe = 1; 311836954dc7SGavin Shan prop32 = of_get_property(np, "ibm,opal-num-pes", NULL); 311936954dc7SGavin Shan if (prop32) 31203a1a4661SBenjamin Herrenschmidt phb->ioda.total_pe = be32_to_cpup(prop32); 312136954dc7SGavin Shan prop32 = of_get_property(np, "ibm,opal-reserved-pe", NULL); 312236954dc7SGavin Shan if (prop32) 312336954dc7SGavin Shan phb->ioda.reserved_pe = be32_to_cpup(prop32); 3124262af557SGuo Chao 3125262af557SGuo Chao /* Parse 64-bit MMIO range */ 3126262af557SGuo Chao pnv_ioda_parse_m64_window(phb); 3127262af557SGuo Chao 3128184cd4a3SBenjamin Herrenschmidt phb->ioda.m32_size = resource_size(&hose->mem_resources[0]); 3129aa0c033fSGavin Shan /* FW Has already off top 64k of M32 space (MSI space) */ 3130184cd4a3SBenjamin Herrenschmidt phb->ioda.m32_size += 0x10000; 3131184cd4a3SBenjamin Herrenschmidt 3132184cd4a3SBenjamin Herrenschmidt phb->ioda.m32_segsize = phb->ioda.m32_size / phb->ioda.total_pe; 31333fd47f06SBenjamin Herrenschmidt phb->ioda.m32_pci_base = hose->mem_resources[0].start - hose->mem_offset[0]; 3134184cd4a3SBenjamin Herrenschmidt phb->ioda.io_size = hose->pci_io_size; 3135184cd4a3SBenjamin Herrenschmidt phb->ioda.io_segsize = phb->ioda.io_size / phb->ioda.total_pe; 3136184cd4a3SBenjamin Herrenschmidt phb->ioda.io_pci_base = 0; /* XXX calculate this ? */ 3137184cd4a3SBenjamin Herrenschmidt 3138c35d2a8cSGavin Shan /* Allocate aux data & arrays. We don't have IO ports on PHB3 */ 3139184cd4a3SBenjamin Herrenschmidt size = _ALIGN_UP(phb->ioda.total_pe / 8, sizeof(unsigned long)); 3140184cd4a3SBenjamin Herrenschmidt m32map_off = size; 3141e47747f4SGavin Shan size += phb->ioda.total_pe * sizeof(phb->ioda.m32_segmap[0]); 3142c35d2a8cSGavin Shan if (phb->type == PNV_PHB_IODA1) { 3143c35d2a8cSGavin Shan iomap_off = size; 3144e47747f4SGavin Shan size += phb->ioda.total_pe * sizeof(phb->ioda.io_segmap[0]); 3145c35d2a8cSGavin Shan } 3146184cd4a3SBenjamin Herrenschmidt pemap_off = size; 3147184cd4a3SBenjamin Herrenschmidt size += phb->ioda.total_pe * sizeof(struct pnv_ioda_pe); 3148e39f223fSMichael Ellerman aux = memblock_virt_alloc(size, 0); 3149184cd4a3SBenjamin Herrenschmidt phb->ioda.pe_alloc = aux; 3150184cd4a3SBenjamin Herrenschmidt phb->ioda.m32_segmap = aux + m32map_off; 3151c35d2a8cSGavin Shan if (phb->type == PNV_PHB_IODA1) 3152184cd4a3SBenjamin Herrenschmidt phb->ioda.io_segmap = aux + iomap_off; 3153184cd4a3SBenjamin Herrenschmidt phb->ioda.pe_array = aux + pemap_off; 315436954dc7SGavin Shan set_bit(phb->ioda.reserved_pe, phb->ioda.pe_alloc); 3155184cd4a3SBenjamin Herrenschmidt 31567ebdf956SGavin Shan INIT_LIST_HEAD(&phb->ioda.pe_dma_list); 3157184cd4a3SBenjamin Herrenschmidt INIT_LIST_HEAD(&phb->ioda.pe_list); 3158781a868fSWei Yang mutex_init(&phb->ioda.pe_list_mutex); 3159184cd4a3SBenjamin Herrenschmidt 3160184cd4a3SBenjamin Herrenschmidt /* Calculate how many 32-bit TCE segments we have */ 3161184cd4a3SBenjamin Herrenschmidt phb->ioda.tce32_count = phb->ioda.m32_pci_base >> 28; 3162184cd4a3SBenjamin Herrenschmidt 3163aa0c033fSGavin Shan #if 0 /* We should really do that ... */ 3164184cd4a3SBenjamin Herrenschmidt rc = opal_pci_set_phb_mem_window(opal->phb_id, 3165184cd4a3SBenjamin Herrenschmidt window_type, 3166184cd4a3SBenjamin Herrenschmidt window_num, 3167184cd4a3SBenjamin Herrenschmidt starting_real_address, 3168184cd4a3SBenjamin Herrenschmidt starting_pci_address, 3169184cd4a3SBenjamin Herrenschmidt segment_size); 3170184cd4a3SBenjamin Herrenschmidt #endif 3171184cd4a3SBenjamin Herrenschmidt 3172262af557SGuo Chao pr_info(" %03d (%03d) PE's M32: 0x%x [segment=0x%x]\n", 3173262af557SGuo Chao phb->ioda.total_pe, phb->ioda.reserved_pe, 3174262af557SGuo Chao phb->ioda.m32_size, phb->ioda.m32_segsize); 3175262af557SGuo Chao if (phb->ioda.m64_size) 3176262af557SGuo Chao pr_info(" M64: 0x%lx [segment=0x%lx]\n", 3177262af557SGuo Chao phb->ioda.m64_size, phb->ioda.m64_segsize); 3178262af557SGuo Chao if (phb->ioda.io_size) 3179262af557SGuo Chao pr_info(" IO: 0x%x [segment=0x%x]\n", 3180184cd4a3SBenjamin Herrenschmidt phb->ioda.io_size, phb->ioda.io_segsize); 3181184cd4a3SBenjamin Herrenschmidt 3182262af557SGuo Chao 3183184cd4a3SBenjamin Herrenschmidt phb->hose->ops = &pnv_pci_ops; 318449dec922SGavin Shan phb->get_pe_state = pnv_ioda_get_pe_state; 318549dec922SGavin Shan phb->freeze_pe = pnv_ioda_freeze_pe; 318649dec922SGavin Shan phb->unfreeze_pe = pnv_ioda_unfreeze_pe; 3187184cd4a3SBenjamin Herrenschmidt 3188184cd4a3SBenjamin Herrenschmidt /* Setup RID -> PE mapping function */ 3189184cd4a3SBenjamin Herrenschmidt phb->bdfn_to_pe = pnv_ioda_bdfn_to_pe; 3190184cd4a3SBenjamin Herrenschmidt 3191184cd4a3SBenjamin Herrenschmidt /* Setup TCEs */ 3192184cd4a3SBenjamin Herrenschmidt phb->dma_dev_setup = pnv_pci_ioda_dma_dev_setup; 3193184cd4a3SBenjamin Herrenschmidt 3194184cd4a3SBenjamin Herrenschmidt /* Setup MSI support */ 3195184cd4a3SBenjamin Herrenschmidt pnv_pci_init_ioda_msis(phb); 3196184cd4a3SBenjamin Herrenschmidt 3197c40a4210SGavin Shan /* 3198c40a4210SGavin Shan * We pass the PCI probe flag PCI_REASSIGN_ALL_RSRC here 3199c40a4210SGavin Shan * to let the PCI core do resource assignment. It's supposed 3200c40a4210SGavin Shan * that the PCI core will do correct I/O and MMIO alignment 3201c40a4210SGavin Shan * for the P2P bridge bars so that each PCI bus (excluding 3202c40a4210SGavin Shan * the child P2P bridges) can form individual PE. 3203184cd4a3SBenjamin Herrenschmidt */ 3204fb446ad0SGavin Shan ppc_md.pcibios_fixup = pnv_pci_ioda_fixup; 320592ae0353SDaniel Axtens hose->controller_ops = pnv_pci_ioda_controller_ops; 3206ad30cb99SMichael Ellerman 32076e628c7dSWei Yang #ifdef CONFIG_PCI_IOV 32086e628c7dSWei Yang ppc_md.pcibios_fixup_sriov = pnv_pci_ioda_fixup_iov_resources; 32095350ab3fSWei Yang ppc_md.pcibios_iov_resource_alignment = pnv_pci_iov_resource_alignment; 3210ad30cb99SMichael Ellerman #endif 3211ad30cb99SMichael Ellerman 3212c40a4210SGavin Shan pci_add_flags(PCI_REASSIGN_ALL_RSRC); 3213184cd4a3SBenjamin Herrenschmidt 3214184cd4a3SBenjamin Herrenschmidt /* Reset IODA tables to a clean state */ 3215d1a85eeeSGavin Shan rc = opal_pci_reset(phb_id, OPAL_RESET_PCI_IODA_TABLE, OPAL_ASSERT_RESET); 3216184cd4a3SBenjamin Herrenschmidt if (rc) 3217f11fe552SBenjamin Herrenschmidt pr_warning(" OPAL Error %ld performing IODA table reset !\n", rc); 3218361f2a2aSGavin Shan 3219361f2a2aSGavin Shan /* If we're running in kdump kerenl, the previous kerenl never 3220361f2a2aSGavin Shan * shutdown PCI devices correctly. We already got IODA table 3221361f2a2aSGavin Shan * cleaned out. So we have to issue PHB reset to stop all PCI 3222361f2a2aSGavin Shan * transactions from previous kerenl. 3223361f2a2aSGavin Shan */ 3224361f2a2aSGavin Shan if (is_kdump_kernel()) { 3225361f2a2aSGavin Shan pr_info(" Issue PHB reset ...\n"); 3226cadf364dSGavin Shan pnv_eeh_phb_reset(hose, EEH_RESET_FUNDAMENTAL); 3227cadf364dSGavin Shan pnv_eeh_phb_reset(hose, EEH_RESET_DEACTIVATE); 3228361f2a2aSGavin Shan } 3229262af557SGuo Chao 32309e9e8935SGavin Shan /* Remove M64 resource if we can't configure it successfully */ 32319e9e8935SGavin Shan if (!phb->init_m64 || phb->init_m64(phb)) 3232262af557SGuo Chao hose->mem_resources[1].flags = 0; 3233184cd4a3SBenjamin Herrenschmidt } 3234184cd4a3SBenjamin Herrenschmidt 323567975005SBjorn Helgaas void __init pnv_pci_init_ioda2_phb(struct device_node *np) 3236aa0c033fSGavin Shan { 3237e9cc17d4SGavin Shan pnv_pci_init_ioda_phb(np, 0, PNV_PHB_IODA2); 3238aa0c033fSGavin Shan } 3239aa0c033fSGavin Shan 3240184cd4a3SBenjamin Herrenschmidt void __init pnv_pci_init_ioda_hub(struct device_node *np) 3241184cd4a3SBenjamin Herrenschmidt { 3242184cd4a3SBenjamin Herrenschmidt struct device_node *phbn; 3243c681b93cSAlistair Popple const __be64 *prop64; 3244184cd4a3SBenjamin Herrenschmidt u64 hub_id; 3245184cd4a3SBenjamin Herrenschmidt 3246184cd4a3SBenjamin Herrenschmidt pr_info("Probing IODA IO-Hub %s\n", np->full_name); 3247184cd4a3SBenjamin Herrenschmidt 3248184cd4a3SBenjamin Herrenschmidt prop64 = of_get_property(np, "ibm,opal-hubid", NULL); 3249184cd4a3SBenjamin Herrenschmidt if (!prop64) { 3250184cd4a3SBenjamin Herrenschmidt pr_err(" Missing \"ibm,opal-hubid\" property !\n"); 3251184cd4a3SBenjamin Herrenschmidt return; 3252184cd4a3SBenjamin Herrenschmidt } 3253184cd4a3SBenjamin Herrenschmidt hub_id = be64_to_cpup(prop64); 3254184cd4a3SBenjamin Herrenschmidt pr_devel(" HUB-ID : 0x%016llx\n", hub_id); 3255184cd4a3SBenjamin Herrenschmidt 3256184cd4a3SBenjamin Herrenschmidt /* Count child PHBs */ 3257184cd4a3SBenjamin Herrenschmidt for_each_child_of_node(np, phbn) { 3258184cd4a3SBenjamin Herrenschmidt /* Look for IODA1 PHBs */ 3259184cd4a3SBenjamin Herrenschmidt if (of_device_is_compatible(phbn, "ibm,ioda-phb")) 3260e9cc17d4SGavin Shan pnv_pci_init_ioda_phb(phbn, hub_id, PNV_PHB_IODA1); 3261184cd4a3SBenjamin Herrenschmidt } 3262184cd4a3SBenjamin Herrenschmidt } 3263