1184cd4a3SBenjamin Herrenschmidt /* 2184cd4a3SBenjamin Herrenschmidt * Support PCI/PCIe on PowerNV platforms 3184cd4a3SBenjamin Herrenschmidt * 4184cd4a3SBenjamin Herrenschmidt * Copyright 2011 Benjamin Herrenschmidt, IBM Corp. 5184cd4a3SBenjamin Herrenschmidt * 6184cd4a3SBenjamin Herrenschmidt * This program is free software; you can redistribute it and/or 7184cd4a3SBenjamin Herrenschmidt * modify it under the terms of the GNU General Public License 8184cd4a3SBenjamin Herrenschmidt * as published by the Free Software Foundation; either version 9184cd4a3SBenjamin Herrenschmidt * 2 of the License, or (at your option) any later version. 10184cd4a3SBenjamin Herrenschmidt */ 11184cd4a3SBenjamin Herrenschmidt 12cee72d5bSBenjamin Herrenschmidt #undef DEBUG 13184cd4a3SBenjamin Herrenschmidt 14184cd4a3SBenjamin Herrenschmidt #include <linux/kernel.h> 15184cd4a3SBenjamin Herrenschmidt #include <linux/pci.h> 16361f2a2aSGavin Shan #include <linux/crash_dump.h> 1737c367f2SGavin Shan #include <linux/debugfs.h> 18184cd4a3SBenjamin Herrenschmidt #include <linux/delay.h> 19184cd4a3SBenjamin Herrenschmidt #include <linux/string.h> 20184cd4a3SBenjamin Herrenschmidt #include <linux/init.h> 21184cd4a3SBenjamin Herrenschmidt #include <linux/bootmem.h> 22184cd4a3SBenjamin Herrenschmidt #include <linux/irq.h> 23184cd4a3SBenjamin Herrenschmidt #include <linux/io.h> 24184cd4a3SBenjamin Herrenschmidt #include <linux/msi.h> 25cd15b048SBenjamin Herrenschmidt #include <linux/memblock.h> 26ac9a5889SAlexey Kardashevskiy #include <linux/iommu.h> 27e57080f1SAlexey Kardashevskiy #include <linux/rculist.h> 28184cd4a3SBenjamin Herrenschmidt 29184cd4a3SBenjamin Herrenschmidt #include <asm/sections.h> 30184cd4a3SBenjamin Herrenschmidt #include <asm/io.h> 31184cd4a3SBenjamin Herrenschmidt #include <asm/prom.h> 32184cd4a3SBenjamin Herrenschmidt #include <asm/pci-bridge.h> 33184cd4a3SBenjamin Herrenschmidt #include <asm/machdep.h> 34fb1b55d6SGavin Shan #include <asm/msi_bitmap.h> 35184cd4a3SBenjamin Herrenschmidt #include <asm/ppc-pci.h> 36184cd4a3SBenjamin Herrenschmidt #include <asm/opal.h> 37184cd4a3SBenjamin Herrenschmidt #include <asm/iommu.h> 38184cd4a3SBenjamin Herrenschmidt #include <asm/tce.h> 39137436c9SGavin Shan #include <asm/xics.h> 4037c367f2SGavin Shan #include <asm/debug.h> 41262af557SGuo Chao #include <asm/firmware.h> 4280c49c7eSIan Munsie #include <asm/pnv-pci.h> 4380c49c7eSIan Munsie 44ec249dd8SMichael Neuling #include <misc/cxl-base.h> 45184cd4a3SBenjamin Herrenschmidt 46184cd4a3SBenjamin Herrenschmidt #include "powernv.h" 47184cd4a3SBenjamin Herrenschmidt #include "pci.h" 48184cd4a3SBenjamin Herrenschmidt 49781a868fSWei Yang /* 256M DMA window, 4K TCE pages, 8 bytes TCE */ 50781a868fSWei Yang #define TCE32_TABLE_SIZE ((0x10000000 / 0x1000) * 8) 51781a868fSWei Yang 526d31c2faSJoe Perches static void pe_level_printk(const struct pnv_ioda_pe *pe, const char *level, 536d31c2faSJoe Perches const char *fmt, ...) 546d31c2faSJoe Perches { 556d31c2faSJoe Perches struct va_format vaf; 566d31c2faSJoe Perches va_list args; 576d31c2faSJoe Perches char pfix[32]; 58184cd4a3SBenjamin Herrenschmidt 596d31c2faSJoe Perches va_start(args, fmt); 606d31c2faSJoe Perches 616d31c2faSJoe Perches vaf.fmt = fmt; 626d31c2faSJoe Perches vaf.va = &args; 636d31c2faSJoe Perches 64781a868fSWei Yang if (pe->flags & PNV_IODA_PE_DEV) 656d31c2faSJoe Perches strlcpy(pfix, dev_name(&pe->pdev->dev), sizeof(pfix)); 66781a868fSWei Yang else if (pe->flags & (PNV_IODA_PE_BUS | PNV_IODA_PE_BUS_ALL)) 676d31c2faSJoe Perches sprintf(pfix, "%04x:%02x ", 686d31c2faSJoe Perches pci_domain_nr(pe->pbus), pe->pbus->number); 69781a868fSWei Yang #ifdef CONFIG_PCI_IOV 70781a868fSWei Yang else if (pe->flags & PNV_IODA_PE_VF) 71781a868fSWei Yang sprintf(pfix, "%04x:%02x:%2x.%d", 72781a868fSWei Yang pci_domain_nr(pe->parent_dev->bus), 73781a868fSWei Yang (pe->rid & 0xff00) >> 8, 74781a868fSWei Yang PCI_SLOT(pe->rid), PCI_FUNC(pe->rid)); 75781a868fSWei Yang #endif /* CONFIG_PCI_IOV*/ 766d31c2faSJoe Perches 776d31c2faSJoe Perches printk("%spci %s: [PE# %.3d] %pV", 786d31c2faSJoe Perches level, pfix, pe->pe_number, &vaf); 796d31c2faSJoe Perches 806d31c2faSJoe Perches va_end(args); 816d31c2faSJoe Perches } 826d31c2faSJoe Perches 836d31c2faSJoe Perches #define pe_err(pe, fmt, ...) \ 846d31c2faSJoe Perches pe_level_printk(pe, KERN_ERR, fmt, ##__VA_ARGS__) 856d31c2faSJoe Perches #define pe_warn(pe, fmt, ...) \ 866d31c2faSJoe Perches pe_level_printk(pe, KERN_WARNING, fmt, ##__VA_ARGS__) 876d31c2faSJoe Perches #define pe_info(pe, fmt, ...) \ 886d31c2faSJoe Perches pe_level_printk(pe, KERN_INFO, fmt, ##__VA_ARGS__) 89184cd4a3SBenjamin Herrenschmidt 904e287840SThadeu Lima de Souza Cascardo static bool pnv_iommu_bypass_disabled __read_mostly; 914e287840SThadeu Lima de Souza Cascardo 924e287840SThadeu Lima de Souza Cascardo static int __init iommu_setup(char *str) 934e287840SThadeu Lima de Souza Cascardo { 944e287840SThadeu Lima de Souza Cascardo if (!str) 954e287840SThadeu Lima de Souza Cascardo return -EINVAL; 964e287840SThadeu Lima de Souza Cascardo 974e287840SThadeu Lima de Souza Cascardo while (*str) { 984e287840SThadeu Lima de Souza Cascardo if (!strncmp(str, "nobypass", 8)) { 994e287840SThadeu Lima de Souza Cascardo pnv_iommu_bypass_disabled = true; 1004e287840SThadeu Lima de Souza Cascardo pr_info("PowerNV: IOMMU bypass window disabled.\n"); 1014e287840SThadeu Lima de Souza Cascardo break; 1024e287840SThadeu Lima de Souza Cascardo } 1034e287840SThadeu Lima de Souza Cascardo str += strcspn(str, ","); 1044e287840SThadeu Lima de Souza Cascardo if (*str == ',') 1054e287840SThadeu Lima de Souza Cascardo str++; 1064e287840SThadeu Lima de Souza Cascardo } 1074e287840SThadeu Lima de Souza Cascardo 1084e287840SThadeu Lima de Souza Cascardo return 0; 1094e287840SThadeu Lima de Souza Cascardo } 1104e287840SThadeu Lima de Souza Cascardo early_param("iommu", iommu_setup); 1114e287840SThadeu Lima de Souza Cascardo 1128e0a1611SAlexey Kardashevskiy /* 1138e0a1611SAlexey Kardashevskiy * stdcix is only supposed to be used in hypervisor real mode as per 1148e0a1611SAlexey Kardashevskiy * the architecture spec 1158e0a1611SAlexey Kardashevskiy */ 1168e0a1611SAlexey Kardashevskiy static inline void __raw_rm_writeq(u64 val, volatile void __iomem *paddr) 1178e0a1611SAlexey Kardashevskiy { 1188e0a1611SAlexey Kardashevskiy __asm__ __volatile__("stdcix %0,0,%1" 1198e0a1611SAlexey Kardashevskiy : : "r" (val), "r" (paddr) : "memory"); 1208e0a1611SAlexey Kardashevskiy } 1218e0a1611SAlexey Kardashevskiy 122262af557SGuo Chao static inline bool pnv_pci_is_mem_pref_64(unsigned long flags) 123262af557SGuo Chao { 124262af557SGuo Chao return ((flags & (IORESOURCE_MEM_64 | IORESOURCE_PREFETCH)) == 125262af557SGuo Chao (IORESOURCE_MEM_64 | IORESOURCE_PREFETCH)); 126262af557SGuo Chao } 127262af557SGuo Chao 1284b82ab18SGavin Shan static void pnv_ioda_reserve_pe(struct pnv_phb *phb, int pe_no) 1294b82ab18SGavin Shan { 1304b82ab18SGavin Shan if (!(pe_no >= 0 && pe_no < phb->ioda.total_pe)) { 1314b82ab18SGavin Shan pr_warn("%s: Invalid PE %d on PHB#%x\n", 1324b82ab18SGavin Shan __func__, pe_no, phb->hose->global_number); 1334b82ab18SGavin Shan return; 1344b82ab18SGavin Shan } 1354b82ab18SGavin Shan 1364b82ab18SGavin Shan if (test_and_set_bit(pe_no, phb->ioda.pe_alloc)) { 1374b82ab18SGavin Shan pr_warn("%s: PE %d was assigned on PHB#%x\n", 1384b82ab18SGavin Shan __func__, pe_no, phb->hose->global_number); 1394b82ab18SGavin Shan return; 1404b82ab18SGavin Shan } 1414b82ab18SGavin Shan 1424b82ab18SGavin Shan phb->ioda.pe_array[pe_no].phb = phb; 1434b82ab18SGavin Shan phb->ioda.pe_array[pe_no].pe_number = pe_no; 1444b82ab18SGavin Shan } 1454b82ab18SGavin Shan 146cad5cef6SGreg Kroah-Hartman static int pnv_ioda_alloc_pe(struct pnv_phb *phb) 147184cd4a3SBenjamin Herrenschmidt { 148184cd4a3SBenjamin Herrenschmidt unsigned long pe; 149184cd4a3SBenjamin Herrenschmidt 150184cd4a3SBenjamin Herrenschmidt do { 151184cd4a3SBenjamin Herrenschmidt pe = find_next_zero_bit(phb->ioda.pe_alloc, 152184cd4a3SBenjamin Herrenschmidt phb->ioda.total_pe, 0); 153184cd4a3SBenjamin Herrenschmidt if (pe >= phb->ioda.total_pe) 154184cd4a3SBenjamin Herrenschmidt return IODA_INVALID_PE; 155184cd4a3SBenjamin Herrenschmidt } while(test_and_set_bit(pe, phb->ioda.pe_alloc)); 156184cd4a3SBenjamin Herrenschmidt 1574cce9550SGavin Shan phb->ioda.pe_array[pe].phb = phb; 158184cd4a3SBenjamin Herrenschmidt phb->ioda.pe_array[pe].pe_number = pe; 159184cd4a3SBenjamin Herrenschmidt return pe; 160184cd4a3SBenjamin Herrenschmidt } 161184cd4a3SBenjamin Herrenschmidt 162cad5cef6SGreg Kroah-Hartman static void pnv_ioda_free_pe(struct pnv_phb *phb, int pe) 163184cd4a3SBenjamin Herrenschmidt { 164184cd4a3SBenjamin Herrenschmidt WARN_ON(phb->ioda.pe_array[pe].pdev); 165184cd4a3SBenjamin Herrenschmidt 166184cd4a3SBenjamin Herrenschmidt memset(&phb->ioda.pe_array[pe], 0, sizeof(struct pnv_ioda_pe)); 167184cd4a3SBenjamin Herrenschmidt clear_bit(pe, phb->ioda.pe_alloc); 168184cd4a3SBenjamin Herrenschmidt } 169184cd4a3SBenjamin Herrenschmidt 170262af557SGuo Chao /* The default M64 BAR is shared by all PEs */ 171262af557SGuo Chao static int pnv_ioda2_init_m64(struct pnv_phb *phb) 172262af557SGuo Chao { 173262af557SGuo Chao const char *desc; 174262af557SGuo Chao struct resource *r; 175262af557SGuo Chao s64 rc; 176262af557SGuo Chao 177262af557SGuo Chao /* Configure the default M64 BAR */ 178262af557SGuo Chao rc = opal_pci_set_phb_mem_window(phb->opal_id, 179262af557SGuo Chao OPAL_M64_WINDOW_TYPE, 180262af557SGuo Chao phb->ioda.m64_bar_idx, 181262af557SGuo Chao phb->ioda.m64_base, 182262af557SGuo Chao 0, /* unused */ 183262af557SGuo Chao phb->ioda.m64_size); 184262af557SGuo Chao if (rc != OPAL_SUCCESS) { 185262af557SGuo Chao desc = "configuring"; 186262af557SGuo Chao goto fail; 187262af557SGuo Chao } 188262af557SGuo Chao 189262af557SGuo Chao /* Enable the default M64 BAR */ 190262af557SGuo Chao rc = opal_pci_phb_mmio_enable(phb->opal_id, 191262af557SGuo Chao OPAL_M64_WINDOW_TYPE, 192262af557SGuo Chao phb->ioda.m64_bar_idx, 193262af557SGuo Chao OPAL_ENABLE_M64_SPLIT); 194262af557SGuo Chao if (rc != OPAL_SUCCESS) { 195262af557SGuo Chao desc = "enabling"; 196262af557SGuo Chao goto fail; 197262af557SGuo Chao } 198262af557SGuo Chao 199262af557SGuo Chao /* Mark the M64 BAR assigned */ 200262af557SGuo Chao set_bit(phb->ioda.m64_bar_idx, &phb->ioda.m64_bar_alloc); 201262af557SGuo Chao 202262af557SGuo Chao /* 203262af557SGuo Chao * Strip off the segment used by the reserved PE, which is 204262af557SGuo Chao * expected to be 0 or last one of PE capabicity. 205262af557SGuo Chao */ 206262af557SGuo Chao r = &phb->hose->mem_resources[1]; 207262af557SGuo Chao if (phb->ioda.reserved_pe == 0) 208262af557SGuo Chao r->start += phb->ioda.m64_segsize; 209262af557SGuo Chao else if (phb->ioda.reserved_pe == (phb->ioda.total_pe - 1)) 210262af557SGuo Chao r->end -= phb->ioda.m64_segsize; 211262af557SGuo Chao else 212262af557SGuo Chao pr_warn(" Cannot strip M64 segment for reserved PE#%d\n", 213262af557SGuo Chao phb->ioda.reserved_pe); 214262af557SGuo Chao 215262af557SGuo Chao return 0; 216262af557SGuo Chao 217262af557SGuo Chao fail: 218262af557SGuo Chao pr_warn(" Failure %lld %s M64 BAR#%d\n", 219262af557SGuo Chao rc, desc, phb->ioda.m64_bar_idx); 220262af557SGuo Chao opal_pci_phb_mmio_enable(phb->opal_id, 221262af557SGuo Chao OPAL_M64_WINDOW_TYPE, 222262af557SGuo Chao phb->ioda.m64_bar_idx, 223262af557SGuo Chao OPAL_DISABLE_M64); 224262af557SGuo Chao return -EIO; 225262af557SGuo Chao } 226262af557SGuo Chao 2275ef73567SGavin Shan static void pnv_ioda2_reserve_m64_pe(struct pnv_phb *phb) 228262af557SGuo Chao { 229262af557SGuo Chao resource_size_t sgsz = phb->ioda.m64_segsize; 230262af557SGuo Chao struct pci_dev *pdev; 231262af557SGuo Chao struct resource *r; 232262af557SGuo Chao int base, step, i; 233262af557SGuo Chao 234262af557SGuo Chao /* 235262af557SGuo Chao * Root bus always has full M64 range and root port has 236262af557SGuo Chao * M64 range used in reality. So we're checking root port 237262af557SGuo Chao * instead of root bus. 238262af557SGuo Chao */ 239262af557SGuo Chao list_for_each_entry(pdev, &phb->hose->bus->devices, bus_list) { 2404b82ab18SGavin Shan for (i = 0; i < PCI_BRIDGE_RESOURCE_NUM; i++) { 2414b82ab18SGavin Shan r = &pdev->resource[PCI_BRIDGE_RESOURCES + i]; 242262af557SGuo Chao if (!r->parent || 243262af557SGuo Chao !pnv_pci_is_mem_pref_64(r->flags)) 244262af557SGuo Chao continue; 245262af557SGuo Chao 246262af557SGuo Chao base = (r->start - phb->ioda.m64_base) / sgsz; 247262af557SGuo Chao for (step = 0; step < resource_size(r) / sgsz; step++) 2484b82ab18SGavin Shan pnv_ioda_reserve_pe(phb, base + step); 249262af557SGuo Chao } 250262af557SGuo Chao } 251262af557SGuo Chao } 252262af557SGuo Chao 253262af557SGuo Chao static int pnv_ioda2_pick_m64_pe(struct pnv_phb *phb, 254262af557SGuo Chao struct pci_bus *bus, int all) 255262af557SGuo Chao { 256262af557SGuo Chao resource_size_t segsz = phb->ioda.m64_segsize; 257262af557SGuo Chao struct pci_dev *pdev; 258262af557SGuo Chao struct resource *r; 259262af557SGuo Chao struct pnv_ioda_pe *master_pe, *pe; 260262af557SGuo Chao unsigned long size, *pe_alloc; 261262af557SGuo Chao bool found; 262262af557SGuo Chao int start, i, j; 263262af557SGuo Chao 264262af557SGuo Chao /* Root bus shouldn't use M64 */ 265262af557SGuo Chao if (pci_is_root_bus(bus)) 266262af557SGuo Chao return IODA_INVALID_PE; 267262af557SGuo Chao 268262af557SGuo Chao /* We support only one M64 window on each bus */ 269262af557SGuo Chao found = false; 270262af557SGuo Chao pci_bus_for_each_resource(bus, r, i) { 271262af557SGuo Chao if (r && r->parent && 272262af557SGuo Chao pnv_pci_is_mem_pref_64(r->flags)) { 273262af557SGuo Chao found = true; 274262af557SGuo Chao break; 275262af557SGuo Chao } 276262af557SGuo Chao } 277262af557SGuo Chao 278262af557SGuo Chao /* No M64 window found ? */ 279262af557SGuo Chao if (!found) 280262af557SGuo Chao return IODA_INVALID_PE; 281262af557SGuo Chao 282262af557SGuo Chao /* Allocate bitmap */ 283262af557SGuo Chao size = _ALIGN_UP(phb->ioda.total_pe / 8, sizeof(unsigned long)); 284262af557SGuo Chao pe_alloc = kzalloc(size, GFP_KERNEL); 285262af557SGuo Chao if (!pe_alloc) { 286262af557SGuo Chao pr_warn("%s: Out of memory !\n", 287262af557SGuo Chao __func__); 288262af557SGuo Chao return IODA_INVALID_PE; 289262af557SGuo Chao } 290262af557SGuo Chao 291262af557SGuo Chao /* 292262af557SGuo Chao * Figure out reserved PE numbers by the PE 293262af557SGuo Chao * the its child PEs. 294262af557SGuo Chao */ 295262af557SGuo Chao start = (r->start - phb->ioda.m64_base) / segsz; 296262af557SGuo Chao for (i = 0; i < resource_size(r) / segsz; i++) 297262af557SGuo Chao set_bit(start + i, pe_alloc); 298262af557SGuo Chao 299262af557SGuo Chao if (all) 300262af557SGuo Chao goto done; 301262af557SGuo Chao 302262af557SGuo Chao /* 303262af557SGuo Chao * If the PE doesn't cover all subordinate buses, 304262af557SGuo Chao * we need subtract from reserved PEs for children. 305262af557SGuo Chao */ 306262af557SGuo Chao list_for_each_entry(pdev, &bus->devices, bus_list) { 307262af557SGuo Chao if (!pdev->subordinate) 308262af557SGuo Chao continue; 309262af557SGuo Chao 310262af557SGuo Chao pci_bus_for_each_resource(pdev->subordinate, r, i) { 311262af557SGuo Chao if (!r || !r->parent || 312262af557SGuo Chao !pnv_pci_is_mem_pref_64(r->flags)) 313262af557SGuo Chao continue; 314262af557SGuo Chao 315262af557SGuo Chao start = (r->start - phb->ioda.m64_base) / segsz; 316262af557SGuo Chao for (j = 0; j < resource_size(r) / segsz ; j++) 317262af557SGuo Chao clear_bit(start + j, pe_alloc); 318262af557SGuo Chao } 319262af557SGuo Chao } 320262af557SGuo Chao 321262af557SGuo Chao /* 322262af557SGuo Chao * the current bus might not own M64 window and that's all 323262af557SGuo Chao * contributed by its child buses. For the case, we needn't 324262af557SGuo Chao * pick M64 dependent PE#. 325262af557SGuo Chao */ 326262af557SGuo Chao if (bitmap_empty(pe_alloc, phb->ioda.total_pe)) { 327262af557SGuo Chao kfree(pe_alloc); 328262af557SGuo Chao return IODA_INVALID_PE; 329262af557SGuo Chao } 330262af557SGuo Chao 331262af557SGuo Chao /* 332262af557SGuo Chao * Figure out the master PE and put all slave PEs to master 333262af557SGuo Chao * PE's list to form compound PE. 334262af557SGuo Chao */ 335262af557SGuo Chao done: 336262af557SGuo Chao master_pe = NULL; 337262af557SGuo Chao i = -1; 338262af557SGuo Chao while ((i = find_next_bit(pe_alloc, phb->ioda.total_pe, i + 1)) < 339262af557SGuo Chao phb->ioda.total_pe) { 340262af557SGuo Chao pe = &phb->ioda.pe_array[i]; 341262af557SGuo Chao 342262af557SGuo Chao if (!master_pe) { 343262af557SGuo Chao pe->flags |= PNV_IODA_PE_MASTER; 344262af557SGuo Chao INIT_LIST_HEAD(&pe->slaves); 345262af557SGuo Chao master_pe = pe; 346262af557SGuo Chao } else { 347262af557SGuo Chao pe->flags |= PNV_IODA_PE_SLAVE; 348262af557SGuo Chao pe->master = master_pe; 349262af557SGuo Chao list_add_tail(&pe->list, &master_pe->slaves); 350262af557SGuo Chao } 351262af557SGuo Chao } 352262af557SGuo Chao 353262af557SGuo Chao kfree(pe_alloc); 354262af557SGuo Chao return master_pe->pe_number; 355262af557SGuo Chao } 356262af557SGuo Chao 357262af557SGuo Chao static void __init pnv_ioda_parse_m64_window(struct pnv_phb *phb) 358262af557SGuo Chao { 359262af557SGuo Chao struct pci_controller *hose = phb->hose; 360262af557SGuo Chao struct device_node *dn = hose->dn; 361262af557SGuo Chao struct resource *res; 362262af557SGuo Chao const u32 *r; 363262af557SGuo Chao u64 pci_addr; 364262af557SGuo Chao 3651665c4a8SGavin Shan /* FIXME: Support M64 for P7IOC */ 3661665c4a8SGavin Shan if (phb->type != PNV_PHB_IODA2) { 3671665c4a8SGavin Shan pr_info(" Not support M64 window\n"); 3681665c4a8SGavin Shan return; 3691665c4a8SGavin Shan } 3701665c4a8SGavin Shan 371262af557SGuo Chao if (!firmware_has_feature(FW_FEATURE_OPALv3)) { 372262af557SGuo Chao pr_info(" Firmware too old to support M64 window\n"); 373262af557SGuo Chao return; 374262af557SGuo Chao } 375262af557SGuo Chao 376262af557SGuo Chao r = of_get_property(dn, "ibm,opal-m64-window", NULL); 377262af557SGuo Chao if (!r) { 378262af557SGuo Chao pr_info(" No <ibm,opal-m64-window> on %s\n", 379262af557SGuo Chao dn->full_name); 380262af557SGuo Chao return; 381262af557SGuo Chao } 382262af557SGuo Chao 383262af557SGuo Chao res = &hose->mem_resources[1]; 384262af557SGuo Chao res->start = of_translate_address(dn, r + 2); 385262af557SGuo Chao res->end = res->start + of_read_number(r + 4, 2) - 1; 386262af557SGuo Chao res->flags = (IORESOURCE_MEM | IORESOURCE_MEM_64 | IORESOURCE_PREFETCH); 387262af557SGuo Chao pci_addr = of_read_number(r, 2); 388262af557SGuo Chao hose->mem_offset[1] = res->start - pci_addr; 389262af557SGuo Chao 390262af557SGuo Chao phb->ioda.m64_size = resource_size(res); 391262af557SGuo Chao phb->ioda.m64_segsize = phb->ioda.m64_size / phb->ioda.total_pe; 392262af557SGuo Chao phb->ioda.m64_base = pci_addr; 393262af557SGuo Chao 394e9863e68SWei Yang pr_info(" MEM64 0x%016llx..0x%016llx -> 0x%016llx\n", 395e9863e68SWei Yang res->start, res->end, pci_addr); 396e9863e68SWei Yang 397262af557SGuo Chao /* Use last M64 BAR to cover M64 window */ 398262af557SGuo Chao phb->ioda.m64_bar_idx = 15; 399262af557SGuo Chao phb->init_m64 = pnv_ioda2_init_m64; 4005ef73567SGavin Shan phb->reserve_m64_pe = pnv_ioda2_reserve_m64_pe; 401262af557SGuo Chao phb->pick_m64_pe = pnv_ioda2_pick_m64_pe; 402262af557SGuo Chao } 403262af557SGuo Chao 40449dec922SGavin Shan static void pnv_ioda_freeze_pe(struct pnv_phb *phb, int pe_no) 40549dec922SGavin Shan { 40649dec922SGavin Shan struct pnv_ioda_pe *pe = &phb->ioda.pe_array[pe_no]; 40749dec922SGavin Shan struct pnv_ioda_pe *slave; 40849dec922SGavin Shan s64 rc; 40949dec922SGavin Shan 41049dec922SGavin Shan /* Fetch master PE */ 41149dec922SGavin Shan if (pe->flags & PNV_IODA_PE_SLAVE) { 41249dec922SGavin Shan pe = pe->master; 413ec8e4e9dSGavin Shan if (WARN_ON(!pe || !(pe->flags & PNV_IODA_PE_MASTER))) 414ec8e4e9dSGavin Shan return; 415ec8e4e9dSGavin Shan 41649dec922SGavin Shan pe_no = pe->pe_number; 41749dec922SGavin Shan } 41849dec922SGavin Shan 41949dec922SGavin Shan /* Freeze master PE */ 42049dec922SGavin Shan rc = opal_pci_eeh_freeze_set(phb->opal_id, 42149dec922SGavin Shan pe_no, 42249dec922SGavin Shan OPAL_EEH_ACTION_SET_FREEZE_ALL); 42349dec922SGavin Shan if (rc != OPAL_SUCCESS) { 42449dec922SGavin Shan pr_warn("%s: Failure %lld freezing PHB#%x-PE#%x\n", 42549dec922SGavin Shan __func__, rc, phb->hose->global_number, pe_no); 42649dec922SGavin Shan return; 42749dec922SGavin Shan } 42849dec922SGavin Shan 42949dec922SGavin Shan /* Freeze slave PEs */ 43049dec922SGavin Shan if (!(pe->flags & PNV_IODA_PE_MASTER)) 43149dec922SGavin Shan return; 43249dec922SGavin Shan 43349dec922SGavin Shan list_for_each_entry(slave, &pe->slaves, list) { 43449dec922SGavin Shan rc = opal_pci_eeh_freeze_set(phb->opal_id, 43549dec922SGavin Shan slave->pe_number, 43649dec922SGavin Shan OPAL_EEH_ACTION_SET_FREEZE_ALL); 43749dec922SGavin Shan if (rc != OPAL_SUCCESS) 43849dec922SGavin Shan pr_warn("%s: Failure %lld freezing PHB#%x-PE#%x\n", 43949dec922SGavin Shan __func__, rc, phb->hose->global_number, 44049dec922SGavin Shan slave->pe_number); 44149dec922SGavin Shan } 44249dec922SGavin Shan } 44349dec922SGavin Shan 444e51df2c1SAnton Blanchard static int pnv_ioda_unfreeze_pe(struct pnv_phb *phb, int pe_no, int opt) 44549dec922SGavin Shan { 44649dec922SGavin Shan struct pnv_ioda_pe *pe, *slave; 44749dec922SGavin Shan s64 rc; 44849dec922SGavin Shan 44949dec922SGavin Shan /* Find master PE */ 45049dec922SGavin Shan pe = &phb->ioda.pe_array[pe_no]; 45149dec922SGavin Shan if (pe->flags & PNV_IODA_PE_SLAVE) { 45249dec922SGavin Shan pe = pe->master; 45349dec922SGavin Shan WARN_ON(!pe || !(pe->flags & PNV_IODA_PE_MASTER)); 45449dec922SGavin Shan pe_no = pe->pe_number; 45549dec922SGavin Shan } 45649dec922SGavin Shan 45749dec922SGavin Shan /* Clear frozen state for master PE */ 45849dec922SGavin Shan rc = opal_pci_eeh_freeze_clear(phb->opal_id, pe_no, opt); 45949dec922SGavin Shan if (rc != OPAL_SUCCESS) { 46049dec922SGavin Shan pr_warn("%s: Failure %lld clear %d on PHB#%x-PE#%x\n", 46149dec922SGavin Shan __func__, rc, opt, phb->hose->global_number, pe_no); 46249dec922SGavin Shan return -EIO; 46349dec922SGavin Shan } 46449dec922SGavin Shan 46549dec922SGavin Shan if (!(pe->flags & PNV_IODA_PE_MASTER)) 46649dec922SGavin Shan return 0; 46749dec922SGavin Shan 46849dec922SGavin Shan /* Clear frozen state for slave PEs */ 46949dec922SGavin Shan list_for_each_entry(slave, &pe->slaves, list) { 47049dec922SGavin Shan rc = opal_pci_eeh_freeze_clear(phb->opal_id, 47149dec922SGavin Shan slave->pe_number, 47249dec922SGavin Shan opt); 47349dec922SGavin Shan if (rc != OPAL_SUCCESS) { 47449dec922SGavin Shan pr_warn("%s: Failure %lld clear %d on PHB#%x-PE#%x\n", 47549dec922SGavin Shan __func__, rc, opt, phb->hose->global_number, 47649dec922SGavin Shan slave->pe_number); 47749dec922SGavin Shan return -EIO; 47849dec922SGavin Shan } 47949dec922SGavin Shan } 48049dec922SGavin Shan 48149dec922SGavin Shan return 0; 48249dec922SGavin Shan } 48349dec922SGavin Shan 48449dec922SGavin Shan static int pnv_ioda_get_pe_state(struct pnv_phb *phb, int pe_no) 48549dec922SGavin Shan { 48649dec922SGavin Shan struct pnv_ioda_pe *slave, *pe; 48749dec922SGavin Shan u8 fstate, state; 48849dec922SGavin Shan __be16 pcierr; 48949dec922SGavin Shan s64 rc; 49049dec922SGavin Shan 49149dec922SGavin Shan /* Sanity check on PE number */ 49249dec922SGavin Shan if (pe_no < 0 || pe_no >= phb->ioda.total_pe) 49349dec922SGavin Shan return OPAL_EEH_STOPPED_PERM_UNAVAIL; 49449dec922SGavin Shan 49549dec922SGavin Shan /* 49649dec922SGavin Shan * Fetch the master PE and the PE instance might be 49749dec922SGavin Shan * not initialized yet. 49849dec922SGavin Shan */ 49949dec922SGavin Shan pe = &phb->ioda.pe_array[pe_no]; 50049dec922SGavin Shan if (pe->flags & PNV_IODA_PE_SLAVE) { 50149dec922SGavin Shan pe = pe->master; 50249dec922SGavin Shan WARN_ON(!pe || !(pe->flags & PNV_IODA_PE_MASTER)); 50349dec922SGavin Shan pe_no = pe->pe_number; 50449dec922SGavin Shan } 50549dec922SGavin Shan 50649dec922SGavin Shan /* Check the master PE */ 50749dec922SGavin Shan rc = opal_pci_eeh_freeze_status(phb->opal_id, pe_no, 50849dec922SGavin Shan &state, &pcierr, NULL); 50949dec922SGavin Shan if (rc != OPAL_SUCCESS) { 51049dec922SGavin Shan pr_warn("%s: Failure %lld getting " 51149dec922SGavin Shan "PHB#%x-PE#%x state\n", 51249dec922SGavin Shan __func__, rc, 51349dec922SGavin Shan phb->hose->global_number, pe_no); 51449dec922SGavin Shan return OPAL_EEH_STOPPED_TEMP_UNAVAIL; 51549dec922SGavin Shan } 51649dec922SGavin Shan 51749dec922SGavin Shan /* Check the slave PE */ 51849dec922SGavin Shan if (!(pe->flags & PNV_IODA_PE_MASTER)) 51949dec922SGavin Shan return state; 52049dec922SGavin Shan 52149dec922SGavin Shan list_for_each_entry(slave, &pe->slaves, list) { 52249dec922SGavin Shan rc = opal_pci_eeh_freeze_status(phb->opal_id, 52349dec922SGavin Shan slave->pe_number, 52449dec922SGavin Shan &fstate, 52549dec922SGavin Shan &pcierr, 52649dec922SGavin Shan NULL); 52749dec922SGavin Shan if (rc != OPAL_SUCCESS) { 52849dec922SGavin Shan pr_warn("%s: Failure %lld getting " 52949dec922SGavin Shan "PHB#%x-PE#%x state\n", 53049dec922SGavin Shan __func__, rc, 53149dec922SGavin Shan phb->hose->global_number, slave->pe_number); 53249dec922SGavin Shan return OPAL_EEH_STOPPED_TEMP_UNAVAIL; 53349dec922SGavin Shan } 53449dec922SGavin Shan 53549dec922SGavin Shan /* 53649dec922SGavin Shan * Override the result based on the ascending 53749dec922SGavin Shan * priority. 53849dec922SGavin Shan */ 53949dec922SGavin Shan if (fstate > state) 54049dec922SGavin Shan state = fstate; 54149dec922SGavin Shan } 54249dec922SGavin Shan 54349dec922SGavin Shan return state; 54449dec922SGavin Shan } 54549dec922SGavin Shan 546184cd4a3SBenjamin Herrenschmidt /* Currently those 2 are only used when MSIs are enabled, this will change 547184cd4a3SBenjamin Herrenschmidt * but in the meantime, we need to protect them to avoid warnings 548184cd4a3SBenjamin Herrenschmidt */ 549184cd4a3SBenjamin Herrenschmidt #ifdef CONFIG_PCI_MSI 550cad5cef6SGreg Kroah-Hartman static struct pnv_ioda_pe *pnv_ioda_get_pe(struct pci_dev *dev) 551184cd4a3SBenjamin Herrenschmidt { 552184cd4a3SBenjamin Herrenschmidt struct pci_controller *hose = pci_bus_to_host(dev->bus); 553184cd4a3SBenjamin Herrenschmidt struct pnv_phb *phb = hose->private_data; 554b72c1f65SBenjamin Herrenschmidt struct pci_dn *pdn = pci_get_pdn(dev); 555184cd4a3SBenjamin Herrenschmidt 556184cd4a3SBenjamin Herrenschmidt if (!pdn) 557184cd4a3SBenjamin Herrenschmidt return NULL; 558184cd4a3SBenjamin Herrenschmidt if (pdn->pe_number == IODA_INVALID_PE) 559184cd4a3SBenjamin Herrenschmidt return NULL; 560184cd4a3SBenjamin Herrenschmidt return &phb->ioda.pe_array[pdn->pe_number]; 561184cd4a3SBenjamin Herrenschmidt } 562184cd4a3SBenjamin Herrenschmidt #endif /* CONFIG_PCI_MSI */ 563184cd4a3SBenjamin Herrenschmidt 564b131a842SGavin Shan static int pnv_ioda_set_one_peltv(struct pnv_phb *phb, 565b131a842SGavin Shan struct pnv_ioda_pe *parent, 566b131a842SGavin Shan struct pnv_ioda_pe *child, 567b131a842SGavin Shan bool is_add) 568b131a842SGavin Shan { 569b131a842SGavin Shan const char *desc = is_add ? "adding" : "removing"; 570b131a842SGavin Shan uint8_t op = is_add ? OPAL_ADD_PE_TO_DOMAIN : 571b131a842SGavin Shan OPAL_REMOVE_PE_FROM_DOMAIN; 572b131a842SGavin Shan struct pnv_ioda_pe *slave; 573b131a842SGavin Shan long rc; 574b131a842SGavin Shan 575b131a842SGavin Shan /* Parent PE affects child PE */ 576b131a842SGavin Shan rc = opal_pci_set_peltv(phb->opal_id, parent->pe_number, 577b131a842SGavin Shan child->pe_number, op); 578b131a842SGavin Shan if (rc != OPAL_SUCCESS) { 579b131a842SGavin Shan pe_warn(child, "OPAL error %ld %s to parent PELTV\n", 580b131a842SGavin Shan rc, desc); 581b131a842SGavin Shan return -ENXIO; 582b131a842SGavin Shan } 583b131a842SGavin Shan 584b131a842SGavin Shan if (!(child->flags & PNV_IODA_PE_MASTER)) 585b131a842SGavin Shan return 0; 586b131a842SGavin Shan 587b131a842SGavin Shan /* Compound case: parent PE affects slave PEs */ 588b131a842SGavin Shan list_for_each_entry(slave, &child->slaves, list) { 589b131a842SGavin Shan rc = opal_pci_set_peltv(phb->opal_id, parent->pe_number, 590b131a842SGavin Shan slave->pe_number, op); 591b131a842SGavin Shan if (rc != OPAL_SUCCESS) { 592b131a842SGavin Shan pe_warn(slave, "OPAL error %ld %s to parent PELTV\n", 593b131a842SGavin Shan rc, desc); 594b131a842SGavin Shan return -ENXIO; 595b131a842SGavin Shan } 596b131a842SGavin Shan } 597b131a842SGavin Shan 598b131a842SGavin Shan return 0; 599b131a842SGavin Shan } 600b131a842SGavin Shan 601b131a842SGavin Shan static int pnv_ioda_set_peltv(struct pnv_phb *phb, 602b131a842SGavin Shan struct pnv_ioda_pe *pe, 603b131a842SGavin Shan bool is_add) 604b131a842SGavin Shan { 605b131a842SGavin Shan struct pnv_ioda_pe *slave; 606781a868fSWei Yang struct pci_dev *pdev = NULL; 607b131a842SGavin Shan int ret; 608b131a842SGavin Shan 609b131a842SGavin Shan /* 610b131a842SGavin Shan * Clear PE frozen state. If it's master PE, we need 611b131a842SGavin Shan * clear slave PE frozen state as well. 612b131a842SGavin Shan */ 613b131a842SGavin Shan if (is_add) { 614b131a842SGavin Shan opal_pci_eeh_freeze_clear(phb->opal_id, pe->pe_number, 615b131a842SGavin Shan OPAL_EEH_ACTION_CLEAR_FREEZE_ALL); 616b131a842SGavin Shan if (pe->flags & PNV_IODA_PE_MASTER) { 617b131a842SGavin Shan list_for_each_entry(slave, &pe->slaves, list) 618b131a842SGavin Shan opal_pci_eeh_freeze_clear(phb->opal_id, 619b131a842SGavin Shan slave->pe_number, 620b131a842SGavin Shan OPAL_EEH_ACTION_CLEAR_FREEZE_ALL); 621b131a842SGavin Shan } 622b131a842SGavin Shan } 623b131a842SGavin Shan 624b131a842SGavin Shan /* 625b131a842SGavin Shan * Associate PE in PELT. We need add the PE into the 626b131a842SGavin Shan * corresponding PELT-V as well. Otherwise, the error 627b131a842SGavin Shan * originated from the PE might contribute to other 628b131a842SGavin Shan * PEs. 629b131a842SGavin Shan */ 630b131a842SGavin Shan ret = pnv_ioda_set_one_peltv(phb, pe, pe, is_add); 631b131a842SGavin Shan if (ret) 632b131a842SGavin Shan return ret; 633b131a842SGavin Shan 634b131a842SGavin Shan /* For compound PEs, any one affects all of them */ 635b131a842SGavin Shan if (pe->flags & PNV_IODA_PE_MASTER) { 636b131a842SGavin Shan list_for_each_entry(slave, &pe->slaves, list) { 637b131a842SGavin Shan ret = pnv_ioda_set_one_peltv(phb, slave, pe, is_add); 638b131a842SGavin Shan if (ret) 639b131a842SGavin Shan return ret; 640b131a842SGavin Shan } 641b131a842SGavin Shan } 642b131a842SGavin Shan 643b131a842SGavin Shan if (pe->flags & (PNV_IODA_PE_BUS_ALL | PNV_IODA_PE_BUS)) 644b131a842SGavin Shan pdev = pe->pbus->self; 645781a868fSWei Yang else if (pe->flags & PNV_IODA_PE_DEV) 646b131a842SGavin Shan pdev = pe->pdev->bus->self; 647781a868fSWei Yang #ifdef CONFIG_PCI_IOV 648781a868fSWei Yang else if (pe->flags & PNV_IODA_PE_VF) 649781a868fSWei Yang pdev = pe->parent_dev->bus->self; 650781a868fSWei Yang #endif /* CONFIG_PCI_IOV */ 651b131a842SGavin Shan while (pdev) { 652b131a842SGavin Shan struct pci_dn *pdn = pci_get_pdn(pdev); 653b131a842SGavin Shan struct pnv_ioda_pe *parent; 654b131a842SGavin Shan 655b131a842SGavin Shan if (pdn && pdn->pe_number != IODA_INVALID_PE) { 656b131a842SGavin Shan parent = &phb->ioda.pe_array[pdn->pe_number]; 657b131a842SGavin Shan ret = pnv_ioda_set_one_peltv(phb, parent, pe, is_add); 658b131a842SGavin Shan if (ret) 659b131a842SGavin Shan return ret; 660b131a842SGavin Shan } 661b131a842SGavin Shan 662b131a842SGavin Shan pdev = pdev->bus->self; 663b131a842SGavin Shan } 664b131a842SGavin Shan 665b131a842SGavin Shan return 0; 666b131a842SGavin Shan } 667b131a842SGavin Shan 668781a868fSWei Yang #ifdef CONFIG_PCI_IOV 669781a868fSWei Yang static int pnv_ioda_deconfigure_pe(struct pnv_phb *phb, struct pnv_ioda_pe *pe) 670781a868fSWei Yang { 671781a868fSWei Yang struct pci_dev *parent; 672781a868fSWei Yang uint8_t bcomp, dcomp, fcomp; 673781a868fSWei Yang int64_t rc; 674781a868fSWei Yang long rid_end, rid; 675781a868fSWei Yang 676781a868fSWei Yang /* Currently, we just deconfigure VF PE. Bus PE will always there.*/ 677781a868fSWei Yang if (pe->pbus) { 678781a868fSWei Yang int count; 679781a868fSWei Yang 680781a868fSWei Yang dcomp = OPAL_IGNORE_RID_DEVICE_NUMBER; 681781a868fSWei Yang fcomp = OPAL_IGNORE_RID_FUNCTION_NUMBER; 682781a868fSWei Yang parent = pe->pbus->self; 683781a868fSWei Yang if (pe->flags & PNV_IODA_PE_BUS_ALL) 684781a868fSWei Yang count = pe->pbus->busn_res.end - pe->pbus->busn_res.start + 1; 685781a868fSWei Yang else 686781a868fSWei Yang count = 1; 687781a868fSWei Yang 688781a868fSWei Yang switch(count) { 689781a868fSWei Yang case 1: bcomp = OpalPciBusAll; break; 690781a868fSWei Yang case 2: bcomp = OpalPciBus7Bits; break; 691781a868fSWei Yang case 4: bcomp = OpalPciBus6Bits; break; 692781a868fSWei Yang case 8: bcomp = OpalPciBus5Bits; break; 693781a868fSWei Yang case 16: bcomp = OpalPciBus4Bits; break; 694781a868fSWei Yang case 32: bcomp = OpalPciBus3Bits; break; 695781a868fSWei Yang default: 696781a868fSWei Yang dev_err(&pe->pbus->dev, "Number of subordinate buses %d unsupported\n", 697781a868fSWei Yang count); 698781a868fSWei Yang /* Do an exact match only */ 699781a868fSWei Yang bcomp = OpalPciBusAll; 700781a868fSWei Yang } 701781a868fSWei Yang rid_end = pe->rid + (count << 8); 702781a868fSWei Yang } else { 703781a868fSWei Yang if (pe->flags & PNV_IODA_PE_VF) 704781a868fSWei Yang parent = pe->parent_dev; 705781a868fSWei Yang else 706781a868fSWei Yang parent = pe->pdev->bus->self; 707781a868fSWei Yang bcomp = OpalPciBusAll; 708781a868fSWei Yang dcomp = OPAL_COMPARE_RID_DEVICE_NUMBER; 709781a868fSWei Yang fcomp = OPAL_COMPARE_RID_FUNCTION_NUMBER; 710781a868fSWei Yang rid_end = pe->rid + 1; 711781a868fSWei Yang } 712781a868fSWei Yang 713781a868fSWei Yang /* Clear the reverse map */ 714781a868fSWei Yang for (rid = pe->rid; rid < rid_end; rid++) 715781a868fSWei Yang phb->ioda.pe_rmap[rid] = 0; 716781a868fSWei Yang 717781a868fSWei Yang /* Release from all parents PELT-V */ 718781a868fSWei Yang while (parent) { 719781a868fSWei Yang struct pci_dn *pdn = pci_get_pdn(parent); 720781a868fSWei Yang if (pdn && pdn->pe_number != IODA_INVALID_PE) { 721781a868fSWei Yang rc = opal_pci_set_peltv(phb->opal_id, pdn->pe_number, 722781a868fSWei Yang pe->pe_number, OPAL_REMOVE_PE_FROM_DOMAIN); 723781a868fSWei Yang /* XXX What to do in case of error ? */ 724781a868fSWei Yang } 725781a868fSWei Yang parent = parent->bus->self; 726781a868fSWei Yang } 727781a868fSWei Yang 728781a868fSWei Yang opal_pci_eeh_freeze_set(phb->opal_id, pe->pe_number, 729781a868fSWei Yang OPAL_EEH_ACTION_CLEAR_FREEZE_ALL); 730781a868fSWei Yang 731781a868fSWei Yang /* Disassociate PE in PELT */ 732781a868fSWei Yang rc = opal_pci_set_peltv(phb->opal_id, pe->pe_number, 733781a868fSWei Yang pe->pe_number, OPAL_REMOVE_PE_FROM_DOMAIN); 734781a868fSWei Yang if (rc) 735781a868fSWei Yang pe_warn(pe, "OPAL error %ld remove self from PELTV\n", rc); 736781a868fSWei Yang rc = opal_pci_set_pe(phb->opal_id, pe->pe_number, pe->rid, 737781a868fSWei Yang bcomp, dcomp, fcomp, OPAL_UNMAP_PE); 738781a868fSWei Yang if (rc) 739781a868fSWei Yang pe_err(pe, "OPAL error %ld trying to setup PELT table\n", rc); 740781a868fSWei Yang 741781a868fSWei Yang pe->pbus = NULL; 742781a868fSWei Yang pe->pdev = NULL; 743781a868fSWei Yang pe->parent_dev = NULL; 744781a868fSWei Yang 745781a868fSWei Yang return 0; 746781a868fSWei Yang } 747781a868fSWei Yang #endif /* CONFIG_PCI_IOV */ 748781a868fSWei Yang 749cad5cef6SGreg Kroah-Hartman static int pnv_ioda_configure_pe(struct pnv_phb *phb, struct pnv_ioda_pe *pe) 750184cd4a3SBenjamin Herrenschmidt { 751184cd4a3SBenjamin Herrenschmidt struct pci_dev *parent; 752184cd4a3SBenjamin Herrenschmidt uint8_t bcomp, dcomp, fcomp; 753184cd4a3SBenjamin Herrenschmidt long rc, rid_end, rid; 754184cd4a3SBenjamin Herrenschmidt 755184cd4a3SBenjamin Herrenschmidt /* Bus validation ? */ 756184cd4a3SBenjamin Herrenschmidt if (pe->pbus) { 757184cd4a3SBenjamin Herrenschmidt int count; 758184cd4a3SBenjamin Herrenschmidt 759184cd4a3SBenjamin Herrenschmidt dcomp = OPAL_IGNORE_RID_DEVICE_NUMBER; 760184cd4a3SBenjamin Herrenschmidt fcomp = OPAL_IGNORE_RID_FUNCTION_NUMBER; 761184cd4a3SBenjamin Herrenschmidt parent = pe->pbus->self; 762fb446ad0SGavin Shan if (pe->flags & PNV_IODA_PE_BUS_ALL) 763b918c62eSYinghai Lu count = pe->pbus->busn_res.end - pe->pbus->busn_res.start + 1; 764fb446ad0SGavin Shan else 765fb446ad0SGavin Shan count = 1; 766fb446ad0SGavin Shan 767184cd4a3SBenjamin Herrenschmidt switch(count) { 768184cd4a3SBenjamin Herrenschmidt case 1: bcomp = OpalPciBusAll; break; 769184cd4a3SBenjamin Herrenschmidt case 2: bcomp = OpalPciBus7Bits; break; 770184cd4a3SBenjamin Herrenschmidt case 4: bcomp = OpalPciBus6Bits; break; 771184cd4a3SBenjamin Herrenschmidt case 8: bcomp = OpalPciBus5Bits; break; 772184cd4a3SBenjamin Herrenschmidt case 16: bcomp = OpalPciBus4Bits; break; 773184cd4a3SBenjamin Herrenschmidt case 32: bcomp = OpalPciBus3Bits; break; 774184cd4a3SBenjamin Herrenschmidt default: 775781a868fSWei Yang dev_err(&pe->pbus->dev, "Number of subordinate buses %d unsupported\n", 776781a868fSWei Yang count); 777184cd4a3SBenjamin Herrenschmidt /* Do an exact match only */ 778184cd4a3SBenjamin Herrenschmidt bcomp = OpalPciBusAll; 779184cd4a3SBenjamin Herrenschmidt } 780184cd4a3SBenjamin Herrenschmidt rid_end = pe->rid + (count << 8); 781184cd4a3SBenjamin Herrenschmidt } else { 782781a868fSWei Yang #ifdef CONFIG_PCI_IOV 783781a868fSWei Yang if (pe->flags & PNV_IODA_PE_VF) 784781a868fSWei Yang parent = pe->parent_dev; 785781a868fSWei Yang else 786781a868fSWei Yang #endif /* CONFIG_PCI_IOV */ 787184cd4a3SBenjamin Herrenschmidt parent = pe->pdev->bus->self; 788184cd4a3SBenjamin Herrenschmidt bcomp = OpalPciBusAll; 789184cd4a3SBenjamin Herrenschmidt dcomp = OPAL_COMPARE_RID_DEVICE_NUMBER; 790184cd4a3SBenjamin Herrenschmidt fcomp = OPAL_COMPARE_RID_FUNCTION_NUMBER; 791184cd4a3SBenjamin Herrenschmidt rid_end = pe->rid + 1; 792184cd4a3SBenjamin Herrenschmidt } 793184cd4a3SBenjamin Herrenschmidt 794631ad691SGavin Shan /* 795631ad691SGavin Shan * Associate PE in PELT. We need add the PE into the 796631ad691SGavin Shan * corresponding PELT-V as well. Otherwise, the error 797631ad691SGavin Shan * originated from the PE might contribute to other 798631ad691SGavin Shan * PEs. 799631ad691SGavin Shan */ 800184cd4a3SBenjamin Herrenschmidt rc = opal_pci_set_pe(phb->opal_id, pe->pe_number, pe->rid, 801184cd4a3SBenjamin Herrenschmidt bcomp, dcomp, fcomp, OPAL_MAP_PE); 802184cd4a3SBenjamin Herrenschmidt if (rc) { 803184cd4a3SBenjamin Herrenschmidt pe_err(pe, "OPAL error %ld trying to setup PELT table\n", rc); 804184cd4a3SBenjamin Herrenschmidt return -ENXIO; 805184cd4a3SBenjamin Herrenschmidt } 806631ad691SGavin Shan 807b131a842SGavin Shan /* Configure PELTV */ 808b131a842SGavin Shan pnv_ioda_set_peltv(phb, pe, true); 809184cd4a3SBenjamin Herrenschmidt 810184cd4a3SBenjamin Herrenschmidt /* Setup reverse map */ 811184cd4a3SBenjamin Herrenschmidt for (rid = pe->rid; rid < rid_end; rid++) 812184cd4a3SBenjamin Herrenschmidt phb->ioda.pe_rmap[rid] = pe->pe_number; 813184cd4a3SBenjamin Herrenschmidt 814184cd4a3SBenjamin Herrenschmidt /* Setup one MVTs on IODA1 */ 8154773f76bSGavin Shan if (phb->type != PNV_PHB_IODA1) { 8164773f76bSGavin Shan pe->mve_number = 0; 8174773f76bSGavin Shan goto out; 8184773f76bSGavin Shan } 8194773f76bSGavin Shan 820184cd4a3SBenjamin Herrenschmidt pe->mve_number = pe->pe_number; 8214773f76bSGavin Shan rc = opal_pci_set_mve(phb->opal_id, pe->mve_number, pe->pe_number); 8224773f76bSGavin Shan if (rc != OPAL_SUCCESS) { 823184cd4a3SBenjamin Herrenschmidt pe_err(pe, "OPAL error %ld setting up MVE %d\n", 824184cd4a3SBenjamin Herrenschmidt rc, pe->mve_number); 825184cd4a3SBenjamin Herrenschmidt pe->mve_number = -1; 826184cd4a3SBenjamin Herrenschmidt } else { 827184cd4a3SBenjamin Herrenschmidt rc = opal_pci_set_mve_enable(phb->opal_id, 828cee72d5bSBenjamin Herrenschmidt pe->mve_number, OPAL_ENABLE_MVE); 829184cd4a3SBenjamin Herrenschmidt if (rc) { 830184cd4a3SBenjamin Herrenschmidt pe_err(pe, "OPAL error %ld enabling MVE %d\n", 831184cd4a3SBenjamin Herrenschmidt rc, pe->mve_number); 832184cd4a3SBenjamin Herrenschmidt pe->mve_number = -1; 833184cd4a3SBenjamin Herrenschmidt } 834184cd4a3SBenjamin Herrenschmidt } 835184cd4a3SBenjamin Herrenschmidt 8364773f76bSGavin Shan out: 837184cd4a3SBenjamin Herrenschmidt return 0; 838184cd4a3SBenjamin Herrenschmidt } 839184cd4a3SBenjamin Herrenschmidt 840cad5cef6SGreg Kroah-Hartman static void pnv_ioda_link_pe_by_weight(struct pnv_phb *phb, 841184cd4a3SBenjamin Herrenschmidt struct pnv_ioda_pe *pe) 842184cd4a3SBenjamin Herrenschmidt { 843184cd4a3SBenjamin Herrenschmidt struct pnv_ioda_pe *lpe; 844184cd4a3SBenjamin Herrenschmidt 8457ebdf956SGavin Shan list_for_each_entry(lpe, &phb->ioda.pe_dma_list, dma_link) { 846184cd4a3SBenjamin Herrenschmidt if (lpe->dma_weight < pe->dma_weight) { 8477ebdf956SGavin Shan list_add_tail(&pe->dma_link, &lpe->dma_link); 848184cd4a3SBenjamin Herrenschmidt return; 849184cd4a3SBenjamin Herrenschmidt } 850184cd4a3SBenjamin Herrenschmidt } 8517ebdf956SGavin Shan list_add_tail(&pe->dma_link, &phb->ioda.pe_dma_list); 852184cd4a3SBenjamin Herrenschmidt } 853184cd4a3SBenjamin Herrenschmidt 854184cd4a3SBenjamin Herrenschmidt static unsigned int pnv_ioda_dma_weight(struct pci_dev *dev) 855184cd4a3SBenjamin Herrenschmidt { 856184cd4a3SBenjamin Herrenschmidt /* This is quite simplistic. The "base" weight of a device 857184cd4a3SBenjamin Herrenschmidt * is 10. 0 means no DMA is to be accounted for it. 858184cd4a3SBenjamin Herrenschmidt */ 859184cd4a3SBenjamin Herrenschmidt 860184cd4a3SBenjamin Herrenschmidt /* If it's a bridge, no DMA */ 861184cd4a3SBenjamin Herrenschmidt if (dev->hdr_type != PCI_HEADER_TYPE_NORMAL) 862184cd4a3SBenjamin Herrenschmidt return 0; 863184cd4a3SBenjamin Herrenschmidt 864184cd4a3SBenjamin Herrenschmidt /* Reduce the weight of slow USB controllers */ 865184cd4a3SBenjamin Herrenschmidt if (dev->class == PCI_CLASS_SERIAL_USB_UHCI || 866184cd4a3SBenjamin Herrenschmidt dev->class == PCI_CLASS_SERIAL_USB_OHCI || 867184cd4a3SBenjamin Herrenschmidt dev->class == PCI_CLASS_SERIAL_USB_EHCI) 868184cd4a3SBenjamin Herrenschmidt return 3; 869184cd4a3SBenjamin Herrenschmidt 870184cd4a3SBenjamin Herrenschmidt /* Increase the weight of RAID (includes Obsidian) */ 871184cd4a3SBenjamin Herrenschmidt if ((dev->class >> 8) == PCI_CLASS_STORAGE_RAID) 872184cd4a3SBenjamin Herrenschmidt return 15; 873184cd4a3SBenjamin Herrenschmidt 874184cd4a3SBenjamin Herrenschmidt /* Default */ 875184cd4a3SBenjamin Herrenschmidt return 10; 876184cd4a3SBenjamin Herrenschmidt } 877184cd4a3SBenjamin Herrenschmidt 878781a868fSWei Yang #ifdef CONFIG_PCI_IOV 879781a868fSWei Yang static int pnv_pci_vf_resource_shift(struct pci_dev *dev, int offset) 880781a868fSWei Yang { 881781a868fSWei Yang struct pci_dn *pdn = pci_get_pdn(dev); 882781a868fSWei Yang int i; 883781a868fSWei Yang struct resource *res, res2; 884781a868fSWei Yang resource_size_t size; 885781a868fSWei Yang u16 num_vfs; 886781a868fSWei Yang 887781a868fSWei Yang if (!dev->is_physfn) 888781a868fSWei Yang return -EINVAL; 889781a868fSWei Yang 890781a868fSWei Yang /* 891781a868fSWei Yang * "offset" is in VFs. The M64 windows are sized so that when they 892781a868fSWei Yang * are segmented, each segment is the same size as the IOV BAR. 893781a868fSWei Yang * Each segment is in a separate PE, and the high order bits of the 894781a868fSWei Yang * address are the PE number. Therefore, each VF's BAR is in a 895781a868fSWei Yang * separate PE, and changing the IOV BAR start address changes the 896781a868fSWei Yang * range of PEs the VFs are in. 897781a868fSWei Yang */ 898781a868fSWei Yang num_vfs = pdn->num_vfs; 899781a868fSWei Yang for (i = 0; i < PCI_SRIOV_NUM_BARS; i++) { 900781a868fSWei Yang res = &dev->resource[i + PCI_IOV_RESOURCES]; 901781a868fSWei Yang if (!res->flags || !res->parent) 902781a868fSWei Yang continue; 903781a868fSWei Yang 904781a868fSWei Yang if (!pnv_pci_is_mem_pref_64(res->flags)) 905781a868fSWei Yang continue; 906781a868fSWei Yang 907781a868fSWei Yang /* 908781a868fSWei Yang * The actual IOV BAR range is determined by the start address 909781a868fSWei Yang * and the actual size for num_vfs VFs BAR. This check is to 910781a868fSWei Yang * make sure that after shifting, the range will not overlap 911781a868fSWei Yang * with another device. 912781a868fSWei Yang */ 913781a868fSWei Yang size = pci_iov_resource_size(dev, i + PCI_IOV_RESOURCES); 914781a868fSWei Yang res2.flags = res->flags; 915781a868fSWei Yang res2.start = res->start + (size * offset); 916781a868fSWei Yang res2.end = res2.start + (size * num_vfs) - 1; 917781a868fSWei Yang 918781a868fSWei Yang if (res2.end > res->end) { 919781a868fSWei Yang dev_err(&dev->dev, "VF BAR%d: %pR would extend past %pR (trying to enable %d VFs shifted by %d)\n", 920781a868fSWei Yang i, &res2, res, num_vfs, offset); 921781a868fSWei Yang return -EBUSY; 922781a868fSWei Yang } 923781a868fSWei Yang } 924781a868fSWei Yang 925781a868fSWei Yang /* 926781a868fSWei Yang * After doing so, there would be a "hole" in the /proc/iomem when 927781a868fSWei Yang * offset is a positive value. It looks like the device return some 928781a868fSWei Yang * mmio back to the system, which actually no one could use it. 929781a868fSWei Yang */ 930781a868fSWei Yang for (i = 0; i < PCI_SRIOV_NUM_BARS; i++) { 931781a868fSWei Yang res = &dev->resource[i + PCI_IOV_RESOURCES]; 932781a868fSWei Yang if (!res->flags || !res->parent) 933781a868fSWei Yang continue; 934781a868fSWei Yang 935781a868fSWei Yang if (!pnv_pci_is_mem_pref_64(res->flags)) 936781a868fSWei Yang continue; 937781a868fSWei Yang 938781a868fSWei Yang size = pci_iov_resource_size(dev, i + PCI_IOV_RESOURCES); 939781a868fSWei Yang res2 = *res; 940781a868fSWei Yang res->start += size * offset; 941781a868fSWei Yang 942781a868fSWei Yang dev_info(&dev->dev, "VF BAR%d: %pR shifted to %pR (enabling %d VFs shifted by %d)\n", 943781a868fSWei Yang i, &res2, res, num_vfs, offset); 944781a868fSWei Yang pci_update_resource(dev, i + PCI_IOV_RESOURCES); 945781a868fSWei Yang } 946781a868fSWei Yang return 0; 947781a868fSWei Yang } 948781a868fSWei Yang #endif /* CONFIG_PCI_IOV */ 949781a868fSWei Yang 950fb446ad0SGavin Shan #if 0 951cad5cef6SGreg Kroah-Hartman static struct pnv_ioda_pe *pnv_ioda_setup_dev_PE(struct pci_dev *dev) 952184cd4a3SBenjamin Herrenschmidt { 953184cd4a3SBenjamin Herrenschmidt struct pci_controller *hose = pci_bus_to_host(dev->bus); 954184cd4a3SBenjamin Herrenschmidt struct pnv_phb *phb = hose->private_data; 955b72c1f65SBenjamin Herrenschmidt struct pci_dn *pdn = pci_get_pdn(dev); 956184cd4a3SBenjamin Herrenschmidt struct pnv_ioda_pe *pe; 957184cd4a3SBenjamin Herrenschmidt int pe_num; 958184cd4a3SBenjamin Herrenschmidt 959184cd4a3SBenjamin Herrenschmidt if (!pdn) { 960184cd4a3SBenjamin Herrenschmidt pr_err("%s: Device tree node not associated properly\n", 961184cd4a3SBenjamin Herrenschmidt pci_name(dev)); 962184cd4a3SBenjamin Herrenschmidt return NULL; 963184cd4a3SBenjamin Herrenschmidt } 964184cd4a3SBenjamin Herrenschmidt if (pdn->pe_number != IODA_INVALID_PE) 965184cd4a3SBenjamin Herrenschmidt return NULL; 966184cd4a3SBenjamin Herrenschmidt 967184cd4a3SBenjamin Herrenschmidt /* PE#0 has been pre-set */ 968184cd4a3SBenjamin Herrenschmidt if (dev->bus->number == 0) 969184cd4a3SBenjamin Herrenschmidt pe_num = 0; 970184cd4a3SBenjamin Herrenschmidt else 971184cd4a3SBenjamin Herrenschmidt pe_num = pnv_ioda_alloc_pe(phb); 972184cd4a3SBenjamin Herrenschmidt if (pe_num == IODA_INVALID_PE) { 973184cd4a3SBenjamin Herrenschmidt pr_warning("%s: Not enough PE# available, disabling device\n", 974184cd4a3SBenjamin Herrenschmidt pci_name(dev)); 975184cd4a3SBenjamin Herrenschmidt return NULL; 976184cd4a3SBenjamin Herrenschmidt } 977184cd4a3SBenjamin Herrenschmidt 978184cd4a3SBenjamin Herrenschmidt /* NOTE: We get only one ref to the pci_dev for the pdn, not for the 979184cd4a3SBenjamin Herrenschmidt * pointer in the PE data structure, both should be destroyed at the 980184cd4a3SBenjamin Herrenschmidt * same time. However, this needs to be looked at more closely again 981184cd4a3SBenjamin Herrenschmidt * once we actually start removing things (Hotplug, SR-IOV, ...) 982184cd4a3SBenjamin Herrenschmidt * 983184cd4a3SBenjamin Herrenschmidt * At some point we want to remove the PDN completely anyways 984184cd4a3SBenjamin Herrenschmidt */ 985184cd4a3SBenjamin Herrenschmidt pe = &phb->ioda.pe_array[pe_num]; 986184cd4a3SBenjamin Herrenschmidt pci_dev_get(dev); 987184cd4a3SBenjamin Herrenschmidt pdn->pcidev = dev; 988184cd4a3SBenjamin Herrenschmidt pdn->pe_number = pe_num; 989184cd4a3SBenjamin Herrenschmidt pe->pdev = dev; 990184cd4a3SBenjamin Herrenschmidt pe->pbus = NULL; 991184cd4a3SBenjamin Herrenschmidt pe->tce32_seg = -1; 992184cd4a3SBenjamin Herrenschmidt pe->mve_number = -1; 993184cd4a3SBenjamin Herrenschmidt pe->rid = dev->bus->number << 8 | pdn->devfn; 994184cd4a3SBenjamin Herrenschmidt 995184cd4a3SBenjamin Herrenschmidt pe_info(pe, "Associated device to PE\n"); 996184cd4a3SBenjamin Herrenschmidt 997184cd4a3SBenjamin Herrenschmidt if (pnv_ioda_configure_pe(phb, pe)) { 998184cd4a3SBenjamin Herrenschmidt /* XXX What do we do here ? */ 999184cd4a3SBenjamin Herrenschmidt if (pe_num) 1000184cd4a3SBenjamin Herrenschmidt pnv_ioda_free_pe(phb, pe_num); 1001184cd4a3SBenjamin Herrenschmidt pdn->pe_number = IODA_INVALID_PE; 1002184cd4a3SBenjamin Herrenschmidt pe->pdev = NULL; 1003184cd4a3SBenjamin Herrenschmidt pci_dev_put(dev); 1004184cd4a3SBenjamin Herrenschmidt return NULL; 1005184cd4a3SBenjamin Herrenschmidt } 1006184cd4a3SBenjamin Herrenschmidt 1007184cd4a3SBenjamin Herrenschmidt /* Assign a DMA weight to the device */ 1008184cd4a3SBenjamin Herrenschmidt pe->dma_weight = pnv_ioda_dma_weight(dev); 1009184cd4a3SBenjamin Herrenschmidt if (pe->dma_weight != 0) { 1010184cd4a3SBenjamin Herrenschmidt phb->ioda.dma_weight += pe->dma_weight; 1011184cd4a3SBenjamin Herrenschmidt phb->ioda.dma_pe_count++; 1012184cd4a3SBenjamin Herrenschmidt } 1013184cd4a3SBenjamin Herrenschmidt 1014184cd4a3SBenjamin Herrenschmidt /* Link the PE */ 1015184cd4a3SBenjamin Herrenschmidt pnv_ioda_link_pe_by_weight(phb, pe); 1016184cd4a3SBenjamin Herrenschmidt 1017184cd4a3SBenjamin Herrenschmidt return pe; 1018184cd4a3SBenjamin Herrenschmidt } 1019fb446ad0SGavin Shan #endif /* Useful for SRIOV case */ 1020184cd4a3SBenjamin Herrenschmidt 1021184cd4a3SBenjamin Herrenschmidt static void pnv_ioda_setup_same_PE(struct pci_bus *bus, struct pnv_ioda_pe *pe) 1022184cd4a3SBenjamin Herrenschmidt { 1023184cd4a3SBenjamin Herrenschmidt struct pci_dev *dev; 1024184cd4a3SBenjamin Herrenschmidt 1025184cd4a3SBenjamin Herrenschmidt list_for_each_entry(dev, &bus->devices, bus_list) { 1026b72c1f65SBenjamin Herrenschmidt struct pci_dn *pdn = pci_get_pdn(dev); 1027184cd4a3SBenjamin Herrenschmidt 1028184cd4a3SBenjamin Herrenschmidt if (pdn == NULL) { 1029184cd4a3SBenjamin Herrenschmidt pr_warn("%s: No device node associated with device !\n", 1030184cd4a3SBenjamin Herrenschmidt pci_name(dev)); 1031184cd4a3SBenjamin Herrenschmidt continue; 1032184cd4a3SBenjamin Herrenschmidt } 1033184cd4a3SBenjamin Herrenschmidt pdn->pe_number = pe->pe_number; 1034184cd4a3SBenjamin Herrenschmidt pe->dma_weight += pnv_ioda_dma_weight(dev); 1035fb446ad0SGavin Shan if ((pe->flags & PNV_IODA_PE_BUS_ALL) && dev->subordinate) 1036184cd4a3SBenjamin Herrenschmidt pnv_ioda_setup_same_PE(dev->subordinate, pe); 1037184cd4a3SBenjamin Herrenschmidt } 1038184cd4a3SBenjamin Herrenschmidt } 1039184cd4a3SBenjamin Herrenschmidt 1040fb446ad0SGavin Shan /* 1041fb446ad0SGavin Shan * There're 2 types of PCI bus sensitive PEs: One that is compromised of 1042fb446ad0SGavin Shan * single PCI bus. Another one that contains the primary PCI bus and its 1043fb446ad0SGavin Shan * subordinate PCI devices and buses. The second type of PE is normally 1044fb446ad0SGavin Shan * orgiriated by PCIe-to-PCI bridge or PLX switch downstream ports. 1045fb446ad0SGavin Shan */ 1046cad5cef6SGreg Kroah-Hartman static void pnv_ioda_setup_bus_PE(struct pci_bus *bus, int all) 1047184cd4a3SBenjamin Herrenschmidt { 1048fb446ad0SGavin Shan struct pci_controller *hose = pci_bus_to_host(bus); 1049184cd4a3SBenjamin Herrenschmidt struct pnv_phb *phb = hose->private_data; 1050184cd4a3SBenjamin Herrenschmidt struct pnv_ioda_pe *pe; 1051262af557SGuo Chao int pe_num = IODA_INVALID_PE; 1052184cd4a3SBenjamin Herrenschmidt 1053262af557SGuo Chao /* Check if PE is determined by M64 */ 1054262af557SGuo Chao if (phb->pick_m64_pe) 1055262af557SGuo Chao pe_num = phb->pick_m64_pe(phb, bus, all); 1056262af557SGuo Chao 1057262af557SGuo Chao /* The PE number isn't pinned by M64 */ 1058262af557SGuo Chao if (pe_num == IODA_INVALID_PE) 1059184cd4a3SBenjamin Herrenschmidt pe_num = pnv_ioda_alloc_pe(phb); 1060262af557SGuo Chao 1061184cd4a3SBenjamin Herrenschmidt if (pe_num == IODA_INVALID_PE) { 1062fb446ad0SGavin Shan pr_warning("%s: Not enough PE# available for PCI bus %04x:%02x\n", 1063fb446ad0SGavin Shan __func__, pci_domain_nr(bus), bus->number); 1064184cd4a3SBenjamin Herrenschmidt return; 1065184cd4a3SBenjamin Herrenschmidt } 1066184cd4a3SBenjamin Herrenschmidt 1067184cd4a3SBenjamin Herrenschmidt pe = &phb->ioda.pe_array[pe_num]; 1068262af557SGuo Chao pe->flags |= (all ? PNV_IODA_PE_BUS_ALL : PNV_IODA_PE_BUS); 1069184cd4a3SBenjamin Herrenschmidt pe->pbus = bus; 1070184cd4a3SBenjamin Herrenschmidt pe->pdev = NULL; 1071184cd4a3SBenjamin Herrenschmidt pe->tce32_seg = -1; 1072184cd4a3SBenjamin Herrenschmidt pe->mve_number = -1; 1073b918c62eSYinghai Lu pe->rid = bus->busn_res.start << 8; 1074184cd4a3SBenjamin Herrenschmidt pe->dma_weight = 0; 1075184cd4a3SBenjamin Herrenschmidt 1076fb446ad0SGavin Shan if (all) 1077fb446ad0SGavin Shan pe_info(pe, "Secondary bus %d..%d associated with PE#%d\n", 1078fb446ad0SGavin Shan bus->busn_res.start, bus->busn_res.end, pe_num); 1079fb446ad0SGavin Shan else 1080fb446ad0SGavin Shan pe_info(pe, "Secondary bus %d associated with PE#%d\n", 1081fb446ad0SGavin Shan bus->busn_res.start, pe_num); 1082184cd4a3SBenjamin Herrenschmidt 1083184cd4a3SBenjamin Herrenschmidt if (pnv_ioda_configure_pe(phb, pe)) { 1084184cd4a3SBenjamin Herrenschmidt /* XXX What do we do here ? */ 1085184cd4a3SBenjamin Herrenschmidt if (pe_num) 1086184cd4a3SBenjamin Herrenschmidt pnv_ioda_free_pe(phb, pe_num); 1087184cd4a3SBenjamin Herrenschmidt pe->pbus = NULL; 1088184cd4a3SBenjamin Herrenschmidt return; 1089184cd4a3SBenjamin Herrenschmidt } 1090184cd4a3SBenjamin Herrenschmidt 1091184cd4a3SBenjamin Herrenschmidt /* Associate it with all child devices */ 1092184cd4a3SBenjamin Herrenschmidt pnv_ioda_setup_same_PE(bus, pe); 1093184cd4a3SBenjamin Herrenschmidt 10947ebdf956SGavin Shan /* Put PE to the list */ 10957ebdf956SGavin Shan list_add_tail(&pe->list, &phb->ioda.pe_list); 10967ebdf956SGavin Shan 1097184cd4a3SBenjamin Herrenschmidt /* Account for one DMA PE if at least one DMA capable device exist 1098184cd4a3SBenjamin Herrenschmidt * below the bridge 1099184cd4a3SBenjamin Herrenschmidt */ 1100184cd4a3SBenjamin Herrenschmidt if (pe->dma_weight != 0) { 1101184cd4a3SBenjamin Herrenschmidt phb->ioda.dma_weight += pe->dma_weight; 1102184cd4a3SBenjamin Herrenschmidt phb->ioda.dma_pe_count++; 1103184cd4a3SBenjamin Herrenschmidt } 1104184cd4a3SBenjamin Herrenschmidt 1105184cd4a3SBenjamin Herrenschmidt /* Link the PE */ 1106184cd4a3SBenjamin Herrenschmidt pnv_ioda_link_pe_by_weight(phb, pe); 1107184cd4a3SBenjamin Herrenschmidt } 1108184cd4a3SBenjamin Herrenschmidt 1109cad5cef6SGreg Kroah-Hartman static void pnv_ioda_setup_PEs(struct pci_bus *bus) 1110184cd4a3SBenjamin Herrenschmidt { 1111184cd4a3SBenjamin Herrenschmidt struct pci_dev *dev; 1112fb446ad0SGavin Shan 1113fb446ad0SGavin Shan pnv_ioda_setup_bus_PE(bus, 0); 1114184cd4a3SBenjamin Herrenschmidt 1115184cd4a3SBenjamin Herrenschmidt list_for_each_entry(dev, &bus->devices, bus_list) { 1116fb446ad0SGavin Shan if (dev->subordinate) { 111762f87c0eSYijing Wang if (pci_pcie_type(dev) == PCI_EXP_TYPE_PCI_BRIDGE) 1118fb446ad0SGavin Shan pnv_ioda_setup_bus_PE(dev->subordinate, 1); 1119fb446ad0SGavin Shan else 1120184cd4a3SBenjamin Herrenschmidt pnv_ioda_setup_PEs(dev->subordinate); 1121184cd4a3SBenjamin Herrenschmidt } 1122184cd4a3SBenjamin Herrenschmidt } 1123fb446ad0SGavin Shan } 1124fb446ad0SGavin Shan 1125fb446ad0SGavin Shan /* 1126fb446ad0SGavin Shan * Configure PEs so that the downstream PCI buses and devices 1127fb446ad0SGavin Shan * could have their associated PE#. Unfortunately, we didn't 1128fb446ad0SGavin Shan * figure out the way to identify the PLX bridge yet. So we 1129fb446ad0SGavin Shan * simply put the PCI bus and the subordinate behind the root 1130fb446ad0SGavin Shan * port to PE# here. The game rule here is expected to be changed 1131fb446ad0SGavin Shan * as soon as we can detected PLX bridge correctly. 1132fb446ad0SGavin Shan */ 1133cad5cef6SGreg Kroah-Hartman static void pnv_pci_ioda_setup_PEs(void) 1134fb446ad0SGavin Shan { 1135fb446ad0SGavin Shan struct pci_controller *hose, *tmp; 1136262af557SGuo Chao struct pnv_phb *phb; 1137fb446ad0SGavin Shan 1138fb446ad0SGavin Shan list_for_each_entry_safe(hose, tmp, &hose_list, list_node) { 1139262af557SGuo Chao phb = hose->private_data; 1140262af557SGuo Chao 1141262af557SGuo Chao /* M64 layout might affect PE allocation */ 11425ef73567SGavin Shan if (phb->reserve_m64_pe) 11435ef73567SGavin Shan phb->reserve_m64_pe(phb); 1144262af557SGuo Chao 1145fb446ad0SGavin Shan pnv_ioda_setup_PEs(hose->bus); 1146fb446ad0SGavin Shan } 1147fb446ad0SGavin Shan } 1148184cd4a3SBenjamin Herrenschmidt 1149a8b2f828SGavin Shan #ifdef CONFIG_PCI_IOV 1150781a868fSWei Yang static int pnv_pci_vf_release_m64(struct pci_dev *pdev) 1151781a868fSWei Yang { 1152781a868fSWei Yang struct pci_bus *bus; 1153781a868fSWei Yang struct pci_controller *hose; 1154781a868fSWei Yang struct pnv_phb *phb; 1155781a868fSWei Yang struct pci_dn *pdn; 115602639b0eSWei Yang int i, j; 1157781a868fSWei Yang 1158781a868fSWei Yang bus = pdev->bus; 1159781a868fSWei Yang hose = pci_bus_to_host(bus); 1160781a868fSWei Yang phb = hose->private_data; 1161781a868fSWei Yang pdn = pci_get_pdn(pdev); 1162781a868fSWei Yang 116302639b0eSWei Yang for (i = 0; i < PCI_SRIOV_NUM_BARS; i++) 116402639b0eSWei Yang for (j = 0; j < M64_PER_IOV; j++) { 116502639b0eSWei Yang if (pdn->m64_wins[i][j] == IODA_INVALID_M64) 1166781a868fSWei Yang continue; 1167781a868fSWei Yang opal_pci_phb_mmio_enable(phb->opal_id, 116802639b0eSWei Yang OPAL_M64_WINDOW_TYPE, pdn->m64_wins[i][j], 0); 116902639b0eSWei Yang clear_bit(pdn->m64_wins[i][j], &phb->ioda.m64_bar_alloc); 117002639b0eSWei Yang pdn->m64_wins[i][j] = IODA_INVALID_M64; 1171781a868fSWei Yang } 1172781a868fSWei Yang 1173781a868fSWei Yang return 0; 1174781a868fSWei Yang } 1175781a868fSWei Yang 117602639b0eSWei Yang static int pnv_pci_vf_assign_m64(struct pci_dev *pdev, u16 num_vfs) 1177781a868fSWei Yang { 1178781a868fSWei Yang struct pci_bus *bus; 1179781a868fSWei Yang struct pci_controller *hose; 1180781a868fSWei Yang struct pnv_phb *phb; 1181781a868fSWei Yang struct pci_dn *pdn; 1182781a868fSWei Yang unsigned int win; 1183781a868fSWei Yang struct resource *res; 118402639b0eSWei Yang int i, j; 1185781a868fSWei Yang int64_t rc; 118602639b0eSWei Yang int total_vfs; 118702639b0eSWei Yang resource_size_t size, start; 118802639b0eSWei Yang int pe_num; 118902639b0eSWei Yang int vf_groups; 119002639b0eSWei Yang int vf_per_group; 1191781a868fSWei Yang 1192781a868fSWei Yang bus = pdev->bus; 1193781a868fSWei Yang hose = pci_bus_to_host(bus); 1194781a868fSWei Yang phb = hose->private_data; 1195781a868fSWei Yang pdn = pci_get_pdn(pdev); 119602639b0eSWei Yang total_vfs = pci_sriov_get_totalvfs(pdev); 1197781a868fSWei Yang 1198781a868fSWei Yang /* Initialize the m64_wins to IODA_INVALID_M64 */ 1199781a868fSWei Yang for (i = 0; i < PCI_SRIOV_NUM_BARS; i++) 120002639b0eSWei Yang for (j = 0; j < M64_PER_IOV; j++) 120102639b0eSWei Yang pdn->m64_wins[i][j] = IODA_INVALID_M64; 120202639b0eSWei Yang 120302639b0eSWei Yang if (pdn->m64_per_iov == M64_PER_IOV) { 120402639b0eSWei Yang vf_groups = (num_vfs <= M64_PER_IOV) ? num_vfs: M64_PER_IOV; 120502639b0eSWei Yang vf_per_group = (num_vfs <= M64_PER_IOV)? 1: 120602639b0eSWei Yang roundup_pow_of_two(num_vfs) / pdn->m64_per_iov; 120702639b0eSWei Yang } else { 120802639b0eSWei Yang vf_groups = 1; 120902639b0eSWei Yang vf_per_group = 1; 121002639b0eSWei Yang } 1211781a868fSWei Yang 1212781a868fSWei Yang for (i = 0; i < PCI_SRIOV_NUM_BARS; i++) { 1213781a868fSWei Yang res = &pdev->resource[i + PCI_IOV_RESOURCES]; 1214781a868fSWei Yang if (!res->flags || !res->parent) 1215781a868fSWei Yang continue; 1216781a868fSWei Yang 1217781a868fSWei Yang if (!pnv_pci_is_mem_pref_64(res->flags)) 1218781a868fSWei Yang continue; 1219781a868fSWei Yang 122002639b0eSWei Yang for (j = 0; j < vf_groups; j++) { 1221781a868fSWei Yang do { 1222781a868fSWei Yang win = find_next_zero_bit(&phb->ioda.m64_bar_alloc, 1223781a868fSWei Yang phb->ioda.m64_bar_idx + 1, 0); 1224781a868fSWei Yang 1225781a868fSWei Yang if (win >= phb->ioda.m64_bar_idx + 1) 1226781a868fSWei Yang goto m64_failed; 1227781a868fSWei Yang } while (test_and_set_bit(win, &phb->ioda.m64_bar_alloc)); 1228781a868fSWei Yang 122902639b0eSWei Yang pdn->m64_wins[i][j] = win; 123002639b0eSWei Yang 123102639b0eSWei Yang if (pdn->m64_per_iov == M64_PER_IOV) { 123202639b0eSWei Yang size = pci_iov_resource_size(pdev, 123302639b0eSWei Yang PCI_IOV_RESOURCES + i); 123402639b0eSWei Yang size = size * vf_per_group; 123502639b0eSWei Yang start = res->start + size * j; 123602639b0eSWei Yang } else { 123702639b0eSWei Yang size = resource_size(res); 123802639b0eSWei Yang start = res->start; 123902639b0eSWei Yang } 1240781a868fSWei Yang 1241781a868fSWei Yang /* Map the M64 here */ 124202639b0eSWei Yang if (pdn->m64_per_iov == M64_PER_IOV) { 124302639b0eSWei Yang pe_num = pdn->offset + j; 124402639b0eSWei Yang rc = opal_pci_map_pe_mmio_window(phb->opal_id, 124502639b0eSWei Yang pe_num, OPAL_M64_WINDOW_TYPE, 124602639b0eSWei Yang pdn->m64_wins[i][j], 0); 124702639b0eSWei Yang } 124802639b0eSWei Yang 1249781a868fSWei Yang rc = opal_pci_set_phb_mem_window(phb->opal_id, 1250781a868fSWei Yang OPAL_M64_WINDOW_TYPE, 125102639b0eSWei Yang pdn->m64_wins[i][j], 125202639b0eSWei Yang start, 1253781a868fSWei Yang 0, /* unused */ 125402639b0eSWei Yang size); 125502639b0eSWei Yang 125602639b0eSWei Yang 1257781a868fSWei Yang if (rc != OPAL_SUCCESS) { 1258781a868fSWei Yang dev_err(&pdev->dev, "Failed to map M64 window #%d: %lld\n", 1259781a868fSWei Yang win, rc); 1260781a868fSWei Yang goto m64_failed; 1261781a868fSWei Yang } 1262781a868fSWei Yang 126302639b0eSWei Yang if (pdn->m64_per_iov == M64_PER_IOV) 1264781a868fSWei Yang rc = opal_pci_phb_mmio_enable(phb->opal_id, 126502639b0eSWei Yang OPAL_M64_WINDOW_TYPE, pdn->m64_wins[i][j], 2); 126602639b0eSWei Yang else 126702639b0eSWei Yang rc = opal_pci_phb_mmio_enable(phb->opal_id, 126802639b0eSWei Yang OPAL_M64_WINDOW_TYPE, pdn->m64_wins[i][j], 1); 126902639b0eSWei Yang 1270781a868fSWei Yang if (rc != OPAL_SUCCESS) { 1271781a868fSWei Yang dev_err(&pdev->dev, "Failed to enable M64 window #%d: %llx\n", 1272781a868fSWei Yang win, rc); 1273781a868fSWei Yang goto m64_failed; 1274781a868fSWei Yang } 1275781a868fSWei Yang } 127602639b0eSWei Yang } 1277781a868fSWei Yang return 0; 1278781a868fSWei Yang 1279781a868fSWei Yang m64_failed: 1280781a868fSWei Yang pnv_pci_vf_release_m64(pdev); 1281781a868fSWei Yang return -EBUSY; 1282781a868fSWei Yang } 1283781a868fSWei Yang 1284781a868fSWei Yang static void pnv_pci_ioda2_release_dma_pe(struct pci_dev *dev, struct pnv_ioda_pe *pe) 1285781a868fSWei Yang { 1286781a868fSWei Yang struct pci_bus *bus; 1287781a868fSWei Yang struct pci_controller *hose; 1288781a868fSWei Yang struct pnv_phb *phb; 1289781a868fSWei Yang struct iommu_table *tbl; 1290781a868fSWei Yang unsigned long addr; 1291781a868fSWei Yang int64_t rc; 1292781a868fSWei Yang 1293781a868fSWei Yang bus = dev->bus; 1294781a868fSWei Yang hose = pci_bus_to_host(bus); 1295781a868fSWei Yang phb = hose->private_data; 1296b348aa65SAlexey Kardashevskiy tbl = pe->table_group.tables[0]; 1297781a868fSWei Yang addr = tbl->it_base; 1298781a868fSWei Yang 1299781a868fSWei Yang opal_pci_map_pe_dma_window(phb->opal_id, pe->pe_number, 1300781a868fSWei Yang pe->pe_number << 1, 1, __pa(addr), 1301781a868fSWei Yang 0, 0x1000); 1302781a868fSWei Yang 1303781a868fSWei Yang rc = opal_pci_map_pe_dma_window_real(pe->phb->opal_id, 1304781a868fSWei Yang pe->pe_number, 1305781a868fSWei Yang (pe->pe_number << 1) + 1, 1306781a868fSWei Yang pe->tce_bypass_base, 1307781a868fSWei Yang 0); 1308781a868fSWei Yang if (rc) 1309781a868fSWei Yang pe_warn(pe, "OPAL error %ld release DMA window\n", rc); 1310781a868fSWei Yang 13110eaf4defSAlexey Kardashevskiy pnv_pci_unlink_table_and_group(tbl, &pe->table_group); 13120eaf4defSAlexey Kardashevskiy if (pe->table_group.group) { 13130eaf4defSAlexey Kardashevskiy iommu_group_put(pe->table_group.group); 13140eaf4defSAlexey Kardashevskiy BUG_ON(pe->table_group.group); 1315ac9a5889SAlexey Kardashevskiy } 1316781a868fSWei Yang iommu_free_table(tbl, of_node_full_name(dev->dev.of_node)); 1317781a868fSWei Yang free_pages(addr, get_order(TCE32_TABLE_SIZE)); 1318781a868fSWei Yang } 1319781a868fSWei Yang 132002639b0eSWei Yang static void pnv_ioda_release_vf_PE(struct pci_dev *pdev, u16 num_vfs) 1321781a868fSWei Yang { 1322781a868fSWei Yang struct pci_bus *bus; 1323781a868fSWei Yang struct pci_controller *hose; 1324781a868fSWei Yang struct pnv_phb *phb; 1325781a868fSWei Yang struct pnv_ioda_pe *pe, *pe_n; 1326781a868fSWei Yang struct pci_dn *pdn; 132702639b0eSWei Yang u16 vf_index; 132802639b0eSWei Yang int64_t rc; 1329781a868fSWei Yang 1330781a868fSWei Yang bus = pdev->bus; 1331781a868fSWei Yang hose = pci_bus_to_host(bus); 1332781a868fSWei Yang phb = hose->private_data; 133302639b0eSWei Yang pdn = pci_get_pdn(pdev); 1334781a868fSWei Yang 1335781a868fSWei Yang if (!pdev->is_physfn) 1336781a868fSWei Yang return; 1337781a868fSWei Yang 133802639b0eSWei Yang if (pdn->m64_per_iov == M64_PER_IOV && num_vfs > M64_PER_IOV) { 133902639b0eSWei Yang int vf_group; 134002639b0eSWei Yang int vf_per_group; 134102639b0eSWei Yang int vf_index1; 134202639b0eSWei Yang 134302639b0eSWei Yang vf_per_group = roundup_pow_of_two(num_vfs) / pdn->m64_per_iov; 134402639b0eSWei Yang 134502639b0eSWei Yang for (vf_group = 0; vf_group < M64_PER_IOV; vf_group++) 134602639b0eSWei Yang for (vf_index = vf_group * vf_per_group; 134702639b0eSWei Yang vf_index < (vf_group + 1) * vf_per_group && 134802639b0eSWei Yang vf_index < num_vfs; 134902639b0eSWei Yang vf_index++) 135002639b0eSWei Yang for (vf_index1 = vf_group * vf_per_group; 135102639b0eSWei Yang vf_index1 < (vf_group + 1) * vf_per_group && 135202639b0eSWei Yang vf_index1 < num_vfs; 135302639b0eSWei Yang vf_index1++){ 135402639b0eSWei Yang 135502639b0eSWei Yang rc = opal_pci_set_peltv(phb->opal_id, 135602639b0eSWei Yang pdn->offset + vf_index, 135702639b0eSWei Yang pdn->offset + vf_index1, 135802639b0eSWei Yang OPAL_REMOVE_PE_FROM_DOMAIN); 135902639b0eSWei Yang 136002639b0eSWei Yang if (rc) 136102639b0eSWei Yang dev_warn(&pdev->dev, "%s: Failed to unlink same group PE#%d(%lld)\n", 136202639b0eSWei Yang __func__, 136302639b0eSWei Yang pdn->offset + vf_index1, rc); 136402639b0eSWei Yang } 136502639b0eSWei Yang } 136602639b0eSWei Yang 1367781a868fSWei Yang list_for_each_entry_safe(pe, pe_n, &phb->ioda.pe_list, list) { 1368781a868fSWei Yang if (pe->parent_dev != pdev) 1369781a868fSWei Yang continue; 1370781a868fSWei Yang 1371781a868fSWei Yang pnv_pci_ioda2_release_dma_pe(pdev, pe); 1372781a868fSWei Yang 1373781a868fSWei Yang /* Remove from list */ 1374781a868fSWei Yang mutex_lock(&phb->ioda.pe_list_mutex); 1375781a868fSWei Yang list_del(&pe->list); 1376781a868fSWei Yang mutex_unlock(&phb->ioda.pe_list_mutex); 1377781a868fSWei Yang 1378781a868fSWei Yang pnv_ioda_deconfigure_pe(phb, pe); 1379781a868fSWei Yang 1380781a868fSWei Yang pnv_ioda_free_pe(phb, pe->pe_number); 1381781a868fSWei Yang } 1382781a868fSWei Yang } 1383781a868fSWei Yang 1384781a868fSWei Yang void pnv_pci_sriov_disable(struct pci_dev *pdev) 1385781a868fSWei Yang { 1386781a868fSWei Yang struct pci_bus *bus; 1387781a868fSWei Yang struct pci_controller *hose; 1388781a868fSWei Yang struct pnv_phb *phb; 1389781a868fSWei Yang struct pci_dn *pdn; 1390781a868fSWei Yang struct pci_sriov *iov; 1391781a868fSWei Yang u16 num_vfs; 1392781a868fSWei Yang 1393781a868fSWei Yang bus = pdev->bus; 1394781a868fSWei Yang hose = pci_bus_to_host(bus); 1395781a868fSWei Yang phb = hose->private_data; 1396781a868fSWei Yang pdn = pci_get_pdn(pdev); 1397781a868fSWei Yang iov = pdev->sriov; 1398781a868fSWei Yang num_vfs = pdn->num_vfs; 1399781a868fSWei Yang 1400781a868fSWei Yang /* Release VF PEs */ 140102639b0eSWei Yang pnv_ioda_release_vf_PE(pdev, num_vfs); 1402781a868fSWei Yang 1403781a868fSWei Yang if (phb->type == PNV_PHB_IODA2) { 140402639b0eSWei Yang if (pdn->m64_per_iov == 1) 1405781a868fSWei Yang pnv_pci_vf_resource_shift(pdev, -pdn->offset); 1406781a868fSWei Yang 1407781a868fSWei Yang /* Release M64 windows */ 1408781a868fSWei Yang pnv_pci_vf_release_m64(pdev); 1409781a868fSWei Yang 1410781a868fSWei Yang /* Release PE numbers */ 1411781a868fSWei Yang bitmap_clear(phb->ioda.pe_alloc, pdn->offset, num_vfs); 1412781a868fSWei Yang pdn->offset = 0; 1413781a868fSWei Yang } 1414781a868fSWei Yang } 1415781a868fSWei Yang 1416781a868fSWei Yang static void pnv_pci_ioda2_setup_dma_pe(struct pnv_phb *phb, 1417781a868fSWei Yang struct pnv_ioda_pe *pe); 1418781a868fSWei Yang static void pnv_ioda_setup_vf_PE(struct pci_dev *pdev, u16 num_vfs) 1419781a868fSWei Yang { 1420781a868fSWei Yang struct pci_bus *bus; 1421781a868fSWei Yang struct pci_controller *hose; 1422781a868fSWei Yang struct pnv_phb *phb; 1423781a868fSWei Yang struct pnv_ioda_pe *pe; 1424781a868fSWei Yang int pe_num; 1425781a868fSWei Yang u16 vf_index; 1426781a868fSWei Yang struct pci_dn *pdn; 142702639b0eSWei Yang int64_t rc; 1428781a868fSWei Yang 1429781a868fSWei Yang bus = pdev->bus; 1430781a868fSWei Yang hose = pci_bus_to_host(bus); 1431781a868fSWei Yang phb = hose->private_data; 1432781a868fSWei Yang pdn = pci_get_pdn(pdev); 1433781a868fSWei Yang 1434781a868fSWei Yang if (!pdev->is_physfn) 1435781a868fSWei Yang return; 1436781a868fSWei Yang 1437781a868fSWei Yang /* Reserve PE for each VF */ 1438781a868fSWei Yang for (vf_index = 0; vf_index < num_vfs; vf_index++) { 1439781a868fSWei Yang pe_num = pdn->offset + vf_index; 1440781a868fSWei Yang 1441781a868fSWei Yang pe = &phb->ioda.pe_array[pe_num]; 1442781a868fSWei Yang pe->pe_number = pe_num; 1443781a868fSWei Yang pe->phb = phb; 1444781a868fSWei Yang pe->flags = PNV_IODA_PE_VF; 1445781a868fSWei Yang pe->pbus = NULL; 1446781a868fSWei Yang pe->parent_dev = pdev; 1447781a868fSWei Yang pe->tce32_seg = -1; 1448781a868fSWei Yang pe->mve_number = -1; 1449781a868fSWei Yang pe->rid = (pci_iov_virtfn_bus(pdev, vf_index) << 8) | 1450781a868fSWei Yang pci_iov_virtfn_devfn(pdev, vf_index); 1451781a868fSWei Yang 1452781a868fSWei Yang pe_info(pe, "VF %04d:%02d:%02d.%d associated with PE#%d\n", 1453781a868fSWei Yang hose->global_number, pdev->bus->number, 1454781a868fSWei Yang PCI_SLOT(pci_iov_virtfn_devfn(pdev, vf_index)), 1455781a868fSWei Yang PCI_FUNC(pci_iov_virtfn_devfn(pdev, vf_index)), pe_num); 1456781a868fSWei Yang 1457781a868fSWei Yang if (pnv_ioda_configure_pe(phb, pe)) { 1458781a868fSWei Yang /* XXX What do we do here ? */ 1459781a868fSWei Yang if (pe_num) 1460781a868fSWei Yang pnv_ioda_free_pe(phb, pe_num); 1461781a868fSWei Yang pe->pdev = NULL; 1462781a868fSWei Yang continue; 1463781a868fSWei Yang } 1464781a868fSWei Yang 1465781a868fSWei Yang /* Put PE to the list */ 1466781a868fSWei Yang mutex_lock(&phb->ioda.pe_list_mutex); 1467781a868fSWei Yang list_add_tail(&pe->list, &phb->ioda.pe_list); 1468781a868fSWei Yang mutex_unlock(&phb->ioda.pe_list_mutex); 1469781a868fSWei Yang 1470781a868fSWei Yang pnv_pci_ioda2_setup_dma_pe(phb, pe); 1471781a868fSWei Yang } 147202639b0eSWei Yang 147302639b0eSWei Yang if (pdn->m64_per_iov == M64_PER_IOV && num_vfs > M64_PER_IOV) { 147402639b0eSWei Yang int vf_group; 147502639b0eSWei Yang int vf_per_group; 147602639b0eSWei Yang int vf_index1; 147702639b0eSWei Yang 147802639b0eSWei Yang vf_per_group = roundup_pow_of_two(num_vfs) / pdn->m64_per_iov; 147902639b0eSWei Yang 148002639b0eSWei Yang for (vf_group = 0; vf_group < M64_PER_IOV; vf_group++) { 148102639b0eSWei Yang for (vf_index = vf_group * vf_per_group; 148202639b0eSWei Yang vf_index < (vf_group + 1) * vf_per_group && 148302639b0eSWei Yang vf_index < num_vfs; 148402639b0eSWei Yang vf_index++) { 148502639b0eSWei Yang for (vf_index1 = vf_group * vf_per_group; 148602639b0eSWei Yang vf_index1 < (vf_group + 1) * vf_per_group && 148702639b0eSWei Yang vf_index1 < num_vfs; 148802639b0eSWei Yang vf_index1++) { 148902639b0eSWei Yang 149002639b0eSWei Yang rc = opal_pci_set_peltv(phb->opal_id, 149102639b0eSWei Yang pdn->offset + vf_index, 149202639b0eSWei Yang pdn->offset + vf_index1, 149302639b0eSWei Yang OPAL_ADD_PE_TO_DOMAIN); 149402639b0eSWei Yang 149502639b0eSWei Yang if (rc) 149602639b0eSWei Yang dev_warn(&pdev->dev, "%s: Failed to link same group PE#%d(%lld)\n", 149702639b0eSWei Yang __func__, 149802639b0eSWei Yang pdn->offset + vf_index1, rc); 149902639b0eSWei Yang } 150002639b0eSWei Yang } 150102639b0eSWei Yang } 150202639b0eSWei Yang } 1503781a868fSWei Yang } 1504781a868fSWei Yang 1505781a868fSWei Yang int pnv_pci_sriov_enable(struct pci_dev *pdev, u16 num_vfs) 1506781a868fSWei Yang { 1507781a868fSWei Yang struct pci_bus *bus; 1508781a868fSWei Yang struct pci_controller *hose; 1509781a868fSWei Yang struct pnv_phb *phb; 1510781a868fSWei Yang struct pci_dn *pdn; 1511781a868fSWei Yang int ret; 1512781a868fSWei Yang 1513781a868fSWei Yang bus = pdev->bus; 1514781a868fSWei Yang hose = pci_bus_to_host(bus); 1515781a868fSWei Yang phb = hose->private_data; 1516781a868fSWei Yang pdn = pci_get_pdn(pdev); 1517781a868fSWei Yang 1518781a868fSWei Yang if (phb->type == PNV_PHB_IODA2) { 1519781a868fSWei Yang /* Calculate available PE for required VFs */ 1520781a868fSWei Yang mutex_lock(&phb->ioda.pe_alloc_mutex); 1521781a868fSWei Yang pdn->offset = bitmap_find_next_zero_area( 1522781a868fSWei Yang phb->ioda.pe_alloc, phb->ioda.total_pe, 1523781a868fSWei Yang 0, num_vfs, 0); 1524781a868fSWei Yang if (pdn->offset >= phb->ioda.total_pe) { 1525781a868fSWei Yang mutex_unlock(&phb->ioda.pe_alloc_mutex); 1526781a868fSWei Yang dev_info(&pdev->dev, "Failed to enable VF%d\n", num_vfs); 1527781a868fSWei Yang pdn->offset = 0; 1528781a868fSWei Yang return -EBUSY; 1529781a868fSWei Yang } 1530781a868fSWei Yang bitmap_set(phb->ioda.pe_alloc, pdn->offset, num_vfs); 1531781a868fSWei Yang pdn->num_vfs = num_vfs; 1532781a868fSWei Yang mutex_unlock(&phb->ioda.pe_alloc_mutex); 1533781a868fSWei Yang 1534781a868fSWei Yang /* Assign M64 window accordingly */ 153502639b0eSWei Yang ret = pnv_pci_vf_assign_m64(pdev, num_vfs); 1536781a868fSWei Yang if (ret) { 1537781a868fSWei Yang dev_info(&pdev->dev, "Not enough M64 window resources\n"); 1538781a868fSWei Yang goto m64_failed; 1539781a868fSWei Yang } 1540781a868fSWei Yang 1541781a868fSWei Yang /* 1542781a868fSWei Yang * When using one M64 BAR to map one IOV BAR, we need to shift 1543781a868fSWei Yang * the IOV BAR according to the PE# allocated to the VFs. 1544781a868fSWei Yang * Otherwise, the PE# for the VF will conflict with others. 1545781a868fSWei Yang */ 154602639b0eSWei Yang if (pdn->m64_per_iov == 1) { 1547781a868fSWei Yang ret = pnv_pci_vf_resource_shift(pdev, pdn->offset); 1548781a868fSWei Yang if (ret) 1549781a868fSWei Yang goto m64_failed; 1550781a868fSWei Yang } 155102639b0eSWei Yang } 1552781a868fSWei Yang 1553781a868fSWei Yang /* Setup VF PEs */ 1554781a868fSWei Yang pnv_ioda_setup_vf_PE(pdev, num_vfs); 1555781a868fSWei Yang 1556781a868fSWei Yang return 0; 1557781a868fSWei Yang 1558781a868fSWei Yang m64_failed: 1559781a868fSWei Yang bitmap_clear(phb->ioda.pe_alloc, pdn->offset, num_vfs); 1560781a868fSWei Yang pdn->offset = 0; 1561781a868fSWei Yang 1562781a868fSWei Yang return ret; 1563781a868fSWei Yang } 1564781a868fSWei Yang 1565a8b2f828SGavin Shan int pcibios_sriov_disable(struct pci_dev *pdev) 1566a8b2f828SGavin Shan { 1567781a868fSWei Yang pnv_pci_sriov_disable(pdev); 1568781a868fSWei Yang 1569a8b2f828SGavin Shan /* Release PCI data */ 1570a8b2f828SGavin Shan remove_dev_pci_data(pdev); 1571a8b2f828SGavin Shan return 0; 1572a8b2f828SGavin Shan } 1573a8b2f828SGavin Shan 1574a8b2f828SGavin Shan int pcibios_sriov_enable(struct pci_dev *pdev, u16 num_vfs) 1575a8b2f828SGavin Shan { 1576a8b2f828SGavin Shan /* Allocate PCI data */ 1577a8b2f828SGavin Shan add_dev_pci_data(pdev); 1578781a868fSWei Yang 1579781a868fSWei Yang pnv_pci_sriov_enable(pdev, num_vfs); 1580a8b2f828SGavin Shan return 0; 1581a8b2f828SGavin Shan } 1582a8b2f828SGavin Shan #endif /* CONFIG_PCI_IOV */ 1583a8b2f828SGavin Shan 1584959c9bddSGavin Shan static void pnv_pci_ioda_dma_dev_setup(struct pnv_phb *phb, struct pci_dev *pdev) 1585184cd4a3SBenjamin Herrenschmidt { 1586b72c1f65SBenjamin Herrenschmidt struct pci_dn *pdn = pci_get_pdn(pdev); 1587959c9bddSGavin Shan struct pnv_ioda_pe *pe; 1588184cd4a3SBenjamin Herrenschmidt 1589959c9bddSGavin Shan /* 1590959c9bddSGavin Shan * The function can be called while the PE# 1591959c9bddSGavin Shan * hasn't been assigned. Do nothing for the 1592959c9bddSGavin Shan * case. 1593959c9bddSGavin Shan */ 1594959c9bddSGavin Shan if (!pdn || pdn->pe_number == IODA_INVALID_PE) 1595959c9bddSGavin Shan return; 1596184cd4a3SBenjamin Herrenschmidt 1597959c9bddSGavin Shan pe = &phb->ioda.pe_array[pdn->pe_number]; 1598cd15b048SBenjamin Herrenschmidt WARN_ON(get_dma_ops(&pdev->dev) != &dma_iommu_ops); 1599b348aa65SAlexey Kardashevskiy set_iommu_table_base(&pdev->dev, pe->table_group.tables[0]); 16004617082eSAlexey Kardashevskiy /* 16014617082eSAlexey Kardashevskiy * Note: iommu_add_device() will fail here as 16024617082eSAlexey Kardashevskiy * for physical PE: the device is already added by now; 16034617082eSAlexey Kardashevskiy * for virtual PE: sysfs entries are not ready yet and 16044617082eSAlexey Kardashevskiy * tce_iommu_bus_notifier will add the device to a group later. 16054617082eSAlexey Kardashevskiy */ 1606184cd4a3SBenjamin Herrenschmidt } 1607184cd4a3SBenjamin Herrenschmidt 1608763d2d8dSDaniel Axtens static int pnv_pci_ioda_dma_set_mask(struct pci_dev *pdev, u64 dma_mask) 1609cd15b048SBenjamin Herrenschmidt { 1610763d2d8dSDaniel Axtens struct pci_controller *hose = pci_bus_to_host(pdev->bus); 1611763d2d8dSDaniel Axtens struct pnv_phb *phb = hose->private_data; 1612cd15b048SBenjamin Herrenschmidt struct pci_dn *pdn = pci_get_pdn(pdev); 1613cd15b048SBenjamin Herrenschmidt struct pnv_ioda_pe *pe; 1614cd15b048SBenjamin Herrenschmidt uint64_t top; 1615cd15b048SBenjamin Herrenschmidt bool bypass = false; 1616cd15b048SBenjamin Herrenschmidt 1617cd15b048SBenjamin Herrenschmidt if (WARN_ON(!pdn || pdn->pe_number == IODA_INVALID_PE)) 1618cd15b048SBenjamin Herrenschmidt return -ENODEV;; 1619cd15b048SBenjamin Herrenschmidt 1620cd15b048SBenjamin Herrenschmidt pe = &phb->ioda.pe_array[pdn->pe_number]; 1621cd15b048SBenjamin Herrenschmidt if (pe->tce_bypass_enabled) { 1622cd15b048SBenjamin Herrenschmidt top = pe->tce_bypass_base + memblock_end_of_DRAM() - 1; 1623cd15b048SBenjamin Herrenschmidt bypass = (dma_mask >= top); 1624cd15b048SBenjamin Herrenschmidt } 1625cd15b048SBenjamin Herrenschmidt 1626cd15b048SBenjamin Herrenschmidt if (bypass) { 1627cd15b048SBenjamin Herrenschmidt dev_info(&pdev->dev, "Using 64-bit DMA iommu bypass\n"); 1628cd15b048SBenjamin Herrenschmidt set_dma_ops(&pdev->dev, &dma_direct_ops); 1629cd15b048SBenjamin Herrenschmidt set_dma_offset(&pdev->dev, pe->tce_bypass_base); 1630cd15b048SBenjamin Herrenschmidt } else { 1631cd15b048SBenjamin Herrenschmidt dev_info(&pdev->dev, "Using 32-bit DMA via iommu\n"); 1632cd15b048SBenjamin Herrenschmidt set_dma_ops(&pdev->dev, &dma_iommu_ops); 1633b348aa65SAlexey Kardashevskiy set_iommu_table_base(&pdev->dev, pe->table_group.tables[0]); 1634cd15b048SBenjamin Herrenschmidt } 1635a32305bfSBrian W Hart *pdev->dev.dma_mask = dma_mask; 1636cd15b048SBenjamin Herrenschmidt return 0; 1637cd15b048SBenjamin Herrenschmidt } 1638cd15b048SBenjamin Herrenschmidt 1639fe7e85c6SGavin Shan static u64 pnv_pci_ioda_dma_get_required_mask(struct pnv_phb *phb, 1640fe7e85c6SGavin Shan struct pci_dev *pdev) 1641fe7e85c6SGavin Shan { 1642fe7e85c6SGavin Shan struct pci_dn *pdn = pci_get_pdn(pdev); 1643fe7e85c6SGavin Shan struct pnv_ioda_pe *pe; 1644fe7e85c6SGavin Shan u64 end, mask; 1645fe7e85c6SGavin Shan 1646fe7e85c6SGavin Shan if (WARN_ON(!pdn || pdn->pe_number == IODA_INVALID_PE)) 1647fe7e85c6SGavin Shan return 0; 1648fe7e85c6SGavin Shan 1649fe7e85c6SGavin Shan pe = &phb->ioda.pe_array[pdn->pe_number]; 1650fe7e85c6SGavin Shan if (!pe->tce_bypass_enabled) 1651fe7e85c6SGavin Shan return __dma_get_required_mask(&pdev->dev); 1652fe7e85c6SGavin Shan 1653fe7e85c6SGavin Shan 1654fe7e85c6SGavin Shan end = pe->tce_bypass_base + memblock_end_of_DRAM(); 1655fe7e85c6SGavin Shan mask = 1ULL << (fls64(end) - 1); 1656fe7e85c6SGavin Shan mask += mask - 1; 1657fe7e85c6SGavin Shan 1658fe7e85c6SGavin Shan return mask; 1659fe7e85c6SGavin Shan } 1660fe7e85c6SGavin Shan 1661dff4a39eSGavin Shan static void pnv_ioda_setup_bus_dma(struct pnv_ioda_pe *pe, 1662ea30e99eSAlexey Kardashevskiy struct pci_bus *bus) 166374251fe2SBenjamin Herrenschmidt { 166474251fe2SBenjamin Herrenschmidt struct pci_dev *dev; 166574251fe2SBenjamin Herrenschmidt 166674251fe2SBenjamin Herrenschmidt list_for_each_entry(dev, &bus->devices, bus_list) { 1667b348aa65SAlexey Kardashevskiy set_iommu_table_base(&dev->dev, pe->table_group.tables[0]); 16684617082eSAlexey Kardashevskiy iommu_add_device(&dev->dev); 1669dff4a39eSGavin Shan 167074251fe2SBenjamin Herrenschmidt if (dev->subordinate) 1671ea30e99eSAlexey Kardashevskiy pnv_ioda_setup_bus_dma(pe, dev->subordinate); 167274251fe2SBenjamin Herrenschmidt } 167374251fe2SBenjamin Herrenschmidt } 167474251fe2SBenjamin Herrenschmidt 1675decbda25SAlexey Kardashevskiy static void pnv_pci_ioda1_tce_invalidate(struct iommu_table *tbl, 1676decbda25SAlexey Kardashevskiy unsigned long index, unsigned long npages, bool rm) 16774cce9550SGavin Shan { 16780eaf4defSAlexey Kardashevskiy struct iommu_table_group_link *tgl = list_first_entry_or_null( 16790eaf4defSAlexey Kardashevskiy &tbl->it_group_list, struct iommu_table_group_link, 16800eaf4defSAlexey Kardashevskiy next); 16810eaf4defSAlexey Kardashevskiy struct pnv_ioda_pe *pe = container_of(tgl->table_group, 1682b348aa65SAlexey Kardashevskiy struct pnv_ioda_pe, table_group); 16833ad26e5cSBenjamin Herrenschmidt __be64 __iomem *invalidate = rm ? 16845780fb04SAlexey Kardashevskiy (__be64 __iomem *)pe->phb->ioda.tce_inval_reg_phys : 16855780fb04SAlexey Kardashevskiy pe->phb->ioda.tce_inval_reg; 16864cce9550SGavin Shan unsigned long start, end, inc; 1687b0376c9bSAlexey Kardashevskiy const unsigned shift = tbl->it_page_shift; 16884cce9550SGavin Shan 1689decbda25SAlexey Kardashevskiy start = __pa(((__be64 *)tbl->it_base) + index - tbl->it_offset); 1690decbda25SAlexey Kardashevskiy end = __pa(((__be64 *)tbl->it_base) + index - tbl->it_offset + 1691decbda25SAlexey Kardashevskiy npages - 1); 16924cce9550SGavin Shan 16934cce9550SGavin Shan /* BML uses this case for p6/p7/galaxy2: Shift addr and put in node */ 16944cce9550SGavin Shan if (tbl->it_busno) { 1695b0376c9bSAlexey Kardashevskiy start <<= shift; 1696b0376c9bSAlexey Kardashevskiy end <<= shift; 1697b0376c9bSAlexey Kardashevskiy inc = 128ull << shift; 16984cce9550SGavin Shan start |= tbl->it_busno; 16994cce9550SGavin Shan end |= tbl->it_busno; 17004cce9550SGavin Shan } else if (tbl->it_type & TCE_PCI_SWINV_PAIR) { 17014cce9550SGavin Shan /* p7ioc-style invalidation, 2 TCEs per write */ 17024cce9550SGavin Shan start |= (1ull << 63); 17034cce9550SGavin Shan end |= (1ull << 63); 17044cce9550SGavin Shan inc = 16; 17054cce9550SGavin Shan } else { 17064cce9550SGavin Shan /* Default (older HW) */ 17074cce9550SGavin Shan inc = 128; 17084cce9550SGavin Shan } 17094cce9550SGavin Shan 17104cce9550SGavin Shan end |= inc - 1; /* round up end to be different than start */ 17114cce9550SGavin Shan 17124cce9550SGavin Shan mb(); /* Ensure above stores are visible */ 17134cce9550SGavin Shan while (start <= end) { 17148e0a1611SAlexey Kardashevskiy if (rm) 17153ad26e5cSBenjamin Herrenschmidt __raw_rm_writeq(cpu_to_be64(start), invalidate); 17168e0a1611SAlexey Kardashevskiy else 17173a1a4661SBenjamin Herrenschmidt __raw_writeq(cpu_to_be64(start), invalidate); 17184cce9550SGavin Shan start += inc; 17194cce9550SGavin Shan } 17204cce9550SGavin Shan 17214cce9550SGavin Shan /* 17224cce9550SGavin Shan * The iommu layer will do another mb() for us on build() 17234cce9550SGavin Shan * and we don't care on free() 17244cce9550SGavin Shan */ 17254cce9550SGavin Shan } 17264cce9550SGavin Shan 1727decbda25SAlexey Kardashevskiy static int pnv_ioda1_tce_build(struct iommu_table *tbl, long index, 1728decbda25SAlexey Kardashevskiy long npages, unsigned long uaddr, 1729decbda25SAlexey Kardashevskiy enum dma_data_direction direction, 1730decbda25SAlexey Kardashevskiy struct dma_attrs *attrs) 1731decbda25SAlexey Kardashevskiy { 1732decbda25SAlexey Kardashevskiy int ret = pnv_tce_build(tbl, index, npages, uaddr, direction, 1733decbda25SAlexey Kardashevskiy attrs); 1734decbda25SAlexey Kardashevskiy 1735decbda25SAlexey Kardashevskiy if (!ret && (tbl->it_type & TCE_PCI_SWINV_CREATE)) 1736decbda25SAlexey Kardashevskiy pnv_pci_ioda1_tce_invalidate(tbl, index, npages, false); 1737decbda25SAlexey Kardashevskiy 1738decbda25SAlexey Kardashevskiy return ret; 1739decbda25SAlexey Kardashevskiy } 1740decbda25SAlexey Kardashevskiy 174105c6cfb9SAlexey Kardashevskiy #ifdef CONFIG_IOMMU_API 174205c6cfb9SAlexey Kardashevskiy static int pnv_ioda1_tce_xchg(struct iommu_table *tbl, long index, 174305c6cfb9SAlexey Kardashevskiy unsigned long *hpa, enum dma_data_direction *direction) 174405c6cfb9SAlexey Kardashevskiy { 174505c6cfb9SAlexey Kardashevskiy long ret = pnv_tce_xchg(tbl, index, hpa, direction); 174605c6cfb9SAlexey Kardashevskiy 174705c6cfb9SAlexey Kardashevskiy if (!ret && (tbl->it_type & 174805c6cfb9SAlexey Kardashevskiy (TCE_PCI_SWINV_CREATE | TCE_PCI_SWINV_FREE))) 174905c6cfb9SAlexey Kardashevskiy pnv_pci_ioda1_tce_invalidate(tbl, index, 1, false); 175005c6cfb9SAlexey Kardashevskiy 175105c6cfb9SAlexey Kardashevskiy return ret; 175205c6cfb9SAlexey Kardashevskiy } 175305c6cfb9SAlexey Kardashevskiy #endif 175405c6cfb9SAlexey Kardashevskiy 1755decbda25SAlexey Kardashevskiy static void pnv_ioda1_tce_free(struct iommu_table *tbl, long index, 1756decbda25SAlexey Kardashevskiy long npages) 1757decbda25SAlexey Kardashevskiy { 1758decbda25SAlexey Kardashevskiy pnv_tce_free(tbl, index, npages); 1759decbda25SAlexey Kardashevskiy 1760decbda25SAlexey Kardashevskiy if (tbl->it_type & TCE_PCI_SWINV_FREE) 1761decbda25SAlexey Kardashevskiy pnv_pci_ioda1_tce_invalidate(tbl, index, npages, false); 1762decbda25SAlexey Kardashevskiy } 1763decbda25SAlexey Kardashevskiy 1764da004c36SAlexey Kardashevskiy static struct iommu_table_ops pnv_ioda1_iommu_ops = { 1765decbda25SAlexey Kardashevskiy .set = pnv_ioda1_tce_build, 176605c6cfb9SAlexey Kardashevskiy #ifdef CONFIG_IOMMU_API 176705c6cfb9SAlexey Kardashevskiy .exchange = pnv_ioda1_tce_xchg, 176805c6cfb9SAlexey Kardashevskiy #endif 1769decbda25SAlexey Kardashevskiy .clear = pnv_ioda1_tce_free, 1770da004c36SAlexey Kardashevskiy .get = pnv_tce_get, 1771da004c36SAlexey Kardashevskiy }; 1772da004c36SAlexey Kardashevskiy 17735780fb04SAlexey Kardashevskiy static inline void pnv_pci_ioda2_tce_invalidate_entire(struct pnv_ioda_pe *pe) 17745780fb04SAlexey Kardashevskiy { 17755780fb04SAlexey Kardashevskiy /* 01xb - invalidate TCEs that match the specified PE# */ 17765780fb04SAlexey Kardashevskiy unsigned long val = (0x4ull << 60) | (pe->pe_number & 0xFF); 17775780fb04SAlexey Kardashevskiy struct pnv_phb *phb = pe->phb; 17785780fb04SAlexey Kardashevskiy 17795780fb04SAlexey Kardashevskiy if (!phb->ioda.tce_inval_reg) 17805780fb04SAlexey Kardashevskiy return; 17815780fb04SAlexey Kardashevskiy 17825780fb04SAlexey Kardashevskiy mb(); /* Ensure above stores are visible */ 17835780fb04SAlexey Kardashevskiy __raw_writeq(cpu_to_be64(val), phb->ioda.tce_inval_reg); 17845780fb04SAlexey Kardashevskiy } 17855780fb04SAlexey Kardashevskiy 1786e57080f1SAlexey Kardashevskiy static void pnv_pci_ioda2_do_tce_invalidate(unsigned pe_number, bool rm, 1787e57080f1SAlexey Kardashevskiy __be64 __iomem *invalidate, unsigned shift, 1788e57080f1SAlexey Kardashevskiy unsigned long index, unsigned long npages) 17894cce9550SGavin Shan { 17904cce9550SGavin Shan unsigned long start, end, inc; 17914cce9550SGavin Shan 17924cce9550SGavin Shan /* We'll invalidate DMA address in PE scope */ 1793b0376c9bSAlexey Kardashevskiy start = 0x2ull << 60; 1794e57080f1SAlexey Kardashevskiy start |= (pe_number & 0xFF); 17954cce9550SGavin Shan end = start; 17964cce9550SGavin Shan 17974cce9550SGavin Shan /* Figure out the start, end and step */ 1798decbda25SAlexey Kardashevskiy start |= (index << shift); 1799decbda25SAlexey Kardashevskiy end |= ((index + npages - 1) << shift); 1800b0376c9bSAlexey Kardashevskiy inc = (0x1ull << shift); 18014cce9550SGavin Shan mb(); 18024cce9550SGavin Shan 18034cce9550SGavin Shan while (start <= end) { 18048e0a1611SAlexey Kardashevskiy if (rm) 18053ad26e5cSBenjamin Herrenschmidt __raw_rm_writeq(cpu_to_be64(start), invalidate); 18068e0a1611SAlexey Kardashevskiy else 18073a1a4661SBenjamin Herrenschmidt __raw_writeq(cpu_to_be64(start), invalidate); 18084cce9550SGavin Shan start += inc; 18094cce9550SGavin Shan } 18104cce9550SGavin Shan } 18114cce9550SGavin Shan 1812e57080f1SAlexey Kardashevskiy static void pnv_pci_ioda2_tce_invalidate(struct iommu_table *tbl, 1813e57080f1SAlexey Kardashevskiy unsigned long index, unsigned long npages, bool rm) 1814e57080f1SAlexey Kardashevskiy { 1815e57080f1SAlexey Kardashevskiy struct iommu_table_group_link *tgl; 1816e57080f1SAlexey Kardashevskiy 1817e57080f1SAlexey Kardashevskiy list_for_each_entry_rcu(tgl, &tbl->it_group_list, next) { 1818e57080f1SAlexey Kardashevskiy struct pnv_ioda_pe *pe = container_of(tgl->table_group, 1819e57080f1SAlexey Kardashevskiy struct pnv_ioda_pe, table_group); 1820e57080f1SAlexey Kardashevskiy __be64 __iomem *invalidate = rm ? 1821e57080f1SAlexey Kardashevskiy (__be64 __iomem *)pe->phb->ioda.tce_inval_reg_phys : 1822e57080f1SAlexey Kardashevskiy pe->phb->ioda.tce_inval_reg; 1823e57080f1SAlexey Kardashevskiy 1824e57080f1SAlexey Kardashevskiy pnv_pci_ioda2_do_tce_invalidate(pe->pe_number, rm, 1825e57080f1SAlexey Kardashevskiy invalidate, tbl->it_page_shift, 1826e57080f1SAlexey Kardashevskiy index, npages); 1827e57080f1SAlexey Kardashevskiy } 1828e57080f1SAlexey Kardashevskiy } 1829e57080f1SAlexey Kardashevskiy 1830decbda25SAlexey Kardashevskiy static int pnv_ioda2_tce_build(struct iommu_table *tbl, long index, 1831decbda25SAlexey Kardashevskiy long npages, unsigned long uaddr, 1832decbda25SAlexey Kardashevskiy enum dma_data_direction direction, 1833decbda25SAlexey Kardashevskiy struct dma_attrs *attrs) 18344cce9550SGavin Shan { 1835decbda25SAlexey Kardashevskiy int ret = pnv_tce_build(tbl, index, npages, uaddr, direction, 1836decbda25SAlexey Kardashevskiy attrs); 18374cce9550SGavin Shan 1838decbda25SAlexey Kardashevskiy if (!ret && (tbl->it_type & TCE_PCI_SWINV_CREATE)) 1839decbda25SAlexey Kardashevskiy pnv_pci_ioda2_tce_invalidate(tbl, index, npages, false); 1840decbda25SAlexey Kardashevskiy 1841decbda25SAlexey Kardashevskiy return ret; 1842decbda25SAlexey Kardashevskiy } 1843decbda25SAlexey Kardashevskiy 184405c6cfb9SAlexey Kardashevskiy #ifdef CONFIG_IOMMU_API 184505c6cfb9SAlexey Kardashevskiy static int pnv_ioda2_tce_xchg(struct iommu_table *tbl, long index, 184605c6cfb9SAlexey Kardashevskiy unsigned long *hpa, enum dma_data_direction *direction) 184705c6cfb9SAlexey Kardashevskiy { 184805c6cfb9SAlexey Kardashevskiy long ret = pnv_tce_xchg(tbl, index, hpa, direction); 184905c6cfb9SAlexey Kardashevskiy 185005c6cfb9SAlexey Kardashevskiy if (!ret && (tbl->it_type & 185105c6cfb9SAlexey Kardashevskiy (TCE_PCI_SWINV_CREATE | TCE_PCI_SWINV_FREE))) 185205c6cfb9SAlexey Kardashevskiy pnv_pci_ioda2_tce_invalidate(tbl, index, 1, false); 185305c6cfb9SAlexey Kardashevskiy 185405c6cfb9SAlexey Kardashevskiy return ret; 185505c6cfb9SAlexey Kardashevskiy } 185605c6cfb9SAlexey Kardashevskiy #endif 185705c6cfb9SAlexey Kardashevskiy 1858decbda25SAlexey Kardashevskiy static void pnv_ioda2_tce_free(struct iommu_table *tbl, long index, 1859decbda25SAlexey Kardashevskiy long npages) 1860decbda25SAlexey Kardashevskiy { 1861decbda25SAlexey Kardashevskiy pnv_tce_free(tbl, index, npages); 1862decbda25SAlexey Kardashevskiy 1863decbda25SAlexey Kardashevskiy if (tbl->it_type & TCE_PCI_SWINV_FREE) 1864decbda25SAlexey Kardashevskiy pnv_pci_ioda2_tce_invalidate(tbl, index, npages, false); 18654cce9550SGavin Shan } 18664cce9550SGavin Shan 1867da004c36SAlexey Kardashevskiy static struct iommu_table_ops pnv_ioda2_iommu_ops = { 1868decbda25SAlexey Kardashevskiy .set = pnv_ioda2_tce_build, 186905c6cfb9SAlexey Kardashevskiy #ifdef CONFIG_IOMMU_API 187005c6cfb9SAlexey Kardashevskiy .exchange = pnv_ioda2_tce_xchg, 187105c6cfb9SAlexey Kardashevskiy #endif 1872decbda25SAlexey Kardashevskiy .clear = pnv_ioda2_tce_free, 1873da004c36SAlexey Kardashevskiy .get = pnv_tce_get, 1874da004c36SAlexey Kardashevskiy }; 1875da004c36SAlexey Kardashevskiy 1876cad5cef6SGreg Kroah-Hartman static void pnv_pci_ioda_setup_dma_pe(struct pnv_phb *phb, 1877cad5cef6SGreg Kroah-Hartman struct pnv_ioda_pe *pe, unsigned int base, 1878184cd4a3SBenjamin Herrenschmidt unsigned int segs) 1879184cd4a3SBenjamin Herrenschmidt { 1880184cd4a3SBenjamin Herrenschmidt 1881184cd4a3SBenjamin Herrenschmidt struct page *tce_mem = NULL; 1882184cd4a3SBenjamin Herrenschmidt struct iommu_table *tbl; 1883184cd4a3SBenjamin Herrenschmidt unsigned int i; 1884184cd4a3SBenjamin Herrenschmidt int64_t rc; 1885184cd4a3SBenjamin Herrenschmidt void *addr; 1886184cd4a3SBenjamin Herrenschmidt 1887184cd4a3SBenjamin Herrenschmidt /* XXX FIXME: Handle 64-bit only DMA devices */ 1888184cd4a3SBenjamin Herrenschmidt /* XXX FIXME: Provide 64-bit DMA facilities & non-4K TCE tables etc.. */ 1889184cd4a3SBenjamin Herrenschmidt /* XXX FIXME: Allocate multi-level tables on PHB3 */ 1890184cd4a3SBenjamin Herrenschmidt 1891184cd4a3SBenjamin Herrenschmidt /* We shouldn't already have a 32-bit DMA associated */ 1892184cd4a3SBenjamin Herrenschmidt if (WARN_ON(pe->tce32_seg >= 0)) 1893184cd4a3SBenjamin Herrenschmidt return; 1894184cd4a3SBenjamin Herrenschmidt 18950eaf4defSAlexey Kardashevskiy tbl = pnv_pci_table_alloc(phb->hose->node); 1896b348aa65SAlexey Kardashevskiy iommu_register_group(&pe->table_group, phb->hose->global_number, 1897b348aa65SAlexey Kardashevskiy pe->pe_number); 18980eaf4defSAlexey Kardashevskiy pnv_pci_link_table_and_group(phb->hose->node, 0, tbl, &pe->table_group); 1899c5773822SAlexey Kardashevskiy 1900184cd4a3SBenjamin Herrenschmidt /* Grab a 32-bit TCE table */ 1901184cd4a3SBenjamin Herrenschmidt pe->tce32_seg = base; 1902184cd4a3SBenjamin Herrenschmidt pe_info(pe, " Setting up 32-bit TCE table at %08x..%08x\n", 1903184cd4a3SBenjamin Herrenschmidt (base << 28), ((base + segs) << 28) - 1); 1904184cd4a3SBenjamin Herrenschmidt 1905184cd4a3SBenjamin Herrenschmidt /* XXX Currently, we allocate one big contiguous table for the 1906184cd4a3SBenjamin Herrenschmidt * TCEs. We only really need one chunk per 256M of TCE space 1907184cd4a3SBenjamin Herrenschmidt * (ie per segment) but that's an optimization for later, it 1908184cd4a3SBenjamin Herrenschmidt * requires some added smarts with our get/put_tce implementation 1909184cd4a3SBenjamin Herrenschmidt */ 1910184cd4a3SBenjamin Herrenschmidt tce_mem = alloc_pages_node(phb->hose->node, GFP_KERNEL, 1911184cd4a3SBenjamin Herrenschmidt get_order(TCE32_TABLE_SIZE * segs)); 1912184cd4a3SBenjamin Herrenschmidt if (!tce_mem) { 1913184cd4a3SBenjamin Herrenschmidt pe_err(pe, " Failed to allocate a 32-bit TCE memory\n"); 1914184cd4a3SBenjamin Herrenschmidt goto fail; 1915184cd4a3SBenjamin Herrenschmidt } 1916184cd4a3SBenjamin Herrenschmidt addr = page_address(tce_mem); 1917184cd4a3SBenjamin Herrenschmidt memset(addr, 0, TCE32_TABLE_SIZE * segs); 1918184cd4a3SBenjamin Herrenschmidt 1919184cd4a3SBenjamin Herrenschmidt /* Configure HW */ 1920184cd4a3SBenjamin Herrenschmidt for (i = 0; i < segs; i++) { 1921184cd4a3SBenjamin Herrenschmidt rc = opal_pci_map_pe_dma_window(phb->opal_id, 1922184cd4a3SBenjamin Herrenschmidt pe->pe_number, 1923184cd4a3SBenjamin Herrenschmidt base + i, 1, 1924184cd4a3SBenjamin Herrenschmidt __pa(addr) + TCE32_TABLE_SIZE * i, 1925184cd4a3SBenjamin Herrenschmidt TCE32_TABLE_SIZE, 0x1000); 1926184cd4a3SBenjamin Herrenschmidt if (rc) { 1927184cd4a3SBenjamin Herrenschmidt pe_err(pe, " Failed to configure 32-bit TCE table," 1928184cd4a3SBenjamin Herrenschmidt " err %ld\n", rc); 1929184cd4a3SBenjamin Herrenschmidt goto fail; 1930184cd4a3SBenjamin Herrenschmidt } 1931184cd4a3SBenjamin Herrenschmidt } 1932184cd4a3SBenjamin Herrenschmidt 1933184cd4a3SBenjamin Herrenschmidt /* Setup linux iommu table */ 1934184cd4a3SBenjamin Herrenschmidt pnv_pci_setup_iommu_table(tbl, addr, TCE32_TABLE_SIZE * segs, 19358fa5d454SAlexey Kardashevskiy base << 28, IOMMU_PAGE_SHIFT_4K); 1936184cd4a3SBenjamin Herrenschmidt 1937184cd4a3SBenjamin Herrenschmidt /* OPAL variant of P7IOC SW invalidated TCEs */ 19385780fb04SAlexey Kardashevskiy if (phb->ioda.tce_inval_reg) 193965fd766bSGavin Shan tbl->it_type |= (TCE_PCI_SWINV_CREATE | 194065fd766bSGavin Shan TCE_PCI_SWINV_FREE | 194165fd766bSGavin Shan TCE_PCI_SWINV_PAIR); 19425780fb04SAlexey Kardashevskiy 1943da004c36SAlexey Kardashevskiy tbl->it_ops = &pnv_ioda1_iommu_ops; 1944184cd4a3SBenjamin Herrenschmidt iommu_init_table(tbl, phb->hose->node); 1945184cd4a3SBenjamin Herrenschmidt 1946781a868fSWei Yang if (pe->flags & PNV_IODA_PE_DEV) { 19474617082eSAlexey Kardashevskiy /* 19484617082eSAlexey Kardashevskiy * Setting table base here only for carrying iommu_group 19494617082eSAlexey Kardashevskiy * further down to let iommu_add_device() do the job. 19504617082eSAlexey Kardashevskiy * pnv_pci_ioda_dma_dev_setup will override it later anyway. 19514617082eSAlexey Kardashevskiy */ 19524617082eSAlexey Kardashevskiy set_iommu_table_base(&pe->pdev->dev, tbl); 19534617082eSAlexey Kardashevskiy iommu_add_device(&pe->pdev->dev); 1954c5773822SAlexey Kardashevskiy } else if (pe->flags & (PNV_IODA_PE_BUS | PNV_IODA_PE_BUS_ALL)) 1955ea30e99eSAlexey Kardashevskiy pnv_ioda_setup_bus_dma(pe, pe->pbus); 195674251fe2SBenjamin Herrenschmidt 1957184cd4a3SBenjamin Herrenschmidt return; 1958184cd4a3SBenjamin Herrenschmidt fail: 1959184cd4a3SBenjamin Herrenschmidt /* XXX Failure: Try to fallback to 64-bit only ? */ 1960184cd4a3SBenjamin Herrenschmidt if (pe->tce32_seg >= 0) 1961184cd4a3SBenjamin Herrenschmidt pe->tce32_seg = -1; 1962184cd4a3SBenjamin Herrenschmidt if (tce_mem) 1963184cd4a3SBenjamin Herrenschmidt __free_pages(tce_mem, get_order(TCE32_TABLE_SIZE * segs)); 19640eaf4defSAlexey Kardashevskiy if (tbl) { 19650eaf4defSAlexey Kardashevskiy pnv_pci_unlink_table_and_group(tbl, &pe->table_group); 19660eaf4defSAlexey Kardashevskiy iommu_free_table(tbl, "pnv"); 19670eaf4defSAlexey Kardashevskiy } 1968184cd4a3SBenjamin Herrenschmidt } 1969184cd4a3SBenjamin Herrenschmidt 1970f87a8864SAlexey Kardashevskiy static void pnv_pci_ioda2_set_bypass(struct pnv_ioda_pe *pe, bool enable) 1971cd15b048SBenjamin Herrenschmidt { 1972cd15b048SBenjamin Herrenschmidt uint16_t window_id = (pe->pe_number << 1 ) + 1; 1973cd15b048SBenjamin Herrenschmidt int64_t rc; 1974cd15b048SBenjamin Herrenschmidt 1975cd15b048SBenjamin Herrenschmidt pe_info(pe, "%sabling 64-bit DMA bypass\n", enable ? "En" : "Dis"); 1976cd15b048SBenjamin Herrenschmidt if (enable) { 1977cd15b048SBenjamin Herrenschmidt phys_addr_t top = memblock_end_of_DRAM(); 1978cd15b048SBenjamin Herrenschmidt 1979cd15b048SBenjamin Herrenschmidt top = roundup_pow_of_two(top); 1980cd15b048SBenjamin Herrenschmidt rc = opal_pci_map_pe_dma_window_real(pe->phb->opal_id, 1981cd15b048SBenjamin Herrenschmidt pe->pe_number, 1982cd15b048SBenjamin Herrenschmidt window_id, 1983cd15b048SBenjamin Herrenschmidt pe->tce_bypass_base, 1984cd15b048SBenjamin Herrenschmidt top); 1985cd15b048SBenjamin Herrenschmidt } else { 1986cd15b048SBenjamin Herrenschmidt rc = opal_pci_map_pe_dma_window_real(pe->phb->opal_id, 1987cd15b048SBenjamin Herrenschmidt pe->pe_number, 1988cd15b048SBenjamin Herrenschmidt window_id, 1989cd15b048SBenjamin Herrenschmidt pe->tce_bypass_base, 1990cd15b048SBenjamin Herrenschmidt 0); 1991cd15b048SBenjamin Herrenschmidt } 1992cd15b048SBenjamin Herrenschmidt if (rc) 1993cd15b048SBenjamin Herrenschmidt pe_err(pe, "OPAL error %lld configuring bypass window\n", rc); 1994cd15b048SBenjamin Herrenschmidt else 1995cd15b048SBenjamin Herrenschmidt pe->tce_bypass_enabled = enable; 1996cd15b048SBenjamin Herrenschmidt } 1997cd15b048SBenjamin Herrenschmidt 1998f87a8864SAlexey Kardashevskiy #ifdef CONFIG_IOMMU_API 1999f87a8864SAlexey Kardashevskiy static void pnv_ioda2_take_ownership(struct iommu_table_group *table_group) 2000cd15b048SBenjamin Herrenschmidt { 2001f87a8864SAlexey Kardashevskiy struct pnv_ioda_pe *pe = container_of(table_group, struct pnv_ioda_pe, 2002f87a8864SAlexey Kardashevskiy table_group); 2003cd15b048SBenjamin Herrenschmidt 2004f87a8864SAlexey Kardashevskiy iommu_take_ownership(table_group->tables[0]); 2005f87a8864SAlexey Kardashevskiy pnv_pci_ioda2_set_bypass(pe, false); 2006cd15b048SBenjamin Herrenschmidt } 2007cd15b048SBenjamin Herrenschmidt 2008f87a8864SAlexey Kardashevskiy static void pnv_ioda2_release_ownership(struct iommu_table_group *table_group) 2009f87a8864SAlexey Kardashevskiy { 2010f87a8864SAlexey Kardashevskiy struct pnv_ioda_pe *pe = container_of(table_group, struct pnv_ioda_pe, 2011f87a8864SAlexey Kardashevskiy table_group); 2012f87a8864SAlexey Kardashevskiy 2013f87a8864SAlexey Kardashevskiy iommu_release_ownership(table_group->tables[0]); 2014f87a8864SAlexey Kardashevskiy pnv_pci_ioda2_set_bypass(pe, true); 2015f87a8864SAlexey Kardashevskiy } 2016f87a8864SAlexey Kardashevskiy 2017f87a8864SAlexey Kardashevskiy static struct iommu_table_group_ops pnv_pci_ioda2_ops = { 2018f87a8864SAlexey Kardashevskiy .take_ownership = pnv_ioda2_take_ownership, 2019f87a8864SAlexey Kardashevskiy .release_ownership = pnv_ioda2_release_ownership, 2020f87a8864SAlexey Kardashevskiy }; 2021f87a8864SAlexey Kardashevskiy #endif 2022f87a8864SAlexey Kardashevskiy 20235780fb04SAlexey Kardashevskiy static void pnv_pci_ioda_setup_opal_tce_kill(struct pnv_phb *phb) 20245780fb04SAlexey Kardashevskiy { 20255780fb04SAlexey Kardashevskiy const __be64 *swinvp; 20265780fb04SAlexey Kardashevskiy 20275780fb04SAlexey Kardashevskiy /* OPAL variant of PHB3 invalidated TCEs */ 20285780fb04SAlexey Kardashevskiy swinvp = of_get_property(phb->hose->dn, "ibm,opal-tce-kill", NULL); 20295780fb04SAlexey Kardashevskiy if (!swinvp) 20305780fb04SAlexey Kardashevskiy return; 20315780fb04SAlexey Kardashevskiy 20325780fb04SAlexey Kardashevskiy phb->ioda.tce_inval_reg_phys = be64_to_cpup(swinvp); 20335780fb04SAlexey Kardashevskiy phb->ioda.tce_inval_reg = ioremap(phb->ioda.tce_inval_reg_phys, 8); 20345780fb04SAlexey Kardashevskiy } 20355780fb04SAlexey Kardashevskiy 2036373f5657SGavin Shan static void pnv_pci_ioda2_setup_dma_pe(struct pnv_phb *phb, 2037373f5657SGavin Shan struct pnv_ioda_pe *pe) 2038373f5657SGavin Shan { 2039373f5657SGavin Shan struct page *tce_mem = NULL; 2040373f5657SGavin Shan void *addr; 2041373f5657SGavin Shan struct iommu_table *tbl; 2042373f5657SGavin Shan unsigned int tce_table_size, end; 2043373f5657SGavin Shan int64_t rc; 2044373f5657SGavin Shan 2045373f5657SGavin Shan /* We shouldn't already have a 32-bit DMA associated */ 2046373f5657SGavin Shan if (WARN_ON(pe->tce32_seg >= 0)) 2047373f5657SGavin Shan return; 2048373f5657SGavin Shan 2049f87a8864SAlexey Kardashevskiy /* TVE #1 is selected by PCI address bit 59 */ 2050f87a8864SAlexey Kardashevskiy pe->tce_bypass_base = 1ull << 59; 2051f87a8864SAlexey Kardashevskiy 20520eaf4defSAlexey Kardashevskiy tbl = pnv_pci_table_alloc(phb->hose->node); 2053b348aa65SAlexey Kardashevskiy iommu_register_group(&pe->table_group, phb->hose->global_number, 2054b348aa65SAlexey Kardashevskiy pe->pe_number); 20550eaf4defSAlexey Kardashevskiy pnv_pci_link_table_and_group(phb->hose->node, 0, tbl, &pe->table_group); 2056c5773822SAlexey Kardashevskiy 2057373f5657SGavin Shan /* The PE will reserve all possible 32-bits space */ 2058373f5657SGavin Shan pe->tce32_seg = 0; 2059373f5657SGavin Shan end = (1 << ilog2(phb->ioda.m32_pci_base)); 2060373f5657SGavin Shan tce_table_size = (end / 0x1000) * 8; 2061373f5657SGavin Shan pe_info(pe, "Setting up 32-bit TCE table at 0..%08x\n", 2062373f5657SGavin Shan end); 2063373f5657SGavin Shan 2064373f5657SGavin Shan /* Allocate TCE table */ 2065373f5657SGavin Shan tce_mem = alloc_pages_node(phb->hose->node, GFP_KERNEL, 2066373f5657SGavin Shan get_order(tce_table_size)); 2067373f5657SGavin Shan if (!tce_mem) { 2068373f5657SGavin Shan pe_err(pe, "Failed to allocate a 32-bit TCE memory\n"); 2069373f5657SGavin Shan goto fail; 2070373f5657SGavin Shan } 2071373f5657SGavin Shan addr = page_address(tce_mem); 2072373f5657SGavin Shan memset(addr, 0, tce_table_size); 2073373f5657SGavin Shan 2074e5aad1e6SAlexey Kardashevskiy /* Setup linux iommu table */ 2075e5aad1e6SAlexey Kardashevskiy pnv_pci_setup_iommu_table(tbl, addr, tce_table_size, 0, 2076e5aad1e6SAlexey Kardashevskiy IOMMU_PAGE_SHIFT_4K); 2077e5aad1e6SAlexey Kardashevskiy 2078e5aad1e6SAlexey Kardashevskiy tbl->it_ops = &pnv_ioda2_iommu_ops; 2079e5aad1e6SAlexey Kardashevskiy iommu_init_table(tbl, phb->hose->node); 2080e5aad1e6SAlexey Kardashevskiy #ifdef CONFIG_IOMMU_API 2081e5aad1e6SAlexey Kardashevskiy pe->table_group.ops = &pnv_pci_ioda2_ops; 2082e5aad1e6SAlexey Kardashevskiy #endif 2083e5aad1e6SAlexey Kardashevskiy 2084373f5657SGavin Shan /* 2085373f5657SGavin Shan * Map TCE table through TVT. The TVE index is the PE number 2086373f5657SGavin Shan * shifted by 1 bit for 32-bits DMA space. 2087373f5657SGavin Shan */ 2088373f5657SGavin Shan rc = opal_pci_map_pe_dma_window(phb->opal_id, pe->pe_number, 2089e5aad1e6SAlexey Kardashevskiy pe->pe_number << 1, 1, __pa(tbl->it_base), 2090e5aad1e6SAlexey Kardashevskiy tbl->it_size << 3, 1ULL << tbl->it_page_shift); 2091373f5657SGavin Shan if (rc) { 2092373f5657SGavin Shan pe_err(pe, "Failed to configure 32-bit TCE table," 2093373f5657SGavin Shan " err %ld\n", rc); 2094373f5657SGavin Shan goto fail; 2095373f5657SGavin Shan } 2096373f5657SGavin Shan 20975780fb04SAlexey Kardashevskiy pnv_pci_ioda2_tce_invalidate_entire(pe); 20985780fb04SAlexey Kardashevskiy 2099373f5657SGavin Shan /* OPAL variant of PHB3 invalidated TCEs */ 21005780fb04SAlexey Kardashevskiy if (phb->ioda.tce_inval_reg) 210165fd766bSGavin Shan tbl->it_type |= (TCE_PCI_SWINV_CREATE | TCE_PCI_SWINV_FREE); 21025780fb04SAlexey Kardashevskiy 2103781a868fSWei Yang if (pe->flags & PNV_IODA_PE_DEV) { 21044617082eSAlexey Kardashevskiy /* 21054617082eSAlexey Kardashevskiy * Setting table base here only for carrying iommu_group 21064617082eSAlexey Kardashevskiy * further down to let iommu_add_device() do the job. 21074617082eSAlexey Kardashevskiy * pnv_pci_ioda_dma_dev_setup will override it later anyway. 21084617082eSAlexey Kardashevskiy */ 21094617082eSAlexey Kardashevskiy set_iommu_table_base(&pe->pdev->dev, tbl); 21104617082eSAlexey Kardashevskiy iommu_add_device(&pe->pdev->dev); 2111c5773822SAlexey Kardashevskiy } else if (pe->flags & (PNV_IODA_PE_BUS | PNV_IODA_PE_BUS_ALL)) 2112ea30e99eSAlexey Kardashevskiy pnv_ioda_setup_bus_dma(pe, pe->pbus); 211374251fe2SBenjamin Herrenschmidt 2114cd15b048SBenjamin Herrenschmidt /* Also create a bypass window */ 21154e287840SThadeu Lima de Souza Cascardo if (!pnv_iommu_bypass_disabled) 2116f87a8864SAlexey Kardashevskiy pnv_pci_ioda2_set_bypass(pe, true); 21174e287840SThadeu Lima de Souza Cascardo 2118373f5657SGavin Shan return; 2119373f5657SGavin Shan fail: 2120373f5657SGavin Shan if (pe->tce32_seg >= 0) 2121373f5657SGavin Shan pe->tce32_seg = -1; 2122373f5657SGavin Shan if (tce_mem) 2123373f5657SGavin Shan __free_pages(tce_mem, get_order(tce_table_size)); 21240eaf4defSAlexey Kardashevskiy if (tbl) { 21250eaf4defSAlexey Kardashevskiy pnv_pci_unlink_table_and_group(tbl, &pe->table_group); 21260eaf4defSAlexey Kardashevskiy iommu_free_table(tbl, "pnv"); 21270eaf4defSAlexey Kardashevskiy } 2128373f5657SGavin Shan } 2129373f5657SGavin Shan 2130cad5cef6SGreg Kroah-Hartman static void pnv_ioda_setup_dma(struct pnv_phb *phb) 2131184cd4a3SBenjamin Herrenschmidt { 2132184cd4a3SBenjamin Herrenschmidt struct pci_controller *hose = phb->hose; 2133184cd4a3SBenjamin Herrenschmidt unsigned int residual, remaining, segs, tw, base; 2134184cd4a3SBenjamin Herrenschmidt struct pnv_ioda_pe *pe; 2135184cd4a3SBenjamin Herrenschmidt 2136184cd4a3SBenjamin Herrenschmidt /* If we have more PE# than segments available, hand out one 2137184cd4a3SBenjamin Herrenschmidt * per PE until we run out and let the rest fail. If not, 2138184cd4a3SBenjamin Herrenschmidt * then we assign at least one segment per PE, plus more based 2139184cd4a3SBenjamin Herrenschmidt * on the amount of devices under that PE 2140184cd4a3SBenjamin Herrenschmidt */ 2141184cd4a3SBenjamin Herrenschmidt if (phb->ioda.dma_pe_count > phb->ioda.tce32_count) 2142184cd4a3SBenjamin Herrenschmidt residual = 0; 2143184cd4a3SBenjamin Herrenschmidt else 2144184cd4a3SBenjamin Herrenschmidt residual = phb->ioda.tce32_count - 2145184cd4a3SBenjamin Herrenschmidt phb->ioda.dma_pe_count; 2146184cd4a3SBenjamin Herrenschmidt 2147184cd4a3SBenjamin Herrenschmidt pr_info("PCI: Domain %04x has %ld available 32-bit DMA segments\n", 2148184cd4a3SBenjamin Herrenschmidt hose->global_number, phb->ioda.tce32_count); 2149184cd4a3SBenjamin Herrenschmidt pr_info("PCI: %d PE# for a total weight of %d\n", 2150184cd4a3SBenjamin Herrenschmidt phb->ioda.dma_pe_count, phb->ioda.dma_weight); 2151184cd4a3SBenjamin Herrenschmidt 21525780fb04SAlexey Kardashevskiy pnv_pci_ioda_setup_opal_tce_kill(phb); 21535780fb04SAlexey Kardashevskiy 2154184cd4a3SBenjamin Herrenschmidt /* Walk our PE list and configure their DMA segments, hand them 2155184cd4a3SBenjamin Herrenschmidt * out one base segment plus any residual segments based on 2156184cd4a3SBenjamin Herrenschmidt * weight 2157184cd4a3SBenjamin Herrenschmidt */ 2158184cd4a3SBenjamin Herrenschmidt remaining = phb->ioda.tce32_count; 2159184cd4a3SBenjamin Herrenschmidt tw = phb->ioda.dma_weight; 2160184cd4a3SBenjamin Herrenschmidt base = 0; 21617ebdf956SGavin Shan list_for_each_entry(pe, &phb->ioda.pe_dma_list, dma_link) { 2162184cd4a3SBenjamin Herrenschmidt if (!pe->dma_weight) 2163184cd4a3SBenjamin Herrenschmidt continue; 2164184cd4a3SBenjamin Herrenschmidt if (!remaining) { 2165184cd4a3SBenjamin Herrenschmidt pe_warn(pe, "No DMA32 resources available\n"); 2166184cd4a3SBenjamin Herrenschmidt continue; 2167184cd4a3SBenjamin Herrenschmidt } 2168184cd4a3SBenjamin Herrenschmidt segs = 1; 2169184cd4a3SBenjamin Herrenschmidt if (residual) { 2170184cd4a3SBenjamin Herrenschmidt segs += ((pe->dma_weight * residual) + (tw / 2)) / tw; 2171184cd4a3SBenjamin Herrenschmidt if (segs > remaining) 2172184cd4a3SBenjamin Herrenschmidt segs = remaining; 2173184cd4a3SBenjamin Herrenschmidt } 2174373f5657SGavin Shan 2175373f5657SGavin Shan /* 2176373f5657SGavin Shan * For IODA2 compliant PHB3, we needn't care about the weight. 2177373f5657SGavin Shan * The all available 32-bits DMA space will be assigned to 2178373f5657SGavin Shan * the specific PE. 2179373f5657SGavin Shan */ 2180373f5657SGavin Shan if (phb->type == PNV_PHB_IODA1) { 2181184cd4a3SBenjamin Herrenschmidt pe_info(pe, "DMA weight %d, assigned %d DMA32 segments\n", 2182184cd4a3SBenjamin Herrenschmidt pe->dma_weight, segs); 2183184cd4a3SBenjamin Herrenschmidt pnv_pci_ioda_setup_dma_pe(phb, pe, base, segs); 2184373f5657SGavin Shan } else { 2185373f5657SGavin Shan pe_info(pe, "Assign DMA32 space\n"); 2186373f5657SGavin Shan segs = 0; 2187373f5657SGavin Shan pnv_pci_ioda2_setup_dma_pe(phb, pe); 2188373f5657SGavin Shan } 2189373f5657SGavin Shan 2190184cd4a3SBenjamin Herrenschmidt remaining -= segs; 2191184cd4a3SBenjamin Herrenschmidt base += segs; 2192184cd4a3SBenjamin Herrenschmidt } 2193184cd4a3SBenjamin Herrenschmidt } 2194184cd4a3SBenjamin Herrenschmidt 2195184cd4a3SBenjamin Herrenschmidt #ifdef CONFIG_PCI_MSI 2196137436c9SGavin Shan static void pnv_ioda2_msi_eoi(struct irq_data *d) 2197137436c9SGavin Shan { 2198137436c9SGavin Shan unsigned int hw_irq = (unsigned int)irqd_to_hwirq(d); 2199137436c9SGavin Shan struct irq_chip *chip = irq_data_get_irq_chip(d); 2200137436c9SGavin Shan struct pnv_phb *phb = container_of(chip, struct pnv_phb, 2201137436c9SGavin Shan ioda.irq_chip); 2202137436c9SGavin Shan int64_t rc; 2203137436c9SGavin Shan 2204137436c9SGavin Shan rc = opal_pci_msi_eoi(phb->opal_id, hw_irq); 2205137436c9SGavin Shan WARN_ON_ONCE(rc); 2206137436c9SGavin Shan 2207137436c9SGavin Shan icp_native_eoi(d); 2208137436c9SGavin Shan } 2209137436c9SGavin Shan 2210fd9a1c26SIan Munsie 2211fd9a1c26SIan Munsie static void set_msi_irq_chip(struct pnv_phb *phb, unsigned int virq) 2212fd9a1c26SIan Munsie { 2213fd9a1c26SIan Munsie struct irq_data *idata; 2214fd9a1c26SIan Munsie struct irq_chip *ichip; 2215fd9a1c26SIan Munsie 2216fd9a1c26SIan Munsie if (phb->type != PNV_PHB_IODA2) 2217fd9a1c26SIan Munsie return; 2218fd9a1c26SIan Munsie 2219fd9a1c26SIan Munsie if (!phb->ioda.irq_chip_init) { 2220fd9a1c26SIan Munsie /* 2221fd9a1c26SIan Munsie * First time we setup an MSI IRQ, we need to setup the 2222fd9a1c26SIan Munsie * corresponding IRQ chip to route correctly. 2223fd9a1c26SIan Munsie */ 2224fd9a1c26SIan Munsie idata = irq_get_irq_data(virq); 2225fd9a1c26SIan Munsie ichip = irq_data_get_irq_chip(idata); 2226fd9a1c26SIan Munsie phb->ioda.irq_chip_init = 1; 2227fd9a1c26SIan Munsie phb->ioda.irq_chip = *ichip; 2228fd9a1c26SIan Munsie phb->ioda.irq_chip.irq_eoi = pnv_ioda2_msi_eoi; 2229fd9a1c26SIan Munsie } 2230fd9a1c26SIan Munsie irq_set_chip(virq, &phb->ioda.irq_chip); 2231fd9a1c26SIan Munsie } 2232fd9a1c26SIan Munsie 223380c49c7eSIan Munsie #ifdef CONFIG_CXL_BASE 223480c49c7eSIan Munsie 22356f963ec2SRyan Grimm struct device_node *pnv_pci_get_phb_node(struct pci_dev *dev) 223680c49c7eSIan Munsie { 223780c49c7eSIan Munsie struct pci_controller *hose = pci_bus_to_host(dev->bus); 223880c49c7eSIan Munsie 22396f963ec2SRyan Grimm return of_node_get(hose->dn); 224080c49c7eSIan Munsie } 22416f963ec2SRyan Grimm EXPORT_SYMBOL(pnv_pci_get_phb_node); 224280c49c7eSIan Munsie 22431212aa1cSRyan Grimm int pnv_phb_to_cxl_mode(struct pci_dev *dev, uint64_t mode) 224480c49c7eSIan Munsie { 224580c49c7eSIan Munsie struct pci_controller *hose = pci_bus_to_host(dev->bus); 224680c49c7eSIan Munsie struct pnv_phb *phb = hose->private_data; 224780c49c7eSIan Munsie struct pnv_ioda_pe *pe; 224880c49c7eSIan Munsie int rc; 224980c49c7eSIan Munsie 225080c49c7eSIan Munsie pe = pnv_ioda_get_pe(dev); 225180c49c7eSIan Munsie if (!pe) 225280c49c7eSIan Munsie return -ENODEV; 225380c49c7eSIan Munsie 225480c49c7eSIan Munsie pe_info(pe, "Switching PHB to CXL\n"); 225580c49c7eSIan Munsie 22561212aa1cSRyan Grimm rc = opal_pci_set_phb_cxl_mode(phb->opal_id, mode, pe->pe_number); 225780c49c7eSIan Munsie if (rc) 225880c49c7eSIan Munsie dev_err(&dev->dev, "opal_pci_set_phb_cxl_mode failed: %i\n", rc); 225980c49c7eSIan Munsie 226080c49c7eSIan Munsie return rc; 226180c49c7eSIan Munsie } 22621212aa1cSRyan Grimm EXPORT_SYMBOL(pnv_phb_to_cxl_mode); 226380c49c7eSIan Munsie 226480c49c7eSIan Munsie /* Find PHB for cxl dev and allocate MSI hwirqs? 226580c49c7eSIan Munsie * Returns the absolute hardware IRQ number 226680c49c7eSIan Munsie */ 226780c49c7eSIan Munsie int pnv_cxl_alloc_hwirqs(struct pci_dev *dev, int num) 226880c49c7eSIan Munsie { 226980c49c7eSIan Munsie struct pci_controller *hose = pci_bus_to_host(dev->bus); 227080c49c7eSIan Munsie struct pnv_phb *phb = hose->private_data; 227180c49c7eSIan Munsie int hwirq = msi_bitmap_alloc_hwirqs(&phb->msi_bmp, num); 227280c49c7eSIan Munsie 227380c49c7eSIan Munsie if (hwirq < 0) { 227480c49c7eSIan Munsie dev_warn(&dev->dev, "Failed to find a free MSI\n"); 227580c49c7eSIan Munsie return -ENOSPC; 227680c49c7eSIan Munsie } 227780c49c7eSIan Munsie 227880c49c7eSIan Munsie return phb->msi_base + hwirq; 227980c49c7eSIan Munsie } 228080c49c7eSIan Munsie EXPORT_SYMBOL(pnv_cxl_alloc_hwirqs); 228180c49c7eSIan Munsie 228280c49c7eSIan Munsie void pnv_cxl_release_hwirqs(struct pci_dev *dev, int hwirq, int num) 228380c49c7eSIan Munsie { 228480c49c7eSIan Munsie struct pci_controller *hose = pci_bus_to_host(dev->bus); 228580c49c7eSIan Munsie struct pnv_phb *phb = hose->private_data; 228680c49c7eSIan Munsie 228780c49c7eSIan Munsie msi_bitmap_free_hwirqs(&phb->msi_bmp, hwirq - phb->msi_base, num); 228880c49c7eSIan Munsie } 228980c49c7eSIan Munsie EXPORT_SYMBOL(pnv_cxl_release_hwirqs); 229080c49c7eSIan Munsie 229180c49c7eSIan Munsie void pnv_cxl_release_hwirq_ranges(struct cxl_irq_ranges *irqs, 229280c49c7eSIan Munsie struct pci_dev *dev) 229380c49c7eSIan Munsie { 229480c49c7eSIan Munsie struct pci_controller *hose = pci_bus_to_host(dev->bus); 229580c49c7eSIan Munsie struct pnv_phb *phb = hose->private_data; 229680c49c7eSIan Munsie int i, hwirq; 229780c49c7eSIan Munsie 229880c49c7eSIan Munsie for (i = 1; i < CXL_IRQ_RANGES; i++) { 229980c49c7eSIan Munsie if (!irqs->range[i]) 230080c49c7eSIan Munsie continue; 230180c49c7eSIan Munsie pr_devel("cxl release irq range 0x%x: offset: 0x%lx limit: %ld\n", 230280c49c7eSIan Munsie i, irqs->offset[i], 230380c49c7eSIan Munsie irqs->range[i]); 230480c49c7eSIan Munsie hwirq = irqs->offset[i] - phb->msi_base; 230580c49c7eSIan Munsie msi_bitmap_free_hwirqs(&phb->msi_bmp, hwirq, 230680c49c7eSIan Munsie irqs->range[i]); 230780c49c7eSIan Munsie } 230880c49c7eSIan Munsie } 230980c49c7eSIan Munsie EXPORT_SYMBOL(pnv_cxl_release_hwirq_ranges); 231080c49c7eSIan Munsie 231180c49c7eSIan Munsie int pnv_cxl_alloc_hwirq_ranges(struct cxl_irq_ranges *irqs, 231280c49c7eSIan Munsie struct pci_dev *dev, int num) 231380c49c7eSIan Munsie { 231480c49c7eSIan Munsie struct pci_controller *hose = pci_bus_to_host(dev->bus); 231580c49c7eSIan Munsie struct pnv_phb *phb = hose->private_data; 231680c49c7eSIan Munsie int i, hwirq, try; 231780c49c7eSIan Munsie 231880c49c7eSIan Munsie memset(irqs, 0, sizeof(struct cxl_irq_ranges)); 231980c49c7eSIan Munsie 232080c49c7eSIan Munsie /* 0 is reserved for the multiplexed PSL DSI interrupt */ 232180c49c7eSIan Munsie for (i = 1; i < CXL_IRQ_RANGES && num; i++) { 232280c49c7eSIan Munsie try = num; 232380c49c7eSIan Munsie while (try) { 232480c49c7eSIan Munsie hwirq = msi_bitmap_alloc_hwirqs(&phb->msi_bmp, try); 232580c49c7eSIan Munsie if (hwirq >= 0) 232680c49c7eSIan Munsie break; 232780c49c7eSIan Munsie try /= 2; 232880c49c7eSIan Munsie } 232980c49c7eSIan Munsie if (!try) 233080c49c7eSIan Munsie goto fail; 233180c49c7eSIan Munsie 233280c49c7eSIan Munsie irqs->offset[i] = phb->msi_base + hwirq; 233380c49c7eSIan Munsie irqs->range[i] = try; 233480c49c7eSIan Munsie pr_devel("cxl alloc irq range 0x%x: offset: 0x%lx limit: %li\n", 233580c49c7eSIan Munsie i, irqs->offset[i], irqs->range[i]); 233680c49c7eSIan Munsie num -= try; 233780c49c7eSIan Munsie } 233880c49c7eSIan Munsie if (num) 233980c49c7eSIan Munsie goto fail; 234080c49c7eSIan Munsie 234180c49c7eSIan Munsie return 0; 234280c49c7eSIan Munsie fail: 234380c49c7eSIan Munsie pnv_cxl_release_hwirq_ranges(irqs, dev); 234480c49c7eSIan Munsie return -ENOSPC; 234580c49c7eSIan Munsie } 234680c49c7eSIan Munsie EXPORT_SYMBOL(pnv_cxl_alloc_hwirq_ranges); 234780c49c7eSIan Munsie 234880c49c7eSIan Munsie int pnv_cxl_get_irq_count(struct pci_dev *dev) 234980c49c7eSIan Munsie { 235080c49c7eSIan Munsie struct pci_controller *hose = pci_bus_to_host(dev->bus); 235180c49c7eSIan Munsie struct pnv_phb *phb = hose->private_data; 235280c49c7eSIan Munsie 235380c49c7eSIan Munsie return phb->msi_bmp.irq_count; 235480c49c7eSIan Munsie } 235580c49c7eSIan Munsie EXPORT_SYMBOL(pnv_cxl_get_irq_count); 235680c49c7eSIan Munsie 235780c49c7eSIan Munsie int pnv_cxl_ioda_msi_setup(struct pci_dev *dev, unsigned int hwirq, 235880c49c7eSIan Munsie unsigned int virq) 235980c49c7eSIan Munsie { 236080c49c7eSIan Munsie struct pci_controller *hose = pci_bus_to_host(dev->bus); 236180c49c7eSIan Munsie struct pnv_phb *phb = hose->private_data; 236280c49c7eSIan Munsie unsigned int xive_num = hwirq - phb->msi_base; 236380c49c7eSIan Munsie struct pnv_ioda_pe *pe; 236480c49c7eSIan Munsie int rc; 236580c49c7eSIan Munsie 236680c49c7eSIan Munsie if (!(pe = pnv_ioda_get_pe(dev))) 236780c49c7eSIan Munsie return -ENODEV; 236880c49c7eSIan Munsie 236980c49c7eSIan Munsie /* Assign XIVE to PE */ 237080c49c7eSIan Munsie rc = opal_pci_set_xive_pe(phb->opal_id, pe->pe_number, xive_num); 237180c49c7eSIan Munsie if (rc) { 237280c49c7eSIan Munsie pe_warn(pe, "%s: OPAL error %d setting msi_base 0x%x " 237380c49c7eSIan Munsie "hwirq 0x%x XIVE 0x%x PE\n", 237480c49c7eSIan Munsie pci_name(dev), rc, phb->msi_base, hwirq, xive_num); 237580c49c7eSIan Munsie return -EIO; 237680c49c7eSIan Munsie } 237780c49c7eSIan Munsie set_msi_irq_chip(phb, virq); 237880c49c7eSIan Munsie 237980c49c7eSIan Munsie return 0; 238080c49c7eSIan Munsie } 238180c49c7eSIan Munsie EXPORT_SYMBOL(pnv_cxl_ioda_msi_setup); 238280c49c7eSIan Munsie #endif 238380c49c7eSIan Munsie 2384184cd4a3SBenjamin Herrenschmidt static int pnv_pci_ioda_msi_setup(struct pnv_phb *phb, struct pci_dev *dev, 2385137436c9SGavin Shan unsigned int hwirq, unsigned int virq, 2386137436c9SGavin Shan unsigned int is_64, struct msi_msg *msg) 2387184cd4a3SBenjamin Herrenschmidt { 2388184cd4a3SBenjamin Herrenschmidt struct pnv_ioda_pe *pe = pnv_ioda_get_pe(dev); 2389184cd4a3SBenjamin Herrenschmidt unsigned int xive_num = hwirq - phb->msi_base; 23903a1a4661SBenjamin Herrenschmidt __be32 data; 2391184cd4a3SBenjamin Herrenschmidt int rc; 2392184cd4a3SBenjamin Herrenschmidt 2393184cd4a3SBenjamin Herrenschmidt /* No PE assigned ? bail out ... no MSI for you ! */ 2394184cd4a3SBenjamin Herrenschmidt if (pe == NULL) 2395184cd4a3SBenjamin Herrenschmidt return -ENXIO; 2396184cd4a3SBenjamin Herrenschmidt 2397184cd4a3SBenjamin Herrenschmidt /* Check if we have an MVE */ 2398184cd4a3SBenjamin Herrenschmidt if (pe->mve_number < 0) 2399184cd4a3SBenjamin Herrenschmidt return -ENXIO; 2400184cd4a3SBenjamin Herrenschmidt 2401b72c1f65SBenjamin Herrenschmidt /* Force 32-bit MSI on some broken devices */ 240236074381SBenjamin Herrenschmidt if (dev->no_64bit_msi) 2403b72c1f65SBenjamin Herrenschmidt is_64 = 0; 2404b72c1f65SBenjamin Herrenschmidt 2405184cd4a3SBenjamin Herrenschmidt /* Assign XIVE to PE */ 2406184cd4a3SBenjamin Herrenschmidt rc = opal_pci_set_xive_pe(phb->opal_id, pe->pe_number, xive_num); 2407184cd4a3SBenjamin Herrenschmidt if (rc) { 2408184cd4a3SBenjamin Herrenschmidt pr_warn("%s: OPAL error %d setting XIVE %d PE\n", 2409184cd4a3SBenjamin Herrenschmidt pci_name(dev), rc, xive_num); 2410184cd4a3SBenjamin Herrenschmidt return -EIO; 2411184cd4a3SBenjamin Herrenschmidt } 2412184cd4a3SBenjamin Herrenschmidt 2413184cd4a3SBenjamin Herrenschmidt if (is_64) { 24143a1a4661SBenjamin Herrenschmidt __be64 addr64; 24153a1a4661SBenjamin Herrenschmidt 2416184cd4a3SBenjamin Herrenschmidt rc = opal_get_msi_64(phb->opal_id, pe->mve_number, xive_num, 1, 2417184cd4a3SBenjamin Herrenschmidt &addr64, &data); 2418184cd4a3SBenjamin Herrenschmidt if (rc) { 2419184cd4a3SBenjamin Herrenschmidt pr_warn("%s: OPAL error %d getting 64-bit MSI data\n", 2420184cd4a3SBenjamin Herrenschmidt pci_name(dev), rc); 2421184cd4a3SBenjamin Herrenschmidt return -EIO; 2422184cd4a3SBenjamin Herrenschmidt } 24233a1a4661SBenjamin Herrenschmidt msg->address_hi = be64_to_cpu(addr64) >> 32; 24243a1a4661SBenjamin Herrenschmidt msg->address_lo = be64_to_cpu(addr64) & 0xfffffffful; 2425184cd4a3SBenjamin Herrenschmidt } else { 24263a1a4661SBenjamin Herrenschmidt __be32 addr32; 24273a1a4661SBenjamin Herrenschmidt 2428184cd4a3SBenjamin Herrenschmidt rc = opal_get_msi_32(phb->opal_id, pe->mve_number, xive_num, 1, 2429184cd4a3SBenjamin Herrenschmidt &addr32, &data); 2430184cd4a3SBenjamin Herrenschmidt if (rc) { 2431184cd4a3SBenjamin Herrenschmidt pr_warn("%s: OPAL error %d getting 32-bit MSI data\n", 2432184cd4a3SBenjamin Herrenschmidt pci_name(dev), rc); 2433184cd4a3SBenjamin Herrenschmidt return -EIO; 2434184cd4a3SBenjamin Herrenschmidt } 2435184cd4a3SBenjamin Herrenschmidt msg->address_hi = 0; 24363a1a4661SBenjamin Herrenschmidt msg->address_lo = be32_to_cpu(addr32); 2437184cd4a3SBenjamin Herrenschmidt } 24383a1a4661SBenjamin Herrenschmidt msg->data = be32_to_cpu(data); 2439184cd4a3SBenjamin Herrenschmidt 2440fd9a1c26SIan Munsie set_msi_irq_chip(phb, virq); 2441137436c9SGavin Shan 2442184cd4a3SBenjamin Herrenschmidt pr_devel("%s: %s-bit MSI on hwirq %x (xive #%d)," 2443184cd4a3SBenjamin Herrenschmidt " address=%x_%08x data=%x PE# %d\n", 2444184cd4a3SBenjamin Herrenschmidt pci_name(dev), is_64 ? "64" : "32", hwirq, xive_num, 2445184cd4a3SBenjamin Herrenschmidt msg->address_hi, msg->address_lo, data, pe->pe_number); 2446184cd4a3SBenjamin Herrenschmidt 2447184cd4a3SBenjamin Herrenschmidt return 0; 2448184cd4a3SBenjamin Herrenschmidt } 2449184cd4a3SBenjamin Herrenschmidt 2450184cd4a3SBenjamin Herrenschmidt static void pnv_pci_init_ioda_msis(struct pnv_phb *phb) 2451184cd4a3SBenjamin Herrenschmidt { 2452fb1b55d6SGavin Shan unsigned int count; 2453184cd4a3SBenjamin Herrenschmidt const __be32 *prop = of_get_property(phb->hose->dn, 2454184cd4a3SBenjamin Herrenschmidt "ibm,opal-msi-ranges", NULL); 2455184cd4a3SBenjamin Herrenschmidt if (!prop) { 2456184cd4a3SBenjamin Herrenschmidt /* BML Fallback */ 2457184cd4a3SBenjamin Herrenschmidt prop = of_get_property(phb->hose->dn, "msi-ranges", NULL); 2458184cd4a3SBenjamin Herrenschmidt } 2459184cd4a3SBenjamin Herrenschmidt if (!prop) 2460184cd4a3SBenjamin Herrenschmidt return; 2461184cd4a3SBenjamin Herrenschmidt 2462184cd4a3SBenjamin Herrenschmidt phb->msi_base = be32_to_cpup(prop); 2463fb1b55d6SGavin Shan count = be32_to_cpup(prop + 1); 2464fb1b55d6SGavin Shan if (msi_bitmap_alloc(&phb->msi_bmp, count, phb->hose->dn)) { 2465184cd4a3SBenjamin Herrenschmidt pr_err("PCI %d: Failed to allocate MSI bitmap !\n", 2466184cd4a3SBenjamin Herrenschmidt phb->hose->global_number); 2467184cd4a3SBenjamin Herrenschmidt return; 2468184cd4a3SBenjamin Herrenschmidt } 2469fb1b55d6SGavin Shan 2470184cd4a3SBenjamin Herrenschmidt phb->msi_setup = pnv_pci_ioda_msi_setup; 2471184cd4a3SBenjamin Herrenschmidt phb->msi32_support = 1; 2472184cd4a3SBenjamin Herrenschmidt pr_info(" Allocated bitmap for %d MSIs (base IRQ 0x%x)\n", 2473fb1b55d6SGavin Shan count, phb->msi_base); 2474184cd4a3SBenjamin Herrenschmidt } 2475184cd4a3SBenjamin Herrenschmidt #else 2476184cd4a3SBenjamin Herrenschmidt static void pnv_pci_init_ioda_msis(struct pnv_phb *phb) { } 2477184cd4a3SBenjamin Herrenschmidt #endif /* CONFIG_PCI_MSI */ 2478184cd4a3SBenjamin Herrenschmidt 24796e628c7dSWei Yang #ifdef CONFIG_PCI_IOV 24806e628c7dSWei Yang static void pnv_pci_ioda_fixup_iov_resources(struct pci_dev *pdev) 24816e628c7dSWei Yang { 24826e628c7dSWei Yang struct pci_controller *hose; 24836e628c7dSWei Yang struct pnv_phb *phb; 24846e628c7dSWei Yang struct resource *res; 24856e628c7dSWei Yang int i; 24866e628c7dSWei Yang resource_size_t size; 24876e628c7dSWei Yang struct pci_dn *pdn; 24885b88ec22SWei Yang int mul, total_vfs; 24896e628c7dSWei Yang 24906e628c7dSWei Yang if (!pdev->is_physfn || pdev->is_added) 24916e628c7dSWei Yang return; 24926e628c7dSWei Yang 24936e628c7dSWei Yang hose = pci_bus_to_host(pdev->bus); 24946e628c7dSWei Yang phb = hose->private_data; 24956e628c7dSWei Yang 24966e628c7dSWei Yang pdn = pci_get_pdn(pdev); 24976e628c7dSWei Yang pdn->vfs_expanded = 0; 24986e628c7dSWei Yang 24995b88ec22SWei Yang total_vfs = pci_sriov_get_totalvfs(pdev); 25005b88ec22SWei Yang pdn->m64_per_iov = 1; 25015b88ec22SWei Yang mul = phb->ioda.total_pe; 25025b88ec22SWei Yang 25035b88ec22SWei Yang for (i = 0; i < PCI_SRIOV_NUM_BARS; i++) { 25045b88ec22SWei Yang res = &pdev->resource[i + PCI_IOV_RESOURCES]; 25055b88ec22SWei Yang if (!res->flags || res->parent) 25065b88ec22SWei Yang continue; 25075b88ec22SWei Yang if (!pnv_pci_is_mem_pref_64(res->flags)) { 25085b88ec22SWei Yang dev_warn(&pdev->dev, " non M64 VF BAR%d: %pR\n", 25095b88ec22SWei Yang i, res); 25105b88ec22SWei Yang continue; 25115b88ec22SWei Yang } 25125b88ec22SWei Yang 25135b88ec22SWei Yang size = pci_iov_resource_size(pdev, i + PCI_IOV_RESOURCES); 25145b88ec22SWei Yang 25155b88ec22SWei Yang /* bigger than 64M */ 25165b88ec22SWei Yang if (size > (1 << 26)) { 25175b88ec22SWei Yang dev_info(&pdev->dev, "PowerNV: VF BAR%d: %pR IOV size is bigger than 64M, roundup power2\n", 25185b88ec22SWei Yang i, res); 25195b88ec22SWei Yang pdn->m64_per_iov = M64_PER_IOV; 25205b88ec22SWei Yang mul = roundup_pow_of_two(total_vfs); 25215b88ec22SWei Yang break; 25225b88ec22SWei Yang } 25235b88ec22SWei Yang } 25245b88ec22SWei Yang 25256e628c7dSWei Yang for (i = 0; i < PCI_SRIOV_NUM_BARS; i++) { 25266e628c7dSWei Yang res = &pdev->resource[i + PCI_IOV_RESOURCES]; 25276e628c7dSWei Yang if (!res->flags || res->parent) 25286e628c7dSWei Yang continue; 25296e628c7dSWei Yang if (!pnv_pci_is_mem_pref_64(res->flags)) { 25306e628c7dSWei Yang dev_warn(&pdev->dev, "Skipping expanding VF BAR%d: %pR\n", 25316e628c7dSWei Yang i, res); 25326e628c7dSWei Yang continue; 25336e628c7dSWei Yang } 25346e628c7dSWei Yang 25356e628c7dSWei Yang dev_dbg(&pdev->dev, " Fixing VF BAR%d: %pR to\n", i, res); 25366e628c7dSWei Yang size = pci_iov_resource_size(pdev, i + PCI_IOV_RESOURCES); 25375b88ec22SWei Yang res->end = res->start + size * mul - 1; 25386e628c7dSWei Yang dev_dbg(&pdev->dev, " %pR\n", res); 25396e628c7dSWei Yang dev_info(&pdev->dev, "VF BAR%d: %pR (expanded to %d VFs for PE alignment)", 25405b88ec22SWei Yang i, res, mul); 25416e628c7dSWei Yang } 25425b88ec22SWei Yang pdn->vfs_expanded = mul; 25436e628c7dSWei Yang } 25446e628c7dSWei Yang #endif /* CONFIG_PCI_IOV */ 25456e628c7dSWei Yang 254611685becSGavin Shan /* 254711685becSGavin Shan * This function is supposed to be called on basis of PE from top 254811685becSGavin Shan * to bottom style. So the the I/O or MMIO segment assigned to 254911685becSGavin Shan * parent PE could be overrided by its child PEs if necessary. 255011685becSGavin Shan */ 2551cad5cef6SGreg Kroah-Hartman static void pnv_ioda_setup_pe_seg(struct pci_controller *hose, 255211685becSGavin Shan struct pnv_ioda_pe *pe) 255311685becSGavin Shan { 255411685becSGavin Shan struct pnv_phb *phb = hose->private_data; 255511685becSGavin Shan struct pci_bus_region region; 255611685becSGavin Shan struct resource *res; 255711685becSGavin Shan int i, index; 255811685becSGavin Shan int rc; 255911685becSGavin Shan 256011685becSGavin Shan /* 256111685becSGavin Shan * NOTE: We only care PCI bus based PE for now. For PCI 256211685becSGavin Shan * device based PE, for example SRIOV sensitive VF should 256311685becSGavin Shan * be figured out later. 256411685becSGavin Shan */ 256511685becSGavin Shan BUG_ON(!(pe->flags & (PNV_IODA_PE_BUS | PNV_IODA_PE_BUS_ALL))); 256611685becSGavin Shan 256711685becSGavin Shan pci_bus_for_each_resource(pe->pbus, res, i) { 256811685becSGavin Shan if (!res || !res->flags || 256911685becSGavin Shan res->start > res->end) 257011685becSGavin Shan continue; 257111685becSGavin Shan 257211685becSGavin Shan if (res->flags & IORESOURCE_IO) { 257311685becSGavin Shan region.start = res->start - phb->ioda.io_pci_base; 257411685becSGavin Shan region.end = res->end - phb->ioda.io_pci_base; 257511685becSGavin Shan index = region.start / phb->ioda.io_segsize; 257611685becSGavin Shan 257711685becSGavin Shan while (index < phb->ioda.total_pe && 257811685becSGavin Shan region.start <= region.end) { 257911685becSGavin Shan phb->ioda.io_segmap[index] = pe->pe_number; 258011685becSGavin Shan rc = opal_pci_map_pe_mmio_window(phb->opal_id, 258111685becSGavin Shan pe->pe_number, OPAL_IO_WINDOW_TYPE, 0, index); 258211685becSGavin Shan if (rc != OPAL_SUCCESS) { 258311685becSGavin Shan pr_err("%s: OPAL error %d when mapping IO " 258411685becSGavin Shan "segment #%d to PE#%d\n", 258511685becSGavin Shan __func__, rc, index, pe->pe_number); 258611685becSGavin Shan break; 258711685becSGavin Shan } 258811685becSGavin Shan 258911685becSGavin Shan region.start += phb->ioda.io_segsize; 259011685becSGavin Shan index++; 259111685becSGavin Shan } 2592027fa02fSGavin Shan } else if ((res->flags & IORESOURCE_MEM) && 2593027fa02fSGavin Shan !pnv_pci_is_mem_pref_64(res->flags)) { 259411685becSGavin Shan region.start = res->start - 25953fd47f06SBenjamin Herrenschmidt hose->mem_offset[0] - 259611685becSGavin Shan phb->ioda.m32_pci_base; 259711685becSGavin Shan region.end = res->end - 25983fd47f06SBenjamin Herrenschmidt hose->mem_offset[0] - 259911685becSGavin Shan phb->ioda.m32_pci_base; 260011685becSGavin Shan index = region.start / phb->ioda.m32_segsize; 260111685becSGavin Shan 260211685becSGavin Shan while (index < phb->ioda.total_pe && 260311685becSGavin Shan region.start <= region.end) { 260411685becSGavin Shan phb->ioda.m32_segmap[index] = pe->pe_number; 260511685becSGavin Shan rc = opal_pci_map_pe_mmio_window(phb->opal_id, 260611685becSGavin Shan pe->pe_number, OPAL_M32_WINDOW_TYPE, 0, index); 260711685becSGavin Shan if (rc != OPAL_SUCCESS) { 260811685becSGavin Shan pr_err("%s: OPAL error %d when mapping M32 " 260911685becSGavin Shan "segment#%d to PE#%d", 261011685becSGavin Shan __func__, rc, index, pe->pe_number); 261111685becSGavin Shan break; 261211685becSGavin Shan } 261311685becSGavin Shan 261411685becSGavin Shan region.start += phb->ioda.m32_segsize; 261511685becSGavin Shan index++; 261611685becSGavin Shan } 261711685becSGavin Shan } 261811685becSGavin Shan } 261911685becSGavin Shan } 262011685becSGavin Shan 2621cad5cef6SGreg Kroah-Hartman static void pnv_pci_ioda_setup_seg(void) 262211685becSGavin Shan { 262311685becSGavin Shan struct pci_controller *tmp, *hose; 262411685becSGavin Shan struct pnv_phb *phb; 262511685becSGavin Shan struct pnv_ioda_pe *pe; 262611685becSGavin Shan 262711685becSGavin Shan list_for_each_entry_safe(hose, tmp, &hose_list, list_node) { 262811685becSGavin Shan phb = hose->private_data; 262911685becSGavin Shan list_for_each_entry(pe, &phb->ioda.pe_list, list) { 263011685becSGavin Shan pnv_ioda_setup_pe_seg(hose, pe); 263111685becSGavin Shan } 263211685becSGavin Shan } 263311685becSGavin Shan } 263411685becSGavin Shan 2635cad5cef6SGreg Kroah-Hartman static void pnv_pci_ioda_setup_DMA(void) 263613395c48SGavin Shan { 263713395c48SGavin Shan struct pci_controller *hose, *tmp; 2638db1266c8SGavin Shan struct pnv_phb *phb; 263913395c48SGavin Shan 264013395c48SGavin Shan list_for_each_entry_safe(hose, tmp, &hose_list, list_node) { 264113395c48SGavin Shan pnv_ioda_setup_dma(hose->private_data); 2642db1266c8SGavin Shan 2643db1266c8SGavin Shan /* Mark the PHB initialization done */ 2644db1266c8SGavin Shan phb = hose->private_data; 2645db1266c8SGavin Shan phb->initialized = 1; 264613395c48SGavin Shan } 264713395c48SGavin Shan } 264813395c48SGavin Shan 264937c367f2SGavin Shan static void pnv_pci_ioda_create_dbgfs(void) 265037c367f2SGavin Shan { 265137c367f2SGavin Shan #ifdef CONFIG_DEBUG_FS 265237c367f2SGavin Shan struct pci_controller *hose, *tmp; 265337c367f2SGavin Shan struct pnv_phb *phb; 265437c367f2SGavin Shan char name[16]; 265537c367f2SGavin Shan 265637c367f2SGavin Shan list_for_each_entry_safe(hose, tmp, &hose_list, list_node) { 265737c367f2SGavin Shan phb = hose->private_data; 265837c367f2SGavin Shan 265937c367f2SGavin Shan sprintf(name, "PCI%04x", hose->global_number); 266037c367f2SGavin Shan phb->dbgfs = debugfs_create_dir(name, powerpc_debugfs_root); 266137c367f2SGavin Shan if (!phb->dbgfs) 266237c367f2SGavin Shan pr_warning("%s: Error on creating debugfs on PHB#%x\n", 266337c367f2SGavin Shan __func__, hose->global_number); 266437c367f2SGavin Shan } 266537c367f2SGavin Shan #endif /* CONFIG_DEBUG_FS */ 266637c367f2SGavin Shan } 266737c367f2SGavin Shan 2668cad5cef6SGreg Kroah-Hartman static void pnv_pci_ioda_fixup(void) 2669fb446ad0SGavin Shan { 2670fb446ad0SGavin Shan pnv_pci_ioda_setup_PEs(); 267111685becSGavin Shan pnv_pci_ioda_setup_seg(); 267213395c48SGavin Shan pnv_pci_ioda_setup_DMA(); 2673e9cc17d4SGavin Shan 267437c367f2SGavin Shan pnv_pci_ioda_create_dbgfs(); 267537c367f2SGavin Shan 2676e9cc17d4SGavin Shan #ifdef CONFIG_EEH 2677e9cc17d4SGavin Shan eeh_init(); 2678dadcd6d6SMike Qiu eeh_addr_cache_build(); 2679e9cc17d4SGavin Shan #endif 2680fb446ad0SGavin Shan } 2681fb446ad0SGavin Shan 2682271fd03aSGavin Shan /* 2683271fd03aSGavin Shan * Returns the alignment for I/O or memory windows for P2P 2684271fd03aSGavin Shan * bridges. That actually depends on how PEs are segmented. 2685271fd03aSGavin Shan * For now, we return I/O or M32 segment size for PE sensitive 2686271fd03aSGavin Shan * P2P bridges. Otherwise, the default values (4KiB for I/O, 2687271fd03aSGavin Shan * 1MiB for memory) will be returned. 2688271fd03aSGavin Shan * 2689271fd03aSGavin Shan * The current PCI bus might be put into one PE, which was 2690271fd03aSGavin Shan * create against the parent PCI bridge. For that case, we 2691271fd03aSGavin Shan * needn't enlarge the alignment so that we can save some 2692271fd03aSGavin Shan * resources. 2693271fd03aSGavin Shan */ 2694271fd03aSGavin Shan static resource_size_t pnv_pci_window_alignment(struct pci_bus *bus, 2695271fd03aSGavin Shan unsigned long type) 2696271fd03aSGavin Shan { 2697271fd03aSGavin Shan struct pci_dev *bridge; 2698271fd03aSGavin Shan struct pci_controller *hose = pci_bus_to_host(bus); 2699271fd03aSGavin Shan struct pnv_phb *phb = hose->private_data; 2700271fd03aSGavin Shan int num_pci_bridges = 0; 2701271fd03aSGavin Shan 2702271fd03aSGavin Shan bridge = bus->self; 2703271fd03aSGavin Shan while (bridge) { 2704271fd03aSGavin Shan if (pci_pcie_type(bridge) == PCI_EXP_TYPE_PCI_BRIDGE) { 2705271fd03aSGavin Shan num_pci_bridges++; 2706271fd03aSGavin Shan if (num_pci_bridges >= 2) 2707271fd03aSGavin Shan return 1; 2708271fd03aSGavin Shan } 2709271fd03aSGavin Shan 2710271fd03aSGavin Shan bridge = bridge->bus->self; 2711271fd03aSGavin Shan } 2712271fd03aSGavin Shan 2713262af557SGuo Chao /* We fail back to M32 if M64 isn't supported */ 2714262af557SGuo Chao if (phb->ioda.m64_segsize && 2715262af557SGuo Chao pnv_pci_is_mem_pref_64(type)) 2716262af557SGuo Chao return phb->ioda.m64_segsize; 2717271fd03aSGavin Shan if (type & IORESOURCE_MEM) 2718271fd03aSGavin Shan return phb->ioda.m32_segsize; 2719271fd03aSGavin Shan 2720271fd03aSGavin Shan return phb->ioda.io_segsize; 2721271fd03aSGavin Shan } 2722271fd03aSGavin Shan 27235350ab3fSWei Yang #ifdef CONFIG_PCI_IOV 27245350ab3fSWei Yang static resource_size_t pnv_pci_iov_resource_alignment(struct pci_dev *pdev, 27255350ab3fSWei Yang int resno) 27265350ab3fSWei Yang { 27275350ab3fSWei Yang struct pci_dn *pdn = pci_get_pdn(pdev); 27285350ab3fSWei Yang resource_size_t align, iov_align; 27295350ab3fSWei Yang 27305350ab3fSWei Yang iov_align = resource_size(&pdev->resource[resno]); 27315350ab3fSWei Yang if (iov_align) 27325350ab3fSWei Yang return iov_align; 27335350ab3fSWei Yang 27345350ab3fSWei Yang align = pci_iov_resource_size(pdev, resno); 27355350ab3fSWei Yang if (pdn->vfs_expanded) 27365350ab3fSWei Yang return pdn->vfs_expanded * align; 27375350ab3fSWei Yang 27385350ab3fSWei Yang return align; 27395350ab3fSWei Yang } 27405350ab3fSWei Yang #endif /* CONFIG_PCI_IOV */ 27415350ab3fSWei Yang 2742184cd4a3SBenjamin Herrenschmidt /* Prevent enabling devices for which we couldn't properly 2743184cd4a3SBenjamin Herrenschmidt * assign a PE 2744184cd4a3SBenjamin Herrenschmidt */ 2745c88c2a18SDaniel Axtens static bool pnv_pci_enable_device_hook(struct pci_dev *dev) 2746184cd4a3SBenjamin Herrenschmidt { 2747db1266c8SGavin Shan struct pci_controller *hose = pci_bus_to_host(dev->bus); 2748db1266c8SGavin Shan struct pnv_phb *phb = hose->private_data; 2749db1266c8SGavin Shan struct pci_dn *pdn; 2750184cd4a3SBenjamin Herrenschmidt 2751db1266c8SGavin Shan /* The function is probably called while the PEs have 2752db1266c8SGavin Shan * not be created yet. For example, resource reassignment 2753db1266c8SGavin Shan * during PCI probe period. We just skip the check if 2754db1266c8SGavin Shan * PEs isn't ready. 2755db1266c8SGavin Shan */ 2756db1266c8SGavin Shan if (!phb->initialized) 2757c88c2a18SDaniel Axtens return true; 2758db1266c8SGavin Shan 2759b72c1f65SBenjamin Herrenschmidt pdn = pci_get_pdn(dev); 2760184cd4a3SBenjamin Herrenschmidt if (!pdn || pdn->pe_number == IODA_INVALID_PE) 2761c88c2a18SDaniel Axtens return false; 2762db1266c8SGavin Shan 2763c88c2a18SDaniel Axtens return true; 2764184cd4a3SBenjamin Herrenschmidt } 2765184cd4a3SBenjamin Herrenschmidt 2766184cd4a3SBenjamin Herrenschmidt static u32 pnv_ioda_bdfn_to_pe(struct pnv_phb *phb, struct pci_bus *bus, 2767184cd4a3SBenjamin Herrenschmidt u32 devfn) 2768184cd4a3SBenjamin Herrenschmidt { 2769184cd4a3SBenjamin Herrenschmidt return phb->ioda.pe_rmap[(bus->number << 8) | devfn]; 2770184cd4a3SBenjamin Herrenschmidt } 2771184cd4a3SBenjamin Herrenschmidt 27727a8e6bbfSMichael Neuling static void pnv_pci_ioda_shutdown(struct pci_controller *hose) 277373ed148aSBenjamin Herrenschmidt { 27747a8e6bbfSMichael Neuling struct pnv_phb *phb = hose->private_data; 27757a8e6bbfSMichael Neuling 2776d1a85eeeSGavin Shan opal_pci_reset(phb->opal_id, OPAL_RESET_PCI_IODA_TABLE, 277773ed148aSBenjamin Herrenschmidt OPAL_ASSERT_RESET); 277873ed148aSBenjamin Herrenschmidt } 277973ed148aSBenjamin Herrenschmidt 278092ae0353SDaniel Axtens static const struct pci_controller_ops pnv_pci_ioda_controller_ops = { 278192ae0353SDaniel Axtens .dma_dev_setup = pnv_pci_dma_dev_setup, 278292ae0353SDaniel Axtens #ifdef CONFIG_PCI_MSI 278392ae0353SDaniel Axtens .setup_msi_irqs = pnv_setup_msi_irqs, 278492ae0353SDaniel Axtens .teardown_msi_irqs = pnv_teardown_msi_irqs, 278592ae0353SDaniel Axtens #endif 278692ae0353SDaniel Axtens .enable_device_hook = pnv_pci_enable_device_hook, 278792ae0353SDaniel Axtens .window_alignment = pnv_pci_window_alignment, 278892ae0353SDaniel Axtens .reset_secondary_bus = pnv_pci_reset_secondary_bus, 2789763d2d8dSDaniel Axtens .dma_set_mask = pnv_pci_ioda_dma_set_mask, 27907a8e6bbfSMichael Neuling .shutdown = pnv_pci_ioda_shutdown, 279192ae0353SDaniel Axtens }; 279292ae0353SDaniel Axtens 2793e51df2c1SAnton Blanchard static void __init pnv_pci_init_ioda_phb(struct device_node *np, 2794e9cc17d4SGavin Shan u64 hub_id, int ioda_type) 2795184cd4a3SBenjamin Herrenschmidt { 2796184cd4a3SBenjamin Herrenschmidt struct pci_controller *hose; 2797184cd4a3SBenjamin Herrenschmidt struct pnv_phb *phb; 27988184616fSGavin Shan unsigned long size, m32map_off, pemap_off, iomap_off = 0; 2799c681b93cSAlistair Popple const __be64 *prop64; 28003a1a4661SBenjamin Herrenschmidt const __be32 *prop32; 2801f1b7cc3eSGavin Shan int len; 2802184cd4a3SBenjamin Herrenschmidt u64 phb_id; 2803184cd4a3SBenjamin Herrenschmidt void *aux; 2804184cd4a3SBenjamin Herrenschmidt long rc; 2805184cd4a3SBenjamin Herrenschmidt 2806aa0c033fSGavin Shan pr_info("Initializing IODA%d OPAL PHB %s\n", ioda_type, np->full_name); 2807184cd4a3SBenjamin Herrenschmidt 2808184cd4a3SBenjamin Herrenschmidt prop64 = of_get_property(np, "ibm,opal-phbid", NULL); 2809184cd4a3SBenjamin Herrenschmidt if (!prop64) { 2810184cd4a3SBenjamin Herrenschmidt pr_err(" Missing \"ibm,opal-phbid\" property !\n"); 2811184cd4a3SBenjamin Herrenschmidt return; 2812184cd4a3SBenjamin Herrenschmidt } 2813184cd4a3SBenjamin Herrenschmidt phb_id = be64_to_cpup(prop64); 2814184cd4a3SBenjamin Herrenschmidt pr_debug(" PHB-ID : 0x%016llx\n", phb_id); 2815184cd4a3SBenjamin Herrenschmidt 2816e39f223fSMichael Ellerman phb = memblock_virt_alloc(sizeof(struct pnv_phb), 0); 281758d714ecSGavin Shan 281858d714ecSGavin Shan /* Allocate PCI controller */ 2819184cd4a3SBenjamin Herrenschmidt phb->hose = hose = pcibios_alloc_controller(np); 282058d714ecSGavin Shan if (!phb->hose) { 282158d714ecSGavin Shan pr_err(" Can't allocate PCI controller for %s\n", 2822184cd4a3SBenjamin Herrenschmidt np->full_name); 2823e39f223fSMichael Ellerman memblock_free(__pa(phb), sizeof(struct pnv_phb)); 2824184cd4a3SBenjamin Herrenschmidt return; 2825184cd4a3SBenjamin Herrenschmidt } 2826184cd4a3SBenjamin Herrenschmidt 2827184cd4a3SBenjamin Herrenschmidt spin_lock_init(&phb->lock); 2828f1b7cc3eSGavin Shan prop32 = of_get_property(np, "bus-range", &len); 2829f1b7cc3eSGavin Shan if (prop32 && len == 8) { 28303a1a4661SBenjamin Herrenschmidt hose->first_busno = be32_to_cpu(prop32[0]); 28313a1a4661SBenjamin Herrenschmidt hose->last_busno = be32_to_cpu(prop32[1]); 2832f1b7cc3eSGavin Shan } else { 2833f1b7cc3eSGavin Shan pr_warn(" Broken <bus-range> on %s\n", np->full_name); 2834184cd4a3SBenjamin Herrenschmidt hose->first_busno = 0; 2835184cd4a3SBenjamin Herrenschmidt hose->last_busno = 0xff; 2836f1b7cc3eSGavin Shan } 2837184cd4a3SBenjamin Herrenschmidt hose->private_data = phb; 2838e9cc17d4SGavin Shan phb->hub_id = hub_id; 2839184cd4a3SBenjamin Herrenschmidt phb->opal_id = phb_id; 2840aa0c033fSGavin Shan phb->type = ioda_type; 2841781a868fSWei Yang mutex_init(&phb->ioda.pe_alloc_mutex); 2842184cd4a3SBenjamin Herrenschmidt 2843cee72d5bSBenjamin Herrenschmidt /* Detect specific models for error handling */ 2844cee72d5bSBenjamin Herrenschmidt if (of_device_is_compatible(np, "ibm,p7ioc-pciex")) 2845cee72d5bSBenjamin Herrenschmidt phb->model = PNV_PHB_MODEL_P7IOC; 2846f3d40c25SBenjamin Herrenschmidt else if (of_device_is_compatible(np, "ibm,power8-pciex")) 2847aa0c033fSGavin Shan phb->model = PNV_PHB_MODEL_PHB3; 2848cee72d5bSBenjamin Herrenschmidt else 2849cee72d5bSBenjamin Herrenschmidt phb->model = PNV_PHB_MODEL_UNKNOWN; 2850cee72d5bSBenjamin Herrenschmidt 2851aa0c033fSGavin Shan /* Parse 32-bit and IO ranges (if any) */ 28522f1ec02eSGavin Shan pci_process_bridge_OF_ranges(hose, np, !hose->global_number); 2853184cd4a3SBenjamin Herrenschmidt 2854aa0c033fSGavin Shan /* Get registers */ 2855184cd4a3SBenjamin Herrenschmidt phb->regs = of_iomap(np, 0); 2856184cd4a3SBenjamin Herrenschmidt if (phb->regs == NULL) 2857184cd4a3SBenjamin Herrenschmidt pr_err(" Failed to map registers !\n"); 2858184cd4a3SBenjamin Herrenschmidt 2859184cd4a3SBenjamin Herrenschmidt /* Initialize more IODA stuff */ 2860aa0c033fSGavin Shan phb->ioda.total_pe = 1; 286136954dc7SGavin Shan prop32 = of_get_property(np, "ibm,opal-num-pes", NULL); 286236954dc7SGavin Shan if (prop32) 28633a1a4661SBenjamin Herrenschmidt phb->ioda.total_pe = be32_to_cpup(prop32); 286436954dc7SGavin Shan prop32 = of_get_property(np, "ibm,opal-reserved-pe", NULL); 286536954dc7SGavin Shan if (prop32) 286636954dc7SGavin Shan phb->ioda.reserved_pe = be32_to_cpup(prop32); 2867262af557SGuo Chao 2868262af557SGuo Chao /* Parse 64-bit MMIO range */ 2869262af557SGuo Chao pnv_ioda_parse_m64_window(phb); 2870262af557SGuo Chao 2871184cd4a3SBenjamin Herrenschmidt phb->ioda.m32_size = resource_size(&hose->mem_resources[0]); 2872aa0c033fSGavin Shan /* FW Has already off top 64k of M32 space (MSI space) */ 2873184cd4a3SBenjamin Herrenschmidt phb->ioda.m32_size += 0x10000; 2874184cd4a3SBenjamin Herrenschmidt 2875184cd4a3SBenjamin Herrenschmidt phb->ioda.m32_segsize = phb->ioda.m32_size / phb->ioda.total_pe; 28763fd47f06SBenjamin Herrenschmidt phb->ioda.m32_pci_base = hose->mem_resources[0].start - hose->mem_offset[0]; 2877184cd4a3SBenjamin Herrenschmidt phb->ioda.io_size = hose->pci_io_size; 2878184cd4a3SBenjamin Herrenschmidt phb->ioda.io_segsize = phb->ioda.io_size / phb->ioda.total_pe; 2879184cd4a3SBenjamin Herrenschmidt phb->ioda.io_pci_base = 0; /* XXX calculate this ? */ 2880184cd4a3SBenjamin Herrenschmidt 2881c35d2a8cSGavin Shan /* Allocate aux data & arrays. We don't have IO ports on PHB3 */ 2882184cd4a3SBenjamin Herrenschmidt size = _ALIGN_UP(phb->ioda.total_pe / 8, sizeof(unsigned long)); 2883184cd4a3SBenjamin Herrenschmidt m32map_off = size; 2884e47747f4SGavin Shan size += phb->ioda.total_pe * sizeof(phb->ioda.m32_segmap[0]); 2885c35d2a8cSGavin Shan if (phb->type == PNV_PHB_IODA1) { 2886c35d2a8cSGavin Shan iomap_off = size; 2887e47747f4SGavin Shan size += phb->ioda.total_pe * sizeof(phb->ioda.io_segmap[0]); 2888c35d2a8cSGavin Shan } 2889184cd4a3SBenjamin Herrenschmidt pemap_off = size; 2890184cd4a3SBenjamin Herrenschmidt size += phb->ioda.total_pe * sizeof(struct pnv_ioda_pe); 2891e39f223fSMichael Ellerman aux = memblock_virt_alloc(size, 0); 2892184cd4a3SBenjamin Herrenschmidt phb->ioda.pe_alloc = aux; 2893184cd4a3SBenjamin Herrenschmidt phb->ioda.m32_segmap = aux + m32map_off; 2894c35d2a8cSGavin Shan if (phb->type == PNV_PHB_IODA1) 2895184cd4a3SBenjamin Herrenschmidt phb->ioda.io_segmap = aux + iomap_off; 2896184cd4a3SBenjamin Herrenschmidt phb->ioda.pe_array = aux + pemap_off; 289736954dc7SGavin Shan set_bit(phb->ioda.reserved_pe, phb->ioda.pe_alloc); 2898184cd4a3SBenjamin Herrenschmidt 28997ebdf956SGavin Shan INIT_LIST_HEAD(&phb->ioda.pe_dma_list); 2900184cd4a3SBenjamin Herrenschmidt INIT_LIST_HEAD(&phb->ioda.pe_list); 2901781a868fSWei Yang mutex_init(&phb->ioda.pe_list_mutex); 2902184cd4a3SBenjamin Herrenschmidt 2903184cd4a3SBenjamin Herrenschmidt /* Calculate how many 32-bit TCE segments we have */ 2904184cd4a3SBenjamin Herrenschmidt phb->ioda.tce32_count = phb->ioda.m32_pci_base >> 28; 2905184cd4a3SBenjamin Herrenschmidt 2906aa0c033fSGavin Shan #if 0 /* We should really do that ... */ 2907184cd4a3SBenjamin Herrenschmidt rc = opal_pci_set_phb_mem_window(opal->phb_id, 2908184cd4a3SBenjamin Herrenschmidt window_type, 2909184cd4a3SBenjamin Herrenschmidt window_num, 2910184cd4a3SBenjamin Herrenschmidt starting_real_address, 2911184cd4a3SBenjamin Herrenschmidt starting_pci_address, 2912184cd4a3SBenjamin Herrenschmidt segment_size); 2913184cd4a3SBenjamin Herrenschmidt #endif 2914184cd4a3SBenjamin Herrenschmidt 2915262af557SGuo Chao pr_info(" %03d (%03d) PE's M32: 0x%x [segment=0x%x]\n", 2916262af557SGuo Chao phb->ioda.total_pe, phb->ioda.reserved_pe, 2917262af557SGuo Chao phb->ioda.m32_size, phb->ioda.m32_segsize); 2918262af557SGuo Chao if (phb->ioda.m64_size) 2919262af557SGuo Chao pr_info(" M64: 0x%lx [segment=0x%lx]\n", 2920262af557SGuo Chao phb->ioda.m64_size, phb->ioda.m64_segsize); 2921262af557SGuo Chao if (phb->ioda.io_size) 2922262af557SGuo Chao pr_info(" IO: 0x%x [segment=0x%x]\n", 2923184cd4a3SBenjamin Herrenschmidt phb->ioda.io_size, phb->ioda.io_segsize); 2924184cd4a3SBenjamin Herrenschmidt 2925262af557SGuo Chao 2926184cd4a3SBenjamin Herrenschmidt phb->hose->ops = &pnv_pci_ops; 292749dec922SGavin Shan phb->get_pe_state = pnv_ioda_get_pe_state; 292849dec922SGavin Shan phb->freeze_pe = pnv_ioda_freeze_pe; 292949dec922SGavin Shan phb->unfreeze_pe = pnv_ioda_unfreeze_pe; 2930184cd4a3SBenjamin Herrenschmidt 2931184cd4a3SBenjamin Herrenschmidt /* Setup RID -> PE mapping function */ 2932184cd4a3SBenjamin Herrenschmidt phb->bdfn_to_pe = pnv_ioda_bdfn_to_pe; 2933184cd4a3SBenjamin Herrenschmidt 2934184cd4a3SBenjamin Herrenschmidt /* Setup TCEs */ 2935184cd4a3SBenjamin Herrenschmidt phb->dma_dev_setup = pnv_pci_ioda_dma_dev_setup; 2936fe7e85c6SGavin Shan phb->dma_get_required_mask = pnv_pci_ioda_dma_get_required_mask; 2937184cd4a3SBenjamin Herrenschmidt 2938184cd4a3SBenjamin Herrenschmidt /* Setup MSI support */ 2939184cd4a3SBenjamin Herrenschmidt pnv_pci_init_ioda_msis(phb); 2940184cd4a3SBenjamin Herrenschmidt 2941c40a4210SGavin Shan /* 2942c40a4210SGavin Shan * We pass the PCI probe flag PCI_REASSIGN_ALL_RSRC here 2943c40a4210SGavin Shan * to let the PCI core do resource assignment. It's supposed 2944c40a4210SGavin Shan * that the PCI core will do correct I/O and MMIO alignment 2945c40a4210SGavin Shan * for the P2P bridge bars so that each PCI bus (excluding 2946c40a4210SGavin Shan * the child P2P bridges) can form individual PE. 2947184cd4a3SBenjamin Herrenschmidt */ 2948fb446ad0SGavin Shan ppc_md.pcibios_fixup = pnv_pci_ioda_fixup; 294992ae0353SDaniel Axtens hose->controller_ops = pnv_pci_ioda_controller_ops; 2950ad30cb99SMichael Ellerman 29516e628c7dSWei Yang #ifdef CONFIG_PCI_IOV 29526e628c7dSWei Yang ppc_md.pcibios_fixup_sriov = pnv_pci_ioda_fixup_iov_resources; 29535350ab3fSWei Yang ppc_md.pcibios_iov_resource_alignment = pnv_pci_iov_resource_alignment; 2954ad30cb99SMichael Ellerman #endif 2955ad30cb99SMichael Ellerman 2956c40a4210SGavin Shan pci_add_flags(PCI_REASSIGN_ALL_RSRC); 2957184cd4a3SBenjamin Herrenschmidt 2958184cd4a3SBenjamin Herrenschmidt /* Reset IODA tables to a clean state */ 2959d1a85eeeSGavin Shan rc = opal_pci_reset(phb_id, OPAL_RESET_PCI_IODA_TABLE, OPAL_ASSERT_RESET); 2960184cd4a3SBenjamin Herrenschmidt if (rc) 2961f11fe552SBenjamin Herrenschmidt pr_warning(" OPAL Error %ld performing IODA table reset !\n", rc); 2962361f2a2aSGavin Shan 2963361f2a2aSGavin Shan /* If we're running in kdump kerenl, the previous kerenl never 2964361f2a2aSGavin Shan * shutdown PCI devices correctly. We already got IODA table 2965361f2a2aSGavin Shan * cleaned out. So we have to issue PHB reset to stop all PCI 2966361f2a2aSGavin Shan * transactions from previous kerenl. 2967361f2a2aSGavin Shan */ 2968361f2a2aSGavin Shan if (is_kdump_kernel()) { 2969361f2a2aSGavin Shan pr_info(" Issue PHB reset ...\n"); 2970cadf364dSGavin Shan pnv_eeh_phb_reset(hose, EEH_RESET_FUNDAMENTAL); 2971cadf364dSGavin Shan pnv_eeh_phb_reset(hose, EEH_RESET_DEACTIVATE); 2972361f2a2aSGavin Shan } 2973262af557SGuo Chao 29749e9e8935SGavin Shan /* Remove M64 resource if we can't configure it successfully */ 29759e9e8935SGavin Shan if (!phb->init_m64 || phb->init_m64(phb)) 2976262af557SGuo Chao hose->mem_resources[1].flags = 0; 2977184cd4a3SBenjamin Herrenschmidt } 2978184cd4a3SBenjamin Herrenschmidt 297967975005SBjorn Helgaas void __init pnv_pci_init_ioda2_phb(struct device_node *np) 2980aa0c033fSGavin Shan { 2981e9cc17d4SGavin Shan pnv_pci_init_ioda_phb(np, 0, PNV_PHB_IODA2); 2982aa0c033fSGavin Shan } 2983aa0c033fSGavin Shan 2984184cd4a3SBenjamin Herrenschmidt void __init pnv_pci_init_ioda_hub(struct device_node *np) 2985184cd4a3SBenjamin Herrenschmidt { 2986184cd4a3SBenjamin Herrenschmidt struct device_node *phbn; 2987c681b93cSAlistair Popple const __be64 *prop64; 2988184cd4a3SBenjamin Herrenschmidt u64 hub_id; 2989184cd4a3SBenjamin Herrenschmidt 2990184cd4a3SBenjamin Herrenschmidt pr_info("Probing IODA IO-Hub %s\n", np->full_name); 2991184cd4a3SBenjamin Herrenschmidt 2992184cd4a3SBenjamin Herrenschmidt prop64 = of_get_property(np, "ibm,opal-hubid", NULL); 2993184cd4a3SBenjamin Herrenschmidt if (!prop64) { 2994184cd4a3SBenjamin Herrenschmidt pr_err(" Missing \"ibm,opal-hubid\" property !\n"); 2995184cd4a3SBenjamin Herrenschmidt return; 2996184cd4a3SBenjamin Herrenschmidt } 2997184cd4a3SBenjamin Herrenschmidt hub_id = be64_to_cpup(prop64); 2998184cd4a3SBenjamin Herrenschmidt pr_devel(" HUB-ID : 0x%016llx\n", hub_id); 2999184cd4a3SBenjamin Herrenschmidt 3000184cd4a3SBenjamin Herrenschmidt /* Count child PHBs */ 3001184cd4a3SBenjamin Herrenschmidt for_each_child_of_node(np, phbn) { 3002184cd4a3SBenjamin Herrenschmidt /* Look for IODA1 PHBs */ 3003184cd4a3SBenjamin Herrenschmidt if (of_device_is_compatible(phbn, "ibm,ioda-phb")) 3004e9cc17d4SGavin Shan pnv_pci_init_ioda_phb(phbn, hub_id, PNV_PHB_IODA1); 3005184cd4a3SBenjamin Herrenschmidt } 3006184cd4a3SBenjamin Herrenschmidt } 3007