12874c5fdSThomas Gleixner // SPDX-License-Identifier: GPL-2.0-or-later 2184cd4a3SBenjamin Herrenschmidt /* 3184cd4a3SBenjamin Herrenschmidt * Support PCI/PCIe on PowerNV platforms 4184cd4a3SBenjamin Herrenschmidt * 5184cd4a3SBenjamin Herrenschmidt * Copyright 2011 Benjamin Herrenschmidt, IBM Corp. 6184cd4a3SBenjamin Herrenschmidt */ 7184cd4a3SBenjamin Herrenschmidt 8cee72d5bSBenjamin Herrenschmidt #undef DEBUG 9184cd4a3SBenjamin Herrenschmidt 10184cd4a3SBenjamin Herrenschmidt #include <linux/kernel.h> 11184cd4a3SBenjamin Herrenschmidt #include <linux/pci.h> 12361f2a2aSGavin Shan #include <linux/crash_dump.h> 13184cd4a3SBenjamin Herrenschmidt #include <linux/delay.h> 14184cd4a3SBenjamin Herrenschmidt #include <linux/string.h> 15184cd4a3SBenjamin Herrenschmidt #include <linux/init.h> 1657c8a661SMike Rapoport #include <linux/memblock.h> 17184cd4a3SBenjamin Herrenschmidt #include <linux/irq.h> 18184cd4a3SBenjamin Herrenschmidt #include <linux/io.h> 19184cd4a3SBenjamin Herrenschmidt #include <linux/msi.h> 20ac9a5889SAlexey Kardashevskiy #include <linux/iommu.h> 21e57080f1SAlexey Kardashevskiy #include <linux/rculist.h> 224793d65dSAlexey Kardashevskiy #include <linux/sizes.h> 23184cd4a3SBenjamin Herrenschmidt 24184cd4a3SBenjamin Herrenschmidt #include <asm/sections.h> 25184cd4a3SBenjamin Herrenschmidt #include <asm/io.h> 26184cd4a3SBenjamin Herrenschmidt #include <asm/prom.h> 27184cd4a3SBenjamin Herrenschmidt #include <asm/pci-bridge.h> 28184cd4a3SBenjamin Herrenschmidt #include <asm/machdep.h> 29fb1b55d6SGavin Shan #include <asm/msi_bitmap.h> 30184cd4a3SBenjamin Herrenschmidt #include <asm/ppc-pci.h> 31184cd4a3SBenjamin Herrenschmidt #include <asm/opal.h> 32184cd4a3SBenjamin Herrenschmidt #include <asm/iommu.h> 33184cd4a3SBenjamin Herrenschmidt #include <asm/tce.h> 34137436c9SGavin Shan #include <asm/xics.h> 357644d581SMichael Ellerman #include <asm/debugfs.h> 36262af557SGuo Chao #include <asm/firmware.h> 3780c49c7eSIan Munsie #include <asm/pnv-pci.h> 38aca6913fSAlexey Kardashevskiy #include <asm/mmzone.h> 3980c49c7eSIan Munsie 40ec249dd8SMichael Neuling #include <misc/cxl-base.h> 41184cd4a3SBenjamin Herrenschmidt 42184cd4a3SBenjamin Herrenschmidt #include "powernv.h" 43184cd4a3SBenjamin Herrenschmidt #include "pci.h" 4444bda4b7SHari Vyas #include "../../../../drivers/pci/pci.h" 45184cd4a3SBenjamin Herrenschmidt 4699451551SGavin Shan #define PNV_IODA1_M64_NUM 16 /* Number of M64 BARs */ 4799451551SGavin Shan #define PNV_IODA1_M64_SEGS 8 /* Segments per M64 BAR */ 48acce971cSGavin Shan #define PNV_IODA1_DMA32_SEGSIZE 0x10000000 49781a868fSWei Yang 507f2c39e9SFrederic Barrat static const char * const pnv_phb_names[] = { "IODA1", "IODA2", "NPU_NVLINK", 517f2c39e9SFrederic Barrat "NPU_OCAPI" }; 52aca6913fSAlexey Kardashevskiy 53c498a4f9SChristoph Hellwig static void pnv_pci_ioda2_set_bypass(struct pnv_ioda_pe *pe, bool enable); 54dc3d8f85SOliver O'Halloran static void pnv_pci_configure_bus(struct pci_bus *bus); 55c498a4f9SChristoph Hellwig 567d623e42SAlexey Kardashevskiy void pe_level_printk(const struct pnv_ioda_pe *pe, const char *level, 576d31c2faSJoe Perches const char *fmt, ...) 586d31c2faSJoe Perches { 596d31c2faSJoe Perches struct va_format vaf; 606d31c2faSJoe Perches va_list args; 616d31c2faSJoe Perches char pfix[32]; 62184cd4a3SBenjamin Herrenschmidt 636d31c2faSJoe Perches va_start(args, fmt); 646d31c2faSJoe Perches 656d31c2faSJoe Perches vaf.fmt = fmt; 666d31c2faSJoe Perches vaf.va = &args; 676d31c2faSJoe Perches 68781a868fSWei Yang if (pe->flags & PNV_IODA_PE_DEV) 696d31c2faSJoe Perches strlcpy(pfix, dev_name(&pe->pdev->dev), sizeof(pfix)); 70781a868fSWei Yang else if (pe->flags & (PNV_IODA_PE_BUS | PNV_IODA_PE_BUS_ALL)) 716d31c2faSJoe Perches sprintf(pfix, "%04x:%02x ", 726d31c2faSJoe Perches pci_domain_nr(pe->pbus), pe->pbus->number); 73781a868fSWei Yang #ifdef CONFIG_PCI_IOV 74781a868fSWei Yang else if (pe->flags & PNV_IODA_PE_VF) 75781a868fSWei Yang sprintf(pfix, "%04x:%02x:%2x.%d", 76781a868fSWei Yang pci_domain_nr(pe->parent_dev->bus), 77781a868fSWei Yang (pe->rid & 0xff00) >> 8, 78781a868fSWei Yang PCI_SLOT(pe->rid), PCI_FUNC(pe->rid)); 79781a868fSWei Yang #endif /* CONFIG_PCI_IOV*/ 806d31c2faSJoe Perches 811f52f176SRussell Currey printk("%spci %s: [PE# %.2x] %pV", 826d31c2faSJoe Perches level, pfix, pe->pe_number, &vaf); 836d31c2faSJoe Perches 846d31c2faSJoe Perches va_end(args); 856d31c2faSJoe Perches } 866d31c2faSJoe Perches 874e287840SThadeu Lima de Souza Cascardo static bool pnv_iommu_bypass_disabled __read_mostly; 8845baee14SGuilherme G. Piccoli static bool pci_reset_phbs __read_mostly; 894e287840SThadeu Lima de Souza Cascardo 904e287840SThadeu Lima de Souza Cascardo static int __init iommu_setup(char *str) 914e287840SThadeu Lima de Souza Cascardo { 924e287840SThadeu Lima de Souza Cascardo if (!str) 934e287840SThadeu Lima de Souza Cascardo return -EINVAL; 944e287840SThadeu Lima de Souza Cascardo 954e287840SThadeu Lima de Souza Cascardo while (*str) { 964e287840SThadeu Lima de Souza Cascardo if (!strncmp(str, "nobypass", 8)) { 974e287840SThadeu Lima de Souza Cascardo pnv_iommu_bypass_disabled = true; 984e287840SThadeu Lima de Souza Cascardo pr_info("PowerNV: IOMMU bypass window disabled.\n"); 994e287840SThadeu Lima de Souza Cascardo break; 1004e287840SThadeu Lima de Souza Cascardo } 1014e287840SThadeu Lima de Souza Cascardo str += strcspn(str, ","); 1024e287840SThadeu Lima de Souza Cascardo if (*str == ',') 1034e287840SThadeu Lima de Souza Cascardo str++; 1044e287840SThadeu Lima de Souza Cascardo } 1054e287840SThadeu Lima de Souza Cascardo 1064e287840SThadeu Lima de Souza Cascardo return 0; 1074e287840SThadeu Lima de Souza Cascardo } 1084e287840SThadeu Lima de Souza Cascardo early_param("iommu", iommu_setup); 1094e287840SThadeu Lima de Souza Cascardo 11045baee14SGuilherme G. Piccoli static int __init pci_reset_phbs_setup(char *str) 11145baee14SGuilherme G. Piccoli { 11245baee14SGuilherme G. Piccoli pci_reset_phbs = true; 11345baee14SGuilherme G. Piccoli return 0; 11445baee14SGuilherme G. Piccoli } 11545baee14SGuilherme G. Piccoli 11645baee14SGuilherme G. Piccoli early_param("ppc_pci_reset_phbs", pci_reset_phbs_setup); 11745baee14SGuilherme G. Piccoli 1181e916772SGavin Shan static struct pnv_ioda_pe *pnv_ioda_init_pe(struct pnv_phb *phb, int pe_no) 1191e916772SGavin Shan { 120313483ddSGavin Shan s64 rc; 121313483ddSGavin Shan 1221e916772SGavin Shan phb->ioda.pe_array[pe_no].phb = phb; 1231e916772SGavin Shan phb->ioda.pe_array[pe_no].pe_number = pe_no; 12401e12629SOliver O'Halloran phb->ioda.pe_array[pe_no].dma_setup_done = false; 1251e916772SGavin Shan 126313483ddSGavin Shan /* 127313483ddSGavin Shan * Clear the PE frozen state as it might be put into frozen state 128313483ddSGavin Shan * in the last PCI remove path. It's not harmful to do so when the 129313483ddSGavin Shan * PE is already in unfrozen state. 130313483ddSGavin Shan */ 131313483ddSGavin Shan rc = opal_pci_eeh_freeze_clear(phb->opal_id, pe_no, 132313483ddSGavin Shan OPAL_EEH_ACTION_CLEAR_FREEZE_ALL); 133d4791db5SRussell Currey if (rc != OPAL_SUCCESS && rc != OPAL_UNSUPPORTED) 1341f52f176SRussell Currey pr_warn("%s: Error %lld unfreezing PHB#%x-PE#%x\n", 135313483ddSGavin Shan __func__, rc, phb->hose->global_number, pe_no); 136313483ddSGavin Shan 1371e916772SGavin Shan return &phb->ioda.pe_array[pe_no]; 1381e916772SGavin Shan } 1391e916772SGavin Shan 1404b82ab18SGavin Shan static void pnv_ioda_reserve_pe(struct pnv_phb *phb, int pe_no) 1414b82ab18SGavin Shan { 14292b8f137SGavin Shan if (!(pe_no >= 0 && pe_no < phb->ioda.total_pe_num)) { 1431f52f176SRussell Currey pr_warn("%s: Invalid PE %x on PHB#%x\n", 1444b82ab18SGavin Shan __func__, pe_no, phb->hose->global_number); 1454b82ab18SGavin Shan return; 1464b82ab18SGavin Shan } 1474b82ab18SGavin Shan 148a4bc676eSOliver O'Halloran mutex_lock(&phb->ioda.pe_alloc_mutex); 149e9dc4d7fSGavin Shan if (test_and_set_bit(pe_no, phb->ioda.pe_alloc)) 1501f52f176SRussell Currey pr_debug("%s: PE %x was reserved on PHB#%x\n", 1514b82ab18SGavin Shan __func__, pe_no, phb->hose->global_number); 152a4bc676eSOliver O'Halloran mutex_unlock(&phb->ioda.pe_alloc_mutex); 1534b82ab18SGavin Shan 1541e916772SGavin Shan pnv_ioda_init_pe(phb, pe_no); 1554b82ab18SGavin Shan } 1564b82ab18SGavin Shan 157a4bc676eSOliver O'Halloran struct pnv_ioda_pe *pnv_ioda_alloc_pe(struct pnv_phb *phb, int count) 158184cd4a3SBenjamin Herrenschmidt { 159a4bc676eSOliver O'Halloran struct pnv_ioda_pe *ret = NULL; 160a4bc676eSOliver O'Halloran int run = 0, pe, i; 161184cd4a3SBenjamin Herrenschmidt 162a4bc676eSOliver O'Halloran mutex_lock(&phb->ioda.pe_alloc_mutex); 163a4bc676eSOliver O'Halloran 164a4bc676eSOliver O'Halloran /* scan backwards for a run of @count cleared bits */ 1659fcd6f4aSGavin Shan for (pe = phb->ioda.total_pe_num - 1; pe >= 0; pe--) { 166a4bc676eSOliver O'Halloran if (test_bit(pe, phb->ioda.pe_alloc)) { 167a4bc676eSOliver O'Halloran run = 0; 168a4bc676eSOliver O'Halloran continue; 169184cd4a3SBenjamin Herrenschmidt } 170184cd4a3SBenjamin Herrenschmidt 171a4bc676eSOliver O'Halloran run++; 172a4bc676eSOliver O'Halloran if (run == count) 173a4bc676eSOliver O'Halloran break; 174a4bc676eSOliver O'Halloran } 175a4bc676eSOliver O'Halloran if (run != count) 176a4bc676eSOliver O'Halloran goto out; 177a4bc676eSOliver O'Halloran 178a4bc676eSOliver O'Halloran for (i = pe; i < pe + count; i++) { 179a4bc676eSOliver O'Halloran set_bit(i, phb->ioda.pe_alloc); 180a4bc676eSOliver O'Halloran pnv_ioda_init_pe(phb, i); 181a4bc676eSOliver O'Halloran } 182a4bc676eSOliver O'Halloran ret = &phb->ioda.pe_array[pe]; 183a4bc676eSOliver O'Halloran 184a4bc676eSOliver O'Halloran out: 185a4bc676eSOliver O'Halloran mutex_unlock(&phb->ioda.pe_alloc_mutex); 186a4bc676eSOliver O'Halloran return ret; 1879fcd6f4aSGavin Shan } 1889fcd6f4aSGavin Shan 18937b59ef0SOliver O'Halloran void pnv_ioda_free_pe(struct pnv_ioda_pe *pe) 190184cd4a3SBenjamin Herrenschmidt { 1911e916772SGavin Shan struct pnv_phb *phb = pe->phb; 192caa58f80SGavin Shan unsigned int pe_num = pe->pe_number; 193184cd4a3SBenjamin Herrenschmidt 1941e916772SGavin Shan WARN_ON(pe->pdev); 195f724385fSFrederic Barrat WARN_ON(pe->npucomp); /* NPUs for nvlink are not supposed to be freed */ 1960bd97167SAlexey Kardashevskiy kfree(pe->npucomp); 1971e916772SGavin Shan memset(pe, 0, sizeof(struct pnv_ioda_pe)); 198a4bc676eSOliver O'Halloran 199a4bc676eSOliver O'Halloran mutex_lock(&phb->ioda.pe_alloc_mutex); 200caa58f80SGavin Shan clear_bit(pe_num, phb->ioda.pe_alloc); 201a4bc676eSOliver O'Halloran mutex_unlock(&phb->ioda.pe_alloc_mutex); 202184cd4a3SBenjamin Herrenschmidt } 203184cd4a3SBenjamin Herrenschmidt 204262af557SGuo Chao /* The default M64 BAR is shared by all PEs */ 205262af557SGuo Chao static int pnv_ioda2_init_m64(struct pnv_phb *phb) 206262af557SGuo Chao { 207262af557SGuo Chao const char *desc; 208262af557SGuo Chao struct resource *r; 209262af557SGuo Chao s64 rc; 210262af557SGuo Chao 211262af557SGuo Chao /* Configure the default M64 BAR */ 212262af557SGuo Chao rc = opal_pci_set_phb_mem_window(phb->opal_id, 213262af557SGuo Chao OPAL_M64_WINDOW_TYPE, 214262af557SGuo Chao phb->ioda.m64_bar_idx, 215262af557SGuo Chao phb->ioda.m64_base, 216262af557SGuo Chao 0, /* unused */ 217262af557SGuo Chao phb->ioda.m64_size); 218262af557SGuo Chao if (rc != OPAL_SUCCESS) { 219262af557SGuo Chao desc = "configuring"; 220262af557SGuo Chao goto fail; 221262af557SGuo Chao } 222262af557SGuo Chao 223262af557SGuo Chao /* Enable the default M64 BAR */ 224262af557SGuo Chao rc = opal_pci_phb_mmio_enable(phb->opal_id, 225262af557SGuo Chao OPAL_M64_WINDOW_TYPE, 226262af557SGuo Chao phb->ioda.m64_bar_idx, 227262af557SGuo Chao OPAL_ENABLE_M64_SPLIT); 228262af557SGuo Chao if (rc != OPAL_SUCCESS) { 229262af557SGuo Chao desc = "enabling"; 230262af557SGuo Chao goto fail; 231262af557SGuo Chao } 232262af557SGuo Chao 233262af557SGuo Chao /* 23463803c39SGavin Shan * Exclude the segments for reserved and root bus PE, which 23563803c39SGavin Shan * are first or last two PEs. 236262af557SGuo Chao */ 237262af557SGuo Chao r = &phb->hose->mem_resources[1]; 23892b8f137SGavin Shan if (phb->ioda.reserved_pe_idx == 0) 23963803c39SGavin Shan r->start += (2 * phb->ioda.m64_segsize); 24092b8f137SGavin Shan else if (phb->ioda.reserved_pe_idx == (phb->ioda.total_pe_num - 1)) 24163803c39SGavin Shan r->end -= (2 * phb->ioda.m64_segsize); 242262af557SGuo Chao else 2431f52f176SRussell Currey pr_warn(" Cannot strip M64 segment for reserved PE#%x\n", 24492b8f137SGavin Shan phb->ioda.reserved_pe_idx); 245262af557SGuo Chao 246262af557SGuo Chao return 0; 247262af557SGuo Chao 248262af557SGuo Chao fail: 249262af557SGuo Chao pr_warn(" Failure %lld %s M64 BAR#%d\n", 250262af557SGuo Chao rc, desc, phb->ioda.m64_bar_idx); 251262af557SGuo Chao opal_pci_phb_mmio_enable(phb->opal_id, 252262af557SGuo Chao OPAL_M64_WINDOW_TYPE, 253262af557SGuo Chao phb->ioda.m64_bar_idx, 254262af557SGuo Chao OPAL_DISABLE_M64); 255262af557SGuo Chao return -EIO; 256262af557SGuo Chao } 257262af557SGuo Chao 258c430670aSGavin Shan static void pnv_ioda_reserve_dev_m64_pe(struct pci_dev *pdev, 25996a2f92bSGavin Shan unsigned long *pe_bitmap) 260262af557SGuo Chao { 2615609ffddSOliver O'Halloran struct pnv_phb *phb = pci_bus_to_pnvhb(pdev->bus); 262262af557SGuo Chao struct resource *r; 26396a2f92bSGavin Shan resource_size_t base, sgsz, start, end; 26496a2f92bSGavin Shan int segno, i; 265262af557SGuo Chao 26696a2f92bSGavin Shan base = phb->ioda.m64_base; 26796a2f92bSGavin Shan sgsz = phb->ioda.m64_segsize; 26896a2f92bSGavin Shan for (i = 0; i <= PCI_ROM_RESOURCE; i++) { 26996a2f92bSGavin Shan r = &pdev->resource[i]; 2705958d19aSBenjamin Herrenschmidt if (!r->parent || !pnv_pci_is_m64(phb, r)) 271262af557SGuo Chao continue; 272262af557SGuo Chao 273e96d904eSChristophe Leroy start = ALIGN_DOWN(r->start - base, sgsz); 274b7115316SChristophe Leroy end = ALIGN(r->end - base, sgsz); 27596a2f92bSGavin Shan for (segno = start / sgsz; segno < end / sgsz; segno++) { 27696a2f92bSGavin Shan if (pe_bitmap) 27796a2f92bSGavin Shan set_bit(segno, pe_bitmap); 27896a2f92bSGavin Shan else 27996a2f92bSGavin Shan pnv_ioda_reserve_pe(phb, segno); 280262af557SGuo Chao } 281262af557SGuo Chao } 282262af557SGuo Chao } 283262af557SGuo Chao 28499451551SGavin Shan static int pnv_ioda1_init_m64(struct pnv_phb *phb) 28599451551SGavin Shan { 28699451551SGavin Shan struct resource *r; 28799451551SGavin Shan int index; 28899451551SGavin Shan 28999451551SGavin Shan /* 29099451551SGavin Shan * There are 16 M64 BARs, each of which has 8 segments. So 29199451551SGavin Shan * there are as many M64 segments as the maximum number of 29299451551SGavin Shan * PEs, which is 128. 29399451551SGavin Shan */ 29499451551SGavin Shan for (index = 0; index < PNV_IODA1_M64_NUM; index++) { 29599451551SGavin Shan unsigned long base, segsz = phb->ioda.m64_segsize; 29699451551SGavin Shan int64_t rc; 29799451551SGavin Shan 29899451551SGavin Shan base = phb->ioda.m64_base + 29999451551SGavin Shan index * PNV_IODA1_M64_SEGS * segsz; 30099451551SGavin Shan rc = opal_pci_set_phb_mem_window(phb->opal_id, 30199451551SGavin Shan OPAL_M64_WINDOW_TYPE, index, base, 0, 30299451551SGavin Shan PNV_IODA1_M64_SEGS * segsz); 30399451551SGavin Shan if (rc != OPAL_SUCCESS) { 3041f52f176SRussell Currey pr_warn(" Error %lld setting M64 PHB#%x-BAR#%d\n", 30599451551SGavin Shan rc, phb->hose->global_number, index); 30699451551SGavin Shan goto fail; 30799451551SGavin Shan } 30899451551SGavin Shan 30999451551SGavin Shan rc = opal_pci_phb_mmio_enable(phb->opal_id, 31099451551SGavin Shan OPAL_M64_WINDOW_TYPE, index, 31199451551SGavin Shan OPAL_ENABLE_M64_SPLIT); 31299451551SGavin Shan if (rc != OPAL_SUCCESS) { 3131f52f176SRussell Currey pr_warn(" Error %lld enabling M64 PHB#%x-BAR#%d\n", 31499451551SGavin Shan rc, phb->hose->global_number, index); 31599451551SGavin Shan goto fail; 31699451551SGavin Shan } 31799451551SGavin Shan } 31899451551SGavin Shan 31936963365SOliver O'Halloran for (index = 0; index < phb->ioda.total_pe_num; index++) { 32036963365SOliver O'Halloran int64_t rc; 32136963365SOliver O'Halloran 32236963365SOliver O'Halloran /* 32336963365SOliver O'Halloran * P7IOC supports M64DT, which helps mapping M64 segment 32436963365SOliver O'Halloran * to one particular PE#. However, PHB3 has fixed mapping 32536963365SOliver O'Halloran * between M64 segment and PE#. In order to have same logic 32636963365SOliver O'Halloran * for P7IOC and PHB3, we enforce fixed mapping between M64 32736963365SOliver O'Halloran * segment and PE# on P7IOC. 32836963365SOliver O'Halloran */ 32936963365SOliver O'Halloran rc = opal_pci_map_pe_mmio_window(phb->opal_id, 33036963365SOliver O'Halloran index, OPAL_M64_WINDOW_TYPE, 33136963365SOliver O'Halloran index / PNV_IODA1_M64_SEGS, 33236963365SOliver O'Halloran index % PNV_IODA1_M64_SEGS); 33336963365SOliver O'Halloran if (rc != OPAL_SUCCESS) { 33436963365SOliver O'Halloran pr_warn("%s: Error %lld mapping M64 for PHB#%x-PE#%x\n", 33536963365SOliver O'Halloran __func__, rc, phb->hose->global_number, 33636963365SOliver O'Halloran index); 33736963365SOliver O'Halloran goto fail; 33836963365SOliver O'Halloran } 33936963365SOliver O'Halloran } 34036963365SOliver O'Halloran 34199451551SGavin Shan /* 34263803c39SGavin Shan * Exclude the segments for reserved and root bus PE, which 34363803c39SGavin Shan * are first or last two PEs. 34499451551SGavin Shan */ 34599451551SGavin Shan r = &phb->hose->mem_resources[1]; 34699451551SGavin Shan if (phb->ioda.reserved_pe_idx == 0) 34763803c39SGavin Shan r->start += (2 * phb->ioda.m64_segsize); 34899451551SGavin Shan else if (phb->ioda.reserved_pe_idx == (phb->ioda.total_pe_num - 1)) 34963803c39SGavin Shan r->end -= (2 * phb->ioda.m64_segsize); 35099451551SGavin Shan else 3511f52f176SRussell Currey WARN(1, "Wrong reserved PE#%x on PHB#%x\n", 35299451551SGavin Shan phb->ioda.reserved_pe_idx, phb->hose->global_number); 35399451551SGavin Shan 35499451551SGavin Shan return 0; 35599451551SGavin Shan 35699451551SGavin Shan fail: 35799451551SGavin Shan for ( ; index >= 0; index--) 35899451551SGavin Shan opal_pci_phb_mmio_enable(phb->opal_id, 35999451551SGavin Shan OPAL_M64_WINDOW_TYPE, index, OPAL_DISABLE_M64); 36099451551SGavin Shan 36199451551SGavin Shan return -EIO; 36299451551SGavin Shan } 36399451551SGavin Shan 364c430670aSGavin Shan static void pnv_ioda_reserve_m64_pe(struct pci_bus *bus, 36596a2f92bSGavin Shan unsigned long *pe_bitmap, 36696a2f92bSGavin Shan bool all) 367262af557SGuo Chao { 368262af557SGuo Chao struct pci_dev *pdev; 36996a2f92bSGavin Shan 37096a2f92bSGavin Shan list_for_each_entry(pdev, &bus->devices, bus_list) { 371c430670aSGavin Shan pnv_ioda_reserve_dev_m64_pe(pdev, pe_bitmap); 37296a2f92bSGavin Shan 37396a2f92bSGavin Shan if (all && pdev->subordinate) 374c430670aSGavin Shan pnv_ioda_reserve_m64_pe(pdev->subordinate, 37596a2f92bSGavin Shan pe_bitmap, all); 37696a2f92bSGavin Shan } 37796a2f92bSGavin Shan } 37896a2f92bSGavin Shan 3791e916772SGavin Shan static struct pnv_ioda_pe *pnv_ioda_pick_m64_pe(struct pci_bus *bus, bool all) 380262af557SGuo Chao { 3815609ffddSOliver O'Halloran struct pnv_phb *phb = pci_bus_to_pnvhb(bus); 382262af557SGuo Chao struct pnv_ioda_pe *master_pe, *pe; 383262af557SGuo Chao unsigned long size, *pe_alloc; 38426ba248dSGavin Shan int i; 385262af557SGuo Chao 386262af557SGuo Chao /* Root bus shouldn't use M64 */ 387262af557SGuo Chao if (pci_is_root_bus(bus)) 3881e916772SGavin Shan return NULL; 389262af557SGuo Chao 390262af557SGuo Chao /* Allocate bitmap */ 391b7115316SChristophe Leroy size = ALIGN(phb->ioda.total_pe_num / 8, sizeof(unsigned long)); 392262af557SGuo Chao pe_alloc = kzalloc(size, GFP_KERNEL); 393262af557SGuo Chao if (!pe_alloc) { 394262af557SGuo Chao pr_warn("%s: Out of memory !\n", 395262af557SGuo Chao __func__); 3961e916772SGavin Shan return NULL; 397262af557SGuo Chao } 398262af557SGuo Chao 39926ba248dSGavin Shan /* Figure out reserved PE numbers by the PE */ 400c430670aSGavin Shan pnv_ioda_reserve_m64_pe(bus, pe_alloc, all); 401262af557SGuo Chao 402262af557SGuo Chao /* 403262af557SGuo Chao * the current bus might not own M64 window and that's all 404262af557SGuo Chao * contributed by its child buses. For the case, we needn't 405262af557SGuo Chao * pick M64 dependent PE#. 406262af557SGuo Chao */ 40792b8f137SGavin Shan if (bitmap_empty(pe_alloc, phb->ioda.total_pe_num)) { 408262af557SGuo Chao kfree(pe_alloc); 4091e916772SGavin Shan return NULL; 410262af557SGuo Chao } 411262af557SGuo Chao 412262af557SGuo Chao /* 413262af557SGuo Chao * Figure out the master PE and put all slave PEs to master 414262af557SGuo Chao * PE's list to form compound PE. 415262af557SGuo Chao */ 416262af557SGuo Chao master_pe = NULL; 417262af557SGuo Chao i = -1; 41892b8f137SGavin Shan while ((i = find_next_bit(pe_alloc, phb->ioda.total_pe_num, i + 1)) < 41992b8f137SGavin Shan phb->ioda.total_pe_num) { 420262af557SGuo Chao pe = &phb->ioda.pe_array[i]; 421262af557SGuo Chao 42293289d8cSGavin Shan phb->ioda.m64_segmap[pe->pe_number] = pe->pe_number; 423262af557SGuo Chao if (!master_pe) { 424262af557SGuo Chao pe->flags |= PNV_IODA_PE_MASTER; 425262af557SGuo Chao INIT_LIST_HEAD(&pe->slaves); 426262af557SGuo Chao master_pe = pe; 427262af557SGuo Chao } else { 428262af557SGuo Chao pe->flags |= PNV_IODA_PE_SLAVE; 429262af557SGuo Chao pe->master = master_pe; 430262af557SGuo Chao list_add_tail(&pe->list, &master_pe->slaves); 431262af557SGuo Chao } 432262af557SGuo Chao } 433262af557SGuo Chao 434262af557SGuo Chao kfree(pe_alloc); 4351e916772SGavin Shan return master_pe; 436262af557SGuo Chao } 437262af557SGuo Chao 438262af557SGuo Chao static void __init pnv_ioda_parse_m64_window(struct pnv_phb *phb) 439262af557SGuo Chao { 440262af557SGuo Chao struct pci_controller *hose = phb->hose; 441262af557SGuo Chao struct device_node *dn = hose->dn; 442262af557SGuo Chao struct resource *res; 443a1339fafSBenjamin Herrenschmidt u32 m64_range[2], i; 4440e7736c6SGavin Shan const __be32 *r; 445262af557SGuo Chao u64 pci_addr; 446262af557SGuo Chao 44799451551SGavin Shan if (phb->type != PNV_PHB_IODA1 && phb->type != PNV_PHB_IODA2) { 4481665c4a8SGavin Shan pr_info(" Not support M64 window\n"); 4491665c4a8SGavin Shan return; 4501665c4a8SGavin Shan } 4511665c4a8SGavin Shan 452e4d54f71SStewart Smith if (!firmware_has_feature(FW_FEATURE_OPAL)) { 453262af557SGuo Chao pr_info(" Firmware too old to support M64 window\n"); 454262af557SGuo Chao return; 455262af557SGuo Chao } 456262af557SGuo Chao 457262af557SGuo Chao r = of_get_property(dn, "ibm,opal-m64-window", NULL); 458262af557SGuo Chao if (!r) { 459b7c670d6SRob Herring pr_info(" No <ibm,opal-m64-window> on %pOF\n", 460b7c670d6SRob Herring dn); 461262af557SGuo Chao return; 462262af557SGuo Chao } 463262af557SGuo Chao 464a1339fafSBenjamin Herrenschmidt /* 465a1339fafSBenjamin Herrenschmidt * Find the available M64 BAR range and pickup the last one for 466a1339fafSBenjamin Herrenschmidt * covering the whole 64-bits space. We support only one range. 467a1339fafSBenjamin Herrenschmidt */ 468a1339fafSBenjamin Herrenschmidt if (of_property_read_u32_array(dn, "ibm,opal-available-m64-ranges", 469a1339fafSBenjamin Herrenschmidt m64_range, 2)) { 470a1339fafSBenjamin Herrenschmidt /* In absence of the property, assume 0..15 */ 471a1339fafSBenjamin Herrenschmidt m64_range[0] = 0; 472a1339fafSBenjamin Herrenschmidt m64_range[1] = 16; 473a1339fafSBenjamin Herrenschmidt } 474a1339fafSBenjamin Herrenschmidt /* We only support 64 bits in our allocator */ 475a1339fafSBenjamin Herrenschmidt if (m64_range[1] > 63) { 476a1339fafSBenjamin Herrenschmidt pr_warn("%s: Limiting M64 range to 63 (from %d) on PHB#%x\n", 477a1339fafSBenjamin Herrenschmidt __func__, m64_range[1], phb->hose->global_number); 478a1339fafSBenjamin Herrenschmidt m64_range[1] = 63; 479a1339fafSBenjamin Herrenschmidt } 480a1339fafSBenjamin Herrenschmidt /* Empty range, no m64 */ 481a1339fafSBenjamin Herrenschmidt if (m64_range[1] <= m64_range[0]) { 482a1339fafSBenjamin Herrenschmidt pr_warn("%s: M64 empty, disabling M64 usage on PHB#%x\n", 483a1339fafSBenjamin Herrenschmidt __func__, phb->hose->global_number); 484a1339fafSBenjamin Herrenschmidt return; 485a1339fafSBenjamin Herrenschmidt } 486a1339fafSBenjamin Herrenschmidt 487a1339fafSBenjamin Herrenschmidt /* Configure M64 informations */ 488262af557SGuo Chao res = &hose->mem_resources[1]; 489e80c4e7cSGavin Shan res->name = dn->full_name; 490262af557SGuo Chao res->start = of_translate_address(dn, r + 2); 491262af557SGuo Chao res->end = res->start + of_read_number(r + 4, 2) - 1; 492262af557SGuo Chao res->flags = (IORESOURCE_MEM | IORESOURCE_MEM_64 | IORESOURCE_PREFETCH); 493262af557SGuo Chao pci_addr = of_read_number(r, 2); 494262af557SGuo Chao hose->mem_offset[1] = res->start - pci_addr; 495262af557SGuo Chao 496262af557SGuo Chao phb->ioda.m64_size = resource_size(res); 49792b8f137SGavin Shan phb->ioda.m64_segsize = phb->ioda.m64_size / phb->ioda.total_pe_num; 498262af557SGuo Chao phb->ioda.m64_base = pci_addr; 499262af557SGuo Chao 500a1339fafSBenjamin Herrenschmidt /* This lines up nicely with the display from processing OF ranges */ 501a1339fafSBenjamin Herrenschmidt pr_info(" MEM 0x%016llx..0x%016llx -> 0x%016llx (M64 #%d..%d)\n", 502a1339fafSBenjamin Herrenschmidt res->start, res->end, pci_addr, m64_range[0], 503a1339fafSBenjamin Herrenschmidt m64_range[0] + m64_range[1] - 1); 504a1339fafSBenjamin Herrenschmidt 505a1339fafSBenjamin Herrenschmidt /* Mark all M64 used up by default */ 506a1339fafSBenjamin Herrenschmidt phb->ioda.m64_bar_alloc = (unsigned long)-1; 507e9863e68SWei Yang 508262af557SGuo Chao /* Use last M64 BAR to cover M64 window */ 509a1339fafSBenjamin Herrenschmidt m64_range[1]--; 510a1339fafSBenjamin Herrenschmidt phb->ioda.m64_bar_idx = m64_range[0] + m64_range[1]; 511a1339fafSBenjamin Herrenschmidt 512a1339fafSBenjamin Herrenschmidt pr_info(" Using M64 #%d as default window\n", phb->ioda.m64_bar_idx); 513a1339fafSBenjamin Herrenschmidt 514a1339fafSBenjamin Herrenschmidt /* Mark remaining ones free */ 515a1339fafSBenjamin Herrenschmidt for (i = m64_range[0]; i < m64_range[1]; i++) 516a1339fafSBenjamin Herrenschmidt clear_bit(i, &phb->ioda.m64_bar_alloc); 517a1339fafSBenjamin Herrenschmidt 518a1339fafSBenjamin Herrenschmidt /* 519a1339fafSBenjamin Herrenschmidt * Setup init functions for M64 based on IODA version, IODA3 uses 520a1339fafSBenjamin Herrenschmidt * the IODA2 code. 521a1339fafSBenjamin Herrenschmidt */ 52299451551SGavin Shan if (phb->type == PNV_PHB_IODA1) 52399451551SGavin Shan phb->init_m64 = pnv_ioda1_init_m64; 52499451551SGavin Shan else 525262af557SGuo Chao phb->init_m64 = pnv_ioda2_init_m64; 526262af557SGuo Chao } 527262af557SGuo Chao 52849dec922SGavin Shan static void pnv_ioda_freeze_pe(struct pnv_phb *phb, int pe_no) 52949dec922SGavin Shan { 53049dec922SGavin Shan struct pnv_ioda_pe *pe = &phb->ioda.pe_array[pe_no]; 53149dec922SGavin Shan struct pnv_ioda_pe *slave; 53249dec922SGavin Shan s64 rc; 53349dec922SGavin Shan 53449dec922SGavin Shan /* Fetch master PE */ 53549dec922SGavin Shan if (pe->flags & PNV_IODA_PE_SLAVE) { 53649dec922SGavin Shan pe = pe->master; 537ec8e4e9dSGavin Shan if (WARN_ON(!pe || !(pe->flags & PNV_IODA_PE_MASTER))) 538ec8e4e9dSGavin Shan return; 539ec8e4e9dSGavin Shan 54049dec922SGavin Shan pe_no = pe->pe_number; 54149dec922SGavin Shan } 54249dec922SGavin Shan 54349dec922SGavin Shan /* Freeze master PE */ 54449dec922SGavin Shan rc = opal_pci_eeh_freeze_set(phb->opal_id, 54549dec922SGavin Shan pe_no, 54649dec922SGavin Shan OPAL_EEH_ACTION_SET_FREEZE_ALL); 54749dec922SGavin Shan if (rc != OPAL_SUCCESS) { 54849dec922SGavin Shan pr_warn("%s: Failure %lld freezing PHB#%x-PE#%x\n", 54949dec922SGavin Shan __func__, rc, phb->hose->global_number, pe_no); 55049dec922SGavin Shan return; 55149dec922SGavin Shan } 55249dec922SGavin Shan 55349dec922SGavin Shan /* Freeze slave PEs */ 55449dec922SGavin Shan if (!(pe->flags & PNV_IODA_PE_MASTER)) 55549dec922SGavin Shan return; 55649dec922SGavin Shan 55749dec922SGavin Shan list_for_each_entry(slave, &pe->slaves, list) { 55849dec922SGavin Shan rc = opal_pci_eeh_freeze_set(phb->opal_id, 55949dec922SGavin Shan slave->pe_number, 56049dec922SGavin Shan OPAL_EEH_ACTION_SET_FREEZE_ALL); 56149dec922SGavin Shan if (rc != OPAL_SUCCESS) 56249dec922SGavin Shan pr_warn("%s: Failure %lld freezing PHB#%x-PE#%x\n", 56349dec922SGavin Shan __func__, rc, phb->hose->global_number, 56449dec922SGavin Shan slave->pe_number); 56549dec922SGavin Shan } 56649dec922SGavin Shan } 56749dec922SGavin Shan 568e51df2c1SAnton Blanchard static int pnv_ioda_unfreeze_pe(struct pnv_phb *phb, int pe_no, int opt) 56949dec922SGavin Shan { 57049dec922SGavin Shan struct pnv_ioda_pe *pe, *slave; 57149dec922SGavin Shan s64 rc; 57249dec922SGavin Shan 57349dec922SGavin Shan /* Find master PE */ 57449dec922SGavin Shan pe = &phb->ioda.pe_array[pe_no]; 57549dec922SGavin Shan if (pe->flags & PNV_IODA_PE_SLAVE) { 57649dec922SGavin Shan pe = pe->master; 57749dec922SGavin Shan WARN_ON(!pe || !(pe->flags & PNV_IODA_PE_MASTER)); 57849dec922SGavin Shan pe_no = pe->pe_number; 57949dec922SGavin Shan } 58049dec922SGavin Shan 58149dec922SGavin Shan /* Clear frozen state for master PE */ 58249dec922SGavin Shan rc = opal_pci_eeh_freeze_clear(phb->opal_id, pe_no, opt); 58349dec922SGavin Shan if (rc != OPAL_SUCCESS) { 58449dec922SGavin Shan pr_warn("%s: Failure %lld clear %d on PHB#%x-PE#%x\n", 58549dec922SGavin Shan __func__, rc, opt, phb->hose->global_number, pe_no); 58649dec922SGavin Shan return -EIO; 58749dec922SGavin Shan } 58849dec922SGavin Shan 58949dec922SGavin Shan if (!(pe->flags & PNV_IODA_PE_MASTER)) 59049dec922SGavin Shan return 0; 59149dec922SGavin Shan 59249dec922SGavin Shan /* Clear frozen state for slave PEs */ 59349dec922SGavin Shan list_for_each_entry(slave, &pe->slaves, list) { 59449dec922SGavin Shan rc = opal_pci_eeh_freeze_clear(phb->opal_id, 59549dec922SGavin Shan slave->pe_number, 59649dec922SGavin Shan opt); 59749dec922SGavin Shan if (rc != OPAL_SUCCESS) { 59849dec922SGavin Shan pr_warn("%s: Failure %lld clear %d on PHB#%x-PE#%x\n", 59949dec922SGavin Shan __func__, rc, opt, phb->hose->global_number, 60049dec922SGavin Shan slave->pe_number); 60149dec922SGavin Shan return -EIO; 60249dec922SGavin Shan } 60349dec922SGavin Shan } 60449dec922SGavin Shan 60549dec922SGavin Shan return 0; 60649dec922SGavin Shan } 60749dec922SGavin Shan 60849dec922SGavin Shan static int pnv_ioda_get_pe_state(struct pnv_phb *phb, int pe_no) 60949dec922SGavin Shan { 61049dec922SGavin Shan struct pnv_ioda_pe *slave, *pe; 611c2057701SAlexey Kardashevskiy u8 fstate = 0, state; 612c2057701SAlexey Kardashevskiy __be16 pcierr = 0; 61349dec922SGavin Shan s64 rc; 61449dec922SGavin Shan 61549dec922SGavin Shan /* Sanity check on PE number */ 61692b8f137SGavin Shan if (pe_no < 0 || pe_no >= phb->ioda.total_pe_num) 61749dec922SGavin Shan return OPAL_EEH_STOPPED_PERM_UNAVAIL; 61849dec922SGavin Shan 61949dec922SGavin Shan /* 62049dec922SGavin Shan * Fetch the master PE and the PE instance might be 62149dec922SGavin Shan * not initialized yet. 62249dec922SGavin Shan */ 62349dec922SGavin Shan pe = &phb->ioda.pe_array[pe_no]; 62449dec922SGavin Shan if (pe->flags & PNV_IODA_PE_SLAVE) { 62549dec922SGavin Shan pe = pe->master; 62649dec922SGavin Shan WARN_ON(!pe || !(pe->flags & PNV_IODA_PE_MASTER)); 62749dec922SGavin Shan pe_no = pe->pe_number; 62849dec922SGavin Shan } 62949dec922SGavin Shan 63049dec922SGavin Shan /* Check the master PE */ 63149dec922SGavin Shan rc = opal_pci_eeh_freeze_status(phb->opal_id, pe_no, 63249dec922SGavin Shan &state, &pcierr, NULL); 63349dec922SGavin Shan if (rc != OPAL_SUCCESS) { 63449dec922SGavin Shan pr_warn("%s: Failure %lld getting " 63549dec922SGavin Shan "PHB#%x-PE#%x state\n", 63649dec922SGavin Shan __func__, rc, 63749dec922SGavin Shan phb->hose->global_number, pe_no); 63849dec922SGavin Shan return OPAL_EEH_STOPPED_TEMP_UNAVAIL; 63949dec922SGavin Shan } 64049dec922SGavin Shan 64149dec922SGavin Shan /* Check the slave PE */ 64249dec922SGavin Shan if (!(pe->flags & PNV_IODA_PE_MASTER)) 64349dec922SGavin Shan return state; 64449dec922SGavin Shan 64549dec922SGavin Shan list_for_each_entry(slave, &pe->slaves, list) { 64649dec922SGavin Shan rc = opal_pci_eeh_freeze_status(phb->opal_id, 64749dec922SGavin Shan slave->pe_number, 64849dec922SGavin Shan &fstate, 64949dec922SGavin Shan &pcierr, 65049dec922SGavin Shan NULL); 65149dec922SGavin Shan if (rc != OPAL_SUCCESS) { 65249dec922SGavin Shan pr_warn("%s: Failure %lld getting " 65349dec922SGavin Shan "PHB#%x-PE#%x state\n", 65449dec922SGavin Shan __func__, rc, 65549dec922SGavin Shan phb->hose->global_number, slave->pe_number); 65649dec922SGavin Shan return OPAL_EEH_STOPPED_TEMP_UNAVAIL; 65749dec922SGavin Shan } 65849dec922SGavin Shan 65949dec922SGavin Shan /* 66049dec922SGavin Shan * Override the result based on the ascending 66149dec922SGavin Shan * priority. 66249dec922SGavin Shan */ 66349dec922SGavin Shan if (fstate > state) 66449dec922SGavin Shan state = fstate; 66549dec922SGavin Shan } 66649dec922SGavin Shan 66749dec922SGavin Shan return state; 66849dec922SGavin Shan } 66949dec922SGavin Shan 670a8d7d5fcSOliver O'Halloran struct pnv_ioda_pe *pnv_pci_bdfn_to_pe(struct pnv_phb *phb, u16 bdfn) 671a8d7d5fcSOliver O'Halloran { 672a8d7d5fcSOliver O'Halloran int pe_number = phb->ioda.pe_rmap[bdfn]; 673a8d7d5fcSOliver O'Halloran 674a8d7d5fcSOliver O'Halloran if (pe_number == IODA_INVALID_PE) 675a8d7d5fcSOliver O'Halloran return NULL; 676a8d7d5fcSOliver O'Halloran 677a8d7d5fcSOliver O'Halloran return &phb->ioda.pe_array[pe_number]; 678a8d7d5fcSOliver O'Halloran } 679a8d7d5fcSOliver O'Halloran 680f456834aSIan Munsie struct pnv_ioda_pe *pnv_ioda_get_pe(struct pci_dev *dev) 681184cd4a3SBenjamin Herrenschmidt { 6825609ffddSOliver O'Halloran struct pnv_phb *phb = pci_bus_to_pnvhb(dev->bus); 683b72c1f65SBenjamin Herrenschmidt struct pci_dn *pdn = pci_get_pdn(dev); 684184cd4a3SBenjamin Herrenschmidt 685184cd4a3SBenjamin Herrenschmidt if (!pdn) 686184cd4a3SBenjamin Herrenschmidt return NULL; 687184cd4a3SBenjamin Herrenschmidt if (pdn->pe_number == IODA_INVALID_PE) 688184cd4a3SBenjamin Herrenschmidt return NULL; 689184cd4a3SBenjamin Herrenschmidt return &phb->ioda.pe_array[pdn->pe_number]; 690184cd4a3SBenjamin Herrenschmidt } 691184cd4a3SBenjamin Herrenschmidt 692b131a842SGavin Shan static int pnv_ioda_set_one_peltv(struct pnv_phb *phb, 693b131a842SGavin Shan struct pnv_ioda_pe *parent, 694b131a842SGavin Shan struct pnv_ioda_pe *child, 695b131a842SGavin Shan bool is_add) 696b131a842SGavin Shan { 697b131a842SGavin Shan const char *desc = is_add ? "adding" : "removing"; 698b131a842SGavin Shan uint8_t op = is_add ? OPAL_ADD_PE_TO_DOMAIN : 699b131a842SGavin Shan OPAL_REMOVE_PE_FROM_DOMAIN; 700b131a842SGavin Shan struct pnv_ioda_pe *slave; 701b131a842SGavin Shan long rc; 702b131a842SGavin Shan 703b131a842SGavin Shan /* Parent PE affects child PE */ 704b131a842SGavin Shan rc = opal_pci_set_peltv(phb->opal_id, parent->pe_number, 705b131a842SGavin Shan child->pe_number, op); 706b131a842SGavin Shan if (rc != OPAL_SUCCESS) { 707b131a842SGavin Shan pe_warn(child, "OPAL error %ld %s to parent PELTV\n", 708b131a842SGavin Shan rc, desc); 709b131a842SGavin Shan return -ENXIO; 710b131a842SGavin Shan } 711b131a842SGavin Shan 712b131a842SGavin Shan if (!(child->flags & PNV_IODA_PE_MASTER)) 713b131a842SGavin Shan return 0; 714b131a842SGavin Shan 715b131a842SGavin Shan /* Compound case: parent PE affects slave PEs */ 716b131a842SGavin Shan list_for_each_entry(slave, &child->slaves, list) { 717b131a842SGavin Shan rc = opal_pci_set_peltv(phb->opal_id, parent->pe_number, 718b131a842SGavin Shan slave->pe_number, op); 719b131a842SGavin Shan if (rc != OPAL_SUCCESS) { 720b131a842SGavin Shan pe_warn(slave, "OPAL error %ld %s to parent PELTV\n", 721b131a842SGavin Shan rc, desc); 722b131a842SGavin Shan return -ENXIO; 723b131a842SGavin Shan } 724b131a842SGavin Shan } 725b131a842SGavin Shan 726b131a842SGavin Shan return 0; 727b131a842SGavin Shan } 728b131a842SGavin Shan 729b131a842SGavin Shan static int pnv_ioda_set_peltv(struct pnv_phb *phb, 730b131a842SGavin Shan struct pnv_ioda_pe *pe, 731b131a842SGavin Shan bool is_add) 732b131a842SGavin Shan { 733b131a842SGavin Shan struct pnv_ioda_pe *slave; 734781a868fSWei Yang struct pci_dev *pdev = NULL; 735b131a842SGavin Shan int ret; 736b131a842SGavin Shan 737b131a842SGavin Shan /* 738b131a842SGavin Shan * Clear PE frozen state. If it's master PE, we need 739b131a842SGavin Shan * clear slave PE frozen state as well. 740b131a842SGavin Shan */ 741b131a842SGavin Shan if (is_add) { 742b131a842SGavin Shan opal_pci_eeh_freeze_clear(phb->opal_id, pe->pe_number, 743b131a842SGavin Shan OPAL_EEH_ACTION_CLEAR_FREEZE_ALL); 744b131a842SGavin Shan if (pe->flags & PNV_IODA_PE_MASTER) { 745b131a842SGavin Shan list_for_each_entry(slave, &pe->slaves, list) 746b131a842SGavin Shan opal_pci_eeh_freeze_clear(phb->opal_id, 747b131a842SGavin Shan slave->pe_number, 748b131a842SGavin Shan OPAL_EEH_ACTION_CLEAR_FREEZE_ALL); 749b131a842SGavin Shan } 750b131a842SGavin Shan } 751b131a842SGavin Shan 752b131a842SGavin Shan /* 753b131a842SGavin Shan * Associate PE in PELT. We need add the PE into the 754b131a842SGavin Shan * corresponding PELT-V as well. Otherwise, the error 755b131a842SGavin Shan * originated from the PE might contribute to other 756b131a842SGavin Shan * PEs. 757b131a842SGavin Shan */ 758b131a842SGavin Shan ret = pnv_ioda_set_one_peltv(phb, pe, pe, is_add); 759b131a842SGavin Shan if (ret) 760b131a842SGavin Shan return ret; 761b131a842SGavin Shan 762b131a842SGavin Shan /* For compound PEs, any one affects all of them */ 763b131a842SGavin Shan if (pe->flags & PNV_IODA_PE_MASTER) { 764b131a842SGavin Shan list_for_each_entry(slave, &pe->slaves, list) { 765b131a842SGavin Shan ret = pnv_ioda_set_one_peltv(phb, slave, pe, is_add); 766b131a842SGavin Shan if (ret) 767b131a842SGavin Shan return ret; 768b131a842SGavin Shan } 769b131a842SGavin Shan } 770b131a842SGavin Shan 771b131a842SGavin Shan if (pe->flags & (PNV_IODA_PE_BUS_ALL | PNV_IODA_PE_BUS)) 772b131a842SGavin Shan pdev = pe->pbus->self; 773781a868fSWei Yang else if (pe->flags & PNV_IODA_PE_DEV) 774b131a842SGavin Shan pdev = pe->pdev->bus->self; 775781a868fSWei Yang #ifdef CONFIG_PCI_IOV 776781a868fSWei Yang else if (pe->flags & PNV_IODA_PE_VF) 777283e2d8aSGavin Shan pdev = pe->parent_dev; 778781a868fSWei Yang #endif /* CONFIG_PCI_IOV */ 779b131a842SGavin Shan while (pdev) { 780b131a842SGavin Shan struct pci_dn *pdn = pci_get_pdn(pdev); 781b131a842SGavin Shan struct pnv_ioda_pe *parent; 782b131a842SGavin Shan 783b131a842SGavin Shan if (pdn && pdn->pe_number != IODA_INVALID_PE) { 784b131a842SGavin Shan parent = &phb->ioda.pe_array[pdn->pe_number]; 785b131a842SGavin Shan ret = pnv_ioda_set_one_peltv(phb, parent, pe, is_add); 786b131a842SGavin Shan if (ret) 787b131a842SGavin Shan return ret; 788b131a842SGavin Shan } 789b131a842SGavin Shan 790b131a842SGavin Shan pdev = pdev->bus->self; 791b131a842SGavin Shan } 792b131a842SGavin Shan 793b131a842SGavin Shan return 0; 794b131a842SGavin Shan } 795b131a842SGavin Shan 796f724385fSFrederic Barrat static void pnv_ioda_unset_peltv(struct pnv_phb *phb, 797f724385fSFrederic Barrat struct pnv_ioda_pe *pe, 798f724385fSFrederic Barrat struct pci_dev *parent) 799f724385fSFrederic Barrat { 800f724385fSFrederic Barrat int64_t rc; 801f724385fSFrederic Barrat 802f724385fSFrederic Barrat while (parent) { 803f724385fSFrederic Barrat struct pci_dn *pdn = pci_get_pdn(parent); 804f724385fSFrederic Barrat 805f724385fSFrederic Barrat if (pdn && pdn->pe_number != IODA_INVALID_PE) { 806f724385fSFrederic Barrat rc = opal_pci_set_peltv(phb->opal_id, pdn->pe_number, 807f724385fSFrederic Barrat pe->pe_number, 808f724385fSFrederic Barrat OPAL_REMOVE_PE_FROM_DOMAIN); 809f724385fSFrederic Barrat /* XXX What to do in case of error ? */ 810f724385fSFrederic Barrat } 811f724385fSFrederic Barrat parent = parent->bus->self; 812f724385fSFrederic Barrat } 813f724385fSFrederic Barrat 814f724385fSFrederic Barrat opal_pci_eeh_freeze_clear(phb->opal_id, pe->pe_number, 815f724385fSFrederic Barrat OPAL_EEH_ACTION_CLEAR_FREEZE_ALL); 816f724385fSFrederic Barrat 817f724385fSFrederic Barrat /* Disassociate PE in PELT */ 818f724385fSFrederic Barrat rc = opal_pci_set_peltv(phb->opal_id, pe->pe_number, 819f724385fSFrederic Barrat pe->pe_number, OPAL_REMOVE_PE_FROM_DOMAIN); 820f724385fSFrederic Barrat if (rc) 821f724385fSFrederic Barrat pe_warn(pe, "OPAL error %lld remove self from PELTV\n", rc); 822f724385fSFrederic Barrat } 823f724385fSFrederic Barrat 82437b59ef0SOliver O'Halloran int pnv_ioda_deconfigure_pe(struct pnv_phb *phb, struct pnv_ioda_pe *pe) 825781a868fSWei Yang { 826781a868fSWei Yang struct pci_dev *parent; 827781a868fSWei Yang uint8_t bcomp, dcomp, fcomp; 828781a868fSWei Yang int64_t rc; 829781a868fSWei Yang long rid_end, rid; 830781a868fSWei Yang 831781a868fSWei Yang /* Currently, we just deconfigure VF PE. Bus PE will always there.*/ 832781a868fSWei Yang if (pe->pbus) { 833781a868fSWei Yang int count; 834781a868fSWei Yang 835781a868fSWei Yang dcomp = OPAL_IGNORE_RID_DEVICE_NUMBER; 836781a868fSWei Yang fcomp = OPAL_IGNORE_RID_FUNCTION_NUMBER; 837781a868fSWei Yang parent = pe->pbus->self; 838781a868fSWei Yang if (pe->flags & PNV_IODA_PE_BUS_ALL) 839552aa086SJulia Lawall count = resource_size(&pe->pbus->busn_res); 840781a868fSWei Yang else 841781a868fSWei Yang count = 1; 842781a868fSWei Yang 843781a868fSWei Yang switch(count) { 844781a868fSWei Yang case 1: bcomp = OpalPciBusAll; break; 845781a868fSWei Yang case 2: bcomp = OpalPciBus7Bits; break; 846781a868fSWei Yang case 4: bcomp = OpalPciBus6Bits; break; 847781a868fSWei Yang case 8: bcomp = OpalPciBus5Bits; break; 848781a868fSWei Yang case 16: bcomp = OpalPciBus4Bits; break; 849781a868fSWei Yang case 32: bcomp = OpalPciBus3Bits; break; 850781a868fSWei Yang default: 851781a868fSWei Yang dev_err(&pe->pbus->dev, "Number of subordinate buses %d unsupported\n", 852781a868fSWei Yang count); 853781a868fSWei Yang /* Do an exact match only */ 854781a868fSWei Yang bcomp = OpalPciBusAll; 855781a868fSWei Yang } 856781a868fSWei Yang rid_end = pe->rid + (count << 8); 857781a868fSWei Yang } else { 85893e01a50SGavin Shan #ifdef CONFIG_PCI_IOV 859781a868fSWei Yang if (pe->flags & PNV_IODA_PE_VF) 860781a868fSWei Yang parent = pe->parent_dev; 861781a868fSWei Yang else 86293e01a50SGavin Shan #endif 863781a868fSWei Yang parent = pe->pdev->bus->self; 864781a868fSWei Yang bcomp = OpalPciBusAll; 865781a868fSWei Yang dcomp = OPAL_COMPARE_RID_DEVICE_NUMBER; 866781a868fSWei Yang fcomp = OPAL_COMPARE_RID_FUNCTION_NUMBER; 867781a868fSWei Yang rid_end = pe->rid + 1; 868781a868fSWei Yang } 869781a868fSWei Yang 870781a868fSWei Yang /* Clear the reverse map */ 871781a868fSWei Yang for (rid = pe->rid; rid < rid_end; rid++) 872c127562aSGavin Shan phb->ioda.pe_rmap[rid] = IODA_INVALID_PE; 873781a868fSWei Yang 874f724385fSFrederic Barrat /* 875f724385fSFrederic Barrat * Release from all parents PELT-V. NPUs don't have a PELTV 876f724385fSFrederic Barrat * table 877f724385fSFrederic Barrat */ 878f724385fSFrederic Barrat if (phb->type != PNV_PHB_NPU_NVLINK && phb->type != PNV_PHB_NPU_OCAPI) 879f724385fSFrederic Barrat pnv_ioda_unset_peltv(phb, pe, parent); 880781a868fSWei Yang 881781a868fSWei Yang rc = opal_pci_set_pe(phb->opal_id, pe->pe_number, pe->rid, 882781a868fSWei Yang bcomp, dcomp, fcomp, OPAL_UNMAP_PE); 883781a868fSWei Yang if (rc) 8841e496391SJoe Perches pe_err(pe, "OPAL error %lld trying to setup PELT table\n", rc); 885781a868fSWei Yang 886781a868fSWei Yang pe->pbus = NULL; 887781a868fSWei Yang pe->pdev = NULL; 88893e01a50SGavin Shan #ifdef CONFIG_PCI_IOV 889781a868fSWei Yang pe->parent_dev = NULL; 89093e01a50SGavin Shan #endif 891781a868fSWei Yang 892781a868fSWei Yang return 0; 893781a868fSWei Yang } 894781a868fSWei Yang 89537b59ef0SOliver O'Halloran int pnv_ioda_configure_pe(struct pnv_phb *phb, struct pnv_ioda_pe *pe) 896184cd4a3SBenjamin Herrenschmidt { 897184cd4a3SBenjamin Herrenschmidt uint8_t bcomp, dcomp, fcomp; 898184cd4a3SBenjamin Herrenschmidt long rc, rid_end, rid; 899184cd4a3SBenjamin Herrenschmidt 900184cd4a3SBenjamin Herrenschmidt /* Bus validation ? */ 901184cd4a3SBenjamin Herrenschmidt if (pe->pbus) { 902184cd4a3SBenjamin Herrenschmidt int count; 903184cd4a3SBenjamin Herrenschmidt 904184cd4a3SBenjamin Herrenschmidt dcomp = OPAL_IGNORE_RID_DEVICE_NUMBER; 905184cd4a3SBenjamin Herrenschmidt fcomp = OPAL_IGNORE_RID_FUNCTION_NUMBER; 906fb446ad0SGavin Shan if (pe->flags & PNV_IODA_PE_BUS_ALL) 907552aa086SJulia Lawall count = resource_size(&pe->pbus->busn_res); 908fb446ad0SGavin Shan else 909fb446ad0SGavin Shan count = 1; 910fb446ad0SGavin Shan 911184cd4a3SBenjamin Herrenschmidt switch(count) { 912184cd4a3SBenjamin Herrenschmidt case 1: bcomp = OpalPciBusAll; break; 913184cd4a3SBenjamin Herrenschmidt case 2: bcomp = OpalPciBus7Bits; break; 914184cd4a3SBenjamin Herrenschmidt case 4: bcomp = OpalPciBus6Bits; break; 915184cd4a3SBenjamin Herrenschmidt case 8: bcomp = OpalPciBus5Bits; break; 916184cd4a3SBenjamin Herrenschmidt case 16: bcomp = OpalPciBus4Bits; break; 917184cd4a3SBenjamin Herrenschmidt case 32: bcomp = OpalPciBus3Bits; break; 918184cd4a3SBenjamin Herrenschmidt default: 919781a868fSWei Yang dev_err(&pe->pbus->dev, "Number of subordinate buses %d unsupported\n", 920781a868fSWei Yang count); 921184cd4a3SBenjamin Herrenschmidt /* Do an exact match only */ 922184cd4a3SBenjamin Herrenschmidt bcomp = OpalPciBusAll; 923184cd4a3SBenjamin Herrenschmidt } 924184cd4a3SBenjamin Herrenschmidt rid_end = pe->rid + (count << 8); 925184cd4a3SBenjamin Herrenschmidt } else { 926184cd4a3SBenjamin Herrenschmidt bcomp = OpalPciBusAll; 927184cd4a3SBenjamin Herrenschmidt dcomp = OPAL_COMPARE_RID_DEVICE_NUMBER; 928184cd4a3SBenjamin Herrenschmidt fcomp = OPAL_COMPARE_RID_FUNCTION_NUMBER; 929184cd4a3SBenjamin Herrenschmidt rid_end = pe->rid + 1; 930184cd4a3SBenjamin Herrenschmidt } 931184cd4a3SBenjamin Herrenschmidt 932631ad691SGavin Shan /* 933631ad691SGavin Shan * Associate PE in PELT. We need add the PE into the 934631ad691SGavin Shan * corresponding PELT-V as well. Otherwise, the error 935631ad691SGavin Shan * originated from the PE might contribute to other 936631ad691SGavin Shan * PEs. 937631ad691SGavin Shan */ 938184cd4a3SBenjamin Herrenschmidt rc = opal_pci_set_pe(phb->opal_id, pe->pe_number, pe->rid, 939184cd4a3SBenjamin Herrenschmidt bcomp, dcomp, fcomp, OPAL_MAP_PE); 940184cd4a3SBenjamin Herrenschmidt if (rc) { 941184cd4a3SBenjamin Herrenschmidt pe_err(pe, "OPAL error %ld trying to setup PELT table\n", rc); 942184cd4a3SBenjamin Herrenschmidt return -ENXIO; 943184cd4a3SBenjamin Herrenschmidt } 944631ad691SGavin Shan 9455d2aa710SAlistair Popple /* 9465d2aa710SAlistair Popple * Configure PELTV. NPUs don't have a PELTV table so skip 9475d2aa710SAlistair Popple * configuration on them. 9485d2aa710SAlistair Popple */ 9497f2c39e9SFrederic Barrat if (phb->type != PNV_PHB_NPU_NVLINK && phb->type != PNV_PHB_NPU_OCAPI) 950b131a842SGavin Shan pnv_ioda_set_peltv(phb, pe, true); 951184cd4a3SBenjamin Herrenschmidt 952184cd4a3SBenjamin Herrenschmidt /* Setup reverse map */ 953184cd4a3SBenjamin Herrenschmidt for (rid = pe->rid; rid < rid_end; rid++) 954184cd4a3SBenjamin Herrenschmidt phb->ioda.pe_rmap[rid] = pe->pe_number; 955184cd4a3SBenjamin Herrenschmidt 956184cd4a3SBenjamin Herrenschmidt /* Setup one MVTs on IODA1 */ 9574773f76bSGavin Shan if (phb->type != PNV_PHB_IODA1) { 9584773f76bSGavin Shan pe->mve_number = 0; 9594773f76bSGavin Shan goto out; 9604773f76bSGavin Shan } 9614773f76bSGavin Shan 962184cd4a3SBenjamin Herrenschmidt pe->mve_number = pe->pe_number; 9634773f76bSGavin Shan rc = opal_pci_set_mve(phb->opal_id, pe->mve_number, pe->pe_number); 9644773f76bSGavin Shan if (rc != OPAL_SUCCESS) { 9651f52f176SRussell Currey pe_err(pe, "OPAL error %ld setting up MVE %x\n", 966184cd4a3SBenjamin Herrenschmidt rc, pe->mve_number); 967184cd4a3SBenjamin Herrenschmidt pe->mve_number = -1; 968184cd4a3SBenjamin Herrenschmidt } else { 969184cd4a3SBenjamin Herrenschmidt rc = opal_pci_set_mve_enable(phb->opal_id, 970cee72d5bSBenjamin Herrenschmidt pe->mve_number, OPAL_ENABLE_MVE); 971184cd4a3SBenjamin Herrenschmidt if (rc) { 9721f52f176SRussell Currey pe_err(pe, "OPAL error %ld enabling MVE %x\n", 973184cd4a3SBenjamin Herrenschmidt rc, pe->mve_number); 974184cd4a3SBenjamin Herrenschmidt pe->mve_number = -1; 975184cd4a3SBenjamin Herrenschmidt } 976184cd4a3SBenjamin Herrenschmidt } 977184cd4a3SBenjamin Herrenschmidt 9784773f76bSGavin Shan out: 979184cd4a3SBenjamin Herrenschmidt return 0; 980184cd4a3SBenjamin Herrenschmidt } 981184cd4a3SBenjamin Herrenschmidt 982cad5cef6SGreg Kroah-Hartman static struct pnv_ioda_pe *pnv_ioda_setup_dev_PE(struct pci_dev *dev) 983184cd4a3SBenjamin Herrenschmidt { 9845609ffddSOliver O'Halloran struct pnv_phb *phb = pci_bus_to_pnvhb(dev->bus); 985b72c1f65SBenjamin Herrenschmidt struct pci_dn *pdn = pci_get_pdn(dev); 986184cd4a3SBenjamin Herrenschmidt struct pnv_ioda_pe *pe; 987184cd4a3SBenjamin Herrenschmidt 988184cd4a3SBenjamin Herrenschmidt if (!pdn) { 989184cd4a3SBenjamin Herrenschmidt pr_err("%s: Device tree node not associated properly\n", 990184cd4a3SBenjamin Herrenschmidt pci_name(dev)); 991184cd4a3SBenjamin Herrenschmidt return NULL; 992184cd4a3SBenjamin Herrenschmidt } 993184cd4a3SBenjamin Herrenschmidt if (pdn->pe_number != IODA_INVALID_PE) 994184cd4a3SBenjamin Herrenschmidt return NULL; 995184cd4a3SBenjamin Herrenschmidt 996a4bc676eSOliver O'Halloran pe = pnv_ioda_alloc_pe(phb, 1); 9971e916772SGavin Shan if (!pe) { 998f2c2cbccSJoe Perches pr_warn("%s: Not enough PE# available, disabling device\n", 999184cd4a3SBenjamin Herrenschmidt pci_name(dev)); 1000184cd4a3SBenjamin Herrenschmidt return NULL; 1001184cd4a3SBenjamin Herrenschmidt } 1002184cd4a3SBenjamin Herrenschmidt 100305dd7da7SFrederic Barrat /* NOTE: We don't get a reference for the pointer in the PE 100405dd7da7SFrederic Barrat * data structure, both the device and PE structures should be 100505dd7da7SFrederic Barrat * destroyed at the same time. However, removing nvlink 100605dd7da7SFrederic Barrat * devices will need some work. 1007184cd4a3SBenjamin Herrenschmidt * 1008184cd4a3SBenjamin Herrenschmidt * At some point we want to remove the PDN completely anyways 1009184cd4a3SBenjamin Herrenschmidt */ 10101e916772SGavin Shan pdn->pe_number = pe->pe_number; 10115d2aa710SAlistair Popple pe->flags = PNV_IODA_PE_DEV; 1012184cd4a3SBenjamin Herrenschmidt pe->pdev = dev; 1013184cd4a3SBenjamin Herrenschmidt pe->pbus = NULL; 1014184cd4a3SBenjamin Herrenschmidt pe->mve_number = -1; 1015184cd4a3SBenjamin Herrenschmidt pe->rid = dev->bus->number << 8 | pdn->devfn; 1016f724385fSFrederic Barrat pe->device_count++; 1017184cd4a3SBenjamin Herrenschmidt 1018184cd4a3SBenjamin Herrenschmidt pe_info(pe, "Associated device to PE\n"); 1019184cd4a3SBenjamin Herrenschmidt 1020184cd4a3SBenjamin Herrenschmidt if (pnv_ioda_configure_pe(phb, pe)) { 1021184cd4a3SBenjamin Herrenschmidt /* XXX What do we do here ? */ 10221e916772SGavin Shan pnv_ioda_free_pe(pe); 1023184cd4a3SBenjamin Herrenschmidt pdn->pe_number = IODA_INVALID_PE; 1024184cd4a3SBenjamin Herrenschmidt pe->pdev = NULL; 1025184cd4a3SBenjamin Herrenschmidt return NULL; 1026184cd4a3SBenjamin Herrenschmidt } 1027184cd4a3SBenjamin Herrenschmidt 10281d4e89cfSAlexey Kardashevskiy /* Put PE to the list */ 102980f1ff83SFrederic Barrat mutex_lock(&phb->ioda.pe_list_mutex); 10301d4e89cfSAlexey Kardashevskiy list_add_tail(&pe->list, &phb->ioda.pe_list); 103180f1ff83SFrederic Barrat mutex_unlock(&phb->ioda.pe_list_mutex); 1032184cd4a3SBenjamin Herrenschmidt return pe; 1033184cd4a3SBenjamin Herrenschmidt } 1034184cd4a3SBenjamin Herrenschmidt 1035fb446ad0SGavin Shan /* 1036fb446ad0SGavin Shan * There're 2 types of PCI bus sensitive PEs: One that is compromised of 1037fb446ad0SGavin Shan * single PCI bus. Another one that contains the primary PCI bus and its 1038fb446ad0SGavin Shan * subordinate PCI devices and buses. The second type of PE is normally 1039fb446ad0SGavin Shan * orgiriated by PCIe-to-PCI bridge or PLX switch downstream ports. 1040fb446ad0SGavin Shan */ 10411e916772SGavin Shan static struct pnv_ioda_pe *pnv_ioda_setup_bus_PE(struct pci_bus *bus, bool all) 1042184cd4a3SBenjamin Herrenschmidt { 10435609ffddSOliver O'Halloran struct pnv_phb *phb = pci_bus_to_pnvhb(bus); 10441e916772SGavin Shan struct pnv_ioda_pe *pe = NULL; 1045ccd1c191SGavin Shan unsigned int pe_num; 1046ccd1c191SGavin Shan 1047ccd1c191SGavin Shan /* 1048ccd1c191SGavin Shan * In partial hotplug case, the PE instance might be still alive. 1049ccd1c191SGavin Shan * We should reuse it instead of allocating a new one. 1050ccd1c191SGavin Shan */ 1051ccd1c191SGavin Shan pe_num = phb->ioda.pe_rmap[bus->number << 8]; 10526ae8aedfSOliver O'Halloran if (WARN_ON(pe_num != IODA_INVALID_PE)) { 1053ccd1c191SGavin Shan pe = &phb->ioda.pe_array[pe_num]; 1054ccd1c191SGavin Shan return NULL; 1055ccd1c191SGavin Shan } 1056184cd4a3SBenjamin Herrenschmidt 105763803c39SGavin Shan /* PE number for root bus should have been reserved */ 1058718d249aSOliver O'Halloran if (pci_is_root_bus(bus)) 105963803c39SGavin Shan pe = &phb->ioda.pe_array[phb->ioda.root_pe_idx]; 106063803c39SGavin Shan 1061262af557SGuo Chao /* Check if PE is determined by M64 */ 1062a25de7afSAlexey Kardashevskiy if (!pe) 1063a25de7afSAlexey Kardashevskiy pe = pnv_ioda_pick_m64_pe(bus, all); 1064262af557SGuo Chao 1065262af557SGuo Chao /* The PE number isn't pinned by M64 */ 10661e916772SGavin Shan if (!pe) 1067a4bc676eSOliver O'Halloran pe = pnv_ioda_alloc_pe(phb, 1); 1068262af557SGuo Chao 10691e916772SGavin Shan if (!pe) { 1070f2c2cbccSJoe Perches pr_warn("%s: Not enough PE# available for PCI bus %04x:%02x\n", 1071fb446ad0SGavin Shan __func__, pci_domain_nr(bus), bus->number); 10721e916772SGavin Shan return NULL; 1073184cd4a3SBenjamin Herrenschmidt } 1074184cd4a3SBenjamin Herrenschmidt 1075262af557SGuo Chao pe->flags |= (all ? PNV_IODA_PE_BUS_ALL : PNV_IODA_PE_BUS); 1076184cd4a3SBenjamin Herrenschmidt pe->pbus = bus; 1077184cd4a3SBenjamin Herrenschmidt pe->pdev = NULL; 1078184cd4a3SBenjamin Herrenschmidt pe->mve_number = -1; 1079b918c62eSYinghai Lu pe->rid = bus->busn_res.start << 8; 1080184cd4a3SBenjamin Herrenschmidt 1081fb446ad0SGavin Shan if (all) 10821e496391SJoe Perches pe_info(pe, "Secondary bus %pad..%pad associated with PE#%x\n", 10831e496391SJoe Perches &bus->busn_res.start, &bus->busn_res.end, 10841e496391SJoe Perches pe->pe_number); 1085fb446ad0SGavin Shan else 10861e496391SJoe Perches pe_info(pe, "Secondary bus %pad associated with PE#%x\n", 10871e496391SJoe Perches &bus->busn_res.start, pe->pe_number); 1088184cd4a3SBenjamin Herrenschmidt 1089184cd4a3SBenjamin Herrenschmidt if (pnv_ioda_configure_pe(phb, pe)) { 1090184cd4a3SBenjamin Herrenschmidt /* XXX What do we do here ? */ 10911e916772SGavin Shan pnv_ioda_free_pe(pe); 1092184cd4a3SBenjamin Herrenschmidt pe->pbus = NULL; 10931e916772SGavin Shan return NULL; 1094184cd4a3SBenjamin Herrenschmidt } 1095184cd4a3SBenjamin Herrenschmidt 10967ebdf956SGavin Shan /* Put PE to the list */ 10977ebdf956SGavin Shan list_add_tail(&pe->list, &phb->ioda.pe_list); 10981e916772SGavin Shan 10991e916772SGavin Shan return pe; 1100184cd4a3SBenjamin Herrenschmidt } 1101184cd4a3SBenjamin Herrenschmidt 1102b521549aSAlistair Popple static struct pnv_ioda_pe *pnv_ioda_setup_npu_PE(struct pci_dev *npu_pdev) 11035d2aa710SAlistair Popple { 1104b521549aSAlistair Popple int pe_num, found_pe = false, rc; 1105b521549aSAlistair Popple long rid; 1106b521549aSAlistair Popple struct pnv_ioda_pe *pe; 1107b521549aSAlistair Popple struct pci_dev *gpu_pdev; 1108b521549aSAlistair Popple struct pci_dn *npu_pdn; 11095609ffddSOliver O'Halloran struct pnv_phb *phb = pci_bus_to_pnvhb(npu_pdev->bus); 1110b521549aSAlistair Popple 1111b521549aSAlistair Popple /* 111205dd7da7SFrederic Barrat * Intentionally leak a reference on the npu device (for 111305dd7da7SFrederic Barrat * nvlink only; this is not an opencapi path) to make sure it 111405dd7da7SFrederic Barrat * never goes away, as it's been the case all along and some 111505dd7da7SFrederic Barrat * work is needed otherwise. 111605dd7da7SFrederic Barrat */ 111705dd7da7SFrederic Barrat pci_dev_get(npu_pdev); 111805dd7da7SFrederic Barrat 111905dd7da7SFrederic Barrat /* 1120b521549aSAlistair Popple * Due to a hardware errata PE#0 on the NPU is reserved for 1121b521549aSAlistair Popple * error handling. This means we only have three PEs remaining 1122b521549aSAlistair Popple * which need to be assigned to four links, implying some 1123b521549aSAlistair Popple * links must share PEs. 1124b521549aSAlistair Popple * 1125b521549aSAlistair Popple * To achieve this we assign PEs such that NPUs linking the 1126b521549aSAlistair Popple * same GPU get assigned the same PE. 1127b521549aSAlistair Popple */ 1128b521549aSAlistair Popple gpu_pdev = pnv_pci_get_gpu_dev(npu_pdev); 112992b8f137SGavin Shan for (pe_num = 0; pe_num < phb->ioda.total_pe_num; pe_num++) { 1130b521549aSAlistair Popple pe = &phb->ioda.pe_array[pe_num]; 1131b521549aSAlistair Popple if (!pe->pdev) 1132b521549aSAlistair Popple continue; 1133b521549aSAlistair Popple 1134b521549aSAlistair Popple if (pnv_pci_get_gpu_dev(pe->pdev) == gpu_pdev) { 1135b521549aSAlistair Popple /* 1136b521549aSAlistair Popple * This device has the same peer GPU so should 1137b521549aSAlistair Popple * be assigned the same PE as the existing 1138b521549aSAlistair Popple * peer NPU. 1139b521549aSAlistair Popple */ 1140b521549aSAlistair Popple dev_info(&npu_pdev->dev, 11411f52f176SRussell Currey "Associating to existing PE %x\n", pe_num); 1142b521549aSAlistair Popple npu_pdn = pci_get_pdn(npu_pdev); 1143b521549aSAlistair Popple rid = npu_pdev->bus->number << 8 | npu_pdn->devfn; 1144b521549aSAlistair Popple npu_pdn->pe_number = pe_num; 1145b521549aSAlistair Popple phb->ioda.pe_rmap[rid] = pe->pe_number; 1146f724385fSFrederic Barrat pe->device_count++; 1147b521549aSAlistair Popple 1148b521549aSAlistair Popple /* Map the PE to this link */ 1149b521549aSAlistair Popple rc = opal_pci_set_pe(phb->opal_id, pe_num, rid, 1150b521549aSAlistair Popple OpalPciBusAll, 1151b521549aSAlistair Popple OPAL_COMPARE_RID_DEVICE_NUMBER, 1152b521549aSAlistair Popple OPAL_COMPARE_RID_FUNCTION_NUMBER, 1153b521549aSAlistair Popple OPAL_MAP_PE); 1154b521549aSAlistair Popple WARN_ON(rc != OPAL_SUCCESS); 1155b521549aSAlistair Popple found_pe = true; 1156b521549aSAlistair Popple break; 1157b521549aSAlistair Popple } 1158b521549aSAlistair Popple } 1159b521549aSAlistair Popple 1160b521549aSAlistair Popple if (!found_pe) 1161b521549aSAlistair Popple /* 1162b521549aSAlistair Popple * Could not find an existing PE so allocate a new 1163b521549aSAlistair Popple * one. 1164b521549aSAlistair Popple */ 1165b521549aSAlistair Popple return pnv_ioda_setup_dev_PE(npu_pdev); 1166b521549aSAlistair Popple else 1167b521549aSAlistair Popple return pe; 1168b521549aSAlistair Popple } 1169b521549aSAlistair Popple 1170b521549aSAlistair Popple static void pnv_ioda_setup_npu_PEs(struct pci_bus *bus) 1171b521549aSAlistair Popple { 11725d2aa710SAlistair Popple struct pci_dev *pdev; 11735d2aa710SAlistair Popple 11745d2aa710SAlistair Popple list_for_each_entry(pdev, &bus->devices, bus_list) 1175b521549aSAlistair Popple pnv_ioda_setup_npu_PE(pdev); 11765d2aa710SAlistair Popple } 11775d2aa710SAlistair Popple 117803b7bf34SOliver O'Halloran static void pnv_pci_ioda_setup_nvlink(void) 1179fb446ad0SGavin Shan { 11800e759bd7SAlexey Kardashevskiy struct pci_controller *hose; 1181262af557SGuo Chao struct pnv_phb *phb; 11820e759bd7SAlexey Kardashevskiy struct pnv_ioda_pe *pe; 1183fb446ad0SGavin Shan 11840e759bd7SAlexey Kardashevskiy list_for_each_entry(hose, &hose_list, list_node) { 1185262af557SGuo Chao phb = hose->private_data; 11867f2c39e9SFrederic Barrat if (phb->type == PNV_PHB_NPU_NVLINK) { 118708f48f32SAlistair Popple /* PE#0 is needed for error reporting */ 118808f48f32SAlistair Popple pnv_ioda_reserve_pe(phb, 0); 1189b521549aSAlistair Popple pnv_ioda_setup_npu_PEs(hose->bus); 11901ab66d1fSAlistair Popple if (phb->model == PNV_PHB_MODEL_NPU2) 11910e759bd7SAlexey Kardashevskiy WARN_ON_ONCE(pnv_npu2_init(hose)); 1192ccd1c191SGavin Shan } 1193fb446ad0SGavin Shan } 11940e759bd7SAlexey Kardashevskiy list_for_each_entry(hose, &hose_list, list_node) { 11950e759bd7SAlexey Kardashevskiy phb = hose->private_data; 11960e759bd7SAlexey Kardashevskiy if (phb->type != PNV_PHB_IODA2) 11970e759bd7SAlexey Kardashevskiy continue; 11980e759bd7SAlexey Kardashevskiy 11990e759bd7SAlexey Kardashevskiy list_for_each_entry(pe, &phb->ioda.pe_list, list) 12000e759bd7SAlexey Kardashevskiy pnv_npu2_map_lpar(pe, MSR_DR | MSR_PR | MSR_HV); 12010e759bd7SAlexey Kardashevskiy } 120203b7bf34SOliver O'Halloran 120303b7bf34SOliver O'Halloran #ifdef CONFIG_IOMMU_API 120403b7bf34SOliver O'Halloran /* setup iommu groups so we can do nvlink pass-thru */ 120503b7bf34SOliver O'Halloran pnv_pci_npu_setup_iommu_groups(); 120603b7bf34SOliver O'Halloran #endif 1207fb446ad0SGavin Shan } 1208184cd4a3SBenjamin Herrenschmidt 120901e12629SOliver O'Halloran static void pnv_pci_ioda1_setup_dma_pe(struct pnv_phb *phb, 121001e12629SOliver O'Halloran struct pnv_ioda_pe *pe); 121101e12629SOliver O'Halloran 12120a25d9c4SOliver O'Halloran static void pnv_pci_ioda_dma_dev_setup(struct pci_dev *pdev) 1213184cd4a3SBenjamin Herrenschmidt { 12145609ffddSOliver O'Halloran struct pnv_phb *phb = pci_bus_to_pnvhb(pdev->bus); 1215b72c1f65SBenjamin Herrenschmidt struct pci_dn *pdn = pci_get_pdn(pdev); 1216959c9bddSGavin Shan struct pnv_ioda_pe *pe; 1217184cd4a3SBenjamin Herrenschmidt 1218dc3d8f85SOliver O'Halloran /* Check if the BDFN for this device is associated with a PE yet */ 1219dc3d8f85SOliver O'Halloran pe = pnv_pci_bdfn_to_pe(phb, pdev->devfn | (pdev->bus->number << 8)); 1220dc3d8f85SOliver O'Halloran if (!pe) { 1221dc3d8f85SOliver O'Halloran /* VF PEs should be pre-configured in pnv_pci_sriov_enable() */ 1222dc3d8f85SOliver O'Halloran if (WARN_ON(pdev->is_virtfn)) 1223959c9bddSGavin Shan return; 1224184cd4a3SBenjamin Herrenschmidt 1225dc3d8f85SOliver O'Halloran pnv_pci_configure_bus(pdev->bus); 1226dc3d8f85SOliver O'Halloran pe = pnv_pci_bdfn_to_pe(phb, pdev->devfn | (pdev->bus->number << 8)); 1227dc3d8f85SOliver O'Halloran pci_info(pdev, "Configured PE#%x\n", pe ? pe->pe_number : 0xfffff); 1228dc3d8f85SOliver O'Halloran 1229dc3d8f85SOliver O'Halloran 1230dc3d8f85SOliver O'Halloran /* 1231dc3d8f85SOliver O'Halloran * If we can't setup the IODA PE something has gone horribly 1232dc3d8f85SOliver O'Halloran * wrong and we can't enable DMA for the device. 1233dc3d8f85SOliver O'Halloran */ 1234dc3d8f85SOliver O'Halloran if (WARN_ON(!pe)) 1235dc3d8f85SOliver O'Halloran return; 1236dc3d8f85SOliver O'Halloran } else { 1237dc3d8f85SOliver O'Halloran pci_info(pdev, "Added to existing PE#%x\n", pe->pe_number); 1238dc3d8f85SOliver O'Halloran } 1239dc3d8f85SOliver O'Halloran 124001e12629SOliver O'Halloran /* 124101e12629SOliver O'Halloran * We assume that bridges *probably* don't need to do any DMA so we can 124201e12629SOliver O'Halloran * skip allocating a TCE table, etc unless we get a non-bridge device. 124301e12629SOliver O'Halloran */ 124401e12629SOliver O'Halloran if (!pe->dma_setup_done && !pci_is_bridge(pdev)) { 124501e12629SOliver O'Halloran switch (phb->type) { 124601e12629SOliver O'Halloran case PNV_PHB_IODA1: 124701e12629SOliver O'Halloran pnv_pci_ioda1_setup_dma_pe(phb, pe); 124801e12629SOliver O'Halloran break; 124901e12629SOliver O'Halloran case PNV_PHB_IODA2: 125001e12629SOliver O'Halloran pnv_pci_ioda2_setup_dma_pe(phb, pe); 125101e12629SOliver O'Halloran break; 125201e12629SOliver O'Halloran default: 125301e12629SOliver O'Halloran pr_warn("%s: No DMA for PHB#%x (type %d)\n", 125401e12629SOliver O'Halloran __func__, phb->hose->global_number, phb->type); 125501e12629SOliver O'Halloran } 125601e12629SOliver O'Halloran } 125701e12629SOliver O'Halloran 1258dc3d8f85SOliver O'Halloran if (pdn) 1259dc3d8f85SOliver O'Halloran pdn->pe_number = pe->pe_number; 1260dc3d8f85SOliver O'Halloran pe->device_count++; 1261dc3d8f85SOliver O'Halloran 1262cd15b048SBenjamin Herrenschmidt WARN_ON(get_dma_ops(&pdev->dev) != &dma_iommu_ops); 12630617fc0cSChristoph Hellwig pdev->dev.archdata.dma_offset = pe->tce_bypass_base; 1264b348aa65SAlexey Kardashevskiy set_iommu_table_base(&pdev->dev, pe->table_group.tables[0]); 126584d8cc07SOliver O'Halloran 126684d8cc07SOliver O'Halloran /* PEs with a DMA weight of zero won't have a group */ 126784d8cc07SOliver O'Halloran if (pe->table_group.group) 126884d8cc07SOliver O'Halloran iommu_add_device(&pe->table_group, &pdev->dev); 1269184cd4a3SBenjamin Herrenschmidt } 1270184cd4a3SBenjamin Herrenschmidt 12718e3f1b1dSRussell Currey /* 12728e3f1b1dSRussell Currey * Reconfigure TVE#0 to be usable as 64-bit DMA space. 12738e3f1b1dSRussell Currey * 12748e3f1b1dSRussell Currey * The first 4GB of virtual memory for a PE is reserved for 32-bit accesses. 12758e3f1b1dSRussell Currey * Devices can only access more than that if bit 59 of the PCI address is set 12768e3f1b1dSRussell Currey * by hardware, which indicates TVE#1 should be used instead of TVE#0. 12778e3f1b1dSRussell Currey * Many PCI devices are not capable of addressing that many bits, and as a 12788e3f1b1dSRussell Currey * result are limited to the 4GB of virtual memory made available to 32-bit 12798e3f1b1dSRussell Currey * devices in TVE#0. 12808e3f1b1dSRussell Currey * 12818e3f1b1dSRussell Currey * In order to work around this, reconfigure TVE#0 to be suitable for 64-bit 12828e3f1b1dSRussell Currey * devices by configuring the virtual memory past the first 4GB inaccessible 12838e3f1b1dSRussell Currey * by 64-bit DMAs. This should only be used by devices that want more than 12848e3f1b1dSRussell Currey * 4GB, and only on PEs that have no 32-bit devices. 12858e3f1b1dSRussell Currey * 12868e3f1b1dSRussell Currey * Currently this will only work on PHB3 (POWER8). 12878e3f1b1dSRussell Currey */ 12888e3f1b1dSRussell Currey static int pnv_pci_ioda_dma_64bit_bypass(struct pnv_ioda_pe *pe) 12898e3f1b1dSRussell Currey { 12908e3f1b1dSRussell Currey u64 window_size, table_size, tce_count, addr; 12918e3f1b1dSRussell Currey struct page *table_pages; 12928e3f1b1dSRussell Currey u64 tce_order = 28; /* 256MB TCEs */ 12938e3f1b1dSRussell Currey __be64 *tces; 12948e3f1b1dSRussell Currey s64 rc; 12958e3f1b1dSRussell Currey 12968e3f1b1dSRussell Currey /* 12978e3f1b1dSRussell Currey * Window size needs to be a power of two, but needs to account for 12988e3f1b1dSRussell Currey * shifting memory by the 4GB offset required to skip 32bit space. 12998e3f1b1dSRussell Currey */ 13008e3f1b1dSRussell Currey window_size = roundup_pow_of_two(memory_hotplug_max() + (1ULL << 32)); 13018e3f1b1dSRussell Currey tce_count = window_size >> tce_order; 13028e3f1b1dSRussell Currey table_size = tce_count << 3; 13038e3f1b1dSRussell Currey 13048e3f1b1dSRussell Currey if (table_size < PAGE_SIZE) 13058e3f1b1dSRussell Currey table_size = PAGE_SIZE; 13068e3f1b1dSRussell Currey 13078e3f1b1dSRussell Currey table_pages = alloc_pages_node(pe->phb->hose->node, GFP_KERNEL, 13088e3f1b1dSRussell Currey get_order(table_size)); 13098e3f1b1dSRussell Currey if (!table_pages) 13108e3f1b1dSRussell Currey goto err; 13118e3f1b1dSRussell Currey 13128e3f1b1dSRussell Currey tces = page_address(table_pages); 13138e3f1b1dSRussell Currey if (!tces) 13148e3f1b1dSRussell Currey goto err; 13158e3f1b1dSRussell Currey 13168e3f1b1dSRussell Currey memset(tces, 0, table_size); 13178e3f1b1dSRussell Currey 13188e3f1b1dSRussell Currey for (addr = 0; addr < memory_hotplug_max(); addr += (1 << tce_order)) { 13198e3f1b1dSRussell Currey tces[(addr + (1ULL << 32)) >> tce_order] = 13208e3f1b1dSRussell Currey cpu_to_be64(addr | TCE_PCI_READ | TCE_PCI_WRITE); 13218e3f1b1dSRussell Currey } 13228e3f1b1dSRussell Currey 13238e3f1b1dSRussell Currey rc = opal_pci_map_pe_dma_window(pe->phb->opal_id, 13248e3f1b1dSRussell Currey pe->pe_number, 13258e3f1b1dSRussell Currey /* reconfigure window 0 */ 13268e3f1b1dSRussell Currey (pe->pe_number << 1) + 0, 13278e3f1b1dSRussell Currey 1, 13288e3f1b1dSRussell Currey __pa(tces), 13298e3f1b1dSRussell Currey table_size, 13308e3f1b1dSRussell Currey 1 << tce_order); 13318e3f1b1dSRussell Currey if (rc == OPAL_SUCCESS) { 13328e3f1b1dSRussell Currey pe_info(pe, "Using 64-bit DMA iommu bypass (through TVE#0)\n"); 13338e3f1b1dSRussell Currey return 0; 13348e3f1b1dSRussell Currey } 13358e3f1b1dSRussell Currey err: 13368e3f1b1dSRussell Currey pe_err(pe, "Error configuring 64-bit DMA bypass\n"); 13378e3f1b1dSRussell Currey return -EIO; 13388e3f1b1dSRussell Currey } 13398e3f1b1dSRussell Currey 13402d6ad41bSChristoph Hellwig static bool pnv_pci_ioda_iommu_bypass_supported(struct pci_dev *pdev, 13412d6ad41bSChristoph Hellwig u64 dma_mask) 1342cd15b048SBenjamin Herrenschmidt { 13435609ffddSOliver O'Halloran struct pnv_phb *phb = pci_bus_to_pnvhb(pdev->bus); 1344cd15b048SBenjamin Herrenschmidt struct pci_dn *pdn = pci_get_pdn(pdev); 1345cd15b048SBenjamin Herrenschmidt struct pnv_ioda_pe *pe; 1346cd15b048SBenjamin Herrenschmidt 1347cd15b048SBenjamin Herrenschmidt if (WARN_ON(!pdn || pdn->pe_number == IODA_INVALID_PE)) 1348b511cdd1SAlexey Kardashevskiy return false; 1349cd15b048SBenjamin Herrenschmidt 1350cd15b048SBenjamin Herrenschmidt pe = &phb->ioda.pe_array[pdn->pe_number]; 1351cd15b048SBenjamin Herrenschmidt if (pe->tce_bypass_enabled) { 13522d6ad41bSChristoph Hellwig u64 top = pe->tce_bypass_base + memblock_end_of_DRAM() - 1; 13532d6ad41bSChristoph Hellwig if (dma_mask >= top) 13542d6ad41bSChristoph Hellwig return true; 1355cd15b048SBenjamin Herrenschmidt } 1356cd15b048SBenjamin Herrenschmidt 13578e3f1b1dSRussell Currey /* 13588e3f1b1dSRussell Currey * If the device can't set the TCE bypass bit but still wants 13598e3f1b1dSRussell Currey * to access 4GB or more, on PHB3 we can reconfigure TVE#0 to 13608e3f1b1dSRussell Currey * bypass the 32-bit region and be usable for 64-bit DMAs. 13618e3f1b1dSRussell Currey * The device needs to be able to address all of this space. 13628e3f1b1dSRussell Currey */ 13638e3f1b1dSRussell Currey if (dma_mask >> 32 && 13648e3f1b1dSRussell Currey dma_mask > (memory_hotplug_max() + (1ULL << 32)) && 1365661fcb45SChristoph Hellwig /* pe->pdev should be set if it's a single device, pe->pbus if not */ 1366661fcb45SChristoph Hellwig (pe->device_count == 1 || !pe->pbus) && 13678e3f1b1dSRussell Currey phb->model == PNV_PHB_MODEL_PHB3) { 13688e3f1b1dSRussell Currey /* Configure the bypass mode */ 13692d6ad41bSChristoph Hellwig s64 rc = pnv_pci_ioda_dma_64bit_bypass(pe); 13708e3f1b1dSRussell Currey if (rc) 1371b511cdd1SAlexey Kardashevskiy return false; 13728e3f1b1dSRussell Currey /* 4GB offset bypasses 32-bit space */ 13730617fc0cSChristoph Hellwig pdev->dev.archdata.dma_offset = (1ULL << 32); 13742d6ad41bSChristoph Hellwig return true; 1375cd15b048SBenjamin Herrenschmidt } 1376cd15b048SBenjamin Herrenschmidt 13772d6ad41bSChristoph Hellwig return false; 1378fe7e85c6SGavin Shan } 1379fe7e85c6SGavin Shan 1380fd141d1aSBenjamin Herrenschmidt static inline __be64 __iomem *pnv_ioda_get_inval_reg(struct pnv_phb *phb, 1381fd141d1aSBenjamin Herrenschmidt bool real_mode) 1382fd141d1aSBenjamin Herrenschmidt { 1383fd141d1aSBenjamin Herrenschmidt return real_mode ? (__be64 __iomem *)(phb->regs_phys + 0x210) : 1384fd141d1aSBenjamin Herrenschmidt (phb->regs + 0x210); 1385fd141d1aSBenjamin Herrenschmidt } 1386fd141d1aSBenjamin Herrenschmidt 1387a34ab7c3SBenjamin Herrenschmidt static void pnv_pci_p7ioc_tce_invalidate(struct iommu_table *tbl, 1388decbda25SAlexey Kardashevskiy unsigned long index, unsigned long npages, bool rm) 13894cce9550SGavin Shan { 13900eaf4defSAlexey Kardashevskiy struct iommu_table_group_link *tgl = list_first_entry_or_null( 13910eaf4defSAlexey Kardashevskiy &tbl->it_group_list, struct iommu_table_group_link, 13920eaf4defSAlexey Kardashevskiy next); 13930eaf4defSAlexey Kardashevskiy struct pnv_ioda_pe *pe = container_of(tgl->table_group, 1394b348aa65SAlexey Kardashevskiy struct pnv_ioda_pe, table_group); 1395fd141d1aSBenjamin Herrenschmidt __be64 __iomem *invalidate = pnv_ioda_get_inval_reg(pe->phb, rm); 13964cce9550SGavin Shan unsigned long start, end, inc; 13974cce9550SGavin Shan 1398decbda25SAlexey Kardashevskiy start = __pa(((__be64 *)tbl->it_base) + index - tbl->it_offset); 1399decbda25SAlexey Kardashevskiy end = __pa(((__be64 *)tbl->it_base) + index - tbl->it_offset + 1400decbda25SAlexey Kardashevskiy npages - 1); 14014cce9550SGavin Shan 14024cce9550SGavin Shan /* p7ioc-style invalidation, 2 TCEs per write */ 14034cce9550SGavin Shan start |= (1ull << 63); 14044cce9550SGavin Shan end |= (1ull << 63); 14054cce9550SGavin Shan inc = 16; 14064cce9550SGavin Shan end |= inc - 1; /* round up end to be different than start */ 14074cce9550SGavin Shan 14084cce9550SGavin Shan mb(); /* Ensure above stores are visible */ 14094cce9550SGavin Shan while (start <= end) { 14108e0a1611SAlexey Kardashevskiy if (rm) 1411001ff2eeSMichael Ellerman __raw_rm_writeq_be(start, invalidate); 14128e0a1611SAlexey Kardashevskiy else 1413001ff2eeSMichael Ellerman __raw_writeq_be(start, invalidate); 1414001ff2eeSMichael Ellerman 14154cce9550SGavin Shan start += inc; 14164cce9550SGavin Shan } 14174cce9550SGavin Shan 14184cce9550SGavin Shan /* 14194cce9550SGavin Shan * The iommu layer will do another mb() for us on build() 14204cce9550SGavin Shan * and we don't care on free() 14214cce9550SGavin Shan */ 14224cce9550SGavin Shan } 14234cce9550SGavin Shan 1424decbda25SAlexey Kardashevskiy static int pnv_ioda1_tce_build(struct iommu_table *tbl, long index, 1425decbda25SAlexey Kardashevskiy long npages, unsigned long uaddr, 1426decbda25SAlexey Kardashevskiy enum dma_data_direction direction, 142700085f1eSKrzysztof Kozlowski unsigned long attrs) 1428decbda25SAlexey Kardashevskiy { 1429decbda25SAlexey Kardashevskiy int ret = pnv_tce_build(tbl, index, npages, uaddr, direction, 1430decbda25SAlexey Kardashevskiy attrs); 1431decbda25SAlexey Kardashevskiy 143208acce1cSBenjamin Herrenschmidt if (!ret) 1433a34ab7c3SBenjamin Herrenschmidt pnv_pci_p7ioc_tce_invalidate(tbl, index, npages, false); 1434decbda25SAlexey Kardashevskiy 1435decbda25SAlexey Kardashevskiy return ret; 1436decbda25SAlexey Kardashevskiy } 1437decbda25SAlexey Kardashevskiy 143805c6cfb9SAlexey Kardashevskiy #ifdef CONFIG_IOMMU_API 143935872480SAlexey Kardashevskiy /* Common for IODA1 and IODA2 */ 144035872480SAlexey Kardashevskiy static int pnv_ioda_tce_xchg_no_kill(struct iommu_table *tbl, long index, 144135872480SAlexey Kardashevskiy unsigned long *hpa, enum dma_data_direction *direction, 144235872480SAlexey Kardashevskiy bool realmode) 144305c6cfb9SAlexey Kardashevskiy { 144435872480SAlexey Kardashevskiy return pnv_tce_xchg(tbl, index, hpa, direction, !realmode); 1445a540aa56SAlexey Kardashevskiy } 144605c6cfb9SAlexey Kardashevskiy #endif 144705c6cfb9SAlexey Kardashevskiy 1448decbda25SAlexey Kardashevskiy static void pnv_ioda1_tce_free(struct iommu_table *tbl, long index, 1449decbda25SAlexey Kardashevskiy long npages) 1450decbda25SAlexey Kardashevskiy { 1451decbda25SAlexey Kardashevskiy pnv_tce_free(tbl, index, npages); 1452decbda25SAlexey Kardashevskiy 1453a34ab7c3SBenjamin Herrenschmidt pnv_pci_p7ioc_tce_invalidate(tbl, index, npages, false); 1454decbda25SAlexey Kardashevskiy } 1455decbda25SAlexey Kardashevskiy 1456da004c36SAlexey Kardashevskiy static struct iommu_table_ops pnv_ioda1_iommu_ops = { 1457decbda25SAlexey Kardashevskiy .set = pnv_ioda1_tce_build, 145805c6cfb9SAlexey Kardashevskiy #ifdef CONFIG_IOMMU_API 145935872480SAlexey Kardashevskiy .xchg_no_kill = pnv_ioda_tce_xchg_no_kill, 146035872480SAlexey Kardashevskiy .tce_kill = pnv_pci_p7ioc_tce_invalidate, 1461090bad39SAlexey Kardashevskiy .useraddrptr = pnv_tce_useraddrptr, 146205c6cfb9SAlexey Kardashevskiy #endif 1463decbda25SAlexey Kardashevskiy .clear = pnv_ioda1_tce_free, 1464da004c36SAlexey Kardashevskiy .get = pnv_tce_get, 1465da004c36SAlexey Kardashevskiy }; 1466da004c36SAlexey Kardashevskiy 1467a34ab7c3SBenjamin Herrenschmidt #define PHB3_TCE_KILL_INVAL_ALL PPC_BIT(0) 1468a34ab7c3SBenjamin Herrenschmidt #define PHB3_TCE_KILL_INVAL_PE PPC_BIT(1) 1469a34ab7c3SBenjamin Herrenschmidt #define PHB3_TCE_KILL_INVAL_ONE PPC_BIT(2) 1470bef9253fSAlexey Kardashevskiy 14716b3d12a9SAlistair Popple static void pnv_pci_phb3_tce_invalidate_entire(struct pnv_phb *phb, bool rm) 14720bbcdb43SAlexey Kardashevskiy { 1473fd141d1aSBenjamin Herrenschmidt __be64 __iomem *invalidate = pnv_ioda_get_inval_reg(phb, rm); 1474a34ab7c3SBenjamin Herrenschmidt const unsigned long val = PHB3_TCE_KILL_INVAL_ALL; 14750bbcdb43SAlexey Kardashevskiy 14760bbcdb43SAlexey Kardashevskiy mb(); /* Ensure previous TCE table stores are visible */ 14770bbcdb43SAlexey Kardashevskiy if (rm) 1478001ff2eeSMichael Ellerman __raw_rm_writeq_be(val, invalidate); 14790bbcdb43SAlexey Kardashevskiy else 1480001ff2eeSMichael Ellerman __raw_writeq_be(val, invalidate); 14810bbcdb43SAlexey Kardashevskiy } 14820bbcdb43SAlexey Kardashevskiy 1483a34ab7c3SBenjamin Herrenschmidt static inline void pnv_pci_phb3_tce_invalidate_pe(struct pnv_ioda_pe *pe) 14845780fb04SAlexey Kardashevskiy { 14855780fb04SAlexey Kardashevskiy /* 01xb - invalidate TCEs that match the specified PE# */ 1486fd141d1aSBenjamin Herrenschmidt __be64 __iomem *invalidate = pnv_ioda_get_inval_reg(pe->phb, false); 1487a34ab7c3SBenjamin Herrenschmidt unsigned long val = PHB3_TCE_KILL_INVAL_PE | (pe->pe_number & 0xFF); 14885780fb04SAlexey Kardashevskiy 14895780fb04SAlexey Kardashevskiy mb(); /* Ensure above stores are visible */ 1490001ff2eeSMichael Ellerman __raw_writeq_be(val, invalidate); 14915780fb04SAlexey Kardashevskiy } 14925780fb04SAlexey Kardashevskiy 1493fd141d1aSBenjamin Herrenschmidt static void pnv_pci_phb3_tce_invalidate(struct pnv_ioda_pe *pe, bool rm, 1494fd141d1aSBenjamin Herrenschmidt unsigned shift, unsigned long index, 1495fd141d1aSBenjamin Herrenschmidt unsigned long npages) 14964cce9550SGavin Shan { 14974d902195SAlexey Kardashevskiy __be64 __iomem *invalidate = pnv_ioda_get_inval_reg(pe->phb, rm); 14984cce9550SGavin Shan unsigned long start, end, inc; 14994cce9550SGavin Shan 15004cce9550SGavin Shan /* We'll invalidate DMA address in PE scope */ 1501a34ab7c3SBenjamin Herrenschmidt start = PHB3_TCE_KILL_INVAL_ONE; 1502fd141d1aSBenjamin Herrenschmidt start |= (pe->pe_number & 0xFF); 15034cce9550SGavin Shan end = start; 15044cce9550SGavin Shan 15054cce9550SGavin Shan /* Figure out the start, end and step */ 1506decbda25SAlexey Kardashevskiy start |= (index << shift); 1507decbda25SAlexey Kardashevskiy end |= ((index + npages - 1) << shift); 1508b0376c9bSAlexey Kardashevskiy inc = (0x1ull << shift); 15094cce9550SGavin Shan mb(); 15104cce9550SGavin Shan 15114cce9550SGavin Shan while (start <= end) { 15128e0a1611SAlexey Kardashevskiy if (rm) 1513001ff2eeSMichael Ellerman __raw_rm_writeq_be(start, invalidate); 15148e0a1611SAlexey Kardashevskiy else 1515001ff2eeSMichael Ellerman __raw_writeq_be(start, invalidate); 15164cce9550SGavin Shan start += inc; 15174cce9550SGavin Shan } 15184cce9550SGavin Shan } 15194cce9550SGavin Shan 1520f0228c41SBenjamin Herrenschmidt static inline void pnv_pci_ioda2_tce_invalidate_pe(struct pnv_ioda_pe *pe) 1521f0228c41SBenjamin Herrenschmidt { 1522f0228c41SBenjamin Herrenschmidt struct pnv_phb *phb = pe->phb; 1523f0228c41SBenjamin Herrenschmidt 1524f0228c41SBenjamin Herrenschmidt if (phb->model == PNV_PHB_MODEL_PHB3 && phb->regs) 1525f0228c41SBenjamin Herrenschmidt pnv_pci_phb3_tce_invalidate_pe(pe); 1526f0228c41SBenjamin Herrenschmidt else 1527f0228c41SBenjamin Herrenschmidt opal_pci_tce_kill(phb->opal_id, OPAL_PCI_TCE_KILL_PE, 1528f0228c41SBenjamin Herrenschmidt pe->pe_number, 0, 0, 0); 1529f0228c41SBenjamin Herrenschmidt } 1530f0228c41SBenjamin Herrenschmidt 1531e57080f1SAlexey Kardashevskiy static void pnv_pci_ioda2_tce_invalidate(struct iommu_table *tbl, 1532e57080f1SAlexey Kardashevskiy unsigned long index, unsigned long npages, bool rm) 1533e57080f1SAlexey Kardashevskiy { 1534e57080f1SAlexey Kardashevskiy struct iommu_table_group_link *tgl; 1535e57080f1SAlexey Kardashevskiy 1536a540aa56SAlexey Kardashevskiy list_for_each_entry_lockless(tgl, &tbl->it_group_list, next) { 1537e57080f1SAlexey Kardashevskiy struct pnv_ioda_pe *pe = container_of(tgl->table_group, 1538e57080f1SAlexey Kardashevskiy struct pnv_ioda_pe, table_group); 1539f0228c41SBenjamin Herrenschmidt struct pnv_phb *phb = pe->phb; 1540f0228c41SBenjamin Herrenschmidt unsigned int shift = tbl->it_page_shift; 1541f0228c41SBenjamin Herrenschmidt 1542616badd2SAlistair Popple /* 1543616badd2SAlistair Popple * NVLink1 can use the TCE kill register directly as 1544616badd2SAlistair Popple * it's the same as PHB3. NVLink2 is different and 1545616badd2SAlistair Popple * should go via the OPAL call. 1546616badd2SAlistair Popple */ 1547616badd2SAlistair Popple if (phb->model == PNV_PHB_MODEL_NPU) { 15480bbcdb43SAlexey Kardashevskiy /* 15490bbcdb43SAlexey Kardashevskiy * The NVLink hardware does not support TCE kill 15500bbcdb43SAlexey Kardashevskiy * per TCE entry so we have to invalidate 15510bbcdb43SAlexey Kardashevskiy * the entire cache for it. 15520bbcdb43SAlexey Kardashevskiy */ 1553f0228c41SBenjamin Herrenschmidt pnv_pci_phb3_tce_invalidate_entire(phb, rm); 15545d2aa710SAlistair Popple continue; 15555d2aa710SAlistair Popple } 1556f0228c41SBenjamin Herrenschmidt if (phb->model == PNV_PHB_MODEL_PHB3 && phb->regs) 1557f0228c41SBenjamin Herrenschmidt pnv_pci_phb3_tce_invalidate(pe, rm, shift, 155885674868SAlexey Kardashevskiy index, npages); 1559f0228c41SBenjamin Herrenschmidt else 1560f0228c41SBenjamin Herrenschmidt opal_pci_tce_kill(phb->opal_id, 1561f0228c41SBenjamin Herrenschmidt OPAL_PCI_TCE_KILL_PAGES, 1562f0228c41SBenjamin Herrenschmidt pe->pe_number, 1u << shift, 1563f0228c41SBenjamin Herrenschmidt index << shift, npages); 1564e57080f1SAlexey Kardashevskiy } 1565e57080f1SAlexey Kardashevskiy } 1566e57080f1SAlexey Kardashevskiy 15676b3d12a9SAlistair Popple void pnv_pci_ioda2_tce_invalidate_entire(struct pnv_phb *phb, bool rm) 15686b3d12a9SAlistair Popple { 15696b3d12a9SAlistair Popple if (phb->model == PNV_PHB_MODEL_NPU || phb->model == PNV_PHB_MODEL_PHB3) 15706b3d12a9SAlistair Popple pnv_pci_phb3_tce_invalidate_entire(phb, rm); 15716b3d12a9SAlistair Popple else 15726b3d12a9SAlistair Popple opal_pci_tce_kill(phb->opal_id, OPAL_PCI_TCE_KILL, 0, 0, 0, 0); 15736b3d12a9SAlistair Popple } 15746b3d12a9SAlistair Popple 1575decbda25SAlexey Kardashevskiy static int pnv_ioda2_tce_build(struct iommu_table *tbl, long index, 1576decbda25SAlexey Kardashevskiy long npages, unsigned long uaddr, 1577decbda25SAlexey Kardashevskiy enum dma_data_direction direction, 157800085f1eSKrzysztof Kozlowski unsigned long attrs) 15794cce9550SGavin Shan { 1580decbda25SAlexey Kardashevskiy int ret = pnv_tce_build(tbl, index, npages, uaddr, direction, 1581decbda25SAlexey Kardashevskiy attrs); 15824cce9550SGavin Shan 158308acce1cSBenjamin Herrenschmidt if (!ret) 1584decbda25SAlexey Kardashevskiy pnv_pci_ioda2_tce_invalidate(tbl, index, npages, false); 1585decbda25SAlexey Kardashevskiy 1586decbda25SAlexey Kardashevskiy return ret; 1587decbda25SAlexey Kardashevskiy } 1588decbda25SAlexey Kardashevskiy 1589decbda25SAlexey Kardashevskiy static void pnv_ioda2_tce_free(struct iommu_table *tbl, long index, 1590decbda25SAlexey Kardashevskiy long npages) 1591decbda25SAlexey Kardashevskiy { 1592decbda25SAlexey Kardashevskiy pnv_tce_free(tbl, index, npages); 1593decbda25SAlexey Kardashevskiy 1594decbda25SAlexey Kardashevskiy pnv_pci_ioda2_tce_invalidate(tbl, index, npages, false); 15954cce9550SGavin Shan } 15964cce9550SGavin Shan 1597da004c36SAlexey Kardashevskiy static struct iommu_table_ops pnv_ioda2_iommu_ops = { 1598decbda25SAlexey Kardashevskiy .set = pnv_ioda2_tce_build, 159905c6cfb9SAlexey Kardashevskiy #ifdef CONFIG_IOMMU_API 160035872480SAlexey Kardashevskiy .xchg_no_kill = pnv_ioda_tce_xchg_no_kill, 160135872480SAlexey Kardashevskiy .tce_kill = pnv_pci_ioda2_tce_invalidate, 1602090bad39SAlexey Kardashevskiy .useraddrptr = pnv_tce_useraddrptr, 160305c6cfb9SAlexey Kardashevskiy #endif 1604decbda25SAlexey Kardashevskiy .clear = pnv_ioda2_tce_free, 1605da004c36SAlexey Kardashevskiy .get = pnv_tce_get, 1606da2bb0daSAlexey Kardashevskiy .free = pnv_pci_ioda2_table_free_pages, 1607da004c36SAlexey Kardashevskiy }; 1608da004c36SAlexey Kardashevskiy 1609801846d1SGavin Shan static int pnv_pci_ioda_dev_dma_weight(struct pci_dev *dev, void *data) 1610801846d1SGavin Shan { 1611801846d1SGavin Shan unsigned int *weight = (unsigned int *)data; 1612801846d1SGavin Shan 1613801846d1SGavin Shan /* This is quite simplistic. The "base" weight of a device 1614801846d1SGavin Shan * is 10. 0 means no DMA is to be accounted for it. 1615801846d1SGavin Shan */ 1616801846d1SGavin Shan if (dev->hdr_type != PCI_HEADER_TYPE_NORMAL) 1617801846d1SGavin Shan return 0; 1618801846d1SGavin Shan 1619801846d1SGavin Shan if (dev->class == PCI_CLASS_SERIAL_USB_UHCI || 1620801846d1SGavin Shan dev->class == PCI_CLASS_SERIAL_USB_OHCI || 1621801846d1SGavin Shan dev->class == PCI_CLASS_SERIAL_USB_EHCI) 1622801846d1SGavin Shan *weight += 3; 1623801846d1SGavin Shan else if ((dev->class >> 8) == PCI_CLASS_STORAGE_RAID) 1624801846d1SGavin Shan *weight += 15; 1625801846d1SGavin Shan else 1626801846d1SGavin Shan *weight += 10; 1627801846d1SGavin Shan 1628801846d1SGavin Shan return 0; 1629801846d1SGavin Shan } 1630801846d1SGavin Shan 1631801846d1SGavin Shan static unsigned int pnv_pci_ioda_pe_dma_weight(struct pnv_ioda_pe *pe) 1632801846d1SGavin Shan { 1633801846d1SGavin Shan unsigned int weight = 0; 1634801846d1SGavin Shan 1635801846d1SGavin Shan /* SRIOV VF has same DMA32 weight as its PF */ 1636801846d1SGavin Shan #ifdef CONFIG_PCI_IOV 1637801846d1SGavin Shan if ((pe->flags & PNV_IODA_PE_VF) && pe->parent_dev) { 1638801846d1SGavin Shan pnv_pci_ioda_dev_dma_weight(pe->parent_dev, &weight); 1639801846d1SGavin Shan return weight; 1640801846d1SGavin Shan } 1641801846d1SGavin Shan #endif 1642801846d1SGavin Shan 1643801846d1SGavin Shan if ((pe->flags & PNV_IODA_PE_DEV) && pe->pdev) { 1644801846d1SGavin Shan pnv_pci_ioda_dev_dma_weight(pe->pdev, &weight); 1645801846d1SGavin Shan } else if ((pe->flags & PNV_IODA_PE_BUS) && pe->pbus) { 1646801846d1SGavin Shan struct pci_dev *pdev; 1647801846d1SGavin Shan 1648801846d1SGavin Shan list_for_each_entry(pdev, &pe->pbus->devices, bus_list) 1649801846d1SGavin Shan pnv_pci_ioda_dev_dma_weight(pdev, &weight); 1650801846d1SGavin Shan } else if ((pe->flags & PNV_IODA_PE_BUS_ALL) && pe->pbus) { 1651801846d1SGavin Shan pci_walk_bus(pe->pbus, pnv_pci_ioda_dev_dma_weight, &weight); 1652801846d1SGavin Shan } 1653801846d1SGavin Shan 1654801846d1SGavin Shan return weight; 1655801846d1SGavin Shan } 1656801846d1SGavin Shan 1657b30d936fSGavin Shan static void pnv_pci_ioda1_setup_dma_pe(struct pnv_phb *phb, 16582b923ed1SGavin Shan struct pnv_ioda_pe *pe) 1659184cd4a3SBenjamin Herrenschmidt { 1660184cd4a3SBenjamin Herrenschmidt 1661184cd4a3SBenjamin Herrenschmidt struct page *tce_mem = NULL; 1662184cd4a3SBenjamin Herrenschmidt struct iommu_table *tbl; 16632b923ed1SGavin Shan unsigned int weight, total_weight = 0; 16642b923ed1SGavin Shan unsigned int tce32_segsz, base, segs, avail, i; 1665184cd4a3SBenjamin Herrenschmidt int64_t rc; 1666184cd4a3SBenjamin Herrenschmidt void *addr; 1667184cd4a3SBenjamin Herrenschmidt 1668184cd4a3SBenjamin Herrenschmidt /* XXX FIXME: Handle 64-bit only DMA devices */ 1669184cd4a3SBenjamin Herrenschmidt /* XXX FIXME: Provide 64-bit DMA facilities & non-4K TCE tables etc.. */ 1670184cd4a3SBenjamin Herrenschmidt /* XXX FIXME: Allocate multi-level tables on PHB3 */ 16712b923ed1SGavin Shan weight = pnv_pci_ioda_pe_dma_weight(pe); 16722b923ed1SGavin Shan if (!weight) 16732b923ed1SGavin Shan return; 1674184cd4a3SBenjamin Herrenschmidt 16752b923ed1SGavin Shan pci_walk_bus(phb->hose->bus, pnv_pci_ioda_dev_dma_weight, 16762b923ed1SGavin Shan &total_weight); 16772b923ed1SGavin Shan segs = (weight * phb->ioda.dma32_count) / total_weight; 16782b923ed1SGavin Shan if (!segs) 16792b923ed1SGavin Shan segs = 1; 16802b923ed1SGavin Shan 16812b923ed1SGavin Shan /* 16822b923ed1SGavin Shan * Allocate contiguous DMA32 segments. We begin with the expected 16832b923ed1SGavin Shan * number of segments. With one more attempt, the number of DMA32 16842b923ed1SGavin Shan * segments to be allocated is decreased by one until one segment 16852b923ed1SGavin Shan * is allocated successfully. 16862b923ed1SGavin Shan */ 16872b923ed1SGavin Shan do { 16882b923ed1SGavin Shan for (base = 0; base <= phb->ioda.dma32_count - segs; base++) { 16892b923ed1SGavin Shan for (avail = 0, i = base; i < base + segs; i++) { 16902b923ed1SGavin Shan if (phb->ioda.dma32_segmap[i] == 16912b923ed1SGavin Shan IODA_INVALID_PE) 16922b923ed1SGavin Shan avail++; 16932b923ed1SGavin Shan } 16942b923ed1SGavin Shan 16952b923ed1SGavin Shan if (avail == segs) 16962b923ed1SGavin Shan goto found; 16972b923ed1SGavin Shan } 16982b923ed1SGavin Shan } while (--segs); 16992b923ed1SGavin Shan 17002b923ed1SGavin Shan if (!segs) { 17012b923ed1SGavin Shan pe_warn(pe, "No available DMA32 segments\n"); 17022b923ed1SGavin Shan return; 17032b923ed1SGavin Shan } 17042b923ed1SGavin Shan 17052b923ed1SGavin Shan found: 17060eaf4defSAlexey Kardashevskiy tbl = pnv_pci_table_alloc(phb->hose->node); 170782eae1afSAlexey Kardashevskiy if (WARN_ON(!tbl)) 170882eae1afSAlexey Kardashevskiy return; 170982eae1afSAlexey Kardashevskiy 1710b348aa65SAlexey Kardashevskiy iommu_register_group(&pe->table_group, phb->hose->global_number, 1711b348aa65SAlexey Kardashevskiy pe->pe_number); 17120eaf4defSAlexey Kardashevskiy pnv_pci_link_table_and_group(phb->hose->node, 0, tbl, &pe->table_group); 1713c5773822SAlexey Kardashevskiy 1714184cd4a3SBenjamin Herrenschmidt /* Grab a 32-bit TCE table */ 17152b923ed1SGavin Shan pe_info(pe, "DMA weight %d (%d), assigned (%d) %d DMA32 segments\n", 17162b923ed1SGavin Shan weight, total_weight, base, segs); 1717184cd4a3SBenjamin Herrenschmidt pe_info(pe, " Setting up 32-bit TCE table at %08x..%08x\n", 1718acce971cSGavin Shan base * PNV_IODA1_DMA32_SEGSIZE, 1719acce971cSGavin Shan (base + segs) * PNV_IODA1_DMA32_SEGSIZE - 1); 1720184cd4a3SBenjamin Herrenschmidt 1721184cd4a3SBenjamin Herrenschmidt /* XXX Currently, we allocate one big contiguous table for the 1722184cd4a3SBenjamin Herrenschmidt * TCEs. We only really need one chunk per 256M of TCE space 1723184cd4a3SBenjamin Herrenschmidt * (ie per segment) but that's an optimization for later, it 1724184cd4a3SBenjamin Herrenschmidt * requires some added smarts with our get/put_tce implementation 1725acce971cSGavin Shan * 1726acce971cSGavin Shan * Each TCE page is 4KB in size and each TCE entry occupies 8 1727acce971cSGavin Shan * bytes 1728184cd4a3SBenjamin Herrenschmidt */ 1729acce971cSGavin Shan tce32_segsz = PNV_IODA1_DMA32_SEGSIZE >> (IOMMU_PAGE_SHIFT_4K - 3); 1730184cd4a3SBenjamin Herrenschmidt tce_mem = alloc_pages_node(phb->hose->node, GFP_KERNEL, 1731acce971cSGavin Shan get_order(tce32_segsz * segs)); 1732184cd4a3SBenjamin Herrenschmidt if (!tce_mem) { 1733184cd4a3SBenjamin Herrenschmidt pe_err(pe, " Failed to allocate a 32-bit TCE memory\n"); 1734184cd4a3SBenjamin Herrenschmidt goto fail; 1735184cd4a3SBenjamin Herrenschmidt } 1736184cd4a3SBenjamin Herrenschmidt addr = page_address(tce_mem); 1737acce971cSGavin Shan memset(addr, 0, tce32_segsz * segs); 1738184cd4a3SBenjamin Herrenschmidt 1739184cd4a3SBenjamin Herrenschmidt /* Configure HW */ 1740184cd4a3SBenjamin Herrenschmidt for (i = 0; i < segs; i++) { 1741184cd4a3SBenjamin Herrenschmidt rc = opal_pci_map_pe_dma_window(phb->opal_id, 1742184cd4a3SBenjamin Herrenschmidt pe->pe_number, 1743184cd4a3SBenjamin Herrenschmidt base + i, 1, 1744acce971cSGavin Shan __pa(addr) + tce32_segsz * i, 1745acce971cSGavin Shan tce32_segsz, IOMMU_PAGE_SIZE_4K); 1746184cd4a3SBenjamin Herrenschmidt if (rc) { 17471e496391SJoe Perches pe_err(pe, " Failed to configure 32-bit TCE table, err %lld\n", 17481e496391SJoe Perches rc); 1749184cd4a3SBenjamin Herrenschmidt goto fail; 1750184cd4a3SBenjamin Herrenschmidt } 1751184cd4a3SBenjamin Herrenschmidt } 1752184cd4a3SBenjamin Herrenschmidt 17532b923ed1SGavin Shan /* Setup DMA32 segment mapping */ 17542b923ed1SGavin Shan for (i = base; i < base + segs; i++) 17552b923ed1SGavin Shan phb->ioda.dma32_segmap[i] = pe->pe_number; 17562b923ed1SGavin Shan 1757184cd4a3SBenjamin Herrenschmidt /* Setup linux iommu table */ 1758acce971cSGavin Shan pnv_pci_setup_iommu_table(tbl, addr, tce32_segsz * segs, 1759acce971cSGavin Shan base * PNV_IODA1_DMA32_SEGSIZE, 1760acce971cSGavin Shan IOMMU_PAGE_SHIFT_4K); 1761184cd4a3SBenjamin Herrenschmidt 1762da004c36SAlexey Kardashevskiy tbl->it_ops = &pnv_ioda1_iommu_ops; 17634793d65dSAlexey Kardashevskiy pe->table_group.tce32_start = tbl->it_offset << tbl->it_page_shift; 17644793d65dSAlexey Kardashevskiy pe->table_group.tce32_size = tbl->it_size << tbl->it_page_shift; 1765201ed7f3SAlexey Kardashevskiy iommu_init_table(tbl, phb->hose->node, 0, 0); 1766184cd4a3SBenjamin Herrenschmidt 176701e12629SOliver O'Halloran pe->dma_setup_done = true; 1768184cd4a3SBenjamin Herrenschmidt return; 1769184cd4a3SBenjamin Herrenschmidt fail: 1770184cd4a3SBenjamin Herrenschmidt /* XXX Failure: Try to fallback to 64-bit only ? */ 1771184cd4a3SBenjamin Herrenschmidt if (tce_mem) 1772acce971cSGavin Shan __free_pages(tce_mem, get_order(tce32_segsz * segs)); 17730eaf4defSAlexey Kardashevskiy if (tbl) { 17740eaf4defSAlexey Kardashevskiy pnv_pci_unlink_table_and_group(tbl, &pe->table_group); 1775e5afdf9dSAlexey Kardashevskiy iommu_tce_table_put(tbl); 17760eaf4defSAlexey Kardashevskiy } 1777184cd4a3SBenjamin Herrenschmidt } 1778184cd4a3SBenjamin Herrenschmidt 177943cb60abSAlexey Kardashevskiy static long pnv_pci_ioda2_set_window(struct iommu_table_group *table_group, 178043cb60abSAlexey Kardashevskiy int num, struct iommu_table *tbl) 178143cb60abSAlexey Kardashevskiy { 178243cb60abSAlexey Kardashevskiy struct pnv_ioda_pe *pe = container_of(table_group, struct pnv_ioda_pe, 178343cb60abSAlexey Kardashevskiy table_group); 178443cb60abSAlexey Kardashevskiy struct pnv_phb *phb = pe->phb; 178543cb60abSAlexey Kardashevskiy int64_t rc; 1786bbb845c4SAlexey Kardashevskiy const unsigned long size = tbl->it_indirect_levels ? 1787bbb845c4SAlexey Kardashevskiy tbl->it_level_size : tbl->it_size; 178843cb60abSAlexey Kardashevskiy const __u64 start_addr = tbl->it_offset << tbl->it_page_shift; 178943cb60abSAlexey Kardashevskiy const __u64 win_size = tbl->it_size << tbl->it_page_shift; 179043cb60abSAlexey Kardashevskiy 17911e496391SJoe Perches pe_info(pe, "Setting up window#%d %llx..%llx pg=%lx\n", 17921e496391SJoe Perches num, start_addr, start_addr + win_size - 1, 179343cb60abSAlexey Kardashevskiy IOMMU_PAGE_SIZE(tbl)); 179443cb60abSAlexey Kardashevskiy 179543cb60abSAlexey Kardashevskiy /* 179643cb60abSAlexey Kardashevskiy * Map TCE table through TVT. The TVE index is the PE number 179743cb60abSAlexey Kardashevskiy * shifted by 1 bit for 32-bits DMA space. 179843cb60abSAlexey Kardashevskiy */ 179943cb60abSAlexey Kardashevskiy rc = opal_pci_map_pe_dma_window(phb->opal_id, 180043cb60abSAlexey Kardashevskiy pe->pe_number, 18014793d65dSAlexey Kardashevskiy (pe->pe_number << 1) + num, 1802bbb845c4SAlexey Kardashevskiy tbl->it_indirect_levels + 1, 180343cb60abSAlexey Kardashevskiy __pa(tbl->it_base), 1804bbb845c4SAlexey Kardashevskiy size << 3, 180543cb60abSAlexey Kardashevskiy IOMMU_PAGE_SIZE(tbl)); 180643cb60abSAlexey Kardashevskiy if (rc) { 18071e496391SJoe Perches pe_err(pe, "Failed to configure TCE table, err %lld\n", rc); 180843cb60abSAlexey Kardashevskiy return rc; 180943cb60abSAlexey Kardashevskiy } 181043cb60abSAlexey Kardashevskiy 181143cb60abSAlexey Kardashevskiy pnv_pci_link_table_and_group(phb->hose->node, num, 181243cb60abSAlexey Kardashevskiy tbl, &pe->table_group); 1813ed7d9a1dSMichael Ellerman pnv_pci_ioda2_tce_invalidate_pe(pe); 181443cb60abSAlexey Kardashevskiy 181543cb60abSAlexey Kardashevskiy return 0; 181643cb60abSAlexey Kardashevskiy } 181743cb60abSAlexey Kardashevskiy 1818c498a4f9SChristoph Hellwig static void pnv_pci_ioda2_set_bypass(struct pnv_ioda_pe *pe, bool enable) 1819cd15b048SBenjamin Herrenschmidt { 1820cd15b048SBenjamin Herrenschmidt uint16_t window_id = (pe->pe_number << 1 ) + 1; 1821cd15b048SBenjamin Herrenschmidt int64_t rc; 1822cd15b048SBenjamin Herrenschmidt 1823cd15b048SBenjamin Herrenschmidt pe_info(pe, "%sabling 64-bit DMA bypass\n", enable ? "En" : "Dis"); 1824cd15b048SBenjamin Herrenschmidt if (enable) { 1825cd15b048SBenjamin Herrenschmidt phys_addr_t top = memblock_end_of_DRAM(); 1826cd15b048SBenjamin Herrenschmidt 1827cd15b048SBenjamin Herrenschmidt top = roundup_pow_of_two(top); 1828cd15b048SBenjamin Herrenschmidt rc = opal_pci_map_pe_dma_window_real(pe->phb->opal_id, 1829cd15b048SBenjamin Herrenschmidt pe->pe_number, 1830cd15b048SBenjamin Herrenschmidt window_id, 1831cd15b048SBenjamin Herrenschmidt pe->tce_bypass_base, 1832cd15b048SBenjamin Herrenschmidt top); 1833cd15b048SBenjamin Herrenschmidt } else { 1834cd15b048SBenjamin Herrenschmidt rc = opal_pci_map_pe_dma_window_real(pe->phb->opal_id, 1835cd15b048SBenjamin Herrenschmidt pe->pe_number, 1836cd15b048SBenjamin Herrenschmidt window_id, 1837cd15b048SBenjamin Herrenschmidt pe->tce_bypass_base, 1838cd15b048SBenjamin Herrenschmidt 0); 1839cd15b048SBenjamin Herrenschmidt } 1840cd15b048SBenjamin Herrenschmidt if (rc) 1841cd15b048SBenjamin Herrenschmidt pe_err(pe, "OPAL error %lld configuring bypass window\n", rc); 1842cd15b048SBenjamin Herrenschmidt else 1843cd15b048SBenjamin Herrenschmidt pe->tce_bypass_enabled = enable; 1844cd15b048SBenjamin Herrenschmidt } 1845cd15b048SBenjamin Herrenschmidt 18464793d65dSAlexey Kardashevskiy static long pnv_pci_ioda2_create_table(struct iommu_table_group *table_group, 18474793d65dSAlexey Kardashevskiy int num, __u32 page_shift, __u64 window_size, __u32 levels, 1848090bad39SAlexey Kardashevskiy bool alloc_userspace_copy, struct iommu_table **ptbl) 18494793d65dSAlexey Kardashevskiy { 18504793d65dSAlexey Kardashevskiy struct pnv_ioda_pe *pe = container_of(table_group, struct pnv_ioda_pe, 18514793d65dSAlexey Kardashevskiy table_group); 18524793d65dSAlexey Kardashevskiy int nid = pe->phb->hose->node; 18534793d65dSAlexey Kardashevskiy __u64 bus_offset = num ? pe->tce_bypass_base : table_group->tce32_start; 18544793d65dSAlexey Kardashevskiy long ret; 18554793d65dSAlexey Kardashevskiy struct iommu_table *tbl; 18564793d65dSAlexey Kardashevskiy 18574793d65dSAlexey Kardashevskiy tbl = pnv_pci_table_alloc(nid); 18584793d65dSAlexey Kardashevskiy if (!tbl) 18594793d65dSAlexey Kardashevskiy return -ENOMEM; 18604793d65dSAlexey Kardashevskiy 186111edf116SAlexey Kardashevskiy tbl->it_ops = &pnv_ioda2_iommu_ops; 186211edf116SAlexey Kardashevskiy 18634793d65dSAlexey Kardashevskiy ret = pnv_pci_ioda2_table_alloc_pages(nid, 18644793d65dSAlexey Kardashevskiy bus_offset, page_shift, window_size, 1865090bad39SAlexey Kardashevskiy levels, alloc_userspace_copy, tbl); 18664793d65dSAlexey Kardashevskiy if (ret) { 1867e5afdf9dSAlexey Kardashevskiy iommu_tce_table_put(tbl); 18684793d65dSAlexey Kardashevskiy return ret; 18694793d65dSAlexey Kardashevskiy } 18704793d65dSAlexey Kardashevskiy 18714793d65dSAlexey Kardashevskiy *ptbl = tbl; 18724793d65dSAlexey Kardashevskiy 18734793d65dSAlexey Kardashevskiy return 0; 18744793d65dSAlexey Kardashevskiy } 18754793d65dSAlexey Kardashevskiy 187646d3e1e1SAlexey Kardashevskiy static long pnv_pci_ioda2_setup_default_config(struct pnv_ioda_pe *pe) 187746d3e1e1SAlexey Kardashevskiy { 187846d3e1e1SAlexey Kardashevskiy struct iommu_table *tbl = NULL; 187946d3e1e1SAlexey Kardashevskiy long rc; 1880201ed7f3SAlexey Kardashevskiy unsigned long res_start, res_end; 188146d3e1e1SAlexey Kardashevskiy 1882bb005455SNishanth Aravamudan /* 1883fa144869SNishanth Aravamudan * crashkernel= specifies the kdump kernel's maximum memory at 1884fa144869SNishanth Aravamudan * some offset and there is no guaranteed the result is a power 1885fa144869SNishanth Aravamudan * of 2, which will cause errors later. 1886fa144869SNishanth Aravamudan */ 1887fa144869SNishanth Aravamudan const u64 max_memory = __rounddown_pow_of_two(memory_hotplug_max()); 1888fa144869SNishanth Aravamudan 1889fa144869SNishanth Aravamudan /* 1890bb005455SNishanth Aravamudan * In memory constrained environments, e.g. kdump kernel, the 1891bb005455SNishanth Aravamudan * DMA window can be larger than available memory, which will 1892bb005455SNishanth Aravamudan * cause errors later. 1893bb005455SNishanth Aravamudan */ 1894201ed7f3SAlexey Kardashevskiy const u64 maxblock = 1UL << (PAGE_SHIFT + MAX_ORDER - 1); 1895bb005455SNishanth Aravamudan 1896201ed7f3SAlexey Kardashevskiy /* 1897201ed7f3SAlexey Kardashevskiy * We create the default window as big as we can. The constraint is 1898201ed7f3SAlexey Kardashevskiy * the max order of allocation possible. The TCE table is likely to 1899201ed7f3SAlexey Kardashevskiy * end up being multilevel and with on-demand allocation in place, 1900201ed7f3SAlexey Kardashevskiy * the initial use is not going to be huge as the default window aims 1901201ed7f3SAlexey Kardashevskiy * to support crippled devices (i.e. not fully 64bit DMAble) only. 1902201ed7f3SAlexey Kardashevskiy */ 1903201ed7f3SAlexey Kardashevskiy /* iommu_table::it_map uses 1 bit per IOMMU page, hence 8 */ 1904201ed7f3SAlexey Kardashevskiy const u64 window_size = min((maxblock * 8) << PAGE_SHIFT, max_memory); 1905201ed7f3SAlexey Kardashevskiy /* Each TCE level cannot exceed maxblock so go multilevel if needed */ 1906201ed7f3SAlexey Kardashevskiy unsigned long tces_order = ilog2(window_size >> PAGE_SHIFT); 1907201ed7f3SAlexey Kardashevskiy unsigned long tcelevel_order = ilog2(maxblock >> 3); 1908201ed7f3SAlexey Kardashevskiy unsigned int levels = tces_order / tcelevel_order; 1909201ed7f3SAlexey Kardashevskiy 1910201ed7f3SAlexey Kardashevskiy if (tces_order % tcelevel_order) 1911201ed7f3SAlexey Kardashevskiy levels += 1; 1912201ed7f3SAlexey Kardashevskiy /* 1913201ed7f3SAlexey Kardashevskiy * We try to stick to default levels (which is >1 at the moment) in 1914201ed7f3SAlexey Kardashevskiy * order to save memory by relying on on-demain TCE level allocation. 1915201ed7f3SAlexey Kardashevskiy */ 1916201ed7f3SAlexey Kardashevskiy levels = max_t(unsigned int, levels, POWERNV_IOMMU_DEFAULT_LEVELS); 1917201ed7f3SAlexey Kardashevskiy 1918201ed7f3SAlexey Kardashevskiy rc = pnv_pci_ioda2_create_table(&pe->table_group, 0, PAGE_SHIFT, 1919201ed7f3SAlexey Kardashevskiy window_size, levels, false, &tbl); 192046d3e1e1SAlexey Kardashevskiy if (rc) { 192146d3e1e1SAlexey Kardashevskiy pe_err(pe, "Failed to create 32-bit TCE table, err %ld", 192246d3e1e1SAlexey Kardashevskiy rc); 192346d3e1e1SAlexey Kardashevskiy return rc; 192446d3e1e1SAlexey Kardashevskiy } 192546d3e1e1SAlexey Kardashevskiy 1926201ed7f3SAlexey Kardashevskiy /* We use top part of 32bit space for MMIO so exclude it from DMA */ 1927201ed7f3SAlexey Kardashevskiy res_start = 0; 1928201ed7f3SAlexey Kardashevskiy res_end = 0; 1929201ed7f3SAlexey Kardashevskiy if (window_size > pe->phb->ioda.m32_pci_base) { 1930201ed7f3SAlexey Kardashevskiy res_start = pe->phb->ioda.m32_pci_base >> tbl->it_page_shift; 1931201ed7f3SAlexey Kardashevskiy res_end = min(window_size, SZ_4G) >> tbl->it_page_shift; 1932201ed7f3SAlexey Kardashevskiy } 1933201ed7f3SAlexey Kardashevskiy iommu_init_table(tbl, pe->phb->hose->node, res_start, res_end); 193446d3e1e1SAlexey Kardashevskiy 193546d3e1e1SAlexey Kardashevskiy rc = pnv_pci_ioda2_set_window(&pe->table_group, 0, tbl); 193646d3e1e1SAlexey Kardashevskiy if (rc) { 193746d3e1e1SAlexey Kardashevskiy pe_err(pe, "Failed to configure 32-bit TCE table, err %ld\n", 193846d3e1e1SAlexey Kardashevskiy rc); 1939e5afdf9dSAlexey Kardashevskiy iommu_tce_table_put(tbl); 194046d3e1e1SAlexey Kardashevskiy return rc; 194146d3e1e1SAlexey Kardashevskiy } 194246d3e1e1SAlexey Kardashevskiy 194346d3e1e1SAlexey Kardashevskiy if (!pnv_iommu_bypass_disabled) 194446d3e1e1SAlexey Kardashevskiy pnv_pci_ioda2_set_bypass(pe, true); 194546d3e1e1SAlexey Kardashevskiy 19465636427dSAlexey Kardashevskiy /* 19475636427dSAlexey Kardashevskiy * Set table base for the case of IOMMU DMA use. Usually this is done 19485636427dSAlexey Kardashevskiy * from dma_dev_setup() which is not called when a device is returned 19495636427dSAlexey Kardashevskiy * from VFIO so do it here. 19505636427dSAlexey Kardashevskiy */ 19515636427dSAlexey Kardashevskiy if (pe->pdev) 19525636427dSAlexey Kardashevskiy set_iommu_table_base(&pe->pdev->dev, tbl); 19535636427dSAlexey Kardashevskiy 195446d3e1e1SAlexey Kardashevskiy return 0; 195546d3e1e1SAlexey Kardashevskiy } 195646d3e1e1SAlexey Kardashevskiy 1957b5926430SAlexey Kardashevskiy static long pnv_pci_ioda2_unset_window(struct iommu_table_group *table_group, 1958b5926430SAlexey Kardashevskiy int num) 1959b5926430SAlexey Kardashevskiy { 1960b5926430SAlexey Kardashevskiy struct pnv_ioda_pe *pe = container_of(table_group, struct pnv_ioda_pe, 1961b5926430SAlexey Kardashevskiy table_group); 1962b5926430SAlexey Kardashevskiy struct pnv_phb *phb = pe->phb; 1963b5926430SAlexey Kardashevskiy long ret; 1964b5926430SAlexey Kardashevskiy 1965b5926430SAlexey Kardashevskiy pe_info(pe, "Removing DMA window #%d\n", num); 1966b5926430SAlexey Kardashevskiy 1967b5926430SAlexey Kardashevskiy ret = opal_pci_map_pe_dma_window(phb->opal_id, pe->pe_number, 1968b5926430SAlexey Kardashevskiy (pe->pe_number << 1) + num, 1969b5926430SAlexey Kardashevskiy 0/* levels */, 0/* table address */, 1970b5926430SAlexey Kardashevskiy 0/* table size */, 0/* page size */); 1971b5926430SAlexey Kardashevskiy if (ret) 1972b5926430SAlexey Kardashevskiy pe_warn(pe, "Unmapping failed, ret = %ld\n", ret); 1973b5926430SAlexey Kardashevskiy else 1974ed7d9a1dSMichael Ellerman pnv_pci_ioda2_tce_invalidate_pe(pe); 1975b5926430SAlexey Kardashevskiy 1976b5926430SAlexey Kardashevskiy pnv_pci_unlink_table_and_group(table_group->tables[num], table_group); 1977b5926430SAlexey Kardashevskiy 1978b5926430SAlexey Kardashevskiy return ret; 1979b5926430SAlexey Kardashevskiy } 1980b5926430SAlexey Kardashevskiy 1981f87a8864SAlexey Kardashevskiy #ifdef CONFIG_IOMMU_API 19820bd97167SAlexey Kardashevskiy unsigned long pnv_pci_ioda2_get_table_size(__u32 page_shift, 198300547193SAlexey Kardashevskiy __u64 window_size, __u32 levels) 198400547193SAlexey Kardashevskiy { 198500547193SAlexey Kardashevskiy unsigned long bytes = 0; 198600547193SAlexey Kardashevskiy const unsigned window_shift = ilog2(window_size); 198700547193SAlexey Kardashevskiy unsigned entries_shift = window_shift - page_shift; 198800547193SAlexey Kardashevskiy unsigned table_shift = entries_shift + 3; 198900547193SAlexey Kardashevskiy unsigned long tce_table_size = max(0x1000UL, 1UL << table_shift); 199000547193SAlexey Kardashevskiy unsigned long direct_table_size; 199100547193SAlexey Kardashevskiy 199200547193SAlexey Kardashevskiy if (!levels || (levels > POWERNV_IOMMU_MAX_LEVELS) || 199300547193SAlexey Kardashevskiy !is_power_of_2(window_size)) 199400547193SAlexey Kardashevskiy return 0; 199500547193SAlexey Kardashevskiy 199600547193SAlexey Kardashevskiy /* Calculate a direct table size from window_size and levels */ 199700547193SAlexey Kardashevskiy entries_shift = (entries_shift + levels - 1) / levels; 199800547193SAlexey Kardashevskiy table_shift = entries_shift + 3; 199900547193SAlexey Kardashevskiy table_shift = max_t(unsigned, table_shift, PAGE_SHIFT); 200000547193SAlexey Kardashevskiy direct_table_size = 1UL << table_shift; 200100547193SAlexey Kardashevskiy 200200547193SAlexey Kardashevskiy for ( ; levels; --levels) { 2003b7115316SChristophe Leroy bytes += ALIGN(tce_table_size, direct_table_size); 200400547193SAlexey Kardashevskiy 200500547193SAlexey Kardashevskiy tce_table_size /= direct_table_size; 200600547193SAlexey Kardashevskiy tce_table_size <<= 3; 2007e49a6a21SAlexey Kardashevskiy tce_table_size = max_t(unsigned long, 2008e49a6a21SAlexey Kardashevskiy tce_table_size, direct_table_size); 200900547193SAlexey Kardashevskiy } 201000547193SAlexey Kardashevskiy 2011090bad39SAlexey Kardashevskiy return bytes + bytes; /* one for HW table, one for userspace copy */ 2012090bad39SAlexey Kardashevskiy } 2013090bad39SAlexey Kardashevskiy 2014090bad39SAlexey Kardashevskiy static long pnv_pci_ioda2_create_table_userspace( 2015090bad39SAlexey Kardashevskiy struct iommu_table_group *table_group, 2016090bad39SAlexey Kardashevskiy int num, __u32 page_shift, __u64 window_size, __u32 levels, 2017090bad39SAlexey Kardashevskiy struct iommu_table **ptbl) 2018090bad39SAlexey Kardashevskiy { 201911f5acceSAlexey Kardashevskiy long ret = pnv_pci_ioda2_create_table(table_group, 2020090bad39SAlexey Kardashevskiy num, page_shift, window_size, levels, true, ptbl); 202111f5acceSAlexey Kardashevskiy 202211f5acceSAlexey Kardashevskiy if (!ret) 202311f5acceSAlexey Kardashevskiy (*ptbl)->it_allocated_size = pnv_pci_ioda2_get_table_size( 202411f5acceSAlexey Kardashevskiy page_shift, window_size, levels); 202511f5acceSAlexey Kardashevskiy return ret; 202600547193SAlexey Kardashevskiy } 202700547193SAlexey Kardashevskiy 2028e3417faeSOliver O'Halloran static void pnv_ioda_setup_bus_dma(struct pnv_ioda_pe *pe, struct pci_bus *bus) 2029e3417faeSOliver O'Halloran { 2030e3417faeSOliver O'Halloran struct pci_dev *dev; 2031e3417faeSOliver O'Halloran 2032e3417faeSOliver O'Halloran list_for_each_entry(dev, &bus->devices, bus_list) { 2033e3417faeSOliver O'Halloran set_iommu_table_base(&dev->dev, pe->table_group.tables[0]); 2034e3417faeSOliver O'Halloran dev->dev.archdata.dma_offset = pe->tce_bypass_base; 2035e3417faeSOliver O'Halloran 2036e3417faeSOliver O'Halloran if ((pe->flags & PNV_IODA_PE_BUS_ALL) && dev->subordinate) 2037e3417faeSOliver O'Halloran pnv_ioda_setup_bus_dma(pe, dev->subordinate); 2038e3417faeSOliver O'Halloran } 2039e3417faeSOliver O'Halloran } 2040e3417faeSOliver O'Halloran 2041f87a8864SAlexey Kardashevskiy static void pnv_ioda2_take_ownership(struct iommu_table_group *table_group) 2042cd15b048SBenjamin Herrenschmidt { 2043f87a8864SAlexey Kardashevskiy struct pnv_ioda_pe *pe = container_of(table_group, struct pnv_ioda_pe, 2044f87a8864SAlexey Kardashevskiy table_group); 204546d3e1e1SAlexey Kardashevskiy /* Store @tbl as pnv_pci_ioda2_unset_window() resets it */ 204646d3e1e1SAlexey Kardashevskiy struct iommu_table *tbl = pe->table_group.tables[0]; 2047cd15b048SBenjamin Herrenschmidt 2048f87a8864SAlexey Kardashevskiy pnv_pci_ioda2_set_bypass(pe, false); 204946d3e1e1SAlexey Kardashevskiy pnv_pci_ioda2_unset_window(&pe->table_group, 0); 2050db08e1d5SAlexey Kardashevskiy if (pe->pbus) 20515eada8a3SAlexey Kardashevskiy pnv_ioda_setup_bus_dma(pe, pe->pbus); 20525636427dSAlexey Kardashevskiy else if (pe->pdev) 20535636427dSAlexey Kardashevskiy set_iommu_table_base(&pe->pdev->dev, NULL); 2054e5afdf9dSAlexey Kardashevskiy iommu_tce_table_put(tbl); 2055cd15b048SBenjamin Herrenschmidt } 2056cd15b048SBenjamin Herrenschmidt 2057f87a8864SAlexey Kardashevskiy static void pnv_ioda2_release_ownership(struct iommu_table_group *table_group) 2058f87a8864SAlexey Kardashevskiy { 2059f87a8864SAlexey Kardashevskiy struct pnv_ioda_pe *pe = container_of(table_group, struct pnv_ioda_pe, 2060f87a8864SAlexey Kardashevskiy table_group); 2061f87a8864SAlexey Kardashevskiy 206246d3e1e1SAlexey Kardashevskiy pnv_pci_ioda2_setup_default_config(pe); 2063db08e1d5SAlexey Kardashevskiy if (pe->pbus) 20645eada8a3SAlexey Kardashevskiy pnv_ioda_setup_bus_dma(pe, pe->pbus); 2065f87a8864SAlexey Kardashevskiy } 2066f87a8864SAlexey Kardashevskiy 2067f87a8864SAlexey Kardashevskiy static struct iommu_table_group_ops pnv_pci_ioda2_ops = { 206800547193SAlexey Kardashevskiy .get_table_size = pnv_pci_ioda2_get_table_size, 2069090bad39SAlexey Kardashevskiy .create_table = pnv_pci_ioda2_create_table_userspace, 20704793d65dSAlexey Kardashevskiy .set_window = pnv_pci_ioda2_set_window, 20714793d65dSAlexey Kardashevskiy .unset_window = pnv_pci_ioda2_unset_window, 2072f87a8864SAlexey Kardashevskiy .take_ownership = pnv_ioda2_take_ownership, 2073f87a8864SAlexey Kardashevskiy .release_ownership = pnv_ioda2_release_ownership, 2074f87a8864SAlexey Kardashevskiy }; 2075f87a8864SAlexey Kardashevskiy #endif 2076f87a8864SAlexey Kardashevskiy 207737b59ef0SOliver O'Halloran void pnv_pci_ioda2_setup_dma_pe(struct pnv_phb *phb, 2078373f5657SGavin Shan struct pnv_ioda_pe *pe) 2079373f5657SGavin Shan { 2080373f5657SGavin Shan int64_t rc; 2081373f5657SGavin Shan 2082f87a8864SAlexey Kardashevskiy /* TVE #1 is selected by PCI address bit 59 */ 2083f87a8864SAlexey Kardashevskiy pe->tce_bypass_base = 1ull << 59; 2084f87a8864SAlexey Kardashevskiy 2085373f5657SGavin Shan /* The PE will reserve all possible 32-bits space */ 2086373f5657SGavin Shan pe_info(pe, "Setting up 32-bit TCE table at 0..%08x\n", 2087aca6913fSAlexey Kardashevskiy phb->ioda.m32_pci_base); 2088373f5657SGavin Shan 2089e5aad1e6SAlexey Kardashevskiy /* Setup linux iommu table */ 20904793d65dSAlexey Kardashevskiy pe->table_group.tce32_start = 0; 20914793d65dSAlexey Kardashevskiy pe->table_group.tce32_size = phb->ioda.m32_pci_base; 20924793d65dSAlexey Kardashevskiy pe->table_group.max_dynamic_windows_supported = 20934793d65dSAlexey Kardashevskiy IOMMU_TABLE_GROUP_MAX_TABLES; 20944793d65dSAlexey Kardashevskiy pe->table_group.max_levels = POWERNV_IOMMU_MAX_LEVELS; 20957ef73cd3SAlexey Kardashevskiy pe->table_group.pgsizes = pnv_ioda_parse_tce_sizes(phb); 2096e5aad1e6SAlexey Kardashevskiy 209746d3e1e1SAlexey Kardashevskiy rc = pnv_pci_ioda2_setup_default_config(pe); 2098801846d1SGavin Shan if (rc) 209946d3e1e1SAlexey Kardashevskiy return; 210046d3e1e1SAlexey Kardashevskiy 21019b9408c5SOliver O'Halloran #ifdef CONFIG_IOMMU_API 21029b9408c5SOliver O'Halloran pe->table_group.ops = &pnv_pci_ioda2_ops; 21039b9408c5SOliver O'Halloran iommu_register_group(&pe->table_group, phb->hose->global_number, 21049b9408c5SOliver O'Halloran pe->pe_number); 21059b9408c5SOliver O'Halloran #endif 210601e12629SOliver O'Halloran pe->dma_setup_done = true; 2107373f5657SGavin Shan } 2108373f5657SGavin Shan 21094ee11c1aSSuresh Warrier int64_t pnv_opal_pci_msi_eoi(struct irq_chip *chip, unsigned int hw_irq) 2110137436c9SGavin Shan { 2111137436c9SGavin Shan struct pnv_phb *phb = container_of(chip, struct pnv_phb, 2112137436c9SGavin Shan ioda.irq_chip); 2113137436c9SGavin Shan 21144ee11c1aSSuresh Warrier return opal_pci_msi_eoi(phb->opal_id, hw_irq); 21154ee11c1aSSuresh Warrier } 21164ee11c1aSSuresh Warrier 21174ee11c1aSSuresh Warrier static void pnv_ioda2_msi_eoi(struct irq_data *d) 21184ee11c1aSSuresh Warrier { 21194ee11c1aSSuresh Warrier int64_t rc; 21204ee11c1aSSuresh Warrier unsigned int hw_irq = (unsigned int)irqd_to_hwirq(d); 21214ee11c1aSSuresh Warrier struct irq_chip *chip = irq_data_get_irq_chip(d); 21224ee11c1aSSuresh Warrier 21234ee11c1aSSuresh Warrier rc = pnv_opal_pci_msi_eoi(chip, hw_irq); 2124137436c9SGavin Shan WARN_ON_ONCE(rc); 2125137436c9SGavin Shan 2126137436c9SGavin Shan icp_native_eoi(d); 2127137436c9SGavin Shan } 2128137436c9SGavin Shan 2129fd9a1c26SIan Munsie 2130f456834aSIan Munsie void pnv_set_msi_irq_chip(struct pnv_phb *phb, unsigned int virq) 2131fd9a1c26SIan Munsie { 2132fd9a1c26SIan Munsie struct irq_data *idata; 2133fd9a1c26SIan Munsie struct irq_chip *ichip; 2134fd9a1c26SIan Munsie 2135fb111334SBenjamin Herrenschmidt /* The MSI EOI OPAL call is only needed on PHB3 */ 2136fb111334SBenjamin Herrenschmidt if (phb->model != PNV_PHB_MODEL_PHB3) 2137fd9a1c26SIan Munsie return; 2138fd9a1c26SIan Munsie 2139fd9a1c26SIan Munsie if (!phb->ioda.irq_chip_init) { 2140fd9a1c26SIan Munsie /* 2141fd9a1c26SIan Munsie * First time we setup an MSI IRQ, we need to setup the 2142fd9a1c26SIan Munsie * corresponding IRQ chip to route correctly. 2143fd9a1c26SIan Munsie */ 2144fd9a1c26SIan Munsie idata = irq_get_irq_data(virq); 2145fd9a1c26SIan Munsie ichip = irq_data_get_irq_chip(idata); 2146fd9a1c26SIan Munsie phb->ioda.irq_chip_init = 1; 2147fd9a1c26SIan Munsie phb->ioda.irq_chip = *ichip; 2148fd9a1c26SIan Munsie phb->ioda.irq_chip.irq_eoi = pnv_ioda2_msi_eoi; 2149fd9a1c26SIan Munsie } 2150fd9a1c26SIan Munsie irq_set_chip(virq, &phb->ioda.irq_chip); 2151fd9a1c26SIan Munsie } 2152fd9a1c26SIan Munsie 21534ee11c1aSSuresh Warrier /* 21544ee11c1aSSuresh Warrier * Returns true iff chip is something that we could call 21554ee11c1aSSuresh Warrier * pnv_opal_pci_msi_eoi for. 21564ee11c1aSSuresh Warrier */ 21574ee11c1aSSuresh Warrier bool is_pnv_opal_msi(struct irq_chip *chip) 21584ee11c1aSSuresh Warrier { 21594ee11c1aSSuresh Warrier return chip->irq_eoi == pnv_ioda2_msi_eoi; 21604ee11c1aSSuresh Warrier } 21614ee11c1aSSuresh Warrier EXPORT_SYMBOL_GPL(is_pnv_opal_msi); 21624ee11c1aSSuresh Warrier 2163184cd4a3SBenjamin Herrenschmidt static int pnv_pci_ioda_msi_setup(struct pnv_phb *phb, struct pci_dev *dev, 2164137436c9SGavin Shan unsigned int hwirq, unsigned int virq, 2165137436c9SGavin Shan unsigned int is_64, struct msi_msg *msg) 2166184cd4a3SBenjamin Herrenschmidt { 2167184cd4a3SBenjamin Herrenschmidt struct pnv_ioda_pe *pe = pnv_ioda_get_pe(dev); 2168184cd4a3SBenjamin Herrenschmidt unsigned int xive_num = hwirq - phb->msi_base; 21693a1a4661SBenjamin Herrenschmidt __be32 data; 2170184cd4a3SBenjamin Herrenschmidt int rc; 2171184cd4a3SBenjamin Herrenschmidt 2172184cd4a3SBenjamin Herrenschmidt /* No PE assigned ? bail out ... no MSI for you ! */ 2173184cd4a3SBenjamin Herrenschmidt if (pe == NULL) 2174184cd4a3SBenjamin Herrenschmidt return -ENXIO; 2175184cd4a3SBenjamin Herrenschmidt 2176184cd4a3SBenjamin Herrenschmidt /* Check if we have an MVE */ 2177184cd4a3SBenjamin Herrenschmidt if (pe->mve_number < 0) 2178184cd4a3SBenjamin Herrenschmidt return -ENXIO; 2179184cd4a3SBenjamin Herrenschmidt 2180b72c1f65SBenjamin Herrenschmidt /* Force 32-bit MSI on some broken devices */ 218136074381SBenjamin Herrenschmidt if (dev->no_64bit_msi) 2182b72c1f65SBenjamin Herrenschmidt is_64 = 0; 2183b72c1f65SBenjamin Herrenschmidt 2184184cd4a3SBenjamin Herrenschmidt /* Assign XIVE to PE */ 2185184cd4a3SBenjamin Herrenschmidt rc = opal_pci_set_xive_pe(phb->opal_id, pe->pe_number, xive_num); 2186184cd4a3SBenjamin Herrenschmidt if (rc) { 2187184cd4a3SBenjamin Herrenschmidt pr_warn("%s: OPAL error %d setting XIVE %d PE\n", 2188184cd4a3SBenjamin Herrenschmidt pci_name(dev), rc, xive_num); 2189184cd4a3SBenjamin Herrenschmidt return -EIO; 2190184cd4a3SBenjamin Herrenschmidt } 2191184cd4a3SBenjamin Herrenschmidt 2192184cd4a3SBenjamin Herrenschmidt if (is_64) { 21933a1a4661SBenjamin Herrenschmidt __be64 addr64; 21943a1a4661SBenjamin Herrenschmidt 2195184cd4a3SBenjamin Herrenschmidt rc = opal_get_msi_64(phb->opal_id, pe->mve_number, xive_num, 1, 2196184cd4a3SBenjamin Herrenschmidt &addr64, &data); 2197184cd4a3SBenjamin Herrenschmidt if (rc) { 2198184cd4a3SBenjamin Herrenschmidt pr_warn("%s: OPAL error %d getting 64-bit MSI data\n", 2199184cd4a3SBenjamin Herrenschmidt pci_name(dev), rc); 2200184cd4a3SBenjamin Herrenschmidt return -EIO; 2201184cd4a3SBenjamin Herrenschmidt } 22023a1a4661SBenjamin Herrenschmidt msg->address_hi = be64_to_cpu(addr64) >> 32; 22033a1a4661SBenjamin Herrenschmidt msg->address_lo = be64_to_cpu(addr64) & 0xfffffffful; 2204184cd4a3SBenjamin Herrenschmidt } else { 22053a1a4661SBenjamin Herrenschmidt __be32 addr32; 22063a1a4661SBenjamin Herrenschmidt 2207184cd4a3SBenjamin Herrenschmidt rc = opal_get_msi_32(phb->opal_id, pe->mve_number, xive_num, 1, 2208184cd4a3SBenjamin Herrenschmidt &addr32, &data); 2209184cd4a3SBenjamin Herrenschmidt if (rc) { 2210184cd4a3SBenjamin Herrenschmidt pr_warn("%s: OPAL error %d getting 32-bit MSI data\n", 2211184cd4a3SBenjamin Herrenschmidt pci_name(dev), rc); 2212184cd4a3SBenjamin Herrenschmidt return -EIO; 2213184cd4a3SBenjamin Herrenschmidt } 2214184cd4a3SBenjamin Herrenschmidt msg->address_hi = 0; 22153a1a4661SBenjamin Herrenschmidt msg->address_lo = be32_to_cpu(addr32); 2216184cd4a3SBenjamin Herrenschmidt } 22173a1a4661SBenjamin Herrenschmidt msg->data = be32_to_cpu(data); 2218184cd4a3SBenjamin Herrenschmidt 2219f456834aSIan Munsie pnv_set_msi_irq_chip(phb, virq); 2220137436c9SGavin Shan 2221184cd4a3SBenjamin Herrenschmidt pr_devel("%s: %s-bit MSI on hwirq %x (xive #%d)," 22221f52f176SRussell Currey " address=%x_%08x data=%x PE# %x\n", 2223184cd4a3SBenjamin Herrenschmidt pci_name(dev), is_64 ? "64" : "32", hwirq, xive_num, 2224184cd4a3SBenjamin Herrenschmidt msg->address_hi, msg->address_lo, data, pe->pe_number); 2225184cd4a3SBenjamin Herrenschmidt 2226184cd4a3SBenjamin Herrenschmidt return 0; 2227184cd4a3SBenjamin Herrenschmidt } 2228184cd4a3SBenjamin Herrenschmidt 2229184cd4a3SBenjamin Herrenschmidt static void pnv_pci_init_ioda_msis(struct pnv_phb *phb) 2230184cd4a3SBenjamin Herrenschmidt { 2231fb1b55d6SGavin Shan unsigned int count; 2232184cd4a3SBenjamin Herrenschmidt const __be32 *prop = of_get_property(phb->hose->dn, 2233184cd4a3SBenjamin Herrenschmidt "ibm,opal-msi-ranges", NULL); 2234184cd4a3SBenjamin Herrenschmidt if (!prop) { 2235184cd4a3SBenjamin Herrenschmidt /* BML Fallback */ 2236184cd4a3SBenjamin Herrenschmidt prop = of_get_property(phb->hose->dn, "msi-ranges", NULL); 2237184cd4a3SBenjamin Herrenschmidt } 2238184cd4a3SBenjamin Herrenschmidt if (!prop) 2239184cd4a3SBenjamin Herrenschmidt return; 2240184cd4a3SBenjamin Herrenschmidt 2241184cd4a3SBenjamin Herrenschmidt phb->msi_base = be32_to_cpup(prop); 2242fb1b55d6SGavin Shan count = be32_to_cpup(prop + 1); 2243fb1b55d6SGavin Shan if (msi_bitmap_alloc(&phb->msi_bmp, count, phb->hose->dn)) { 2244184cd4a3SBenjamin Herrenschmidt pr_err("PCI %d: Failed to allocate MSI bitmap !\n", 2245184cd4a3SBenjamin Herrenschmidt phb->hose->global_number); 2246184cd4a3SBenjamin Herrenschmidt return; 2247184cd4a3SBenjamin Herrenschmidt } 2248fb1b55d6SGavin Shan 2249184cd4a3SBenjamin Herrenschmidt phb->msi_setup = pnv_pci_ioda_msi_setup; 2250184cd4a3SBenjamin Herrenschmidt phb->msi32_support = 1; 2251184cd4a3SBenjamin Herrenschmidt pr_info(" Allocated bitmap for %d MSIs (base IRQ 0x%x)\n", 2252fb1b55d6SGavin Shan count, phb->msi_base); 2253184cd4a3SBenjamin Herrenschmidt } 2254184cd4a3SBenjamin Herrenschmidt 225523e79425SGavin Shan static void pnv_ioda_setup_pe_res(struct pnv_ioda_pe *pe, 225623e79425SGavin Shan struct resource *res) 225711685becSGavin Shan { 225823e79425SGavin Shan struct pnv_phb *phb = pe->phb; 225911685becSGavin Shan struct pci_bus_region region; 226023e79425SGavin Shan int index; 226123e79425SGavin Shan int64_t rc; 226211685becSGavin Shan 226323e79425SGavin Shan if (!res || !res->flags || res->start > res->end) 226423e79425SGavin Shan return; 226511685becSGavin Shan 226611685becSGavin Shan if (res->flags & IORESOURCE_IO) { 226711685becSGavin Shan region.start = res->start - phb->ioda.io_pci_base; 226811685becSGavin Shan region.end = res->end - phb->ioda.io_pci_base; 226911685becSGavin Shan index = region.start / phb->ioda.io_segsize; 227011685becSGavin Shan 227192b8f137SGavin Shan while (index < phb->ioda.total_pe_num && 227211685becSGavin Shan region.start <= region.end) { 227311685becSGavin Shan phb->ioda.io_segmap[index] = pe->pe_number; 227411685becSGavin Shan rc = opal_pci_map_pe_mmio_window(phb->opal_id, 227511685becSGavin Shan pe->pe_number, OPAL_IO_WINDOW_TYPE, 0, index); 227611685becSGavin Shan if (rc != OPAL_SUCCESS) { 22771f52f176SRussell Currey pr_err("%s: Error %lld mapping IO segment#%d to PE#%x\n", 227811685becSGavin Shan __func__, rc, index, pe->pe_number); 227911685becSGavin Shan break; 228011685becSGavin Shan } 228111685becSGavin Shan 228211685becSGavin Shan region.start += phb->ioda.io_segsize; 228311685becSGavin Shan index++; 228411685becSGavin Shan } 2285027fa02fSGavin Shan } else if ((res->flags & IORESOURCE_MEM) && 22865958d19aSBenjamin Herrenschmidt !pnv_pci_is_m64(phb, res)) { 228711685becSGavin Shan region.start = res->start - 228823e79425SGavin Shan phb->hose->mem_offset[0] - 228911685becSGavin Shan phb->ioda.m32_pci_base; 229011685becSGavin Shan region.end = res->end - 229123e79425SGavin Shan phb->hose->mem_offset[0] - 229211685becSGavin Shan phb->ioda.m32_pci_base; 229311685becSGavin Shan index = region.start / phb->ioda.m32_segsize; 229411685becSGavin Shan 229592b8f137SGavin Shan while (index < phb->ioda.total_pe_num && 229611685becSGavin Shan region.start <= region.end) { 229711685becSGavin Shan phb->ioda.m32_segmap[index] = pe->pe_number; 229811685becSGavin Shan rc = opal_pci_map_pe_mmio_window(phb->opal_id, 229911685becSGavin Shan pe->pe_number, OPAL_M32_WINDOW_TYPE, 0, index); 230011685becSGavin Shan if (rc != OPAL_SUCCESS) { 23011f52f176SRussell Currey pr_err("%s: Error %lld mapping M32 segment#%d to PE#%x", 230211685becSGavin Shan __func__, rc, index, pe->pe_number); 230311685becSGavin Shan break; 230411685becSGavin Shan } 230511685becSGavin Shan 230611685becSGavin Shan region.start += phb->ioda.m32_segsize; 230711685becSGavin Shan index++; 230811685becSGavin Shan } 230911685becSGavin Shan } 231011685becSGavin Shan } 231123e79425SGavin Shan 231223e79425SGavin Shan /* 231323e79425SGavin Shan * This function is supposed to be called on basis of PE from top 231423e79425SGavin Shan * to bottom style. So the the I/O or MMIO segment assigned to 231503671057SMasahiro Yamada * parent PE could be overridden by its child PEs if necessary. 231623e79425SGavin Shan */ 231723e79425SGavin Shan static void pnv_ioda_setup_pe_seg(struct pnv_ioda_pe *pe) 231823e79425SGavin Shan { 231969d733e7SGavin Shan struct pci_dev *pdev; 232023e79425SGavin Shan int i; 232123e79425SGavin Shan 232223e79425SGavin Shan /* 232323e79425SGavin Shan * NOTE: We only care PCI bus based PE for now. For PCI 232423e79425SGavin Shan * device based PE, for example SRIOV sensitive VF should 232523e79425SGavin Shan * be figured out later. 232623e79425SGavin Shan */ 232723e79425SGavin Shan BUG_ON(!(pe->flags & (PNV_IODA_PE_BUS | PNV_IODA_PE_BUS_ALL))); 232823e79425SGavin Shan 232969d733e7SGavin Shan list_for_each_entry(pdev, &pe->pbus->devices, bus_list) { 233069d733e7SGavin Shan for (i = 0; i <= PCI_ROM_RESOURCE; i++) 233169d733e7SGavin Shan pnv_ioda_setup_pe_res(pe, &pdev->resource[i]); 233269d733e7SGavin Shan 233369d733e7SGavin Shan /* 233469d733e7SGavin Shan * If the PE contains all subordinate PCI buses, the 233569d733e7SGavin Shan * windows of the child bridges should be mapped to 233669d733e7SGavin Shan * the PE as well. 233769d733e7SGavin Shan */ 233869d733e7SGavin Shan if (!(pe->flags & PNV_IODA_PE_BUS_ALL) || !pci_is_bridge(pdev)) 233969d733e7SGavin Shan continue; 234069d733e7SGavin Shan for (i = 0; i < PCI_BRIDGE_RESOURCE_NUM; i++) 234169d733e7SGavin Shan pnv_ioda_setup_pe_res(pe, 234269d733e7SGavin Shan &pdev->resource[PCI_BRIDGE_RESOURCES + i]); 234369d733e7SGavin Shan } 234411685becSGavin Shan } 234511685becSGavin Shan 234698b665daSRussell Currey #ifdef CONFIG_DEBUG_FS 234798b665daSRussell Currey static int pnv_pci_diag_data_set(void *data, u64 val) 234898b665daSRussell Currey { 234922ba7289SOliver O'Halloran struct pnv_phb *phb = data; 235098b665daSRussell Currey s64 ret; 235198b665daSRussell Currey 235298b665daSRussell Currey /* Retrieve the diag data from firmware */ 23535cb1f8fdSRussell Currey ret = opal_pci_get_phb_diag_data2(phb->opal_id, phb->diag_data, 23545cb1f8fdSRussell Currey phb->diag_data_size); 235598b665daSRussell Currey if (ret != OPAL_SUCCESS) 235698b665daSRussell Currey return -EIO; 235798b665daSRussell Currey 235898b665daSRussell Currey /* Print the diag data to the kernel log */ 23595cb1f8fdSRussell Currey pnv_pci_dump_phb_diag_data(phb->hose, phb->diag_data); 236098b665daSRussell Currey return 0; 236198b665daSRussell Currey } 236298b665daSRussell Currey 2363bfa2325eSYueHaibing DEFINE_DEBUGFS_ATTRIBUTE(pnv_pci_diag_data_fops, NULL, pnv_pci_diag_data_set, 2364bfa2325eSYueHaibing "%llu\n"); 236598b665daSRussell Currey 236618697d2bSOliver O'Halloran static int pnv_pci_ioda_pe_dump(void *data, u64 val) 236718697d2bSOliver O'Halloran { 236818697d2bSOliver O'Halloran struct pnv_phb *phb = data; 236918697d2bSOliver O'Halloran int pe_num; 237018697d2bSOliver O'Halloran 237118697d2bSOliver O'Halloran for (pe_num = 0; pe_num < phb->ioda.total_pe_num; pe_num++) { 237218697d2bSOliver O'Halloran struct pnv_ioda_pe *pe = &phb->ioda.pe_array[pe_num]; 237318697d2bSOliver O'Halloran 237418697d2bSOliver O'Halloran if (!test_bit(pe_num, phb->ioda.pe_alloc)) 237518697d2bSOliver O'Halloran continue; 237618697d2bSOliver O'Halloran 237718697d2bSOliver O'Halloran pe_warn(pe, "rid: %04x dev count: %2d flags: %s%s%s%s%s%s\n", 237818697d2bSOliver O'Halloran pe->rid, pe->device_count, 237918697d2bSOliver O'Halloran (pe->flags & PNV_IODA_PE_DEV) ? "dev " : "", 238018697d2bSOliver O'Halloran (pe->flags & PNV_IODA_PE_BUS) ? "bus " : "", 238118697d2bSOliver O'Halloran (pe->flags & PNV_IODA_PE_BUS_ALL) ? "all " : "", 238218697d2bSOliver O'Halloran (pe->flags & PNV_IODA_PE_MASTER) ? "master " : "", 238318697d2bSOliver O'Halloran (pe->flags & PNV_IODA_PE_SLAVE) ? "slave " : "", 238418697d2bSOliver O'Halloran (pe->flags & PNV_IODA_PE_VF) ? "vf " : ""); 238518697d2bSOliver O'Halloran } 238618697d2bSOliver O'Halloran 238718697d2bSOliver O'Halloran return 0; 238818697d2bSOliver O'Halloran } 238918697d2bSOliver O'Halloran 239018697d2bSOliver O'Halloran DEFINE_DEBUGFS_ATTRIBUTE(pnv_pci_ioda_pe_dump_fops, NULL, 239118697d2bSOliver O'Halloran pnv_pci_ioda_pe_dump, "%llu\n"); 239218697d2bSOliver O'Halloran 239398b665daSRussell Currey #endif /* CONFIG_DEBUG_FS */ 239498b665daSRussell Currey 239537c367f2SGavin Shan static void pnv_pci_ioda_create_dbgfs(void) 239637c367f2SGavin Shan { 239737c367f2SGavin Shan #ifdef CONFIG_DEBUG_FS 239837c367f2SGavin Shan struct pci_controller *hose, *tmp; 239937c367f2SGavin Shan struct pnv_phb *phb; 240037c367f2SGavin Shan char name[16]; 240137c367f2SGavin Shan 240237c367f2SGavin Shan list_for_each_entry_safe(hose, tmp, &hose_list, list_node) { 240337c367f2SGavin Shan phb = hose->private_data; 240437c367f2SGavin Shan 240537c367f2SGavin Shan sprintf(name, "PCI%04x", hose->global_number); 240637c367f2SGavin Shan phb->dbgfs = debugfs_create_dir(name, powerpc_debugfs_root); 240798b665daSRussell Currey 2408bfa2325eSYueHaibing debugfs_create_file_unsafe("dump_diag_regs", 0200, phb->dbgfs, 240922ba7289SOliver O'Halloran phb, &pnv_pci_diag_data_fops); 241018697d2bSOliver O'Halloran debugfs_create_file_unsafe("dump_ioda_pe_state", 0200, phb->dbgfs, 241118697d2bSOliver O'Halloran phb, &pnv_pci_ioda_pe_dump_fops); 241237c367f2SGavin Shan } 241337c367f2SGavin Shan #endif /* CONFIG_DEBUG_FS */ 241437c367f2SGavin Shan } 241537c367f2SGavin Shan 2416db217319SBenjamin Herrenschmidt static void pnv_pci_enable_bridge(struct pci_bus *bus) 2417db217319SBenjamin Herrenschmidt { 2418db217319SBenjamin Herrenschmidt struct pci_dev *dev = bus->self; 2419db217319SBenjamin Herrenschmidt struct pci_bus *child; 2420db217319SBenjamin Herrenschmidt 2421db217319SBenjamin Herrenschmidt /* Empty bus ? bail */ 2422db217319SBenjamin Herrenschmidt if (list_empty(&bus->devices)) 2423db217319SBenjamin Herrenschmidt return; 2424db217319SBenjamin Herrenschmidt 2425db217319SBenjamin Herrenschmidt /* 2426db217319SBenjamin Herrenschmidt * If there's a bridge associated with that bus enable it. This works 2427db217319SBenjamin Herrenschmidt * around races in the generic code if the enabling is done during 2428db217319SBenjamin Herrenschmidt * parallel probing. This can be removed once those races have been 2429db217319SBenjamin Herrenschmidt * fixed. 2430db217319SBenjamin Herrenschmidt */ 2431db217319SBenjamin Herrenschmidt if (dev) { 2432db217319SBenjamin Herrenschmidt int rc = pci_enable_device(dev); 2433db217319SBenjamin Herrenschmidt if (rc) 2434db217319SBenjamin Herrenschmidt pci_err(dev, "Error enabling bridge (%d)\n", rc); 2435db217319SBenjamin Herrenschmidt pci_set_master(dev); 2436db217319SBenjamin Herrenschmidt } 2437db217319SBenjamin Herrenschmidt 2438db217319SBenjamin Herrenschmidt /* Perform the same to child busses */ 2439db217319SBenjamin Herrenschmidt list_for_each_entry(child, &bus->children, node) 2440db217319SBenjamin Herrenschmidt pnv_pci_enable_bridge(child); 2441db217319SBenjamin Herrenschmidt } 2442db217319SBenjamin Herrenschmidt 2443db217319SBenjamin Herrenschmidt static void pnv_pci_enable_bridges(void) 2444db217319SBenjamin Herrenschmidt { 2445db217319SBenjamin Herrenschmidt struct pci_controller *hose; 2446db217319SBenjamin Herrenschmidt 2447db217319SBenjamin Herrenschmidt list_for_each_entry(hose, &hose_list, list_node) 2448db217319SBenjamin Herrenschmidt pnv_pci_enable_bridge(hose->bus); 2449db217319SBenjamin Herrenschmidt } 2450db217319SBenjamin Herrenschmidt 2451cad5cef6SGreg Kroah-Hartman static void pnv_pci_ioda_fixup(void) 2452fb446ad0SGavin Shan { 245303b7bf34SOliver O'Halloran pnv_pci_ioda_setup_nvlink(); 245437c367f2SGavin Shan pnv_pci_ioda_create_dbgfs(); 245537c367f2SGavin Shan 2456db217319SBenjamin Herrenschmidt pnv_pci_enable_bridges(); 2457db217319SBenjamin Herrenschmidt 2458e9cc17d4SGavin Shan #ifdef CONFIG_EEH 2459b9fde58dSBenjamin Herrenschmidt pnv_eeh_post_init(); 2460e9cc17d4SGavin Shan #endif 2461fb446ad0SGavin Shan } 2462fb446ad0SGavin Shan 2463271fd03aSGavin Shan /* 2464271fd03aSGavin Shan * Returns the alignment for I/O or memory windows for P2P 2465271fd03aSGavin Shan * bridges. That actually depends on how PEs are segmented. 2466271fd03aSGavin Shan * For now, we return I/O or M32 segment size for PE sensitive 2467271fd03aSGavin Shan * P2P bridges. Otherwise, the default values (4KiB for I/O, 2468271fd03aSGavin Shan * 1MiB for memory) will be returned. 2469271fd03aSGavin Shan * 2470271fd03aSGavin Shan * The current PCI bus might be put into one PE, which was 2471271fd03aSGavin Shan * create against the parent PCI bridge. For that case, we 2472271fd03aSGavin Shan * needn't enlarge the alignment so that we can save some 2473271fd03aSGavin Shan * resources. 2474271fd03aSGavin Shan */ 2475271fd03aSGavin Shan static resource_size_t pnv_pci_window_alignment(struct pci_bus *bus, 2476271fd03aSGavin Shan unsigned long type) 2477271fd03aSGavin Shan { 24785609ffddSOliver O'Halloran struct pnv_phb *phb = pci_bus_to_pnvhb(bus); 2479271fd03aSGavin Shan int num_pci_bridges = 0; 24805609ffddSOliver O'Halloran struct pci_dev *bridge; 2481271fd03aSGavin Shan 2482271fd03aSGavin Shan bridge = bus->self; 2483271fd03aSGavin Shan while (bridge) { 2484271fd03aSGavin Shan if (pci_pcie_type(bridge) == PCI_EXP_TYPE_PCI_BRIDGE) { 2485271fd03aSGavin Shan num_pci_bridges++; 2486271fd03aSGavin Shan if (num_pci_bridges >= 2) 2487271fd03aSGavin Shan return 1; 2488271fd03aSGavin Shan } 2489271fd03aSGavin Shan 2490271fd03aSGavin Shan bridge = bridge->bus->self; 2491271fd03aSGavin Shan } 2492271fd03aSGavin Shan 24935958d19aSBenjamin Herrenschmidt /* 24945958d19aSBenjamin Herrenschmidt * We fall back to M32 if M64 isn't supported. We enforce the M64 24955958d19aSBenjamin Herrenschmidt * alignment for any 64-bit resource, PCIe doesn't care and 24965958d19aSBenjamin Herrenschmidt * bridges only do 64-bit prefetchable anyway. 24975958d19aSBenjamin Herrenschmidt */ 2498b79331a5SRussell Currey if (phb->ioda.m64_segsize && pnv_pci_is_m64_flags(type)) 2499262af557SGuo Chao return phb->ioda.m64_segsize; 2500271fd03aSGavin Shan if (type & IORESOURCE_MEM) 2501271fd03aSGavin Shan return phb->ioda.m32_segsize; 2502271fd03aSGavin Shan 2503271fd03aSGavin Shan return phb->ioda.io_segsize; 2504271fd03aSGavin Shan } 2505271fd03aSGavin Shan 250640e2a47eSGavin Shan /* 250740e2a47eSGavin Shan * We are updating root port or the upstream port of the 250840e2a47eSGavin Shan * bridge behind the root port with PHB's windows in order 250940e2a47eSGavin Shan * to accommodate the changes on required resources during 251040e2a47eSGavin Shan * PCI (slot) hotplug, which is connected to either root 251140e2a47eSGavin Shan * port or the downstream ports of PCIe switch behind the 251240e2a47eSGavin Shan * root port. 251340e2a47eSGavin Shan */ 251440e2a47eSGavin Shan static void pnv_pci_fixup_bridge_resources(struct pci_bus *bus, 251540e2a47eSGavin Shan unsigned long type) 251640e2a47eSGavin Shan { 251740e2a47eSGavin Shan struct pci_controller *hose = pci_bus_to_host(bus); 251840e2a47eSGavin Shan struct pnv_phb *phb = hose->private_data; 251940e2a47eSGavin Shan struct pci_dev *bridge = bus->self; 252040e2a47eSGavin Shan struct resource *r, *w; 252140e2a47eSGavin Shan bool msi_region = false; 252240e2a47eSGavin Shan int i; 252340e2a47eSGavin Shan 252440e2a47eSGavin Shan /* Check if we need apply fixup to the bridge's windows */ 252540e2a47eSGavin Shan if (!pci_is_root_bus(bridge->bus) && 252640e2a47eSGavin Shan !pci_is_root_bus(bridge->bus->self->bus)) 252740e2a47eSGavin Shan return; 252840e2a47eSGavin Shan 252940e2a47eSGavin Shan /* Fixup the resources */ 253040e2a47eSGavin Shan for (i = 0; i < PCI_BRIDGE_RESOURCE_NUM; i++) { 253140e2a47eSGavin Shan r = &bridge->resource[PCI_BRIDGE_RESOURCES + i]; 253240e2a47eSGavin Shan if (!r->flags || !r->parent) 253340e2a47eSGavin Shan continue; 253440e2a47eSGavin Shan 253540e2a47eSGavin Shan w = NULL; 253640e2a47eSGavin Shan if (r->flags & type & IORESOURCE_IO) 253740e2a47eSGavin Shan w = &hose->io_resource; 25385958d19aSBenjamin Herrenschmidt else if (pnv_pci_is_m64(phb, r) && 253940e2a47eSGavin Shan (type & IORESOURCE_PREFETCH) && 254040e2a47eSGavin Shan phb->ioda.m64_segsize) 254140e2a47eSGavin Shan w = &hose->mem_resources[1]; 254240e2a47eSGavin Shan else if (r->flags & type & IORESOURCE_MEM) { 254340e2a47eSGavin Shan w = &hose->mem_resources[0]; 254440e2a47eSGavin Shan msi_region = true; 254540e2a47eSGavin Shan } 254640e2a47eSGavin Shan 254740e2a47eSGavin Shan r->start = w->start; 254840e2a47eSGavin Shan r->end = w->end; 254940e2a47eSGavin Shan 255040e2a47eSGavin Shan /* The 64KB 32-bits MSI region shouldn't be included in 255140e2a47eSGavin Shan * the 32-bits bridge window. Otherwise, we can see strange 255240e2a47eSGavin Shan * issues. One of them is EEH error observed on Garrison. 255340e2a47eSGavin Shan * 255440e2a47eSGavin Shan * Exclude top 1MB region which is the minimal alignment of 255540e2a47eSGavin Shan * 32-bits bridge window. 255640e2a47eSGavin Shan */ 255740e2a47eSGavin Shan if (msi_region) { 255840e2a47eSGavin Shan r->end += 0x10000; 255940e2a47eSGavin Shan r->end -= 0x100000; 256040e2a47eSGavin Shan } 256140e2a47eSGavin Shan } 256240e2a47eSGavin Shan } 256340e2a47eSGavin Shan 2564dc3d8f85SOliver O'Halloran static void pnv_pci_configure_bus(struct pci_bus *bus) 2565ccd1c191SGavin Shan { 2566ccd1c191SGavin Shan struct pci_dev *bridge = bus->self; 2567ccd1c191SGavin Shan struct pnv_ioda_pe *pe; 2568dc3d8f85SOliver O'Halloran bool all = (bridge && pci_pcie_type(bridge) == PCI_EXP_TYPE_PCI_BRIDGE); 2569ccd1c191SGavin Shan 2570dc3d8f85SOliver O'Halloran dev_info(&bus->dev, "Configuring PE for bus\n"); 257140e2a47eSGavin Shan 2572ccd1c191SGavin Shan /* Don't assign PE to PCI bus, which doesn't have subordinate devices */ 25736ae8aedfSOliver O'Halloran if (WARN_ON(list_empty(&bus->devices))) 2574ccd1c191SGavin Shan return; 2575ccd1c191SGavin Shan 2576ccd1c191SGavin Shan /* Reserve PEs according to used M64 resources */ 2577a25de7afSAlexey Kardashevskiy pnv_ioda_reserve_m64_pe(bus, NULL, all); 2578ccd1c191SGavin Shan 2579ccd1c191SGavin Shan /* 2580ccd1c191SGavin Shan * Assign PE. We might run here because of partial hotplug. 2581ccd1c191SGavin Shan * For the case, we just pick up the existing PE and should 2582ccd1c191SGavin Shan * not allocate resources again. 2583ccd1c191SGavin Shan */ 2584ccd1c191SGavin Shan pe = pnv_ioda_setup_bus_PE(bus, all); 2585ccd1c191SGavin Shan if (!pe) 2586ccd1c191SGavin Shan return; 2587ccd1c191SGavin Shan 2588ccd1c191SGavin Shan pnv_ioda_setup_pe_seg(pe); 2589ccd1c191SGavin Shan } 2590ccd1c191SGavin Shan 259138274637SYongji Xie static resource_size_t pnv_pci_default_alignment(void) 259238274637SYongji Xie { 259338274637SYongji Xie return PAGE_SIZE; 259438274637SYongji Xie } 259538274637SYongji Xie 2596184cd4a3SBenjamin Herrenschmidt /* Prevent enabling devices for which we couldn't properly 2597184cd4a3SBenjamin Herrenschmidt * assign a PE 2598184cd4a3SBenjamin Herrenschmidt */ 25998bf6b91aSAlastair D'Silva static bool pnv_pci_enable_device_hook(struct pci_dev *dev) 2600184cd4a3SBenjamin Herrenschmidt { 2601db1266c8SGavin Shan struct pci_dn *pdn; 2602184cd4a3SBenjamin Herrenschmidt 2603b72c1f65SBenjamin Herrenschmidt pdn = pci_get_pdn(dev); 26046c58b1b4SOliver O'Halloran if (!pdn || pdn->pe_number == IODA_INVALID_PE) { 26056c58b1b4SOliver O'Halloran pci_err(dev, "pci_enable_device() blocked, no PE assigned.\n"); 2606c88c2a18SDaniel Axtens return false; 26076c58b1b4SOliver O'Halloran } 2608db1266c8SGavin Shan 2609c88c2a18SDaniel Axtens return true; 2610184cd4a3SBenjamin Herrenschmidt } 2611184cd4a3SBenjamin Herrenschmidt 2612c1a2feadSFrederic Barrat static bool pnv_ocapi_enable_device_hook(struct pci_dev *dev) 2613c1a2feadSFrederic Barrat { 2614c1a2feadSFrederic Barrat struct pci_dn *pdn; 2615c1a2feadSFrederic Barrat struct pnv_ioda_pe *pe; 2616c1a2feadSFrederic Barrat 2617c1a2feadSFrederic Barrat pdn = pci_get_pdn(dev); 2618c1a2feadSFrederic Barrat if (!pdn) 2619c1a2feadSFrederic Barrat return false; 2620c1a2feadSFrederic Barrat 2621c1a2feadSFrederic Barrat if (pdn->pe_number == IODA_INVALID_PE) { 2622c1a2feadSFrederic Barrat pe = pnv_ioda_setup_dev_PE(dev); 2623c1a2feadSFrederic Barrat if (!pe) 2624c1a2feadSFrederic Barrat return false; 2625c1a2feadSFrederic Barrat } 2626c1a2feadSFrederic Barrat return true; 2627c1a2feadSFrederic Barrat } 2628c1a2feadSFrederic Barrat 2629c5f7700bSGavin Shan static long pnv_pci_ioda1_unset_window(struct iommu_table_group *table_group, 2630c5f7700bSGavin Shan int num) 2631c5f7700bSGavin Shan { 2632c5f7700bSGavin Shan struct pnv_ioda_pe *pe = container_of(table_group, 2633c5f7700bSGavin Shan struct pnv_ioda_pe, table_group); 2634c5f7700bSGavin Shan struct pnv_phb *phb = pe->phb; 2635c5f7700bSGavin Shan unsigned int idx; 2636c5f7700bSGavin Shan long rc; 2637c5f7700bSGavin Shan 2638c5f7700bSGavin Shan pe_info(pe, "Removing DMA window #%d\n", num); 2639c5f7700bSGavin Shan for (idx = 0; idx < phb->ioda.dma32_count; idx++) { 2640c5f7700bSGavin Shan if (phb->ioda.dma32_segmap[idx] != pe->pe_number) 2641c5f7700bSGavin Shan continue; 2642c5f7700bSGavin Shan 2643c5f7700bSGavin Shan rc = opal_pci_map_pe_dma_window(phb->opal_id, pe->pe_number, 2644c5f7700bSGavin Shan idx, 0, 0ul, 0ul, 0ul); 2645c5f7700bSGavin Shan if (rc != OPAL_SUCCESS) { 2646c5f7700bSGavin Shan pe_warn(pe, "Failure %ld unmapping DMA32 segment#%d\n", 2647c5f7700bSGavin Shan rc, idx); 2648c5f7700bSGavin Shan return rc; 2649c5f7700bSGavin Shan } 2650c5f7700bSGavin Shan 2651c5f7700bSGavin Shan phb->ioda.dma32_segmap[idx] = IODA_INVALID_PE; 2652c5f7700bSGavin Shan } 2653c5f7700bSGavin Shan 2654c5f7700bSGavin Shan pnv_pci_unlink_table_and_group(table_group->tables[num], table_group); 2655c5f7700bSGavin Shan return OPAL_SUCCESS; 2656c5f7700bSGavin Shan } 2657c5f7700bSGavin Shan 2658c5f7700bSGavin Shan static void pnv_pci_ioda1_release_pe_dma(struct pnv_ioda_pe *pe) 2659c5f7700bSGavin Shan { 2660c5f7700bSGavin Shan struct iommu_table *tbl = pe->table_group.tables[0]; 2661c5f7700bSGavin Shan int64_t rc; 2662c5f7700bSGavin Shan 266301e12629SOliver O'Halloran if (!pe->dma_setup_done) 2664c5f7700bSGavin Shan return; 2665c5f7700bSGavin Shan 2666c5f7700bSGavin Shan rc = pnv_pci_ioda1_unset_window(&pe->table_group, 0); 2667c5f7700bSGavin Shan if (rc != OPAL_SUCCESS) 2668c5f7700bSGavin Shan return; 2669c5f7700bSGavin Shan 2670a34ab7c3SBenjamin Herrenschmidt pnv_pci_p7ioc_tce_invalidate(tbl, tbl->it_offset, tbl->it_size, false); 2671c5f7700bSGavin Shan if (pe->table_group.group) { 2672c5f7700bSGavin Shan iommu_group_put(pe->table_group.group); 2673c5f7700bSGavin Shan WARN_ON(pe->table_group.group); 2674c5f7700bSGavin Shan } 2675c5f7700bSGavin Shan 2676c5f7700bSGavin Shan free_pages(tbl->it_base, get_order(tbl->it_size << 3)); 2677e5afdf9dSAlexey Kardashevskiy iommu_tce_table_put(tbl); 2678c5f7700bSGavin Shan } 2679c5f7700bSGavin Shan 268037b59ef0SOliver O'Halloran void pnv_pci_ioda2_release_pe_dma(struct pnv_ioda_pe *pe) 2681c5f7700bSGavin Shan { 2682c5f7700bSGavin Shan struct iommu_table *tbl = pe->table_group.tables[0]; 2683c5f7700bSGavin Shan int64_t rc; 2684c5f7700bSGavin Shan 2685e17a7c0eSFrederic Barrat if (!pe->dma_setup_done) 2686c5f7700bSGavin Shan return; 2687c5f7700bSGavin Shan 2688c5f7700bSGavin Shan rc = pnv_pci_ioda2_unset_window(&pe->table_group, 0); 2689c5f7700bSGavin Shan if (rc) 26901e496391SJoe Perches pe_warn(pe, "OPAL error %lld release DMA window\n", rc); 2691c5f7700bSGavin Shan 2692c5f7700bSGavin Shan pnv_pci_ioda2_set_bypass(pe, false); 2693c5f7700bSGavin Shan if (pe->table_group.group) { 2694c5f7700bSGavin Shan iommu_group_put(pe->table_group.group); 2695c5f7700bSGavin Shan WARN_ON(pe->table_group.group); 2696c5f7700bSGavin Shan } 2697c5f7700bSGavin Shan 2698e5afdf9dSAlexey Kardashevskiy iommu_tce_table_put(tbl); 2699c5f7700bSGavin Shan } 2700c5f7700bSGavin Shan 2701c5f7700bSGavin Shan static void pnv_ioda_free_pe_seg(struct pnv_ioda_pe *pe, 2702c5f7700bSGavin Shan unsigned short win, 2703c5f7700bSGavin Shan unsigned int *map) 2704c5f7700bSGavin Shan { 2705c5f7700bSGavin Shan struct pnv_phb *phb = pe->phb; 2706c5f7700bSGavin Shan int idx; 2707c5f7700bSGavin Shan int64_t rc; 2708c5f7700bSGavin Shan 2709c5f7700bSGavin Shan for (idx = 0; idx < phb->ioda.total_pe_num; idx++) { 2710c5f7700bSGavin Shan if (map[idx] != pe->pe_number) 2711c5f7700bSGavin Shan continue; 2712c5f7700bSGavin Shan 2713c5f7700bSGavin Shan rc = opal_pci_map_pe_mmio_window(phb->opal_id, 2714c5f7700bSGavin Shan phb->ioda.reserved_pe_idx, win, 0, idx); 2715c5f7700bSGavin Shan 2716c5f7700bSGavin Shan if (rc != OPAL_SUCCESS) 27171e496391SJoe Perches pe_warn(pe, "Error %lld unmapping (%d) segment#%d\n", 2718c5f7700bSGavin Shan rc, win, idx); 2719c5f7700bSGavin Shan 2720c5f7700bSGavin Shan map[idx] = IODA_INVALID_PE; 2721c5f7700bSGavin Shan } 2722c5f7700bSGavin Shan } 2723c5f7700bSGavin Shan 2724c5f7700bSGavin Shan static void pnv_ioda_release_pe_seg(struct pnv_ioda_pe *pe) 2725c5f7700bSGavin Shan { 2726c5f7700bSGavin Shan struct pnv_phb *phb = pe->phb; 2727c5f7700bSGavin Shan 2728c5f7700bSGavin Shan if (phb->type == PNV_PHB_IODA1) { 2729c5f7700bSGavin Shan pnv_ioda_free_pe_seg(pe, OPAL_IO_WINDOW_TYPE, 2730c5f7700bSGavin Shan phb->ioda.io_segmap); 2731c5f7700bSGavin Shan pnv_ioda_free_pe_seg(pe, OPAL_M32_WINDOW_TYPE, 2732c5f7700bSGavin Shan phb->ioda.m32_segmap); 273336963365SOliver O'Halloran /* M64 is pre-configured by pnv_ioda1_init_m64() */ 2734c5f7700bSGavin Shan } else if (phb->type == PNV_PHB_IODA2) { 2735c5f7700bSGavin Shan pnv_ioda_free_pe_seg(pe, OPAL_M32_WINDOW_TYPE, 2736c5f7700bSGavin Shan phb->ioda.m32_segmap); 2737c5f7700bSGavin Shan } 2738c5f7700bSGavin Shan } 2739c5f7700bSGavin Shan 2740c5f7700bSGavin Shan static void pnv_ioda_release_pe(struct pnv_ioda_pe *pe) 2741c5f7700bSGavin Shan { 2742c5f7700bSGavin Shan struct pnv_phb *phb = pe->phb; 2743c5f7700bSGavin Shan struct pnv_ioda_pe *slave, *tmp; 2744c5f7700bSGavin Shan 2745e5500ab6SOliver O'Halloran pe_info(pe, "Releasing PE\n"); 2746e5500ab6SOliver O'Halloran 274780f1ff83SFrederic Barrat mutex_lock(&phb->ioda.pe_list_mutex); 2748c5f7700bSGavin Shan list_del(&pe->list); 274980f1ff83SFrederic Barrat mutex_unlock(&phb->ioda.pe_list_mutex); 275080f1ff83SFrederic Barrat 2751c5f7700bSGavin Shan switch (phb->type) { 2752c5f7700bSGavin Shan case PNV_PHB_IODA1: 2753c5f7700bSGavin Shan pnv_pci_ioda1_release_pe_dma(pe); 2754c5f7700bSGavin Shan break; 2755c5f7700bSGavin Shan case PNV_PHB_IODA2: 2756c5f7700bSGavin Shan pnv_pci_ioda2_release_pe_dma(pe); 2757c5f7700bSGavin Shan break; 2758f724385fSFrederic Barrat case PNV_PHB_NPU_OCAPI: 2759f724385fSFrederic Barrat break; 2760c5f7700bSGavin Shan default: 2761c5f7700bSGavin Shan WARN_ON(1); 2762c5f7700bSGavin Shan } 2763c5f7700bSGavin Shan 2764c5f7700bSGavin Shan pnv_ioda_release_pe_seg(pe); 2765c5f7700bSGavin Shan pnv_ioda_deconfigure_pe(pe->phb, pe); 2766b314427aSGavin Shan 2767b314427aSGavin Shan /* Release slave PEs in the compound PE */ 2768b314427aSGavin Shan if (pe->flags & PNV_IODA_PE_MASTER) { 2769b314427aSGavin Shan list_for_each_entry_safe(slave, tmp, &pe->slaves, list) { 2770b314427aSGavin Shan list_del(&slave->list); 2771b314427aSGavin Shan pnv_ioda_free_pe(slave); 2772b314427aSGavin Shan } 2773b314427aSGavin Shan } 2774b314427aSGavin Shan 27756eaed166SGavin Shan /* 27766eaed166SGavin Shan * The PE for root bus can be removed because of hotplug in EEH 27776eaed166SGavin Shan * recovery for fenced PHB error. We need to mark the PE dead so 27786eaed166SGavin Shan * that it can be populated again in PCI hot add path. The PE 27796eaed166SGavin Shan * shouldn't be destroyed as it's the global reserved resource. 27806eaed166SGavin Shan */ 2781718d249aSOliver O'Halloran if (phb->ioda.root_pe_idx == pe->pe_number) 2782718d249aSOliver O'Halloran return; 2783718d249aSOliver O'Halloran 2784c5f7700bSGavin Shan pnv_ioda_free_pe(pe); 2785c5f7700bSGavin Shan } 2786c5f7700bSGavin Shan 2787c5f7700bSGavin Shan static void pnv_pci_release_device(struct pci_dev *pdev) 2788c5f7700bSGavin Shan { 27895609ffddSOliver O'Halloran struct pnv_phb *phb = pci_bus_to_pnvhb(pdev->bus); 2790c5f7700bSGavin Shan struct pci_dn *pdn = pci_get_pdn(pdev); 2791c5f7700bSGavin Shan struct pnv_ioda_pe *pe; 2792c5f7700bSGavin Shan 279337b59ef0SOliver O'Halloran /* The VF PE state is torn down when sriov_disable() is called */ 2794c5f7700bSGavin Shan if (pdev->is_virtfn) 2795c5f7700bSGavin Shan return; 2796c5f7700bSGavin Shan 2797c5f7700bSGavin Shan if (!pdn || pdn->pe_number == IODA_INVALID_PE) 2798c5f7700bSGavin Shan return; 2799c5f7700bSGavin Shan 280037b59ef0SOliver O'Halloran #ifdef CONFIG_PCI_IOV 280137b59ef0SOliver O'Halloran /* 280237b59ef0SOliver O'Halloran * FIXME: Try move this to sriov_disable(). It's here since we allocate 280337b59ef0SOliver O'Halloran * the iov state at probe time since we need to fiddle with the IOV 280437b59ef0SOliver O'Halloran * resources. 280537b59ef0SOliver O'Halloran */ 280637b59ef0SOliver O'Halloran if (pdev->is_physfn) 280737b59ef0SOliver O'Halloran kfree(pdev->dev.archdata.iov_data); 280837b59ef0SOliver O'Halloran #endif 280937b59ef0SOliver O'Halloran 281029bf282dSGavin Shan /* 281129bf282dSGavin Shan * PCI hotplug can happen as part of EEH error recovery. The @pdn 281229bf282dSGavin Shan * isn't removed and added afterwards in this scenario. We should 281329bf282dSGavin Shan * set the PE number in @pdn to an invalid one. Otherwise, the PE's 281429bf282dSGavin Shan * device count is decreased on removing devices while failing to 281529bf282dSGavin Shan * be increased on adding devices. It leads to unbalanced PE's device 281629bf282dSGavin Shan * count and eventually make normal PCI hotplug path broken. 281729bf282dSGavin Shan */ 2818c5f7700bSGavin Shan pe = &phb->ioda.pe_array[pdn->pe_number]; 281929bf282dSGavin Shan pdn->pe_number = IODA_INVALID_PE; 282029bf282dSGavin Shan 2821c5f7700bSGavin Shan WARN_ON(--pe->device_count < 0); 2822c5f7700bSGavin Shan if (pe->device_count == 0) 2823c5f7700bSGavin Shan pnv_ioda_release_pe(pe); 2824c5f7700bSGavin Shan } 2825c5f7700bSGavin Shan 2826ab7032e7SAlexey Kardashevskiy static void pnv_npu_disable_device(struct pci_dev *pdev) 2827ab7032e7SAlexey Kardashevskiy { 2828ab7032e7SAlexey Kardashevskiy struct eeh_dev *edev = pci_dev_to_eeh_dev(pdev); 2829ab7032e7SAlexey Kardashevskiy struct eeh_pe *eehpe = edev ? edev->pe : NULL; 2830ab7032e7SAlexey Kardashevskiy 2831ab7032e7SAlexey Kardashevskiy if (eehpe && eeh_ops && eeh_ops->reset) 2832ab7032e7SAlexey Kardashevskiy eeh_ops->reset(eehpe, EEH_RESET_HOT); 2833ab7032e7SAlexey Kardashevskiy } 2834ab7032e7SAlexey Kardashevskiy 28357a8e6bbfSMichael Neuling static void pnv_pci_ioda_shutdown(struct pci_controller *hose) 283673ed148aSBenjamin Herrenschmidt { 28377a8e6bbfSMichael Neuling struct pnv_phb *phb = hose->private_data; 28387a8e6bbfSMichael Neuling 2839d1a85eeeSGavin Shan opal_pci_reset(phb->opal_id, OPAL_RESET_PCI_IODA_TABLE, 284073ed148aSBenjamin Herrenschmidt OPAL_ASSERT_RESET); 284173ed148aSBenjamin Herrenschmidt } 284273ed148aSBenjamin Herrenschmidt 2843946743d0SOliver O'Halloran static void pnv_pci_ioda_dma_bus_setup(struct pci_bus *bus) 2844946743d0SOliver O'Halloran { 28455609ffddSOliver O'Halloran struct pnv_phb *phb = pci_bus_to_pnvhb(bus); 2846946743d0SOliver O'Halloran struct pnv_ioda_pe *pe; 2847946743d0SOliver O'Halloran 2848946743d0SOliver O'Halloran list_for_each_entry(pe, &phb->ioda.pe_list, list) { 2849946743d0SOliver O'Halloran if (!(pe->flags & (PNV_IODA_PE_BUS | PNV_IODA_PE_BUS_ALL))) 2850946743d0SOliver O'Halloran continue; 2851946743d0SOliver O'Halloran 2852946743d0SOliver O'Halloran if (!pe->pbus) 2853946743d0SOliver O'Halloran continue; 2854946743d0SOliver O'Halloran 2855946743d0SOliver O'Halloran if (bus->number == ((pe->rid >> 8) & 0xFF)) { 2856946743d0SOliver O'Halloran pe->pbus = bus; 2857946743d0SOliver O'Halloran break; 2858946743d0SOliver O'Halloran } 2859946743d0SOliver O'Halloran } 2860946743d0SOliver O'Halloran } 2861946743d0SOliver O'Halloran 286292ae0353SDaniel Axtens static const struct pci_controller_ops pnv_pci_ioda_controller_ops = { 28630a25d9c4SOliver O'Halloran .dma_dev_setup = pnv_pci_ioda_dma_dev_setup, 2864946743d0SOliver O'Halloran .dma_bus_setup = pnv_pci_ioda_dma_bus_setup, 28652d6ad41bSChristoph Hellwig .iommu_bypass_supported = pnv_pci_ioda_iommu_bypass_supported, 286692ae0353SDaniel Axtens .setup_msi_irqs = pnv_setup_msi_irqs, 286792ae0353SDaniel Axtens .teardown_msi_irqs = pnv_teardown_msi_irqs, 286892ae0353SDaniel Axtens .enable_device_hook = pnv_pci_enable_device_hook, 2869c5f7700bSGavin Shan .release_device = pnv_pci_release_device, 287092ae0353SDaniel Axtens .window_alignment = pnv_pci_window_alignment, 2871dc3d8f85SOliver O'Halloran .setup_bridge = pnv_pci_fixup_bridge_resources, 287292ae0353SDaniel Axtens .reset_secondary_bus = pnv_pci_reset_secondary_bus, 28737a8e6bbfSMichael Neuling .shutdown = pnv_pci_ioda_shutdown, 287492ae0353SDaniel Axtens }; 287592ae0353SDaniel Axtens 28765d2aa710SAlistair Popple static const struct pci_controller_ops pnv_npu_ioda_controller_ops = { 28775d2aa710SAlistair Popple .setup_msi_irqs = pnv_setup_msi_irqs, 28785d2aa710SAlistair Popple .teardown_msi_irqs = pnv_teardown_msi_irqs, 28795d2aa710SAlistair Popple .enable_device_hook = pnv_pci_enable_device_hook, 28805d2aa710SAlistair Popple .window_alignment = pnv_pci_window_alignment, 28815d2aa710SAlistair Popple .reset_secondary_bus = pnv_pci_reset_secondary_bus, 28825d2aa710SAlistair Popple .shutdown = pnv_pci_ioda_shutdown, 2883ab7032e7SAlexey Kardashevskiy .disable_device = pnv_npu_disable_device, 28845d2aa710SAlistair Popple }; 28855d2aa710SAlistair Popple 28867f2c39e9SFrederic Barrat static const struct pci_controller_ops pnv_npu_ocapi_ioda_controller_ops = { 2887c1a2feadSFrederic Barrat .enable_device_hook = pnv_ocapi_enable_device_hook, 2888f724385fSFrederic Barrat .release_device = pnv_pci_release_device, 28897f2c39e9SFrederic Barrat .window_alignment = pnv_pci_window_alignment, 28907f2c39e9SFrederic Barrat .reset_secondary_bus = pnv_pci_reset_secondary_bus, 28917f2c39e9SFrederic Barrat .shutdown = pnv_pci_ioda_shutdown, 28927f2c39e9SFrederic Barrat }; 28937f2c39e9SFrederic Barrat 2894e51df2c1SAnton Blanchard static void __init pnv_pci_init_ioda_phb(struct device_node *np, 2895e9cc17d4SGavin Shan u64 hub_id, int ioda_type) 2896184cd4a3SBenjamin Herrenschmidt { 2897184cd4a3SBenjamin Herrenschmidt struct pci_controller *hose; 2898184cd4a3SBenjamin Herrenschmidt struct pnv_phb *phb; 28992b923ed1SGavin Shan unsigned long size, m64map_off, m32map_off, pemap_off; 29002b923ed1SGavin Shan unsigned long iomap_off = 0, dma32map_off = 0; 2901718d249aSOliver O'Halloran struct pnv_ioda_pe *root_pe; 2902fd141d1aSBenjamin Herrenschmidt struct resource r; 2903c681b93cSAlistair Popple const __be64 *prop64; 29043a1a4661SBenjamin Herrenschmidt const __be32 *prop32; 2905f1b7cc3eSGavin Shan int len; 29063fa23ff8SGavin Shan unsigned int segno; 2907184cd4a3SBenjamin Herrenschmidt u64 phb_id; 2908184cd4a3SBenjamin Herrenschmidt void *aux; 2909184cd4a3SBenjamin Herrenschmidt long rc; 2910184cd4a3SBenjamin Herrenschmidt 291108a45b32SBenjamin Herrenschmidt if (!of_device_is_available(np)) 291208a45b32SBenjamin Herrenschmidt return; 291308a45b32SBenjamin Herrenschmidt 2914b7c670d6SRob Herring pr_info("Initializing %s PHB (%pOF)\n", pnv_phb_names[ioda_type], np); 2915184cd4a3SBenjamin Herrenschmidt 2916184cd4a3SBenjamin Herrenschmidt prop64 = of_get_property(np, "ibm,opal-phbid", NULL); 2917184cd4a3SBenjamin Herrenschmidt if (!prop64) { 2918184cd4a3SBenjamin Herrenschmidt pr_err(" Missing \"ibm,opal-phbid\" property !\n"); 2919184cd4a3SBenjamin Herrenschmidt return; 2920184cd4a3SBenjamin Herrenschmidt } 2921184cd4a3SBenjamin Herrenschmidt phb_id = be64_to_cpup(prop64); 2922184cd4a3SBenjamin Herrenschmidt pr_debug(" PHB-ID : 0x%016llx\n", phb_id); 2923184cd4a3SBenjamin Herrenschmidt 2924*dea6f4c6SMichael Ellerman phb = kzalloc(sizeof(*phb), GFP_KERNEL); 29258a7f97b9SMike Rapoport if (!phb) 29268a7f97b9SMike Rapoport panic("%s: Failed to allocate %zu bytes\n", __func__, 29278a7f97b9SMike Rapoport sizeof(*phb)); 292858d714ecSGavin Shan 292958d714ecSGavin Shan /* Allocate PCI controller */ 2930184cd4a3SBenjamin Herrenschmidt phb->hose = hose = pcibios_alloc_controller(np); 293158d714ecSGavin Shan if (!phb->hose) { 2932b7c670d6SRob Herring pr_err(" Can't allocate PCI controller for %pOF\n", 2933b7c670d6SRob Herring np); 2934e39f223fSMichael Ellerman memblock_free(__pa(phb), sizeof(struct pnv_phb)); 2935184cd4a3SBenjamin Herrenschmidt return; 2936184cd4a3SBenjamin Herrenschmidt } 2937184cd4a3SBenjamin Herrenschmidt 2938184cd4a3SBenjamin Herrenschmidt spin_lock_init(&phb->lock); 2939f1b7cc3eSGavin Shan prop32 = of_get_property(np, "bus-range", &len); 2940f1b7cc3eSGavin Shan if (prop32 && len == 8) { 29413a1a4661SBenjamin Herrenschmidt hose->first_busno = be32_to_cpu(prop32[0]); 29423a1a4661SBenjamin Herrenschmidt hose->last_busno = be32_to_cpu(prop32[1]); 2943f1b7cc3eSGavin Shan } else { 2944b7c670d6SRob Herring pr_warn(" Broken <bus-range> on %pOF\n", np); 2945184cd4a3SBenjamin Herrenschmidt hose->first_busno = 0; 2946184cd4a3SBenjamin Herrenschmidt hose->last_busno = 0xff; 2947f1b7cc3eSGavin Shan } 2948184cd4a3SBenjamin Herrenschmidt hose->private_data = phb; 2949e9cc17d4SGavin Shan phb->hub_id = hub_id; 2950184cd4a3SBenjamin Herrenschmidt phb->opal_id = phb_id; 2951aa0c033fSGavin Shan phb->type = ioda_type; 2952781a868fSWei Yang mutex_init(&phb->ioda.pe_alloc_mutex); 2953184cd4a3SBenjamin Herrenschmidt 2954cee72d5bSBenjamin Herrenschmidt /* Detect specific models for error handling */ 2955cee72d5bSBenjamin Herrenschmidt if (of_device_is_compatible(np, "ibm,p7ioc-pciex")) 2956cee72d5bSBenjamin Herrenschmidt phb->model = PNV_PHB_MODEL_P7IOC; 2957f3d40c25SBenjamin Herrenschmidt else if (of_device_is_compatible(np, "ibm,power8-pciex")) 2958aa0c033fSGavin Shan phb->model = PNV_PHB_MODEL_PHB3; 29595d2aa710SAlistair Popple else if (of_device_is_compatible(np, "ibm,power8-npu-pciex")) 29605d2aa710SAlistair Popple phb->model = PNV_PHB_MODEL_NPU; 2961616badd2SAlistair Popple else if (of_device_is_compatible(np, "ibm,power9-npu-pciex")) 2962616badd2SAlistair Popple phb->model = PNV_PHB_MODEL_NPU2; 2963cee72d5bSBenjamin Herrenschmidt else 2964cee72d5bSBenjamin Herrenschmidt phb->model = PNV_PHB_MODEL_UNKNOWN; 2965cee72d5bSBenjamin Herrenschmidt 29665cb1f8fdSRussell Currey /* Initialize diagnostic data buffer */ 29675cb1f8fdSRussell Currey prop32 = of_get_property(np, "ibm,phb-diag-data-size", NULL); 29685cb1f8fdSRussell Currey if (prop32) 29695cb1f8fdSRussell Currey phb->diag_data_size = be32_to_cpup(prop32); 29705cb1f8fdSRussell Currey else 29715cb1f8fdSRussell Currey phb->diag_data_size = PNV_PCI_DIAG_BUF_SIZE; 29725cb1f8fdSRussell Currey 2973*dea6f4c6SMichael Ellerman phb->diag_data = kzalloc(phb->diag_data_size, GFP_KERNEL); 29748a7f97b9SMike Rapoport if (!phb->diag_data) 29758a7f97b9SMike Rapoport panic("%s: Failed to allocate %u bytes\n", __func__, 29768a7f97b9SMike Rapoport phb->diag_data_size); 29775cb1f8fdSRussell Currey 2978aa0c033fSGavin Shan /* Parse 32-bit and IO ranges (if any) */ 29792f1ec02eSGavin Shan pci_process_bridge_OF_ranges(hose, np, !hose->global_number); 2980184cd4a3SBenjamin Herrenschmidt 2981aa0c033fSGavin Shan /* Get registers */ 2982fd141d1aSBenjamin Herrenschmidt if (!of_address_to_resource(np, 0, &r)) { 2983fd141d1aSBenjamin Herrenschmidt phb->regs_phys = r.start; 2984fd141d1aSBenjamin Herrenschmidt phb->regs = ioremap(r.start, resource_size(&r)); 2985184cd4a3SBenjamin Herrenschmidt if (phb->regs == NULL) 2986184cd4a3SBenjamin Herrenschmidt pr_err(" Failed to map registers !\n"); 2987fd141d1aSBenjamin Herrenschmidt } 2988577c8c88SGavin Shan 2989184cd4a3SBenjamin Herrenschmidt /* Initialize more IODA stuff */ 299092b8f137SGavin Shan phb->ioda.total_pe_num = 1; 299136954dc7SGavin Shan prop32 = of_get_property(np, "ibm,opal-num-pes", NULL); 299236954dc7SGavin Shan if (prop32) 299392b8f137SGavin Shan phb->ioda.total_pe_num = be32_to_cpup(prop32); 299436954dc7SGavin Shan prop32 = of_get_property(np, "ibm,opal-reserved-pe", NULL); 299536954dc7SGavin Shan if (prop32) 299692b8f137SGavin Shan phb->ioda.reserved_pe_idx = be32_to_cpup(prop32); 2997262af557SGuo Chao 2998c127562aSGavin Shan /* Invalidate RID to PE# mapping */ 2999c127562aSGavin Shan for (segno = 0; segno < ARRAY_SIZE(phb->ioda.pe_rmap); segno++) 3000c127562aSGavin Shan phb->ioda.pe_rmap[segno] = IODA_INVALID_PE; 3001c127562aSGavin Shan 3002262af557SGuo Chao /* Parse 64-bit MMIO range */ 3003262af557SGuo Chao pnv_ioda_parse_m64_window(phb); 3004262af557SGuo Chao 3005184cd4a3SBenjamin Herrenschmidt phb->ioda.m32_size = resource_size(&hose->mem_resources[0]); 3006aa0c033fSGavin Shan /* FW Has already off top 64k of M32 space (MSI space) */ 3007184cd4a3SBenjamin Herrenschmidt phb->ioda.m32_size += 0x10000; 3008184cd4a3SBenjamin Herrenschmidt 300992b8f137SGavin Shan phb->ioda.m32_segsize = phb->ioda.m32_size / phb->ioda.total_pe_num; 30103fd47f06SBenjamin Herrenschmidt phb->ioda.m32_pci_base = hose->mem_resources[0].start - hose->mem_offset[0]; 3011184cd4a3SBenjamin Herrenschmidt phb->ioda.io_size = hose->pci_io_size; 301292b8f137SGavin Shan phb->ioda.io_segsize = phb->ioda.io_size / phb->ioda.total_pe_num; 3013184cd4a3SBenjamin Herrenschmidt phb->ioda.io_pci_base = 0; /* XXX calculate this ? */ 3014184cd4a3SBenjamin Herrenschmidt 30152b923ed1SGavin Shan /* Calculate how many 32-bit TCE segments we have */ 30162b923ed1SGavin Shan phb->ioda.dma32_count = phb->ioda.m32_pci_base / 30172b923ed1SGavin Shan PNV_IODA1_DMA32_SEGSIZE; 30182b923ed1SGavin Shan 3019c35d2a8cSGavin Shan /* Allocate aux data & arrays. We don't have IO ports on PHB3 */ 3020b7115316SChristophe Leroy size = ALIGN(max_t(unsigned, phb->ioda.total_pe_num, 8) / 8, 302192a86756SAlexey Kardashevskiy sizeof(unsigned long)); 302293289d8cSGavin Shan m64map_off = size; 302393289d8cSGavin Shan size += phb->ioda.total_pe_num * sizeof(phb->ioda.m64_segmap[0]); 3024184cd4a3SBenjamin Herrenschmidt m32map_off = size; 302592b8f137SGavin Shan size += phb->ioda.total_pe_num * sizeof(phb->ioda.m32_segmap[0]); 3026c35d2a8cSGavin Shan if (phb->type == PNV_PHB_IODA1) { 3027c35d2a8cSGavin Shan iomap_off = size; 302892b8f137SGavin Shan size += phb->ioda.total_pe_num * sizeof(phb->ioda.io_segmap[0]); 30292b923ed1SGavin Shan dma32map_off = size; 30302b923ed1SGavin Shan size += phb->ioda.dma32_count * 30312b923ed1SGavin Shan sizeof(phb->ioda.dma32_segmap[0]); 3032c35d2a8cSGavin Shan } 3033184cd4a3SBenjamin Herrenschmidt pemap_off = size; 303492b8f137SGavin Shan size += phb->ioda.total_pe_num * sizeof(struct pnv_ioda_pe); 3035*dea6f4c6SMichael Ellerman aux = kzalloc(size, GFP_KERNEL); 30368a7f97b9SMike Rapoport if (!aux) 30378a7f97b9SMike Rapoport panic("%s: Failed to allocate %lu bytes\n", __func__, size); 3038fbbefb32SOliver O'Halloran 3039184cd4a3SBenjamin Herrenschmidt phb->ioda.pe_alloc = aux; 304093289d8cSGavin Shan phb->ioda.m64_segmap = aux + m64map_off; 3041184cd4a3SBenjamin Herrenschmidt phb->ioda.m32_segmap = aux + m32map_off; 304293289d8cSGavin Shan for (segno = 0; segno < phb->ioda.total_pe_num; segno++) { 304393289d8cSGavin Shan phb->ioda.m64_segmap[segno] = IODA_INVALID_PE; 30443fa23ff8SGavin Shan phb->ioda.m32_segmap[segno] = IODA_INVALID_PE; 304593289d8cSGavin Shan } 30463fa23ff8SGavin Shan if (phb->type == PNV_PHB_IODA1) { 3047184cd4a3SBenjamin Herrenschmidt phb->ioda.io_segmap = aux + iomap_off; 30483fa23ff8SGavin Shan for (segno = 0; segno < phb->ioda.total_pe_num; segno++) 30493fa23ff8SGavin Shan phb->ioda.io_segmap[segno] = IODA_INVALID_PE; 30502b923ed1SGavin Shan 30512b923ed1SGavin Shan phb->ioda.dma32_segmap = aux + dma32map_off; 30522b923ed1SGavin Shan for (segno = 0; segno < phb->ioda.dma32_count; segno++) 30532b923ed1SGavin Shan phb->ioda.dma32_segmap[segno] = IODA_INVALID_PE; 30543fa23ff8SGavin Shan } 3055184cd4a3SBenjamin Herrenschmidt phb->ioda.pe_array = aux + pemap_off; 305663803c39SGavin Shan 305763803c39SGavin Shan /* 305863803c39SGavin Shan * Choose PE number for root bus, which shouldn't have 305963803c39SGavin Shan * M64 resources consumed by its child devices. To pick 306063803c39SGavin Shan * the PE number adjacent to the reserved one if possible. 306163803c39SGavin Shan */ 306263803c39SGavin Shan pnv_ioda_reserve_pe(phb, phb->ioda.reserved_pe_idx); 306363803c39SGavin Shan if (phb->ioda.reserved_pe_idx == 0) { 306463803c39SGavin Shan phb->ioda.root_pe_idx = 1; 306563803c39SGavin Shan pnv_ioda_reserve_pe(phb, phb->ioda.root_pe_idx); 306663803c39SGavin Shan } else if (phb->ioda.reserved_pe_idx == (phb->ioda.total_pe_num - 1)) { 306763803c39SGavin Shan phb->ioda.root_pe_idx = phb->ioda.reserved_pe_idx - 1; 306863803c39SGavin Shan pnv_ioda_reserve_pe(phb, phb->ioda.root_pe_idx); 306963803c39SGavin Shan } else { 3070718d249aSOliver O'Halloran /* otherwise just allocate one */ 3071a4bc676eSOliver O'Halloran root_pe = pnv_ioda_alloc_pe(phb, 1); 3072718d249aSOliver O'Halloran phb->ioda.root_pe_idx = root_pe->pe_number; 307363803c39SGavin Shan } 3074184cd4a3SBenjamin Herrenschmidt 3075184cd4a3SBenjamin Herrenschmidt INIT_LIST_HEAD(&phb->ioda.pe_list); 3076781a868fSWei Yang mutex_init(&phb->ioda.pe_list_mutex); 3077184cd4a3SBenjamin Herrenschmidt 3078184cd4a3SBenjamin Herrenschmidt /* Calculate how many 32-bit TCE segments we have */ 30792b923ed1SGavin Shan phb->ioda.dma32_count = phb->ioda.m32_pci_base / 3080acce971cSGavin Shan PNV_IODA1_DMA32_SEGSIZE; 3081184cd4a3SBenjamin Herrenschmidt 3082aa0c033fSGavin Shan #if 0 /* We should really do that ... */ 3083184cd4a3SBenjamin Herrenschmidt rc = opal_pci_set_phb_mem_window(opal->phb_id, 3084184cd4a3SBenjamin Herrenschmidt window_type, 3085184cd4a3SBenjamin Herrenschmidt window_num, 3086184cd4a3SBenjamin Herrenschmidt starting_real_address, 3087184cd4a3SBenjamin Herrenschmidt starting_pci_address, 3088184cd4a3SBenjamin Herrenschmidt segment_size); 3089184cd4a3SBenjamin Herrenschmidt #endif 3090184cd4a3SBenjamin Herrenschmidt 3091262af557SGuo Chao pr_info(" %03d (%03d) PE's M32: 0x%x [segment=0x%x]\n", 309292b8f137SGavin Shan phb->ioda.total_pe_num, phb->ioda.reserved_pe_idx, 3093262af557SGuo Chao phb->ioda.m32_size, phb->ioda.m32_segsize); 3094262af557SGuo Chao if (phb->ioda.m64_size) 3095262af557SGuo Chao pr_info(" M64: 0x%lx [segment=0x%lx]\n", 3096262af557SGuo Chao phb->ioda.m64_size, phb->ioda.m64_segsize); 3097262af557SGuo Chao if (phb->ioda.io_size) 3098262af557SGuo Chao pr_info(" IO: 0x%x [segment=0x%x]\n", 3099184cd4a3SBenjamin Herrenschmidt phb->ioda.io_size, phb->ioda.io_segsize); 3100184cd4a3SBenjamin Herrenschmidt 3101262af557SGuo Chao 3102184cd4a3SBenjamin Herrenschmidt phb->hose->ops = &pnv_pci_ops; 310349dec922SGavin Shan phb->get_pe_state = pnv_ioda_get_pe_state; 310449dec922SGavin Shan phb->freeze_pe = pnv_ioda_freeze_pe; 310549dec922SGavin Shan phb->unfreeze_pe = pnv_ioda_unfreeze_pe; 3106184cd4a3SBenjamin Herrenschmidt 3107184cd4a3SBenjamin Herrenschmidt /* Setup MSI support */ 3108184cd4a3SBenjamin Herrenschmidt pnv_pci_init_ioda_msis(phb); 3109184cd4a3SBenjamin Herrenschmidt 3110c40a4210SGavin Shan /* 3111c40a4210SGavin Shan * We pass the PCI probe flag PCI_REASSIGN_ALL_RSRC here 3112c40a4210SGavin Shan * to let the PCI core do resource assignment. It's supposed 3113c40a4210SGavin Shan * that the PCI core will do correct I/O and MMIO alignment 3114c40a4210SGavin Shan * for the P2P bridge bars so that each PCI bus (excluding 3115c40a4210SGavin Shan * the child P2P bridges) can form individual PE. 3116184cd4a3SBenjamin Herrenschmidt */ 3117fb446ad0SGavin Shan ppc_md.pcibios_fixup = pnv_pci_ioda_fixup; 31185d2aa710SAlistair Popple 31197f2c39e9SFrederic Barrat switch (phb->type) { 31207f2c39e9SFrederic Barrat case PNV_PHB_NPU_NVLINK: 31215d2aa710SAlistair Popple hose->controller_ops = pnv_npu_ioda_controller_ops; 31227f2c39e9SFrederic Barrat break; 31237f2c39e9SFrederic Barrat case PNV_PHB_NPU_OCAPI: 31247f2c39e9SFrederic Barrat hose->controller_ops = pnv_npu_ocapi_ioda_controller_ops; 31257f2c39e9SFrederic Barrat break; 31267f2c39e9SFrederic Barrat default: 312792ae0353SDaniel Axtens hose->controller_ops = pnv_pci_ioda_controller_ops; 3128f9f83456SAlexey Kardashevskiy } 3129ad30cb99SMichael Ellerman 313038274637SYongji Xie ppc_md.pcibios_default_alignment = pnv_pci_default_alignment; 313138274637SYongji Xie 31326e628c7dSWei Yang #ifdef CONFIG_PCI_IOV 3133965c94f3SOliver O'Halloran ppc_md.pcibios_fixup_sriov = pnv_pci_ioda_fixup_iov; 31345350ab3fSWei Yang ppc_md.pcibios_iov_resource_alignment = pnv_pci_iov_resource_alignment; 3135988fc3baSBryant G. Ly ppc_md.pcibios_sriov_enable = pnv_pcibios_sriov_enable; 3136988fc3baSBryant G. Ly ppc_md.pcibios_sriov_disable = pnv_pcibios_sriov_disable; 3137ad30cb99SMichael Ellerman #endif 3138ad30cb99SMichael Ellerman 3139c40a4210SGavin Shan pci_add_flags(PCI_REASSIGN_ALL_RSRC); 3140184cd4a3SBenjamin Herrenschmidt 3141184cd4a3SBenjamin Herrenschmidt /* Reset IODA tables to a clean state */ 3142d1a85eeeSGavin Shan rc = opal_pci_reset(phb_id, OPAL_RESET_PCI_IODA_TABLE, OPAL_ASSERT_RESET); 3143184cd4a3SBenjamin Herrenschmidt if (rc) 3144f2c2cbccSJoe Perches pr_warn(" OPAL Error %ld performing IODA table reset !\n", rc); 3145361f2a2aSGavin Shan 31466060e9eaSAndrew Donnellan /* 31476060e9eaSAndrew Donnellan * If we're running in kdump kernel, the previous kernel never 3148361f2a2aSGavin Shan * shutdown PCI devices correctly. We already got IODA table 3149361f2a2aSGavin Shan * cleaned out. So we have to issue PHB reset to stop all PCI 315045baee14SGuilherme G. Piccoli * transactions from previous kernel. The ppc_pci_reset_phbs 3151b174b4fbSOliver O'Halloran * kernel parameter will force this reset too. Additionally, 3152b174b4fbSOliver O'Halloran * if the IODA reset above failed then use a bigger hammer. 3153b174b4fbSOliver O'Halloran * This can happen if we get a PHB fatal error in very early 3154b174b4fbSOliver O'Halloran * boot. 3155361f2a2aSGavin Shan */ 3156b174b4fbSOliver O'Halloran if (is_kdump_kernel() || pci_reset_phbs || rc) { 3157361f2a2aSGavin Shan pr_info(" Issue PHB reset ...\n"); 3158cadf364dSGavin Shan pnv_eeh_phb_reset(hose, EEH_RESET_FUNDAMENTAL); 3159cadf364dSGavin Shan pnv_eeh_phb_reset(hose, EEH_RESET_DEACTIVATE); 3160361f2a2aSGavin Shan } 3161262af557SGuo Chao 31629e9e8935SGavin Shan /* Remove M64 resource if we can't configure it successfully */ 31639e9e8935SGavin Shan if (!phb->init_m64 || phb->init_m64(phb)) 3164262af557SGuo Chao hose->mem_resources[1].flags = 0; 3165fbbefb32SOliver O'Halloran 3166fbbefb32SOliver O'Halloran /* create pci_dn's for DT nodes under this PHB */ 3167fbbefb32SOliver O'Halloran pci_devs_phb_init_dynamic(hose); 3168184cd4a3SBenjamin Herrenschmidt } 3169184cd4a3SBenjamin Herrenschmidt 317067975005SBjorn Helgaas void __init pnv_pci_init_ioda2_phb(struct device_node *np) 3171aa0c033fSGavin Shan { 3172e9cc17d4SGavin Shan pnv_pci_init_ioda_phb(np, 0, PNV_PHB_IODA2); 3173aa0c033fSGavin Shan } 3174aa0c033fSGavin Shan 31755d2aa710SAlistair Popple void __init pnv_pci_init_npu_phb(struct device_node *np) 31765d2aa710SAlistair Popple { 31777f2c39e9SFrederic Barrat pnv_pci_init_ioda_phb(np, 0, PNV_PHB_NPU_NVLINK); 31785d2aa710SAlistair Popple } 31795d2aa710SAlistair Popple 31807f2c39e9SFrederic Barrat void __init pnv_pci_init_npu2_opencapi_phb(struct device_node *np) 31817f2c39e9SFrederic Barrat { 31827f2c39e9SFrederic Barrat pnv_pci_init_ioda_phb(np, 0, PNV_PHB_NPU_OCAPI); 3183184cd4a3SBenjamin Herrenschmidt } 3184184cd4a3SBenjamin Herrenschmidt 3185228c2f41SAndrew Donnellan static void pnv_npu2_opencapi_cfg_size_fixup(struct pci_dev *dev) 3186228c2f41SAndrew Donnellan { 31875609ffddSOliver O'Halloran struct pnv_phb *phb = pci_bus_to_pnvhb(dev->bus); 3188228c2f41SAndrew Donnellan 3189228c2f41SAndrew Donnellan if (!machine_is(powernv)) 3190228c2f41SAndrew Donnellan return; 3191228c2f41SAndrew Donnellan 3192228c2f41SAndrew Donnellan if (phb->type == PNV_PHB_NPU_OCAPI) 3193228c2f41SAndrew Donnellan dev->cfg_size = PCI_CFG_SPACE_EXP_SIZE; 3194228c2f41SAndrew Donnellan } 3195228c2f41SAndrew Donnellan DECLARE_PCI_FIXUP_EARLY(PCI_ANY_ID, PCI_ANY_ID, pnv_npu2_opencapi_cfg_size_fixup); 3196228c2f41SAndrew Donnellan 3197184cd4a3SBenjamin Herrenschmidt void __init pnv_pci_init_ioda_hub(struct device_node *np) 3198184cd4a3SBenjamin Herrenschmidt { 3199184cd4a3SBenjamin Herrenschmidt struct device_node *phbn; 3200184cd4a3SBenjamin Herrenschmidt const __be64 *prop64; 3201184cd4a3SBenjamin Herrenschmidt u64 hub_id; 3202184cd4a3SBenjamin Herrenschmidt 3203b7c670d6SRob Herring pr_info("Probing IODA IO-Hub %pOF\n", np); 3204184cd4a3SBenjamin Herrenschmidt 3205184cd4a3SBenjamin Herrenschmidt prop64 = of_get_property(np, "ibm,opal-hubid", NULL); 3206184cd4a3SBenjamin Herrenschmidt if (!prop64) { 3207184cd4a3SBenjamin Herrenschmidt pr_err(" Missing \"ibm,opal-hubid\" property !\n"); 3208184cd4a3SBenjamin Herrenschmidt return; 3209184cd4a3SBenjamin Herrenschmidt } 3210184cd4a3SBenjamin Herrenschmidt hub_id = be64_to_cpup(prop64); 3211184cd4a3SBenjamin Herrenschmidt pr_devel(" HUB-ID : 0x%016llx\n", hub_id); 3212184cd4a3SBenjamin Herrenschmidt 3213184cd4a3SBenjamin Herrenschmidt /* Count child PHBs */ 3214184cd4a3SBenjamin Herrenschmidt for_each_child_of_node(np, phbn) { 3215184cd4a3SBenjamin Herrenschmidt /* Look for IODA1 PHBs */ 3216184cd4a3SBenjamin Herrenschmidt if (of_device_is_compatible(phbn, "ibm,ioda-phb")) 3217184cd4a3SBenjamin Herrenschmidt pnv_pci_init_ioda_phb(phbn, hub_id, PNV_PHB_IODA1); 3218184cd4a3SBenjamin Herrenschmidt } 3219184cd4a3SBenjamin Herrenschmidt } 3220