12874c5fdSThomas Gleixner // SPDX-License-Identifier: GPL-2.0-or-later 2184cd4a3SBenjamin Herrenschmidt /* 3184cd4a3SBenjamin Herrenschmidt * Support PCI/PCIe on PowerNV platforms 4184cd4a3SBenjamin Herrenschmidt * 5184cd4a3SBenjamin Herrenschmidt * Copyright 2011 Benjamin Herrenschmidt, IBM Corp. 6184cd4a3SBenjamin Herrenschmidt */ 7184cd4a3SBenjamin Herrenschmidt 8cee72d5bSBenjamin Herrenschmidt #undef DEBUG 9184cd4a3SBenjamin Herrenschmidt 10184cd4a3SBenjamin Herrenschmidt #include <linux/kernel.h> 11184cd4a3SBenjamin Herrenschmidt #include <linux/pci.h> 12361f2a2aSGavin Shan #include <linux/crash_dump.h> 13184cd4a3SBenjamin Herrenschmidt #include <linux/delay.h> 14184cd4a3SBenjamin Herrenschmidt #include <linux/string.h> 15184cd4a3SBenjamin Herrenschmidt #include <linux/init.h> 1657c8a661SMike Rapoport #include <linux/memblock.h> 17184cd4a3SBenjamin Herrenschmidt #include <linux/irq.h> 18184cd4a3SBenjamin Herrenschmidt #include <linux/io.h> 19184cd4a3SBenjamin Herrenschmidt #include <linux/msi.h> 20ac9a5889SAlexey Kardashevskiy #include <linux/iommu.h> 21e57080f1SAlexey Kardashevskiy #include <linux/rculist.h> 224793d65dSAlexey Kardashevskiy #include <linux/sizes.h> 23184cd4a3SBenjamin Herrenschmidt 24184cd4a3SBenjamin Herrenschmidt #include <asm/sections.h> 25184cd4a3SBenjamin Herrenschmidt #include <asm/io.h> 26184cd4a3SBenjamin Herrenschmidt #include <asm/prom.h> 27184cd4a3SBenjamin Herrenschmidt #include <asm/pci-bridge.h> 28184cd4a3SBenjamin Herrenschmidt #include <asm/machdep.h> 29fb1b55d6SGavin Shan #include <asm/msi_bitmap.h> 30184cd4a3SBenjamin Herrenschmidt #include <asm/ppc-pci.h> 31184cd4a3SBenjamin Herrenschmidt #include <asm/opal.h> 32184cd4a3SBenjamin Herrenschmidt #include <asm/iommu.h> 33184cd4a3SBenjamin Herrenschmidt #include <asm/tce.h> 34137436c9SGavin Shan #include <asm/xics.h> 357644d581SMichael Ellerman #include <asm/debugfs.h> 36262af557SGuo Chao #include <asm/firmware.h> 3780c49c7eSIan Munsie #include <asm/pnv-pci.h> 38aca6913fSAlexey Kardashevskiy #include <asm/mmzone.h> 3980c49c7eSIan Munsie 40ec249dd8SMichael Neuling #include <misc/cxl-base.h> 41184cd4a3SBenjamin Herrenschmidt 42184cd4a3SBenjamin Herrenschmidt #include "powernv.h" 43184cd4a3SBenjamin Herrenschmidt #include "pci.h" 4444bda4b7SHari Vyas #include "../../../../drivers/pci/pci.h" 45184cd4a3SBenjamin Herrenschmidt 4699451551SGavin Shan #define PNV_IODA1_M64_NUM 16 /* Number of M64 BARs */ 4799451551SGavin Shan #define PNV_IODA1_M64_SEGS 8 /* Segments per M64 BAR */ 48acce971cSGavin Shan #define PNV_IODA1_DMA32_SEGSIZE 0x10000000 49781a868fSWei Yang 507f2c39e9SFrederic Barrat static const char * const pnv_phb_names[] = { "IODA1", "IODA2", "NPU_NVLINK", 517f2c39e9SFrederic Barrat "NPU_OCAPI" }; 52aca6913fSAlexey Kardashevskiy 53c498a4f9SChristoph Hellwig static void pnv_pci_ioda2_set_bypass(struct pnv_ioda_pe *pe, bool enable); 54dc3d8f85SOliver O'Halloran static void pnv_pci_configure_bus(struct pci_bus *bus); 55c498a4f9SChristoph Hellwig 567d623e42SAlexey Kardashevskiy void pe_level_printk(const struct pnv_ioda_pe *pe, const char *level, 576d31c2faSJoe Perches const char *fmt, ...) 586d31c2faSJoe Perches { 596d31c2faSJoe Perches struct va_format vaf; 606d31c2faSJoe Perches va_list args; 616d31c2faSJoe Perches char pfix[32]; 62184cd4a3SBenjamin Herrenschmidt 636d31c2faSJoe Perches va_start(args, fmt); 646d31c2faSJoe Perches 656d31c2faSJoe Perches vaf.fmt = fmt; 666d31c2faSJoe Perches vaf.va = &args; 676d31c2faSJoe Perches 68781a868fSWei Yang if (pe->flags & PNV_IODA_PE_DEV) 696d31c2faSJoe Perches strlcpy(pfix, dev_name(&pe->pdev->dev), sizeof(pfix)); 70781a868fSWei Yang else if (pe->flags & (PNV_IODA_PE_BUS | PNV_IODA_PE_BUS_ALL)) 716d31c2faSJoe Perches sprintf(pfix, "%04x:%02x ", 726d31c2faSJoe Perches pci_domain_nr(pe->pbus), pe->pbus->number); 73781a868fSWei Yang #ifdef CONFIG_PCI_IOV 74781a868fSWei Yang else if (pe->flags & PNV_IODA_PE_VF) 75781a868fSWei Yang sprintf(pfix, "%04x:%02x:%2x.%d", 76781a868fSWei Yang pci_domain_nr(pe->parent_dev->bus), 77781a868fSWei Yang (pe->rid & 0xff00) >> 8, 78781a868fSWei Yang PCI_SLOT(pe->rid), PCI_FUNC(pe->rid)); 79781a868fSWei Yang #endif /* CONFIG_PCI_IOV*/ 806d31c2faSJoe Perches 811f52f176SRussell Currey printk("%spci %s: [PE# %.2x] %pV", 826d31c2faSJoe Perches level, pfix, pe->pe_number, &vaf); 836d31c2faSJoe Perches 846d31c2faSJoe Perches va_end(args); 856d31c2faSJoe Perches } 866d31c2faSJoe Perches 874e287840SThadeu Lima de Souza Cascardo static bool pnv_iommu_bypass_disabled __read_mostly; 8845baee14SGuilherme G. Piccoli static bool pci_reset_phbs __read_mostly; 894e287840SThadeu Lima de Souza Cascardo 904e287840SThadeu Lima de Souza Cascardo static int __init iommu_setup(char *str) 914e287840SThadeu Lima de Souza Cascardo { 924e287840SThadeu Lima de Souza Cascardo if (!str) 934e287840SThadeu Lima de Souza Cascardo return -EINVAL; 944e287840SThadeu Lima de Souza Cascardo 954e287840SThadeu Lima de Souza Cascardo while (*str) { 964e287840SThadeu Lima de Souza Cascardo if (!strncmp(str, "nobypass", 8)) { 974e287840SThadeu Lima de Souza Cascardo pnv_iommu_bypass_disabled = true; 984e287840SThadeu Lima de Souza Cascardo pr_info("PowerNV: IOMMU bypass window disabled.\n"); 994e287840SThadeu Lima de Souza Cascardo break; 1004e287840SThadeu Lima de Souza Cascardo } 1014e287840SThadeu Lima de Souza Cascardo str += strcspn(str, ","); 1024e287840SThadeu Lima de Souza Cascardo if (*str == ',') 1034e287840SThadeu Lima de Souza Cascardo str++; 1044e287840SThadeu Lima de Souza Cascardo } 1054e287840SThadeu Lima de Souza Cascardo 1064e287840SThadeu Lima de Souza Cascardo return 0; 1074e287840SThadeu Lima de Souza Cascardo } 1084e287840SThadeu Lima de Souza Cascardo early_param("iommu", iommu_setup); 1094e287840SThadeu Lima de Souza Cascardo 11045baee14SGuilherme G. Piccoli static int __init pci_reset_phbs_setup(char *str) 11145baee14SGuilherme G. Piccoli { 11245baee14SGuilherme G. Piccoli pci_reset_phbs = true; 11345baee14SGuilherme G. Piccoli return 0; 11445baee14SGuilherme G. Piccoli } 11545baee14SGuilherme G. Piccoli 11645baee14SGuilherme G. Piccoli early_param("ppc_pci_reset_phbs", pci_reset_phbs_setup); 11745baee14SGuilherme G. Piccoli 1185958d19aSBenjamin Herrenschmidt static inline bool pnv_pci_is_m64(struct pnv_phb *phb, struct resource *r) 119262af557SGuo Chao { 1205958d19aSBenjamin Herrenschmidt /* 1215958d19aSBenjamin Herrenschmidt * WARNING: We cannot rely on the resource flags. The Linux PCI 1225958d19aSBenjamin Herrenschmidt * allocation code sometimes decides to put a 64-bit prefetchable 1235958d19aSBenjamin Herrenschmidt * BAR in the 32-bit window, so we have to compare the addresses. 1245958d19aSBenjamin Herrenschmidt * 1255958d19aSBenjamin Herrenschmidt * For simplicity we only test resource start. 1265958d19aSBenjamin Herrenschmidt */ 1275958d19aSBenjamin Herrenschmidt return (r->start >= phb->ioda.m64_base && 1285958d19aSBenjamin Herrenschmidt r->start < (phb->ioda.m64_base + phb->ioda.m64_size)); 129262af557SGuo Chao } 130262af557SGuo Chao 131b79331a5SRussell Currey static inline bool pnv_pci_is_m64_flags(unsigned long resource_flags) 132b79331a5SRussell Currey { 133b79331a5SRussell Currey unsigned long flags = (IORESOURCE_MEM_64 | IORESOURCE_PREFETCH); 134b79331a5SRussell Currey 135b79331a5SRussell Currey return (resource_flags & flags) == flags; 136b79331a5SRussell Currey } 137b79331a5SRussell Currey 1381e916772SGavin Shan static struct pnv_ioda_pe *pnv_ioda_init_pe(struct pnv_phb *phb, int pe_no) 1391e916772SGavin Shan { 140313483ddSGavin Shan s64 rc; 141313483ddSGavin Shan 1421e916772SGavin Shan phb->ioda.pe_array[pe_no].phb = phb; 1431e916772SGavin Shan phb->ioda.pe_array[pe_no].pe_number = pe_no; 1441e916772SGavin Shan 145313483ddSGavin Shan /* 146313483ddSGavin Shan * Clear the PE frozen state as it might be put into frozen state 147313483ddSGavin Shan * in the last PCI remove path. It's not harmful to do so when the 148313483ddSGavin Shan * PE is already in unfrozen state. 149313483ddSGavin Shan */ 150313483ddSGavin Shan rc = opal_pci_eeh_freeze_clear(phb->opal_id, pe_no, 151313483ddSGavin Shan OPAL_EEH_ACTION_CLEAR_FREEZE_ALL); 152d4791db5SRussell Currey if (rc != OPAL_SUCCESS && rc != OPAL_UNSUPPORTED) 1531f52f176SRussell Currey pr_warn("%s: Error %lld unfreezing PHB#%x-PE#%x\n", 154313483ddSGavin Shan __func__, rc, phb->hose->global_number, pe_no); 155313483ddSGavin Shan 1561e916772SGavin Shan return &phb->ioda.pe_array[pe_no]; 1571e916772SGavin Shan } 1581e916772SGavin Shan 1594b82ab18SGavin Shan static void pnv_ioda_reserve_pe(struct pnv_phb *phb, int pe_no) 1604b82ab18SGavin Shan { 16192b8f137SGavin Shan if (!(pe_no >= 0 && pe_no < phb->ioda.total_pe_num)) { 1621f52f176SRussell Currey pr_warn("%s: Invalid PE %x on PHB#%x\n", 1634b82ab18SGavin Shan __func__, pe_no, phb->hose->global_number); 1644b82ab18SGavin Shan return; 1654b82ab18SGavin Shan } 1664b82ab18SGavin Shan 167e9dc4d7fSGavin Shan if (test_and_set_bit(pe_no, phb->ioda.pe_alloc)) 1681f52f176SRussell Currey pr_debug("%s: PE %x was reserved on PHB#%x\n", 1694b82ab18SGavin Shan __func__, pe_no, phb->hose->global_number); 1704b82ab18SGavin Shan 1711e916772SGavin Shan pnv_ioda_init_pe(phb, pe_no); 1724b82ab18SGavin Shan } 1734b82ab18SGavin Shan 1741e916772SGavin Shan static struct pnv_ioda_pe *pnv_ioda_alloc_pe(struct pnv_phb *phb) 175184cd4a3SBenjamin Herrenschmidt { 17660964816SAndrzej Hajda long pe; 177184cd4a3SBenjamin Herrenschmidt 1789fcd6f4aSGavin Shan for (pe = phb->ioda.total_pe_num - 1; pe >= 0; pe--) { 1799fcd6f4aSGavin Shan if (!test_and_set_bit(pe, phb->ioda.pe_alloc)) 1801e916772SGavin Shan return pnv_ioda_init_pe(phb, pe); 181184cd4a3SBenjamin Herrenschmidt } 182184cd4a3SBenjamin Herrenschmidt 1839fcd6f4aSGavin Shan return NULL; 1849fcd6f4aSGavin Shan } 1859fcd6f4aSGavin Shan 1861e916772SGavin Shan static void pnv_ioda_free_pe(struct pnv_ioda_pe *pe) 187184cd4a3SBenjamin Herrenschmidt { 1881e916772SGavin Shan struct pnv_phb *phb = pe->phb; 189caa58f80SGavin Shan unsigned int pe_num = pe->pe_number; 190184cd4a3SBenjamin Herrenschmidt 1911e916772SGavin Shan WARN_ON(pe->pdev); 192f724385fSFrederic Barrat WARN_ON(pe->npucomp); /* NPUs for nvlink are not supposed to be freed */ 1930bd97167SAlexey Kardashevskiy kfree(pe->npucomp); 1941e916772SGavin Shan memset(pe, 0, sizeof(struct pnv_ioda_pe)); 195caa58f80SGavin Shan clear_bit(pe_num, phb->ioda.pe_alloc); 196184cd4a3SBenjamin Herrenschmidt } 197184cd4a3SBenjamin Herrenschmidt 198262af557SGuo Chao /* The default M64 BAR is shared by all PEs */ 199262af557SGuo Chao static int pnv_ioda2_init_m64(struct pnv_phb *phb) 200262af557SGuo Chao { 201262af557SGuo Chao const char *desc; 202262af557SGuo Chao struct resource *r; 203262af557SGuo Chao s64 rc; 204262af557SGuo Chao 205262af557SGuo Chao /* Configure the default M64 BAR */ 206262af557SGuo Chao rc = opal_pci_set_phb_mem_window(phb->opal_id, 207262af557SGuo Chao OPAL_M64_WINDOW_TYPE, 208262af557SGuo Chao phb->ioda.m64_bar_idx, 209262af557SGuo Chao phb->ioda.m64_base, 210262af557SGuo Chao 0, /* unused */ 211262af557SGuo Chao phb->ioda.m64_size); 212262af557SGuo Chao if (rc != OPAL_SUCCESS) { 213262af557SGuo Chao desc = "configuring"; 214262af557SGuo Chao goto fail; 215262af557SGuo Chao } 216262af557SGuo Chao 217262af557SGuo Chao /* Enable the default M64 BAR */ 218262af557SGuo Chao rc = opal_pci_phb_mmio_enable(phb->opal_id, 219262af557SGuo Chao OPAL_M64_WINDOW_TYPE, 220262af557SGuo Chao phb->ioda.m64_bar_idx, 221262af557SGuo Chao OPAL_ENABLE_M64_SPLIT); 222262af557SGuo Chao if (rc != OPAL_SUCCESS) { 223262af557SGuo Chao desc = "enabling"; 224262af557SGuo Chao goto fail; 225262af557SGuo Chao } 226262af557SGuo Chao 227262af557SGuo Chao /* 22863803c39SGavin Shan * Exclude the segments for reserved and root bus PE, which 22963803c39SGavin Shan * are first or last two PEs. 230262af557SGuo Chao */ 231262af557SGuo Chao r = &phb->hose->mem_resources[1]; 23292b8f137SGavin Shan if (phb->ioda.reserved_pe_idx == 0) 23363803c39SGavin Shan r->start += (2 * phb->ioda.m64_segsize); 23492b8f137SGavin Shan else if (phb->ioda.reserved_pe_idx == (phb->ioda.total_pe_num - 1)) 23563803c39SGavin Shan r->end -= (2 * phb->ioda.m64_segsize); 236262af557SGuo Chao else 2371f52f176SRussell Currey pr_warn(" Cannot strip M64 segment for reserved PE#%x\n", 23892b8f137SGavin Shan phb->ioda.reserved_pe_idx); 239262af557SGuo Chao 240262af557SGuo Chao return 0; 241262af557SGuo Chao 242262af557SGuo Chao fail: 243262af557SGuo Chao pr_warn(" Failure %lld %s M64 BAR#%d\n", 244262af557SGuo Chao rc, desc, phb->ioda.m64_bar_idx); 245262af557SGuo Chao opal_pci_phb_mmio_enable(phb->opal_id, 246262af557SGuo Chao OPAL_M64_WINDOW_TYPE, 247262af557SGuo Chao phb->ioda.m64_bar_idx, 248262af557SGuo Chao OPAL_DISABLE_M64); 249262af557SGuo Chao return -EIO; 250262af557SGuo Chao } 251262af557SGuo Chao 252c430670aSGavin Shan static void pnv_ioda_reserve_dev_m64_pe(struct pci_dev *pdev, 25396a2f92bSGavin Shan unsigned long *pe_bitmap) 254262af557SGuo Chao { 25596a2f92bSGavin Shan struct pci_controller *hose = pci_bus_to_host(pdev->bus); 25696a2f92bSGavin Shan struct pnv_phb *phb = hose->private_data; 257262af557SGuo Chao struct resource *r; 25896a2f92bSGavin Shan resource_size_t base, sgsz, start, end; 25996a2f92bSGavin Shan int segno, i; 260262af557SGuo Chao 26196a2f92bSGavin Shan base = phb->ioda.m64_base; 26296a2f92bSGavin Shan sgsz = phb->ioda.m64_segsize; 26396a2f92bSGavin Shan for (i = 0; i <= PCI_ROM_RESOURCE; i++) { 26496a2f92bSGavin Shan r = &pdev->resource[i]; 2655958d19aSBenjamin Herrenschmidt if (!r->parent || !pnv_pci_is_m64(phb, r)) 266262af557SGuo Chao continue; 267262af557SGuo Chao 268e96d904eSChristophe Leroy start = ALIGN_DOWN(r->start - base, sgsz); 269b7115316SChristophe Leroy end = ALIGN(r->end - base, sgsz); 27096a2f92bSGavin Shan for (segno = start / sgsz; segno < end / sgsz; segno++) { 27196a2f92bSGavin Shan if (pe_bitmap) 27296a2f92bSGavin Shan set_bit(segno, pe_bitmap); 27396a2f92bSGavin Shan else 27496a2f92bSGavin Shan pnv_ioda_reserve_pe(phb, segno); 275262af557SGuo Chao } 276262af557SGuo Chao } 277262af557SGuo Chao } 278262af557SGuo Chao 27999451551SGavin Shan static int pnv_ioda1_init_m64(struct pnv_phb *phb) 28099451551SGavin Shan { 28199451551SGavin Shan struct resource *r; 28299451551SGavin Shan int index; 28399451551SGavin Shan 28499451551SGavin Shan /* 28599451551SGavin Shan * There are 16 M64 BARs, each of which has 8 segments. So 28699451551SGavin Shan * there are as many M64 segments as the maximum number of 28799451551SGavin Shan * PEs, which is 128. 28899451551SGavin Shan */ 28999451551SGavin Shan for (index = 0; index < PNV_IODA1_M64_NUM; index++) { 29099451551SGavin Shan unsigned long base, segsz = phb->ioda.m64_segsize; 29199451551SGavin Shan int64_t rc; 29299451551SGavin Shan 29399451551SGavin Shan base = phb->ioda.m64_base + 29499451551SGavin Shan index * PNV_IODA1_M64_SEGS * segsz; 29599451551SGavin Shan rc = opal_pci_set_phb_mem_window(phb->opal_id, 29699451551SGavin Shan OPAL_M64_WINDOW_TYPE, index, base, 0, 29799451551SGavin Shan PNV_IODA1_M64_SEGS * segsz); 29899451551SGavin Shan if (rc != OPAL_SUCCESS) { 2991f52f176SRussell Currey pr_warn(" Error %lld setting M64 PHB#%x-BAR#%d\n", 30099451551SGavin Shan rc, phb->hose->global_number, index); 30199451551SGavin Shan goto fail; 30299451551SGavin Shan } 30399451551SGavin Shan 30499451551SGavin Shan rc = opal_pci_phb_mmio_enable(phb->opal_id, 30599451551SGavin Shan OPAL_M64_WINDOW_TYPE, index, 30699451551SGavin Shan OPAL_ENABLE_M64_SPLIT); 30799451551SGavin Shan if (rc != OPAL_SUCCESS) { 3081f52f176SRussell Currey pr_warn(" Error %lld enabling M64 PHB#%x-BAR#%d\n", 30999451551SGavin Shan rc, phb->hose->global_number, index); 31099451551SGavin Shan goto fail; 31199451551SGavin Shan } 31299451551SGavin Shan } 31399451551SGavin Shan 31499451551SGavin Shan /* 31563803c39SGavin Shan * Exclude the segments for reserved and root bus PE, which 31663803c39SGavin Shan * are first or last two PEs. 31799451551SGavin Shan */ 31899451551SGavin Shan r = &phb->hose->mem_resources[1]; 31999451551SGavin Shan if (phb->ioda.reserved_pe_idx == 0) 32063803c39SGavin Shan r->start += (2 * phb->ioda.m64_segsize); 32199451551SGavin Shan else if (phb->ioda.reserved_pe_idx == (phb->ioda.total_pe_num - 1)) 32263803c39SGavin Shan r->end -= (2 * phb->ioda.m64_segsize); 32399451551SGavin Shan else 3241f52f176SRussell Currey WARN(1, "Wrong reserved PE#%x on PHB#%x\n", 32599451551SGavin Shan phb->ioda.reserved_pe_idx, phb->hose->global_number); 32699451551SGavin Shan 32799451551SGavin Shan return 0; 32899451551SGavin Shan 32999451551SGavin Shan fail: 33099451551SGavin Shan for ( ; index >= 0; index--) 33199451551SGavin Shan opal_pci_phb_mmio_enable(phb->opal_id, 33299451551SGavin Shan OPAL_M64_WINDOW_TYPE, index, OPAL_DISABLE_M64); 33399451551SGavin Shan 33499451551SGavin Shan return -EIO; 33599451551SGavin Shan } 33699451551SGavin Shan 337c430670aSGavin Shan static void pnv_ioda_reserve_m64_pe(struct pci_bus *bus, 33896a2f92bSGavin Shan unsigned long *pe_bitmap, 33996a2f92bSGavin Shan bool all) 340262af557SGuo Chao { 341262af557SGuo Chao struct pci_dev *pdev; 34296a2f92bSGavin Shan 34396a2f92bSGavin Shan list_for_each_entry(pdev, &bus->devices, bus_list) { 344c430670aSGavin Shan pnv_ioda_reserve_dev_m64_pe(pdev, pe_bitmap); 34596a2f92bSGavin Shan 34696a2f92bSGavin Shan if (all && pdev->subordinate) 347c430670aSGavin Shan pnv_ioda_reserve_m64_pe(pdev->subordinate, 34896a2f92bSGavin Shan pe_bitmap, all); 34996a2f92bSGavin Shan } 35096a2f92bSGavin Shan } 35196a2f92bSGavin Shan 3521e916772SGavin Shan static struct pnv_ioda_pe *pnv_ioda_pick_m64_pe(struct pci_bus *bus, bool all) 353262af557SGuo Chao { 35426ba248dSGavin Shan struct pci_controller *hose = pci_bus_to_host(bus); 35526ba248dSGavin Shan struct pnv_phb *phb = hose->private_data; 356262af557SGuo Chao struct pnv_ioda_pe *master_pe, *pe; 357262af557SGuo Chao unsigned long size, *pe_alloc; 35826ba248dSGavin Shan int i; 359262af557SGuo Chao 360262af557SGuo Chao /* Root bus shouldn't use M64 */ 361262af557SGuo Chao if (pci_is_root_bus(bus)) 3621e916772SGavin Shan return NULL; 363262af557SGuo Chao 364262af557SGuo Chao /* Allocate bitmap */ 365b7115316SChristophe Leroy size = ALIGN(phb->ioda.total_pe_num / 8, sizeof(unsigned long)); 366262af557SGuo Chao pe_alloc = kzalloc(size, GFP_KERNEL); 367262af557SGuo Chao if (!pe_alloc) { 368262af557SGuo Chao pr_warn("%s: Out of memory !\n", 369262af557SGuo Chao __func__); 3701e916772SGavin Shan return NULL; 371262af557SGuo Chao } 372262af557SGuo Chao 37326ba248dSGavin Shan /* Figure out reserved PE numbers by the PE */ 374c430670aSGavin Shan pnv_ioda_reserve_m64_pe(bus, pe_alloc, all); 375262af557SGuo Chao 376262af557SGuo Chao /* 377262af557SGuo Chao * the current bus might not own M64 window and that's all 378262af557SGuo Chao * contributed by its child buses. For the case, we needn't 379262af557SGuo Chao * pick M64 dependent PE#. 380262af557SGuo Chao */ 38192b8f137SGavin Shan if (bitmap_empty(pe_alloc, phb->ioda.total_pe_num)) { 382262af557SGuo Chao kfree(pe_alloc); 3831e916772SGavin Shan return NULL; 384262af557SGuo Chao } 385262af557SGuo Chao 386262af557SGuo Chao /* 387262af557SGuo Chao * Figure out the master PE and put all slave PEs to master 388262af557SGuo Chao * PE's list to form compound PE. 389262af557SGuo Chao */ 390262af557SGuo Chao master_pe = NULL; 391262af557SGuo Chao i = -1; 39292b8f137SGavin Shan while ((i = find_next_bit(pe_alloc, phb->ioda.total_pe_num, i + 1)) < 39392b8f137SGavin Shan phb->ioda.total_pe_num) { 394262af557SGuo Chao pe = &phb->ioda.pe_array[i]; 395262af557SGuo Chao 39693289d8cSGavin Shan phb->ioda.m64_segmap[pe->pe_number] = pe->pe_number; 397262af557SGuo Chao if (!master_pe) { 398262af557SGuo Chao pe->flags |= PNV_IODA_PE_MASTER; 399262af557SGuo Chao INIT_LIST_HEAD(&pe->slaves); 400262af557SGuo Chao master_pe = pe; 401262af557SGuo Chao } else { 402262af557SGuo Chao pe->flags |= PNV_IODA_PE_SLAVE; 403262af557SGuo Chao pe->master = master_pe; 404262af557SGuo Chao list_add_tail(&pe->list, &master_pe->slaves); 405262af557SGuo Chao } 40699451551SGavin Shan 40799451551SGavin Shan /* 40899451551SGavin Shan * P7IOC supports M64DT, which helps mapping M64 segment 40999451551SGavin Shan * to one particular PE#. However, PHB3 has fixed mapping 41099451551SGavin Shan * between M64 segment and PE#. In order to have same logic 41199451551SGavin Shan * for P7IOC and PHB3, we enforce fixed mapping between M64 41299451551SGavin Shan * segment and PE# on P7IOC. 41399451551SGavin Shan */ 41499451551SGavin Shan if (phb->type == PNV_PHB_IODA1) { 41599451551SGavin Shan int64_t rc; 41699451551SGavin Shan 41799451551SGavin Shan rc = opal_pci_map_pe_mmio_window(phb->opal_id, 41899451551SGavin Shan pe->pe_number, OPAL_M64_WINDOW_TYPE, 41999451551SGavin Shan pe->pe_number / PNV_IODA1_M64_SEGS, 42099451551SGavin Shan pe->pe_number % PNV_IODA1_M64_SEGS); 42199451551SGavin Shan if (rc != OPAL_SUCCESS) 4221f52f176SRussell Currey pr_warn("%s: Error %lld mapping M64 for PHB#%x-PE#%x\n", 42399451551SGavin Shan __func__, rc, phb->hose->global_number, 42499451551SGavin Shan pe->pe_number); 42599451551SGavin Shan } 426262af557SGuo Chao } 427262af557SGuo Chao 428262af557SGuo Chao kfree(pe_alloc); 4291e916772SGavin Shan return master_pe; 430262af557SGuo Chao } 431262af557SGuo Chao 432262af557SGuo Chao static void __init pnv_ioda_parse_m64_window(struct pnv_phb *phb) 433262af557SGuo Chao { 434262af557SGuo Chao struct pci_controller *hose = phb->hose; 435262af557SGuo Chao struct device_node *dn = hose->dn; 436262af557SGuo Chao struct resource *res; 437a1339fafSBenjamin Herrenschmidt u32 m64_range[2], i; 4380e7736c6SGavin Shan const __be32 *r; 439262af557SGuo Chao u64 pci_addr; 440262af557SGuo Chao 44199451551SGavin Shan if (phb->type != PNV_PHB_IODA1 && phb->type != PNV_PHB_IODA2) { 4421665c4a8SGavin Shan pr_info(" Not support M64 window\n"); 4431665c4a8SGavin Shan return; 4441665c4a8SGavin Shan } 4451665c4a8SGavin Shan 446e4d54f71SStewart Smith if (!firmware_has_feature(FW_FEATURE_OPAL)) { 447262af557SGuo Chao pr_info(" Firmware too old to support M64 window\n"); 448262af557SGuo Chao return; 449262af557SGuo Chao } 450262af557SGuo Chao 451262af557SGuo Chao r = of_get_property(dn, "ibm,opal-m64-window", NULL); 452262af557SGuo Chao if (!r) { 453b7c670d6SRob Herring pr_info(" No <ibm,opal-m64-window> on %pOF\n", 454b7c670d6SRob Herring dn); 455262af557SGuo Chao return; 456262af557SGuo Chao } 457262af557SGuo Chao 458a1339fafSBenjamin Herrenschmidt /* 459a1339fafSBenjamin Herrenschmidt * Find the available M64 BAR range and pickup the last one for 460a1339fafSBenjamin Herrenschmidt * covering the whole 64-bits space. We support only one range. 461a1339fafSBenjamin Herrenschmidt */ 462a1339fafSBenjamin Herrenschmidt if (of_property_read_u32_array(dn, "ibm,opal-available-m64-ranges", 463a1339fafSBenjamin Herrenschmidt m64_range, 2)) { 464a1339fafSBenjamin Herrenschmidt /* In absence of the property, assume 0..15 */ 465a1339fafSBenjamin Herrenschmidt m64_range[0] = 0; 466a1339fafSBenjamin Herrenschmidt m64_range[1] = 16; 467a1339fafSBenjamin Herrenschmidt } 468a1339fafSBenjamin Herrenschmidt /* We only support 64 bits in our allocator */ 469a1339fafSBenjamin Herrenschmidt if (m64_range[1] > 63) { 470a1339fafSBenjamin Herrenschmidt pr_warn("%s: Limiting M64 range to 63 (from %d) on PHB#%x\n", 471a1339fafSBenjamin Herrenschmidt __func__, m64_range[1], phb->hose->global_number); 472a1339fafSBenjamin Herrenschmidt m64_range[1] = 63; 473a1339fafSBenjamin Herrenschmidt } 474a1339fafSBenjamin Herrenschmidt /* Empty range, no m64 */ 475a1339fafSBenjamin Herrenschmidt if (m64_range[1] <= m64_range[0]) { 476a1339fafSBenjamin Herrenschmidt pr_warn("%s: M64 empty, disabling M64 usage on PHB#%x\n", 477a1339fafSBenjamin Herrenschmidt __func__, phb->hose->global_number); 478a1339fafSBenjamin Herrenschmidt return; 479a1339fafSBenjamin Herrenschmidt } 480a1339fafSBenjamin Herrenschmidt 481a1339fafSBenjamin Herrenschmidt /* Configure M64 informations */ 482262af557SGuo Chao res = &hose->mem_resources[1]; 483e80c4e7cSGavin Shan res->name = dn->full_name; 484262af557SGuo Chao res->start = of_translate_address(dn, r + 2); 485262af557SGuo Chao res->end = res->start + of_read_number(r + 4, 2) - 1; 486262af557SGuo Chao res->flags = (IORESOURCE_MEM | IORESOURCE_MEM_64 | IORESOURCE_PREFETCH); 487262af557SGuo Chao pci_addr = of_read_number(r, 2); 488262af557SGuo Chao hose->mem_offset[1] = res->start - pci_addr; 489262af557SGuo Chao 490262af557SGuo Chao phb->ioda.m64_size = resource_size(res); 49192b8f137SGavin Shan phb->ioda.m64_segsize = phb->ioda.m64_size / phb->ioda.total_pe_num; 492262af557SGuo Chao phb->ioda.m64_base = pci_addr; 493262af557SGuo Chao 494a1339fafSBenjamin Herrenschmidt /* This lines up nicely with the display from processing OF ranges */ 495a1339fafSBenjamin Herrenschmidt pr_info(" MEM 0x%016llx..0x%016llx -> 0x%016llx (M64 #%d..%d)\n", 496a1339fafSBenjamin Herrenschmidt res->start, res->end, pci_addr, m64_range[0], 497a1339fafSBenjamin Herrenschmidt m64_range[0] + m64_range[1] - 1); 498a1339fafSBenjamin Herrenschmidt 499a1339fafSBenjamin Herrenschmidt /* Mark all M64 used up by default */ 500a1339fafSBenjamin Herrenschmidt phb->ioda.m64_bar_alloc = (unsigned long)-1; 501e9863e68SWei Yang 502262af557SGuo Chao /* Use last M64 BAR to cover M64 window */ 503a1339fafSBenjamin Herrenschmidt m64_range[1]--; 504a1339fafSBenjamin Herrenschmidt phb->ioda.m64_bar_idx = m64_range[0] + m64_range[1]; 505a1339fafSBenjamin Herrenschmidt 506a1339fafSBenjamin Herrenschmidt pr_info(" Using M64 #%d as default window\n", phb->ioda.m64_bar_idx); 507a1339fafSBenjamin Herrenschmidt 508a1339fafSBenjamin Herrenschmidt /* Mark remaining ones free */ 509a1339fafSBenjamin Herrenschmidt for (i = m64_range[0]; i < m64_range[1]; i++) 510a1339fafSBenjamin Herrenschmidt clear_bit(i, &phb->ioda.m64_bar_alloc); 511a1339fafSBenjamin Herrenschmidt 512a1339fafSBenjamin Herrenschmidt /* 513a1339fafSBenjamin Herrenschmidt * Setup init functions for M64 based on IODA version, IODA3 uses 514a1339fafSBenjamin Herrenschmidt * the IODA2 code. 515a1339fafSBenjamin Herrenschmidt */ 51699451551SGavin Shan if (phb->type == PNV_PHB_IODA1) 51799451551SGavin Shan phb->init_m64 = pnv_ioda1_init_m64; 51899451551SGavin Shan else 519262af557SGuo Chao phb->init_m64 = pnv_ioda2_init_m64; 520262af557SGuo Chao } 521262af557SGuo Chao 52249dec922SGavin Shan static void pnv_ioda_freeze_pe(struct pnv_phb *phb, int pe_no) 52349dec922SGavin Shan { 52449dec922SGavin Shan struct pnv_ioda_pe *pe = &phb->ioda.pe_array[pe_no]; 52549dec922SGavin Shan struct pnv_ioda_pe *slave; 52649dec922SGavin Shan s64 rc; 52749dec922SGavin Shan 52849dec922SGavin Shan /* Fetch master PE */ 52949dec922SGavin Shan if (pe->flags & PNV_IODA_PE_SLAVE) { 53049dec922SGavin Shan pe = pe->master; 531ec8e4e9dSGavin Shan if (WARN_ON(!pe || !(pe->flags & PNV_IODA_PE_MASTER))) 532ec8e4e9dSGavin Shan return; 533ec8e4e9dSGavin Shan 53449dec922SGavin Shan pe_no = pe->pe_number; 53549dec922SGavin Shan } 53649dec922SGavin Shan 53749dec922SGavin Shan /* Freeze master PE */ 53849dec922SGavin Shan rc = opal_pci_eeh_freeze_set(phb->opal_id, 53949dec922SGavin Shan pe_no, 54049dec922SGavin Shan OPAL_EEH_ACTION_SET_FREEZE_ALL); 54149dec922SGavin Shan if (rc != OPAL_SUCCESS) { 54249dec922SGavin Shan pr_warn("%s: Failure %lld freezing PHB#%x-PE#%x\n", 54349dec922SGavin Shan __func__, rc, phb->hose->global_number, pe_no); 54449dec922SGavin Shan return; 54549dec922SGavin Shan } 54649dec922SGavin Shan 54749dec922SGavin Shan /* Freeze slave PEs */ 54849dec922SGavin Shan if (!(pe->flags & PNV_IODA_PE_MASTER)) 54949dec922SGavin Shan return; 55049dec922SGavin Shan 55149dec922SGavin Shan list_for_each_entry(slave, &pe->slaves, list) { 55249dec922SGavin Shan rc = opal_pci_eeh_freeze_set(phb->opal_id, 55349dec922SGavin Shan slave->pe_number, 55449dec922SGavin Shan OPAL_EEH_ACTION_SET_FREEZE_ALL); 55549dec922SGavin Shan if (rc != OPAL_SUCCESS) 55649dec922SGavin Shan pr_warn("%s: Failure %lld freezing PHB#%x-PE#%x\n", 55749dec922SGavin Shan __func__, rc, phb->hose->global_number, 55849dec922SGavin Shan slave->pe_number); 55949dec922SGavin Shan } 56049dec922SGavin Shan } 56149dec922SGavin Shan 562e51df2c1SAnton Blanchard static int pnv_ioda_unfreeze_pe(struct pnv_phb *phb, int pe_no, int opt) 56349dec922SGavin Shan { 56449dec922SGavin Shan struct pnv_ioda_pe *pe, *slave; 56549dec922SGavin Shan s64 rc; 56649dec922SGavin Shan 56749dec922SGavin Shan /* Find master PE */ 56849dec922SGavin Shan pe = &phb->ioda.pe_array[pe_no]; 56949dec922SGavin Shan if (pe->flags & PNV_IODA_PE_SLAVE) { 57049dec922SGavin Shan pe = pe->master; 57149dec922SGavin Shan WARN_ON(!pe || !(pe->flags & PNV_IODA_PE_MASTER)); 57249dec922SGavin Shan pe_no = pe->pe_number; 57349dec922SGavin Shan } 57449dec922SGavin Shan 57549dec922SGavin Shan /* Clear frozen state for master PE */ 57649dec922SGavin Shan rc = opal_pci_eeh_freeze_clear(phb->opal_id, pe_no, opt); 57749dec922SGavin Shan if (rc != OPAL_SUCCESS) { 57849dec922SGavin Shan pr_warn("%s: Failure %lld clear %d on PHB#%x-PE#%x\n", 57949dec922SGavin Shan __func__, rc, opt, phb->hose->global_number, pe_no); 58049dec922SGavin Shan return -EIO; 58149dec922SGavin Shan } 58249dec922SGavin Shan 58349dec922SGavin Shan if (!(pe->flags & PNV_IODA_PE_MASTER)) 58449dec922SGavin Shan return 0; 58549dec922SGavin Shan 58649dec922SGavin Shan /* Clear frozen state for slave PEs */ 58749dec922SGavin Shan list_for_each_entry(slave, &pe->slaves, list) { 58849dec922SGavin Shan rc = opal_pci_eeh_freeze_clear(phb->opal_id, 58949dec922SGavin Shan slave->pe_number, 59049dec922SGavin Shan opt); 59149dec922SGavin Shan if (rc != OPAL_SUCCESS) { 59249dec922SGavin Shan pr_warn("%s: Failure %lld clear %d on PHB#%x-PE#%x\n", 59349dec922SGavin Shan __func__, rc, opt, phb->hose->global_number, 59449dec922SGavin Shan slave->pe_number); 59549dec922SGavin Shan return -EIO; 59649dec922SGavin Shan } 59749dec922SGavin Shan } 59849dec922SGavin Shan 59949dec922SGavin Shan return 0; 60049dec922SGavin Shan } 60149dec922SGavin Shan 60249dec922SGavin Shan static int pnv_ioda_get_pe_state(struct pnv_phb *phb, int pe_no) 60349dec922SGavin Shan { 60449dec922SGavin Shan struct pnv_ioda_pe *slave, *pe; 605c2057701SAlexey Kardashevskiy u8 fstate = 0, state; 606c2057701SAlexey Kardashevskiy __be16 pcierr = 0; 60749dec922SGavin Shan s64 rc; 60849dec922SGavin Shan 60949dec922SGavin Shan /* Sanity check on PE number */ 61092b8f137SGavin Shan if (pe_no < 0 || pe_no >= phb->ioda.total_pe_num) 61149dec922SGavin Shan return OPAL_EEH_STOPPED_PERM_UNAVAIL; 61249dec922SGavin Shan 61349dec922SGavin Shan /* 61449dec922SGavin Shan * Fetch the master PE and the PE instance might be 61549dec922SGavin Shan * not initialized yet. 61649dec922SGavin Shan */ 61749dec922SGavin Shan pe = &phb->ioda.pe_array[pe_no]; 61849dec922SGavin Shan if (pe->flags & PNV_IODA_PE_SLAVE) { 61949dec922SGavin Shan pe = pe->master; 62049dec922SGavin Shan WARN_ON(!pe || !(pe->flags & PNV_IODA_PE_MASTER)); 62149dec922SGavin Shan pe_no = pe->pe_number; 62249dec922SGavin Shan } 62349dec922SGavin Shan 62449dec922SGavin Shan /* Check the master PE */ 62549dec922SGavin Shan rc = opal_pci_eeh_freeze_status(phb->opal_id, pe_no, 62649dec922SGavin Shan &state, &pcierr, NULL); 62749dec922SGavin Shan if (rc != OPAL_SUCCESS) { 62849dec922SGavin Shan pr_warn("%s: Failure %lld getting " 62949dec922SGavin Shan "PHB#%x-PE#%x state\n", 63049dec922SGavin Shan __func__, rc, 63149dec922SGavin Shan phb->hose->global_number, pe_no); 63249dec922SGavin Shan return OPAL_EEH_STOPPED_TEMP_UNAVAIL; 63349dec922SGavin Shan } 63449dec922SGavin Shan 63549dec922SGavin Shan /* Check the slave PE */ 63649dec922SGavin Shan if (!(pe->flags & PNV_IODA_PE_MASTER)) 63749dec922SGavin Shan return state; 63849dec922SGavin Shan 63949dec922SGavin Shan list_for_each_entry(slave, &pe->slaves, list) { 64049dec922SGavin Shan rc = opal_pci_eeh_freeze_status(phb->opal_id, 64149dec922SGavin Shan slave->pe_number, 64249dec922SGavin Shan &fstate, 64349dec922SGavin Shan &pcierr, 64449dec922SGavin Shan NULL); 64549dec922SGavin Shan if (rc != OPAL_SUCCESS) { 64649dec922SGavin Shan pr_warn("%s: Failure %lld getting " 64749dec922SGavin Shan "PHB#%x-PE#%x state\n", 64849dec922SGavin Shan __func__, rc, 64949dec922SGavin Shan phb->hose->global_number, slave->pe_number); 65049dec922SGavin Shan return OPAL_EEH_STOPPED_TEMP_UNAVAIL; 65149dec922SGavin Shan } 65249dec922SGavin Shan 65349dec922SGavin Shan /* 65449dec922SGavin Shan * Override the result based on the ascending 65549dec922SGavin Shan * priority. 65649dec922SGavin Shan */ 65749dec922SGavin Shan if (fstate > state) 65849dec922SGavin Shan state = fstate; 65949dec922SGavin Shan } 66049dec922SGavin Shan 66149dec922SGavin Shan return state; 66249dec922SGavin Shan } 66349dec922SGavin Shan 664a8d7d5fcSOliver O'Halloran struct pnv_ioda_pe *pnv_pci_bdfn_to_pe(struct pnv_phb *phb, u16 bdfn) 665a8d7d5fcSOliver O'Halloran { 666a8d7d5fcSOliver O'Halloran int pe_number = phb->ioda.pe_rmap[bdfn]; 667a8d7d5fcSOliver O'Halloran 668a8d7d5fcSOliver O'Halloran if (pe_number == IODA_INVALID_PE) 669a8d7d5fcSOliver O'Halloran return NULL; 670a8d7d5fcSOliver O'Halloran 671a8d7d5fcSOliver O'Halloran return &phb->ioda.pe_array[pe_number]; 672a8d7d5fcSOliver O'Halloran } 673a8d7d5fcSOliver O'Halloran 674f456834aSIan Munsie struct pnv_ioda_pe *pnv_ioda_get_pe(struct pci_dev *dev) 675184cd4a3SBenjamin Herrenschmidt { 676184cd4a3SBenjamin Herrenschmidt struct pci_controller *hose = pci_bus_to_host(dev->bus); 677184cd4a3SBenjamin Herrenschmidt struct pnv_phb *phb = hose->private_data; 678b72c1f65SBenjamin Herrenschmidt struct pci_dn *pdn = pci_get_pdn(dev); 679184cd4a3SBenjamin Herrenschmidt 680184cd4a3SBenjamin Herrenschmidt if (!pdn) 681184cd4a3SBenjamin Herrenschmidt return NULL; 682184cd4a3SBenjamin Herrenschmidt if (pdn->pe_number == IODA_INVALID_PE) 683184cd4a3SBenjamin Herrenschmidt return NULL; 684184cd4a3SBenjamin Herrenschmidt return &phb->ioda.pe_array[pdn->pe_number]; 685184cd4a3SBenjamin Herrenschmidt } 686184cd4a3SBenjamin Herrenschmidt 687b131a842SGavin Shan static int pnv_ioda_set_one_peltv(struct pnv_phb *phb, 688b131a842SGavin Shan struct pnv_ioda_pe *parent, 689b131a842SGavin Shan struct pnv_ioda_pe *child, 690b131a842SGavin Shan bool is_add) 691b131a842SGavin Shan { 692b131a842SGavin Shan const char *desc = is_add ? "adding" : "removing"; 693b131a842SGavin Shan uint8_t op = is_add ? OPAL_ADD_PE_TO_DOMAIN : 694b131a842SGavin Shan OPAL_REMOVE_PE_FROM_DOMAIN; 695b131a842SGavin Shan struct pnv_ioda_pe *slave; 696b131a842SGavin Shan long rc; 697b131a842SGavin Shan 698b131a842SGavin Shan /* Parent PE affects child PE */ 699b131a842SGavin Shan rc = opal_pci_set_peltv(phb->opal_id, parent->pe_number, 700b131a842SGavin Shan child->pe_number, op); 701b131a842SGavin Shan if (rc != OPAL_SUCCESS) { 702b131a842SGavin Shan pe_warn(child, "OPAL error %ld %s to parent PELTV\n", 703b131a842SGavin Shan rc, desc); 704b131a842SGavin Shan return -ENXIO; 705b131a842SGavin Shan } 706b131a842SGavin Shan 707b131a842SGavin Shan if (!(child->flags & PNV_IODA_PE_MASTER)) 708b131a842SGavin Shan return 0; 709b131a842SGavin Shan 710b131a842SGavin Shan /* Compound case: parent PE affects slave PEs */ 711b131a842SGavin Shan list_for_each_entry(slave, &child->slaves, list) { 712b131a842SGavin Shan rc = opal_pci_set_peltv(phb->opal_id, parent->pe_number, 713b131a842SGavin Shan slave->pe_number, op); 714b131a842SGavin Shan if (rc != OPAL_SUCCESS) { 715b131a842SGavin Shan pe_warn(slave, "OPAL error %ld %s to parent PELTV\n", 716b131a842SGavin Shan rc, desc); 717b131a842SGavin Shan return -ENXIO; 718b131a842SGavin Shan } 719b131a842SGavin Shan } 720b131a842SGavin Shan 721b131a842SGavin Shan return 0; 722b131a842SGavin Shan } 723b131a842SGavin Shan 724b131a842SGavin Shan static int pnv_ioda_set_peltv(struct pnv_phb *phb, 725b131a842SGavin Shan struct pnv_ioda_pe *pe, 726b131a842SGavin Shan bool is_add) 727b131a842SGavin Shan { 728b131a842SGavin Shan struct pnv_ioda_pe *slave; 729781a868fSWei Yang struct pci_dev *pdev = NULL; 730b131a842SGavin Shan int ret; 731b131a842SGavin Shan 732b131a842SGavin Shan /* 733b131a842SGavin Shan * Clear PE frozen state. If it's master PE, we need 734b131a842SGavin Shan * clear slave PE frozen state as well. 735b131a842SGavin Shan */ 736b131a842SGavin Shan if (is_add) { 737b131a842SGavin Shan opal_pci_eeh_freeze_clear(phb->opal_id, pe->pe_number, 738b131a842SGavin Shan OPAL_EEH_ACTION_CLEAR_FREEZE_ALL); 739b131a842SGavin Shan if (pe->flags & PNV_IODA_PE_MASTER) { 740b131a842SGavin Shan list_for_each_entry(slave, &pe->slaves, list) 741b131a842SGavin Shan opal_pci_eeh_freeze_clear(phb->opal_id, 742b131a842SGavin Shan slave->pe_number, 743b131a842SGavin Shan OPAL_EEH_ACTION_CLEAR_FREEZE_ALL); 744b131a842SGavin Shan } 745b131a842SGavin Shan } 746b131a842SGavin Shan 747b131a842SGavin Shan /* 748b131a842SGavin Shan * Associate PE in PELT. We need add the PE into the 749b131a842SGavin Shan * corresponding PELT-V as well. Otherwise, the error 750b131a842SGavin Shan * originated from the PE might contribute to other 751b131a842SGavin Shan * PEs. 752b131a842SGavin Shan */ 753b131a842SGavin Shan ret = pnv_ioda_set_one_peltv(phb, pe, pe, is_add); 754b131a842SGavin Shan if (ret) 755b131a842SGavin Shan return ret; 756b131a842SGavin Shan 757b131a842SGavin Shan /* For compound PEs, any one affects all of them */ 758b131a842SGavin Shan if (pe->flags & PNV_IODA_PE_MASTER) { 759b131a842SGavin Shan list_for_each_entry(slave, &pe->slaves, list) { 760b131a842SGavin Shan ret = pnv_ioda_set_one_peltv(phb, slave, pe, is_add); 761b131a842SGavin Shan if (ret) 762b131a842SGavin Shan return ret; 763b131a842SGavin Shan } 764b131a842SGavin Shan } 765b131a842SGavin Shan 766b131a842SGavin Shan if (pe->flags & (PNV_IODA_PE_BUS_ALL | PNV_IODA_PE_BUS)) 767b131a842SGavin Shan pdev = pe->pbus->self; 768781a868fSWei Yang else if (pe->flags & PNV_IODA_PE_DEV) 769b131a842SGavin Shan pdev = pe->pdev->bus->self; 770781a868fSWei Yang #ifdef CONFIG_PCI_IOV 771781a868fSWei Yang else if (pe->flags & PNV_IODA_PE_VF) 772283e2d8aSGavin Shan pdev = pe->parent_dev; 773781a868fSWei Yang #endif /* CONFIG_PCI_IOV */ 774b131a842SGavin Shan while (pdev) { 775b131a842SGavin Shan struct pci_dn *pdn = pci_get_pdn(pdev); 776b131a842SGavin Shan struct pnv_ioda_pe *parent; 777b131a842SGavin Shan 778b131a842SGavin Shan if (pdn && pdn->pe_number != IODA_INVALID_PE) { 779b131a842SGavin Shan parent = &phb->ioda.pe_array[pdn->pe_number]; 780b131a842SGavin Shan ret = pnv_ioda_set_one_peltv(phb, parent, pe, is_add); 781b131a842SGavin Shan if (ret) 782b131a842SGavin Shan return ret; 783b131a842SGavin Shan } 784b131a842SGavin Shan 785b131a842SGavin Shan pdev = pdev->bus->self; 786b131a842SGavin Shan } 787b131a842SGavin Shan 788b131a842SGavin Shan return 0; 789b131a842SGavin Shan } 790b131a842SGavin Shan 791f724385fSFrederic Barrat static void pnv_ioda_unset_peltv(struct pnv_phb *phb, 792f724385fSFrederic Barrat struct pnv_ioda_pe *pe, 793f724385fSFrederic Barrat struct pci_dev *parent) 794f724385fSFrederic Barrat { 795f724385fSFrederic Barrat int64_t rc; 796f724385fSFrederic Barrat 797f724385fSFrederic Barrat while (parent) { 798f724385fSFrederic Barrat struct pci_dn *pdn = pci_get_pdn(parent); 799f724385fSFrederic Barrat 800f724385fSFrederic Barrat if (pdn && pdn->pe_number != IODA_INVALID_PE) { 801f724385fSFrederic Barrat rc = opal_pci_set_peltv(phb->opal_id, pdn->pe_number, 802f724385fSFrederic Barrat pe->pe_number, 803f724385fSFrederic Barrat OPAL_REMOVE_PE_FROM_DOMAIN); 804f724385fSFrederic Barrat /* XXX What to do in case of error ? */ 805f724385fSFrederic Barrat } 806f724385fSFrederic Barrat parent = parent->bus->self; 807f724385fSFrederic Barrat } 808f724385fSFrederic Barrat 809f724385fSFrederic Barrat opal_pci_eeh_freeze_clear(phb->opal_id, pe->pe_number, 810f724385fSFrederic Barrat OPAL_EEH_ACTION_CLEAR_FREEZE_ALL); 811f724385fSFrederic Barrat 812f724385fSFrederic Barrat /* Disassociate PE in PELT */ 813f724385fSFrederic Barrat rc = opal_pci_set_peltv(phb->opal_id, pe->pe_number, 814f724385fSFrederic Barrat pe->pe_number, OPAL_REMOVE_PE_FROM_DOMAIN); 815f724385fSFrederic Barrat if (rc) 816f724385fSFrederic Barrat pe_warn(pe, "OPAL error %lld remove self from PELTV\n", rc); 817f724385fSFrederic Barrat } 818f724385fSFrederic Barrat 819781a868fSWei Yang static int pnv_ioda_deconfigure_pe(struct pnv_phb *phb, struct pnv_ioda_pe *pe) 820781a868fSWei Yang { 821781a868fSWei Yang struct pci_dev *parent; 822781a868fSWei Yang uint8_t bcomp, dcomp, fcomp; 823781a868fSWei Yang int64_t rc; 824781a868fSWei Yang long rid_end, rid; 825781a868fSWei Yang 826781a868fSWei Yang /* Currently, we just deconfigure VF PE. Bus PE will always there.*/ 827781a868fSWei Yang if (pe->pbus) { 828781a868fSWei Yang int count; 829781a868fSWei Yang 830781a868fSWei Yang dcomp = OPAL_IGNORE_RID_DEVICE_NUMBER; 831781a868fSWei Yang fcomp = OPAL_IGNORE_RID_FUNCTION_NUMBER; 832781a868fSWei Yang parent = pe->pbus->self; 833781a868fSWei Yang if (pe->flags & PNV_IODA_PE_BUS_ALL) 834552aa086SJulia Lawall count = resource_size(&pe->pbus->busn_res); 835781a868fSWei Yang else 836781a868fSWei Yang count = 1; 837781a868fSWei Yang 838781a868fSWei Yang switch(count) { 839781a868fSWei Yang case 1: bcomp = OpalPciBusAll; break; 840781a868fSWei Yang case 2: bcomp = OpalPciBus7Bits; break; 841781a868fSWei Yang case 4: bcomp = OpalPciBus6Bits; break; 842781a868fSWei Yang case 8: bcomp = OpalPciBus5Bits; break; 843781a868fSWei Yang case 16: bcomp = OpalPciBus4Bits; break; 844781a868fSWei Yang case 32: bcomp = OpalPciBus3Bits; break; 845781a868fSWei Yang default: 846781a868fSWei Yang dev_err(&pe->pbus->dev, "Number of subordinate buses %d unsupported\n", 847781a868fSWei Yang count); 848781a868fSWei Yang /* Do an exact match only */ 849781a868fSWei Yang bcomp = OpalPciBusAll; 850781a868fSWei Yang } 851781a868fSWei Yang rid_end = pe->rid + (count << 8); 852781a868fSWei Yang } else { 85393e01a50SGavin Shan #ifdef CONFIG_PCI_IOV 854781a868fSWei Yang if (pe->flags & PNV_IODA_PE_VF) 855781a868fSWei Yang parent = pe->parent_dev; 856781a868fSWei Yang else 85793e01a50SGavin Shan #endif 858781a868fSWei Yang parent = pe->pdev->bus->self; 859781a868fSWei Yang bcomp = OpalPciBusAll; 860781a868fSWei Yang dcomp = OPAL_COMPARE_RID_DEVICE_NUMBER; 861781a868fSWei Yang fcomp = OPAL_COMPARE_RID_FUNCTION_NUMBER; 862781a868fSWei Yang rid_end = pe->rid + 1; 863781a868fSWei Yang } 864781a868fSWei Yang 865781a868fSWei Yang /* Clear the reverse map */ 866781a868fSWei Yang for (rid = pe->rid; rid < rid_end; rid++) 867c127562aSGavin Shan phb->ioda.pe_rmap[rid] = IODA_INVALID_PE; 868781a868fSWei Yang 869f724385fSFrederic Barrat /* 870f724385fSFrederic Barrat * Release from all parents PELT-V. NPUs don't have a PELTV 871f724385fSFrederic Barrat * table 872f724385fSFrederic Barrat */ 873f724385fSFrederic Barrat if (phb->type != PNV_PHB_NPU_NVLINK && phb->type != PNV_PHB_NPU_OCAPI) 874f724385fSFrederic Barrat pnv_ioda_unset_peltv(phb, pe, parent); 875781a868fSWei Yang 876781a868fSWei Yang rc = opal_pci_set_pe(phb->opal_id, pe->pe_number, pe->rid, 877781a868fSWei Yang bcomp, dcomp, fcomp, OPAL_UNMAP_PE); 878781a868fSWei Yang if (rc) 8791e496391SJoe Perches pe_err(pe, "OPAL error %lld trying to setup PELT table\n", rc); 880781a868fSWei Yang 881781a868fSWei Yang pe->pbus = NULL; 882781a868fSWei Yang pe->pdev = NULL; 88393e01a50SGavin Shan #ifdef CONFIG_PCI_IOV 884781a868fSWei Yang pe->parent_dev = NULL; 88593e01a50SGavin Shan #endif 886781a868fSWei Yang 887781a868fSWei Yang return 0; 888781a868fSWei Yang } 889781a868fSWei Yang 890cad5cef6SGreg Kroah-Hartman static int pnv_ioda_configure_pe(struct pnv_phb *phb, struct pnv_ioda_pe *pe) 891184cd4a3SBenjamin Herrenschmidt { 892184cd4a3SBenjamin Herrenschmidt struct pci_dev *parent; 893184cd4a3SBenjamin Herrenschmidt uint8_t bcomp, dcomp, fcomp; 894184cd4a3SBenjamin Herrenschmidt long rc, rid_end, rid; 895184cd4a3SBenjamin Herrenschmidt 896184cd4a3SBenjamin Herrenschmidt /* Bus validation ? */ 897184cd4a3SBenjamin Herrenschmidt if (pe->pbus) { 898184cd4a3SBenjamin Herrenschmidt int count; 899184cd4a3SBenjamin Herrenschmidt 900184cd4a3SBenjamin Herrenschmidt dcomp = OPAL_IGNORE_RID_DEVICE_NUMBER; 901184cd4a3SBenjamin Herrenschmidt fcomp = OPAL_IGNORE_RID_FUNCTION_NUMBER; 902184cd4a3SBenjamin Herrenschmidt parent = pe->pbus->self; 903fb446ad0SGavin Shan if (pe->flags & PNV_IODA_PE_BUS_ALL) 904552aa086SJulia Lawall count = resource_size(&pe->pbus->busn_res); 905fb446ad0SGavin Shan else 906fb446ad0SGavin Shan count = 1; 907fb446ad0SGavin Shan 908184cd4a3SBenjamin Herrenschmidt switch(count) { 909184cd4a3SBenjamin Herrenschmidt case 1: bcomp = OpalPciBusAll; break; 910184cd4a3SBenjamin Herrenschmidt case 2: bcomp = OpalPciBus7Bits; break; 911184cd4a3SBenjamin Herrenschmidt case 4: bcomp = OpalPciBus6Bits; break; 912184cd4a3SBenjamin Herrenschmidt case 8: bcomp = OpalPciBus5Bits; break; 913184cd4a3SBenjamin Herrenschmidt case 16: bcomp = OpalPciBus4Bits; break; 914184cd4a3SBenjamin Herrenschmidt case 32: bcomp = OpalPciBus3Bits; break; 915184cd4a3SBenjamin Herrenschmidt default: 916781a868fSWei Yang dev_err(&pe->pbus->dev, "Number of subordinate buses %d unsupported\n", 917781a868fSWei Yang count); 918184cd4a3SBenjamin Herrenschmidt /* Do an exact match only */ 919184cd4a3SBenjamin Herrenschmidt bcomp = OpalPciBusAll; 920184cd4a3SBenjamin Herrenschmidt } 921184cd4a3SBenjamin Herrenschmidt rid_end = pe->rid + (count << 8); 922184cd4a3SBenjamin Herrenschmidt } else { 923781a868fSWei Yang #ifdef CONFIG_PCI_IOV 924781a868fSWei Yang if (pe->flags & PNV_IODA_PE_VF) 925781a868fSWei Yang parent = pe->parent_dev; 926781a868fSWei Yang else 927781a868fSWei Yang #endif /* CONFIG_PCI_IOV */ 928184cd4a3SBenjamin Herrenschmidt parent = pe->pdev->bus->self; 929184cd4a3SBenjamin Herrenschmidt bcomp = OpalPciBusAll; 930184cd4a3SBenjamin Herrenschmidt dcomp = OPAL_COMPARE_RID_DEVICE_NUMBER; 931184cd4a3SBenjamin Herrenschmidt fcomp = OPAL_COMPARE_RID_FUNCTION_NUMBER; 932184cd4a3SBenjamin Herrenschmidt rid_end = pe->rid + 1; 933184cd4a3SBenjamin Herrenschmidt } 934184cd4a3SBenjamin Herrenschmidt 935631ad691SGavin Shan /* 936631ad691SGavin Shan * Associate PE in PELT. We need add the PE into the 937631ad691SGavin Shan * corresponding PELT-V as well. Otherwise, the error 938631ad691SGavin Shan * originated from the PE might contribute to other 939631ad691SGavin Shan * PEs. 940631ad691SGavin Shan */ 941184cd4a3SBenjamin Herrenschmidt rc = opal_pci_set_pe(phb->opal_id, pe->pe_number, pe->rid, 942184cd4a3SBenjamin Herrenschmidt bcomp, dcomp, fcomp, OPAL_MAP_PE); 943184cd4a3SBenjamin Herrenschmidt if (rc) { 944184cd4a3SBenjamin Herrenschmidt pe_err(pe, "OPAL error %ld trying to setup PELT table\n", rc); 945184cd4a3SBenjamin Herrenschmidt return -ENXIO; 946184cd4a3SBenjamin Herrenschmidt } 947631ad691SGavin Shan 9485d2aa710SAlistair Popple /* 9495d2aa710SAlistair Popple * Configure PELTV. NPUs don't have a PELTV table so skip 9505d2aa710SAlistair Popple * configuration on them. 9515d2aa710SAlistair Popple */ 9527f2c39e9SFrederic Barrat if (phb->type != PNV_PHB_NPU_NVLINK && phb->type != PNV_PHB_NPU_OCAPI) 953b131a842SGavin Shan pnv_ioda_set_peltv(phb, pe, true); 954184cd4a3SBenjamin Herrenschmidt 955184cd4a3SBenjamin Herrenschmidt /* Setup reverse map */ 956184cd4a3SBenjamin Herrenschmidt for (rid = pe->rid; rid < rid_end; rid++) 957184cd4a3SBenjamin Herrenschmidt phb->ioda.pe_rmap[rid] = pe->pe_number; 958184cd4a3SBenjamin Herrenschmidt 959184cd4a3SBenjamin Herrenschmidt /* Setup one MVTs on IODA1 */ 9604773f76bSGavin Shan if (phb->type != PNV_PHB_IODA1) { 9614773f76bSGavin Shan pe->mve_number = 0; 9624773f76bSGavin Shan goto out; 9634773f76bSGavin Shan } 9644773f76bSGavin Shan 965184cd4a3SBenjamin Herrenschmidt pe->mve_number = pe->pe_number; 9664773f76bSGavin Shan rc = opal_pci_set_mve(phb->opal_id, pe->mve_number, pe->pe_number); 9674773f76bSGavin Shan if (rc != OPAL_SUCCESS) { 9681f52f176SRussell Currey pe_err(pe, "OPAL error %ld setting up MVE %x\n", 969184cd4a3SBenjamin Herrenschmidt rc, pe->mve_number); 970184cd4a3SBenjamin Herrenschmidt pe->mve_number = -1; 971184cd4a3SBenjamin Herrenschmidt } else { 972184cd4a3SBenjamin Herrenschmidt rc = opal_pci_set_mve_enable(phb->opal_id, 973cee72d5bSBenjamin Herrenschmidt pe->mve_number, OPAL_ENABLE_MVE); 974184cd4a3SBenjamin Herrenschmidt if (rc) { 9751f52f176SRussell Currey pe_err(pe, "OPAL error %ld enabling MVE %x\n", 976184cd4a3SBenjamin Herrenschmidt rc, pe->mve_number); 977184cd4a3SBenjamin Herrenschmidt pe->mve_number = -1; 978184cd4a3SBenjamin Herrenschmidt } 979184cd4a3SBenjamin Herrenschmidt } 980184cd4a3SBenjamin Herrenschmidt 9814773f76bSGavin Shan out: 982184cd4a3SBenjamin Herrenschmidt return 0; 983184cd4a3SBenjamin Herrenschmidt } 984184cd4a3SBenjamin Herrenschmidt 985781a868fSWei Yang #ifdef CONFIG_PCI_IOV 986781a868fSWei Yang static int pnv_pci_vf_resource_shift(struct pci_dev *dev, int offset) 987781a868fSWei Yang { 988781a868fSWei Yang struct pci_dn *pdn = pci_get_pdn(dev); 989781a868fSWei Yang int i; 990781a868fSWei Yang struct resource *res, res2; 991781a868fSWei Yang resource_size_t size; 992781a868fSWei Yang u16 num_vfs; 993781a868fSWei Yang 994781a868fSWei Yang if (!dev->is_physfn) 995781a868fSWei Yang return -EINVAL; 996781a868fSWei Yang 997781a868fSWei Yang /* 998781a868fSWei Yang * "offset" is in VFs. The M64 windows are sized so that when they 999781a868fSWei Yang * are segmented, each segment is the same size as the IOV BAR. 1000781a868fSWei Yang * Each segment is in a separate PE, and the high order bits of the 1001781a868fSWei Yang * address are the PE number. Therefore, each VF's BAR is in a 1002781a868fSWei Yang * separate PE, and changing the IOV BAR start address changes the 1003781a868fSWei Yang * range of PEs the VFs are in. 1004781a868fSWei Yang */ 1005781a868fSWei Yang num_vfs = pdn->num_vfs; 1006781a868fSWei Yang for (i = 0; i < PCI_SRIOV_NUM_BARS; i++) { 1007781a868fSWei Yang res = &dev->resource[i + PCI_IOV_RESOURCES]; 1008781a868fSWei Yang if (!res->flags || !res->parent) 1009781a868fSWei Yang continue; 1010781a868fSWei Yang 1011781a868fSWei Yang /* 1012781a868fSWei Yang * The actual IOV BAR range is determined by the start address 1013781a868fSWei Yang * and the actual size for num_vfs VFs BAR. This check is to 1014781a868fSWei Yang * make sure that after shifting, the range will not overlap 1015781a868fSWei Yang * with another device. 1016781a868fSWei Yang */ 1017781a868fSWei Yang size = pci_iov_resource_size(dev, i + PCI_IOV_RESOURCES); 1018781a868fSWei Yang res2.flags = res->flags; 1019781a868fSWei Yang res2.start = res->start + (size * offset); 1020781a868fSWei Yang res2.end = res2.start + (size * num_vfs) - 1; 1021781a868fSWei Yang 1022781a868fSWei Yang if (res2.end > res->end) { 1023781a868fSWei Yang dev_err(&dev->dev, "VF BAR%d: %pR would extend past %pR (trying to enable %d VFs shifted by %d)\n", 1024781a868fSWei Yang i, &res2, res, num_vfs, offset); 1025781a868fSWei Yang return -EBUSY; 1026781a868fSWei Yang } 1027781a868fSWei Yang } 1028781a868fSWei Yang 1029781a868fSWei Yang /* 1030d6f934fdSAlexey Kardashevskiy * Since M64 BAR shares segments among all possible 256 PEs, 1031d6f934fdSAlexey Kardashevskiy * we have to shift the beginning of PF IOV BAR to make it start from 1032d6f934fdSAlexey Kardashevskiy * the segment which belongs to the PE number assigned to the first VF. 1033d6f934fdSAlexey Kardashevskiy * This creates a "hole" in the /proc/iomem which could be used for 1034d6f934fdSAlexey Kardashevskiy * allocating other resources so we reserve this area below and 1035d6f934fdSAlexey Kardashevskiy * release when IOV is released. 1036781a868fSWei Yang */ 1037781a868fSWei Yang for (i = 0; i < PCI_SRIOV_NUM_BARS; i++) { 1038781a868fSWei Yang res = &dev->resource[i + PCI_IOV_RESOURCES]; 1039781a868fSWei Yang if (!res->flags || !res->parent) 1040781a868fSWei Yang continue; 1041781a868fSWei Yang 1042781a868fSWei Yang size = pci_iov_resource_size(dev, i + PCI_IOV_RESOURCES); 1043781a868fSWei Yang res2 = *res; 1044781a868fSWei Yang res->start += size * offset; 1045781a868fSWei Yang 104674703cc4SWei Yang dev_info(&dev->dev, "VF BAR%d: %pR shifted to %pR (%sabling %d VFs shifted by %d)\n", 104774703cc4SWei Yang i, &res2, res, (offset > 0) ? "En" : "Dis", 104874703cc4SWei Yang num_vfs, offset); 1049d6f934fdSAlexey Kardashevskiy 1050d6f934fdSAlexey Kardashevskiy if (offset < 0) { 1051d6f934fdSAlexey Kardashevskiy devm_release_resource(&dev->dev, &pdn->holes[i]); 1052d6f934fdSAlexey Kardashevskiy memset(&pdn->holes[i], 0, sizeof(pdn->holes[i])); 1053d6f934fdSAlexey Kardashevskiy } 1054d6f934fdSAlexey Kardashevskiy 1055781a868fSWei Yang pci_update_resource(dev, i + PCI_IOV_RESOURCES); 1056d6f934fdSAlexey Kardashevskiy 1057d6f934fdSAlexey Kardashevskiy if (offset > 0) { 1058d6f934fdSAlexey Kardashevskiy pdn->holes[i].start = res2.start; 1059d6f934fdSAlexey Kardashevskiy pdn->holes[i].end = res2.start + size * offset - 1; 1060d6f934fdSAlexey Kardashevskiy pdn->holes[i].flags = IORESOURCE_BUS; 1061d6f934fdSAlexey Kardashevskiy pdn->holes[i].name = "pnv_iov_reserved"; 1062d6f934fdSAlexey Kardashevskiy devm_request_resource(&dev->dev, res->parent, 1063d6f934fdSAlexey Kardashevskiy &pdn->holes[i]); 1064d6f934fdSAlexey Kardashevskiy } 1065781a868fSWei Yang } 1066781a868fSWei Yang return 0; 1067781a868fSWei Yang } 1068781a868fSWei Yang #endif /* CONFIG_PCI_IOV */ 1069781a868fSWei Yang 1070cad5cef6SGreg Kroah-Hartman static struct pnv_ioda_pe *pnv_ioda_setup_dev_PE(struct pci_dev *dev) 1071184cd4a3SBenjamin Herrenschmidt { 1072184cd4a3SBenjamin Herrenschmidt struct pci_controller *hose = pci_bus_to_host(dev->bus); 1073184cd4a3SBenjamin Herrenschmidt struct pnv_phb *phb = hose->private_data; 1074b72c1f65SBenjamin Herrenschmidt struct pci_dn *pdn = pci_get_pdn(dev); 1075184cd4a3SBenjamin Herrenschmidt struct pnv_ioda_pe *pe; 1076184cd4a3SBenjamin Herrenschmidt 1077184cd4a3SBenjamin Herrenschmidt if (!pdn) { 1078184cd4a3SBenjamin Herrenschmidt pr_err("%s: Device tree node not associated properly\n", 1079184cd4a3SBenjamin Herrenschmidt pci_name(dev)); 1080184cd4a3SBenjamin Herrenschmidt return NULL; 1081184cd4a3SBenjamin Herrenschmidt } 1082184cd4a3SBenjamin Herrenschmidt if (pdn->pe_number != IODA_INVALID_PE) 1083184cd4a3SBenjamin Herrenschmidt return NULL; 1084184cd4a3SBenjamin Herrenschmidt 10851e916772SGavin Shan pe = pnv_ioda_alloc_pe(phb); 10861e916772SGavin Shan if (!pe) { 1087f2c2cbccSJoe Perches pr_warn("%s: Not enough PE# available, disabling device\n", 1088184cd4a3SBenjamin Herrenschmidt pci_name(dev)); 1089184cd4a3SBenjamin Herrenschmidt return NULL; 1090184cd4a3SBenjamin Herrenschmidt } 1091184cd4a3SBenjamin Herrenschmidt 109205dd7da7SFrederic Barrat /* NOTE: We don't get a reference for the pointer in the PE 109305dd7da7SFrederic Barrat * data structure, both the device and PE structures should be 109405dd7da7SFrederic Barrat * destroyed at the same time. However, removing nvlink 109505dd7da7SFrederic Barrat * devices will need some work. 1096184cd4a3SBenjamin Herrenschmidt * 1097184cd4a3SBenjamin Herrenschmidt * At some point we want to remove the PDN completely anyways 1098184cd4a3SBenjamin Herrenschmidt */ 10991e916772SGavin Shan pdn->pe_number = pe->pe_number; 11005d2aa710SAlistair Popple pe->flags = PNV_IODA_PE_DEV; 1101184cd4a3SBenjamin Herrenschmidt pe->pdev = dev; 1102184cd4a3SBenjamin Herrenschmidt pe->pbus = NULL; 1103184cd4a3SBenjamin Herrenschmidt pe->mve_number = -1; 1104184cd4a3SBenjamin Herrenschmidt pe->rid = dev->bus->number << 8 | pdn->devfn; 1105f724385fSFrederic Barrat pe->device_count++; 1106184cd4a3SBenjamin Herrenschmidt 1107184cd4a3SBenjamin Herrenschmidt pe_info(pe, "Associated device to PE\n"); 1108184cd4a3SBenjamin Herrenschmidt 1109184cd4a3SBenjamin Herrenschmidt if (pnv_ioda_configure_pe(phb, pe)) { 1110184cd4a3SBenjamin Herrenschmidt /* XXX What do we do here ? */ 11111e916772SGavin Shan pnv_ioda_free_pe(pe); 1112184cd4a3SBenjamin Herrenschmidt pdn->pe_number = IODA_INVALID_PE; 1113184cd4a3SBenjamin Herrenschmidt pe->pdev = NULL; 1114184cd4a3SBenjamin Herrenschmidt return NULL; 1115184cd4a3SBenjamin Herrenschmidt } 1116184cd4a3SBenjamin Herrenschmidt 11171d4e89cfSAlexey Kardashevskiy /* Put PE to the list */ 111880f1ff83SFrederic Barrat mutex_lock(&phb->ioda.pe_list_mutex); 11191d4e89cfSAlexey Kardashevskiy list_add_tail(&pe->list, &phb->ioda.pe_list); 112080f1ff83SFrederic Barrat mutex_unlock(&phb->ioda.pe_list_mutex); 1121184cd4a3SBenjamin Herrenschmidt return pe; 1122184cd4a3SBenjamin Herrenschmidt } 1123184cd4a3SBenjamin Herrenschmidt 1124fb446ad0SGavin Shan /* 1125fb446ad0SGavin Shan * There're 2 types of PCI bus sensitive PEs: One that is compromised of 1126fb446ad0SGavin Shan * single PCI bus. Another one that contains the primary PCI bus and its 1127fb446ad0SGavin Shan * subordinate PCI devices and buses. The second type of PE is normally 1128fb446ad0SGavin Shan * orgiriated by PCIe-to-PCI bridge or PLX switch downstream ports. 1129fb446ad0SGavin Shan */ 11301e916772SGavin Shan static struct pnv_ioda_pe *pnv_ioda_setup_bus_PE(struct pci_bus *bus, bool all) 1131184cd4a3SBenjamin Herrenschmidt { 1132fb446ad0SGavin Shan struct pci_controller *hose = pci_bus_to_host(bus); 1133184cd4a3SBenjamin Herrenschmidt struct pnv_phb *phb = hose->private_data; 11341e916772SGavin Shan struct pnv_ioda_pe *pe = NULL; 1135ccd1c191SGavin Shan unsigned int pe_num; 1136ccd1c191SGavin Shan 1137ccd1c191SGavin Shan /* 1138ccd1c191SGavin Shan * In partial hotplug case, the PE instance might be still alive. 1139ccd1c191SGavin Shan * We should reuse it instead of allocating a new one. 1140ccd1c191SGavin Shan */ 1141ccd1c191SGavin Shan pe_num = phb->ioda.pe_rmap[bus->number << 8]; 1142ccd1c191SGavin Shan if (pe_num != IODA_INVALID_PE) { 1143ccd1c191SGavin Shan pe = &phb->ioda.pe_array[pe_num]; 1144ccd1c191SGavin Shan return NULL; 1145ccd1c191SGavin Shan } 1146184cd4a3SBenjamin Herrenschmidt 114763803c39SGavin Shan /* PE number for root bus should have been reserved */ 114863803c39SGavin Shan if (pci_is_root_bus(bus) && 114963803c39SGavin Shan phb->ioda.root_pe_idx != IODA_INVALID_PE) 115063803c39SGavin Shan pe = &phb->ioda.pe_array[phb->ioda.root_pe_idx]; 115163803c39SGavin Shan 1152262af557SGuo Chao /* Check if PE is determined by M64 */ 1153a25de7afSAlexey Kardashevskiy if (!pe) 1154a25de7afSAlexey Kardashevskiy pe = pnv_ioda_pick_m64_pe(bus, all); 1155262af557SGuo Chao 1156262af557SGuo Chao /* The PE number isn't pinned by M64 */ 11571e916772SGavin Shan if (!pe) 11581e916772SGavin Shan pe = pnv_ioda_alloc_pe(phb); 1159262af557SGuo Chao 11601e916772SGavin Shan if (!pe) { 1161f2c2cbccSJoe Perches pr_warn("%s: Not enough PE# available for PCI bus %04x:%02x\n", 1162fb446ad0SGavin Shan __func__, pci_domain_nr(bus), bus->number); 11631e916772SGavin Shan return NULL; 1164184cd4a3SBenjamin Herrenschmidt } 1165184cd4a3SBenjamin Herrenschmidt 1166262af557SGuo Chao pe->flags |= (all ? PNV_IODA_PE_BUS_ALL : PNV_IODA_PE_BUS); 1167184cd4a3SBenjamin Herrenschmidt pe->pbus = bus; 1168184cd4a3SBenjamin Herrenschmidt pe->pdev = NULL; 1169184cd4a3SBenjamin Herrenschmidt pe->mve_number = -1; 1170b918c62eSYinghai Lu pe->rid = bus->busn_res.start << 8; 1171184cd4a3SBenjamin Herrenschmidt 1172fb446ad0SGavin Shan if (all) 11731e496391SJoe Perches pe_info(pe, "Secondary bus %pad..%pad associated with PE#%x\n", 11741e496391SJoe Perches &bus->busn_res.start, &bus->busn_res.end, 11751e496391SJoe Perches pe->pe_number); 1176fb446ad0SGavin Shan else 11771e496391SJoe Perches pe_info(pe, "Secondary bus %pad associated with PE#%x\n", 11781e496391SJoe Perches &bus->busn_res.start, pe->pe_number); 1179184cd4a3SBenjamin Herrenschmidt 1180184cd4a3SBenjamin Herrenschmidt if (pnv_ioda_configure_pe(phb, pe)) { 1181184cd4a3SBenjamin Herrenschmidt /* XXX What do we do here ? */ 11821e916772SGavin Shan pnv_ioda_free_pe(pe); 1183184cd4a3SBenjamin Herrenschmidt pe->pbus = NULL; 11841e916772SGavin Shan return NULL; 1185184cd4a3SBenjamin Herrenschmidt } 1186184cd4a3SBenjamin Herrenschmidt 11877ebdf956SGavin Shan /* Put PE to the list */ 11887ebdf956SGavin Shan list_add_tail(&pe->list, &phb->ioda.pe_list); 11891e916772SGavin Shan 11901e916772SGavin Shan return pe; 1191184cd4a3SBenjamin Herrenschmidt } 1192184cd4a3SBenjamin Herrenschmidt 1193b521549aSAlistair Popple static struct pnv_ioda_pe *pnv_ioda_setup_npu_PE(struct pci_dev *npu_pdev) 11945d2aa710SAlistair Popple { 1195b521549aSAlistair Popple int pe_num, found_pe = false, rc; 1196b521549aSAlistair Popple long rid; 1197b521549aSAlistair Popple struct pnv_ioda_pe *pe; 1198b521549aSAlistair Popple struct pci_dev *gpu_pdev; 1199b521549aSAlistair Popple struct pci_dn *npu_pdn; 1200b521549aSAlistair Popple struct pci_controller *hose = pci_bus_to_host(npu_pdev->bus); 1201b521549aSAlistair Popple struct pnv_phb *phb = hose->private_data; 1202b521549aSAlistair Popple 1203b521549aSAlistair Popple /* 120405dd7da7SFrederic Barrat * Intentionally leak a reference on the npu device (for 120505dd7da7SFrederic Barrat * nvlink only; this is not an opencapi path) to make sure it 120605dd7da7SFrederic Barrat * never goes away, as it's been the case all along and some 120705dd7da7SFrederic Barrat * work is needed otherwise. 120805dd7da7SFrederic Barrat */ 120905dd7da7SFrederic Barrat pci_dev_get(npu_pdev); 121005dd7da7SFrederic Barrat 121105dd7da7SFrederic Barrat /* 1212b521549aSAlistair Popple * Due to a hardware errata PE#0 on the NPU is reserved for 1213b521549aSAlistair Popple * error handling. This means we only have three PEs remaining 1214b521549aSAlistair Popple * which need to be assigned to four links, implying some 1215b521549aSAlistair Popple * links must share PEs. 1216b521549aSAlistair Popple * 1217b521549aSAlistair Popple * To achieve this we assign PEs such that NPUs linking the 1218b521549aSAlistair Popple * same GPU get assigned the same PE. 1219b521549aSAlistair Popple */ 1220b521549aSAlistair Popple gpu_pdev = pnv_pci_get_gpu_dev(npu_pdev); 122192b8f137SGavin Shan for (pe_num = 0; pe_num < phb->ioda.total_pe_num; pe_num++) { 1222b521549aSAlistair Popple pe = &phb->ioda.pe_array[pe_num]; 1223b521549aSAlistair Popple if (!pe->pdev) 1224b521549aSAlistair Popple continue; 1225b521549aSAlistair Popple 1226b521549aSAlistair Popple if (pnv_pci_get_gpu_dev(pe->pdev) == gpu_pdev) { 1227b521549aSAlistair Popple /* 1228b521549aSAlistair Popple * This device has the same peer GPU so should 1229b521549aSAlistair Popple * be assigned the same PE as the existing 1230b521549aSAlistair Popple * peer NPU. 1231b521549aSAlistair Popple */ 1232b521549aSAlistair Popple dev_info(&npu_pdev->dev, 12331f52f176SRussell Currey "Associating to existing PE %x\n", pe_num); 1234b521549aSAlistair Popple npu_pdn = pci_get_pdn(npu_pdev); 1235b521549aSAlistair Popple rid = npu_pdev->bus->number << 8 | npu_pdn->devfn; 1236b521549aSAlistair Popple npu_pdn->pe_number = pe_num; 1237b521549aSAlistair Popple phb->ioda.pe_rmap[rid] = pe->pe_number; 1238f724385fSFrederic Barrat pe->device_count++; 1239b521549aSAlistair Popple 1240b521549aSAlistair Popple /* Map the PE to this link */ 1241b521549aSAlistair Popple rc = opal_pci_set_pe(phb->opal_id, pe_num, rid, 1242b521549aSAlistair Popple OpalPciBusAll, 1243b521549aSAlistair Popple OPAL_COMPARE_RID_DEVICE_NUMBER, 1244b521549aSAlistair Popple OPAL_COMPARE_RID_FUNCTION_NUMBER, 1245b521549aSAlistair Popple OPAL_MAP_PE); 1246b521549aSAlistair Popple WARN_ON(rc != OPAL_SUCCESS); 1247b521549aSAlistair Popple found_pe = true; 1248b521549aSAlistair Popple break; 1249b521549aSAlistair Popple } 1250b521549aSAlistair Popple } 1251b521549aSAlistair Popple 1252b521549aSAlistair Popple if (!found_pe) 1253b521549aSAlistair Popple /* 1254b521549aSAlistair Popple * Could not find an existing PE so allocate a new 1255b521549aSAlistair Popple * one. 1256b521549aSAlistair Popple */ 1257b521549aSAlistair Popple return pnv_ioda_setup_dev_PE(npu_pdev); 1258b521549aSAlistair Popple else 1259b521549aSAlistair Popple return pe; 1260b521549aSAlistair Popple } 1261b521549aSAlistair Popple 1262b521549aSAlistair Popple static void pnv_ioda_setup_npu_PEs(struct pci_bus *bus) 1263b521549aSAlistair Popple { 12645d2aa710SAlistair Popple struct pci_dev *pdev; 12655d2aa710SAlistair Popple 12665d2aa710SAlistair Popple list_for_each_entry(pdev, &bus->devices, bus_list) 1267b521549aSAlistair Popple pnv_ioda_setup_npu_PE(pdev); 12685d2aa710SAlistair Popple } 12695d2aa710SAlistair Popple 127003b7bf34SOliver O'Halloran static void pnv_pci_ioda_setup_nvlink(void) 1271fb446ad0SGavin Shan { 12720e759bd7SAlexey Kardashevskiy struct pci_controller *hose; 1273262af557SGuo Chao struct pnv_phb *phb; 12740e759bd7SAlexey Kardashevskiy struct pnv_ioda_pe *pe; 1275fb446ad0SGavin Shan 12760e759bd7SAlexey Kardashevskiy list_for_each_entry(hose, &hose_list, list_node) { 1277262af557SGuo Chao phb = hose->private_data; 12787f2c39e9SFrederic Barrat if (phb->type == PNV_PHB_NPU_NVLINK) { 127908f48f32SAlistair Popple /* PE#0 is needed for error reporting */ 128008f48f32SAlistair Popple pnv_ioda_reserve_pe(phb, 0); 1281b521549aSAlistair Popple pnv_ioda_setup_npu_PEs(hose->bus); 12821ab66d1fSAlistair Popple if (phb->model == PNV_PHB_MODEL_NPU2) 12830e759bd7SAlexey Kardashevskiy WARN_ON_ONCE(pnv_npu2_init(hose)); 1284ccd1c191SGavin Shan } 1285fb446ad0SGavin Shan } 12860e759bd7SAlexey Kardashevskiy list_for_each_entry(hose, &hose_list, list_node) { 12870e759bd7SAlexey Kardashevskiy phb = hose->private_data; 12880e759bd7SAlexey Kardashevskiy if (phb->type != PNV_PHB_IODA2) 12890e759bd7SAlexey Kardashevskiy continue; 12900e759bd7SAlexey Kardashevskiy 12910e759bd7SAlexey Kardashevskiy list_for_each_entry(pe, &phb->ioda.pe_list, list) 12920e759bd7SAlexey Kardashevskiy pnv_npu2_map_lpar(pe, MSR_DR | MSR_PR | MSR_HV); 12930e759bd7SAlexey Kardashevskiy } 129403b7bf34SOliver O'Halloran 129503b7bf34SOliver O'Halloran #ifdef CONFIG_IOMMU_API 129603b7bf34SOliver O'Halloran /* setup iommu groups so we can do nvlink pass-thru */ 129703b7bf34SOliver O'Halloran pnv_pci_npu_setup_iommu_groups(); 129803b7bf34SOliver O'Halloran #endif 1299fb446ad0SGavin Shan } 1300184cd4a3SBenjamin Herrenschmidt 1301a8b2f828SGavin Shan #ifdef CONFIG_PCI_IOV 1302ee8222feSWei Yang static int pnv_pci_vf_release_m64(struct pci_dev *pdev, u16 num_vfs) 1303781a868fSWei Yang { 1304781a868fSWei Yang struct pci_bus *bus; 1305781a868fSWei Yang struct pci_controller *hose; 1306781a868fSWei Yang struct pnv_phb *phb; 1307781a868fSWei Yang struct pci_dn *pdn; 130802639b0eSWei Yang int i, j; 1309ee8222feSWei Yang int m64_bars; 1310781a868fSWei Yang 1311781a868fSWei Yang bus = pdev->bus; 1312781a868fSWei Yang hose = pci_bus_to_host(bus); 1313781a868fSWei Yang phb = hose->private_data; 1314781a868fSWei Yang pdn = pci_get_pdn(pdev); 1315781a868fSWei Yang 1316ee8222feSWei Yang if (pdn->m64_single_mode) 1317ee8222feSWei Yang m64_bars = num_vfs; 1318ee8222feSWei Yang else 1319ee8222feSWei Yang m64_bars = 1; 1320ee8222feSWei Yang 132102639b0eSWei Yang for (i = 0; i < PCI_SRIOV_NUM_BARS; i++) 1322ee8222feSWei Yang for (j = 0; j < m64_bars; j++) { 1323ee8222feSWei Yang if (pdn->m64_map[j][i] == IODA_INVALID_M64) 1324781a868fSWei Yang continue; 1325781a868fSWei Yang opal_pci_phb_mmio_enable(phb->opal_id, 1326ee8222feSWei Yang OPAL_M64_WINDOW_TYPE, pdn->m64_map[j][i], 0); 1327ee8222feSWei Yang clear_bit(pdn->m64_map[j][i], &phb->ioda.m64_bar_alloc); 1328ee8222feSWei Yang pdn->m64_map[j][i] = IODA_INVALID_M64; 1329781a868fSWei Yang } 1330781a868fSWei Yang 1331ee8222feSWei Yang kfree(pdn->m64_map); 1332781a868fSWei Yang return 0; 1333781a868fSWei Yang } 1334781a868fSWei Yang 133502639b0eSWei Yang static int pnv_pci_vf_assign_m64(struct pci_dev *pdev, u16 num_vfs) 1336781a868fSWei Yang { 1337781a868fSWei Yang struct pci_bus *bus; 1338781a868fSWei Yang struct pci_controller *hose; 1339781a868fSWei Yang struct pnv_phb *phb; 1340781a868fSWei Yang struct pci_dn *pdn; 1341781a868fSWei Yang unsigned int win; 1342781a868fSWei Yang struct resource *res; 134302639b0eSWei Yang int i, j; 1344781a868fSWei Yang int64_t rc; 134502639b0eSWei Yang int total_vfs; 134602639b0eSWei Yang resource_size_t size, start; 134702639b0eSWei Yang int pe_num; 1348ee8222feSWei Yang int m64_bars; 1349781a868fSWei Yang 1350781a868fSWei Yang bus = pdev->bus; 1351781a868fSWei Yang hose = pci_bus_to_host(bus); 1352781a868fSWei Yang phb = hose->private_data; 1353781a868fSWei Yang pdn = pci_get_pdn(pdev); 135402639b0eSWei Yang total_vfs = pci_sriov_get_totalvfs(pdev); 1355781a868fSWei Yang 1356ee8222feSWei Yang if (pdn->m64_single_mode) 1357ee8222feSWei Yang m64_bars = num_vfs; 1358ee8222feSWei Yang else 1359ee8222feSWei Yang m64_bars = 1; 136002639b0eSWei Yang 1361fb37e128SMarkus Elfring pdn->m64_map = kmalloc_array(m64_bars, 1362fb37e128SMarkus Elfring sizeof(*pdn->m64_map), 1363fb37e128SMarkus Elfring GFP_KERNEL); 1364ee8222feSWei Yang if (!pdn->m64_map) 1365ee8222feSWei Yang return -ENOMEM; 1366ee8222feSWei Yang /* Initialize the m64_map to IODA_INVALID_M64 */ 1367ee8222feSWei Yang for (i = 0; i < m64_bars ; i++) 1368ee8222feSWei Yang for (j = 0; j < PCI_SRIOV_NUM_BARS; j++) 1369ee8222feSWei Yang pdn->m64_map[i][j] = IODA_INVALID_M64; 1370ee8222feSWei Yang 1371781a868fSWei Yang 1372781a868fSWei Yang for (i = 0; i < PCI_SRIOV_NUM_BARS; i++) { 1373781a868fSWei Yang res = &pdev->resource[i + PCI_IOV_RESOURCES]; 1374781a868fSWei Yang if (!res->flags || !res->parent) 1375781a868fSWei Yang continue; 1376781a868fSWei Yang 1377ee8222feSWei Yang for (j = 0; j < m64_bars; j++) { 1378781a868fSWei Yang do { 1379781a868fSWei Yang win = find_next_zero_bit(&phb->ioda.m64_bar_alloc, 1380781a868fSWei Yang phb->ioda.m64_bar_idx + 1, 0); 1381781a868fSWei Yang 1382781a868fSWei Yang if (win >= phb->ioda.m64_bar_idx + 1) 1383781a868fSWei Yang goto m64_failed; 1384781a868fSWei Yang } while (test_and_set_bit(win, &phb->ioda.m64_bar_alloc)); 1385781a868fSWei Yang 1386ee8222feSWei Yang pdn->m64_map[j][i] = win; 138702639b0eSWei Yang 1388ee8222feSWei Yang if (pdn->m64_single_mode) { 138902639b0eSWei Yang size = pci_iov_resource_size(pdev, 139002639b0eSWei Yang PCI_IOV_RESOURCES + i); 139102639b0eSWei Yang start = res->start + size * j; 139202639b0eSWei Yang } else { 139302639b0eSWei Yang size = resource_size(res); 139402639b0eSWei Yang start = res->start; 139502639b0eSWei Yang } 1396781a868fSWei Yang 1397781a868fSWei Yang /* Map the M64 here */ 1398ee8222feSWei Yang if (pdn->m64_single_mode) { 1399be283eebSWei Yang pe_num = pdn->pe_num_map[j]; 140002639b0eSWei Yang rc = opal_pci_map_pe_mmio_window(phb->opal_id, 140102639b0eSWei Yang pe_num, OPAL_M64_WINDOW_TYPE, 1402ee8222feSWei Yang pdn->m64_map[j][i], 0); 140302639b0eSWei Yang } 140402639b0eSWei Yang 1405781a868fSWei Yang rc = opal_pci_set_phb_mem_window(phb->opal_id, 1406781a868fSWei Yang OPAL_M64_WINDOW_TYPE, 1407ee8222feSWei Yang pdn->m64_map[j][i], 140802639b0eSWei Yang start, 1409781a868fSWei Yang 0, /* unused */ 141002639b0eSWei Yang size); 141102639b0eSWei Yang 141202639b0eSWei Yang 1413781a868fSWei Yang if (rc != OPAL_SUCCESS) { 1414781a868fSWei Yang dev_err(&pdev->dev, "Failed to map M64 window #%d: %lld\n", 1415781a868fSWei Yang win, rc); 1416781a868fSWei Yang goto m64_failed; 1417781a868fSWei Yang } 1418781a868fSWei Yang 1419ee8222feSWei Yang if (pdn->m64_single_mode) 1420781a868fSWei Yang rc = opal_pci_phb_mmio_enable(phb->opal_id, 1421ee8222feSWei Yang OPAL_M64_WINDOW_TYPE, pdn->m64_map[j][i], 2); 142202639b0eSWei Yang else 142302639b0eSWei Yang rc = opal_pci_phb_mmio_enable(phb->opal_id, 1424ee8222feSWei Yang OPAL_M64_WINDOW_TYPE, pdn->m64_map[j][i], 1); 142502639b0eSWei Yang 1426781a868fSWei Yang if (rc != OPAL_SUCCESS) { 1427781a868fSWei Yang dev_err(&pdev->dev, "Failed to enable M64 window #%d: %llx\n", 1428781a868fSWei Yang win, rc); 1429781a868fSWei Yang goto m64_failed; 1430781a868fSWei Yang } 1431781a868fSWei Yang } 143202639b0eSWei Yang } 1433781a868fSWei Yang return 0; 1434781a868fSWei Yang 1435781a868fSWei Yang m64_failed: 1436ee8222feSWei Yang pnv_pci_vf_release_m64(pdev, num_vfs); 1437781a868fSWei Yang return -EBUSY; 1438781a868fSWei Yang } 1439781a868fSWei Yang 1440c035e37bSAlexey Kardashevskiy static long pnv_pci_ioda2_unset_window(struct iommu_table_group *table_group, 1441c035e37bSAlexey Kardashevskiy int num); 1442c035e37bSAlexey Kardashevskiy 1443781a868fSWei Yang static void pnv_pci_ioda2_release_dma_pe(struct pci_dev *dev, struct pnv_ioda_pe *pe) 1444781a868fSWei Yang { 1445781a868fSWei Yang struct iommu_table *tbl; 1446781a868fSWei Yang int64_t rc; 1447781a868fSWei Yang 1448b348aa65SAlexey Kardashevskiy tbl = pe->table_group.tables[0]; 1449c035e37bSAlexey Kardashevskiy rc = pnv_pci_ioda2_unset_window(&pe->table_group, 0); 1450781a868fSWei Yang if (rc) 14511e496391SJoe Perches pe_warn(pe, "OPAL error %lld release DMA window\n", rc); 1452781a868fSWei Yang 1453c035e37bSAlexey Kardashevskiy pnv_pci_ioda2_set_bypass(pe, false); 14540eaf4defSAlexey Kardashevskiy if (pe->table_group.group) { 14550eaf4defSAlexey Kardashevskiy iommu_group_put(pe->table_group.group); 14560eaf4defSAlexey Kardashevskiy BUG_ON(pe->table_group.group); 1457ac9a5889SAlexey Kardashevskiy } 1458e5afdf9dSAlexey Kardashevskiy iommu_tce_table_put(tbl); 1459781a868fSWei Yang } 1460781a868fSWei Yang 1461ee8222feSWei Yang static void pnv_ioda_release_vf_PE(struct pci_dev *pdev) 1462781a868fSWei Yang { 1463781a868fSWei Yang struct pci_bus *bus; 1464781a868fSWei Yang struct pci_controller *hose; 1465781a868fSWei Yang struct pnv_phb *phb; 1466781a868fSWei Yang struct pnv_ioda_pe *pe, *pe_n; 1467781a868fSWei Yang struct pci_dn *pdn; 1468781a868fSWei Yang 1469781a868fSWei Yang bus = pdev->bus; 1470781a868fSWei Yang hose = pci_bus_to_host(bus); 1471781a868fSWei Yang phb = hose->private_data; 147202639b0eSWei Yang pdn = pci_get_pdn(pdev); 1473781a868fSWei Yang 1474781a868fSWei Yang if (!pdev->is_physfn) 1475781a868fSWei Yang return; 1476781a868fSWei Yang 1477781a868fSWei Yang list_for_each_entry_safe(pe, pe_n, &phb->ioda.pe_list, list) { 1478781a868fSWei Yang if (pe->parent_dev != pdev) 1479781a868fSWei Yang continue; 1480781a868fSWei Yang 1481781a868fSWei Yang pnv_pci_ioda2_release_dma_pe(pdev, pe); 1482781a868fSWei Yang 1483781a868fSWei Yang /* Remove from list */ 1484781a868fSWei Yang mutex_lock(&phb->ioda.pe_list_mutex); 1485781a868fSWei Yang list_del(&pe->list); 1486781a868fSWei Yang mutex_unlock(&phb->ioda.pe_list_mutex); 1487781a868fSWei Yang 1488781a868fSWei Yang pnv_ioda_deconfigure_pe(phb, pe); 1489781a868fSWei Yang 14901e916772SGavin Shan pnv_ioda_free_pe(pe); 1491781a868fSWei Yang } 1492781a868fSWei Yang } 1493781a868fSWei Yang 1494781a868fSWei Yang void pnv_pci_sriov_disable(struct pci_dev *pdev) 1495781a868fSWei Yang { 1496781a868fSWei Yang struct pci_bus *bus; 1497781a868fSWei Yang struct pci_controller *hose; 1498781a868fSWei Yang struct pnv_phb *phb; 14991e916772SGavin Shan struct pnv_ioda_pe *pe; 1500781a868fSWei Yang struct pci_dn *pdn; 1501be283eebSWei Yang u16 num_vfs, i; 1502781a868fSWei Yang 1503781a868fSWei Yang bus = pdev->bus; 1504781a868fSWei Yang hose = pci_bus_to_host(bus); 1505781a868fSWei Yang phb = hose->private_data; 1506781a868fSWei Yang pdn = pci_get_pdn(pdev); 1507781a868fSWei Yang num_vfs = pdn->num_vfs; 1508781a868fSWei Yang 1509781a868fSWei Yang /* Release VF PEs */ 1510ee8222feSWei Yang pnv_ioda_release_vf_PE(pdev); 1511781a868fSWei Yang 1512781a868fSWei Yang if (phb->type == PNV_PHB_IODA2) { 1513ee8222feSWei Yang if (!pdn->m64_single_mode) 1514be283eebSWei Yang pnv_pci_vf_resource_shift(pdev, -*pdn->pe_num_map); 1515781a868fSWei Yang 1516781a868fSWei Yang /* Release M64 windows */ 1517ee8222feSWei Yang pnv_pci_vf_release_m64(pdev, num_vfs); 1518781a868fSWei Yang 1519781a868fSWei Yang /* Release PE numbers */ 1520be283eebSWei Yang if (pdn->m64_single_mode) { 1521be283eebSWei Yang for (i = 0; i < num_vfs; i++) { 15221e916772SGavin Shan if (pdn->pe_num_map[i] == IODA_INVALID_PE) 15231e916772SGavin Shan continue; 15241e916772SGavin Shan 15251e916772SGavin Shan pe = &phb->ioda.pe_array[pdn->pe_num_map[i]]; 15261e916772SGavin Shan pnv_ioda_free_pe(pe); 1527be283eebSWei Yang } 1528be283eebSWei Yang } else 1529be283eebSWei Yang bitmap_clear(phb->ioda.pe_alloc, *pdn->pe_num_map, num_vfs); 1530be283eebSWei Yang /* Releasing pe_num_map */ 1531be283eebSWei Yang kfree(pdn->pe_num_map); 1532781a868fSWei Yang } 1533781a868fSWei Yang } 1534781a868fSWei Yang 1535781a868fSWei Yang static void pnv_pci_ioda2_setup_dma_pe(struct pnv_phb *phb, 1536781a868fSWei Yang struct pnv_ioda_pe *pe); 1537781a868fSWei Yang static void pnv_ioda_setup_vf_PE(struct pci_dev *pdev, u16 num_vfs) 1538781a868fSWei Yang { 1539781a868fSWei Yang struct pci_bus *bus; 1540781a868fSWei Yang struct pci_controller *hose; 1541781a868fSWei Yang struct pnv_phb *phb; 1542781a868fSWei Yang struct pnv_ioda_pe *pe; 1543781a868fSWei Yang int pe_num; 1544781a868fSWei Yang u16 vf_index; 1545781a868fSWei Yang struct pci_dn *pdn; 1546781a868fSWei Yang 1547781a868fSWei Yang bus = pdev->bus; 1548781a868fSWei Yang hose = pci_bus_to_host(bus); 1549781a868fSWei Yang phb = hose->private_data; 1550781a868fSWei Yang pdn = pci_get_pdn(pdev); 1551781a868fSWei Yang 1552781a868fSWei Yang if (!pdev->is_physfn) 1553781a868fSWei Yang return; 1554781a868fSWei Yang 1555781a868fSWei Yang /* Reserve PE for each VF */ 1556781a868fSWei Yang for (vf_index = 0; vf_index < num_vfs; vf_index++) { 15573b5b9997SOliver O'Halloran int vf_devfn = pci_iov_virtfn_devfn(pdev, vf_index); 15583b5b9997SOliver O'Halloran int vf_bus = pci_iov_virtfn_bus(pdev, vf_index); 15593b5b9997SOliver O'Halloran struct pci_dn *vf_pdn; 15603b5b9997SOliver O'Halloran 1561be283eebSWei Yang if (pdn->m64_single_mode) 1562be283eebSWei Yang pe_num = pdn->pe_num_map[vf_index]; 1563be283eebSWei Yang else 1564be283eebSWei Yang pe_num = *pdn->pe_num_map + vf_index; 1565781a868fSWei Yang 1566781a868fSWei Yang pe = &phb->ioda.pe_array[pe_num]; 1567781a868fSWei Yang pe->pe_number = pe_num; 1568781a868fSWei Yang pe->phb = phb; 1569781a868fSWei Yang pe->flags = PNV_IODA_PE_VF; 1570781a868fSWei Yang pe->pbus = NULL; 1571781a868fSWei Yang pe->parent_dev = pdev; 1572781a868fSWei Yang pe->mve_number = -1; 15733b5b9997SOliver O'Halloran pe->rid = (vf_bus << 8) | vf_devfn; 1574781a868fSWei Yang 15751f52f176SRussell Currey pe_info(pe, "VF %04d:%02d:%02d.%d associated with PE#%x\n", 1576781a868fSWei Yang hose->global_number, pdev->bus->number, 15773b5b9997SOliver O'Halloran PCI_SLOT(vf_devfn), PCI_FUNC(vf_devfn), pe_num); 1578781a868fSWei Yang 1579781a868fSWei Yang if (pnv_ioda_configure_pe(phb, pe)) { 1580781a868fSWei Yang /* XXX What do we do here ? */ 15811e916772SGavin Shan pnv_ioda_free_pe(pe); 1582781a868fSWei Yang pe->pdev = NULL; 1583781a868fSWei Yang continue; 1584781a868fSWei Yang } 1585781a868fSWei Yang 1586781a868fSWei Yang /* Put PE to the list */ 1587781a868fSWei Yang mutex_lock(&phb->ioda.pe_list_mutex); 1588781a868fSWei Yang list_add_tail(&pe->list, &phb->ioda.pe_list); 1589781a868fSWei Yang mutex_unlock(&phb->ioda.pe_list_mutex); 1590781a868fSWei Yang 15913b5b9997SOliver O'Halloran /* associate this pe to it's pdn */ 15923b5b9997SOliver O'Halloran list_for_each_entry(vf_pdn, &pdn->parent->child_list, list) { 15933b5b9997SOliver O'Halloran if (vf_pdn->busno == vf_bus && 15943b5b9997SOliver O'Halloran vf_pdn->devfn == vf_devfn) { 15953b5b9997SOliver O'Halloran vf_pdn->pe_number = pe_num; 15963b5b9997SOliver O'Halloran break; 15973b5b9997SOliver O'Halloran } 15983b5b9997SOliver O'Halloran } 15993b5b9997SOliver O'Halloran 1600781a868fSWei Yang pnv_pci_ioda2_setup_dma_pe(phb, pe); 1601781a868fSWei Yang } 1602781a868fSWei Yang } 1603781a868fSWei Yang 1604781a868fSWei Yang int pnv_pci_sriov_enable(struct pci_dev *pdev, u16 num_vfs) 1605781a868fSWei Yang { 1606781a868fSWei Yang struct pci_bus *bus; 1607781a868fSWei Yang struct pci_controller *hose; 1608781a868fSWei Yang struct pnv_phb *phb; 16091e916772SGavin Shan struct pnv_ioda_pe *pe; 1610781a868fSWei Yang struct pci_dn *pdn; 1611781a868fSWei Yang int ret; 1612be283eebSWei Yang u16 i; 1613781a868fSWei Yang 1614781a868fSWei Yang bus = pdev->bus; 1615781a868fSWei Yang hose = pci_bus_to_host(bus); 1616781a868fSWei Yang phb = hose->private_data; 1617781a868fSWei Yang pdn = pci_get_pdn(pdev); 1618781a868fSWei Yang 1619781a868fSWei Yang if (phb->type == PNV_PHB_IODA2) { 1620b0331854SWei Yang if (!pdn->vfs_expanded) { 1621b0331854SWei Yang dev_info(&pdev->dev, "don't support this SRIOV device" 1622b0331854SWei Yang " with non 64bit-prefetchable IOV BAR\n"); 1623b0331854SWei Yang return -ENOSPC; 1624b0331854SWei Yang } 1625b0331854SWei Yang 1626ee8222feSWei Yang /* 1627ee8222feSWei Yang * When M64 BARs functions in Single PE mode, the number of VFs 1628ee8222feSWei Yang * could be enabled must be less than the number of M64 BARs. 1629ee8222feSWei Yang */ 1630ee8222feSWei Yang if (pdn->m64_single_mode && num_vfs > phb->ioda.m64_bar_idx) { 1631ee8222feSWei Yang dev_info(&pdev->dev, "Not enough M64 BAR for VFs\n"); 1632ee8222feSWei Yang return -EBUSY; 1633ee8222feSWei Yang } 1634ee8222feSWei Yang 1635be283eebSWei Yang /* Allocating pe_num_map */ 1636be283eebSWei Yang if (pdn->m64_single_mode) 1637fb37e128SMarkus Elfring pdn->pe_num_map = kmalloc_array(num_vfs, 1638fb37e128SMarkus Elfring sizeof(*pdn->pe_num_map), 1639be283eebSWei Yang GFP_KERNEL); 1640be283eebSWei Yang else 1641be283eebSWei Yang pdn->pe_num_map = kmalloc(sizeof(*pdn->pe_num_map), GFP_KERNEL); 1642be283eebSWei Yang 1643be283eebSWei Yang if (!pdn->pe_num_map) 1644be283eebSWei Yang return -ENOMEM; 1645be283eebSWei Yang 1646be283eebSWei Yang if (pdn->m64_single_mode) 1647be283eebSWei Yang for (i = 0; i < num_vfs; i++) 1648be283eebSWei Yang pdn->pe_num_map[i] = IODA_INVALID_PE; 1649be283eebSWei Yang 1650781a868fSWei Yang /* Calculate available PE for required VFs */ 1651be283eebSWei Yang if (pdn->m64_single_mode) { 1652be283eebSWei Yang for (i = 0; i < num_vfs; i++) { 16531e916772SGavin Shan pe = pnv_ioda_alloc_pe(phb); 16541e916772SGavin Shan if (!pe) { 1655be283eebSWei Yang ret = -EBUSY; 1656be283eebSWei Yang goto m64_failed; 1657be283eebSWei Yang } 16581e916772SGavin Shan 16591e916772SGavin Shan pdn->pe_num_map[i] = pe->pe_number; 1660be283eebSWei Yang } 1661be283eebSWei Yang } else { 1662781a868fSWei Yang mutex_lock(&phb->ioda.pe_alloc_mutex); 1663be283eebSWei Yang *pdn->pe_num_map = bitmap_find_next_zero_area( 166492b8f137SGavin Shan phb->ioda.pe_alloc, phb->ioda.total_pe_num, 1665781a868fSWei Yang 0, num_vfs, 0); 166692b8f137SGavin Shan if (*pdn->pe_num_map >= phb->ioda.total_pe_num) { 1667781a868fSWei Yang mutex_unlock(&phb->ioda.pe_alloc_mutex); 1668781a868fSWei Yang dev_info(&pdev->dev, "Failed to enable VF%d\n", num_vfs); 1669be283eebSWei Yang kfree(pdn->pe_num_map); 1670781a868fSWei Yang return -EBUSY; 1671781a868fSWei Yang } 1672be283eebSWei Yang bitmap_set(phb->ioda.pe_alloc, *pdn->pe_num_map, num_vfs); 1673781a868fSWei Yang mutex_unlock(&phb->ioda.pe_alloc_mutex); 1674be283eebSWei Yang } 1675be283eebSWei Yang pdn->num_vfs = num_vfs; 1676781a868fSWei Yang 1677781a868fSWei Yang /* Assign M64 window accordingly */ 167802639b0eSWei Yang ret = pnv_pci_vf_assign_m64(pdev, num_vfs); 1679781a868fSWei Yang if (ret) { 1680781a868fSWei Yang dev_info(&pdev->dev, "Not enough M64 window resources\n"); 1681781a868fSWei Yang goto m64_failed; 1682781a868fSWei Yang } 1683781a868fSWei Yang 1684781a868fSWei Yang /* 1685781a868fSWei Yang * When using one M64 BAR to map one IOV BAR, we need to shift 1686781a868fSWei Yang * the IOV BAR according to the PE# allocated to the VFs. 1687781a868fSWei Yang * Otherwise, the PE# for the VF will conflict with others. 1688781a868fSWei Yang */ 1689ee8222feSWei Yang if (!pdn->m64_single_mode) { 1690be283eebSWei Yang ret = pnv_pci_vf_resource_shift(pdev, *pdn->pe_num_map); 1691781a868fSWei Yang if (ret) 1692781a868fSWei Yang goto m64_failed; 1693781a868fSWei Yang } 169402639b0eSWei Yang } 1695781a868fSWei Yang 1696781a868fSWei Yang /* Setup VF PEs */ 1697781a868fSWei Yang pnv_ioda_setup_vf_PE(pdev, num_vfs); 1698781a868fSWei Yang 1699781a868fSWei Yang return 0; 1700781a868fSWei Yang 1701781a868fSWei Yang m64_failed: 1702be283eebSWei Yang if (pdn->m64_single_mode) { 1703be283eebSWei Yang for (i = 0; i < num_vfs; i++) { 17041e916772SGavin Shan if (pdn->pe_num_map[i] == IODA_INVALID_PE) 17051e916772SGavin Shan continue; 17061e916772SGavin Shan 17071e916772SGavin Shan pe = &phb->ioda.pe_array[pdn->pe_num_map[i]]; 17081e916772SGavin Shan pnv_ioda_free_pe(pe); 1709be283eebSWei Yang } 1710be283eebSWei Yang } else 1711be283eebSWei Yang bitmap_clear(phb->ioda.pe_alloc, *pdn->pe_num_map, num_vfs); 1712be283eebSWei Yang 1713be283eebSWei Yang /* Releasing pe_num_map */ 1714be283eebSWei Yang kfree(pdn->pe_num_map); 1715781a868fSWei Yang 1716781a868fSWei Yang return ret; 1717781a868fSWei Yang } 1718781a868fSWei Yang 1719988fc3baSBryant G. Ly int pnv_pcibios_sriov_disable(struct pci_dev *pdev) 1720a8b2f828SGavin Shan { 1721781a868fSWei Yang pnv_pci_sriov_disable(pdev); 1722781a868fSWei Yang 1723a8b2f828SGavin Shan /* Release PCI data */ 17248cd6aaccSOliver O'Halloran remove_sriov_vf_pdns(pdev); 1725a8b2f828SGavin Shan return 0; 1726a8b2f828SGavin Shan } 1727a8b2f828SGavin Shan 1728988fc3baSBryant G. Ly int pnv_pcibios_sriov_enable(struct pci_dev *pdev, u16 num_vfs) 1729a8b2f828SGavin Shan { 1730a8b2f828SGavin Shan /* Allocate PCI data */ 17318cd6aaccSOliver O'Halloran add_sriov_vf_pdns(pdev); 1732781a868fSWei Yang 1733ee8222feSWei Yang return pnv_pci_sriov_enable(pdev, num_vfs); 1734a8b2f828SGavin Shan } 1735a8b2f828SGavin Shan #endif /* CONFIG_PCI_IOV */ 1736a8b2f828SGavin Shan 17370a25d9c4SOliver O'Halloran static void pnv_pci_ioda_dma_dev_setup(struct pci_dev *pdev) 1738184cd4a3SBenjamin Herrenschmidt { 17390a25d9c4SOliver O'Halloran struct pci_controller *hose = pci_bus_to_host(pdev->bus); 17400a25d9c4SOliver O'Halloran struct pnv_phb *phb = hose->private_data; 1741b72c1f65SBenjamin Herrenschmidt struct pci_dn *pdn = pci_get_pdn(pdev); 1742959c9bddSGavin Shan struct pnv_ioda_pe *pe; 1743184cd4a3SBenjamin Herrenschmidt 1744dc3d8f85SOliver O'Halloran /* Check if the BDFN for this device is associated with a PE yet */ 1745dc3d8f85SOliver O'Halloran pe = pnv_pci_bdfn_to_pe(phb, pdev->devfn | (pdev->bus->number << 8)); 1746dc3d8f85SOliver O'Halloran if (!pe) { 1747dc3d8f85SOliver O'Halloran /* VF PEs should be pre-configured in pnv_pci_sriov_enable() */ 1748dc3d8f85SOliver O'Halloran if (WARN_ON(pdev->is_virtfn)) 1749959c9bddSGavin Shan return; 1750184cd4a3SBenjamin Herrenschmidt 1751dc3d8f85SOliver O'Halloran pnv_pci_configure_bus(pdev->bus); 1752dc3d8f85SOliver O'Halloran pe = pnv_pci_bdfn_to_pe(phb, pdev->devfn | (pdev->bus->number << 8)); 1753dc3d8f85SOliver O'Halloran pci_info(pdev, "Configured PE#%x\n", pe ? pe->pe_number : 0xfffff); 1754dc3d8f85SOliver O'Halloran 1755dc3d8f85SOliver O'Halloran 1756dc3d8f85SOliver O'Halloran /* 1757dc3d8f85SOliver O'Halloran * If we can't setup the IODA PE something has gone horribly 1758dc3d8f85SOliver O'Halloran * wrong and we can't enable DMA for the device. 1759dc3d8f85SOliver O'Halloran */ 1760dc3d8f85SOliver O'Halloran if (WARN_ON(!pe)) 1761dc3d8f85SOliver O'Halloran return; 1762dc3d8f85SOliver O'Halloran } else { 1763dc3d8f85SOliver O'Halloran pci_info(pdev, "Added to existing PE#%x\n", pe->pe_number); 1764dc3d8f85SOliver O'Halloran } 1765dc3d8f85SOliver O'Halloran 1766dc3d8f85SOliver O'Halloran if (pdn) 1767dc3d8f85SOliver O'Halloran pdn->pe_number = pe->pe_number; 1768dc3d8f85SOliver O'Halloran pe->device_count++; 1769dc3d8f85SOliver O'Halloran 1770cd15b048SBenjamin Herrenschmidt WARN_ON(get_dma_ops(&pdev->dev) != &dma_iommu_ops); 17710617fc0cSChristoph Hellwig pdev->dev.archdata.dma_offset = pe->tce_bypass_base; 1772b348aa65SAlexey Kardashevskiy set_iommu_table_base(&pdev->dev, pe->table_group.tables[0]); 177384d8cc07SOliver O'Halloran 177484d8cc07SOliver O'Halloran /* PEs with a DMA weight of zero won't have a group */ 177584d8cc07SOliver O'Halloran if (pe->table_group.group) 177684d8cc07SOliver O'Halloran iommu_add_device(&pe->table_group, &pdev->dev); 1777184cd4a3SBenjamin Herrenschmidt } 1778184cd4a3SBenjamin Herrenschmidt 17798e3f1b1dSRussell Currey /* 17808e3f1b1dSRussell Currey * Reconfigure TVE#0 to be usable as 64-bit DMA space. 17818e3f1b1dSRussell Currey * 17828e3f1b1dSRussell Currey * The first 4GB of virtual memory for a PE is reserved for 32-bit accesses. 17838e3f1b1dSRussell Currey * Devices can only access more than that if bit 59 of the PCI address is set 17848e3f1b1dSRussell Currey * by hardware, which indicates TVE#1 should be used instead of TVE#0. 17858e3f1b1dSRussell Currey * Many PCI devices are not capable of addressing that many bits, and as a 17868e3f1b1dSRussell Currey * result are limited to the 4GB of virtual memory made available to 32-bit 17878e3f1b1dSRussell Currey * devices in TVE#0. 17888e3f1b1dSRussell Currey * 17898e3f1b1dSRussell Currey * In order to work around this, reconfigure TVE#0 to be suitable for 64-bit 17908e3f1b1dSRussell Currey * devices by configuring the virtual memory past the first 4GB inaccessible 17918e3f1b1dSRussell Currey * by 64-bit DMAs. This should only be used by devices that want more than 17928e3f1b1dSRussell Currey * 4GB, and only on PEs that have no 32-bit devices. 17938e3f1b1dSRussell Currey * 17948e3f1b1dSRussell Currey * Currently this will only work on PHB3 (POWER8). 17958e3f1b1dSRussell Currey */ 17968e3f1b1dSRussell Currey static int pnv_pci_ioda_dma_64bit_bypass(struct pnv_ioda_pe *pe) 17978e3f1b1dSRussell Currey { 17988e3f1b1dSRussell Currey u64 window_size, table_size, tce_count, addr; 17998e3f1b1dSRussell Currey struct page *table_pages; 18008e3f1b1dSRussell Currey u64 tce_order = 28; /* 256MB TCEs */ 18018e3f1b1dSRussell Currey __be64 *tces; 18028e3f1b1dSRussell Currey s64 rc; 18038e3f1b1dSRussell Currey 18048e3f1b1dSRussell Currey /* 18058e3f1b1dSRussell Currey * Window size needs to be a power of two, but needs to account for 18068e3f1b1dSRussell Currey * shifting memory by the 4GB offset required to skip 32bit space. 18078e3f1b1dSRussell Currey */ 18088e3f1b1dSRussell Currey window_size = roundup_pow_of_two(memory_hotplug_max() + (1ULL << 32)); 18098e3f1b1dSRussell Currey tce_count = window_size >> tce_order; 18108e3f1b1dSRussell Currey table_size = tce_count << 3; 18118e3f1b1dSRussell Currey 18128e3f1b1dSRussell Currey if (table_size < PAGE_SIZE) 18138e3f1b1dSRussell Currey table_size = PAGE_SIZE; 18148e3f1b1dSRussell Currey 18158e3f1b1dSRussell Currey table_pages = alloc_pages_node(pe->phb->hose->node, GFP_KERNEL, 18168e3f1b1dSRussell Currey get_order(table_size)); 18178e3f1b1dSRussell Currey if (!table_pages) 18188e3f1b1dSRussell Currey goto err; 18198e3f1b1dSRussell Currey 18208e3f1b1dSRussell Currey tces = page_address(table_pages); 18218e3f1b1dSRussell Currey if (!tces) 18228e3f1b1dSRussell Currey goto err; 18238e3f1b1dSRussell Currey 18248e3f1b1dSRussell Currey memset(tces, 0, table_size); 18258e3f1b1dSRussell Currey 18268e3f1b1dSRussell Currey for (addr = 0; addr < memory_hotplug_max(); addr += (1 << tce_order)) { 18278e3f1b1dSRussell Currey tces[(addr + (1ULL << 32)) >> tce_order] = 18288e3f1b1dSRussell Currey cpu_to_be64(addr | TCE_PCI_READ | TCE_PCI_WRITE); 18298e3f1b1dSRussell Currey } 18308e3f1b1dSRussell Currey 18318e3f1b1dSRussell Currey rc = opal_pci_map_pe_dma_window(pe->phb->opal_id, 18328e3f1b1dSRussell Currey pe->pe_number, 18338e3f1b1dSRussell Currey /* reconfigure window 0 */ 18348e3f1b1dSRussell Currey (pe->pe_number << 1) + 0, 18358e3f1b1dSRussell Currey 1, 18368e3f1b1dSRussell Currey __pa(tces), 18378e3f1b1dSRussell Currey table_size, 18388e3f1b1dSRussell Currey 1 << tce_order); 18398e3f1b1dSRussell Currey if (rc == OPAL_SUCCESS) { 18408e3f1b1dSRussell Currey pe_info(pe, "Using 64-bit DMA iommu bypass (through TVE#0)\n"); 18418e3f1b1dSRussell Currey return 0; 18428e3f1b1dSRussell Currey } 18438e3f1b1dSRussell Currey err: 18448e3f1b1dSRussell Currey pe_err(pe, "Error configuring 64-bit DMA bypass\n"); 18458e3f1b1dSRussell Currey return -EIO; 18468e3f1b1dSRussell Currey } 18478e3f1b1dSRussell Currey 18482d6ad41bSChristoph Hellwig static bool pnv_pci_ioda_iommu_bypass_supported(struct pci_dev *pdev, 18492d6ad41bSChristoph Hellwig u64 dma_mask) 1850cd15b048SBenjamin Herrenschmidt { 1851763d2d8dSDaniel Axtens struct pci_controller *hose = pci_bus_to_host(pdev->bus); 1852763d2d8dSDaniel Axtens struct pnv_phb *phb = hose->private_data; 1853cd15b048SBenjamin Herrenschmidt struct pci_dn *pdn = pci_get_pdn(pdev); 1854cd15b048SBenjamin Herrenschmidt struct pnv_ioda_pe *pe; 1855cd15b048SBenjamin Herrenschmidt 1856cd15b048SBenjamin Herrenschmidt if (WARN_ON(!pdn || pdn->pe_number == IODA_INVALID_PE)) 1857b511cdd1SAlexey Kardashevskiy return false; 1858cd15b048SBenjamin Herrenschmidt 1859cd15b048SBenjamin Herrenschmidt pe = &phb->ioda.pe_array[pdn->pe_number]; 1860cd15b048SBenjamin Herrenschmidt if (pe->tce_bypass_enabled) { 18612d6ad41bSChristoph Hellwig u64 top = pe->tce_bypass_base + memblock_end_of_DRAM() - 1; 18622d6ad41bSChristoph Hellwig if (dma_mask >= top) 18632d6ad41bSChristoph Hellwig return true; 1864cd15b048SBenjamin Herrenschmidt } 1865cd15b048SBenjamin Herrenschmidt 18668e3f1b1dSRussell Currey /* 18678e3f1b1dSRussell Currey * If the device can't set the TCE bypass bit but still wants 18688e3f1b1dSRussell Currey * to access 4GB or more, on PHB3 we can reconfigure TVE#0 to 18698e3f1b1dSRussell Currey * bypass the 32-bit region and be usable for 64-bit DMAs. 18708e3f1b1dSRussell Currey * The device needs to be able to address all of this space. 18718e3f1b1dSRussell Currey */ 18728e3f1b1dSRussell Currey if (dma_mask >> 32 && 18738e3f1b1dSRussell Currey dma_mask > (memory_hotplug_max() + (1ULL << 32)) && 1874661fcb45SChristoph Hellwig /* pe->pdev should be set if it's a single device, pe->pbus if not */ 1875661fcb45SChristoph Hellwig (pe->device_count == 1 || !pe->pbus) && 18768e3f1b1dSRussell Currey phb->model == PNV_PHB_MODEL_PHB3) { 18778e3f1b1dSRussell Currey /* Configure the bypass mode */ 18782d6ad41bSChristoph Hellwig s64 rc = pnv_pci_ioda_dma_64bit_bypass(pe); 18798e3f1b1dSRussell Currey if (rc) 1880b511cdd1SAlexey Kardashevskiy return false; 18818e3f1b1dSRussell Currey /* 4GB offset bypasses 32-bit space */ 18820617fc0cSChristoph Hellwig pdev->dev.archdata.dma_offset = (1ULL << 32); 18832d6ad41bSChristoph Hellwig return true; 1884cd15b048SBenjamin Herrenschmidt } 1885cd15b048SBenjamin Herrenschmidt 18862d6ad41bSChristoph Hellwig return false; 1887fe7e85c6SGavin Shan } 1888fe7e85c6SGavin Shan 18895eada8a3SAlexey Kardashevskiy static void pnv_ioda_setup_bus_dma(struct pnv_ioda_pe *pe, struct pci_bus *bus) 189074251fe2SBenjamin Herrenschmidt { 189174251fe2SBenjamin Herrenschmidt struct pci_dev *dev; 189274251fe2SBenjamin Herrenschmidt 189374251fe2SBenjamin Herrenschmidt list_for_each_entry(dev, &bus->devices, bus_list) { 1894b348aa65SAlexey Kardashevskiy set_iommu_table_base(&dev->dev, pe->table_group.tables[0]); 18950617fc0cSChristoph Hellwig dev->dev.archdata.dma_offset = pe->tce_bypass_base; 1896dff4a39eSGavin Shan 18975c89a87dSAlexey Kardashevskiy if ((pe->flags & PNV_IODA_PE_BUS_ALL) && dev->subordinate) 18985eada8a3SAlexey Kardashevskiy pnv_ioda_setup_bus_dma(pe, dev->subordinate); 189974251fe2SBenjamin Herrenschmidt } 190074251fe2SBenjamin Herrenschmidt } 190174251fe2SBenjamin Herrenschmidt 1902fd141d1aSBenjamin Herrenschmidt static inline __be64 __iomem *pnv_ioda_get_inval_reg(struct pnv_phb *phb, 1903fd141d1aSBenjamin Herrenschmidt bool real_mode) 1904fd141d1aSBenjamin Herrenschmidt { 1905fd141d1aSBenjamin Herrenschmidt return real_mode ? (__be64 __iomem *)(phb->regs_phys + 0x210) : 1906fd141d1aSBenjamin Herrenschmidt (phb->regs + 0x210); 1907fd141d1aSBenjamin Herrenschmidt } 1908fd141d1aSBenjamin Herrenschmidt 1909a34ab7c3SBenjamin Herrenschmidt static void pnv_pci_p7ioc_tce_invalidate(struct iommu_table *tbl, 1910decbda25SAlexey Kardashevskiy unsigned long index, unsigned long npages, bool rm) 19114cce9550SGavin Shan { 19120eaf4defSAlexey Kardashevskiy struct iommu_table_group_link *tgl = list_first_entry_or_null( 19130eaf4defSAlexey Kardashevskiy &tbl->it_group_list, struct iommu_table_group_link, 19140eaf4defSAlexey Kardashevskiy next); 19150eaf4defSAlexey Kardashevskiy struct pnv_ioda_pe *pe = container_of(tgl->table_group, 1916b348aa65SAlexey Kardashevskiy struct pnv_ioda_pe, table_group); 1917fd141d1aSBenjamin Herrenschmidt __be64 __iomem *invalidate = pnv_ioda_get_inval_reg(pe->phb, rm); 19184cce9550SGavin Shan unsigned long start, end, inc; 19194cce9550SGavin Shan 1920decbda25SAlexey Kardashevskiy start = __pa(((__be64 *)tbl->it_base) + index - tbl->it_offset); 1921decbda25SAlexey Kardashevskiy end = __pa(((__be64 *)tbl->it_base) + index - tbl->it_offset + 1922decbda25SAlexey Kardashevskiy npages - 1); 19234cce9550SGavin Shan 19244cce9550SGavin Shan /* p7ioc-style invalidation, 2 TCEs per write */ 19254cce9550SGavin Shan start |= (1ull << 63); 19264cce9550SGavin Shan end |= (1ull << 63); 19274cce9550SGavin Shan inc = 16; 19284cce9550SGavin Shan end |= inc - 1; /* round up end to be different than start */ 19294cce9550SGavin Shan 19304cce9550SGavin Shan mb(); /* Ensure above stores are visible */ 19314cce9550SGavin Shan while (start <= end) { 19328e0a1611SAlexey Kardashevskiy if (rm) 1933001ff2eeSMichael Ellerman __raw_rm_writeq_be(start, invalidate); 19348e0a1611SAlexey Kardashevskiy else 1935001ff2eeSMichael Ellerman __raw_writeq_be(start, invalidate); 1936001ff2eeSMichael Ellerman 19374cce9550SGavin Shan start += inc; 19384cce9550SGavin Shan } 19394cce9550SGavin Shan 19404cce9550SGavin Shan /* 19414cce9550SGavin Shan * The iommu layer will do another mb() for us on build() 19424cce9550SGavin Shan * and we don't care on free() 19434cce9550SGavin Shan */ 19444cce9550SGavin Shan } 19454cce9550SGavin Shan 1946decbda25SAlexey Kardashevskiy static int pnv_ioda1_tce_build(struct iommu_table *tbl, long index, 1947decbda25SAlexey Kardashevskiy long npages, unsigned long uaddr, 1948decbda25SAlexey Kardashevskiy enum dma_data_direction direction, 194900085f1eSKrzysztof Kozlowski unsigned long attrs) 1950decbda25SAlexey Kardashevskiy { 1951decbda25SAlexey Kardashevskiy int ret = pnv_tce_build(tbl, index, npages, uaddr, direction, 1952decbda25SAlexey Kardashevskiy attrs); 1953decbda25SAlexey Kardashevskiy 195408acce1cSBenjamin Herrenschmidt if (!ret) 1955a34ab7c3SBenjamin Herrenschmidt pnv_pci_p7ioc_tce_invalidate(tbl, index, npages, false); 1956decbda25SAlexey Kardashevskiy 1957decbda25SAlexey Kardashevskiy return ret; 1958decbda25SAlexey Kardashevskiy } 1959decbda25SAlexey Kardashevskiy 196005c6cfb9SAlexey Kardashevskiy #ifdef CONFIG_IOMMU_API 196135872480SAlexey Kardashevskiy /* Common for IODA1 and IODA2 */ 196235872480SAlexey Kardashevskiy static int pnv_ioda_tce_xchg_no_kill(struct iommu_table *tbl, long index, 196335872480SAlexey Kardashevskiy unsigned long *hpa, enum dma_data_direction *direction, 196435872480SAlexey Kardashevskiy bool realmode) 196505c6cfb9SAlexey Kardashevskiy { 196635872480SAlexey Kardashevskiy return pnv_tce_xchg(tbl, index, hpa, direction, !realmode); 1967a540aa56SAlexey Kardashevskiy } 196805c6cfb9SAlexey Kardashevskiy #endif 196905c6cfb9SAlexey Kardashevskiy 1970decbda25SAlexey Kardashevskiy static void pnv_ioda1_tce_free(struct iommu_table *tbl, long index, 1971decbda25SAlexey Kardashevskiy long npages) 1972decbda25SAlexey Kardashevskiy { 1973decbda25SAlexey Kardashevskiy pnv_tce_free(tbl, index, npages); 1974decbda25SAlexey Kardashevskiy 1975a34ab7c3SBenjamin Herrenschmidt pnv_pci_p7ioc_tce_invalidate(tbl, index, npages, false); 1976decbda25SAlexey Kardashevskiy } 1977decbda25SAlexey Kardashevskiy 1978da004c36SAlexey Kardashevskiy static struct iommu_table_ops pnv_ioda1_iommu_ops = { 1979decbda25SAlexey Kardashevskiy .set = pnv_ioda1_tce_build, 198005c6cfb9SAlexey Kardashevskiy #ifdef CONFIG_IOMMU_API 198135872480SAlexey Kardashevskiy .xchg_no_kill = pnv_ioda_tce_xchg_no_kill, 198235872480SAlexey Kardashevskiy .tce_kill = pnv_pci_p7ioc_tce_invalidate, 1983090bad39SAlexey Kardashevskiy .useraddrptr = pnv_tce_useraddrptr, 198405c6cfb9SAlexey Kardashevskiy #endif 1985decbda25SAlexey Kardashevskiy .clear = pnv_ioda1_tce_free, 1986da004c36SAlexey Kardashevskiy .get = pnv_tce_get, 1987da004c36SAlexey Kardashevskiy }; 1988da004c36SAlexey Kardashevskiy 1989a34ab7c3SBenjamin Herrenschmidt #define PHB3_TCE_KILL_INVAL_ALL PPC_BIT(0) 1990a34ab7c3SBenjamin Herrenschmidt #define PHB3_TCE_KILL_INVAL_PE PPC_BIT(1) 1991a34ab7c3SBenjamin Herrenschmidt #define PHB3_TCE_KILL_INVAL_ONE PPC_BIT(2) 1992bef9253fSAlexey Kardashevskiy 19936b3d12a9SAlistair Popple static void pnv_pci_phb3_tce_invalidate_entire(struct pnv_phb *phb, bool rm) 19940bbcdb43SAlexey Kardashevskiy { 1995fd141d1aSBenjamin Herrenschmidt __be64 __iomem *invalidate = pnv_ioda_get_inval_reg(phb, rm); 1996a34ab7c3SBenjamin Herrenschmidt const unsigned long val = PHB3_TCE_KILL_INVAL_ALL; 19970bbcdb43SAlexey Kardashevskiy 19980bbcdb43SAlexey Kardashevskiy mb(); /* Ensure previous TCE table stores are visible */ 19990bbcdb43SAlexey Kardashevskiy if (rm) 2000001ff2eeSMichael Ellerman __raw_rm_writeq_be(val, invalidate); 20010bbcdb43SAlexey Kardashevskiy else 2002001ff2eeSMichael Ellerman __raw_writeq_be(val, invalidate); 20030bbcdb43SAlexey Kardashevskiy } 20040bbcdb43SAlexey Kardashevskiy 2005a34ab7c3SBenjamin Herrenschmidt static inline void pnv_pci_phb3_tce_invalidate_pe(struct pnv_ioda_pe *pe) 20065780fb04SAlexey Kardashevskiy { 20075780fb04SAlexey Kardashevskiy /* 01xb - invalidate TCEs that match the specified PE# */ 2008fd141d1aSBenjamin Herrenschmidt __be64 __iomem *invalidate = pnv_ioda_get_inval_reg(pe->phb, false); 2009a34ab7c3SBenjamin Herrenschmidt unsigned long val = PHB3_TCE_KILL_INVAL_PE | (pe->pe_number & 0xFF); 20105780fb04SAlexey Kardashevskiy 20115780fb04SAlexey Kardashevskiy mb(); /* Ensure above stores are visible */ 2012001ff2eeSMichael Ellerman __raw_writeq_be(val, invalidate); 20135780fb04SAlexey Kardashevskiy } 20145780fb04SAlexey Kardashevskiy 2015fd141d1aSBenjamin Herrenschmidt static void pnv_pci_phb3_tce_invalidate(struct pnv_ioda_pe *pe, bool rm, 2016fd141d1aSBenjamin Herrenschmidt unsigned shift, unsigned long index, 2017fd141d1aSBenjamin Herrenschmidt unsigned long npages) 20184cce9550SGavin Shan { 20194d902195SAlexey Kardashevskiy __be64 __iomem *invalidate = pnv_ioda_get_inval_reg(pe->phb, rm); 20204cce9550SGavin Shan unsigned long start, end, inc; 20214cce9550SGavin Shan 20224cce9550SGavin Shan /* We'll invalidate DMA address in PE scope */ 2023a34ab7c3SBenjamin Herrenschmidt start = PHB3_TCE_KILL_INVAL_ONE; 2024fd141d1aSBenjamin Herrenschmidt start |= (pe->pe_number & 0xFF); 20254cce9550SGavin Shan end = start; 20264cce9550SGavin Shan 20274cce9550SGavin Shan /* Figure out the start, end and step */ 2028decbda25SAlexey Kardashevskiy start |= (index << shift); 2029decbda25SAlexey Kardashevskiy end |= ((index + npages - 1) << shift); 2030b0376c9bSAlexey Kardashevskiy inc = (0x1ull << shift); 20314cce9550SGavin Shan mb(); 20324cce9550SGavin Shan 20334cce9550SGavin Shan while (start <= end) { 20348e0a1611SAlexey Kardashevskiy if (rm) 2035001ff2eeSMichael Ellerman __raw_rm_writeq_be(start, invalidate); 20368e0a1611SAlexey Kardashevskiy else 2037001ff2eeSMichael Ellerman __raw_writeq_be(start, invalidate); 20384cce9550SGavin Shan start += inc; 20394cce9550SGavin Shan } 20404cce9550SGavin Shan } 20414cce9550SGavin Shan 2042f0228c41SBenjamin Herrenschmidt static inline void pnv_pci_ioda2_tce_invalidate_pe(struct pnv_ioda_pe *pe) 2043f0228c41SBenjamin Herrenschmidt { 2044f0228c41SBenjamin Herrenschmidt struct pnv_phb *phb = pe->phb; 2045f0228c41SBenjamin Herrenschmidt 2046f0228c41SBenjamin Herrenschmidt if (phb->model == PNV_PHB_MODEL_PHB3 && phb->regs) 2047f0228c41SBenjamin Herrenschmidt pnv_pci_phb3_tce_invalidate_pe(pe); 2048f0228c41SBenjamin Herrenschmidt else 2049f0228c41SBenjamin Herrenschmidt opal_pci_tce_kill(phb->opal_id, OPAL_PCI_TCE_KILL_PE, 2050f0228c41SBenjamin Herrenschmidt pe->pe_number, 0, 0, 0); 2051f0228c41SBenjamin Herrenschmidt } 2052f0228c41SBenjamin Herrenschmidt 2053e57080f1SAlexey Kardashevskiy static void pnv_pci_ioda2_tce_invalidate(struct iommu_table *tbl, 2054e57080f1SAlexey Kardashevskiy unsigned long index, unsigned long npages, bool rm) 2055e57080f1SAlexey Kardashevskiy { 2056e57080f1SAlexey Kardashevskiy struct iommu_table_group_link *tgl; 2057e57080f1SAlexey Kardashevskiy 2058a540aa56SAlexey Kardashevskiy list_for_each_entry_lockless(tgl, &tbl->it_group_list, next) { 2059e57080f1SAlexey Kardashevskiy struct pnv_ioda_pe *pe = container_of(tgl->table_group, 2060e57080f1SAlexey Kardashevskiy struct pnv_ioda_pe, table_group); 2061f0228c41SBenjamin Herrenschmidt struct pnv_phb *phb = pe->phb; 2062f0228c41SBenjamin Herrenschmidt unsigned int shift = tbl->it_page_shift; 2063f0228c41SBenjamin Herrenschmidt 2064616badd2SAlistair Popple /* 2065616badd2SAlistair Popple * NVLink1 can use the TCE kill register directly as 2066616badd2SAlistair Popple * it's the same as PHB3. NVLink2 is different and 2067616badd2SAlistair Popple * should go via the OPAL call. 2068616badd2SAlistair Popple */ 2069616badd2SAlistair Popple if (phb->model == PNV_PHB_MODEL_NPU) { 20700bbcdb43SAlexey Kardashevskiy /* 20710bbcdb43SAlexey Kardashevskiy * The NVLink hardware does not support TCE kill 20720bbcdb43SAlexey Kardashevskiy * per TCE entry so we have to invalidate 20730bbcdb43SAlexey Kardashevskiy * the entire cache for it. 20740bbcdb43SAlexey Kardashevskiy */ 2075f0228c41SBenjamin Herrenschmidt pnv_pci_phb3_tce_invalidate_entire(phb, rm); 20765d2aa710SAlistair Popple continue; 20775d2aa710SAlistair Popple } 2078f0228c41SBenjamin Herrenschmidt if (phb->model == PNV_PHB_MODEL_PHB3 && phb->regs) 2079f0228c41SBenjamin Herrenschmidt pnv_pci_phb3_tce_invalidate(pe, rm, shift, 208085674868SAlexey Kardashevskiy index, npages); 2081f0228c41SBenjamin Herrenschmidt else 2082f0228c41SBenjamin Herrenschmidt opal_pci_tce_kill(phb->opal_id, 2083f0228c41SBenjamin Herrenschmidt OPAL_PCI_TCE_KILL_PAGES, 2084f0228c41SBenjamin Herrenschmidt pe->pe_number, 1u << shift, 2085f0228c41SBenjamin Herrenschmidt index << shift, npages); 2086e57080f1SAlexey Kardashevskiy } 2087e57080f1SAlexey Kardashevskiy } 2088e57080f1SAlexey Kardashevskiy 20896b3d12a9SAlistair Popple void pnv_pci_ioda2_tce_invalidate_entire(struct pnv_phb *phb, bool rm) 20906b3d12a9SAlistair Popple { 20916b3d12a9SAlistair Popple if (phb->model == PNV_PHB_MODEL_NPU || phb->model == PNV_PHB_MODEL_PHB3) 20926b3d12a9SAlistair Popple pnv_pci_phb3_tce_invalidate_entire(phb, rm); 20936b3d12a9SAlistair Popple else 20946b3d12a9SAlistair Popple opal_pci_tce_kill(phb->opal_id, OPAL_PCI_TCE_KILL, 0, 0, 0, 0); 20956b3d12a9SAlistair Popple } 20966b3d12a9SAlistair Popple 2097decbda25SAlexey Kardashevskiy static int pnv_ioda2_tce_build(struct iommu_table *tbl, long index, 2098decbda25SAlexey Kardashevskiy long npages, unsigned long uaddr, 2099decbda25SAlexey Kardashevskiy enum dma_data_direction direction, 210000085f1eSKrzysztof Kozlowski unsigned long attrs) 21014cce9550SGavin Shan { 2102decbda25SAlexey Kardashevskiy int ret = pnv_tce_build(tbl, index, npages, uaddr, direction, 2103decbda25SAlexey Kardashevskiy attrs); 21044cce9550SGavin Shan 210508acce1cSBenjamin Herrenschmidt if (!ret) 2106decbda25SAlexey Kardashevskiy pnv_pci_ioda2_tce_invalidate(tbl, index, npages, false); 2107decbda25SAlexey Kardashevskiy 2108decbda25SAlexey Kardashevskiy return ret; 2109decbda25SAlexey Kardashevskiy } 2110decbda25SAlexey Kardashevskiy 2111decbda25SAlexey Kardashevskiy static void pnv_ioda2_tce_free(struct iommu_table *tbl, long index, 2112decbda25SAlexey Kardashevskiy long npages) 2113decbda25SAlexey Kardashevskiy { 2114decbda25SAlexey Kardashevskiy pnv_tce_free(tbl, index, npages); 2115decbda25SAlexey Kardashevskiy 2116decbda25SAlexey Kardashevskiy pnv_pci_ioda2_tce_invalidate(tbl, index, npages, false); 21174cce9550SGavin Shan } 21184cce9550SGavin Shan 2119da004c36SAlexey Kardashevskiy static struct iommu_table_ops pnv_ioda2_iommu_ops = { 2120decbda25SAlexey Kardashevskiy .set = pnv_ioda2_tce_build, 212105c6cfb9SAlexey Kardashevskiy #ifdef CONFIG_IOMMU_API 212235872480SAlexey Kardashevskiy .xchg_no_kill = pnv_ioda_tce_xchg_no_kill, 212335872480SAlexey Kardashevskiy .tce_kill = pnv_pci_ioda2_tce_invalidate, 2124090bad39SAlexey Kardashevskiy .useraddrptr = pnv_tce_useraddrptr, 212505c6cfb9SAlexey Kardashevskiy #endif 2126decbda25SAlexey Kardashevskiy .clear = pnv_ioda2_tce_free, 2127da004c36SAlexey Kardashevskiy .get = pnv_tce_get, 2128da2bb0daSAlexey Kardashevskiy .free = pnv_pci_ioda2_table_free_pages, 2129da004c36SAlexey Kardashevskiy }; 2130da004c36SAlexey Kardashevskiy 2131801846d1SGavin Shan static int pnv_pci_ioda_dev_dma_weight(struct pci_dev *dev, void *data) 2132801846d1SGavin Shan { 2133801846d1SGavin Shan unsigned int *weight = (unsigned int *)data; 2134801846d1SGavin Shan 2135801846d1SGavin Shan /* This is quite simplistic. The "base" weight of a device 2136801846d1SGavin Shan * is 10. 0 means no DMA is to be accounted for it. 2137801846d1SGavin Shan */ 2138801846d1SGavin Shan if (dev->hdr_type != PCI_HEADER_TYPE_NORMAL) 2139801846d1SGavin Shan return 0; 2140801846d1SGavin Shan 2141801846d1SGavin Shan if (dev->class == PCI_CLASS_SERIAL_USB_UHCI || 2142801846d1SGavin Shan dev->class == PCI_CLASS_SERIAL_USB_OHCI || 2143801846d1SGavin Shan dev->class == PCI_CLASS_SERIAL_USB_EHCI) 2144801846d1SGavin Shan *weight += 3; 2145801846d1SGavin Shan else if ((dev->class >> 8) == PCI_CLASS_STORAGE_RAID) 2146801846d1SGavin Shan *weight += 15; 2147801846d1SGavin Shan else 2148801846d1SGavin Shan *weight += 10; 2149801846d1SGavin Shan 2150801846d1SGavin Shan return 0; 2151801846d1SGavin Shan } 2152801846d1SGavin Shan 2153801846d1SGavin Shan static unsigned int pnv_pci_ioda_pe_dma_weight(struct pnv_ioda_pe *pe) 2154801846d1SGavin Shan { 2155801846d1SGavin Shan unsigned int weight = 0; 2156801846d1SGavin Shan 2157801846d1SGavin Shan /* SRIOV VF has same DMA32 weight as its PF */ 2158801846d1SGavin Shan #ifdef CONFIG_PCI_IOV 2159801846d1SGavin Shan if ((pe->flags & PNV_IODA_PE_VF) && pe->parent_dev) { 2160801846d1SGavin Shan pnv_pci_ioda_dev_dma_weight(pe->parent_dev, &weight); 2161801846d1SGavin Shan return weight; 2162801846d1SGavin Shan } 2163801846d1SGavin Shan #endif 2164801846d1SGavin Shan 2165801846d1SGavin Shan if ((pe->flags & PNV_IODA_PE_DEV) && pe->pdev) { 2166801846d1SGavin Shan pnv_pci_ioda_dev_dma_weight(pe->pdev, &weight); 2167801846d1SGavin Shan } else if ((pe->flags & PNV_IODA_PE_BUS) && pe->pbus) { 2168801846d1SGavin Shan struct pci_dev *pdev; 2169801846d1SGavin Shan 2170801846d1SGavin Shan list_for_each_entry(pdev, &pe->pbus->devices, bus_list) 2171801846d1SGavin Shan pnv_pci_ioda_dev_dma_weight(pdev, &weight); 2172801846d1SGavin Shan } else if ((pe->flags & PNV_IODA_PE_BUS_ALL) && pe->pbus) { 2173801846d1SGavin Shan pci_walk_bus(pe->pbus, pnv_pci_ioda_dev_dma_weight, &weight); 2174801846d1SGavin Shan } 2175801846d1SGavin Shan 2176801846d1SGavin Shan return weight; 2177801846d1SGavin Shan } 2178801846d1SGavin Shan 2179b30d936fSGavin Shan static void pnv_pci_ioda1_setup_dma_pe(struct pnv_phb *phb, 21802b923ed1SGavin Shan struct pnv_ioda_pe *pe) 2181184cd4a3SBenjamin Herrenschmidt { 2182184cd4a3SBenjamin Herrenschmidt 2183184cd4a3SBenjamin Herrenschmidt struct page *tce_mem = NULL; 2184184cd4a3SBenjamin Herrenschmidt struct iommu_table *tbl; 21852b923ed1SGavin Shan unsigned int weight, total_weight = 0; 21862b923ed1SGavin Shan unsigned int tce32_segsz, base, segs, avail, i; 2187184cd4a3SBenjamin Herrenschmidt int64_t rc; 2188184cd4a3SBenjamin Herrenschmidt void *addr; 2189184cd4a3SBenjamin Herrenschmidt 2190184cd4a3SBenjamin Herrenschmidt /* XXX FIXME: Handle 64-bit only DMA devices */ 2191184cd4a3SBenjamin Herrenschmidt /* XXX FIXME: Provide 64-bit DMA facilities & non-4K TCE tables etc.. */ 2192184cd4a3SBenjamin Herrenschmidt /* XXX FIXME: Allocate multi-level tables on PHB3 */ 21932b923ed1SGavin Shan weight = pnv_pci_ioda_pe_dma_weight(pe); 21942b923ed1SGavin Shan if (!weight) 21952b923ed1SGavin Shan return; 2196184cd4a3SBenjamin Herrenschmidt 21972b923ed1SGavin Shan pci_walk_bus(phb->hose->bus, pnv_pci_ioda_dev_dma_weight, 21982b923ed1SGavin Shan &total_weight); 21992b923ed1SGavin Shan segs = (weight * phb->ioda.dma32_count) / total_weight; 22002b923ed1SGavin Shan if (!segs) 22012b923ed1SGavin Shan segs = 1; 22022b923ed1SGavin Shan 22032b923ed1SGavin Shan /* 22042b923ed1SGavin Shan * Allocate contiguous DMA32 segments. We begin with the expected 22052b923ed1SGavin Shan * number of segments. With one more attempt, the number of DMA32 22062b923ed1SGavin Shan * segments to be allocated is decreased by one until one segment 22072b923ed1SGavin Shan * is allocated successfully. 22082b923ed1SGavin Shan */ 22092b923ed1SGavin Shan do { 22102b923ed1SGavin Shan for (base = 0; base <= phb->ioda.dma32_count - segs; base++) { 22112b923ed1SGavin Shan for (avail = 0, i = base; i < base + segs; i++) { 22122b923ed1SGavin Shan if (phb->ioda.dma32_segmap[i] == 22132b923ed1SGavin Shan IODA_INVALID_PE) 22142b923ed1SGavin Shan avail++; 22152b923ed1SGavin Shan } 22162b923ed1SGavin Shan 22172b923ed1SGavin Shan if (avail == segs) 22182b923ed1SGavin Shan goto found; 22192b923ed1SGavin Shan } 22202b923ed1SGavin Shan } while (--segs); 22212b923ed1SGavin Shan 22222b923ed1SGavin Shan if (!segs) { 22232b923ed1SGavin Shan pe_warn(pe, "No available DMA32 segments\n"); 22242b923ed1SGavin Shan return; 22252b923ed1SGavin Shan } 22262b923ed1SGavin Shan 22272b923ed1SGavin Shan found: 22280eaf4defSAlexey Kardashevskiy tbl = pnv_pci_table_alloc(phb->hose->node); 222982eae1afSAlexey Kardashevskiy if (WARN_ON(!tbl)) 223082eae1afSAlexey Kardashevskiy return; 223182eae1afSAlexey Kardashevskiy 2232b348aa65SAlexey Kardashevskiy iommu_register_group(&pe->table_group, phb->hose->global_number, 2233b348aa65SAlexey Kardashevskiy pe->pe_number); 22340eaf4defSAlexey Kardashevskiy pnv_pci_link_table_and_group(phb->hose->node, 0, tbl, &pe->table_group); 2235c5773822SAlexey Kardashevskiy 2236184cd4a3SBenjamin Herrenschmidt /* Grab a 32-bit TCE table */ 22372b923ed1SGavin Shan pe_info(pe, "DMA weight %d (%d), assigned (%d) %d DMA32 segments\n", 22382b923ed1SGavin Shan weight, total_weight, base, segs); 2239184cd4a3SBenjamin Herrenschmidt pe_info(pe, " Setting up 32-bit TCE table at %08x..%08x\n", 2240acce971cSGavin Shan base * PNV_IODA1_DMA32_SEGSIZE, 2241acce971cSGavin Shan (base + segs) * PNV_IODA1_DMA32_SEGSIZE - 1); 2242184cd4a3SBenjamin Herrenschmidt 2243184cd4a3SBenjamin Herrenschmidt /* XXX Currently, we allocate one big contiguous table for the 2244184cd4a3SBenjamin Herrenschmidt * TCEs. We only really need one chunk per 256M of TCE space 2245184cd4a3SBenjamin Herrenschmidt * (ie per segment) but that's an optimization for later, it 2246184cd4a3SBenjamin Herrenschmidt * requires some added smarts with our get/put_tce implementation 2247acce971cSGavin Shan * 2248acce971cSGavin Shan * Each TCE page is 4KB in size and each TCE entry occupies 8 2249acce971cSGavin Shan * bytes 2250184cd4a3SBenjamin Herrenschmidt */ 2251acce971cSGavin Shan tce32_segsz = PNV_IODA1_DMA32_SEGSIZE >> (IOMMU_PAGE_SHIFT_4K - 3); 2252184cd4a3SBenjamin Herrenschmidt tce_mem = alloc_pages_node(phb->hose->node, GFP_KERNEL, 2253acce971cSGavin Shan get_order(tce32_segsz * segs)); 2254184cd4a3SBenjamin Herrenschmidt if (!tce_mem) { 2255184cd4a3SBenjamin Herrenschmidt pe_err(pe, " Failed to allocate a 32-bit TCE memory\n"); 2256184cd4a3SBenjamin Herrenschmidt goto fail; 2257184cd4a3SBenjamin Herrenschmidt } 2258184cd4a3SBenjamin Herrenschmidt addr = page_address(tce_mem); 2259acce971cSGavin Shan memset(addr, 0, tce32_segsz * segs); 2260184cd4a3SBenjamin Herrenschmidt 2261184cd4a3SBenjamin Herrenschmidt /* Configure HW */ 2262184cd4a3SBenjamin Herrenschmidt for (i = 0; i < segs; i++) { 2263184cd4a3SBenjamin Herrenschmidt rc = opal_pci_map_pe_dma_window(phb->opal_id, 2264184cd4a3SBenjamin Herrenschmidt pe->pe_number, 2265184cd4a3SBenjamin Herrenschmidt base + i, 1, 2266acce971cSGavin Shan __pa(addr) + tce32_segsz * i, 2267acce971cSGavin Shan tce32_segsz, IOMMU_PAGE_SIZE_4K); 2268184cd4a3SBenjamin Herrenschmidt if (rc) { 22691e496391SJoe Perches pe_err(pe, " Failed to configure 32-bit TCE table, err %lld\n", 22701e496391SJoe Perches rc); 2271184cd4a3SBenjamin Herrenschmidt goto fail; 2272184cd4a3SBenjamin Herrenschmidt } 2273184cd4a3SBenjamin Herrenschmidt } 2274184cd4a3SBenjamin Herrenschmidt 22752b923ed1SGavin Shan /* Setup DMA32 segment mapping */ 22762b923ed1SGavin Shan for (i = base; i < base + segs; i++) 22772b923ed1SGavin Shan phb->ioda.dma32_segmap[i] = pe->pe_number; 22782b923ed1SGavin Shan 2279184cd4a3SBenjamin Herrenschmidt /* Setup linux iommu table */ 2280acce971cSGavin Shan pnv_pci_setup_iommu_table(tbl, addr, tce32_segsz * segs, 2281acce971cSGavin Shan base * PNV_IODA1_DMA32_SEGSIZE, 2282acce971cSGavin Shan IOMMU_PAGE_SHIFT_4K); 2283184cd4a3SBenjamin Herrenschmidt 2284da004c36SAlexey Kardashevskiy tbl->it_ops = &pnv_ioda1_iommu_ops; 22854793d65dSAlexey Kardashevskiy pe->table_group.tce32_start = tbl->it_offset << tbl->it_page_shift; 22864793d65dSAlexey Kardashevskiy pe->table_group.tce32_size = tbl->it_size << tbl->it_page_shift; 2287201ed7f3SAlexey Kardashevskiy iommu_init_table(tbl, phb->hose->node, 0, 0); 2288184cd4a3SBenjamin Herrenschmidt 2289184cd4a3SBenjamin Herrenschmidt return; 2290184cd4a3SBenjamin Herrenschmidt fail: 2291184cd4a3SBenjamin Herrenschmidt /* XXX Failure: Try to fallback to 64-bit only ? */ 2292184cd4a3SBenjamin Herrenschmidt if (tce_mem) 2293acce971cSGavin Shan __free_pages(tce_mem, get_order(tce32_segsz * segs)); 22940eaf4defSAlexey Kardashevskiy if (tbl) { 22950eaf4defSAlexey Kardashevskiy pnv_pci_unlink_table_and_group(tbl, &pe->table_group); 2296e5afdf9dSAlexey Kardashevskiy iommu_tce_table_put(tbl); 22970eaf4defSAlexey Kardashevskiy } 2298184cd4a3SBenjamin Herrenschmidt } 2299184cd4a3SBenjamin Herrenschmidt 230043cb60abSAlexey Kardashevskiy static long pnv_pci_ioda2_set_window(struct iommu_table_group *table_group, 230143cb60abSAlexey Kardashevskiy int num, struct iommu_table *tbl) 230243cb60abSAlexey Kardashevskiy { 230343cb60abSAlexey Kardashevskiy struct pnv_ioda_pe *pe = container_of(table_group, struct pnv_ioda_pe, 230443cb60abSAlexey Kardashevskiy table_group); 230543cb60abSAlexey Kardashevskiy struct pnv_phb *phb = pe->phb; 230643cb60abSAlexey Kardashevskiy int64_t rc; 2307bbb845c4SAlexey Kardashevskiy const unsigned long size = tbl->it_indirect_levels ? 2308bbb845c4SAlexey Kardashevskiy tbl->it_level_size : tbl->it_size; 230943cb60abSAlexey Kardashevskiy const __u64 start_addr = tbl->it_offset << tbl->it_page_shift; 231043cb60abSAlexey Kardashevskiy const __u64 win_size = tbl->it_size << tbl->it_page_shift; 231143cb60abSAlexey Kardashevskiy 23121e496391SJoe Perches pe_info(pe, "Setting up window#%d %llx..%llx pg=%lx\n", 23131e496391SJoe Perches num, start_addr, start_addr + win_size - 1, 231443cb60abSAlexey Kardashevskiy IOMMU_PAGE_SIZE(tbl)); 231543cb60abSAlexey Kardashevskiy 231643cb60abSAlexey Kardashevskiy /* 231743cb60abSAlexey Kardashevskiy * Map TCE table through TVT. The TVE index is the PE number 231843cb60abSAlexey Kardashevskiy * shifted by 1 bit for 32-bits DMA space. 231943cb60abSAlexey Kardashevskiy */ 232043cb60abSAlexey Kardashevskiy rc = opal_pci_map_pe_dma_window(phb->opal_id, 232143cb60abSAlexey Kardashevskiy pe->pe_number, 23224793d65dSAlexey Kardashevskiy (pe->pe_number << 1) + num, 2323bbb845c4SAlexey Kardashevskiy tbl->it_indirect_levels + 1, 232443cb60abSAlexey Kardashevskiy __pa(tbl->it_base), 2325bbb845c4SAlexey Kardashevskiy size << 3, 232643cb60abSAlexey Kardashevskiy IOMMU_PAGE_SIZE(tbl)); 232743cb60abSAlexey Kardashevskiy if (rc) { 23281e496391SJoe Perches pe_err(pe, "Failed to configure TCE table, err %lld\n", rc); 232943cb60abSAlexey Kardashevskiy return rc; 233043cb60abSAlexey Kardashevskiy } 233143cb60abSAlexey Kardashevskiy 233243cb60abSAlexey Kardashevskiy pnv_pci_link_table_and_group(phb->hose->node, num, 233343cb60abSAlexey Kardashevskiy tbl, &pe->table_group); 2334ed7d9a1dSMichael Ellerman pnv_pci_ioda2_tce_invalidate_pe(pe); 233543cb60abSAlexey Kardashevskiy 233643cb60abSAlexey Kardashevskiy return 0; 233743cb60abSAlexey Kardashevskiy } 233843cb60abSAlexey Kardashevskiy 2339c498a4f9SChristoph Hellwig static void pnv_pci_ioda2_set_bypass(struct pnv_ioda_pe *pe, bool enable) 2340cd15b048SBenjamin Herrenschmidt { 2341cd15b048SBenjamin Herrenschmidt uint16_t window_id = (pe->pe_number << 1 ) + 1; 2342cd15b048SBenjamin Herrenschmidt int64_t rc; 2343cd15b048SBenjamin Herrenschmidt 2344cd15b048SBenjamin Herrenschmidt pe_info(pe, "%sabling 64-bit DMA bypass\n", enable ? "En" : "Dis"); 2345cd15b048SBenjamin Herrenschmidt if (enable) { 2346cd15b048SBenjamin Herrenschmidt phys_addr_t top = memblock_end_of_DRAM(); 2347cd15b048SBenjamin Herrenschmidt 2348cd15b048SBenjamin Herrenschmidt top = roundup_pow_of_two(top); 2349cd15b048SBenjamin Herrenschmidt rc = opal_pci_map_pe_dma_window_real(pe->phb->opal_id, 2350cd15b048SBenjamin Herrenschmidt pe->pe_number, 2351cd15b048SBenjamin Herrenschmidt window_id, 2352cd15b048SBenjamin Herrenschmidt pe->tce_bypass_base, 2353cd15b048SBenjamin Herrenschmidt top); 2354cd15b048SBenjamin Herrenschmidt } else { 2355cd15b048SBenjamin Herrenschmidt rc = opal_pci_map_pe_dma_window_real(pe->phb->opal_id, 2356cd15b048SBenjamin Herrenschmidt pe->pe_number, 2357cd15b048SBenjamin Herrenschmidt window_id, 2358cd15b048SBenjamin Herrenschmidt pe->tce_bypass_base, 2359cd15b048SBenjamin Herrenschmidt 0); 2360cd15b048SBenjamin Herrenschmidt } 2361cd15b048SBenjamin Herrenschmidt if (rc) 2362cd15b048SBenjamin Herrenschmidt pe_err(pe, "OPAL error %lld configuring bypass window\n", rc); 2363cd15b048SBenjamin Herrenschmidt else 2364cd15b048SBenjamin Herrenschmidt pe->tce_bypass_enabled = enable; 2365cd15b048SBenjamin Herrenschmidt } 2366cd15b048SBenjamin Herrenschmidt 23674793d65dSAlexey Kardashevskiy static long pnv_pci_ioda2_create_table(struct iommu_table_group *table_group, 23684793d65dSAlexey Kardashevskiy int num, __u32 page_shift, __u64 window_size, __u32 levels, 2369090bad39SAlexey Kardashevskiy bool alloc_userspace_copy, struct iommu_table **ptbl) 23704793d65dSAlexey Kardashevskiy { 23714793d65dSAlexey Kardashevskiy struct pnv_ioda_pe *pe = container_of(table_group, struct pnv_ioda_pe, 23724793d65dSAlexey Kardashevskiy table_group); 23734793d65dSAlexey Kardashevskiy int nid = pe->phb->hose->node; 23744793d65dSAlexey Kardashevskiy __u64 bus_offset = num ? pe->tce_bypass_base : table_group->tce32_start; 23754793d65dSAlexey Kardashevskiy long ret; 23764793d65dSAlexey Kardashevskiy struct iommu_table *tbl; 23774793d65dSAlexey Kardashevskiy 23784793d65dSAlexey Kardashevskiy tbl = pnv_pci_table_alloc(nid); 23794793d65dSAlexey Kardashevskiy if (!tbl) 23804793d65dSAlexey Kardashevskiy return -ENOMEM; 23814793d65dSAlexey Kardashevskiy 238211edf116SAlexey Kardashevskiy tbl->it_ops = &pnv_ioda2_iommu_ops; 238311edf116SAlexey Kardashevskiy 23844793d65dSAlexey Kardashevskiy ret = pnv_pci_ioda2_table_alloc_pages(nid, 23854793d65dSAlexey Kardashevskiy bus_offset, page_shift, window_size, 2386090bad39SAlexey Kardashevskiy levels, alloc_userspace_copy, tbl); 23874793d65dSAlexey Kardashevskiy if (ret) { 2388e5afdf9dSAlexey Kardashevskiy iommu_tce_table_put(tbl); 23894793d65dSAlexey Kardashevskiy return ret; 23904793d65dSAlexey Kardashevskiy } 23914793d65dSAlexey Kardashevskiy 23924793d65dSAlexey Kardashevskiy *ptbl = tbl; 23934793d65dSAlexey Kardashevskiy 23944793d65dSAlexey Kardashevskiy return 0; 23954793d65dSAlexey Kardashevskiy } 23964793d65dSAlexey Kardashevskiy 239746d3e1e1SAlexey Kardashevskiy static long pnv_pci_ioda2_setup_default_config(struct pnv_ioda_pe *pe) 239846d3e1e1SAlexey Kardashevskiy { 239946d3e1e1SAlexey Kardashevskiy struct iommu_table *tbl = NULL; 240046d3e1e1SAlexey Kardashevskiy long rc; 2401201ed7f3SAlexey Kardashevskiy unsigned long res_start, res_end; 240246d3e1e1SAlexey Kardashevskiy 2403bb005455SNishanth Aravamudan /* 2404fa144869SNishanth Aravamudan * crashkernel= specifies the kdump kernel's maximum memory at 2405fa144869SNishanth Aravamudan * some offset and there is no guaranteed the result is a power 2406fa144869SNishanth Aravamudan * of 2, which will cause errors later. 2407fa144869SNishanth Aravamudan */ 2408fa144869SNishanth Aravamudan const u64 max_memory = __rounddown_pow_of_two(memory_hotplug_max()); 2409fa144869SNishanth Aravamudan 2410fa144869SNishanth Aravamudan /* 2411bb005455SNishanth Aravamudan * In memory constrained environments, e.g. kdump kernel, the 2412bb005455SNishanth Aravamudan * DMA window can be larger than available memory, which will 2413bb005455SNishanth Aravamudan * cause errors later. 2414bb005455SNishanth Aravamudan */ 2415201ed7f3SAlexey Kardashevskiy const u64 maxblock = 1UL << (PAGE_SHIFT + MAX_ORDER - 1); 2416bb005455SNishanth Aravamudan 2417201ed7f3SAlexey Kardashevskiy /* 2418201ed7f3SAlexey Kardashevskiy * We create the default window as big as we can. The constraint is 2419201ed7f3SAlexey Kardashevskiy * the max order of allocation possible. The TCE table is likely to 2420201ed7f3SAlexey Kardashevskiy * end up being multilevel and with on-demand allocation in place, 2421201ed7f3SAlexey Kardashevskiy * the initial use is not going to be huge as the default window aims 2422201ed7f3SAlexey Kardashevskiy * to support crippled devices (i.e. not fully 64bit DMAble) only. 2423201ed7f3SAlexey Kardashevskiy */ 2424201ed7f3SAlexey Kardashevskiy /* iommu_table::it_map uses 1 bit per IOMMU page, hence 8 */ 2425201ed7f3SAlexey Kardashevskiy const u64 window_size = min((maxblock * 8) << PAGE_SHIFT, max_memory); 2426201ed7f3SAlexey Kardashevskiy /* Each TCE level cannot exceed maxblock so go multilevel if needed */ 2427201ed7f3SAlexey Kardashevskiy unsigned long tces_order = ilog2(window_size >> PAGE_SHIFT); 2428201ed7f3SAlexey Kardashevskiy unsigned long tcelevel_order = ilog2(maxblock >> 3); 2429201ed7f3SAlexey Kardashevskiy unsigned int levels = tces_order / tcelevel_order; 2430201ed7f3SAlexey Kardashevskiy 2431201ed7f3SAlexey Kardashevskiy if (tces_order % tcelevel_order) 2432201ed7f3SAlexey Kardashevskiy levels += 1; 2433201ed7f3SAlexey Kardashevskiy /* 2434201ed7f3SAlexey Kardashevskiy * We try to stick to default levels (which is >1 at the moment) in 2435201ed7f3SAlexey Kardashevskiy * order to save memory by relying on on-demain TCE level allocation. 2436201ed7f3SAlexey Kardashevskiy */ 2437201ed7f3SAlexey Kardashevskiy levels = max_t(unsigned int, levels, POWERNV_IOMMU_DEFAULT_LEVELS); 2438201ed7f3SAlexey Kardashevskiy 2439201ed7f3SAlexey Kardashevskiy rc = pnv_pci_ioda2_create_table(&pe->table_group, 0, PAGE_SHIFT, 2440201ed7f3SAlexey Kardashevskiy window_size, levels, false, &tbl); 244146d3e1e1SAlexey Kardashevskiy if (rc) { 244246d3e1e1SAlexey Kardashevskiy pe_err(pe, "Failed to create 32-bit TCE table, err %ld", 244346d3e1e1SAlexey Kardashevskiy rc); 244446d3e1e1SAlexey Kardashevskiy return rc; 244546d3e1e1SAlexey Kardashevskiy } 244646d3e1e1SAlexey Kardashevskiy 2447201ed7f3SAlexey Kardashevskiy /* We use top part of 32bit space for MMIO so exclude it from DMA */ 2448201ed7f3SAlexey Kardashevskiy res_start = 0; 2449201ed7f3SAlexey Kardashevskiy res_end = 0; 2450201ed7f3SAlexey Kardashevskiy if (window_size > pe->phb->ioda.m32_pci_base) { 2451201ed7f3SAlexey Kardashevskiy res_start = pe->phb->ioda.m32_pci_base >> tbl->it_page_shift; 2452201ed7f3SAlexey Kardashevskiy res_end = min(window_size, SZ_4G) >> tbl->it_page_shift; 2453201ed7f3SAlexey Kardashevskiy } 2454201ed7f3SAlexey Kardashevskiy iommu_init_table(tbl, pe->phb->hose->node, res_start, res_end); 245546d3e1e1SAlexey Kardashevskiy 245646d3e1e1SAlexey Kardashevskiy rc = pnv_pci_ioda2_set_window(&pe->table_group, 0, tbl); 245746d3e1e1SAlexey Kardashevskiy if (rc) { 245846d3e1e1SAlexey Kardashevskiy pe_err(pe, "Failed to configure 32-bit TCE table, err %ld\n", 245946d3e1e1SAlexey Kardashevskiy rc); 2460e5afdf9dSAlexey Kardashevskiy iommu_tce_table_put(tbl); 246146d3e1e1SAlexey Kardashevskiy return rc; 246246d3e1e1SAlexey Kardashevskiy } 246346d3e1e1SAlexey Kardashevskiy 246446d3e1e1SAlexey Kardashevskiy if (!pnv_iommu_bypass_disabled) 246546d3e1e1SAlexey Kardashevskiy pnv_pci_ioda2_set_bypass(pe, true); 246646d3e1e1SAlexey Kardashevskiy 24675636427dSAlexey Kardashevskiy /* 24685636427dSAlexey Kardashevskiy * Set table base for the case of IOMMU DMA use. Usually this is done 24695636427dSAlexey Kardashevskiy * from dma_dev_setup() which is not called when a device is returned 24705636427dSAlexey Kardashevskiy * from VFIO so do it here. 24715636427dSAlexey Kardashevskiy */ 24725636427dSAlexey Kardashevskiy if (pe->pdev) 24735636427dSAlexey Kardashevskiy set_iommu_table_base(&pe->pdev->dev, tbl); 24745636427dSAlexey Kardashevskiy 247546d3e1e1SAlexey Kardashevskiy return 0; 247646d3e1e1SAlexey Kardashevskiy } 247746d3e1e1SAlexey Kardashevskiy 2478b5926430SAlexey Kardashevskiy #if defined(CONFIG_IOMMU_API) || defined(CONFIG_PCI_IOV) 2479b5926430SAlexey Kardashevskiy static long pnv_pci_ioda2_unset_window(struct iommu_table_group *table_group, 2480b5926430SAlexey Kardashevskiy int num) 2481b5926430SAlexey Kardashevskiy { 2482b5926430SAlexey Kardashevskiy struct pnv_ioda_pe *pe = container_of(table_group, struct pnv_ioda_pe, 2483b5926430SAlexey Kardashevskiy table_group); 2484b5926430SAlexey Kardashevskiy struct pnv_phb *phb = pe->phb; 2485b5926430SAlexey Kardashevskiy long ret; 2486b5926430SAlexey Kardashevskiy 2487b5926430SAlexey Kardashevskiy pe_info(pe, "Removing DMA window #%d\n", num); 2488b5926430SAlexey Kardashevskiy 2489b5926430SAlexey Kardashevskiy ret = opal_pci_map_pe_dma_window(phb->opal_id, pe->pe_number, 2490b5926430SAlexey Kardashevskiy (pe->pe_number << 1) + num, 2491b5926430SAlexey Kardashevskiy 0/* levels */, 0/* table address */, 2492b5926430SAlexey Kardashevskiy 0/* table size */, 0/* page size */); 2493b5926430SAlexey Kardashevskiy if (ret) 2494b5926430SAlexey Kardashevskiy pe_warn(pe, "Unmapping failed, ret = %ld\n", ret); 2495b5926430SAlexey Kardashevskiy else 2496ed7d9a1dSMichael Ellerman pnv_pci_ioda2_tce_invalidate_pe(pe); 2497b5926430SAlexey Kardashevskiy 2498b5926430SAlexey Kardashevskiy pnv_pci_unlink_table_and_group(table_group->tables[num], table_group); 2499b5926430SAlexey Kardashevskiy 2500b5926430SAlexey Kardashevskiy return ret; 2501b5926430SAlexey Kardashevskiy } 2502b5926430SAlexey Kardashevskiy #endif 2503b5926430SAlexey Kardashevskiy 2504f87a8864SAlexey Kardashevskiy #ifdef CONFIG_IOMMU_API 25050bd97167SAlexey Kardashevskiy unsigned long pnv_pci_ioda2_get_table_size(__u32 page_shift, 250600547193SAlexey Kardashevskiy __u64 window_size, __u32 levels) 250700547193SAlexey Kardashevskiy { 250800547193SAlexey Kardashevskiy unsigned long bytes = 0; 250900547193SAlexey Kardashevskiy const unsigned window_shift = ilog2(window_size); 251000547193SAlexey Kardashevskiy unsigned entries_shift = window_shift - page_shift; 251100547193SAlexey Kardashevskiy unsigned table_shift = entries_shift + 3; 251200547193SAlexey Kardashevskiy unsigned long tce_table_size = max(0x1000UL, 1UL << table_shift); 251300547193SAlexey Kardashevskiy unsigned long direct_table_size; 251400547193SAlexey Kardashevskiy 251500547193SAlexey Kardashevskiy if (!levels || (levels > POWERNV_IOMMU_MAX_LEVELS) || 251600547193SAlexey Kardashevskiy !is_power_of_2(window_size)) 251700547193SAlexey Kardashevskiy return 0; 251800547193SAlexey Kardashevskiy 251900547193SAlexey Kardashevskiy /* Calculate a direct table size from window_size and levels */ 252000547193SAlexey Kardashevskiy entries_shift = (entries_shift + levels - 1) / levels; 252100547193SAlexey Kardashevskiy table_shift = entries_shift + 3; 252200547193SAlexey Kardashevskiy table_shift = max_t(unsigned, table_shift, PAGE_SHIFT); 252300547193SAlexey Kardashevskiy direct_table_size = 1UL << table_shift; 252400547193SAlexey Kardashevskiy 252500547193SAlexey Kardashevskiy for ( ; levels; --levels) { 2526b7115316SChristophe Leroy bytes += ALIGN(tce_table_size, direct_table_size); 252700547193SAlexey Kardashevskiy 252800547193SAlexey Kardashevskiy tce_table_size /= direct_table_size; 252900547193SAlexey Kardashevskiy tce_table_size <<= 3; 2530e49a6a21SAlexey Kardashevskiy tce_table_size = max_t(unsigned long, 2531e49a6a21SAlexey Kardashevskiy tce_table_size, direct_table_size); 253200547193SAlexey Kardashevskiy } 253300547193SAlexey Kardashevskiy 2534090bad39SAlexey Kardashevskiy return bytes + bytes; /* one for HW table, one for userspace copy */ 2535090bad39SAlexey Kardashevskiy } 2536090bad39SAlexey Kardashevskiy 2537090bad39SAlexey Kardashevskiy static long pnv_pci_ioda2_create_table_userspace( 2538090bad39SAlexey Kardashevskiy struct iommu_table_group *table_group, 2539090bad39SAlexey Kardashevskiy int num, __u32 page_shift, __u64 window_size, __u32 levels, 2540090bad39SAlexey Kardashevskiy struct iommu_table **ptbl) 2541090bad39SAlexey Kardashevskiy { 254211f5acceSAlexey Kardashevskiy long ret = pnv_pci_ioda2_create_table(table_group, 2543090bad39SAlexey Kardashevskiy num, page_shift, window_size, levels, true, ptbl); 254411f5acceSAlexey Kardashevskiy 254511f5acceSAlexey Kardashevskiy if (!ret) 254611f5acceSAlexey Kardashevskiy (*ptbl)->it_allocated_size = pnv_pci_ioda2_get_table_size( 254711f5acceSAlexey Kardashevskiy page_shift, window_size, levels); 254811f5acceSAlexey Kardashevskiy return ret; 254900547193SAlexey Kardashevskiy } 255000547193SAlexey Kardashevskiy 2551f87a8864SAlexey Kardashevskiy static void pnv_ioda2_take_ownership(struct iommu_table_group *table_group) 2552cd15b048SBenjamin Herrenschmidt { 2553f87a8864SAlexey Kardashevskiy struct pnv_ioda_pe *pe = container_of(table_group, struct pnv_ioda_pe, 2554f87a8864SAlexey Kardashevskiy table_group); 255546d3e1e1SAlexey Kardashevskiy /* Store @tbl as pnv_pci_ioda2_unset_window() resets it */ 255646d3e1e1SAlexey Kardashevskiy struct iommu_table *tbl = pe->table_group.tables[0]; 2557cd15b048SBenjamin Herrenschmidt 2558f87a8864SAlexey Kardashevskiy pnv_pci_ioda2_set_bypass(pe, false); 255946d3e1e1SAlexey Kardashevskiy pnv_pci_ioda2_unset_window(&pe->table_group, 0); 2560db08e1d5SAlexey Kardashevskiy if (pe->pbus) 25615eada8a3SAlexey Kardashevskiy pnv_ioda_setup_bus_dma(pe, pe->pbus); 25625636427dSAlexey Kardashevskiy else if (pe->pdev) 25635636427dSAlexey Kardashevskiy set_iommu_table_base(&pe->pdev->dev, NULL); 2564e5afdf9dSAlexey Kardashevskiy iommu_tce_table_put(tbl); 2565cd15b048SBenjamin Herrenschmidt } 2566cd15b048SBenjamin Herrenschmidt 2567f87a8864SAlexey Kardashevskiy static void pnv_ioda2_release_ownership(struct iommu_table_group *table_group) 2568f87a8864SAlexey Kardashevskiy { 2569f87a8864SAlexey Kardashevskiy struct pnv_ioda_pe *pe = container_of(table_group, struct pnv_ioda_pe, 2570f87a8864SAlexey Kardashevskiy table_group); 2571f87a8864SAlexey Kardashevskiy 257246d3e1e1SAlexey Kardashevskiy pnv_pci_ioda2_setup_default_config(pe); 2573db08e1d5SAlexey Kardashevskiy if (pe->pbus) 25745eada8a3SAlexey Kardashevskiy pnv_ioda_setup_bus_dma(pe, pe->pbus); 2575f87a8864SAlexey Kardashevskiy } 2576f87a8864SAlexey Kardashevskiy 2577f87a8864SAlexey Kardashevskiy static struct iommu_table_group_ops pnv_pci_ioda2_ops = { 257800547193SAlexey Kardashevskiy .get_table_size = pnv_pci_ioda2_get_table_size, 2579090bad39SAlexey Kardashevskiy .create_table = pnv_pci_ioda2_create_table_userspace, 25804793d65dSAlexey Kardashevskiy .set_window = pnv_pci_ioda2_set_window, 25814793d65dSAlexey Kardashevskiy .unset_window = pnv_pci_ioda2_unset_window, 2582f87a8864SAlexey Kardashevskiy .take_ownership = pnv_ioda2_take_ownership, 2583f87a8864SAlexey Kardashevskiy .release_ownership = pnv_ioda2_release_ownership, 2584f87a8864SAlexey Kardashevskiy }; 2585f87a8864SAlexey Kardashevskiy #endif 2586f87a8864SAlexey Kardashevskiy 2587373f5657SGavin Shan static void pnv_pci_ioda2_setup_dma_pe(struct pnv_phb *phb, 2588373f5657SGavin Shan struct pnv_ioda_pe *pe) 2589373f5657SGavin Shan { 2590373f5657SGavin Shan int64_t rc; 2591373f5657SGavin Shan 2592ccd1c191SGavin Shan if (!pnv_pci_ioda_pe_dma_weight(pe)) 2593ccd1c191SGavin Shan return; 2594ccd1c191SGavin Shan 2595f87a8864SAlexey Kardashevskiy /* TVE #1 is selected by PCI address bit 59 */ 2596f87a8864SAlexey Kardashevskiy pe->tce_bypass_base = 1ull << 59; 2597f87a8864SAlexey Kardashevskiy 2598373f5657SGavin Shan /* The PE will reserve all possible 32-bits space */ 2599373f5657SGavin Shan pe_info(pe, "Setting up 32-bit TCE table at 0..%08x\n", 2600aca6913fSAlexey Kardashevskiy phb->ioda.m32_pci_base); 2601373f5657SGavin Shan 2602e5aad1e6SAlexey Kardashevskiy /* Setup linux iommu table */ 26034793d65dSAlexey Kardashevskiy pe->table_group.tce32_start = 0; 26044793d65dSAlexey Kardashevskiy pe->table_group.tce32_size = phb->ioda.m32_pci_base; 26054793d65dSAlexey Kardashevskiy pe->table_group.max_dynamic_windows_supported = 26064793d65dSAlexey Kardashevskiy IOMMU_TABLE_GROUP_MAX_TABLES; 26074793d65dSAlexey Kardashevskiy pe->table_group.max_levels = POWERNV_IOMMU_MAX_LEVELS; 26087ef73cd3SAlexey Kardashevskiy pe->table_group.pgsizes = pnv_ioda_parse_tce_sizes(phb); 2609e5aad1e6SAlexey Kardashevskiy 261046d3e1e1SAlexey Kardashevskiy rc = pnv_pci_ioda2_setup_default_config(pe); 2611801846d1SGavin Shan if (rc) 261246d3e1e1SAlexey Kardashevskiy return; 261346d3e1e1SAlexey Kardashevskiy 26149b9408c5SOliver O'Halloran #ifdef CONFIG_IOMMU_API 26159b9408c5SOliver O'Halloran pe->table_group.ops = &pnv_pci_ioda2_ops; 26169b9408c5SOliver O'Halloran iommu_register_group(&pe->table_group, phb->hose->global_number, 26179b9408c5SOliver O'Halloran pe->pe_number); 26189b9408c5SOliver O'Halloran #endif 2619373f5657SGavin Shan } 2620373f5657SGavin Shan 26214ee11c1aSSuresh Warrier int64_t pnv_opal_pci_msi_eoi(struct irq_chip *chip, unsigned int hw_irq) 2622137436c9SGavin Shan { 2623137436c9SGavin Shan struct pnv_phb *phb = container_of(chip, struct pnv_phb, 2624137436c9SGavin Shan ioda.irq_chip); 2625137436c9SGavin Shan 26264ee11c1aSSuresh Warrier return opal_pci_msi_eoi(phb->opal_id, hw_irq); 26274ee11c1aSSuresh Warrier } 26284ee11c1aSSuresh Warrier 26294ee11c1aSSuresh Warrier static void pnv_ioda2_msi_eoi(struct irq_data *d) 26304ee11c1aSSuresh Warrier { 26314ee11c1aSSuresh Warrier int64_t rc; 26324ee11c1aSSuresh Warrier unsigned int hw_irq = (unsigned int)irqd_to_hwirq(d); 26334ee11c1aSSuresh Warrier struct irq_chip *chip = irq_data_get_irq_chip(d); 26344ee11c1aSSuresh Warrier 26354ee11c1aSSuresh Warrier rc = pnv_opal_pci_msi_eoi(chip, hw_irq); 2636137436c9SGavin Shan WARN_ON_ONCE(rc); 2637137436c9SGavin Shan 2638137436c9SGavin Shan icp_native_eoi(d); 2639137436c9SGavin Shan } 2640137436c9SGavin Shan 2641fd9a1c26SIan Munsie 2642f456834aSIan Munsie void pnv_set_msi_irq_chip(struct pnv_phb *phb, unsigned int virq) 2643fd9a1c26SIan Munsie { 2644fd9a1c26SIan Munsie struct irq_data *idata; 2645fd9a1c26SIan Munsie struct irq_chip *ichip; 2646fd9a1c26SIan Munsie 2647fb111334SBenjamin Herrenschmidt /* The MSI EOI OPAL call is only needed on PHB3 */ 2648fb111334SBenjamin Herrenschmidt if (phb->model != PNV_PHB_MODEL_PHB3) 2649fd9a1c26SIan Munsie return; 2650fd9a1c26SIan Munsie 2651fd9a1c26SIan Munsie if (!phb->ioda.irq_chip_init) { 2652fd9a1c26SIan Munsie /* 2653fd9a1c26SIan Munsie * First time we setup an MSI IRQ, we need to setup the 2654fd9a1c26SIan Munsie * corresponding IRQ chip to route correctly. 2655fd9a1c26SIan Munsie */ 2656fd9a1c26SIan Munsie idata = irq_get_irq_data(virq); 2657fd9a1c26SIan Munsie ichip = irq_data_get_irq_chip(idata); 2658fd9a1c26SIan Munsie phb->ioda.irq_chip_init = 1; 2659fd9a1c26SIan Munsie phb->ioda.irq_chip = *ichip; 2660fd9a1c26SIan Munsie phb->ioda.irq_chip.irq_eoi = pnv_ioda2_msi_eoi; 2661fd9a1c26SIan Munsie } 2662fd9a1c26SIan Munsie irq_set_chip(virq, &phb->ioda.irq_chip); 2663fd9a1c26SIan Munsie } 2664fd9a1c26SIan Munsie 26654ee11c1aSSuresh Warrier /* 26664ee11c1aSSuresh Warrier * Returns true iff chip is something that we could call 26674ee11c1aSSuresh Warrier * pnv_opal_pci_msi_eoi for. 26684ee11c1aSSuresh Warrier */ 26694ee11c1aSSuresh Warrier bool is_pnv_opal_msi(struct irq_chip *chip) 26704ee11c1aSSuresh Warrier { 26714ee11c1aSSuresh Warrier return chip->irq_eoi == pnv_ioda2_msi_eoi; 26724ee11c1aSSuresh Warrier } 26734ee11c1aSSuresh Warrier EXPORT_SYMBOL_GPL(is_pnv_opal_msi); 26744ee11c1aSSuresh Warrier 2675184cd4a3SBenjamin Herrenschmidt static int pnv_pci_ioda_msi_setup(struct pnv_phb *phb, struct pci_dev *dev, 2676137436c9SGavin Shan unsigned int hwirq, unsigned int virq, 2677137436c9SGavin Shan unsigned int is_64, struct msi_msg *msg) 2678184cd4a3SBenjamin Herrenschmidt { 2679184cd4a3SBenjamin Herrenschmidt struct pnv_ioda_pe *pe = pnv_ioda_get_pe(dev); 2680184cd4a3SBenjamin Herrenschmidt unsigned int xive_num = hwirq - phb->msi_base; 26813a1a4661SBenjamin Herrenschmidt __be32 data; 2682184cd4a3SBenjamin Herrenschmidt int rc; 2683184cd4a3SBenjamin Herrenschmidt 2684184cd4a3SBenjamin Herrenschmidt /* No PE assigned ? bail out ... no MSI for you ! */ 2685184cd4a3SBenjamin Herrenschmidt if (pe == NULL) 2686184cd4a3SBenjamin Herrenschmidt return -ENXIO; 2687184cd4a3SBenjamin Herrenschmidt 2688184cd4a3SBenjamin Herrenschmidt /* Check if we have an MVE */ 2689184cd4a3SBenjamin Herrenschmidt if (pe->mve_number < 0) 2690184cd4a3SBenjamin Herrenschmidt return -ENXIO; 2691184cd4a3SBenjamin Herrenschmidt 2692b72c1f65SBenjamin Herrenschmidt /* Force 32-bit MSI on some broken devices */ 269336074381SBenjamin Herrenschmidt if (dev->no_64bit_msi) 2694b72c1f65SBenjamin Herrenschmidt is_64 = 0; 2695b72c1f65SBenjamin Herrenschmidt 2696184cd4a3SBenjamin Herrenschmidt /* Assign XIVE to PE */ 2697184cd4a3SBenjamin Herrenschmidt rc = opal_pci_set_xive_pe(phb->opal_id, pe->pe_number, xive_num); 2698184cd4a3SBenjamin Herrenschmidt if (rc) { 2699184cd4a3SBenjamin Herrenschmidt pr_warn("%s: OPAL error %d setting XIVE %d PE\n", 2700184cd4a3SBenjamin Herrenschmidt pci_name(dev), rc, xive_num); 2701184cd4a3SBenjamin Herrenschmidt return -EIO; 2702184cd4a3SBenjamin Herrenschmidt } 2703184cd4a3SBenjamin Herrenschmidt 2704184cd4a3SBenjamin Herrenschmidt if (is_64) { 27053a1a4661SBenjamin Herrenschmidt __be64 addr64; 27063a1a4661SBenjamin Herrenschmidt 2707184cd4a3SBenjamin Herrenschmidt rc = opal_get_msi_64(phb->opal_id, pe->mve_number, xive_num, 1, 2708184cd4a3SBenjamin Herrenschmidt &addr64, &data); 2709184cd4a3SBenjamin Herrenschmidt if (rc) { 2710184cd4a3SBenjamin Herrenschmidt pr_warn("%s: OPAL error %d getting 64-bit MSI data\n", 2711184cd4a3SBenjamin Herrenschmidt pci_name(dev), rc); 2712184cd4a3SBenjamin Herrenschmidt return -EIO; 2713184cd4a3SBenjamin Herrenschmidt } 27143a1a4661SBenjamin Herrenschmidt msg->address_hi = be64_to_cpu(addr64) >> 32; 27153a1a4661SBenjamin Herrenschmidt msg->address_lo = be64_to_cpu(addr64) & 0xfffffffful; 2716184cd4a3SBenjamin Herrenschmidt } else { 27173a1a4661SBenjamin Herrenschmidt __be32 addr32; 27183a1a4661SBenjamin Herrenschmidt 2719184cd4a3SBenjamin Herrenschmidt rc = opal_get_msi_32(phb->opal_id, pe->mve_number, xive_num, 1, 2720184cd4a3SBenjamin Herrenschmidt &addr32, &data); 2721184cd4a3SBenjamin Herrenschmidt if (rc) { 2722184cd4a3SBenjamin Herrenschmidt pr_warn("%s: OPAL error %d getting 32-bit MSI data\n", 2723184cd4a3SBenjamin Herrenschmidt pci_name(dev), rc); 2724184cd4a3SBenjamin Herrenschmidt return -EIO; 2725184cd4a3SBenjamin Herrenschmidt } 2726184cd4a3SBenjamin Herrenschmidt msg->address_hi = 0; 27273a1a4661SBenjamin Herrenschmidt msg->address_lo = be32_to_cpu(addr32); 2728184cd4a3SBenjamin Herrenschmidt } 27293a1a4661SBenjamin Herrenschmidt msg->data = be32_to_cpu(data); 2730184cd4a3SBenjamin Herrenschmidt 2731f456834aSIan Munsie pnv_set_msi_irq_chip(phb, virq); 2732137436c9SGavin Shan 2733184cd4a3SBenjamin Herrenschmidt pr_devel("%s: %s-bit MSI on hwirq %x (xive #%d)," 27341f52f176SRussell Currey " address=%x_%08x data=%x PE# %x\n", 2735184cd4a3SBenjamin Herrenschmidt pci_name(dev), is_64 ? "64" : "32", hwirq, xive_num, 2736184cd4a3SBenjamin Herrenschmidt msg->address_hi, msg->address_lo, data, pe->pe_number); 2737184cd4a3SBenjamin Herrenschmidt 2738184cd4a3SBenjamin Herrenschmidt return 0; 2739184cd4a3SBenjamin Herrenschmidt } 2740184cd4a3SBenjamin Herrenschmidt 2741184cd4a3SBenjamin Herrenschmidt static void pnv_pci_init_ioda_msis(struct pnv_phb *phb) 2742184cd4a3SBenjamin Herrenschmidt { 2743fb1b55d6SGavin Shan unsigned int count; 2744184cd4a3SBenjamin Herrenschmidt const __be32 *prop = of_get_property(phb->hose->dn, 2745184cd4a3SBenjamin Herrenschmidt "ibm,opal-msi-ranges", NULL); 2746184cd4a3SBenjamin Herrenschmidt if (!prop) { 2747184cd4a3SBenjamin Herrenschmidt /* BML Fallback */ 2748184cd4a3SBenjamin Herrenschmidt prop = of_get_property(phb->hose->dn, "msi-ranges", NULL); 2749184cd4a3SBenjamin Herrenschmidt } 2750184cd4a3SBenjamin Herrenschmidt if (!prop) 2751184cd4a3SBenjamin Herrenschmidt return; 2752184cd4a3SBenjamin Herrenschmidt 2753184cd4a3SBenjamin Herrenschmidt phb->msi_base = be32_to_cpup(prop); 2754fb1b55d6SGavin Shan count = be32_to_cpup(prop + 1); 2755fb1b55d6SGavin Shan if (msi_bitmap_alloc(&phb->msi_bmp, count, phb->hose->dn)) { 2756184cd4a3SBenjamin Herrenschmidt pr_err("PCI %d: Failed to allocate MSI bitmap !\n", 2757184cd4a3SBenjamin Herrenschmidt phb->hose->global_number); 2758184cd4a3SBenjamin Herrenschmidt return; 2759184cd4a3SBenjamin Herrenschmidt } 2760fb1b55d6SGavin Shan 2761184cd4a3SBenjamin Herrenschmidt phb->msi_setup = pnv_pci_ioda_msi_setup; 2762184cd4a3SBenjamin Herrenschmidt phb->msi32_support = 1; 2763184cd4a3SBenjamin Herrenschmidt pr_info(" Allocated bitmap for %d MSIs (base IRQ 0x%x)\n", 2764fb1b55d6SGavin Shan count, phb->msi_base); 2765184cd4a3SBenjamin Herrenschmidt } 2766184cd4a3SBenjamin Herrenschmidt 27676e628c7dSWei Yang #ifdef CONFIG_PCI_IOV 27686e628c7dSWei Yang static void pnv_pci_ioda_fixup_iov_resources(struct pci_dev *pdev) 27696e628c7dSWei Yang { 2770f2dd0afeSWei Yang struct pci_controller *hose = pci_bus_to_host(pdev->bus); 2771f2dd0afeSWei Yang struct pnv_phb *phb = hose->private_data; 2772f2dd0afeSWei Yang const resource_size_t gate = phb->ioda.m64_segsize >> 2; 27736e628c7dSWei Yang struct resource *res; 27746e628c7dSWei Yang int i; 2775dfcc8d45SWei Yang resource_size_t size, total_vf_bar_sz; 27766e628c7dSWei Yang struct pci_dn *pdn; 27775b88ec22SWei Yang int mul, total_vfs; 27786e628c7dSWei Yang 27796e628c7dSWei Yang pdn = pci_get_pdn(pdev); 27806e628c7dSWei Yang pdn->vfs_expanded = 0; 2781ee8222feSWei Yang pdn->m64_single_mode = false; 27826e628c7dSWei Yang 27835b88ec22SWei Yang total_vfs = pci_sriov_get_totalvfs(pdev); 278492b8f137SGavin Shan mul = phb->ioda.total_pe_num; 2785dfcc8d45SWei Yang total_vf_bar_sz = 0; 27865b88ec22SWei Yang 27875b88ec22SWei Yang for (i = 0; i < PCI_SRIOV_NUM_BARS; i++) { 27885b88ec22SWei Yang res = &pdev->resource[i + PCI_IOV_RESOURCES]; 27895b88ec22SWei Yang if (!res->flags || res->parent) 27905b88ec22SWei Yang continue; 2791b79331a5SRussell Currey if (!pnv_pci_is_m64_flags(res->flags)) { 2792b0331854SWei Yang dev_warn(&pdev->dev, "Don't support SR-IOV with" 2793b0331854SWei Yang " non M64 VF BAR%d: %pR. \n", 27945b88ec22SWei Yang i, res); 2795b0331854SWei Yang goto truncate_iov; 27965b88ec22SWei Yang } 27975b88ec22SWei Yang 2798dfcc8d45SWei Yang total_vf_bar_sz += pci_iov_resource_size(pdev, 2799dfcc8d45SWei Yang i + PCI_IOV_RESOURCES); 28005b88ec22SWei Yang 2801f2dd0afeSWei Yang /* 2802f2dd0afeSWei Yang * If bigger than quarter of M64 segment size, just round up 2803f2dd0afeSWei Yang * power of two. 2804f2dd0afeSWei Yang * 2805f2dd0afeSWei Yang * Generally, one M64 BAR maps one IOV BAR. To avoid conflict 2806f2dd0afeSWei Yang * with other devices, IOV BAR size is expanded to be 2807f2dd0afeSWei Yang * (total_pe * VF_BAR_size). When VF_BAR_size is half of M64 2808f2dd0afeSWei Yang * segment size , the expanded size would equal to half of the 2809f2dd0afeSWei Yang * whole M64 space size, which will exhaust the M64 Space and 2810f2dd0afeSWei Yang * limit the system flexibility. This is a design decision to 2811f2dd0afeSWei Yang * set the boundary to quarter of the M64 segment size. 2812f2dd0afeSWei Yang */ 2813dfcc8d45SWei Yang if (total_vf_bar_sz > gate) { 28145b88ec22SWei Yang mul = roundup_pow_of_two(total_vfs); 2815dfcc8d45SWei Yang dev_info(&pdev->dev, 2816dfcc8d45SWei Yang "VF BAR Total IOV size %llx > %llx, roundup to %d VFs\n", 2817dfcc8d45SWei Yang total_vf_bar_sz, gate, mul); 2818ee8222feSWei Yang pdn->m64_single_mode = true; 28195b88ec22SWei Yang break; 28205b88ec22SWei Yang } 28215b88ec22SWei Yang } 28225b88ec22SWei Yang 28236e628c7dSWei Yang for (i = 0; i < PCI_SRIOV_NUM_BARS; i++) { 28246e628c7dSWei Yang res = &pdev->resource[i + PCI_IOV_RESOURCES]; 28256e628c7dSWei Yang if (!res->flags || res->parent) 28266e628c7dSWei Yang continue; 28276e628c7dSWei Yang 28286e628c7dSWei Yang size = pci_iov_resource_size(pdev, i + PCI_IOV_RESOURCES); 2829ee8222feSWei Yang /* 2830ee8222feSWei Yang * On PHB3, the minimum size alignment of M64 BAR in single 2831ee8222feSWei Yang * mode is 32MB. 2832ee8222feSWei Yang */ 2833ee8222feSWei Yang if (pdn->m64_single_mode && (size < SZ_32M)) 2834ee8222feSWei Yang goto truncate_iov; 2835ee8222feSWei Yang dev_dbg(&pdev->dev, " Fixing VF BAR%d: %pR to\n", i, res); 28365b88ec22SWei Yang res->end = res->start + size * mul - 1; 28376e628c7dSWei Yang dev_dbg(&pdev->dev, " %pR\n", res); 28386e628c7dSWei Yang dev_info(&pdev->dev, "VF BAR%d: %pR (expanded to %d VFs for PE alignment)", 28395b88ec22SWei Yang i, res, mul); 28406e628c7dSWei Yang } 28415b88ec22SWei Yang pdn->vfs_expanded = mul; 2842b0331854SWei Yang 2843b0331854SWei Yang return; 2844b0331854SWei Yang 2845b0331854SWei Yang truncate_iov: 2846b0331854SWei Yang /* To save MMIO space, IOV BAR is truncated. */ 2847b0331854SWei Yang for (i = 0; i < PCI_SRIOV_NUM_BARS; i++) { 2848b0331854SWei Yang res = &pdev->resource[i + PCI_IOV_RESOURCES]; 2849b0331854SWei Yang res->flags = 0; 2850b0331854SWei Yang res->end = res->start - 1; 2851b0331854SWei Yang } 28526e628c7dSWei Yang } 2853965c94f3SOliver O'Halloran 2854965c94f3SOliver O'Halloran static void pnv_pci_ioda_fixup_iov(struct pci_dev *pdev) 2855965c94f3SOliver O'Halloran { 2856965c94f3SOliver O'Halloran if (WARN_ON(pci_dev_is_added(pdev))) 2857965c94f3SOliver O'Halloran return; 2858965c94f3SOliver O'Halloran 2859965c94f3SOliver O'Halloran if (pdev->is_virtfn) { 2860965c94f3SOliver O'Halloran struct pnv_ioda_pe *pe = pnv_ioda_get_pe(pdev); 2861965c94f3SOliver O'Halloran 2862965c94f3SOliver O'Halloran /* 2863965c94f3SOliver O'Halloran * VF PEs are single-device PEs so their pdev pointer needs to 2864965c94f3SOliver O'Halloran * be set. The pdev doesn't exist when the PE is allocated (in 2865965c94f3SOliver O'Halloran * (pcibios_sriov_enable()) so we fix it up here. 2866965c94f3SOliver O'Halloran */ 2867965c94f3SOliver O'Halloran pe->pdev = pdev; 2868965c94f3SOliver O'Halloran WARN_ON(!(pe->flags & PNV_IODA_PE_VF)); 2869965c94f3SOliver O'Halloran } else if (pdev->is_physfn) { 2870965c94f3SOliver O'Halloran /* 2871965c94f3SOliver O'Halloran * For PFs adjust their allocated IOV resources to match what 2872965c94f3SOliver O'Halloran * the PHB can support using it's M64 BAR table. 2873965c94f3SOliver O'Halloran */ 2874965c94f3SOliver O'Halloran pnv_pci_ioda_fixup_iov_resources(pdev); 2875965c94f3SOliver O'Halloran } 2876965c94f3SOliver O'Halloran } 28776e628c7dSWei Yang #endif /* CONFIG_PCI_IOV */ 28786e628c7dSWei Yang 287923e79425SGavin Shan static void pnv_ioda_setup_pe_res(struct pnv_ioda_pe *pe, 288023e79425SGavin Shan struct resource *res) 288111685becSGavin Shan { 288223e79425SGavin Shan struct pnv_phb *phb = pe->phb; 288311685becSGavin Shan struct pci_bus_region region; 288423e79425SGavin Shan int index; 288523e79425SGavin Shan int64_t rc; 288611685becSGavin Shan 288723e79425SGavin Shan if (!res || !res->flags || res->start > res->end) 288823e79425SGavin Shan return; 288911685becSGavin Shan 289011685becSGavin Shan if (res->flags & IORESOURCE_IO) { 289111685becSGavin Shan region.start = res->start - phb->ioda.io_pci_base; 289211685becSGavin Shan region.end = res->end - phb->ioda.io_pci_base; 289311685becSGavin Shan index = region.start / phb->ioda.io_segsize; 289411685becSGavin Shan 289592b8f137SGavin Shan while (index < phb->ioda.total_pe_num && 289611685becSGavin Shan region.start <= region.end) { 289711685becSGavin Shan phb->ioda.io_segmap[index] = pe->pe_number; 289811685becSGavin Shan rc = opal_pci_map_pe_mmio_window(phb->opal_id, 289911685becSGavin Shan pe->pe_number, OPAL_IO_WINDOW_TYPE, 0, index); 290011685becSGavin Shan if (rc != OPAL_SUCCESS) { 29011f52f176SRussell Currey pr_err("%s: Error %lld mapping IO segment#%d to PE#%x\n", 290211685becSGavin Shan __func__, rc, index, pe->pe_number); 290311685becSGavin Shan break; 290411685becSGavin Shan } 290511685becSGavin Shan 290611685becSGavin Shan region.start += phb->ioda.io_segsize; 290711685becSGavin Shan index++; 290811685becSGavin Shan } 2909027fa02fSGavin Shan } else if ((res->flags & IORESOURCE_MEM) && 29105958d19aSBenjamin Herrenschmidt !pnv_pci_is_m64(phb, res)) { 291111685becSGavin Shan region.start = res->start - 291223e79425SGavin Shan phb->hose->mem_offset[0] - 291311685becSGavin Shan phb->ioda.m32_pci_base; 291411685becSGavin Shan region.end = res->end - 291523e79425SGavin Shan phb->hose->mem_offset[0] - 291611685becSGavin Shan phb->ioda.m32_pci_base; 291711685becSGavin Shan index = region.start / phb->ioda.m32_segsize; 291811685becSGavin Shan 291992b8f137SGavin Shan while (index < phb->ioda.total_pe_num && 292011685becSGavin Shan region.start <= region.end) { 292111685becSGavin Shan phb->ioda.m32_segmap[index] = pe->pe_number; 292211685becSGavin Shan rc = opal_pci_map_pe_mmio_window(phb->opal_id, 292311685becSGavin Shan pe->pe_number, OPAL_M32_WINDOW_TYPE, 0, index); 292411685becSGavin Shan if (rc != OPAL_SUCCESS) { 29251f52f176SRussell Currey pr_err("%s: Error %lld mapping M32 segment#%d to PE#%x", 292611685becSGavin Shan __func__, rc, index, pe->pe_number); 292711685becSGavin Shan break; 292811685becSGavin Shan } 292911685becSGavin Shan 293011685becSGavin Shan region.start += phb->ioda.m32_segsize; 293111685becSGavin Shan index++; 293211685becSGavin Shan } 293311685becSGavin Shan } 293411685becSGavin Shan } 293523e79425SGavin Shan 293623e79425SGavin Shan /* 293723e79425SGavin Shan * This function is supposed to be called on basis of PE from top 293823e79425SGavin Shan * to bottom style. So the the I/O or MMIO segment assigned to 293903671057SMasahiro Yamada * parent PE could be overridden by its child PEs if necessary. 294023e79425SGavin Shan */ 294123e79425SGavin Shan static void pnv_ioda_setup_pe_seg(struct pnv_ioda_pe *pe) 294223e79425SGavin Shan { 294369d733e7SGavin Shan struct pci_dev *pdev; 294423e79425SGavin Shan int i; 294523e79425SGavin Shan 294623e79425SGavin Shan /* 294723e79425SGavin Shan * NOTE: We only care PCI bus based PE for now. For PCI 294823e79425SGavin Shan * device based PE, for example SRIOV sensitive VF should 294923e79425SGavin Shan * be figured out later. 295023e79425SGavin Shan */ 295123e79425SGavin Shan BUG_ON(!(pe->flags & (PNV_IODA_PE_BUS | PNV_IODA_PE_BUS_ALL))); 295223e79425SGavin Shan 295369d733e7SGavin Shan list_for_each_entry(pdev, &pe->pbus->devices, bus_list) { 295469d733e7SGavin Shan for (i = 0; i <= PCI_ROM_RESOURCE; i++) 295569d733e7SGavin Shan pnv_ioda_setup_pe_res(pe, &pdev->resource[i]); 295669d733e7SGavin Shan 295769d733e7SGavin Shan /* 295869d733e7SGavin Shan * If the PE contains all subordinate PCI buses, the 295969d733e7SGavin Shan * windows of the child bridges should be mapped to 296069d733e7SGavin Shan * the PE as well. 296169d733e7SGavin Shan */ 296269d733e7SGavin Shan if (!(pe->flags & PNV_IODA_PE_BUS_ALL) || !pci_is_bridge(pdev)) 296369d733e7SGavin Shan continue; 296469d733e7SGavin Shan for (i = 0; i < PCI_BRIDGE_RESOURCE_NUM; i++) 296569d733e7SGavin Shan pnv_ioda_setup_pe_res(pe, 296669d733e7SGavin Shan &pdev->resource[PCI_BRIDGE_RESOURCES + i]); 296769d733e7SGavin Shan } 296811685becSGavin Shan } 296911685becSGavin Shan 297098b665daSRussell Currey #ifdef CONFIG_DEBUG_FS 297198b665daSRussell Currey static int pnv_pci_diag_data_set(void *data, u64 val) 297298b665daSRussell Currey { 297322ba7289SOliver O'Halloran struct pnv_phb *phb = data; 297498b665daSRussell Currey s64 ret; 297598b665daSRussell Currey 297698b665daSRussell Currey /* Retrieve the diag data from firmware */ 29775cb1f8fdSRussell Currey ret = opal_pci_get_phb_diag_data2(phb->opal_id, phb->diag_data, 29785cb1f8fdSRussell Currey phb->diag_data_size); 297998b665daSRussell Currey if (ret != OPAL_SUCCESS) 298098b665daSRussell Currey return -EIO; 298198b665daSRussell Currey 298298b665daSRussell Currey /* Print the diag data to the kernel log */ 29835cb1f8fdSRussell Currey pnv_pci_dump_phb_diag_data(phb->hose, phb->diag_data); 298498b665daSRussell Currey return 0; 298598b665daSRussell Currey } 298698b665daSRussell Currey 2987bfa2325eSYueHaibing DEFINE_DEBUGFS_ATTRIBUTE(pnv_pci_diag_data_fops, NULL, pnv_pci_diag_data_set, 2988bfa2325eSYueHaibing "%llu\n"); 298998b665daSRussell Currey 299018697d2bSOliver O'Halloran static int pnv_pci_ioda_pe_dump(void *data, u64 val) 299118697d2bSOliver O'Halloran { 299218697d2bSOliver O'Halloran struct pnv_phb *phb = data; 299318697d2bSOliver O'Halloran int pe_num; 299418697d2bSOliver O'Halloran 299518697d2bSOliver O'Halloran for (pe_num = 0; pe_num < phb->ioda.total_pe_num; pe_num++) { 299618697d2bSOliver O'Halloran struct pnv_ioda_pe *pe = &phb->ioda.pe_array[pe_num]; 299718697d2bSOliver O'Halloran 299818697d2bSOliver O'Halloran if (!test_bit(pe_num, phb->ioda.pe_alloc)) 299918697d2bSOliver O'Halloran continue; 300018697d2bSOliver O'Halloran 300118697d2bSOliver O'Halloran pe_warn(pe, "rid: %04x dev count: %2d flags: %s%s%s%s%s%s\n", 300218697d2bSOliver O'Halloran pe->rid, pe->device_count, 300318697d2bSOliver O'Halloran (pe->flags & PNV_IODA_PE_DEV) ? "dev " : "", 300418697d2bSOliver O'Halloran (pe->flags & PNV_IODA_PE_BUS) ? "bus " : "", 300518697d2bSOliver O'Halloran (pe->flags & PNV_IODA_PE_BUS_ALL) ? "all " : "", 300618697d2bSOliver O'Halloran (pe->flags & PNV_IODA_PE_MASTER) ? "master " : "", 300718697d2bSOliver O'Halloran (pe->flags & PNV_IODA_PE_SLAVE) ? "slave " : "", 300818697d2bSOliver O'Halloran (pe->flags & PNV_IODA_PE_VF) ? "vf " : ""); 300918697d2bSOliver O'Halloran } 301018697d2bSOliver O'Halloran 301118697d2bSOliver O'Halloran return 0; 301218697d2bSOliver O'Halloran } 301318697d2bSOliver O'Halloran 301418697d2bSOliver O'Halloran DEFINE_DEBUGFS_ATTRIBUTE(pnv_pci_ioda_pe_dump_fops, NULL, 301518697d2bSOliver O'Halloran pnv_pci_ioda_pe_dump, "%llu\n"); 301618697d2bSOliver O'Halloran 301798b665daSRussell Currey #endif /* CONFIG_DEBUG_FS */ 301898b665daSRussell Currey 301937c367f2SGavin Shan static void pnv_pci_ioda_create_dbgfs(void) 302037c367f2SGavin Shan { 302137c367f2SGavin Shan #ifdef CONFIG_DEBUG_FS 302237c367f2SGavin Shan struct pci_controller *hose, *tmp; 302337c367f2SGavin Shan struct pnv_phb *phb; 302437c367f2SGavin Shan char name[16]; 302537c367f2SGavin Shan 302637c367f2SGavin Shan list_for_each_entry_safe(hose, tmp, &hose_list, list_node) { 302737c367f2SGavin Shan phb = hose->private_data; 302837c367f2SGavin Shan 3029ccd1c191SGavin Shan /* Notify initialization of PHB done */ 3030ccd1c191SGavin Shan phb->initialized = 1; 3031ccd1c191SGavin Shan 303237c367f2SGavin Shan sprintf(name, "PCI%04x", hose->global_number); 303337c367f2SGavin Shan phb->dbgfs = debugfs_create_dir(name, powerpc_debugfs_root); 303498b665daSRussell Currey 3035bfa2325eSYueHaibing debugfs_create_file_unsafe("dump_diag_regs", 0200, phb->dbgfs, 303622ba7289SOliver O'Halloran phb, &pnv_pci_diag_data_fops); 303718697d2bSOliver O'Halloran debugfs_create_file_unsafe("dump_ioda_pe_state", 0200, phb->dbgfs, 303818697d2bSOliver O'Halloran phb, &pnv_pci_ioda_pe_dump_fops); 303937c367f2SGavin Shan } 304037c367f2SGavin Shan #endif /* CONFIG_DEBUG_FS */ 304137c367f2SGavin Shan } 304237c367f2SGavin Shan 3043db217319SBenjamin Herrenschmidt static void pnv_pci_enable_bridge(struct pci_bus *bus) 3044db217319SBenjamin Herrenschmidt { 3045db217319SBenjamin Herrenschmidt struct pci_dev *dev = bus->self; 3046db217319SBenjamin Herrenschmidt struct pci_bus *child; 3047db217319SBenjamin Herrenschmidt 3048db217319SBenjamin Herrenschmidt /* Empty bus ? bail */ 3049db217319SBenjamin Herrenschmidt if (list_empty(&bus->devices)) 3050db217319SBenjamin Herrenschmidt return; 3051db217319SBenjamin Herrenschmidt 3052db217319SBenjamin Herrenschmidt /* 3053db217319SBenjamin Herrenschmidt * If there's a bridge associated with that bus enable it. This works 3054db217319SBenjamin Herrenschmidt * around races in the generic code if the enabling is done during 3055db217319SBenjamin Herrenschmidt * parallel probing. This can be removed once those races have been 3056db217319SBenjamin Herrenschmidt * fixed. 3057db217319SBenjamin Herrenschmidt */ 3058db217319SBenjamin Herrenschmidt if (dev) { 3059db217319SBenjamin Herrenschmidt int rc = pci_enable_device(dev); 3060db217319SBenjamin Herrenschmidt if (rc) 3061db217319SBenjamin Herrenschmidt pci_err(dev, "Error enabling bridge (%d)\n", rc); 3062db217319SBenjamin Herrenschmidt pci_set_master(dev); 3063db217319SBenjamin Herrenschmidt } 3064db217319SBenjamin Herrenschmidt 3065db217319SBenjamin Herrenschmidt /* Perform the same to child busses */ 3066db217319SBenjamin Herrenschmidt list_for_each_entry(child, &bus->children, node) 3067db217319SBenjamin Herrenschmidt pnv_pci_enable_bridge(child); 3068db217319SBenjamin Herrenschmidt } 3069db217319SBenjamin Herrenschmidt 3070db217319SBenjamin Herrenschmidt static void pnv_pci_enable_bridges(void) 3071db217319SBenjamin Herrenschmidt { 3072db217319SBenjamin Herrenschmidt struct pci_controller *hose; 3073db217319SBenjamin Herrenschmidt 3074db217319SBenjamin Herrenschmidt list_for_each_entry(hose, &hose_list, list_node) 3075db217319SBenjamin Herrenschmidt pnv_pci_enable_bridge(hose->bus); 3076db217319SBenjamin Herrenschmidt } 3077db217319SBenjamin Herrenschmidt 3078cad5cef6SGreg Kroah-Hartman static void pnv_pci_ioda_fixup(void) 3079fb446ad0SGavin Shan { 308003b7bf34SOliver O'Halloran pnv_pci_ioda_setup_nvlink(); 308137c367f2SGavin Shan pnv_pci_ioda_create_dbgfs(); 308237c367f2SGavin Shan 3083db217319SBenjamin Herrenschmidt pnv_pci_enable_bridges(); 3084db217319SBenjamin Herrenschmidt 3085e9cc17d4SGavin Shan #ifdef CONFIG_EEH 3086b9fde58dSBenjamin Herrenschmidt pnv_eeh_post_init(); 3087e9cc17d4SGavin Shan #endif 3088fb446ad0SGavin Shan } 3089fb446ad0SGavin Shan 3090271fd03aSGavin Shan /* 3091271fd03aSGavin Shan * Returns the alignment for I/O or memory windows for P2P 3092271fd03aSGavin Shan * bridges. That actually depends on how PEs are segmented. 3093271fd03aSGavin Shan * For now, we return I/O or M32 segment size for PE sensitive 3094271fd03aSGavin Shan * P2P bridges. Otherwise, the default values (4KiB for I/O, 3095271fd03aSGavin Shan * 1MiB for memory) will be returned. 3096271fd03aSGavin Shan * 3097271fd03aSGavin Shan * The current PCI bus might be put into one PE, which was 3098271fd03aSGavin Shan * create against the parent PCI bridge. For that case, we 3099271fd03aSGavin Shan * needn't enlarge the alignment so that we can save some 3100271fd03aSGavin Shan * resources. 3101271fd03aSGavin Shan */ 3102271fd03aSGavin Shan static resource_size_t pnv_pci_window_alignment(struct pci_bus *bus, 3103271fd03aSGavin Shan unsigned long type) 3104271fd03aSGavin Shan { 3105271fd03aSGavin Shan struct pci_dev *bridge; 3106271fd03aSGavin Shan struct pci_controller *hose = pci_bus_to_host(bus); 3107271fd03aSGavin Shan struct pnv_phb *phb = hose->private_data; 3108271fd03aSGavin Shan int num_pci_bridges = 0; 3109271fd03aSGavin Shan 3110271fd03aSGavin Shan bridge = bus->self; 3111271fd03aSGavin Shan while (bridge) { 3112271fd03aSGavin Shan if (pci_pcie_type(bridge) == PCI_EXP_TYPE_PCI_BRIDGE) { 3113271fd03aSGavin Shan num_pci_bridges++; 3114271fd03aSGavin Shan if (num_pci_bridges >= 2) 3115271fd03aSGavin Shan return 1; 3116271fd03aSGavin Shan } 3117271fd03aSGavin Shan 3118271fd03aSGavin Shan bridge = bridge->bus->self; 3119271fd03aSGavin Shan } 3120271fd03aSGavin Shan 31215958d19aSBenjamin Herrenschmidt /* 31225958d19aSBenjamin Herrenschmidt * We fall back to M32 if M64 isn't supported. We enforce the M64 31235958d19aSBenjamin Herrenschmidt * alignment for any 64-bit resource, PCIe doesn't care and 31245958d19aSBenjamin Herrenschmidt * bridges only do 64-bit prefetchable anyway. 31255958d19aSBenjamin Herrenschmidt */ 3126b79331a5SRussell Currey if (phb->ioda.m64_segsize && pnv_pci_is_m64_flags(type)) 3127262af557SGuo Chao return phb->ioda.m64_segsize; 3128271fd03aSGavin Shan if (type & IORESOURCE_MEM) 3129271fd03aSGavin Shan return phb->ioda.m32_segsize; 3130271fd03aSGavin Shan 3131271fd03aSGavin Shan return phb->ioda.io_segsize; 3132271fd03aSGavin Shan } 3133271fd03aSGavin Shan 313440e2a47eSGavin Shan /* 313540e2a47eSGavin Shan * We are updating root port or the upstream port of the 313640e2a47eSGavin Shan * bridge behind the root port with PHB's windows in order 313740e2a47eSGavin Shan * to accommodate the changes on required resources during 313840e2a47eSGavin Shan * PCI (slot) hotplug, which is connected to either root 313940e2a47eSGavin Shan * port or the downstream ports of PCIe switch behind the 314040e2a47eSGavin Shan * root port. 314140e2a47eSGavin Shan */ 314240e2a47eSGavin Shan static void pnv_pci_fixup_bridge_resources(struct pci_bus *bus, 314340e2a47eSGavin Shan unsigned long type) 314440e2a47eSGavin Shan { 314540e2a47eSGavin Shan struct pci_controller *hose = pci_bus_to_host(bus); 314640e2a47eSGavin Shan struct pnv_phb *phb = hose->private_data; 314740e2a47eSGavin Shan struct pci_dev *bridge = bus->self; 314840e2a47eSGavin Shan struct resource *r, *w; 314940e2a47eSGavin Shan bool msi_region = false; 315040e2a47eSGavin Shan int i; 315140e2a47eSGavin Shan 315240e2a47eSGavin Shan /* Check if we need apply fixup to the bridge's windows */ 315340e2a47eSGavin Shan if (!pci_is_root_bus(bridge->bus) && 315440e2a47eSGavin Shan !pci_is_root_bus(bridge->bus->self->bus)) 315540e2a47eSGavin Shan return; 315640e2a47eSGavin Shan 315740e2a47eSGavin Shan /* Fixup the resources */ 315840e2a47eSGavin Shan for (i = 0; i < PCI_BRIDGE_RESOURCE_NUM; i++) { 315940e2a47eSGavin Shan r = &bridge->resource[PCI_BRIDGE_RESOURCES + i]; 316040e2a47eSGavin Shan if (!r->flags || !r->parent) 316140e2a47eSGavin Shan continue; 316240e2a47eSGavin Shan 316340e2a47eSGavin Shan w = NULL; 316440e2a47eSGavin Shan if (r->flags & type & IORESOURCE_IO) 316540e2a47eSGavin Shan w = &hose->io_resource; 31665958d19aSBenjamin Herrenschmidt else if (pnv_pci_is_m64(phb, r) && 316740e2a47eSGavin Shan (type & IORESOURCE_PREFETCH) && 316840e2a47eSGavin Shan phb->ioda.m64_segsize) 316940e2a47eSGavin Shan w = &hose->mem_resources[1]; 317040e2a47eSGavin Shan else if (r->flags & type & IORESOURCE_MEM) { 317140e2a47eSGavin Shan w = &hose->mem_resources[0]; 317240e2a47eSGavin Shan msi_region = true; 317340e2a47eSGavin Shan } 317440e2a47eSGavin Shan 317540e2a47eSGavin Shan r->start = w->start; 317640e2a47eSGavin Shan r->end = w->end; 317740e2a47eSGavin Shan 317840e2a47eSGavin Shan /* The 64KB 32-bits MSI region shouldn't be included in 317940e2a47eSGavin Shan * the 32-bits bridge window. Otherwise, we can see strange 318040e2a47eSGavin Shan * issues. One of them is EEH error observed on Garrison. 318140e2a47eSGavin Shan * 318240e2a47eSGavin Shan * Exclude top 1MB region which is the minimal alignment of 318340e2a47eSGavin Shan * 32-bits bridge window. 318440e2a47eSGavin Shan */ 318540e2a47eSGavin Shan if (msi_region) { 318640e2a47eSGavin Shan r->end += 0x10000; 318740e2a47eSGavin Shan r->end -= 0x100000; 318840e2a47eSGavin Shan } 318940e2a47eSGavin Shan } 319040e2a47eSGavin Shan } 319140e2a47eSGavin Shan 3192dc3d8f85SOliver O'Halloran static void pnv_pci_configure_bus(struct pci_bus *bus) 3193ccd1c191SGavin Shan { 3194ccd1c191SGavin Shan struct pci_controller *hose = pci_bus_to_host(bus); 3195ccd1c191SGavin Shan struct pnv_phb *phb = hose->private_data; 3196ccd1c191SGavin Shan struct pci_dev *bridge = bus->self; 3197ccd1c191SGavin Shan struct pnv_ioda_pe *pe; 3198dc3d8f85SOliver O'Halloran bool all = (bridge && pci_pcie_type(bridge) == PCI_EXP_TYPE_PCI_BRIDGE); 3199ccd1c191SGavin Shan 3200dc3d8f85SOliver O'Halloran dev_info(&bus->dev, "Configuring PE for bus\n"); 320140e2a47eSGavin Shan 320263803c39SGavin Shan /* The PE for root bus should be realized before any one else */ 320363803c39SGavin Shan if (!phb->ioda.root_pe_populated) { 320463803c39SGavin Shan pe = pnv_ioda_setup_bus_PE(phb->hose->bus, false); 320563803c39SGavin Shan if (pe) { 320663803c39SGavin Shan phb->ioda.root_pe_idx = pe->pe_number; 320763803c39SGavin Shan phb->ioda.root_pe_populated = true; 320863803c39SGavin Shan } 320963803c39SGavin Shan } 321063803c39SGavin Shan 3211ccd1c191SGavin Shan /* Don't assign PE to PCI bus, which doesn't have subordinate devices */ 3212ccd1c191SGavin Shan if (list_empty(&bus->devices)) 3213ccd1c191SGavin Shan return; 3214ccd1c191SGavin Shan 3215ccd1c191SGavin Shan /* Reserve PEs according to used M64 resources */ 3216a25de7afSAlexey Kardashevskiy pnv_ioda_reserve_m64_pe(bus, NULL, all); 3217ccd1c191SGavin Shan 3218ccd1c191SGavin Shan /* 3219ccd1c191SGavin Shan * Assign PE. We might run here because of partial hotplug. 3220ccd1c191SGavin Shan * For the case, we just pick up the existing PE and should 3221ccd1c191SGavin Shan * not allocate resources again. 3222ccd1c191SGavin Shan */ 3223ccd1c191SGavin Shan pe = pnv_ioda_setup_bus_PE(bus, all); 3224ccd1c191SGavin Shan if (!pe) 3225ccd1c191SGavin Shan return; 3226ccd1c191SGavin Shan 3227ccd1c191SGavin Shan pnv_ioda_setup_pe_seg(pe); 3228ccd1c191SGavin Shan switch (phb->type) { 3229ccd1c191SGavin Shan case PNV_PHB_IODA1: 3230ccd1c191SGavin Shan pnv_pci_ioda1_setup_dma_pe(phb, pe); 3231ccd1c191SGavin Shan break; 3232ccd1c191SGavin Shan case PNV_PHB_IODA2: 3233ccd1c191SGavin Shan pnv_pci_ioda2_setup_dma_pe(phb, pe); 3234ccd1c191SGavin Shan break; 3235ccd1c191SGavin Shan default: 32361f52f176SRussell Currey pr_warn("%s: No DMA for PHB#%x (type %d)\n", 3237ccd1c191SGavin Shan __func__, phb->hose->global_number, phb->type); 3238ccd1c191SGavin Shan } 3239ccd1c191SGavin Shan } 3240ccd1c191SGavin Shan 324138274637SYongji Xie static resource_size_t pnv_pci_default_alignment(void) 324238274637SYongji Xie { 324338274637SYongji Xie return PAGE_SIZE; 324438274637SYongji Xie } 324538274637SYongji Xie 32465350ab3fSWei Yang #ifdef CONFIG_PCI_IOV 32475350ab3fSWei Yang static resource_size_t pnv_pci_iov_resource_alignment(struct pci_dev *pdev, 32485350ab3fSWei Yang int resno) 32495350ab3fSWei Yang { 3250ee8222feSWei Yang struct pci_controller *hose = pci_bus_to_host(pdev->bus); 3251ee8222feSWei Yang struct pnv_phb *phb = hose->private_data; 32525350ab3fSWei Yang struct pci_dn *pdn = pci_get_pdn(pdev); 32537fbe7a93SWei Yang resource_size_t align; 32545350ab3fSWei Yang 32557fbe7a93SWei Yang /* 32567fbe7a93SWei Yang * On PowerNV platform, IOV BAR is mapped by M64 BAR to enable the 32577fbe7a93SWei Yang * SR-IOV. While from hardware perspective, the range mapped by M64 32587fbe7a93SWei Yang * BAR should be size aligned. 32597fbe7a93SWei Yang * 3260ee8222feSWei Yang * When IOV BAR is mapped with M64 BAR in Single PE mode, the extra 3261ee8222feSWei Yang * powernv-specific hardware restriction is gone. But if just use the 3262ee8222feSWei Yang * VF BAR size as the alignment, PF BAR / VF BAR may be allocated with 3263ee8222feSWei Yang * in one segment of M64 #15, which introduces the PE conflict between 3264ee8222feSWei Yang * PF and VF. Based on this, the minimum alignment of an IOV BAR is 3265ee8222feSWei Yang * m64_segsize. 3266ee8222feSWei Yang * 32677fbe7a93SWei Yang * This function returns the total IOV BAR size if M64 BAR is in 32687fbe7a93SWei Yang * Shared PE mode or just VF BAR size if not. 3269ee8222feSWei Yang * If the M64 BAR is in Single PE mode, return the VF BAR size or 3270ee8222feSWei Yang * M64 segment size if IOV BAR size is less. 32717fbe7a93SWei Yang */ 32725350ab3fSWei Yang align = pci_iov_resource_size(pdev, resno); 32737fbe7a93SWei Yang if (!pdn->vfs_expanded) 32745350ab3fSWei Yang return align; 3275ee8222feSWei Yang if (pdn->m64_single_mode) 3276ee8222feSWei Yang return max(align, (resource_size_t)phb->ioda.m64_segsize); 32777fbe7a93SWei Yang 32787fbe7a93SWei Yang return pdn->vfs_expanded * align; 32795350ab3fSWei Yang } 32805350ab3fSWei Yang #endif /* CONFIG_PCI_IOV */ 32815350ab3fSWei Yang 3282184cd4a3SBenjamin Herrenschmidt /* Prevent enabling devices for which we couldn't properly 3283184cd4a3SBenjamin Herrenschmidt * assign a PE 3284184cd4a3SBenjamin Herrenschmidt */ 32858bf6b91aSAlastair D'Silva static bool pnv_pci_enable_device_hook(struct pci_dev *dev) 3286184cd4a3SBenjamin Herrenschmidt { 3287db1266c8SGavin Shan struct pci_controller *hose = pci_bus_to_host(dev->bus); 3288db1266c8SGavin Shan struct pnv_phb *phb = hose->private_data; 3289db1266c8SGavin Shan struct pci_dn *pdn; 3290184cd4a3SBenjamin Herrenschmidt 3291db1266c8SGavin Shan /* The function is probably called while the PEs have 3292db1266c8SGavin Shan * not be created yet. For example, resource reassignment 3293db1266c8SGavin Shan * during PCI probe period. We just skip the check if 3294db1266c8SGavin Shan * PEs isn't ready. 3295db1266c8SGavin Shan */ 3296db1266c8SGavin Shan if (!phb->initialized) 3297c88c2a18SDaniel Axtens return true; 3298db1266c8SGavin Shan 3299b72c1f65SBenjamin Herrenschmidt pdn = pci_get_pdn(dev); 3300184cd4a3SBenjamin Herrenschmidt if (!pdn || pdn->pe_number == IODA_INVALID_PE) 3301c88c2a18SDaniel Axtens return false; 3302db1266c8SGavin Shan 3303c88c2a18SDaniel Axtens return true; 3304184cd4a3SBenjamin Herrenschmidt } 3305184cd4a3SBenjamin Herrenschmidt 3306c1a2feadSFrederic Barrat static bool pnv_ocapi_enable_device_hook(struct pci_dev *dev) 3307c1a2feadSFrederic Barrat { 3308c1a2feadSFrederic Barrat struct pci_controller *hose = pci_bus_to_host(dev->bus); 3309c1a2feadSFrederic Barrat struct pnv_phb *phb = hose->private_data; 3310c1a2feadSFrederic Barrat struct pci_dn *pdn; 3311c1a2feadSFrederic Barrat struct pnv_ioda_pe *pe; 3312c1a2feadSFrederic Barrat 3313c1a2feadSFrederic Barrat if (!phb->initialized) 3314c1a2feadSFrederic Barrat return true; 3315c1a2feadSFrederic Barrat 3316c1a2feadSFrederic Barrat pdn = pci_get_pdn(dev); 3317c1a2feadSFrederic Barrat if (!pdn) 3318c1a2feadSFrederic Barrat return false; 3319c1a2feadSFrederic Barrat 3320c1a2feadSFrederic Barrat if (pdn->pe_number == IODA_INVALID_PE) { 3321c1a2feadSFrederic Barrat pe = pnv_ioda_setup_dev_PE(dev); 3322c1a2feadSFrederic Barrat if (!pe) 3323c1a2feadSFrederic Barrat return false; 3324c1a2feadSFrederic Barrat } 3325c1a2feadSFrederic Barrat return true; 3326c1a2feadSFrederic Barrat } 3327c1a2feadSFrederic Barrat 3328c5f7700bSGavin Shan static long pnv_pci_ioda1_unset_window(struct iommu_table_group *table_group, 3329c5f7700bSGavin Shan int num) 3330c5f7700bSGavin Shan { 3331c5f7700bSGavin Shan struct pnv_ioda_pe *pe = container_of(table_group, 3332c5f7700bSGavin Shan struct pnv_ioda_pe, table_group); 3333c5f7700bSGavin Shan struct pnv_phb *phb = pe->phb; 3334c5f7700bSGavin Shan unsigned int idx; 3335c5f7700bSGavin Shan long rc; 3336c5f7700bSGavin Shan 3337c5f7700bSGavin Shan pe_info(pe, "Removing DMA window #%d\n", num); 3338c5f7700bSGavin Shan for (idx = 0; idx < phb->ioda.dma32_count; idx++) { 3339c5f7700bSGavin Shan if (phb->ioda.dma32_segmap[idx] != pe->pe_number) 3340c5f7700bSGavin Shan continue; 3341c5f7700bSGavin Shan 3342c5f7700bSGavin Shan rc = opal_pci_map_pe_dma_window(phb->opal_id, pe->pe_number, 3343c5f7700bSGavin Shan idx, 0, 0ul, 0ul, 0ul); 3344c5f7700bSGavin Shan if (rc != OPAL_SUCCESS) { 3345c5f7700bSGavin Shan pe_warn(pe, "Failure %ld unmapping DMA32 segment#%d\n", 3346c5f7700bSGavin Shan rc, idx); 3347c5f7700bSGavin Shan return rc; 3348c5f7700bSGavin Shan } 3349c5f7700bSGavin Shan 3350c5f7700bSGavin Shan phb->ioda.dma32_segmap[idx] = IODA_INVALID_PE; 3351c5f7700bSGavin Shan } 3352c5f7700bSGavin Shan 3353c5f7700bSGavin Shan pnv_pci_unlink_table_and_group(table_group->tables[num], table_group); 3354c5f7700bSGavin Shan return OPAL_SUCCESS; 3355c5f7700bSGavin Shan } 3356c5f7700bSGavin Shan 3357c5f7700bSGavin Shan static void pnv_pci_ioda1_release_pe_dma(struct pnv_ioda_pe *pe) 3358c5f7700bSGavin Shan { 3359c5f7700bSGavin Shan unsigned int weight = pnv_pci_ioda_pe_dma_weight(pe); 3360c5f7700bSGavin Shan struct iommu_table *tbl = pe->table_group.tables[0]; 3361c5f7700bSGavin Shan int64_t rc; 3362c5f7700bSGavin Shan 3363c5f7700bSGavin Shan if (!weight) 3364c5f7700bSGavin Shan return; 3365c5f7700bSGavin Shan 3366c5f7700bSGavin Shan rc = pnv_pci_ioda1_unset_window(&pe->table_group, 0); 3367c5f7700bSGavin Shan if (rc != OPAL_SUCCESS) 3368c5f7700bSGavin Shan return; 3369c5f7700bSGavin Shan 3370a34ab7c3SBenjamin Herrenschmidt pnv_pci_p7ioc_tce_invalidate(tbl, tbl->it_offset, tbl->it_size, false); 3371c5f7700bSGavin Shan if (pe->table_group.group) { 3372c5f7700bSGavin Shan iommu_group_put(pe->table_group.group); 3373c5f7700bSGavin Shan WARN_ON(pe->table_group.group); 3374c5f7700bSGavin Shan } 3375c5f7700bSGavin Shan 3376c5f7700bSGavin Shan free_pages(tbl->it_base, get_order(tbl->it_size << 3)); 3377e5afdf9dSAlexey Kardashevskiy iommu_tce_table_put(tbl); 3378c5f7700bSGavin Shan } 3379c5f7700bSGavin Shan 3380c5f7700bSGavin Shan static void pnv_pci_ioda2_release_pe_dma(struct pnv_ioda_pe *pe) 3381c5f7700bSGavin Shan { 3382c5f7700bSGavin Shan struct iommu_table *tbl = pe->table_group.tables[0]; 3383c5f7700bSGavin Shan unsigned int weight = pnv_pci_ioda_pe_dma_weight(pe); 3384c5f7700bSGavin Shan #ifdef CONFIG_IOMMU_API 3385c5f7700bSGavin Shan int64_t rc; 3386c5f7700bSGavin Shan #endif 3387c5f7700bSGavin Shan 3388c5f7700bSGavin Shan if (!weight) 3389c5f7700bSGavin Shan return; 3390c5f7700bSGavin Shan 3391c5f7700bSGavin Shan #ifdef CONFIG_IOMMU_API 3392c5f7700bSGavin Shan rc = pnv_pci_ioda2_unset_window(&pe->table_group, 0); 3393c5f7700bSGavin Shan if (rc) 33941e496391SJoe Perches pe_warn(pe, "OPAL error %lld release DMA window\n", rc); 3395c5f7700bSGavin Shan #endif 3396c5f7700bSGavin Shan 3397c5f7700bSGavin Shan pnv_pci_ioda2_set_bypass(pe, false); 3398c5f7700bSGavin Shan if (pe->table_group.group) { 3399c5f7700bSGavin Shan iommu_group_put(pe->table_group.group); 3400c5f7700bSGavin Shan WARN_ON(pe->table_group.group); 3401c5f7700bSGavin Shan } 3402c5f7700bSGavin Shan 3403e5afdf9dSAlexey Kardashevskiy iommu_tce_table_put(tbl); 3404c5f7700bSGavin Shan } 3405c5f7700bSGavin Shan 3406c5f7700bSGavin Shan static void pnv_ioda_free_pe_seg(struct pnv_ioda_pe *pe, 3407c5f7700bSGavin Shan unsigned short win, 3408c5f7700bSGavin Shan unsigned int *map) 3409c5f7700bSGavin Shan { 3410c5f7700bSGavin Shan struct pnv_phb *phb = pe->phb; 3411c5f7700bSGavin Shan int idx; 3412c5f7700bSGavin Shan int64_t rc; 3413c5f7700bSGavin Shan 3414c5f7700bSGavin Shan for (idx = 0; idx < phb->ioda.total_pe_num; idx++) { 3415c5f7700bSGavin Shan if (map[idx] != pe->pe_number) 3416c5f7700bSGavin Shan continue; 3417c5f7700bSGavin Shan 3418c5f7700bSGavin Shan if (win == OPAL_M64_WINDOW_TYPE) 3419c5f7700bSGavin Shan rc = opal_pci_map_pe_mmio_window(phb->opal_id, 3420c5f7700bSGavin Shan phb->ioda.reserved_pe_idx, win, 3421c5f7700bSGavin Shan idx / PNV_IODA1_M64_SEGS, 3422c5f7700bSGavin Shan idx % PNV_IODA1_M64_SEGS); 3423c5f7700bSGavin Shan else 3424c5f7700bSGavin Shan rc = opal_pci_map_pe_mmio_window(phb->opal_id, 3425c5f7700bSGavin Shan phb->ioda.reserved_pe_idx, win, 0, idx); 3426c5f7700bSGavin Shan 3427c5f7700bSGavin Shan if (rc != OPAL_SUCCESS) 34281e496391SJoe Perches pe_warn(pe, "Error %lld unmapping (%d) segment#%d\n", 3429c5f7700bSGavin Shan rc, win, idx); 3430c5f7700bSGavin Shan 3431c5f7700bSGavin Shan map[idx] = IODA_INVALID_PE; 3432c5f7700bSGavin Shan } 3433c5f7700bSGavin Shan } 3434c5f7700bSGavin Shan 3435c5f7700bSGavin Shan static void pnv_ioda_release_pe_seg(struct pnv_ioda_pe *pe) 3436c5f7700bSGavin Shan { 3437c5f7700bSGavin Shan struct pnv_phb *phb = pe->phb; 3438c5f7700bSGavin Shan 3439c5f7700bSGavin Shan if (phb->type == PNV_PHB_IODA1) { 3440c5f7700bSGavin Shan pnv_ioda_free_pe_seg(pe, OPAL_IO_WINDOW_TYPE, 3441c5f7700bSGavin Shan phb->ioda.io_segmap); 3442c5f7700bSGavin Shan pnv_ioda_free_pe_seg(pe, OPAL_M32_WINDOW_TYPE, 3443c5f7700bSGavin Shan phb->ioda.m32_segmap); 3444c5f7700bSGavin Shan pnv_ioda_free_pe_seg(pe, OPAL_M64_WINDOW_TYPE, 3445c5f7700bSGavin Shan phb->ioda.m64_segmap); 3446c5f7700bSGavin Shan } else if (phb->type == PNV_PHB_IODA2) { 3447c5f7700bSGavin Shan pnv_ioda_free_pe_seg(pe, OPAL_M32_WINDOW_TYPE, 3448c5f7700bSGavin Shan phb->ioda.m32_segmap); 3449c5f7700bSGavin Shan } 3450c5f7700bSGavin Shan } 3451c5f7700bSGavin Shan 3452c5f7700bSGavin Shan static void pnv_ioda_release_pe(struct pnv_ioda_pe *pe) 3453c5f7700bSGavin Shan { 3454c5f7700bSGavin Shan struct pnv_phb *phb = pe->phb; 3455c5f7700bSGavin Shan struct pnv_ioda_pe *slave, *tmp; 3456c5f7700bSGavin Shan 3457e5500ab6SOliver O'Halloran pe_info(pe, "Releasing PE\n"); 3458e5500ab6SOliver O'Halloran 345980f1ff83SFrederic Barrat mutex_lock(&phb->ioda.pe_list_mutex); 3460c5f7700bSGavin Shan list_del(&pe->list); 346180f1ff83SFrederic Barrat mutex_unlock(&phb->ioda.pe_list_mutex); 346280f1ff83SFrederic Barrat 3463c5f7700bSGavin Shan switch (phb->type) { 3464c5f7700bSGavin Shan case PNV_PHB_IODA1: 3465c5f7700bSGavin Shan pnv_pci_ioda1_release_pe_dma(pe); 3466c5f7700bSGavin Shan break; 3467c5f7700bSGavin Shan case PNV_PHB_IODA2: 3468c5f7700bSGavin Shan pnv_pci_ioda2_release_pe_dma(pe); 3469c5f7700bSGavin Shan break; 3470f724385fSFrederic Barrat case PNV_PHB_NPU_OCAPI: 3471f724385fSFrederic Barrat break; 3472c5f7700bSGavin Shan default: 3473c5f7700bSGavin Shan WARN_ON(1); 3474c5f7700bSGavin Shan } 3475c5f7700bSGavin Shan 3476c5f7700bSGavin Shan pnv_ioda_release_pe_seg(pe); 3477c5f7700bSGavin Shan pnv_ioda_deconfigure_pe(pe->phb, pe); 3478b314427aSGavin Shan 3479b314427aSGavin Shan /* Release slave PEs in the compound PE */ 3480b314427aSGavin Shan if (pe->flags & PNV_IODA_PE_MASTER) { 3481b314427aSGavin Shan list_for_each_entry_safe(slave, tmp, &pe->slaves, list) { 3482b314427aSGavin Shan list_del(&slave->list); 3483b314427aSGavin Shan pnv_ioda_free_pe(slave); 3484b314427aSGavin Shan } 3485b314427aSGavin Shan } 3486b314427aSGavin Shan 34876eaed166SGavin Shan /* 34886eaed166SGavin Shan * The PE for root bus can be removed because of hotplug in EEH 34896eaed166SGavin Shan * recovery for fenced PHB error. We need to mark the PE dead so 34906eaed166SGavin Shan * that it can be populated again in PCI hot add path. The PE 34916eaed166SGavin Shan * shouldn't be destroyed as it's the global reserved resource. 34926eaed166SGavin Shan */ 34936eaed166SGavin Shan if (phb->ioda.root_pe_populated && 34946eaed166SGavin Shan phb->ioda.root_pe_idx == pe->pe_number) 34956eaed166SGavin Shan phb->ioda.root_pe_populated = false; 34966eaed166SGavin Shan else 3497c5f7700bSGavin Shan pnv_ioda_free_pe(pe); 3498c5f7700bSGavin Shan } 3499c5f7700bSGavin Shan 3500c5f7700bSGavin Shan static void pnv_pci_release_device(struct pci_dev *pdev) 3501c5f7700bSGavin Shan { 3502c5f7700bSGavin Shan struct pci_controller *hose = pci_bus_to_host(pdev->bus); 3503c5f7700bSGavin Shan struct pnv_phb *phb = hose->private_data; 3504c5f7700bSGavin Shan struct pci_dn *pdn = pci_get_pdn(pdev); 3505c5f7700bSGavin Shan struct pnv_ioda_pe *pe; 3506c5f7700bSGavin Shan 3507c5f7700bSGavin Shan if (pdev->is_virtfn) 3508c5f7700bSGavin Shan return; 3509c5f7700bSGavin Shan 3510c5f7700bSGavin Shan if (!pdn || pdn->pe_number == IODA_INVALID_PE) 3511c5f7700bSGavin Shan return; 3512c5f7700bSGavin Shan 351329bf282dSGavin Shan /* 351429bf282dSGavin Shan * PCI hotplug can happen as part of EEH error recovery. The @pdn 351529bf282dSGavin Shan * isn't removed and added afterwards in this scenario. We should 351629bf282dSGavin Shan * set the PE number in @pdn to an invalid one. Otherwise, the PE's 351729bf282dSGavin Shan * device count is decreased on removing devices while failing to 351829bf282dSGavin Shan * be increased on adding devices. It leads to unbalanced PE's device 351929bf282dSGavin Shan * count and eventually make normal PCI hotplug path broken. 352029bf282dSGavin Shan */ 3521c5f7700bSGavin Shan pe = &phb->ioda.pe_array[pdn->pe_number]; 352229bf282dSGavin Shan pdn->pe_number = IODA_INVALID_PE; 352329bf282dSGavin Shan 3524c5f7700bSGavin Shan WARN_ON(--pe->device_count < 0); 3525c5f7700bSGavin Shan if (pe->device_count == 0) 3526c5f7700bSGavin Shan pnv_ioda_release_pe(pe); 3527c5f7700bSGavin Shan } 3528c5f7700bSGavin Shan 3529ab7032e7SAlexey Kardashevskiy static void pnv_npu_disable_device(struct pci_dev *pdev) 3530ab7032e7SAlexey Kardashevskiy { 3531ab7032e7SAlexey Kardashevskiy struct eeh_dev *edev = pci_dev_to_eeh_dev(pdev); 3532ab7032e7SAlexey Kardashevskiy struct eeh_pe *eehpe = edev ? edev->pe : NULL; 3533ab7032e7SAlexey Kardashevskiy 3534ab7032e7SAlexey Kardashevskiy if (eehpe && eeh_ops && eeh_ops->reset) 3535ab7032e7SAlexey Kardashevskiy eeh_ops->reset(eehpe, EEH_RESET_HOT); 3536ab7032e7SAlexey Kardashevskiy } 3537ab7032e7SAlexey Kardashevskiy 35387a8e6bbfSMichael Neuling static void pnv_pci_ioda_shutdown(struct pci_controller *hose) 353973ed148aSBenjamin Herrenschmidt { 35407a8e6bbfSMichael Neuling struct pnv_phb *phb = hose->private_data; 35417a8e6bbfSMichael Neuling 3542d1a85eeeSGavin Shan opal_pci_reset(phb->opal_id, OPAL_RESET_PCI_IODA_TABLE, 354373ed148aSBenjamin Herrenschmidt OPAL_ASSERT_RESET); 354473ed148aSBenjamin Herrenschmidt } 354573ed148aSBenjamin Herrenschmidt 3546946743d0SOliver O'Halloran static void pnv_pci_ioda_dma_bus_setup(struct pci_bus *bus) 3547946743d0SOliver O'Halloran { 3548946743d0SOliver O'Halloran struct pci_controller *hose = bus->sysdata; 3549946743d0SOliver O'Halloran struct pnv_phb *phb = hose->private_data; 3550946743d0SOliver O'Halloran struct pnv_ioda_pe *pe; 3551946743d0SOliver O'Halloran 3552946743d0SOliver O'Halloran list_for_each_entry(pe, &phb->ioda.pe_list, list) { 3553946743d0SOliver O'Halloran if (!(pe->flags & (PNV_IODA_PE_BUS | PNV_IODA_PE_BUS_ALL))) 3554946743d0SOliver O'Halloran continue; 3555946743d0SOliver O'Halloran 3556946743d0SOliver O'Halloran if (!pe->pbus) 3557946743d0SOliver O'Halloran continue; 3558946743d0SOliver O'Halloran 3559946743d0SOliver O'Halloran if (bus->number == ((pe->rid >> 8) & 0xFF)) { 3560946743d0SOliver O'Halloran pe->pbus = bus; 3561946743d0SOliver O'Halloran break; 3562946743d0SOliver O'Halloran } 3563946743d0SOliver O'Halloran } 3564946743d0SOliver O'Halloran } 3565946743d0SOliver O'Halloran 356692ae0353SDaniel Axtens static const struct pci_controller_ops pnv_pci_ioda_controller_ops = { 35670a25d9c4SOliver O'Halloran .dma_dev_setup = pnv_pci_ioda_dma_dev_setup, 3568946743d0SOliver O'Halloran .dma_bus_setup = pnv_pci_ioda_dma_bus_setup, 35692d6ad41bSChristoph Hellwig .iommu_bypass_supported = pnv_pci_ioda_iommu_bypass_supported, 357092ae0353SDaniel Axtens .setup_msi_irqs = pnv_setup_msi_irqs, 357192ae0353SDaniel Axtens .teardown_msi_irqs = pnv_teardown_msi_irqs, 357292ae0353SDaniel Axtens .enable_device_hook = pnv_pci_enable_device_hook, 3573c5f7700bSGavin Shan .release_device = pnv_pci_release_device, 357492ae0353SDaniel Axtens .window_alignment = pnv_pci_window_alignment, 3575dc3d8f85SOliver O'Halloran .setup_bridge = pnv_pci_fixup_bridge_resources, 357692ae0353SDaniel Axtens .reset_secondary_bus = pnv_pci_reset_secondary_bus, 35777a8e6bbfSMichael Neuling .shutdown = pnv_pci_ioda_shutdown, 357892ae0353SDaniel Axtens }; 357992ae0353SDaniel Axtens 35805d2aa710SAlistair Popple static const struct pci_controller_ops pnv_npu_ioda_controller_ops = { 35815d2aa710SAlistair Popple .setup_msi_irqs = pnv_setup_msi_irqs, 35825d2aa710SAlistair Popple .teardown_msi_irqs = pnv_teardown_msi_irqs, 35835d2aa710SAlistair Popple .enable_device_hook = pnv_pci_enable_device_hook, 35845d2aa710SAlistair Popple .window_alignment = pnv_pci_window_alignment, 35855d2aa710SAlistair Popple .reset_secondary_bus = pnv_pci_reset_secondary_bus, 35865d2aa710SAlistair Popple .shutdown = pnv_pci_ioda_shutdown, 3587ab7032e7SAlexey Kardashevskiy .disable_device = pnv_npu_disable_device, 35885d2aa710SAlistair Popple }; 35895d2aa710SAlistair Popple 35907f2c39e9SFrederic Barrat static const struct pci_controller_ops pnv_npu_ocapi_ioda_controller_ops = { 3591c1a2feadSFrederic Barrat .enable_device_hook = pnv_ocapi_enable_device_hook, 3592f724385fSFrederic Barrat .release_device = pnv_pci_release_device, 35937f2c39e9SFrederic Barrat .window_alignment = pnv_pci_window_alignment, 35947f2c39e9SFrederic Barrat .reset_secondary_bus = pnv_pci_reset_secondary_bus, 35957f2c39e9SFrederic Barrat .shutdown = pnv_pci_ioda_shutdown, 35967f2c39e9SFrederic Barrat }; 35977f2c39e9SFrederic Barrat 3598e51df2c1SAnton Blanchard static void __init pnv_pci_init_ioda_phb(struct device_node *np, 3599e9cc17d4SGavin Shan u64 hub_id, int ioda_type) 3600184cd4a3SBenjamin Herrenschmidt { 3601184cd4a3SBenjamin Herrenschmidt struct pci_controller *hose; 3602184cd4a3SBenjamin Herrenschmidt struct pnv_phb *phb; 36032b923ed1SGavin Shan unsigned long size, m64map_off, m32map_off, pemap_off; 36042b923ed1SGavin Shan unsigned long iomap_off = 0, dma32map_off = 0; 3605fd141d1aSBenjamin Herrenschmidt struct resource r; 3606c681b93cSAlistair Popple const __be64 *prop64; 36073a1a4661SBenjamin Herrenschmidt const __be32 *prop32; 3608f1b7cc3eSGavin Shan int len; 36093fa23ff8SGavin Shan unsigned int segno; 3610184cd4a3SBenjamin Herrenschmidt u64 phb_id; 3611184cd4a3SBenjamin Herrenschmidt void *aux; 3612184cd4a3SBenjamin Herrenschmidt long rc; 3613184cd4a3SBenjamin Herrenschmidt 361408a45b32SBenjamin Herrenschmidt if (!of_device_is_available(np)) 361508a45b32SBenjamin Herrenschmidt return; 361608a45b32SBenjamin Herrenschmidt 3617b7c670d6SRob Herring pr_info("Initializing %s PHB (%pOF)\n", pnv_phb_names[ioda_type], np); 3618184cd4a3SBenjamin Herrenschmidt 3619184cd4a3SBenjamin Herrenschmidt prop64 = of_get_property(np, "ibm,opal-phbid", NULL); 3620184cd4a3SBenjamin Herrenschmidt if (!prop64) { 3621184cd4a3SBenjamin Herrenschmidt pr_err(" Missing \"ibm,opal-phbid\" property !\n"); 3622184cd4a3SBenjamin Herrenschmidt return; 3623184cd4a3SBenjamin Herrenschmidt } 3624184cd4a3SBenjamin Herrenschmidt phb_id = be64_to_cpup(prop64); 3625184cd4a3SBenjamin Herrenschmidt pr_debug(" PHB-ID : 0x%016llx\n", phb_id); 3626184cd4a3SBenjamin Herrenschmidt 36277e1c4e27SMike Rapoport phb = memblock_alloc(sizeof(*phb), SMP_CACHE_BYTES); 36288a7f97b9SMike Rapoport if (!phb) 36298a7f97b9SMike Rapoport panic("%s: Failed to allocate %zu bytes\n", __func__, 36308a7f97b9SMike Rapoport sizeof(*phb)); 363158d714ecSGavin Shan 363258d714ecSGavin Shan /* Allocate PCI controller */ 3633184cd4a3SBenjamin Herrenschmidt phb->hose = hose = pcibios_alloc_controller(np); 363458d714ecSGavin Shan if (!phb->hose) { 3635b7c670d6SRob Herring pr_err(" Can't allocate PCI controller for %pOF\n", 3636b7c670d6SRob Herring np); 3637e39f223fSMichael Ellerman memblock_free(__pa(phb), sizeof(struct pnv_phb)); 3638184cd4a3SBenjamin Herrenschmidt return; 3639184cd4a3SBenjamin Herrenschmidt } 3640184cd4a3SBenjamin Herrenschmidt 3641184cd4a3SBenjamin Herrenschmidt spin_lock_init(&phb->lock); 3642f1b7cc3eSGavin Shan prop32 = of_get_property(np, "bus-range", &len); 3643f1b7cc3eSGavin Shan if (prop32 && len == 8) { 36443a1a4661SBenjamin Herrenschmidt hose->first_busno = be32_to_cpu(prop32[0]); 36453a1a4661SBenjamin Herrenschmidt hose->last_busno = be32_to_cpu(prop32[1]); 3646f1b7cc3eSGavin Shan } else { 3647b7c670d6SRob Herring pr_warn(" Broken <bus-range> on %pOF\n", np); 3648184cd4a3SBenjamin Herrenschmidt hose->first_busno = 0; 3649184cd4a3SBenjamin Herrenschmidt hose->last_busno = 0xff; 3650f1b7cc3eSGavin Shan } 3651184cd4a3SBenjamin Herrenschmidt hose->private_data = phb; 3652e9cc17d4SGavin Shan phb->hub_id = hub_id; 3653184cd4a3SBenjamin Herrenschmidt phb->opal_id = phb_id; 3654aa0c033fSGavin Shan phb->type = ioda_type; 3655781a868fSWei Yang mutex_init(&phb->ioda.pe_alloc_mutex); 3656184cd4a3SBenjamin Herrenschmidt 3657cee72d5bSBenjamin Herrenschmidt /* Detect specific models for error handling */ 3658cee72d5bSBenjamin Herrenschmidt if (of_device_is_compatible(np, "ibm,p7ioc-pciex")) 3659cee72d5bSBenjamin Herrenschmidt phb->model = PNV_PHB_MODEL_P7IOC; 3660f3d40c25SBenjamin Herrenschmidt else if (of_device_is_compatible(np, "ibm,power8-pciex")) 3661aa0c033fSGavin Shan phb->model = PNV_PHB_MODEL_PHB3; 36625d2aa710SAlistair Popple else if (of_device_is_compatible(np, "ibm,power8-npu-pciex")) 36635d2aa710SAlistair Popple phb->model = PNV_PHB_MODEL_NPU; 3664616badd2SAlistair Popple else if (of_device_is_compatible(np, "ibm,power9-npu-pciex")) 3665616badd2SAlistair Popple phb->model = PNV_PHB_MODEL_NPU2; 3666cee72d5bSBenjamin Herrenschmidt else 3667cee72d5bSBenjamin Herrenschmidt phb->model = PNV_PHB_MODEL_UNKNOWN; 3668cee72d5bSBenjamin Herrenschmidt 36695cb1f8fdSRussell Currey /* Initialize diagnostic data buffer */ 36705cb1f8fdSRussell Currey prop32 = of_get_property(np, "ibm,phb-diag-data-size", NULL); 36715cb1f8fdSRussell Currey if (prop32) 36725cb1f8fdSRussell Currey phb->diag_data_size = be32_to_cpup(prop32); 36735cb1f8fdSRussell Currey else 36745cb1f8fdSRussell Currey phb->diag_data_size = PNV_PCI_DIAG_BUF_SIZE; 36755cb1f8fdSRussell Currey 36767e1c4e27SMike Rapoport phb->diag_data = memblock_alloc(phb->diag_data_size, SMP_CACHE_BYTES); 36778a7f97b9SMike Rapoport if (!phb->diag_data) 36788a7f97b9SMike Rapoport panic("%s: Failed to allocate %u bytes\n", __func__, 36798a7f97b9SMike Rapoport phb->diag_data_size); 36805cb1f8fdSRussell Currey 3681aa0c033fSGavin Shan /* Parse 32-bit and IO ranges (if any) */ 36822f1ec02eSGavin Shan pci_process_bridge_OF_ranges(hose, np, !hose->global_number); 3683184cd4a3SBenjamin Herrenschmidt 3684aa0c033fSGavin Shan /* Get registers */ 3685fd141d1aSBenjamin Herrenschmidt if (!of_address_to_resource(np, 0, &r)) { 3686fd141d1aSBenjamin Herrenschmidt phb->regs_phys = r.start; 3687fd141d1aSBenjamin Herrenschmidt phb->regs = ioremap(r.start, resource_size(&r)); 3688184cd4a3SBenjamin Herrenschmidt if (phb->regs == NULL) 3689184cd4a3SBenjamin Herrenschmidt pr_err(" Failed to map registers !\n"); 3690fd141d1aSBenjamin Herrenschmidt } 3691577c8c88SGavin Shan 3692184cd4a3SBenjamin Herrenschmidt /* Initialize more IODA stuff */ 369392b8f137SGavin Shan phb->ioda.total_pe_num = 1; 369436954dc7SGavin Shan prop32 = of_get_property(np, "ibm,opal-num-pes", NULL); 369536954dc7SGavin Shan if (prop32) 369692b8f137SGavin Shan phb->ioda.total_pe_num = be32_to_cpup(prop32); 369736954dc7SGavin Shan prop32 = of_get_property(np, "ibm,opal-reserved-pe", NULL); 369836954dc7SGavin Shan if (prop32) 369992b8f137SGavin Shan phb->ioda.reserved_pe_idx = be32_to_cpup(prop32); 3700262af557SGuo Chao 3701c127562aSGavin Shan /* Invalidate RID to PE# mapping */ 3702c127562aSGavin Shan for (segno = 0; segno < ARRAY_SIZE(phb->ioda.pe_rmap); segno++) 3703c127562aSGavin Shan phb->ioda.pe_rmap[segno] = IODA_INVALID_PE; 3704c127562aSGavin Shan 3705262af557SGuo Chao /* Parse 64-bit MMIO range */ 3706262af557SGuo Chao pnv_ioda_parse_m64_window(phb); 3707262af557SGuo Chao 3708184cd4a3SBenjamin Herrenschmidt phb->ioda.m32_size = resource_size(&hose->mem_resources[0]); 3709aa0c033fSGavin Shan /* FW Has already off top 64k of M32 space (MSI space) */ 3710184cd4a3SBenjamin Herrenschmidt phb->ioda.m32_size += 0x10000; 3711184cd4a3SBenjamin Herrenschmidt 371292b8f137SGavin Shan phb->ioda.m32_segsize = phb->ioda.m32_size / phb->ioda.total_pe_num; 37133fd47f06SBenjamin Herrenschmidt phb->ioda.m32_pci_base = hose->mem_resources[0].start - hose->mem_offset[0]; 3714184cd4a3SBenjamin Herrenschmidt phb->ioda.io_size = hose->pci_io_size; 371592b8f137SGavin Shan phb->ioda.io_segsize = phb->ioda.io_size / phb->ioda.total_pe_num; 3716184cd4a3SBenjamin Herrenschmidt phb->ioda.io_pci_base = 0; /* XXX calculate this ? */ 3717184cd4a3SBenjamin Herrenschmidt 37182b923ed1SGavin Shan /* Calculate how many 32-bit TCE segments we have */ 37192b923ed1SGavin Shan phb->ioda.dma32_count = phb->ioda.m32_pci_base / 37202b923ed1SGavin Shan PNV_IODA1_DMA32_SEGSIZE; 37212b923ed1SGavin Shan 3722c35d2a8cSGavin Shan /* Allocate aux data & arrays. We don't have IO ports on PHB3 */ 3723b7115316SChristophe Leroy size = ALIGN(max_t(unsigned, phb->ioda.total_pe_num, 8) / 8, 372492a86756SAlexey Kardashevskiy sizeof(unsigned long)); 372593289d8cSGavin Shan m64map_off = size; 372693289d8cSGavin Shan size += phb->ioda.total_pe_num * sizeof(phb->ioda.m64_segmap[0]); 3727184cd4a3SBenjamin Herrenschmidt m32map_off = size; 372892b8f137SGavin Shan size += phb->ioda.total_pe_num * sizeof(phb->ioda.m32_segmap[0]); 3729c35d2a8cSGavin Shan if (phb->type == PNV_PHB_IODA1) { 3730c35d2a8cSGavin Shan iomap_off = size; 373192b8f137SGavin Shan size += phb->ioda.total_pe_num * sizeof(phb->ioda.io_segmap[0]); 37322b923ed1SGavin Shan dma32map_off = size; 37332b923ed1SGavin Shan size += phb->ioda.dma32_count * 37342b923ed1SGavin Shan sizeof(phb->ioda.dma32_segmap[0]); 3735c35d2a8cSGavin Shan } 3736184cd4a3SBenjamin Herrenschmidt pemap_off = size; 373792b8f137SGavin Shan size += phb->ioda.total_pe_num * sizeof(struct pnv_ioda_pe); 37387e1c4e27SMike Rapoport aux = memblock_alloc(size, SMP_CACHE_BYTES); 37398a7f97b9SMike Rapoport if (!aux) 37408a7f97b9SMike Rapoport panic("%s: Failed to allocate %lu bytes\n", __func__, size); 3741184cd4a3SBenjamin Herrenschmidt phb->ioda.pe_alloc = aux; 374293289d8cSGavin Shan phb->ioda.m64_segmap = aux + m64map_off; 3743184cd4a3SBenjamin Herrenschmidt phb->ioda.m32_segmap = aux + m32map_off; 374493289d8cSGavin Shan for (segno = 0; segno < phb->ioda.total_pe_num; segno++) { 374593289d8cSGavin Shan phb->ioda.m64_segmap[segno] = IODA_INVALID_PE; 37463fa23ff8SGavin Shan phb->ioda.m32_segmap[segno] = IODA_INVALID_PE; 374793289d8cSGavin Shan } 37483fa23ff8SGavin Shan if (phb->type == PNV_PHB_IODA1) { 3749184cd4a3SBenjamin Herrenschmidt phb->ioda.io_segmap = aux + iomap_off; 37503fa23ff8SGavin Shan for (segno = 0; segno < phb->ioda.total_pe_num; segno++) 37513fa23ff8SGavin Shan phb->ioda.io_segmap[segno] = IODA_INVALID_PE; 37522b923ed1SGavin Shan 37532b923ed1SGavin Shan phb->ioda.dma32_segmap = aux + dma32map_off; 37542b923ed1SGavin Shan for (segno = 0; segno < phb->ioda.dma32_count; segno++) 37552b923ed1SGavin Shan phb->ioda.dma32_segmap[segno] = IODA_INVALID_PE; 37563fa23ff8SGavin Shan } 3757184cd4a3SBenjamin Herrenschmidt phb->ioda.pe_array = aux + pemap_off; 375863803c39SGavin Shan 375963803c39SGavin Shan /* 376063803c39SGavin Shan * Choose PE number for root bus, which shouldn't have 376163803c39SGavin Shan * M64 resources consumed by its child devices. To pick 376263803c39SGavin Shan * the PE number adjacent to the reserved one if possible. 376363803c39SGavin Shan */ 376463803c39SGavin Shan pnv_ioda_reserve_pe(phb, phb->ioda.reserved_pe_idx); 376563803c39SGavin Shan if (phb->ioda.reserved_pe_idx == 0) { 376663803c39SGavin Shan phb->ioda.root_pe_idx = 1; 376763803c39SGavin Shan pnv_ioda_reserve_pe(phb, phb->ioda.root_pe_idx); 376863803c39SGavin Shan } else if (phb->ioda.reserved_pe_idx == (phb->ioda.total_pe_num - 1)) { 376963803c39SGavin Shan phb->ioda.root_pe_idx = phb->ioda.reserved_pe_idx - 1; 377063803c39SGavin Shan pnv_ioda_reserve_pe(phb, phb->ioda.root_pe_idx); 377163803c39SGavin Shan } else { 377263803c39SGavin Shan phb->ioda.root_pe_idx = IODA_INVALID_PE; 377363803c39SGavin Shan } 3774184cd4a3SBenjamin Herrenschmidt 3775184cd4a3SBenjamin Herrenschmidt INIT_LIST_HEAD(&phb->ioda.pe_list); 3776781a868fSWei Yang mutex_init(&phb->ioda.pe_list_mutex); 3777184cd4a3SBenjamin Herrenschmidt 3778184cd4a3SBenjamin Herrenschmidt /* Calculate how many 32-bit TCE segments we have */ 37792b923ed1SGavin Shan phb->ioda.dma32_count = phb->ioda.m32_pci_base / 3780acce971cSGavin Shan PNV_IODA1_DMA32_SEGSIZE; 3781184cd4a3SBenjamin Herrenschmidt 3782aa0c033fSGavin Shan #if 0 /* We should really do that ... */ 3783184cd4a3SBenjamin Herrenschmidt rc = opal_pci_set_phb_mem_window(opal->phb_id, 3784184cd4a3SBenjamin Herrenschmidt window_type, 3785184cd4a3SBenjamin Herrenschmidt window_num, 3786184cd4a3SBenjamin Herrenschmidt starting_real_address, 3787184cd4a3SBenjamin Herrenschmidt starting_pci_address, 3788184cd4a3SBenjamin Herrenschmidt segment_size); 3789184cd4a3SBenjamin Herrenschmidt #endif 3790184cd4a3SBenjamin Herrenschmidt 3791262af557SGuo Chao pr_info(" %03d (%03d) PE's M32: 0x%x [segment=0x%x]\n", 379292b8f137SGavin Shan phb->ioda.total_pe_num, phb->ioda.reserved_pe_idx, 3793262af557SGuo Chao phb->ioda.m32_size, phb->ioda.m32_segsize); 3794262af557SGuo Chao if (phb->ioda.m64_size) 3795262af557SGuo Chao pr_info(" M64: 0x%lx [segment=0x%lx]\n", 3796262af557SGuo Chao phb->ioda.m64_size, phb->ioda.m64_segsize); 3797262af557SGuo Chao if (phb->ioda.io_size) 3798262af557SGuo Chao pr_info(" IO: 0x%x [segment=0x%x]\n", 3799184cd4a3SBenjamin Herrenschmidt phb->ioda.io_size, phb->ioda.io_segsize); 3800184cd4a3SBenjamin Herrenschmidt 3801262af557SGuo Chao 3802184cd4a3SBenjamin Herrenschmidt phb->hose->ops = &pnv_pci_ops; 380349dec922SGavin Shan phb->get_pe_state = pnv_ioda_get_pe_state; 380449dec922SGavin Shan phb->freeze_pe = pnv_ioda_freeze_pe; 380549dec922SGavin Shan phb->unfreeze_pe = pnv_ioda_unfreeze_pe; 3806184cd4a3SBenjamin Herrenschmidt 3807184cd4a3SBenjamin Herrenschmidt /* Setup MSI support */ 3808184cd4a3SBenjamin Herrenschmidt pnv_pci_init_ioda_msis(phb); 3809184cd4a3SBenjamin Herrenschmidt 3810c40a4210SGavin Shan /* 3811c40a4210SGavin Shan * We pass the PCI probe flag PCI_REASSIGN_ALL_RSRC here 3812c40a4210SGavin Shan * to let the PCI core do resource assignment. It's supposed 3813c40a4210SGavin Shan * that the PCI core will do correct I/O and MMIO alignment 3814c40a4210SGavin Shan * for the P2P bridge bars so that each PCI bus (excluding 3815c40a4210SGavin Shan * the child P2P bridges) can form individual PE. 3816184cd4a3SBenjamin Herrenschmidt */ 3817fb446ad0SGavin Shan ppc_md.pcibios_fixup = pnv_pci_ioda_fixup; 38185d2aa710SAlistair Popple 38197f2c39e9SFrederic Barrat switch (phb->type) { 38207f2c39e9SFrederic Barrat case PNV_PHB_NPU_NVLINK: 38215d2aa710SAlistair Popple hose->controller_ops = pnv_npu_ioda_controller_ops; 38227f2c39e9SFrederic Barrat break; 38237f2c39e9SFrederic Barrat case PNV_PHB_NPU_OCAPI: 38247f2c39e9SFrederic Barrat hose->controller_ops = pnv_npu_ocapi_ioda_controller_ops; 38257f2c39e9SFrederic Barrat break; 38267f2c39e9SFrederic Barrat default: 382792ae0353SDaniel Axtens hose->controller_ops = pnv_pci_ioda_controller_ops; 3828f9f83456SAlexey Kardashevskiy } 3829ad30cb99SMichael Ellerman 383038274637SYongji Xie ppc_md.pcibios_default_alignment = pnv_pci_default_alignment; 383138274637SYongji Xie 38326e628c7dSWei Yang #ifdef CONFIG_PCI_IOV 3833965c94f3SOliver O'Halloran ppc_md.pcibios_fixup_sriov = pnv_pci_ioda_fixup_iov; 38345350ab3fSWei Yang ppc_md.pcibios_iov_resource_alignment = pnv_pci_iov_resource_alignment; 3835988fc3baSBryant G. Ly ppc_md.pcibios_sriov_enable = pnv_pcibios_sriov_enable; 3836988fc3baSBryant G. Ly ppc_md.pcibios_sriov_disable = pnv_pcibios_sriov_disable; 3837ad30cb99SMichael Ellerman #endif 3838ad30cb99SMichael Ellerman 3839c40a4210SGavin Shan pci_add_flags(PCI_REASSIGN_ALL_RSRC); 3840184cd4a3SBenjamin Herrenschmidt 3841184cd4a3SBenjamin Herrenschmidt /* Reset IODA tables to a clean state */ 3842d1a85eeeSGavin Shan rc = opal_pci_reset(phb_id, OPAL_RESET_PCI_IODA_TABLE, OPAL_ASSERT_RESET); 3843184cd4a3SBenjamin Herrenschmidt if (rc) 3844f2c2cbccSJoe Perches pr_warn(" OPAL Error %ld performing IODA table reset !\n", rc); 3845361f2a2aSGavin Shan 38466060e9eaSAndrew Donnellan /* 38476060e9eaSAndrew Donnellan * If we're running in kdump kernel, the previous kernel never 3848361f2a2aSGavin Shan * shutdown PCI devices correctly. We already got IODA table 3849361f2a2aSGavin Shan * cleaned out. So we have to issue PHB reset to stop all PCI 385045baee14SGuilherme G. Piccoli * transactions from previous kernel. The ppc_pci_reset_phbs 3851b174b4fbSOliver O'Halloran * kernel parameter will force this reset too. Additionally, 3852b174b4fbSOliver O'Halloran * if the IODA reset above failed then use a bigger hammer. 3853b174b4fbSOliver O'Halloran * This can happen if we get a PHB fatal error in very early 3854b174b4fbSOliver O'Halloran * boot. 3855361f2a2aSGavin Shan */ 3856b174b4fbSOliver O'Halloran if (is_kdump_kernel() || pci_reset_phbs || rc) { 3857361f2a2aSGavin Shan pr_info(" Issue PHB reset ...\n"); 3858cadf364dSGavin Shan pnv_eeh_phb_reset(hose, EEH_RESET_FUNDAMENTAL); 3859cadf364dSGavin Shan pnv_eeh_phb_reset(hose, EEH_RESET_DEACTIVATE); 3860361f2a2aSGavin Shan } 3861262af557SGuo Chao 38629e9e8935SGavin Shan /* Remove M64 resource if we can't configure it successfully */ 38639e9e8935SGavin Shan if (!phb->init_m64 || phb->init_m64(phb)) 3864262af557SGuo Chao hose->mem_resources[1].flags = 0; 3865184cd4a3SBenjamin Herrenschmidt } 3866184cd4a3SBenjamin Herrenschmidt 386767975005SBjorn Helgaas void __init pnv_pci_init_ioda2_phb(struct device_node *np) 3868aa0c033fSGavin Shan { 3869e9cc17d4SGavin Shan pnv_pci_init_ioda_phb(np, 0, PNV_PHB_IODA2); 3870aa0c033fSGavin Shan } 3871aa0c033fSGavin Shan 38725d2aa710SAlistair Popple void __init pnv_pci_init_npu_phb(struct device_node *np) 38735d2aa710SAlistair Popple { 38747f2c39e9SFrederic Barrat pnv_pci_init_ioda_phb(np, 0, PNV_PHB_NPU_NVLINK); 38755d2aa710SAlistair Popple } 38765d2aa710SAlistair Popple 38777f2c39e9SFrederic Barrat void __init pnv_pci_init_npu2_opencapi_phb(struct device_node *np) 38787f2c39e9SFrederic Barrat { 38797f2c39e9SFrederic Barrat pnv_pci_init_ioda_phb(np, 0, PNV_PHB_NPU_OCAPI); 3880184cd4a3SBenjamin Herrenschmidt } 3881184cd4a3SBenjamin Herrenschmidt 3882228c2f41SAndrew Donnellan static void pnv_npu2_opencapi_cfg_size_fixup(struct pci_dev *dev) 3883228c2f41SAndrew Donnellan { 3884228c2f41SAndrew Donnellan struct pci_controller *hose = pci_bus_to_host(dev->bus); 3885228c2f41SAndrew Donnellan struct pnv_phb *phb = hose->private_data; 3886228c2f41SAndrew Donnellan 3887228c2f41SAndrew Donnellan if (!machine_is(powernv)) 3888228c2f41SAndrew Donnellan return; 3889228c2f41SAndrew Donnellan 3890228c2f41SAndrew Donnellan if (phb->type == PNV_PHB_NPU_OCAPI) 3891228c2f41SAndrew Donnellan dev->cfg_size = PCI_CFG_SPACE_EXP_SIZE; 3892228c2f41SAndrew Donnellan } 3893228c2f41SAndrew Donnellan DECLARE_PCI_FIXUP_EARLY(PCI_ANY_ID, PCI_ANY_ID, pnv_npu2_opencapi_cfg_size_fixup); 3894228c2f41SAndrew Donnellan 3895184cd4a3SBenjamin Herrenschmidt void __init pnv_pci_init_ioda_hub(struct device_node *np) 3896184cd4a3SBenjamin Herrenschmidt { 3897184cd4a3SBenjamin Herrenschmidt struct device_node *phbn; 3898184cd4a3SBenjamin Herrenschmidt const __be64 *prop64; 3899184cd4a3SBenjamin Herrenschmidt u64 hub_id; 3900184cd4a3SBenjamin Herrenschmidt 3901b7c670d6SRob Herring pr_info("Probing IODA IO-Hub %pOF\n", np); 3902184cd4a3SBenjamin Herrenschmidt 3903184cd4a3SBenjamin Herrenschmidt prop64 = of_get_property(np, "ibm,opal-hubid", NULL); 3904184cd4a3SBenjamin Herrenschmidt if (!prop64) { 3905184cd4a3SBenjamin Herrenschmidt pr_err(" Missing \"ibm,opal-hubid\" property !\n"); 3906184cd4a3SBenjamin Herrenschmidt return; 3907184cd4a3SBenjamin Herrenschmidt } 3908184cd4a3SBenjamin Herrenschmidt hub_id = be64_to_cpup(prop64); 3909184cd4a3SBenjamin Herrenschmidt pr_devel(" HUB-ID : 0x%016llx\n", hub_id); 3910184cd4a3SBenjamin Herrenschmidt 3911184cd4a3SBenjamin Herrenschmidt /* Count child PHBs */ 3912184cd4a3SBenjamin Herrenschmidt for_each_child_of_node(np, phbn) { 3913184cd4a3SBenjamin Herrenschmidt /* Look for IODA1 PHBs */ 3914184cd4a3SBenjamin Herrenschmidt if (of_device_is_compatible(phbn, "ibm,ioda-phb")) 3915184cd4a3SBenjamin Herrenschmidt pnv_pci_init_ioda_phb(phbn, hub_id, PNV_PHB_IODA1); 3916184cd4a3SBenjamin Herrenschmidt } 3917184cd4a3SBenjamin Herrenschmidt } 3918