1184cd4a3SBenjamin Herrenschmidt /* 2184cd4a3SBenjamin Herrenschmidt * Support PCI/PCIe on PowerNV platforms 3184cd4a3SBenjamin Herrenschmidt * 4184cd4a3SBenjamin Herrenschmidt * Copyright 2011 Benjamin Herrenschmidt, IBM Corp. 5184cd4a3SBenjamin Herrenschmidt * 6184cd4a3SBenjamin Herrenschmidt * This program is free software; you can redistribute it and/or 7184cd4a3SBenjamin Herrenschmidt * modify it under the terms of the GNU General Public License 8184cd4a3SBenjamin Herrenschmidt * as published by the Free Software Foundation; either version 9184cd4a3SBenjamin Herrenschmidt * 2 of the License, or (at your option) any later version. 10184cd4a3SBenjamin Herrenschmidt */ 11184cd4a3SBenjamin Herrenschmidt 12cee72d5bSBenjamin Herrenschmidt #undef DEBUG 13184cd4a3SBenjamin Herrenschmidt 14184cd4a3SBenjamin Herrenschmidt #include <linux/kernel.h> 15184cd4a3SBenjamin Herrenschmidt #include <linux/pci.h> 16361f2a2aSGavin Shan #include <linux/crash_dump.h> 1737c367f2SGavin Shan #include <linux/debugfs.h> 18184cd4a3SBenjamin Herrenschmidt #include <linux/delay.h> 19184cd4a3SBenjamin Herrenschmidt #include <linux/string.h> 20184cd4a3SBenjamin Herrenschmidt #include <linux/init.h> 21184cd4a3SBenjamin Herrenschmidt #include <linux/bootmem.h> 22184cd4a3SBenjamin Herrenschmidt #include <linux/irq.h> 23184cd4a3SBenjamin Herrenschmidt #include <linux/io.h> 24184cd4a3SBenjamin Herrenschmidt #include <linux/msi.h> 25cd15b048SBenjamin Herrenschmidt #include <linux/memblock.h> 26184cd4a3SBenjamin Herrenschmidt 27184cd4a3SBenjamin Herrenschmidt #include <asm/sections.h> 28184cd4a3SBenjamin Herrenschmidt #include <asm/io.h> 29184cd4a3SBenjamin Herrenschmidt #include <asm/prom.h> 30184cd4a3SBenjamin Herrenschmidt #include <asm/pci-bridge.h> 31184cd4a3SBenjamin Herrenschmidt #include <asm/machdep.h> 32fb1b55d6SGavin Shan #include <asm/msi_bitmap.h> 33184cd4a3SBenjamin Herrenschmidt #include <asm/ppc-pci.h> 34184cd4a3SBenjamin Herrenschmidt #include <asm/opal.h> 35184cd4a3SBenjamin Herrenschmidt #include <asm/iommu.h> 36184cd4a3SBenjamin Herrenschmidt #include <asm/tce.h> 37137436c9SGavin Shan #include <asm/xics.h> 3837c367f2SGavin Shan #include <asm/debug.h> 39262af557SGuo Chao #include <asm/firmware.h> 40184cd4a3SBenjamin Herrenschmidt 41184cd4a3SBenjamin Herrenschmidt #include "powernv.h" 42184cd4a3SBenjamin Herrenschmidt #include "pci.h" 43184cd4a3SBenjamin Herrenschmidt 446d31c2faSJoe Perches static void pe_level_printk(const struct pnv_ioda_pe *pe, const char *level, 456d31c2faSJoe Perches const char *fmt, ...) 466d31c2faSJoe Perches { 476d31c2faSJoe Perches struct va_format vaf; 486d31c2faSJoe Perches va_list args; 496d31c2faSJoe Perches char pfix[32]; 50184cd4a3SBenjamin Herrenschmidt 516d31c2faSJoe Perches va_start(args, fmt); 526d31c2faSJoe Perches 536d31c2faSJoe Perches vaf.fmt = fmt; 546d31c2faSJoe Perches vaf.va = &args; 556d31c2faSJoe Perches 566d31c2faSJoe Perches if (pe->pdev) 576d31c2faSJoe Perches strlcpy(pfix, dev_name(&pe->pdev->dev), sizeof(pfix)); 586d31c2faSJoe Perches else 596d31c2faSJoe Perches sprintf(pfix, "%04x:%02x ", 606d31c2faSJoe Perches pci_domain_nr(pe->pbus), pe->pbus->number); 616d31c2faSJoe Perches 626d31c2faSJoe Perches printk("%spci %s: [PE# %.3d] %pV", 636d31c2faSJoe Perches level, pfix, pe->pe_number, &vaf); 646d31c2faSJoe Perches 656d31c2faSJoe Perches va_end(args); 666d31c2faSJoe Perches } 676d31c2faSJoe Perches 686d31c2faSJoe Perches #define pe_err(pe, fmt, ...) \ 696d31c2faSJoe Perches pe_level_printk(pe, KERN_ERR, fmt, ##__VA_ARGS__) 706d31c2faSJoe Perches #define pe_warn(pe, fmt, ...) \ 716d31c2faSJoe Perches pe_level_printk(pe, KERN_WARNING, fmt, ##__VA_ARGS__) 726d31c2faSJoe Perches #define pe_info(pe, fmt, ...) \ 736d31c2faSJoe Perches pe_level_printk(pe, KERN_INFO, fmt, ##__VA_ARGS__) 74184cd4a3SBenjamin Herrenschmidt 758e0a1611SAlexey Kardashevskiy /* 768e0a1611SAlexey Kardashevskiy * stdcix is only supposed to be used in hypervisor real mode as per 778e0a1611SAlexey Kardashevskiy * the architecture spec 788e0a1611SAlexey Kardashevskiy */ 798e0a1611SAlexey Kardashevskiy static inline void __raw_rm_writeq(u64 val, volatile void __iomem *paddr) 808e0a1611SAlexey Kardashevskiy { 818e0a1611SAlexey Kardashevskiy __asm__ __volatile__("stdcix %0,0,%1" 828e0a1611SAlexey Kardashevskiy : : "r" (val), "r" (paddr) : "memory"); 838e0a1611SAlexey Kardashevskiy } 848e0a1611SAlexey Kardashevskiy 85262af557SGuo Chao static inline bool pnv_pci_is_mem_pref_64(unsigned long flags) 86262af557SGuo Chao { 87262af557SGuo Chao return ((flags & (IORESOURCE_MEM_64 | IORESOURCE_PREFETCH)) == 88262af557SGuo Chao (IORESOURCE_MEM_64 | IORESOURCE_PREFETCH)); 89262af557SGuo Chao } 90262af557SGuo Chao 91cad5cef6SGreg Kroah-Hartman static int pnv_ioda_alloc_pe(struct pnv_phb *phb) 92184cd4a3SBenjamin Herrenschmidt { 93184cd4a3SBenjamin Herrenschmidt unsigned long pe; 94184cd4a3SBenjamin Herrenschmidt 95184cd4a3SBenjamin Herrenschmidt do { 96184cd4a3SBenjamin Herrenschmidt pe = find_next_zero_bit(phb->ioda.pe_alloc, 97184cd4a3SBenjamin Herrenschmidt phb->ioda.total_pe, 0); 98184cd4a3SBenjamin Herrenschmidt if (pe >= phb->ioda.total_pe) 99184cd4a3SBenjamin Herrenschmidt return IODA_INVALID_PE; 100184cd4a3SBenjamin Herrenschmidt } while(test_and_set_bit(pe, phb->ioda.pe_alloc)); 101184cd4a3SBenjamin Herrenschmidt 1024cce9550SGavin Shan phb->ioda.pe_array[pe].phb = phb; 103184cd4a3SBenjamin Herrenschmidt phb->ioda.pe_array[pe].pe_number = pe; 104184cd4a3SBenjamin Herrenschmidt return pe; 105184cd4a3SBenjamin Herrenschmidt } 106184cd4a3SBenjamin Herrenschmidt 107cad5cef6SGreg Kroah-Hartman static void pnv_ioda_free_pe(struct pnv_phb *phb, int pe) 108184cd4a3SBenjamin Herrenschmidt { 109184cd4a3SBenjamin Herrenschmidt WARN_ON(phb->ioda.pe_array[pe].pdev); 110184cd4a3SBenjamin Herrenschmidt 111184cd4a3SBenjamin Herrenschmidt memset(&phb->ioda.pe_array[pe], 0, sizeof(struct pnv_ioda_pe)); 112184cd4a3SBenjamin Herrenschmidt clear_bit(pe, phb->ioda.pe_alloc); 113184cd4a3SBenjamin Herrenschmidt } 114184cd4a3SBenjamin Herrenschmidt 115262af557SGuo Chao /* The default M64 BAR is shared by all PEs */ 116262af557SGuo Chao static int pnv_ioda2_init_m64(struct pnv_phb *phb) 117262af557SGuo Chao { 118262af557SGuo Chao const char *desc; 119262af557SGuo Chao struct resource *r; 120262af557SGuo Chao s64 rc; 121262af557SGuo Chao 122262af557SGuo Chao /* Configure the default M64 BAR */ 123262af557SGuo Chao rc = opal_pci_set_phb_mem_window(phb->opal_id, 124262af557SGuo Chao OPAL_M64_WINDOW_TYPE, 125262af557SGuo Chao phb->ioda.m64_bar_idx, 126262af557SGuo Chao phb->ioda.m64_base, 127262af557SGuo Chao 0, /* unused */ 128262af557SGuo Chao phb->ioda.m64_size); 129262af557SGuo Chao if (rc != OPAL_SUCCESS) { 130262af557SGuo Chao desc = "configuring"; 131262af557SGuo Chao goto fail; 132262af557SGuo Chao } 133262af557SGuo Chao 134262af557SGuo Chao /* Enable the default M64 BAR */ 135262af557SGuo Chao rc = opal_pci_phb_mmio_enable(phb->opal_id, 136262af557SGuo Chao OPAL_M64_WINDOW_TYPE, 137262af557SGuo Chao phb->ioda.m64_bar_idx, 138262af557SGuo Chao OPAL_ENABLE_M64_SPLIT); 139262af557SGuo Chao if (rc != OPAL_SUCCESS) { 140262af557SGuo Chao desc = "enabling"; 141262af557SGuo Chao goto fail; 142262af557SGuo Chao } 143262af557SGuo Chao 144262af557SGuo Chao /* Mark the M64 BAR assigned */ 145262af557SGuo Chao set_bit(phb->ioda.m64_bar_idx, &phb->ioda.m64_bar_alloc); 146262af557SGuo Chao 147262af557SGuo Chao /* 148262af557SGuo Chao * Strip off the segment used by the reserved PE, which is 149262af557SGuo Chao * expected to be 0 or last one of PE capabicity. 150262af557SGuo Chao */ 151262af557SGuo Chao r = &phb->hose->mem_resources[1]; 152262af557SGuo Chao if (phb->ioda.reserved_pe == 0) 153262af557SGuo Chao r->start += phb->ioda.m64_segsize; 154262af557SGuo Chao else if (phb->ioda.reserved_pe == (phb->ioda.total_pe - 1)) 155262af557SGuo Chao r->end -= phb->ioda.m64_segsize; 156262af557SGuo Chao else 157262af557SGuo Chao pr_warn(" Cannot strip M64 segment for reserved PE#%d\n", 158262af557SGuo Chao phb->ioda.reserved_pe); 159262af557SGuo Chao 160262af557SGuo Chao return 0; 161262af557SGuo Chao 162262af557SGuo Chao fail: 163262af557SGuo Chao pr_warn(" Failure %lld %s M64 BAR#%d\n", 164262af557SGuo Chao rc, desc, phb->ioda.m64_bar_idx); 165262af557SGuo Chao opal_pci_phb_mmio_enable(phb->opal_id, 166262af557SGuo Chao OPAL_M64_WINDOW_TYPE, 167262af557SGuo Chao phb->ioda.m64_bar_idx, 168262af557SGuo Chao OPAL_DISABLE_M64); 169262af557SGuo Chao return -EIO; 170262af557SGuo Chao } 171262af557SGuo Chao 172262af557SGuo Chao static void pnv_ioda2_alloc_m64_pe(struct pnv_phb *phb) 173262af557SGuo Chao { 174262af557SGuo Chao resource_size_t sgsz = phb->ioda.m64_segsize; 175262af557SGuo Chao struct pci_dev *pdev; 176262af557SGuo Chao struct resource *r; 177262af557SGuo Chao int base, step, i; 178262af557SGuo Chao 179262af557SGuo Chao /* 180262af557SGuo Chao * Root bus always has full M64 range and root port has 181262af557SGuo Chao * M64 range used in reality. So we're checking root port 182262af557SGuo Chao * instead of root bus. 183262af557SGuo Chao */ 184262af557SGuo Chao list_for_each_entry(pdev, &phb->hose->bus->devices, bus_list) { 185262af557SGuo Chao for (i = PCI_BRIDGE_RESOURCES; 186262af557SGuo Chao i <= PCI_BRIDGE_RESOURCE_END; i++) { 187262af557SGuo Chao r = &pdev->resource[i]; 188262af557SGuo Chao if (!r->parent || 189262af557SGuo Chao !pnv_pci_is_mem_pref_64(r->flags)) 190262af557SGuo Chao continue; 191262af557SGuo Chao 192262af557SGuo Chao base = (r->start - phb->ioda.m64_base) / sgsz; 193262af557SGuo Chao for (step = 0; step < resource_size(r) / sgsz; step++) 194262af557SGuo Chao set_bit(base + step, phb->ioda.pe_alloc); 195262af557SGuo Chao } 196262af557SGuo Chao } 197262af557SGuo Chao } 198262af557SGuo Chao 199262af557SGuo Chao static int pnv_ioda2_pick_m64_pe(struct pnv_phb *phb, 200262af557SGuo Chao struct pci_bus *bus, int all) 201262af557SGuo Chao { 202262af557SGuo Chao resource_size_t segsz = phb->ioda.m64_segsize; 203262af557SGuo Chao struct pci_dev *pdev; 204262af557SGuo Chao struct resource *r; 205262af557SGuo Chao struct pnv_ioda_pe *master_pe, *pe; 206262af557SGuo Chao unsigned long size, *pe_alloc; 207262af557SGuo Chao bool found; 208262af557SGuo Chao int start, i, j; 209262af557SGuo Chao 210262af557SGuo Chao /* Root bus shouldn't use M64 */ 211262af557SGuo Chao if (pci_is_root_bus(bus)) 212262af557SGuo Chao return IODA_INVALID_PE; 213262af557SGuo Chao 214262af557SGuo Chao /* We support only one M64 window on each bus */ 215262af557SGuo Chao found = false; 216262af557SGuo Chao pci_bus_for_each_resource(bus, r, i) { 217262af557SGuo Chao if (r && r->parent && 218262af557SGuo Chao pnv_pci_is_mem_pref_64(r->flags)) { 219262af557SGuo Chao found = true; 220262af557SGuo Chao break; 221262af557SGuo Chao } 222262af557SGuo Chao } 223262af557SGuo Chao 224262af557SGuo Chao /* No M64 window found ? */ 225262af557SGuo Chao if (!found) 226262af557SGuo Chao return IODA_INVALID_PE; 227262af557SGuo Chao 228262af557SGuo Chao /* Allocate bitmap */ 229262af557SGuo Chao size = _ALIGN_UP(phb->ioda.total_pe / 8, sizeof(unsigned long)); 230262af557SGuo Chao pe_alloc = kzalloc(size, GFP_KERNEL); 231262af557SGuo Chao if (!pe_alloc) { 232262af557SGuo Chao pr_warn("%s: Out of memory !\n", 233262af557SGuo Chao __func__); 234262af557SGuo Chao return IODA_INVALID_PE; 235262af557SGuo Chao } 236262af557SGuo Chao 237262af557SGuo Chao /* 238262af557SGuo Chao * Figure out reserved PE numbers by the PE 239262af557SGuo Chao * the its child PEs. 240262af557SGuo Chao */ 241262af557SGuo Chao start = (r->start - phb->ioda.m64_base) / segsz; 242262af557SGuo Chao for (i = 0; i < resource_size(r) / segsz; i++) 243262af557SGuo Chao set_bit(start + i, pe_alloc); 244262af557SGuo Chao 245262af557SGuo Chao if (all) 246262af557SGuo Chao goto done; 247262af557SGuo Chao 248262af557SGuo Chao /* 249262af557SGuo Chao * If the PE doesn't cover all subordinate buses, 250262af557SGuo Chao * we need subtract from reserved PEs for children. 251262af557SGuo Chao */ 252262af557SGuo Chao list_for_each_entry(pdev, &bus->devices, bus_list) { 253262af557SGuo Chao if (!pdev->subordinate) 254262af557SGuo Chao continue; 255262af557SGuo Chao 256262af557SGuo Chao pci_bus_for_each_resource(pdev->subordinate, r, i) { 257262af557SGuo Chao if (!r || !r->parent || 258262af557SGuo Chao !pnv_pci_is_mem_pref_64(r->flags)) 259262af557SGuo Chao continue; 260262af557SGuo Chao 261262af557SGuo Chao start = (r->start - phb->ioda.m64_base) / segsz; 262262af557SGuo Chao for (j = 0; j < resource_size(r) / segsz ; j++) 263262af557SGuo Chao clear_bit(start + j, pe_alloc); 264262af557SGuo Chao } 265262af557SGuo Chao } 266262af557SGuo Chao 267262af557SGuo Chao /* 268262af557SGuo Chao * the current bus might not own M64 window and that's all 269262af557SGuo Chao * contributed by its child buses. For the case, we needn't 270262af557SGuo Chao * pick M64 dependent PE#. 271262af557SGuo Chao */ 272262af557SGuo Chao if (bitmap_empty(pe_alloc, phb->ioda.total_pe)) { 273262af557SGuo Chao kfree(pe_alloc); 274262af557SGuo Chao return IODA_INVALID_PE; 275262af557SGuo Chao } 276262af557SGuo Chao 277262af557SGuo Chao /* 278262af557SGuo Chao * Figure out the master PE and put all slave PEs to master 279262af557SGuo Chao * PE's list to form compound PE. 280262af557SGuo Chao */ 281262af557SGuo Chao done: 282262af557SGuo Chao master_pe = NULL; 283262af557SGuo Chao i = -1; 284262af557SGuo Chao while ((i = find_next_bit(pe_alloc, phb->ioda.total_pe, i + 1)) < 285262af557SGuo Chao phb->ioda.total_pe) { 286262af557SGuo Chao pe = &phb->ioda.pe_array[i]; 287262af557SGuo Chao pe->phb = phb; 288262af557SGuo Chao pe->pe_number = i; 289262af557SGuo Chao 290262af557SGuo Chao if (!master_pe) { 291262af557SGuo Chao pe->flags |= PNV_IODA_PE_MASTER; 292262af557SGuo Chao INIT_LIST_HEAD(&pe->slaves); 293262af557SGuo Chao master_pe = pe; 294262af557SGuo Chao } else { 295262af557SGuo Chao pe->flags |= PNV_IODA_PE_SLAVE; 296262af557SGuo Chao pe->master = master_pe; 297262af557SGuo Chao list_add_tail(&pe->list, &master_pe->slaves); 298262af557SGuo Chao } 299262af557SGuo Chao } 300262af557SGuo Chao 301262af557SGuo Chao kfree(pe_alloc); 302262af557SGuo Chao return master_pe->pe_number; 303262af557SGuo Chao } 304262af557SGuo Chao 305262af557SGuo Chao static void __init pnv_ioda_parse_m64_window(struct pnv_phb *phb) 306262af557SGuo Chao { 307262af557SGuo Chao struct pci_controller *hose = phb->hose; 308262af557SGuo Chao struct device_node *dn = hose->dn; 309262af557SGuo Chao struct resource *res; 310262af557SGuo Chao const u32 *r; 311262af557SGuo Chao u64 pci_addr; 312262af557SGuo Chao 313262af557SGuo Chao if (!firmware_has_feature(FW_FEATURE_OPALv3)) { 314262af557SGuo Chao pr_info(" Firmware too old to support M64 window\n"); 315262af557SGuo Chao return; 316262af557SGuo Chao } 317262af557SGuo Chao 318262af557SGuo Chao r = of_get_property(dn, "ibm,opal-m64-window", NULL); 319262af557SGuo Chao if (!r) { 320262af557SGuo Chao pr_info(" No <ibm,opal-m64-window> on %s\n", 321262af557SGuo Chao dn->full_name); 322262af557SGuo Chao return; 323262af557SGuo Chao } 324262af557SGuo Chao 325262af557SGuo Chao /* FIXME: Support M64 for P7IOC */ 326262af557SGuo Chao if (phb->type != PNV_PHB_IODA2) { 327262af557SGuo Chao pr_info(" Not support M64 window\n"); 328262af557SGuo Chao return; 329262af557SGuo Chao } 330262af557SGuo Chao 331262af557SGuo Chao res = &hose->mem_resources[1]; 332262af557SGuo Chao res->start = of_translate_address(dn, r + 2); 333262af557SGuo Chao res->end = res->start + of_read_number(r + 4, 2) - 1; 334262af557SGuo Chao res->flags = (IORESOURCE_MEM | IORESOURCE_MEM_64 | IORESOURCE_PREFETCH); 335262af557SGuo Chao pci_addr = of_read_number(r, 2); 336262af557SGuo Chao hose->mem_offset[1] = res->start - pci_addr; 337262af557SGuo Chao 338262af557SGuo Chao phb->ioda.m64_size = resource_size(res); 339262af557SGuo Chao phb->ioda.m64_segsize = phb->ioda.m64_size / phb->ioda.total_pe; 340262af557SGuo Chao phb->ioda.m64_base = pci_addr; 341262af557SGuo Chao 342262af557SGuo Chao /* Use last M64 BAR to cover M64 window */ 343262af557SGuo Chao phb->ioda.m64_bar_idx = 15; 344262af557SGuo Chao phb->init_m64 = pnv_ioda2_init_m64; 345262af557SGuo Chao phb->alloc_m64_pe = pnv_ioda2_alloc_m64_pe; 346262af557SGuo Chao phb->pick_m64_pe = pnv_ioda2_pick_m64_pe; 347262af557SGuo Chao } 348262af557SGuo Chao 34949dec922SGavin Shan static void pnv_ioda_freeze_pe(struct pnv_phb *phb, int pe_no) 35049dec922SGavin Shan { 35149dec922SGavin Shan struct pnv_ioda_pe *pe = &phb->ioda.pe_array[pe_no]; 35249dec922SGavin Shan struct pnv_ioda_pe *slave; 35349dec922SGavin Shan s64 rc; 35449dec922SGavin Shan 35549dec922SGavin Shan /* Fetch master PE */ 35649dec922SGavin Shan if (pe->flags & PNV_IODA_PE_SLAVE) { 35749dec922SGavin Shan pe = pe->master; 35849dec922SGavin Shan WARN_ON(!pe || !(pe->flags & PNV_IODA_PE_MASTER)); 35949dec922SGavin Shan pe_no = pe->pe_number; 36049dec922SGavin Shan } 36149dec922SGavin Shan 36249dec922SGavin Shan /* Freeze master PE */ 36349dec922SGavin Shan rc = opal_pci_eeh_freeze_set(phb->opal_id, 36449dec922SGavin Shan pe_no, 36549dec922SGavin Shan OPAL_EEH_ACTION_SET_FREEZE_ALL); 36649dec922SGavin Shan if (rc != OPAL_SUCCESS) { 36749dec922SGavin Shan pr_warn("%s: Failure %lld freezing PHB#%x-PE#%x\n", 36849dec922SGavin Shan __func__, rc, phb->hose->global_number, pe_no); 36949dec922SGavin Shan return; 37049dec922SGavin Shan } 37149dec922SGavin Shan 37249dec922SGavin Shan /* Freeze slave PEs */ 37349dec922SGavin Shan if (!(pe->flags & PNV_IODA_PE_MASTER)) 37449dec922SGavin Shan return; 37549dec922SGavin Shan 37649dec922SGavin Shan list_for_each_entry(slave, &pe->slaves, list) { 37749dec922SGavin Shan rc = opal_pci_eeh_freeze_set(phb->opal_id, 37849dec922SGavin Shan slave->pe_number, 37949dec922SGavin Shan OPAL_EEH_ACTION_SET_FREEZE_ALL); 38049dec922SGavin Shan if (rc != OPAL_SUCCESS) 38149dec922SGavin Shan pr_warn("%s: Failure %lld freezing PHB#%x-PE#%x\n", 38249dec922SGavin Shan __func__, rc, phb->hose->global_number, 38349dec922SGavin Shan slave->pe_number); 38449dec922SGavin Shan } 38549dec922SGavin Shan } 38649dec922SGavin Shan 387e51df2c1SAnton Blanchard static int pnv_ioda_unfreeze_pe(struct pnv_phb *phb, int pe_no, int opt) 38849dec922SGavin Shan { 38949dec922SGavin Shan struct pnv_ioda_pe *pe, *slave; 39049dec922SGavin Shan s64 rc; 39149dec922SGavin Shan 39249dec922SGavin Shan /* Find master PE */ 39349dec922SGavin Shan pe = &phb->ioda.pe_array[pe_no]; 39449dec922SGavin Shan if (pe->flags & PNV_IODA_PE_SLAVE) { 39549dec922SGavin Shan pe = pe->master; 39649dec922SGavin Shan WARN_ON(!pe || !(pe->flags & PNV_IODA_PE_MASTER)); 39749dec922SGavin Shan pe_no = pe->pe_number; 39849dec922SGavin Shan } 39949dec922SGavin Shan 40049dec922SGavin Shan /* Clear frozen state for master PE */ 40149dec922SGavin Shan rc = opal_pci_eeh_freeze_clear(phb->opal_id, pe_no, opt); 40249dec922SGavin Shan if (rc != OPAL_SUCCESS) { 40349dec922SGavin Shan pr_warn("%s: Failure %lld clear %d on PHB#%x-PE#%x\n", 40449dec922SGavin Shan __func__, rc, opt, phb->hose->global_number, pe_no); 40549dec922SGavin Shan return -EIO; 40649dec922SGavin Shan } 40749dec922SGavin Shan 40849dec922SGavin Shan if (!(pe->flags & PNV_IODA_PE_MASTER)) 40949dec922SGavin Shan return 0; 41049dec922SGavin Shan 41149dec922SGavin Shan /* Clear frozen state for slave PEs */ 41249dec922SGavin Shan list_for_each_entry(slave, &pe->slaves, list) { 41349dec922SGavin Shan rc = opal_pci_eeh_freeze_clear(phb->opal_id, 41449dec922SGavin Shan slave->pe_number, 41549dec922SGavin Shan opt); 41649dec922SGavin Shan if (rc != OPAL_SUCCESS) { 41749dec922SGavin Shan pr_warn("%s: Failure %lld clear %d on PHB#%x-PE#%x\n", 41849dec922SGavin Shan __func__, rc, opt, phb->hose->global_number, 41949dec922SGavin Shan slave->pe_number); 42049dec922SGavin Shan return -EIO; 42149dec922SGavin Shan } 42249dec922SGavin Shan } 42349dec922SGavin Shan 42449dec922SGavin Shan return 0; 42549dec922SGavin Shan } 42649dec922SGavin Shan 42749dec922SGavin Shan static int pnv_ioda_get_pe_state(struct pnv_phb *phb, int pe_no) 42849dec922SGavin Shan { 42949dec922SGavin Shan struct pnv_ioda_pe *slave, *pe; 43049dec922SGavin Shan u8 fstate, state; 43149dec922SGavin Shan __be16 pcierr; 43249dec922SGavin Shan s64 rc; 43349dec922SGavin Shan 43449dec922SGavin Shan /* Sanity check on PE number */ 43549dec922SGavin Shan if (pe_no < 0 || pe_no >= phb->ioda.total_pe) 43649dec922SGavin Shan return OPAL_EEH_STOPPED_PERM_UNAVAIL; 43749dec922SGavin Shan 43849dec922SGavin Shan /* 43949dec922SGavin Shan * Fetch the master PE and the PE instance might be 44049dec922SGavin Shan * not initialized yet. 44149dec922SGavin Shan */ 44249dec922SGavin Shan pe = &phb->ioda.pe_array[pe_no]; 44349dec922SGavin Shan if (pe->flags & PNV_IODA_PE_SLAVE) { 44449dec922SGavin Shan pe = pe->master; 44549dec922SGavin Shan WARN_ON(!pe || !(pe->flags & PNV_IODA_PE_MASTER)); 44649dec922SGavin Shan pe_no = pe->pe_number; 44749dec922SGavin Shan } 44849dec922SGavin Shan 44949dec922SGavin Shan /* Check the master PE */ 45049dec922SGavin Shan rc = opal_pci_eeh_freeze_status(phb->opal_id, pe_no, 45149dec922SGavin Shan &state, &pcierr, NULL); 45249dec922SGavin Shan if (rc != OPAL_SUCCESS) { 45349dec922SGavin Shan pr_warn("%s: Failure %lld getting " 45449dec922SGavin Shan "PHB#%x-PE#%x state\n", 45549dec922SGavin Shan __func__, rc, 45649dec922SGavin Shan phb->hose->global_number, pe_no); 45749dec922SGavin Shan return OPAL_EEH_STOPPED_TEMP_UNAVAIL; 45849dec922SGavin Shan } 45949dec922SGavin Shan 46049dec922SGavin Shan /* Check the slave PE */ 46149dec922SGavin Shan if (!(pe->flags & PNV_IODA_PE_MASTER)) 46249dec922SGavin Shan return state; 46349dec922SGavin Shan 46449dec922SGavin Shan list_for_each_entry(slave, &pe->slaves, list) { 46549dec922SGavin Shan rc = opal_pci_eeh_freeze_status(phb->opal_id, 46649dec922SGavin Shan slave->pe_number, 46749dec922SGavin Shan &fstate, 46849dec922SGavin Shan &pcierr, 46949dec922SGavin Shan NULL); 47049dec922SGavin Shan if (rc != OPAL_SUCCESS) { 47149dec922SGavin Shan pr_warn("%s: Failure %lld getting " 47249dec922SGavin Shan "PHB#%x-PE#%x state\n", 47349dec922SGavin Shan __func__, rc, 47449dec922SGavin Shan phb->hose->global_number, slave->pe_number); 47549dec922SGavin Shan return OPAL_EEH_STOPPED_TEMP_UNAVAIL; 47649dec922SGavin Shan } 47749dec922SGavin Shan 47849dec922SGavin Shan /* 47949dec922SGavin Shan * Override the result based on the ascending 48049dec922SGavin Shan * priority. 48149dec922SGavin Shan */ 48249dec922SGavin Shan if (fstate > state) 48349dec922SGavin Shan state = fstate; 48449dec922SGavin Shan } 48549dec922SGavin Shan 48649dec922SGavin Shan return state; 48749dec922SGavin Shan } 48849dec922SGavin Shan 489184cd4a3SBenjamin Herrenschmidt /* Currently those 2 are only used when MSIs are enabled, this will change 490184cd4a3SBenjamin Herrenschmidt * but in the meantime, we need to protect them to avoid warnings 491184cd4a3SBenjamin Herrenschmidt */ 492184cd4a3SBenjamin Herrenschmidt #ifdef CONFIG_PCI_MSI 493cad5cef6SGreg Kroah-Hartman static struct pnv_ioda_pe *pnv_ioda_get_pe(struct pci_dev *dev) 494184cd4a3SBenjamin Herrenschmidt { 495184cd4a3SBenjamin Herrenschmidt struct pci_controller *hose = pci_bus_to_host(dev->bus); 496184cd4a3SBenjamin Herrenschmidt struct pnv_phb *phb = hose->private_data; 497b72c1f65SBenjamin Herrenschmidt struct pci_dn *pdn = pci_get_pdn(dev); 498184cd4a3SBenjamin Herrenschmidt 499184cd4a3SBenjamin Herrenschmidt if (!pdn) 500184cd4a3SBenjamin Herrenschmidt return NULL; 501184cd4a3SBenjamin Herrenschmidt if (pdn->pe_number == IODA_INVALID_PE) 502184cd4a3SBenjamin Herrenschmidt return NULL; 503184cd4a3SBenjamin Herrenschmidt return &phb->ioda.pe_array[pdn->pe_number]; 504184cd4a3SBenjamin Herrenschmidt } 505184cd4a3SBenjamin Herrenschmidt #endif /* CONFIG_PCI_MSI */ 506184cd4a3SBenjamin Herrenschmidt 507cad5cef6SGreg Kroah-Hartman static int pnv_ioda_configure_pe(struct pnv_phb *phb, struct pnv_ioda_pe *pe) 508184cd4a3SBenjamin Herrenschmidt { 509184cd4a3SBenjamin Herrenschmidt struct pci_dev *parent; 510184cd4a3SBenjamin Herrenschmidt uint8_t bcomp, dcomp, fcomp; 511184cd4a3SBenjamin Herrenschmidt long rc, rid_end, rid; 512184cd4a3SBenjamin Herrenschmidt 513184cd4a3SBenjamin Herrenschmidt /* Bus validation ? */ 514184cd4a3SBenjamin Herrenschmidt if (pe->pbus) { 515184cd4a3SBenjamin Herrenschmidt int count; 516184cd4a3SBenjamin Herrenschmidt 517184cd4a3SBenjamin Herrenschmidt dcomp = OPAL_IGNORE_RID_DEVICE_NUMBER; 518184cd4a3SBenjamin Herrenschmidt fcomp = OPAL_IGNORE_RID_FUNCTION_NUMBER; 519184cd4a3SBenjamin Herrenschmidt parent = pe->pbus->self; 520fb446ad0SGavin Shan if (pe->flags & PNV_IODA_PE_BUS_ALL) 521b918c62eSYinghai Lu count = pe->pbus->busn_res.end - pe->pbus->busn_res.start + 1; 522fb446ad0SGavin Shan else 523fb446ad0SGavin Shan count = 1; 524fb446ad0SGavin Shan 525184cd4a3SBenjamin Herrenschmidt switch(count) { 526184cd4a3SBenjamin Herrenschmidt case 1: bcomp = OpalPciBusAll; break; 527184cd4a3SBenjamin Herrenschmidt case 2: bcomp = OpalPciBus7Bits; break; 528184cd4a3SBenjamin Herrenschmidt case 4: bcomp = OpalPciBus6Bits; break; 529184cd4a3SBenjamin Herrenschmidt case 8: bcomp = OpalPciBus5Bits; break; 530184cd4a3SBenjamin Herrenschmidt case 16: bcomp = OpalPciBus4Bits; break; 531184cd4a3SBenjamin Herrenschmidt case 32: bcomp = OpalPciBus3Bits; break; 532184cd4a3SBenjamin Herrenschmidt default: 533184cd4a3SBenjamin Herrenschmidt pr_err("%s: Number of subordinate busses %d" 534184cd4a3SBenjamin Herrenschmidt " unsupported\n", 535184cd4a3SBenjamin Herrenschmidt pci_name(pe->pbus->self), count); 536184cd4a3SBenjamin Herrenschmidt /* Do an exact match only */ 537184cd4a3SBenjamin Herrenschmidt bcomp = OpalPciBusAll; 538184cd4a3SBenjamin Herrenschmidt } 539184cd4a3SBenjamin Herrenschmidt rid_end = pe->rid + (count << 8); 540184cd4a3SBenjamin Herrenschmidt } else { 541184cd4a3SBenjamin Herrenschmidt parent = pe->pdev->bus->self; 542184cd4a3SBenjamin Herrenschmidt bcomp = OpalPciBusAll; 543184cd4a3SBenjamin Herrenschmidt dcomp = OPAL_COMPARE_RID_DEVICE_NUMBER; 544184cd4a3SBenjamin Herrenschmidt fcomp = OPAL_COMPARE_RID_FUNCTION_NUMBER; 545184cd4a3SBenjamin Herrenschmidt rid_end = pe->rid + 1; 546184cd4a3SBenjamin Herrenschmidt } 547184cd4a3SBenjamin Herrenschmidt 548631ad691SGavin Shan /* 549631ad691SGavin Shan * Associate PE in PELT. We need add the PE into the 550631ad691SGavin Shan * corresponding PELT-V as well. Otherwise, the error 551631ad691SGavin Shan * originated from the PE might contribute to other 552631ad691SGavin Shan * PEs. 553631ad691SGavin Shan */ 554184cd4a3SBenjamin Herrenschmidt rc = opal_pci_set_pe(phb->opal_id, pe->pe_number, pe->rid, 555184cd4a3SBenjamin Herrenschmidt bcomp, dcomp, fcomp, OPAL_MAP_PE); 556184cd4a3SBenjamin Herrenschmidt if (rc) { 557184cd4a3SBenjamin Herrenschmidt pe_err(pe, "OPAL error %ld trying to setup PELT table\n", rc); 558184cd4a3SBenjamin Herrenschmidt return -ENXIO; 559184cd4a3SBenjamin Herrenschmidt } 560631ad691SGavin Shan 561631ad691SGavin Shan rc = opal_pci_set_peltv(phb->opal_id, pe->pe_number, 562631ad691SGavin Shan pe->pe_number, OPAL_ADD_PE_TO_DOMAIN); 563631ad691SGavin Shan if (rc) 564631ad691SGavin Shan pe_warn(pe, "OPAL error %d adding self to PELTV\n", rc); 565184cd4a3SBenjamin Herrenschmidt opal_pci_eeh_freeze_clear(phb->opal_id, pe->pe_number, 566184cd4a3SBenjamin Herrenschmidt OPAL_EEH_ACTION_CLEAR_FREEZE_ALL); 567184cd4a3SBenjamin Herrenschmidt 568184cd4a3SBenjamin Herrenschmidt /* Add to all parents PELT-V */ 569184cd4a3SBenjamin Herrenschmidt while (parent) { 570b72c1f65SBenjamin Herrenschmidt struct pci_dn *pdn = pci_get_pdn(parent); 571184cd4a3SBenjamin Herrenschmidt if (pdn && pdn->pe_number != IODA_INVALID_PE) { 572184cd4a3SBenjamin Herrenschmidt rc = opal_pci_set_peltv(phb->opal_id, pdn->pe_number, 573cee72d5bSBenjamin Herrenschmidt pe->pe_number, OPAL_ADD_PE_TO_DOMAIN); 574184cd4a3SBenjamin Herrenschmidt /* XXX What to do in case of error ? */ 575184cd4a3SBenjamin Herrenschmidt } 576184cd4a3SBenjamin Herrenschmidt parent = parent->bus->self; 577184cd4a3SBenjamin Herrenschmidt } 578184cd4a3SBenjamin Herrenschmidt /* Setup reverse map */ 579184cd4a3SBenjamin Herrenschmidt for (rid = pe->rid; rid < rid_end; rid++) 580184cd4a3SBenjamin Herrenschmidt phb->ioda.pe_rmap[rid] = pe->pe_number; 581184cd4a3SBenjamin Herrenschmidt 582184cd4a3SBenjamin Herrenschmidt /* Setup one MVTs on IODA1 */ 583184cd4a3SBenjamin Herrenschmidt if (phb->type == PNV_PHB_IODA1) { 584184cd4a3SBenjamin Herrenschmidt pe->mve_number = pe->pe_number; 585184cd4a3SBenjamin Herrenschmidt rc = opal_pci_set_mve(phb->opal_id, pe->mve_number, 586184cd4a3SBenjamin Herrenschmidt pe->pe_number); 587184cd4a3SBenjamin Herrenschmidt if (rc) { 588184cd4a3SBenjamin Herrenschmidt pe_err(pe, "OPAL error %ld setting up MVE %d\n", 589184cd4a3SBenjamin Herrenschmidt rc, pe->mve_number); 590184cd4a3SBenjamin Herrenschmidt pe->mve_number = -1; 591184cd4a3SBenjamin Herrenschmidt } else { 592184cd4a3SBenjamin Herrenschmidt rc = opal_pci_set_mve_enable(phb->opal_id, 593cee72d5bSBenjamin Herrenschmidt pe->mve_number, OPAL_ENABLE_MVE); 594184cd4a3SBenjamin Herrenschmidt if (rc) { 595184cd4a3SBenjamin Herrenschmidt pe_err(pe, "OPAL error %ld enabling MVE %d\n", 596184cd4a3SBenjamin Herrenschmidt rc, pe->mve_number); 597184cd4a3SBenjamin Herrenschmidt pe->mve_number = -1; 598184cd4a3SBenjamin Herrenschmidt } 599184cd4a3SBenjamin Herrenschmidt } 600184cd4a3SBenjamin Herrenschmidt } else if (phb->type == PNV_PHB_IODA2) 601184cd4a3SBenjamin Herrenschmidt pe->mve_number = 0; 602184cd4a3SBenjamin Herrenschmidt 603184cd4a3SBenjamin Herrenschmidt return 0; 604184cd4a3SBenjamin Herrenschmidt } 605184cd4a3SBenjamin Herrenschmidt 606cad5cef6SGreg Kroah-Hartman static void pnv_ioda_link_pe_by_weight(struct pnv_phb *phb, 607184cd4a3SBenjamin Herrenschmidt struct pnv_ioda_pe *pe) 608184cd4a3SBenjamin Herrenschmidt { 609184cd4a3SBenjamin Herrenschmidt struct pnv_ioda_pe *lpe; 610184cd4a3SBenjamin Herrenschmidt 6117ebdf956SGavin Shan list_for_each_entry(lpe, &phb->ioda.pe_dma_list, dma_link) { 612184cd4a3SBenjamin Herrenschmidt if (lpe->dma_weight < pe->dma_weight) { 6137ebdf956SGavin Shan list_add_tail(&pe->dma_link, &lpe->dma_link); 614184cd4a3SBenjamin Herrenschmidt return; 615184cd4a3SBenjamin Herrenschmidt } 616184cd4a3SBenjamin Herrenschmidt } 6177ebdf956SGavin Shan list_add_tail(&pe->dma_link, &phb->ioda.pe_dma_list); 618184cd4a3SBenjamin Herrenschmidt } 619184cd4a3SBenjamin Herrenschmidt 620184cd4a3SBenjamin Herrenschmidt static unsigned int pnv_ioda_dma_weight(struct pci_dev *dev) 621184cd4a3SBenjamin Herrenschmidt { 622184cd4a3SBenjamin Herrenschmidt /* This is quite simplistic. The "base" weight of a device 623184cd4a3SBenjamin Herrenschmidt * is 10. 0 means no DMA is to be accounted for it. 624184cd4a3SBenjamin Herrenschmidt */ 625184cd4a3SBenjamin Herrenschmidt 626184cd4a3SBenjamin Herrenschmidt /* If it's a bridge, no DMA */ 627184cd4a3SBenjamin Herrenschmidt if (dev->hdr_type != PCI_HEADER_TYPE_NORMAL) 628184cd4a3SBenjamin Herrenschmidt return 0; 629184cd4a3SBenjamin Herrenschmidt 630184cd4a3SBenjamin Herrenschmidt /* Reduce the weight of slow USB controllers */ 631184cd4a3SBenjamin Herrenschmidt if (dev->class == PCI_CLASS_SERIAL_USB_UHCI || 632184cd4a3SBenjamin Herrenschmidt dev->class == PCI_CLASS_SERIAL_USB_OHCI || 633184cd4a3SBenjamin Herrenschmidt dev->class == PCI_CLASS_SERIAL_USB_EHCI) 634184cd4a3SBenjamin Herrenschmidt return 3; 635184cd4a3SBenjamin Herrenschmidt 636184cd4a3SBenjamin Herrenschmidt /* Increase the weight of RAID (includes Obsidian) */ 637184cd4a3SBenjamin Herrenschmidt if ((dev->class >> 8) == PCI_CLASS_STORAGE_RAID) 638184cd4a3SBenjamin Herrenschmidt return 15; 639184cd4a3SBenjamin Herrenschmidt 640184cd4a3SBenjamin Herrenschmidt /* Default */ 641184cd4a3SBenjamin Herrenschmidt return 10; 642184cd4a3SBenjamin Herrenschmidt } 643184cd4a3SBenjamin Herrenschmidt 644fb446ad0SGavin Shan #if 0 645cad5cef6SGreg Kroah-Hartman static struct pnv_ioda_pe *pnv_ioda_setup_dev_PE(struct pci_dev *dev) 646184cd4a3SBenjamin Herrenschmidt { 647184cd4a3SBenjamin Herrenschmidt struct pci_controller *hose = pci_bus_to_host(dev->bus); 648184cd4a3SBenjamin Herrenschmidt struct pnv_phb *phb = hose->private_data; 649b72c1f65SBenjamin Herrenschmidt struct pci_dn *pdn = pci_get_pdn(dev); 650184cd4a3SBenjamin Herrenschmidt struct pnv_ioda_pe *pe; 651184cd4a3SBenjamin Herrenschmidt int pe_num; 652184cd4a3SBenjamin Herrenschmidt 653184cd4a3SBenjamin Herrenschmidt if (!pdn) { 654184cd4a3SBenjamin Herrenschmidt pr_err("%s: Device tree node not associated properly\n", 655184cd4a3SBenjamin Herrenschmidt pci_name(dev)); 656184cd4a3SBenjamin Herrenschmidt return NULL; 657184cd4a3SBenjamin Herrenschmidt } 658184cd4a3SBenjamin Herrenschmidt if (pdn->pe_number != IODA_INVALID_PE) 659184cd4a3SBenjamin Herrenschmidt return NULL; 660184cd4a3SBenjamin Herrenschmidt 661184cd4a3SBenjamin Herrenschmidt /* PE#0 has been pre-set */ 662184cd4a3SBenjamin Herrenschmidt if (dev->bus->number == 0) 663184cd4a3SBenjamin Herrenschmidt pe_num = 0; 664184cd4a3SBenjamin Herrenschmidt else 665184cd4a3SBenjamin Herrenschmidt pe_num = pnv_ioda_alloc_pe(phb); 666184cd4a3SBenjamin Herrenschmidt if (pe_num == IODA_INVALID_PE) { 667184cd4a3SBenjamin Herrenschmidt pr_warning("%s: Not enough PE# available, disabling device\n", 668184cd4a3SBenjamin Herrenschmidt pci_name(dev)); 669184cd4a3SBenjamin Herrenschmidt return NULL; 670184cd4a3SBenjamin Herrenschmidt } 671184cd4a3SBenjamin Herrenschmidt 672184cd4a3SBenjamin Herrenschmidt /* NOTE: We get only one ref to the pci_dev for the pdn, not for the 673184cd4a3SBenjamin Herrenschmidt * pointer in the PE data structure, both should be destroyed at the 674184cd4a3SBenjamin Herrenschmidt * same time. However, this needs to be looked at more closely again 675184cd4a3SBenjamin Herrenschmidt * once we actually start removing things (Hotplug, SR-IOV, ...) 676184cd4a3SBenjamin Herrenschmidt * 677184cd4a3SBenjamin Herrenschmidt * At some point we want to remove the PDN completely anyways 678184cd4a3SBenjamin Herrenschmidt */ 679184cd4a3SBenjamin Herrenschmidt pe = &phb->ioda.pe_array[pe_num]; 680184cd4a3SBenjamin Herrenschmidt pci_dev_get(dev); 681184cd4a3SBenjamin Herrenschmidt pdn->pcidev = dev; 682184cd4a3SBenjamin Herrenschmidt pdn->pe_number = pe_num; 683184cd4a3SBenjamin Herrenschmidt pe->pdev = dev; 684184cd4a3SBenjamin Herrenschmidt pe->pbus = NULL; 685184cd4a3SBenjamin Herrenschmidt pe->tce32_seg = -1; 686184cd4a3SBenjamin Herrenschmidt pe->mve_number = -1; 687184cd4a3SBenjamin Herrenschmidt pe->rid = dev->bus->number << 8 | pdn->devfn; 688184cd4a3SBenjamin Herrenschmidt 689184cd4a3SBenjamin Herrenschmidt pe_info(pe, "Associated device to PE\n"); 690184cd4a3SBenjamin Herrenschmidt 691184cd4a3SBenjamin Herrenschmidt if (pnv_ioda_configure_pe(phb, pe)) { 692184cd4a3SBenjamin Herrenschmidt /* XXX What do we do here ? */ 693184cd4a3SBenjamin Herrenschmidt if (pe_num) 694184cd4a3SBenjamin Herrenschmidt pnv_ioda_free_pe(phb, pe_num); 695184cd4a3SBenjamin Herrenschmidt pdn->pe_number = IODA_INVALID_PE; 696184cd4a3SBenjamin Herrenschmidt pe->pdev = NULL; 697184cd4a3SBenjamin Herrenschmidt pci_dev_put(dev); 698184cd4a3SBenjamin Herrenschmidt return NULL; 699184cd4a3SBenjamin Herrenschmidt } 700184cd4a3SBenjamin Herrenschmidt 701184cd4a3SBenjamin Herrenschmidt /* Assign a DMA weight to the device */ 702184cd4a3SBenjamin Herrenschmidt pe->dma_weight = pnv_ioda_dma_weight(dev); 703184cd4a3SBenjamin Herrenschmidt if (pe->dma_weight != 0) { 704184cd4a3SBenjamin Herrenschmidt phb->ioda.dma_weight += pe->dma_weight; 705184cd4a3SBenjamin Herrenschmidt phb->ioda.dma_pe_count++; 706184cd4a3SBenjamin Herrenschmidt } 707184cd4a3SBenjamin Herrenschmidt 708184cd4a3SBenjamin Herrenschmidt /* Link the PE */ 709184cd4a3SBenjamin Herrenschmidt pnv_ioda_link_pe_by_weight(phb, pe); 710184cd4a3SBenjamin Herrenschmidt 711184cd4a3SBenjamin Herrenschmidt return pe; 712184cd4a3SBenjamin Herrenschmidt } 713fb446ad0SGavin Shan #endif /* Useful for SRIOV case */ 714184cd4a3SBenjamin Herrenschmidt 715184cd4a3SBenjamin Herrenschmidt static void pnv_ioda_setup_same_PE(struct pci_bus *bus, struct pnv_ioda_pe *pe) 716184cd4a3SBenjamin Herrenschmidt { 717184cd4a3SBenjamin Herrenschmidt struct pci_dev *dev; 718184cd4a3SBenjamin Herrenschmidt 719184cd4a3SBenjamin Herrenschmidt list_for_each_entry(dev, &bus->devices, bus_list) { 720b72c1f65SBenjamin Herrenschmidt struct pci_dn *pdn = pci_get_pdn(dev); 721184cd4a3SBenjamin Herrenschmidt 722184cd4a3SBenjamin Herrenschmidt if (pdn == NULL) { 723184cd4a3SBenjamin Herrenschmidt pr_warn("%s: No device node associated with device !\n", 724184cd4a3SBenjamin Herrenschmidt pci_name(dev)); 725184cd4a3SBenjamin Herrenschmidt continue; 726184cd4a3SBenjamin Herrenschmidt } 727184cd4a3SBenjamin Herrenschmidt pdn->pcidev = dev; 728184cd4a3SBenjamin Herrenschmidt pdn->pe_number = pe->pe_number; 729184cd4a3SBenjamin Herrenschmidt pe->dma_weight += pnv_ioda_dma_weight(dev); 730fb446ad0SGavin Shan if ((pe->flags & PNV_IODA_PE_BUS_ALL) && dev->subordinate) 731184cd4a3SBenjamin Herrenschmidt pnv_ioda_setup_same_PE(dev->subordinate, pe); 732184cd4a3SBenjamin Herrenschmidt } 733184cd4a3SBenjamin Herrenschmidt } 734184cd4a3SBenjamin Herrenschmidt 735fb446ad0SGavin Shan /* 736fb446ad0SGavin Shan * There're 2 types of PCI bus sensitive PEs: One that is compromised of 737fb446ad0SGavin Shan * single PCI bus. Another one that contains the primary PCI bus and its 738fb446ad0SGavin Shan * subordinate PCI devices and buses. The second type of PE is normally 739fb446ad0SGavin Shan * orgiriated by PCIe-to-PCI bridge or PLX switch downstream ports. 740fb446ad0SGavin Shan */ 741cad5cef6SGreg Kroah-Hartman static void pnv_ioda_setup_bus_PE(struct pci_bus *bus, int all) 742184cd4a3SBenjamin Herrenschmidt { 743fb446ad0SGavin Shan struct pci_controller *hose = pci_bus_to_host(bus); 744184cd4a3SBenjamin Herrenschmidt struct pnv_phb *phb = hose->private_data; 745184cd4a3SBenjamin Herrenschmidt struct pnv_ioda_pe *pe; 746262af557SGuo Chao int pe_num = IODA_INVALID_PE; 747184cd4a3SBenjamin Herrenschmidt 748262af557SGuo Chao /* Check if PE is determined by M64 */ 749262af557SGuo Chao if (phb->pick_m64_pe) 750262af557SGuo Chao pe_num = phb->pick_m64_pe(phb, bus, all); 751262af557SGuo Chao 752262af557SGuo Chao /* The PE number isn't pinned by M64 */ 753262af557SGuo Chao if (pe_num == IODA_INVALID_PE) 754184cd4a3SBenjamin Herrenschmidt pe_num = pnv_ioda_alloc_pe(phb); 755262af557SGuo Chao 756184cd4a3SBenjamin Herrenschmidt if (pe_num == IODA_INVALID_PE) { 757fb446ad0SGavin Shan pr_warning("%s: Not enough PE# available for PCI bus %04x:%02x\n", 758fb446ad0SGavin Shan __func__, pci_domain_nr(bus), bus->number); 759184cd4a3SBenjamin Herrenschmidt return; 760184cd4a3SBenjamin Herrenschmidt } 761184cd4a3SBenjamin Herrenschmidt 762184cd4a3SBenjamin Herrenschmidt pe = &phb->ioda.pe_array[pe_num]; 763262af557SGuo Chao pe->flags |= (all ? PNV_IODA_PE_BUS_ALL : PNV_IODA_PE_BUS); 764184cd4a3SBenjamin Herrenschmidt pe->pbus = bus; 765184cd4a3SBenjamin Herrenschmidt pe->pdev = NULL; 766184cd4a3SBenjamin Herrenschmidt pe->tce32_seg = -1; 767184cd4a3SBenjamin Herrenschmidt pe->mve_number = -1; 768b918c62eSYinghai Lu pe->rid = bus->busn_res.start << 8; 769184cd4a3SBenjamin Herrenschmidt pe->dma_weight = 0; 770184cd4a3SBenjamin Herrenschmidt 771fb446ad0SGavin Shan if (all) 772fb446ad0SGavin Shan pe_info(pe, "Secondary bus %d..%d associated with PE#%d\n", 773fb446ad0SGavin Shan bus->busn_res.start, bus->busn_res.end, pe_num); 774fb446ad0SGavin Shan else 775fb446ad0SGavin Shan pe_info(pe, "Secondary bus %d associated with PE#%d\n", 776fb446ad0SGavin Shan bus->busn_res.start, pe_num); 777184cd4a3SBenjamin Herrenschmidt 778184cd4a3SBenjamin Herrenschmidt if (pnv_ioda_configure_pe(phb, pe)) { 779184cd4a3SBenjamin Herrenschmidt /* XXX What do we do here ? */ 780184cd4a3SBenjamin Herrenschmidt if (pe_num) 781184cd4a3SBenjamin Herrenschmidt pnv_ioda_free_pe(phb, pe_num); 782184cd4a3SBenjamin Herrenschmidt pe->pbus = NULL; 783184cd4a3SBenjamin Herrenschmidt return; 784184cd4a3SBenjamin Herrenschmidt } 785184cd4a3SBenjamin Herrenschmidt 786184cd4a3SBenjamin Herrenschmidt /* Associate it with all child devices */ 787184cd4a3SBenjamin Herrenschmidt pnv_ioda_setup_same_PE(bus, pe); 788184cd4a3SBenjamin Herrenschmidt 7897ebdf956SGavin Shan /* Put PE to the list */ 7907ebdf956SGavin Shan list_add_tail(&pe->list, &phb->ioda.pe_list); 7917ebdf956SGavin Shan 792184cd4a3SBenjamin Herrenschmidt /* Account for one DMA PE if at least one DMA capable device exist 793184cd4a3SBenjamin Herrenschmidt * below the bridge 794184cd4a3SBenjamin Herrenschmidt */ 795184cd4a3SBenjamin Herrenschmidt if (pe->dma_weight != 0) { 796184cd4a3SBenjamin Herrenschmidt phb->ioda.dma_weight += pe->dma_weight; 797184cd4a3SBenjamin Herrenschmidt phb->ioda.dma_pe_count++; 798184cd4a3SBenjamin Herrenschmidt } 799184cd4a3SBenjamin Herrenschmidt 800184cd4a3SBenjamin Herrenschmidt /* Link the PE */ 801184cd4a3SBenjamin Herrenschmidt pnv_ioda_link_pe_by_weight(phb, pe); 802184cd4a3SBenjamin Herrenschmidt } 803184cd4a3SBenjamin Herrenschmidt 804cad5cef6SGreg Kroah-Hartman static void pnv_ioda_setup_PEs(struct pci_bus *bus) 805184cd4a3SBenjamin Herrenschmidt { 806184cd4a3SBenjamin Herrenschmidt struct pci_dev *dev; 807fb446ad0SGavin Shan 808fb446ad0SGavin Shan pnv_ioda_setup_bus_PE(bus, 0); 809184cd4a3SBenjamin Herrenschmidt 810184cd4a3SBenjamin Herrenschmidt list_for_each_entry(dev, &bus->devices, bus_list) { 811fb446ad0SGavin Shan if (dev->subordinate) { 81262f87c0eSYijing Wang if (pci_pcie_type(dev) == PCI_EXP_TYPE_PCI_BRIDGE) 813fb446ad0SGavin Shan pnv_ioda_setup_bus_PE(dev->subordinate, 1); 814fb446ad0SGavin Shan else 815184cd4a3SBenjamin Herrenschmidt pnv_ioda_setup_PEs(dev->subordinate); 816184cd4a3SBenjamin Herrenschmidt } 817184cd4a3SBenjamin Herrenschmidt } 818fb446ad0SGavin Shan } 819fb446ad0SGavin Shan 820fb446ad0SGavin Shan /* 821fb446ad0SGavin Shan * Configure PEs so that the downstream PCI buses and devices 822fb446ad0SGavin Shan * could have their associated PE#. Unfortunately, we didn't 823fb446ad0SGavin Shan * figure out the way to identify the PLX bridge yet. So we 824fb446ad0SGavin Shan * simply put the PCI bus and the subordinate behind the root 825fb446ad0SGavin Shan * port to PE# here. The game rule here is expected to be changed 826fb446ad0SGavin Shan * as soon as we can detected PLX bridge correctly. 827fb446ad0SGavin Shan */ 828cad5cef6SGreg Kroah-Hartman static void pnv_pci_ioda_setup_PEs(void) 829fb446ad0SGavin Shan { 830fb446ad0SGavin Shan struct pci_controller *hose, *tmp; 831262af557SGuo Chao struct pnv_phb *phb; 832fb446ad0SGavin Shan 833fb446ad0SGavin Shan list_for_each_entry_safe(hose, tmp, &hose_list, list_node) { 834262af557SGuo Chao phb = hose->private_data; 835262af557SGuo Chao 836262af557SGuo Chao /* M64 layout might affect PE allocation */ 837262af557SGuo Chao if (phb->alloc_m64_pe) 838262af557SGuo Chao phb->alloc_m64_pe(phb); 839262af557SGuo Chao 840fb446ad0SGavin Shan pnv_ioda_setup_PEs(hose->bus); 841fb446ad0SGavin Shan } 842fb446ad0SGavin Shan } 843184cd4a3SBenjamin Herrenschmidt 844959c9bddSGavin Shan static void pnv_pci_ioda_dma_dev_setup(struct pnv_phb *phb, struct pci_dev *pdev) 845184cd4a3SBenjamin Herrenschmidt { 846b72c1f65SBenjamin Herrenschmidt struct pci_dn *pdn = pci_get_pdn(pdev); 847959c9bddSGavin Shan struct pnv_ioda_pe *pe; 848184cd4a3SBenjamin Herrenschmidt 849959c9bddSGavin Shan /* 850959c9bddSGavin Shan * The function can be called while the PE# 851959c9bddSGavin Shan * hasn't been assigned. Do nothing for the 852959c9bddSGavin Shan * case. 853959c9bddSGavin Shan */ 854959c9bddSGavin Shan if (!pdn || pdn->pe_number == IODA_INVALID_PE) 855959c9bddSGavin Shan return; 856184cd4a3SBenjamin Herrenschmidt 857959c9bddSGavin Shan pe = &phb->ioda.pe_array[pdn->pe_number]; 858cd15b048SBenjamin Herrenschmidt WARN_ON(get_dma_ops(&pdev->dev) != &dma_iommu_ops); 859763fe0adSGavin Shan set_iommu_table_base_and_group(&pdev->dev, &pe->tce32_table); 860184cd4a3SBenjamin Herrenschmidt } 861184cd4a3SBenjamin Herrenschmidt 862cd15b048SBenjamin Herrenschmidt static int pnv_pci_ioda_dma_set_mask(struct pnv_phb *phb, 863cd15b048SBenjamin Herrenschmidt struct pci_dev *pdev, u64 dma_mask) 864cd15b048SBenjamin Herrenschmidt { 865cd15b048SBenjamin Herrenschmidt struct pci_dn *pdn = pci_get_pdn(pdev); 866cd15b048SBenjamin Herrenschmidt struct pnv_ioda_pe *pe; 867cd15b048SBenjamin Herrenschmidt uint64_t top; 868cd15b048SBenjamin Herrenschmidt bool bypass = false; 869cd15b048SBenjamin Herrenschmidt 870cd15b048SBenjamin Herrenschmidt if (WARN_ON(!pdn || pdn->pe_number == IODA_INVALID_PE)) 871cd15b048SBenjamin Herrenschmidt return -ENODEV;; 872cd15b048SBenjamin Herrenschmidt 873cd15b048SBenjamin Herrenschmidt pe = &phb->ioda.pe_array[pdn->pe_number]; 874cd15b048SBenjamin Herrenschmidt if (pe->tce_bypass_enabled) { 875cd15b048SBenjamin Herrenschmidt top = pe->tce_bypass_base + memblock_end_of_DRAM() - 1; 876cd15b048SBenjamin Herrenschmidt bypass = (dma_mask >= top); 877cd15b048SBenjamin Herrenschmidt } 878cd15b048SBenjamin Herrenschmidt 879cd15b048SBenjamin Herrenschmidt if (bypass) { 880cd15b048SBenjamin Herrenschmidt dev_info(&pdev->dev, "Using 64-bit DMA iommu bypass\n"); 881cd15b048SBenjamin Herrenschmidt set_dma_ops(&pdev->dev, &dma_direct_ops); 882cd15b048SBenjamin Herrenschmidt set_dma_offset(&pdev->dev, pe->tce_bypass_base); 883cd15b048SBenjamin Herrenschmidt } else { 884cd15b048SBenjamin Herrenschmidt dev_info(&pdev->dev, "Using 32-bit DMA via iommu\n"); 885cd15b048SBenjamin Herrenschmidt set_dma_ops(&pdev->dev, &dma_iommu_ops); 886cd15b048SBenjamin Herrenschmidt set_iommu_table_base(&pdev->dev, &pe->tce32_table); 887cd15b048SBenjamin Herrenschmidt } 888a32305bfSBrian W Hart *pdev->dev.dma_mask = dma_mask; 889cd15b048SBenjamin Herrenschmidt return 0; 890cd15b048SBenjamin Herrenschmidt } 891cd15b048SBenjamin Herrenschmidt 892dff4a39eSGavin Shan static void pnv_ioda_setup_bus_dma(struct pnv_ioda_pe *pe, 893dff4a39eSGavin Shan struct pci_bus *bus, 894dff4a39eSGavin Shan bool add_to_iommu_group) 89574251fe2SBenjamin Herrenschmidt { 89674251fe2SBenjamin Herrenschmidt struct pci_dev *dev; 89774251fe2SBenjamin Herrenschmidt 89874251fe2SBenjamin Herrenschmidt list_for_each_entry(dev, &bus->devices, bus_list) { 899dff4a39eSGavin Shan if (add_to_iommu_group) 900dff4a39eSGavin Shan set_iommu_table_base_and_group(&dev->dev, 901dff4a39eSGavin Shan &pe->tce32_table); 902dff4a39eSGavin Shan else 903dff4a39eSGavin Shan set_iommu_table_base(&dev->dev, &pe->tce32_table); 904dff4a39eSGavin Shan 90574251fe2SBenjamin Herrenschmidt if (dev->subordinate) 906dff4a39eSGavin Shan pnv_ioda_setup_bus_dma(pe, dev->subordinate, 907dff4a39eSGavin Shan add_to_iommu_group); 90874251fe2SBenjamin Herrenschmidt } 90974251fe2SBenjamin Herrenschmidt } 91074251fe2SBenjamin Herrenschmidt 9118e0a1611SAlexey Kardashevskiy static void pnv_pci_ioda1_tce_invalidate(struct pnv_ioda_pe *pe, 9128e0a1611SAlexey Kardashevskiy struct iommu_table *tbl, 9133ad26e5cSBenjamin Herrenschmidt __be64 *startp, __be64 *endp, bool rm) 9144cce9550SGavin Shan { 9153ad26e5cSBenjamin Herrenschmidt __be64 __iomem *invalidate = rm ? 9163ad26e5cSBenjamin Herrenschmidt (__be64 __iomem *)pe->tce_inval_reg_phys : 9173ad26e5cSBenjamin Herrenschmidt (__be64 __iomem *)tbl->it_index; 9184cce9550SGavin Shan unsigned long start, end, inc; 919b0376c9bSAlexey Kardashevskiy const unsigned shift = tbl->it_page_shift; 9204cce9550SGavin Shan 9214cce9550SGavin Shan start = __pa(startp); 9224cce9550SGavin Shan end = __pa(endp); 9234cce9550SGavin Shan 9244cce9550SGavin Shan /* BML uses this case for p6/p7/galaxy2: Shift addr and put in node */ 9254cce9550SGavin Shan if (tbl->it_busno) { 926b0376c9bSAlexey Kardashevskiy start <<= shift; 927b0376c9bSAlexey Kardashevskiy end <<= shift; 928b0376c9bSAlexey Kardashevskiy inc = 128ull << shift; 9294cce9550SGavin Shan start |= tbl->it_busno; 9304cce9550SGavin Shan end |= tbl->it_busno; 9314cce9550SGavin Shan } else if (tbl->it_type & TCE_PCI_SWINV_PAIR) { 9324cce9550SGavin Shan /* p7ioc-style invalidation, 2 TCEs per write */ 9334cce9550SGavin Shan start |= (1ull << 63); 9344cce9550SGavin Shan end |= (1ull << 63); 9354cce9550SGavin Shan inc = 16; 9364cce9550SGavin Shan } else { 9374cce9550SGavin Shan /* Default (older HW) */ 9384cce9550SGavin Shan inc = 128; 9394cce9550SGavin Shan } 9404cce9550SGavin Shan 9414cce9550SGavin Shan end |= inc - 1; /* round up end to be different than start */ 9424cce9550SGavin Shan 9434cce9550SGavin Shan mb(); /* Ensure above stores are visible */ 9444cce9550SGavin Shan while (start <= end) { 9458e0a1611SAlexey Kardashevskiy if (rm) 9463ad26e5cSBenjamin Herrenschmidt __raw_rm_writeq(cpu_to_be64(start), invalidate); 9478e0a1611SAlexey Kardashevskiy else 9483a1a4661SBenjamin Herrenschmidt __raw_writeq(cpu_to_be64(start), invalidate); 9494cce9550SGavin Shan start += inc; 9504cce9550SGavin Shan } 9514cce9550SGavin Shan 9524cce9550SGavin Shan /* 9534cce9550SGavin Shan * The iommu layer will do another mb() for us on build() 9544cce9550SGavin Shan * and we don't care on free() 9554cce9550SGavin Shan */ 9564cce9550SGavin Shan } 9574cce9550SGavin Shan 9584cce9550SGavin Shan static void pnv_pci_ioda2_tce_invalidate(struct pnv_ioda_pe *pe, 9594cce9550SGavin Shan struct iommu_table *tbl, 9603ad26e5cSBenjamin Herrenschmidt __be64 *startp, __be64 *endp, bool rm) 9614cce9550SGavin Shan { 9624cce9550SGavin Shan unsigned long start, end, inc; 9633ad26e5cSBenjamin Herrenschmidt __be64 __iomem *invalidate = rm ? 9643ad26e5cSBenjamin Herrenschmidt (__be64 __iomem *)pe->tce_inval_reg_phys : 9653ad26e5cSBenjamin Herrenschmidt (__be64 __iomem *)tbl->it_index; 966b0376c9bSAlexey Kardashevskiy const unsigned shift = tbl->it_page_shift; 9674cce9550SGavin Shan 9684cce9550SGavin Shan /* We'll invalidate DMA address in PE scope */ 969b0376c9bSAlexey Kardashevskiy start = 0x2ull << 60; 9704cce9550SGavin Shan start |= (pe->pe_number & 0xFF); 9714cce9550SGavin Shan end = start; 9724cce9550SGavin Shan 9734cce9550SGavin Shan /* Figure out the start, end and step */ 9744cce9550SGavin Shan inc = tbl->it_offset + (((u64)startp - tbl->it_base) / sizeof(u64)); 975b0376c9bSAlexey Kardashevskiy start |= (inc << shift); 9764cce9550SGavin Shan inc = tbl->it_offset + (((u64)endp - tbl->it_base) / sizeof(u64)); 977b0376c9bSAlexey Kardashevskiy end |= (inc << shift); 978b0376c9bSAlexey Kardashevskiy inc = (0x1ull << shift); 9794cce9550SGavin Shan mb(); 9804cce9550SGavin Shan 9814cce9550SGavin Shan while (start <= end) { 9828e0a1611SAlexey Kardashevskiy if (rm) 9833ad26e5cSBenjamin Herrenschmidt __raw_rm_writeq(cpu_to_be64(start), invalidate); 9848e0a1611SAlexey Kardashevskiy else 9853a1a4661SBenjamin Herrenschmidt __raw_writeq(cpu_to_be64(start), invalidate); 9864cce9550SGavin Shan start += inc; 9874cce9550SGavin Shan } 9884cce9550SGavin Shan } 9894cce9550SGavin Shan 9904cce9550SGavin Shan void pnv_pci_ioda_tce_invalidate(struct iommu_table *tbl, 9913ad26e5cSBenjamin Herrenschmidt __be64 *startp, __be64 *endp, bool rm) 9924cce9550SGavin Shan { 9934cce9550SGavin Shan struct pnv_ioda_pe *pe = container_of(tbl, struct pnv_ioda_pe, 9944cce9550SGavin Shan tce32_table); 9954cce9550SGavin Shan struct pnv_phb *phb = pe->phb; 9964cce9550SGavin Shan 9974cce9550SGavin Shan if (phb->type == PNV_PHB_IODA1) 9988e0a1611SAlexey Kardashevskiy pnv_pci_ioda1_tce_invalidate(pe, tbl, startp, endp, rm); 9994cce9550SGavin Shan else 10008e0a1611SAlexey Kardashevskiy pnv_pci_ioda2_tce_invalidate(pe, tbl, startp, endp, rm); 10014cce9550SGavin Shan } 10024cce9550SGavin Shan 1003cad5cef6SGreg Kroah-Hartman static void pnv_pci_ioda_setup_dma_pe(struct pnv_phb *phb, 1004cad5cef6SGreg Kroah-Hartman struct pnv_ioda_pe *pe, unsigned int base, 1005184cd4a3SBenjamin Herrenschmidt unsigned int segs) 1006184cd4a3SBenjamin Herrenschmidt { 1007184cd4a3SBenjamin Herrenschmidt 1008184cd4a3SBenjamin Herrenschmidt struct page *tce_mem = NULL; 1009184cd4a3SBenjamin Herrenschmidt const __be64 *swinvp; 1010184cd4a3SBenjamin Herrenschmidt struct iommu_table *tbl; 1011184cd4a3SBenjamin Herrenschmidt unsigned int i; 1012184cd4a3SBenjamin Herrenschmidt int64_t rc; 1013184cd4a3SBenjamin Herrenschmidt void *addr; 1014184cd4a3SBenjamin Herrenschmidt 1015184cd4a3SBenjamin Herrenschmidt /* 256M DMA window, 4K TCE pages, 8 bytes TCE */ 1016184cd4a3SBenjamin Herrenschmidt #define TCE32_TABLE_SIZE ((0x10000000 / 0x1000) * 8) 1017184cd4a3SBenjamin Herrenschmidt 1018184cd4a3SBenjamin Herrenschmidt /* XXX FIXME: Handle 64-bit only DMA devices */ 1019184cd4a3SBenjamin Herrenschmidt /* XXX FIXME: Provide 64-bit DMA facilities & non-4K TCE tables etc.. */ 1020184cd4a3SBenjamin Herrenschmidt /* XXX FIXME: Allocate multi-level tables on PHB3 */ 1021184cd4a3SBenjamin Herrenschmidt 1022184cd4a3SBenjamin Herrenschmidt /* We shouldn't already have a 32-bit DMA associated */ 1023184cd4a3SBenjamin Herrenschmidt if (WARN_ON(pe->tce32_seg >= 0)) 1024184cd4a3SBenjamin Herrenschmidt return; 1025184cd4a3SBenjamin Herrenschmidt 1026184cd4a3SBenjamin Herrenschmidt /* Grab a 32-bit TCE table */ 1027184cd4a3SBenjamin Herrenschmidt pe->tce32_seg = base; 1028184cd4a3SBenjamin Herrenschmidt pe_info(pe, " Setting up 32-bit TCE table at %08x..%08x\n", 1029184cd4a3SBenjamin Herrenschmidt (base << 28), ((base + segs) << 28) - 1); 1030184cd4a3SBenjamin Herrenschmidt 1031184cd4a3SBenjamin Herrenschmidt /* XXX Currently, we allocate one big contiguous table for the 1032184cd4a3SBenjamin Herrenschmidt * TCEs. We only really need one chunk per 256M of TCE space 1033184cd4a3SBenjamin Herrenschmidt * (ie per segment) but that's an optimization for later, it 1034184cd4a3SBenjamin Herrenschmidt * requires some added smarts with our get/put_tce implementation 1035184cd4a3SBenjamin Herrenschmidt */ 1036184cd4a3SBenjamin Herrenschmidt tce_mem = alloc_pages_node(phb->hose->node, GFP_KERNEL, 1037184cd4a3SBenjamin Herrenschmidt get_order(TCE32_TABLE_SIZE * segs)); 1038184cd4a3SBenjamin Herrenschmidt if (!tce_mem) { 1039184cd4a3SBenjamin Herrenschmidt pe_err(pe, " Failed to allocate a 32-bit TCE memory\n"); 1040184cd4a3SBenjamin Herrenschmidt goto fail; 1041184cd4a3SBenjamin Herrenschmidt } 1042184cd4a3SBenjamin Herrenschmidt addr = page_address(tce_mem); 1043184cd4a3SBenjamin Herrenschmidt memset(addr, 0, TCE32_TABLE_SIZE * segs); 1044184cd4a3SBenjamin Herrenschmidt 1045184cd4a3SBenjamin Herrenschmidt /* Configure HW */ 1046184cd4a3SBenjamin Herrenschmidt for (i = 0; i < segs; i++) { 1047184cd4a3SBenjamin Herrenschmidt rc = opal_pci_map_pe_dma_window(phb->opal_id, 1048184cd4a3SBenjamin Herrenschmidt pe->pe_number, 1049184cd4a3SBenjamin Herrenschmidt base + i, 1, 1050184cd4a3SBenjamin Herrenschmidt __pa(addr) + TCE32_TABLE_SIZE * i, 1051184cd4a3SBenjamin Herrenschmidt TCE32_TABLE_SIZE, 0x1000); 1052184cd4a3SBenjamin Herrenschmidt if (rc) { 1053184cd4a3SBenjamin Herrenschmidt pe_err(pe, " Failed to configure 32-bit TCE table," 1054184cd4a3SBenjamin Herrenschmidt " err %ld\n", rc); 1055184cd4a3SBenjamin Herrenschmidt goto fail; 1056184cd4a3SBenjamin Herrenschmidt } 1057184cd4a3SBenjamin Herrenschmidt } 1058184cd4a3SBenjamin Herrenschmidt 1059184cd4a3SBenjamin Herrenschmidt /* Setup linux iommu table */ 1060184cd4a3SBenjamin Herrenschmidt tbl = &pe->tce32_table; 1061184cd4a3SBenjamin Herrenschmidt pnv_pci_setup_iommu_table(tbl, addr, TCE32_TABLE_SIZE * segs, 10628fa5d454SAlexey Kardashevskiy base << 28, IOMMU_PAGE_SHIFT_4K); 1063184cd4a3SBenjamin Herrenschmidt 1064184cd4a3SBenjamin Herrenschmidt /* OPAL variant of P7IOC SW invalidated TCEs */ 1065184cd4a3SBenjamin Herrenschmidt swinvp = of_get_property(phb->hose->dn, "ibm,opal-tce-kill", NULL); 1066184cd4a3SBenjamin Herrenschmidt if (swinvp) { 1067184cd4a3SBenjamin Herrenschmidt /* We need a couple more fields -- an address and a data 1068184cd4a3SBenjamin Herrenschmidt * to or. Since the bus is only printed out on table free 1069184cd4a3SBenjamin Herrenschmidt * errors, and on the first pass the data will be a relative 1070184cd4a3SBenjamin Herrenschmidt * bus number, print that out instead. 1071184cd4a3SBenjamin Herrenschmidt */ 10728e0a1611SAlexey Kardashevskiy pe->tce_inval_reg_phys = be64_to_cpup(swinvp); 10738e0a1611SAlexey Kardashevskiy tbl->it_index = (unsigned long)ioremap(pe->tce_inval_reg_phys, 10748e0a1611SAlexey Kardashevskiy 8); 107565fd766bSGavin Shan tbl->it_type |= (TCE_PCI_SWINV_CREATE | 107665fd766bSGavin Shan TCE_PCI_SWINV_FREE | 107765fd766bSGavin Shan TCE_PCI_SWINV_PAIR); 1078184cd4a3SBenjamin Herrenschmidt } 1079184cd4a3SBenjamin Herrenschmidt iommu_init_table(tbl, phb->hose->node); 1080e9bc03feSGavin Shan iommu_register_group(tbl, phb->hose->global_number, pe->pe_number); 1081184cd4a3SBenjamin Herrenschmidt 108274251fe2SBenjamin Herrenschmidt if (pe->pdev) 1083d905c5dfSAlexey Kardashevskiy set_iommu_table_base_and_group(&pe->pdev->dev, tbl); 108474251fe2SBenjamin Herrenschmidt else 1085dff4a39eSGavin Shan pnv_ioda_setup_bus_dma(pe, pe->pbus, true); 108674251fe2SBenjamin Herrenschmidt 1087184cd4a3SBenjamin Herrenschmidt return; 1088184cd4a3SBenjamin Herrenschmidt fail: 1089184cd4a3SBenjamin Herrenschmidt /* XXX Failure: Try to fallback to 64-bit only ? */ 1090184cd4a3SBenjamin Herrenschmidt if (pe->tce32_seg >= 0) 1091184cd4a3SBenjamin Herrenschmidt pe->tce32_seg = -1; 1092184cd4a3SBenjamin Herrenschmidt if (tce_mem) 1093184cd4a3SBenjamin Herrenschmidt __free_pages(tce_mem, get_order(TCE32_TABLE_SIZE * segs)); 1094184cd4a3SBenjamin Herrenschmidt } 1095184cd4a3SBenjamin Herrenschmidt 1096cd15b048SBenjamin Herrenschmidt static void pnv_pci_ioda2_set_bypass(struct iommu_table *tbl, bool enable) 1097cd15b048SBenjamin Herrenschmidt { 1098cd15b048SBenjamin Herrenschmidt struct pnv_ioda_pe *pe = container_of(tbl, struct pnv_ioda_pe, 1099cd15b048SBenjamin Herrenschmidt tce32_table); 1100cd15b048SBenjamin Herrenschmidt uint16_t window_id = (pe->pe_number << 1 ) + 1; 1101cd15b048SBenjamin Herrenschmidt int64_t rc; 1102cd15b048SBenjamin Herrenschmidt 1103cd15b048SBenjamin Herrenschmidt pe_info(pe, "%sabling 64-bit DMA bypass\n", enable ? "En" : "Dis"); 1104cd15b048SBenjamin Herrenschmidt if (enable) { 1105cd15b048SBenjamin Herrenschmidt phys_addr_t top = memblock_end_of_DRAM(); 1106cd15b048SBenjamin Herrenschmidt 1107cd15b048SBenjamin Herrenschmidt top = roundup_pow_of_two(top); 1108cd15b048SBenjamin Herrenschmidt rc = opal_pci_map_pe_dma_window_real(pe->phb->opal_id, 1109cd15b048SBenjamin Herrenschmidt pe->pe_number, 1110cd15b048SBenjamin Herrenschmidt window_id, 1111cd15b048SBenjamin Herrenschmidt pe->tce_bypass_base, 1112cd15b048SBenjamin Herrenschmidt top); 1113cd15b048SBenjamin Herrenschmidt } else { 1114cd15b048SBenjamin Herrenschmidt rc = opal_pci_map_pe_dma_window_real(pe->phb->opal_id, 1115cd15b048SBenjamin Herrenschmidt pe->pe_number, 1116cd15b048SBenjamin Herrenschmidt window_id, 1117cd15b048SBenjamin Herrenschmidt pe->tce_bypass_base, 1118cd15b048SBenjamin Herrenschmidt 0); 1119cd15b048SBenjamin Herrenschmidt 1120cd15b048SBenjamin Herrenschmidt /* 1121dff4a39eSGavin Shan * EEH needs the mapping between IOMMU table and group 1122dff4a39eSGavin Shan * of those VFIO/KVM pass-through devices. We can postpone 1123dff4a39eSGavin Shan * resetting DMA ops until the DMA mask is configured in 1124dff4a39eSGavin Shan * host side. 1125cd15b048SBenjamin Herrenschmidt */ 1126dff4a39eSGavin Shan if (pe->pdev) 1127dff4a39eSGavin Shan set_iommu_table_base(&pe->pdev->dev, tbl); 1128dff4a39eSGavin Shan else 1129dff4a39eSGavin Shan pnv_ioda_setup_bus_dma(pe, pe->pbus, false); 1130cd15b048SBenjamin Herrenschmidt } 1131cd15b048SBenjamin Herrenschmidt if (rc) 1132cd15b048SBenjamin Herrenschmidt pe_err(pe, "OPAL error %lld configuring bypass window\n", rc); 1133cd15b048SBenjamin Herrenschmidt else 1134cd15b048SBenjamin Herrenschmidt pe->tce_bypass_enabled = enable; 1135cd15b048SBenjamin Herrenschmidt } 1136cd15b048SBenjamin Herrenschmidt 1137cd15b048SBenjamin Herrenschmidt static void pnv_pci_ioda2_setup_bypass_pe(struct pnv_phb *phb, 1138cd15b048SBenjamin Herrenschmidt struct pnv_ioda_pe *pe) 1139cd15b048SBenjamin Herrenschmidt { 1140cd15b048SBenjamin Herrenschmidt /* TVE #1 is selected by PCI address bit 59 */ 1141cd15b048SBenjamin Herrenschmidt pe->tce_bypass_base = 1ull << 59; 1142cd15b048SBenjamin Herrenschmidt 1143cd15b048SBenjamin Herrenschmidt /* Install set_bypass callback for VFIO */ 1144cd15b048SBenjamin Herrenschmidt pe->tce32_table.set_bypass = pnv_pci_ioda2_set_bypass; 1145cd15b048SBenjamin Herrenschmidt 1146cd15b048SBenjamin Herrenschmidt /* Enable bypass by default */ 1147cd15b048SBenjamin Herrenschmidt pnv_pci_ioda2_set_bypass(&pe->tce32_table, true); 1148cd15b048SBenjamin Herrenschmidt } 1149cd15b048SBenjamin Herrenschmidt 1150373f5657SGavin Shan static void pnv_pci_ioda2_setup_dma_pe(struct pnv_phb *phb, 1151373f5657SGavin Shan struct pnv_ioda_pe *pe) 1152373f5657SGavin Shan { 1153373f5657SGavin Shan struct page *tce_mem = NULL; 1154373f5657SGavin Shan void *addr; 1155373f5657SGavin Shan const __be64 *swinvp; 1156373f5657SGavin Shan struct iommu_table *tbl; 1157373f5657SGavin Shan unsigned int tce_table_size, end; 1158373f5657SGavin Shan int64_t rc; 1159373f5657SGavin Shan 1160373f5657SGavin Shan /* We shouldn't already have a 32-bit DMA associated */ 1161373f5657SGavin Shan if (WARN_ON(pe->tce32_seg >= 0)) 1162373f5657SGavin Shan return; 1163373f5657SGavin Shan 1164373f5657SGavin Shan /* The PE will reserve all possible 32-bits space */ 1165373f5657SGavin Shan pe->tce32_seg = 0; 1166373f5657SGavin Shan end = (1 << ilog2(phb->ioda.m32_pci_base)); 1167373f5657SGavin Shan tce_table_size = (end / 0x1000) * 8; 1168373f5657SGavin Shan pe_info(pe, "Setting up 32-bit TCE table at 0..%08x\n", 1169373f5657SGavin Shan end); 1170373f5657SGavin Shan 1171373f5657SGavin Shan /* Allocate TCE table */ 1172373f5657SGavin Shan tce_mem = alloc_pages_node(phb->hose->node, GFP_KERNEL, 1173373f5657SGavin Shan get_order(tce_table_size)); 1174373f5657SGavin Shan if (!tce_mem) { 1175373f5657SGavin Shan pe_err(pe, "Failed to allocate a 32-bit TCE memory\n"); 1176373f5657SGavin Shan goto fail; 1177373f5657SGavin Shan } 1178373f5657SGavin Shan addr = page_address(tce_mem); 1179373f5657SGavin Shan memset(addr, 0, tce_table_size); 1180373f5657SGavin Shan 1181373f5657SGavin Shan /* 1182373f5657SGavin Shan * Map TCE table through TVT. The TVE index is the PE number 1183373f5657SGavin Shan * shifted by 1 bit for 32-bits DMA space. 1184373f5657SGavin Shan */ 1185373f5657SGavin Shan rc = opal_pci_map_pe_dma_window(phb->opal_id, pe->pe_number, 1186373f5657SGavin Shan pe->pe_number << 1, 1, __pa(addr), 1187373f5657SGavin Shan tce_table_size, 0x1000); 1188373f5657SGavin Shan if (rc) { 1189373f5657SGavin Shan pe_err(pe, "Failed to configure 32-bit TCE table," 1190373f5657SGavin Shan " err %ld\n", rc); 1191373f5657SGavin Shan goto fail; 1192373f5657SGavin Shan } 1193373f5657SGavin Shan 1194373f5657SGavin Shan /* Setup linux iommu table */ 1195373f5657SGavin Shan tbl = &pe->tce32_table; 11968fa5d454SAlexey Kardashevskiy pnv_pci_setup_iommu_table(tbl, addr, tce_table_size, 0, 11978fa5d454SAlexey Kardashevskiy IOMMU_PAGE_SHIFT_4K); 1198373f5657SGavin Shan 1199373f5657SGavin Shan /* OPAL variant of PHB3 invalidated TCEs */ 1200373f5657SGavin Shan swinvp = of_get_property(phb->hose->dn, "ibm,opal-tce-kill", NULL); 1201373f5657SGavin Shan if (swinvp) { 1202373f5657SGavin Shan /* We need a couple more fields -- an address and a data 1203373f5657SGavin Shan * to or. Since the bus is only printed out on table free 1204373f5657SGavin Shan * errors, and on the first pass the data will be a relative 1205373f5657SGavin Shan * bus number, print that out instead. 1206373f5657SGavin Shan */ 12078e0a1611SAlexey Kardashevskiy pe->tce_inval_reg_phys = be64_to_cpup(swinvp); 12088e0a1611SAlexey Kardashevskiy tbl->it_index = (unsigned long)ioremap(pe->tce_inval_reg_phys, 12098e0a1611SAlexey Kardashevskiy 8); 121065fd766bSGavin Shan tbl->it_type |= (TCE_PCI_SWINV_CREATE | TCE_PCI_SWINV_FREE); 1211373f5657SGavin Shan } 1212373f5657SGavin Shan iommu_init_table(tbl, phb->hose->node); 1213e9bc03feSGavin Shan iommu_register_group(tbl, phb->hose->global_number, pe->pe_number); 1214373f5657SGavin Shan 121574251fe2SBenjamin Herrenschmidt if (pe->pdev) 1216d905c5dfSAlexey Kardashevskiy set_iommu_table_base_and_group(&pe->pdev->dev, tbl); 121774251fe2SBenjamin Herrenschmidt else 1218dff4a39eSGavin Shan pnv_ioda_setup_bus_dma(pe, pe->pbus, true); 121974251fe2SBenjamin Herrenschmidt 1220cd15b048SBenjamin Herrenschmidt /* Also create a bypass window */ 1221cd15b048SBenjamin Herrenschmidt pnv_pci_ioda2_setup_bypass_pe(phb, pe); 1222373f5657SGavin Shan return; 1223373f5657SGavin Shan fail: 1224373f5657SGavin Shan if (pe->tce32_seg >= 0) 1225373f5657SGavin Shan pe->tce32_seg = -1; 1226373f5657SGavin Shan if (tce_mem) 1227373f5657SGavin Shan __free_pages(tce_mem, get_order(tce_table_size)); 1228373f5657SGavin Shan } 1229373f5657SGavin Shan 1230cad5cef6SGreg Kroah-Hartman static void pnv_ioda_setup_dma(struct pnv_phb *phb) 1231184cd4a3SBenjamin Herrenschmidt { 1232184cd4a3SBenjamin Herrenschmidt struct pci_controller *hose = phb->hose; 1233184cd4a3SBenjamin Herrenschmidt unsigned int residual, remaining, segs, tw, base; 1234184cd4a3SBenjamin Herrenschmidt struct pnv_ioda_pe *pe; 1235184cd4a3SBenjamin Herrenschmidt 1236184cd4a3SBenjamin Herrenschmidt /* If we have more PE# than segments available, hand out one 1237184cd4a3SBenjamin Herrenschmidt * per PE until we run out and let the rest fail. If not, 1238184cd4a3SBenjamin Herrenschmidt * then we assign at least one segment per PE, plus more based 1239184cd4a3SBenjamin Herrenschmidt * on the amount of devices under that PE 1240184cd4a3SBenjamin Herrenschmidt */ 1241184cd4a3SBenjamin Herrenschmidt if (phb->ioda.dma_pe_count > phb->ioda.tce32_count) 1242184cd4a3SBenjamin Herrenschmidt residual = 0; 1243184cd4a3SBenjamin Herrenschmidt else 1244184cd4a3SBenjamin Herrenschmidt residual = phb->ioda.tce32_count - 1245184cd4a3SBenjamin Herrenschmidt phb->ioda.dma_pe_count; 1246184cd4a3SBenjamin Herrenschmidt 1247184cd4a3SBenjamin Herrenschmidt pr_info("PCI: Domain %04x has %ld available 32-bit DMA segments\n", 1248184cd4a3SBenjamin Herrenschmidt hose->global_number, phb->ioda.tce32_count); 1249184cd4a3SBenjamin Herrenschmidt pr_info("PCI: %d PE# for a total weight of %d\n", 1250184cd4a3SBenjamin Herrenschmidt phb->ioda.dma_pe_count, phb->ioda.dma_weight); 1251184cd4a3SBenjamin Herrenschmidt 1252184cd4a3SBenjamin Herrenschmidt /* Walk our PE list and configure their DMA segments, hand them 1253184cd4a3SBenjamin Herrenschmidt * out one base segment plus any residual segments based on 1254184cd4a3SBenjamin Herrenschmidt * weight 1255184cd4a3SBenjamin Herrenschmidt */ 1256184cd4a3SBenjamin Herrenschmidt remaining = phb->ioda.tce32_count; 1257184cd4a3SBenjamin Herrenschmidt tw = phb->ioda.dma_weight; 1258184cd4a3SBenjamin Herrenschmidt base = 0; 12597ebdf956SGavin Shan list_for_each_entry(pe, &phb->ioda.pe_dma_list, dma_link) { 1260184cd4a3SBenjamin Herrenschmidt if (!pe->dma_weight) 1261184cd4a3SBenjamin Herrenschmidt continue; 1262184cd4a3SBenjamin Herrenschmidt if (!remaining) { 1263184cd4a3SBenjamin Herrenschmidt pe_warn(pe, "No DMA32 resources available\n"); 1264184cd4a3SBenjamin Herrenschmidt continue; 1265184cd4a3SBenjamin Herrenschmidt } 1266184cd4a3SBenjamin Herrenschmidt segs = 1; 1267184cd4a3SBenjamin Herrenschmidt if (residual) { 1268184cd4a3SBenjamin Herrenschmidt segs += ((pe->dma_weight * residual) + (tw / 2)) / tw; 1269184cd4a3SBenjamin Herrenschmidt if (segs > remaining) 1270184cd4a3SBenjamin Herrenschmidt segs = remaining; 1271184cd4a3SBenjamin Herrenschmidt } 1272373f5657SGavin Shan 1273373f5657SGavin Shan /* 1274373f5657SGavin Shan * For IODA2 compliant PHB3, we needn't care about the weight. 1275373f5657SGavin Shan * The all available 32-bits DMA space will be assigned to 1276373f5657SGavin Shan * the specific PE. 1277373f5657SGavin Shan */ 1278373f5657SGavin Shan if (phb->type == PNV_PHB_IODA1) { 1279184cd4a3SBenjamin Herrenschmidt pe_info(pe, "DMA weight %d, assigned %d DMA32 segments\n", 1280184cd4a3SBenjamin Herrenschmidt pe->dma_weight, segs); 1281184cd4a3SBenjamin Herrenschmidt pnv_pci_ioda_setup_dma_pe(phb, pe, base, segs); 1282373f5657SGavin Shan } else { 1283373f5657SGavin Shan pe_info(pe, "Assign DMA32 space\n"); 1284373f5657SGavin Shan segs = 0; 1285373f5657SGavin Shan pnv_pci_ioda2_setup_dma_pe(phb, pe); 1286373f5657SGavin Shan } 1287373f5657SGavin Shan 1288184cd4a3SBenjamin Herrenschmidt remaining -= segs; 1289184cd4a3SBenjamin Herrenschmidt base += segs; 1290184cd4a3SBenjamin Herrenschmidt } 1291184cd4a3SBenjamin Herrenschmidt } 1292184cd4a3SBenjamin Herrenschmidt 1293184cd4a3SBenjamin Herrenschmidt #ifdef CONFIG_PCI_MSI 1294137436c9SGavin Shan static void pnv_ioda2_msi_eoi(struct irq_data *d) 1295137436c9SGavin Shan { 1296137436c9SGavin Shan unsigned int hw_irq = (unsigned int)irqd_to_hwirq(d); 1297137436c9SGavin Shan struct irq_chip *chip = irq_data_get_irq_chip(d); 1298137436c9SGavin Shan struct pnv_phb *phb = container_of(chip, struct pnv_phb, 1299137436c9SGavin Shan ioda.irq_chip); 1300137436c9SGavin Shan int64_t rc; 1301137436c9SGavin Shan 1302137436c9SGavin Shan rc = opal_pci_msi_eoi(phb->opal_id, hw_irq); 1303137436c9SGavin Shan WARN_ON_ONCE(rc); 1304137436c9SGavin Shan 1305137436c9SGavin Shan icp_native_eoi(d); 1306137436c9SGavin Shan } 1307137436c9SGavin Shan 1308184cd4a3SBenjamin Herrenschmidt static int pnv_pci_ioda_msi_setup(struct pnv_phb *phb, struct pci_dev *dev, 1309137436c9SGavin Shan unsigned int hwirq, unsigned int virq, 1310137436c9SGavin Shan unsigned int is_64, struct msi_msg *msg) 1311184cd4a3SBenjamin Herrenschmidt { 1312184cd4a3SBenjamin Herrenschmidt struct pnv_ioda_pe *pe = pnv_ioda_get_pe(dev); 1313b72c1f65SBenjamin Herrenschmidt struct pci_dn *pdn = pci_get_pdn(dev); 1314137436c9SGavin Shan struct irq_data *idata; 1315137436c9SGavin Shan struct irq_chip *ichip; 1316184cd4a3SBenjamin Herrenschmidt unsigned int xive_num = hwirq - phb->msi_base; 13173a1a4661SBenjamin Herrenschmidt __be32 data; 1318184cd4a3SBenjamin Herrenschmidt int rc; 1319184cd4a3SBenjamin Herrenschmidt 1320184cd4a3SBenjamin Herrenschmidt /* No PE assigned ? bail out ... no MSI for you ! */ 1321184cd4a3SBenjamin Herrenschmidt if (pe == NULL) 1322184cd4a3SBenjamin Herrenschmidt return -ENXIO; 1323184cd4a3SBenjamin Herrenschmidt 1324184cd4a3SBenjamin Herrenschmidt /* Check if we have an MVE */ 1325184cd4a3SBenjamin Herrenschmidt if (pe->mve_number < 0) 1326184cd4a3SBenjamin Herrenschmidt return -ENXIO; 1327184cd4a3SBenjamin Herrenschmidt 1328b72c1f65SBenjamin Herrenschmidt /* Force 32-bit MSI on some broken devices */ 1329b72c1f65SBenjamin Herrenschmidt if (pdn && pdn->force_32bit_msi) 1330b72c1f65SBenjamin Herrenschmidt is_64 = 0; 1331b72c1f65SBenjamin Herrenschmidt 1332184cd4a3SBenjamin Herrenschmidt /* Assign XIVE to PE */ 1333184cd4a3SBenjamin Herrenschmidt rc = opal_pci_set_xive_pe(phb->opal_id, pe->pe_number, xive_num); 1334184cd4a3SBenjamin Herrenschmidt if (rc) { 1335184cd4a3SBenjamin Herrenschmidt pr_warn("%s: OPAL error %d setting XIVE %d PE\n", 1336184cd4a3SBenjamin Herrenschmidt pci_name(dev), rc, xive_num); 1337184cd4a3SBenjamin Herrenschmidt return -EIO; 1338184cd4a3SBenjamin Herrenschmidt } 1339184cd4a3SBenjamin Herrenschmidt 1340184cd4a3SBenjamin Herrenschmidt if (is_64) { 13413a1a4661SBenjamin Herrenschmidt __be64 addr64; 13423a1a4661SBenjamin Herrenschmidt 1343184cd4a3SBenjamin Herrenschmidt rc = opal_get_msi_64(phb->opal_id, pe->mve_number, xive_num, 1, 1344184cd4a3SBenjamin Herrenschmidt &addr64, &data); 1345184cd4a3SBenjamin Herrenschmidt if (rc) { 1346184cd4a3SBenjamin Herrenschmidt pr_warn("%s: OPAL error %d getting 64-bit MSI data\n", 1347184cd4a3SBenjamin Herrenschmidt pci_name(dev), rc); 1348184cd4a3SBenjamin Herrenschmidt return -EIO; 1349184cd4a3SBenjamin Herrenschmidt } 13503a1a4661SBenjamin Herrenschmidt msg->address_hi = be64_to_cpu(addr64) >> 32; 13513a1a4661SBenjamin Herrenschmidt msg->address_lo = be64_to_cpu(addr64) & 0xfffffffful; 1352184cd4a3SBenjamin Herrenschmidt } else { 13533a1a4661SBenjamin Herrenschmidt __be32 addr32; 13543a1a4661SBenjamin Herrenschmidt 1355184cd4a3SBenjamin Herrenschmidt rc = opal_get_msi_32(phb->opal_id, pe->mve_number, xive_num, 1, 1356184cd4a3SBenjamin Herrenschmidt &addr32, &data); 1357184cd4a3SBenjamin Herrenschmidt if (rc) { 1358184cd4a3SBenjamin Herrenschmidt pr_warn("%s: OPAL error %d getting 32-bit MSI data\n", 1359184cd4a3SBenjamin Herrenschmidt pci_name(dev), rc); 1360184cd4a3SBenjamin Herrenschmidt return -EIO; 1361184cd4a3SBenjamin Herrenschmidt } 1362184cd4a3SBenjamin Herrenschmidt msg->address_hi = 0; 13633a1a4661SBenjamin Herrenschmidt msg->address_lo = be32_to_cpu(addr32); 1364184cd4a3SBenjamin Herrenschmidt } 13653a1a4661SBenjamin Herrenschmidt msg->data = be32_to_cpu(data); 1366184cd4a3SBenjamin Herrenschmidt 1367137436c9SGavin Shan /* 1368137436c9SGavin Shan * Change the IRQ chip for the MSI interrupts on PHB3. 1369137436c9SGavin Shan * The corresponding IRQ chip should be populated for 1370137436c9SGavin Shan * the first time. 1371137436c9SGavin Shan */ 1372137436c9SGavin Shan if (phb->type == PNV_PHB_IODA2) { 1373137436c9SGavin Shan if (!phb->ioda.irq_chip_init) { 1374137436c9SGavin Shan idata = irq_get_irq_data(virq); 1375137436c9SGavin Shan ichip = irq_data_get_irq_chip(idata); 1376137436c9SGavin Shan phb->ioda.irq_chip_init = 1; 1377137436c9SGavin Shan phb->ioda.irq_chip = *ichip; 1378137436c9SGavin Shan phb->ioda.irq_chip.irq_eoi = pnv_ioda2_msi_eoi; 1379137436c9SGavin Shan } 1380137436c9SGavin Shan 1381137436c9SGavin Shan irq_set_chip(virq, &phb->ioda.irq_chip); 1382137436c9SGavin Shan } 1383137436c9SGavin Shan 1384184cd4a3SBenjamin Herrenschmidt pr_devel("%s: %s-bit MSI on hwirq %x (xive #%d)," 1385184cd4a3SBenjamin Herrenschmidt " address=%x_%08x data=%x PE# %d\n", 1386184cd4a3SBenjamin Herrenschmidt pci_name(dev), is_64 ? "64" : "32", hwirq, xive_num, 1387184cd4a3SBenjamin Herrenschmidt msg->address_hi, msg->address_lo, data, pe->pe_number); 1388184cd4a3SBenjamin Herrenschmidt 1389184cd4a3SBenjamin Herrenschmidt return 0; 1390184cd4a3SBenjamin Herrenschmidt } 1391184cd4a3SBenjamin Herrenschmidt 1392184cd4a3SBenjamin Herrenschmidt static void pnv_pci_init_ioda_msis(struct pnv_phb *phb) 1393184cd4a3SBenjamin Herrenschmidt { 1394fb1b55d6SGavin Shan unsigned int count; 1395184cd4a3SBenjamin Herrenschmidt const __be32 *prop = of_get_property(phb->hose->dn, 1396184cd4a3SBenjamin Herrenschmidt "ibm,opal-msi-ranges", NULL); 1397184cd4a3SBenjamin Herrenschmidt if (!prop) { 1398184cd4a3SBenjamin Herrenschmidt /* BML Fallback */ 1399184cd4a3SBenjamin Herrenschmidt prop = of_get_property(phb->hose->dn, "msi-ranges", NULL); 1400184cd4a3SBenjamin Herrenschmidt } 1401184cd4a3SBenjamin Herrenschmidt if (!prop) 1402184cd4a3SBenjamin Herrenschmidt return; 1403184cd4a3SBenjamin Herrenschmidt 1404184cd4a3SBenjamin Herrenschmidt phb->msi_base = be32_to_cpup(prop); 1405fb1b55d6SGavin Shan count = be32_to_cpup(prop + 1); 1406fb1b55d6SGavin Shan if (msi_bitmap_alloc(&phb->msi_bmp, count, phb->hose->dn)) { 1407184cd4a3SBenjamin Herrenschmidt pr_err("PCI %d: Failed to allocate MSI bitmap !\n", 1408184cd4a3SBenjamin Herrenschmidt phb->hose->global_number); 1409184cd4a3SBenjamin Herrenschmidt return; 1410184cd4a3SBenjamin Herrenschmidt } 1411fb1b55d6SGavin Shan 1412184cd4a3SBenjamin Herrenschmidt phb->msi_setup = pnv_pci_ioda_msi_setup; 1413184cd4a3SBenjamin Herrenschmidt phb->msi32_support = 1; 1414184cd4a3SBenjamin Herrenschmidt pr_info(" Allocated bitmap for %d MSIs (base IRQ 0x%x)\n", 1415fb1b55d6SGavin Shan count, phb->msi_base); 1416184cd4a3SBenjamin Herrenschmidt } 1417184cd4a3SBenjamin Herrenschmidt #else 1418184cd4a3SBenjamin Herrenschmidt static void pnv_pci_init_ioda_msis(struct pnv_phb *phb) { } 1419184cd4a3SBenjamin Herrenschmidt #endif /* CONFIG_PCI_MSI */ 1420184cd4a3SBenjamin Herrenschmidt 142111685becSGavin Shan /* 142211685becSGavin Shan * This function is supposed to be called on basis of PE from top 142311685becSGavin Shan * to bottom style. So the the I/O or MMIO segment assigned to 142411685becSGavin Shan * parent PE could be overrided by its child PEs if necessary. 142511685becSGavin Shan */ 1426cad5cef6SGreg Kroah-Hartman static void pnv_ioda_setup_pe_seg(struct pci_controller *hose, 142711685becSGavin Shan struct pnv_ioda_pe *pe) 142811685becSGavin Shan { 142911685becSGavin Shan struct pnv_phb *phb = hose->private_data; 143011685becSGavin Shan struct pci_bus_region region; 143111685becSGavin Shan struct resource *res; 143211685becSGavin Shan int i, index; 143311685becSGavin Shan int rc; 143411685becSGavin Shan 143511685becSGavin Shan /* 143611685becSGavin Shan * NOTE: We only care PCI bus based PE for now. For PCI 143711685becSGavin Shan * device based PE, for example SRIOV sensitive VF should 143811685becSGavin Shan * be figured out later. 143911685becSGavin Shan */ 144011685becSGavin Shan BUG_ON(!(pe->flags & (PNV_IODA_PE_BUS | PNV_IODA_PE_BUS_ALL))); 144111685becSGavin Shan 144211685becSGavin Shan pci_bus_for_each_resource(pe->pbus, res, i) { 144311685becSGavin Shan if (!res || !res->flags || 144411685becSGavin Shan res->start > res->end) 144511685becSGavin Shan continue; 144611685becSGavin Shan 144711685becSGavin Shan if (res->flags & IORESOURCE_IO) { 144811685becSGavin Shan region.start = res->start - phb->ioda.io_pci_base; 144911685becSGavin Shan region.end = res->end - phb->ioda.io_pci_base; 145011685becSGavin Shan index = region.start / phb->ioda.io_segsize; 145111685becSGavin Shan 145211685becSGavin Shan while (index < phb->ioda.total_pe && 145311685becSGavin Shan region.start <= region.end) { 145411685becSGavin Shan phb->ioda.io_segmap[index] = pe->pe_number; 145511685becSGavin Shan rc = opal_pci_map_pe_mmio_window(phb->opal_id, 145611685becSGavin Shan pe->pe_number, OPAL_IO_WINDOW_TYPE, 0, index); 145711685becSGavin Shan if (rc != OPAL_SUCCESS) { 145811685becSGavin Shan pr_err("%s: OPAL error %d when mapping IO " 145911685becSGavin Shan "segment #%d to PE#%d\n", 146011685becSGavin Shan __func__, rc, index, pe->pe_number); 146111685becSGavin Shan break; 146211685becSGavin Shan } 146311685becSGavin Shan 146411685becSGavin Shan region.start += phb->ioda.io_segsize; 146511685becSGavin Shan index++; 146611685becSGavin Shan } 146711685becSGavin Shan } else if (res->flags & IORESOURCE_MEM) { 146811685becSGavin Shan region.start = res->start - 14693fd47f06SBenjamin Herrenschmidt hose->mem_offset[0] - 147011685becSGavin Shan phb->ioda.m32_pci_base; 147111685becSGavin Shan region.end = res->end - 14723fd47f06SBenjamin Herrenschmidt hose->mem_offset[0] - 147311685becSGavin Shan phb->ioda.m32_pci_base; 147411685becSGavin Shan index = region.start / phb->ioda.m32_segsize; 147511685becSGavin Shan 147611685becSGavin Shan while (index < phb->ioda.total_pe && 147711685becSGavin Shan region.start <= region.end) { 147811685becSGavin Shan phb->ioda.m32_segmap[index] = pe->pe_number; 147911685becSGavin Shan rc = opal_pci_map_pe_mmio_window(phb->opal_id, 148011685becSGavin Shan pe->pe_number, OPAL_M32_WINDOW_TYPE, 0, index); 148111685becSGavin Shan if (rc != OPAL_SUCCESS) { 148211685becSGavin Shan pr_err("%s: OPAL error %d when mapping M32 " 148311685becSGavin Shan "segment#%d to PE#%d", 148411685becSGavin Shan __func__, rc, index, pe->pe_number); 148511685becSGavin Shan break; 148611685becSGavin Shan } 148711685becSGavin Shan 148811685becSGavin Shan region.start += phb->ioda.m32_segsize; 148911685becSGavin Shan index++; 149011685becSGavin Shan } 149111685becSGavin Shan } 149211685becSGavin Shan } 149311685becSGavin Shan } 149411685becSGavin Shan 1495cad5cef6SGreg Kroah-Hartman static void pnv_pci_ioda_setup_seg(void) 149611685becSGavin Shan { 149711685becSGavin Shan struct pci_controller *tmp, *hose; 149811685becSGavin Shan struct pnv_phb *phb; 149911685becSGavin Shan struct pnv_ioda_pe *pe; 150011685becSGavin Shan 150111685becSGavin Shan list_for_each_entry_safe(hose, tmp, &hose_list, list_node) { 150211685becSGavin Shan phb = hose->private_data; 150311685becSGavin Shan list_for_each_entry(pe, &phb->ioda.pe_list, list) { 150411685becSGavin Shan pnv_ioda_setup_pe_seg(hose, pe); 150511685becSGavin Shan } 150611685becSGavin Shan } 150711685becSGavin Shan } 150811685becSGavin Shan 1509cad5cef6SGreg Kroah-Hartman static void pnv_pci_ioda_setup_DMA(void) 151013395c48SGavin Shan { 151113395c48SGavin Shan struct pci_controller *hose, *tmp; 1512db1266c8SGavin Shan struct pnv_phb *phb; 151313395c48SGavin Shan 151413395c48SGavin Shan list_for_each_entry_safe(hose, tmp, &hose_list, list_node) { 151513395c48SGavin Shan pnv_ioda_setup_dma(hose->private_data); 1516db1266c8SGavin Shan 1517db1266c8SGavin Shan /* Mark the PHB initialization done */ 1518db1266c8SGavin Shan phb = hose->private_data; 1519db1266c8SGavin Shan phb->initialized = 1; 152013395c48SGavin Shan } 152113395c48SGavin Shan } 152213395c48SGavin Shan 152337c367f2SGavin Shan static void pnv_pci_ioda_create_dbgfs(void) 152437c367f2SGavin Shan { 152537c367f2SGavin Shan #ifdef CONFIG_DEBUG_FS 152637c367f2SGavin Shan struct pci_controller *hose, *tmp; 152737c367f2SGavin Shan struct pnv_phb *phb; 152837c367f2SGavin Shan char name[16]; 152937c367f2SGavin Shan 153037c367f2SGavin Shan list_for_each_entry_safe(hose, tmp, &hose_list, list_node) { 153137c367f2SGavin Shan phb = hose->private_data; 153237c367f2SGavin Shan 153337c367f2SGavin Shan sprintf(name, "PCI%04x", hose->global_number); 153437c367f2SGavin Shan phb->dbgfs = debugfs_create_dir(name, powerpc_debugfs_root); 153537c367f2SGavin Shan if (!phb->dbgfs) 153637c367f2SGavin Shan pr_warning("%s: Error on creating debugfs on PHB#%x\n", 153737c367f2SGavin Shan __func__, hose->global_number); 153837c367f2SGavin Shan } 153937c367f2SGavin Shan #endif /* CONFIG_DEBUG_FS */ 154037c367f2SGavin Shan } 154137c367f2SGavin Shan 1542cad5cef6SGreg Kroah-Hartman static void pnv_pci_ioda_fixup(void) 1543fb446ad0SGavin Shan { 1544fb446ad0SGavin Shan pnv_pci_ioda_setup_PEs(); 154511685becSGavin Shan pnv_pci_ioda_setup_seg(); 154613395c48SGavin Shan pnv_pci_ioda_setup_DMA(); 1547e9cc17d4SGavin Shan 154837c367f2SGavin Shan pnv_pci_ioda_create_dbgfs(); 154937c367f2SGavin Shan 1550e9cc17d4SGavin Shan #ifdef CONFIG_EEH 1551e9cc17d4SGavin Shan eeh_init(); 1552dadcd6d6SMike Qiu eeh_addr_cache_build(); 1553e9cc17d4SGavin Shan #endif 1554fb446ad0SGavin Shan } 1555fb446ad0SGavin Shan 1556271fd03aSGavin Shan /* 1557271fd03aSGavin Shan * Returns the alignment for I/O or memory windows for P2P 1558271fd03aSGavin Shan * bridges. That actually depends on how PEs are segmented. 1559271fd03aSGavin Shan * For now, we return I/O or M32 segment size for PE sensitive 1560271fd03aSGavin Shan * P2P bridges. Otherwise, the default values (4KiB for I/O, 1561271fd03aSGavin Shan * 1MiB for memory) will be returned. 1562271fd03aSGavin Shan * 1563271fd03aSGavin Shan * The current PCI bus might be put into one PE, which was 1564271fd03aSGavin Shan * create against the parent PCI bridge. For that case, we 1565271fd03aSGavin Shan * needn't enlarge the alignment so that we can save some 1566271fd03aSGavin Shan * resources. 1567271fd03aSGavin Shan */ 1568271fd03aSGavin Shan static resource_size_t pnv_pci_window_alignment(struct pci_bus *bus, 1569271fd03aSGavin Shan unsigned long type) 1570271fd03aSGavin Shan { 1571271fd03aSGavin Shan struct pci_dev *bridge; 1572271fd03aSGavin Shan struct pci_controller *hose = pci_bus_to_host(bus); 1573271fd03aSGavin Shan struct pnv_phb *phb = hose->private_data; 1574271fd03aSGavin Shan int num_pci_bridges = 0; 1575271fd03aSGavin Shan 1576271fd03aSGavin Shan bridge = bus->self; 1577271fd03aSGavin Shan while (bridge) { 1578271fd03aSGavin Shan if (pci_pcie_type(bridge) == PCI_EXP_TYPE_PCI_BRIDGE) { 1579271fd03aSGavin Shan num_pci_bridges++; 1580271fd03aSGavin Shan if (num_pci_bridges >= 2) 1581271fd03aSGavin Shan return 1; 1582271fd03aSGavin Shan } 1583271fd03aSGavin Shan 1584271fd03aSGavin Shan bridge = bridge->bus->self; 1585271fd03aSGavin Shan } 1586271fd03aSGavin Shan 1587262af557SGuo Chao /* We fail back to M32 if M64 isn't supported */ 1588262af557SGuo Chao if (phb->ioda.m64_segsize && 1589262af557SGuo Chao pnv_pci_is_mem_pref_64(type)) 1590262af557SGuo Chao return phb->ioda.m64_segsize; 1591271fd03aSGavin Shan if (type & IORESOURCE_MEM) 1592271fd03aSGavin Shan return phb->ioda.m32_segsize; 1593271fd03aSGavin Shan 1594271fd03aSGavin Shan return phb->ioda.io_segsize; 1595271fd03aSGavin Shan } 1596271fd03aSGavin Shan 1597184cd4a3SBenjamin Herrenschmidt /* Prevent enabling devices for which we couldn't properly 1598184cd4a3SBenjamin Herrenschmidt * assign a PE 1599184cd4a3SBenjamin Herrenschmidt */ 1600cad5cef6SGreg Kroah-Hartman static int pnv_pci_enable_device_hook(struct pci_dev *dev) 1601184cd4a3SBenjamin Herrenschmidt { 1602db1266c8SGavin Shan struct pci_controller *hose = pci_bus_to_host(dev->bus); 1603db1266c8SGavin Shan struct pnv_phb *phb = hose->private_data; 1604db1266c8SGavin Shan struct pci_dn *pdn; 1605184cd4a3SBenjamin Herrenschmidt 1606db1266c8SGavin Shan /* The function is probably called while the PEs have 1607db1266c8SGavin Shan * not be created yet. For example, resource reassignment 1608db1266c8SGavin Shan * during PCI probe period. We just skip the check if 1609db1266c8SGavin Shan * PEs isn't ready. 1610db1266c8SGavin Shan */ 1611db1266c8SGavin Shan if (!phb->initialized) 1612db1266c8SGavin Shan return 0; 1613db1266c8SGavin Shan 1614b72c1f65SBenjamin Herrenschmidt pdn = pci_get_pdn(dev); 1615184cd4a3SBenjamin Herrenschmidt if (!pdn || pdn->pe_number == IODA_INVALID_PE) 1616184cd4a3SBenjamin Herrenschmidt return -EINVAL; 1617db1266c8SGavin Shan 1618184cd4a3SBenjamin Herrenschmidt return 0; 1619184cd4a3SBenjamin Herrenschmidt } 1620184cd4a3SBenjamin Herrenschmidt 1621184cd4a3SBenjamin Herrenschmidt static u32 pnv_ioda_bdfn_to_pe(struct pnv_phb *phb, struct pci_bus *bus, 1622184cd4a3SBenjamin Herrenschmidt u32 devfn) 1623184cd4a3SBenjamin Herrenschmidt { 1624184cd4a3SBenjamin Herrenschmidt return phb->ioda.pe_rmap[(bus->number << 8) | devfn]; 1625184cd4a3SBenjamin Herrenschmidt } 1626184cd4a3SBenjamin Herrenschmidt 162773ed148aSBenjamin Herrenschmidt static void pnv_pci_ioda_shutdown(struct pnv_phb *phb) 162873ed148aSBenjamin Herrenschmidt { 1629d1a85eeeSGavin Shan opal_pci_reset(phb->opal_id, OPAL_RESET_PCI_IODA_TABLE, 163073ed148aSBenjamin Herrenschmidt OPAL_ASSERT_RESET); 163173ed148aSBenjamin Herrenschmidt } 163273ed148aSBenjamin Herrenschmidt 1633e51df2c1SAnton Blanchard static void __init pnv_pci_init_ioda_phb(struct device_node *np, 1634e9cc17d4SGavin Shan u64 hub_id, int ioda_type) 1635184cd4a3SBenjamin Herrenschmidt { 1636184cd4a3SBenjamin Herrenschmidt struct pci_controller *hose; 1637184cd4a3SBenjamin Herrenschmidt struct pnv_phb *phb; 16388184616fSGavin Shan unsigned long size, m32map_off, pemap_off, iomap_off = 0; 1639c681b93cSAlistair Popple const __be64 *prop64; 16403a1a4661SBenjamin Herrenschmidt const __be32 *prop32; 1641f1b7cc3eSGavin Shan int len; 1642184cd4a3SBenjamin Herrenschmidt u64 phb_id; 1643184cd4a3SBenjamin Herrenschmidt void *aux; 1644184cd4a3SBenjamin Herrenschmidt long rc; 1645184cd4a3SBenjamin Herrenschmidt 1646aa0c033fSGavin Shan pr_info("Initializing IODA%d OPAL PHB %s\n", ioda_type, np->full_name); 1647184cd4a3SBenjamin Herrenschmidt 1648184cd4a3SBenjamin Herrenschmidt prop64 = of_get_property(np, "ibm,opal-phbid", NULL); 1649184cd4a3SBenjamin Herrenschmidt if (!prop64) { 1650184cd4a3SBenjamin Herrenschmidt pr_err(" Missing \"ibm,opal-phbid\" property !\n"); 1651184cd4a3SBenjamin Herrenschmidt return; 1652184cd4a3SBenjamin Herrenschmidt } 1653184cd4a3SBenjamin Herrenschmidt phb_id = be64_to_cpup(prop64); 1654184cd4a3SBenjamin Herrenschmidt pr_debug(" PHB-ID : 0x%016llx\n", phb_id); 1655184cd4a3SBenjamin Herrenschmidt 1656184cd4a3SBenjamin Herrenschmidt phb = alloc_bootmem(sizeof(struct pnv_phb)); 165758d714ecSGavin Shan if (!phb) { 165858d714ecSGavin Shan pr_err(" Out of memory !\n"); 165958d714ecSGavin Shan return; 166058d714ecSGavin Shan } 166158d714ecSGavin Shan 166258d714ecSGavin Shan /* Allocate PCI controller */ 1663184cd4a3SBenjamin Herrenschmidt memset(phb, 0, sizeof(struct pnv_phb)); 1664184cd4a3SBenjamin Herrenschmidt phb->hose = hose = pcibios_alloc_controller(np); 166558d714ecSGavin Shan if (!phb->hose) { 166658d714ecSGavin Shan pr_err(" Can't allocate PCI controller for %s\n", 1667184cd4a3SBenjamin Herrenschmidt np->full_name); 166858d714ecSGavin Shan free_bootmem((unsigned long)phb, sizeof(struct pnv_phb)); 1669184cd4a3SBenjamin Herrenschmidt return; 1670184cd4a3SBenjamin Herrenschmidt } 1671184cd4a3SBenjamin Herrenschmidt 1672184cd4a3SBenjamin Herrenschmidt spin_lock_init(&phb->lock); 1673f1b7cc3eSGavin Shan prop32 = of_get_property(np, "bus-range", &len); 1674f1b7cc3eSGavin Shan if (prop32 && len == 8) { 16753a1a4661SBenjamin Herrenschmidt hose->first_busno = be32_to_cpu(prop32[0]); 16763a1a4661SBenjamin Herrenschmidt hose->last_busno = be32_to_cpu(prop32[1]); 1677f1b7cc3eSGavin Shan } else { 1678f1b7cc3eSGavin Shan pr_warn(" Broken <bus-range> on %s\n", np->full_name); 1679184cd4a3SBenjamin Herrenschmidt hose->first_busno = 0; 1680184cd4a3SBenjamin Herrenschmidt hose->last_busno = 0xff; 1681f1b7cc3eSGavin Shan } 1682184cd4a3SBenjamin Herrenschmidt hose->private_data = phb; 1683e9cc17d4SGavin Shan phb->hub_id = hub_id; 1684184cd4a3SBenjamin Herrenschmidt phb->opal_id = phb_id; 1685aa0c033fSGavin Shan phb->type = ioda_type; 1686184cd4a3SBenjamin Herrenschmidt 1687cee72d5bSBenjamin Herrenschmidt /* Detect specific models for error handling */ 1688cee72d5bSBenjamin Herrenschmidt if (of_device_is_compatible(np, "ibm,p7ioc-pciex")) 1689cee72d5bSBenjamin Herrenschmidt phb->model = PNV_PHB_MODEL_P7IOC; 1690f3d40c25SBenjamin Herrenschmidt else if (of_device_is_compatible(np, "ibm,power8-pciex")) 1691aa0c033fSGavin Shan phb->model = PNV_PHB_MODEL_PHB3; 1692cee72d5bSBenjamin Herrenschmidt else 1693cee72d5bSBenjamin Herrenschmidt phb->model = PNV_PHB_MODEL_UNKNOWN; 1694cee72d5bSBenjamin Herrenschmidt 1695aa0c033fSGavin Shan /* Parse 32-bit and IO ranges (if any) */ 16962f1ec02eSGavin Shan pci_process_bridge_OF_ranges(hose, np, !hose->global_number); 1697184cd4a3SBenjamin Herrenschmidt 1698aa0c033fSGavin Shan /* Get registers */ 1699184cd4a3SBenjamin Herrenschmidt phb->regs = of_iomap(np, 0); 1700184cd4a3SBenjamin Herrenschmidt if (phb->regs == NULL) 1701184cd4a3SBenjamin Herrenschmidt pr_err(" Failed to map registers !\n"); 1702184cd4a3SBenjamin Herrenschmidt 1703184cd4a3SBenjamin Herrenschmidt /* Initialize more IODA stuff */ 1704aa0c033fSGavin Shan phb->ioda.total_pe = 1; 170536954dc7SGavin Shan prop32 = of_get_property(np, "ibm,opal-num-pes", NULL); 170636954dc7SGavin Shan if (prop32) 17073a1a4661SBenjamin Herrenschmidt phb->ioda.total_pe = be32_to_cpup(prop32); 170836954dc7SGavin Shan prop32 = of_get_property(np, "ibm,opal-reserved-pe", NULL); 170936954dc7SGavin Shan if (prop32) 171036954dc7SGavin Shan phb->ioda.reserved_pe = be32_to_cpup(prop32); 1711262af557SGuo Chao 1712262af557SGuo Chao /* Parse 64-bit MMIO range */ 1713262af557SGuo Chao pnv_ioda_parse_m64_window(phb); 1714262af557SGuo Chao 1715184cd4a3SBenjamin Herrenschmidt phb->ioda.m32_size = resource_size(&hose->mem_resources[0]); 1716aa0c033fSGavin Shan /* FW Has already off top 64k of M32 space (MSI space) */ 1717184cd4a3SBenjamin Herrenschmidt phb->ioda.m32_size += 0x10000; 1718184cd4a3SBenjamin Herrenschmidt 1719184cd4a3SBenjamin Herrenschmidt phb->ioda.m32_segsize = phb->ioda.m32_size / phb->ioda.total_pe; 17203fd47f06SBenjamin Herrenschmidt phb->ioda.m32_pci_base = hose->mem_resources[0].start - hose->mem_offset[0]; 1721184cd4a3SBenjamin Herrenschmidt phb->ioda.io_size = hose->pci_io_size; 1722184cd4a3SBenjamin Herrenschmidt phb->ioda.io_segsize = phb->ioda.io_size / phb->ioda.total_pe; 1723184cd4a3SBenjamin Herrenschmidt phb->ioda.io_pci_base = 0; /* XXX calculate this ? */ 1724184cd4a3SBenjamin Herrenschmidt 1725c35d2a8cSGavin Shan /* Allocate aux data & arrays. We don't have IO ports on PHB3 */ 1726184cd4a3SBenjamin Herrenschmidt size = _ALIGN_UP(phb->ioda.total_pe / 8, sizeof(unsigned long)); 1727184cd4a3SBenjamin Herrenschmidt m32map_off = size; 1728e47747f4SGavin Shan size += phb->ioda.total_pe * sizeof(phb->ioda.m32_segmap[0]); 1729c35d2a8cSGavin Shan if (phb->type == PNV_PHB_IODA1) { 1730c35d2a8cSGavin Shan iomap_off = size; 1731e47747f4SGavin Shan size += phb->ioda.total_pe * sizeof(phb->ioda.io_segmap[0]); 1732c35d2a8cSGavin Shan } 1733184cd4a3SBenjamin Herrenschmidt pemap_off = size; 1734184cd4a3SBenjamin Herrenschmidt size += phb->ioda.total_pe * sizeof(struct pnv_ioda_pe); 1735184cd4a3SBenjamin Herrenschmidt aux = alloc_bootmem(size); 1736184cd4a3SBenjamin Herrenschmidt memset(aux, 0, size); 1737184cd4a3SBenjamin Herrenschmidt phb->ioda.pe_alloc = aux; 1738184cd4a3SBenjamin Herrenschmidt phb->ioda.m32_segmap = aux + m32map_off; 1739c35d2a8cSGavin Shan if (phb->type == PNV_PHB_IODA1) 1740184cd4a3SBenjamin Herrenschmidt phb->ioda.io_segmap = aux + iomap_off; 1741184cd4a3SBenjamin Herrenschmidt phb->ioda.pe_array = aux + pemap_off; 174236954dc7SGavin Shan set_bit(phb->ioda.reserved_pe, phb->ioda.pe_alloc); 1743184cd4a3SBenjamin Herrenschmidt 17447ebdf956SGavin Shan INIT_LIST_HEAD(&phb->ioda.pe_dma_list); 1745184cd4a3SBenjamin Herrenschmidt INIT_LIST_HEAD(&phb->ioda.pe_list); 1746184cd4a3SBenjamin Herrenschmidt 1747184cd4a3SBenjamin Herrenschmidt /* Calculate how many 32-bit TCE segments we have */ 1748184cd4a3SBenjamin Herrenschmidt phb->ioda.tce32_count = phb->ioda.m32_pci_base >> 28; 1749184cd4a3SBenjamin Herrenschmidt 1750aa0c033fSGavin Shan #if 0 /* We should really do that ... */ 1751184cd4a3SBenjamin Herrenschmidt rc = opal_pci_set_phb_mem_window(opal->phb_id, 1752184cd4a3SBenjamin Herrenschmidt window_type, 1753184cd4a3SBenjamin Herrenschmidt window_num, 1754184cd4a3SBenjamin Herrenschmidt starting_real_address, 1755184cd4a3SBenjamin Herrenschmidt starting_pci_address, 1756184cd4a3SBenjamin Herrenschmidt segment_size); 1757184cd4a3SBenjamin Herrenschmidt #endif 1758184cd4a3SBenjamin Herrenschmidt 1759262af557SGuo Chao pr_info(" %03d (%03d) PE's M32: 0x%x [segment=0x%x]\n", 1760262af557SGuo Chao phb->ioda.total_pe, phb->ioda.reserved_pe, 1761262af557SGuo Chao phb->ioda.m32_size, phb->ioda.m32_segsize); 1762262af557SGuo Chao if (phb->ioda.m64_size) 1763262af557SGuo Chao pr_info(" M64: 0x%lx [segment=0x%lx]\n", 1764262af557SGuo Chao phb->ioda.m64_size, phb->ioda.m64_segsize); 1765262af557SGuo Chao if (phb->ioda.io_size) 1766262af557SGuo Chao pr_info(" IO: 0x%x [segment=0x%x]\n", 1767184cd4a3SBenjamin Herrenschmidt phb->ioda.io_size, phb->ioda.io_segsize); 1768184cd4a3SBenjamin Herrenschmidt 1769262af557SGuo Chao 1770184cd4a3SBenjamin Herrenschmidt phb->hose->ops = &pnv_pci_ops; 177149dec922SGavin Shan phb->get_pe_state = pnv_ioda_get_pe_state; 177249dec922SGavin Shan phb->freeze_pe = pnv_ioda_freeze_pe; 177349dec922SGavin Shan phb->unfreeze_pe = pnv_ioda_unfreeze_pe; 1774e9cc17d4SGavin Shan #ifdef CONFIG_EEH 1775e9cc17d4SGavin Shan phb->eeh_ops = &ioda_eeh_ops; 1776e9cc17d4SGavin Shan #endif 1777184cd4a3SBenjamin Herrenschmidt 1778184cd4a3SBenjamin Herrenschmidt /* Setup RID -> PE mapping function */ 1779184cd4a3SBenjamin Herrenschmidt phb->bdfn_to_pe = pnv_ioda_bdfn_to_pe; 1780184cd4a3SBenjamin Herrenschmidt 1781184cd4a3SBenjamin Herrenschmidt /* Setup TCEs */ 1782184cd4a3SBenjamin Herrenschmidt phb->dma_dev_setup = pnv_pci_ioda_dma_dev_setup; 1783cd15b048SBenjamin Herrenschmidt phb->dma_set_mask = pnv_pci_ioda_dma_set_mask; 1784184cd4a3SBenjamin Herrenschmidt 178573ed148aSBenjamin Herrenschmidt /* Setup shutdown function for kexec */ 178673ed148aSBenjamin Herrenschmidt phb->shutdown = pnv_pci_ioda_shutdown; 178773ed148aSBenjamin Herrenschmidt 1788184cd4a3SBenjamin Herrenschmidt /* Setup MSI support */ 1789184cd4a3SBenjamin Herrenschmidt pnv_pci_init_ioda_msis(phb); 1790184cd4a3SBenjamin Herrenschmidt 1791c40a4210SGavin Shan /* 1792c40a4210SGavin Shan * We pass the PCI probe flag PCI_REASSIGN_ALL_RSRC here 1793c40a4210SGavin Shan * to let the PCI core do resource assignment. It's supposed 1794c40a4210SGavin Shan * that the PCI core will do correct I/O and MMIO alignment 1795c40a4210SGavin Shan * for the P2P bridge bars so that each PCI bus (excluding 1796c40a4210SGavin Shan * the child P2P bridges) can form individual PE. 1797184cd4a3SBenjamin Herrenschmidt */ 1798fb446ad0SGavin Shan ppc_md.pcibios_fixup = pnv_pci_ioda_fixup; 1799184cd4a3SBenjamin Herrenschmidt ppc_md.pcibios_enable_device_hook = pnv_pci_enable_device_hook; 1800271fd03aSGavin Shan ppc_md.pcibios_window_alignment = pnv_pci_window_alignment; 1801d92a208dSGavin Shan ppc_md.pcibios_reset_secondary_bus = pnv_pci_reset_secondary_bus; 1802c40a4210SGavin Shan pci_add_flags(PCI_REASSIGN_ALL_RSRC); 1803184cd4a3SBenjamin Herrenschmidt 1804184cd4a3SBenjamin Herrenschmidt /* Reset IODA tables to a clean state */ 1805d1a85eeeSGavin Shan rc = opal_pci_reset(phb_id, OPAL_RESET_PCI_IODA_TABLE, OPAL_ASSERT_RESET); 1806184cd4a3SBenjamin Herrenschmidt if (rc) 1807f11fe552SBenjamin Herrenschmidt pr_warning(" OPAL Error %ld performing IODA table reset !\n", rc); 1808361f2a2aSGavin Shan 1809361f2a2aSGavin Shan /* If we're running in kdump kerenl, the previous kerenl never 1810361f2a2aSGavin Shan * shutdown PCI devices correctly. We already got IODA table 1811361f2a2aSGavin Shan * cleaned out. So we have to issue PHB reset to stop all PCI 1812361f2a2aSGavin Shan * transactions from previous kerenl. 1813361f2a2aSGavin Shan */ 1814361f2a2aSGavin Shan if (is_kdump_kernel()) { 1815361f2a2aSGavin Shan pr_info(" Issue PHB reset ...\n"); 1816361f2a2aSGavin Shan ioda_eeh_phb_reset(hose, EEH_RESET_FUNDAMENTAL); 1817361f2a2aSGavin Shan ioda_eeh_phb_reset(hose, OPAL_DEASSERT_RESET); 1818361f2a2aSGavin Shan } 1819262af557SGuo Chao 1820262af557SGuo Chao /* Configure M64 window */ 1821262af557SGuo Chao if (phb->init_m64 && phb->init_m64(phb)) 1822262af557SGuo Chao hose->mem_resources[1].flags = 0; 1823184cd4a3SBenjamin Herrenschmidt } 1824184cd4a3SBenjamin Herrenschmidt 182567975005SBjorn Helgaas void __init pnv_pci_init_ioda2_phb(struct device_node *np) 1826aa0c033fSGavin Shan { 1827e9cc17d4SGavin Shan pnv_pci_init_ioda_phb(np, 0, PNV_PHB_IODA2); 1828aa0c033fSGavin Shan } 1829aa0c033fSGavin Shan 1830184cd4a3SBenjamin Herrenschmidt void __init pnv_pci_init_ioda_hub(struct device_node *np) 1831184cd4a3SBenjamin Herrenschmidt { 1832184cd4a3SBenjamin Herrenschmidt struct device_node *phbn; 1833c681b93cSAlistair Popple const __be64 *prop64; 1834184cd4a3SBenjamin Herrenschmidt u64 hub_id; 1835184cd4a3SBenjamin Herrenschmidt 1836184cd4a3SBenjamin Herrenschmidt pr_info("Probing IODA IO-Hub %s\n", np->full_name); 1837184cd4a3SBenjamin Herrenschmidt 1838184cd4a3SBenjamin Herrenschmidt prop64 = of_get_property(np, "ibm,opal-hubid", NULL); 1839184cd4a3SBenjamin Herrenschmidt if (!prop64) { 1840184cd4a3SBenjamin Herrenschmidt pr_err(" Missing \"ibm,opal-hubid\" property !\n"); 1841184cd4a3SBenjamin Herrenschmidt return; 1842184cd4a3SBenjamin Herrenschmidt } 1843184cd4a3SBenjamin Herrenschmidt hub_id = be64_to_cpup(prop64); 1844184cd4a3SBenjamin Herrenschmidt pr_devel(" HUB-ID : 0x%016llx\n", hub_id); 1845184cd4a3SBenjamin Herrenschmidt 1846184cd4a3SBenjamin Herrenschmidt /* Count child PHBs */ 1847184cd4a3SBenjamin Herrenschmidt for_each_child_of_node(np, phbn) { 1848184cd4a3SBenjamin Herrenschmidt /* Look for IODA1 PHBs */ 1849184cd4a3SBenjamin Herrenschmidt if (of_device_is_compatible(phbn, "ibm,ioda-phb")) 1850e9cc17d4SGavin Shan pnv_pci_init_ioda_phb(phbn, hub_id, PNV_PHB_IODA1); 1851184cd4a3SBenjamin Herrenschmidt } 1852184cd4a3SBenjamin Herrenschmidt } 1853