1184cd4a3SBenjamin Herrenschmidt /* 2184cd4a3SBenjamin Herrenschmidt * Support PCI/PCIe on PowerNV platforms 3184cd4a3SBenjamin Herrenschmidt * 4184cd4a3SBenjamin Herrenschmidt * Copyright 2011 Benjamin Herrenschmidt, IBM Corp. 5184cd4a3SBenjamin Herrenschmidt * 6184cd4a3SBenjamin Herrenschmidt * This program is free software; you can redistribute it and/or 7184cd4a3SBenjamin Herrenschmidt * modify it under the terms of the GNU General Public License 8184cd4a3SBenjamin Herrenschmidt * as published by the Free Software Foundation; either version 9184cd4a3SBenjamin Herrenschmidt * 2 of the License, or (at your option) any later version. 10184cd4a3SBenjamin Herrenschmidt */ 11184cd4a3SBenjamin Herrenschmidt 12cee72d5bSBenjamin Herrenschmidt #undef DEBUG 13184cd4a3SBenjamin Herrenschmidt 14184cd4a3SBenjamin Herrenschmidt #include <linux/kernel.h> 15184cd4a3SBenjamin Herrenschmidt #include <linux/pci.h> 16361f2a2aSGavin Shan #include <linux/crash_dump.h> 1737c367f2SGavin Shan #include <linux/debugfs.h> 18184cd4a3SBenjamin Herrenschmidt #include <linux/delay.h> 19184cd4a3SBenjamin Herrenschmidt #include <linux/string.h> 20184cd4a3SBenjamin Herrenschmidt #include <linux/init.h> 21184cd4a3SBenjamin Herrenschmidt #include <linux/bootmem.h> 22184cd4a3SBenjamin Herrenschmidt #include <linux/irq.h> 23184cd4a3SBenjamin Herrenschmidt #include <linux/io.h> 24184cd4a3SBenjamin Herrenschmidt #include <linux/msi.h> 25cd15b048SBenjamin Herrenschmidt #include <linux/memblock.h> 26184cd4a3SBenjamin Herrenschmidt 27184cd4a3SBenjamin Herrenschmidt #include <asm/sections.h> 28184cd4a3SBenjamin Herrenschmidt #include <asm/io.h> 29184cd4a3SBenjamin Herrenschmidt #include <asm/prom.h> 30184cd4a3SBenjamin Herrenschmidt #include <asm/pci-bridge.h> 31184cd4a3SBenjamin Herrenschmidt #include <asm/machdep.h> 32fb1b55d6SGavin Shan #include <asm/msi_bitmap.h> 33184cd4a3SBenjamin Herrenschmidt #include <asm/ppc-pci.h> 34184cd4a3SBenjamin Herrenschmidt #include <asm/opal.h> 35184cd4a3SBenjamin Herrenschmidt #include <asm/iommu.h> 36184cd4a3SBenjamin Herrenschmidt #include <asm/tce.h> 37137436c9SGavin Shan #include <asm/xics.h> 3837c367f2SGavin Shan #include <asm/debug.h> 39262af557SGuo Chao #include <asm/firmware.h> 4080c49c7eSIan Munsie #include <asm/pnv-pci.h> 4180c49c7eSIan Munsie 4280c49c7eSIan Munsie #include <misc/cxl.h> 43184cd4a3SBenjamin Herrenschmidt 44184cd4a3SBenjamin Herrenschmidt #include "powernv.h" 45184cd4a3SBenjamin Herrenschmidt #include "pci.h" 46184cd4a3SBenjamin Herrenschmidt 476d31c2faSJoe Perches static void pe_level_printk(const struct pnv_ioda_pe *pe, const char *level, 486d31c2faSJoe Perches const char *fmt, ...) 496d31c2faSJoe Perches { 506d31c2faSJoe Perches struct va_format vaf; 516d31c2faSJoe Perches va_list args; 526d31c2faSJoe Perches char pfix[32]; 53184cd4a3SBenjamin Herrenschmidt 546d31c2faSJoe Perches va_start(args, fmt); 556d31c2faSJoe Perches 566d31c2faSJoe Perches vaf.fmt = fmt; 576d31c2faSJoe Perches vaf.va = &args; 586d31c2faSJoe Perches 596d31c2faSJoe Perches if (pe->pdev) 606d31c2faSJoe Perches strlcpy(pfix, dev_name(&pe->pdev->dev), sizeof(pfix)); 616d31c2faSJoe Perches else 626d31c2faSJoe Perches sprintf(pfix, "%04x:%02x ", 636d31c2faSJoe Perches pci_domain_nr(pe->pbus), pe->pbus->number); 646d31c2faSJoe Perches 656d31c2faSJoe Perches printk("%spci %s: [PE# %.3d] %pV", 666d31c2faSJoe Perches level, pfix, pe->pe_number, &vaf); 676d31c2faSJoe Perches 686d31c2faSJoe Perches va_end(args); 696d31c2faSJoe Perches } 706d31c2faSJoe Perches 716d31c2faSJoe Perches #define pe_err(pe, fmt, ...) \ 726d31c2faSJoe Perches pe_level_printk(pe, KERN_ERR, fmt, ##__VA_ARGS__) 736d31c2faSJoe Perches #define pe_warn(pe, fmt, ...) \ 746d31c2faSJoe Perches pe_level_printk(pe, KERN_WARNING, fmt, ##__VA_ARGS__) 756d31c2faSJoe Perches #define pe_info(pe, fmt, ...) \ 766d31c2faSJoe Perches pe_level_printk(pe, KERN_INFO, fmt, ##__VA_ARGS__) 77184cd4a3SBenjamin Herrenschmidt 784e287840SThadeu Lima de Souza Cascardo static bool pnv_iommu_bypass_disabled __read_mostly; 794e287840SThadeu Lima de Souza Cascardo 804e287840SThadeu Lima de Souza Cascardo static int __init iommu_setup(char *str) 814e287840SThadeu Lima de Souza Cascardo { 824e287840SThadeu Lima de Souza Cascardo if (!str) 834e287840SThadeu Lima de Souza Cascardo return -EINVAL; 844e287840SThadeu Lima de Souza Cascardo 854e287840SThadeu Lima de Souza Cascardo while (*str) { 864e287840SThadeu Lima de Souza Cascardo if (!strncmp(str, "nobypass", 8)) { 874e287840SThadeu Lima de Souza Cascardo pnv_iommu_bypass_disabled = true; 884e287840SThadeu Lima de Souza Cascardo pr_info("PowerNV: IOMMU bypass window disabled.\n"); 894e287840SThadeu Lima de Souza Cascardo break; 904e287840SThadeu Lima de Souza Cascardo } 914e287840SThadeu Lima de Souza Cascardo str += strcspn(str, ","); 924e287840SThadeu Lima de Souza Cascardo if (*str == ',') 934e287840SThadeu Lima de Souza Cascardo str++; 944e287840SThadeu Lima de Souza Cascardo } 954e287840SThadeu Lima de Souza Cascardo 964e287840SThadeu Lima de Souza Cascardo return 0; 974e287840SThadeu Lima de Souza Cascardo } 984e287840SThadeu Lima de Souza Cascardo early_param("iommu", iommu_setup); 994e287840SThadeu Lima de Souza Cascardo 1008e0a1611SAlexey Kardashevskiy /* 1018e0a1611SAlexey Kardashevskiy * stdcix is only supposed to be used in hypervisor real mode as per 1028e0a1611SAlexey Kardashevskiy * the architecture spec 1038e0a1611SAlexey Kardashevskiy */ 1048e0a1611SAlexey Kardashevskiy static inline void __raw_rm_writeq(u64 val, volatile void __iomem *paddr) 1058e0a1611SAlexey Kardashevskiy { 1068e0a1611SAlexey Kardashevskiy __asm__ __volatile__("stdcix %0,0,%1" 1078e0a1611SAlexey Kardashevskiy : : "r" (val), "r" (paddr) : "memory"); 1088e0a1611SAlexey Kardashevskiy } 1098e0a1611SAlexey Kardashevskiy 110262af557SGuo Chao static inline bool pnv_pci_is_mem_pref_64(unsigned long flags) 111262af557SGuo Chao { 112262af557SGuo Chao return ((flags & (IORESOURCE_MEM_64 | IORESOURCE_PREFETCH)) == 113262af557SGuo Chao (IORESOURCE_MEM_64 | IORESOURCE_PREFETCH)); 114262af557SGuo Chao } 115262af557SGuo Chao 1164b82ab18SGavin Shan static void pnv_ioda_reserve_pe(struct pnv_phb *phb, int pe_no) 1174b82ab18SGavin Shan { 1184b82ab18SGavin Shan if (!(pe_no >= 0 && pe_no < phb->ioda.total_pe)) { 1194b82ab18SGavin Shan pr_warn("%s: Invalid PE %d on PHB#%x\n", 1204b82ab18SGavin Shan __func__, pe_no, phb->hose->global_number); 1214b82ab18SGavin Shan return; 1224b82ab18SGavin Shan } 1234b82ab18SGavin Shan 1244b82ab18SGavin Shan if (test_and_set_bit(pe_no, phb->ioda.pe_alloc)) { 1254b82ab18SGavin Shan pr_warn("%s: PE %d was assigned on PHB#%x\n", 1264b82ab18SGavin Shan __func__, pe_no, phb->hose->global_number); 1274b82ab18SGavin Shan return; 1284b82ab18SGavin Shan } 1294b82ab18SGavin Shan 1304b82ab18SGavin Shan phb->ioda.pe_array[pe_no].phb = phb; 1314b82ab18SGavin Shan phb->ioda.pe_array[pe_no].pe_number = pe_no; 1324b82ab18SGavin Shan } 1334b82ab18SGavin Shan 134cad5cef6SGreg Kroah-Hartman static int pnv_ioda_alloc_pe(struct pnv_phb *phb) 135184cd4a3SBenjamin Herrenschmidt { 136184cd4a3SBenjamin Herrenschmidt unsigned long pe; 137184cd4a3SBenjamin Herrenschmidt 138184cd4a3SBenjamin Herrenschmidt do { 139184cd4a3SBenjamin Herrenschmidt pe = find_next_zero_bit(phb->ioda.pe_alloc, 140184cd4a3SBenjamin Herrenschmidt phb->ioda.total_pe, 0); 141184cd4a3SBenjamin Herrenschmidt if (pe >= phb->ioda.total_pe) 142184cd4a3SBenjamin Herrenschmidt return IODA_INVALID_PE; 143184cd4a3SBenjamin Herrenschmidt } while(test_and_set_bit(pe, phb->ioda.pe_alloc)); 144184cd4a3SBenjamin Herrenschmidt 1454cce9550SGavin Shan phb->ioda.pe_array[pe].phb = phb; 146184cd4a3SBenjamin Herrenschmidt phb->ioda.pe_array[pe].pe_number = pe; 147184cd4a3SBenjamin Herrenschmidt return pe; 148184cd4a3SBenjamin Herrenschmidt } 149184cd4a3SBenjamin Herrenschmidt 150cad5cef6SGreg Kroah-Hartman static void pnv_ioda_free_pe(struct pnv_phb *phb, int pe) 151184cd4a3SBenjamin Herrenschmidt { 152184cd4a3SBenjamin Herrenschmidt WARN_ON(phb->ioda.pe_array[pe].pdev); 153184cd4a3SBenjamin Herrenschmidt 154184cd4a3SBenjamin Herrenschmidt memset(&phb->ioda.pe_array[pe], 0, sizeof(struct pnv_ioda_pe)); 155184cd4a3SBenjamin Herrenschmidt clear_bit(pe, phb->ioda.pe_alloc); 156184cd4a3SBenjamin Herrenschmidt } 157184cd4a3SBenjamin Herrenschmidt 158262af557SGuo Chao /* The default M64 BAR is shared by all PEs */ 159262af557SGuo Chao static int pnv_ioda2_init_m64(struct pnv_phb *phb) 160262af557SGuo Chao { 161262af557SGuo Chao const char *desc; 162262af557SGuo Chao struct resource *r; 163262af557SGuo Chao s64 rc; 164262af557SGuo Chao 165262af557SGuo Chao /* Configure the default M64 BAR */ 166262af557SGuo Chao rc = opal_pci_set_phb_mem_window(phb->opal_id, 167262af557SGuo Chao OPAL_M64_WINDOW_TYPE, 168262af557SGuo Chao phb->ioda.m64_bar_idx, 169262af557SGuo Chao phb->ioda.m64_base, 170262af557SGuo Chao 0, /* unused */ 171262af557SGuo Chao phb->ioda.m64_size); 172262af557SGuo Chao if (rc != OPAL_SUCCESS) { 173262af557SGuo Chao desc = "configuring"; 174262af557SGuo Chao goto fail; 175262af557SGuo Chao } 176262af557SGuo Chao 177262af557SGuo Chao /* Enable the default M64 BAR */ 178262af557SGuo Chao rc = opal_pci_phb_mmio_enable(phb->opal_id, 179262af557SGuo Chao OPAL_M64_WINDOW_TYPE, 180262af557SGuo Chao phb->ioda.m64_bar_idx, 181262af557SGuo Chao OPAL_ENABLE_M64_SPLIT); 182262af557SGuo Chao if (rc != OPAL_SUCCESS) { 183262af557SGuo Chao desc = "enabling"; 184262af557SGuo Chao goto fail; 185262af557SGuo Chao } 186262af557SGuo Chao 187262af557SGuo Chao /* Mark the M64 BAR assigned */ 188262af557SGuo Chao set_bit(phb->ioda.m64_bar_idx, &phb->ioda.m64_bar_alloc); 189262af557SGuo Chao 190262af557SGuo Chao /* 191262af557SGuo Chao * Strip off the segment used by the reserved PE, which is 192262af557SGuo Chao * expected to be 0 or last one of PE capabicity. 193262af557SGuo Chao */ 194262af557SGuo Chao r = &phb->hose->mem_resources[1]; 195262af557SGuo Chao if (phb->ioda.reserved_pe == 0) 196262af557SGuo Chao r->start += phb->ioda.m64_segsize; 197262af557SGuo Chao else if (phb->ioda.reserved_pe == (phb->ioda.total_pe - 1)) 198262af557SGuo Chao r->end -= phb->ioda.m64_segsize; 199262af557SGuo Chao else 200262af557SGuo Chao pr_warn(" Cannot strip M64 segment for reserved PE#%d\n", 201262af557SGuo Chao phb->ioda.reserved_pe); 202262af557SGuo Chao 203262af557SGuo Chao return 0; 204262af557SGuo Chao 205262af557SGuo Chao fail: 206262af557SGuo Chao pr_warn(" Failure %lld %s M64 BAR#%d\n", 207262af557SGuo Chao rc, desc, phb->ioda.m64_bar_idx); 208262af557SGuo Chao opal_pci_phb_mmio_enable(phb->opal_id, 209262af557SGuo Chao OPAL_M64_WINDOW_TYPE, 210262af557SGuo Chao phb->ioda.m64_bar_idx, 211262af557SGuo Chao OPAL_DISABLE_M64); 212262af557SGuo Chao return -EIO; 213262af557SGuo Chao } 214262af557SGuo Chao 2155ef73567SGavin Shan static void pnv_ioda2_reserve_m64_pe(struct pnv_phb *phb) 216262af557SGuo Chao { 217262af557SGuo Chao resource_size_t sgsz = phb->ioda.m64_segsize; 218262af557SGuo Chao struct pci_dev *pdev; 219262af557SGuo Chao struct resource *r; 220262af557SGuo Chao int base, step, i; 221262af557SGuo Chao 222262af557SGuo Chao /* 223262af557SGuo Chao * Root bus always has full M64 range and root port has 224262af557SGuo Chao * M64 range used in reality. So we're checking root port 225262af557SGuo Chao * instead of root bus. 226262af557SGuo Chao */ 227262af557SGuo Chao list_for_each_entry(pdev, &phb->hose->bus->devices, bus_list) { 2284b82ab18SGavin Shan for (i = 0; i < PCI_BRIDGE_RESOURCE_NUM; i++) { 2294b82ab18SGavin Shan r = &pdev->resource[PCI_BRIDGE_RESOURCES + i]; 230262af557SGuo Chao if (!r->parent || 231262af557SGuo Chao !pnv_pci_is_mem_pref_64(r->flags)) 232262af557SGuo Chao continue; 233262af557SGuo Chao 234262af557SGuo Chao base = (r->start - phb->ioda.m64_base) / sgsz; 235262af557SGuo Chao for (step = 0; step < resource_size(r) / sgsz; step++) 2364b82ab18SGavin Shan pnv_ioda_reserve_pe(phb, base + step); 237262af557SGuo Chao } 238262af557SGuo Chao } 239262af557SGuo Chao } 240262af557SGuo Chao 241262af557SGuo Chao static int pnv_ioda2_pick_m64_pe(struct pnv_phb *phb, 242262af557SGuo Chao struct pci_bus *bus, int all) 243262af557SGuo Chao { 244262af557SGuo Chao resource_size_t segsz = phb->ioda.m64_segsize; 245262af557SGuo Chao struct pci_dev *pdev; 246262af557SGuo Chao struct resource *r; 247262af557SGuo Chao struct pnv_ioda_pe *master_pe, *pe; 248262af557SGuo Chao unsigned long size, *pe_alloc; 249262af557SGuo Chao bool found; 250262af557SGuo Chao int start, i, j; 251262af557SGuo Chao 252262af557SGuo Chao /* Root bus shouldn't use M64 */ 253262af557SGuo Chao if (pci_is_root_bus(bus)) 254262af557SGuo Chao return IODA_INVALID_PE; 255262af557SGuo Chao 256262af557SGuo Chao /* We support only one M64 window on each bus */ 257262af557SGuo Chao found = false; 258262af557SGuo Chao pci_bus_for_each_resource(bus, r, i) { 259262af557SGuo Chao if (r && r->parent && 260262af557SGuo Chao pnv_pci_is_mem_pref_64(r->flags)) { 261262af557SGuo Chao found = true; 262262af557SGuo Chao break; 263262af557SGuo Chao } 264262af557SGuo Chao } 265262af557SGuo Chao 266262af557SGuo Chao /* No M64 window found ? */ 267262af557SGuo Chao if (!found) 268262af557SGuo Chao return IODA_INVALID_PE; 269262af557SGuo Chao 270262af557SGuo Chao /* Allocate bitmap */ 271262af557SGuo Chao size = _ALIGN_UP(phb->ioda.total_pe / 8, sizeof(unsigned long)); 272262af557SGuo Chao pe_alloc = kzalloc(size, GFP_KERNEL); 273262af557SGuo Chao if (!pe_alloc) { 274262af557SGuo Chao pr_warn("%s: Out of memory !\n", 275262af557SGuo Chao __func__); 276262af557SGuo Chao return IODA_INVALID_PE; 277262af557SGuo Chao } 278262af557SGuo Chao 279262af557SGuo Chao /* 280262af557SGuo Chao * Figure out reserved PE numbers by the PE 281262af557SGuo Chao * the its child PEs. 282262af557SGuo Chao */ 283262af557SGuo Chao start = (r->start - phb->ioda.m64_base) / segsz; 284262af557SGuo Chao for (i = 0; i < resource_size(r) / segsz; i++) 285262af557SGuo Chao set_bit(start + i, pe_alloc); 286262af557SGuo Chao 287262af557SGuo Chao if (all) 288262af557SGuo Chao goto done; 289262af557SGuo Chao 290262af557SGuo Chao /* 291262af557SGuo Chao * If the PE doesn't cover all subordinate buses, 292262af557SGuo Chao * we need subtract from reserved PEs for children. 293262af557SGuo Chao */ 294262af557SGuo Chao list_for_each_entry(pdev, &bus->devices, bus_list) { 295262af557SGuo Chao if (!pdev->subordinate) 296262af557SGuo Chao continue; 297262af557SGuo Chao 298262af557SGuo Chao pci_bus_for_each_resource(pdev->subordinate, r, i) { 299262af557SGuo Chao if (!r || !r->parent || 300262af557SGuo Chao !pnv_pci_is_mem_pref_64(r->flags)) 301262af557SGuo Chao continue; 302262af557SGuo Chao 303262af557SGuo Chao start = (r->start - phb->ioda.m64_base) / segsz; 304262af557SGuo Chao for (j = 0; j < resource_size(r) / segsz ; j++) 305262af557SGuo Chao clear_bit(start + j, pe_alloc); 306262af557SGuo Chao } 307262af557SGuo Chao } 308262af557SGuo Chao 309262af557SGuo Chao /* 310262af557SGuo Chao * the current bus might not own M64 window and that's all 311262af557SGuo Chao * contributed by its child buses. For the case, we needn't 312262af557SGuo Chao * pick M64 dependent PE#. 313262af557SGuo Chao */ 314262af557SGuo Chao if (bitmap_empty(pe_alloc, phb->ioda.total_pe)) { 315262af557SGuo Chao kfree(pe_alloc); 316262af557SGuo Chao return IODA_INVALID_PE; 317262af557SGuo Chao } 318262af557SGuo Chao 319262af557SGuo Chao /* 320262af557SGuo Chao * Figure out the master PE and put all slave PEs to master 321262af557SGuo Chao * PE's list to form compound PE. 322262af557SGuo Chao */ 323262af557SGuo Chao done: 324262af557SGuo Chao master_pe = NULL; 325262af557SGuo Chao i = -1; 326262af557SGuo Chao while ((i = find_next_bit(pe_alloc, phb->ioda.total_pe, i + 1)) < 327262af557SGuo Chao phb->ioda.total_pe) { 328262af557SGuo Chao pe = &phb->ioda.pe_array[i]; 329262af557SGuo Chao 330262af557SGuo Chao if (!master_pe) { 331262af557SGuo Chao pe->flags |= PNV_IODA_PE_MASTER; 332262af557SGuo Chao INIT_LIST_HEAD(&pe->slaves); 333262af557SGuo Chao master_pe = pe; 334262af557SGuo Chao } else { 335262af557SGuo Chao pe->flags |= PNV_IODA_PE_SLAVE; 336262af557SGuo Chao pe->master = master_pe; 337262af557SGuo Chao list_add_tail(&pe->list, &master_pe->slaves); 338262af557SGuo Chao } 339262af557SGuo Chao } 340262af557SGuo Chao 341262af557SGuo Chao kfree(pe_alloc); 342262af557SGuo Chao return master_pe->pe_number; 343262af557SGuo Chao } 344262af557SGuo Chao 345262af557SGuo Chao static void __init pnv_ioda_parse_m64_window(struct pnv_phb *phb) 346262af557SGuo Chao { 347262af557SGuo Chao struct pci_controller *hose = phb->hose; 348262af557SGuo Chao struct device_node *dn = hose->dn; 349262af557SGuo Chao struct resource *res; 350262af557SGuo Chao const u32 *r; 351262af557SGuo Chao u64 pci_addr; 352262af557SGuo Chao 3531665c4a8SGavin Shan /* FIXME: Support M64 for P7IOC */ 3541665c4a8SGavin Shan if (phb->type != PNV_PHB_IODA2) { 3551665c4a8SGavin Shan pr_info(" Not support M64 window\n"); 3561665c4a8SGavin Shan return; 3571665c4a8SGavin Shan } 3581665c4a8SGavin Shan 359262af557SGuo Chao if (!firmware_has_feature(FW_FEATURE_OPALv3)) { 360262af557SGuo Chao pr_info(" Firmware too old to support M64 window\n"); 361262af557SGuo Chao return; 362262af557SGuo Chao } 363262af557SGuo Chao 364262af557SGuo Chao r = of_get_property(dn, "ibm,opal-m64-window", NULL); 365262af557SGuo Chao if (!r) { 366262af557SGuo Chao pr_info(" No <ibm,opal-m64-window> on %s\n", 367262af557SGuo Chao dn->full_name); 368262af557SGuo Chao return; 369262af557SGuo Chao } 370262af557SGuo Chao 371262af557SGuo Chao res = &hose->mem_resources[1]; 372262af557SGuo Chao res->start = of_translate_address(dn, r + 2); 373262af557SGuo Chao res->end = res->start + of_read_number(r + 4, 2) - 1; 374262af557SGuo Chao res->flags = (IORESOURCE_MEM | IORESOURCE_MEM_64 | IORESOURCE_PREFETCH); 375262af557SGuo Chao pci_addr = of_read_number(r, 2); 376262af557SGuo Chao hose->mem_offset[1] = res->start - pci_addr; 377262af557SGuo Chao 378262af557SGuo Chao phb->ioda.m64_size = resource_size(res); 379262af557SGuo Chao phb->ioda.m64_segsize = phb->ioda.m64_size / phb->ioda.total_pe; 380262af557SGuo Chao phb->ioda.m64_base = pci_addr; 381262af557SGuo Chao 382e9863e68SWei Yang pr_info(" MEM64 0x%016llx..0x%016llx -> 0x%016llx\n", 383e9863e68SWei Yang res->start, res->end, pci_addr); 384e9863e68SWei Yang 385262af557SGuo Chao /* Use last M64 BAR to cover M64 window */ 386262af557SGuo Chao phb->ioda.m64_bar_idx = 15; 387262af557SGuo Chao phb->init_m64 = pnv_ioda2_init_m64; 3885ef73567SGavin Shan phb->reserve_m64_pe = pnv_ioda2_reserve_m64_pe; 389262af557SGuo Chao phb->pick_m64_pe = pnv_ioda2_pick_m64_pe; 390262af557SGuo Chao } 391262af557SGuo Chao 39249dec922SGavin Shan static void pnv_ioda_freeze_pe(struct pnv_phb *phb, int pe_no) 39349dec922SGavin Shan { 39449dec922SGavin Shan struct pnv_ioda_pe *pe = &phb->ioda.pe_array[pe_no]; 39549dec922SGavin Shan struct pnv_ioda_pe *slave; 39649dec922SGavin Shan s64 rc; 39749dec922SGavin Shan 39849dec922SGavin Shan /* Fetch master PE */ 39949dec922SGavin Shan if (pe->flags & PNV_IODA_PE_SLAVE) { 40049dec922SGavin Shan pe = pe->master; 401ec8e4e9dSGavin Shan if (WARN_ON(!pe || !(pe->flags & PNV_IODA_PE_MASTER))) 402ec8e4e9dSGavin Shan return; 403ec8e4e9dSGavin Shan 40449dec922SGavin Shan pe_no = pe->pe_number; 40549dec922SGavin Shan } 40649dec922SGavin Shan 40749dec922SGavin Shan /* Freeze master PE */ 40849dec922SGavin Shan rc = opal_pci_eeh_freeze_set(phb->opal_id, 40949dec922SGavin Shan pe_no, 41049dec922SGavin Shan OPAL_EEH_ACTION_SET_FREEZE_ALL); 41149dec922SGavin Shan if (rc != OPAL_SUCCESS) { 41249dec922SGavin Shan pr_warn("%s: Failure %lld freezing PHB#%x-PE#%x\n", 41349dec922SGavin Shan __func__, rc, phb->hose->global_number, pe_no); 41449dec922SGavin Shan return; 41549dec922SGavin Shan } 41649dec922SGavin Shan 41749dec922SGavin Shan /* Freeze slave PEs */ 41849dec922SGavin Shan if (!(pe->flags & PNV_IODA_PE_MASTER)) 41949dec922SGavin Shan return; 42049dec922SGavin Shan 42149dec922SGavin Shan list_for_each_entry(slave, &pe->slaves, list) { 42249dec922SGavin Shan rc = opal_pci_eeh_freeze_set(phb->opal_id, 42349dec922SGavin Shan slave->pe_number, 42449dec922SGavin Shan OPAL_EEH_ACTION_SET_FREEZE_ALL); 42549dec922SGavin Shan if (rc != OPAL_SUCCESS) 42649dec922SGavin Shan pr_warn("%s: Failure %lld freezing PHB#%x-PE#%x\n", 42749dec922SGavin Shan __func__, rc, phb->hose->global_number, 42849dec922SGavin Shan slave->pe_number); 42949dec922SGavin Shan } 43049dec922SGavin Shan } 43149dec922SGavin Shan 432e51df2c1SAnton Blanchard static int pnv_ioda_unfreeze_pe(struct pnv_phb *phb, int pe_no, int opt) 43349dec922SGavin Shan { 43449dec922SGavin Shan struct pnv_ioda_pe *pe, *slave; 43549dec922SGavin Shan s64 rc; 43649dec922SGavin Shan 43749dec922SGavin Shan /* Find master PE */ 43849dec922SGavin Shan pe = &phb->ioda.pe_array[pe_no]; 43949dec922SGavin Shan if (pe->flags & PNV_IODA_PE_SLAVE) { 44049dec922SGavin Shan pe = pe->master; 44149dec922SGavin Shan WARN_ON(!pe || !(pe->flags & PNV_IODA_PE_MASTER)); 44249dec922SGavin Shan pe_no = pe->pe_number; 44349dec922SGavin Shan } 44449dec922SGavin Shan 44549dec922SGavin Shan /* Clear frozen state for master PE */ 44649dec922SGavin Shan rc = opal_pci_eeh_freeze_clear(phb->opal_id, pe_no, opt); 44749dec922SGavin Shan if (rc != OPAL_SUCCESS) { 44849dec922SGavin Shan pr_warn("%s: Failure %lld clear %d on PHB#%x-PE#%x\n", 44949dec922SGavin Shan __func__, rc, opt, phb->hose->global_number, pe_no); 45049dec922SGavin Shan return -EIO; 45149dec922SGavin Shan } 45249dec922SGavin Shan 45349dec922SGavin Shan if (!(pe->flags & PNV_IODA_PE_MASTER)) 45449dec922SGavin Shan return 0; 45549dec922SGavin Shan 45649dec922SGavin Shan /* Clear frozen state for slave PEs */ 45749dec922SGavin Shan list_for_each_entry(slave, &pe->slaves, list) { 45849dec922SGavin Shan rc = opal_pci_eeh_freeze_clear(phb->opal_id, 45949dec922SGavin Shan slave->pe_number, 46049dec922SGavin Shan opt); 46149dec922SGavin Shan if (rc != OPAL_SUCCESS) { 46249dec922SGavin Shan pr_warn("%s: Failure %lld clear %d on PHB#%x-PE#%x\n", 46349dec922SGavin Shan __func__, rc, opt, phb->hose->global_number, 46449dec922SGavin Shan slave->pe_number); 46549dec922SGavin Shan return -EIO; 46649dec922SGavin Shan } 46749dec922SGavin Shan } 46849dec922SGavin Shan 46949dec922SGavin Shan return 0; 47049dec922SGavin Shan } 47149dec922SGavin Shan 47249dec922SGavin Shan static int pnv_ioda_get_pe_state(struct pnv_phb *phb, int pe_no) 47349dec922SGavin Shan { 47449dec922SGavin Shan struct pnv_ioda_pe *slave, *pe; 47549dec922SGavin Shan u8 fstate, state; 47649dec922SGavin Shan __be16 pcierr; 47749dec922SGavin Shan s64 rc; 47849dec922SGavin Shan 47949dec922SGavin Shan /* Sanity check on PE number */ 48049dec922SGavin Shan if (pe_no < 0 || pe_no >= phb->ioda.total_pe) 48149dec922SGavin Shan return OPAL_EEH_STOPPED_PERM_UNAVAIL; 48249dec922SGavin Shan 48349dec922SGavin Shan /* 48449dec922SGavin Shan * Fetch the master PE and the PE instance might be 48549dec922SGavin Shan * not initialized yet. 48649dec922SGavin Shan */ 48749dec922SGavin Shan pe = &phb->ioda.pe_array[pe_no]; 48849dec922SGavin Shan if (pe->flags & PNV_IODA_PE_SLAVE) { 48949dec922SGavin Shan pe = pe->master; 49049dec922SGavin Shan WARN_ON(!pe || !(pe->flags & PNV_IODA_PE_MASTER)); 49149dec922SGavin Shan pe_no = pe->pe_number; 49249dec922SGavin Shan } 49349dec922SGavin Shan 49449dec922SGavin Shan /* Check the master PE */ 49549dec922SGavin Shan rc = opal_pci_eeh_freeze_status(phb->opal_id, pe_no, 49649dec922SGavin Shan &state, &pcierr, NULL); 49749dec922SGavin Shan if (rc != OPAL_SUCCESS) { 49849dec922SGavin Shan pr_warn("%s: Failure %lld getting " 49949dec922SGavin Shan "PHB#%x-PE#%x state\n", 50049dec922SGavin Shan __func__, rc, 50149dec922SGavin Shan phb->hose->global_number, pe_no); 50249dec922SGavin Shan return OPAL_EEH_STOPPED_TEMP_UNAVAIL; 50349dec922SGavin Shan } 50449dec922SGavin Shan 50549dec922SGavin Shan /* Check the slave PE */ 50649dec922SGavin Shan if (!(pe->flags & PNV_IODA_PE_MASTER)) 50749dec922SGavin Shan return state; 50849dec922SGavin Shan 50949dec922SGavin Shan list_for_each_entry(slave, &pe->slaves, list) { 51049dec922SGavin Shan rc = opal_pci_eeh_freeze_status(phb->opal_id, 51149dec922SGavin Shan slave->pe_number, 51249dec922SGavin Shan &fstate, 51349dec922SGavin Shan &pcierr, 51449dec922SGavin Shan NULL); 51549dec922SGavin Shan if (rc != OPAL_SUCCESS) { 51649dec922SGavin Shan pr_warn("%s: Failure %lld getting " 51749dec922SGavin Shan "PHB#%x-PE#%x state\n", 51849dec922SGavin Shan __func__, rc, 51949dec922SGavin Shan phb->hose->global_number, slave->pe_number); 52049dec922SGavin Shan return OPAL_EEH_STOPPED_TEMP_UNAVAIL; 52149dec922SGavin Shan } 52249dec922SGavin Shan 52349dec922SGavin Shan /* 52449dec922SGavin Shan * Override the result based on the ascending 52549dec922SGavin Shan * priority. 52649dec922SGavin Shan */ 52749dec922SGavin Shan if (fstate > state) 52849dec922SGavin Shan state = fstate; 52949dec922SGavin Shan } 53049dec922SGavin Shan 53149dec922SGavin Shan return state; 53249dec922SGavin Shan } 53349dec922SGavin Shan 534184cd4a3SBenjamin Herrenschmidt /* Currently those 2 are only used when MSIs are enabled, this will change 535184cd4a3SBenjamin Herrenschmidt * but in the meantime, we need to protect them to avoid warnings 536184cd4a3SBenjamin Herrenschmidt */ 537184cd4a3SBenjamin Herrenschmidt #ifdef CONFIG_PCI_MSI 538cad5cef6SGreg Kroah-Hartman static struct pnv_ioda_pe *pnv_ioda_get_pe(struct pci_dev *dev) 539184cd4a3SBenjamin Herrenschmidt { 540184cd4a3SBenjamin Herrenschmidt struct pci_controller *hose = pci_bus_to_host(dev->bus); 541184cd4a3SBenjamin Herrenschmidt struct pnv_phb *phb = hose->private_data; 542b72c1f65SBenjamin Herrenschmidt struct pci_dn *pdn = pci_get_pdn(dev); 543184cd4a3SBenjamin Herrenschmidt 544184cd4a3SBenjamin Herrenschmidt if (!pdn) 545184cd4a3SBenjamin Herrenschmidt return NULL; 546184cd4a3SBenjamin Herrenschmidt if (pdn->pe_number == IODA_INVALID_PE) 547184cd4a3SBenjamin Herrenschmidt return NULL; 548184cd4a3SBenjamin Herrenschmidt return &phb->ioda.pe_array[pdn->pe_number]; 549184cd4a3SBenjamin Herrenschmidt } 550184cd4a3SBenjamin Herrenschmidt #endif /* CONFIG_PCI_MSI */ 551184cd4a3SBenjamin Herrenschmidt 552b131a842SGavin Shan static int pnv_ioda_set_one_peltv(struct pnv_phb *phb, 553b131a842SGavin Shan struct pnv_ioda_pe *parent, 554b131a842SGavin Shan struct pnv_ioda_pe *child, 555b131a842SGavin Shan bool is_add) 556b131a842SGavin Shan { 557b131a842SGavin Shan const char *desc = is_add ? "adding" : "removing"; 558b131a842SGavin Shan uint8_t op = is_add ? OPAL_ADD_PE_TO_DOMAIN : 559b131a842SGavin Shan OPAL_REMOVE_PE_FROM_DOMAIN; 560b131a842SGavin Shan struct pnv_ioda_pe *slave; 561b131a842SGavin Shan long rc; 562b131a842SGavin Shan 563b131a842SGavin Shan /* Parent PE affects child PE */ 564b131a842SGavin Shan rc = opal_pci_set_peltv(phb->opal_id, parent->pe_number, 565b131a842SGavin Shan child->pe_number, op); 566b131a842SGavin Shan if (rc != OPAL_SUCCESS) { 567b131a842SGavin Shan pe_warn(child, "OPAL error %ld %s to parent PELTV\n", 568b131a842SGavin Shan rc, desc); 569b131a842SGavin Shan return -ENXIO; 570b131a842SGavin Shan } 571b131a842SGavin Shan 572b131a842SGavin Shan if (!(child->flags & PNV_IODA_PE_MASTER)) 573b131a842SGavin Shan return 0; 574b131a842SGavin Shan 575b131a842SGavin Shan /* Compound case: parent PE affects slave PEs */ 576b131a842SGavin Shan list_for_each_entry(slave, &child->slaves, list) { 577b131a842SGavin Shan rc = opal_pci_set_peltv(phb->opal_id, parent->pe_number, 578b131a842SGavin Shan slave->pe_number, op); 579b131a842SGavin Shan if (rc != OPAL_SUCCESS) { 580b131a842SGavin Shan pe_warn(slave, "OPAL error %ld %s to parent PELTV\n", 581b131a842SGavin Shan rc, desc); 582b131a842SGavin Shan return -ENXIO; 583b131a842SGavin Shan } 584b131a842SGavin Shan } 585b131a842SGavin Shan 586b131a842SGavin Shan return 0; 587b131a842SGavin Shan } 588b131a842SGavin Shan 589b131a842SGavin Shan static int pnv_ioda_set_peltv(struct pnv_phb *phb, 590b131a842SGavin Shan struct pnv_ioda_pe *pe, 591b131a842SGavin Shan bool is_add) 592b131a842SGavin Shan { 593b131a842SGavin Shan struct pnv_ioda_pe *slave; 594b131a842SGavin Shan struct pci_dev *pdev; 595b131a842SGavin Shan int ret; 596b131a842SGavin Shan 597b131a842SGavin Shan /* 598b131a842SGavin Shan * Clear PE frozen state. If it's master PE, we need 599b131a842SGavin Shan * clear slave PE frozen state as well. 600b131a842SGavin Shan */ 601b131a842SGavin Shan if (is_add) { 602b131a842SGavin Shan opal_pci_eeh_freeze_clear(phb->opal_id, pe->pe_number, 603b131a842SGavin Shan OPAL_EEH_ACTION_CLEAR_FREEZE_ALL); 604b131a842SGavin Shan if (pe->flags & PNV_IODA_PE_MASTER) { 605b131a842SGavin Shan list_for_each_entry(slave, &pe->slaves, list) 606b131a842SGavin Shan opal_pci_eeh_freeze_clear(phb->opal_id, 607b131a842SGavin Shan slave->pe_number, 608b131a842SGavin Shan OPAL_EEH_ACTION_CLEAR_FREEZE_ALL); 609b131a842SGavin Shan } 610b131a842SGavin Shan } 611b131a842SGavin Shan 612b131a842SGavin Shan /* 613b131a842SGavin Shan * Associate PE in PELT. We need add the PE into the 614b131a842SGavin Shan * corresponding PELT-V as well. Otherwise, the error 615b131a842SGavin Shan * originated from the PE might contribute to other 616b131a842SGavin Shan * PEs. 617b131a842SGavin Shan */ 618b131a842SGavin Shan ret = pnv_ioda_set_one_peltv(phb, pe, pe, is_add); 619b131a842SGavin Shan if (ret) 620b131a842SGavin Shan return ret; 621b131a842SGavin Shan 622b131a842SGavin Shan /* For compound PEs, any one affects all of them */ 623b131a842SGavin Shan if (pe->flags & PNV_IODA_PE_MASTER) { 624b131a842SGavin Shan list_for_each_entry(slave, &pe->slaves, list) { 625b131a842SGavin Shan ret = pnv_ioda_set_one_peltv(phb, slave, pe, is_add); 626b131a842SGavin Shan if (ret) 627b131a842SGavin Shan return ret; 628b131a842SGavin Shan } 629b131a842SGavin Shan } 630b131a842SGavin Shan 631b131a842SGavin Shan if (pe->flags & (PNV_IODA_PE_BUS_ALL | PNV_IODA_PE_BUS)) 632b131a842SGavin Shan pdev = pe->pbus->self; 633b131a842SGavin Shan else 634b131a842SGavin Shan pdev = pe->pdev->bus->self; 635b131a842SGavin Shan while (pdev) { 636b131a842SGavin Shan struct pci_dn *pdn = pci_get_pdn(pdev); 637b131a842SGavin Shan struct pnv_ioda_pe *parent; 638b131a842SGavin Shan 639b131a842SGavin Shan if (pdn && pdn->pe_number != IODA_INVALID_PE) { 640b131a842SGavin Shan parent = &phb->ioda.pe_array[pdn->pe_number]; 641b131a842SGavin Shan ret = pnv_ioda_set_one_peltv(phb, parent, pe, is_add); 642b131a842SGavin Shan if (ret) 643b131a842SGavin Shan return ret; 644b131a842SGavin Shan } 645b131a842SGavin Shan 646b131a842SGavin Shan pdev = pdev->bus->self; 647b131a842SGavin Shan } 648b131a842SGavin Shan 649b131a842SGavin Shan return 0; 650b131a842SGavin Shan } 651b131a842SGavin Shan 652cad5cef6SGreg Kroah-Hartman static int pnv_ioda_configure_pe(struct pnv_phb *phb, struct pnv_ioda_pe *pe) 653184cd4a3SBenjamin Herrenschmidt { 654184cd4a3SBenjamin Herrenschmidt struct pci_dev *parent; 655184cd4a3SBenjamin Herrenschmidt uint8_t bcomp, dcomp, fcomp; 656184cd4a3SBenjamin Herrenschmidt long rc, rid_end, rid; 657184cd4a3SBenjamin Herrenschmidt 658184cd4a3SBenjamin Herrenschmidt /* Bus validation ? */ 659184cd4a3SBenjamin Herrenschmidt if (pe->pbus) { 660184cd4a3SBenjamin Herrenschmidt int count; 661184cd4a3SBenjamin Herrenschmidt 662184cd4a3SBenjamin Herrenschmidt dcomp = OPAL_IGNORE_RID_DEVICE_NUMBER; 663184cd4a3SBenjamin Herrenschmidt fcomp = OPAL_IGNORE_RID_FUNCTION_NUMBER; 664184cd4a3SBenjamin Herrenschmidt parent = pe->pbus->self; 665fb446ad0SGavin Shan if (pe->flags & PNV_IODA_PE_BUS_ALL) 666b918c62eSYinghai Lu count = pe->pbus->busn_res.end - pe->pbus->busn_res.start + 1; 667fb446ad0SGavin Shan else 668fb446ad0SGavin Shan count = 1; 669fb446ad0SGavin Shan 670184cd4a3SBenjamin Herrenschmidt switch(count) { 671184cd4a3SBenjamin Herrenschmidt case 1: bcomp = OpalPciBusAll; break; 672184cd4a3SBenjamin Herrenschmidt case 2: bcomp = OpalPciBus7Bits; break; 673184cd4a3SBenjamin Herrenschmidt case 4: bcomp = OpalPciBus6Bits; break; 674184cd4a3SBenjamin Herrenschmidt case 8: bcomp = OpalPciBus5Bits; break; 675184cd4a3SBenjamin Herrenschmidt case 16: bcomp = OpalPciBus4Bits; break; 676184cd4a3SBenjamin Herrenschmidt case 32: bcomp = OpalPciBus3Bits; break; 677184cd4a3SBenjamin Herrenschmidt default: 678184cd4a3SBenjamin Herrenschmidt pr_err("%s: Number of subordinate busses %d" 679184cd4a3SBenjamin Herrenschmidt " unsupported\n", 680184cd4a3SBenjamin Herrenschmidt pci_name(pe->pbus->self), count); 681184cd4a3SBenjamin Herrenschmidt /* Do an exact match only */ 682184cd4a3SBenjamin Herrenschmidt bcomp = OpalPciBusAll; 683184cd4a3SBenjamin Herrenschmidt } 684184cd4a3SBenjamin Herrenschmidt rid_end = pe->rid + (count << 8); 685184cd4a3SBenjamin Herrenschmidt } else { 686184cd4a3SBenjamin Herrenschmidt parent = pe->pdev->bus->self; 687184cd4a3SBenjamin Herrenschmidt bcomp = OpalPciBusAll; 688184cd4a3SBenjamin Herrenschmidt dcomp = OPAL_COMPARE_RID_DEVICE_NUMBER; 689184cd4a3SBenjamin Herrenschmidt fcomp = OPAL_COMPARE_RID_FUNCTION_NUMBER; 690184cd4a3SBenjamin Herrenschmidt rid_end = pe->rid + 1; 691184cd4a3SBenjamin Herrenschmidt } 692184cd4a3SBenjamin Herrenschmidt 693631ad691SGavin Shan /* 694631ad691SGavin Shan * Associate PE in PELT. We need add the PE into the 695631ad691SGavin Shan * corresponding PELT-V as well. Otherwise, the error 696631ad691SGavin Shan * originated from the PE might contribute to other 697631ad691SGavin Shan * PEs. 698631ad691SGavin Shan */ 699184cd4a3SBenjamin Herrenschmidt rc = opal_pci_set_pe(phb->opal_id, pe->pe_number, pe->rid, 700184cd4a3SBenjamin Herrenschmidt bcomp, dcomp, fcomp, OPAL_MAP_PE); 701184cd4a3SBenjamin Herrenschmidt if (rc) { 702184cd4a3SBenjamin Herrenschmidt pe_err(pe, "OPAL error %ld trying to setup PELT table\n", rc); 703184cd4a3SBenjamin Herrenschmidt return -ENXIO; 704184cd4a3SBenjamin Herrenschmidt } 705631ad691SGavin Shan 706b131a842SGavin Shan /* Configure PELTV */ 707b131a842SGavin Shan pnv_ioda_set_peltv(phb, pe, true); 708184cd4a3SBenjamin Herrenschmidt 709184cd4a3SBenjamin Herrenschmidt /* Setup reverse map */ 710184cd4a3SBenjamin Herrenschmidt for (rid = pe->rid; rid < rid_end; rid++) 711184cd4a3SBenjamin Herrenschmidt phb->ioda.pe_rmap[rid] = pe->pe_number; 712184cd4a3SBenjamin Herrenschmidt 713184cd4a3SBenjamin Herrenschmidt /* Setup one MVTs on IODA1 */ 7144773f76bSGavin Shan if (phb->type != PNV_PHB_IODA1) { 7154773f76bSGavin Shan pe->mve_number = 0; 7164773f76bSGavin Shan goto out; 7174773f76bSGavin Shan } 7184773f76bSGavin Shan 719184cd4a3SBenjamin Herrenschmidt pe->mve_number = pe->pe_number; 7204773f76bSGavin Shan rc = opal_pci_set_mve(phb->opal_id, pe->mve_number, pe->pe_number); 7214773f76bSGavin Shan if (rc != OPAL_SUCCESS) { 722184cd4a3SBenjamin Herrenschmidt pe_err(pe, "OPAL error %ld setting up MVE %d\n", 723184cd4a3SBenjamin Herrenschmidt rc, pe->mve_number); 724184cd4a3SBenjamin Herrenschmidt pe->mve_number = -1; 725184cd4a3SBenjamin Herrenschmidt } else { 726184cd4a3SBenjamin Herrenschmidt rc = opal_pci_set_mve_enable(phb->opal_id, 727cee72d5bSBenjamin Herrenschmidt pe->mve_number, OPAL_ENABLE_MVE); 728184cd4a3SBenjamin Herrenschmidt if (rc) { 729184cd4a3SBenjamin Herrenschmidt pe_err(pe, "OPAL error %ld enabling MVE %d\n", 730184cd4a3SBenjamin Herrenschmidt rc, pe->mve_number); 731184cd4a3SBenjamin Herrenschmidt pe->mve_number = -1; 732184cd4a3SBenjamin Herrenschmidt } 733184cd4a3SBenjamin Herrenschmidt } 734184cd4a3SBenjamin Herrenschmidt 7354773f76bSGavin Shan out: 736184cd4a3SBenjamin Herrenschmidt return 0; 737184cd4a3SBenjamin Herrenschmidt } 738184cd4a3SBenjamin Herrenschmidt 739cad5cef6SGreg Kroah-Hartman static void pnv_ioda_link_pe_by_weight(struct pnv_phb *phb, 740184cd4a3SBenjamin Herrenschmidt struct pnv_ioda_pe *pe) 741184cd4a3SBenjamin Herrenschmidt { 742184cd4a3SBenjamin Herrenschmidt struct pnv_ioda_pe *lpe; 743184cd4a3SBenjamin Herrenschmidt 7447ebdf956SGavin Shan list_for_each_entry(lpe, &phb->ioda.pe_dma_list, dma_link) { 745184cd4a3SBenjamin Herrenschmidt if (lpe->dma_weight < pe->dma_weight) { 7467ebdf956SGavin Shan list_add_tail(&pe->dma_link, &lpe->dma_link); 747184cd4a3SBenjamin Herrenschmidt return; 748184cd4a3SBenjamin Herrenschmidt } 749184cd4a3SBenjamin Herrenschmidt } 7507ebdf956SGavin Shan list_add_tail(&pe->dma_link, &phb->ioda.pe_dma_list); 751184cd4a3SBenjamin Herrenschmidt } 752184cd4a3SBenjamin Herrenschmidt 753184cd4a3SBenjamin Herrenschmidt static unsigned int pnv_ioda_dma_weight(struct pci_dev *dev) 754184cd4a3SBenjamin Herrenschmidt { 755184cd4a3SBenjamin Herrenschmidt /* This is quite simplistic. The "base" weight of a device 756184cd4a3SBenjamin Herrenschmidt * is 10. 0 means no DMA is to be accounted for it. 757184cd4a3SBenjamin Herrenschmidt */ 758184cd4a3SBenjamin Herrenschmidt 759184cd4a3SBenjamin Herrenschmidt /* If it's a bridge, no DMA */ 760184cd4a3SBenjamin Herrenschmidt if (dev->hdr_type != PCI_HEADER_TYPE_NORMAL) 761184cd4a3SBenjamin Herrenschmidt return 0; 762184cd4a3SBenjamin Herrenschmidt 763184cd4a3SBenjamin Herrenschmidt /* Reduce the weight of slow USB controllers */ 764184cd4a3SBenjamin Herrenschmidt if (dev->class == PCI_CLASS_SERIAL_USB_UHCI || 765184cd4a3SBenjamin Herrenschmidt dev->class == PCI_CLASS_SERIAL_USB_OHCI || 766184cd4a3SBenjamin Herrenschmidt dev->class == PCI_CLASS_SERIAL_USB_EHCI) 767184cd4a3SBenjamin Herrenschmidt return 3; 768184cd4a3SBenjamin Herrenschmidt 769184cd4a3SBenjamin Herrenschmidt /* Increase the weight of RAID (includes Obsidian) */ 770184cd4a3SBenjamin Herrenschmidt if ((dev->class >> 8) == PCI_CLASS_STORAGE_RAID) 771184cd4a3SBenjamin Herrenschmidt return 15; 772184cd4a3SBenjamin Herrenschmidt 773184cd4a3SBenjamin Herrenschmidt /* Default */ 774184cd4a3SBenjamin Herrenschmidt return 10; 775184cd4a3SBenjamin Herrenschmidt } 776184cd4a3SBenjamin Herrenschmidt 777fb446ad0SGavin Shan #if 0 778cad5cef6SGreg Kroah-Hartman static struct pnv_ioda_pe *pnv_ioda_setup_dev_PE(struct pci_dev *dev) 779184cd4a3SBenjamin Herrenschmidt { 780184cd4a3SBenjamin Herrenschmidt struct pci_controller *hose = pci_bus_to_host(dev->bus); 781184cd4a3SBenjamin Herrenschmidt struct pnv_phb *phb = hose->private_data; 782b72c1f65SBenjamin Herrenschmidt struct pci_dn *pdn = pci_get_pdn(dev); 783184cd4a3SBenjamin Herrenschmidt struct pnv_ioda_pe *pe; 784184cd4a3SBenjamin Herrenschmidt int pe_num; 785184cd4a3SBenjamin Herrenschmidt 786184cd4a3SBenjamin Herrenschmidt if (!pdn) { 787184cd4a3SBenjamin Herrenschmidt pr_err("%s: Device tree node not associated properly\n", 788184cd4a3SBenjamin Herrenschmidt pci_name(dev)); 789184cd4a3SBenjamin Herrenschmidt return NULL; 790184cd4a3SBenjamin Herrenschmidt } 791184cd4a3SBenjamin Herrenschmidt if (pdn->pe_number != IODA_INVALID_PE) 792184cd4a3SBenjamin Herrenschmidt return NULL; 793184cd4a3SBenjamin Herrenschmidt 794184cd4a3SBenjamin Herrenschmidt /* PE#0 has been pre-set */ 795184cd4a3SBenjamin Herrenschmidt if (dev->bus->number == 0) 796184cd4a3SBenjamin Herrenschmidt pe_num = 0; 797184cd4a3SBenjamin Herrenschmidt else 798184cd4a3SBenjamin Herrenschmidt pe_num = pnv_ioda_alloc_pe(phb); 799184cd4a3SBenjamin Herrenschmidt if (pe_num == IODA_INVALID_PE) { 800184cd4a3SBenjamin Herrenschmidt pr_warning("%s: Not enough PE# available, disabling device\n", 801184cd4a3SBenjamin Herrenschmidt pci_name(dev)); 802184cd4a3SBenjamin Herrenschmidt return NULL; 803184cd4a3SBenjamin Herrenschmidt } 804184cd4a3SBenjamin Herrenschmidt 805184cd4a3SBenjamin Herrenschmidt /* NOTE: We get only one ref to the pci_dev for the pdn, not for the 806184cd4a3SBenjamin Herrenschmidt * pointer in the PE data structure, both should be destroyed at the 807184cd4a3SBenjamin Herrenschmidt * same time. However, this needs to be looked at more closely again 808184cd4a3SBenjamin Herrenschmidt * once we actually start removing things (Hotplug, SR-IOV, ...) 809184cd4a3SBenjamin Herrenschmidt * 810184cd4a3SBenjamin Herrenschmidt * At some point we want to remove the PDN completely anyways 811184cd4a3SBenjamin Herrenschmidt */ 812184cd4a3SBenjamin Herrenschmidt pe = &phb->ioda.pe_array[pe_num]; 813184cd4a3SBenjamin Herrenschmidt pci_dev_get(dev); 814184cd4a3SBenjamin Herrenschmidt pdn->pcidev = dev; 815184cd4a3SBenjamin Herrenschmidt pdn->pe_number = pe_num; 816184cd4a3SBenjamin Herrenschmidt pe->pdev = dev; 817184cd4a3SBenjamin Herrenschmidt pe->pbus = NULL; 818184cd4a3SBenjamin Herrenschmidt pe->tce32_seg = -1; 819184cd4a3SBenjamin Herrenschmidt pe->mve_number = -1; 820184cd4a3SBenjamin Herrenschmidt pe->rid = dev->bus->number << 8 | pdn->devfn; 821184cd4a3SBenjamin Herrenschmidt 822184cd4a3SBenjamin Herrenschmidt pe_info(pe, "Associated device to PE\n"); 823184cd4a3SBenjamin Herrenschmidt 824184cd4a3SBenjamin Herrenschmidt if (pnv_ioda_configure_pe(phb, pe)) { 825184cd4a3SBenjamin Herrenschmidt /* XXX What do we do here ? */ 826184cd4a3SBenjamin Herrenschmidt if (pe_num) 827184cd4a3SBenjamin Herrenschmidt pnv_ioda_free_pe(phb, pe_num); 828184cd4a3SBenjamin Herrenschmidt pdn->pe_number = IODA_INVALID_PE; 829184cd4a3SBenjamin Herrenschmidt pe->pdev = NULL; 830184cd4a3SBenjamin Herrenschmidt pci_dev_put(dev); 831184cd4a3SBenjamin Herrenschmidt return NULL; 832184cd4a3SBenjamin Herrenschmidt } 833184cd4a3SBenjamin Herrenschmidt 834184cd4a3SBenjamin Herrenschmidt /* Assign a DMA weight to the device */ 835184cd4a3SBenjamin Herrenschmidt pe->dma_weight = pnv_ioda_dma_weight(dev); 836184cd4a3SBenjamin Herrenschmidt if (pe->dma_weight != 0) { 837184cd4a3SBenjamin Herrenschmidt phb->ioda.dma_weight += pe->dma_weight; 838184cd4a3SBenjamin Herrenschmidt phb->ioda.dma_pe_count++; 839184cd4a3SBenjamin Herrenschmidt } 840184cd4a3SBenjamin Herrenschmidt 841184cd4a3SBenjamin Herrenschmidt /* Link the PE */ 842184cd4a3SBenjamin Herrenschmidt pnv_ioda_link_pe_by_weight(phb, pe); 843184cd4a3SBenjamin Herrenschmidt 844184cd4a3SBenjamin Herrenschmidt return pe; 845184cd4a3SBenjamin Herrenschmidt } 846fb446ad0SGavin Shan #endif /* Useful for SRIOV case */ 847184cd4a3SBenjamin Herrenschmidt 848184cd4a3SBenjamin Herrenschmidt static void pnv_ioda_setup_same_PE(struct pci_bus *bus, struct pnv_ioda_pe *pe) 849184cd4a3SBenjamin Herrenschmidt { 850184cd4a3SBenjamin Herrenschmidt struct pci_dev *dev; 851184cd4a3SBenjamin Herrenschmidt 852184cd4a3SBenjamin Herrenschmidt list_for_each_entry(dev, &bus->devices, bus_list) { 853b72c1f65SBenjamin Herrenschmidt struct pci_dn *pdn = pci_get_pdn(dev); 854184cd4a3SBenjamin Herrenschmidt 855184cd4a3SBenjamin Herrenschmidt if (pdn == NULL) { 856184cd4a3SBenjamin Herrenschmidt pr_warn("%s: No device node associated with device !\n", 857184cd4a3SBenjamin Herrenschmidt pci_name(dev)); 858184cd4a3SBenjamin Herrenschmidt continue; 859184cd4a3SBenjamin Herrenschmidt } 860184cd4a3SBenjamin Herrenschmidt pdn->pcidev = dev; 861184cd4a3SBenjamin Herrenschmidt pdn->pe_number = pe->pe_number; 862184cd4a3SBenjamin Herrenschmidt pe->dma_weight += pnv_ioda_dma_weight(dev); 863fb446ad0SGavin Shan if ((pe->flags & PNV_IODA_PE_BUS_ALL) && dev->subordinate) 864184cd4a3SBenjamin Herrenschmidt pnv_ioda_setup_same_PE(dev->subordinate, pe); 865184cd4a3SBenjamin Herrenschmidt } 866184cd4a3SBenjamin Herrenschmidt } 867184cd4a3SBenjamin Herrenschmidt 868fb446ad0SGavin Shan /* 869fb446ad0SGavin Shan * There're 2 types of PCI bus sensitive PEs: One that is compromised of 870fb446ad0SGavin Shan * single PCI bus. Another one that contains the primary PCI bus and its 871fb446ad0SGavin Shan * subordinate PCI devices and buses. The second type of PE is normally 872fb446ad0SGavin Shan * orgiriated by PCIe-to-PCI bridge or PLX switch downstream ports. 873fb446ad0SGavin Shan */ 874cad5cef6SGreg Kroah-Hartman static void pnv_ioda_setup_bus_PE(struct pci_bus *bus, int all) 875184cd4a3SBenjamin Herrenschmidt { 876fb446ad0SGavin Shan struct pci_controller *hose = pci_bus_to_host(bus); 877184cd4a3SBenjamin Herrenschmidt struct pnv_phb *phb = hose->private_data; 878184cd4a3SBenjamin Herrenschmidt struct pnv_ioda_pe *pe; 879262af557SGuo Chao int pe_num = IODA_INVALID_PE; 880184cd4a3SBenjamin Herrenschmidt 881262af557SGuo Chao /* Check if PE is determined by M64 */ 882262af557SGuo Chao if (phb->pick_m64_pe) 883262af557SGuo Chao pe_num = phb->pick_m64_pe(phb, bus, all); 884262af557SGuo Chao 885262af557SGuo Chao /* The PE number isn't pinned by M64 */ 886262af557SGuo Chao if (pe_num == IODA_INVALID_PE) 887184cd4a3SBenjamin Herrenschmidt pe_num = pnv_ioda_alloc_pe(phb); 888262af557SGuo Chao 889184cd4a3SBenjamin Herrenschmidt if (pe_num == IODA_INVALID_PE) { 890fb446ad0SGavin Shan pr_warning("%s: Not enough PE# available for PCI bus %04x:%02x\n", 891fb446ad0SGavin Shan __func__, pci_domain_nr(bus), bus->number); 892184cd4a3SBenjamin Herrenschmidt return; 893184cd4a3SBenjamin Herrenschmidt } 894184cd4a3SBenjamin Herrenschmidt 895184cd4a3SBenjamin Herrenschmidt pe = &phb->ioda.pe_array[pe_num]; 896262af557SGuo Chao pe->flags |= (all ? PNV_IODA_PE_BUS_ALL : PNV_IODA_PE_BUS); 897184cd4a3SBenjamin Herrenschmidt pe->pbus = bus; 898184cd4a3SBenjamin Herrenschmidt pe->pdev = NULL; 899184cd4a3SBenjamin Herrenschmidt pe->tce32_seg = -1; 900184cd4a3SBenjamin Herrenschmidt pe->mve_number = -1; 901b918c62eSYinghai Lu pe->rid = bus->busn_res.start << 8; 902184cd4a3SBenjamin Herrenschmidt pe->dma_weight = 0; 903184cd4a3SBenjamin Herrenschmidt 904fb446ad0SGavin Shan if (all) 905fb446ad0SGavin Shan pe_info(pe, "Secondary bus %d..%d associated with PE#%d\n", 906fb446ad0SGavin Shan bus->busn_res.start, bus->busn_res.end, pe_num); 907fb446ad0SGavin Shan else 908fb446ad0SGavin Shan pe_info(pe, "Secondary bus %d associated with PE#%d\n", 909fb446ad0SGavin Shan bus->busn_res.start, pe_num); 910184cd4a3SBenjamin Herrenschmidt 911184cd4a3SBenjamin Herrenschmidt if (pnv_ioda_configure_pe(phb, pe)) { 912184cd4a3SBenjamin Herrenschmidt /* XXX What do we do here ? */ 913184cd4a3SBenjamin Herrenschmidt if (pe_num) 914184cd4a3SBenjamin Herrenschmidt pnv_ioda_free_pe(phb, pe_num); 915184cd4a3SBenjamin Herrenschmidt pe->pbus = NULL; 916184cd4a3SBenjamin Herrenschmidt return; 917184cd4a3SBenjamin Herrenschmidt } 918184cd4a3SBenjamin Herrenschmidt 919184cd4a3SBenjamin Herrenschmidt /* Associate it with all child devices */ 920184cd4a3SBenjamin Herrenschmidt pnv_ioda_setup_same_PE(bus, pe); 921184cd4a3SBenjamin Herrenschmidt 9227ebdf956SGavin Shan /* Put PE to the list */ 9237ebdf956SGavin Shan list_add_tail(&pe->list, &phb->ioda.pe_list); 9247ebdf956SGavin Shan 925184cd4a3SBenjamin Herrenschmidt /* Account for one DMA PE if at least one DMA capable device exist 926184cd4a3SBenjamin Herrenschmidt * below the bridge 927184cd4a3SBenjamin Herrenschmidt */ 928184cd4a3SBenjamin Herrenschmidt if (pe->dma_weight != 0) { 929184cd4a3SBenjamin Herrenschmidt phb->ioda.dma_weight += pe->dma_weight; 930184cd4a3SBenjamin Herrenschmidt phb->ioda.dma_pe_count++; 931184cd4a3SBenjamin Herrenschmidt } 932184cd4a3SBenjamin Herrenschmidt 933184cd4a3SBenjamin Herrenschmidt /* Link the PE */ 934184cd4a3SBenjamin Herrenschmidt pnv_ioda_link_pe_by_weight(phb, pe); 935184cd4a3SBenjamin Herrenschmidt } 936184cd4a3SBenjamin Herrenschmidt 937cad5cef6SGreg Kroah-Hartman static void pnv_ioda_setup_PEs(struct pci_bus *bus) 938184cd4a3SBenjamin Herrenschmidt { 939184cd4a3SBenjamin Herrenschmidt struct pci_dev *dev; 940fb446ad0SGavin Shan 941fb446ad0SGavin Shan pnv_ioda_setup_bus_PE(bus, 0); 942184cd4a3SBenjamin Herrenschmidt 943184cd4a3SBenjamin Herrenschmidt list_for_each_entry(dev, &bus->devices, bus_list) { 944fb446ad0SGavin Shan if (dev->subordinate) { 94562f87c0eSYijing Wang if (pci_pcie_type(dev) == PCI_EXP_TYPE_PCI_BRIDGE) 946fb446ad0SGavin Shan pnv_ioda_setup_bus_PE(dev->subordinate, 1); 947fb446ad0SGavin Shan else 948184cd4a3SBenjamin Herrenschmidt pnv_ioda_setup_PEs(dev->subordinate); 949184cd4a3SBenjamin Herrenschmidt } 950184cd4a3SBenjamin Herrenschmidt } 951fb446ad0SGavin Shan } 952fb446ad0SGavin Shan 953fb446ad0SGavin Shan /* 954fb446ad0SGavin Shan * Configure PEs so that the downstream PCI buses and devices 955fb446ad0SGavin Shan * could have their associated PE#. Unfortunately, we didn't 956fb446ad0SGavin Shan * figure out the way to identify the PLX bridge yet. So we 957fb446ad0SGavin Shan * simply put the PCI bus and the subordinate behind the root 958fb446ad0SGavin Shan * port to PE# here. The game rule here is expected to be changed 959fb446ad0SGavin Shan * as soon as we can detected PLX bridge correctly. 960fb446ad0SGavin Shan */ 961cad5cef6SGreg Kroah-Hartman static void pnv_pci_ioda_setup_PEs(void) 962fb446ad0SGavin Shan { 963fb446ad0SGavin Shan struct pci_controller *hose, *tmp; 964262af557SGuo Chao struct pnv_phb *phb; 965fb446ad0SGavin Shan 966fb446ad0SGavin Shan list_for_each_entry_safe(hose, tmp, &hose_list, list_node) { 967262af557SGuo Chao phb = hose->private_data; 968262af557SGuo Chao 969262af557SGuo Chao /* M64 layout might affect PE allocation */ 9705ef73567SGavin Shan if (phb->reserve_m64_pe) 9715ef73567SGavin Shan phb->reserve_m64_pe(phb); 972262af557SGuo Chao 973fb446ad0SGavin Shan pnv_ioda_setup_PEs(hose->bus); 974fb446ad0SGavin Shan } 975fb446ad0SGavin Shan } 976184cd4a3SBenjamin Herrenschmidt 977959c9bddSGavin Shan static void pnv_pci_ioda_dma_dev_setup(struct pnv_phb *phb, struct pci_dev *pdev) 978184cd4a3SBenjamin Herrenschmidt { 979b72c1f65SBenjamin Herrenschmidt struct pci_dn *pdn = pci_get_pdn(pdev); 980959c9bddSGavin Shan struct pnv_ioda_pe *pe; 981184cd4a3SBenjamin Herrenschmidt 982959c9bddSGavin Shan /* 983959c9bddSGavin Shan * The function can be called while the PE# 984959c9bddSGavin Shan * hasn't been assigned. Do nothing for the 985959c9bddSGavin Shan * case. 986959c9bddSGavin Shan */ 987959c9bddSGavin Shan if (!pdn || pdn->pe_number == IODA_INVALID_PE) 988959c9bddSGavin Shan return; 989184cd4a3SBenjamin Herrenschmidt 990959c9bddSGavin Shan pe = &phb->ioda.pe_array[pdn->pe_number]; 991cd15b048SBenjamin Herrenschmidt WARN_ON(get_dma_ops(&pdev->dev) != &dma_iommu_ops); 992763fe0adSGavin Shan set_iommu_table_base_and_group(&pdev->dev, &pe->tce32_table); 993184cd4a3SBenjamin Herrenschmidt } 994184cd4a3SBenjamin Herrenschmidt 995cd15b048SBenjamin Herrenschmidt static int pnv_pci_ioda_dma_set_mask(struct pnv_phb *phb, 996cd15b048SBenjamin Herrenschmidt struct pci_dev *pdev, u64 dma_mask) 997cd15b048SBenjamin Herrenschmidt { 998cd15b048SBenjamin Herrenschmidt struct pci_dn *pdn = pci_get_pdn(pdev); 999cd15b048SBenjamin Herrenschmidt struct pnv_ioda_pe *pe; 1000cd15b048SBenjamin Herrenschmidt uint64_t top; 1001cd15b048SBenjamin Herrenschmidt bool bypass = false; 1002cd15b048SBenjamin Herrenschmidt 1003cd15b048SBenjamin Herrenschmidt if (WARN_ON(!pdn || pdn->pe_number == IODA_INVALID_PE)) 1004cd15b048SBenjamin Herrenschmidt return -ENODEV;; 1005cd15b048SBenjamin Herrenschmidt 1006cd15b048SBenjamin Herrenschmidt pe = &phb->ioda.pe_array[pdn->pe_number]; 1007cd15b048SBenjamin Herrenschmidt if (pe->tce_bypass_enabled) { 1008cd15b048SBenjamin Herrenschmidt top = pe->tce_bypass_base + memblock_end_of_DRAM() - 1; 1009cd15b048SBenjamin Herrenschmidt bypass = (dma_mask >= top); 1010cd15b048SBenjamin Herrenschmidt } 1011cd15b048SBenjamin Herrenschmidt 1012cd15b048SBenjamin Herrenschmidt if (bypass) { 1013cd15b048SBenjamin Herrenschmidt dev_info(&pdev->dev, "Using 64-bit DMA iommu bypass\n"); 1014cd15b048SBenjamin Herrenschmidt set_dma_ops(&pdev->dev, &dma_direct_ops); 1015cd15b048SBenjamin Herrenschmidt set_dma_offset(&pdev->dev, pe->tce_bypass_base); 1016cd15b048SBenjamin Herrenschmidt } else { 1017cd15b048SBenjamin Herrenschmidt dev_info(&pdev->dev, "Using 32-bit DMA via iommu\n"); 1018cd15b048SBenjamin Herrenschmidt set_dma_ops(&pdev->dev, &dma_iommu_ops); 1019cd15b048SBenjamin Herrenschmidt set_iommu_table_base(&pdev->dev, &pe->tce32_table); 1020cd15b048SBenjamin Herrenschmidt } 1021a32305bfSBrian W Hart *pdev->dev.dma_mask = dma_mask; 1022cd15b048SBenjamin Herrenschmidt return 0; 1023cd15b048SBenjamin Herrenschmidt } 1024cd15b048SBenjamin Herrenschmidt 1025fe7e85c6SGavin Shan static u64 pnv_pci_ioda_dma_get_required_mask(struct pnv_phb *phb, 1026fe7e85c6SGavin Shan struct pci_dev *pdev) 1027fe7e85c6SGavin Shan { 1028fe7e85c6SGavin Shan struct pci_dn *pdn = pci_get_pdn(pdev); 1029fe7e85c6SGavin Shan struct pnv_ioda_pe *pe; 1030fe7e85c6SGavin Shan u64 end, mask; 1031fe7e85c6SGavin Shan 1032fe7e85c6SGavin Shan if (WARN_ON(!pdn || pdn->pe_number == IODA_INVALID_PE)) 1033fe7e85c6SGavin Shan return 0; 1034fe7e85c6SGavin Shan 1035fe7e85c6SGavin Shan pe = &phb->ioda.pe_array[pdn->pe_number]; 1036fe7e85c6SGavin Shan if (!pe->tce_bypass_enabled) 1037fe7e85c6SGavin Shan return __dma_get_required_mask(&pdev->dev); 1038fe7e85c6SGavin Shan 1039fe7e85c6SGavin Shan 1040fe7e85c6SGavin Shan end = pe->tce_bypass_base + memblock_end_of_DRAM(); 1041fe7e85c6SGavin Shan mask = 1ULL << (fls64(end) - 1); 1042fe7e85c6SGavin Shan mask += mask - 1; 1043fe7e85c6SGavin Shan 1044fe7e85c6SGavin Shan return mask; 1045fe7e85c6SGavin Shan } 1046fe7e85c6SGavin Shan 1047dff4a39eSGavin Shan static void pnv_ioda_setup_bus_dma(struct pnv_ioda_pe *pe, 1048dff4a39eSGavin Shan struct pci_bus *bus, 1049dff4a39eSGavin Shan bool add_to_iommu_group) 105074251fe2SBenjamin Herrenschmidt { 105174251fe2SBenjamin Herrenschmidt struct pci_dev *dev; 105274251fe2SBenjamin Herrenschmidt 105374251fe2SBenjamin Herrenschmidt list_for_each_entry(dev, &bus->devices, bus_list) { 1054dff4a39eSGavin Shan if (add_to_iommu_group) 1055dff4a39eSGavin Shan set_iommu_table_base_and_group(&dev->dev, 1056dff4a39eSGavin Shan &pe->tce32_table); 1057dff4a39eSGavin Shan else 1058dff4a39eSGavin Shan set_iommu_table_base(&dev->dev, &pe->tce32_table); 1059dff4a39eSGavin Shan 106074251fe2SBenjamin Herrenschmidt if (dev->subordinate) 1061dff4a39eSGavin Shan pnv_ioda_setup_bus_dma(pe, dev->subordinate, 1062dff4a39eSGavin Shan add_to_iommu_group); 106374251fe2SBenjamin Herrenschmidt } 106474251fe2SBenjamin Herrenschmidt } 106574251fe2SBenjamin Herrenschmidt 10668e0a1611SAlexey Kardashevskiy static void pnv_pci_ioda1_tce_invalidate(struct pnv_ioda_pe *pe, 10678e0a1611SAlexey Kardashevskiy struct iommu_table *tbl, 10683ad26e5cSBenjamin Herrenschmidt __be64 *startp, __be64 *endp, bool rm) 10694cce9550SGavin Shan { 10703ad26e5cSBenjamin Herrenschmidt __be64 __iomem *invalidate = rm ? 10713ad26e5cSBenjamin Herrenschmidt (__be64 __iomem *)pe->tce_inval_reg_phys : 10723ad26e5cSBenjamin Herrenschmidt (__be64 __iomem *)tbl->it_index; 10734cce9550SGavin Shan unsigned long start, end, inc; 1074b0376c9bSAlexey Kardashevskiy const unsigned shift = tbl->it_page_shift; 10754cce9550SGavin Shan 10764cce9550SGavin Shan start = __pa(startp); 10774cce9550SGavin Shan end = __pa(endp); 10784cce9550SGavin Shan 10794cce9550SGavin Shan /* BML uses this case for p6/p7/galaxy2: Shift addr and put in node */ 10804cce9550SGavin Shan if (tbl->it_busno) { 1081b0376c9bSAlexey Kardashevskiy start <<= shift; 1082b0376c9bSAlexey Kardashevskiy end <<= shift; 1083b0376c9bSAlexey Kardashevskiy inc = 128ull << shift; 10844cce9550SGavin Shan start |= tbl->it_busno; 10854cce9550SGavin Shan end |= tbl->it_busno; 10864cce9550SGavin Shan } else if (tbl->it_type & TCE_PCI_SWINV_PAIR) { 10874cce9550SGavin Shan /* p7ioc-style invalidation, 2 TCEs per write */ 10884cce9550SGavin Shan start |= (1ull << 63); 10894cce9550SGavin Shan end |= (1ull << 63); 10904cce9550SGavin Shan inc = 16; 10914cce9550SGavin Shan } else { 10924cce9550SGavin Shan /* Default (older HW) */ 10934cce9550SGavin Shan inc = 128; 10944cce9550SGavin Shan } 10954cce9550SGavin Shan 10964cce9550SGavin Shan end |= inc - 1; /* round up end to be different than start */ 10974cce9550SGavin Shan 10984cce9550SGavin Shan mb(); /* Ensure above stores are visible */ 10994cce9550SGavin Shan while (start <= end) { 11008e0a1611SAlexey Kardashevskiy if (rm) 11013ad26e5cSBenjamin Herrenschmidt __raw_rm_writeq(cpu_to_be64(start), invalidate); 11028e0a1611SAlexey Kardashevskiy else 11033a1a4661SBenjamin Herrenschmidt __raw_writeq(cpu_to_be64(start), invalidate); 11044cce9550SGavin Shan start += inc; 11054cce9550SGavin Shan } 11064cce9550SGavin Shan 11074cce9550SGavin Shan /* 11084cce9550SGavin Shan * The iommu layer will do another mb() for us on build() 11094cce9550SGavin Shan * and we don't care on free() 11104cce9550SGavin Shan */ 11114cce9550SGavin Shan } 11124cce9550SGavin Shan 11134cce9550SGavin Shan static void pnv_pci_ioda2_tce_invalidate(struct pnv_ioda_pe *pe, 11144cce9550SGavin Shan struct iommu_table *tbl, 11153ad26e5cSBenjamin Herrenschmidt __be64 *startp, __be64 *endp, bool rm) 11164cce9550SGavin Shan { 11174cce9550SGavin Shan unsigned long start, end, inc; 11183ad26e5cSBenjamin Herrenschmidt __be64 __iomem *invalidate = rm ? 11193ad26e5cSBenjamin Herrenschmidt (__be64 __iomem *)pe->tce_inval_reg_phys : 11203ad26e5cSBenjamin Herrenschmidt (__be64 __iomem *)tbl->it_index; 1121b0376c9bSAlexey Kardashevskiy const unsigned shift = tbl->it_page_shift; 11224cce9550SGavin Shan 11234cce9550SGavin Shan /* We'll invalidate DMA address in PE scope */ 1124b0376c9bSAlexey Kardashevskiy start = 0x2ull << 60; 11254cce9550SGavin Shan start |= (pe->pe_number & 0xFF); 11264cce9550SGavin Shan end = start; 11274cce9550SGavin Shan 11284cce9550SGavin Shan /* Figure out the start, end and step */ 11294cce9550SGavin Shan inc = tbl->it_offset + (((u64)startp - tbl->it_base) / sizeof(u64)); 1130b0376c9bSAlexey Kardashevskiy start |= (inc << shift); 11314cce9550SGavin Shan inc = tbl->it_offset + (((u64)endp - tbl->it_base) / sizeof(u64)); 1132b0376c9bSAlexey Kardashevskiy end |= (inc << shift); 1133b0376c9bSAlexey Kardashevskiy inc = (0x1ull << shift); 11344cce9550SGavin Shan mb(); 11354cce9550SGavin Shan 11364cce9550SGavin Shan while (start <= end) { 11378e0a1611SAlexey Kardashevskiy if (rm) 11383ad26e5cSBenjamin Herrenschmidt __raw_rm_writeq(cpu_to_be64(start), invalidate); 11398e0a1611SAlexey Kardashevskiy else 11403a1a4661SBenjamin Herrenschmidt __raw_writeq(cpu_to_be64(start), invalidate); 11414cce9550SGavin Shan start += inc; 11424cce9550SGavin Shan } 11434cce9550SGavin Shan } 11444cce9550SGavin Shan 11454cce9550SGavin Shan void pnv_pci_ioda_tce_invalidate(struct iommu_table *tbl, 11463ad26e5cSBenjamin Herrenschmidt __be64 *startp, __be64 *endp, bool rm) 11474cce9550SGavin Shan { 11484cce9550SGavin Shan struct pnv_ioda_pe *pe = container_of(tbl, struct pnv_ioda_pe, 11494cce9550SGavin Shan tce32_table); 11504cce9550SGavin Shan struct pnv_phb *phb = pe->phb; 11514cce9550SGavin Shan 11524cce9550SGavin Shan if (phb->type == PNV_PHB_IODA1) 11538e0a1611SAlexey Kardashevskiy pnv_pci_ioda1_tce_invalidate(pe, tbl, startp, endp, rm); 11544cce9550SGavin Shan else 11558e0a1611SAlexey Kardashevskiy pnv_pci_ioda2_tce_invalidate(pe, tbl, startp, endp, rm); 11564cce9550SGavin Shan } 11574cce9550SGavin Shan 1158cad5cef6SGreg Kroah-Hartman static void pnv_pci_ioda_setup_dma_pe(struct pnv_phb *phb, 1159cad5cef6SGreg Kroah-Hartman struct pnv_ioda_pe *pe, unsigned int base, 1160184cd4a3SBenjamin Herrenschmidt unsigned int segs) 1161184cd4a3SBenjamin Herrenschmidt { 1162184cd4a3SBenjamin Herrenschmidt 1163184cd4a3SBenjamin Herrenschmidt struct page *tce_mem = NULL; 1164184cd4a3SBenjamin Herrenschmidt const __be64 *swinvp; 1165184cd4a3SBenjamin Herrenschmidt struct iommu_table *tbl; 1166184cd4a3SBenjamin Herrenschmidt unsigned int i; 1167184cd4a3SBenjamin Herrenschmidt int64_t rc; 1168184cd4a3SBenjamin Herrenschmidt void *addr; 1169184cd4a3SBenjamin Herrenschmidt 1170184cd4a3SBenjamin Herrenschmidt /* 256M DMA window, 4K TCE pages, 8 bytes TCE */ 1171184cd4a3SBenjamin Herrenschmidt #define TCE32_TABLE_SIZE ((0x10000000 / 0x1000) * 8) 1172184cd4a3SBenjamin Herrenschmidt 1173184cd4a3SBenjamin Herrenschmidt /* XXX FIXME: Handle 64-bit only DMA devices */ 1174184cd4a3SBenjamin Herrenschmidt /* XXX FIXME: Provide 64-bit DMA facilities & non-4K TCE tables etc.. */ 1175184cd4a3SBenjamin Herrenschmidt /* XXX FIXME: Allocate multi-level tables on PHB3 */ 1176184cd4a3SBenjamin Herrenschmidt 1177184cd4a3SBenjamin Herrenschmidt /* We shouldn't already have a 32-bit DMA associated */ 1178184cd4a3SBenjamin Herrenschmidt if (WARN_ON(pe->tce32_seg >= 0)) 1179184cd4a3SBenjamin Herrenschmidt return; 1180184cd4a3SBenjamin Herrenschmidt 1181184cd4a3SBenjamin Herrenschmidt /* Grab a 32-bit TCE table */ 1182184cd4a3SBenjamin Herrenschmidt pe->tce32_seg = base; 1183184cd4a3SBenjamin Herrenschmidt pe_info(pe, " Setting up 32-bit TCE table at %08x..%08x\n", 1184184cd4a3SBenjamin Herrenschmidt (base << 28), ((base + segs) << 28) - 1); 1185184cd4a3SBenjamin Herrenschmidt 1186184cd4a3SBenjamin Herrenschmidt /* XXX Currently, we allocate one big contiguous table for the 1187184cd4a3SBenjamin Herrenschmidt * TCEs. We only really need one chunk per 256M of TCE space 1188184cd4a3SBenjamin Herrenschmidt * (ie per segment) but that's an optimization for later, it 1189184cd4a3SBenjamin Herrenschmidt * requires some added smarts with our get/put_tce implementation 1190184cd4a3SBenjamin Herrenschmidt */ 1191184cd4a3SBenjamin Herrenschmidt tce_mem = alloc_pages_node(phb->hose->node, GFP_KERNEL, 1192184cd4a3SBenjamin Herrenschmidt get_order(TCE32_TABLE_SIZE * segs)); 1193184cd4a3SBenjamin Herrenschmidt if (!tce_mem) { 1194184cd4a3SBenjamin Herrenschmidt pe_err(pe, " Failed to allocate a 32-bit TCE memory\n"); 1195184cd4a3SBenjamin Herrenschmidt goto fail; 1196184cd4a3SBenjamin Herrenschmidt } 1197184cd4a3SBenjamin Herrenschmidt addr = page_address(tce_mem); 1198184cd4a3SBenjamin Herrenschmidt memset(addr, 0, TCE32_TABLE_SIZE * segs); 1199184cd4a3SBenjamin Herrenschmidt 1200184cd4a3SBenjamin Herrenschmidt /* Configure HW */ 1201184cd4a3SBenjamin Herrenschmidt for (i = 0; i < segs; i++) { 1202184cd4a3SBenjamin Herrenschmidt rc = opal_pci_map_pe_dma_window(phb->opal_id, 1203184cd4a3SBenjamin Herrenschmidt pe->pe_number, 1204184cd4a3SBenjamin Herrenschmidt base + i, 1, 1205184cd4a3SBenjamin Herrenschmidt __pa(addr) + TCE32_TABLE_SIZE * i, 1206184cd4a3SBenjamin Herrenschmidt TCE32_TABLE_SIZE, 0x1000); 1207184cd4a3SBenjamin Herrenschmidt if (rc) { 1208184cd4a3SBenjamin Herrenschmidt pe_err(pe, " Failed to configure 32-bit TCE table," 1209184cd4a3SBenjamin Herrenschmidt " err %ld\n", rc); 1210184cd4a3SBenjamin Herrenschmidt goto fail; 1211184cd4a3SBenjamin Herrenschmidt } 1212184cd4a3SBenjamin Herrenschmidt } 1213184cd4a3SBenjamin Herrenschmidt 1214184cd4a3SBenjamin Herrenschmidt /* Setup linux iommu table */ 1215184cd4a3SBenjamin Herrenschmidt tbl = &pe->tce32_table; 1216184cd4a3SBenjamin Herrenschmidt pnv_pci_setup_iommu_table(tbl, addr, TCE32_TABLE_SIZE * segs, 12178fa5d454SAlexey Kardashevskiy base << 28, IOMMU_PAGE_SHIFT_4K); 1218184cd4a3SBenjamin Herrenschmidt 1219184cd4a3SBenjamin Herrenschmidt /* OPAL variant of P7IOC SW invalidated TCEs */ 1220184cd4a3SBenjamin Herrenschmidt swinvp = of_get_property(phb->hose->dn, "ibm,opal-tce-kill", NULL); 1221184cd4a3SBenjamin Herrenschmidt if (swinvp) { 1222184cd4a3SBenjamin Herrenschmidt /* We need a couple more fields -- an address and a data 1223184cd4a3SBenjamin Herrenschmidt * to or. Since the bus is only printed out on table free 1224184cd4a3SBenjamin Herrenschmidt * errors, and on the first pass the data will be a relative 1225184cd4a3SBenjamin Herrenschmidt * bus number, print that out instead. 1226184cd4a3SBenjamin Herrenschmidt */ 12278e0a1611SAlexey Kardashevskiy pe->tce_inval_reg_phys = be64_to_cpup(swinvp); 12288e0a1611SAlexey Kardashevskiy tbl->it_index = (unsigned long)ioremap(pe->tce_inval_reg_phys, 12298e0a1611SAlexey Kardashevskiy 8); 123065fd766bSGavin Shan tbl->it_type |= (TCE_PCI_SWINV_CREATE | 123165fd766bSGavin Shan TCE_PCI_SWINV_FREE | 123265fd766bSGavin Shan TCE_PCI_SWINV_PAIR); 1233184cd4a3SBenjamin Herrenschmidt } 1234184cd4a3SBenjamin Herrenschmidt iommu_init_table(tbl, phb->hose->node); 1235e9bc03feSGavin Shan iommu_register_group(tbl, phb->hose->global_number, pe->pe_number); 1236184cd4a3SBenjamin Herrenschmidt 123774251fe2SBenjamin Herrenschmidt if (pe->pdev) 1238d905c5dfSAlexey Kardashevskiy set_iommu_table_base_and_group(&pe->pdev->dev, tbl); 123974251fe2SBenjamin Herrenschmidt else 1240dff4a39eSGavin Shan pnv_ioda_setup_bus_dma(pe, pe->pbus, true); 124174251fe2SBenjamin Herrenschmidt 1242184cd4a3SBenjamin Herrenschmidt return; 1243184cd4a3SBenjamin Herrenschmidt fail: 1244184cd4a3SBenjamin Herrenschmidt /* XXX Failure: Try to fallback to 64-bit only ? */ 1245184cd4a3SBenjamin Herrenschmidt if (pe->tce32_seg >= 0) 1246184cd4a3SBenjamin Herrenschmidt pe->tce32_seg = -1; 1247184cd4a3SBenjamin Herrenschmidt if (tce_mem) 1248184cd4a3SBenjamin Herrenschmidt __free_pages(tce_mem, get_order(TCE32_TABLE_SIZE * segs)); 1249184cd4a3SBenjamin Herrenschmidt } 1250184cd4a3SBenjamin Herrenschmidt 1251cd15b048SBenjamin Herrenschmidt static void pnv_pci_ioda2_set_bypass(struct iommu_table *tbl, bool enable) 1252cd15b048SBenjamin Herrenschmidt { 1253cd15b048SBenjamin Herrenschmidt struct pnv_ioda_pe *pe = container_of(tbl, struct pnv_ioda_pe, 1254cd15b048SBenjamin Herrenschmidt tce32_table); 1255cd15b048SBenjamin Herrenschmidt uint16_t window_id = (pe->pe_number << 1 ) + 1; 1256cd15b048SBenjamin Herrenschmidt int64_t rc; 1257cd15b048SBenjamin Herrenschmidt 1258cd15b048SBenjamin Herrenschmidt pe_info(pe, "%sabling 64-bit DMA bypass\n", enable ? "En" : "Dis"); 1259cd15b048SBenjamin Herrenschmidt if (enable) { 1260cd15b048SBenjamin Herrenschmidt phys_addr_t top = memblock_end_of_DRAM(); 1261cd15b048SBenjamin Herrenschmidt 1262cd15b048SBenjamin Herrenschmidt top = roundup_pow_of_two(top); 1263cd15b048SBenjamin Herrenschmidt rc = opal_pci_map_pe_dma_window_real(pe->phb->opal_id, 1264cd15b048SBenjamin Herrenschmidt pe->pe_number, 1265cd15b048SBenjamin Herrenschmidt window_id, 1266cd15b048SBenjamin Herrenschmidt pe->tce_bypass_base, 1267cd15b048SBenjamin Herrenschmidt top); 1268cd15b048SBenjamin Herrenschmidt } else { 1269cd15b048SBenjamin Herrenschmidt rc = opal_pci_map_pe_dma_window_real(pe->phb->opal_id, 1270cd15b048SBenjamin Herrenschmidt pe->pe_number, 1271cd15b048SBenjamin Herrenschmidt window_id, 1272cd15b048SBenjamin Herrenschmidt pe->tce_bypass_base, 1273cd15b048SBenjamin Herrenschmidt 0); 1274cd15b048SBenjamin Herrenschmidt 1275cd15b048SBenjamin Herrenschmidt /* 1276dff4a39eSGavin Shan * EEH needs the mapping between IOMMU table and group 1277dff4a39eSGavin Shan * of those VFIO/KVM pass-through devices. We can postpone 1278dff4a39eSGavin Shan * resetting DMA ops until the DMA mask is configured in 1279dff4a39eSGavin Shan * host side. 1280cd15b048SBenjamin Herrenschmidt */ 1281dff4a39eSGavin Shan if (pe->pdev) 1282dff4a39eSGavin Shan set_iommu_table_base(&pe->pdev->dev, tbl); 1283dff4a39eSGavin Shan else 1284dff4a39eSGavin Shan pnv_ioda_setup_bus_dma(pe, pe->pbus, false); 1285cd15b048SBenjamin Herrenschmidt } 1286cd15b048SBenjamin Herrenschmidt if (rc) 1287cd15b048SBenjamin Herrenschmidt pe_err(pe, "OPAL error %lld configuring bypass window\n", rc); 1288cd15b048SBenjamin Herrenschmidt else 1289cd15b048SBenjamin Herrenschmidt pe->tce_bypass_enabled = enable; 1290cd15b048SBenjamin Herrenschmidt } 1291cd15b048SBenjamin Herrenschmidt 1292cd15b048SBenjamin Herrenschmidt static void pnv_pci_ioda2_setup_bypass_pe(struct pnv_phb *phb, 1293cd15b048SBenjamin Herrenschmidt struct pnv_ioda_pe *pe) 1294cd15b048SBenjamin Herrenschmidt { 1295cd15b048SBenjamin Herrenschmidt /* TVE #1 is selected by PCI address bit 59 */ 1296cd15b048SBenjamin Herrenschmidt pe->tce_bypass_base = 1ull << 59; 1297cd15b048SBenjamin Herrenschmidt 1298cd15b048SBenjamin Herrenschmidt /* Install set_bypass callback for VFIO */ 1299cd15b048SBenjamin Herrenschmidt pe->tce32_table.set_bypass = pnv_pci_ioda2_set_bypass; 1300cd15b048SBenjamin Herrenschmidt 1301cd15b048SBenjamin Herrenschmidt /* Enable bypass by default */ 1302cd15b048SBenjamin Herrenschmidt pnv_pci_ioda2_set_bypass(&pe->tce32_table, true); 1303cd15b048SBenjamin Herrenschmidt } 1304cd15b048SBenjamin Herrenschmidt 1305373f5657SGavin Shan static void pnv_pci_ioda2_setup_dma_pe(struct pnv_phb *phb, 1306373f5657SGavin Shan struct pnv_ioda_pe *pe) 1307373f5657SGavin Shan { 1308373f5657SGavin Shan struct page *tce_mem = NULL; 1309373f5657SGavin Shan void *addr; 1310373f5657SGavin Shan const __be64 *swinvp; 1311373f5657SGavin Shan struct iommu_table *tbl; 1312373f5657SGavin Shan unsigned int tce_table_size, end; 1313373f5657SGavin Shan int64_t rc; 1314373f5657SGavin Shan 1315373f5657SGavin Shan /* We shouldn't already have a 32-bit DMA associated */ 1316373f5657SGavin Shan if (WARN_ON(pe->tce32_seg >= 0)) 1317373f5657SGavin Shan return; 1318373f5657SGavin Shan 1319373f5657SGavin Shan /* The PE will reserve all possible 32-bits space */ 1320373f5657SGavin Shan pe->tce32_seg = 0; 1321373f5657SGavin Shan end = (1 << ilog2(phb->ioda.m32_pci_base)); 1322373f5657SGavin Shan tce_table_size = (end / 0x1000) * 8; 1323373f5657SGavin Shan pe_info(pe, "Setting up 32-bit TCE table at 0..%08x\n", 1324373f5657SGavin Shan end); 1325373f5657SGavin Shan 1326373f5657SGavin Shan /* Allocate TCE table */ 1327373f5657SGavin Shan tce_mem = alloc_pages_node(phb->hose->node, GFP_KERNEL, 1328373f5657SGavin Shan get_order(tce_table_size)); 1329373f5657SGavin Shan if (!tce_mem) { 1330373f5657SGavin Shan pe_err(pe, "Failed to allocate a 32-bit TCE memory\n"); 1331373f5657SGavin Shan goto fail; 1332373f5657SGavin Shan } 1333373f5657SGavin Shan addr = page_address(tce_mem); 1334373f5657SGavin Shan memset(addr, 0, tce_table_size); 1335373f5657SGavin Shan 1336373f5657SGavin Shan /* 1337373f5657SGavin Shan * Map TCE table through TVT. The TVE index is the PE number 1338373f5657SGavin Shan * shifted by 1 bit for 32-bits DMA space. 1339373f5657SGavin Shan */ 1340373f5657SGavin Shan rc = opal_pci_map_pe_dma_window(phb->opal_id, pe->pe_number, 1341373f5657SGavin Shan pe->pe_number << 1, 1, __pa(addr), 1342373f5657SGavin Shan tce_table_size, 0x1000); 1343373f5657SGavin Shan if (rc) { 1344373f5657SGavin Shan pe_err(pe, "Failed to configure 32-bit TCE table," 1345373f5657SGavin Shan " err %ld\n", rc); 1346373f5657SGavin Shan goto fail; 1347373f5657SGavin Shan } 1348373f5657SGavin Shan 1349373f5657SGavin Shan /* Setup linux iommu table */ 1350373f5657SGavin Shan tbl = &pe->tce32_table; 13518fa5d454SAlexey Kardashevskiy pnv_pci_setup_iommu_table(tbl, addr, tce_table_size, 0, 13528fa5d454SAlexey Kardashevskiy IOMMU_PAGE_SHIFT_4K); 1353373f5657SGavin Shan 1354373f5657SGavin Shan /* OPAL variant of PHB3 invalidated TCEs */ 1355373f5657SGavin Shan swinvp = of_get_property(phb->hose->dn, "ibm,opal-tce-kill", NULL); 1356373f5657SGavin Shan if (swinvp) { 1357373f5657SGavin Shan /* We need a couple more fields -- an address and a data 1358373f5657SGavin Shan * to or. Since the bus is only printed out on table free 1359373f5657SGavin Shan * errors, and on the first pass the data will be a relative 1360373f5657SGavin Shan * bus number, print that out instead. 1361373f5657SGavin Shan */ 13628e0a1611SAlexey Kardashevskiy pe->tce_inval_reg_phys = be64_to_cpup(swinvp); 13638e0a1611SAlexey Kardashevskiy tbl->it_index = (unsigned long)ioremap(pe->tce_inval_reg_phys, 13648e0a1611SAlexey Kardashevskiy 8); 136565fd766bSGavin Shan tbl->it_type |= (TCE_PCI_SWINV_CREATE | TCE_PCI_SWINV_FREE); 1366373f5657SGavin Shan } 1367373f5657SGavin Shan iommu_init_table(tbl, phb->hose->node); 1368e9bc03feSGavin Shan iommu_register_group(tbl, phb->hose->global_number, pe->pe_number); 1369373f5657SGavin Shan 137074251fe2SBenjamin Herrenschmidt if (pe->pdev) 1371d905c5dfSAlexey Kardashevskiy set_iommu_table_base_and_group(&pe->pdev->dev, tbl); 137274251fe2SBenjamin Herrenschmidt else 1373dff4a39eSGavin Shan pnv_ioda_setup_bus_dma(pe, pe->pbus, true); 137474251fe2SBenjamin Herrenschmidt 1375cd15b048SBenjamin Herrenschmidt /* Also create a bypass window */ 13764e287840SThadeu Lima de Souza Cascardo if (!pnv_iommu_bypass_disabled) 1377cd15b048SBenjamin Herrenschmidt pnv_pci_ioda2_setup_bypass_pe(phb, pe); 13784e287840SThadeu Lima de Souza Cascardo 1379373f5657SGavin Shan return; 1380373f5657SGavin Shan fail: 1381373f5657SGavin Shan if (pe->tce32_seg >= 0) 1382373f5657SGavin Shan pe->tce32_seg = -1; 1383373f5657SGavin Shan if (tce_mem) 1384373f5657SGavin Shan __free_pages(tce_mem, get_order(tce_table_size)); 1385373f5657SGavin Shan } 1386373f5657SGavin Shan 1387cad5cef6SGreg Kroah-Hartman static void pnv_ioda_setup_dma(struct pnv_phb *phb) 1388184cd4a3SBenjamin Herrenschmidt { 1389184cd4a3SBenjamin Herrenschmidt struct pci_controller *hose = phb->hose; 1390184cd4a3SBenjamin Herrenschmidt unsigned int residual, remaining, segs, tw, base; 1391184cd4a3SBenjamin Herrenschmidt struct pnv_ioda_pe *pe; 1392184cd4a3SBenjamin Herrenschmidt 1393184cd4a3SBenjamin Herrenschmidt /* If we have more PE# than segments available, hand out one 1394184cd4a3SBenjamin Herrenschmidt * per PE until we run out and let the rest fail. If not, 1395184cd4a3SBenjamin Herrenschmidt * then we assign at least one segment per PE, plus more based 1396184cd4a3SBenjamin Herrenschmidt * on the amount of devices under that PE 1397184cd4a3SBenjamin Herrenschmidt */ 1398184cd4a3SBenjamin Herrenschmidt if (phb->ioda.dma_pe_count > phb->ioda.tce32_count) 1399184cd4a3SBenjamin Herrenschmidt residual = 0; 1400184cd4a3SBenjamin Herrenschmidt else 1401184cd4a3SBenjamin Herrenschmidt residual = phb->ioda.tce32_count - 1402184cd4a3SBenjamin Herrenschmidt phb->ioda.dma_pe_count; 1403184cd4a3SBenjamin Herrenschmidt 1404184cd4a3SBenjamin Herrenschmidt pr_info("PCI: Domain %04x has %ld available 32-bit DMA segments\n", 1405184cd4a3SBenjamin Herrenschmidt hose->global_number, phb->ioda.tce32_count); 1406184cd4a3SBenjamin Herrenschmidt pr_info("PCI: %d PE# for a total weight of %d\n", 1407184cd4a3SBenjamin Herrenschmidt phb->ioda.dma_pe_count, phb->ioda.dma_weight); 1408184cd4a3SBenjamin Herrenschmidt 1409184cd4a3SBenjamin Herrenschmidt /* Walk our PE list and configure their DMA segments, hand them 1410184cd4a3SBenjamin Herrenschmidt * out one base segment plus any residual segments based on 1411184cd4a3SBenjamin Herrenschmidt * weight 1412184cd4a3SBenjamin Herrenschmidt */ 1413184cd4a3SBenjamin Herrenschmidt remaining = phb->ioda.tce32_count; 1414184cd4a3SBenjamin Herrenschmidt tw = phb->ioda.dma_weight; 1415184cd4a3SBenjamin Herrenschmidt base = 0; 14167ebdf956SGavin Shan list_for_each_entry(pe, &phb->ioda.pe_dma_list, dma_link) { 1417184cd4a3SBenjamin Herrenschmidt if (!pe->dma_weight) 1418184cd4a3SBenjamin Herrenschmidt continue; 1419184cd4a3SBenjamin Herrenschmidt if (!remaining) { 1420184cd4a3SBenjamin Herrenschmidt pe_warn(pe, "No DMA32 resources available\n"); 1421184cd4a3SBenjamin Herrenschmidt continue; 1422184cd4a3SBenjamin Herrenschmidt } 1423184cd4a3SBenjamin Herrenschmidt segs = 1; 1424184cd4a3SBenjamin Herrenschmidt if (residual) { 1425184cd4a3SBenjamin Herrenschmidt segs += ((pe->dma_weight * residual) + (tw / 2)) / tw; 1426184cd4a3SBenjamin Herrenschmidt if (segs > remaining) 1427184cd4a3SBenjamin Herrenschmidt segs = remaining; 1428184cd4a3SBenjamin Herrenschmidt } 1429373f5657SGavin Shan 1430373f5657SGavin Shan /* 1431373f5657SGavin Shan * For IODA2 compliant PHB3, we needn't care about the weight. 1432373f5657SGavin Shan * The all available 32-bits DMA space will be assigned to 1433373f5657SGavin Shan * the specific PE. 1434373f5657SGavin Shan */ 1435373f5657SGavin Shan if (phb->type == PNV_PHB_IODA1) { 1436184cd4a3SBenjamin Herrenschmidt pe_info(pe, "DMA weight %d, assigned %d DMA32 segments\n", 1437184cd4a3SBenjamin Herrenschmidt pe->dma_weight, segs); 1438184cd4a3SBenjamin Herrenschmidt pnv_pci_ioda_setup_dma_pe(phb, pe, base, segs); 1439373f5657SGavin Shan } else { 1440373f5657SGavin Shan pe_info(pe, "Assign DMA32 space\n"); 1441373f5657SGavin Shan segs = 0; 1442373f5657SGavin Shan pnv_pci_ioda2_setup_dma_pe(phb, pe); 1443373f5657SGavin Shan } 1444373f5657SGavin Shan 1445184cd4a3SBenjamin Herrenschmidt remaining -= segs; 1446184cd4a3SBenjamin Herrenschmidt base += segs; 1447184cd4a3SBenjamin Herrenschmidt } 1448184cd4a3SBenjamin Herrenschmidt } 1449184cd4a3SBenjamin Herrenschmidt 1450184cd4a3SBenjamin Herrenschmidt #ifdef CONFIG_PCI_MSI 1451137436c9SGavin Shan static void pnv_ioda2_msi_eoi(struct irq_data *d) 1452137436c9SGavin Shan { 1453137436c9SGavin Shan unsigned int hw_irq = (unsigned int)irqd_to_hwirq(d); 1454137436c9SGavin Shan struct irq_chip *chip = irq_data_get_irq_chip(d); 1455137436c9SGavin Shan struct pnv_phb *phb = container_of(chip, struct pnv_phb, 1456137436c9SGavin Shan ioda.irq_chip); 1457137436c9SGavin Shan int64_t rc; 1458137436c9SGavin Shan 1459137436c9SGavin Shan rc = opal_pci_msi_eoi(phb->opal_id, hw_irq); 1460137436c9SGavin Shan WARN_ON_ONCE(rc); 1461137436c9SGavin Shan 1462137436c9SGavin Shan icp_native_eoi(d); 1463137436c9SGavin Shan } 1464137436c9SGavin Shan 1465fd9a1c26SIan Munsie 1466fd9a1c26SIan Munsie static void set_msi_irq_chip(struct pnv_phb *phb, unsigned int virq) 1467fd9a1c26SIan Munsie { 1468fd9a1c26SIan Munsie struct irq_data *idata; 1469fd9a1c26SIan Munsie struct irq_chip *ichip; 1470fd9a1c26SIan Munsie 1471fd9a1c26SIan Munsie if (phb->type != PNV_PHB_IODA2) 1472fd9a1c26SIan Munsie return; 1473fd9a1c26SIan Munsie 1474fd9a1c26SIan Munsie if (!phb->ioda.irq_chip_init) { 1475fd9a1c26SIan Munsie /* 1476fd9a1c26SIan Munsie * First time we setup an MSI IRQ, we need to setup the 1477fd9a1c26SIan Munsie * corresponding IRQ chip to route correctly. 1478fd9a1c26SIan Munsie */ 1479fd9a1c26SIan Munsie idata = irq_get_irq_data(virq); 1480fd9a1c26SIan Munsie ichip = irq_data_get_irq_chip(idata); 1481fd9a1c26SIan Munsie phb->ioda.irq_chip_init = 1; 1482fd9a1c26SIan Munsie phb->ioda.irq_chip = *ichip; 1483fd9a1c26SIan Munsie phb->ioda.irq_chip.irq_eoi = pnv_ioda2_msi_eoi; 1484fd9a1c26SIan Munsie } 1485fd9a1c26SIan Munsie irq_set_chip(virq, &phb->ioda.irq_chip); 1486fd9a1c26SIan Munsie } 1487fd9a1c26SIan Munsie 148880c49c7eSIan Munsie #ifdef CONFIG_CXL_BASE 148980c49c7eSIan Munsie 14906f963ec2SRyan Grimm struct device_node *pnv_pci_get_phb_node(struct pci_dev *dev) 149180c49c7eSIan Munsie { 149280c49c7eSIan Munsie struct pci_controller *hose = pci_bus_to_host(dev->bus); 149380c49c7eSIan Munsie 14946f963ec2SRyan Grimm return of_node_get(hose->dn); 149580c49c7eSIan Munsie } 14966f963ec2SRyan Grimm EXPORT_SYMBOL(pnv_pci_get_phb_node); 149780c49c7eSIan Munsie 14981212aa1cSRyan Grimm int pnv_phb_to_cxl_mode(struct pci_dev *dev, uint64_t mode) 149980c49c7eSIan Munsie { 150080c49c7eSIan Munsie struct pci_controller *hose = pci_bus_to_host(dev->bus); 150180c49c7eSIan Munsie struct pnv_phb *phb = hose->private_data; 150280c49c7eSIan Munsie struct pnv_ioda_pe *pe; 150380c49c7eSIan Munsie int rc; 150480c49c7eSIan Munsie 150580c49c7eSIan Munsie pe = pnv_ioda_get_pe(dev); 150680c49c7eSIan Munsie if (!pe) 150780c49c7eSIan Munsie return -ENODEV; 150880c49c7eSIan Munsie 150980c49c7eSIan Munsie pe_info(pe, "Switching PHB to CXL\n"); 151080c49c7eSIan Munsie 15111212aa1cSRyan Grimm rc = opal_pci_set_phb_cxl_mode(phb->opal_id, mode, pe->pe_number); 151280c49c7eSIan Munsie if (rc) 151380c49c7eSIan Munsie dev_err(&dev->dev, "opal_pci_set_phb_cxl_mode failed: %i\n", rc); 151480c49c7eSIan Munsie 151580c49c7eSIan Munsie return rc; 151680c49c7eSIan Munsie } 15171212aa1cSRyan Grimm EXPORT_SYMBOL(pnv_phb_to_cxl_mode); 151880c49c7eSIan Munsie 151980c49c7eSIan Munsie /* Find PHB for cxl dev and allocate MSI hwirqs? 152080c49c7eSIan Munsie * Returns the absolute hardware IRQ number 152180c49c7eSIan Munsie */ 152280c49c7eSIan Munsie int pnv_cxl_alloc_hwirqs(struct pci_dev *dev, int num) 152380c49c7eSIan Munsie { 152480c49c7eSIan Munsie struct pci_controller *hose = pci_bus_to_host(dev->bus); 152580c49c7eSIan Munsie struct pnv_phb *phb = hose->private_data; 152680c49c7eSIan Munsie int hwirq = msi_bitmap_alloc_hwirqs(&phb->msi_bmp, num); 152780c49c7eSIan Munsie 152880c49c7eSIan Munsie if (hwirq < 0) { 152980c49c7eSIan Munsie dev_warn(&dev->dev, "Failed to find a free MSI\n"); 153080c49c7eSIan Munsie return -ENOSPC; 153180c49c7eSIan Munsie } 153280c49c7eSIan Munsie 153380c49c7eSIan Munsie return phb->msi_base + hwirq; 153480c49c7eSIan Munsie } 153580c49c7eSIan Munsie EXPORT_SYMBOL(pnv_cxl_alloc_hwirqs); 153680c49c7eSIan Munsie 153780c49c7eSIan Munsie void pnv_cxl_release_hwirqs(struct pci_dev *dev, int hwirq, int num) 153880c49c7eSIan Munsie { 153980c49c7eSIan Munsie struct pci_controller *hose = pci_bus_to_host(dev->bus); 154080c49c7eSIan Munsie struct pnv_phb *phb = hose->private_data; 154180c49c7eSIan Munsie 154280c49c7eSIan Munsie msi_bitmap_free_hwirqs(&phb->msi_bmp, hwirq - phb->msi_base, num); 154380c49c7eSIan Munsie } 154480c49c7eSIan Munsie EXPORT_SYMBOL(pnv_cxl_release_hwirqs); 154580c49c7eSIan Munsie 154680c49c7eSIan Munsie void pnv_cxl_release_hwirq_ranges(struct cxl_irq_ranges *irqs, 154780c49c7eSIan Munsie struct pci_dev *dev) 154880c49c7eSIan Munsie { 154980c49c7eSIan Munsie struct pci_controller *hose = pci_bus_to_host(dev->bus); 155080c49c7eSIan Munsie struct pnv_phb *phb = hose->private_data; 155180c49c7eSIan Munsie int i, hwirq; 155280c49c7eSIan Munsie 155380c49c7eSIan Munsie for (i = 1; i < CXL_IRQ_RANGES; i++) { 155480c49c7eSIan Munsie if (!irqs->range[i]) 155580c49c7eSIan Munsie continue; 155680c49c7eSIan Munsie pr_devel("cxl release irq range 0x%x: offset: 0x%lx limit: %ld\n", 155780c49c7eSIan Munsie i, irqs->offset[i], 155880c49c7eSIan Munsie irqs->range[i]); 155980c49c7eSIan Munsie hwirq = irqs->offset[i] - phb->msi_base; 156080c49c7eSIan Munsie msi_bitmap_free_hwirqs(&phb->msi_bmp, hwirq, 156180c49c7eSIan Munsie irqs->range[i]); 156280c49c7eSIan Munsie } 156380c49c7eSIan Munsie } 156480c49c7eSIan Munsie EXPORT_SYMBOL(pnv_cxl_release_hwirq_ranges); 156580c49c7eSIan Munsie 156680c49c7eSIan Munsie int pnv_cxl_alloc_hwirq_ranges(struct cxl_irq_ranges *irqs, 156780c49c7eSIan Munsie struct pci_dev *dev, int num) 156880c49c7eSIan Munsie { 156980c49c7eSIan Munsie struct pci_controller *hose = pci_bus_to_host(dev->bus); 157080c49c7eSIan Munsie struct pnv_phb *phb = hose->private_data; 157180c49c7eSIan Munsie int i, hwirq, try; 157280c49c7eSIan Munsie 157380c49c7eSIan Munsie memset(irqs, 0, sizeof(struct cxl_irq_ranges)); 157480c49c7eSIan Munsie 157580c49c7eSIan Munsie /* 0 is reserved for the multiplexed PSL DSI interrupt */ 157680c49c7eSIan Munsie for (i = 1; i < CXL_IRQ_RANGES && num; i++) { 157780c49c7eSIan Munsie try = num; 157880c49c7eSIan Munsie while (try) { 157980c49c7eSIan Munsie hwirq = msi_bitmap_alloc_hwirqs(&phb->msi_bmp, try); 158080c49c7eSIan Munsie if (hwirq >= 0) 158180c49c7eSIan Munsie break; 158280c49c7eSIan Munsie try /= 2; 158380c49c7eSIan Munsie } 158480c49c7eSIan Munsie if (!try) 158580c49c7eSIan Munsie goto fail; 158680c49c7eSIan Munsie 158780c49c7eSIan Munsie irqs->offset[i] = phb->msi_base + hwirq; 158880c49c7eSIan Munsie irqs->range[i] = try; 158980c49c7eSIan Munsie pr_devel("cxl alloc irq range 0x%x: offset: 0x%lx limit: %li\n", 159080c49c7eSIan Munsie i, irqs->offset[i], irqs->range[i]); 159180c49c7eSIan Munsie num -= try; 159280c49c7eSIan Munsie } 159380c49c7eSIan Munsie if (num) 159480c49c7eSIan Munsie goto fail; 159580c49c7eSIan Munsie 159680c49c7eSIan Munsie return 0; 159780c49c7eSIan Munsie fail: 159880c49c7eSIan Munsie pnv_cxl_release_hwirq_ranges(irqs, dev); 159980c49c7eSIan Munsie return -ENOSPC; 160080c49c7eSIan Munsie } 160180c49c7eSIan Munsie EXPORT_SYMBOL(pnv_cxl_alloc_hwirq_ranges); 160280c49c7eSIan Munsie 160380c49c7eSIan Munsie int pnv_cxl_get_irq_count(struct pci_dev *dev) 160480c49c7eSIan Munsie { 160580c49c7eSIan Munsie struct pci_controller *hose = pci_bus_to_host(dev->bus); 160680c49c7eSIan Munsie struct pnv_phb *phb = hose->private_data; 160780c49c7eSIan Munsie 160880c49c7eSIan Munsie return phb->msi_bmp.irq_count; 160980c49c7eSIan Munsie } 161080c49c7eSIan Munsie EXPORT_SYMBOL(pnv_cxl_get_irq_count); 161180c49c7eSIan Munsie 161280c49c7eSIan Munsie int pnv_cxl_ioda_msi_setup(struct pci_dev *dev, unsigned int hwirq, 161380c49c7eSIan Munsie unsigned int virq) 161480c49c7eSIan Munsie { 161580c49c7eSIan Munsie struct pci_controller *hose = pci_bus_to_host(dev->bus); 161680c49c7eSIan Munsie struct pnv_phb *phb = hose->private_data; 161780c49c7eSIan Munsie unsigned int xive_num = hwirq - phb->msi_base; 161880c49c7eSIan Munsie struct pnv_ioda_pe *pe; 161980c49c7eSIan Munsie int rc; 162080c49c7eSIan Munsie 162180c49c7eSIan Munsie if (!(pe = pnv_ioda_get_pe(dev))) 162280c49c7eSIan Munsie return -ENODEV; 162380c49c7eSIan Munsie 162480c49c7eSIan Munsie /* Assign XIVE to PE */ 162580c49c7eSIan Munsie rc = opal_pci_set_xive_pe(phb->opal_id, pe->pe_number, xive_num); 162680c49c7eSIan Munsie if (rc) { 162780c49c7eSIan Munsie pe_warn(pe, "%s: OPAL error %d setting msi_base 0x%x " 162880c49c7eSIan Munsie "hwirq 0x%x XIVE 0x%x PE\n", 162980c49c7eSIan Munsie pci_name(dev), rc, phb->msi_base, hwirq, xive_num); 163080c49c7eSIan Munsie return -EIO; 163180c49c7eSIan Munsie } 163280c49c7eSIan Munsie set_msi_irq_chip(phb, virq); 163380c49c7eSIan Munsie 163480c49c7eSIan Munsie return 0; 163580c49c7eSIan Munsie } 163680c49c7eSIan Munsie EXPORT_SYMBOL(pnv_cxl_ioda_msi_setup); 163780c49c7eSIan Munsie #endif 163880c49c7eSIan Munsie 1639184cd4a3SBenjamin Herrenschmidt static int pnv_pci_ioda_msi_setup(struct pnv_phb *phb, struct pci_dev *dev, 1640137436c9SGavin Shan unsigned int hwirq, unsigned int virq, 1641137436c9SGavin Shan unsigned int is_64, struct msi_msg *msg) 1642184cd4a3SBenjamin Herrenschmidt { 1643184cd4a3SBenjamin Herrenschmidt struct pnv_ioda_pe *pe = pnv_ioda_get_pe(dev); 1644184cd4a3SBenjamin Herrenschmidt unsigned int xive_num = hwirq - phb->msi_base; 16453a1a4661SBenjamin Herrenschmidt __be32 data; 1646184cd4a3SBenjamin Herrenschmidt int rc; 1647184cd4a3SBenjamin Herrenschmidt 1648184cd4a3SBenjamin Herrenschmidt /* No PE assigned ? bail out ... no MSI for you ! */ 1649184cd4a3SBenjamin Herrenschmidt if (pe == NULL) 1650184cd4a3SBenjamin Herrenschmidt return -ENXIO; 1651184cd4a3SBenjamin Herrenschmidt 1652184cd4a3SBenjamin Herrenschmidt /* Check if we have an MVE */ 1653184cd4a3SBenjamin Herrenschmidt if (pe->mve_number < 0) 1654184cd4a3SBenjamin Herrenschmidt return -ENXIO; 1655184cd4a3SBenjamin Herrenschmidt 1656b72c1f65SBenjamin Herrenschmidt /* Force 32-bit MSI on some broken devices */ 165736074381SBenjamin Herrenschmidt if (dev->no_64bit_msi) 1658b72c1f65SBenjamin Herrenschmidt is_64 = 0; 1659b72c1f65SBenjamin Herrenschmidt 1660184cd4a3SBenjamin Herrenschmidt /* Assign XIVE to PE */ 1661184cd4a3SBenjamin Herrenschmidt rc = opal_pci_set_xive_pe(phb->opal_id, pe->pe_number, xive_num); 1662184cd4a3SBenjamin Herrenschmidt if (rc) { 1663184cd4a3SBenjamin Herrenschmidt pr_warn("%s: OPAL error %d setting XIVE %d PE\n", 1664184cd4a3SBenjamin Herrenschmidt pci_name(dev), rc, xive_num); 1665184cd4a3SBenjamin Herrenschmidt return -EIO; 1666184cd4a3SBenjamin Herrenschmidt } 1667184cd4a3SBenjamin Herrenschmidt 1668184cd4a3SBenjamin Herrenschmidt if (is_64) { 16693a1a4661SBenjamin Herrenschmidt __be64 addr64; 16703a1a4661SBenjamin Herrenschmidt 1671184cd4a3SBenjamin Herrenschmidt rc = opal_get_msi_64(phb->opal_id, pe->mve_number, xive_num, 1, 1672184cd4a3SBenjamin Herrenschmidt &addr64, &data); 1673184cd4a3SBenjamin Herrenschmidt if (rc) { 1674184cd4a3SBenjamin Herrenschmidt pr_warn("%s: OPAL error %d getting 64-bit MSI data\n", 1675184cd4a3SBenjamin Herrenschmidt pci_name(dev), rc); 1676184cd4a3SBenjamin Herrenschmidt return -EIO; 1677184cd4a3SBenjamin Herrenschmidt } 16783a1a4661SBenjamin Herrenschmidt msg->address_hi = be64_to_cpu(addr64) >> 32; 16793a1a4661SBenjamin Herrenschmidt msg->address_lo = be64_to_cpu(addr64) & 0xfffffffful; 1680184cd4a3SBenjamin Herrenschmidt } else { 16813a1a4661SBenjamin Herrenschmidt __be32 addr32; 16823a1a4661SBenjamin Herrenschmidt 1683184cd4a3SBenjamin Herrenschmidt rc = opal_get_msi_32(phb->opal_id, pe->mve_number, xive_num, 1, 1684184cd4a3SBenjamin Herrenschmidt &addr32, &data); 1685184cd4a3SBenjamin Herrenschmidt if (rc) { 1686184cd4a3SBenjamin Herrenschmidt pr_warn("%s: OPAL error %d getting 32-bit MSI data\n", 1687184cd4a3SBenjamin Herrenschmidt pci_name(dev), rc); 1688184cd4a3SBenjamin Herrenschmidt return -EIO; 1689184cd4a3SBenjamin Herrenschmidt } 1690184cd4a3SBenjamin Herrenschmidt msg->address_hi = 0; 16913a1a4661SBenjamin Herrenschmidt msg->address_lo = be32_to_cpu(addr32); 1692184cd4a3SBenjamin Herrenschmidt } 16933a1a4661SBenjamin Herrenschmidt msg->data = be32_to_cpu(data); 1694184cd4a3SBenjamin Herrenschmidt 1695fd9a1c26SIan Munsie set_msi_irq_chip(phb, virq); 1696137436c9SGavin Shan 1697184cd4a3SBenjamin Herrenschmidt pr_devel("%s: %s-bit MSI on hwirq %x (xive #%d)," 1698184cd4a3SBenjamin Herrenschmidt " address=%x_%08x data=%x PE# %d\n", 1699184cd4a3SBenjamin Herrenschmidt pci_name(dev), is_64 ? "64" : "32", hwirq, xive_num, 1700184cd4a3SBenjamin Herrenschmidt msg->address_hi, msg->address_lo, data, pe->pe_number); 1701184cd4a3SBenjamin Herrenschmidt 1702184cd4a3SBenjamin Herrenschmidt return 0; 1703184cd4a3SBenjamin Herrenschmidt } 1704184cd4a3SBenjamin Herrenschmidt 1705184cd4a3SBenjamin Herrenschmidt static void pnv_pci_init_ioda_msis(struct pnv_phb *phb) 1706184cd4a3SBenjamin Herrenschmidt { 1707fb1b55d6SGavin Shan unsigned int count; 1708184cd4a3SBenjamin Herrenschmidt const __be32 *prop = of_get_property(phb->hose->dn, 1709184cd4a3SBenjamin Herrenschmidt "ibm,opal-msi-ranges", NULL); 1710184cd4a3SBenjamin Herrenschmidt if (!prop) { 1711184cd4a3SBenjamin Herrenschmidt /* BML Fallback */ 1712184cd4a3SBenjamin Herrenschmidt prop = of_get_property(phb->hose->dn, "msi-ranges", NULL); 1713184cd4a3SBenjamin Herrenschmidt } 1714184cd4a3SBenjamin Herrenschmidt if (!prop) 1715184cd4a3SBenjamin Herrenschmidt return; 1716184cd4a3SBenjamin Herrenschmidt 1717184cd4a3SBenjamin Herrenschmidt phb->msi_base = be32_to_cpup(prop); 1718fb1b55d6SGavin Shan count = be32_to_cpup(prop + 1); 1719fb1b55d6SGavin Shan if (msi_bitmap_alloc(&phb->msi_bmp, count, phb->hose->dn)) { 1720184cd4a3SBenjamin Herrenschmidt pr_err("PCI %d: Failed to allocate MSI bitmap !\n", 1721184cd4a3SBenjamin Herrenschmidt phb->hose->global_number); 1722184cd4a3SBenjamin Herrenschmidt return; 1723184cd4a3SBenjamin Herrenschmidt } 1724fb1b55d6SGavin Shan 1725184cd4a3SBenjamin Herrenschmidt phb->msi_setup = pnv_pci_ioda_msi_setup; 1726184cd4a3SBenjamin Herrenschmidt phb->msi32_support = 1; 1727184cd4a3SBenjamin Herrenschmidt pr_info(" Allocated bitmap for %d MSIs (base IRQ 0x%x)\n", 1728fb1b55d6SGavin Shan count, phb->msi_base); 1729184cd4a3SBenjamin Herrenschmidt } 1730184cd4a3SBenjamin Herrenschmidt #else 1731184cd4a3SBenjamin Herrenschmidt static void pnv_pci_init_ioda_msis(struct pnv_phb *phb) { } 1732184cd4a3SBenjamin Herrenschmidt #endif /* CONFIG_PCI_MSI */ 1733184cd4a3SBenjamin Herrenschmidt 173411685becSGavin Shan /* 173511685becSGavin Shan * This function is supposed to be called on basis of PE from top 173611685becSGavin Shan * to bottom style. So the the I/O or MMIO segment assigned to 173711685becSGavin Shan * parent PE could be overrided by its child PEs if necessary. 173811685becSGavin Shan */ 1739cad5cef6SGreg Kroah-Hartman static void pnv_ioda_setup_pe_seg(struct pci_controller *hose, 174011685becSGavin Shan struct pnv_ioda_pe *pe) 174111685becSGavin Shan { 174211685becSGavin Shan struct pnv_phb *phb = hose->private_data; 174311685becSGavin Shan struct pci_bus_region region; 174411685becSGavin Shan struct resource *res; 174511685becSGavin Shan int i, index; 174611685becSGavin Shan int rc; 174711685becSGavin Shan 174811685becSGavin Shan /* 174911685becSGavin Shan * NOTE: We only care PCI bus based PE for now. For PCI 175011685becSGavin Shan * device based PE, for example SRIOV sensitive VF should 175111685becSGavin Shan * be figured out later. 175211685becSGavin Shan */ 175311685becSGavin Shan BUG_ON(!(pe->flags & (PNV_IODA_PE_BUS | PNV_IODA_PE_BUS_ALL))); 175411685becSGavin Shan 175511685becSGavin Shan pci_bus_for_each_resource(pe->pbus, res, i) { 175611685becSGavin Shan if (!res || !res->flags || 175711685becSGavin Shan res->start > res->end) 175811685becSGavin Shan continue; 175911685becSGavin Shan 176011685becSGavin Shan if (res->flags & IORESOURCE_IO) { 176111685becSGavin Shan region.start = res->start - phb->ioda.io_pci_base; 176211685becSGavin Shan region.end = res->end - phb->ioda.io_pci_base; 176311685becSGavin Shan index = region.start / phb->ioda.io_segsize; 176411685becSGavin Shan 176511685becSGavin Shan while (index < phb->ioda.total_pe && 176611685becSGavin Shan region.start <= region.end) { 176711685becSGavin Shan phb->ioda.io_segmap[index] = pe->pe_number; 176811685becSGavin Shan rc = opal_pci_map_pe_mmio_window(phb->opal_id, 176911685becSGavin Shan pe->pe_number, OPAL_IO_WINDOW_TYPE, 0, index); 177011685becSGavin Shan if (rc != OPAL_SUCCESS) { 177111685becSGavin Shan pr_err("%s: OPAL error %d when mapping IO " 177211685becSGavin Shan "segment #%d to PE#%d\n", 177311685becSGavin Shan __func__, rc, index, pe->pe_number); 177411685becSGavin Shan break; 177511685becSGavin Shan } 177611685becSGavin Shan 177711685becSGavin Shan region.start += phb->ioda.io_segsize; 177811685becSGavin Shan index++; 177911685becSGavin Shan } 1780027fa02fSGavin Shan } else if ((res->flags & IORESOURCE_MEM) && 1781027fa02fSGavin Shan !pnv_pci_is_mem_pref_64(res->flags)) { 178211685becSGavin Shan region.start = res->start - 17833fd47f06SBenjamin Herrenschmidt hose->mem_offset[0] - 178411685becSGavin Shan phb->ioda.m32_pci_base; 178511685becSGavin Shan region.end = res->end - 17863fd47f06SBenjamin Herrenschmidt hose->mem_offset[0] - 178711685becSGavin Shan phb->ioda.m32_pci_base; 178811685becSGavin Shan index = region.start / phb->ioda.m32_segsize; 178911685becSGavin Shan 179011685becSGavin Shan while (index < phb->ioda.total_pe && 179111685becSGavin Shan region.start <= region.end) { 179211685becSGavin Shan phb->ioda.m32_segmap[index] = pe->pe_number; 179311685becSGavin Shan rc = opal_pci_map_pe_mmio_window(phb->opal_id, 179411685becSGavin Shan pe->pe_number, OPAL_M32_WINDOW_TYPE, 0, index); 179511685becSGavin Shan if (rc != OPAL_SUCCESS) { 179611685becSGavin Shan pr_err("%s: OPAL error %d when mapping M32 " 179711685becSGavin Shan "segment#%d to PE#%d", 179811685becSGavin Shan __func__, rc, index, pe->pe_number); 179911685becSGavin Shan break; 180011685becSGavin Shan } 180111685becSGavin Shan 180211685becSGavin Shan region.start += phb->ioda.m32_segsize; 180311685becSGavin Shan index++; 180411685becSGavin Shan } 180511685becSGavin Shan } 180611685becSGavin Shan } 180711685becSGavin Shan } 180811685becSGavin Shan 1809cad5cef6SGreg Kroah-Hartman static void pnv_pci_ioda_setup_seg(void) 181011685becSGavin Shan { 181111685becSGavin Shan struct pci_controller *tmp, *hose; 181211685becSGavin Shan struct pnv_phb *phb; 181311685becSGavin Shan struct pnv_ioda_pe *pe; 181411685becSGavin Shan 181511685becSGavin Shan list_for_each_entry_safe(hose, tmp, &hose_list, list_node) { 181611685becSGavin Shan phb = hose->private_data; 181711685becSGavin Shan list_for_each_entry(pe, &phb->ioda.pe_list, list) { 181811685becSGavin Shan pnv_ioda_setup_pe_seg(hose, pe); 181911685becSGavin Shan } 182011685becSGavin Shan } 182111685becSGavin Shan } 182211685becSGavin Shan 1823cad5cef6SGreg Kroah-Hartman static void pnv_pci_ioda_setup_DMA(void) 182413395c48SGavin Shan { 182513395c48SGavin Shan struct pci_controller *hose, *tmp; 1826db1266c8SGavin Shan struct pnv_phb *phb; 182713395c48SGavin Shan 182813395c48SGavin Shan list_for_each_entry_safe(hose, tmp, &hose_list, list_node) { 182913395c48SGavin Shan pnv_ioda_setup_dma(hose->private_data); 1830db1266c8SGavin Shan 1831db1266c8SGavin Shan /* Mark the PHB initialization done */ 1832db1266c8SGavin Shan phb = hose->private_data; 1833db1266c8SGavin Shan phb->initialized = 1; 183413395c48SGavin Shan } 183513395c48SGavin Shan } 183613395c48SGavin Shan 183737c367f2SGavin Shan static void pnv_pci_ioda_create_dbgfs(void) 183837c367f2SGavin Shan { 183937c367f2SGavin Shan #ifdef CONFIG_DEBUG_FS 184037c367f2SGavin Shan struct pci_controller *hose, *tmp; 184137c367f2SGavin Shan struct pnv_phb *phb; 184237c367f2SGavin Shan char name[16]; 184337c367f2SGavin Shan 184437c367f2SGavin Shan list_for_each_entry_safe(hose, tmp, &hose_list, list_node) { 184537c367f2SGavin Shan phb = hose->private_data; 184637c367f2SGavin Shan 184737c367f2SGavin Shan sprintf(name, "PCI%04x", hose->global_number); 184837c367f2SGavin Shan phb->dbgfs = debugfs_create_dir(name, powerpc_debugfs_root); 184937c367f2SGavin Shan if (!phb->dbgfs) 185037c367f2SGavin Shan pr_warning("%s: Error on creating debugfs on PHB#%x\n", 185137c367f2SGavin Shan __func__, hose->global_number); 185237c367f2SGavin Shan } 185337c367f2SGavin Shan #endif /* CONFIG_DEBUG_FS */ 185437c367f2SGavin Shan } 185537c367f2SGavin Shan 1856cad5cef6SGreg Kroah-Hartman static void pnv_pci_ioda_fixup(void) 1857fb446ad0SGavin Shan { 1858fb446ad0SGavin Shan pnv_pci_ioda_setup_PEs(); 185911685becSGavin Shan pnv_pci_ioda_setup_seg(); 186013395c48SGavin Shan pnv_pci_ioda_setup_DMA(); 1861e9cc17d4SGavin Shan 186237c367f2SGavin Shan pnv_pci_ioda_create_dbgfs(); 186337c367f2SGavin Shan 1864e9cc17d4SGavin Shan #ifdef CONFIG_EEH 1865e9cc17d4SGavin Shan eeh_init(); 1866dadcd6d6SMike Qiu eeh_addr_cache_build(); 1867e9cc17d4SGavin Shan #endif 1868fb446ad0SGavin Shan } 1869fb446ad0SGavin Shan 1870271fd03aSGavin Shan /* 1871271fd03aSGavin Shan * Returns the alignment for I/O or memory windows for P2P 1872271fd03aSGavin Shan * bridges. That actually depends on how PEs are segmented. 1873271fd03aSGavin Shan * For now, we return I/O or M32 segment size for PE sensitive 1874271fd03aSGavin Shan * P2P bridges. Otherwise, the default values (4KiB for I/O, 1875271fd03aSGavin Shan * 1MiB for memory) will be returned. 1876271fd03aSGavin Shan * 1877271fd03aSGavin Shan * The current PCI bus might be put into one PE, which was 1878271fd03aSGavin Shan * create against the parent PCI bridge. For that case, we 1879271fd03aSGavin Shan * needn't enlarge the alignment so that we can save some 1880271fd03aSGavin Shan * resources. 1881271fd03aSGavin Shan */ 1882271fd03aSGavin Shan static resource_size_t pnv_pci_window_alignment(struct pci_bus *bus, 1883271fd03aSGavin Shan unsigned long type) 1884271fd03aSGavin Shan { 1885271fd03aSGavin Shan struct pci_dev *bridge; 1886271fd03aSGavin Shan struct pci_controller *hose = pci_bus_to_host(bus); 1887271fd03aSGavin Shan struct pnv_phb *phb = hose->private_data; 1888271fd03aSGavin Shan int num_pci_bridges = 0; 1889271fd03aSGavin Shan 1890271fd03aSGavin Shan bridge = bus->self; 1891271fd03aSGavin Shan while (bridge) { 1892271fd03aSGavin Shan if (pci_pcie_type(bridge) == PCI_EXP_TYPE_PCI_BRIDGE) { 1893271fd03aSGavin Shan num_pci_bridges++; 1894271fd03aSGavin Shan if (num_pci_bridges >= 2) 1895271fd03aSGavin Shan return 1; 1896271fd03aSGavin Shan } 1897271fd03aSGavin Shan 1898271fd03aSGavin Shan bridge = bridge->bus->self; 1899271fd03aSGavin Shan } 1900271fd03aSGavin Shan 1901262af557SGuo Chao /* We fail back to M32 if M64 isn't supported */ 1902262af557SGuo Chao if (phb->ioda.m64_segsize && 1903262af557SGuo Chao pnv_pci_is_mem_pref_64(type)) 1904262af557SGuo Chao return phb->ioda.m64_segsize; 1905271fd03aSGavin Shan if (type & IORESOURCE_MEM) 1906271fd03aSGavin Shan return phb->ioda.m32_segsize; 1907271fd03aSGavin Shan 1908271fd03aSGavin Shan return phb->ioda.io_segsize; 1909271fd03aSGavin Shan } 1910271fd03aSGavin Shan 1911184cd4a3SBenjamin Herrenschmidt /* Prevent enabling devices for which we couldn't properly 1912184cd4a3SBenjamin Herrenschmidt * assign a PE 1913184cd4a3SBenjamin Herrenschmidt */ 1914c88c2a18SDaniel Axtens static bool pnv_pci_enable_device_hook(struct pci_dev *dev) 1915184cd4a3SBenjamin Herrenschmidt { 1916db1266c8SGavin Shan struct pci_controller *hose = pci_bus_to_host(dev->bus); 1917db1266c8SGavin Shan struct pnv_phb *phb = hose->private_data; 1918db1266c8SGavin Shan struct pci_dn *pdn; 1919184cd4a3SBenjamin Herrenschmidt 1920db1266c8SGavin Shan /* The function is probably called while the PEs have 1921db1266c8SGavin Shan * not be created yet. For example, resource reassignment 1922db1266c8SGavin Shan * during PCI probe period. We just skip the check if 1923db1266c8SGavin Shan * PEs isn't ready. 1924db1266c8SGavin Shan */ 1925db1266c8SGavin Shan if (!phb->initialized) 1926c88c2a18SDaniel Axtens return true; 1927db1266c8SGavin Shan 1928b72c1f65SBenjamin Herrenschmidt pdn = pci_get_pdn(dev); 1929184cd4a3SBenjamin Herrenschmidt if (!pdn || pdn->pe_number == IODA_INVALID_PE) 1930c88c2a18SDaniel Axtens return false; 1931db1266c8SGavin Shan 1932c88c2a18SDaniel Axtens return true; 1933184cd4a3SBenjamin Herrenschmidt } 1934184cd4a3SBenjamin Herrenschmidt 1935184cd4a3SBenjamin Herrenschmidt static u32 pnv_ioda_bdfn_to_pe(struct pnv_phb *phb, struct pci_bus *bus, 1936184cd4a3SBenjamin Herrenschmidt u32 devfn) 1937184cd4a3SBenjamin Herrenschmidt { 1938184cd4a3SBenjamin Herrenschmidt return phb->ioda.pe_rmap[(bus->number << 8) | devfn]; 1939184cd4a3SBenjamin Herrenschmidt } 1940184cd4a3SBenjamin Herrenschmidt 194173ed148aSBenjamin Herrenschmidt static void pnv_pci_ioda_shutdown(struct pnv_phb *phb) 194273ed148aSBenjamin Herrenschmidt { 1943d1a85eeeSGavin Shan opal_pci_reset(phb->opal_id, OPAL_RESET_PCI_IODA_TABLE, 194473ed148aSBenjamin Herrenschmidt OPAL_ASSERT_RESET); 194573ed148aSBenjamin Herrenschmidt } 194673ed148aSBenjamin Herrenschmidt 1947e51df2c1SAnton Blanchard static void __init pnv_pci_init_ioda_phb(struct device_node *np, 1948e9cc17d4SGavin Shan u64 hub_id, int ioda_type) 1949184cd4a3SBenjamin Herrenschmidt { 1950184cd4a3SBenjamin Herrenschmidt struct pci_controller *hose; 1951184cd4a3SBenjamin Herrenschmidt struct pnv_phb *phb; 19528184616fSGavin Shan unsigned long size, m32map_off, pemap_off, iomap_off = 0; 1953c681b93cSAlistair Popple const __be64 *prop64; 19543a1a4661SBenjamin Herrenschmidt const __be32 *prop32; 1955f1b7cc3eSGavin Shan int len; 1956184cd4a3SBenjamin Herrenschmidt u64 phb_id; 1957184cd4a3SBenjamin Herrenschmidt void *aux; 1958184cd4a3SBenjamin Herrenschmidt long rc; 1959184cd4a3SBenjamin Herrenschmidt 1960aa0c033fSGavin Shan pr_info("Initializing IODA%d OPAL PHB %s\n", ioda_type, np->full_name); 1961184cd4a3SBenjamin Herrenschmidt 1962184cd4a3SBenjamin Herrenschmidt prop64 = of_get_property(np, "ibm,opal-phbid", NULL); 1963184cd4a3SBenjamin Herrenschmidt if (!prop64) { 1964184cd4a3SBenjamin Herrenschmidt pr_err(" Missing \"ibm,opal-phbid\" property !\n"); 1965184cd4a3SBenjamin Herrenschmidt return; 1966184cd4a3SBenjamin Herrenschmidt } 1967184cd4a3SBenjamin Herrenschmidt phb_id = be64_to_cpup(prop64); 1968184cd4a3SBenjamin Herrenschmidt pr_debug(" PHB-ID : 0x%016llx\n", phb_id); 1969184cd4a3SBenjamin Herrenschmidt 1970e39f223fSMichael Ellerman phb = memblock_virt_alloc(sizeof(struct pnv_phb), 0); 197158d714ecSGavin Shan 197258d714ecSGavin Shan /* Allocate PCI controller */ 1973184cd4a3SBenjamin Herrenschmidt phb->hose = hose = pcibios_alloc_controller(np); 197458d714ecSGavin Shan if (!phb->hose) { 197558d714ecSGavin Shan pr_err(" Can't allocate PCI controller for %s\n", 1976184cd4a3SBenjamin Herrenschmidt np->full_name); 1977e39f223fSMichael Ellerman memblock_free(__pa(phb), sizeof(struct pnv_phb)); 1978184cd4a3SBenjamin Herrenschmidt return; 1979184cd4a3SBenjamin Herrenschmidt } 1980184cd4a3SBenjamin Herrenschmidt 1981184cd4a3SBenjamin Herrenschmidt spin_lock_init(&phb->lock); 1982f1b7cc3eSGavin Shan prop32 = of_get_property(np, "bus-range", &len); 1983f1b7cc3eSGavin Shan if (prop32 && len == 8) { 19843a1a4661SBenjamin Herrenschmidt hose->first_busno = be32_to_cpu(prop32[0]); 19853a1a4661SBenjamin Herrenschmidt hose->last_busno = be32_to_cpu(prop32[1]); 1986f1b7cc3eSGavin Shan } else { 1987f1b7cc3eSGavin Shan pr_warn(" Broken <bus-range> on %s\n", np->full_name); 1988184cd4a3SBenjamin Herrenschmidt hose->first_busno = 0; 1989184cd4a3SBenjamin Herrenschmidt hose->last_busno = 0xff; 1990f1b7cc3eSGavin Shan } 1991184cd4a3SBenjamin Herrenschmidt hose->private_data = phb; 1992e9cc17d4SGavin Shan phb->hub_id = hub_id; 1993184cd4a3SBenjamin Herrenschmidt phb->opal_id = phb_id; 1994aa0c033fSGavin Shan phb->type = ioda_type; 1995184cd4a3SBenjamin Herrenschmidt 1996cee72d5bSBenjamin Herrenschmidt /* Detect specific models for error handling */ 1997cee72d5bSBenjamin Herrenschmidt if (of_device_is_compatible(np, "ibm,p7ioc-pciex")) 1998cee72d5bSBenjamin Herrenschmidt phb->model = PNV_PHB_MODEL_P7IOC; 1999f3d40c25SBenjamin Herrenschmidt else if (of_device_is_compatible(np, "ibm,power8-pciex")) 2000aa0c033fSGavin Shan phb->model = PNV_PHB_MODEL_PHB3; 2001cee72d5bSBenjamin Herrenschmidt else 2002cee72d5bSBenjamin Herrenschmidt phb->model = PNV_PHB_MODEL_UNKNOWN; 2003cee72d5bSBenjamin Herrenschmidt 2004aa0c033fSGavin Shan /* Parse 32-bit and IO ranges (if any) */ 20052f1ec02eSGavin Shan pci_process_bridge_OF_ranges(hose, np, !hose->global_number); 2006184cd4a3SBenjamin Herrenschmidt 2007aa0c033fSGavin Shan /* Get registers */ 2008184cd4a3SBenjamin Herrenschmidt phb->regs = of_iomap(np, 0); 2009184cd4a3SBenjamin Herrenschmidt if (phb->regs == NULL) 2010184cd4a3SBenjamin Herrenschmidt pr_err(" Failed to map registers !\n"); 2011184cd4a3SBenjamin Herrenschmidt 2012184cd4a3SBenjamin Herrenschmidt /* Initialize more IODA stuff */ 2013aa0c033fSGavin Shan phb->ioda.total_pe = 1; 201436954dc7SGavin Shan prop32 = of_get_property(np, "ibm,opal-num-pes", NULL); 201536954dc7SGavin Shan if (prop32) 20163a1a4661SBenjamin Herrenschmidt phb->ioda.total_pe = be32_to_cpup(prop32); 201736954dc7SGavin Shan prop32 = of_get_property(np, "ibm,opal-reserved-pe", NULL); 201836954dc7SGavin Shan if (prop32) 201936954dc7SGavin Shan phb->ioda.reserved_pe = be32_to_cpup(prop32); 2020262af557SGuo Chao 2021262af557SGuo Chao /* Parse 64-bit MMIO range */ 2022262af557SGuo Chao pnv_ioda_parse_m64_window(phb); 2023262af557SGuo Chao 2024184cd4a3SBenjamin Herrenschmidt phb->ioda.m32_size = resource_size(&hose->mem_resources[0]); 2025aa0c033fSGavin Shan /* FW Has already off top 64k of M32 space (MSI space) */ 2026184cd4a3SBenjamin Herrenschmidt phb->ioda.m32_size += 0x10000; 2027184cd4a3SBenjamin Herrenschmidt 2028184cd4a3SBenjamin Herrenschmidt phb->ioda.m32_segsize = phb->ioda.m32_size / phb->ioda.total_pe; 20293fd47f06SBenjamin Herrenschmidt phb->ioda.m32_pci_base = hose->mem_resources[0].start - hose->mem_offset[0]; 2030184cd4a3SBenjamin Herrenschmidt phb->ioda.io_size = hose->pci_io_size; 2031184cd4a3SBenjamin Herrenschmidt phb->ioda.io_segsize = phb->ioda.io_size / phb->ioda.total_pe; 2032184cd4a3SBenjamin Herrenschmidt phb->ioda.io_pci_base = 0; /* XXX calculate this ? */ 2033184cd4a3SBenjamin Herrenschmidt 2034c35d2a8cSGavin Shan /* Allocate aux data & arrays. We don't have IO ports on PHB3 */ 2035184cd4a3SBenjamin Herrenschmidt size = _ALIGN_UP(phb->ioda.total_pe / 8, sizeof(unsigned long)); 2036184cd4a3SBenjamin Herrenschmidt m32map_off = size; 2037e47747f4SGavin Shan size += phb->ioda.total_pe * sizeof(phb->ioda.m32_segmap[0]); 2038c35d2a8cSGavin Shan if (phb->type == PNV_PHB_IODA1) { 2039c35d2a8cSGavin Shan iomap_off = size; 2040e47747f4SGavin Shan size += phb->ioda.total_pe * sizeof(phb->ioda.io_segmap[0]); 2041c35d2a8cSGavin Shan } 2042184cd4a3SBenjamin Herrenschmidt pemap_off = size; 2043184cd4a3SBenjamin Herrenschmidt size += phb->ioda.total_pe * sizeof(struct pnv_ioda_pe); 2044e39f223fSMichael Ellerman aux = memblock_virt_alloc(size, 0); 2045184cd4a3SBenjamin Herrenschmidt phb->ioda.pe_alloc = aux; 2046184cd4a3SBenjamin Herrenschmidt phb->ioda.m32_segmap = aux + m32map_off; 2047c35d2a8cSGavin Shan if (phb->type == PNV_PHB_IODA1) 2048184cd4a3SBenjamin Herrenschmidt phb->ioda.io_segmap = aux + iomap_off; 2049184cd4a3SBenjamin Herrenschmidt phb->ioda.pe_array = aux + pemap_off; 205036954dc7SGavin Shan set_bit(phb->ioda.reserved_pe, phb->ioda.pe_alloc); 2051184cd4a3SBenjamin Herrenschmidt 20527ebdf956SGavin Shan INIT_LIST_HEAD(&phb->ioda.pe_dma_list); 2053184cd4a3SBenjamin Herrenschmidt INIT_LIST_HEAD(&phb->ioda.pe_list); 2054184cd4a3SBenjamin Herrenschmidt 2055184cd4a3SBenjamin Herrenschmidt /* Calculate how many 32-bit TCE segments we have */ 2056184cd4a3SBenjamin Herrenschmidt phb->ioda.tce32_count = phb->ioda.m32_pci_base >> 28; 2057184cd4a3SBenjamin Herrenschmidt 2058aa0c033fSGavin Shan #if 0 /* We should really do that ... */ 2059184cd4a3SBenjamin Herrenschmidt rc = opal_pci_set_phb_mem_window(opal->phb_id, 2060184cd4a3SBenjamin Herrenschmidt window_type, 2061184cd4a3SBenjamin Herrenschmidt window_num, 2062184cd4a3SBenjamin Herrenschmidt starting_real_address, 2063184cd4a3SBenjamin Herrenschmidt starting_pci_address, 2064184cd4a3SBenjamin Herrenschmidt segment_size); 2065184cd4a3SBenjamin Herrenschmidt #endif 2066184cd4a3SBenjamin Herrenschmidt 2067262af557SGuo Chao pr_info(" %03d (%03d) PE's M32: 0x%x [segment=0x%x]\n", 2068262af557SGuo Chao phb->ioda.total_pe, phb->ioda.reserved_pe, 2069262af557SGuo Chao phb->ioda.m32_size, phb->ioda.m32_segsize); 2070262af557SGuo Chao if (phb->ioda.m64_size) 2071262af557SGuo Chao pr_info(" M64: 0x%lx [segment=0x%lx]\n", 2072262af557SGuo Chao phb->ioda.m64_size, phb->ioda.m64_segsize); 2073262af557SGuo Chao if (phb->ioda.io_size) 2074262af557SGuo Chao pr_info(" IO: 0x%x [segment=0x%x]\n", 2075184cd4a3SBenjamin Herrenschmidt phb->ioda.io_size, phb->ioda.io_segsize); 2076184cd4a3SBenjamin Herrenschmidt 2077262af557SGuo Chao 2078184cd4a3SBenjamin Herrenschmidt phb->hose->ops = &pnv_pci_ops; 207949dec922SGavin Shan phb->get_pe_state = pnv_ioda_get_pe_state; 208049dec922SGavin Shan phb->freeze_pe = pnv_ioda_freeze_pe; 208149dec922SGavin Shan phb->unfreeze_pe = pnv_ioda_unfreeze_pe; 2082184cd4a3SBenjamin Herrenschmidt 2083184cd4a3SBenjamin Herrenschmidt /* Setup RID -> PE mapping function */ 2084184cd4a3SBenjamin Herrenschmidt phb->bdfn_to_pe = pnv_ioda_bdfn_to_pe; 2085184cd4a3SBenjamin Herrenschmidt 2086184cd4a3SBenjamin Herrenschmidt /* Setup TCEs */ 2087184cd4a3SBenjamin Herrenschmidt phb->dma_dev_setup = pnv_pci_ioda_dma_dev_setup; 2088cd15b048SBenjamin Herrenschmidt phb->dma_set_mask = pnv_pci_ioda_dma_set_mask; 2089fe7e85c6SGavin Shan phb->dma_get_required_mask = pnv_pci_ioda_dma_get_required_mask; 2090184cd4a3SBenjamin Herrenschmidt 209173ed148aSBenjamin Herrenschmidt /* Setup shutdown function for kexec */ 209273ed148aSBenjamin Herrenschmidt phb->shutdown = pnv_pci_ioda_shutdown; 209373ed148aSBenjamin Herrenschmidt 2094184cd4a3SBenjamin Herrenschmidt /* Setup MSI support */ 2095184cd4a3SBenjamin Herrenschmidt pnv_pci_init_ioda_msis(phb); 2096184cd4a3SBenjamin Herrenschmidt 2097c40a4210SGavin Shan /* 2098c40a4210SGavin Shan * We pass the PCI probe flag PCI_REASSIGN_ALL_RSRC here 2099c40a4210SGavin Shan * to let the PCI core do resource assignment. It's supposed 2100c40a4210SGavin Shan * that the PCI core will do correct I/O and MMIO alignment 2101c40a4210SGavin Shan * for the P2P bridge bars so that each PCI bus (excluding 2102c40a4210SGavin Shan * the child P2P bridges) can form individual PE. 2103184cd4a3SBenjamin Herrenschmidt */ 2104fb446ad0SGavin Shan ppc_md.pcibios_fixup = pnv_pci_ioda_fixup; 2105184cd4a3SBenjamin Herrenschmidt ppc_md.pcibios_enable_device_hook = pnv_pci_enable_device_hook; 2106271fd03aSGavin Shan ppc_md.pcibios_window_alignment = pnv_pci_window_alignment; 2107d92a208dSGavin Shan ppc_md.pcibios_reset_secondary_bus = pnv_pci_reset_secondary_bus; 2108c40a4210SGavin Shan pci_add_flags(PCI_REASSIGN_ALL_RSRC); 2109184cd4a3SBenjamin Herrenschmidt 2110184cd4a3SBenjamin Herrenschmidt /* Reset IODA tables to a clean state */ 2111d1a85eeeSGavin Shan rc = opal_pci_reset(phb_id, OPAL_RESET_PCI_IODA_TABLE, OPAL_ASSERT_RESET); 2112184cd4a3SBenjamin Herrenschmidt if (rc) 2113f11fe552SBenjamin Herrenschmidt pr_warning(" OPAL Error %ld performing IODA table reset !\n", rc); 2114361f2a2aSGavin Shan 2115361f2a2aSGavin Shan /* If we're running in kdump kerenl, the previous kerenl never 2116361f2a2aSGavin Shan * shutdown PCI devices correctly. We already got IODA table 2117361f2a2aSGavin Shan * cleaned out. So we have to issue PHB reset to stop all PCI 2118361f2a2aSGavin Shan * transactions from previous kerenl. 2119361f2a2aSGavin Shan */ 2120361f2a2aSGavin Shan if (is_kdump_kernel()) { 2121361f2a2aSGavin Shan pr_info(" Issue PHB reset ...\n"); 2122cadf364dSGavin Shan pnv_eeh_phb_reset(hose, EEH_RESET_FUNDAMENTAL); 2123cadf364dSGavin Shan pnv_eeh_phb_reset(hose, EEH_RESET_DEACTIVATE); 2124361f2a2aSGavin Shan } 2125262af557SGuo Chao 21269e9e8935SGavin Shan /* Remove M64 resource if we can't configure it successfully */ 21279e9e8935SGavin Shan if (!phb->init_m64 || phb->init_m64(phb)) 2128262af557SGuo Chao hose->mem_resources[1].flags = 0; 2129184cd4a3SBenjamin Herrenschmidt } 2130184cd4a3SBenjamin Herrenschmidt 213167975005SBjorn Helgaas void __init pnv_pci_init_ioda2_phb(struct device_node *np) 2132aa0c033fSGavin Shan { 2133e9cc17d4SGavin Shan pnv_pci_init_ioda_phb(np, 0, PNV_PHB_IODA2); 2134aa0c033fSGavin Shan } 2135aa0c033fSGavin Shan 2136184cd4a3SBenjamin Herrenschmidt void __init pnv_pci_init_ioda_hub(struct device_node *np) 2137184cd4a3SBenjamin Herrenschmidt { 2138184cd4a3SBenjamin Herrenschmidt struct device_node *phbn; 2139c681b93cSAlistair Popple const __be64 *prop64; 2140184cd4a3SBenjamin Herrenschmidt u64 hub_id; 2141184cd4a3SBenjamin Herrenschmidt 2142184cd4a3SBenjamin Herrenschmidt pr_info("Probing IODA IO-Hub %s\n", np->full_name); 2143184cd4a3SBenjamin Herrenschmidt 2144184cd4a3SBenjamin Herrenschmidt prop64 = of_get_property(np, "ibm,opal-hubid", NULL); 2145184cd4a3SBenjamin Herrenschmidt if (!prop64) { 2146184cd4a3SBenjamin Herrenschmidt pr_err(" Missing \"ibm,opal-hubid\" property !\n"); 2147184cd4a3SBenjamin Herrenschmidt return; 2148184cd4a3SBenjamin Herrenschmidt } 2149184cd4a3SBenjamin Herrenschmidt hub_id = be64_to_cpup(prop64); 2150184cd4a3SBenjamin Herrenschmidt pr_devel(" HUB-ID : 0x%016llx\n", hub_id); 2151184cd4a3SBenjamin Herrenschmidt 2152184cd4a3SBenjamin Herrenschmidt /* Count child PHBs */ 2153184cd4a3SBenjamin Herrenschmidt for_each_child_of_node(np, phbn) { 2154184cd4a3SBenjamin Herrenschmidt /* Look for IODA1 PHBs */ 2155184cd4a3SBenjamin Herrenschmidt if (of_device_is_compatible(phbn, "ibm,ioda-phb")) 2156e9cc17d4SGavin Shan pnv_pci_init_ioda_phb(phbn, hub_id, PNV_PHB_IODA1); 2157184cd4a3SBenjamin Herrenschmidt } 2158184cd4a3SBenjamin Herrenschmidt } 2159