1184cd4a3SBenjamin Herrenschmidt /* 2184cd4a3SBenjamin Herrenschmidt * Support PCI/PCIe on PowerNV platforms 3184cd4a3SBenjamin Herrenschmidt * 4184cd4a3SBenjamin Herrenschmidt * Copyright 2011 Benjamin Herrenschmidt, IBM Corp. 5184cd4a3SBenjamin Herrenschmidt * 6184cd4a3SBenjamin Herrenschmidt * This program is free software; you can redistribute it and/or 7184cd4a3SBenjamin Herrenschmidt * modify it under the terms of the GNU General Public License 8184cd4a3SBenjamin Herrenschmidt * as published by the Free Software Foundation; either version 9184cd4a3SBenjamin Herrenschmidt * 2 of the License, or (at your option) any later version. 10184cd4a3SBenjamin Herrenschmidt */ 11184cd4a3SBenjamin Herrenschmidt 12cee72d5bSBenjamin Herrenschmidt #undef DEBUG 13184cd4a3SBenjamin Herrenschmidt 14184cd4a3SBenjamin Herrenschmidt #include <linux/kernel.h> 15184cd4a3SBenjamin Herrenschmidt #include <linux/pci.h> 1637c367f2SGavin Shan #include <linux/debugfs.h> 17184cd4a3SBenjamin Herrenschmidt #include <linux/delay.h> 18184cd4a3SBenjamin Herrenschmidt #include <linux/string.h> 19184cd4a3SBenjamin Herrenschmidt #include <linux/init.h> 20184cd4a3SBenjamin Herrenschmidt #include <linux/bootmem.h> 21184cd4a3SBenjamin Herrenschmidt #include <linux/irq.h> 22184cd4a3SBenjamin Herrenschmidt #include <linux/io.h> 23184cd4a3SBenjamin Herrenschmidt #include <linux/msi.h> 24184cd4a3SBenjamin Herrenschmidt 25184cd4a3SBenjamin Herrenschmidt #include <asm/sections.h> 26184cd4a3SBenjamin Herrenschmidt #include <asm/io.h> 27184cd4a3SBenjamin Herrenschmidt #include <asm/prom.h> 28184cd4a3SBenjamin Herrenschmidt #include <asm/pci-bridge.h> 29184cd4a3SBenjamin Herrenschmidt #include <asm/machdep.h> 30fb1b55d6SGavin Shan #include <asm/msi_bitmap.h> 31184cd4a3SBenjamin Herrenschmidt #include <asm/ppc-pci.h> 32184cd4a3SBenjamin Herrenschmidt #include <asm/opal.h> 33184cd4a3SBenjamin Herrenschmidt #include <asm/iommu.h> 34184cd4a3SBenjamin Herrenschmidt #include <asm/tce.h> 35137436c9SGavin Shan #include <asm/xics.h> 3637c367f2SGavin Shan #include <asm/debug.h> 37184cd4a3SBenjamin Herrenschmidt 38184cd4a3SBenjamin Herrenschmidt #include "powernv.h" 39184cd4a3SBenjamin Herrenschmidt #include "pci.h" 40184cd4a3SBenjamin Herrenschmidt 41184cd4a3SBenjamin Herrenschmidt #define define_pe_printk_level(func, kern_level) \ 42184cd4a3SBenjamin Herrenschmidt static int func(const struct pnv_ioda_pe *pe, const char *fmt, ...) \ 43184cd4a3SBenjamin Herrenschmidt { \ 44184cd4a3SBenjamin Herrenschmidt struct va_format vaf; \ 45184cd4a3SBenjamin Herrenschmidt va_list args; \ 46490e078dSGavin Shan char pfix[32]; \ 47184cd4a3SBenjamin Herrenschmidt int r; \ 48184cd4a3SBenjamin Herrenschmidt \ 49184cd4a3SBenjamin Herrenschmidt va_start(args, fmt); \ 50184cd4a3SBenjamin Herrenschmidt \ 51184cd4a3SBenjamin Herrenschmidt vaf.fmt = fmt; \ 52184cd4a3SBenjamin Herrenschmidt vaf.va = &args; \ 53184cd4a3SBenjamin Herrenschmidt \ 54490e078dSGavin Shan if (pe->pdev) \ 55490e078dSGavin Shan strlcpy(pfix, dev_name(&pe->pdev->dev), \ 56490e078dSGavin Shan sizeof(pfix)); \ 57490e078dSGavin Shan else \ 58490e078dSGavin Shan sprintf(pfix, "%04x:%02x ", \ 59490e078dSGavin Shan pci_domain_nr(pe->pbus), \ 60490e078dSGavin Shan pe->pbus->number); \ 61490e078dSGavin Shan r = printk(kern_level "pci %s: [PE# %.3d] %pV", \ 62490e078dSGavin Shan pfix, pe->pe_number, &vaf); \ 63490e078dSGavin Shan \ 64184cd4a3SBenjamin Herrenschmidt va_end(args); \ 65184cd4a3SBenjamin Herrenschmidt \ 66184cd4a3SBenjamin Herrenschmidt return r; \ 67184cd4a3SBenjamin Herrenschmidt } \ 68184cd4a3SBenjamin Herrenschmidt 69184cd4a3SBenjamin Herrenschmidt define_pe_printk_level(pe_err, KERN_ERR); 70184cd4a3SBenjamin Herrenschmidt define_pe_printk_level(pe_warn, KERN_WARNING); 71184cd4a3SBenjamin Herrenschmidt define_pe_printk_level(pe_info, KERN_INFO); 72184cd4a3SBenjamin Herrenschmidt 73cad5cef6SGreg Kroah-Hartman static int pnv_ioda_alloc_pe(struct pnv_phb *phb) 74184cd4a3SBenjamin Herrenschmidt { 75184cd4a3SBenjamin Herrenschmidt unsigned long pe; 76184cd4a3SBenjamin Herrenschmidt 77184cd4a3SBenjamin Herrenschmidt do { 78184cd4a3SBenjamin Herrenschmidt pe = find_next_zero_bit(phb->ioda.pe_alloc, 79184cd4a3SBenjamin Herrenschmidt phb->ioda.total_pe, 0); 80184cd4a3SBenjamin Herrenschmidt if (pe >= phb->ioda.total_pe) 81184cd4a3SBenjamin Herrenschmidt return IODA_INVALID_PE; 82184cd4a3SBenjamin Herrenschmidt } while(test_and_set_bit(pe, phb->ioda.pe_alloc)); 83184cd4a3SBenjamin Herrenschmidt 844cce9550SGavin Shan phb->ioda.pe_array[pe].phb = phb; 85184cd4a3SBenjamin Herrenschmidt phb->ioda.pe_array[pe].pe_number = pe; 86184cd4a3SBenjamin Herrenschmidt return pe; 87184cd4a3SBenjamin Herrenschmidt } 88184cd4a3SBenjamin Herrenschmidt 89cad5cef6SGreg Kroah-Hartman static void pnv_ioda_free_pe(struct pnv_phb *phb, int pe) 90184cd4a3SBenjamin Herrenschmidt { 91184cd4a3SBenjamin Herrenschmidt WARN_ON(phb->ioda.pe_array[pe].pdev); 92184cd4a3SBenjamin Herrenschmidt 93184cd4a3SBenjamin Herrenschmidt memset(&phb->ioda.pe_array[pe], 0, sizeof(struct pnv_ioda_pe)); 94184cd4a3SBenjamin Herrenschmidt clear_bit(pe, phb->ioda.pe_alloc); 95184cd4a3SBenjamin Herrenschmidt } 96184cd4a3SBenjamin Herrenschmidt 97184cd4a3SBenjamin Herrenschmidt /* Currently those 2 are only used when MSIs are enabled, this will change 98184cd4a3SBenjamin Herrenschmidt * but in the meantime, we need to protect them to avoid warnings 99184cd4a3SBenjamin Herrenschmidt */ 100184cd4a3SBenjamin Herrenschmidt #ifdef CONFIG_PCI_MSI 101cad5cef6SGreg Kroah-Hartman static struct pnv_ioda_pe *pnv_ioda_get_pe(struct pci_dev *dev) 102184cd4a3SBenjamin Herrenschmidt { 103184cd4a3SBenjamin Herrenschmidt struct pci_controller *hose = pci_bus_to_host(dev->bus); 104184cd4a3SBenjamin Herrenschmidt struct pnv_phb *phb = hose->private_data; 105b72c1f65SBenjamin Herrenschmidt struct pci_dn *pdn = pci_get_pdn(dev); 106184cd4a3SBenjamin Herrenschmidt 107184cd4a3SBenjamin Herrenschmidt if (!pdn) 108184cd4a3SBenjamin Herrenschmidt return NULL; 109184cd4a3SBenjamin Herrenschmidt if (pdn->pe_number == IODA_INVALID_PE) 110184cd4a3SBenjamin Herrenschmidt return NULL; 111184cd4a3SBenjamin Herrenschmidt return &phb->ioda.pe_array[pdn->pe_number]; 112184cd4a3SBenjamin Herrenschmidt } 113184cd4a3SBenjamin Herrenschmidt #endif /* CONFIG_PCI_MSI */ 114184cd4a3SBenjamin Herrenschmidt 115cad5cef6SGreg Kroah-Hartman static int pnv_ioda_configure_pe(struct pnv_phb *phb, struct pnv_ioda_pe *pe) 116184cd4a3SBenjamin Herrenschmidt { 117184cd4a3SBenjamin Herrenschmidt struct pci_dev *parent; 118184cd4a3SBenjamin Herrenschmidt uint8_t bcomp, dcomp, fcomp; 119184cd4a3SBenjamin Herrenschmidt long rc, rid_end, rid; 120184cd4a3SBenjamin Herrenschmidt 121184cd4a3SBenjamin Herrenschmidt /* Bus validation ? */ 122184cd4a3SBenjamin Herrenschmidt if (pe->pbus) { 123184cd4a3SBenjamin Herrenschmidt int count; 124184cd4a3SBenjamin Herrenschmidt 125184cd4a3SBenjamin Herrenschmidt dcomp = OPAL_IGNORE_RID_DEVICE_NUMBER; 126184cd4a3SBenjamin Herrenschmidt fcomp = OPAL_IGNORE_RID_FUNCTION_NUMBER; 127184cd4a3SBenjamin Herrenschmidt parent = pe->pbus->self; 128fb446ad0SGavin Shan if (pe->flags & PNV_IODA_PE_BUS_ALL) 129b918c62eSYinghai Lu count = pe->pbus->busn_res.end - pe->pbus->busn_res.start + 1; 130fb446ad0SGavin Shan else 131fb446ad0SGavin Shan count = 1; 132fb446ad0SGavin Shan 133184cd4a3SBenjamin Herrenschmidt switch(count) { 134184cd4a3SBenjamin Herrenschmidt case 1: bcomp = OpalPciBusAll; break; 135184cd4a3SBenjamin Herrenschmidt case 2: bcomp = OpalPciBus7Bits; break; 136184cd4a3SBenjamin Herrenschmidt case 4: bcomp = OpalPciBus6Bits; break; 137184cd4a3SBenjamin Herrenschmidt case 8: bcomp = OpalPciBus5Bits; break; 138184cd4a3SBenjamin Herrenschmidt case 16: bcomp = OpalPciBus4Bits; break; 139184cd4a3SBenjamin Herrenschmidt case 32: bcomp = OpalPciBus3Bits; break; 140184cd4a3SBenjamin Herrenschmidt default: 141184cd4a3SBenjamin Herrenschmidt pr_err("%s: Number of subordinate busses %d" 142184cd4a3SBenjamin Herrenschmidt " unsupported\n", 143184cd4a3SBenjamin Herrenschmidt pci_name(pe->pbus->self), count); 144184cd4a3SBenjamin Herrenschmidt /* Do an exact match only */ 145184cd4a3SBenjamin Herrenschmidt bcomp = OpalPciBusAll; 146184cd4a3SBenjamin Herrenschmidt } 147184cd4a3SBenjamin Herrenschmidt rid_end = pe->rid + (count << 8); 148184cd4a3SBenjamin Herrenschmidt } else { 149184cd4a3SBenjamin Herrenschmidt parent = pe->pdev->bus->self; 150184cd4a3SBenjamin Herrenschmidt bcomp = OpalPciBusAll; 151184cd4a3SBenjamin Herrenschmidt dcomp = OPAL_COMPARE_RID_DEVICE_NUMBER; 152184cd4a3SBenjamin Herrenschmidt fcomp = OPAL_COMPARE_RID_FUNCTION_NUMBER; 153184cd4a3SBenjamin Herrenschmidt rid_end = pe->rid + 1; 154184cd4a3SBenjamin Herrenschmidt } 155184cd4a3SBenjamin Herrenschmidt 156184cd4a3SBenjamin Herrenschmidt /* Associate PE in PELT */ 157184cd4a3SBenjamin Herrenschmidt rc = opal_pci_set_pe(phb->opal_id, pe->pe_number, pe->rid, 158184cd4a3SBenjamin Herrenschmidt bcomp, dcomp, fcomp, OPAL_MAP_PE); 159184cd4a3SBenjamin Herrenschmidt if (rc) { 160184cd4a3SBenjamin Herrenschmidt pe_err(pe, "OPAL error %ld trying to setup PELT table\n", rc); 161184cd4a3SBenjamin Herrenschmidt return -ENXIO; 162184cd4a3SBenjamin Herrenschmidt } 163184cd4a3SBenjamin Herrenschmidt opal_pci_eeh_freeze_clear(phb->opal_id, pe->pe_number, 164184cd4a3SBenjamin Herrenschmidt OPAL_EEH_ACTION_CLEAR_FREEZE_ALL); 165184cd4a3SBenjamin Herrenschmidt 166184cd4a3SBenjamin Herrenschmidt /* Add to all parents PELT-V */ 167184cd4a3SBenjamin Herrenschmidt while (parent) { 168b72c1f65SBenjamin Herrenschmidt struct pci_dn *pdn = pci_get_pdn(parent); 169184cd4a3SBenjamin Herrenschmidt if (pdn && pdn->pe_number != IODA_INVALID_PE) { 170184cd4a3SBenjamin Herrenschmidt rc = opal_pci_set_peltv(phb->opal_id, pdn->pe_number, 171cee72d5bSBenjamin Herrenschmidt pe->pe_number, OPAL_ADD_PE_TO_DOMAIN); 172184cd4a3SBenjamin Herrenschmidt /* XXX What to do in case of error ? */ 173184cd4a3SBenjamin Herrenschmidt } 174184cd4a3SBenjamin Herrenschmidt parent = parent->bus->self; 175184cd4a3SBenjamin Herrenschmidt } 176184cd4a3SBenjamin Herrenschmidt /* Setup reverse map */ 177184cd4a3SBenjamin Herrenschmidt for (rid = pe->rid; rid < rid_end; rid++) 178184cd4a3SBenjamin Herrenschmidt phb->ioda.pe_rmap[rid] = pe->pe_number; 179184cd4a3SBenjamin Herrenschmidt 180184cd4a3SBenjamin Herrenschmidt /* Setup one MVTs on IODA1 */ 181184cd4a3SBenjamin Herrenschmidt if (phb->type == PNV_PHB_IODA1) { 182184cd4a3SBenjamin Herrenschmidt pe->mve_number = pe->pe_number; 183184cd4a3SBenjamin Herrenschmidt rc = opal_pci_set_mve(phb->opal_id, pe->mve_number, 184184cd4a3SBenjamin Herrenschmidt pe->pe_number); 185184cd4a3SBenjamin Herrenschmidt if (rc) { 186184cd4a3SBenjamin Herrenschmidt pe_err(pe, "OPAL error %ld setting up MVE %d\n", 187184cd4a3SBenjamin Herrenschmidt rc, pe->mve_number); 188184cd4a3SBenjamin Herrenschmidt pe->mve_number = -1; 189184cd4a3SBenjamin Herrenschmidt } else { 190184cd4a3SBenjamin Herrenschmidt rc = opal_pci_set_mve_enable(phb->opal_id, 191cee72d5bSBenjamin Herrenschmidt pe->mve_number, OPAL_ENABLE_MVE); 192184cd4a3SBenjamin Herrenschmidt if (rc) { 193184cd4a3SBenjamin Herrenschmidt pe_err(pe, "OPAL error %ld enabling MVE %d\n", 194184cd4a3SBenjamin Herrenschmidt rc, pe->mve_number); 195184cd4a3SBenjamin Herrenschmidt pe->mve_number = -1; 196184cd4a3SBenjamin Herrenschmidt } 197184cd4a3SBenjamin Herrenschmidt } 198184cd4a3SBenjamin Herrenschmidt } else if (phb->type == PNV_PHB_IODA2) 199184cd4a3SBenjamin Herrenschmidt pe->mve_number = 0; 200184cd4a3SBenjamin Herrenschmidt 201184cd4a3SBenjamin Herrenschmidt return 0; 202184cd4a3SBenjamin Herrenschmidt } 203184cd4a3SBenjamin Herrenschmidt 204cad5cef6SGreg Kroah-Hartman static void pnv_ioda_link_pe_by_weight(struct pnv_phb *phb, 205184cd4a3SBenjamin Herrenschmidt struct pnv_ioda_pe *pe) 206184cd4a3SBenjamin Herrenschmidt { 207184cd4a3SBenjamin Herrenschmidt struct pnv_ioda_pe *lpe; 208184cd4a3SBenjamin Herrenschmidt 2097ebdf956SGavin Shan list_for_each_entry(lpe, &phb->ioda.pe_dma_list, dma_link) { 210184cd4a3SBenjamin Herrenschmidt if (lpe->dma_weight < pe->dma_weight) { 2117ebdf956SGavin Shan list_add_tail(&pe->dma_link, &lpe->dma_link); 212184cd4a3SBenjamin Herrenschmidt return; 213184cd4a3SBenjamin Herrenschmidt } 214184cd4a3SBenjamin Herrenschmidt } 2157ebdf956SGavin Shan list_add_tail(&pe->dma_link, &phb->ioda.pe_dma_list); 216184cd4a3SBenjamin Herrenschmidt } 217184cd4a3SBenjamin Herrenschmidt 218184cd4a3SBenjamin Herrenschmidt static unsigned int pnv_ioda_dma_weight(struct pci_dev *dev) 219184cd4a3SBenjamin Herrenschmidt { 220184cd4a3SBenjamin Herrenschmidt /* This is quite simplistic. The "base" weight of a device 221184cd4a3SBenjamin Herrenschmidt * is 10. 0 means no DMA is to be accounted for it. 222184cd4a3SBenjamin Herrenschmidt */ 223184cd4a3SBenjamin Herrenschmidt 224184cd4a3SBenjamin Herrenschmidt /* If it's a bridge, no DMA */ 225184cd4a3SBenjamin Herrenschmidt if (dev->hdr_type != PCI_HEADER_TYPE_NORMAL) 226184cd4a3SBenjamin Herrenschmidt return 0; 227184cd4a3SBenjamin Herrenschmidt 228184cd4a3SBenjamin Herrenschmidt /* Reduce the weight of slow USB controllers */ 229184cd4a3SBenjamin Herrenschmidt if (dev->class == PCI_CLASS_SERIAL_USB_UHCI || 230184cd4a3SBenjamin Herrenschmidt dev->class == PCI_CLASS_SERIAL_USB_OHCI || 231184cd4a3SBenjamin Herrenschmidt dev->class == PCI_CLASS_SERIAL_USB_EHCI) 232184cd4a3SBenjamin Herrenschmidt return 3; 233184cd4a3SBenjamin Herrenschmidt 234184cd4a3SBenjamin Herrenschmidt /* Increase the weight of RAID (includes Obsidian) */ 235184cd4a3SBenjamin Herrenschmidt if ((dev->class >> 8) == PCI_CLASS_STORAGE_RAID) 236184cd4a3SBenjamin Herrenschmidt return 15; 237184cd4a3SBenjamin Herrenschmidt 238184cd4a3SBenjamin Herrenschmidt /* Default */ 239184cd4a3SBenjamin Herrenschmidt return 10; 240184cd4a3SBenjamin Herrenschmidt } 241184cd4a3SBenjamin Herrenschmidt 242fb446ad0SGavin Shan #if 0 243cad5cef6SGreg Kroah-Hartman static struct pnv_ioda_pe *pnv_ioda_setup_dev_PE(struct pci_dev *dev) 244184cd4a3SBenjamin Herrenschmidt { 245184cd4a3SBenjamin Herrenschmidt struct pci_controller *hose = pci_bus_to_host(dev->bus); 246184cd4a3SBenjamin Herrenschmidt struct pnv_phb *phb = hose->private_data; 247b72c1f65SBenjamin Herrenschmidt struct pci_dn *pdn = pci_get_pdn(dev); 248184cd4a3SBenjamin Herrenschmidt struct pnv_ioda_pe *pe; 249184cd4a3SBenjamin Herrenschmidt int pe_num; 250184cd4a3SBenjamin Herrenschmidt 251184cd4a3SBenjamin Herrenschmidt if (!pdn) { 252184cd4a3SBenjamin Herrenschmidt pr_err("%s: Device tree node not associated properly\n", 253184cd4a3SBenjamin Herrenschmidt pci_name(dev)); 254184cd4a3SBenjamin Herrenschmidt return NULL; 255184cd4a3SBenjamin Herrenschmidt } 256184cd4a3SBenjamin Herrenschmidt if (pdn->pe_number != IODA_INVALID_PE) 257184cd4a3SBenjamin Herrenschmidt return NULL; 258184cd4a3SBenjamin Herrenschmidt 259184cd4a3SBenjamin Herrenschmidt /* PE#0 has been pre-set */ 260184cd4a3SBenjamin Herrenschmidt if (dev->bus->number == 0) 261184cd4a3SBenjamin Herrenschmidt pe_num = 0; 262184cd4a3SBenjamin Herrenschmidt else 263184cd4a3SBenjamin Herrenschmidt pe_num = pnv_ioda_alloc_pe(phb); 264184cd4a3SBenjamin Herrenschmidt if (pe_num == IODA_INVALID_PE) { 265184cd4a3SBenjamin Herrenschmidt pr_warning("%s: Not enough PE# available, disabling device\n", 266184cd4a3SBenjamin Herrenschmidt pci_name(dev)); 267184cd4a3SBenjamin Herrenschmidt return NULL; 268184cd4a3SBenjamin Herrenschmidt } 269184cd4a3SBenjamin Herrenschmidt 270184cd4a3SBenjamin Herrenschmidt /* NOTE: We get only one ref to the pci_dev for the pdn, not for the 271184cd4a3SBenjamin Herrenschmidt * pointer in the PE data structure, both should be destroyed at the 272184cd4a3SBenjamin Herrenschmidt * same time. However, this needs to be looked at more closely again 273184cd4a3SBenjamin Herrenschmidt * once we actually start removing things (Hotplug, SR-IOV, ...) 274184cd4a3SBenjamin Herrenschmidt * 275184cd4a3SBenjamin Herrenschmidt * At some point we want to remove the PDN completely anyways 276184cd4a3SBenjamin Herrenschmidt */ 277184cd4a3SBenjamin Herrenschmidt pe = &phb->ioda.pe_array[pe_num]; 278184cd4a3SBenjamin Herrenschmidt pci_dev_get(dev); 279184cd4a3SBenjamin Herrenschmidt pdn->pcidev = dev; 280184cd4a3SBenjamin Herrenschmidt pdn->pe_number = pe_num; 281184cd4a3SBenjamin Herrenschmidt pe->pdev = dev; 282184cd4a3SBenjamin Herrenschmidt pe->pbus = NULL; 283184cd4a3SBenjamin Herrenschmidt pe->tce32_seg = -1; 284184cd4a3SBenjamin Herrenschmidt pe->mve_number = -1; 285184cd4a3SBenjamin Herrenschmidt pe->rid = dev->bus->number << 8 | pdn->devfn; 286184cd4a3SBenjamin Herrenschmidt 287184cd4a3SBenjamin Herrenschmidt pe_info(pe, "Associated device to PE\n"); 288184cd4a3SBenjamin Herrenschmidt 289184cd4a3SBenjamin Herrenschmidt if (pnv_ioda_configure_pe(phb, pe)) { 290184cd4a3SBenjamin Herrenschmidt /* XXX What do we do here ? */ 291184cd4a3SBenjamin Herrenschmidt if (pe_num) 292184cd4a3SBenjamin Herrenschmidt pnv_ioda_free_pe(phb, pe_num); 293184cd4a3SBenjamin Herrenschmidt pdn->pe_number = IODA_INVALID_PE; 294184cd4a3SBenjamin Herrenschmidt pe->pdev = NULL; 295184cd4a3SBenjamin Herrenschmidt pci_dev_put(dev); 296184cd4a3SBenjamin Herrenschmidt return NULL; 297184cd4a3SBenjamin Herrenschmidt } 298184cd4a3SBenjamin Herrenschmidt 299184cd4a3SBenjamin Herrenschmidt /* Assign a DMA weight to the device */ 300184cd4a3SBenjamin Herrenschmidt pe->dma_weight = pnv_ioda_dma_weight(dev); 301184cd4a3SBenjamin Herrenschmidt if (pe->dma_weight != 0) { 302184cd4a3SBenjamin Herrenschmidt phb->ioda.dma_weight += pe->dma_weight; 303184cd4a3SBenjamin Herrenschmidt phb->ioda.dma_pe_count++; 304184cd4a3SBenjamin Herrenschmidt } 305184cd4a3SBenjamin Herrenschmidt 306184cd4a3SBenjamin Herrenschmidt /* Link the PE */ 307184cd4a3SBenjamin Herrenschmidt pnv_ioda_link_pe_by_weight(phb, pe); 308184cd4a3SBenjamin Herrenschmidt 309184cd4a3SBenjamin Herrenschmidt return pe; 310184cd4a3SBenjamin Herrenschmidt } 311fb446ad0SGavin Shan #endif /* Useful for SRIOV case */ 312184cd4a3SBenjamin Herrenschmidt 313184cd4a3SBenjamin Herrenschmidt static void pnv_ioda_setup_same_PE(struct pci_bus *bus, struct pnv_ioda_pe *pe) 314184cd4a3SBenjamin Herrenschmidt { 315184cd4a3SBenjamin Herrenschmidt struct pci_dev *dev; 316184cd4a3SBenjamin Herrenschmidt 317184cd4a3SBenjamin Herrenschmidt list_for_each_entry(dev, &bus->devices, bus_list) { 318b72c1f65SBenjamin Herrenschmidt struct pci_dn *pdn = pci_get_pdn(dev); 319184cd4a3SBenjamin Herrenschmidt 320184cd4a3SBenjamin Herrenschmidt if (pdn == NULL) { 321184cd4a3SBenjamin Herrenschmidt pr_warn("%s: No device node associated with device !\n", 322184cd4a3SBenjamin Herrenschmidt pci_name(dev)); 323184cd4a3SBenjamin Herrenschmidt continue; 324184cd4a3SBenjamin Herrenschmidt } 325184cd4a3SBenjamin Herrenschmidt pci_dev_get(dev); 326184cd4a3SBenjamin Herrenschmidt pdn->pcidev = dev; 327184cd4a3SBenjamin Herrenschmidt pdn->pe_number = pe->pe_number; 328184cd4a3SBenjamin Herrenschmidt pe->dma_weight += pnv_ioda_dma_weight(dev); 329fb446ad0SGavin Shan if ((pe->flags & PNV_IODA_PE_BUS_ALL) && dev->subordinate) 330184cd4a3SBenjamin Herrenschmidt pnv_ioda_setup_same_PE(dev->subordinate, pe); 331184cd4a3SBenjamin Herrenschmidt } 332184cd4a3SBenjamin Herrenschmidt } 333184cd4a3SBenjamin Herrenschmidt 334fb446ad0SGavin Shan /* 335fb446ad0SGavin Shan * There're 2 types of PCI bus sensitive PEs: One that is compromised of 336fb446ad0SGavin Shan * single PCI bus. Another one that contains the primary PCI bus and its 337fb446ad0SGavin Shan * subordinate PCI devices and buses. The second type of PE is normally 338fb446ad0SGavin Shan * orgiriated by PCIe-to-PCI bridge or PLX switch downstream ports. 339fb446ad0SGavin Shan */ 340cad5cef6SGreg Kroah-Hartman static void pnv_ioda_setup_bus_PE(struct pci_bus *bus, int all) 341184cd4a3SBenjamin Herrenschmidt { 342fb446ad0SGavin Shan struct pci_controller *hose = pci_bus_to_host(bus); 343184cd4a3SBenjamin Herrenschmidt struct pnv_phb *phb = hose->private_data; 344184cd4a3SBenjamin Herrenschmidt struct pnv_ioda_pe *pe; 345184cd4a3SBenjamin Herrenschmidt int pe_num; 346184cd4a3SBenjamin Herrenschmidt 347184cd4a3SBenjamin Herrenschmidt pe_num = pnv_ioda_alloc_pe(phb); 348184cd4a3SBenjamin Herrenschmidt if (pe_num == IODA_INVALID_PE) { 349fb446ad0SGavin Shan pr_warning("%s: Not enough PE# available for PCI bus %04x:%02x\n", 350fb446ad0SGavin Shan __func__, pci_domain_nr(bus), bus->number); 351184cd4a3SBenjamin Herrenschmidt return; 352184cd4a3SBenjamin Herrenschmidt } 353184cd4a3SBenjamin Herrenschmidt 354184cd4a3SBenjamin Herrenschmidt pe = &phb->ioda.pe_array[pe_num]; 355fb446ad0SGavin Shan pe->flags = (all ? PNV_IODA_PE_BUS_ALL : PNV_IODA_PE_BUS); 356184cd4a3SBenjamin Herrenschmidt pe->pbus = bus; 357184cd4a3SBenjamin Herrenschmidt pe->pdev = NULL; 358184cd4a3SBenjamin Herrenschmidt pe->tce32_seg = -1; 359184cd4a3SBenjamin Herrenschmidt pe->mve_number = -1; 360b918c62eSYinghai Lu pe->rid = bus->busn_res.start << 8; 361184cd4a3SBenjamin Herrenschmidt pe->dma_weight = 0; 362184cd4a3SBenjamin Herrenschmidt 363fb446ad0SGavin Shan if (all) 364fb446ad0SGavin Shan pe_info(pe, "Secondary bus %d..%d associated with PE#%d\n", 365fb446ad0SGavin Shan bus->busn_res.start, bus->busn_res.end, pe_num); 366fb446ad0SGavin Shan else 367fb446ad0SGavin Shan pe_info(pe, "Secondary bus %d associated with PE#%d\n", 368fb446ad0SGavin Shan bus->busn_res.start, pe_num); 369184cd4a3SBenjamin Herrenschmidt 370184cd4a3SBenjamin Herrenschmidt if (pnv_ioda_configure_pe(phb, pe)) { 371184cd4a3SBenjamin Herrenschmidt /* XXX What do we do here ? */ 372184cd4a3SBenjamin Herrenschmidt if (pe_num) 373184cd4a3SBenjamin Herrenschmidt pnv_ioda_free_pe(phb, pe_num); 374184cd4a3SBenjamin Herrenschmidt pe->pbus = NULL; 375184cd4a3SBenjamin Herrenschmidt return; 376184cd4a3SBenjamin Herrenschmidt } 377184cd4a3SBenjamin Herrenschmidt 378184cd4a3SBenjamin Herrenschmidt /* Associate it with all child devices */ 379184cd4a3SBenjamin Herrenschmidt pnv_ioda_setup_same_PE(bus, pe); 380184cd4a3SBenjamin Herrenschmidt 3817ebdf956SGavin Shan /* Put PE to the list */ 3827ebdf956SGavin Shan list_add_tail(&pe->list, &phb->ioda.pe_list); 3837ebdf956SGavin Shan 384184cd4a3SBenjamin Herrenschmidt /* Account for one DMA PE if at least one DMA capable device exist 385184cd4a3SBenjamin Herrenschmidt * below the bridge 386184cd4a3SBenjamin Herrenschmidt */ 387184cd4a3SBenjamin Herrenschmidt if (pe->dma_weight != 0) { 388184cd4a3SBenjamin Herrenschmidt phb->ioda.dma_weight += pe->dma_weight; 389184cd4a3SBenjamin Herrenschmidt phb->ioda.dma_pe_count++; 390184cd4a3SBenjamin Herrenschmidt } 391184cd4a3SBenjamin Herrenschmidt 392184cd4a3SBenjamin Herrenschmidt /* Link the PE */ 393184cd4a3SBenjamin Herrenschmidt pnv_ioda_link_pe_by_weight(phb, pe); 394184cd4a3SBenjamin Herrenschmidt } 395184cd4a3SBenjamin Herrenschmidt 396cad5cef6SGreg Kroah-Hartman static void pnv_ioda_setup_PEs(struct pci_bus *bus) 397184cd4a3SBenjamin Herrenschmidt { 398184cd4a3SBenjamin Herrenschmidt struct pci_dev *dev; 399fb446ad0SGavin Shan 400fb446ad0SGavin Shan pnv_ioda_setup_bus_PE(bus, 0); 401184cd4a3SBenjamin Herrenschmidt 402184cd4a3SBenjamin Herrenschmidt list_for_each_entry(dev, &bus->devices, bus_list) { 403fb446ad0SGavin Shan if (dev->subordinate) { 40462f87c0eSYijing Wang if (pci_pcie_type(dev) == PCI_EXP_TYPE_PCI_BRIDGE) 405fb446ad0SGavin Shan pnv_ioda_setup_bus_PE(dev->subordinate, 1); 406fb446ad0SGavin Shan else 407184cd4a3SBenjamin Herrenschmidt pnv_ioda_setup_PEs(dev->subordinate); 408184cd4a3SBenjamin Herrenschmidt } 409184cd4a3SBenjamin Herrenschmidt } 410fb446ad0SGavin Shan } 411fb446ad0SGavin Shan 412fb446ad0SGavin Shan /* 413fb446ad0SGavin Shan * Configure PEs so that the downstream PCI buses and devices 414fb446ad0SGavin Shan * could have their associated PE#. Unfortunately, we didn't 415fb446ad0SGavin Shan * figure out the way to identify the PLX bridge yet. So we 416fb446ad0SGavin Shan * simply put the PCI bus and the subordinate behind the root 417fb446ad0SGavin Shan * port to PE# here. The game rule here is expected to be changed 418fb446ad0SGavin Shan * as soon as we can detected PLX bridge correctly. 419fb446ad0SGavin Shan */ 420cad5cef6SGreg Kroah-Hartman static void pnv_pci_ioda_setup_PEs(void) 421fb446ad0SGavin Shan { 422fb446ad0SGavin Shan struct pci_controller *hose, *tmp; 423fb446ad0SGavin Shan 424fb446ad0SGavin Shan list_for_each_entry_safe(hose, tmp, &hose_list, list_node) { 425fb446ad0SGavin Shan pnv_ioda_setup_PEs(hose->bus); 426fb446ad0SGavin Shan } 427fb446ad0SGavin Shan } 428184cd4a3SBenjamin Herrenschmidt 429959c9bddSGavin Shan static void pnv_pci_ioda_dma_dev_setup(struct pnv_phb *phb, struct pci_dev *pdev) 430184cd4a3SBenjamin Herrenschmidt { 431b72c1f65SBenjamin Herrenschmidt struct pci_dn *pdn = pci_get_pdn(pdev); 432959c9bddSGavin Shan struct pnv_ioda_pe *pe; 433184cd4a3SBenjamin Herrenschmidt 434959c9bddSGavin Shan /* 435959c9bddSGavin Shan * The function can be called while the PE# 436959c9bddSGavin Shan * hasn't been assigned. Do nothing for the 437959c9bddSGavin Shan * case. 438959c9bddSGavin Shan */ 439959c9bddSGavin Shan if (!pdn || pdn->pe_number == IODA_INVALID_PE) 440959c9bddSGavin Shan return; 441184cd4a3SBenjamin Herrenschmidt 442959c9bddSGavin Shan pe = &phb->ioda.pe_array[pdn->pe_number]; 443959c9bddSGavin Shan set_iommu_table_base(&pdev->dev, &pe->tce32_table); 444184cd4a3SBenjamin Herrenschmidt } 445184cd4a3SBenjamin Herrenschmidt 44674251fe2SBenjamin Herrenschmidt static void pnv_ioda_setup_bus_dma(struct pnv_ioda_pe *pe, struct pci_bus *bus) 44774251fe2SBenjamin Herrenschmidt { 44874251fe2SBenjamin Herrenschmidt struct pci_dev *dev; 44974251fe2SBenjamin Herrenschmidt 45074251fe2SBenjamin Herrenschmidt list_for_each_entry(dev, &bus->devices, bus_list) { 45174251fe2SBenjamin Herrenschmidt set_iommu_table_base(&dev->dev, &pe->tce32_table); 45274251fe2SBenjamin Herrenschmidt if (dev->subordinate) 45374251fe2SBenjamin Herrenschmidt pnv_ioda_setup_bus_dma(pe, dev->subordinate); 45474251fe2SBenjamin Herrenschmidt } 45574251fe2SBenjamin Herrenschmidt } 45674251fe2SBenjamin Herrenschmidt 4574cce9550SGavin Shan static void pnv_pci_ioda1_tce_invalidate(struct iommu_table *tbl, 4584cce9550SGavin Shan u64 *startp, u64 *endp) 4594cce9550SGavin Shan { 4604cce9550SGavin Shan u64 __iomem *invalidate = (u64 __iomem *)tbl->it_index; 4614cce9550SGavin Shan unsigned long start, end, inc; 4624cce9550SGavin Shan 4634cce9550SGavin Shan start = __pa(startp); 4644cce9550SGavin Shan end = __pa(endp); 4654cce9550SGavin Shan 4664cce9550SGavin Shan /* BML uses this case for p6/p7/galaxy2: Shift addr and put in node */ 4674cce9550SGavin Shan if (tbl->it_busno) { 4684cce9550SGavin Shan start <<= 12; 4694cce9550SGavin Shan end <<= 12; 4704cce9550SGavin Shan inc = 128 << 12; 4714cce9550SGavin Shan start |= tbl->it_busno; 4724cce9550SGavin Shan end |= tbl->it_busno; 4734cce9550SGavin Shan } else if (tbl->it_type & TCE_PCI_SWINV_PAIR) { 4744cce9550SGavin Shan /* p7ioc-style invalidation, 2 TCEs per write */ 4754cce9550SGavin Shan start |= (1ull << 63); 4764cce9550SGavin Shan end |= (1ull << 63); 4774cce9550SGavin Shan inc = 16; 4784cce9550SGavin Shan } else { 4794cce9550SGavin Shan /* Default (older HW) */ 4804cce9550SGavin Shan inc = 128; 4814cce9550SGavin Shan } 4824cce9550SGavin Shan 4834cce9550SGavin Shan end |= inc - 1; /* round up end to be different than start */ 4844cce9550SGavin Shan 4854cce9550SGavin Shan mb(); /* Ensure above stores are visible */ 4864cce9550SGavin Shan while (start <= end) { 4874cce9550SGavin Shan __raw_writeq(start, invalidate); 4884cce9550SGavin Shan start += inc; 4894cce9550SGavin Shan } 4904cce9550SGavin Shan 4914cce9550SGavin Shan /* 4924cce9550SGavin Shan * The iommu layer will do another mb() for us on build() 4934cce9550SGavin Shan * and we don't care on free() 4944cce9550SGavin Shan */ 4954cce9550SGavin Shan } 4964cce9550SGavin Shan 4974cce9550SGavin Shan static void pnv_pci_ioda2_tce_invalidate(struct pnv_ioda_pe *pe, 4984cce9550SGavin Shan struct iommu_table *tbl, 4994cce9550SGavin Shan u64 *startp, u64 *endp) 5004cce9550SGavin Shan { 5014cce9550SGavin Shan unsigned long start, end, inc; 5024cce9550SGavin Shan u64 __iomem *invalidate = (u64 __iomem *)tbl->it_index; 5034cce9550SGavin Shan 5044cce9550SGavin Shan /* We'll invalidate DMA address in PE scope */ 5054cce9550SGavin Shan start = 0x2ul << 60; 5064cce9550SGavin Shan start |= (pe->pe_number & 0xFF); 5074cce9550SGavin Shan end = start; 5084cce9550SGavin Shan 5094cce9550SGavin Shan /* Figure out the start, end and step */ 5104cce9550SGavin Shan inc = tbl->it_offset + (((u64)startp - tbl->it_base) / sizeof(u64)); 5114cce9550SGavin Shan start |= (inc << 12); 5124cce9550SGavin Shan inc = tbl->it_offset + (((u64)endp - tbl->it_base) / sizeof(u64)); 5134cce9550SGavin Shan end |= (inc << 12); 5144cce9550SGavin Shan inc = (0x1ul << 12); 5154cce9550SGavin Shan mb(); 5164cce9550SGavin Shan 5174cce9550SGavin Shan while (start <= end) { 5184cce9550SGavin Shan __raw_writeq(start, invalidate); 5194cce9550SGavin Shan start += inc; 5204cce9550SGavin Shan } 5214cce9550SGavin Shan } 5224cce9550SGavin Shan 5234cce9550SGavin Shan void pnv_pci_ioda_tce_invalidate(struct iommu_table *tbl, 5244cce9550SGavin Shan u64 *startp, u64 *endp) 5254cce9550SGavin Shan { 5264cce9550SGavin Shan struct pnv_ioda_pe *pe = container_of(tbl, struct pnv_ioda_pe, 5274cce9550SGavin Shan tce32_table); 5284cce9550SGavin Shan struct pnv_phb *phb = pe->phb; 5294cce9550SGavin Shan 5304cce9550SGavin Shan if (phb->type == PNV_PHB_IODA1) 5314cce9550SGavin Shan pnv_pci_ioda1_tce_invalidate(tbl, startp, endp); 5324cce9550SGavin Shan else 5334cce9550SGavin Shan pnv_pci_ioda2_tce_invalidate(pe, tbl, startp, endp); 5344cce9550SGavin Shan } 5354cce9550SGavin Shan 536cad5cef6SGreg Kroah-Hartman static void pnv_pci_ioda_setup_dma_pe(struct pnv_phb *phb, 537cad5cef6SGreg Kroah-Hartman struct pnv_ioda_pe *pe, unsigned int base, 538184cd4a3SBenjamin Herrenschmidt unsigned int segs) 539184cd4a3SBenjamin Herrenschmidt { 540184cd4a3SBenjamin Herrenschmidt 541184cd4a3SBenjamin Herrenschmidt struct page *tce_mem = NULL; 542184cd4a3SBenjamin Herrenschmidt const __be64 *swinvp; 543184cd4a3SBenjamin Herrenschmidt struct iommu_table *tbl; 544184cd4a3SBenjamin Herrenschmidt unsigned int i; 545184cd4a3SBenjamin Herrenschmidt int64_t rc; 546184cd4a3SBenjamin Herrenschmidt void *addr; 547184cd4a3SBenjamin Herrenschmidt 548184cd4a3SBenjamin Herrenschmidt /* 256M DMA window, 4K TCE pages, 8 bytes TCE */ 549184cd4a3SBenjamin Herrenschmidt #define TCE32_TABLE_SIZE ((0x10000000 / 0x1000) * 8) 550184cd4a3SBenjamin Herrenschmidt 551184cd4a3SBenjamin Herrenschmidt /* XXX FIXME: Handle 64-bit only DMA devices */ 552184cd4a3SBenjamin Herrenschmidt /* XXX FIXME: Provide 64-bit DMA facilities & non-4K TCE tables etc.. */ 553184cd4a3SBenjamin Herrenschmidt /* XXX FIXME: Allocate multi-level tables on PHB3 */ 554184cd4a3SBenjamin Herrenschmidt 555184cd4a3SBenjamin Herrenschmidt /* We shouldn't already have a 32-bit DMA associated */ 556184cd4a3SBenjamin Herrenschmidt if (WARN_ON(pe->tce32_seg >= 0)) 557184cd4a3SBenjamin Herrenschmidt return; 558184cd4a3SBenjamin Herrenschmidt 559184cd4a3SBenjamin Herrenschmidt /* Grab a 32-bit TCE table */ 560184cd4a3SBenjamin Herrenschmidt pe->tce32_seg = base; 561184cd4a3SBenjamin Herrenschmidt pe_info(pe, " Setting up 32-bit TCE table at %08x..%08x\n", 562184cd4a3SBenjamin Herrenschmidt (base << 28), ((base + segs) << 28) - 1); 563184cd4a3SBenjamin Herrenschmidt 564184cd4a3SBenjamin Herrenschmidt /* XXX Currently, we allocate one big contiguous table for the 565184cd4a3SBenjamin Herrenschmidt * TCEs. We only really need one chunk per 256M of TCE space 566184cd4a3SBenjamin Herrenschmidt * (ie per segment) but that's an optimization for later, it 567184cd4a3SBenjamin Herrenschmidt * requires some added smarts with our get/put_tce implementation 568184cd4a3SBenjamin Herrenschmidt */ 569184cd4a3SBenjamin Herrenschmidt tce_mem = alloc_pages_node(phb->hose->node, GFP_KERNEL, 570184cd4a3SBenjamin Herrenschmidt get_order(TCE32_TABLE_SIZE * segs)); 571184cd4a3SBenjamin Herrenschmidt if (!tce_mem) { 572184cd4a3SBenjamin Herrenschmidt pe_err(pe, " Failed to allocate a 32-bit TCE memory\n"); 573184cd4a3SBenjamin Herrenschmidt goto fail; 574184cd4a3SBenjamin Herrenschmidt } 575184cd4a3SBenjamin Herrenschmidt addr = page_address(tce_mem); 576184cd4a3SBenjamin Herrenschmidt memset(addr, 0, TCE32_TABLE_SIZE * segs); 577184cd4a3SBenjamin Herrenschmidt 578184cd4a3SBenjamin Herrenschmidt /* Configure HW */ 579184cd4a3SBenjamin Herrenschmidt for (i = 0; i < segs; i++) { 580184cd4a3SBenjamin Herrenschmidt rc = opal_pci_map_pe_dma_window(phb->opal_id, 581184cd4a3SBenjamin Herrenschmidt pe->pe_number, 582184cd4a3SBenjamin Herrenschmidt base + i, 1, 583184cd4a3SBenjamin Herrenschmidt __pa(addr) + TCE32_TABLE_SIZE * i, 584184cd4a3SBenjamin Herrenschmidt TCE32_TABLE_SIZE, 0x1000); 585184cd4a3SBenjamin Herrenschmidt if (rc) { 586184cd4a3SBenjamin Herrenschmidt pe_err(pe, " Failed to configure 32-bit TCE table," 587184cd4a3SBenjamin Herrenschmidt " err %ld\n", rc); 588184cd4a3SBenjamin Herrenschmidt goto fail; 589184cd4a3SBenjamin Herrenschmidt } 590184cd4a3SBenjamin Herrenschmidt } 591184cd4a3SBenjamin Herrenschmidt 592184cd4a3SBenjamin Herrenschmidt /* Setup linux iommu table */ 593184cd4a3SBenjamin Herrenschmidt tbl = &pe->tce32_table; 594184cd4a3SBenjamin Herrenschmidt pnv_pci_setup_iommu_table(tbl, addr, TCE32_TABLE_SIZE * segs, 595184cd4a3SBenjamin Herrenschmidt base << 28); 596184cd4a3SBenjamin Herrenschmidt 597184cd4a3SBenjamin Herrenschmidt /* OPAL variant of P7IOC SW invalidated TCEs */ 598184cd4a3SBenjamin Herrenschmidt swinvp = of_get_property(phb->hose->dn, "ibm,opal-tce-kill", NULL); 599184cd4a3SBenjamin Herrenschmidt if (swinvp) { 600184cd4a3SBenjamin Herrenschmidt /* We need a couple more fields -- an address and a data 601184cd4a3SBenjamin Herrenschmidt * to or. Since the bus is only printed out on table free 602184cd4a3SBenjamin Herrenschmidt * errors, and on the first pass the data will be a relative 603184cd4a3SBenjamin Herrenschmidt * bus number, print that out instead. 604184cd4a3SBenjamin Herrenschmidt */ 605184cd4a3SBenjamin Herrenschmidt tbl->it_busno = 0; 606184cd4a3SBenjamin Herrenschmidt tbl->it_index = (unsigned long)ioremap(be64_to_cpup(swinvp), 8); 607373f5657SGavin Shan tbl->it_type = TCE_PCI_SWINV_CREATE | TCE_PCI_SWINV_FREE | 608373f5657SGavin Shan TCE_PCI_SWINV_PAIR; 609184cd4a3SBenjamin Herrenschmidt } 610184cd4a3SBenjamin Herrenschmidt iommu_init_table(tbl, phb->hose->node); 6114e13c1acSAlexey Kardashevskiy iommu_register_group(tbl, pci_domain_nr(pe->pbus), pe->pe_number); 612184cd4a3SBenjamin Herrenschmidt 61374251fe2SBenjamin Herrenschmidt if (pe->pdev) 61474251fe2SBenjamin Herrenschmidt set_iommu_table_base(&pe->pdev->dev, tbl); 61574251fe2SBenjamin Herrenschmidt else 61674251fe2SBenjamin Herrenschmidt pnv_ioda_setup_bus_dma(pe, pe->pbus); 61774251fe2SBenjamin Herrenschmidt 618184cd4a3SBenjamin Herrenschmidt return; 619184cd4a3SBenjamin Herrenschmidt fail: 620184cd4a3SBenjamin Herrenschmidt /* XXX Failure: Try to fallback to 64-bit only ? */ 621184cd4a3SBenjamin Herrenschmidt if (pe->tce32_seg >= 0) 622184cd4a3SBenjamin Herrenschmidt pe->tce32_seg = -1; 623184cd4a3SBenjamin Herrenschmidt if (tce_mem) 624184cd4a3SBenjamin Herrenschmidt __free_pages(tce_mem, get_order(TCE32_TABLE_SIZE * segs)); 625184cd4a3SBenjamin Herrenschmidt } 626184cd4a3SBenjamin Herrenschmidt 627373f5657SGavin Shan static void pnv_pci_ioda2_setup_dma_pe(struct pnv_phb *phb, 628373f5657SGavin Shan struct pnv_ioda_pe *pe) 629373f5657SGavin Shan { 630373f5657SGavin Shan struct page *tce_mem = NULL; 631373f5657SGavin Shan void *addr; 632373f5657SGavin Shan const __be64 *swinvp; 633373f5657SGavin Shan struct iommu_table *tbl; 634373f5657SGavin Shan unsigned int tce_table_size, end; 635373f5657SGavin Shan int64_t rc; 636373f5657SGavin Shan 637373f5657SGavin Shan /* We shouldn't already have a 32-bit DMA associated */ 638373f5657SGavin Shan if (WARN_ON(pe->tce32_seg >= 0)) 639373f5657SGavin Shan return; 640373f5657SGavin Shan 641373f5657SGavin Shan /* The PE will reserve all possible 32-bits space */ 642373f5657SGavin Shan pe->tce32_seg = 0; 643373f5657SGavin Shan end = (1 << ilog2(phb->ioda.m32_pci_base)); 644373f5657SGavin Shan tce_table_size = (end / 0x1000) * 8; 645373f5657SGavin Shan pe_info(pe, "Setting up 32-bit TCE table at 0..%08x\n", 646373f5657SGavin Shan end); 647373f5657SGavin Shan 648373f5657SGavin Shan /* Allocate TCE table */ 649373f5657SGavin Shan tce_mem = alloc_pages_node(phb->hose->node, GFP_KERNEL, 650373f5657SGavin Shan get_order(tce_table_size)); 651373f5657SGavin Shan if (!tce_mem) { 652373f5657SGavin Shan pe_err(pe, "Failed to allocate a 32-bit TCE memory\n"); 653373f5657SGavin Shan goto fail; 654373f5657SGavin Shan } 655373f5657SGavin Shan addr = page_address(tce_mem); 656373f5657SGavin Shan memset(addr, 0, tce_table_size); 657373f5657SGavin Shan 658373f5657SGavin Shan /* 659373f5657SGavin Shan * Map TCE table through TVT. The TVE index is the PE number 660373f5657SGavin Shan * shifted by 1 bit for 32-bits DMA space. 661373f5657SGavin Shan */ 662373f5657SGavin Shan rc = opal_pci_map_pe_dma_window(phb->opal_id, pe->pe_number, 663373f5657SGavin Shan pe->pe_number << 1, 1, __pa(addr), 664373f5657SGavin Shan tce_table_size, 0x1000); 665373f5657SGavin Shan if (rc) { 666373f5657SGavin Shan pe_err(pe, "Failed to configure 32-bit TCE table," 667373f5657SGavin Shan " err %ld\n", rc); 668373f5657SGavin Shan goto fail; 669373f5657SGavin Shan } 670373f5657SGavin Shan 671373f5657SGavin Shan /* Setup linux iommu table */ 672373f5657SGavin Shan tbl = &pe->tce32_table; 673373f5657SGavin Shan pnv_pci_setup_iommu_table(tbl, addr, tce_table_size, 0); 674373f5657SGavin Shan 675373f5657SGavin Shan /* OPAL variant of PHB3 invalidated TCEs */ 676373f5657SGavin Shan swinvp = of_get_property(phb->hose->dn, "ibm,opal-tce-kill", NULL); 677373f5657SGavin Shan if (swinvp) { 678373f5657SGavin Shan /* We need a couple more fields -- an address and a data 679373f5657SGavin Shan * to or. Since the bus is only printed out on table free 680373f5657SGavin Shan * errors, and on the first pass the data will be a relative 681373f5657SGavin Shan * bus number, print that out instead. 682373f5657SGavin Shan */ 683373f5657SGavin Shan tbl->it_busno = 0; 684373f5657SGavin Shan tbl->it_index = (unsigned long)ioremap(be64_to_cpup(swinvp), 8); 685373f5657SGavin Shan tbl->it_type = TCE_PCI_SWINV_CREATE | TCE_PCI_SWINV_FREE; 686373f5657SGavin Shan } 687373f5657SGavin Shan iommu_init_table(tbl, phb->hose->node); 688373f5657SGavin Shan 68974251fe2SBenjamin Herrenschmidt if (pe->pdev) 69074251fe2SBenjamin Herrenschmidt set_iommu_table_base(&pe->pdev->dev, tbl); 69174251fe2SBenjamin Herrenschmidt else 69274251fe2SBenjamin Herrenschmidt pnv_ioda_setup_bus_dma(pe, pe->pbus); 69374251fe2SBenjamin Herrenschmidt 694373f5657SGavin Shan return; 695373f5657SGavin Shan fail: 696373f5657SGavin Shan if (pe->tce32_seg >= 0) 697373f5657SGavin Shan pe->tce32_seg = -1; 698373f5657SGavin Shan if (tce_mem) 699373f5657SGavin Shan __free_pages(tce_mem, get_order(tce_table_size)); 700373f5657SGavin Shan } 701373f5657SGavin Shan 702cad5cef6SGreg Kroah-Hartman static void pnv_ioda_setup_dma(struct pnv_phb *phb) 703184cd4a3SBenjamin Herrenschmidt { 704184cd4a3SBenjamin Herrenschmidt struct pci_controller *hose = phb->hose; 705184cd4a3SBenjamin Herrenschmidt unsigned int residual, remaining, segs, tw, base; 706184cd4a3SBenjamin Herrenschmidt struct pnv_ioda_pe *pe; 707184cd4a3SBenjamin Herrenschmidt 708184cd4a3SBenjamin Herrenschmidt /* If we have more PE# than segments available, hand out one 709184cd4a3SBenjamin Herrenschmidt * per PE until we run out and let the rest fail. If not, 710184cd4a3SBenjamin Herrenschmidt * then we assign at least one segment per PE, plus more based 711184cd4a3SBenjamin Herrenschmidt * on the amount of devices under that PE 712184cd4a3SBenjamin Herrenschmidt */ 713184cd4a3SBenjamin Herrenschmidt if (phb->ioda.dma_pe_count > phb->ioda.tce32_count) 714184cd4a3SBenjamin Herrenschmidt residual = 0; 715184cd4a3SBenjamin Herrenschmidt else 716184cd4a3SBenjamin Herrenschmidt residual = phb->ioda.tce32_count - 717184cd4a3SBenjamin Herrenschmidt phb->ioda.dma_pe_count; 718184cd4a3SBenjamin Herrenschmidt 719184cd4a3SBenjamin Herrenschmidt pr_info("PCI: Domain %04x has %ld available 32-bit DMA segments\n", 720184cd4a3SBenjamin Herrenschmidt hose->global_number, phb->ioda.tce32_count); 721184cd4a3SBenjamin Herrenschmidt pr_info("PCI: %d PE# for a total weight of %d\n", 722184cd4a3SBenjamin Herrenschmidt phb->ioda.dma_pe_count, phb->ioda.dma_weight); 723184cd4a3SBenjamin Herrenschmidt 724184cd4a3SBenjamin Herrenschmidt /* Walk our PE list and configure their DMA segments, hand them 725184cd4a3SBenjamin Herrenschmidt * out one base segment plus any residual segments based on 726184cd4a3SBenjamin Herrenschmidt * weight 727184cd4a3SBenjamin Herrenschmidt */ 728184cd4a3SBenjamin Herrenschmidt remaining = phb->ioda.tce32_count; 729184cd4a3SBenjamin Herrenschmidt tw = phb->ioda.dma_weight; 730184cd4a3SBenjamin Herrenschmidt base = 0; 7317ebdf956SGavin Shan list_for_each_entry(pe, &phb->ioda.pe_dma_list, dma_link) { 732184cd4a3SBenjamin Herrenschmidt if (!pe->dma_weight) 733184cd4a3SBenjamin Herrenschmidt continue; 734184cd4a3SBenjamin Herrenschmidt if (!remaining) { 735184cd4a3SBenjamin Herrenschmidt pe_warn(pe, "No DMA32 resources available\n"); 736184cd4a3SBenjamin Herrenschmidt continue; 737184cd4a3SBenjamin Herrenschmidt } 738184cd4a3SBenjamin Herrenschmidt segs = 1; 739184cd4a3SBenjamin Herrenschmidt if (residual) { 740184cd4a3SBenjamin Herrenschmidt segs += ((pe->dma_weight * residual) + (tw / 2)) / tw; 741184cd4a3SBenjamin Herrenschmidt if (segs > remaining) 742184cd4a3SBenjamin Herrenschmidt segs = remaining; 743184cd4a3SBenjamin Herrenschmidt } 744373f5657SGavin Shan 745373f5657SGavin Shan /* 746373f5657SGavin Shan * For IODA2 compliant PHB3, we needn't care about the weight. 747373f5657SGavin Shan * The all available 32-bits DMA space will be assigned to 748373f5657SGavin Shan * the specific PE. 749373f5657SGavin Shan */ 750373f5657SGavin Shan if (phb->type == PNV_PHB_IODA1) { 751184cd4a3SBenjamin Herrenschmidt pe_info(pe, "DMA weight %d, assigned %d DMA32 segments\n", 752184cd4a3SBenjamin Herrenschmidt pe->dma_weight, segs); 753184cd4a3SBenjamin Herrenschmidt pnv_pci_ioda_setup_dma_pe(phb, pe, base, segs); 754373f5657SGavin Shan } else { 755373f5657SGavin Shan pe_info(pe, "Assign DMA32 space\n"); 756373f5657SGavin Shan segs = 0; 757373f5657SGavin Shan pnv_pci_ioda2_setup_dma_pe(phb, pe); 758373f5657SGavin Shan } 759373f5657SGavin Shan 760184cd4a3SBenjamin Herrenschmidt remaining -= segs; 761184cd4a3SBenjamin Herrenschmidt base += segs; 762184cd4a3SBenjamin Herrenschmidt } 763184cd4a3SBenjamin Herrenschmidt } 764184cd4a3SBenjamin Herrenschmidt 765184cd4a3SBenjamin Herrenschmidt #ifdef CONFIG_PCI_MSI 766137436c9SGavin Shan static void pnv_ioda2_msi_eoi(struct irq_data *d) 767137436c9SGavin Shan { 768137436c9SGavin Shan unsigned int hw_irq = (unsigned int)irqd_to_hwirq(d); 769137436c9SGavin Shan struct irq_chip *chip = irq_data_get_irq_chip(d); 770137436c9SGavin Shan struct pnv_phb *phb = container_of(chip, struct pnv_phb, 771137436c9SGavin Shan ioda.irq_chip); 772137436c9SGavin Shan int64_t rc; 773137436c9SGavin Shan 774137436c9SGavin Shan rc = opal_pci_msi_eoi(phb->opal_id, hw_irq); 775137436c9SGavin Shan WARN_ON_ONCE(rc); 776137436c9SGavin Shan 777137436c9SGavin Shan icp_native_eoi(d); 778137436c9SGavin Shan } 779137436c9SGavin Shan 780184cd4a3SBenjamin Herrenschmidt static int pnv_pci_ioda_msi_setup(struct pnv_phb *phb, struct pci_dev *dev, 781137436c9SGavin Shan unsigned int hwirq, unsigned int virq, 782137436c9SGavin Shan unsigned int is_64, struct msi_msg *msg) 783184cd4a3SBenjamin Herrenschmidt { 784184cd4a3SBenjamin Herrenschmidt struct pnv_ioda_pe *pe = pnv_ioda_get_pe(dev); 785b72c1f65SBenjamin Herrenschmidt struct pci_dn *pdn = pci_get_pdn(dev); 786137436c9SGavin Shan struct irq_data *idata; 787137436c9SGavin Shan struct irq_chip *ichip; 788184cd4a3SBenjamin Herrenschmidt unsigned int xive_num = hwirq - phb->msi_base; 789184cd4a3SBenjamin Herrenschmidt uint64_t addr64; 790184cd4a3SBenjamin Herrenschmidt uint32_t addr32, data; 791184cd4a3SBenjamin Herrenschmidt int rc; 792184cd4a3SBenjamin Herrenschmidt 793184cd4a3SBenjamin Herrenschmidt /* No PE assigned ? bail out ... no MSI for you ! */ 794184cd4a3SBenjamin Herrenschmidt if (pe == NULL) 795184cd4a3SBenjamin Herrenschmidt return -ENXIO; 796184cd4a3SBenjamin Herrenschmidt 797184cd4a3SBenjamin Herrenschmidt /* Check if we have an MVE */ 798184cd4a3SBenjamin Herrenschmidt if (pe->mve_number < 0) 799184cd4a3SBenjamin Herrenschmidt return -ENXIO; 800184cd4a3SBenjamin Herrenschmidt 801b72c1f65SBenjamin Herrenschmidt /* Force 32-bit MSI on some broken devices */ 802b72c1f65SBenjamin Herrenschmidt if (pdn && pdn->force_32bit_msi) 803b72c1f65SBenjamin Herrenschmidt is_64 = 0; 804b72c1f65SBenjamin Herrenschmidt 805184cd4a3SBenjamin Herrenschmidt /* Assign XIVE to PE */ 806184cd4a3SBenjamin Herrenschmidt rc = opal_pci_set_xive_pe(phb->opal_id, pe->pe_number, xive_num); 807184cd4a3SBenjamin Herrenschmidt if (rc) { 808184cd4a3SBenjamin Herrenschmidt pr_warn("%s: OPAL error %d setting XIVE %d PE\n", 809184cd4a3SBenjamin Herrenschmidt pci_name(dev), rc, xive_num); 810184cd4a3SBenjamin Herrenschmidt return -EIO; 811184cd4a3SBenjamin Herrenschmidt } 812184cd4a3SBenjamin Herrenschmidt 813184cd4a3SBenjamin Herrenschmidt if (is_64) { 814184cd4a3SBenjamin Herrenschmidt rc = opal_get_msi_64(phb->opal_id, pe->mve_number, xive_num, 1, 815184cd4a3SBenjamin Herrenschmidt &addr64, &data); 816184cd4a3SBenjamin Herrenschmidt if (rc) { 817184cd4a3SBenjamin Herrenschmidt pr_warn("%s: OPAL error %d getting 64-bit MSI data\n", 818184cd4a3SBenjamin Herrenschmidt pci_name(dev), rc); 819184cd4a3SBenjamin Herrenschmidt return -EIO; 820184cd4a3SBenjamin Herrenschmidt } 821184cd4a3SBenjamin Herrenschmidt msg->address_hi = addr64 >> 32; 822184cd4a3SBenjamin Herrenschmidt msg->address_lo = addr64 & 0xfffffffful; 823184cd4a3SBenjamin Herrenschmidt } else { 824184cd4a3SBenjamin Herrenschmidt rc = opal_get_msi_32(phb->opal_id, pe->mve_number, xive_num, 1, 825184cd4a3SBenjamin Herrenschmidt &addr32, &data); 826184cd4a3SBenjamin Herrenschmidt if (rc) { 827184cd4a3SBenjamin Herrenschmidt pr_warn("%s: OPAL error %d getting 32-bit MSI data\n", 828184cd4a3SBenjamin Herrenschmidt pci_name(dev), rc); 829184cd4a3SBenjamin Herrenschmidt return -EIO; 830184cd4a3SBenjamin Herrenschmidt } 831184cd4a3SBenjamin Herrenschmidt msg->address_hi = 0; 832184cd4a3SBenjamin Herrenschmidt msg->address_lo = addr32; 833184cd4a3SBenjamin Herrenschmidt } 834184cd4a3SBenjamin Herrenschmidt msg->data = data; 835184cd4a3SBenjamin Herrenschmidt 836137436c9SGavin Shan /* 837137436c9SGavin Shan * Change the IRQ chip for the MSI interrupts on PHB3. 838137436c9SGavin Shan * The corresponding IRQ chip should be populated for 839137436c9SGavin Shan * the first time. 840137436c9SGavin Shan */ 841137436c9SGavin Shan if (phb->type == PNV_PHB_IODA2) { 842137436c9SGavin Shan if (!phb->ioda.irq_chip_init) { 843137436c9SGavin Shan idata = irq_get_irq_data(virq); 844137436c9SGavin Shan ichip = irq_data_get_irq_chip(idata); 845137436c9SGavin Shan phb->ioda.irq_chip_init = 1; 846137436c9SGavin Shan phb->ioda.irq_chip = *ichip; 847137436c9SGavin Shan phb->ioda.irq_chip.irq_eoi = pnv_ioda2_msi_eoi; 848137436c9SGavin Shan } 849137436c9SGavin Shan 850137436c9SGavin Shan irq_set_chip(virq, &phb->ioda.irq_chip); 851137436c9SGavin Shan } 852137436c9SGavin Shan 853184cd4a3SBenjamin Herrenschmidt pr_devel("%s: %s-bit MSI on hwirq %x (xive #%d)," 854184cd4a3SBenjamin Herrenschmidt " address=%x_%08x data=%x PE# %d\n", 855184cd4a3SBenjamin Herrenschmidt pci_name(dev), is_64 ? "64" : "32", hwirq, xive_num, 856184cd4a3SBenjamin Herrenschmidt msg->address_hi, msg->address_lo, data, pe->pe_number); 857184cd4a3SBenjamin Herrenschmidt 858184cd4a3SBenjamin Herrenschmidt return 0; 859184cd4a3SBenjamin Herrenschmidt } 860184cd4a3SBenjamin Herrenschmidt 861184cd4a3SBenjamin Herrenschmidt static void pnv_pci_init_ioda_msis(struct pnv_phb *phb) 862184cd4a3SBenjamin Herrenschmidt { 863fb1b55d6SGavin Shan unsigned int count; 864184cd4a3SBenjamin Herrenschmidt const __be32 *prop = of_get_property(phb->hose->dn, 865184cd4a3SBenjamin Herrenschmidt "ibm,opal-msi-ranges", NULL); 866184cd4a3SBenjamin Herrenschmidt if (!prop) { 867184cd4a3SBenjamin Herrenschmidt /* BML Fallback */ 868184cd4a3SBenjamin Herrenschmidt prop = of_get_property(phb->hose->dn, "msi-ranges", NULL); 869184cd4a3SBenjamin Herrenschmidt } 870184cd4a3SBenjamin Herrenschmidt if (!prop) 871184cd4a3SBenjamin Herrenschmidt return; 872184cd4a3SBenjamin Herrenschmidt 873184cd4a3SBenjamin Herrenschmidt phb->msi_base = be32_to_cpup(prop); 874fb1b55d6SGavin Shan count = be32_to_cpup(prop + 1); 875fb1b55d6SGavin Shan if (msi_bitmap_alloc(&phb->msi_bmp, count, phb->hose->dn)) { 876184cd4a3SBenjamin Herrenschmidt pr_err("PCI %d: Failed to allocate MSI bitmap !\n", 877184cd4a3SBenjamin Herrenschmidt phb->hose->global_number); 878184cd4a3SBenjamin Herrenschmidt return; 879184cd4a3SBenjamin Herrenschmidt } 880fb1b55d6SGavin Shan 881184cd4a3SBenjamin Herrenschmidt phb->msi_setup = pnv_pci_ioda_msi_setup; 882184cd4a3SBenjamin Herrenschmidt phb->msi32_support = 1; 883184cd4a3SBenjamin Herrenschmidt pr_info(" Allocated bitmap for %d MSIs (base IRQ 0x%x)\n", 884fb1b55d6SGavin Shan count, phb->msi_base); 885184cd4a3SBenjamin Herrenschmidt } 886184cd4a3SBenjamin Herrenschmidt #else 887184cd4a3SBenjamin Herrenschmidt static void pnv_pci_init_ioda_msis(struct pnv_phb *phb) { } 888184cd4a3SBenjamin Herrenschmidt #endif /* CONFIG_PCI_MSI */ 889184cd4a3SBenjamin Herrenschmidt 89011685becSGavin Shan /* 89111685becSGavin Shan * This function is supposed to be called on basis of PE from top 89211685becSGavin Shan * to bottom style. So the the I/O or MMIO segment assigned to 89311685becSGavin Shan * parent PE could be overrided by its child PEs if necessary. 89411685becSGavin Shan */ 895cad5cef6SGreg Kroah-Hartman static void pnv_ioda_setup_pe_seg(struct pci_controller *hose, 89611685becSGavin Shan struct pnv_ioda_pe *pe) 89711685becSGavin Shan { 89811685becSGavin Shan struct pnv_phb *phb = hose->private_data; 89911685becSGavin Shan struct pci_bus_region region; 90011685becSGavin Shan struct resource *res; 90111685becSGavin Shan int i, index; 90211685becSGavin Shan int rc; 90311685becSGavin Shan 90411685becSGavin Shan /* 90511685becSGavin Shan * NOTE: We only care PCI bus based PE for now. For PCI 90611685becSGavin Shan * device based PE, for example SRIOV sensitive VF should 90711685becSGavin Shan * be figured out later. 90811685becSGavin Shan */ 90911685becSGavin Shan BUG_ON(!(pe->flags & (PNV_IODA_PE_BUS | PNV_IODA_PE_BUS_ALL))); 91011685becSGavin Shan 91111685becSGavin Shan pci_bus_for_each_resource(pe->pbus, res, i) { 91211685becSGavin Shan if (!res || !res->flags || 91311685becSGavin Shan res->start > res->end) 91411685becSGavin Shan continue; 91511685becSGavin Shan 91611685becSGavin Shan if (res->flags & IORESOURCE_IO) { 91711685becSGavin Shan region.start = res->start - phb->ioda.io_pci_base; 91811685becSGavin Shan region.end = res->end - phb->ioda.io_pci_base; 91911685becSGavin Shan index = region.start / phb->ioda.io_segsize; 92011685becSGavin Shan 92111685becSGavin Shan while (index < phb->ioda.total_pe && 92211685becSGavin Shan region.start <= region.end) { 92311685becSGavin Shan phb->ioda.io_segmap[index] = pe->pe_number; 92411685becSGavin Shan rc = opal_pci_map_pe_mmio_window(phb->opal_id, 92511685becSGavin Shan pe->pe_number, OPAL_IO_WINDOW_TYPE, 0, index); 92611685becSGavin Shan if (rc != OPAL_SUCCESS) { 92711685becSGavin Shan pr_err("%s: OPAL error %d when mapping IO " 92811685becSGavin Shan "segment #%d to PE#%d\n", 92911685becSGavin Shan __func__, rc, index, pe->pe_number); 93011685becSGavin Shan break; 93111685becSGavin Shan } 93211685becSGavin Shan 93311685becSGavin Shan region.start += phb->ioda.io_segsize; 93411685becSGavin Shan index++; 93511685becSGavin Shan } 93611685becSGavin Shan } else if (res->flags & IORESOURCE_MEM) { 9373fd47f06SBenjamin Herrenschmidt /* WARNING: Assumes M32 is mem region 0 in PHB. We need to 9383fd47f06SBenjamin Herrenschmidt * harden that algorithm when we start supporting M64 9393fd47f06SBenjamin Herrenschmidt */ 94011685becSGavin Shan region.start = res->start - 9413fd47f06SBenjamin Herrenschmidt hose->mem_offset[0] - 94211685becSGavin Shan phb->ioda.m32_pci_base; 94311685becSGavin Shan region.end = res->end - 9443fd47f06SBenjamin Herrenschmidt hose->mem_offset[0] - 94511685becSGavin Shan phb->ioda.m32_pci_base; 94611685becSGavin Shan index = region.start / phb->ioda.m32_segsize; 94711685becSGavin Shan 94811685becSGavin Shan while (index < phb->ioda.total_pe && 94911685becSGavin Shan region.start <= region.end) { 95011685becSGavin Shan phb->ioda.m32_segmap[index] = pe->pe_number; 95111685becSGavin Shan rc = opal_pci_map_pe_mmio_window(phb->opal_id, 95211685becSGavin Shan pe->pe_number, OPAL_M32_WINDOW_TYPE, 0, index); 95311685becSGavin Shan if (rc != OPAL_SUCCESS) { 95411685becSGavin Shan pr_err("%s: OPAL error %d when mapping M32 " 95511685becSGavin Shan "segment#%d to PE#%d", 95611685becSGavin Shan __func__, rc, index, pe->pe_number); 95711685becSGavin Shan break; 95811685becSGavin Shan } 95911685becSGavin Shan 96011685becSGavin Shan region.start += phb->ioda.m32_segsize; 96111685becSGavin Shan index++; 96211685becSGavin Shan } 96311685becSGavin Shan } 96411685becSGavin Shan } 96511685becSGavin Shan } 96611685becSGavin Shan 967cad5cef6SGreg Kroah-Hartman static void pnv_pci_ioda_setup_seg(void) 96811685becSGavin Shan { 96911685becSGavin Shan struct pci_controller *tmp, *hose; 97011685becSGavin Shan struct pnv_phb *phb; 97111685becSGavin Shan struct pnv_ioda_pe *pe; 97211685becSGavin Shan 97311685becSGavin Shan list_for_each_entry_safe(hose, tmp, &hose_list, list_node) { 97411685becSGavin Shan phb = hose->private_data; 97511685becSGavin Shan list_for_each_entry(pe, &phb->ioda.pe_list, list) { 97611685becSGavin Shan pnv_ioda_setup_pe_seg(hose, pe); 97711685becSGavin Shan } 97811685becSGavin Shan } 97911685becSGavin Shan } 98011685becSGavin Shan 981cad5cef6SGreg Kroah-Hartman static void pnv_pci_ioda_setup_DMA(void) 98213395c48SGavin Shan { 98313395c48SGavin Shan struct pci_controller *hose, *tmp; 984db1266c8SGavin Shan struct pnv_phb *phb; 98513395c48SGavin Shan 98613395c48SGavin Shan list_for_each_entry_safe(hose, tmp, &hose_list, list_node) { 98713395c48SGavin Shan pnv_ioda_setup_dma(hose->private_data); 988db1266c8SGavin Shan 989db1266c8SGavin Shan /* Mark the PHB initialization done */ 990db1266c8SGavin Shan phb = hose->private_data; 991db1266c8SGavin Shan phb->initialized = 1; 99213395c48SGavin Shan } 99313395c48SGavin Shan } 99413395c48SGavin Shan 99537c367f2SGavin Shan static void pnv_pci_ioda_create_dbgfs(void) 99637c367f2SGavin Shan { 99737c367f2SGavin Shan #ifdef CONFIG_DEBUG_FS 99837c367f2SGavin Shan struct pci_controller *hose, *tmp; 99937c367f2SGavin Shan struct pnv_phb *phb; 100037c367f2SGavin Shan char name[16]; 100137c367f2SGavin Shan 100237c367f2SGavin Shan list_for_each_entry_safe(hose, tmp, &hose_list, list_node) { 100337c367f2SGavin Shan phb = hose->private_data; 100437c367f2SGavin Shan 100537c367f2SGavin Shan sprintf(name, "PCI%04x", hose->global_number); 100637c367f2SGavin Shan phb->dbgfs = debugfs_create_dir(name, powerpc_debugfs_root); 100737c367f2SGavin Shan if (!phb->dbgfs) 100837c367f2SGavin Shan pr_warning("%s: Error on creating debugfs on PHB#%x\n", 100937c367f2SGavin Shan __func__, hose->global_number); 101037c367f2SGavin Shan } 101137c367f2SGavin Shan #endif /* CONFIG_DEBUG_FS */ 101237c367f2SGavin Shan } 101337c367f2SGavin Shan 1014cad5cef6SGreg Kroah-Hartman static void pnv_pci_ioda_fixup(void) 1015fb446ad0SGavin Shan { 1016fb446ad0SGavin Shan pnv_pci_ioda_setup_PEs(); 101711685becSGavin Shan pnv_pci_ioda_setup_seg(); 101813395c48SGavin Shan pnv_pci_ioda_setup_DMA(); 1019e9cc17d4SGavin Shan 102037c367f2SGavin Shan pnv_pci_ioda_create_dbgfs(); 102137c367f2SGavin Shan 1022e9cc17d4SGavin Shan #ifdef CONFIG_EEH 102388b6d14bSGavin Shan eeh_probe_mode_set(EEH_PROBE_MODE_DEV); 1024e9cc17d4SGavin Shan eeh_addr_cache_build(); 1025e9cc17d4SGavin Shan eeh_init(); 1026e9cc17d4SGavin Shan #endif 1027fb446ad0SGavin Shan } 1028fb446ad0SGavin Shan 1029271fd03aSGavin Shan /* 1030271fd03aSGavin Shan * Returns the alignment for I/O or memory windows for P2P 1031271fd03aSGavin Shan * bridges. That actually depends on how PEs are segmented. 1032271fd03aSGavin Shan * For now, we return I/O or M32 segment size for PE sensitive 1033271fd03aSGavin Shan * P2P bridges. Otherwise, the default values (4KiB for I/O, 1034271fd03aSGavin Shan * 1MiB for memory) will be returned. 1035271fd03aSGavin Shan * 1036271fd03aSGavin Shan * The current PCI bus might be put into one PE, which was 1037271fd03aSGavin Shan * create against the parent PCI bridge. For that case, we 1038271fd03aSGavin Shan * needn't enlarge the alignment so that we can save some 1039271fd03aSGavin Shan * resources. 1040271fd03aSGavin Shan */ 1041271fd03aSGavin Shan static resource_size_t pnv_pci_window_alignment(struct pci_bus *bus, 1042271fd03aSGavin Shan unsigned long type) 1043271fd03aSGavin Shan { 1044271fd03aSGavin Shan struct pci_dev *bridge; 1045271fd03aSGavin Shan struct pci_controller *hose = pci_bus_to_host(bus); 1046271fd03aSGavin Shan struct pnv_phb *phb = hose->private_data; 1047271fd03aSGavin Shan int num_pci_bridges = 0; 1048271fd03aSGavin Shan 1049271fd03aSGavin Shan bridge = bus->self; 1050271fd03aSGavin Shan while (bridge) { 1051271fd03aSGavin Shan if (pci_pcie_type(bridge) == PCI_EXP_TYPE_PCI_BRIDGE) { 1052271fd03aSGavin Shan num_pci_bridges++; 1053271fd03aSGavin Shan if (num_pci_bridges >= 2) 1054271fd03aSGavin Shan return 1; 1055271fd03aSGavin Shan } 1056271fd03aSGavin Shan 1057271fd03aSGavin Shan bridge = bridge->bus->self; 1058271fd03aSGavin Shan } 1059271fd03aSGavin Shan 1060271fd03aSGavin Shan /* We need support prefetchable memory window later */ 1061271fd03aSGavin Shan if (type & IORESOURCE_MEM) 1062271fd03aSGavin Shan return phb->ioda.m32_segsize; 1063271fd03aSGavin Shan 1064271fd03aSGavin Shan return phb->ioda.io_segsize; 1065271fd03aSGavin Shan } 1066271fd03aSGavin Shan 1067184cd4a3SBenjamin Herrenschmidt /* Prevent enabling devices for which we couldn't properly 1068184cd4a3SBenjamin Herrenschmidt * assign a PE 1069184cd4a3SBenjamin Herrenschmidt */ 1070cad5cef6SGreg Kroah-Hartman static int pnv_pci_enable_device_hook(struct pci_dev *dev) 1071184cd4a3SBenjamin Herrenschmidt { 1072db1266c8SGavin Shan struct pci_controller *hose = pci_bus_to_host(dev->bus); 1073db1266c8SGavin Shan struct pnv_phb *phb = hose->private_data; 1074db1266c8SGavin Shan struct pci_dn *pdn; 1075184cd4a3SBenjamin Herrenschmidt 1076db1266c8SGavin Shan /* The function is probably called while the PEs have 1077db1266c8SGavin Shan * not be created yet. For example, resource reassignment 1078db1266c8SGavin Shan * during PCI probe period. We just skip the check if 1079db1266c8SGavin Shan * PEs isn't ready. 1080db1266c8SGavin Shan */ 1081db1266c8SGavin Shan if (!phb->initialized) 1082db1266c8SGavin Shan return 0; 1083db1266c8SGavin Shan 1084b72c1f65SBenjamin Herrenschmidt pdn = pci_get_pdn(dev); 1085184cd4a3SBenjamin Herrenschmidt if (!pdn || pdn->pe_number == IODA_INVALID_PE) 1086184cd4a3SBenjamin Herrenschmidt return -EINVAL; 1087db1266c8SGavin Shan 1088184cd4a3SBenjamin Herrenschmidt return 0; 1089184cd4a3SBenjamin Herrenschmidt } 1090184cd4a3SBenjamin Herrenschmidt 1091184cd4a3SBenjamin Herrenschmidt static u32 pnv_ioda_bdfn_to_pe(struct pnv_phb *phb, struct pci_bus *bus, 1092184cd4a3SBenjamin Herrenschmidt u32 devfn) 1093184cd4a3SBenjamin Herrenschmidt { 1094184cd4a3SBenjamin Herrenschmidt return phb->ioda.pe_rmap[(bus->number << 8) | devfn]; 1095184cd4a3SBenjamin Herrenschmidt } 1096184cd4a3SBenjamin Herrenschmidt 109773ed148aSBenjamin Herrenschmidt static void pnv_pci_ioda_shutdown(struct pnv_phb *phb) 109873ed148aSBenjamin Herrenschmidt { 109973ed148aSBenjamin Herrenschmidt opal_pci_reset(phb->opal_id, OPAL_PCI_IODA_TABLE_RESET, 110073ed148aSBenjamin Herrenschmidt OPAL_ASSERT_RESET); 110173ed148aSBenjamin Herrenschmidt } 110273ed148aSBenjamin Herrenschmidt 1103e9cc17d4SGavin Shan void __init pnv_pci_init_ioda_phb(struct device_node *np, 1104e9cc17d4SGavin Shan u64 hub_id, int ioda_type) 1105184cd4a3SBenjamin Herrenschmidt { 1106184cd4a3SBenjamin Herrenschmidt struct pci_controller *hose; 1107184cd4a3SBenjamin Herrenschmidt struct pnv_phb *phb; 1108184cd4a3SBenjamin Herrenschmidt unsigned long size, m32map_off, iomap_off, pemap_off; 1109c681b93cSAlistair Popple const __be64 *prop64; 1110aa0c033fSGavin Shan const u32 *prop32; 1111f1b7cc3eSGavin Shan int len; 1112184cd4a3SBenjamin Herrenschmidt u64 phb_id; 1113184cd4a3SBenjamin Herrenschmidt void *aux; 1114184cd4a3SBenjamin Herrenschmidt long rc; 1115184cd4a3SBenjamin Herrenschmidt 1116aa0c033fSGavin Shan pr_info("Initializing IODA%d OPAL PHB %s\n", ioda_type, np->full_name); 1117184cd4a3SBenjamin Herrenschmidt 1118184cd4a3SBenjamin Herrenschmidt prop64 = of_get_property(np, "ibm,opal-phbid", NULL); 1119184cd4a3SBenjamin Herrenschmidt if (!prop64) { 1120184cd4a3SBenjamin Herrenschmidt pr_err(" Missing \"ibm,opal-phbid\" property !\n"); 1121184cd4a3SBenjamin Herrenschmidt return; 1122184cd4a3SBenjamin Herrenschmidt } 1123184cd4a3SBenjamin Herrenschmidt phb_id = be64_to_cpup(prop64); 1124184cd4a3SBenjamin Herrenschmidt pr_debug(" PHB-ID : 0x%016llx\n", phb_id); 1125184cd4a3SBenjamin Herrenschmidt 1126184cd4a3SBenjamin Herrenschmidt phb = alloc_bootmem(sizeof(struct pnv_phb)); 112758d714ecSGavin Shan if (!phb) { 112858d714ecSGavin Shan pr_err(" Out of memory !\n"); 112958d714ecSGavin Shan return; 113058d714ecSGavin Shan } 113158d714ecSGavin Shan 113258d714ecSGavin Shan /* Allocate PCI controller */ 1133184cd4a3SBenjamin Herrenschmidt memset(phb, 0, sizeof(struct pnv_phb)); 1134184cd4a3SBenjamin Herrenschmidt phb->hose = hose = pcibios_alloc_controller(np); 113558d714ecSGavin Shan if (!phb->hose) { 113658d714ecSGavin Shan pr_err(" Can't allocate PCI controller for %s\n", 1137184cd4a3SBenjamin Herrenschmidt np->full_name); 113858d714ecSGavin Shan free_bootmem((unsigned long)phb, sizeof(struct pnv_phb)); 1139184cd4a3SBenjamin Herrenschmidt return; 1140184cd4a3SBenjamin Herrenschmidt } 1141184cd4a3SBenjamin Herrenschmidt 1142184cd4a3SBenjamin Herrenschmidt spin_lock_init(&phb->lock); 1143f1b7cc3eSGavin Shan prop32 = of_get_property(np, "bus-range", &len); 1144f1b7cc3eSGavin Shan if (prop32 && len == 8) { 1145f1b7cc3eSGavin Shan hose->first_busno = prop32[0]; 1146f1b7cc3eSGavin Shan hose->last_busno = prop32[1]; 1147f1b7cc3eSGavin Shan } else { 1148f1b7cc3eSGavin Shan pr_warn(" Broken <bus-range> on %s\n", np->full_name); 1149184cd4a3SBenjamin Herrenschmidt hose->first_busno = 0; 1150184cd4a3SBenjamin Herrenschmidt hose->last_busno = 0xff; 1151f1b7cc3eSGavin Shan } 1152184cd4a3SBenjamin Herrenschmidt hose->private_data = phb; 1153e9cc17d4SGavin Shan phb->hub_id = hub_id; 1154184cd4a3SBenjamin Herrenschmidt phb->opal_id = phb_id; 1155aa0c033fSGavin Shan phb->type = ioda_type; 1156184cd4a3SBenjamin Herrenschmidt 1157cee72d5bSBenjamin Herrenschmidt /* Detect specific models for error handling */ 1158cee72d5bSBenjamin Herrenschmidt if (of_device_is_compatible(np, "ibm,p7ioc-pciex")) 1159cee72d5bSBenjamin Herrenschmidt phb->model = PNV_PHB_MODEL_P7IOC; 1160f3d40c25SBenjamin Herrenschmidt else if (of_device_is_compatible(np, "ibm,power8-pciex")) 1161aa0c033fSGavin Shan phb->model = PNV_PHB_MODEL_PHB3; 1162cee72d5bSBenjamin Herrenschmidt else 1163cee72d5bSBenjamin Herrenschmidt phb->model = PNV_PHB_MODEL_UNKNOWN; 1164cee72d5bSBenjamin Herrenschmidt 1165aa0c033fSGavin Shan /* Parse 32-bit and IO ranges (if any) */ 11662f1ec02eSGavin Shan pci_process_bridge_OF_ranges(hose, np, !hose->global_number); 1167184cd4a3SBenjamin Herrenschmidt 1168aa0c033fSGavin Shan /* Get registers */ 1169184cd4a3SBenjamin Herrenschmidt phb->regs = of_iomap(np, 0); 1170184cd4a3SBenjamin Herrenschmidt if (phb->regs == NULL) 1171184cd4a3SBenjamin Herrenschmidt pr_err(" Failed to map registers !\n"); 1172184cd4a3SBenjamin Herrenschmidt 1173184cd4a3SBenjamin Herrenschmidt /* Initialize more IODA stuff */ 1174aa0c033fSGavin Shan prop32 = of_get_property(np, "ibm,opal-num-pes", NULL); 1175aa0c033fSGavin Shan if (!prop32) 1176aa0c033fSGavin Shan phb->ioda.total_pe = 1; 1177aa0c033fSGavin Shan else 1178aa0c033fSGavin Shan phb->ioda.total_pe = *prop32; 1179184cd4a3SBenjamin Herrenschmidt 1180184cd4a3SBenjamin Herrenschmidt phb->ioda.m32_size = resource_size(&hose->mem_resources[0]); 1181aa0c033fSGavin Shan /* FW Has already off top 64k of M32 space (MSI space) */ 1182184cd4a3SBenjamin Herrenschmidt phb->ioda.m32_size += 0x10000; 1183184cd4a3SBenjamin Herrenschmidt 1184184cd4a3SBenjamin Herrenschmidt phb->ioda.m32_segsize = phb->ioda.m32_size / phb->ioda.total_pe; 11853fd47f06SBenjamin Herrenschmidt phb->ioda.m32_pci_base = hose->mem_resources[0].start - hose->mem_offset[0]; 1186184cd4a3SBenjamin Herrenschmidt phb->ioda.io_size = hose->pci_io_size; 1187184cd4a3SBenjamin Herrenschmidt phb->ioda.io_segsize = phb->ioda.io_size / phb->ioda.total_pe; 1188184cd4a3SBenjamin Herrenschmidt phb->ioda.io_pci_base = 0; /* XXX calculate this ? */ 1189184cd4a3SBenjamin Herrenschmidt 1190c35d2a8cSGavin Shan /* Allocate aux data & arrays. We don't have IO ports on PHB3 */ 1191184cd4a3SBenjamin Herrenschmidt size = _ALIGN_UP(phb->ioda.total_pe / 8, sizeof(unsigned long)); 1192184cd4a3SBenjamin Herrenschmidt m32map_off = size; 1193e47747f4SGavin Shan size += phb->ioda.total_pe * sizeof(phb->ioda.m32_segmap[0]); 1194184cd4a3SBenjamin Herrenschmidt iomap_off = size; 1195c35d2a8cSGavin Shan if (phb->type == PNV_PHB_IODA1) { 1196c35d2a8cSGavin Shan iomap_off = size; 1197e47747f4SGavin Shan size += phb->ioda.total_pe * sizeof(phb->ioda.io_segmap[0]); 1198c35d2a8cSGavin Shan } 1199184cd4a3SBenjamin Herrenschmidt pemap_off = size; 1200184cd4a3SBenjamin Herrenschmidt size += phb->ioda.total_pe * sizeof(struct pnv_ioda_pe); 1201184cd4a3SBenjamin Herrenschmidt aux = alloc_bootmem(size); 1202184cd4a3SBenjamin Herrenschmidt memset(aux, 0, size); 1203184cd4a3SBenjamin Herrenschmidt phb->ioda.pe_alloc = aux; 1204184cd4a3SBenjamin Herrenschmidt phb->ioda.m32_segmap = aux + m32map_off; 1205c35d2a8cSGavin Shan if (phb->type == PNV_PHB_IODA1) 1206184cd4a3SBenjamin Herrenschmidt phb->ioda.io_segmap = aux + iomap_off; 1207184cd4a3SBenjamin Herrenschmidt phb->ioda.pe_array = aux + pemap_off; 1208184cd4a3SBenjamin Herrenschmidt set_bit(0, phb->ioda.pe_alloc); 1209184cd4a3SBenjamin Herrenschmidt 12107ebdf956SGavin Shan INIT_LIST_HEAD(&phb->ioda.pe_dma_list); 1211184cd4a3SBenjamin Herrenschmidt INIT_LIST_HEAD(&phb->ioda.pe_list); 1212184cd4a3SBenjamin Herrenschmidt 1213184cd4a3SBenjamin Herrenschmidt /* Calculate how many 32-bit TCE segments we have */ 1214184cd4a3SBenjamin Herrenschmidt phb->ioda.tce32_count = phb->ioda.m32_pci_base >> 28; 1215184cd4a3SBenjamin Herrenschmidt 1216184cd4a3SBenjamin Herrenschmidt /* Clear unusable m64 */ 1217184cd4a3SBenjamin Herrenschmidt hose->mem_resources[1].flags = 0; 1218184cd4a3SBenjamin Herrenschmidt hose->mem_resources[1].start = 0; 1219184cd4a3SBenjamin Herrenschmidt hose->mem_resources[1].end = 0; 1220184cd4a3SBenjamin Herrenschmidt hose->mem_resources[2].flags = 0; 1221184cd4a3SBenjamin Herrenschmidt hose->mem_resources[2].start = 0; 1222184cd4a3SBenjamin Herrenschmidt hose->mem_resources[2].end = 0; 1223184cd4a3SBenjamin Herrenschmidt 1224aa0c033fSGavin Shan #if 0 /* We should really do that ... */ 1225184cd4a3SBenjamin Herrenschmidt rc = opal_pci_set_phb_mem_window(opal->phb_id, 1226184cd4a3SBenjamin Herrenschmidt window_type, 1227184cd4a3SBenjamin Herrenschmidt window_num, 1228184cd4a3SBenjamin Herrenschmidt starting_real_address, 1229184cd4a3SBenjamin Herrenschmidt starting_pci_address, 1230184cd4a3SBenjamin Herrenschmidt segment_size); 1231184cd4a3SBenjamin Herrenschmidt #endif 1232184cd4a3SBenjamin Herrenschmidt 1233184cd4a3SBenjamin Herrenschmidt pr_info(" %d PE's M32: 0x%x [segment=0x%x] IO: 0x%x [segment=0x%x]\n", 1234184cd4a3SBenjamin Herrenschmidt phb->ioda.total_pe, 1235184cd4a3SBenjamin Herrenschmidt phb->ioda.m32_size, phb->ioda.m32_segsize, 1236184cd4a3SBenjamin Herrenschmidt phb->ioda.io_size, phb->ioda.io_segsize); 1237184cd4a3SBenjamin Herrenschmidt 1238184cd4a3SBenjamin Herrenschmidt phb->hose->ops = &pnv_pci_ops; 1239e9cc17d4SGavin Shan #ifdef CONFIG_EEH 1240e9cc17d4SGavin Shan phb->eeh_ops = &ioda_eeh_ops; 1241e9cc17d4SGavin Shan #endif 1242184cd4a3SBenjamin Herrenschmidt 1243184cd4a3SBenjamin Herrenschmidt /* Setup RID -> PE mapping function */ 1244184cd4a3SBenjamin Herrenschmidt phb->bdfn_to_pe = pnv_ioda_bdfn_to_pe; 1245184cd4a3SBenjamin Herrenschmidt 1246184cd4a3SBenjamin Herrenschmidt /* Setup TCEs */ 1247184cd4a3SBenjamin Herrenschmidt phb->dma_dev_setup = pnv_pci_ioda_dma_dev_setup; 1248184cd4a3SBenjamin Herrenschmidt 124973ed148aSBenjamin Herrenschmidt /* Setup shutdown function for kexec */ 125073ed148aSBenjamin Herrenschmidt phb->shutdown = pnv_pci_ioda_shutdown; 125173ed148aSBenjamin Herrenschmidt 1252184cd4a3SBenjamin Herrenschmidt /* Setup MSI support */ 1253184cd4a3SBenjamin Herrenschmidt pnv_pci_init_ioda_msis(phb); 1254184cd4a3SBenjamin Herrenschmidt 1255c40a4210SGavin Shan /* 1256c40a4210SGavin Shan * We pass the PCI probe flag PCI_REASSIGN_ALL_RSRC here 1257c40a4210SGavin Shan * to let the PCI core do resource assignment. It's supposed 1258c40a4210SGavin Shan * that the PCI core will do correct I/O and MMIO alignment 1259c40a4210SGavin Shan * for the P2P bridge bars so that each PCI bus (excluding 1260c40a4210SGavin Shan * the child P2P bridges) can form individual PE. 1261184cd4a3SBenjamin Herrenschmidt */ 1262fb446ad0SGavin Shan ppc_md.pcibios_fixup = pnv_pci_ioda_fixup; 1263184cd4a3SBenjamin Herrenschmidt ppc_md.pcibios_enable_device_hook = pnv_pci_enable_device_hook; 1264271fd03aSGavin Shan ppc_md.pcibios_window_alignment = pnv_pci_window_alignment; 1265c40a4210SGavin Shan pci_add_flags(PCI_REASSIGN_ALL_RSRC); 1266184cd4a3SBenjamin Herrenschmidt 1267184cd4a3SBenjamin Herrenschmidt /* Reset IODA tables to a clean state */ 1268f11fe552SBenjamin Herrenschmidt rc = opal_pci_reset(phb_id, OPAL_PCI_IODA_TABLE_RESET, OPAL_ASSERT_RESET); 1269184cd4a3SBenjamin Herrenschmidt if (rc) 1270f11fe552SBenjamin Herrenschmidt pr_warning(" OPAL Error %ld performing IODA table reset !\n", rc); 1271aa0c033fSGavin Shan 1272aa0c033fSGavin Shan /* 1273aa0c033fSGavin Shan * On IODA1 map everything to PE#0, on IODA2 we assume the IODA reset 1274aa0c033fSGavin Shan * has cleared the RTT which has the same effect 1275aa0c033fSGavin Shan */ 1276aa0c033fSGavin Shan if (ioda_type == PNV_PHB_IODA1) 1277184cd4a3SBenjamin Herrenschmidt opal_pci_set_pe(phb_id, 0, 0, 7, 1, 1 , OPAL_MAP_PE); 1278184cd4a3SBenjamin Herrenschmidt } 1279184cd4a3SBenjamin Herrenschmidt 128067975005SBjorn Helgaas void __init pnv_pci_init_ioda2_phb(struct device_node *np) 1281aa0c033fSGavin Shan { 1282e9cc17d4SGavin Shan pnv_pci_init_ioda_phb(np, 0, PNV_PHB_IODA2); 1283aa0c033fSGavin Shan } 1284aa0c033fSGavin Shan 1285184cd4a3SBenjamin Herrenschmidt void __init pnv_pci_init_ioda_hub(struct device_node *np) 1286184cd4a3SBenjamin Herrenschmidt { 1287184cd4a3SBenjamin Herrenschmidt struct device_node *phbn; 1288c681b93cSAlistair Popple const __be64 *prop64; 1289184cd4a3SBenjamin Herrenschmidt u64 hub_id; 1290184cd4a3SBenjamin Herrenschmidt 1291184cd4a3SBenjamin Herrenschmidt pr_info("Probing IODA IO-Hub %s\n", np->full_name); 1292184cd4a3SBenjamin Herrenschmidt 1293184cd4a3SBenjamin Herrenschmidt prop64 = of_get_property(np, "ibm,opal-hubid", NULL); 1294184cd4a3SBenjamin Herrenschmidt if (!prop64) { 1295184cd4a3SBenjamin Herrenschmidt pr_err(" Missing \"ibm,opal-hubid\" property !\n"); 1296184cd4a3SBenjamin Herrenschmidt return; 1297184cd4a3SBenjamin Herrenschmidt } 1298184cd4a3SBenjamin Herrenschmidt hub_id = be64_to_cpup(prop64); 1299184cd4a3SBenjamin Herrenschmidt pr_devel(" HUB-ID : 0x%016llx\n", hub_id); 1300184cd4a3SBenjamin Herrenschmidt 1301184cd4a3SBenjamin Herrenschmidt /* Count child PHBs */ 1302184cd4a3SBenjamin Herrenschmidt for_each_child_of_node(np, phbn) { 1303184cd4a3SBenjamin Herrenschmidt /* Look for IODA1 PHBs */ 1304184cd4a3SBenjamin Herrenschmidt if (of_device_is_compatible(phbn, "ibm,ioda-phb")) 1305e9cc17d4SGavin Shan pnv_pci_init_ioda_phb(phbn, hub_id, PNV_PHB_IODA1); 1306184cd4a3SBenjamin Herrenschmidt } 1307184cd4a3SBenjamin Herrenschmidt } 1308