1184cd4a3SBenjamin Herrenschmidt /* 2184cd4a3SBenjamin Herrenschmidt * Support PCI/PCIe on PowerNV platforms 3184cd4a3SBenjamin Herrenschmidt * 4184cd4a3SBenjamin Herrenschmidt * Copyright 2011 Benjamin Herrenschmidt, IBM Corp. 5184cd4a3SBenjamin Herrenschmidt * 6184cd4a3SBenjamin Herrenschmidt * This program is free software; you can redistribute it and/or 7184cd4a3SBenjamin Herrenschmidt * modify it under the terms of the GNU General Public License 8184cd4a3SBenjamin Herrenschmidt * as published by the Free Software Foundation; either version 9184cd4a3SBenjamin Herrenschmidt * 2 of the License, or (at your option) any later version. 10184cd4a3SBenjamin Herrenschmidt */ 11184cd4a3SBenjamin Herrenschmidt 12cee72d5bSBenjamin Herrenschmidt #undef DEBUG 13184cd4a3SBenjamin Herrenschmidt 14184cd4a3SBenjamin Herrenschmidt #include <linux/kernel.h> 15184cd4a3SBenjamin Herrenschmidt #include <linux/pci.h> 16361f2a2aSGavin Shan #include <linux/crash_dump.h> 17184cd4a3SBenjamin Herrenschmidt #include <linux/delay.h> 18184cd4a3SBenjamin Herrenschmidt #include <linux/string.h> 19184cd4a3SBenjamin Herrenschmidt #include <linux/init.h> 2057c8a661SMike Rapoport #include <linux/memblock.h> 21184cd4a3SBenjamin Herrenschmidt #include <linux/irq.h> 22184cd4a3SBenjamin Herrenschmidt #include <linux/io.h> 23184cd4a3SBenjamin Herrenschmidt #include <linux/msi.h> 24ac9a5889SAlexey Kardashevskiy #include <linux/iommu.h> 25e57080f1SAlexey Kardashevskiy #include <linux/rculist.h> 264793d65dSAlexey Kardashevskiy #include <linux/sizes.h> 27184cd4a3SBenjamin Herrenschmidt 28184cd4a3SBenjamin Herrenschmidt #include <asm/sections.h> 29184cd4a3SBenjamin Herrenschmidt #include <asm/io.h> 30184cd4a3SBenjamin Herrenschmidt #include <asm/prom.h> 31184cd4a3SBenjamin Herrenschmidt #include <asm/pci-bridge.h> 32184cd4a3SBenjamin Herrenschmidt #include <asm/machdep.h> 33fb1b55d6SGavin Shan #include <asm/msi_bitmap.h> 34184cd4a3SBenjamin Herrenschmidt #include <asm/ppc-pci.h> 35184cd4a3SBenjamin Herrenschmidt #include <asm/opal.h> 36184cd4a3SBenjamin Herrenschmidt #include <asm/iommu.h> 37184cd4a3SBenjamin Herrenschmidt #include <asm/tce.h> 38137436c9SGavin Shan #include <asm/xics.h> 397644d581SMichael Ellerman #include <asm/debugfs.h> 40262af557SGuo Chao #include <asm/firmware.h> 4180c49c7eSIan Munsie #include <asm/pnv-pci.h> 42aca6913fSAlexey Kardashevskiy #include <asm/mmzone.h> 4380c49c7eSIan Munsie 44ec249dd8SMichael Neuling #include <misc/cxl-base.h> 45184cd4a3SBenjamin Herrenschmidt 46184cd4a3SBenjamin Herrenschmidt #include "powernv.h" 47184cd4a3SBenjamin Herrenschmidt #include "pci.h" 4844bda4b7SHari Vyas #include "../../../../drivers/pci/pci.h" 49184cd4a3SBenjamin Herrenschmidt 5099451551SGavin Shan #define PNV_IODA1_M64_NUM 16 /* Number of M64 BARs */ 5199451551SGavin Shan #define PNV_IODA1_M64_SEGS 8 /* Segments per M64 BAR */ 52acce971cSGavin Shan #define PNV_IODA1_DMA32_SEGSIZE 0x10000000 53781a868fSWei Yang 547f2c39e9SFrederic Barrat static const char * const pnv_phb_names[] = { "IODA1", "IODA2", "NPU_NVLINK", 557f2c39e9SFrederic Barrat "NPU_OCAPI" }; 56aca6913fSAlexey Kardashevskiy 57c498a4f9SChristoph Hellwig static void pnv_pci_ioda2_set_bypass(struct pnv_ioda_pe *pe, bool enable); 58c498a4f9SChristoph Hellwig 597d623e42SAlexey Kardashevskiy void pe_level_printk(const struct pnv_ioda_pe *pe, const char *level, 606d31c2faSJoe Perches const char *fmt, ...) 616d31c2faSJoe Perches { 626d31c2faSJoe Perches struct va_format vaf; 636d31c2faSJoe Perches va_list args; 646d31c2faSJoe Perches char pfix[32]; 65184cd4a3SBenjamin Herrenschmidt 666d31c2faSJoe Perches va_start(args, fmt); 676d31c2faSJoe Perches 686d31c2faSJoe Perches vaf.fmt = fmt; 696d31c2faSJoe Perches vaf.va = &args; 706d31c2faSJoe Perches 71781a868fSWei Yang if (pe->flags & PNV_IODA_PE_DEV) 726d31c2faSJoe Perches strlcpy(pfix, dev_name(&pe->pdev->dev), sizeof(pfix)); 73781a868fSWei Yang else if (pe->flags & (PNV_IODA_PE_BUS | PNV_IODA_PE_BUS_ALL)) 746d31c2faSJoe Perches sprintf(pfix, "%04x:%02x ", 756d31c2faSJoe Perches pci_domain_nr(pe->pbus), pe->pbus->number); 76781a868fSWei Yang #ifdef CONFIG_PCI_IOV 77781a868fSWei Yang else if (pe->flags & PNV_IODA_PE_VF) 78781a868fSWei Yang sprintf(pfix, "%04x:%02x:%2x.%d", 79781a868fSWei Yang pci_domain_nr(pe->parent_dev->bus), 80781a868fSWei Yang (pe->rid & 0xff00) >> 8, 81781a868fSWei Yang PCI_SLOT(pe->rid), PCI_FUNC(pe->rid)); 82781a868fSWei Yang #endif /* CONFIG_PCI_IOV*/ 836d31c2faSJoe Perches 841f52f176SRussell Currey printk("%spci %s: [PE# %.2x] %pV", 856d31c2faSJoe Perches level, pfix, pe->pe_number, &vaf); 866d31c2faSJoe Perches 876d31c2faSJoe Perches va_end(args); 886d31c2faSJoe Perches } 896d31c2faSJoe Perches 904e287840SThadeu Lima de Souza Cascardo static bool pnv_iommu_bypass_disabled __read_mostly; 9145baee14SGuilherme G. Piccoli static bool pci_reset_phbs __read_mostly; 924e287840SThadeu Lima de Souza Cascardo 934e287840SThadeu Lima de Souza Cascardo static int __init iommu_setup(char *str) 944e287840SThadeu Lima de Souza Cascardo { 954e287840SThadeu Lima de Souza Cascardo if (!str) 964e287840SThadeu Lima de Souza Cascardo return -EINVAL; 974e287840SThadeu Lima de Souza Cascardo 984e287840SThadeu Lima de Souza Cascardo while (*str) { 994e287840SThadeu Lima de Souza Cascardo if (!strncmp(str, "nobypass", 8)) { 1004e287840SThadeu Lima de Souza Cascardo pnv_iommu_bypass_disabled = true; 1014e287840SThadeu Lima de Souza Cascardo pr_info("PowerNV: IOMMU bypass window disabled.\n"); 1024e287840SThadeu Lima de Souza Cascardo break; 1034e287840SThadeu Lima de Souza Cascardo } 1044e287840SThadeu Lima de Souza Cascardo str += strcspn(str, ","); 1054e287840SThadeu Lima de Souza Cascardo if (*str == ',') 1064e287840SThadeu Lima de Souza Cascardo str++; 1074e287840SThadeu Lima de Souza Cascardo } 1084e287840SThadeu Lima de Souza Cascardo 1094e287840SThadeu Lima de Souza Cascardo return 0; 1104e287840SThadeu Lima de Souza Cascardo } 1114e287840SThadeu Lima de Souza Cascardo early_param("iommu", iommu_setup); 1124e287840SThadeu Lima de Souza Cascardo 11345baee14SGuilherme G. Piccoli static int __init pci_reset_phbs_setup(char *str) 11445baee14SGuilherme G. Piccoli { 11545baee14SGuilherme G. Piccoli pci_reset_phbs = true; 11645baee14SGuilherme G. Piccoli return 0; 11745baee14SGuilherme G. Piccoli } 11845baee14SGuilherme G. Piccoli 11945baee14SGuilherme G. Piccoli early_param("ppc_pci_reset_phbs", pci_reset_phbs_setup); 12045baee14SGuilherme G. Piccoli 1215958d19aSBenjamin Herrenschmidt static inline bool pnv_pci_is_m64(struct pnv_phb *phb, struct resource *r) 122262af557SGuo Chao { 1235958d19aSBenjamin Herrenschmidt /* 1245958d19aSBenjamin Herrenschmidt * WARNING: We cannot rely on the resource flags. The Linux PCI 1255958d19aSBenjamin Herrenschmidt * allocation code sometimes decides to put a 64-bit prefetchable 1265958d19aSBenjamin Herrenschmidt * BAR in the 32-bit window, so we have to compare the addresses. 1275958d19aSBenjamin Herrenschmidt * 1285958d19aSBenjamin Herrenschmidt * For simplicity we only test resource start. 1295958d19aSBenjamin Herrenschmidt */ 1305958d19aSBenjamin Herrenschmidt return (r->start >= phb->ioda.m64_base && 1315958d19aSBenjamin Herrenschmidt r->start < (phb->ioda.m64_base + phb->ioda.m64_size)); 132262af557SGuo Chao } 133262af557SGuo Chao 134b79331a5SRussell Currey static inline bool pnv_pci_is_m64_flags(unsigned long resource_flags) 135b79331a5SRussell Currey { 136b79331a5SRussell Currey unsigned long flags = (IORESOURCE_MEM_64 | IORESOURCE_PREFETCH); 137b79331a5SRussell Currey 138b79331a5SRussell Currey return (resource_flags & flags) == flags; 139b79331a5SRussell Currey } 140b79331a5SRussell Currey 1411e916772SGavin Shan static struct pnv_ioda_pe *pnv_ioda_init_pe(struct pnv_phb *phb, int pe_no) 1421e916772SGavin Shan { 143313483ddSGavin Shan s64 rc; 144313483ddSGavin Shan 1451e916772SGavin Shan phb->ioda.pe_array[pe_no].phb = phb; 1461e916772SGavin Shan phb->ioda.pe_array[pe_no].pe_number = pe_no; 1471e916772SGavin Shan 148313483ddSGavin Shan /* 149313483ddSGavin Shan * Clear the PE frozen state as it might be put into frozen state 150313483ddSGavin Shan * in the last PCI remove path. It's not harmful to do so when the 151313483ddSGavin Shan * PE is already in unfrozen state. 152313483ddSGavin Shan */ 153313483ddSGavin Shan rc = opal_pci_eeh_freeze_clear(phb->opal_id, pe_no, 154313483ddSGavin Shan OPAL_EEH_ACTION_CLEAR_FREEZE_ALL); 155d4791db5SRussell Currey if (rc != OPAL_SUCCESS && rc != OPAL_UNSUPPORTED) 1561f52f176SRussell Currey pr_warn("%s: Error %lld unfreezing PHB#%x-PE#%x\n", 157313483ddSGavin Shan __func__, rc, phb->hose->global_number, pe_no); 158313483ddSGavin Shan 1591e916772SGavin Shan return &phb->ioda.pe_array[pe_no]; 1601e916772SGavin Shan } 1611e916772SGavin Shan 1624b82ab18SGavin Shan static void pnv_ioda_reserve_pe(struct pnv_phb *phb, int pe_no) 1634b82ab18SGavin Shan { 16492b8f137SGavin Shan if (!(pe_no >= 0 && pe_no < phb->ioda.total_pe_num)) { 1651f52f176SRussell Currey pr_warn("%s: Invalid PE %x on PHB#%x\n", 1664b82ab18SGavin Shan __func__, pe_no, phb->hose->global_number); 1674b82ab18SGavin Shan return; 1684b82ab18SGavin Shan } 1694b82ab18SGavin Shan 170e9dc4d7fSGavin Shan if (test_and_set_bit(pe_no, phb->ioda.pe_alloc)) 1711f52f176SRussell Currey pr_debug("%s: PE %x was reserved on PHB#%x\n", 1724b82ab18SGavin Shan __func__, pe_no, phb->hose->global_number); 1734b82ab18SGavin Shan 1741e916772SGavin Shan pnv_ioda_init_pe(phb, pe_no); 1754b82ab18SGavin Shan } 1764b82ab18SGavin Shan 1771e916772SGavin Shan static struct pnv_ioda_pe *pnv_ioda_alloc_pe(struct pnv_phb *phb) 178184cd4a3SBenjamin Herrenschmidt { 17960964816SAndrzej Hajda long pe; 180184cd4a3SBenjamin Herrenschmidt 1819fcd6f4aSGavin Shan for (pe = phb->ioda.total_pe_num - 1; pe >= 0; pe--) { 1829fcd6f4aSGavin Shan if (!test_and_set_bit(pe, phb->ioda.pe_alloc)) 1831e916772SGavin Shan return pnv_ioda_init_pe(phb, pe); 184184cd4a3SBenjamin Herrenschmidt } 185184cd4a3SBenjamin Herrenschmidt 1869fcd6f4aSGavin Shan return NULL; 1879fcd6f4aSGavin Shan } 1889fcd6f4aSGavin Shan 1891e916772SGavin Shan static void pnv_ioda_free_pe(struct pnv_ioda_pe *pe) 190184cd4a3SBenjamin Herrenschmidt { 1911e916772SGavin Shan struct pnv_phb *phb = pe->phb; 192caa58f80SGavin Shan unsigned int pe_num = pe->pe_number; 193184cd4a3SBenjamin Herrenschmidt 1941e916772SGavin Shan WARN_ON(pe->pdev); 1950bd97167SAlexey Kardashevskiy WARN_ON(pe->npucomp); /* NPUs are not supposed to be freed */ 1960bd97167SAlexey Kardashevskiy kfree(pe->npucomp); 1971e916772SGavin Shan memset(pe, 0, sizeof(struct pnv_ioda_pe)); 198caa58f80SGavin Shan clear_bit(pe_num, phb->ioda.pe_alloc); 199184cd4a3SBenjamin Herrenschmidt } 200184cd4a3SBenjamin Herrenschmidt 201262af557SGuo Chao /* The default M64 BAR is shared by all PEs */ 202262af557SGuo Chao static int pnv_ioda2_init_m64(struct pnv_phb *phb) 203262af557SGuo Chao { 204262af557SGuo Chao const char *desc; 205262af557SGuo Chao struct resource *r; 206262af557SGuo Chao s64 rc; 207262af557SGuo Chao 208262af557SGuo Chao /* Configure the default M64 BAR */ 209262af557SGuo Chao rc = opal_pci_set_phb_mem_window(phb->opal_id, 210262af557SGuo Chao OPAL_M64_WINDOW_TYPE, 211262af557SGuo Chao phb->ioda.m64_bar_idx, 212262af557SGuo Chao phb->ioda.m64_base, 213262af557SGuo Chao 0, /* unused */ 214262af557SGuo Chao phb->ioda.m64_size); 215262af557SGuo Chao if (rc != OPAL_SUCCESS) { 216262af557SGuo Chao desc = "configuring"; 217262af557SGuo Chao goto fail; 218262af557SGuo Chao } 219262af557SGuo Chao 220262af557SGuo Chao /* Enable the default M64 BAR */ 221262af557SGuo Chao rc = opal_pci_phb_mmio_enable(phb->opal_id, 222262af557SGuo Chao OPAL_M64_WINDOW_TYPE, 223262af557SGuo Chao phb->ioda.m64_bar_idx, 224262af557SGuo Chao OPAL_ENABLE_M64_SPLIT); 225262af557SGuo Chao if (rc != OPAL_SUCCESS) { 226262af557SGuo Chao desc = "enabling"; 227262af557SGuo Chao goto fail; 228262af557SGuo Chao } 229262af557SGuo Chao 230262af557SGuo Chao /* 23163803c39SGavin Shan * Exclude the segments for reserved and root bus PE, which 23263803c39SGavin Shan * are first or last two PEs. 233262af557SGuo Chao */ 234262af557SGuo Chao r = &phb->hose->mem_resources[1]; 23592b8f137SGavin Shan if (phb->ioda.reserved_pe_idx == 0) 23663803c39SGavin Shan r->start += (2 * phb->ioda.m64_segsize); 23792b8f137SGavin Shan else if (phb->ioda.reserved_pe_idx == (phb->ioda.total_pe_num - 1)) 23863803c39SGavin Shan r->end -= (2 * phb->ioda.m64_segsize); 239262af557SGuo Chao else 2401f52f176SRussell Currey pr_warn(" Cannot strip M64 segment for reserved PE#%x\n", 24192b8f137SGavin Shan phb->ioda.reserved_pe_idx); 242262af557SGuo Chao 243262af557SGuo Chao return 0; 244262af557SGuo Chao 245262af557SGuo Chao fail: 246262af557SGuo Chao pr_warn(" Failure %lld %s M64 BAR#%d\n", 247262af557SGuo Chao rc, desc, phb->ioda.m64_bar_idx); 248262af557SGuo Chao opal_pci_phb_mmio_enable(phb->opal_id, 249262af557SGuo Chao OPAL_M64_WINDOW_TYPE, 250262af557SGuo Chao phb->ioda.m64_bar_idx, 251262af557SGuo Chao OPAL_DISABLE_M64); 252262af557SGuo Chao return -EIO; 253262af557SGuo Chao } 254262af557SGuo Chao 255c430670aSGavin Shan static void pnv_ioda_reserve_dev_m64_pe(struct pci_dev *pdev, 25696a2f92bSGavin Shan unsigned long *pe_bitmap) 257262af557SGuo Chao { 25896a2f92bSGavin Shan struct pci_controller *hose = pci_bus_to_host(pdev->bus); 25996a2f92bSGavin Shan struct pnv_phb *phb = hose->private_data; 260262af557SGuo Chao struct resource *r; 26196a2f92bSGavin Shan resource_size_t base, sgsz, start, end; 26296a2f92bSGavin Shan int segno, i; 263262af557SGuo Chao 26496a2f92bSGavin Shan base = phb->ioda.m64_base; 26596a2f92bSGavin Shan sgsz = phb->ioda.m64_segsize; 26696a2f92bSGavin Shan for (i = 0; i <= PCI_ROM_RESOURCE; i++) { 26796a2f92bSGavin Shan r = &pdev->resource[i]; 2685958d19aSBenjamin Herrenschmidt if (!r->parent || !pnv_pci_is_m64(phb, r)) 269262af557SGuo Chao continue; 270262af557SGuo Chao 27196a2f92bSGavin Shan start = _ALIGN_DOWN(r->start - base, sgsz); 27296a2f92bSGavin Shan end = _ALIGN_UP(r->end - base, sgsz); 27396a2f92bSGavin Shan for (segno = start / sgsz; segno < end / sgsz; segno++) { 27496a2f92bSGavin Shan if (pe_bitmap) 27596a2f92bSGavin Shan set_bit(segno, pe_bitmap); 27696a2f92bSGavin Shan else 27796a2f92bSGavin Shan pnv_ioda_reserve_pe(phb, segno); 278262af557SGuo Chao } 279262af557SGuo Chao } 280262af557SGuo Chao } 281262af557SGuo Chao 28299451551SGavin Shan static int pnv_ioda1_init_m64(struct pnv_phb *phb) 28399451551SGavin Shan { 28499451551SGavin Shan struct resource *r; 28599451551SGavin Shan int index; 28699451551SGavin Shan 28799451551SGavin Shan /* 28899451551SGavin Shan * There are 16 M64 BARs, each of which has 8 segments. So 28999451551SGavin Shan * there are as many M64 segments as the maximum number of 29099451551SGavin Shan * PEs, which is 128. 29199451551SGavin Shan */ 29299451551SGavin Shan for (index = 0; index < PNV_IODA1_M64_NUM; index++) { 29399451551SGavin Shan unsigned long base, segsz = phb->ioda.m64_segsize; 29499451551SGavin Shan int64_t rc; 29599451551SGavin Shan 29699451551SGavin Shan base = phb->ioda.m64_base + 29799451551SGavin Shan index * PNV_IODA1_M64_SEGS * segsz; 29899451551SGavin Shan rc = opal_pci_set_phb_mem_window(phb->opal_id, 29999451551SGavin Shan OPAL_M64_WINDOW_TYPE, index, base, 0, 30099451551SGavin Shan PNV_IODA1_M64_SEGS * segsz); 30199451551SGavin Shan if (rc != OPAL_SUCCESS) { 3021f52f176SRussell Currey pr_warn(" Error %lld setting M64 PHB#%x-BAR#%d\n", 30399451551SGavin Shan rc, phb->hose->global_number, index); 30499451551SGavin Shan goto fail; 30599451551SGavin Shan } 30699451551SGavin Shan 30799451551SGavin Shan rc = opal_pci_phb_mmio_enable(phb->opal_id, 30899451551SGavin Shan OPAL_M64_WINDOW_TYPE, index, 30999451551SGavin Shan OPAL_ENABLE_M64_SPLIT); 31099451551SGavin Shan if (rc != OPAL_SUCCESS) { 3111f52f176SRussell Currey pr_warn(" Error %lld enabling M64 PHB#%x-BAR#%d\n", 31299451551SGavin Shan rc, phb->hose->global_number, index); 31399451551SGavin Shan goto fail; 31499451551SGavin Shan } 31599451551SGavin Shan } 31699451551SGavin Shan 31799451551SGavin Shan /* 31863803c39SGavin Shan * Exclude the segments for reserved and root bus PE, which 31963803c39SGavin Shan * are first or last two PEs. 32099451551SGavin Shan */ 32199451551SGavin Shan r = &phb->hose->mem_resources[1]; 32299451551SGavin Shan if (phb->ioda.reserved_pe_idx == 0) 32363803c39SGavin Shan r->start += (2 * phb->ioda.m64_segsize); 32499451551SGavin Shan else if (phb->ioda.reserved_pe_idx == (phb->ioda.total_pe_num - 1)) 32563803c39SGavin Shan r->end -= (2 * phb->ioda.m64_segsize); 32699451551SGavin Shan else 3271f52f176SRussell Currey WARN(1, "Wrong reserved PE#%x on PHB#%x\n", 32899451551SGavin Shan phb->ioda.reserved_pe_idx, phb->hose->global_number); 32999451551SGavin Shan 33099451551SGavin Shan return 0; 33199451551SGavin Shan 33299451551SGavin Shan fail: 33399451551SGavin Shan for ( ; index >= 0; index--) 33499451551SGavin Shan opal_pci_phb_mmio_enable(phb->opal_id, 33599451551SGavin Shan OPAL_M64_WINDOW_TYPE, index, OPAL_DISABLE_M64); 33699451551SGavin Shan 33799451551SGavin Shan return -EIO; 33899451551SGavin Shan } 33999451551SGavin Shan 340c430670aSGavin Shan static void pnv_ioda_reserve_m64_pe(struct pci_bus *bus, 34196a2f92bSGavin Shan unsigned long *pe_bitmap, 34296a2f92bSGavin Shan bool all) 343262af557SGuo Chao { 344262af557SGuo Chao struct pci_dev *pdev; 34596a2f92bSGavin Shan 34696a2f92bSGavin Shan list_for_each_entry(pdev, &bus->devices, bus_list) { 347c430670aSGavin Shan pnv_ioda_reserve_dev_m64_pe(pdev, pe_bitmap); 34896a2f92bSGavin Shan 34996a2f92bSGavin Shan if (all && pdev->subordinate) 350c430670aSGavin Shan pnv_ioda_reserve_m64_pe(pdev->subordinate, 35196a2f92bSGavin Shan pe_bitmap, all); 35296a2f92bSGavin Shan } 35396a2f92bSGavin Shan } 35496a2f92bSGavin Shan 3551e916772SGavin Shan static struct pnv_ioda_pe *pnv_ioda_pick_m64_pe(struct pci_bus *bus, bool all) 356262af557SGuo Chao { 35726ba248dSGavin Shan struct pci_controller *hose = pci_bus_to_host(bus); 35826ba248dSGavin Shan struct pnv_phb *phb = hose->private_data; 359262af557SGuo Chao struct pnv_ioda_pe *master_pe, *pe; 360262af557SGuo Chao unsigned long size, *pe_alloc; 36126ba248dSGavin Shan int i; 362262af557SGuo Chao 363262af557SGuo Chao /* Root bus shouldn't use M64 */ 364262af557SGuo Chao if (pci_is_root_bus(bus)) 3651e916772SGavin Shan return NULL; 366262af557SGuo Chao 367262af557SGuo Chao /* Allocate bitmap */ 36892b8f137SGavin Shan size = _ALIGN_UP(phb->ioda.total_pe_num / 8, sizeof(unsigned long)); 369262af557SGuo Chao pe_alloc = kzalloc(size, GFP_KERNEL); 370262af557SGuo Chao if (!pe_alloc) { 371262af557SGuo Chao pr_warn("%s: Out of memory !\n", 372262af557SGuo Chao __func__); 3731e916772SGavin Shan return NULL; 374262af557SGuo Chao } 375262af557SGuo Chao 37626ba248dSGavin Shan /* Figure out reserved PE numbers by the PE */ 377c430670aSGavin Shan pnv_ioda_reserve_m64_pe(bus, pe_alloc, all); 378262af557SGuo Chao 379262af557SGuo Chao /* 380262af557SGuo Chao * the current bus might not own M64 window and that's all 381262af557SGuo Chao * contributed by its child buses. For the case, we needn't 382262af557SGuo Chao * pick M64 dependent PE#. 383262af557SGuo Chao */ 38492b8f137SGavin Shan if (bitmap_empty(pe_alloc, phb->ioda.total_pe_num)) { 385262af557SGuo Chao kfree(pe_alloc); 3861e916772SGavin Shan return NULL; 387262af557SGuo Chao } 388262af557SGuo Chao 389262af557SGuo Chao /* 390262af557SGuo Chao * Figure out the master PE and put all slave PEs to master 391262af557SGuo Chao * PE's list to form compound PE. 392262af557SGuo Chao */ 393262af557SGuo Chao master_pe = NULL; 394262af557SGuo Chao i = -1; 39592b8f137SGavin Shan while ((i = find_next_bit(pe_alloc, phb->ioda.total_pe_num, i + 1)) < 39692b8f137SGavin Shan phb->ioda.total_pe_num) { 397262af557SGuo Chao pe = &phb->ioda.pe_array[i]; 398262af557SGuo Chao 39993289d8cSGavin Shan phb->ioda.m64_segmap[pe->pe_number] = pe->pe_number; 400262af557SGuo Chao if (!master_pe) { 401262af557SGuo Chao pe->flags |= PNV_IODA_PE_MASTER; 402262af557SGuo Chao INIT_LIST_HEAD(&pe->slaves); 403262af557SGuo Chao master_pe = pe; 404262af557SGuo Chao } else { 405262af557SGuo Chao pe->flags |= PNV_IODA_PE_SLAVE; 406262af557SGuo Chao pe->master = master_pe; 407262af557SGuo Chao list_add_tail(&pe->list, &master_pe->slaves); 408262af557SGuo Chao } 40999451551SGavin Shan 41099451551SGavin Shan /* 41199451551SGavin Shan * P7IOC supports M64DT, which helps mapping M64 segment 41299451551SGavin Shan * to one particular PE#. However, PHB3 has fixed mapping 41399451551SGavin Shan * between M64 segment and PE#. In order to have same logic 41499451551SGavin Shan * for P7IOC and PHB3, we enforce fixed mapping between M64 41599451551SGavin Shan * segment and PE# on P7IOC. 41699451551SGavin Shan */ 41799451551SGavin Shan if (phb->type == PNV_PHB_IODA1) { 41899451551SGavin Shan int64_t rc; 41999451551SGavin Shan 42099451551SGavin Shan rc = opal_pci_map_pe_mmio_window(phb->opal_id, 42199451551SGavin Shan pe->pe_number, OPAL_M64_WINDOW_TYPE, 42299451551SGavin Shan pe->pe_number / PNV_IODA1_M64_SEGS, 42399451551SGavin Shan pe->pe_number % PNV_IODA1_M64_SEGS); 42499451551SGavin Shan if (rc != OPAL_SUCCESS) 4251f52f176SRussell Currey pr_warn("%s: Error %lld mapping M64 for PHB#%x-PE#%x\n", 42699451551SGavin Shan __func__, rc, phb->hose->global_number, 42799451551SGavin Shan pe->pe_number); 42899451551SGavin Shan } 429262af557SGuo Chao } 430262af557SGuo Chao 431262af557SGuo Chao kfree(pe_alloc); 4321e916772SGavin Shan return master_pe; 433262af557SGuo Chao } 434262af557SGuo Chao 435262af557SGuo Chao static void __init pnv_ioda_parse_m64_window(struct pnv_phb *phb) 436262af557SGuo Chao { 437262af557SGuo Chao struct pci_controller *hose = phb->hose; 438262af557SGuo Chao struct device_node *dn = hose->dn; 439262af557SGuo Chao struct resource *res; 440a1339fafSBenjamin Herrenschmidt u32 m64_range[2], i; 4410e7736c6SGavin Shan const __be32 *r; 442262af557SGuo Chao u64 pci_addr; 443262af557SGuo Chao 44499451551SGavin Shan if (phb->type != PNV_PHB_IODA1 && phb->type != PNV_PHB_IODA2) { 4451665c4a8SGavin Shan pr_info(" Not support M64 window\n"); 4461665c4a8SGavin Shan return; 4471665c4a8SGavin Shan } 4481665c4a8SGavin Shan 449e4d54f71SStewart Smith if (!firmware_has_feature(FW_FEATURE_OPAL)) { 450262af557SGuo Chao pr_info(" Firmware too old to support M64 window\n"); 451262af557SGuo Chao return; 452262af557SGuo Chao } 453262af557SGuo Chao 454262af557SGuo Chao r = of_get_property(dn, "ibm,opal-m64-window", NULL); 455262af557SGuo Chao if (!r) { 456b7c670d6SRob Herring pr_info(" No <ibm,opal-m64-window> on %pOF\n", 457b7c670d6SRob Herring dn); 458262af557SGuo Chao return; 459262af557SGuo Chao } 460262af557SGuo Chao 461a1339fafSBenjamin Herrenschmidt /* 462a1339fafSBenjamin Herrenschmidt * Find the available M64 BAR range and pickup the last one for 463a1339fafSBenjamin Herrenschmidt * covering the whole 64-bits space. We support only one range. 464a1339fafSBenjamin Herrenschmidt */ 465a1339fafSBenjamin Herrenschmidt if (of_property_read_u32_array(dn, "ibm,opal-available-m64-ranges", 466a1339fafSBenjamin Herrenschmidt m64_range, 2)) { 467a1339fafSBenjamin Herrenschmidt /* In absence of the property, assume 0..15 */ 468a1339fafSBenjamin Herrenschmidt m64_range[0] = 0; 469a1339fafSBenjamin Herrenschmidt m64_range[1] = 16; 470a1339fafSBenjamin Herrenschmidt } 471a1339fafSBenjamin Herrenschmidt /* We only support 64 bits in our allocator */ 472a1339fafSBenjamin Herrenschmidt if (m64_range[1] > 63) { 473a1339fafSBenjamin Herrenschmidt pr_warn("%s: Limiting M64 range to 63 (from %d) on PHB#%x\n", 474a1339fafSBenjamin Herrenschmidt __func__, m64_range[1], phb->hose->global_number); 475a1339fafSBenjamin Herrenschmidt m64_range[1] = 63; 476a1339fafSBenjamin Herrenschmidt } 477a1339fafSBenjamin Herrenschmidt /* Empty range, no m64 */ 478a1339fafSBenjamin Herrenschmidt if (m64_range[1] <= m64_range[0]) { 479a1339fafSBenjamin Herrenschmidt pr_warn("%s: M64 empty, disabling M64 usage on PHB#%x\n", 480a1339fafSBenjamin Herrenschmidt __func__, phb->hose->global_number); 481a1339fafSBenjamin Herrenschmidt return; 482a1339fafSBenjamin Herrenschmidt } 483a1339fafSBenjamin Herrenschmidt 484a1339fafSBenjamin Herrenschmidt /* Configure M64 informations */ 485262af557SGuo Chao res = &hose->mem_resources[1]; 486e80c4e7cSGavin Shan res->name = dn->full_name; 487262af557SGuo Chao res->start = of_translate_address(dn, r + 2); 488262af557SGuo Chao res->end = res->start + of_read_number(r + 4, 2) - 1; 489262af557SGuo Chao res->flags = (IORESOURCE_MEM | IORESOURCE_MEM_64 | IORESOURCE_PREFETCH); 490262af557SGuo Chao pci_addr = of_read_number(r, 2); 491262af557SGuo Chao hose->mem_offset[1] = res->start - pci_addr; 492262af557SGuo Chao 493262af557SGuo Chao phb->ioda.m64_size = resource_size(res); 49492b8f137SGavin Shan phb->ioda.m64_segsize = phb->ioda.m64_size / phb->ioda.total_pe_num; 495262af557SGuo Chao phb->ioda.m64_base = pci_addr; 496262af557SGuo Chao 497a1339fafSBenjamin Herrenschmidt /* This lines up nicely with the display from processing OF ranges */ 498a1339fafSBenjamin Herrenschmidt pr_info(" MEM 0x%016llx..0x%016llx -> 0x%016llx (M64 #%d..%d)\n", 499a1339fafSBenjamin Herrenschmidt res->start, res->end, pci_addr, m64_range[0], 500a1339fafSBenjamin Herrenschmidt m64_range[0] + m64_range[1] - 1); 501a1339fafSBenjamin Herrenschmidt 502a1339fafSBenjamin Herrenschmidt /* Mark all M64 used up by default */ 503a1339fafSBenjamin Herrenschmidt phb->ioda.m64_bar_alloc = (unsigned long)-1; 504e9863e68SWei Yang 505262af557SGuo Chao /* Use last M64 BAR to cover M64 window */ 506a1339fafSBenjamin Herrenschmidt m64_range[1]--; 507a1339fafSBenjamin Herrenschmidt phb->ioda.m64_bar_idx = m64_range[0] + m64_range[1]; 508a1339fafSBenjamin Herrenschmidt 509a1339fafSBenjamin Herrenschmidt pr_info(" Using M64 #%d as default window\n", phb->ioda.m64_bar_idx); 510a1339fafSBenjamin Herrenschmidt 511a1339fafSBenjamin Herrenschmidt /* Mark remaining ones free */ 512a1339fafSBenjamin Herrenschmidt for (i = m64_range[0]; i < m64_range[1]; i++) 513a1339fafSBenjamin Herrenschmidt clear_bit(i, &phb->ioda.m64_bar_alloc); 514a1339fafSBenjamin Herrenschmidt 515a1339fafSBenjamin Herrenschmidt /* 516a1339fafSBenjamin Herrenschmidt * Setup init functions for M64 based on IODA version, IODA3 uses 517a1339fafSBenjamin Herrenschmidt * the IODA2 code. 518a1339fafSBenjamin Herrenschmidt */ 51999451551SGavin Shan if (phb->type == PNV_PHB_IODA1) 52099451551SGavin Shan phb->init_m64 = pnv_ioda1_init_m64; 52199451551SGavin Shan else 522262af557SGuo Chao phb->init_m64 = pnv_ioda2_init_m64; 523262af557SGuo Chao } 524262af557SGuo Chao 52549dec922SGavin Shan static void pnv_ioda_freeze_pe(struct pnv_phb *phb, int pe_no) 52649dec922SGavin Shan { 52749dec922SGavin Shan struct pnv_ioda_pe *pe = &phb->ioda.pe_array[pe_no]; 52849dec922SGavin Shan struct pnv_ioda_pe *slave; 52949dec922SGavin Shan s64 rc; 53049dec922SGavin Shan 53149dec922SGavin Shan /* Fetch master PE */ 53249dec922SGavin Shan if (pe->flags & PNV_IODA_PE_SLAVE) { 53349dec922SGavin Shan pe = pe->master; 534ec8e4e9dSGavin Shan if (WARN_ON(!pe || !(pe->flags & PNV_IODA_PE_MASTER))) 535ec8e4e9dSGavin Shan return; 536ec8e4e9dSGavin Shan 53749dec922SGavin Shan pe_no = pe->pe_number; 53849dec922SGavin Shan } 53949dec922SGavin Shan 54049dec922SGavin Shan /* Freeze master PE */ 54149dec922SGavin Shan rc = opal_pci_eeh_freeze_set(phb->opal_id, 54249dec922SGavin Shan pe_no, 54349dec922SGavin Shan OPAL_EEH_ACTION_SET_FREEZE_ALL); 54449dec922SGavin Shan if (rc != OPAL_SUCCESS) { 54549dec922SGavin Shan pr_warn("%s: Failure %lld freezing PHB#%x-PE#%x\n", 54649dec922SGavin Shan __func__, rc, phb->hose->global_number, pe_no); 54749dec922SGavin Shan return; 54849dec922SGavin Shan } 54949dec922SGavin Shan 55049dec922SGavin Shan /* Freeze slave PEs */ 55149dec922SGavin Shan if (!(pe->flags & PNV_IODA_PE_MASTER)) 55249dec922SGavin Shan return; 55349dec922SGavin Shan 55449dec922SGavin Shan list_for_each_entry(slave, &pe->slaves, list) { 55549dec922SGavin Shan rc = opal_pci_eeh_freeze_set(phb->opal_id, 55649dec922SGavin Shan slave->pe_number, 55749dec922SGavin Shan OPAL_EEH_ACTION_SET_FREEZE_ALL); 55849dec922SGavin Shan if (rc != OPAL_SUCCESS) 55949dec922SGavin Shan pr_warn("%s: Failure %lld freezing PHB#%x-PE#%x\n", 56049dec922SGavin Shan __func__, rc, phb->hose->global_number, 56149dec922SGavin Shan slave->pe_number); 56249dec922SGavin Shan } 56349dec922SGavin Shan } 56449dec922SGavin Shan 565e51df2c1SAnton Blanchard static int pnv_ioda_unfreeze_pe(struct pnv_phb *phb, int pe_no, int opt) 56649dec922SGavin Shan { 56749dec922SGavin Shan struct pnv_ioda_pe *pe, *slave; 56849dec922SGavin Shan s64 rc; 56949dec922SGavin Shan 57049dec922SGavin Shan /* Find master PE */ 57149dec922SGavin Shan pe = &phb->ioda.pe_array[pe_no]; 57249dec922SGavin Shan if (pe->flags & PNV_IODA_PE_SLAVE) { 57349dec922SGavin Shan pe = pe->master; 57449dec922SGavin Shan WARN_ON(!pe || !(pe->flags & PNV_IODA_PE_MASTER)); 57549dec922SGavin Shan pe_no = pe->pe_number; 57649dec922SGavin Shan } 57749dec922SGavin Shan 57849dec922SGavin Shan /* Clear frozen state for master PE */ 57949dec922SGavin Shan rc = opal_pci_eeh_freeze_clear(phb->opal_id, pe_no, opt); 58049dec922SGavin Shan if (rc != OPAL_SUCCESS) { 58149dec922SGavin Shan pr_warn("%s: Failure %lld clear %d on PHB#%x-PE#%x\n", 58249dec922SGavin Shan __func__, rc, opt, phb->hose->global_number, pe_no); 58349dec922SGavin Shan return -EIO; 58449dec922SGavin Shan } 58549dec922SGavin Shan 58649dec922SGavin Shan if (!(pe->flags & PNV_IODA_PE_MASTER)) 58749dec922SGavin Shan return 0; 58849dec922SGavin Shan 58949dec922SGavin Shan /* Clear frozen state for slave PEs */ 59049dec922SGavin Shan list_for_each_entry(slave, &pe->slaves, list) { 59149dec922SGavin Shan rc = opal_pci_eeh_freeze_clear(phb->opal_id, 59249dec922SGavin Shan slave->pe_number, 59349dec922SGavin Shan opt); 59449dec922SGavin Shan if (rc != OPAL_SUCCESS) { 59549dec922SGavin Shan pr_warn("%s: Failure %lld clear %d on PHB#%x-PE#%x\n", 59649dec922SGavin Shan __func__, rc, opt, phb->hose->global_number, 59749dec922SGavin Shan slave->pe_number); 59849dec922SGavin Shan return -EIO; 59949dec922SGavin Shan } 60049dec922SGavin Shan } 60149dec922SGavin Shan 60249dec922SGavin Shan return 0; 60349dec922SGavin Shan } 60449dec922SGavin Shan 60549dec922SGavin Shan static int pnv_ioda_get_pe_state(struct pnv_phb *phb, int pe_no) 60649dec922SGavin Shan { 60749dec922SGavin Shan struct pnv_ioda_pe *slave, *pe; 608c2057701SAlexey Kardashevskiy u8 fstate = 0, state; 609c2057701SAlexey Kardashevskiy __be16 pcierr = 0; 61049dec922SGavin Shan s64 rc; 61149dec922SGavin Shan 61249dec922SGavin Shan /* Sanity check on PE number */ 61392b8f137SGavin Shan if (pe_no < 0 || pe_no >= phb->ioda.total_pe_num) 61449dec922SGavin Shan return OPAL_EEH_STOPPED_PERM_UNAVAIL; 61549dec922SGavin Shan 61649dec922SGavin Shan /* 61749dec922SGavin Shan * Fetch the master PE and the PE instance might be 61849dec922SGavin Shan * not initialized yet. 61949dec922SGavin Shan */ 62049dec922SGavin Shan pe = &phb->ioda.pe_array[pe_no]; 62149dec922SGavin Shan if (pe->flags & PNV_IODA_PE_SLAVE) { 62249dec922SGavin Shan pe = pe->master; 62349dec922SGavin Shan WARN_ON(!pe || !(pe->flags & PNV_IODA_PE_MASTER)); 62449dec922SGavin Shan pe_no = pe->pe_number; 62549dec922SGavin Shan } 62649dec922SGavin Shan 62749dec922SGavin Shan /* Check the master PE */ 62849dec922SGavin Shan rc = opal_pci_eeh_freeze_status(phb->opal_id, pe_no, 62949dec922SGavin Shan &state, &pcierr, NULL); 63049dec922SGavin Shan if (rc != OPAL_SUCCESS) { 63149dec922SGavin Shan pr_warn("%s: Failure %lld getting " 63249dec922SGavin Shan "PHB#%x-PE#%x state\n", 63349dec922SGavin Shan __func__, rc, 63449dec922SGavin Shan phb->hose->global_number, pe_no); 63549dec922SGavin Shan return OPAL_EEH_STOPPED_TEMP_UNAVAIL; 63649dec922SGavin Shan } 63749dec922SGavin Shan 63849dec922SGavin Shan /* Check the slave PE */ 63949dec922SGavin Shan if (!(pe->flags & PNV_IODA_PE_MASTER)) 64049dec922SGavin Shan return state; 64149dec922SGavin Shan 64249dec922SGavin Shan list_for_each_entry(slave, &pe->slaves, list) { 64349dec922SGavin Shan rc = opal_pci_eeh_freeze_status(phb->opal_id, 64449dec922SGavin Shan slave->pe_number, 64549dec922SGavin Shan &fstate, 64649dec922SGavin Shan &pcierr, 64749dec922SGavin Shan NULL); 64849dec922SGavin Shan if (rc != OPAL_SUCCESS) { 64949dec922SGavin Shan pr_warn("%s: Failure %lld getting " 65049dec922SGavin Shan "PHB#%x-PE#%x state\n", 65149dec922SGavin Shan __func__, rc, 65249dec922SGavin Shan phb->hose->global_number, slave->pe_number); 65349dec922SGavin Shan return OPAL_EEH_STOPPED_TEMP_UNAVAIL; 65449dec922SGavin Shan } 65549dec922SGavin Shan 65649dec922SGavin Shan /* 65749dec922SGavin Shan * Override the result based on the ascending 65849dec922SGavin Shan * priority. 65949dec922SGavin Shan */ 66049dec922SGavin Shan if (fstate > state) 66149dec922SGavin Shan state = fstate; 66249dec922SGavin Shan } 66349dec922SGavin Shan 66449dec922SGavin Shan return state; 66549dec922SGavin Shan } 66649dec922SGavin Shan 667f456834aSIan Munsie struct pnv_ioda_pe *pnv_ioda_get_pe(struct pci_dev *dev) 668184cd4a3SBenjamin Herrenschmidt { 669184cd4a3SBenjamin Herrenschmidt struct pci_controller *hose = pci_bus_to_host(dev->bus); 670184cd4a3SBenjamin Herrenschmidt struct pnv_phb *phb = hose->private_data; 671b72c1f65SBenjamin Herrenschmidt struct pci_dn *pdn = pci_get_pdn(dev); 672184cd4a3SBenjamin Herrenschmidt 673184cd4a3SBenjamin Herrenschmidt if (!pdn) 674184cd4a3SBenjamin Herrenschmidt return NULL; 675184cd4a3SBenjamin Herrenschmidt if (pdn->pe_number == IODA_INVALID_PE) 676184cd4a3SBenjamin Herrenschmidt return NULL; 677184cd4a3SBenjamin Herrenschmidt return &phb->ioda.pe_array[pdn->pe_number]; 678184cd4a3SBenjamin Herrenschmidt } 679184cd4a3SBenjamin Herrenschmidt 680b131a842SGavin Shan static int pnv_ioda_set_one_peltv(struct pnv_phb *phb, 681b131a842SGavin Shan struct pnv_ioda_pe *parent, 682b131a842SGavin Shan struct pnv_ioda_pe *child, 683b131a842SGavin Shan bool is_add) 684b131a842SGavin Shan { 685b131a842SGavin Shan const char *desc = is_add ? "adding" : "removing"; 686b131a842SGavin Shan uint8_t op = is_add ? OPAL_ADD_PE_TO_DOMAIN : 687b131a842SGavin Shan OPAL_REMOVE_PE_FROM_DOMAIN; 688b131a842SGavin Shan struct pnv_ioda_pe *slave; 689b131a842SGavin Shan long rc; 690b131a842SGavin Shan 691b131a842SGavin Shan /* Parent PE affects child PE */ 692b131a842SGavin Shan rc = opal_pci_set_peltv(phb->opal_id, parent->pe_number, 693b131a842SGavin Shan child->pe_number, op); 694b131a842SGavin Shan if (rc != OPAL_SUCCESS) { 695b131a842SGavin Shan pe_warn(child, "OPAL error %ld %s to parent PELTV\n", 696b131a842SGavin Shan rc, desc); 697b131a842SGavin Shan return -ENXIO; 698b131a842SGavin Shan } 699b131a842SGavin Shan 700b131a842SGavin Shan if (!(child->flags & PNV_IODA_PE_MASTER)) 701b131a842SGavin Shan return 0; 702b131a842SGavin Shan 703b131a842SGavin Shan /* Compound case: parent PE affects slave PEs */ 704b131a842SGavin Shan list_for_each_entry(slave, &child->slaves, list) { 705b131a842SGavin Shan rc = opal_pci_set_peltv(phb->opal_id, parent->pe_number, 706b131a842SGavin Shan slave->pe_number, op); 707b131a842SGavin Shan if (rc != OPAL_SUCCESS) { 708b131a842SGavin Shan pe_warn(slave, "OPAL error %ld %s to parent PELTV\n", 709b131a842SGavin Shan rc, desc); 710b131a842SGavin Shan return -ENXIO; 711b131a842SGavin Shan } 712b131a842SGavin Shan } 713b131a842SGavin Shan 714b131a842SGavin Shan return 0; 715b131a842SGavin Shan } 716b131a842SGavin Shan 717b131a842SGavin Shan static int pnv_ioda_set_peltv(struct pnv_phb *phb, 718b131a842SGavin Shan struct pnv_ioda_pe *pe, 719b131a842SGavin Shan bool is_add) 720b131a842SGavin Shan { 721b131a842SGavin Shan struct pnv_ioda_pe *slave; 722781a868fSWei Yang struct pci_dev *pdev = NULL; 723b131a842SGavin Shan int ret; 724b131a842SGavin Shan 725b131a842SGavin Shan /* 726b131a842SGavin Shan * Clear PE frozen state. If it's master PE, we need 727b131a842SGavin Shan * clear slave PE frozen state as well. 728b131a842SGavin Shan */ 729b131a842SGavin Shan if (is_add) { 730b131a842SGavin Shan opal_pci_eeh_freeze_clear(phb->opal_id, pe->pe_number, 731b131a842SGavin Shan OPAL_EEH_ACTION_CLEAR_FREEZE_ALL); 732b131a842SGavin Shan if (pe->flags & PNV_IODA_PE_MASTER) { 733b131a842SGavin Shan list_for_each_entry(slave, &pe->slaves, list) 734b131a842SGavin Shan opal_pci_eeh_freeze_clear(phb->opal_id, 735b131a842SGavin Shan slave->pe_number, 736b131a842SGavin Shan OPAL_EEH_ACTION_CLEAR_FREEZE_ALL); 737b131a842SGavin Shan } 738b131a842SGavin Shan } 739b131a842SGavin Shan 740b131a842SGavin Shan /* 741b131a842SGavin Shan * Associate PE in PELT. We need add the PE into the 742b131a842SGavin Shan * corresponding PELT-V as well. Otherwise, the error 743b131a842SGavin Shan * originated from the PE might contribute to other 744b131a842SGavin Shan * PEs. 745b131a842SGavin Shan */ 746b131a842SGavin Shan ret = pnv_ioda_set_one_peltv(phb, pe, pe, is_add); 747b131a842SGavin Shan if (ret) 748b131a842SGavin Shan return ret; 749b131a842SGavin Shan 750b131a842SGavin Shan /* For compound PEs, any one affects all of them */ 751b131a842SGavin Shan if (pe->flags & PNV_IODA_PE_MASTER) { 752b131a842SGavin Shan list_for_each_entry(slave, &pe->slaves, list) { 753b131a842SGavin Shan ret = pnv_ioda_set_one_peltv(phb, slave, pe, is_add); 754b131a842SGavin Shan if (ret) 755b131a842SGavin Shan return ret; 756b131a842SGavin Shan } 757b131a842SGavin Shan } 758b131a842SGavin Shan 759b131a842SGavin Shan if (pe->flags & (PNV_IODA_PE_BUS_ALL | PNV_IODA_PE_BUS)) 760b131a842SGavin Shan pdev = pe->pbus->self; 761781a868fSWei Yang else if (pe->flags & PNV_IODA_PE_DEV) 762b131a842SGavin Shan pdev = pe->pdev->bus->self; 763781a868fSWei Yang #ifdef CONFIG_PCI_IOV 764781a868fSWei Yang else if (pe->flags & PNV_IODA_PE_VF) 765283e2d8aSGavin Shan pdev = pe->parent_dev; 766781a868fSWei Yang #endif /* CONFIG_PCI_IOV */ 767b131a842SGavin Shan while (pdev) { 768b131a842SGavin Shan struct pci_dn *pdn = pci_get_pdn(pdev); 769b131a842SGavin Shan struct pnv_ioda_pe *parent; 770b131a842SGavin Shan 771b131a842SGavin Shan if (pdn && pdn->pe_number != IODA_INVALID_PE) { 772b131a842SGavin Shan parent = &phb->ioda.pe_array[pdn->pe_number]; 773b131a842SGavin Shan ret = pnv_ioda_set_one_peltv(phb, parent, pe, is_add); 774b131a842SGavin Shan if (ret) 775b131a842SGavin Shan return ret; 776b131a842SGavin Shan } 777b131a842SGavin Shan 778b131a842SGavin Shan pdev = pdev->bus->self; 779b131a842SGavin Shan } 780b131a842SGavin Shan 781b131a842SGavin Shan return 0; 782b131a842SGavin Shan } 783b131a842SGavin Shan 784781a868fSWei Yang static int pnv_ioda_deconfigure_pe(struct pnv_phb *phb, struct pnv_ioda_pe *pe) 785781a868fSWei Yang { 786781a868fSWei Yang struct pci_dev *parent; 787781a868fSWei Yang uint8_t bcomp, dcomp, fcomp; 788781a868fSWei Yang int64_t rc; 789781a868fSWei Yang long rid_end, rid; 790781a868fSWei Yang 791781a868fSWei Yang /* Currently, we just deconfigure VF PE. Bus PE will always there.*/ 792781a868fSWei Yang if (pe->pbus) { 793781a868fSWei Yang int count; 794781a868fSWei Yang 795781a868fSWei Yang dcomp = OPAL_IGNORE_RID_DEVICE_NUMBER; 796781a868fSWei Yang fcomp = OPAL_IGNORE_RID_FUNCTION_NUMBER; 797781a868fSWei Yang parent = pe->pbus->self; 798781a868fSWei Yang if (pe->flags & PNV_IODA_PE_BUS_ALL) 799781a868fSWei Yang count = pe->pbus->busn_res.end - pe->pbus->busn_res.start + 1; 800781a868fSWei Yang else 801781a868fSWei Yang count = 1; 802781a868fSWei Yang 803781a868fSWei Yang switch(count) { 804781a868fSWei Yang case 1: bcomp = OpalPciBusAll; break; 805781a868fSWei Yang case 2: bcomp = OpalPciBus7Bits; break; 806781a868fSWei Yang case 4: bcomp = OpalPciBus6Bits; break; 807781a868fSWei Yang case 8: bcomp = OpalPciBus5Bits; break; 808781a868fSWei Yang case 16: bcomp = OpalPciBus4Bits; break; 809781a868fSWei Yang case 32: bcomp = OpalPciBus3Bits; break; 810781a868fSWei Yang default: 811781a868fSWei Yang dev_err(&pe->pbus->dev, "Number of subordinate buses %d unsupported\n", 812781a868fSWei Yang count); 813781a868fSWei Yang /* Do an exact match only */ 814781a868fSWei Yang bcomp = OpalPciBusAll; 815781a868fSWei Yang } 816781a868fSWei Yang rid_end = pe->rid + (count << 8); 817781a868fSWei Yang } else { 81893e01a50SGavin Shan #ifdef CONFIG_PCI_IOV 819781a868fSWei Yang if (pe->flags & PNV_IODA_PE_VF) 820781a868fSWei Yang parent = pe->parent_dev; 821781a868fSWei Yang else 82293e01a50SGavin Shan #endif 823781a868fSWei Yang parent = pe->pdev->bus->self; 824781a868fSWei Yang bcomp = OpalPciBusAll; 825781a868fSWei Yang dcomp = OPAL_COMPARE_RID_DEVICE_NUMBER; 826781a868fSWei Yang fcomp = OPAL_COMPARE_RID_FUNCTION_NUMBER; 827781a868fSWei Yang rid_end = pe->rid + 1; 828781a868fSWei Yang } 829781a868fSWei Yang 830781a868fSWei Yang /* Clear the reverse map */ 831781a868fSWei Yang for (rid = pe->rid; rid < rid_end; rid++) 832c127562aSGavin Shan phb->ioda.pe_rmap[rid] = IODA_INVALID_PE; 833781a868fSWei Yang 834781a868fSWei Yang /* Release from all parents PELT-V */ 835781a868fSWei Yang while (parent) { 836781a868fSWei Yang struct pci_dn *pdn = pci_get_pdn(parent); 837781a868fSWei Yang if (pdn && pdn->pe_number != IODA_INVALID_PE) { 838781a868fSWei Yang rc = opal_pci_set_peltv(phb->opal_id, pdn->pe_number, 839781a868fSWei Yang pe->pe_number, OPAL_REMOVE_PE_FROM_DOMAIN); 840781a868fSWei Yang /* XXX What to do in case of error ? */ 841781a868fSWei Yang } 842781a868fSWei Yang parent = parent->bus->self; 843781a868fSWei Yang } 844781a868fSWei Yang 845f951e510SGavin Shan opal_pci_eeh_freeze_clear(phb->opal_id, pe->pe_number, 846781a868fSWei Yang OPAL_EEH_ACTION_CLEAR_FREEZE_ALL); 847781a868fSWei Yang 848781a868fSWei Yang /* Disassociate PE in PELT */ 849781a868fSWei Yang rc = opal_pci_set_peltv(phb->opal_id, pe->pe_number, 850781a868fSWei Yang pe->pe_number, OPAL_REMOVE_PE_FROM_DOMAIN); 851781a868fSWei Yang if (rc) 8521e496391SJoe Perches pe_warn(pe, "OPAL error %lld remove self from PELTV\n", rc); 853781a868fSWei Yang rc = opal_pci_set_pe(phb->opal_id, pe->pe_number, pe->rid, 854781a868fSWei Yang bcomp, dcomp, fcomp, OPAL_UNMAP_PE); 855781a868fSWei Yang if (rc) 8561e496391SJoe Perches pe_err(pe, "OPAL error %lld trying to setup PELT table\n", rc); 857781a868fSWei Yang 858781a868fSWei Yang pe->pbus = NULL; 859781a868fSWei Yang pe->pdev = NULL; 86093e01a50SGavin Shan #ifdef CONFIG_PCI_IOV 861781a868fSWei Yang pe->parent_dev = NULL; 86293e01a50SGavin Shan #endif 863781a868fSWei Yang 864781a868fSWei Yang return 0; 865781a868fSWei Yang } 866781a868fSWei Yang 867cad5cef6SGreg Kroah-Hartman static int pnv_ioda_configure_pe(struct pnv_phb *phb, struct pnv_ioda_pe *pe) 868184cd4a3SBenjamin Herrenschmidt { 869184cd4a3SBenjamin Herrenschmidt struct pci_dev *parent; 870184cd4a3SBenjamin Herrenschmidt uint8_t bcomp, dcomp, fcomp; 871184cd4a3SBenjamin Herrenschmidt long rc, rid_end, rid; 872184cd4a3SBenjamin Herrenschmidt 873184cd4a3SBenjamin Herrenschmidt /* Bus validation ? */ 874184cd4a3SBenjamin Herrenschmidt if (pe->pbus) { 875184cd4a3SBenjamin Herrenschmidt int count; 876184cd4a3SBenjamin Herrenschmidt 877184cd4a3SBenjamin Herrenschmidt dcomp = OPAL_IGNORE_RID_DEVICE_NUMBER; 878184cd4a3SBenjamin Herrenschmidt fcomp = OPAL_IGNORE_RID_FUNCTION_NUMBER; 879184cd4a3SBenjamin Herrenschmidt parent = pe->pbus->self; 880fb446ad0SGavin Shan if (pe->flags & PNV_IODA_PE_BUS_ALL) 881b918c62eSYinghai Lu count = pe->pbus->busn_res.end - pe->pbus->busn_res.start + 1; 882fb446ad0SGavin Shan else 883fb446ad0SGavin Shan count = 1; 884fb446ad0SGavin Shan 885184cd4a3SBenjamin Herrenschmidt switch(count) { 886184cd4a3SBenjamin Herrenschmidt case 1: bcomp = OpalPciBusAll; break; 887184cd4a3SBenjamin Herrenschmidt case 2: bcomp = OpalPciBus7Bits; break; 888184cd4a3SBenjamin Herrenschmidt case 4: bcomp = OpalPciBus6Bits; break; 889184cd4a3SBenjamin Herrenschmidt case 8: bcomp = OpalPciBus5Bits; break; 890184cd4a3SBenjamin Herrenschmidt case 16: bcomp = OpalPciBus4Bits; break; 891184cd4a3SBenjamin Herrenschmidt case 32: bcomp = OpalPciBus3Bits; break; 892184cd4a3SBenjamin Herrenschmidt default: 893781a868fSWei Yang dev_err(&pe->pbus->dev, "Number of subordinate buses %d unsupported\n", 894781a868fSWei Yang count); 895184cd4a3SBenjamin Herrenschmidt /* Do an exact match only */ 896184cd4a3SBenjamin Herrenschmidt bcomp = OpalPciBusAll; 897184cd4a3SBenjamin Herrenschmidt } 898184cd4a3SBenjamin Herrenschmidt rid_end = pe->rid + (count << 8); 899184cd4a3SBenjamin Herrenschmidt } else { 900781a868fSWei Yang #ifdef CONFIG_PCI_IOV 901781a868fSWei Yang if (pe->flags & PNV_IODA_PE_VF) 902781a868fSWei Yang parent = pe->parent_dev; 903781a868fSWei Yang else 904781a868fSWei Yang #endif /* CONFIG_PCI_IOV */ 905184cd4a3SBenjamin Herrenschmidt parent = pe->pdev->bus->self; 906184cd4a3SBenjamin Herrenschmidt bcomp = OpalPciBusAll; 907184cd4a3SBenjamin Herrenschmidt dcomp = OPAL_COMPARE_RID_DEVICE_NUMBER; 908184cd4a3SBenjamin Herrenschmidt fcomp = OPAL_COMPARE_RID_FUNCTION_NUMBER; 909184cd4a3SBenjamin Herrenschmidt rid_end = pe->rid + 1; 910184cd4a3SBenjamin Herrenschmidt } 911184cd4a3SBenjamin Herrenschmidt 912631ad691SGavin Shan /* 913631ad691SGavin Shan * Associate PE in PELT. We need add the PE into the 914631ad691SGavin Shan * corresponding PELT-V as well. Otherwise, the error 915631ad691SGavin Shan * originated from the PE might contribute to other 916631ad691SGavin Shan * PEs. 917631ad691SGavin Shan */ 918184cd4a3SBenjamin Herrenschmidt rc = opal_pci_set_pe(phb->opal_id, pe->pe_number, pe->rid, 919184cd4a3SBenjamin Herrenschmidt bcomp, dcomp, fcomp, OPAL_MAP_PE); 920184cd4a3SBenjamin Herrenschmidt if (rc) { 921184cd4a3SBenjamin Herrenschmidt pe_err(pe, "OPAL error %ld trying to setup PELT table\n", rc); 922184cd4a3SBenjamin Herrenschmidt return -ENXIO; 923184cd4a3SBenjamin Herrenschmidt } 924631ad691SGavin Shan 9255d2aa710SAlistair Popple /* 9265d2aa710SAlistair Popple * Configure PELTV. NPUs don't have a PELTV table so skip 9275d2aa710SAlistair Popple * configuration on them. 9285d2aa710SAlistair Popple */ 9297f2c39e9SFrederic Barrat if (phb->type != PNV_PHB_NPU_NVLINK && phb->type != PNV_PHB_NPU_OCAPI) 930b131a842SGavin Shan pnv_ioda_set_peltv(phb, pe, true); 931184cd4a3SBenjamin Herrenschmidt 932184cd4a3SBenjamin Herrenschmidt /* Setup reverse map */ 933184cd4a3SBenjamin Herrenschmidt for (rid = pe->rid; rid < rid_end; rid++) 934184cd4a3SBenjamin Herrenschmidt phb->ioda.pe_rmap[rid] = pe->pe_number; 935184cd4a3SBenjamin Herrenschmidt 936184cd4a3SBenjamin Herrenschmidt /* Setup one MVTs on IODA1 */ 9374773f76bSGavin Shan if (phb->type != PNV_PHB_IODA1) { 9384773f76bSGavin Shan pe->mve_number = 0; 9394773f76bSGavin Shan goto out; 9404773f76bSGavin Shan } 9414773f76bSGavin Shan 942184cd4a3SBenjamin Herrenschmidt pe->mve_number = pe->pe_number; 9434773f76bSGavin Shan rc = opal_pci_set_mve(phb->opal_id, pe->mve_number, pe->pe_number); 9444773f76bSGavin Shan if (rc != OPAL_SUCCESS) { 9451f52f176SRussell Currey pe_err(pe, "OPAL error %ld setting up MVE %x\n", 946184cd4a3SBenjamin Herrenschmidt rc, pe->mve_number); 947184cd4a3SBenjamin Herrenschmidt pe->mve_number = -1; 948184cd4a3SBenjamin Herrenschmidt } else { 949184cd4a3SBenjamin Herrenschmidt rc = opal_pci_set_mve_enable(phb->opal_id, 950cee72d5bSBenjamin Herrenschmidt pe->mve_number, OPAL_ENABLE_MVE); 951184cd4a3SBenjamin Herrenschmidt if (rc) { 9521f52f176SRussell Currey pe_err(pe, "OPAL error %ld enabling MVE %x\n", 953184cd4a3SBenjamin Herrenschmidt rc, pe->mve_number); 954184cd4a3SBenjamin Herrenschmidt pe->mve_number = -1; 955184cd4a3SBenjamin Herrenschmidt } 956184cd4a3SBenjamin Herrenschmidt } 957184cd4a3SBenjamin Herrenschmidt 9584773f76bSGavin Shan out: 959184cd4a3SBenjamin Herrenschmidt return 0; 960184cd4a3SBenjamin Herrenschmidt } 961184cd4a3SBenjamin Herrenschmidt 962781a868fSWei Yang #ifdef CONFIG_PCI_IOV 963781a868fSWei Yang static int pnv_pci_vf_resource_shift(struct pci_dev *dev, int offset) 964781a868fSWei Yang { 965781a868fSWei Yang struct pci_dn *pdn = pci_get_pdn(dev); 966781a868fSWei Yang int i; 967781a868fSWei Yang struct resource *res, res2; 968781a868fSWei Yang resource_size_t size; 969781a868fSWei Yang u16 num_vfs; 970781a868fSWei Yang 971781a868fSWei Yang if (!dev->is_physfn) 972781a868fSWei Yang return -EINVAL; 973781a868fSWei Yang 974781a868fSWei Yang /* 975781a868fSWei Yang * "offset" is in VFs. The M64 windows are sized so that when they 976781a868fSWei Yang * are segmented, each segment is the same size as the IOV BAR. 977781a868fSWei Yang * Each segment is in a separate PE, and the high order bits of the 978781a868fSWei Yang * address are the PE number. Therefore, each VF's BAR is in a 979781a868fSWei Yang * separate PE, and changing the IOV BAR start address changes the 980781a868fSWei Yang * range of PEs the VFs are in. 981781a868fSWei Yang */ 982781a868fSWei Yang num_vfs = pdn->num_vfs; 983781a868fSWei Yang for (i = 0; i < PCI_SRIOV_NUM_BARS; i++) { 984781a868fSWei Yang res = &dev->resource[i + PCI_IOV_RESOURCES]; 985781a868fSWei Yang if (!res->flags || !res->parent) 986781a868fSWei Yang continue; 987781a868fSWei Yang 988781a868fSWei Yang /* 989781a868fSWei Yang * The actual IOV BAR range is determined by the start address 990781a868fSWei Yang * and the actual size for num_vfs VFs BAR. This check is to 991781a868fSWei Yang * make sure that after shifting, the range will not overlap 992781a868fSWei Yang * with another device. 993781a868fSWei Yang */ 994781a868fSWei Yang size = pci_iov_resource_size(dev, i + PCI_IOV_RESOURCES); 995781a868fSWei Yang res2.flags = res->flags; 996781a868fSWei Yang res2.start = res->start + (size * offset); 997781a868fSWei Yang res2.end = res2.start + (size * num_vfs) - 1; 998781a868fSWei Yang 999781a868fSWei Yang if (res2.end > res->end) { 1000781a868fSWei Yang dev_err(&dev->dev, "VF BAR%d: %pR would extend past %pR (trying to enable %d VFs shifted by %d)\n", 1001781a868fSWei Yang i, &res2, res, num_vfs, offset); 1002781a868fSWei Yang return -EBUSY; 1003781a868fSWei Yang } 1004781a868fSWei Yang } 1005781a868fSWei Yang 1006781a868fSWei Yang /* 1007d6f934fdSAlexey Kardashevskiy * Since M64 BAR shares segments among all possible 256 PEs, 1008d6f934fdSAlexey Kardashevskiy * we have to shift the beginning of PF IOV BAR to make it start from 1009d6f934fdSAlexey Kardashevskiy * the segment which belongs to the PE number assigned to the first VF. 1010d6f934fdSAlexey Kardashevskiy * This creates a "hole" in the /proc/iomem which could be used for 1011d6f934fdSAlexey Kardashevskiy * allocating other resources so we reserve this area below and 1012d6f934fdSAlexey Kardashevskiy * release when IOV is released. 1013781a868fSWei Yang */ 1014781a868fSWei Yang for (i = 0; i < PCI_SRIOV_NUM_BARS; i++) { 1015781a868fSWei Yang res = &dev->resource[i + PCI_IOV_RESOURCES]; 1016781a868fSWei Yang if (!res->flags || !res->parent) 1017781a868fSWei Yang continue; 1018781a868fSWei Yang 1019781a868fSWei Yang size = pci_iov_resource_size(dev, i + PCI_IOV_RESOURCES); 1020781a868fSWei Yang res2 = *res; 1021781a868fSWei Yang res->start += size * offset; 1022781a868fSWei Yang 102374703cc4SWei Yang dev_info(&dev->dev, "VF BAR%d: %pR shifted to %pR (%sabling %d VFs shifted by %d)\n", 102474703cc4SWei Yang i, &res2, res, (offset > 0) ? "En" : "Dis", 102574703cc4SWei Yang num_vfs, offset); 1026d6f934fdSAlexey Kardashevskiy 1027d6f934fdSAlexey Kardashevskiy if (offset < 0) { 1028d6f934fdSAlexey Kardashevskiy devm_release_resource(&dev->dev, &pdn->holes[i]); 1029d6f934fdSAlexey Kardashevskiy memset(&pdn->holes[i], 0, sizeof(pdn->holes[i])); 1030d6f934fdSAlexey Kardashevskiy } 1031d6f934fdSAlexey Kardashevskiy 1032781a868fSWei Yang pci_update_resource(dev, i + PCI_IOV_RESOURCES); 1033d6f934fdSAlexey Kardashevskiy 1034d6f934fdSAlexey Kardashevskiy if (offset > 0) { 1035d6f934fdSAlexey Kardashevskiy pdn->holes[i].start = res2.start; 1036d6f934fdSAlexey Kardashevskiy pdn->holes[i].end = res2.start + size * offset - 1; 1037d6f934fdSAlexey Kardashevskiy pdn->holes[i].flags = IORESOURCE_BUS; 1038d6f934fdSAlexey Kardashevskiy pdn->holes[i].name = "pnv_iov_reserved"; 1039d6f934fdSAlexey Kardashevskiy devm_request_resource(&dev->dev, res->parent, 1040d6f934fdSAlexey Kardashevskiy &pdn->holes[i]); 1041d6f934fdSAlexey Kardashevskiy } 1042781a868fSWei Yang } 1043781a868fSWei Yang return 0; 1044781a868fSWei Yang } 1045781a868fSWei Yang #endif /* CONFIG_PCI_IOV */ 1046781a868fSWei Yang 1047cad5cef6SGreg Kroah-Hartman static struct pnv_ioda_pe *pnv_ioda_setup_dev_PE(struct pci_dev *dev) 1048184cd4a3SBenjamin Herrenschmidt { 1049184cd4a3SBenjamin Herrenschmidt struct pci_controller *hose = pci_bus_to_host(dev->bus); 1050184cd4a3SBenjamin Herrenschmidt struct pnv_phb *phb = hose->private_data; 1051b72c1f65SBenjamin Herrenschmidt struct pci_dn *pdn = pci_get_pdn(dev); 1052184cd4a3SBenjamin Herrenschmidt struct pnv_ioda_pe *pe; 1053184cd4a3SBenjamin Herrenschmidt 1054184cd4a3SBenjamin Herrenschmidt if (!pdn) { 1055184cd4a3SBenjamin Herrenschmidt pr_err("%s: Device tree node not associated properly\n", 1056184cd4a3SBenjamin Herrenschmidt pci_name(dev)); 1057184cd4a3SBenjamin Herrenschmidt return NULL; 1058184cd4a3SBenjamin Herrenschmidt } 1059184cd4a3SBenjamin Herrenschmidt if (pdn->pe_number != IODA_INVALID_PE) 1060184cd4a3SBenjamin Herrenschmidt return NULL; 1061184cd4a3SBenjamin Herrenschmidt 10621e916772SGavin Shan pe = pnv_ioda_alloc_pe(phb); 10631e916772SGavin Shan if (!pe) { 1064f2c2cbccSJoe Perches pr_warn("%s: Not enough PE# available, disabling device\n", 1065184cd4a3SBenjamin Herrenschmidt pci_name(dev)); 1066184cd4a3SBenjamin Herrenschmidt return NULL; 1067184cd4a3SBenjamin Herrenschmidt } 1068184cd4a3SBenjamin Herrenschmidt 1069184cd4a3SBenjamin Herrenschmidt /* NOTE: We get only one ref to the pci_dev for the pdn, not for the 1070184cd4a3SBenjamin Herrenschmidt * pointer in the PE data structure, both should be destroyed at the 1071184cd4a3SBenjamin Herrenschmidt * same time. However, this needs to be looked at more closely again 1072184cd4a3SBenjamin Herrenschmidt * once we actually start removing things (Hotplug, SR-IOV, ...) 1073184cd4a3SBenjamin Herrenschmidt * 1074184cd4a3SBenjamin Herrenschmidt * At some point we want to remove the PDN completely anyways 1075184cd4a3SBenjamin Herrenschmidt */ 1076184cd4a3SBenjamin Herrenschmidt pci_dev_get(dev); 10771e916772SGavin Shan pdn->pe_number = pe->pe_number; 10785d2aa710SAlistair Popple pe->flags = PNV_IODA_PE_DEV; 1079184cd4a3SBenjamin Herrenschmidt pe->pdev = dev; 1080184cd4a3SBenjamin Herrenschmidt pe->pbus = NULL; 1081184cd4a3SBenjamin Herrenschmidt pe->mve_number = -1; 1082184cd4a3SBenjamin Herrenschmidt pe->rid = dev->bus->number << 8 | pdn->devfn; 1083184cd4a3SBenjamin Herrenschmidt 1084184cd4a3SBenjamin Herrenschmidt pe_info(pe, "Associated device to PE\n"); 1085184cd4a3SBenjamin Herrenschmidt 1086184cd4a3SBenjamin Herrenschmidt if (pnv_ioda_configure_pe(phb, pe)) { 1087184cd4a3SBenjamin Herrenschmidt /* XXX What do we do here ? */ 10881e916772SGavin Shan pnv_ioda_free_pe(pe); 1089184cd4a3SBenjamin Herrenschmidt pdn->pe_number = IODA_INVALID_PE; 1090184cd4a3SBenjamin Herrenschmidt pe->pdev = NULL; 1091184cd4a3SBenjamin Herrenschmidt pci_dev_put(dev); 1092184cd4a3SBenjamin Herrenschmidt return NULL; 1093184cd4a3SBenjamin Herrenschmidt } 1094184cd4a3SBenjamin Herrenschmidt 10951d4e89cfSAlexey Kardashevskiy /* Put PE to the list */ 10961d4e89cfSAlexey Kardashevskiy list_add_tail(&pe->list, &phb->ioda.pe_list); 10971d4e89cfSAlexey Kardashevskiy 1098184cd4a3SBenjamin Herrenschmidt return pe; 1099184cd4a3SBenjamin Herrenschmidt } 1100184cd4a3SBenjamin Herrenschmidt 1101184cd4a3SBenjamin Herrenschmidt static void pnv_ioda_setup_same_PE(struct pci_bus *bus, struct pnv_ioda_pe *pe) 1102184cd4a3SBenjamin Herrenschmidt { 1103184cd4a3SBenjamin Herrenschmidt struct pci_dev *dev; 1104184cd4a3SBenjamin Herrenschmidt 1105184cd4a3SBenjamin Herrenschmidt list_for_each_entry(dev, &bus->devices, bus_list) { 1106b72c1f65SBenjamin Herrenschmidt struct pci_dn *pdn = pci_get_pdn(dev); 1107184cd4a3SBenjamin Herrenschmidt 1108184cd4a3SBenjamin Herrenschmidt if (pdn == NULL) { 1109184cd4a3SBenjamin Herrenschmidt pr_warn("%s: No device node associated with device !\n", 1110184cd4a3SBenjamin Herrenschmidt pci_name(dev)); 1111184cd4a3SBenjamin Herrenschmidt continue; 1112184cd4a3SBenjamin Herrenschmidt } 1113ccd1c191SGavin Shan 1114ccd1c191SGavin Shan /* 1115ccd1c191SGavin Shan * In partial hotplug case, the PCI device might be still 1116ccd1c191SGavin Shan * associated with the PE and needn't attach it to the PE 1117ccd1c191SGavin Shan * again. 1118ccd1c191SGavin Shan */ 1119ccd1c191SGavin Shan if (pdn->pe_number != IODA_INVALID_PE) 1120ccd1c191SGavin Shan continue; 1121ccd1c191SGavin Shan 1122c5f7700bSGavin Shan pe->device_count++; 1123184cd4a3SBenjamin Herrenschmidt pdn->pe_number = pe->pe_number; 1124fb446ad0SGavin Shan if ((pe->flags & PNV_IODA_PE_BUS_ALL) && dev->subordinate) 1125184cd4a3SBenjamin Herrenschmidt pnv_ioda_setup_same_PE(dev->subordinate, pe); 1126184cd4a3SBenjamin Herrenschmidt } 1127184cd4a3SBenjamin Herrenschmidt } 1128184cd4a3SBenjamin Herrenschmidt 1129fb446ad0SGavin Shan /* 1130fb446ad0SGavin Shan * There're 2 types of PCI bus sensitive PEs: One that is compromised of 1131fb446ad0SGavin Shan * single PCI bus. Another one that contains the primary PCI bus and its 1132fb446ad0SGavin Shan * subordinate PCI devices and buses. The second type of PE is normally 1133fb446ad0SGavin Shan * orgiriated by PCIe-to-PCI bridge or PLX switch downstream ports. 1134fb446ad0SGavin Shan */ 11351e916772SGavin Shan static struct pnv_ioda_pe *pnv_ioda_setup_bus_PE(struct pci_bus *bus, bool all) 1136184cd4a3SBenjamin Herrenschmidt { 1137fb446ad0SGavin Shan struct pci_controller *hose = pci_bus_to_host(bus); 1138184cd4a3SBenjamin Herrenschmidt struct pnv_phb *phb = hose->private_data; 11391e916772SGavin Shan struct pnv_ioda_pe *pe = NULL; 1140ccd1c191SGavin Shan unsigned int pe_num; 1141ccd1c191SGavin Shan 1142ccd1c191SGavin Shan /* 1143ccd1c191SGavin Shan * In partial hotplug case, the PE instance might be still alive. 1144ccd1c191SGavin Shan * We should reuse it instead of allocating a new one. 1145ccd1c191SGavin Shan */ 1146ccd1c191SGavin Shan pe_num = phb->ioda.pe_rmap[bus->number << 8]; 1147ccd1c191SGavin Shan if (pe_num != IODA_INVALID_PE) { 1148ccd1c191SGavin Shan pe = &phb->ioda.pe_array[pe_num]; 1149ccd1c191SGavin Shan pnv_ioda_setup_same_PE(bus, pe); 1150ccd1c191SGavin Shan return NULL; 1151ccd1c191SGavin Shan } 1152184cd4a3SBenjamin Herrenschmidt 115363803c39SGavin Shan /* PE number for root bus should have been reserved */ 115463803c39SGavin Shan if (pci_is_root_bus(bus) && 115563803c39SGavin Shan phb->ioda.root_pe_idx != IODA_INVALID_PE) 115663803c39SGavin Shan pe = &phb->ioda.pe_array[phb->ioda.root_pe_idx]; 115763803c39SGavin Shan 1158262af557SGuo Chao /* Check if PE is determined by M64 */ 1159a25de7afSAlexey Kardashevskiy if (!pe) 1160a25de7afSAlexey Kardashevskiy pe = pnv_ioda_pick_m64_pe(bus, all); 1161262af557SGuo Chao 1162262af557SGuo Chao /* The PE number isn't pinned by M64 */ 11631e916772SGavin Shan if (!pe) 11641e916772SGavin Shan pe = pnv_ioda_alloc_pe(phb); 1165262af557SGuo Chao 11661e916772SGavin Shan if (!pe) { 1167f2c2cbccSJoe Perches pr_warn("%s: Not enough PE# available for PCI bus %04x:%02x\n", 1168fb446ad0SGavin Shan __func__, pci_domain_nr(bus), bus->number); 11691e916772SGavin Shan return NULL; 1170184cd4a3SBenjamin Herrenschmidt } 1171184cd4a3SBenjamin Herrenschmidt 1172262af557SGuo Chao pe->flags |= (all ? PNV_IODA_PE_BUS_ALL : PNV_IODA_PE_BUS); 1173184cd4a3SBenjamin Herrenschmidt pe->pbus = bus; 1174184cd4a3SBenjamin Herrenschmidt pe->pdev = NULL; 1175184cd4a3SBenjamin Herrenschmidt pe->mve_number = -1; 1176b918c62eSYinghai Lu pe->rid = bus->busn_res.start << 8; 1177184cd4a3SBenjamin Herrenschmidt 1178fb446ad0SGavin Shan if (all) 11791e496391SJoe Perches pe_info(pe, "Secondary bus %pad..%pad associated with PE#%x\n", 11801e496391SJoe Perches &bus->busn_res.start, &bus->busn_res.end, 11811e496391SJoe Perches pe->pe_number); 1182fb446ad0SGavin Shan else 11831e496391SJoe Perches pe_info(pe, "Secondary bus %pad associated with PE#%x\n", 11841e496391SJoe Perches &bus->busn_res.start, pe->pe_number); 1185184cd4a3SBenjamin Herrenschmidt 1186184cd4a3SBenjamin Herrenschmidt if (pnv_ioda_configure_pe(phb, pe)) { 1187184cd4a3SBenjamin Herrenschmidt /* XXX What do we do here ? */ 11881e916772SGavin Shan pnv_ioda_free_pe(pe); 1189184cd4a3SBenjamin Herrenschmidt pe->pbus = NULL; 11901e916772SGavin Shan return NULL; 1191184cd4a3SBenjamin Herrenschmidt } 1192184cd4a3SBenjamin Herrenschmidt 1193184cd4a3SBenjamin Herrenschmidt /* Associate it with all child devices */ 1194184cd4a3SBenjamin Herrenschmidt pnv_ioda_setup_same_PE(bus, pe); 1195184cd4a3SBenjamin Herrenschmidt 11967ebdf956SGavin Shan /* Put PE to the list */ 11977ebdf956SGavin Shan list_add_tail(&pe->list, &phb->ioda.pe_list); 11981e916772SGavin Shan 11991e916772SGavin Shan return pe; 1200184cd4a3SBenjamin Herrenschmidt } 1201184cd4a3SBenjamin Herrenschmidt 1202b521549aSAlistair Popple static struct pnv_ioda_pe *pnv_ioda_setup_npu_PE(struct pci_dev *npu_pdev) 12035d2aa710SAlistair Popple { 1204b521549aSAlistair Popple int pe_num, found_pe = false, rc; 1205b521549aSAlistair Popple long rid; 1206b521549aSAlistair Popple struct pnv_ioda_pe *pe; 1207b521549aSAlistair Popple struct pci_dev *gpu_pdev; 1208b521549aSAlistair Popple struct pci_dn *npu_pdn; 1209b521549aSAlistair Popple struct pci_controller *hose = pci_bus_to_host(npu_pdev->bus); 1210b521549aSAlistair Popple struct pnv_phb *phb = hose->private_data; 1211b521549aSAlistair Popple 1212b521549aSAlistair Popple /* 1213b521549aSAlistair Popple * Due to a hardware errata PE#0 on the NPU is reserved for 1214b521549aSAlistair Popple * error handling. This means we only have three PEs remaining 1215b521549aSAlistair Popple * which need to be assigned to four links, implying some 1216b521549aSAlistair Popple * links must share PEs. 1217b521549aSAlistair Popple * 1218b521549aSAlistair Popple * To achieve this we assign PEs such that NPUs linking the 1219b521549aSAlistair Popple * same GPU get assigned the same PE. 1220b521549aSAlistair Popple */ 1221b521549aSAlistair Popple gpu_pdev = pnv_pci_get_gpu_dev(npu_pdev); 122292b8f137SGavin Shan for (pe_num = 0; pe_num < phb->ioda.total_pe_num; pe_num++) { 1223b521549aSAlistair Popple pe = &phb->ioda.pe_array[pe_num]; 1224b521549aSAlistair Popple if (!pe->pdev) 1225b521549aSAlistair Popple continue; 1226b521549aSAlistair Popple 1227b521549aSAlistair Popple if (pnv_pci_get_gpu_dev(pe->pdev) == gpu_pdev) { 1228b521549aSAlistair Popple /* 1229b521549aSAlistair Popple * This device has the same peer GPU so should 1230b521549aSAlistair Popple * be assigned the same PE as the existing 1231b521549aSAlistair Popple * peer NPU. 1232b521549aSAlistair Popple */ 1233b521549aSAlistair Popple dev_info(&npu_pdev->dev, 12341f52f176SRussell Currey "Associating to existing PE %x\n", pe_num); 1235b521549aSAlistair Popple pci_dev_get(npu_pdev); 1236b521549aSAlistair Popple npu_pdn = pci_get_pdn(npu_pdev); 1237b521549aSAlistair Popple rid = npu_pdev->bus->number << 8 | npu_pdn->devfn; 1238b521549aSAlistair Popple npu_pdn->pe_number = pe_num; 1239b521549aSAlistair Popple phb->ioda.pe_rmap[rid] = pe->pe_number; 1240b521549aSAlistair Popple 1241b521549aSAlistair Popple /* Map the PE to this link */ 1242b521549aSAlistair Popple rc = opal_pci_set_pe(phb->opal_id, pe_num, rid, 1243b521549aSAlistair Popple OpalPciBusAll, 1244b521549aSAlistair Popple OPAL_COMPARE_RID_DEVICE_NUMBER, 1245b521549aSAlistair Popple OPAL_COMPARE_RID_FUNCTION_NUMBER, 1246b521549aSAlistair Popple OPAL_MAP_PE); 1247b521549aSAlistair Popple WARN_ON(rc != OPAL_SUCCESS); 1248b521549aSAlistair Popple found_pe = true; 1249b521549aSAlistair Popple break; 1250b521549aSAlistair Popple } 1251b521549aSAlistair Popple } 1252b521549aSAlistair Popple 1253b521549aSAlistair Popple if (!found_pe) 1254b521549aSAlistair Popple /* 1255b521549aSAlistair Popple * Could not find an existing PE so allocate a new 1256b521549aSAlistair Popple * one. 1257b521549aSAlistair Popple */ 1258b521549aSAlistair Popple return pnv_ioda_setup_dev_PE(npu_pdev); 1259b521549aSAlistair Popple else 1260b521549aSAlistair Popple return pe; 1261b521549aSAlistair Popple } 1262b521549aSAlistair Popple 1263b521549aSAlistair Popple static void pnv_ioda_setup_npu_PEs(struct pci_bus *bus) 1264b521549aSAlistair Popple { 12655d2aa710SAlistair Popple struct pci_dev *pdev; 12665d2aa710SAlistair Popple 12675d2aa710SAlistair Popple list_for_each_entry(pdev, &bus->devices, bus_list) 1268b521549aSAlistair Popple pnv_ioda_setup_npu_PE(pdev); 12695d2aa710SAlistair Popple } 12705d2aa710SAlistair Popple 1271cad5cef6SGreg Kroah-Hartman static void pnv_pci_ioda_setup_PEs(void) 1272fb446ad0SGavin Shan { 12730e759bd7SAlexey Kardashevskiy struct pci_controller *hose; 1274262af557SGuo Chao struct pnv_phb *phb; 12757f2c39e9SFrederic Barrat struct pci_bus *bus; 12767f2c39e9SFrederic Barrat struct pci_dev *pdev; 12770e759bd7SAlexey Kardashevskiy struct pnv_ioda_pe *pe; 1278fb446ad0SGavin Shan 12790e759bd7SAlexey Kardashevskiy list_for_each_entry(hose, &hose_list, list_node) { 1280262af557SGuo Chao phb = hose->private_data; 12817f2c39e9SFrederic Barrat if (phb->type == PNV_PHB_NPU_NVLINK) { 128208f48f32SAlistair Popple /* PE#0 is needed for error reporting */ 128308f48f32SAlistair Popple pnv_ioda_reserve_pe(phb, 0); 1284b521549aSAlistair Popple pnv_ioda_setup_npu_PEs(hose->bus); 12851ab66d1fSAlistair Popple if (phb->model == PNV_PHB_MODEL_NPU2) 12860e759bd7SAlexey Kardashevskiy WARN_ON_ONCE(pnv_npu2_init(hose)); 1287ccd1c191SGavin Shan } 12887f2c39e9SFrederic Barrat if (phb->type == PNV_PHB_NPU_OCAPI) { 12897f2c39e9SFrederic Barrat bus = hose->bus; 12907f2c39e9SFrederic Barrat list_for_each_entry(pdev, &bus->devices, bus_list) 12917f2c39e9SFrederic Barrat pnv_ioda_setup_dev_PE(pdev); 12927f2c39e9SFrederic Barrat } 1293fb446ad0SGavin Shan } 12940e759bd7SAlexey Kardashevskiy list_for_each_entry(hose, &hose_list, list_node) { 12950e759bd7SAlexey Kardashevskiy phb = hose->private_data; 12960e759bd7SAlexey Kardashevskiy if (phb->type != PNV_PHB_IODA2) 12970e759bd7SAlexey Kardashevskiy continue; 12980e759bd7SAlexey Kardashevskiy 12990e759bd7SAlexey Kardashevskiy list_for_each_entry(pe, &phb->ioda.pe_list, list) 13000e759bd7SAlexey Kardashevskiy pnv_npu2_map_lpar(pe, MSR_DR | MSR_PR | MSR_HV); 13010e759bd7SAlexey Kardashevskiy } 1302fb446ad0SGavin Shan } 1303184cd4a3SBenjamin Herrenschmidt 1304a8b2f828SGavin Shan #ifdef CONFIG_PCI_IOV 1305ee8222feSWei Yang static int pnv_pci_vf_release_m64(struct pci_dev *pdev, u16 num_vfs) 1306781a868fSWei Yang { 1307781a868fSWei Yang struct pci_bus *bus; 1308781a868fSWei Yang struct pci_controller *hose; 1309781a868fSWei Yang struct pnv_phb *phb; 1310781a868fSWei Yang struct pci_dn *pdn; 131102639b0eSWei Yang int i, j; 1312ee8222feSWei Yang int m64_bars; 1313781a868fSWei Yang 1314781a868fSWei Yang bus = pdev->bus; 1315781a868fSWei Yang hose = pci_bus_to_host(bus); 1316781a868fSWei Yang phb = hose->private_data; 1317781a868fSWei Yang pdn = pci_get_pdn(pdev); 1318781a868fSWei Yang 1319ee8222feSWei Yang if (pdn->m64_single_mode) 1320ee8222feSWei Yang m64_bars = num_vfs; 1321ee8222feSWei Yang else 1322ee8222feSWei Yang m64_bars = 1; 1323ee8222feSWei Yang 132402639b0eSWei Yang for (i = 0; i < PCI_SRIOV_NUM_BARS; i++) 1325ee8222feSWei Yang for (j = 0; j < m64_bars; j++) { 1326ee8222feSWei Yang if (pdn->m64_map[j][i] == IODA_INVALID_M64) 1327781a868fSWei Yang continue; 1328781a868fSWei Yang opal_pci_phb_mmio_enable(phb->opal_id, 1329ee8222feSWei Yang OPAL_M64_WINDOW_TYPE, pdn->m64_map[j][i], 0); 1330ee8222feSWei Yang clear_bit(pdn->m64_map[j][i], &phb->ioda.m64_bar_alloc); 1331ee8222feSWei Yang pdn->m64_map[j][i] = IODA_INVALID_M64; 1332781a868fSWei Yang } 1333781a868fSWei Yang 1334ee8222feSWei Yang kfree(pdn->m64_map); 1335781a868fSWei Yang return 0; 1336781a868fSWei Yang } 1337781a868fSWei Yang 133802639b0eSWei Yang static int pnv_pci_vf_assign_m64(struct pci_dev *pdev, u16 num_vfs) 1339781a868fSWei Yang { 1340781a868fSWei Yang struct pci_bus *bus; 1341781a868fSWei Yang struct pci_controller *hose; 1342781a868fSWei Yang struct pnv_phb *phb; 1343781a868fSWei Yang struct pci_dn *pdn; 1344781a868fSWei Yang unsigned int win; 1345781a868fSWei Yang struct resource *res; 134602639b0eSWei Yang int i, j; 1347781a868fSWei Yang int64_t rc; 134802639b0eSWei Yang int total_vfs; 134902639b0eSWei Yang resource_size_t size, start; 135002639b0eSWei Yang int pe_num; 1351ee8222feSWei Yang int m64_bars; 1352781a868fSWei Yang 1353781a868fSWei Yang bus = pdev->bus; 1354781a868fSWei Yang hose = pci_bus_to_host(bus); 1355781a868fSWei Yang phb = hose->private_data; 1356781a868fSWei Yang pdn = pci_get_pdn(pdev); 135702639b0eSWei Yang total_vfs = pci_sriov_get_totalvfs(pdev); 1358781a868fSWei Yang 1359ee8222feSWei Yang if (pdn->m64_single_mode) 1360ee8222feSWei Yang m64_bars = num_vfs; 1361ee8222feSWei Yang else 1362ee8222feSWei Yang m64_bars = 1; 136302639b0eSWei Yang 1364fb37e128SMarkus Elfring pdn->m64_map = kmalloc_array(m64_bars, 1365fb37e128SMarkus Elfring sizeof(*pdn->m64_map), 1366fb37e128SMarkus Elfring GFP_KERNEL); 1367ee8222feSWei Yang if (!pdn->m64_map) 1368ee8222feSWei Yang return -ENOMEM; 1369ee8222feSWei Yang /* Initialize the m64_map to IODA_INVALID_M64 */ 1370ee8222feSWei Yang for (i = 0; i < m64_bars ; i++) 1371ee8222feSWei Yang for (j = 0; j < PCI_SRIOV_NUM_BARS; j++) 1372ee8222feSWei Yang pdn->m64_map[i][j] = IODA_INVALID_M64; 1373ee8222feSWei Yang 1374781a868fSWei Yang 1375781a868fSWei Yang for (i = 0; i < PCI_SRIOV_NUM_BARS; i++) { 1376781a868fSWei Yang res = &pdev->resource[i + PCI_IOV_RESOURCES]; 1377781a868fSWei Yang if (!res->flags || !res->parent) 1378781a868fSWei Yang continue; 1379781a868fSWei Yang 1380ee8222feSWei Yang for (j = 0; j < m64_bars; j++) { 1381781a868fSWei Yang do { 1382781a868fSWei Yang win = find_next_zero_bit(&phb->ioda.m64_bar_alloc, 1383781a868fSWei Yang phb->ioda.m64_bar_idx + 1, 0); 1384781a868fSWei Yang 1385781a868fSWei Yang if (win >= phb->ioda.m64_bar_idx + 1) 1386781a868fSWei Yang goto m64_failed; 1387781a868fSWei Yang } while (test_and_set_bit(win, &phb->ioda.m64_bar_alloc)); 1388781a868fSWei Yang 1389ee8222feSWei Yang pdn->m64_map[j][i] = win; 139002639b0eSWei Yang 1391ee8222feSWei Yang if (pdn->m64_single_mode) { 139202639b0eSWei Yang size = pci_iov_resource_size(pdev, 139302639b0eSWei Yang PCI_IOV_RESOURCES + i); 139402639b0eSWei Yang start = res->start + size * j; 139502639b0eSWei Yang } else { 139602639b0eSWei Yang size = resource_size(res); 139702639b0eSWei Yang start = res->start; 139802639b0eSWei Yang } 1399781a868fSWei Yang 1400781a868fSWei Yang /* Map the M64 here */ 1401ee8222feSWei Yang if (pdn->m64_single_mode) { 1402be283eebSWei Yang pe_num = pdn->pe_num_map[j]; 140302639b0eSWei Yang rc = opal_pci_map_pe_mmio_window(phb->opal_id, 140402639b0eSWei Yang pe_num, OPAL_M64_WINDOW_TYPE, 1405ee8222feSWei Yang pdn->m64_map[j][i], 0); 140602639b0eSWei Yang } 140702639b0eSWei Yang 1408781a868fSWei Yang rc = opal_pci_set_phb_mem_window(phb->opal_id, 1409781a868fSWei Yang OPAL_M64_WINDOW_TYPE, 1410ee8222feSWei Yang pdn->m64_map[j][i], 141102639b0eSWei Yang start, 1412781a868fSWei Yang 0, /* unused */ 141302639b0eSWei Yang size); 141402639b0eSWei Yang 141502639b0eSWei Yang 1416781a868fSWei Yang if (rc != OPAL_SUCCESS) { 1417781a868fSWei Yang dev_err(&pdev->dev, "Failed to map M64 window #%d: %lld\n", 1418781a868fSWei Yang win, rc); 1419781a868fSWei Yang goto m64_failed; 1420781a868fSWei Yang } 1421781a868fSWei Yang 1422ee8222feSWei Yang if (pdn->m64_single_mode) 1423781a868fSWei Yang rc = opal_pci_phb_mmio_enable(phb->opal_id, 1424ee8222feSWei Yang OPAL_M64_WINDOW_TYPE, pdn->m64_map[j][i], 2); 142502639b0eSWei Yang else 142602639b0eSWei Yang rc = opal_pci_phb_mmio_enable(phb->opal_id, 1427ee8222feSWei Yang OPAL_M64_WINDOW_TYPE, pdn->m64_map[j][i], 1); 142802639b0eSWei Yang 1429781a868fSWei Yang if (rc != OPAL_SUCCESS) { 1430781a868fSWei Yang dev_err(&pdev->dev, "Failed to enable M64 window #%d: %llx\n", 1431781a868fSWei Yang win, rc); 1432781a868fSWei Yang goto m64_failed; 1433781a868fSWei Yang } 1434781a868fSWei Yang } 143502639b0eSWei Yang } 1436781a868fSWei Yang return 0; 1437781a868fSWei Yang 1438781a868fSWei Yang m64_failed: 1439ee8222feSWei Yang pnv_pci_vf_release_m64(pdev, num_vfs); 1440781a868fSWei Yang return -EBUSY; 1441781a868fSWei Yang } 1442781a868fSWei Yang 1443c035e37bSAlexey Kardashevskiy static long pnv_pci_ioda2_unset_window(struct iommu_table_group *table_group, 1444c035e37bSAlexey Kardashevskiy int num); 1445c035e37bSAlexey Kardashevskiy 1446781a868fSWei Yang static void pnv_pci_ioda2_release_dma_pe(struct pci_dev *dev, struct pnv_ioda_pe *pe) 1447781a868fSWei Yang { 1448781a868fSWei Yang struct iommu_table *tbl; 1449781a868fSWei Yang int64_t rc; 1450781a868fSWei Yang 1451b348aa65SAlexey Kardashevskiy tbl = pe->table_group.tables[0]; 1452c035e37bSAlexey Kardashevskiy rc = pnv_pci_ioda2_unset_window(&pe->table_group, 0); 1453781a868fSWei Yang if (rc) 14541e496391SJoe Perches pe_warn(pe, "OPAL error %lld release DMA window\n", rc); 1455781a868fSWei Yang 1456c035e37bSAlexey Kardashevskiy pnv_pci_ioda2_set_bypass(pe, false); 14570eaf4defSAlexey Kardashevskiy if (pe->table_group.group) { 14580eaf4defSAlexey Kardashevskiy iommu_group_put(pe->table_group.group); 14590eaf4defSAlexey Kardashevskiy BUG_ON(pe->table_group.group); 1460ac9a5889SAlexey Kardashevskiy } 1461e5afdf9dSAlexey Kardashevskiy iommu_tce_table_put(tbl); 1462781a868fSWei Yang } 1463781a868fSWei Yang 1464ee8222feSWei Yang static void pnv_ioda_release_vf_PE(struct pci_dev *pdev) 1465781a868fSWei Yang { 1466781a868fSWei Yang struct pci_bus *bus; 1467781a868fSWei Yang struct pci_controller *hose; 1468781a868fSWei Yang struct pnv_phb *phb; 1469781a868fSWei Yang struct pnv_ioda_pe *pe, *pe_n; 1470781a868fSWei Yang struct pci_dn *pdn; 1471781a868fSWei Yang 1472781a868fSWei Yang bus = pdev->bus; 1473781a868fSWei Yang hose = pci_bus_to_host(bus); 1474781a868fSWei Yang phb = hose->private_data; 147502639b0eSWei Yang pdn = pci_get_pdn(pdev); 1476781a868fSWei Yang 1477781a868fSWei Yang if (!pdev->is_physfn) 1478781a868fSWei Yang return; 1479781a868fSWei Yang 1480781a868fSWei Yang list_for_each_entry_safe(pe, pe_n, &phb->ioda.pe_list, list) { 1481781a868fSWei Yang if (pe->parent_dev != pdev) 1482781a868fSWei Yang continue; 1483781a868fSWei Yang 1484781a868fSWei Yang pnv_pci_ioda2_release_dma_pe(pdev, pe); 1485781a868fSWei Yang 1486781a868fSWei Yang /* Remove from list */ 1487781a868fSWei Yang mutex_lock(&phb->ioda.pe_list_mutex); 1488781a868fSWei Yang list_del(&pe->list); 1489781a868fSWei Yang mutex_unlock(&phb->ioda.pe_list_mutex); 1490781a868fSWei Yang 1491781a868fSWei Yang pnv_ioda_deconfigure_pe(phb, pe); 1492781a868fSWei Yang 14931e916772SGavin Shan pnv_ioda_free_pe(pe); 1494781a868fSWei Yang } 1495781a868fSWei Yang } 1496781a868fSWei Yang 1497781a868fSWei Yang void pnv_pci_sriov_disable(struct pci_dev *pdev) 1498781a868fSWei Yang { 1499781a868fSWei Yang struct pci_bus *bus; 1500781a868fSWei Yang struct pci_controller *hose; 1501781a868fSWei Yang struct pnv_phb *phb; 15021e916772SGavin Shan struct pnv_ioda_pe *pe; 1503781a868fSWei Yang struct pci_dn *pdn; 1504be283eebSWei Yang u16 num_vfs, i; 1505781a868fSWei Yang 1506781a868fSWei Yang bus = pdev->bus; 1507781a868fSWei Yang hose = pci_bus_to_host(bus); 1508781a868fSWei Yang phb = hose->private_data; 1509781a868fSWei Yang pdn = pci_get_pdn(pdev); 1510781a868fSWei Yang num_vfs = pdn->num_vfs; 1511781a868fSWei Yang 1512781a868fSWei Yang /* Release VF PEs */ 1513ee8222feSWei Yang pnv_ioda_release_vf_PE(pdev); 1514781a868fSWei Yang 1515781a868fSWei Yang if (phb->type == PNV_PHB_IODA2) { 1516ee8222feSWei Yang if (!pdn->m64_single_mode) 1517be283eebSWei Yang pnv_pci_vf_resource_shift(pdev, -*pdn->pe_num_map); 1518781a868fSWei Yang 1519781a868fSWei Yang /* Release M64 windows */ 1520ee8222feSWei Yang pnv_pci_vf_release_m64(pdev, num_vfs); 1521781a868fSWei Yang 1522781a868fSWei Yang /* Release PE numbers */ 1523be283eebSWei Yang if (pdn->m64_single_mode) { 1524be283eebSWei Yang for (i = 0; i < num_vfs; i++) { 15251e916772SGavin Shan if (pdn->pe_num_map[i] == IODA_INVALID_PE) 15261e916772SGavin Shan continue; 15271e916772SGavin Shan 15281e916772SGavin Shan pe = &phb->ioda.pe_array[pdn->pe_num_map[i]]; 15291e916772SGavin Shan pnv_ioda_free_pe(pe); 1530be283eebSWei Yang } 1531be283eebSWei Yang } else 1532be283eebSWei Yang bitmap_clear(phb->ioda.pe_alloc, *pdn->pe_num_map, num_vfs); 1533be283eebSWei Yang /* Releasing pe_num_map */ 1534be283eebSWei Yang kfree(pdn->pe_num_map); 1535781a868fSWei Yang } 1536781a868fSWei Yang } 1537781a868fSWei Yang 1538781a868fSWei Yang static void pnv_pci_ioda2_setup_dma_pe(struct pnv_phb *phb, 1539781a868fSWei Yang struct pnv_ioda_pe *pe); 15405eada8a3SAlexey Kardashevskiy #ifdef CONFIG_IOMMU_API 15410bd97167SAlexey Kardashevskiy static void pnv_ioda_setup_bus_iommu_group(struct pnv_ioda_pe *pe, 15420bd97167SAlexey Kardashevskiy struct iommu_table_group *table_group, struct pci_bus *bus); 15430bd97167SAlexey Kardashevskiy 15445eada8a3SAlexey Kardashevskiy #endif 1545781a868fSWei Yang static void pnv_ioda_setup_vf_PE(struct pci_dev *pdev, u16 num_vfs) 1546781a868fSWei Yang { 1547781a868fSWei Yang struct pci_bus *bus; 1548781a868fSWei Yang struct pci_controller *hose; 1549781a868fSWei Yang struct pnv_phb *phb; 1550781a868fSWei Yang struct pnv_ioda_pe *pe; 1551781a868fSWei Yang int pe_num; 1552781a868fSWei Yang u16 vf_index; 1553781a868fSWei Yang struct pci_dn *pdn; 1554781a868fSWei Yang 1555781a868fSWei Yang bus = pdev->bus; 1556781a868fSWei Yang hose = pci_bus_to_host(bus); 1557781a868fSWei Yang phb = hose->private_data; 1558781a868fSWei Yang pdn = pci_get_pdn(pdev); 1559781a868fSWei Yang 1560781a868fSWei Yang if (!pdev->is_physfn) 1561781a868fSWei Yang return; 1562781a868fSWei Yang 1563781a868fSWei Yang /* Reserve PE for each VF */ 1564781a868fSWei Yang for (vf_index = 0; vf_index < num_vfs; vf_index++) { 1565be283eebSWei Yang if (pdn->m64_single_mode) 1566be283eebSWei Yang pe_num = pdn->pe_num_map[vf_index]; 1567be283eebSWei Yang else 1568be283eebSWei Yang pe_num = *pdn->pe_num_map + vf_index; 1569781a868fSWei Yang 1570781a868fSWei Yang pe = &phb->ioda.pe_array[pe_num]; 1571781a868fSWei Yang pe->pe_number = pe_num; 1572781a868fSWei Yang pe->phb = phb; 1573781a868fSWei Yang pe->flags = PNV_IODA_PE_VF; 1574781a868fSWei Yang pe->pbus = NULL; 1575781a868fSWei Yang pe->parent_dev = pdev; 1576781a868fSWei Yang pe->mve_number = -1; 1577781a868fSWei Yang pe->rid = (pci_iov_virtfn_bus(pdev, vf_index) << 8) | 1578781a868fSWei Yang pci_iov_virtfn_devfn(pdev, vf_index); 1579781a868fSWei Yang 15801f52f176SRussell Currey pe_info(pe, "VF %04d:%02d:%02d.%d associated with PE#%x\n", 1581781a868fSWei Yang hose->global_number, pdev->bus->number, 1582781a868fSWei Yang PCI_SLOT(pci_iov_virtfn_devfn(pdev, vf_index)), 1583781a868fSWei Yang PCI_FUNC(pci_iov_virtfn_devfn(pdev, vf_index)), pe_num); 1584781a868fSWei Yang 1585781a868fSWei Yang if (pnv_ioda_configure_pe(phb, pe)) { 1586781a868fSWei Yang /* XXX What do we do here ? */ 15871e916772SGavin Shan pnv_ioda_free_pe(pe); 1588781a868fSWei Yang pe->pdev = NULL; 1589781a868fSWei Yang continue; 1590781a868fSWei Yang } 1591781a868fSWei Yang 1592781a868fSWei Yang /* Put PE to the list */ 1593781a868fSWei Yang mutex_lock(&phb->ioda.pe_list_mutex); 1594781a868fSWei Yang list_add_tail(&pe->list, &phb->ioda.pe_list); 1595781a868fSWei Yang mutex_unlock(&phb->ioda.pe_list_mutex); 1596781a868fSWei Yang 1597781a868fSWei Yang pnv_pci_ioda2_setup_dma_pe(phb, pe); 15985eada8a3SAlexey Kardashevskiy #ifdef CONFIG_IOMMU_API 15998f5b2734SAlexey Kardashevskiy iommu_register_group(&pe->table_group, 16008f5b2734SAlexey Kardashevskiy pe->phb->hose->global_number, pe->pe_number); 16010bd97167SAlexey Kardashevskiy pnv_ioda_setup_bus_iommu_group(pe, &pe->table_group, NULL); 16025eada8a3SAlexey Kardashevskiy #endif 1603781a868fSWei Yang } 1604781a868fSWei Yang } 1605781a868fSWei Yang 1606781a868fSWei Yang int pnv_pci_sriov_enable(struct pci_dev *pdev, u16 num_vfs) 1607781a868fSWei Yang { 1608781a868fSWei Yang struct pci_bus *bus; 1609781a868fSWei Yang struct pci_controller *hose; 1610781a868fSWei Yang struct pnv_phb *phb; 16111e916772SGavin Shan struct pnv_ioda_pe *pe; 1612781a868fSWei Yang struct pci_dn *pdn; 1613781a868fSWei Yang int ret; 1614be283eebSWei Yang u16 i; 1615781a868fSWei Yang 1616781a868fSWei Yang bus = pdev->bus; 1617781a868fSWei Yang hose = pci_bus_to_host(bus); 1618781a868fSWei Yang phb = hose->private_data; 1619781a868fSWei Yang pdn = pci_get_pdn(pdev); 1620781a868fSWei Yang 1621781a868fSWei Yang if (phb->type == PNV_PHB_IODA2) { 1622b0331854SWei Yang if (!pdn->vfs_expanded) { 1623b0331854SWei Yang dev_info(&pdev->dev, "don't support this SRIOV device" 1624b0331854SWei Yang " with non 64bit-prefetchable IOV BAR\n"); 1625b0331854SWei Yang return -ENOSPC; 1626b0331854SWei Yang } 1627b0331854SWei Yang 1628ee8222feSWei Yang /* 1629ee8222feSWei Yang * When M64 BARs functions in Single PE mode, the number of VFs 1630ee8222feSWei Yang * could be enabled must be less than the number of M64 BARs. 1631ee8222feSWei Yang */ 1632ee8222feSWei Yang if (pdn->m64_single_mode && num_vfs > phb->ioda.m64_bar_idx) { 1633ee8222feSWei Yang dev_info(&pdev->dev, "Not enough M64 BAR for VFs\n"); 1634ee8222feSWei Yang return -EBUSY; 1635ee8222feSWei Yang } 1636ee8222feSWei Yang 1637be283eebSWei Yang /* Allocating pe_num_map */ 1638be283eebSWei Yang if (pdn->m64_single_mode) 1639fb37e128SMarkus Elfring pdn->pe_num_map = kmalloc_array(num_vfs, 1640fb37e128SMarkus Elfring sizeof(*pdn->pe_num_map), 1641be283eebSWei Yang GFP_KERNEL); 1642be283eebSWei Yang else 1643be283eebSWei Yang pdn->pe_num_map = kmalloc(sizeof(*pdn->pe_num_map), GFP_KERNEL); 1644be283eebSWei Yang 1645be283eebSWei Yang if (!pdn->pe_num_map) 1646be283eebSWei Yang return -ENOMEM; 1647be283eebSWei Yang 1648be283eebSWei Yang if (pdn->m64_single_mode) 1649be283eebSWei Yang for (i = 0; i < num_vfs; i++) 1650be283eebSWei Yang pdn->pe_num_map[i] = IODA_INVALID_PE; 1651be283eebSWei Yang 1652781a868fSWei Yang /* Calculate available PE for required VFs */ 1653be283eebSWei Yang if (pdn->m64_single_mode) { 1654be283eebSWei Yang for (i = 0; i < num_vfs; i++) { 16551e916772SGavin Shan pe = pnv_ioda_alloc_pe(phb); 16561e916772SGavin Shan if (!pe) { 1657be283eebSWei Yang ret = -EBUSY; 1658be283eebSWei Yang goto m64_failed; 1659be283eebSWei Yang } 16601e916772SGavin Shan 16611e916772SGavin Shan pdn->pe_num_map[i] = pe->pe_number; 1662be283eebSWei Yang } 1663be283eebSWei Yang } else { 1664781a868fSWei Yang mutex_lock(&phb->ioda.pe_alloc_mutex); 1665be283eebSWei Yang *pdn->pe_num_map = bitmap_find_next_zero_area( 166692b8f137SGavin Shan phb->ioda.pe_alloc, phb->ioda.total_pe_num, 1667781a868fSWei Yang 0, num_vfs, 0); 166892b8f137SGavin Shan if (*pdn->pe_num_map >= phb->ioda.total_pe_num) { 1669781a868fSWei Yang mutex_unlock(&phb->ioda.pe_alloc_mutex); 1670781a868fSWei Yang dev_info(&pdev->dev, "Failed to enable VF%d\n", num_vfs); 1671be283eebSWei Yang kfree(pdn->pe_num_map); 1672781a868fSWei Yang return -EBUSY; 1673781a868fSWei Yang } 1674be283eebSWei Yang bitmap_set(phb->ioda.pe_alloc, *pdn->pe_num_map, num_vfs); 1675781a868fSWei Yang mutex_unlock(&phb->ioda.pe_alloc_mutex); 1676be283eebSWei Yang } 1677be283eebSWei Yang pdn->num_vfs = num_vfs; 1678781a868fSWei Yang 1679781a868fSWei Yang /* Assign M64 window accordingly */ 168002639b0eSWei Yang ret = pnv_pci_vf_assign_m64(pdev, num_vfs); 1681781a868fSWei Yang if (ret) { 1682781a868fSWei Yang dev_info(&pdev->dev, "Not enough M64 window resources\n"); 1683781a868fSWei Yang goto m64_failed; 1684781a868fSWei Yang } 1685781a868fSWei Yang 1686781a868fSWei Yang /* 1687781a868fSWei Yang * When using one M64 BAR to map one IOV BAR, we need to shift 1688781a868fSWei Yang * the IOV BAR according to the PE# allocated to the VFs. 1689781a868fSWei Yang * Otherwise, the PE# for the VF will conflict with others. 1690781a868fSWei Yang */ 1691ee8222feSWei Yang if (!pdn->m64_single_mode) { 1692be283eebSWei Yang ret = pnv_pci_vf_resource_shift(pdev, *pdn->pe_num_map); 1693781a868fSWei Yang if (ret) 1694781a868fSWei Yang goto m64_failed; 1695781a868fSWei Yang } 169602639b0eSWei Yang } 1697781a868fSWei Yang 1698781a868fSWei Yang /* Setup VF PEs */ 1699781a868fSWei Yang pnv_ioda_setup_vf_PE(pdev, num_vfs); 1700781a868fSWei Yang 1701781a868fSWei Yang return 0; 1702781a868fSWei Yang 1703781a868fSWei Yang m64_failed: 1704be283eebSWei Yang if (pdn->m64_single_mode) { 1705be283eebSWei Yang for (i = 0; i < num_vfs; i++) { 17061e916772SGavin Shan if (pdn->pe_num_map[i] == IODA_INVALID_PE) 17071e916772SGavin Shan continue; 17081e916772SGavin Shan 17091e916772SGavin Shan pe = &phb->ioda.pe_array[pdn->pe_num_map[i]]; 17101e916772SGavin Shan pnv_ioda_free_pe(pe); 1711be283eebSWei Yang } 1712be283eebSWei Yang } else 1713be283eebSWei Yang bitmap_clear(phb->ioda.pe_alloc, *pdn->pe_num_map, num_vfs); 1714be283eebSWei Yang 1715be283eebSWei Yang /* Releasing pe_num_map */ 1716be283eebSWei Yang kfree(pdn->pe_num_map); 1717781a868fSWei Yang 1718781a868fSWei Yang return ret; 1719781a868fSWei Yang } 1720781a868fSWei Yang 1721988fc3baSBryant G. Ly int pnv_pcibios_sriov_disable(struct pci_dev *pdev) 1722a8b2f828SGavin Shan { 1723781a868fSWei Yang pnv_pci_sriov_disable(pdev); 1724781a868fSWei Yang 1725a8b2f828SGavin Shan /* Release PCI data */ 1726a8b2f828SGavin Shan remove_dev_pci_data(pdev); 1727a8b2f828SGavin Shan return 0; 1728a8b2f828SGavin Shan } 1729a8b2f828SGavin Shan 1730988fc3baSBryant G. Ly int pnv_pcibios_sriov_enable(struct pci_dev *pdev, u16 num_vfs) 1731a8b2f828SGavin Shan { 1732a8b2f828SGavin Shan /* Allocate PCI data */ 1733a8b2f828SGavin Shan add_dev_pci_data(pdev); 1734781a868fSWei Yang 1735ee8222feSWei Yang return pnv_pci_sriov_enable(pdev, num_vfs); 1736a8b2f828SGavin Shan } 1737a8b2f828SGavin Shan #endif /* CONFIG_PCI_IOV */ 1738a8b2f828SGavin Shan 1739959c9bddSGavin Shan static void pnv_pci_ioda_dma_dev_setup(struct pnv_phb *phb, struct pci_dev *pdev) 1740184cd4a3SBenjamin Herrenschmidt { 1741b72c1f65SBenjamin Herrenschmidt struct pci_dn *pdn = pci_get_pdn(pdev); 1742959c9bddSGavin Shan struct pnv_ioda_pe *pe; 1743184cd4a3SBenjamin Herrenschmidt 1744959c9bddSGavin Shan /* 1745959c9bddSGavin Shan * The function can be called while the PE# 1746959c9bddSGavin Shan * hasn't been assigned. Do nothing for the 1747959c9bddSGavin Shan * case. 1748959c9bddSGavin Shan */ 1749959c9bddSGavin Shan if (!pdn || pdn->pe_number == IODA_INVALID_PE) 1750959c9bddSGavin Shan return; 1751184cd4a3SBenjamin Herrenschmidt 1752959c9bddSGavin Shan pe = &phb->ioda.pe_array[pdn->pe_number]; 1753cd15b048SBenjamin Herrenschmidt WARN_ON(get_dma_ops(&pdev->dev) != &dma_iommu_ops); 17540617fc0cSChristoph Hellwig pdev->dev.archdata.dma_offset = pe->tce_bypass_base; 1755b348aa65SAlexey Kardashevskiy set_iommu_table_base(&pdev->dev, pe->table_group.tables[0]); 17564617082eSAlexey Kardashevskiy /* 17574617082eSAlexey Kardashevskiy * Note: iommu_add_device() will fail here as 17584617082eSAlexey Kardashevskiy * for physical PE: the device is already added by now; 17594617082eSAlexey Kardashevskiy * for virtual PE: sysfs entries are not ready yet and 17604617082eSAlexey Kardashevskiy * tce_iommu_bus_notifier will add the device to a group later. 17614617082eSAlexey Kardashevskiy */ 1762184cd4a3SBenjamin Herrenschmidt } 1763184cd4a3SBenjamin Herrenschmidt 17648e3f1b1dSRussell Currey /* 17658e3f1b1dSRussell Currey * Reconfigure TVE#0 to be usable as 64-bit DMA space. 17668e3f1b1dSRussell Currey * 17678e3f1b1dSRussell Currey * The first 4GB of virtual memory for a PE is reserved for 32-bit accesses. 17688e3f1b1dSRussell Currey * Devices can only access more than that if bit 59 of the PCI address is set 17698e3f1b1dSRussell Currey * by hardware, which indicates TVE#1 should be used instead of TVE#0. 17708e3f1b1dSRussell Currey * Many PCI devices are not capable of addressing that many bits, and as a 17718e3f1b1dSRussell Currey * result are limited to the 4GB of virtual memory made available to 32-bit 17728e3f1b1dSRussell Currey * devices in TVE#0. 17738e3f1b1dSRussell Currey * 17748e3f1b1dSRussell Currey * In order to work around this, reconfigure TVE#0 to be suitable for 64-bit 17758e3f1b1dSRussell Currey * devices by configuring the virtual memory past the first 4GB inaccessible 17768e3f1b1dSRussell Currey * by 64-bit DMAs. This should only be used by devices that want more than 17778e3f1b1dSRussell Currey * 4GB, and only on PEs that have no 32-bit devices. 17788e3f1b1dSRussell Currey * 17798e3f1b1dSRussell Currey * Currently this will only work on PHB3 (POWER8). 17808e3f1b1dSRussell Currey */ 17818e3f1b1dSRussell Currey static int pnv_pci_ioda_dma_64bit_bypass(struct pnv_ioda_pe *pe) 17828e3f1b1dSRussell Currey { 17838e3f1b1dSRussell Currey u64 window_size, table_size, tce_count, addr; 17848e3f1b1dSRussell Currey struct page *table_pages; 17858e3f1b1dSRussell Currey u64 tce_order = 28; /* 256MB TCEs */ 17868e3f1b1dSRussell Currey __be64 *tces; 17878e3f1b1dSRussell Currey s64 rc; 17888e3f1b1dSRussell Currey 17898e3f1b1dSRussell Currey /* 17908e3f1b1dSRussell Currey * Window size needs to be a power of two, but needs to account for 17918e3f1b1dSRussell Currey * shifting memory by the 4GB offset required to skip 32bit space. 17928e3f1b1dSRussell Currey */ 17938e3f1b1dSRussell Currey window_size = roundup_pow_of_two(memory_hotplug_max() + (1ULL << 32)); 17948e3f1b1dSRussell Currey tce_count = window_size >> tce_order; 17958e3f1b1dSRussell Currey table_size = tce_count << 3; 17968e3f1b1dSRussell Currey 17978e3f1b1dSRussell Currey if (table_size < PAGE_SIZE) 17988e3f1b1dSRussell Currey table_size = PAGE_SIZE; 17998e3f1b1dSRussell Currey 18008e3f1b1dSRussell Currey table_pages = alloc_pages_node(pe->phb->hose->node, GFP_KERNEL, 18018e3f1b1dSRussell Currey get_order(table_size)); 18028e3f1b1dSRussell Currey if (!table_pages) 18038e3f1b1dSRussell Currey goto err; 18048e3f1b1dSRussell Currey 18058e3f1b1dSRussell Currey tces = page_address(table_pages); 18068e3f1b1dSRussell Currey if (!tces) 18078e3f1b1dSRussell Currey goto err; 18088e3f1b1dSRussell Currey 18098e3f1b1dSRussell Currey memset(tces, 0, table_size); 18108e3f1b1dSRussell Currey 18118e3f1b1dSRussell Currey for (addr = 0; addr < memory_hotplug_max(); addr += (1 << tce_order)) { 18128e3f1b1dSRussell Currey tces[(addr + (1ULL << 32)) >> tce_order] = 18138e3f1b1dSRussell Currey cpu_to_be64(addr | TCE_PCI_READ | TCE_PCI_WRITE); 18148e3f1b1dSRussell Currey } 18158e3f1b1dSRussell Currey 18168e3f1b1dSRussell Currey rc = opal_pci_map_pe_dma_window(pe->phb->opal_id, 18178e3f1b1dSRussell Currey pe->pe_number, 18188e3f1b1dSRussell Currey /* reconfigure window 0 */ 18198e3f1b1dSRussell Currey (pe->pe_number << 1) + 0, 18208e3f1b1dSRussell Currey 1, 18218e3f1b1dSRussell Currey __pa(tces), 18228e3f1b1dSRussell Currey table_size, 18238e3f1b1dSRussell Currey 1 << tce_order); 18248e3f1b1dSRussell Currey if (rc == OPAL_SUCCESS) { 18258e3f1b1dSRussell Currey pe_info(pe, "Using 64-bit DMA iommu bypass (through TVE#0)\n"); 18268e3f1b1dSRussell Currey return 0; 18278e3f1b1dSRussell Currey } 18288e3f1b1dSRussell Currey err: 18298e3f1b1dSRussell Currey pe_err(pe, "Error configuring 64-bit DMA bypass\n"); 18308e3f1b1dSRussell Currey return -EIO; 18318e3f1b1dSRussell Currey } 18328e3f1b1dSRussell Currey 18332d6ad41bSChristoph Hellwig static bool pnv_pci_ioda_iommu_bypass_supported(struct pci_dev *pdev, 18342d6ad41bSChristoph Hellwig u64 dma_mask) 1835cd15b048SBenjamin Herrenschmidt { 1836763d2d8dSDaniel Axtens struct pci_controller *hose = pci_bus_to_host(pdev->bus); 1837763d2d8dSDaniel Axtens struct pnv_phb *phb = hose->private_data; 1838cd15b048SBenjamin Herrenschmidt struct pci_dn *pdn = pci_get_pdn(pdev); 1839cd15b048SBenjamin Herrenschmidt struct pnv_ioda_pe *pe; 1840cd15b048SBenjamin Herrenschmidt 1841cd15b048SBenjamin Herrenschmidt if (WARN_ON(!pdn || pdn->pe_number == IODA_INVALID_PE)) 1842b511cdd1SAlexey Kardashevskiy return false; 1843cd15b048SBenjamin Herrenschmidt 1844cd15b048SBenjamin Herrenschmidt pe = &phb->ioda.pe_array[pdn->pe_number]; 1845cd15b048SBenjamin Herrenschmidt if (pe->tce_bypass_enabled) { 18462d6ad41bSChristoph Hellwig u64 top = pe->tce_bypass_base + memblock_end_of_DRAM() - 1; 18472d6ad41bSChristoph Hellwig if (dma_mask >= top) 18482d6ad41bSChristoph Hellwig return true; 1849cd15b048SBenjamin Herrenschmidt } 1850cd15b048SBenjamin Herrenschmidt 18518e3f1b1dSRussell Currey /* 18528e3f1b1dSRussell Currey * If the device can't set the TCE bypass bit but still wants 18538e3f1b1dSRussell Currey * to access 4GB or more, on PHB3 we can reconfigure TVE#0 to 18548e3f1b1dSRussell Currey * bypass the 32-bit region and be usable for 64-bit DMAs. 18558e3f1b1dSRussell Currey * The device needs to be able to address all of this space. 18568e3f1b1dSRussell Currey */ 18578e3f1b1dSRussell Currey if (dma_mask >> 32 && 18588e3f1b1dSRussell Currey dma_mask > (memory_hotplug_max() + (1ULL << 32)) && 1859661fcb45SChristoph Hellwig /* pe->pdev should be set if it's a single device, pe->pbus if not */ 1860661fcb45SChristoph Hellwig (pe->device_count == 1 || !pe->pbus) && 18618e3f1b1dSRussell Currey phb->model == PNV_PHB_MODEL_PHB3) { 18628e3f1b1dSRussell Currey /* Configure the bypass mode */ 18632d6ad41bSChristoph Hellwig s64 rc = pnv_pci_ioda_dma_64bit_bypass(pe); 18648e3f1b1dSRussell Currey if (rc) 1865b511cdd1SAlexey Kardashevskiy return false; 18668e3f1b1dSRussell Currey /* 4GB offset bypasses 32-bit space */ 18670617fc0cSChristoph Hellwig pdev->dev.archdata.dma_offset = (1ULL << 32); 18682d6ad41bSChristoph Hellwig return true; 1869cd15b048SBenjamin Herrenschmidt } 1870cd15b048SBenjamin Herrenschmidt 18712d6ad41bSChristoph Hellwig return false; 1872fe7e85c6SGavin Shan } 1873fe7e85c6SGavin Shan 18745eada8a3SAlexey Kardashevskiy static void pnv_ioda_setup_bus_dma(struct pnv_ioda_pe *pe, struct pci_bus *bus) 187574251fe2SBenjamin Herrenschmidt { 187674251fe2SBenjamin Herrenschmidt struct pci_dev *dev; 187774251fe2SBenjamin Herrenschmidt 187874251fe2SBenjamin Herrenschmidt list_for_each_entry(dev, &bus->devices, bus_list) { 1879b348aa65SAlexey Kardashevskiy set_iommu_table_base(&dev->dev, pe->table_group.tables[0]); 18800617fc0cSChristoph Hellwig dev->dev.archdata.dma_offset = pe->tce_bypass_base; 1881dff4a39eSGavin Shan 18825c89a87dSAlexey Kardashevskiy if ((pe->flags & PNV_IODA_PE_BUS_ALL) && dev->subordinate) 18835eada8a3SAlexey Kardashevskiy pnv_ioda_setup_bus_dma(pe, dev->subordinate); 188474251fe2SBenjamin Herrenschmidt } 188574251fe2SBenjamin Herrenschmidt } 188674251fe2SBenjamin Herrenschmidt 1887fd141d1aSBenjamin Herrenschmidt static inline __be64 __iomem *pnv_ioda_get_inval_reg(struct pnv_phb *phb, 1888fd141d1aSBenjamin Herrenschmidt bool real_mode) 1889fd141d1aSBenjamin Herrenschmidt { 1890fd141d1aSBenjamin Herrenschmidt return real_mode ? (__be64 __iomem *)(phb->regs_phys + 0x210) : 1891fd141d1aSBenjamin Herrenschmidt (phb->regs + 0x210); 1892fd141d1aSBenjamin Herrenschmidt } 1893fd141d1aSBenjamin Herrenschmidt 1894a34ab7c3SBenjamin Herrenschmidt static void pnv_pci_p7ioc_tce_invalidate(struct iommu_table *tbl, 1895decbda25SAlexey Kardashevskiy unsigned long index, unsigned long npages, bool rm) 18964cce9550SGavin Shan { 18970eaf4defSAlexey Kardashevskiy struct iommu_table_group_link *tgl = list_first_entry_or_null( 18980eaf4defSAlexey Kardashevskiy &tbl->it_group_list, struct iommu_table_group_link, 18990eaf4defSAlexey Kardashevskiy next); 19000eaf4defSAlexey Kardashevskiy struct pnv_ioda_pe *pe = container_of(tgl->table_group, 1901b348aa65SAlexey Kardashevskiy struct pnv_ioda_pe, table_group); 1902fd141d1aSBenjamin Herrenschmidt __be64 __iomem *invalidate = pnv_ioda_get_inval_reg(pe->phb, rm); 19034cce9550SGavin Shan unsigned long start, end, inc; 19044cce9550SGavin Shan 1905decbda25SAlexey Kardashevskiy start = __pa(((__be64 *)tbl->it_base) + index - tbl->it_offset); 1906decbda25SAlexey Kardashevskiy end = __pa(((__be64 *)tbl->it_base) + index - tbl->it_offset + 1907decbda25SAlexey Kardashevskiy npages - 1); 19084cce9550SGavin Shan 19094cce9550SGavin Shan /* p7ioc-style invalidation, 2 TCEs per write */ 19104cce9550SGavin Shan start |= (1ull << 63); 19114cce9550SGavin Shan end |= (1ull << 63); 19124cce9550SGavin Shan inc = 16; 19134cce9550SGavin Shan end |= inc - 1; /* round up end to be different than start */ 19144cce9550SGavin Shan 19154cce9550SGavin Shan mb(); /* Ensure above stores are visible */ 19164cce9550SGavin Shan while (start <= end) { 19178e0a1611SAlexey Kardashevskiy if (rm) 1918001ff2eeSMichael Ellerman __raw_rm_writeq_be(start, invalidate); 19198e0a1611SAlexey Kardashevskiy else 1920001ff2eeSMichael Ellerman __raw_writeq_be(start, invalidate); 1921001ff2eeSMichael Ellerman 19224cce9550SGavin Shan start += inc; 19234cce9550SGavin Shan } 19244cce9550SGavin Shan 19254cce9550SGavin Shan /* 19264cce9550SGavin Shan * The iommu layer will do another mb() for us on build() 19274cce9550SGavin Shan * and we don't care on free() 19284cce9550SGavin Shan */ 19294cce9550SGavin Shan } 19304cce9550SGavin Shan 1931decbda25SAlexey Kardashevskiy static int pnv_ioda1_tce_build(struct iommu_table *tbl, long index, 1932decbda25SAlexey Kardashevskiy long npages, unsigned long uaddr, 1933decbda25SAlexey Kardashevskiy enum dma_data_direction direction, 193400085f1eSKrzysztof Kozlowski unsigned long attrs) 1935decbda25SAlexey Kardashevskiy { 1936decbda25SAlexey Kardashevskiy int ret = pnv_tce_build(tbl, index, npages, uaddr, direction, 1937decbda25SAlexey Kardashevskiy attrs); 1938decbda25SAlexey Kardashevskiy 193908acce1cSBenjamin Herrenschmidt if (!ret) 1940a34ab7c3SBenjamin Herrenschmidt pnv_pci_p7ioc_tce_invalidate(tbl, index, npages, false); 1941decbda25SAlexey Kardashevskiy 1942decbda25SAlexey Kardashevskiy return ret; 1943decbda25SAlexey Kardashevskiy } 1944decbda25SAlexey Kardashevskiy 194505c6cfb9SAlexey Kardashevskiy #ifdef CONFIG_IOMMU_API 194605c6cfb9SAlexey Kardashevskiy static int pnv_ioda1_tce_xchg(struct iommu_table *tbl, long index, 194705c6cfb9SAlexey Kardashevskiy unsigned long *hpa, enum dma_data_direction *direction) 194805c6cfb9SAlexey Kardashevskiy { 1949a68bd126SAlexey Kardashevskiy long ret = pnv_tce_xchg(tbl, index, hpa, direction, true); 195005c6cfb9SAlexey Kardashevskiy 195108acce1cSBenjamin Herrenschmidt if (!ret) 1952a34ab7c3SBenjamin Herrenschmidt pnv_pci_p7ioc_tce_invalidate(tbl, index, 1, false); 195305c6cfb9SAlexey Kardashevskiy 195405c6cfb9SAlexey Kardashevskiy return ret; 195505c6cfb9SAlexey Kardashevskiy } 1956a540aa56SAlexey Kardashevskiy 1957a540aa56SAlexey Kardashevskiy static int pnv_ioda1_tce_xchg_rm(struct iommu_table *tbl, long index, 1958a540aa56SAlexey Kardashevskiy unsigned long *hpa, enum dma_data_direction *direction) 1959a540aa56SAlexey Kardashevskiy { 1960a68bd126SAlexey Kardashevskiy long ret = pnv_tce_xchg(tbl, index, hpa, direction, false); 1961a540aa56SAlexey Kardashevskiy 1962a540aa56SAlexey Kardashevskiy if (!ret) 1963a540aa56SAlexey Kardashevskiy pnv_pci_p7ioc_tce_invalidate(tbl, index, 1, true); 1964a540aa56SAlexey Kardashevskiy 1965a540aa56SAlexey Kardashevskiy return ret; 1966a540aa56SAlexey Kardashevskiy } 196705c6cfb9SAlexey Kardashevskiy #endif 196805c6cfb9SAlexey Kardashevskiy 1969decbda25SAlexey Kardashevskiy static void pnv_ioda1_tce_free(struct iommu_table *tbl, long index, 1970decbda25SAlexey Kardashevskiy long npages) 1971decbda25SAlexey Kardashevskiy { 1972decbda25SAlexey Kardashevskiy pnv_tce_free(tbl, index, npages); 1973decbda25SAlexey Kardashevskiy 1974a34ab7c3SBenjamin Herrenschmidt pnv_pci_p7ioc_tce_invalidate(tbl, index, npages, false); 1975decbda25SAlexey Kardashevskiy } 1976decbda25SAlexey Kardashevskiy 1977da004c36SAlexey Kardashevskiy static struct iommu_table_ops pnv_ioda1_iommu_ops = { 1978decbda25SAlexey Kardashevskiy .set = pnv_ioda1_tce_build, 197905c6cfb9SAlexey Kardashevskiy #ifdef CONFIG_IOMMU_API 198005c6cfb9SAlexey Kardashevskiy .exchange = pnv_ioda1_tce_xchg, 1981a540aa56SAlexey Kardashevskiy .exchange_rm = pnv_ioda1_tce_xchg_rm, 1982090bad39SAlexey Kardashevskiy .useraddrptr = pnv_tce_useraddrptr, 198305c6cfb9SAlexey Kardashevskiy #endif 1984decbda25SAlexey Kardashevskiy .clear = pnv_ioda1_tce_free, 1985da004c36SAlexey Kardashevskiy .get = pnv_tce_get, 1986da004c36SAlexey Kardashevskiy }; 1987da004c36SAlexey Kardashevskiy 1988a34ab7c3SBenjamin Herrenschmidt #define PHB3_TCE_KILL_INVAL_ALL PPC_BIT(0) 1989a34ab7c3SBenjamin Herrenschmidt #define PHB3_TCE_KILL_INVAL_PE PPC_BIT(1) 1990a34ab7c3SBenjamin Herrenschmidt #define PHB3_TCE_KILL_INVAL_ONE PPC_BIT(2) 1991bef9253fSAlexey Kardashevskiy 19926b3d12a9SAlistair Popple static void pnv_pci_phb3_tce_invalidate_entire(struct pnv_phb *phb, bool rm) 19930bbcdb43SAlexey Kardashevskiy { 1994fd141d1aSBenjamin Herrenschmidt __be64 __iomem *invalidate = pnv_ioda_get_inval_reg(phb, rm); 1995a34ab7c3SBenjamin Herrenschmidt const unsigned long val = PHB3_TCE_KILL_INVAL_ALL; 19960bbcdb43SAlexey Kardashevskiy 19970bbcdb43SAlexey Kardashevskiy mb(); /* Ensure previous TCE table stores are visible */ 19980bbcdb43SAlexey Kardashevskiy if (rm) 1999001ff2eeSMichael Ellerman __raw_rm_writeq_be(val, invalidate); 20000bbcdb43SAlexey Kardashevskiy else 2001001ff2eeSMichael Ellerman __raw_writeq_be(val, invalidate); 20020bbcdb43SAlexey Kardashevskiy } 20030bbcdb43SAlexey Kardashevskiy 2004a34ab7c3SBenjamin Herrenschmidt static inline void pnv_pci_phb3_tce_invalidate_pe(struct pnv_ioda_pe *pe) 20055780fb04SAlexey Kardashevskiy { 20065780fb04SAlexey Kardashevskiy /* 01xb - invalidate TCEs that match the specified PE# */ 2007fd141d1aSBenjamin Herrenschmidt __be64 __iomem *invalidate = pnv_ioda_get_inval_reg(pe->phb, false); 2008a34ab7c3SBenjamin Herrenschmidt unsigned long val = PHB3_TCE_KILL_INVAL_PE | (pe->pe_number & 0xFF); 20095780fb04SAlexey Kardashevskiy 20105780fb04SAlexey Kardashevskiy mb(); /* Ensure above stores are visible */ 2011001ff2eeSMichael Ellerman __raw_writeq_be(val, invalidate); 20125780fb04SAlexey Kardashevskiy } 20135780fb04SAlexey Kardashevskiy 2014fd141d1aSBenjamin Herrenschmidt static void pnv_pci_phb3_tce_invalidate(struct pnv_ioda_pe *pe, bool rm, 2015fd141d1aSBenjamin Herrenschmidt unsigned shift, unsigned long index, 2016fd141d1aSBenjamin Herrenschmidt unsigned long npages) 20174cce9550SGavin Shan { 20184d902195SAlexey Kardashevskiy __be64 __iomem *invalidate = pnv_ioda_get_inval_reg(pe->phb, rm); 20194cce9550SGavin Shan unsigned long start, end, inc; 20204cce9550SGavin Shan 20214cce9550SGavin Shan /* We'll invalidate DMA address in PE scope */ 2022a34ab7c3SBenjamin Herrenschmidt start = PHB3_TCE_KILL_INVAL_ONE; 2023fd141d1aSBenjamin Herrenschmidt start |= (pe->pe_number & 0xFF); 20244cce9550SGavin Shan end = start; 20254cce9550SGavin Shan 20264cce9550SGavin Shan /* Figure out the start, end and step */ 2027decbda25SAlexey Kardashevskiy start |= (index << shift); 2028decbda25SAlexey Kardashevskiy end |= ((index + npages - 1) << shift); 2029b0376c9bSAlexey Kardashevskiy inc = (0x1ull << shift); 20304cce9550SGavin Shan mb(); 20314cce9550SGavin Shan 20324cce9550SGavin Shan while (start <= end) { 20338e0a1611SAlexey Kardashevskiy if (rm) 2034001ff2eeSMichael Ellerman __raw_rm_writeq_be(start, invalidate); 20358e0a1611SAlexey Kardashevskiy else 2036001ff2eeSMichael Ellerman __raw_writeq_be(start, invalidate); 20374cce9550SGavin Shan start += inc; 20384cce9550SGavin Shan } 20394cce9550SGavin Shan } 20404cce9550SGavin Shan 2041f0228c41SBenjamin Herrenschmidt static inline void pnv_pci_ioda2_tce_invalidate_pe(struct pnv_ioda_pe *pe) 2042f0228c41SBenjamin Herrenschmidt { 2043f0228c41SBenjamin Herrenschmidt struct pnv_phb *phb = pe->phb; 2044f0228c41SBenjamin Herrenschmidt 2045f0228c41SBenjamin Herrenschmidt if (phb->model == PNV_PHB_MODEL_PHB3 && phb->regs) 2046f0228c41SBenjamin Herrenschmidt pnv_pci_phb3_tce_invalidate_pe(pe); 2047f0228c41SBenjamin Herrenschmidt else 2048f0228c41SBenjamin Herrenschmidt opal_pci_tce_kill(phb->opal_id, OPAL_PCI_TCE_KILL_PE, 2049f0228c41SBenjamin Herrenschmidt pe->pe_number, 0, 0, 0); 2050f0228c41SBenjamin Herrenschmidt } 2051f0228c41SBenjamin Herrenschmidt 2052e57080f1SAlexey Kardashevskiy static void pnv_pci_ioda2_tce_invalidate(struct iommu_table *tbl, 2053e57080f1SAlexey Kardashevskiy unsigned long index, unsigned long npages, bool rm) 2054e57080f1SAlexey Kardashevskiy { 2055e57080f1SAlexey Kardashevskiy struct iommu_table_group_link *tgl; 2056e57080f1SAlexey Kardashevskiy 2057a540aa56SAlexey Kardashevskiy list_for_each_entry_lockless(tgl, &tbl->it_group_list, next) { 2058e57080f1SAlexey Kardashevskiy struct pnv_ioda_pe *pe = container_of(tgl->table_group, 2059e57080f1SAlexey Kardashevskiy struct pnv_ioda_pe, table_group); 2060f0228c41SBenjamin Herrenschmidt struct pnv_phb *phb = pe->phb; 2061f0228c41SBenjamin Herrenschmidt unsigned int shift = tbl->it_page_shift; 2062f0228c41SBenjamin Herrenschmidt 2063616badd2SAlistair Popple /* 2064616badd2SAlistair Popple * NVLink1 can use the TCE kill register directly as 2065616badd2SAlistair Popple * it's the same as PHB3. NVLink2 is different and 2066616badd2SAlistair Popple * should go via the OPAL call. 2067616badd2SAlistair Popple */ 2068616badd2SAlistair Popple if (phb->model == PNV_PHB_MODEL_NPU) { 20690bbcdb43SAlexey Kardashevskiy /* 20700bbcdb43SAlexey Kardashevskiy * The NVLink hardware does not support TCE kill 20710bbcdb43SAlexey Kardashevskiy * per TCE entry so we have to invalidate 20720bbcdb43SAlexey Kardashevskiy * the entire cache for it. 20730bbcdb43SAlexey Kardashevskiy */ 2074f0228c41SBenjamin Herrenschmidt pnv_pci_phb3_tce_invalidate_entire(phb, rm); 20755d2aa710SAlistair Popple continue; 20765d2aa710SAlistair Popple } 2077f0228c41SBenjamin Herrenschmidt if (phb->model == PNV_PHB_MODEL_PHB3 && phb->regs) 2078f0228c41SBenjamin Herrenschmidt pnv_pci_phb3_tce_invalidate(pe, rm, shift, 207985674868SAlexey Kardashevskiy index, npages); 2080f0228c41SBenjamin Herrenschmidt else 2081f0228c41SBenjamin Herrenschmidt opal_pci_tce_kill(phb->opal_id, 2082f0228c41SBenjamin Herrenschmidt OPAL_PCI_TCE_KILL_PAGES, 2083f0228c41SBenjamin Herrenschmidt pe->pe_number, 1u << shift, 2084f0228c41SBenjamin Herrenschmidt index << shift, npages); 2085e57080f1SAlexey Kardashevskiy } 2086e57080f1SAlexey Kardashevskiy } 2087e57080f1SAlexey Kardashevskiy 20886b3d12a9SAlistair Popple void pnv_pci_ioda2_tce_invalidate_entire(struct pnv_phb *phb, bool rm) 20896b3d12a9SAlistair Popple { 20906b3d12a9SAlistair Popple if (phb->model == PNV_PHB_MODEL_NPU || phb->model == PNV_PHB_MODEL_PHB3) 20916b3d12a9SAlistair Popple pnv_pci_phb3_tce_invalidate_entire(phb, rm); 20926b3d12a9SAlistair Popple else 20936b3d12a9SAlistair Popple opal_pci_tce_kill(phb->opal_id, OPAL_PCI_TCE_KILL, 0, 0, 0, 0); 20946b3d12a9SAlistair Popple } 20956b3d12a9SAlistair Popple 2096decbda25SAlexey Kardashevskiy static int pnv_ioda2_tce_build(struct iommu_table *tbl, long index, 2097decbda25SAlexey Kardashevskiy long npages, unsigned long uaddr, 2098decbda25SAlexey Kardashevskiy enum dma_data_direction direction, 209900085f1eSKrzysztof Kozlowski unsigned long attrs) 21004cce9550SGavin Shan { 2101decbda25SAlexey Kardashevskiy int ret = pnv_tce_build(tbl, index, npages, uaddr, direction, 2102decbda25SAlexey Kardashevskiy attrs); 21034cce9550SGavin Shan 210408acce1cSBenjamin Herrenschmidt if (!ret) 2105decbda25SAlexey Kardashevskiy pnv_pci_ioda2_tce_invalidate(tbl, index, npages, false); 2106decbda25SAlexey Kardashevskiy 2107decbda25SAlexey Kardashevskiy return ret; 2108decbda25SAlexey Kardashevskiy } 2109decbda25SAlexey Kardashevskiy 211005c6cfb9SAlexey Kardashevskiy #ifdef CONFIG_IOMMU_API 211105c6cfb9SAlexey Kardashevskiy static int pnv_ioda2_tce_xchg(struct iommu_table *tbl, long index, 211205c6cfb9SAlexey Kardashevskiy unsigned long *hpa, enum dma_data_direction *direction) 211305c6cfb9SAlexey Kardashevskiy { 2114a68bd126SAlexey Kardashevskiy long ret = pnv_tce_xchg(tbl, index, hpa, direction, true); 211505c6cfb9SAlexey Kardashevskiy 211608acce1cSBenjamin Herrenschmidt if (!ret) 211705c6cfb9SAlexey Kardashevskiy pnv_pci_ioda2_tce_invalidate(tbl, index, 1, false); 211805c6cfb9SAlexey Kardashevskiy 211905c6cfb9SAlexey Kardashevskiy return ret; 212005c6cfb9SAlexey Kardashevskiy } 2121a540aa56SAlexey Kardashevskiy 2122a540aa56SAlexey Kardashevskiy static int pnv_ioda2_tce_xchg_rm(struct iommu_table *tbl, long index, 2123a540aa56SAlexey Kardashevskiy unsigned long *hpa, enum dma_data_direction *direction) 2124a540aa56SAlexey Kardashevskiy { 2125a68bd126SAlexey Kardashevskiy long ret = pnv_tce_xchg(tbl, index, hpa, direction, false); 2126a540aa56SAlexey Kardashevskiy 2127a540aa56SAlexey Kardashevskiy if (!ret) 2128a540aa56SAlexey Kardashevskiy pnv_pci_ioda2_tce_invalidate(tbl, index, 1, true); 2129a540aa56SAlexey Kardashevskiy 2130a540aa56SAlexey Kardashevskiy return ret; 2131a540aa56SAlexey Kardashevskiy } 213205c6cfb9SAlexey Kardashevskiy #endif 213305c6cfb9SAlexey Kardashevskiy 2134decbda25SAlexey Kardashevskiy static void pnv_ioda2_tce_free(struct iommu_table *tbl, long index, 2135decbda25SAlexey Kardashevskiy long npages) 2136decbda25SAlexey Kardashevskiy { 2137decbda25SAlexey Kardashevskiy pnv_tce_free(tbl, index, npages); 2138decbda25SAlexey Kardashevskiy 2139decbda25SAlexey Kardashevskiy pnv_pci_ioda2_tce_invalidate(tbl, index, npages, false); 21404cce9550SGavin Shan } 21414cce9550SGavin Shan 2142da004c36SAlexey Kardashevskiy static struct iommu_table_ops pnv_ioda2_iommu_ops = { 2143decbda25SAlexey Kardashevskiy .set = pnv_ioda2_tce_build, 214405c6cfb9SAlexey Kardashevskiy #ifdef CONFIG_IOMMU_API 214505c6cfb9SAlexey Kardashevskiy .exchange = pnv_ioda2_tce_xchg, 2146a540aa56SAlexey Kardashevskiy .exchange_rm = pnv_ioda2_tce_xchg_rm, 2147090bad39SAlexey Kardashevskiy .useraddrptr = pnv_tce_useraddrptr, 214805c6cfb9SAlexey Kardashevskiy #endif 2149decbda25SAlexey Kardashevskiy .clear = pnv_ioda2_tce_free, 2150da004c36SAlexey Kardashevskiy .get = pnv_tce_get, 2151da2bb0daSAlexey Kardashevskiy .free = pnv_pci_ioda2_table_free_pages, 2152da004c36SAlexey Kardashevskiy }; 2153da004c36SAlexey Kardashevskiy 2154801846d1SGavin Shan static int pnv_pci_ioda_dev_dma_weight(struct pci_dev *dev, void *data) 2155801846d1SGavin Shan { 2156801846d1SGavin Shan unsigned int *weight = (unsigned int *)data; 2157801846d1SGavin Shan 2158801846d1SGavin Shan /* This is quite simplistic. The "base" weight of a device 2159801846d1SGavin Shan * is 10. 0 means no DMA is to be accounted for it. 2160801846d1SGavin Shan */ 2161801846d1SGavin Shan if (dev->hdr_type != PCI_HEADER_TYPE_NORMAL) 2162801846d1SGavin Shan return 0; 2163801846d1SGavin Shan 2164801846d1SGavin Shan if (dev->class == PCI_CLASS_SERIAL_USB_UHCI || 2165801846d1SGavin Shan dev->class == PCI_CLASS_SERIAL_USB_OHCI || 2166801846d1SGavin Shan dev->class == PCI_CLASS_SERIAL_USB_EHCI) 2167801846d1SGavin Shan *weight += 3; 2168801846d1SGavin Shan else if ((dev->class >> 8) == PCI_CLASS_STORAGE_RAID) 2169801846d1SGavin Shan *weight += 15; 2170801846d1SGavin Shan else 2171801846d1SGavin Shan *weight += 10; 2172801846d1SGavin Shan 2173801846d1SGavin Shan return 0; 2174801846d1SGavin Shan } 2175801846d1SGavin Shan 2176801846d1SGavin Shan static unsigned int pnv_pci_ioda_pe_dma_weight(struct pnv_ioda_pe *pe) 2177801846d1SGavin Shan { 2178801846d1SGavin Shan unsigned int weight = 0; 2179801846d1SGavin Shan 2180801846d1SGavin Shan /* SRIOV VF has same DMA32 weight as its PF */ 2181801846d1SGavin Shan #ifdef CONFIG_PCI_IOV 2182801846d1SGavin Shan if ((pe->flags & PNV_IODA_PE_VF) && pe->parent_dev) { 2183801846d1SGavin Shan pnv_pci_ioda_dev_dma_weight(pe->parent_dev, &weight); 2184801846d1SGavin Shan return weight; 2185801846d1SGavin Shan } 2186801846d1SGavin Shan #endif 2187801846d1SGavin Shan 2188801846d1SGavin Shan if ((pe->flags & PNV_IODA_PE_DEV) && pe->pdev) { 2189801846d1SGavin Shan pnv_pci_ioda_dev_dma_weight(pe->pdev, &weight); 2190801846d1SGavin Shan } else if ((pe->flags & PNV_IODA_PE_BUS) && pe->pbus) { 2191801846d1SGavin Shan struct pci_dev *pdev; 2192801846d1SGavin Shan 2193801846d1SGavin Shan list_for_each_entry(pdev, &pe->pbus->devices, bus_list) 2194801846d1SGavin Shan pnv_pci_ioda_dev_dma_weight(pdev, &weight); 2195801846d1SGavin Shan } else if ((pe->flags & PNV_IODA_PE_BUS_ALL) && pe->pbus) { 2196801846d1SGavin Shan pci_walk_bus(pe->pbus, pnv_pci_ioda_dev_dma_weight, &weight); 2197801846d1SGavin Shan } 2198801846d1SGavin Shan 2199801846d1SGavin Shan return weight; 2200801846d1SGavin Shan } 2201801846d1SGavin Shan 2202b30d936fSGavin Shan static void pnv_pci_ioda1_setup_dma_pe(struct pnv_phb *phb, 22032b923ed1SGavin Shan struct pnv_ioda_pe *pe) 2204184cd4a3SBenjamin Herrenschmidt { 2205184cd4a3SBenjamin Herrenschmidt 2206184cd4a3SBenjamin Herrenschmidt struct page *tce_mem = NULL; 2207184cd4a3SBenjamin Herrenschmidt struct iommu_table *tbl; 22082b923ed1SGavin Shan unsigned int weight, total_weight = 0; 22092b923ed1SGavin Shan unsigned int tce32_segsz, base, segs, avail, i; 2210184cd4a3SBenjamin Herrenschmidt int64_t rc; 2211184cd4a3SBenjamin Herrenschmidt void *addr; 2212184cd4a3SBenjamin Herrenschmidt 2213184cd4a3SBenjamin Herrenschmidt /* XXX FIXME: Handle 64-bit only DMA devices */ 2214184cd4a3SBenjamin Herrenschmidt /* XXX FIXME: Provide 64-bit DMA facilities & non-4K TCE tables etc.. */ 2215184cd4a3SBenjamin Herrenschmidt /* XXX FIXME: Allocate multi-level tables on PHB3 */ 22162b923ed1SGavin Shan weight = pnv_pci_ioda_pe_dma_weight(pe); 22172b923ed1SGavin Shan if (!weight) 22182b923ed1SGavin Shan return; 2219184cd4a3SBenjamin Herrenschmidt 22202b923ed1SGavin Shan pci_walk_bus(phb->hose->bus, pnv_pci_ioda_dev_dma_weight, 22212b923ed1SGavin Shan &total_weight); 22222b923ed1SGavin Shan segs = (weight * phb->ioda.dma32_count) / total_weight; 22232b923ed1SGavin Shan if (!segs) 22242b923ed1SGavin Shan segs = 1; 22252b923ed1SGavin Shan 22262b923ed1SGavin Shan /* 22272b923ed1SGavin Shan * Allocate contiguous DMA32 segments. We begin with the expected 22282b923ed1SGavin Shan * number of segments. With one more attempt, the number of DMA32 22292b923ed1SGavin Shan * segments to be allocated is decreased by one until one segment 22302b923ed1SGavin Shan * is allocated successfully. 22312b923ed1SGavin Shan */ 22322b923ed1SGavin Shan do { 22332b923ed1SGavin Shan for (base = 0; base <= phb->ioda.dma32_count - segs; base++) { 22342b923ed1SGavin Shan for (avail = 0, i = base; i < base + segs; i++) { 22352b923ed1SGavin Shan if (phb->ioda.dma32_segmap[i] == 22362b923ed1SGavin Shan IODA_INVALID_PE) 22372b923ed1SGavin Shan avail++; 22382b923ed1SGavin Shan } 22392b923ed1SGavin Shan 22402b923ed1SGavin Shan if (avail == segs) 22412b923ed1SGavin Shan goto found; 22422b923ed1SGavin Shan } 22432b923ed1SGavin Shan } while (--segs); 22442b923ed1SGavin Shan 22452b923ed1SGavin Shan if (!segs) { 22462b923ed1SGavin Shan pe_warn(pe, "No available DMA32 segments\n"); 22472b923ed1SGavin Shan return; 22482b923ed1SGavin Shan } 22492b923ed1SGavin Shan 22502b923ed1SGavin Shan found: 22510eaf4defSAlexey Kardashevskiy tbl = pnv_pci_table_alloc(phb->hose->node); 225282eae1afSAlexey Kardashevskiy if (WARN_ON(!tbl)) 225382eae1afSAlexey Kardashevskiy return; 225482eae1afSAlexey Kardashevskiy 2255b348aa65SAlexey Kardashevskiy iommu_register_group(&pe->table_group, phb->hose->global_number, 2256b348aa65SAlexey Kardashevskiy pe->pe_number); 22570eaf4defSAlexey Kardashevskiy pnv_pci_link_table_and_group(phb->hose->node, 0, tbl, &pe->table_group); 2258c5773822SAlexey Kardashevskiy 2259184cd4a3SBenjamin Herrenschmidt /* Grab a 32-bit TCE table */ 22602b923ed1SGavin Shan pe_info(pe, "DMA weight %d (%d), assigned (%d) %d DMA32 segments\n", 22612b923ed1SGavin Shan weight, total_weight, base, segs); 2262184cd4a3SBenjamin Herrenschmidt pe_info(pe, " Setting up 32-bit TCE table at %08x..%08x\n", 2263acce971cSGavin Shan base * PNV_IODA1_DMA32_SEGSIZE, 2264acce971cSGavin Shan (base + segs) * PNV_IODA1_DMA32_SEGSIZE - 1); 2265184cd4a3SBenjamin Herrenschmidt 2266184cd4a3SBenjamin Herrenschmidt /* XXX Currently, we allocate one big contiguous table for the 2267184cd4a3SBenjamin Herrenschmidt * TCEs. We only really need one chunk per 256M of TCE space 2268184cd4a3SBenjamin Herrenschmidt * (ie per segment) but that's an optimization for later, it 2269184cd4a3SBenjamin Herrenschmidt * requires some added smarts with our get/put_tce implementation 2270acce971cSGavin Shan * 2271acce971cSGavin Shan * Each TCE page is 4KB in size and each TCE entry occupies 8 2272acce971cSGavin Shan * bytes 2273184cd4a3SBenjamin Herrenschmidt */ 2274acce971cSGavin Shan tce32_segsz = PNV_IODA1_DMA32_SEGSIZE >> (IOMMU_PAGE_SHIFT_4K - 3); 2275184cd4a3SBenjamin Herrenschmidt tce_mem = alloc_pages_node(phb->hose->node, GFP_KERNEL, 2276acce971cSGavin Shan get_order(tce32_segsz * segs)); 2277184cd4a3SBenjamin Herrenschmidt if (!tce_mem) { 2278184cd4a3SBenjamin Herrenschmidt pe_err(pe, " Failed to allocate a 32-bit TCE memory\n"); 2279184cd4a3SBenjamin Herrenschmidt goto fail; 2280184cd4a3SBenjamin Herrenschmidt } 2281184cd4a3SBenjamin Herrenschmidt addr = page_address(tce_mem); 2282acce971cSGavin Shan memset(addr, 0, tce32_segsz * segs); 2283184cd4a3SBenjamin Herrenschmidt 2284184cd4a3SBenjamin Herrenschmidt /* Configure HW */ 2285184cd4a3SBenjamin Herrenschmidt for (i = 0; i < segs; i++) { 2286184cd4a3SBenjamin Herrenschmidt rc = opal_pci_map_pe_dma_window(phb->opal_id, 2287184cd4a3SBenjamin Herrenschmidt pe->pe_number, 2288184cd4a3SBenjamin Herrenschmidt base + i, 1, 2289acce971cSGavin Shan __pa(addr) + tce32_segsz * i, 2290acce971cSGavin Shan tce32_segsz, IOMMU_PAGE_SIZE_4K); 2291184cd4a3SBenjamin Herrenschmidt if (rc) { 22921e496391SJoe Perches pe_err(pe, " Failed to configure 32-bit TCE table, err %lld\n", 22931e496391SJoe Perches rc); 2294184cd4a3SBenjamin Herrenschmidt goto fail; 2295184cd4a3SBenjamin Herrenschmidt } 2296184cd4a3SBenjamin Herrenschmidt } 2297184cd4a3SBenjamin Herrenschmidt 22982b923ed1SGavin Shan /* Setup DMA32 segment mapping */ 22992b923ed1SGavin Shan for (i = base; i < base + segs; i++) 23002b923ed1SGavin Shan phb->ioda.dma32_segmap[i] = pe->pe_number; 23012b923ed1SGavin Shan 2302184cd4a3SBenjamin Herrenschmidt /* Setup linux iommu table */ 2303acce971cSGavin Shan pnv_pci_setup_iommu_table(tbl, addr, tce32_segsz * segs, 2304acce971cSGavin Shan base * PNV_IODA1_DMA32_SEGSIZE, 2305acce971cSGavin Shan IOMMU_PAGE_SHIFT_4K); 2306184cd4a3SBenjamin Herrenschmidt 2307da004c36SAlexey Kardashevskiy tbl->it_ops = &pnv_ioda1_iommu_ops; 23084793d65dSAlexey Kardashevskiy pe->table_group.tce32_start = tbl->it_offset << tbl->it_page_shift; 23094793d65dSAlexey Kardashevskiy pe->table_group.tce32_size = tbl->it_size << tbl->it_page_shift; 2310184cd4a3SBenjamin Herrenschmidt iommu_init_table(tbl, phb->hose->node); 2311184cd4a3SBenjamin Herrenschmidt 2312f21b0a45SAlexey Kardashevskiy if (pe->flags & (PNV_IODA_PE_BUS | PNV_IODA_PE_BUS_ALL)) 23135eada8a3SAlexey Kardashevskiy pnv_ioda_setup_bus_dma(pe, pe->pbus); 231474251fe2SBenjamin Herrenschmidt 2315184cd4a3SBenjamin Herrenschmidt return; 2316184cd4a3SBenjamin Herrenschmidt fail: 2317184cd4a3SBenjamin Herrenschmidt /* XXX Failure: Try to fallback to 64-bit only ? */ 2318184cd4a3SBenjamin Herrenschmidt if (tce_mem) 2319acce971cSGavin Shan __free_pages(tce_mem, get_order(tce32_segsz * segs)); 23200eaf4defSAlexey Kardashevskiy if (tbl) { 23210eaf4defSAlexey Kardashevskiy pnv_pci_unlink_table_and_group(tbl, &pe->table_group); 2322e5afdf9dSAlexey Kardashevskiy iommu_tce_table_put(tbl); 23230eaf4defSAlexey Kardashevskiy } 2324184cd4a3SBenjamin Herrenschmidt } 2325184cd4a3SBenjamin Herrenschmidt 232643cb60abSAlexey Kardashevskiy static long pnv_pci_ioda2_set_window(struct iommu_table_group *table_group, 232743cb60abSAlexey Kardashevskiy int num, struct iommu_table *tbl) 232843cb60abSAlexey Kardashevskiy { 232943cb60abSAlexey Kardashevskiy struct pnv_ioda_pe *pe = container_of(table_group, struct pnv_ioda_pe, 233043cb60abSAlexey Kardashevskiy table_group); 233143cb60abSAlexey Kardashevskiy struct pnv_phb *phb = pe->phb; 233243cb60abSAlexey Kardashevskiy int64_t rc; 2333bbb845c4SAlexey Kardashevskiy const unsigned long size = tbl->it_indirect_levels ? 2334bbb845c4SAlexey Kardashevskiy tbl->it_level_size : tbl->it_size; 233543cb60abSAlexey Kardashevskiy const __u64 start_addr = tbl->it_offset << tbl->it_page_shift; 233643cb60abSAlexey Kardashevskiy const __u64 win_size = tbl->it_size << tbl->it_page_shift; 233743cb60abSAlexey Kardashevskiy 23381e496391SJoe Perches pe_info(pe, "Setting up window#%d %llx..%llx pg=%lx\n", 23391e496391SJoe Perches num, start_addr, start_addr + win_size - 1, 234043cb60abSAlexey Kardashevskiy IOMMU_PAGE_SIZE(tbl)); 234143cb60abSAlexey Kardashevskiy 234243cb60abSAlexey Kardashevskiy /* 234343cb60abSAlexey Kardashevskiy * Map TCE table through TVT. The TVE index is the PE number 234443cb60abSAlexey Kardashevskiy * shifted by 1 bit for 32-bits DMA space. 234543cb60abSAlexey Kardashevskiy */ 234643cb60abSAlexey Kardashevskiy rc = opal_pci_map_pe_dma_window(phb->opal_id, 234743cb60abSAlexey Kardashevskiy pe->pe_number, 23484793d65dSAlexey Kardashevskiy (pe->pe_number << 1) + num, 2349bbb845c4SAlexey Kardashevskiy tbl->it_indirect_levels + 1, 235043cb60abSAlexey Kardashevskiy __pa(tbl->it_base), 2351bbb845c4SAlexey Kardashevskiy size << 3, 235243cb60abSAlexey Kardashevskiy IOMMU_PAGE_SIZE(tbl)); 235343cb60abSAlexey Kardashevskiy if (rc) { 23541e496391SJoe Perches pe_err(pe, "Failed to configure TCE table, err %lld\n", rc); 235543cb60abSAlexey Kardashevskiy return rc; 235643cb60abSAlexey Kardashevskiy } 235743cb60abSAlexey Kardashevskiy 235843cb60abSAlexey Kardashevskiy pnv_pci_link_table_and_group(phb->hose->node, num, 235943cb60abSAlexey Kardashevskiy tbl, &pe->table_group); 2360ed7d9a1dSMichael Ellerman pnv_pci_ioda2_tce_invalidate_pe(pe); 236143cb60abSAlexey Kardashevskiy 236243cb60abSAlexey Kardashevskiy return 0; 236343cb60abSAlexey Kardashevskiy } 236443cb60abSAlexey Kardashevskiy 2365c498a4f9SChristoph Hellwig static void pnv_pci_ioda2_set_bypass(struct pnv_ioda_pe *pe, bool enable) 2366cd15b048SBenjamin Herrenschmidt { 2367cd15b048SBenjamin Herrenschmidt uint16_t window_id = (pe->pe_number << 1 ) + 1; 2368cd15b048SBenjamin Herrenschmidt int64_t rc; 2369cd15b048SBenjamin Herrenschmidt 2370cd15b048SBenjamin Herrenschmidt pe_info(pe, "%sabling 64-bit DMA bypass\n", enable ? "En" : "Dis"); 2371cd15b048SBenjamin Herrenschmidt if (enable) { 2372cd15b048SBenjamin Herrenschmidt phys_addr_t top = memblock_end_of_DRAM(); 2373cd15b048SBenjamin Herrenschmidt 2374cd15b048SBenjamin Herrenschmidt top = roundup_pow_of_two(top); 2375cd15b048SBenjamin Herrenschmidt rc = opal_pci_map_pe_dma_window_real(pe->phb->opal_id, 2376cd15b048SBenjamin Herrenschmidt pe->pe_number, 2377cd15b048SBenjamin Herrenschmidt window_id, 2378cd15b048SBenjamin Herrenschmidt pe->tce_bypass_base, 2379cd15b048SBenjamin Herrenschmidt top); 2380cd15b048SBenjamin Herrenschmidt } else { 2381cd15b048SBenjamin Herrenschmidt rc = opal_pci_map_pe_dma_window_real(pe->phb->opal_id, 2382cd15b048SBenjamin Herrenschmidt pe->pe_number, 2383cd15b048SBenjamin Herrenschmidt window_id, 2384cd15b048SBenjamin Herrenschmidt pe->tce_bypass_base, 2385cd15b048SBenjamin Herrenschmidt 0); 2386cd15b048SBenjamin Herrenschmidt } 2387cd15b048SBenjamin Herrenschmidt if (rc) 2388cd15b048SBenjamin Herrenschmidt pe_err(pe, "OPAL error %lld configuring bypass window\n", rc); 2389cd15b048SBenjamin Herrenschmidt else 2390cd15b048SBenjamin Herrenschmidt pe->tce_bypass_enabled = enable; 2391cd15b048SBenjamin Herrenschmidt } 2392cd15b048SBenjamin Herrenschmidt 23934793d65dSAlexey Kardashevskiy static long pnv_pci_ioda2_create_table(struct iommu_table_group *table_group, 23944793d65dSAlexey Kardashevskiy int num, __u32 page_shift, __u64 window_size, __u32 levels, 2395090bad39SAlexey Kardashevskiy bool alloc_userspace_copy, struct iommu_table **ptbl) 23964793d65dSAlexey Kardashevskiy { 23974793d65dSAlexey Kardashevskiy struct pnv_ioda_pe *pe = container_of(table_group, struct pnv_ioda_pe, 23984793d65dSAlexey Kardashevskiy table_group); 23994793d65dSAlexey Kardashevskiy int nid = pe->phb->hose->node; 24004793d65dSAlexey Kardashevskiy __u64 bus_offset = num ? pe->tce_bypass_base : table_group->tce32_start; 24014793d65dSAlexey Kardashevskiy long ret; 24024793d65dSAlexey Kardashevskiy struct iommu_table *tbl; 24034793d65dSAlexey Kardashevskiy 24044793d65dSAlexey Kardashevskiy tbl = pnv_pci_table_alloc(nid); 24054793d65dSAlexey Kardashevskiy if (!tbl) 24064793d65dSAlexey Kardashevskiy return -ENOMEM; 24074793d65dSAlexey Kardashevskiy 240811edf116SAlexey Kardashevskiy tbl->it_ops = &pnv_ioda2_iommu_ops; 240911edf116SAlexey Kardashevskiy 24104793d65dSAlexey Kardashevskiy ret = pnv_pci_ioda2_table_alloc_pages(nid, 24114793d65dSAlexey Kardashevskiy bus_offset, page_shift, window_size, 2412090bad39SAlexey Kardashevskiy levels, alloc_userspace_copy, tbl); 24134793d65dSAlexey Kardashevskiy if (ret) { 2414e5afdf9dSAlexey Kardashevskiy iommu_tce_table_put(tbl); 24154793d65dSAlexey Kardashevskiy return ret; 24164793d65dSAlexey Kardashevskiy } 24174793d65dSAlexey Kardashevskiy 24184793d65dSAlexey Kardashevskiy *ptbl = tbl; 24194793d65dSAlexey Kardashevskiy 24204793d65dSAlexey Kardashevskiy return 0; 24214793d65dSAlexey Kardashevskiy } 24224793d65dSAlexey Kardashevskiy 242346d3e1e1SAlexey Kardashevskiy static long pnv_pci_ioda2_setup_default_config(struct pnv_ioda_pe *pe) 242446d3e1e1SAlexey Kardashevskiy { 242546d3e1e1SAlexey Kardashevskiy struct iommu_table *tbl = NULL; 242646d3e1e1SAlexey Kardashevskiy long rc; 242746d3e1e1SAlexey Kardashevskiy 2428bb005455SNishanth Aravamudan /* 2429fa144869SNishanth Aravamudan * crashkernel= specifies the kdump kernel's maximum memory at 2430fa144869SNishanth Aravamudan * some offset and there is no guaranteed the result is a power 2431fa144869SNishanth Aravamudan * of 2, which will cause errors later. 2432fa144869SNishanth Aravamudan */ 2433fa144869SNishanth Aravamudan const u64 max_memory = __rounddown_pow_of_two(memory_hotplug_max()); 2434fa144869SNishanth Aravamudan 2435fa144869SNishanth Aravamudan /* 2436bb005455SNishanth Aravamudan * In memory constrained environments, e.g. kdump kernel, the 2437bb005455SNishanth Aravamudan * DMA window can be larger than available memory, which will 2438bb005455SNishanth Aravamudan * cause errors later. 2439bb005455SNishanth Aravamudan */ 2440fa144869SNishanth Aravamudan const u64 window_size = min((u64)pe->table_group.tce32_size, max_memory); 2441bb005455SNishanth Aravamudan 244246d3e1e1SAlexey Kardashevskiy rc = pnv_pci_ioda2_create_table(&pe->table_group, 0, 244346d3e1e1SAlexey Kardashevskiy IOMMU_PAGE_SHIFT_4K, 2444bb005455SNishanth Aravamudan window_size, 2445090bad39SAlexey Kardashevskiy POWERNV_IOMMU_DEFAULT_LEVELS, false, &tbl); 244646d3e1e1SAlexey Kardashevskiy if (rc) { 244746d3e1e1SAlexey Kardashevskiy pe_err(pe, "Failed to create 32-bit TCE table, err %ld", 244846d3e1e1SAlexey Kardashevskiy rc); 244946d3e1e1SAlexey Kardashevskiy return rc; 245046d3e1e1SAlexey Kardashevskiy } 245146d3e1e1SAlexey Kardashevskiy 245246d3e1e1SAlexey Kardashevskiy iommu_init_table(tbl, pe->phb->hose->node); 245346d3e1e1SAlexey Kardashevskiy 245446d3e1e1SAlexey Kardashevskiy rc = pnv_pci_ioda2_set_window(&pe->table_group, 0, tbl); 245546d3e1e1SAlexey Kardashevskiy if (rc) { 245646d3e1e1SAlexey Kardashevskiy pe_err(pe, "Failed to configure 32-bit TCE table, err %ld\n", 245746d3e1e1SAlexey Kardashevskiy rc); 2458e5afdf9dSAlexey Kardashevskiy iommu_tce_table_put(tbl); 245946d3e1e1SAlexey Kardashevskiy return rc; 246046d3e1e1SAlexey Kardashevskiy } 246146d3e1e1SAlexey Kardashevskiy 246246d3e1e1SAlexey Kardashevskiy if (!pnv_iommu_bypass_disabled) 246346d3e1e1SAlexey Kardashevskiy pnv_pci_ioda2_set_bypass(pe, true); 246446d3e1e1SAlexey Kardashevskiy 246546d3e1e1SAlexey Kardashevskiy return 0; 246646d3e1e1SAlexey Kardashevskiy } 246746d3e1e1SAlexey Kardashevskiy 2468b5926430SAlexey Kardashevskiy #if defined(CONFIG_IOMMU_API) || defined(CONFIG_PCI_IOV) 2469b5926430SAlexey Kardashevskiy static long pnv_pci_ioda2_unset_window(struct iommu_table_group *table_group, 2470b5926430SAlexey Kardashevskiy int num) 2471b5926430SAlexey Kardashevskiy { 2472b5926430SAlexey Kardashevskiy struct pnv_ioda_pe *pe = container_of(table_group, struct pnv_ioda_pe, 2473b5926430SAlexey Kardashevskiy table_group); 2474b5926430SAlexey Kardashevskiy struct pnv_phb *phb = pe->phb; 2475b5926430SAlexey Kardashevskiy long ret; 2476b5926430SAlexey Kardashevskiy 2477b5926430SAlexey Kardashevskiy pe_info(pe, "Removing DMA window #%d\n", num); 2478b5926430SAlexey Kardashevskiy 2479b5926430SAlexey Kardashevskiy ret = opal_pci_map_pe_dma_window(phb->opal_id, pe->pe_number, 2480b5926430SAlexey Kardashevskiy (pe->pe_number << 1) + num, 2481b5926430SAlexey Kardashevskiy 0/* levels */, 0/* table address */, 2482b5926430SAlexey Kardashevskiy 0/* table size */, 0/* page size */); 2483b5926430SAlexey Kardashevskiy if (ret) 2484b5926430SAlexey Kardashevskiy pe_warn(pe, "Unmapping failed, ret = %ld\n", ret); 2485b5926430SAlexey Kardashevskiy else 2486ed7d9a1dSMichael Ellerman pnv_pci_ioda2_tce_invalidate_pe(pe); 2487b5926430SAlexey Kardashevskiy 2488b5926430SAlexey Kardashevskiy pnv_pci_unlink_table_and_group(table_group->tables[num], table_group); 2489b5926430SAlexey Kardashevskiy 2490b5926430SAlexey Kardashevskiy return ret; 2491b5926430SAlexey Kardashevskiy } 2492b5926430SAlexey Kardashevskiy #endif 2493b5926430SAlexey Kardashevskiy 2494f87a8864SAlexey Kardashevskiy #ifdef CONFIG_IOMMU_API 24950bd97167SAlexey Kardashevskiy unsigned long pnv_pci_ioda2_get_table_size(__u32 page_shift, 249600547193SAlexey Kardashevskiy __u64 window_size, __u32 levels) 249700547193SAlexey Kardashevskiy { 249800547193SAlexey Kardashevskiy unsigned long bytes = 0; 249900547193SAlexey Kardashevskiy const unsigned window_shift = ilog2(window_size); 250000547193SAlexey Kardashevskiy unsigned entries_shift = window_shift - page_shift; 250100547193SAlexey Kardashevskiy unsigned table_shift = entries_shift + 3; 250200547193SAlexey Kardashevskiy unsigned long tce_table_size = max(0x1000UL, 1UL << table_shift); 250300547193SAlexey Kardashevskiy unsigned long direct_table_size; 250400547193SAlexey Kardashevskiy 250500547193SAlexey Kardashevskiy if (!levels || (levels > POWERNV_IOMMU_MAX_LEVELS) || 250600547193SAlexey Kardashevskiy !is_power_of_2(window_size)) 250700547193SAlexey Kardashevskiy return 0; 250800547193SAlexey Kardashevskiy 250900547193SAlexey Kardashevskiy /* Calculate a direct table size from window_size and levels */ 251000547193SAlexey Kardashevskiy entries_shift = (entries_shift + levels - 1) / levels; 251100547193SAlexey Kardashevskiy table_shift = entries_shift + 3; 251200547193SAlexey Kardashevskiy table_shift = max_t(unsigned, table_shift, PAGE_SHIFT); 251300547193SAlexey Kardashevskiy direct_table_size = 1UL << table_shift; 251400547193SAlexey Kardashevskiy 251500547193SAlexey Kardashevskiy for ( ; levels; --levels) { 251600547193SAlexey Kardashevskiy bytes += _ALIGN_UP(tce_table_size, direct_table_size); 251700547193SAlexey Kardashevskiy 251800547193SAlexey Kardashevskiy tce_table_size /= direct_table_size; 251900547193SAlexey Kardashevskiy tce_table_size <<= 3; 2520e49a6a21SAlexey Kardashevskiy tce_table_size = max_t(unsigned long, 2521e49a6a21SAlexey Kardashevskiy tce_table_size, direct_table_size); 252200547193SAlexey Kardashevskiy } 252300547193SAlexey Kardashevskiy 2524090bad39SAlexey Kardashevskiy return bytes + bytes; /* one for HW table, one for userspace copy */ 2525090bad39SAlexey Kardashevskiy } 2526090bad39SAlexey Kardashevskiy 2527090bad39SAlexey Kardashevskiy static long pnv_pci_ioda2_create_table_userspace( 2528090bad39SAlexey Kardashevskiy struct iommu_table_group *table_group, 2529090bad39SAlexey Kardashevskiy int num, __u32 page_shift, __u64 window_size, __u32 levels, 2530090bad39SAlexey Kardashevskiy struct iommu_table **ptbl) 2531090bad39SAlexey Kardashevskiy { 253211f5acceSAlexey Kardashevskiy long ret = pnv_pci_ioda2_create_table(table_group, 2533090bad39SAlexey Kardashevskiy num, page_shift, window_size, levels, true, ptbl); 253411f5acceSAlexey Kardashevskiy 253511f5acceSAlexey Kardashevskiy if (!ret) 253611f5acceSAlexey Kardashevskiy (*ptbl)->it_allocated_size = pnv_pci_ioda2_get_table_size( 253711f5acceSAlexey Kardashevskiy page_shift, window_size, levels); 253811f5acceSAlexey Kardashevskiy return ret; 253900547193SAlexey Kardashevskiy } 254000547193SAlexey Kardashevskiy 2541f87a8864SAlexey Kardashevskiy static void pnv_ioda2_take_ownership(struct iommu_table_group *table_group) 2542cd15b048SBenjamin Herrenschmidt { 2543f87a8864SAlexey Kardashevskiy struct pnv_ioda_pe *pe = container_of(table_group, struct pnv_ioda_pe, 2544f87a8864SAlexey Kardashevskiy table_group); 254546d3e1e1SAlexey Kardashevskiy /* Store @tbl as pnv_pci_ioda2_unset_window() resets it */ 254646d3e1e1SAlexey Kardashevskiy struct iommu_table *tbl = pe->table_group.tables[0]; 2547cd15b048SBenjamin Herrenschmidt 2548f87a8864SAlexey Kardashevskiy pnv_pci_ioda2_set_bypass(pe, false); 254946d3e1e1SAlexey Kardashevskiy pnv_pci_ioda2_unset_window(&pe->table_group, 0); 2550db08e1d5SAlexey Kardashevskiy if (pe->pbus) 25515eada8a3SAlexey Kardashevskiy pnv_ioda_setup_bus_dma(pe, pe->pbus); 2552e5afdf9dSAlexey Kardashevskiy iommu_tce_table_put(tbl); 2553cd15b048SBenjamin Herrenschmidt } 2554cd15b048SBenjamin Herrenschmidt 2555f87a8864SAlexey Kardashevskiy static void pnv_ioda2_release_ownership(struct iommu_table_group *table_group) 2556f87a8864SAlexey Kardashevskiy { 2557f87a8864SAlexey Kardashevskiy struct pnv_ioda_pe *pe = container_of(table_group, struct pnv_ioda_pe, 2558f87a8864SAlexey Kardashevskiy table_group); 2559f87a8864SAlexey Kardashevskiy 256046d3e1e1SAlexey Kardashevskiy pnv_pci_ioda2_setup_default_config(pe); 2561db08e1d5SAlexey Kardashevskiy if (pe->pbus) 25625eada8a3SAlexey Kardashevskiy pnv_ioda_setup_bus_dma(pe, pe->pbus); 2563f87a8864SAlexey Kardashevskiy } 2564f87a8864SAlexey Kardashevskiy 2565f87a8864SAlexey Kardashevskiy static struct iommu_table_group_ops pnv_pci_ioda2_ops = { 256600547193SAlexey Kardashevskiy .get_table_size = pnv_pci_ioda2_get_table_size, 2567090bad39SAlexey Kardashevskiy .create_table = pnv_pci_ioda2_create_table_userspace, 25684793d65dSAlexey Kardashevskiy .set_window = pnv_pci_ioda2_set_window, 25694793d65dSAlexey Kardashevskiy .unset_window = pnv_pci_ioda2_unset_window, 2570f87a8864SAlexey Kardashevskiy .take_ownership = pnv_ioda2_take_ownership, 2571f87a8864SAlexey Kardashevskiy .release_ownership = pnv_ioda2_release_ownership, 2572f87a8864SAlexey Kardashevskiy }; 2573b5cb9ab1SAlexey Kardashevskiy 25745eada8a3SAlexey Kardashevskiy static void pnv_ioda_setup_bus_iommu_group_add_devices(struct pnv_ioda_pe *pe, 25750bd97167SAlexey Kardashevskiy struct iommu_table_group *table_group, 25765eada8a3SAlexey Kardashevskiy struct pci_bus *bus) 25775eada8a3SAlexey Kardashevskiy { 25785eada8a3SAlexey Kardashevskiy struct pci_dev *dev; 25795eada8a3SAlexey Kardashevskiy 25805eada8a3SAlexey Kardashevskiy list_for_each_entry(dev, &bus->devices, bus_list) { 25810bd97167SAlexey Kardashevskiy iommu_add_device(table_group, &dev->dev); 25825eada8a3SAlexey Kardashevskiy 25835eada8a3SAlexey Kardashevskiy if ((pe->flags & PNV_IODA_PE_BUS_ALL) && dev->subordinate) 25845eada8a3SAlexey Kardashevskiy pnv_ioda_setup_bus_iommu_group_add_devices(pe, 25850bd97167SAlexey Kardashevskiy table_group, dev->subordinate); 25865eada8a3SAlexey Kardashevskiy } 25875eada8a3SAlexey Kardashevskiy } 25885eada8a3SAlexey Kardashevskiy 25890bd97167SAlexey Kardashevskiy static void pnv_ioda_setup_bus_iommu_group(struct pnv_ioda_pe *pe, 25900bd97167SAlexey Kardashevskiy struct iommu_table_group *table_group, struct pci_bus *bus) 25915eada8a3SAlexey Kardashevskiy { 25925eada8a3SAlexey Kardashevskiy 25935eada8a3SAlexey Kardashevskiy if (pe->flags & PNV_IODA_PE_DEV) 25940bd97167SAlexey Kardashevskiy iommu_add_device(table_group, &pe->pdev->dev); 25950bd97167SAlexey Kardashevskiy 25960bd97167SAlexey Kardashevskiy if ((pe->flags & (PNV_IODA_PE_BUS | PNV_IODA_PE_BUS_ALL)) || bus) 25970bd97167SAlexey Kardashevskiy pnv_ioda_setup_bus_iommu_group_add_devices(pe, table_group, 25980bd97167SAlexey Kardashevskiy bus); 25995eada8a3SAlexey Kardashevskiy } 26005eada8a3SAlexey Kardashevskiy 26010bd97167SAlexey Kardashevskiy static unsigned long pnv_ioda_parse_tce_sizes(struct pnv_phb *phb); 26020bd97167SAlexey Kardashevskiy 2603b5cb9ab1SAlexey Kardashevskiy static void pnv_pci_ioda_setup_iommu_api(void) 2604b5cb9ab1SAlexey Kardashevskiy { 26050bd97167SAlexey Kardashevskiy struct pci_controller *hose; 2606b5cb9ab1SAlexey Kardashevskiy struct pnv_phb *phb; 26070bd97167SAlexey Kardashevskiy struct pnv_ioda_pe *pe; 2608b5cb9ab1SAlexey Kardashevskiy 2609b5cb9ab1SAlexey Kardashevskiy /* 26105eada8a3SAlexey Kardashevskiy * There are 4 types of PEs: 26115eada8a3SAlexey Kardashevskiy * - PNV_IODA_PE_BUS: a downstream port with an adapter, 26125eada8a3SAlexey Kardashevskiy * created from pnv_pci_setup_bridge(); 26135eada8a3SAlexey Kardashevskiy * - PNV_IODA_PE_BUS_ALL: a PCI-PCIX bridge with devices behind it, 26145eada8a3SAlexey Kardashevskiy * created from pnv_pci_setup_bridge(); 26155eada8a3SAlexey Kardashevskiy * - PNV_IODA_PE_VF: a SRIOV virtual function, 26165eada8a3SAlexey Kardashevskiy * created from pnv_pcibios_sriov_enable(); 26175eada8a3SAlexey Kardashevskiy * - PNV_IODA_PE_DEV: an NPU or OCAPI device, 26185eada8a3SAlexey Kardashevskiy * created from pnv_pci_ioda_fixup(). 26195eada8a3SAlexey Kardashevskiy * 26205eada8a3SAlexey Kardashevskiy * Normally a PE is represented by an IOMMU group, however for 26215eada8a3SAlexey Kardashevskiy * devices with side channels the groups need to be more strict. 26225eada8a3SAlexey Kardashevskiy */ 26235eada8a3SAlexey Kardashevskiy list_for_each_entry(hose, &hose_list, list_node) { 26245eada8a3SAlexey Kardashevskiy phb = hose->private_data; 26255eada8a3SAlexey Kardashevskiy 26266bca5159SFrederic Barrat if (phb->type == PNV_PHB_NPU_NVLINK || 26276bca5159SFrederic Barrat phb->type == PNV_PHB_NPU_OCAPI) 26285eada8a3SAlexey Kardashevskiy continue; 26295eada8a3SAlexey Kardashevskiy 26300bd97167SAlexey Kardashevskiy list_for_each_entry(pe, &phb->ioda.pe_list, list) { 26310bd97167SAlexey Kardashevskiy struct iommu_table_group *table_group; 26320bd97167SAlexey Kardashevskiy 26330bd97167SAlexey Kardashevskiy table_group = pnv_try_setup_npu_table_group(pe); 26340bd97167SAlexey Kardashevskiy if (!table_group) { 26350bd97167SAlexey Kardashevskiy if (!pnv_pci_ioda_pe_dma_weight(pe)) 26360bd97167SAlexey Kardashevskiy continue; 26370bd97167SAlexey Kardashevskiy 26380bd97167SAlexey Kardashevskiy table_group = &pe->table_group; 26390bd97167SAlexey Kardashevskiy iommu_register_group(&pe->table_group, 26400bd97167SAlexey Kardashevskiy pe->phb->hose->global_number, 26410bd97167SAlexey Kardashevskiy pe->pe_number); 26420bd97167SAlexey Kardashevskiy } 26430bd97167SAlexey Kardashevskiy pnv_ioda_setup_bus_iommu_group(pe, table_group, 26440bd97167SAlexey Kardashevskiy pe->pbus); 26450bd97167SAlexey Kardashevskiy } 26465eada8a3SAlexey Kardashevskiy } 26475eada8a3SAlexey Kardashevskiy 26485eada8a3SAlexey Kardashevskiy /* 2649b5cb9ab1SAlexey Kardashevskiy * Now we have all PHBs discovered, time to add NPU devices to 2650b5cb9ab1SAlexey Kardashevskiy * the corresponding IOMMU groups. 2651b5cb9ab1SAlexey Kardashevskiy */ 26520bd97167SAlexey Kardashevskiy list_for_each_entry(hose, &hose_list, list_node) { 26530bd97167SAlexey Kardashevskiy unsigned long pgsizes; 26540bd97167SAlexey Kardashevskiy 2655b5cb9ab1SAlexey Kardashevskiy phb = hose->private_data; 2656b5cb9ab1SAlexey Kardashevskiy 26577f2c39e9SFrederic Barrat if (phb->type != PNV_PHB_NPU_NVLINK) 2658b5cb9ab1SAlexey Kardashevskiy continue; 2659b5cb9ab1SAlexey Kardashevskiy 26600bd97167SAlexey Kardashevskiy pgsizes = pnv_ioda_parse_tce_sizes(phb); 2661b5cb9ab1SAlexey Kardashevskiy list_for_each_entry(pe, &phb->ioda.pe_list, list) { 26620bd97167SAlexey Kardashevskiy /* 26630bd97167SAlexey Kardashevskiy * IODA2 bridges get this set up from 26640bd97167SAlexey Kardashevskiy * pci_controller_ops::setup_bridge but NPU bridges 26650bd97167SAlexey Kardashevskiy * do not have this hook defined so we do it here. 26660bd97167SAlexey Kardashevskiy */ 26670bd97167SAlexey Kardashevskiy pe->table_group.pgsizes = pgsizes; 26680bd97167SAlexey Kardashevskiy pnv_npu_compound_attach(pe); 2669b5cb9ab1SAlexey Kardashevskiy } 2670b5cb9ab1SAlexey Kardashevskiy } 2671b5cb9ab1SAlexey Kardashevskiy } 2672b5cb9ab1SAlexey Kardashevskiy #else /* !CONFIG_IOMMU_API */ 2673b5cb9ab1SAlexey Kardashevskiy static void pnv_pci_ioda_setup_iommu_api(void) { }; 2674f87a8864SAlexey Kardashevskiy #endif 2675f87a8864SAlexey Kardashevskiy 26767ef73cd3SAlexey Kardashevskiy static unsigned long pnv_ioda_parse_tce_sizes(struct pnv_phb *phb) 26777ef73cd3SAlexey Kardashevskiy { 26787ef73cd3SAlexey Kardashevskiy struct pci_controller *hose = phb->hose; 26797ef73cd3SAlexey Kardashevskiy struct device_node *dn = hose->dn; 26807ef73cd3SAlexey Kardashevskiy unsigned long mask = 0; 26817ef73cd3SAlexey Kardashevskiy int i, rc, count; 26827ef73cd3SAlexey Kardashevskiy u32 val; 26837ef73cd3SAlexey Kardashevskiy 26847ef73cd3SAlexey Kardashevskiy count = of_property_count_u32_elems(dn, "ibm,supported-tce-sizes"); 26857ef73cd3SAlexey Kardashevskiy if (count <= 0) { 26867ef73cd3SAlexey Kardashevskiy mask = SZ_4K | SZ_64K; 26877ef73cd3SAlexey Kardashevskiy /* Add 16M for POWER8 by default */ 26887ef73cd3SAlexey Kardashevskiy if (cpu_has_feature(CPU_FTR_ARCH_207S) && 26897ef73cd3SAlexey Kardashevskiy !cpu_has_feature(CPU_FTR_ARCH_300)) 269000c376fdSAlexey Kardashevskiy mask |= SZ_16M | SZ_256M; 26917ef73cd3SAlexey Kardashevskiy return mask; 26927ef73cd3SAlexey Kardashevskiy } 26937ef73cd3SAlexey Kardashevskiy 26947ef73cd3SAlexey Kardashevskiy for (i = 0; i < count; i++) { 26957ef73cd3SAlexey Kardashevskiy rc = of_property_read_u32_index(dn, "ibm,supported-tce-sizes", 26967ef73cd3SAlexey Kardashevskiy i, &val); 26977ef73cd3SAlexey Kardashevskiy if (rc == 0) 26987ef73cd3SAlexey Kardashevskiy mask |= 1ULL << val; 26997ef73cd3SAlexey Kardashevskiy } 27007ef73cd3SAlexey Kardashevskiy 27017ef73cd3SAlexey Kardashevskiy return mask; 27027ef73cd3SAlexey Kardashevskiy } 27037ef73cd3SAlexey Kardashevskiy 2704373f5657SGavin Shan static void pnv_pci_ioda2_setup_dma_pe(struct pnv_phb *phb, 2705373f5657SGavin Shan struct pnv_ioda_pe *pe) 2706373f5657SGavin Shan { 2707373f5657SGavin Shan int64_t rc; 2708373f5657SGavin Shan 2709ccd1c191SGavin Shan if (!pnv_pci_ioda_pe_dma_weight(pe)) 2710ccd1c191SGavin Shan return; 2711ccd1c191SGavin Shan 2712f87a8864SAlexey Kardashevskiy /* TVE #1 is selected by PCI address bit 59 */ 2713f87a8864SAlexey Kardashevskiy pe->tce_bypass_base = 1ull << 59; 2714f87a8864SAlexey Kardashevskiy 2715373f5657SGavin Shan /* The PE will reserve all possible 32-bits space */ 2716373f5657SGavin Shan pe_info(pe, "Setting up 32-bit TCE table at 0..%08x\n", 2717aca6913fSAlexey Kardashevskiy phb->ioda.m32_pci_base); 2718373f5657SGavin Shan 2719e5aad1e6SAlexey Kardashevskiy /* Setup linux iommu table */ 27204793d65dSAlexey Kardashevskiy pe->table_group.tce32_start = 0; 27214793d65dSAlexey Kardashevskiy pe->table_group.tce32_size = phb->ioda.m32_pci_base; 27224793d65dSAlexey Kardashevskiy pe->table_group.max_dynamic_windows_supported = 27234793d65dSAlexey Kardashevskiy IOMMU_TABLE_GROUP_MAX_TABLES; 27244793d65dSAlexey Kardashevskiy pe->table_group.max_levels = POWERNV_IOMMU_MAX_LEVELS; 27257ef73cd3SAlexey Kardashevskiy pe->table_group.pgsizes = pnv_ioda_parse_tce_sizes(phb); 2726e5aad1e6SAlexey Kardashevskiy #ifdef CONFIG_IOMMU_API 2727e5aad1e6SAlexey Kardashevskiy pe->table_group.ops = &pnv_pci_ioda2_ops; 2728e5aad1e6SAlexey Kardashevskiy #endif 2729e5aad1e6SAlexey Kardashevskiy 273046d3e1e1SAlexey Kardashevskiy rc = pnv_pci_ioda2_setup_default_config(pe); 2731801846d1SGavin Shan if (rc) 273246d3e1e1SAlexey Kardashevskiy return; 273346d3e1e1SAlexey Kardashevskiy 273420f13b95SAlexey Kardashevskiy if (pe->flags & (PNV_IODA_PE_BUS | PNV_IODA_PE_BUS_ALL)) 27355eada8a3SAlexey Kardashevskiy pnv_ioda_setup_bus_dma(pe, pe->pbus); 2736373f5657SGavin Shan } 2737373f5657SGavin Shan 27384ee11c1aSSuresh Warrier int64_t pnv_opal_pci_msi_eoi(struct irq_chip *chip, unsigned int hw_irq) 2739137436c9SGavin Shan { 2740137436c9SGavin Shan struct pnv_phb *phb = container_of(chip, struct pnv_phb, 2741137436c9SGavin Shan ioda.irq_chip); 2742137436c9SGavin Shan 27434ee11c1aSSuresh Warrier return opal_pci_msi_eoi(phb->opal_id, hw_irq); 27444ee11c1aSSuresh Warrier } 27454ee11c1aSSuresh Warrier 27464ee11c1aSSuresh Warrier static void pnv_ioda2_msi_eoi(struct irq_data *d) 27474ee11c1aSSuresh Warrier { 27484ee11c1aSSuresh Warrier int64_t rc; 27494ee11c1aSSuresh Warrier unsigned int hw_irq = (unsigned int)irqd_to_hwirq(d); 27504ee11c1aSSuresh Warrier struct irq_chip *chip = irq_data_get_irq_chip(d); 27514ee11c1aSSuresh Warrier 27524ee11c1aSSuresh Warrier rc = pnv_opal_pci_msi_eoi(chip, hw_irq); 2753137436c9SGavin Shan WARN_ON_ONCE(rc); 2754137436c9SGavin Shan 2755137436c9SGavin Shan icp_native_eoi(d); 2756137436c9SGavin Shan } 2757137436c9SGavin Shan 2758fd9a1c26SIan Munsie 2759f456834aSIan Munsie void pnv_set_msi_irq_chip(struct pnv_phb *phb, unsigned int virq) 2760fd9a1c26SIan Munsie { 2761fd9a1c26SIan Munsie struct irq_data *idata; 2762fd9a1c26SIan Munsie struct irq_chip *ichip; 2763fd9a1c26SIan Munsie 2764fb111334SBenjamin Herrenschmidt /* The MSI EOI OPAL call is only needed on PHB3 */ 2765fb111334SBenjamin Herrenschmidt if (phb->model != PNV_PHB_MODEL_PHB3) 2766fd9a1c26SIan Munsie return; 2767fd9a1c26SIan Munsie 2768fd9a1c26SIan Munsie if (!phb->ioda.irq_chip_init) { 2769fd9a1c26SIan Munsie /* 2770fd9a1c26SIan Munsie * First time we setup an MSI IRQ, we need to setup the 2771fd9a1c26SIan Munsie * corresponding IRQ chip to route correctly. 2772fd9a1c26SIan Munsie */ 2773fd9a1c26SIan Munsie idata = irq_get_irq_data(virq); 2774fd9a1c26SIan Munsie ichip = irq_data_get_irq_chip(idata); 2775fd9a1c26SIan Munsie phb->ioda.irq_chip_init = 1; 2776fd9a1c26SIan Munsie phb->ioda.irq_chip = *ichip; 2777fd9a1c26SIan Munsie phb->ioda.irq_chip.irq_eoi = pnv_ioda2_msi_eoi; 2778fd9a1c26SIan Munsie } 2779fd9a1c26SIan Munsie irq_set_chip(virq, &phb->ioda.irq_chip); 2780fd9a1c26SIan Munsie } 2781fd9a1c26SIan Munsie 27824ee11c1aSSuresh Warrier /* 27834ee11c1aSSuresh Warrier * Returns true iff chip is something that we could call 27844ee11c1aSSuresh Warrier * pnv_opal_pci_msi_eoi for. 27854ee11c1aSSuresh Warrier */ 27864ee11c1aSSuresh Warrier bool is_pnv_opal_msi(struct irq_chip *chip) 27874ee11c1aSSuresh Warrier { 27884ee11c1aSSuresh Warrier return chip->irq_eoi == pnv_ioda2_msi_eoi; 27894ee11c1aSSuresh Warrier } 27904ee11c1aSSuresh Warrier EXPORT_SYMBOL_GPL(is_pnv_opal_msi); 27914ee11c1aSSuresh Warrier 2792184cd4a3SBenjamin Herrenschmidt static int pnv_pci_ioda_msi_setup(struct pnv_phb *phb, struct pci_dev *dev, 2793137436c9SGavin Shan unsigned int hwirq, unsigned int virq, 2794137436c9SGavin Shan unsigned int is_64, struct msi_msg *msg) 2795184cd4a3SBenjamin Herrenschmidt { 2796184cd4a3SBenjamin Herrenschmidt struct pnv_ioda_pe *pe = pnv_ioda_get_pe(dev); 2797184cd4a3SBenjamin Herrenschmidt unsigned int xive_num = hwirq - phb->msi_base; 27983a1a4661SBenjamin Herrenschmidt __be32 data; 2799184cd4a3SBenjamin Herrenschmidt int rc; 2800184cd4a3SBenjamin Herrenschmidt 2801184cd4a3SBenjamin Herrenschmidt /* No PE assigned ? bail out ... no MSI for you ! */ 2802184cd4a3SBenjamin Herrenschmidt if (pe == NULL) 2803184cd4a3SBenjamin Herrenschmidt return -ENXIO; 2804184cd4a3SBenjamin Herrenschmidt 2805184cd4a3SBenjamin Herrenschmidt /* Check if we have an MVE */ 2806184cd4a3SBenjamin Herrenschmidt if (pe->mve_number < 0) 2807184cd4a3SBenjamin Herrenschmidt return -ENXIO; 2808184cd4a3SBenjamin Herrenschmidt 2809b72c1f65SBenjamin Herrenschmidt /* Force 32-bit MSI on some broken devices */ 281036074381SBenjamin Herrenschmidt if (dev->no_64bit_msi) 2811b72c1f65SBenjamin Herrenschmidt is_64 = 0; 2812b72c1f65SBenjamin Herrenschmidt 2813184cd4a3SBenjamin Herrenschmidt /* Assign XIVE to PE */ 2814184cd4a3SBenjamin Herrenschmidt rc = opal_pci_set_xive_pe(phb->opal_id, pe->pe_number, xive_num); 2815184cd4a3SBenjamin Herrenschmidt if (rc) { 2816184cd4a3SBenjamin Herrenschmidt pr_warn("%s: OPAL error %d setting XIVE %d PE\n", 2817184cd4a3SBenjamin Herrenschmidt pci_name(dev), rc, xive_num); 2818184cd4a3SBenjamin Herrenschmidt return -EIO; 2819184cd4a3SBenjamin Herrenschmidt } 2820184cd4a3SBenjamin Herrenschmidt 2821184cd4a3SBenjamin Herrenschmidt if (is_64) { 28223a1a4661SBenjamin Herrenschmidt __be64 addr64; 28233a1a4661SBenjamin Herrenschmidt 2824184cd4a3SBenjamin Herrenschmidt rc = opal_get_msi_64(phb->opal_id, pe->mve_number, xive_num, 1, 2825184cd4a3SBenjamin Herrenschmidt &addr64, &data); 2826184cd4a3SBenjamin Herrenschmidt if (rc) { 2827184cd4a3SBenjamin Herrenschmidt pr_warn("%s: OPAL error %d getting 64-bit MSI data\n", 2828184cd4a3SBenjamin Herrenschmidt pci_name(dev), rc); 2829184cd4a3SBenjamin Herrenschmidt return -EIO; 2830184cd4a3SBenjamin Herrenschmidt } 28313a1a4661SBenjamin Herrenschmidt msg->address_hi = be64_to_cpu(addr64) >> 32; 28323a1a4661SBenjamin Herrenschmidt msg->address_lo = be64_to_cpu(addr64) & 0xfffffffful; 2833184cd4a3SBenjamin Herrenschmidt } else { 28343a1a4661SBenjamin Herrenschmidt __be32 addr32; 28353a1a4661SBenjamin Herrenschmidt 2836184cd4a3SBenjamin Herrenschmidt rc = opal_get_msi_32(phb->opal_id, pe->mve_number, xive_num, 1, 2837184cd4a3SBenjamin Herrenschmidt &addr32, &data); 2838184cd4a3SBenjamin Herrenschmidt if (rc) { 2839184cd4a3SBenjamin Herrenschmidt pr_warn("%s: OPAL error %d getting 32-bit MSI data\n", 2840184cd4a3SBenjamin Herrenschmidt pci_name(dev), rc); 2841184cd4a3SBenjamin Herrenschmidt return -EIO; 2842184cd4a3SBenjamin Herrenschmidt } 2843184cd4a3SBenjamin Herrenschmidt msg->address_hi = 0; 28443a1a4661SBenjamin Herrenschmidt msg->address_lo = be32_to_cpu(addr32); 2845184cd4a3SBenjamin Herrenschmidt } 28463a1a4661SBenjamin Herrenschmidt msg->data = be32_to_cpu(data); 2847184cd4a3SBenjamin Herrenschmidt 2848f456834aSIan Munsie pnv_set_msi_irq_chip(phb, virq); 2849137436c9SGavin Shan 2850184cd4a3SBenjamin Herrenschmidt pr_devel("%s: %s-bit MSI on hwirq %x (xive #%d)," 28511f52f176SRussell Currey " address=%x_%08x data=%x PE# %x\n", 2852184cd4a3SBenjamin Herrenschmidt pci_name(dev), is_64 ? "64" : "32", hwirq, xive_num, 2853184cd4a3SBenjamin Herrenschmidt msg->address_hi, msg->address_lo, data, pe->pe_number); 2854184cd4a3SBenjamin Herrenschmidt 2855184cd4a3SBenjamin Herrenschmidt return 0; 2856184cd4a3SBenjamin Herrenschmidt } 2857184cd4a3SBenjamin Herrenschmidt 2858184cd4a3SBenjamin Herrenschmidt static void pnv_pci_init_ioda_msis(struct pnv_phb *phb) 2859184cd4a3SBenjamin Herrenschmidt { 2860fb1b55d6SGavin Shan unsigned int count; 2861184cd4a3SBenjamin Herrenschmidt const __be32 *prop = of_get_property(phb->hose->dn, 2862184cd4a3SBenjamin Herrenschmidt "ibm,opal-msi-ranges", NULL); 2863184cd4a3SBenjamin Herrenschmidt if (!prop) { 2864184cd4a3SBenjamin Herrenschmidt /* BML Fallback */ 2865184cd4a3SBenjamin Herrenschmidt prop = of_get_property(phb->hose->dn, "msi-ranges", NULL); 2866184cd4a3SBenjamin Herrenschmidt } 2867184cd4a3SBenjamin Herrenschmidt if (!prop) 2868184cd4a3SBenjamin Herrenschmidt return; 2869184cd4a3SBenjamin Herrenschmidt 2870184cd4a3SBenjamin Herrenschmidt phb->msi_base = be32_to_cpup(prop); 2871fb1b55d6SGavin Shan count = be32_to_cpup(prop + 1); 2872fb1b55d6SGavin Shan if (msi_bitmap_alloc(&phb->msi_bmp, count, phb->hose->dn)) { 2873184cd4a3SBenjamin Herrenschmidt pr_err("PCI %d: Failed to allocate MSI bitmap !\n", 2874184cd4a3SBenjamin Herrenschmidt phb->hose->global_number); 2875184cd4a3SBenjamin Herrenschmidt return; 2876184cd4a3SBenjamin Herrenschmidt } 2877fb1b55d6SGavin Shan 2878184cd4a3SBenjamin Herrenschmidt phb->msi_setup = pnv_pci_ioda_msi_setup; 2879184cd4a3SBenjamin Herrenschmidt phb->msi32_support = 1; 2880184cd4a3SBenjamin Herrenschmidt pr_info(" Allocated bitmap for %d MSIs (base IRQ 0x%x)\n", 2881fb1b55d6SGavin Shan count, phb->msi_base); 2882184cd4a3SBenjamin Herrenschmidt } 2883184cd4a3SBenjamin Herrenschmidt 28846e628c7dSWei Yang #ifdef CONFIG_PCI_IOV 28856e628c7dSWei Yang static void pnv_pci_ioda_fixup_iov_resources(struct pci_dev *pdev) 28866e628c7dSWei Yang { 2887f2dd0afeSWei Yang struct pci_controller *hose = pci_bus_to_host(pdev->bus); 2888f2dd0afeSWei Yang struct pnv_phb *phb = hose->private_data; 2889f2dd0afeSWei Yang const resource_size_t gate = phb->ioda.m64_segsize >> 2; 28906e628c7dSWei Yang struct resource *res; 28916e628c7dSWei Yang int i; 2892dfcc8d45SWei Yang resource_size_t size, total_vf_bar_sz; 28936e628c7dSWei Yang struct pci_dn *pdn; 28945b88ec22SWei Yang int mul, total_vfs; 28956e628c7dSWei Yang 289644bda4b7SHari Vyas if (!pdev->is_physfn || pci_dev_is_added(pdev)) 28976e628c7dSWei Yang return; 28986e628c7dSWei Yang 28996e628c7dSWei Yang pdn = pci_get_pdn(pdev); 29006e628c7dSWei Yang pdn->vfs_expanded = 0; 2901ee8222feSWei Yang pdn->m64_single_mode = false; 29026e628c7dSWei Yang 29035b88ec22SWei Yang total_vfs = pci_sriov_get_totalvfs(pdev); 290492b8f137SGavin Shan mul = phb->ioda.total_pe_num; 2905dfcc8d45SWei Yang total_vf_bar_sz = 0; 29065b88ec22SWei Yang 29075b88ec22SWei Yang for (i = 0; i < PCI_SRIOV_NUM_BARS; i++) { 29085b88ec22SWei Yang res = &pdev->resource[i + PCI_IOV_RESOURCES]; 29095b88ec22SWei Yang if (!res->flags || res->parent) 29105b88ec22SWei Yang continue; 2911b79331a5SRussell Currey if (!pnv_pci_is_m64_flags(res->flags)) { 2912b0331854SWei Yang dev_warn(&pdev->dev, "Don't support SR-IOV with" 2913b0331854SWei Yang " non M64 VF BAR%d: %pR. \n", 29145b88ec22SWei Yang i, res); 2915b0331854SWei Yang goto truncate_iov; 29165b88ec22SWei Yang } 29175b88ec22SWei Yang 2918dfcc8d45SWei Yang total_vf_bar_sz += pci_iov_resource_size(pdev, 2919dfcc8d45SWei Yang i + PCI_IOV_RESOURCES); 29205b88ec22SWei Yang 2921f2dd0afeSWei Yang /* 2922f2dd0afeSWei Yang * If bigger than quarter of M64 segment size, just round up 2923f2dd0afeSWei Yang * power of two. 2924f2dd0afeSWei Yang * 2925f2dd0afeSWei Yang * Generally, one M64 BAR maps one IOV BAR. To avoid conflict 2926f2dd0afeSWei Yang * with other devices, IOV BAR size is expanded to be 2927f2dd0afeSWei Yang * (total_pe * VF_BAR_size). When VF_BAR_size is half of M64 2928f2dd0afeSWei Yang * segment size , the expanded size would equal to half of the 2929f2dd0afeSWei Yang * whole M64 space size, which will exhaust the M64 Space and 2930f2dd0afeSWei Yang * limit the system flexibility. This is a design decision to 2931f2dd0afeSWei Yang * set the boundary to quarter of the M64 segment size. 2932f2dd0afeSWei Yang */ 2933dfcc8d45SWei Yang if (total_vf_bar_sz > gate) { 29345b88ec22SWei Yang mul = roundup_pow_of_two(total_vfs); 2935dfcc8d45SWei Yang dev_info(&pdev->dev, 2936dfcc8d45SWei Yang "VF BAR Total IOV size %llx > %llx, roundup to %d VFs\n", 2937dfcc8d45SWei Yang total_vf_bar_sz, gate, mul); 2938ee8222feSWei Yang pdn->m64_single_mode = true; 29395b88ec22SWei Yang break; 29405b88ec22SWei Yang } 29415b88ec22SWei Yang } 29425b88ec22SWei Yang 29436e628c7dSWei Yang for (i = 0; i < PCI_SRIOV_NUM_BARS; i++) { 29446e628c7dSWei Yang res = &pdev->resource[i + PCI_IOV_RESOURCES]; 29456e628c7dSWei Yang if (!res->flags || res->parent) 29466e628c7dSWei Yang continue; 29476e628c7dSWei Yang 29486e628c7dSWei Yang size = pci_iov_resource_size(pdev, i + PCI_IOV_RESOURCES); 2949ee8222feSWei Yang /* 2950ee8222feSWei Yang * On PHB3, the minimum size alignment of M64 BAR in single 2951ee8222feSWei Yang * mode is 32MB. 2952ee8222feSWei Yang */ 2953ee8222feSWei Yang if (pdn->m64_single_mode && (size < SZ_32M)) 2954ee8222feSWei Yang goto truncate_iov; 2955ee8222feSWei Yang dev_dbg(&pdev->dev, " Fixing VF BAR%d: %pR to\n", i, res); 29565b88ec22SWei Yang res->end = res->start + size * mul - 1; 29576e628c7dSWei Yang dev_dbg(&pdev->dev, " %pR\n", res); 29586e628c7dSWei Yang dev_info(&pdev->dev, "VF BAR%d: %pR (expanded to %d VFs for PE alignment)", 29595b88ec22SWei Yang i, res, mul); 29606e628c7dSWei Yang } 29615b88ec22SWei Yang pdn->vfs_expanded = mul; 2962b0331854SWei Yang 2963b0331854SWei Yang return; 2964b0331854SWei Yang 2965b0331854SWei Yang truncate_iov: 2966b0331854SWei Yang /* To save MMIO space, IOV BAR is truncated. */ 2967b0331854SWei Yang for (i = 0; i < PCI_SRIOV_NUM_BARS; i++) { 2968b0331854SWei Yang res = &pdev->resource[i + PCI_IOV_RESOURCES]; 2969b0331854SWei Yang res->flags = 0; 2970b0331854SWei Yang res->end = res->start - 1; 2971b0331854SWei Yang } 29726e628c7dSWei Yang } 29736e628c7dSWei Yang #endif /* CONFIG_PCI_IOV */ 29746e628c7dSWei Yang 297523e79425SGavin Shan static void pnv_ioda_setup_pe_res(struct pnv_ioda_pe *pe, 297623e79425SGavin Shan struct resource *res) 297711685becSGavin Shan { 297823e79425SGavin Shan struct pnv_phb *phb = pe->phb; 297911685becSGavin Shan struct pci_bus_region region; 298023e79425SGavin Shan int index; 298123e79425SGavin Shan int64_t rc; 298211685becSGavin Shan 298323e79425SGavin Shan if (!res || !res->flags || res->start > res->end) 298423e79425SGavin Shan return; 298511685becSGavin Shan 298611685becSGavin Shan if (res->flags & IORESOURCE_IO) { 298711685becSGavin Shan region.start = res->start - phb->ioda.io_pci_base; 298811685becSGavin Shan region.end = res->end - phb->ioda.io_pci_base; 298911685becSGavin Shan index = region.start / phb->ioda.io_segsize; 299011685becSGavin Shan 299192b8f137SGavin Shan while (index < phb->ioda.total_pe_num && 299211685becSGavin Shan region.start <= region.end) { 299311685becSGavin Shan phb->ioda.io_segmap[index] = pe->pe_number; 299411685becSGavin Shan rc = opal_pci_map_pe_mmio_window(phb->opal_id, 299511685becSGavin Shan pe->pe_number, OPAL_IO_WINDOW_TYPE, 0, index); 299611685becSGavin Shan if (rc != OPAL_SUCCESS) { 29971f52f176SRussell Currey pr_err("%s: Error %lld mapping IO segment#%d to PE#%x\n", 299811685becSGavin Shan __func__, rc, index, pe->pe_number); 299911685becSGavin Shan break; 300011685becSGavin Shan } 300111685becSGavin Shan 300211685becSGavin Shan region.start += phb->ioda.io_segsize; 300311685becSGavin Shan index++; 300411685becSGavin Shan } 3005027fa02fSGavin Shan } else if ((res->flags & IORESOURCE_MEM) && 30065958d19aSBenjamin Herrenschmidt !pnv_pci_is_m64(phb, res)) { 300711685becSGavin Shan region.start = res->start - 300823e79425SGavin Shan phb->hose->mem_offset[0] - 300911685becSGavin Shan phb->ioda.m32_pci_base; 301011685becSGavin Shan region.end = res->end - 301123e79425SGavin Shan phb->hose->mem_offset[0] - 301211685becSGavin Shan phb->ioda.m32_pci_base; 301311685becSGavin Shan index = region.start / phb->ioda.m32_segsize; 301411685becSGavin Shan 301592b8f137SGavin Shan while (index < phb->ioda.total_pe_num && 301611685becSGavin Shan region.start <= region.end) { 301711685becSGavin Shan phb->ioda.m32_segmap[index] = pe->pe_number; 301811685becSGavin Shan rc = opal_pci_map_pe_mmio_window(phb->opal_id, 301911685becSGavin Shan pe->pe_number, OPAL_M32_WINDOW_TYPE, 0, index); 302011685becSGavin Shan if (rc != OPAL_SUCCESS) { 30211f52f176SRussell Currey pr_err("%s: Error %lld mapping M32 segment#%d to PE#%x", 302211685becSGavin Shan __func__, rc, index, pe->pe_number); 302311685becSGavin Shan break; 302411685becSGavin Shan } 302511685becSGavin Shan 302611685becSGavin Shan region.start += phb->ioda.m32_segsize; 302711685becSGavin Shan index++; 302811685becSGavin Shan } 302911685becSGavin Shan } 303011685becSGavin Shan } 303123e79425SGavin Shan 303223e79425SGavin Shan /* 303323e79425SGavin Shan * This function is supposed to be called on basis of PE from top 303423e79425SGavin Shan * to bottom style. So the the I/O or MMIO segment assigned to 303503671057SMasahiro Yamada * parent PE could be overridden by its child PEs if necessary. 303623e79425SGavin Shan */ 303723e79425SGavin Shan static void pnv_ioda_setup_pe_seg(struct pnv_ioda_pe *pe) 303823e79425SGavin Shan { 303969d733e7SGavin Shan struct pci_dev *pdev; 304023e79425SGavin Shan int i; 304123e79425SGavin Shan 304223e79425SGavin Shan /* 304323e79425SGavin Shan * NOTE: We only care PCI bus based PE for now. For PCI 304423e79425SGavin Shan * device based PE, for example SRIOV sensitive VF should 304523e79425SGavin Shan * be figured out later. 304623e79425SGavin Shan */ 304723e79425SGavin Shan BUG_ON(!(pe->flags & (PNV_IODA_PE_BUS | PNV_IODA_PE_BUS_ALL))); 304823e79425SGavin Shan 304969d733e7SGavin Shan list_for_each_entry(pdev, &pe->pbus->devices, bus_list) { 305069d733e7SGavin Shan for (i = 0; i <= PCI_ROM_RESOURCE; i++) 305169d733e7SGavin Shan pnv_ioda_setup_pe_res(pe, &pdev->resource[i]); 305269d733e7SGavin Shan 305369d733e7SGavin Shan /* 305469d733e7SGavin Shan * If the PE contains all subordinate PCI buses, the 305569d733e7SGavin Shan * windows of the child bridges should be mapped to 305669d733e7SGavin Shan * the PE as well. 305769d733e7SGavin Shan */ 305869d733e7SGavin Shan if (!(pe->flags & PNV_IODA_PE_BUS_ALL) || !pci_is_bridge(pdev)) 305969d733e7SGavin Shan continue; 306069d733e7SGavin Shan for (i = 0; i < PCI_BRIDGE_RESOURCE_NUM; i++) 306169d733e7SGavin Shan pnv_ioda_setup_pe_res(pe, 306269d733e7SGavin Shan &pdev->resource[PCI_BRIDGE_RESOURCES + i]); 306369d733e7SGavin Shan } 306411685becSGavin Shan } 306511685becSGavin Shan 306698b665daSRussell Currey #ifdef CONFIG_DEBUG_FS 306798b665daSRussell Currey static int pnv_pci_diag_data_set(void *data, u64 val) 306898b665daSRussell Currey { 306998b665daSRussell Currey struct pci_controller *hose; 307098b665daSRussell Currey struct pnv_phb *phb; 307198b665daSRussell Currey s64 ret; 307298b665daSRussell Currey 307398b665daSRussell Currey if (val != 1ULL) 307498b665daSRussell Currey return -EINVAL; 307598b665daSRussell Currey 307698b665daSRussell Currey hose = (struct pci_controller *)data; 307798b665daSRussell Currey if (!hose || !hose->private_data) 307898b665daSRussell Currey return -ENODEV; 307998b665daSRussell Currey 308098b665daSRussell Currey phb = hose->private_data; 308198b665daSRussell Currey 308298b665daSRussell Currey /* Retrieve the diag data from firmware */ 30835cb1f8fdSRussell Currey ret = opal_pci_get_phb_diag_data2(phb->opal_id, phb->diag_data, 30845cb1f8fdSRussell Currey phb->diag_data_size); 308598b665daSRussell Currey if (ret != OPAL_SUCCESS) 308698b665daSRussell Currey return -EIO; 308798b665daSRussell Currey 308898b665daSRussell Currey /* Print the diag data to the kernel log */ 30895cb1f8fdSRussell Currey pnv_pci_dump_phb_diag_data(phb->hose, phb->diag_data); 309098b665daSRussell Currey return 0; 309198b665daSRussell Currey } 309298b665daSRussell Currey 309398b665daSRussell Currey DEFINE_SIMPLE_ATTRIBUTE(pnv_pci_diag_data_fops, NULL, 309498b665daSRussell Currey pnv_pci_diag_data_set, "%llu\n"); 309598b665daSRussell Currey 309698b665daSRussell Currey #endif /* CONFIG_DEBUG_FS */ 309798b665daSRussell Currey 309837c367f2SGavin Shan static void pnv_pci_ioda_create_dbgfs(void) 309937c367f2SGavin Shan { 310037c367f2SGavin Shan #ifdef CONFIG_DEBUG_FS 310137c367f2SGavin Shan struct pci_controller *hose, *tmp; 310237c367f2SGavin Shan struct pnv_phb *phb; 310337c367f2SGavin Shan char name[16]; 310437c367f2SGavin Shan 310537c367f2SGavin Shan list_for_each_entry_safe(hose, tmp, &hose_list, list_node) { 310637c367f2SGavin Shan phb = hose->private_data; 310737c367f2SGavin Shan 3108ccd1c191SGavin Shan /* Notify initialization of PHB done */ 3109ccd1c191SGavin Shan phb->initialized = 1; 3110ccd1c191SGavin Shan 311137c367f2SGavin Shan sprintf(name, "PCI%04x", hose->global_number); 311237c367f2SGavin Shan phb->dbgfs = debugfs_create_dir(name, powerpc_debugfs_root); 311398b665daSRussell Currey if (!phb->dbgfs) { 3114f2c2cbccSJoe Perches pr_warn("%s: Error on creating debugfs on PHB#%x\n", 311537c367f2SGavin Shan __func__, hose->global_number); 311698b665daSRussell Currey continue; 311798b665daSRussell Currey } 311898b665daSRussell Currey 311998b665daSRussell Currey debugfs_create_file("dump_diag_regs", 0200, phb->dbgfs, hose, 312098b665daSRussell Currey &pnv_pci_diag_data_fops); 312137c367f2SGavin Shan } 312237c367f2SGavin Shan #endif /* CONFIG_DEBUG_FS */ 312337c367f2SGavin Shan } 312437c367f2SGavin Shan 3125db217319SBenjamin Herrenschmidt static void pnv_pci_enable_bridge(struct pci_bus *bus) 3126db217319SBenjamin Herrenschmidt { 3127db217319SBenjamin Herrenschmidt struct pci_dev *dev = bus->self; 3128db217319SBenjamin Herrenschmidt struct pci_bus *child; 3129db217319SBenjamin Herrenschmidt 3130db217319SBenjamin Herrenschmidt /* Empty bus ? bail */ 3131db217319SBenjamin Herrenschmidt if (list_empty(&bus->devices)) 3132db217319SBenjamin Herrenschmidt return; 3133db217319SBenjamin Herrenschmidt 3134db217319SBenjamin Herrenschmidt /* 3135db217319SBenjamin Herrenschmidt * If there's a bridge associated with that bus enable it. This works 3136db217319SBenjamin Herrenschmidt * around races in the generic code if the enabling is done during 3137db217319SBenjamin Herrenschmidt * parallel probing. This can be removed once those races have been 3138db217319SBenjamin Herrenschmidt * fixed. 3139db217319SBenjamin Herrenschmidt */ 3140db217319SBenjamin Herrenschmidt if (dev) { 3141db217319SBenjamin Herrenschmidt int rc = pci_enable_device(dev); 3142db217319SBenjamin Herrenschmidt if (rc) 3143db217319SBenjamin Herrenschmidt pci_err(dev, "Error enabling bridge (%d)\n", rc); 3144db217319SBenjamin Herrenschmidt pci_set_master(dev); 3145db217319SBenjamin Herrenschmidt } 3146db217319SBenjamin Herrenschmidt 3147db217319SBenjamin Herrenschmidt /* Perform the same to child busses */ 3148db217319SBenjamin Herrenschmidt list_for_each_entry(child, &bus->children, node) 3149db217319SBenjamin Herrenschmidt pnv_pci_enable_bridge(child); 3150db217319SBenjamin Herrenschmidt } 3151db217319SBenjamin Herrenschmidt 3152db217319SBenjamin Herrenschmidt static void pnv_pci_enable_bridges(void) 3153db217319SBenjamin Herrenschmidt { 3154db217319SBenjamin Herrenschmidt struct pci_controller *hose; 3155db217319SBenjamin Herrenschmidt 3156db217319SBenjamin Herrenschmidt list_for_each_entry(hose, &hose_list, list_node) 3157db217319SBenjamin Herrenschmidt pnv_pci_enable_bridge(hose->bus); 3158db217319SBenjamin Herrenschmidt } 3159db217319SBenjamin Herrenschmidt 3160cad5cef6SGreg Kroah-Hartman static void pnv_pci_ioda_fixup(void) 3161fb446ad0SGavin Shan { 3162fb446ad0SGavin Shan pnv_pci_ioda_setup_PEs(); 3163ccd1c191SGavin Shan pnv_pci_ioda_setup_iommu_api(); 316437c367f2SGavin Shan pnv_pci_ioda_create_dbgfs(); 316537c367f2SGavin Shan 3166db217319SBenjamin Herrenschmidt pnv_pci_enable_bridges(); 3167db217319SBenjamin Herrenschmidt 3168e9cc17d4SGavin Shan #ifdef CONFIG_EEH 3169b9fde58dSBenjamin Herrenschmidt pnv_eeh_post_init(); 3170e9cc17d4SGavin Shan #endif 3171fb446ad0SGavin Shan } 3172fb446ad0SGavin Shan 3173271fd03aSGavin Shan /* 3174271fd03aSGavin Shan * Returns the alignment for I/O or memory windows for P2P 3175271fd03aSGavin Shan * bridges. That actually depends on how PEs are segmented. 3176271fd03aSGavin Shan * For now, we return I/O or M32 segment size for PE sensitive 3177271fd03aSGavin Shan * P2P bridges. Otherwise, the default values (4KiB for I/O, 3178271fd03aSGavin Shan * 1MiB for memory) will be returned. 3179271fd03aSGavin Shan * 3180271fd03aSGavin Shan * The current PCI bus might be put into one PE, which was 3181271fd03aSGavin Shan * create against the parent PCI bridge. For that case, we 3182271fd03aSGavin Shan * needn't enlarge the alignment so that we can save some 3183271fd03aSGavin Shan * resources. 3184271fd03aSGavin Shan */ 3185271fd03aSGavin Shan static resource_size_t pnv_pci_window_alignment(struct pci_bus *bus, 3186271fd03aSGavin Shan unsigned long type) 3187271fd03aSGavin Shan { 3188271fd03aSGavin Shan struct pci_dev *bridge; 3189271fd03aSGavin Shan struct pci_controller *hose = pci_bus_to_host(bus); 3190271fd03aSGavin Shan struct pnv_phb *phb = hose->private_data; 3191271fd03aSGavin Shan int num_pci_bridges = 0; 3192271fd03aSGavin Shan 3193271fd03aSGavin Shan bridge = bus->self; 3194271fd03aSGavin Shan while (bridge) { 3195271fd03aSGavin Shan if (pci_pcie_type(bridge) == PCI_EXP_TYPE_PCI_BRIDGE) { 3196271fd03aSGavin Shan num_pci_bridges++; 3197271fd03aSGavin Shan if (num_pci_bridges >= 2) 3198271fd03aSGavin Shan return 1; 3199271fd03aSGavin Shan } 3200271fd03aSGavin Shan 3201271fd03aSGavin Shan bridge = bridge->bus->self; 3202271fd03aSGavin Shan } 3203271fd03aSGavin Shan 32045958d19aSBenjamin Herrenschmidt /* 32055958d19aSBenjamin Herrenschmidt * We fall back to M32 if M64 isn't supported. We enforce the M64 32065958d19aSBenjamin Herrenschmidt * alignment for any 64-bit resource, PCIe doesn't care and 32075958d19aSBenjamin Herrenschmidt * bridges only do 64-bit prefetchable anyway. 32085958d19aSBenjamin Herrenschmidt */ 3209b79331a5SRussell Currey if (phb->ioda.m64_segsize && pnv_pci_is_m64_flags(type)) 3210262af557SGuo Chao return phb->ioda.m64_segsize; 3211271fd03aSGavin Shan if (type & IORESOURCE_MEM) 3212271fd03aSGavin Shan return phb->ioda.m32_segsize; 3213271fd03aSGavin Shan 3214271fd03aSGavin Shan return phb->ioda.io_segsize; 3215271fd03aSGavin Shan } 3216271fd03aSGavin Shan 321740e2a47eSGavin Shan /* 321840e2a47eSGavin Shan * We are updating root port or the upstream port of the 321940e2a47eSGavin Shan * bridge behind the root port with PHB's windows in order 322040e2a47eSGavin Shan * to accommodate the changes on required resources during 322140e2a47eSGavin Shan * PCI (slot) hotplug, which is connected to either root 322240e2a47eSGavin Shan * port or the downstream ports of PCIe switch behind the 322340e2a47eSGavin Shan * root port. 322440e2a47eSGavin Shan */ 322540e2a47eSGavin Shan static void pnv_pci_fixup_bridge_resources(struct pci_bus *bus, 322640e2a47eSGavin Shan unsigned long type) 322740e2a47eSGavin Shan { 322840e2a47eSGavin Shan struct pci_controller *hose = pci_bus_to_host(bus); 322940e2a47eSGavin Shan struct pnv_phb *phb = hose->private_data; 323040e2a47eSGavin Shan struct pci_dev *bridge = bus->self; 323140e2a47eSGavin Shan struct resource *r, *w; 323240e2a47eSGavin Shan bool msi_region = false; 323340e2a47eSGavin Shan int i; 323440e2a47eSGavin Shan 323540e2a47eSGavin Shan /* Check if we need apply fixup to the bridge's windows */ 323640e2a47eSGavin Shan if (!pci_is_root_bus(bridge->bus) && 323740e2a47eSGavin Shan !pci_is_root_bus(bridge->bus->self->bus)) 323840e2a47eSGavin Shan return; 323940e2a47eSGavin Shan 324040e2a47eSGavin Shan /* Fixup the resources */ 324140e2a47eSGavin Shan for (i = 0; i < PCI_BRIDGE_RESOURCE_NUM; i++) { 324240e2a47eSGavin Shan r = &bridge->resource[PCI_BRIDGE_RESOURCES + i]; 324340e2a47eSGavin Shan if (!r->flags || !r->parent) 324440e2a47eSGavin Shan continue; 324540e2a47eSGavin Shan 324640e2a47eSGavin Shan w = NULL; 324740e2a47eSGavin Shan if (r->flags & type & IORESOURCE_IO) 324840e2a47eSGavin Shan w = &hose->io_resource; 32495958d19aSBenjamin Herrenschmidt else if (pnv_pci_is_m64(phb, r) && 325040e2a47eSGavin Shan (type & IORESOURCE_PREFETCH) && 325140e2a47eSGavin Shan phb->ioda.m64_segsize) 325240e2a47eSGavin Shan w = &hose->mem_resources[1]; 325340e2a47eSGavin Shan else if (r->flags & type & IORESOURCE_MEM) { 325440e2a47eSGavin Shan w = &hose->mem_resources[0]; 325540e2a47eSGavin Shan msi_region = true; 325640e2a47eSGavin Shan } 325740e2a47eSGavin Shan 325840e2a47eSGavin Shan r->start = w->start; 325940e2a47eSGavin Shan r->end = w->end; 326040e2a47eSGavin Shan 326140e2a47eSGavin Shan /* The 64KB 32-bits MSI region shouldn't be included in 326240e2a47eSGavin Shan * the 32-bits bridge window. Otherwise, we can see strange 326340e2a47eSGavin Shan * issues. One of them is EEH error observed on Garrison. 326440e2a47eSGavin Shan * 326540e2a47eSGavin Shan * Exclude top 1MB region which is the minimal alignment of 326640e2a47eSGavin Shan * 32-bits bridge window. 326740e2a47eSGavin Shan */ 326840e2a47eSGavin Shan if (msi_region) { 326940e2a47eSGavin Shan r->end += 0x10000; 327040e2a47eSGavin Shan r->end -= 0x100000; 327140e2a47eSGavin Shan } 327240e2a47eSGavin Shan } 327340e2a47eSGavin Shan } 327440e2a47eSGavin Shan 3275ccd1c191SGavin Shan static void pnv_pci_setup_bridge(struct pci_bus *bus, unsigned long type) 3276ccd1c191SGavin Shan { 3277ccd1c191SGavin Shan struct pci_controller *hose = pci_bus_to_host(bus); 3278ccd1c191SGavin Shan struct pnv_phb *phb = hose->private_data; 3279ccd1c191SGavin Shan struct pci_dev *bridge = bus->self; 3280ccd1c191SGavin Shan struct pnv_ioda_pe *pe; 3281ccd1c191SGavin Shan bool all = (pci_pcie_type(bridge) == PCI_EXP_TYPE_PCI_BRIDGE); 3282ccd1c191SGavin Shan 328340e2a47eSGavin Shan /* Extend bridge's windows if necessary */ 328440e2a47eSGavin Shan pnv_pci_fixup_bridge_resources(bus, type); 328540e2a47eSGavin Shan 328663803c39SGavin Shan /* The PE for root bus should be realized before any one else */ 328763803c39SGavin Shan if (!phb->ioda.root_pe_populated) { 328863803c39SGavin Shan pe = pnv_ioda_setup_bus_PE(phb->hose->bus, false); 328963803c39SGavin Shan if (pe) { 329063803c39SGavin Shan phb->ioda.root_pe_idx = pe->pe_number; 329163803c39SGavin Shan phb->ioda.root_pe_populated = true; 329263803c39SGavin Shan } 329363803c39SGavin Shan } 329463803c39SGavin Shan 3295ccd1c191SGavin Shan /* Don't assign PE to PCI bus, which doesn't have subordinate devices */ 3296ccd1c191SGavin Shan if (list_empty(&bus->devices)) 3297ccd1c191SGavin Shan return; 3298ccd1c191SGavin Shan 3299ccd1c191SGavin Shan /* Reserve PEs according to used M64 resources */ 3300a25de7afSAlexey Kardashevskiy pnv_ioda_reserve_m64_pe(bus, NULL, all); 3301ccd1c191SGavin Shan 3302ccd1c191SGavin Shan /* 3303ccd1c191SGavin Shan * Assign PE. We might run here because of partial hotplug. 3304ccd1c191SGavin Shan * For the case, we just pick up the existing PE and should 3305ccd1c191SGavin Shan * not allocate resources again. 3306ccd1c191SGavin Shan */ 3307ccd1c191SGavin Shan pe = pnv_ioda_setup_bus_PE(bus, all); 3308ccd1c191SGavin Shan if (!pe) 3309ccd1c191SGavin Shan return; 3310ccd1c191SGavin Shan 3311ccd1c191SGavin Shan pnv_ioda_setup_pe_seg(pe); 3312ccd1c191SGavin Shan switch (phb->type) { 3313ccd1c191SGavin Shan case PNV_PHB_IODA1: 3314ccd1c191SGavin Shan pnv_pci_ioda1_setup_dma_pe(phb, pe); 3315ccd1c191SGavin Shan break; 3316ccd1c191SGavin Shan case PNV_PHB_IODA2: 3317ccd1c191SGavin Shan pnv_pci_ioda2_setup_dma_pe(phb, pe); 3318ccd1c191SGavin Shan break; 3319ccd1c191SGavin Shan default: 33201f52f176SRussell Currey pr_warn("%s: No DMA for PHB#%x (type %d)\n", 3321ccd1c191SGavin Shan __func__, phb->hose->global_number, phb->type); 3322ccd1c191SGavin Shan } 3323ccd1c191SGavin Shan } 3324ccd1c191SGavin Shan 332538274637SYongji Xie static resource_size_t pnv_pci_default_alignment(void) 332638274637SYongji Xie { 332738274637SYongji Xie return PAGE_SIZE; 332838274637SYongji Xie } 332938274637SYongji Xie 33305350ab3fSWei Yang #ifdef CONFIG_PCI_IOV 33315350ab3fSWei Yang static resource_size_t pnv_pci_iov_resource_alignment(struct pci_dev *pdev, 33325350ab3fSWei Yang int resno) 33335350ab3fSWei Yang { 3334ee8222feSWei Yang struct pci_controller *hose = pci_bus_to_host(pdev->bus); 3335ee8222feSWei Yang struct pnv_phb *phb = hose->private_data; 33365350ab3fSWei Yang struct pci_dn *pdn = pci_get_pdn(pdev); 33377fbe7a93SWei Yang resource_size_t align; 33385350ab3fSWei Yang 33397fbe7a93SWei Yang /* 33407fbe7a93SWei Yang * On PowerNV platform, IOV BAR is mapped by M64 BAR to enable the 33417fbe7a93SWei Yang * SR-IOV. While from hardware perspective, the range mapped by M64 33427fbe7a93SWei Yang * BAR should be size aligned. 33437fbe7a93SWei Yang * 3344ee8222feSWei Yang * When IOV BAR is mapped with M64 BAR in Single PE mode, the extra 3345ee8222feSWei Yang * powernv-specific hardware restriction is gone. But if just use the 3346ee8222feSWei Yang * VF BAR size as the alignment, PF BAR / VF BAR may be allocated with 3347ee8222feSWei Yang * in one segment of M64 #15, which introduces the PE conflict between 3348ee8222feSWei Yang * PF and VF. Based on this, the minimum alignment of an IOV BAR is 3349ee8222feSWei Yang * m64_segsize. 3350ee8222feSWei Yang * 33517fbe7a93SWei Yang * This function returns the total IOV BAR size if M64 BAR is in 33527fbe7a93SWei Yang * Shared PE mode or just VF BAR size if not. 3353ee8222feSWei Yang * If the M64 BAR is in Single PE mode, return the VF BAR size or 3354ee8222feSWei Yang * M64 segment size if IOV BAR size is less. 33557fbe7a93SWei Yang */ 33565350ab3fSWei Yang align = pci_iov_resource_size(pdev, resno); 33577fbe7a93SWei Yang if (!pdn->vfs_expanded) 33585350ab3fSWei Yang return align; 3359ee8222feSWei Yang if (pdn->m64_single_mode) 3360ee8222feSWei Yang return max(align, (resource_size_t)phb->ioda.m64_segsize); 33617fbe7a93SWei Yang 33627fbe7a93SWei Yang return pdn->vfs_expanded * align; 33635350ab3fSWei Yang } 33645350ab3fSWei Yang #endif /* CONFIG_PCI_IOV */ 33655350ab3fSWei Yang 3366184cd4a3SBenjamin Herrenschmidt /* Prevent enabling devices for which we couldn't properly 3367184cd4a3SBenjamin Herrenschmidt * assign a PE 3368184cd4a3SBenjamin Herrenschmidt */ 33698bf6b91aSAlastair D'Silva static bool pnv_pci_enable_device_hook(struct pci_dev *dev) 3370184cd4a3SBenjamin Herrenschmidt { 3371db1266c8SGavin Shan struct pci_controller *hose = pci_bus_to_host(dev->bus); 3372db1266c8SGavin Shan struct pnv_phb *phb = hose->private_data; 3373db1266c8SGavin Shan struct pci_dn *pdn; 3374184cd4a3SBenjamin Herrenschmidt 3375db1266c8SGavin Shan /* The function is probably called while the PEs have 3376db1266c8SGavin Shan * not be created yet. For example, resource reassignment 3377db1266c8SGavin Shan * during PCI probe period. We just skip the check if 3378db1266c8SGavin Shan * PEs isn't ready. 3379db1266c8SGavin Shan */ 3380db1266c8SGavin Shan if (!phb->initialized) 3381c88c2a18SDaniel Axtens return true; 3382db1266c8SGavin Shan 3383b72c1f65SBenjamin Herrenschmidt pdn = pci_get_pdn(dev); 3384184cd4a3SBenjamin Herrenschmidt if (!pdn || pdn->pe_number == IODA_INVALID_PE) 3385c88c2a18SDaniel Axtens return false; 3386db1266c8SGavin Shan 3387c88c2a18SDaniel Axtens return true; 3388184cd4a3SBenjamin Herrenschmidt } 3389184cd4a3SBenjamin Herrenschmidt 3390c5f7700bSGavin Shan static long pnv_pci_ioda1_unset_window(struct iommu_table_group *table_group, 3391c5f7700bSGavin Shan int num) 3392c5f7700bSGavin Shan { 3393c5f7700bSGavin Shan struct pnv_ioda_pe *pe = container_of(table_group, 3394c5f7700bSGavin Shan struct pnv_ioda_pe, table_group); 3395c5f7700bSGavin Shan struct pnv_phb *phb = pe->phb; 3396c5f7700bSGavin Shan unsigned int idx; 3397c5f7700bSGavin Shan long rc; 3398c5f7700bSGavin Shan 3399c5f7700bSGavin Shan pe_info(pe, "Removing DMA window #%d\n", num); 3400c5f7700bSGavin Shan for (idx = 0; idx < phb->ioda.dma32_count; idx++) { 3401c5f7700bSGavin Shan if (phb->ioda.dma32_segmap[idx] != pe->pe_number) 3402c5f7700bSGavin Shan continue; 3403c5f7700bSGavin Shan 3404c5f7700bSGavin Shan rc = opal_pci_map_pe_dma_window(phb->opal_id, pe->pe_number, 3405c5f7700bSGavin Shan idx, 0, 0ul, 0ul, 0ul); 3406c5f7700bSGavin Shan if (rc != OPAL_SUCCESS) { 3407c5f7700bSGavin Shan pe_warn(pe, "Failure %ld unmapping DMA32 segment#%d\n", 3408c5f7700bSGavin Shan rc, idx); 3409c5f7700bSGavin Shan return rc; 3410c5f7700bSGavin Shan } 3411c5f7700bSGavin Shan 3412c5f7700bSGavin Shan phb->ioda.dma32_segmap[idx] = IODA_INVALID_PE; 3413c5f7700bSGavin Shan } 3414c5f7700bSGavin Shan 3415c5f7700bSGavin Shan pnv_pci_unlink_table_and_group(table_group->tables[num], table_group); 3416c5f7700bSGavin Shan return OPAL_SUCCESS; 3417c5f7700bSGavin Shan } 3418c5f7700bSGavin Shan 3419c5f7700bSGavin Shan static void pnv_pci_ioda1_release_pe_dma(struct pnv_ioda_pe *pe) 3420c5f7700bSGavin Shan { 3421c5f7700bSGavin Shan unsigned int weight = pnv_pci_ioda_pe_dma_weight(pe); 3422c5f7700bSGavin Shan struct iommu_table *tbl = pe->table_group.tables[0]; 3423c5f7700bSGavin Shan int64_t rc; 3424c5f7700bSGavin Shan 3425c5f7700bSGavin Shan if (!weight) 3426c5f7700bSGavin Shan return; 3427c5f7700bSGavin Shan 3428c5f7700bSGavin Shan rc = pnv_pci_ioda1_unset_window(&pe->table_group, 0); 3429c5f7700bSGavin Shan if (rc != OPAL_SUCCESS) 3430c5f7700bSGavin Shan return; 3431c5f7700bSGavin Shan 3432a34ab7c3SBenjamin Herrenschmidt pnv_pci_p7ioc_tce_invalidate(tbl, tbl->it_offset, tbl->it_size, false); 3433c5f7700bSGavin Shan if (pe->table_group.group) { 3434c5f7700bSGavin Shan iommu_group_put(pe->table_group.group); 3435c5f7700bSGavin Shan WARN_ON(pe->table_group.group); 3436c5f7700bSGavin Shan } 3437c5f7700bSGavin Shan 3438c5f7700bSGavin Shan free_pages(tbl->it_base, get_order(tbl->it_size << 3)); 3439e5afdf9dSAlexey Kardashevskiy iommu_tce_table_put(tbl); 3440c5f7700bSGavin Shan } 3441c5f7700bSGavin Shan 3442c5f7700bSGavin Shan static void pnv_pci_ioda2_release_pe_dma(struct pnv_ioda_pe *pe) 3443c5f7700bSGavin Shan { 3444c5f7700bSGavin Shan struct iommu_table *tbl = pe->table_group.tables[0]; 3445c5f7700bSGavin Shan unsigned int weight = pnv_pci_ioda_pe_dma_weight(pe); 3446c5f7700bSGavin Shan #ifdef CONFIG_IOMMU_API 3447c5f7700bSGavin Shan int64_t rc; 3448c5f7700bSGavin Shan #endif 3449c5f7700bSGavin Shan 3450c5f7700bSGavin Shan if (!weight) 3451c5f7700bSGavin Shan return; 3452c5f7700bSGavin Shan 3453c5f7700bSGavin Shan #ifdef CONFIG_IOMMU_API 3454c5f7700bSGavin Shan rc = pnv_pci_ioda2_unset_window(&pe->table_group, 0); 3455c5f7700bSGavin Shan if (rc) 34561e496391SJoe Perches pe_warn(pe, "OPAL error %lld release DMA window\n", rc); 3457c5f7700bSGavin Shan #endif 3458c5f7700bSGavin Shan 3459c5f7700bSGavin Shan pnv_pci_ioda2_set_bypass(pe, false); 3460c5f7700bSGavin Shan if (pe->table_group.group) { 3461c5f7700bSGavin Shan iommu_group_put(pe->table_group.group); 3462c5f7700bSGavin Shan WARN_ON(pe->table_group.group); 3463c5f7700bSGavin Shan } 3464c5f7700bSGavin Shan 3465e5afdf9dSAlexey Kardashevskiy iommu_tce_table_put(tbl); 3466c5f7700bSGavin Shan } 3467c5f7700bSGavin Shan 3468c5f7700bSGavin Shan static void pnv_ioda_free_pe_seg(struct pnv_ioda_pe *pe, 3469c5f7700bSGavin Shan unsigned short win, 3470c5f7700bSGavin Shan unsigned int *map) 3471c5f7700bSGavin Shan { 3472c5f7700bSGavin Shan struct pnv_phb *phb = pe->phb; 3473c5f7700bSGavin Shan int idx; 3474c5f7700bSGavin Shan int64_t rc; 3475c5f7700bSGavin Shan 3476c5f7700bSGavin Shan for (idx = 0; idx < phb->ioda.total_pe_num; idx++) { 3477c5f7700bSGavin Shan if (map[idx] != pe->pe_number) 3478c5f7700bSGavin Shan continue; 3479c5f7700bSGavin Shan 3480c5f7700bSGavin Shan if (win == OPAL_M64_WINDOW_TYPE) 3481c5f7700bSGavin Shan rc = opal_pci_map_pe_mmio_window(phb->opal_id, 3482c5f7700bSGavin Shan phb->ioda.reserved_pe_idx, win, 3483c5f7700bSGavin Shan idx / PNV_IODA1_M64_SEGS, 3484c5f7700bSGavin Shan idx % PNV_IODA1_M64_SEGS); 3485c5f7700bSGavin Shan else 3486c5f7700bSGavin Shan rc = opal_pci_map_pe_mmio_window(phb->opal_id, 3487c5f7700bSGavin Shan phb->ioda.reserved_pe_idx, win, 0, idx); 3488c5f7700bSGavin Shan 3489c5f7700bSGavin Shan if (rc != OPAL_SUCCESS) 34901e496391SJoe Perches pe_warn(pe, "Error %lld unmapping (%d) segment#%d\n", 3491c5f7700bSGavin Shan rc, win, idx); 3492c5f7700bSGavin Shan 3493c5f7700bSGavin Shan map[idx] = IODA_INVALID_PE; 3494c5f7700bSGavin Shan } 3495c5f7700bSGavin Shan } 3496c5f7700bSGavin Shan 3497c5f7700bSGavin Shan static void pnv_ioda_release_pe_seg(struct pnv_ioda_pe *pe) 3498c5f7700bSGavin Shan { 3499c5f7700bSGavin Shan struct pnv_phb *phb = pe->phb; 3500c5f7700bSGavin Shan 3501c5f7700bSGavin Shan if (phb->type == PNV_PHB_IODA1) { 3502c5f7700bSGavin Shan pnv_ioda_free_pe_seg(pe, OPAL_IO_WINDOW_TYPE, 3503c5f7700bSGavin Shan phb->ioda.io_segmap); 3504c5f7700bSGavin Shan pnv_ioda_free_pe_seg(pe, OPAL_M32_WINDOW_TYPE, 3505c5f7700bSGavin Shan phb->ioda.m32_segmap); 3506c5f7700bSGavin Shan pnv_ioda_free_pe_seg(pe, OPAL_M64_WINDOW_TYPE, 3507c5f7700bSGavin Shan phb->ioda.m64_segmap); 3508c5f7700bSGavin Shan } else if (phb->type == PNV_PHB_IODA2) { 3509c5f7700bSGavin Shan pnv_ioda_free_pe_seg(pe, OPAL_M32_WINDOW_TYPE, 3510c5f7700bSGavin Shan phb->ioda.m32_segmap); 3511c5f7700bSGavin Shan } 3512c5f7700bSGavin Shan } 3513c5f7700bSGavin Shan 3514c5f7700bSGavin Shan static void pnv_ioda_release_pe(struct pnv_ioda_pe *pe) 3515c5f7700bSGavin Shan { 3516c5f7700bSGavin Shan struct pnv_phb *phb = pe->phb; 3517c5f7700bSGavin Shan struct pnv_ioda_pe *slave, *tmp; 3518c5f7700bSGavin Shan 3519c5f7700bSGavin Shan list_del(&pe->list); 3520c5f7700bSGavin Shan switch (phb->type) { 3521c5f7700bSGavin Shan case PNV_PHB_IODA1: 3522c5f7700bSGavin Shan pnv_pci_ioda1_release_pe_dma(pe); 3523c5f7700bSGavin Shan break; 3524c5f7700bSGavin Shan case PNV_PHB_IODA2: 3525c5f7700bSGavin Shan pnv_pci_ioda2_release_pe_dma(pe); 3526c5f7700bSGavin Shan break; 3527c5f7700bSGavin Shan default: 3528c5f7700bSGavin Shan WARN_ON(1); 3529c5f7700bSGavin Shan } 3530c5f7700bSGavin Shan 3531c5f7700bSGavin Shan pnv_ioda_release_pe_seg(pe); 3532c5f7700bSGavin Shan pnv_ioda_deconfigure_pe(pe->phb, pe); 3533b314427aSGavin Shan 3534b314427aSGavin Shan /* Release slave PEs in the compound PE */ 3535b314427aSGavin Shan if (pe->flags & PNV_IODA_PE_MASTER) { 3536b314427aSGavin Shan list_for_each_entry_safe(slave, tmp, &pe->slaves, list) { 3537b314427aSGavin Shan list_del(&slave->list); 3538b314427aSGavin Shan pnv_ioda_free_pe(slave); 3539b314427aSGavin Shan } 3540b314427aSGavin Shan } 3541b314427aSGavin Shan 35426eaed166SGavin Shan /* 35436eaed166SGavin Shan * The PE for root bus can be removed because of hotplug in EEH 35446eaed166SGavin Shan * recovery for fenced PHB error. We need to mark the PE dead so 35456eaed166SGavin Shan * that it can be populated again in PCI hot add path. The PE 35466eaed166SGavin Shan * shouldn't be destroyed as it's the global reserved resource. 35476eaed166SGavin Shan */ 35486eaed166SGavin Shan if (phb->ioda.root_pe_populated && 35496eaed166SGavin Shan phb->ioda.root_pe_idx == pe->pe_number) 35506eaed166SGavin Shan phb->ioda.root_pe_populated = false; 35516eaed166SGavin Shan else 3552c5f7700bSGavin Shan pnv_ioda_free_pe(pe); 3553c5f7700bSGavin Shan } 3554c5f7700bSGavin Shan 3555c5f7700bSGavin Shan static void pnv_pci_release_device(struct pci_dev *pdev) 3556c5f7700bSGavin Shan { 3557c5f7700bSGavin Shan struct pci_controller *hose = pci_bus_to_host(pdev->bus); 3558c5f7700bSGavin Shan struct pnv_phb *phb = hose->private_data; 3559c5f7700bSGavin Shan struct pci_dn *pdn = pci_get_pdn(pdev); 3560c5f7700bSGavin Shan struct pnv_ioda_pe *pe; 3561c5f7700bSGavin Shan 3562c5f7700bSGavin Shan if (pdev->is_virtfn) 3563c5f7700bSGavin Shan return; 3564c5f7700bSGavin Shan 3565c5f7700bSGavin Shan if (!pdn || pdn->pe_number == IODA_INVALID_PE) 3566c5f7700bSGavin Shan return; 3567c5f7700bSGavin Shan 356829bf282dSGavin Shan /* 356929bf282dSGavin Shan * PCI hotplug can happen as part of EEH error recovery. The @pdn 357029bf282dSGavin Shan * isn't removed and added afterwards in this scenario. We should 357129bf282dSGavin Shan * set the PE number in @pdn to an invalid one. Otherwise, the PE's 357229bf282dSGavin Shan * device count is decreased on removing devices while failing to 357329bf282dSGavin Shan * be increased on adding devices. It leads to unbalanced PE's device 357429bf282dSGavin Shan * count and eventually make normal PCI hotplug path broken. 357529bf282dSGavin Shan */ 3576c5f7700bSGavin Shan pe = &phb->ioda.pe_array[pdn->pe_number]; 357729bf282dSGavin Shan pdn->pe_number = IODA_INVALID_PE; 357829bf282dSGavin Shan 3579c5f7700bSGavin Shan WARN_ON(--pe->device_count < 0); 3580c5f7700bSGavin Shan if (pe->device_count == 0) 3581c5f7700bSGavin Shan pnv_ioda_release_pe(pe); 3582c5f7700bSGavin Shan } 3583c5f7700bSGavin Shan 3584ab7032e7SAlexey Kardashevskiy static void pnv_npu_disable_device(struct pci_dev *pdev) 3585ab7032e7SAlexey Kardashevskiy { 3586ab7032e7SAlexey Kardashevskiy struct eeh_dev *edev = pci_dev_to_eeh_dev(pdev); 3587ab7032e7SAlexey Kardashevskiy struct eeh_pe *eehpe = edev ? edev->pe : NULL; 3588ab7032e7SAlexey Kardashevskiy 3589ab7032e7SAlexey Kardashevskiy if (eehpe && eeh_ops && eeh_ops->reset) 3590ab7032e7SAlexey Kardashevskiy eeh_ops->reset(eehpe, EEH_RESET_HOT); 3591ab7032e7SAlexey Kardashevskiy } 3592ab7032e7SAlexey Kardashevskiy 35937a8e6bbfSMichael Neuling static void pnv_pci_ioda_shutdown(struct pci_controller *hose) 359473ed148aSBenjamin Herrenschmidt { 35957a8e6bbfSMichael Neuling struct pnv_phb *phb = hose->private_data; 35967a8e6bbfSMichael Neuling 3597d1a85eeeSGavin Shan opal_pci_reset(phb->opal_id, OPAL_RESET_PCI_IODA_TABLE, 359873ed148aSBenjamin Herrenschmidt OPAL_ASSERT_RESET); 359973ed148aSBenjamin Herrenschmidt } 360073ed148aSBenjamin Herrenschmidt 360192ae0353SDaniel Axtens static const struct pci_controller_ops pnv_pci_ioda_controller_ops = { 360292ae0353SDaniel Axtens .dma_dev_setup = pnv_pci_dma_dev_setup, 36031bc74f1cSGavin Shan .dma_bus_setup = pnv_pci_dma_bus_setup, 36042d6ad41bSChristoph Hellwig .iommu_bypass_supported = pnv_pci_ioda_iommu_bypass_supported, 360592ae0353SDaniel Axtens .setup_msi_irqs = pnv_setup_msi_irqs, 360692ae0353SDaniel Axtens .teardown_msi_irqs = pnv_teardown_msi_irqs, 360792ae0353SDaniel Axtens .enable_device_hook = pnv_pci_enable_device_hook, 3608c5f7700bSGavin Shan .release_device = pnv_pci_release_device, 360992ae0353SDaniel Axtens .window_alignment = pnv_pci_window_alignment, 3610ccd1c191SGavin Shan .setup_bridge = pnv_pci_setup_bridge, 361192ae0353SDaniel Axtens .reset_secondary_bus = pnv_pci_reset_secondary_bus, 36127a8e6bbfSMichael Neuling .shutdown = pnv_pci_ioda_shutdown, 361392ae0353SDaniel Axtens }; 361492ae0353SDaniel Axtens 36155d2aa710SAlistair Popple static const struct pci_controller_ops pnv_npu_ioda_controller_ops = { 36165d2aa710SAlistair Popple .dma_dev_setup = pnv_pci_dma_dev_setup, 36175d2aa710SAlistair Popple .setup_msi_irqs = pnv_setup_msi_irqs, 36185d2aa710SAlistair Popple .teardown_msi_irqs = pnv_teardown_msi_irqs, 36195d2aa710SAlistair Popple .enable_device_hook = pnv_pci_enable_device_hook, 36205d2aa710SAlistair Popple .window_alignment = pnv_pci_window_alignment, 36215d2aa710SAlistair Popple .reset_secondary_bus = pnv_pci_reset_secondary_bus, 36225d2aa710SAlistair Popple .shutdown = pnv_pci_ioda_shutdown, 3623ab7032e7SAlexey Kardashevskiy .disable_device = pnv_npu_disable_device, 36245d2aa710SAlistair Popple }; 36255d2aa710SAlistair Popple 36267f2c39e9SFrederic Barrat static const struct pci_controller_ops pnv_npu_ocapi_ioda_controller_ops = { 36277f2c39e9SFrederic Barrat .enable_device_hook = pnv_pci_enable_device_hook, 36287f2c39e9SFrederic Barrat .window_alignment = pnv_pci_window_alignment, 36297f2c39e9SFrederic Barrat .reset_secondary_bus = pnv_pci_reset_secondary_bus, 36307f2c39e9SFrederic Barrat .shutdown = pnv_pci_ioda_shutdown, 36317f2c39e9SFrederic Barrat }; 36327f2c39e9SFrederic Barrat 3633e51df2c1SAnton Blanchard static void __init pnv_pci_init_ioda_phb(struct device_node *np, 3634e9cc17d4SGavin Shan u64 hub_id, int ioda_type) 3635184cd4a3SBenjamin Herrenschmidt { 3636184cd4a3SBenjamin Herrenschmidt struct pci_controller *hose; 3637184cd4a3SBenjamin Herrenschmidt struct pnv_phb *phb; 36382b923ed1SGavin Shan unsigned long size, m64map_off, m32map_off, pemap_off; 36392b923ed1SGavin Shan unsigned long iomap_off = 0, dma32map_off = 0; 3640fd141d1aSBenjamin Herrenschmidt struct resource r; 3641c681b93cSAlistair Popple const __be64 *prop64; 36423a1a4661SBenjamin Herrenschmidt const __be32 *prop32; 3643f1b7cc3eSGavin Shan int len; 36443fa23ff8SGavin Shan unsigned int segno; 3645184cd4a3SBenjamin Herrenschmidt u64 phb_id; 3646184cd4a3SBenjamin Herrenschmidt void *aux; 3647184cd4a3SBenjamin Herrenschmidt long rc; 3648184cd4a3SBenjamin Herrenschmidt 364908a45b32SBenjamin Herrenschmidt if (!of_device_is_available(np)) 365008a45b32SBenjamin Herrenschmidt return; 365108a45b32SBenjamin Herrenschmidt 3652b7c670d6SRob Herring pr_info("Initializing %s PHB (%pOF)\n", pnv_phb_names[ioda_type], np); 3653184cd4a3SBenjamin Herrenschmidt 3654184cd4a3SBenjamin Herrenschmidt prop64 = of_get_property(np, "ibm,opal-phbid", NULL); 3655184cd4a3SBenjamin Herrenschmidt if (!prop64) { 3656184cd4a3SBenjamin Herrenschmidt pr_err(" Missing \"ibm,opal-phbid\" property !\n"); 3657184cd4a3SBenjamin Herrenschmidt return; 3658184cd4a3SBenjamin Herrenschmidt } 3659184cd4a3SBenjamin Herrenschmidt phb_id = be64_to_cpup(prop64); 3660184cd4a3SBenjamin Herrenschmidt pr_debug(" PHB-ID : 0x%016llx\n", phb_id); 3661184cd4a3SBenjamin Herrenschmidt 36627e1c4e27SMike Rapoport phb = memblock_alloc(sizeof(*phb), SMP_CACHE_BYTES); 36638a7f97b9SMike Rapoport if (!phb) 36648a7f97b9SMike Rapoport panic("%s: Failed to allocate %zu bytes\n", __func__, 36658a7f97b9SMike Rapoport sizeof(*phb)); 366658d714ecSGavin Shan 366758d714ecSGavin Shan /* Allocate PCI controller */ 3668184cd4a3SBenjamin Herrenschmidt phb->hose = hose = pcibios_alloc_controller(np); 366958d714ecSGavin Shan if (!phb->hose) { 3670b7c670d6SRob Herring pr_err(" Can't allocate PCI controller for %pOF\n", 3671b7c670d6SRob Herring np); 3672e39f223fSMichael Ellerman memblock_free(__pa(phb), sizeof(struct pnv_phb)); 3673184cd4a3SBenjamin Herrenschmidt return; 3674184cd4a3SBenjamin Herrenschmidt } 3675184cd4a3SBenjamin Herrenschmidt 3676184cd4a3SBenjamin Herrenschmidt spin_lock_init(&phb->lock); 3677f1b7cc3eSGavin Shan prop32 = of_get_property(np, "bus-range", &len); 3678f1b7cc3eSGavin Shan if (prop32 && len == 8) { 36793a1a4661SBenjamin Herrenschmidt hose->first_busno = be32_to_cpu(prop32[0]); 36803a1a4661SBenjamin Herrenschmidt hose->last_busno = be32_to_cpu(prop32[1]); 3681f1b7cc3eSGavin Shan } else { 3682b7c670d6SRob Herring pr_warn(" Broken <bus-range> on %pOF\n", np); 3683184cd4a3SBenjamin Herrenschmidt hose->first_busno = 0; 3684184cd4a3SBenjamin Herrenschmidt hose->last_busno = 0xff; 3685f1b7cc3eSGavin Shan } 3686184cd4a3SBenjamin Herrenschmidt hose->private_data = phb; 3687e9cc17d4SGavin Shan phb->hub_id = hub_id; 3688184cd4a3SBenjamin Herrenschmidt phb->opal_id = phb_id; 3689aa0c033fSGavin Shan phb->type = ioda_type; 3690781a868fSWei Yang mutex_init(&phb->ioda.pe_alloc_mutex); 3691184cd4a3SBenjamin Herrenschmidt 3692cee72d5bSBenjamin Herrenschmidt /* Detect specific models for error handling */ 3693cee72d5bSBenjamin Herrenschmidt if (of_device_is_compatible(np, "ibm,p7ioc-pciex")) 3694cee72d5bSBenjamin Herrenschmidt phb->model = PNV_PHB_MODEL_P7IOC; 3695f3d40c25SBenjamin Herrenschmidt else if (of_device_is_compatible(np, "ibm,power8-pciex")) 3696aa0c033fSGavin Shan phb->model = PNV_PHB_MODEL_PHB3; 36975d2aa710SAlistair Popple else if (of_device_is_compatible(np, "ibm,power8-npu-pciex")) 36985d2aa710SAlistair Popple phb->model = PNV_PHB_MODEL_NPU; 3699616badd2SAlistair Popple else if (of_device_is_compatible(np, "ibm,power9-npu-pciex")) 3700616badd2SAlistair Popple phb->model = PNV_PHB_MODEL_NPU2; 3701cee72d5bSBenjamin Herrenschmidt else 3702cee72d5bSBenjamin Herrenschmidt phb->model = PNV_PHB_MODEL_UNKNOWN; 3703cee72d5bSBenjamin Herrenschmidt 37045cb1f8fdSRussell Currey /* Initialize diagnostic data buffer */ 37055cb1f8fdSRussell Currey prop32 = of_get_property(np, "ibm,phb-diag-data-size", NULL); 37065cb1f8fdSRussell Currey if (prop32) 37075cb1f8fdSRussell Currey phb->diag_data_size = be32_to_cpup(prop32); 37085cb1f8fdSRussell Currey else 37095cb1f8fdSRussell Currey phb->diag_data_size = PNV_PCI_DIAG_BUF_SIZE; 37105cb1f8fdSRussell Currey 37117e1c4e27SMike Rapoport phb->diag_data = memblock_alloc(phb->diag_data_size, SMP_CACHE_BYTES); 37128a7f97b9SMike Rapoport if (!phb->diag_data) 37138a7f97b9SMike Rapoport panic("%s: Failed to allocate %u bytes\n", __func__, 37148a7f97b9SMike Rapoport phb->diag_data_size); 37155cb1f8fdSRussell Currey 3716aa0c033fSGavin Shan /* Parse 32-bit and IO ranges (if any) */ 37172f1ec02eSGavin Shan pci_process_bridge_OF_ranges(hose, np, !hose->global_number); 3718184cd4a3SBenjamin Herrenschmidt 3719aa0c033fSGavin Shan /* Get registers */ 3720fd141d1aSBenjamin Herrenschmidt if (!of_address_to_resource(np, 0, &r)) { 3721fd141d1aSBenjamin Herrenschmidt phb->regs_phys = r.start; 3722fd141d1aSBenjamin Herrenschmidt phb->regs = ioremap(r.start, resource_size(&r)); 3723184cd4a3SBenjamin Herrenschmidt if (phb->regs == NULL) 3724184cd4a3SBenjamin Herrenschmidt pr_err(" Failed to map registers !\n"); 3725fd141d1aSBenjamin Herrenschmidt } 3726577c8c88SGavin Shan 3727184cd4a3SBenjamin Herrenschmidt /* Initialize more IODA stuff */ 372892b8f137SGavin Shan phb->ioda.total_pe_num = 1; 372936954dc7SGavin Shan prop32 = of_get_property(np, "ibm,opal-num-pes", NULL); 373036954dc7SGavin Shan if (prop32) 373192b8f137SGavin Shan phb->ioda.total_pe_num = be32_to_cpup(prop32); 373236954dc7SGavin Shan prop32 = of_get_property(np, "ibm,opal-reserved-pe", NULL); 373336954dc7SGavin Shan if (prop32) 373492b8f137SGavin Shan phb->ioda.reserved_pe_idx = be32_to_cpup(prop32); 3735262af557SGuo Chao 3736c127562aSGavin Shan /* Invalidate RID to PE# mapping */ 3737c127562aSGavin Shan for (segno = 0; segno < ARRAY_SIZE(phb->ioda.pe_rmap); segno++) 3738c127562aSGavin Shan phb->ioda.pe_rmap[segno] = IODA_INVALID_PE; 3739c127562aSGavin Shan 3740262af557SGuo Chao /* Parse 64-bit MMIO range */ 3741262af557SGuo Chao pnv_ioda_parse_m64_window(phb); 3742262af557SGuo Chao 3743184cd4a3SBenjamin Herrenschmidt phb->ioda.m32_size = resource_size(&hose->mem_resources[0]); 3744aa0c033fSGavin Shan /* FW Has already off top 64k of M32 space (MSI space) */ 3745184cd4a3SBenjamin Herrenschmidt phb->ioda.m32_size += 0x10000; 3746184cd4a3SBenjamin Herrenschmidt 374792b8f137SGavin Shan phb->ioda.m32_segsize = phb->ioda.m32_size / phb->ioda.total_pe_num; 37483fd47f06SBenjamin Herrenschmidt phb->ioda.m32_pci_base = hose->mem_resources[0].start - hose->mem_offset[0]; 3749184cd4a3SBenjamin Herrenschmidt phb->ioda.io_size = hose->pci_io_size; 375092b8f137SGavin Shan phb->ioda.io_segsize = phb->ioda.io_size / phb->ioda.total_pe_num; 3751184cd4a3SBenjamin Herrenschmidt phb->ioda.io_pci_base = 0; /* XXX calculate this ? */ 3752184cd4a3SBenjamin Herrenschmidt 37532b923ed1SGavin Shan /* Calculate how many 32-bit TCE segments we have */ 37542b923ed1SGavin Shan phb->ioda.dma32_count = phb->ioda.m32_pci_base / 37552b923ed1SGavin Shan PNV_IODA1_DMA32_SEGSIZE; 37562b923ed1SGavin Shan 3757c35d2a8cSGavin Shan /* Allocate aux data & arrays. We don't have IO ports on PHB3 */ 375892a86756SAlexey Kardashevskiy size = _ALIGN_UP(max_t(unsigned, phb->ioda.total_pe_num, 8) / 8, 375992a86756SAlexey Kardashevskiy sizeof(unsigned long)); 376093289d8cSGavin Shan m64map_off = size; 376193289d8cSGavin Shan size += phb->ioda.total_pe_num * sizeof(phb->ioda.m64_segmap[0]); 3762184cd4a3SBenjamin Herrenschmidt m32map_off = size; 376392b8f137SGavin Shan size += phb->ioda.total_pe_num * sizeof(phb->ioda.m32_segmap[0]); 3764c35d2a8cSGavin Shan if (phb->type == PNV_PHB_IODA1) { 3765c35d2a8cSGavin Shan iomap_off = size; 376692b8f137SGavin Shan size += phb->ioda.total_pe_num * sizeof(phb->ioda.io_segmap[0]); 37672b923ed1SGavin Shan dma32map_off = size; 37682b923ed1SGavin Shan size += phb->ioda.dma32_count * 37692b923ed1SGavin Shan sizeof(phb->ioda.dma32_segmap[0]); 3770c35d2a8cSGavin Shan } 3771184cd4a3SBenjamin Herrenschmidt pemap_off = size; 377292b8f137SGavin Shan size += phb->ioda.total_pe_num * sizeof(struct pnv_ioda_pe); 37737e1c4e27SMike Rapoport aux = memblock_alloc(size, SMP_CACHE_BYTES); 37748a7f97b9SMike Rapoport if (!aux) 37758a7f97b9SMike Rapoport panic("%s: Failed to allocate %lu bytes\n", __func__, size); 3776184cd4a3SBenjamin Herrenschmidt phb->ioda.pe_alloc = aux; 377793289d8cSGavin Shan phb->ioda.m64_segmap = aux + m64map_off; 3778184cd4a3SBenjamin Herrenschmidt phb->ioda.m32_segmap = aux + m32map_off; 377993289d8cSGavin Shan for (segno = 0; segno < phb->ioda.total_pe_num; segno++) { 378093289d8cSGavin Shan phb->ioda.m64_segmap[segno] = IODA_INVALID_PE; 37813fa23ff8SGavin Shan phb->ioda.m32_segmap[segno] = IODA_INVALID_PE; 378293289d8cSGavin Shan } 37833fa23ff8SGavin Shan if (phb->type == PNV_PHB_IODA1) { 3784184cd4a3SBenjamin Herrenschmidt phb->ioda.io_segmap = aux + iomap_off; 37853fa23ff8SGavin Shan for (segno = 0; segno < phb->ioda.total_pe_num; segno++) 37863fa23ff8SGavin Shan phb->ioda.io_segmap[segno] = IODA_INVALID_PE; 37872b923ed1SGavin Shan 37882b923ed1SGavin Shan phb->ioda.dma32_segmap = aux + dma32map_off; 37892b923ed1SGavin Shan for (segno = 0; segno < phb->ioda.dma32_count; segno++) 37902b923ed1SGavin Shan phb->ioda.dma32_segmap[segno] = IODA_INVALID_PE; 37913fa23ff8SGavin Shan } 3792184cd4a3SBenjamin Herrenschmidt phb->ioda.pe_array = aux + pemap_off; 379363803c39SGavin Shan 379463803c39SGavin Shan /* 379563803c39SGavin Shan * Choose PE number for root bus, which shouldn't have 379663803c39SGavin Shan * M64 resources consumed by its child devices. To pick 379763803c39SGavin Shan * the PE number adjacent to the reserved one if possible. 379863803c39SGavin Shan */ 379963803c39SGavin Shan pnv_ioda_reserve_pe(phb, phb->ioda.reserved_pe_idx); 380063803c39SGavin Shan if (phb->ioda.reserved_pe_idx == 0) { 380163803c39SGavin Shan phb->ioda.root_pe_idx = 1; 380263803c39SGavin Shan pnv_ioda_reserve_pe(phb, phb->ioda.root_pe_idx); 380363803c39SGavin Shan } else if (phb->ioda.reserved_pe_idx == (phb->ioda.total_pe_num - 1)) { 380463803c39SGavin Shan phb->ioda.root_pe_idx = phb->ioda.reserved_pe_idx - 1; 380563803c39SGavin Shan pnv_ioda_reserve_pe(phb, phb->ioda.root_pe_idx); 380663803c39SGavin Shan } else { 380763803c39SGavin Shan phb->ioda.root_pe_idx = IODA_INVALID_PE; 380863803c39SGavin Shan } 3809184cd4a3SBenjamin Herrenschmidt 3810184cd4a3SBenjamin Herrenschmidt INIT_LIST_HEAD(&phb->ioda.pe_list); 3811781a868fSWei Yang mutex_init(&phb->ioda.pe_list_mutex); 3812184cd4a3SBenjamin Herrenschmidt 3813184cd4a3SBenjamin Herrenschmidt /* Calculate how many 32-bit TCE segments we have */ 38142b923ed1SGavin Shan phb->ioda.dma32_count = phb->ioda.m32_pci_base / 3815acce971cSGavin Shan PNV_IODA1_DMA32_SEGSIZE; 3816184cd4a3SBenjamin Herrenschmidt 3817aa0c033fSGavin Shan #if 0 /* We should really do that ... */ 3818184cd4a3SBenjamin Herrenschmidt rc = opal_pci_set_phb_mem_window(opal->phb_id, 3819184cd4a3SBenjamin Herrenschmidt window_type, 3820184cd4a3SBenjamin Herrenschmidt window_num, 3821184cd4a3SBenjamin Herrenschmidt starting_real_address, 3822184cd4a3SBenjamin Herrenschmidt starting_pci_address, 3823184cd4a3SBenjamin Herrenschmidt segment_size); 3824184cd4a3SBenjamin Herrenschmidt #endif 3825184cd4a3SBenjamin Herrenschmidt 3826262af557SGuo Chao pr_info(" %03d (%03d) PE's M32: 0x%x [segment=0x%x]\n", 382792b8f137SGavin Shan phb->ioda.total_pe_num, phb->ioda.reserved_pe_idx, 3828262af557SGuo Chao phb->ioda.m32_size, phb->ioda.m32_segsize); 3829262af557SGuo Chao if (phb->ioda.m64_size) 3830262af557SGuo Chao pr_info(" M64: 0x%lx [segment=0x%lx]\n", 3831262af557SGuo Chao phb->ioda.m64_size, phb->ioda.m64_segsize); 3832262af557SGuo Chao if (phb->ioda.io_size) 3833262af557SGuo Chao pr_info(" IO: 0x%x [segment=0x%x]\n", 3834184cd4a3SBenjamin Herrenschmidt phb->ioda.io_size, phb->ioda.io_segsize); 3835184cd4a3SBenjamin Herrenschmidt 3836262af557SGuo Chao 3837184cd4a3SBenjamin Herrenschmidt phb->hose->ops = &pnv_pci_ops; 383849dec922SGavin Shan phb->get_pe_state = pnv_ioda_get_pe_state; 383949dec922SGavin Shan phb->freeze_pe = pnv_ioda_freeze_pe; 384049dec922SGavin Shan phb->unfreeze_pe = pnv_ioda_unfreeze_pe; 3841184cd4a3SBenjamin Herrenschmidt 3842184cd4a3SBenjamin Herrenschmidt /* Setup MSI support */ 3843184cd4a3SBenjamin Herrenschmidt pnv_pci_init_ioda_msis(phb); 3844184cd4a3SBenjamin Herrenschmidt 3845c40a4210SGavin Shan /* 3846c40a4210SGavin Shan * We pass the PCI probe flag PCI_REASSIGN_ALL_RSRC here 3847c40a4210SGavin Shan * to let the PCI core do resource assignment. It's supposed 3848c40a4210SGavin Shan * that the PCI core will do correct I/O and MMIO alignment 3849c40a4210SGavin Shan * for the P2P bridge bars so that each PCI bus (excluding 3850c40a4210SGavin Shan * the child P2P bridges) can form individual PE. 3851184cd4a3SBenjamin Herrenschmidt */ 3852fb446ad0SGavin Shan ppc_md.pcibios_fixup = pnv_pci_ioda_fixup; 38535d2aa710SAlistair Popple 38547f2c39e9SFrederic Barrat switch (phb->type) { 38557f2c39e9SFrederic Barrat case PNV_PHB_NPU_NVLINK: 38565d2aa710SAlistair Popple hose->controller_ops = pnv_npu_ioda_controller_ops; 38577f2c39e9SFrederic Barrat break; 38587f2c39e9SFrederic Barrat case PNV_PHB_NPU_OCAPI: 38597f2c39e9SFrederic Barrat hose->controller_ops = pnv_npu_ocapi_ioda_controller_ops; 38607f2c39e9SFrederic Barrat break; 38617f2c39e9SFrederic Barrat default: 3862f9f83456SAlexey Kardashevskiy phb->dma_dev_setup = pnv_pci_ioda_dma_dev_setup; 386392ae0353SDaniel Axtens hose->controller_ops = pnv_pci_ioda_controller_ops; 3864f9f83456SAlexey Kardashevskiy } 3865ad30cb99SMichael Ellerman 386638274637SYongji Xie ppc_md.pcibios_default_alignment = pnv_pci_default_alignment; 386738274637SYongji Xie 38686e628c7dSWei Yang #ifdef CONFIG_PCI_IOV 38696e628c7dSWei Yang ppc_md.pcibios_fixup_sriov = pnv_pci_ioda_fixup_iov_resources; 38705350ab3fSWei Yang ppc_md.pcibios_iov_resource_alignment = pnv_pci_iov_resource_alignment; 3871988fc3baSBryant G. Ly ppc_md.pcibios_sriov_enable = pnv_pcibios_sriov_enable; 3872988fc3baSBryant G. Ly ppc_md.pcibios_sriov_disable = pnv_pcibios_sriov_disable; 3873ad30cb99SMichael Ellerman #endif 3874ad30cb99SMichael Ellerman 3875c40a4210SGavin Shan pci_add_flags(PCI_REASSIGN_ALL_RSRC); 3876184cd4a3SBenjamin Herrenschmidt 3877184cd4a3SBenjamin Herrenschmidt /* Reset IODA tables to a clean state */ 3878d1a85eeeSGavin Shan rc = opal_pci_reset(phb_id, OPAL_RESET_PCI_IODA_TABLE, OPAL_ASSERT_RESET); 3879184cd4a3SBenjamin Herrenschmidt if (rc) 3880f2c2cbccSJoe Perches pr_warn(" OPAL Error %ld performing IODA table reset !\n", rc); 3881361f2a2aSGavin Shan 38826060e9eaSAndrew Donnellan /* 38836060e9eaSAndrew Donnellan * If we're running in kdump kernel, the previous kernel never 3884361f2a2aSGavin Shan * shutdown PCI devices correctly. We already got IODA table 3885361f2a2aSGavin Shan * cleaned out. So we have to issue PHB reset to stop all PCI 388645baee14SGuilherme G. Piccoli * transactions from previous kernel. The ppc_pci_reset_phbs 3887b174b4fbSOliver O'Halloran * kernel parameter will force this reset too. Additionally, 3888b174b4fbSOliver O'Halloran * if the IODA reset above failed then use a bigger hammer. 3889b174b4fbSOliver O'Halloran * This can happen if we get a PHB fatal error in very early 3890b174b4fbSOliver O'Halloran * boot. 3891361f2a2aSGavin Shan */ 3892b174b4fbSOliver O'Halloran if (is_kdump_kernel() || pci_reset_phbs || rc) { 3893361f2a2aSGavin Shan pr_info(" Issue PHB reset ...\n"); 3894cadf364dSGavin Shan pnv_eeh_phb_reset(hose, EEH_RESET_FUNDAMENTAL); 3895cadf364dSGavin Shan pnv_eeh_phb_reset(hose, EEH_RESET_DEACTIVATE); 3896361f2a2aSGavin Shan } 3897262af557SGuo Chao 38989e9e8935SGavin Shan /* Remove M64 resource if we can't configure it successfully */ 38999e9e8935SGavin Shan if (!phb->init_m64 || phb->init_m64(phb)) 3900262af557SGuo Chao hose->mem_resources[1].flags = 0; 3901184cd4a3SBenjamin Herrenschmidt } 3902184cd4a3SBenjamin Herrenschmidt 390367975005SBjorn Helgaas void __init pnv_pci_init_ioda2_phb(struct device_node *np) 3904aa0c033fSGavin Shan { 3905e9cc17d4SGavin Shan pnv_pci_init_ioda_phb(np, 0, PNV_PHB_IODA2); 3906aa0c033fSGavin Shan } 3907aa0c033fSGavin Shan 39085d2aa710SAlistair Popple void __init pnv_pci_init_npu_phb(struct device_node *np) 39095d2aa710SAlistair Popple { 39107f2c39e9SFrederic Barrat pnv_pci_init_ioda_phb(np, 0, PNV_PHB_NPU_NVLINK); 39115d2aa710SAlistair Popple } 39125d2aa710SAlistair Popple 39137f2c39e9SFrederic Barrat void __init pnv_pci_init_npu2_opencapi_phb(struct device_node *np) 39147f2c39e9SFrederic Barrat { 39157f2c39e9SFrederic Barrat pnv_pci_init_ioda_phb(np, 0, PNV_PHB_NPU_OCAPI); 3916184cd4a3SBenjamin Herrenschmidt } 3917184cd4a3SBenjamin Herrenschmidt 3918228c2f41SAndrew Donnellan static void pnv_npu2_opencapi_cfg_size_fixup(struct pci_dev *dev) 3919228c2f41SAndrew Donnellan { 3920228c2f41SAndrew Donnellan struct pci_controller *hose = pci_bus_to_host(dev->bus); 3921228c2f41SAndrew Donnellan struct pnv_phb *phb = hose->private_data; 3922228c2f41SAndrew Donnellan 3923228c2f41SAndrew Donnellan if (!machine_is(powernv)) 3924228c2f41SAndrew Donnellan return; 3925228c2f41SAndrew Donnellan 3926228c2f41SAndrew Donnellan if (phb->type == PNV_PHB_NPU_OCAPI) 3927228c2f41SAndrew Donnellan dev->cfg_size = PCI_CFG_SPACE_EXP_SIZE; 3928228c2f41SAndrew Donnellan } 3929228c2f41SAndrew Donnellan DECLARE_PCI_FIXUP_EARLY(PCI_ANY_ID, PCI_ANY_ID, pnv_npu2_opencapi_cfg_size_fixup); 3930228c2f41SAndrew Donnellan 3931184cd4a3SBenjamin Herrenschmidt void __init pnv_pci_init_ioda_hub(struct device_node *np) 3932184cd4a3SBenjamin Herrenschmidt { 3933184cd4a3SBenjamin Herrenschmidt struct device_node *phbn; 3934184cd4a3SBenjamin Herrenschmidt const __be64 *prop64; 3935184cd4a3SBenjamin Herrenschmidt u64 hub_id; 3936184cd4a3SBenjamin Herrenschmidt 3937b7c670d6SRob Herring pr_info("Probing IODA IO-Hub %pOF\n", np); 3938184cd4a3SBenjamin Herrenschmidt 3939184cd4a3SBenjamin Herrenschmidt prop64 = of_get_property(np, "ibm,opal-hubid", NULL); 3940184cd4a3SBenjamin Herrenschmidt if (!prop64) { 3941184cd4a3SBenjamin Herrenschmidt pr_err(" Missing \"ibm,opal-hubid\" property !\n"); 3942184cd4a3SBenjamin Herrenschmidt return; 3943184cd4a3SBenjamin Herrenschmidt } 3944184cd4a3SBenjamin Herrenschmidt hub_id = be64_to_cpup(prop64); 3945184cd4a3SBenjamin Herrenschmidt pr_devel(" HUB-ID : 0x%016llx\n", hub_id); 3946184cd4a3SBenjamin Herrenschmidt 3947184cd4a3SBenjamin Herrenschmidt /* Count child PHBs */ 3948184cd4a3SBenjamin Herrenschmidt for_each_child_of_node(np, phbn) { 3949184cd4a3SBenjamin Herrenschmidt /* Look for IODA1 PHBs */ 3950184cd4a3SBenjamin Herrenschmidt if (of_device_is_compatible(phbn, "ibm,ioda-phb")) 3951184cd4a3SBenjamin Herrenschmidt pnv_pci_init_ioda_phb(phbn, hub_id, PNV_PHB_IODA1); 3952184cd4a3SBenjamin Herrenschmidt } 3953184cd4a3SBenjamin Herrenschmidt } 3954