1184cd4a3SBenjamin Herrenschmidt /* 2184cd4a3SBenjamin Herrenschmidt * Support PCI/PCIe on PowerNV platforms 3184cd4a3SBenjamin Herrenschmidt * 4184cd4a3SBenjamin Herrenschmidt * Copyright 2011 Benjamin Herrenschmidt, IBM Corp. 5184cd4a3SBenjamin Herrenschmidt * 6184cd4a3SBenjamin Herrenschmidt * This program is free software; you can redistribute it and/or 7184cd4a3SBenjamin Herrenschmidt * modify it under the terms of the GNU General Public License 8184cd4a3SBenjamin Herrenschmidt * as published by the Free Software Foundation; either version 9184cd4a3SBenjamin Herrenschmidt * 2 of the License, or (at your option) any later version. 10184cd4a3SBenjamin Herrenschmidt */ 11184cd4a3SBenjamin Herrenschmidt 12cee72d5bSBenjamin Herrenschmidt #undef DEBUG 13184cd4a3SBenjamin Herrenschmidt 14184cd4a3SBenjamin Herrenschmidt #include <linux/kernel.h> 15184cd4a3SBenjamin Herrenschmidt #include <linux/pci.h> 16361f2a2aSGavin Shan #include <linux/crash_dump.h> 17184cd4a3SBenjamin Herrenschmidt #include <linux/delay.h> 18184cd4a3SBenjamin Herrenschmidt #include <linux/string.h> 19184cd4a3SBenjamin Herrenschmidt #include <linux/init.h> 20184cd4a3SBenjamin Herrenschmidt #include <linux/bootmem.h> 21184cd4a3SBenjamin Herrenschmidt #include <linux/irq.h> 22184cd4a3SBenjamin Herrenschmidt #include <linux/io.h> 23184cd4a3SBenjamin Herrenschmidt #include <linux/msi.h> 24cd15b048SBenjamin Herrenschmidt #include <linux/memblock.h> 25ac9a5889SAlexey Kardashevskiy #include <linux/iommu.h> 26e57080f1SAlexey Kardashevskiy #include <linux/rculist.h> 274793d65dSAlexey Kardashevskiy #include <linux/sizes.h> 28184cd4a3SBenjamin Herrenschmidt 29184cd4a3SBenjamin Herrenschmidt #include <asm/sections.h> 30184cd4a3SBenjamin Herrenschmidt #include <asm/io.h> 31184cd4a3SBenjamin Herrenschmidt #include <asm/prom.h> 32184cd4a3SBenjamin Herrenschmidt #include <asm/pci-bridge.h> 33184cd4a3SBenjamin Herrenschmidt #include <asm/machdep.h> 34fb1b55d6SGavin Shan #include <asm/msi_bitmap.h> 35184cd4a3SBenjamin Herrenschmidt #include <asm/ppc-pci.h> 36184cd4a3SBenjamin Herrenschmidt #include <asm/opal.h> 37184cd4a3SBenjamin Herrenschmidt #include <asm/iommu.h> 38184cd4a3SBenjamin Herrenschmidt #include <asm/tce.h> 39137436c9SGavin Shan #include <asm/xics.h> 407644d581SMichael Ellerman #include <asm/debugfs.h> 41262af557SGuo Chao #include <asm/firmware.h> 4280c49c7eSIan Munsie #include <asm/pnv-pci.h> 43aca6913fSAlexey Kardashevskiy #include <asm/mmzone.h> 4480c49c7eSIan Munsie 45ec249dd8SMichael Neuling #include <misc/cxl-base.h> 46184cd4a3SBenjamin Herrenschmidt 47184cd4a3SBenjamin Herrenschmidt #include "powernv.h" 48184cd4a3SBenjamin Herrenschmidt #include "pci.h" 49184cd4a3SBenjamin Herrenschmidt 5099451551SGavin Shan #define PNV_IODA1_M64_NUM 16 /* Number of M64 BARs */ 5199451551SGavin Shan #define PNV_IODA1_M64_SEGS 8 /* Segments per M64 BAR */ 52acce971cSGavin Shan #define PNV_IODA1_DMA32_SEGSIZE 0x10000000 53781a868fSWei Yang 54bbb845c4SAlexey Kardashevskiy #define POWERNV_IOMMU_DEFAULT_LEVELS 1 55bbb845c4SAlexey Kardashevskiy #define POWERNV_IOMMU_MAX_LEVELS 5 56bbb845c4SAlexey Kardashevskiy 579497a1c1SGavin Shan static const char * const pnv_phb_names[] = { "IODA1", "IODA2", "NPU" }; 58aca6913fSAlexey Kardashevskiy static void pnv_pci_ioda2_table_free_pages(struct iommu_table *tbl); 59aca6913fSAlexey Kardashevskiy 607d623e42SAlexey Kardashevskiy void pe_level_printk(const struct pnv_ioda_pe *pe, const char *level, 616d31c2faSJoe Perches const char *fmt, ...) 626d31c2faSJoe Perches { 636d31c2faSJoe Perches struct va_format vaf; 646d31c2faSJoe Perches va_list args; 656d31c2faSJoe Perches char pfix[32]; 66184cd4a3SBenjamin Herrenschmidt 676d31c2faSJoe Perches va_start(args, fmt); 686d31c2faSJoe Perches 696d31c2faSJoe Perches vaf.fmt = fmt; 706d31c2faSJoe Perches vaf.va = &args; 716d31c2faSJoe Perches 72781a868fSWei Yang if (pe->flags & PNV_IODA_PE_DEV) 736d31c2faSJoe Perches strlcpy(pfix, dev_name(&pe->pdev->dev), sizeof(pfix)); 74781a868fSWei Yang else if (pe->flags & (PNV_IODA_PE_BUS | PNV_IODA_PE_BUS_ALL)) 756d31c2faSJoe Perches sprintf(pfix, "%04x:%02x ", 766d31c2faSJoe Perches pci_domain_nr(pe->pbus), pe->pbus->number); 77781a868fSWei Yang #ifdef CONFIG_PCI_IOV 78781a868fSWei Yang else if (pe->flags & PNV_IODA_PE_VF) 79781a868fSWei Yang sprintf(pfix, "%04x:%02x:%2x.%d", 80781a868fSWei Yang pci_domain_nr(pe->parent_dev->bus), 81781a868fSWei Yang (pe->rid & 0xff00) >> 8, 82781a868fSWei Yang PCI_SLOT(pe->rid), PCI_FUNC(pe->rid)); 83781a868fSWei Yang #endif /* CONFIG_PCI_IOV*/ 846d31c2faSJoe Perches 851f52f176SRussell Currey printk("%spci %s: [PE# %.2x] %pV", 866d31c2faSJoe Perches level, pfix, pe->pe_number, &vaf); 876d31c2faSJoe Perches 886d31c2faSJoe Perches va_end(args); 896d31c2faSJoe Perches } 906d31c2faSJoe Perches 914e287840SThadeu Lima de Souza Cascardo static bool pnv_iommu_bypass_disabled __read_mostly; 924e287840SThadeu Lima de Souza Cascardo 934e287840SThadeu Lima de Souza Cascardo static int __init iommu_setup(char *str) 944e287840SThadeu Lima de Souza Cascardo { 954e287840SThadeu Lima de Souza Cascardo if (!str) 964e287840SThadeu Lima de Souza Cascardo return -EINVAL; 974e287840SThadeu Lima de Souza Cascardo 984e287840SThadeu Lima de Souza Cascardo while (*str) { 994e287840SThadeu Lima de Souza Cascardo if (!strncmp(str, "nobypass", 8)) { 1004e287840SThadeu Lima de Souza Cascardo pnv_iommu_bypass_disabled = true; 1014e287840SThadeu Lima de Souza Cascardo pr_info("PowerNV: IOMMU bypass window disabled.\n"); 1024e287840SThadeu Lima de Souza Cascardo break; 1034e287840SThadeu Lima de Souza Cascardo } 1044e287840SThadeu Lima de Souza Cascardo str += strcspn(str, ","); 1054e287840SThadeu Lima de Souza Cascardo if (*str == ',') 1064e287840SThadeu Lima de Souza Cascardo str++; 1074e287840SThadeu Lima de Souza Cascardo } 1084e287840SThadeu Lima de Souza Cascardo 1094e287840SThadeu Lima de Souza Cascardo return 0; 1104e287840SThadeu Lima de Souza Cascardo } 1114e287840SThadeu Lima de Souza Cascardo early_param("iommu", iommu_setup); 1124e287840SThadeu Lima de Souza Cascardo 1135958d19aSBenjamin Herrenschmidt static inline bool pnv_pci_is_m64(struct pnv_phb *phb, struct resource *r) 114262af557SGuo Chao { 1155958d19aSBenjamin Herrenschmidt /* 1165958d19aSBenjamin Herrenschmidt * WARNING: We cannot rely on the resource flags. The Linux PCI 1175958d19aSBenjamin Herrenschmidt * allocation code sometimes decides to put a 64-bit prefetchable 1185958d19aSBenjamin Herrenschmidt * BAR in the 32-bit window, so we have to compare the addresses. 1195958d19aSBenjamin Herrenschmidt * 1205958d19aSBenjamin Herrenschmidt * For simplicity we only test resource start. 1215958d19aSBenjamin Herrenschmidt */ 1225958d19aSBenjamin Herrenschmidt return (r->start >= phb->ioda.m64_base && 1235958d19aSBenjamin Herrenschmidt r->start < (phb->ioda.m64_base + phb->ioda.m64_size)); 124262af557SGuo Chao } 125262af557SGuo Chao 126b79331a5SRussell Currey static inline bool pnv_pci_is_m64_flags(unsigned long resource_flags) 127b79331a5SRussell Currey { 128b79331a5SRussell Currey unsigned long flags = (IORESOURCE_MEM_64 | IORESOURCE_PREFETCH); 129b79331a5SRussell Currey 130b79331a5SRussell Currey return (resource_flags & flags) == flags; 131b79331a5SRussell Currey } 132b79331a5SRussell Currey 1331e916772SGavin Shan static struct pnv_ioda_pe *pnv_ioda_init_pe(struct pnv_phb *phb, int pe_no) 1341e916772SGavin Shan { 135313483ddSGavin Shan s64 rc; 136313483ddSGavin Shan 1371e916772SGavin Shan phb->ioda.pe_array[pe_no].phb = phb; 1381e916772SGavin Shan phb->ioda.pe_array[pe_no].pe_number = pe_no; 1391e916772SGavin Shan 140313483ddSGavin Shan /* 141313483ddSGavin Shan * Clear the PE frozen state as it might be put into frozen state 142313483ddSGavin Shan * in the last PCI remove path. It's not harmful to do so when the 143313483ddSGavin Shan * PE is already in unfrozen state. 144313483ddSGavin Shan */ 145313483ddSGavin Shan rc = opal_pci_eeh_freeze_clear(phb->opal_id, pe_no, 146313483ddSGavin Shan OPAL_EEH_ACTION_CLEAR_FREEZE_ALL); 147d4791db5SRussell Currey if (rc != OPAL_SUCCESS && rc != OPAL_UNSUPPORTED) 1481f52f176SRussell Currey pr_warn("%s: Error %lld unfreezing PHB#%x-PE#%x\n", 149313483ddSGavin Shan __func__, rc, phb->hose->global_number, pe_no); 150313483ddSGavin Shan 1511e916772SGavin Shan return &phb->ioda.pe_array[pe_no]; 1521e916772SGavin Shan } 1531e916772SGavin Shan 1544b82ab18SGavin Shan static void pnv_ioda_reserve_pe(struct pnv_phb *phb, int pe_no) 1554b82ab18SGavin Shan { 15692b8f137SGavin Shan if (!(pe_no >= 0 && pe_no < phb->ioda.total_pe_num)) { 1571f52f176SRussell Currey pr_warn("%s: Invalid PE %x on PHB#%x\n", 1584b82ab18SGavin Shan __func__, pe_no, phb->hose->global_number); 1594b82ab18SGavin Shan return; 1604b82ab18SGavin Shan } 1614b82ab18SGavin Shan 162e9dc4d7fSGavin Shan if (test_and_set_bit(pe_no, phb->ioda.pe_alloc)) 1631f52f176SRussell Currey pr_debug("%s: PE %x was reserved on PHB#%x\n", 1644b82ab18SGavin Shan __func__, pe_no, phb->hose->global_number); 1654b82ab18SGavin Shan 1661e916772SGavin Shan pnv_ioda_init_pe(phb, pe_no); 1674b82ab18SGavin Shan } 1684b82ab18SGavin Shan 1691e916772SGavin Shan static struct pnv_ioda_pe *pnv_ioda_alloc_pe(struct pnv_phb *phb) 170184cd4a3SBenjamin Herrenschmidt { 17160964816SAndrzej Hajda long pe; 172184cd4a3SBenjamin Herrenschmidt 1739fcd6f4aSGavin Shan for (pe = phb->ioda.total_pe_num - 1; pe >= 0; pe--) { 1749fcd6f4aSGavin Shan if (!test_and_set_bit(pe, phb->ioda.pe_alloc)) 1751e916772SGavin Shan return pnv_ioda_init_pe(phb, pe); 176184cd4a3SBenjamin Herrenschmidt } 177184cd4a3SBenjamin Herrenschmidt 1789fcd6f4aSGavin Shan return NULL; 1799fcd6f4aSGavin Shan } 1809fcd6f4aSGavin Shan 1811e916772SGavin Shan static void pnv_ioda_free_pe(struct pnv_ioda_pe *pe) 182184cd4a3SBenjamin Herrenschmidt { 1831e916772SGavin Shan struct pnv_phb *phb = pe->phb; 184caa58f80SGavin Shan unsigned int pe_num = pe->pe_number; 185184cd4a3SBenjamin Herrenschmidt 1861e916772SGavin Shan WARN_ON(pe->pdev); 1871e916772SGavin Shan 1881e916772SGavin Shan memset(pe, 0, sizeof(struct pnv_ioda_pe)); 189caa58f80SGavin Shan clear_bit(pe_num, phb->ioda.pe_alloc); 190184cd4a3SBenjamin Herrenschmidt } 191184cd4a3SBenjamin Herrenschmidt 192262af557SGuo Chao /* The default M64 BAR is shared by all PEs */ 193262af557SGuo Chao static int pnv_ioda2_init_m64(struct pnv_phb *phb) 194262af557SGuo Chao { 195262af557SGuo Chao const char *desc; 196262af557SGuo Chao struct resource *r; 197262af557SGuo Chao s64 rc; 198262af557SGuo Chao 199262af557SGuo Chao /* Configure the default M64 BAR */ 200262af557SGuo Chao rc = opal_pci_set_phb_mem_window(phb->opal_id, 201262af557SGuo Chao OPAL_M64_WINDOW_TYPE, 202262af557SGuo Chao phb->ioda.m64_bar_idx, 203262af557SGuo Chao phb->ioda.m64_base, 204262af557SGuo Chao 0, /* unused */ 205262af557SGuo Chao phb->ioda.m64_size); 206262af557SGuo Chao if (rc != OPAL_SUCCESS) { 207262af557SGuo Chao desc = "configuring"; 208262af557SGuo Chao goto fail; 209262af557SGuo Chao } 210262af557SGuo Chao 211262af557SGuo Chao /* Enable the default M64 BAR */ 212262af557SGuo Chao rc = opal_pci_phb_mmio_enable(phb->opal_id, 213262af557SGuo Chao OPAL_M64_WINDOW_TYPE, 214262af557SGuo Chao phb->ioda.m64_bar_idx, 215262af557SGuo Chao OPAL_ENABLE_M64_SPLIT); 216262af557SGuo Chao if (rc != OPAL_SUCCESS) { 217262af557SGuo Chao desc = "enabling"; 218262af557SGuo Chao goto fail; 219262af557SGuo Chao } 220262af557SGuo Chao 221262af557SGuo Chao /* 22263803c39SGavin Shan * Exclude the segments for reserved and root bus PE, which 22363803c39SGavin Shan * are first or last two PEs. 224262af557SGuo Chao */ 225262af557SGuo Chao r = &phb->hose->mem_resources[1]; 22692b8f137SGavin Shan if (phb->ioda.reserved_pe_idx == 0) 22763803c39SGavin Shan r->start += (2 * phb->ioda.m64_segsize); 22892b8f137SGavin Shan else if (phb->ioda.reserved_pe_idx == (phb->ioda.total_pe_num - 1)) 22963803c39SGavin Shan r->end -= (2 * phb->ioda.m64_segsize); 230262af557SGuo Chao else 2311f52f176SRussell Currey pr_warn(" Cannot strip M64 segment for reserved PE#%x\n", 23292b8f137SGavin Shan phb->ioda.reserved_pe_idx); 233262af557SGuo Chao 234262af557SGuo Chao return 0; 235262af557SGuo Chao 236262af557SGuo Chao fail: 237262af557SGuo Chao pr_warn(" Failure %lld %s M64 BAR#%d\n", 238262af557SGuo Chao rc, desc, phb->ioda.m64_bar_idx); 239262af557SGuo Chao opal_pci_phb_mmio_enable(phb->opal_id, 240262af557SGuo Chao OPAL_M64_WINDOW_TYPE, 241262af557SGuo Chao phb->ioda.m64_bar_idx, 242262af557SGuo Chao OPAL_DISABLE_M64); 243262af557SGuo Chao return -EIO; 244262af557SGuo Chao } 245262af557SGuo Chao 246c430670aSGavin Shan static void pnv_ioda_reserve_dev_m64_pe(struct pci_dev *pdev, 24796a2f92bSGavin Shan unsigned long *pe_bitmap) 248262af557SGuo Chao { 24996a2f92bSGavin Shan struct pci_controller *hose = pci_bus_to_host(pdev->bus); 25096a2f92bSGavin Shan struct pnv_phb *phb = hose->private_data; 251262af557SGuo Chao struct resource *r; 25296a2f92bSGavin Shan resource_size_t base, sgsz, start, end; 25396a2f92bSGavin Shan int segno, i; 254262af557SGuo Chao 25596a2f92bSGavin Shan base = phb->ioda.m64_base; 25696a2f92bSGavin Shan sgsz = phb->ioda.m64_segsize; 25796a2f92bSGavin Shan for (i = 0; i <= PCI_ROM_RESOURCE; i++) { 25896a2f92bSGavin Shan r = &pdev->resource[i]; 2595958d19aSBenjamin Herrenschmidt if (!r->parent || !pnv_pci_is_m64(phb, r)) 260262af557SGuo Chao continue; 261262af557SGuo Chao 26296a2f92bSGavin Shan start = _ALIGN_DOWN(r->start - base, sgsz); 26396a2f92bSGavin Shan end = _ALIGN_UP(r->end - base, sgsz); 26496a2f92bSGavin Shan for (segno = start / sgsz; segno < end / sgsz; segno++) { 26596a2f92bSGavin Shan if (pe_bitmap) 26696a2f92bSGavin Shan set_bit(segno, pe_bitmap); 26796a2f92bSGavin Shan else 26896a2f92bSGavin Shan pnv_ioda_reserve_pe(phb, segno); 269262af557SGuo Chao } 270262af557SGuo Chao } 271262af557SGuo Chao } 272262af557SGuo Chao 27399451551SGavin Shan static int pnv_ioda1_init_m64(struct pnv_phb *phb) 27499451551SGavin Shan { 27599451551SGavin Shan struct resource *r; 27699451551SGavin Shan int index; 27799451551SGavin Shan 27899451551SGavin Shan /* 27999451551SGavin Shan * There are 16 M64 BARs, each of which has 8 segments. So 28099451551SGavin Shan * there are as many M64 segments as the maximum number of 28199451551SGavin Shan * PEs, which is 128. 28299451551SGavin Shan */ 28399451551SGavin Shan for (index = 0; index < PNV_IODA1_M64_NUM; index++) { 28499451551SGavin Shan unsigned long base, segsz = phb->ioda.m64_segsize; 28599451551SGavin Shan int64_t rc; 28699451551SGavin Shan 28799451551SGavin Shan base = phb->ioda.m64_base + 28899451551SGavin Shan index * PNV_IODA1_M64_SEGS * segsz; 28999451551SGavin Shan rc = opal_pci_set_phb_mem_window(phb->opal_id, 29099451551SGavin Shan OPAL_M64_WINDOW_TYPE, index, base, 0, 29199451551SGavin Shan PNV_IODA1_M64_SEGS * segsz); 29299451551SGavin Shan if (rc != OPAL_SUCCESS) { 2931f52f176SRussell Currey pr_warn(" Error %lld setting M64 PHB#%x-BAR#%d\n", 29499451551SGavin Shan rc, phb->hose->global_number, index); 29599451551SGavin Shan goto fail; 29699451551SGavin Shan } 29799451551SGavin Shan 29899451551SGavin Shan rc = opal_pci_phb_mmio_enable(phb->opal_id, 29999451551SGavin Shan OPAL_M64_WINDOW_TYPE, index, 30099451551SGavin Shan OPAL_ENABLE_M64_SPLIT); 30199451551SGavin Shan if (rc != OPAL_SUCCESS) { 3021f52f176SRussell Currey pr_warn(" Error %lld enabling M64 PHB#%x-BAR#%d\n", 30399451551SGavin Shan rc, phb->hose->global_number, index); 30499451551SGavin Shan goto fail; 30599451551SGavin Shan } 30699451551SGavin Shan } 30799451551SGavin Shan 30899451551SGavin Shan /* 30963803c39SGavin Shan * Exclude the segments for reserved and root bus PE, which 31063803c39SGavin Shan * are first or last two PEs. 31199451551SGavin Shan */ 31299451551SGavin Shan r = &phb->hose->mem_resources[1]; 31399451551SGavin Shan if (phb->ioda.reserved_pe_idx == 0) 31463803c39SGavin Shan r->start += (2 * phb->ioda.m64_segsize); 31599451551SGavin Shan else if (phb->ioda.reserved_pe_idx == (phb->ioda.total_pe_num - 1)) 31663803c39SGavin Shan r->end -= (2 * phb->ioda.m64_segsize); 31799451551SGavin Shan else 3181f52f176SRussell Currey WARN(1, "Wrong reserved PE#%x on PHB#%x\n", 31999451551SGavin Shan phb->ioda.reserved_pe_idx, phb->hose->global_number); 32099451551SGavin Shan 32199451551SGavin Shan return 0; 32299451551SGavin Shan 32399451551SGavin Shan fail: 32499451551SGavin Shan for ( ; index >= 0; index--) 32599451551SGavin Shan opal_pci_phb_mmio_enable(phb->opal_id, 32699451551SGavin Shan OPAL_M64_WINDOW_TYPE, index, OPAL_DISABLE_M64); 32799451551SGavin Shan 32899451551SGavin Shan return -EIO; 32999451551SGavin Shan } 33099451551SGavin Shan 331c430670aSGavin Shan static void pnv_ioda_reserve_m64_pe(struct pci_bus *bus, 33296a2f92bSGavin Shan unsigned long *pe_bitmap, 33396a2f92bSGavin Shan bool all) 334262af557SGuo Chao { 335262af557SGuo Chao struct pci_dev *pdev; 33696a2f92bSGavin Shan 33796a2f92bSGavin Shan list_for_each_entry(pdev, &bus->devices, bus_list) { 338c430670aSGavin Shan pnv_ioda_reserve_dev_m64_pe(pdev, pe_bitmap); 33996a2f92bSGavin Shan 34096a2f92bSGavin Shan if (all && pdev->subordinate) 341c430670aSGavin Shan pnv_ioda_reserve_m64_pe(pdev->subordinate, 34296a2f92bSGavin Shan pe_bitmap, all); 34396a2f92bSGavin Shan } 34496a2f92bSGavin Shan } 34596a2f92bSGavin Shan 3461e916772SGavin Shan static struct pnv_ioda_pe *pnv_ioda_pick_m64_pe(struct pci_bus *bus, bool all) 347262af557SGuo Chao { 34826ba248dSGavin Shan struct pci_controller *hose = pci_bus_to_host(bus); 34926ba248dSGavin Shan struct pnv_phb *phb = hose->private_data; 350262af557SGuo Chao struct pnv_ioda_pe *master_pe, *pe; 351262af557SGuo Chao unsigned long size, *pe_alloc; 35226ba248dSGavin Shan int i; 353262af557SGuo Chao 354262af557SGuo Chao /* Root bus shouldn't use M64 */ 355262af557SGuo Chao if (pci_is_root_bus(bus)) 3561e916772SGavin Shan return NULL; 357262af557SGuo Chao 358262af557SGuo Chao /* Allocate bitmap */ 35992b8f137SGavin Shan size = _ALIGN_UP(phb->ioda.total_pe_num / 8, sizeof(unsigned long)); 360262af557SGuo Chao pe_alloc = kzalloc(size, GFP_KERNEL); 361262af557SGuo Chao if (!pe_alloc) { 362262af557SGuo Chao pr_warn("%s: Out of memory !\n", 363262af557SGuo Chao __func__); 3641e916772SGavin Shan return NULL; 365262af557SGuo Chao } 366262af557SGuo Chao 36726ba248dSGavin Shan /* Figure out reserved PE numbers by the PE */ 368c430670aSGavin Shan pnv_ioda_reserve_m64_pe(bus, pe_alloc, all); 369262af557SGuo Chao 370262af557SGuo Chao /* 371262af557SGuo Chao * the current bus might not own M64 window and that's all 372262af557SGuo Chao * contributed by its child buses. For the case, we needn't 373262af557SGuo Chao * pick M64 dependent PE#. 374262af557SGuo Chao */ 37592b8f137SGavin Shan if (bitmap_empty(pe_alloc, phb->ioda.total_pe_num)) { 376262af557SGuo Chao kfree(pe_alloc); 3771e916772SGavin Shan return NULL; 378262af557SGuo Chao } 379262af557SGuo Chao 380262af557SGuo Chao /* 381262af557SGuo Chao * Figure out the master PE and put all slave PEs to master 382262af557SGuo Chao * PE's list to form compound PE. 383262af557SGuo Chao */ 384262af557SGuo Chao master_pe = NULL; 385262af557SGuo Chao i = -1; 38692b8f137SGavin Shan while ((i = find_next_bit(pe_alloc, phb->ioda.total_pe_num, i + 1)) < 38792b8f137SGavin Shan phb->ioda.total_pe_num) { 388262af557SGuo Chao pe = &phb->ioda.pe_array[i]; 389262af557SGuo Chao 39093289d8cSGavin Shan phb->ioda.m64_segmap[pe->pe_number] = pe->pe_number; 391262af557SGuo Chao if (!master_pe) { 392262af557SGuo Chao pe->flags |= PNV_IODA_PE_MASTER; 393262af557SGuo Chao INIT_LIST_HEAD(&pe->slaves); 394262af557SGuo Chao master_pe = pe; 395262af557SGuo Chao } else { 396262af557SGuo Chao pe->flags |= PNV_IODA_PE_SLAVE; 397262af557SGuo Chao pe->master = master_pe; 398262af557SGuo Chao list_add_tail(&pe->list, &master_pe->slaves); 399262af557SGuo Chao } 40099451551SGavin Shan 40199451551SGavin Shan /* 40299451551SGavin Shan * P7IOC supports M64DT, which helps mapping M64 segment 40399451551SGavin Shan * to one particular PE#. However, PHB3 has fixed mapping 40499451551SGavin Shan * between M64 segment and PE#. In order to have same logic 40599451551SGavin Shan * for P7IOC and PHB3, we enforce fixed mapping between M64 40699451551SGavin Shan * segment and PE# on P7IOC. 40799451551SGavin Shan */ 40899451551SGavin Shan if (phb->type == PNV_PHB_IODA1) { 40999451551SGavin Shan int64_t rc; 41099451551SGavin Shan 41199451551SGavin Shan rc = opal_pci_map_pe_mmio_window(phb->opal_id, 41299451551SGavin Shan pe->pe_number, OPAL_M64_WINDOW_TYPE, 41399451551SGavin Shan pe->pe_number / PNV_IODA1_M64_SEGS, 41499451551SGavin Shan pe->pe_number % PNV_IODA1_M64_SEGS); 41599451551SGavin Shan if (rc != OPAL_SUCCESS) 4161f52f176SRussell Currey pr_warn("%s: Error %lld mapping M64 for PHB#%x-PE#%x\n", 41799451551SGavin Shan __func__, rc, phb->hose->global_number, 41899451551SGavin Shan pe->pe_number); 41999451551SGavin Shan } 420262af557SGuo Chao } 421262af557SGuo Chao 422262af557SGuo Chao kfree(pe_alloc); 4231e916772SGavin Shan return master_pe; 424262af557SGuo Chao } 425262af557SGuo Chao 426262af557SGuo Chao static void __init pnv_ioda_parse_m64_window(struct pnv_phb *phb) 427262af557SGuo Chao { 428262af557SGuo Chao struct pci_controller *hose = phb->hose; 429262af557SGuo Chao struct device_node *dn = hose->dn; 430262af557SGuo Chao struct resource *res; 431a1339fafSBenjamin Herrenschmidt u32 m64_range[2], i; 4320e7736c6SGavin Shan const __be32 *r; 433262af557SGuo Chao u64 pci_addr; 434262af557SGuo Chao 43599451551SGavin Shan if (phb->type != PNV_PHB_IODA1 && phb->type != PNV_PHB_IODA2) { 4361665c4a8SGavin Shan pr_info(" Not support M64 window\n"); 4371665c4a8SGavin Shan return; 4381665c4a8SGavin Shan } 4391665c4a8SGavin Shan 440e4d54f71SStewart Smith if (!firmware_has_feature(FW_FEATURE_OPAL)) { 441262af557SGuo Chao pr_info(" Firmware too old to support M64 window\n"); 442262af557SGuo Chao return; 443262af557SGuo Chao } 444262af557SGuo Chao 445262af557SGuo Chao r = of_get_property(dn, "ibm,opal-m64-window", NULL); 446262af557SGuo Chao if (!r) { 447b7c670d6SRob Herring pr_info(" No <ibm,opal-m64-window> on %pOF\n", 448b7c670d6SRob Herring dn); 449262af557SGuo Chao return; 450262af557SGuo Chao } 451262af557SGuo Chao 452a1339fafSBenjamin Herrenschmidt /* 453a1339fafSBenjamin Herrenschmidt * Find the available M64 BAR range and pickup the last one for 454a1339fafSBenjamin Herrenschmidt * covering the whole 64-bits space. We support only one range. 455a1339fafSBenjamin Herrenschmidt */ 456a1339fafSBenjamin Herrenschmidt if (of_property_read_u32_array(dn, "ibm,opal-available-m64-ranges", 457a1339fafSBenjamin Herrenschmidt m64_range, 2)) { 458a1339fafSBenjamin Herrenschmidt /* In absence of the property, assume 0..15 */ 459a1339fafSBenjamin Herrenschmidt m64_range[0] = 0; 460a1339fafSBenjamin Herrenschmidt m64_range[1] = 16; 461a1339fafSBenjamin Herrenschmidt } 462a1339fafSBenjamin Herrenschmidt /* We only support 64 bits in our allocator */ 463a1339fafSBenjamin Herrenschmidt if (m64_range[1] > 63) { 464a1339fafSBenjamin Herrenschmidt pr_warn("%s: Limiting M64 range to 63 (from %d) on PHB#%x\n", 465a1339fafSBenjamin Herrenschmidt __func__, m64_range[1], phb->hose->global_number); 466a1339fafSBenjamin Herrenschmidt m64_range[1] = 63; 467a1339fafSBenjamin Herrenschmidt } 468a1339fafSBenjamin Herrenschmidt /* Empty range, no m64 */ 469a1339fafSBenjamin Herrenschmidt if (m64_range[1] <= m64_range[0]) { 470a1339fafSBenjamin Herrenschmidt pr_warn("%s: M64 empty, disabling M64 usage on PHB#%x\n", 471a1339fafSBenjamin Herrenschmidt __func__, phb->hose->global_number); 472a1339fafSBenjamin Herrenschmidt return; 473a1339fafSBenjamin Herrenschmidt } 474a1339fafSBenjamin Herrenschmidt 475a1339fafSBenjamin Herrenschmidt /* Configure M64 informations */ 476262af557SGuo Chao res = &hose->mem_resources[1]; 477e80c4e7cSGavin Shan res->name = dn->full_name; 478262af557SGuo Chao res->start = of_translate_address(dn, r + 2); 479262af557SGuo Chao res->end = res->start + of_read_number(r + 4, 2) - 1; 480262af557SGuo Chao res->flags = (IORESOURCE_MEM | IORESOURCE_MEM_64 | IORESOURCE_PREFETCH); 481262af557SGuo Chao pci_addr = of_read_number(r, 2); 482262af557SGuo Chao hose->mem_offset[1] = res->start - pci_addr; 483262af557SGuo Chao 484262af557SGuo Chao phb->ioda.m64_size = resource_size(res); 48592b8f137SGavin Shan phb->ioda.m64_segsize = phb->ioda.m64_size / phb->ioda.total_pe_num; 486262af557SGuo Chao phb->ioda.m64_base = pci_addr; 487262af557SGuo Chao 488a1339fafSBenjamin Herrenschmidt /* This lines up nicely with the display from processing OF ranges */ 489a1339fafSBenjamin Herrenschmidt pr_info(" MEM 0x%016llx..0x%016llx -> 0x%016llx (M64 #%d..%d)\n", 490a1339fafSBenjamin Herrenschmidt res->start, res->end, pci_addr, m64_range[0], 491a1339fafSBenjamin Herrenschmidt m64_range[0] + m64_range[1] - 1); 492a1339fafSBenjamin Herrenschmidt 493a1339fafSBenjamin Herrenschmidt /* Mark all M64 used up by default */ 494a1339fafSBenjamin Herrenschmidt phb->ioda.m64_bar_alloc = (unsigned long)-1; 495e9863e68SWei Yang 496262af557SGuo Chao /* Use last M64 BAR to cover M64 window */ 497a1339fafSBenjamin Herrenschmidt m64_range[1]--; 498a1339fafSBenjamin Herrenschmidt phb->ioda.m64_bar_idx = m64_range[0] + m64_range[1]; 499a1339fafSBenjamin Herrenschmidt 500a1339fafSBenjamin Herrenschmidt pr_info(" Using M64 #%d as default window\n", phb->ioda.m64_bar_idx); 501a1339fafSBenjamin Herrenschmidt 502a1339fafSBenjamin Herrenschmidt /* Mark remaining ones free */ 503a1339fafSBenjamin Herrenschmidt for (i = m64_range[0]; i < m64_range[1]; i++) 504a1339fafSBenjamin Herrenschmidt clear_bit(i, &phb->ioda.m64_bar_alloc); 505a1339fafSBenjamin Herrenschmidt 506a1339fafSBenjamin Herrenschmidt /* 507a1339fafSBenjamin Herrenschmidt * Setup init functions for M64 based on IODA version, IODA3 uses 508a1339fafSBenjamin Herrenschmidt * the IODA2 code. 509a1339fafSBenjamin Herrenschmidt */ 51099451551SGavin Shan if (phb->type == PNV_PHB_IODA1) 51199451551SGavin Shan phb->init_m64 = pnv_ioda1_init_m64; 51299451551SGavin Shan else 513262af557SGuo Chao phb->init_m64 = pnv_ioda2_init_m64; 514c430670aSGavin Shan phb->reserve_m64_pe = pnv_ioda_reserve_m64_pe; 515c430670aSGavin Shan phb->pick_m64_pe = pnv_ioda_pick_m64_pe; 516262af557SGuo Chao } 517262af557SGuo Chao 51849dec922SGavin Shan static void pnv_ioda_freeze_pe(struct pnv_phb *phb, int pe_no) 51949dec922SGavin Shan { 52049dec922SGavin Shan struct pnv_ioda_pe *pe = &phb->ioda.pe_array[pe_no]; 52149dec922SGavin Shan struct pnv_ioda_pe *slave; 52249dec922SGavin Shan s64 rc; 52349dec922SGavin Shan 52449dec922SGavin Shan /* Fetch master PE */ 52549dec922SGavin Shan if (pe->flags & PNV_IODA_PE_SLAVE) { 52649dec922SGavin Shan pe = pe->master; 527ec8e4e9dSGavin Shan if (WARN_ON(!pe || !(pe->flags & PNV_IODA_PE_MASTER))) 528ec8e4e9dSGavin Shan return; 529ec8e4e9dSGavin Shan 53049dec922SGavin Shan pe_no = pe->pe_number; 53149dec922SGavin Shan } 53249dec922SGavin Shan 53349dec922SGavin Shan /* Freeze master PE */ 53449dec922SGavin Shan rc = opal_pci_eeh_freeze_set(phb->opal_id, 53549dec922SGavin Shan pe_no, 53649dec922SGavin Shan OPAL_EEH_ACTION_SET_FREEZE_ALL); 53749dec922SGavin Shan if (rc != OPAL_SUCCESS) { 53849dec922SGavin Shan pr_warn("%s: Failure %lld freezing PHB#%x-PE#%x\n", 53949dec922SGavin Shan __func__, rc, phb->hose->global_number, pe_no); 54049dec922SGavin Shan return; 54149dec922SGavin Shan } 54249dec922SGavin Shan 54349dec922SGavin Shan /* Freeze slave PEs */ 54449dec922SGavin Shan if (!(pe->flags & PNV_IODA_PE_MASTER)) 54549dec922SGavin Shan return; 54649dec922SGavin Shan 54749dec922SGavin Shan list_for_each_entry(slave, &pe->slaves, list) { 54849dec922SGavin Shan rc = opal_pci_eeh_freeze_set(phb->opal_id, 54949dec922SGavin Shan slave->pe_number, 55049dec922SGavin Shan OPAL_EEH_ACTION_SET_FREEZE_ALL); 55149dec922SGavin Shan if (rc != OPAL_SUCCESS) 55249dec922SGavin Shan pr_warn("%s: Failure %lld freezing PHB#%x-PE#%x\n", 55349dec922SGavin Shan __func__, rc, phb->hose->global_number, 55449dec922SGavin Shan slave->pe_number); 55549dec922SGavin Shan } 55649dec922SGavin Shan } 55749dec922SGavin Shan 558e51df2c1SAnton Blanchard static int pnv_ioda_unfreeze_pe(struct pnv_phb *phb, int pe_no, int opt) 55949dec922SGavin Shan { 56049dec922SGavin Shan struct pnv_ioda_pe *pe, *slave; 56149dec922SGavin Shan s64 rc; 56249dec922SGavin Shan 56349dec922SGavin Shan /* Find master PE */ 56449dec922SGavin Shan pe = &phb->ioda.pe_array[pe_no]; 56549dec922SGavin Shan if (pe->flags & PNV_IODA_PE_SLAVE) { 56649dec922SGavin Shan pe = pe->master; 56749dec922SGavin Shan WARN_ON(!pe || !(pe->flags & PNV_IODA_PE_MASTER)); 56849dec922SGavin Shan pe_no = pe->pe_number; 56949dec922SGavin Shan } 57049dec922SGavin Shan 57149dec922SGavin Shan /* Clear frozen state for master PE */ 57249dec922SGavin Shan rc = opal_pci_eeh_freeze_clear(phb->opal_id, pe_no, opt); 57349dec922SGavin Shan if (rc != OPAL_SUCCESS) { 57449dec922SGavin Shan pr_warn("%s: Failure %lld clear %d on PHB#%x-PE#%x\n", 57549dec922SGavin Shan __func__, rc, opt, phb->hose->global_number, pe_no); 57649dec922SGavin Shan return -EIO; 57749dec922SGavin Shan } 57849dec922SGavin Shan 57949dec922SGavin Shan if (!(pe->flags & PNV_IODA_PE_MASTER)) 58049dec922SGavin Shan return 0; 58149dec922SGavin Shan 58249dec922SGavin Shan /* Clear frozen state for slave PEs */ 58349dec922SGavin Shan list_for_each_entry(slave, &pe->slaves, list) { 58449dec922SGavin Shan rc = opal_pci_eeh_freeze_clear(phb->opal_id, 58549dec922SGavin Shan slave->pe_number, 58649dec922SGavin Shan opt); 58749dec922SGavin Shan if (rc != OPAL_SUCCESS) { 58849dec922SGavin Shan pr_warn("%s: Failure %lld clear %d on PHB#%x-PE#%x\n", 58949dec922SGavin Shan __func__, rc, opt, phb->hose->global_number, 59049dec922SGavin Shan slave->pe_number); 59149dec922SGavin Shan return -EIO; 59249dec922SGavin Shan } 59349dec922SGavin Shan } 59449dec922SGavin Shan 59549dec922SGavin Shan return 0; 59649dec922SGavin Shan } 59749dec922SGavin Shan 59849dec922SGavin Shan static int pnv_ioda_get_pe_state(struct pnv_phb *phb, int pe_no) 59949dec922SGavin Shan { 60049dec922SGavin Shan struct pnv_ioda_pe *slave, *pe; 60149dec922SGavin Shan u8 fstate, state; 60249dec922SGavin Shan __be16 pcierr; 60349dec922SGavin Shan s64 rc; 60449dec922SGavin Shan 60549dec922SGavin Shan /* Sanity check on PE number */ 60692b8f137SGavin Shan if (pe_no < 0 || pe_no >= phb->ioda.total_pe_num) 60749dec922SGavin Shan return OPAL_EEH_STOPPED_PERM_UNAVAIL; 60849dec922SGavin Shan 60949dec922SGavin Shan /* 61049dec922SGavin Shan * Fetch the master PE and the PE instance might be 61149dec922SGavin Shan * not initialized yet. 61249dec922SGavin Shan */ 61349dec922SGavin Shan pe = &phb->ioda.pe_array[pe_no]; 61449dec922SGavin Shan if (pe->flags & PNV_IODA_PE_SLAVE) { 61549dec922SGavin Shan pe = pe->master; 61649dec922SGavin Shan WARN_ON(!pe || !(pe->flags & PNV_IODA_PE_MASTER)); 61749dec922SGavin Shan pe_no = pe->pe_number; 61849dec922SGavin Shan } 61949dec922SGavin Shan 62049dec922SGavin Shan /* Check the master PE */ 62149dec922SGavin Shan rc = opal_pci_eeh_freeze_status(phb->opal_id, pe_no, 62249dec922SGavin Shan &state, &pcierr, NULL); 62349dec922SGavin Shan if (rc != OPAL_SUCCESS) { 62449dec922SGavin Shan pr_warn("%s: Failure %lld getting " 62549dec922SGavin Shan "PHB#%x-PE#%x state\n", 62649dec922SGavin Shan __func__, rc, 62749dec922SGavin Shan phb->hose->global_number, pe_no); 62849dec922SGavin Shan return OPAL_EEH_STOPPED_TEMP_UNAVAIL; 62949dec922SGavin Shan } 63049dec922SGavin Shan 63149dec922SGavin Shan /* Check the slave PE */ 63249dec922SGavin Shan if (!(pe->flags & PNV_IODA_PE_MASTER)) 63349dec922SGavin Shan return state; 63449dec922SGavin Shan 63549dec922SGavin Shan list_for_each_entry(slave, &pe->slaves, list) { 63649dec922SGavin Shan rc = opal_pci_eeh_freeze_status(phb->opal_id, 63749dec922SGavin Shan slave->pe_number, 63849dec922SGavin Shan &fstate, 63949dec922SGavin Shan &pcierr, 64049dec922SGavin Shan NULL); 64149dec922SGavin Shan if (rc != OPAL_SUCCESS) { 64249dec922SGavin Shan pr_warn("%s: Failure %lld getting " 64349dec922SGavin Shan "PHB#%x-PE#%x state\n", 64449dec922SGavin Shan __func__, rc, 64549dec922SGavin Shan phb->hose->global_number, slave->pe_number); 64649dec922SGavin Shan return OPAL_EEH_STOPPED_TEMP_UNAVAIL; 64749dec922SGavin Shan } 64849dec922SGavin Shan 64949dec922SGavin Shan /* 65049dec922SGavin Shan * Override the result based on the ascending 65149dec922SGavin Shan * priority. 65249dec922SGavin Shan */ 65349dec922SGavin Shan if (fstate > state) 65449dec922SGavin Shan state = fstate; 65549dec922SGavin Shan } 65649dec922SGavin Shan 65749dec922SGavin Shan return state; 65849dec922SGavin Shan } 65949dec922SGavin Shan 660184cd4a3SBenjamin Herrenschmidt /* Currently those 2 are only used when MSIs are enabled, this will change 661184cd4a3SBenjamin Herrenschmidt * but in the meantime, we need to protect them to avoid warnings 662184cd4a3SBenjamin Herrenschmidt */ 663184cd4a3SBenjamin Herrenschmidt #ifdef CONFIG_PCI_MSI 664f456834aSIan Munsie struct pnv_ioda_pe *pnv_ioda_get_pe(struct pci_dev *dev) 665184cd4a3SBenjamin Herrenschmidt { 666184cd4a3SBenjamin Herrenschmidt struct pci_controller *hose = pci_bus_to_host(dev->bus); 667184cd4a3SBenjamin Herrenschmidt struct pnv_phb *phb = hose->private_data; 668b72c1f65SBenjamin Herrenschmidt struct pci_dn *pdn = pci_get_pdn(dev); 669184cd4a3SBenjamin Herrenschmidt 670184cd4a3SBenjamin Herrenschmidt if (!pdn) 671184cd4a3SBenjamin Herrenschmidt return NULL; 672184cd4a3SBenjamin Herrenschmidt if (pdn->pe_number == IODA_INVALID_PE) 673184cd4a3SBenjamin Herrenschmidt return NULL; 674184cd4a3SBenjamin Herrenschmidt return &phb->ioda.pe_array[pdn->pe_number]; 675184cd4a3SBenjamin Herrenschmidt } 676184cd4a3SBenjamin Herrenschmidt #endif /* CONFIG_PCI_MSI */ 677184cd4a3SBenjamin Herrenschmidt 678b131a842SGavin Shan static int pnv_ioda_set_one_peltv(struct pnv_phb *phb, 679b131a842SGavin Shan struct pnv_ioda_pe *parent, 680b131a842SGavin Shan struct pnv_ioda_pe *child, 681b131a842SGavin Shan bool is_add) 682b131a842SGavin Shan { 683b131a842SGavin Shan const char *desc = is_add ? "adding" : "removing"; 684b131a842SGavin Shan uint8_t op = is_add ? OPAL_ADD_PE_TO_DOMAIN : 685b131a842SGavin Shan OPAL_REMOVE_PE_FROM_DOMAIN; 686b131a842SGavin Shan struct pnv_ioda_pe *slave; 687b131a842SGavin Shan long rc; 688b131a842SGavin Shan 689b131a842SGavin Shan /* Parent PE affects child PE */ 690b131a842SGavin Shan rc = opal_pci_set_peltv(phb->opal_id, parent->pe_number, 691b131a842SGavin Shan child->pe_number, op); 692b131a842SGavin Shan if (rc != OPAL_SUCCESS) { 693b131a842SGavin Shan pe_warn(child, "OPAL error %ld %s to parent PELTV\n", 694b131a842SGavin Shan rc, desc); 695b131a842SGavin Shan return -ENXIO; 696b131a842SGavin Shan } 697b131a842SGavin Shan 698b131a842SGavin Shan if (!(child->flags & PNV_IODA_PE_MASTER)) 699b131a842SGavin Shan return 0; 700b131a842SGavin Shan 701b131a842SGavin Shan /* Compound case: parent PE affects slave PEs */ 702b131a842SGavin Shan list_for_each_entry(slave, &child->slaves, list) { 703b131a842SGavin Shan rc = opal_pci_set_peltv(phb->opal_id, parent->pe_number, 704b131a842SGavin Shan slave->pe_number, op); 705b131a842SGavin Shan if (rc != OPAL_SUCCESS) { 706b131a842SGavin Shan pe_warn(slave, "OPAL error %ld %s to parent PELTV\n", 707b131a842SGavin Shan rc, desc); 708b131a842SGavin Shan return -ENXIO; 709b131a842SGavin Shan } 710b131a842SGavin Shan } 711b131a842SGavin Shan 712b131a842SGavin Shan return 0; 713b131a842SGavin Shan } 714b131a842SGavin Shan 715b131a842SGavin Shan static int pnv_ioda_set_peltv(struct pnv_phb *phb, 716b131a842SGavin Shan struct pnv_ioda_pe *pe, 717b131a842SGavin Shan bool is_add) 718b131a842SGavin Shan { 719b131a842SGavin Shan struct pnv_ioda_pe *slave; 720781a868fSWei Yang struct pci_dev *pdev = NULL; 721b131a842SGavin Shan int ret; 722b131a842SGavin Shan 723b131a842SGavin Shan /* 724b131a842SGavin Shan * Clear PE frozen state. If it's master PE, we need 725b131a842SGavin Shan * clear slave PE frozen state as well. 726b131a842SGavin Shan */ 727b131a842SGavin Shan if (is_add) { 728b131a842SGavin Shan opal_pci_eeh_freeze_clear(phb->opal_id, pe->pe_number, 729b131a842SGavin Shan OPAL_EEH_ACTION_CLEAR_FREEZE_ALL); 730b131a842SGavin Shan if (pe->flags & PNV_IODA_PE_MASTER) { 731b131a842SGavin Shan list_for_each_entry(slave, &pe->slaves, list) 732b131a842SGavin Shan opal_pci_eeh_freeze_clear(phb->opal_id, 733b131a842SGavin Shan slave->pe_number, 734b131a842SGavin Shan OPAL_EEH_ACTION_CLEAR_FREEZE_ALL); 735b131a842SGavin Shan } 736b131a842SGavin Shan } 737b131a842SGavin Shan 738b131a842SGavin Shan /* 739b131a842SGavin Shan * Associate PE in PELT. We need add the PE into the 740b131a842SGavin Shan * corresponding PELT-V as well. Otherwise, the error 741b131a842SGavin Shan * originated from the PE might contribute to other 742b131a842SGavin Shan * PEs. 743b131a842SGavin Shan */ 744b131a842SGavin Shan ret = pnv_ioda_set_one_peltv(phb, pe, pe, is_add); 745b131a842SGavin Shan if (ret) 746b131a842SGavin Shan return ret; 747b131a842SGavin Shan 748b131a842SGavin Shan /* For compound PEs, any one affects all of them */ 749b131a842SGavin Shan if (pe->flags & PNV_IODA_PE_MASTER) { 750b131a842SGavin Shan list_for_each_entry(slave, &pe->slaves, list) { 751b131a842SGavin Shan ret = pnv_ioda_set_one_peltv(phb, slave, pe, is_add); 752b131a842SGavin Shan if (ret) 753b131a842SGavin Shan return ret; 754b131a842SGavin Shan } 755b131a842SGavin Shan } 756b131a842SGavin Shan 757b131a842SGavin Shan if (pe->flags & (PNV_IODA_PE_BUS_ALL | PNV_IODA_PE_BUS)) 758b131a842SGavin Shan pdev = pe->pbus->self; 759781a868fSWei Yang else if (pe->flags & PNV_IODA_PE_DEV) 760b131a842SGavin Shan pdev = pe->pdev->bus->self; 761781a868fSWei Yang #ifdef CONFIG_PCI_IOV 762781a868fSWei Yang else if (pe->flags & PNV_IODA_PE_VF) 763283e2d8aSGavin Shan pdev = pe->parent_dev; 764781a868fSWei Yang #endif /* CONFIG_PCI_IOV */ 765b131a842SGavin Shan while (pdev) { 766b131a842SGavin Shan struct pci_dn *pdn = pci_get_pdn(pdev); 767b131a842SGavin Shan struct pnv_ioda_pe *parent; 768b131a842SGavin Shan 769b131a842SGavin Shan if (pdn && pdn->pe_number != IODA_INVALID_PE) { 770b131a842SGavin Shan parent = &phb->ioda.pe_array[pdn->pe_number]; 771b131a842SGavin Shan ret = pnv_ioda_set_one_peltv(phb, parent, pe, is_add); 772b131a842SGavin Shan if (ret) 773b131a842SGavin Shan return ret; 774b131a842SGavin Shan } 775b131a842SGavin Shan 776b131a842SGavin Shan pdev = pdev->bus->self; 777b131a842SGavin Shan } 778b131a842SGavin Shan 779b131a842SGavin Shan return 0; 780b131a842SGavin Shan } 781b131a842SGavin Shan 782781a868fSWei Yang static int pnv_ioda_deconfigure_pe(struct pnv_phb *phb, struct pnv_ioda_pe *pe) 783781a868fSWei Yang { 784781a868fSWei Yang struct pci_dev *parent; 785781a868fSWei Yang uint8_t bcomp, dcomp, fcomp; 786781a868fSWei Yang int64_t rc; 787781a868fSWei Yang long rid_end, rid; 788781a868fSWei Yang 789781a868fSWei Yang /* Currently, we just deconfigure VF PE. Bus PE will always there.*/ 790781a868fSWei Yang if (pe->pbus) { 791781a868fSWei Yang int count; 792781a868fSWei Yang 793781a868fSWei Yang dcomp = OPAL_IGNORE_RID_DEVICE_NUMBER; 794781a868fSWei Yang fcomp = OPAL_IGNORE_RID_FUNCTION_NUMBER; 795781a868fSWei Yang parent = pe->pbus->self; 796781a868fSWei Yang if (pe->flags & PNV_IODA_PE_BUS_ALL) 797781a868fSWei Yang count = pe->pbus->busn_res.end - pe->pbus->busn_res.start + 1; 798781a868fSWei Yang else 799781a868fSWei Yang count = 1; 800781a868fSWei Yang 801781a868fSWei Yang switch(count) { 802781a868fSWei Yang case 1: bcomp = OpalPciBusAll; break; 803781a868fSWei Yang case 2: bcomp = OpalPciBus7Bits; break; 804781a868fSWei Yang case 4: bcomp = OpalPciBus6Bits; break; 805781a868fSWei Yang case 8: bcomp = OpalPciBus5Bits; break; 806781a868fSWei Yang case 16: bcomp = OpalPciBus4Bits; break; 807781a868fSWei Yang case 32: bcomp = OpalPciBus3Bits; break; 808781a868fSWei Yang default: 809781a868fSWei Yang dev_err(&pe->pbus->dev, "Number of subordinate buses %d unsupported\n", 810781a868fSWei Yang count); 811781a868fSWei Yang /* Do an exact match only */ 812781a868fSWei Yang bcomp = OpalPciBusAll; 813781a868fSWei Yang } 814781a868fSWei Yang rid_end = pe->rid + (count << 8); 815781a868fSWei Yang } else { 81693e01a50SGavin Shan #ifdef CONFIG_PCI_IOV 817781a868fSWei Yang if (pe->flags & PNV_IODA_PE_VF) 818781a868fSWei Yang parent = pe->parent_dev; 819781a868fSWei Yang else 82093e01a50SGavin Shan #endif 821781a868fSWei Yang parent = pe->pdev->bus->self; 822781a868fSWei Yang bcomp = OpalPciBusAll; 823781a868fSWei Yang dcomp = OPAL_COMPARE_RID_DEVICE_NUMBER; 824781a868fSWei Yang fcomp = OPAL_COMPARE_RID_FUNCTION_NUMBER; 825781a868fSWei Yang rid_end = pe->rid + 1; 826781a868fSWei Yang } 827781a868fSWei Yang 828781a868fSWei Yang /* Clear the reverse map */ 829781a868fSWei Yang for (rid = pe->rid; rid < rid_end; rid++) 830c127562aSGavin Shan phb->ioda.pe_rmap[rid] = IODA_INVALID_PE; 831781a868fSWei Yang 832781a868fSWei Yang /* Release from all parents PELT-V */ 833781a868fSWei Yang while (parent) { 834781a868fSWei Yang struct pci_dn *pdn = pci_get_pdn(parent); 835781a868fSWei Yang if (pdn && pdn->pe_number != IODA_INVALID_PE) { 836781a868fSWei Yang rc = opal_pci_set_peltv(phb->opal_id, pdn->pe_number, 837781a868fSWei Yang pe->pe_number, OPAL_REMOVE_PE_FROM_DOMAIN); 838781a868fSWei Yang /* XXX What to do in case of error ? */ 839781a868fSWei Yang } 840781a868fSWei Yang parent = parent->bus->self; 841781a868fSWei Yang } 842781a868fSWei Yang 843f951e510SGavin Shan opal_pci_eeh_freeze_clear(phb->opal_id, pe->pe_number, 844781a868fSWei Yang OPAL_EEH_ACTION_CLEAR_FREEZE_ALL); 845781a868fSWei Yang 846781a868fSWei Yang /* Disassociate PE in PELT */ 847781a868fSWei Yang rc = opal_pci_set_peltv(phb->opal_id, pe->pe_number, 848781a868fSWei Yang pe->pe_number, OPAL_REMOVE_PE_FROM_DOMAIN); 849781a868fSWei Yang if (rc) 850781a868fSWei Yang pe_warn(pe, "OPAL error %ld remove self from PELTV\n", rc); 851781a868fSWei Yang rc = opal_pci_set_pe(phb->opal_id, pe->pe_number, pe->rid, 852781a868fSWei Yang bcomp, dcomp, fcomp, OPAL_UNMAP_PE); 853781a868fSWei Yang if (rc) 854781a868fSWei Yang pe_err(pe, "OPAL error %ld trying to setup PELT table\n", rc); 855781a868fSWei Yang 856781a868fSWei Yang pe->pbus = NULL; 857781a868fSWei Yang pe->pdev = NULL; 85893e01a50SGavin Shan #ifdef CONFIG_PCI_IOV 859781a868fSWei Yang pe->parent_dev = NULL; 86093e01a50SGavin Shan #endif 861781a868fSWei Yang 862781a868fSWei Yang return 0; 863781a868fSWei Yang } 864781a868fSWei Yang 865cad5cef6SGreg Kroah-Hartman static int pnv_ioda_configure_pe(struct pnv_phb *phb, struct pnv_ioda_pe *pe) 866184cd4a3SBenjamin Herrenschmidt { 867184cd4a3SBenjamin Herrenschmidt struct pci_dev *parent; 868184cd4a3SBenjamin Herrenschmidt uint8_t bcomp, dcomp, fcomp; 869184cd4a3SBenjamin Herrenschmidt long rc, rid_end, rid; 870184cd4a3SBenjamin Herrenschmidt 871184cd4a3SBenjamin Herrenschmidt /* Bus validation ? */ 872184cd4a3SBenjamin Herrenschmidt if (pe->pbus) { 873184cd4a3SBenjamin Herrenschmidt int count; 874184cd4a3SBenjamin Herrenschmidt 875184cd4a3SBenjamin Herrenschmidt dcomp = OPAL_IGNORE_RID_DEVICE_NUMBER; 876184cd4a3SBenjamin Herrenschmidt fcomp = OPAL_IGNORE_RID_FUNCTION_NUMBER; 877184cd4a3SBenjamin Herrenschmidt parent = pe->pbus->self; 878fb446ad0SGavin Shan if (pe->flags & PNV_IODA_PE_BUS_ALL) 879b918c62eSYinghai Lu count = pe->pbus->busn_res.end - pe->pbus->busn_res.start + 1; 880fb446ad0SGavin Shan else 881fb446ad0SGavin Shan count = 1; 882fb446ad0SGavin Shan 883184cd4a3SBenjamin Herrenschmidt switch(count) { 884184cd4a3SBenjamin Herrenschmidt case 1: bcomp = OpalPciBusAll; break; 885184cd4a3SBenjamin Herrenschmidt case 2: bcomp = OpalPciBus7Bits; break; 886184cd4a3SBenjamin Herrenschmidt case 4: bcomp = OpalPciBus6Bits; break; 887184cd4a3SBenjamin Herrenschmidt case 8: bcomp = OpalPciBus5Bits; break; 888184cd4a3SBenjamin Herrenschmidt case 16: bcomp = OpalPciBus4Bits; break; 889184cd4a3SBenjamin Herrenschmidt case 32: bcomp = OpalPciBus3Bits; break; 890184cd4a3SBenjamin Herrenschmidt default: 891781a868fSWei Yang dev_err(&pe->pbus->dev, "Number of subordinate buses %d unsupported\n", 892781a868fSWei Yang count); 893184cd4a3SBenjamin Herrenschmidt /* Do an exact match only */ 894184cd4a3SBenjamin Herrenschmidt bcomp = OpalPciBusAll; 895184cd4a3SBenjamin Herrenschmidt } 896184cd4a3SBenjamin Herrenschmidt rid_end = pe->rid + (count << 8); 897184cd4a3SBenjamin Herrenschmidt } else { 898781a868fSWei Yang #ifdef CONFIG_PCI_IOV 899781a868fSWei Yang if (pe->flags & PNV_IODA_PE_VF) 900781a868fSWei Yang parent = pe->parent_dev; 901781a868fSWei Yang else 902781a868fSWei Yang #endif /* CONFIG_PCI_IOV */ 903184cd4a3SBenjamin Herrenschmidt parent = pe->pdev->bus->self; 904184cd4a3SBenjamin Herrenschmidt bcomp = OpalPciBusAll; 905184cd4a3SBenjamin Herrenschmidt dcomp = OPAL_COMPARE_RID_DEVICE_NUMBER; 906184cd4a3SBenjamin Herrenschmidt fcomp = OPAL_COMPARE_RID_FUNCTION_NUMBER; 907184cd4a3SBenjamin Herrenschmidt rid_end = pe->rid + 1; 908184cd4a3SBenjamin Herrenschmidt } 909184cd4a3SBenjamin Herrenschmidt 910631ad691SGavin Shan /* 911631ad691SGavin Shan * Associate PE in PELT. We need add the PE into the 912631ad691SGavin Shan * corresponding PELT-V as well. Otherwise, the error 913631ad691SGavin Shan * originated from the PE might contribute to other 914631ad691SGavin Shan * PEs. 915631ad691SGavin Shan */ 916184cd4a3SBenjamin Herrenschmidt rc = opal_pci_set_pe(phb->opal_id, pe->pe_number, pe->rid, 917184cd4a3SBenjamin Herrenschmidt bcomp, dcomp, fcomp, OPAL_MAP_PE); 918184cd4a3SBenjamin Herrenschmidt if (rc) { 919184cd4a3SBenjamin Herrenschmidt pe_err(pe, "OPAL error %ld trying to setup PELT table\n", rc); 920184cd4a3SBenjamin Herrenschmidt return -ENXIO; 921184cd4a3SBenjamin Herrenschmidt } 922631ad691SGavin Shan 9235d2aa710SAlistair Popple /* 9245d2aa710SAlistair Popple * Configure PELTV. NPUs don't have a PELTV table so skip 9255d2aa710SAlistair Popple * configuration on them. 9265d2aa710SAlistair Popple */ 9275d2aa710SAlistair Popple if (phb->type != PNV_PHB_NPU) 928b131a842SGavin Shan pnv_ioda_set_peltv(phb, pe, true); 929184cd4a3SBenjamin Herrenschmidt 930184cd4a3SBenjamin Herrenschmidt /* Setup reverse map */ 931184cd4a3SBenjamin Herrenschmidt for (rid = pe->rid; rid < rid_end; rid++) 932184cd4a3SBenjamin Herrenschmidt phb->ioda.pe_rmap[rid] = pe->pe_number; 933184cd4a3SBenjamin Herrenschmidt 934184cd4a3SBenjamin Herrenschmidt /* Setup one MVTs on IODA1 */ 9354773f76bSGavin Shan if (phb->type != PNV_PHB_IODA1) { 9364773f76bSGavin Shan pe->mve_number = 0; 9374773f76bSGavin Shan goto out; 9384773f76bSGavin Shan } 9394773f76bSGavin Shan 940184cd4a3SBenjamin Herrenschmidt pe->mve_number = pe->pe_number; 9414773f76bSGavin Shan rc = opal_pci_set_mve(phb->opal_id, pe->mve_number, pe->pe_number); 9424773f76bSGavin Shan if (rc != OPAL_SUCCESS) { 9431f52f176SRussell Currey pe_err(pe, "OPAL error %ld setting up MVE %x\n", 944184cd4a3SBenjamin Herrenschmidt rc, pe->mve_number); 945184cd4a3SBenjamin Herrenschmidt pe->mve_number = -1; 946184cd4a3SBenjamin Herrenschmidt } else { 947184cd4a3SBenjamin Herrenschmidt rc = opal_pci_set_mve_enable(phb->opal_id, 948cee72d5bSBenjamin Herrenschmidt pe->mve_number, OPAL_ENABLE_MVE); 949184cd4a3SBenjamin Herrenschmidt if (rc) { 9501f52f176SRussell Currey pe_err(pe, "OPAL error %ld enabling MVE %x\n", 951184cd4a3SBenjamin Herrenschmidt rc, pe->mve_number); 952184cd4a3SBenjamin Herrenschmidt pe->mve_number = -1; 953184cd4a3SBenjamin Herrenschmidt } 954184cd4a3SBenjamin Herrenschmidt } 955184cd4a3SBenjamin Herrenschmidt 9564773f76bSGavin Shan out: 957184cd4a3SBenjamin Herrenschmidt return 0; 958184cd4a3SBenjamin Herrenschmidt } 959184cd4a3SBenjamin Herrenschmidt 960781a868fSWei Yang #ifdef CONFIG_PCI_IOV 961781a868fSWei Yang static int pnv_pci_vf_resource_shift(struct pci_dev *dev, int offset) 962781a868fSWei Yang { 963781a868fSWei Yang struct pci_dn *pdn = pci_get_pdn(dev); 964781a868fSWei Yang int i; 965781a868fSWei Yang struct resource *res, res2; 966781a868fSWei Yang resource_size_t size; 967781a868fSWei Yang u16 num_vfs; 968781a868fSWei Yang 969781a868fSWei Yang if (!dev->is_physfn) 970781a868fSWei Yang return -EINVAL; 971781a868fSWei Yang 972781a868fSWei Yang /* 973781a868fSWei Yang * "offset" is in VFs. The M64 windows are sized so that when they 974781a868fSWei Yang * are segmented, each segment is the same size as the IOV BAR. 975781a868fSWei Yang * Each segment is in a separate PE, and the high order bits of the 976781a868fSWei Yang * address are the PE number. Therefore, each VF's BAR is in a 977781a868fSWei Yang * separate PE, and changing the IOV BAR start address changes the 978781a868fSWei Yang * range of PEs the VFs are in. 979781a868fSWei Yang */ 980781a868fSWei Yang num_vfs = pdn->num_vfs; 981781a868fSWei Yang for (i = 0; i < PCI_SRIOV_NUM_BARS; i++) { 982781a868fSWei Yang res = &dev->resource[i + PCI_IOV_RESOURCES]; 983781a868fSWei Yang if (!res->flags || !res->parent) 984781a868fSWei Yang continue; 985781a868fSWei Yang 986781a868fSWei Yang /* 987781a868fSWei Yang * The actual IOV BAR range is determined by the start address 988781a868fSWei Yang * and the actual size for num_vfs VFs BAR. This check is to 989781a868fSWei Yang * make sure that after shifting, the range will not overlap 990781a868fSWei Yang * with another device. 991781a868fSWei Yang */ 992781a868fSWei Yang size = pci_iov_resource_size(dev, i + PCI_IOV_RESOURCES); 993781a868fSWei Yang res2.flags = res->flags; 994781a868fSWei Yang res2.start = res->start + (size * offset); 995781a868fSWei Yang res2.end = res2.start + (size * num_vfs) - 1; 996781a868fSWei Yang 997781a868fSWei Yang if (res2.end > res->end) { 998781a868fSWei Yang dev_err(&dev->dev, "VF BAR%d: %pR would extend past %pR (trying to enable %d VFs shifted by %d)\n", 999781a868fSWei Yang i, &res2, res, num_vfs, offset); 1000781a868fSWei Yang return -EBUSY; 1001781a868fSWei Yang } 1002781a868fSWei Yang } 1003781a868fSWei Yang 1004781a868fSWei Yang /* 1005781a868fSWei Yang * After doing so, there would be a "hole" in the /proc/iomem when 1006781a868fSWei Yang * offset is a positive value. It looks like the device return some 1007781a868fSWei Yang * mmio back to the system, which actually no one could use it. 1008781a868fSWei Yang */ 1009781a868fSWei Yang for (i = 0; i < PCI_SRIOV_NUM_BARS; i++) { 1010781a868fSWei Yang res = &dev->resource[i + PCI_IOV_RESOURCES]; 1011781a868fSWei Yang if (!res->flags || !res->parent) 1012781a868fSWei Yang continue; 1013781a868fSWei Yang 1014781a868fSWei Yang size = pci_iov_resource_size(dev, i + PCI_IOV_RESOURCES); 1015781a868fSWei Yang res2 = *res; 1016781a868fSWei Yang res->start += size * offset; 1017781a868fSWei Yang 101874703cc4SWei Yang dev_info(&dev->dev, "VF BAR%d: %pR shifted to %pR (%sabling %d VFs shifted by %d)\n", 101974703cc4SWei Yang i, &res2, res, (offset > 0) ? "En" : "Dis", 102074703cc4SWei Yang num_vfs, offset); 1021781a868fSWei Yang pci_update_resource(dev, i + PCI_IOV_RESOURCES); 1022781a868fSWei Yang } 1023781a868fSWei Yang return 0; 1024781a868fSWei Yang } 1025781a868fSWei Yang #endif /* CONFIG_PCI_IOV */ 1026781a868fSWei Yang 1027cad5cef6SGreg Kroah-Hartman static struct pnv_ioda_pe *pnv_ioda_setup_dev_PE(struct pci_dev *dev) 1028184cd4a3SBenjamin Herrenschmidt { 1029184cd4a3SBenjamin Herrenschmidt struct pci_controller *hose = pci_bus_to_host(dev->bus); 1030184cd4a3SBenjamin Herrenschmidt struct pnv_phb *phb = hose->private_data; 1031b72c1f65SBenjamin Herrenschmidt struct pci_dn *pdn = pci_get_pdn(dev); 1032184cd4a3SBenjamin Herrenschmidt struct pnv_ioda_pe *pe; 1033184cd4a3SBenjamin Herrenschmidt 1034184cd4a3SBenjamin Herrenschmidt if (!pdn) { 1035184cd4a3SBenjamin Herrenschmidt pr_err("%s: Device tree node not associated properly\n", 1036184cd4a3SBenjamin Herrenschmidt pci_name(dev)); 1037184cd4a3SBenjamin Herrenschmidt return NULL; 1038184cd4a3SBenjamin Herrenschmidt } 1039184cd4a3SBenjamin Herrenschmidt if (pdn->pe_number != IODA_INVALID_PE) 1040184cd4a3SBenjamin Herrenschmidt return NULL; 1041184cd4a3SBenjamin Herrenschmidt 10421e916772SGavin Shan pe = pnv_ioda_alloc_pe(phb); 10431e916772SGavin Shan if (!pe) { 1044184cd4a3SBenjamin Herrenschmidt pr_warning("%s: Not enough PE# available, disabling device\n", 1045184cd4a3SBenjamin Herrenschmidt pci_name(dev)); 1046184cd4a3SBenjamin Herrenschmidt return NULL; 1047184cd4a3SBenjamin Herrenschmidt } 1048184cd4a3SBenjamin Herrenschmidt 1049184cd4a3SBenjamin Herrenschmidt /* NOTE: We get only one ref to the pci_dev for the pdn, not for the 1050184cd4a3SBenjamin Herrenschmidt * pointer in the PE data structure, both should be destroyed at the 1051184cd4a3SBenjamin Herrenschmidt * same time. However, this needs to be looked at more closely again 1052184cd4a3SBenjamin Herrenschmidt * once we actually start removing things (Hotplug, SR-IOV, ...) 1053184cd4a3SBenjamin Herrenschmidt * 1054184cd4a3SBenjamin Herrenschmidt * At some point we want to remove the PDN completely anyways 1055184cd4a3SBenjamin Herrenschmidt */ 1056184cd4a3SBenjamin Herrenschmidt pci_dev_get(dev); 1057184cd4a3SBenjamin Herrenschmidt pdn->pcidev = dev; 10581e916772SGavin Shan pdn->pe_number = pe->pe_number; 10595d2aa710SAlistair Popple pe->flags = PNV_IODA_PE_DEV; 1060184cd4a3SBenjamin Herrenschmidt pe->pdev = dev; 1061184cd4a3SBenjamin Herrenschmidt pe->pbus = NULL; 1062184cd4a3SBenjamin Herrenschmidt pe->mve_number = -1; 1063184cd4a3SBenjamin Herrenschmidt pe->rid = dev->bus->number << 8 | pdn->devfn; 1064184cd4a3SBenjamin Herrenschmidt 1065184cd4a3SBenjamin Herrenschmidt pe_info(pe, "Associated device to PE\n"); 1066184cd4a3SBenjamin Herrenschmidt 1067184cd4a3SBenjamin Herrenschmidt if (pnv_ioda_configure_pe(phb, pe)) { 1068184cd4a3SBenjamin Herrenschmidt /* XXX What do we do here ? */ 10691e916772SGavin Shan pnv_ioda_free_pe(pe); 1070184cd4a3SBenjamin Herrenschmidt pdn->pe_number = IODA_INVALID_PE; 1071184cd4a3SBenjamin Herrenschmidt pe->pdev = NULL; 1072184cd4a3SBenjamin Herrenschmidt pci_dev_put(dev); 1073184cd4a3SBenjamin Herrenschmidt return NULL; 1074184cd4a3SBenjamin Herrenschmidt } 1075184cd4a3SBenjamin Herrenschmidt 10761d4e89cfSAlexey Kardashevskiy /* Put PE to the list */ 10771d4e89cfSAlexey Kardashevskiy list_add_tail(&pe->list, &phb->ioda.pe_list); 10781d4e89cfSAlexey Kardashevskiy 1079184cd4a3SBenjamin Herrenschmidt return pe; 1080184cd4a3SBenjamin Herrenschmidt } 1081184cd4a3SBenjamin Herrenschmidt 1082184cd4a3SBenjamin Herrenschmidt static void pnv_ioda_setup_same_PE(struct pci_bus *bus, struct pnv_ioda_pe *pe) 1083184cd4a3SBenjamin Herrenschmidt { 1084184cd4a3SBenjamin Herrenschmidt struct pci_dev *dev; 1085184cd4a3SBenjamin Herrenschmidt 1086184cd4a3SBenjamin Herrenschmidt list_for_each_entry(dev, &bus->devices, bus_list) { 1087b72c1f65SBenjamin Herrenschmidt struct pci_dn *pdn = pci_get_pdn(dev); 1088184cd4a3SBenjamin Herrenschmidt 1089184cd4a3SBenjamin Herrenschmidt if (pdn == NULL) { 1090184cd4a3SBenjamin Herrenschmidt pr_warn("%s: No device node associated with device !\n", 1091184cd4a3SBenjamin Herrenschmidt pci_name(dev)); 1092184cd4a3SBenjamin Herrenschmidt continue; 1093184cd4a3SBenjamin Herrenschmidt } 1094ccd1c191SGavin Shan 1095ccd1c191SGavin Shan /* 1096ccd1c191SGavin Shan * In partial hotplug case, the PCI device might be still 1097ccd1c191SGavin Shan * associated with the PE and needn't attach it to the PE 1098ccd1c191SGavin Shan * again. 1099ccd1c191SGavin Shan */ 1100ccd1c191SGavin Shan if (pdn->pe_number != IODA_INVALID_PE) 1101ccd1c191SGavin Shan continue; 1102ccd1c191SGavin Shan 1103c5f7700bSGavin Shan pe->device_count++; 110494973b24SAlistair Popple pdn->pcidev = dev; 1105184cd4a3SBenjamin Herrenschmidt pdn->pe_number = pe->pe_number; 1106fb446ad0SGavin Shan if ((pe->flags & PNV_IODA_PE_BUS_ALL) && dev->subordinate) 1107184cd4a3SBenjamin Herrenschmidt pnv_ioda_setup_same_PE(dev->subordinate, pe); 1108184cd4a3SBenjamin Herrenschmidt } 1109184cd4a3SBenjamin Herrenschmidt } 1110184cd4a3SBenjamin Herrenschmidt 1111fb446ad0SGavin Shan /* 1112fb446ad0SGavin Shan * There're 2 types of PCI bus sensitive PEs: One that is compromised of 1113fb446ad0SGavin Shan * single PCI bus. Another one that contains the primary PCI bus and its 1114fb446ad0SGavin Shan * subordinate PCI devices and buses. The second type of PE is normally 1115fb446ad0SGavin Shan * orgiriated by PCIe-to-PCI bridge or PLX switch downstream ports. 1116fb446ad0SGavin Shan */ 11171e916772SGavin Shan static struct pnv_ioda_pe *pnv_ioda_setup_bus_PE(struct pci_bus *bus, bool all) 1118184cd4a3SBenjamin Herrenschmidt { 1119fb446ad0SGavin Shan struct pci_controller *hose = pci_bus_to_host(bus); 1120184cd4a3SBenjamin Herrenschmidt struct pnv_phb *phb = hose->private_data; 11211e916772SGavin Shan struct pnv_ioda_pe *pe = NULL; 1122ccd1c191SGavin Shan unsigned int pe_num; 1123ccd1c191SGavin Shan 1124ccd1c191SGavin Shan /* 1125ccd1c191SGavin Shan * In partial hotplug case, the PE instance might be still alive. 1126ccd1c191SGavin Shan * We should reuse it instead of allocating a new one. 1127ccd1c191SGavin Shan */ 1128ccd1c191SGavin Shan pe_num = phb->ioda.pe_rmap[bus->number << 8]; 1129ccd1c191SGavin Shan if (pe_num != IODA_INVALID_PE) { 1130ccd1c191SGavin Shan pe = &phb->ioda.pe_array[pe_num]; 1131ccd1c191SGavin Shan pnv_ioda_setup_same_PE(bus, pe); 1132ccd1c191SGavin Shan return NULL; 1133ccd1c191SGavin Shan } 1134184cd4a3SBenjamin Herrenschmidt 113563803c39SGavin Shan /* PE number for root bus should have been reserved */ 113663803c39SGavin Shan if (pci_is_root_bus(bus) && 113763803c39SGavin Shan phb->ioda.root_pe_idx != IODA_INVALID_PE) 113863803c39SGavin Shan pe = &phb->ioda.pe_array[phb->ioda.root_pe_idx]; 113963803c39SGavin Shan 1140262af557SGuo Chao /* Check if PE is determined by M64 */ 114163803c39SGavin Shan if (!pe && phb->pick_m64_pe) 11421e916772SGavin Shan pe = phb->pick_m64_pe(bus, all); 1143262af557SGuo Chao 1144262af557SGuo Chao /* The PE number isn't pinned by M64 */ 11451e916772SGavin Shan if (!pe) 11461e916772SGavin Shan pe = pnv_ioda_alloc_pe(phb); 1147262af557SGuo Chao 11481e916772SGavin Shan if (!pe) { 1149fb446ad0SGavin Shan pr_warning("%s: Not enough PE# available for PCI bus %04x:%02x\n", 1150fb446ad0SGavin Shan __func__, pci_domain_nr(bus), bus->number); 11511e916772SGavin Shan return NULL; 1152184cd4a3SBenjamin Herrenschmidt } 1153184cd4a3SBenjamin Herrenschmidt 1154262af557SGuo Chao pe->flags |= (all ? PNV_IODA_PE_BUS_ALL : PNV_IODA_PE_BUS); 1155184cd4a3SBenjamin Herrenschmidt pe->pbus = bus; 1156184cd4a3SBenjamin Herrenschmidt pe->pdev = NULL; 1157184cd4a3SBenjamin Herrenschmidt pe->mve_number = -1; 1158b918c62eSYinghai Lu pe->rid = bus->busn_res.start << 8; 1159184cd4a3SBenjamin Herrenschmidt 1160fb446ad0SGavin Shan if (all) 11611f52f176SRussell Currey pe_info(pe, "Secondary bus %d..%d associated with PE#%x\n", 11621e916772SGavin Shan bus->busn_res.start, bus->busn_res.end, pe->pe_number); 1163fb446ad0SGavin Shan else 11641f52f176SRussell Currey pe_info(pe, "Secondary bus %d associated with PE#%x\n", 11651e916772SGavin Shan bus->busn_res.start, pe->pe_number); 1166184cd4a3SBenjamin Herrenschmidt 1167184cd4a3SBenjamin Herrenschmidt if (pnv_ioda_configure_pe(phb, pe)) { 1168184cd4a3SBenjamin Herrenschmidt /* XXX What do we do here ? */ 11691e916772SGavin Shan pnv_ioda_free_pe(pe); 1170184cd4a3SBenjamin Herrenschmidt pe->pbus = NULL; 11711e916772SGavin Shan return NULL; 1172184cd4a3SBenjamin Herrenschmidt } 1173184cd4a3SBenjamin Herrenschmidt 1174184cd4a3SBenjamin Herrenschmidt /* Associate it with all child devices */ 1175184cd4a3SBenjamin Herrenschmidt pnv_ioda_setup_same_PE(bus, pe); 1176184cd4a3SBenjamin Herrenschmidt 11777ebdf956SGavin Shan /* Put PE to the list */ 11787ebdf956SGavin Shan list_add_tail(&pe->list, &phb->ioda.pe_list); 11791e916772SGavin Shan 11801e916772SGavin Shan return pe; 1181184cd4a3SBenjamin Herrenschmidt } 1182184cd4a3SBenjamin Herrenschmidt 1183b521549aSAlistair Popple static struct pnv_ioda_pe *pnv_ioda_setup_npu_PE(struct pci_dev *npu_pdev) 11845d2aa710SAlistair Popple { 1185b521549aSAlistair Popple int pe_num, found_pe = false, rc; 1186b521549aSAlistair Popple long rid; 1187b521549aSAlistair Popple struct pnv_ioda_pe *pe; 1188b521549aSAlistair Popple struct pci_dev *gpu_pdev; 1189b521549aSAlistair Popple struct pci_dn *npu_pdn; 1190b521549aSAlistair Popple struct pci_controller *hose = pci_bus_to_host(npu_pdev->bus); 1191b521549aSAlistair Popple struct pnv_phb *phb = hose->private_data; 1192b521549aSAlistair Popple 1193b521549aSAlistair Popple /* 1194b521549aSAlistair Popple * Due to a hardware errata PE#0 on the NPU is reserved for 1195b521549aSAlistair Popple * error handling. This means we only have three PEs remaining 1196b521549aSAlistair Popple * which need to be assigned to four links, implying some 1197b521549aSAlistair Popple * links must share PEs. 1198b521549aSAlistair Popple * 1199b521549aSAlistair Popple * To achieve this we assign PEs such that NPUs linking the 1200b521549aSAlistair Popple * same GPU get assigned the same PE. 1201b521549aSAlistair Popple */ 1202b521549aSAlistair Popple gpu_pdev = pnv_pci_get_gpu_dev(npu_pdev); 120392b8f137SGavin Shan for (pe_num = 0; pe_num < phb->ioda.total_pe_num; pe_num++) { 1204b521549aSAlistair Popple pe = &phb->ioda.pe_array[pe_num]; 1205b521549aSAlistair Popple if (!pe->pdev) 1206b521549aSAlistair Popple continue; 1207b521549aSAlistair Popple 1208b521549aSAlistair Popple if (pnv_pci_get_gpu_dev(pe->pdev) == gpu_pdev) { 1209b521549aSAlistair Popple /* 1210b521549aSAlistair Popple * This device has the same peer GPU so should 1211b521549aSAlistair Popple * be assigned the same PE as the existing 1212b521549aSAlistair Popple * peer NPU. 1213b521549aSAlistair Popple */ 1214b521549aSAlistair Popple dev_info(&npu_pdev->dev, 12151f52f176SRussell Currey "Associating to existing PE %x\n", pe_num); 1216b521549aSAlistair Popple pci_dev_get(npu_pdev); 1217b521549aSAlistair Popple npu_pdn = pci_get_pdn(npu_pdev); 1218b521549aSAlistair Popple rid = npu_pdev->bus->number << 8 | npu_pdn->devfn; 1219b521549aSAlistair Popple npu_pdn->pcidev = npu_pdev; 1220b521549aSAlistair Popple npu_pdn->pe_number = pe_num; 1221b521549aSAlistair Popple phb->ioda.pe_rmap[rid] = pe->pe_number; 1222b521549aSAlistair Popple 1223b521549aSAlistair Popple /* Map the PE to this link */ 1224b521549aSAlistair Popple rc = opal_pci_set_pe(phb->opal_id, pe_num, rid, 1225b521549aSAlistair Popple OpalPciBusAll, 1226b521549aSAlistair Popple OPAL_COMPARE_RID_DEVICE_NUMBER, 1227b521549aSAlistair Popple OPAL_COMPARE_RID_FUNCTION_NUMBER, 1228b521549aSAlistair Popple OPAL_MAP_PE); 1229b521549aSAlistair Popple WARN_ON(rc != OPAL_SUCCESS); 1230b521549aSAlistair Popple found_pe = true; 1231b521549aSAlistair Popple break; 1232b521549aSAlistair Popple } 1233b521549aSAlistair Popple } 1234b521549aSAlistair Popple 1235b521549aSAlistair Popple if (!found_pe) 1236b521549aSAlistair Popple /* 1237b521549aSAlistair Popple * Could not find an existing PE so allocate a new 1238b521549aSAlistair Popple * one. 1239b521549aSAlistair Popple */ 1240b521549aSAlistair Popple return pnv_ioda_setup_dev_PE(npu_pdev); 1241b521549aSAlistair Popple else 1242b521549aSAlistair Popple return pe; 1243b521549aSAlistair Popple } 1244b521549aSAlistair Popple 1245b521549aSAlistair Popple static void pnv_ioda_setup_npu_PEs(struct pci_bus *bus) 1246b521549aSAlistair Popple { 12475d2aa710SAlistair Popple struct pci_dev *pdev; 12485d2aa710SAlistair Popple 12495d2aa710SAlistair Popple list_for_each_entry(pdev, &bus->devices, bus_list) 1250b521549aSAlistair Popple pnv_ioda_setup_npu_PE(pdev); 12515d2aa710SAlistair Popple } 12525d2aa710SAlistair Popple 1253cad5cef6SGreg Kroah-Hartman static void pnv_pci_ioda_setup_PEs(void) 1254fb446ad0SGavin Shan { 1255fb446ad0SGavin Shan struct pci_controller *hose, *tmp; 1256262af557SGuo Chao struct pnv_phb *phb; 1257fb446ad0SGavin Shan 1258fb446ad0SGavin Shan list_for_each_entry_safe(hose, tmp, &hose_list, list_node) { 1259262af557SGuo Chao phb = hose->private_data; 126008f48f32SAlistair Popple if (phb->type == PNV_PHB_NPU) { 126108f48f32SAlistair Popple /* PE#0 is needed for error reporting */ 126208f48f32SAlistair Popple pnv_ioda_reserve_pe(phb, 0); 1263b521549aSAlistair Popple pnv_ioda_setup_npu_PEs(hose->bus); 12641ab66d1fSAlistair Popple if (phb->model == PNV_PHB_MODEL_NPU2) 12651ab66d1fSAlistair Popple pnv_npu2_init(phb); 1266ccd1c191SGavin Shan } 1267fb446ad0SGavin Shan } 1268fb446ad0SGavin Shan } 1269184cd4a3SBenjamin Herrenschmidt 1270a8b2f828SGavin Shan #ifdef CONFIG_PCI_IOV 1271ee8222feSWei Yang static int pnv_pci_vf_release_m64(struct pci_dev *pdev, u16 num_vfs) 1272781a868fSWei Yang { 1273781a868fSWei Yang struct pci_bus *bus; 1274781a868fSWei Yang struct pci_controller *hose; 1275781a868fSWei Yang struct pnv_phb *phb; 1276781a868fSWei Yang struct pci_dn *pdn; 127702639b0eSWei Yang int i, j; 1278ee8222feSWei Yang int m64_bars; 1279781a868fSWei Yang 1280781a868fSWei Yang bus = pdev->bus; 1281781a868fSWei Yang hose = pci_bus_to_host(bus); 1282781a868fSWei Yang phb = hose->private_data; 1283781a868fSWei Yang pdn = pci_get_pdn(pdev); 1284781a868fSWei Yang 1285ee8222feSWei Yang if (pdn->m64_single_mode) 1286ee8222feSWei Yang m64_bars = num_vfs; 1287ee8222feSWei Yang else 1288ee8222feSWei Yang m64_bars = 1; 1289ee8222feSWei Yang 129002639b0eSWei Yang for (i = 0; i < PCI_SRIOV_NUM_BARS; i++) 1291ee8222feSWei Yang for (j = 0; j < m64_bars; j++) { 1292ee8222feSWei Yang if (pdn->m64_map[j][i] == IODA_INVALID_M64) 1293781a868fSWei Yang continue; 1294781a868fSWei Yang opal_pci_phb_mmio_enable(phb->opal_id, 1295ee8222feSWei Yang OPAL_M64_WINDOW_TYPE, pdn->m64_map[j][i], 0); 1296ee8222feSWei Yang clear_bit(pdn->m64_map[j][i], &phb->ioda.m64_bar_alloc); 1297ee8222feSWei Yang pdn->m64_map[j][i] = IODA_INVALID_M64; 1298781a868fSWei Yang } 1299781a868fSWei Yang 1300ee8222feSWei Yang kfree(pdn->m64_map); 1301781a868fSWei Yang return 0; 1302781a868fSWei Yang } 1303781a868fSWei Yang 130402639b0eSWei Yang static int pnv_pci_vf_assign_m64(struct pci_dev *pdev, u16 num_vfs) 1305781a868fSWei Yang { 1306781a868fSWei Yang struct pci_bus *bus; 1307781a868fSWei Yang struct pci_controller *hose; 1308781a868fSWei Yang struct pnv_phb *phb; 1309781a868fSWei Yang struct pci_dn *pdn; 1310781a868fSWei Yang unsigned int win; 1311781a868fSWei Yang struct resource *res; 131202639b0eSWei Yang int i, j; 1313781a868fSWei Yang int64_t rc; 131402639b0eSWei Yang int total_vfs; 131502639b0eSWei Yang resource_size_t size, start; 131602639b0eSWei Yang int pe_num; 1317ee8222feSWei Yang int m64_bars; 1318781a868fSWei Yang 1319781a868fSWei Yang bus = pdev->bus; 1320781a868fSWei Yang hose = pci_bus_to_host(bus); 1321781a868fSWei Yang phb = hose->private_data; 1322781a868fSWei Yang pdn = pci_get_pdn(pdev); 132302639b0eSWei Yang total_vfs = pci_sriov_get_totalvfs(pdev); 1324781a868fSWei Yang 1325ee8222feSWei Yang if (pdn->m64_single_mode) 1326ee8222feSWei Yang m64_bars = num_vfs; 1327ee8222feSWei Yang else 1328ee8222feSWei Yang m64_bars = 1; 132902639b0eSWei Yang 1330fb37e128SMarkus Elfring pdn->m64_map = kmalloc_array(m64_bars, 1331fb37e128SMarkus Elfring sizeof(*pdn->m64_map), 1332fb37e128SMarkus Elfring GFP_KERNEL); 1333ee8222feSWei Yang if (!pdn->m64_map) 1334ee8222feSWei Yang return -ENOMEM; 1335ee8222feSWei Yang /* Initialize the m64_map to IODA_INVALID_M64 */ 1336ee8222feSWei Yang for (i = 0; i < m64_bars ; i++) 1337ee8222feSWei Yang for (j = 0; j < PCI_SRIOV_NUM_BARS; j++) 1338ee8222feSWei Yang pdn->m64_map[i][j] = IODA_INVALID_M64; 1339ee8222feSWei Yang 1340781a868fSWei Yang 1341781a868fSWei Yang for (i = 0; i < PCI_SRIOV_NUM_BARS; i++) { 1342781a868fSWei Yang res = &pdev->resource[i + PCI_IOV_RESOURCES]; 1343781a868fSWei Yang if (!res->flags || !res->parent) 1344781a868fSWei Yang continue; 1345781a868fSWei Yang 1346ee8222feSWei Yang for (j = 0; j < m64_bars; j++) { 1347781a868fSWei Yang do { 1348781a868fSWei Yang win = find_next_zero_bit(&phb->ioda.m64_bar_alloc, 1349781a868fSWei Yang phb->ioda.m64_bar_idx + 1, 0); 1350781a868fSWei Yang 1351781a868fSWei Yang if (win >= phb->ioda.m64_bar_idx + 1) 1352781a868fSWei Yang goto m64_failed; 1353781a868fSWei Yang } while (test_and_set_bit(win, &phb->ioda.m64_bar_alloc)); 1354781a868fSWei Yang 1355ee8222feSWei Yang pdn->m64_map[j][i] = win; 135602639b0eSWei Yang 1357ee8222feSWei Yang if (pdn->m64_single_mode) { 135802639b0eSWei Yang size = pci_iov_resource_size(pdev, 135902639b0eSWei Yang PCI_IOV_RESOURCES + i); 136002639b0eSWei Yang start = res->start + size * j; 136102639b0eSWei Yang } else { 136202639b0eSWei Yang size = resource_size(res); 136302639b0eSWei Yang start = res->start; 136402639b0eSWei Yang } 1365781a868fSWei Yang 1366781a868fSWei Yang /* Map the M64 here */ 1367ee8222feSWei Yang if (pdn->m64_single_mode) { 1368be283eebSWei Yang pe_num = pdn->pe_num_map[j]; 136902639b0eSWei Yang rc = opal_pci_map_pe_mmio_window(phb->opal_id, 137002639b0eSWei Yang pe_num, OPAL_M64_WINDOW_TYPE, 1371ee8222feSWei Yang pdn->m64_map[j][i], 0); 137202639b0eSWei Yang } 137302639b0eSWei Yang 1374781a868fSWei Yang rc = opal_pci_set_phb_mem_window(phb->opal_id, 1375781a868fSWei Yang OPAL_M64_WINDOW_TYPE, 1376ee8222feSWei Yang pdn->m64_map[j][i], 137702639b0eSWei Yang start, 1378781a868fSWei Yang 0, /* unused */ 137902639b0eSWei Yang size); 138002639b0eSWei Yang 138102639b0eSWei Yang 1382781a868fSWei Yang if (rc != OPAL_SUCCESS) { 1383781a868fSWei Yang dev_err(&pdev->dev, "Failed to map M64 window #%d: %lld\n", 1384781a868fSWei Yang win, rc); 1385781a868fSWei Yang goto m64_failed; 1386781a868fSWei Yang } 1387781a868fSWei Yang 1388ee8222feSWei Yang if (pdn->m64_single_mode) 1389781a868fSWei Yang rc = opal_pci_phb_mmio_enable(phb->opal_id, 1390ee8222feSWei Yang OPAL_M64_WINDOW_TYPE, pdn->m64_map[j][i], 2); 139102639b0eSWei Yang else 139202639b0eSWei Yang rc = opal_pci_phb_mmio_enable(phb->opal_id, 1393ee8222feSWei Yang OPAL_M64_WINDOW_TYPE, pdn->m64_map[j][i], 1); 139402639b0eSWei Yang 1395781a868fSWei Yang if (rc != OPAL_SUCCESS) { 1396781a868fSWei Yang dev_err(&pdev->dev, "Failed to enable M64 window #%d: %llx\n", 1397781a868fSWei Yang win, rc); 1398781a868fSWei Yang goto m64_failed; 1399781a868fSWei Yang } 1400781a868fSWei Yang } 140102639b0eSWei Yang } 1402781a868fSWei Yang return 0; 1403781a868fSWei Yang 1404781a868fSWei Yang m64_failed: 1405ee8222feSWei Yang pnv_pci_vf_release_m64(pdev, num_vfs); 1406781a868fSWei Yang return -EBUSY; 1407781a868fSWei Yang } 1408781a868fSWei Yang 1409c035e37bSAlexey Kardashevskiy static long pnv_pci_ioda2_unset_window(struct iommu_table_group *table_group, 1410c035e37bSAlexey Kardashevskiy int num); 1411c035e37bSAlexey Kardashevskiy 1412781a868fSWei Yang static void pnv_pci_ioda2_release_dma_pe(struct pci_dev *dev, struct pnv_ioda_pe *pe) 1413781a868fSWei Yang { 1414781a868fSWei Yang struct iommu_table *tbl; 1415781a868fSWei Yang int64_t rc; 1416781a868fSWei Yang 1417b348aa65SAlexey Kardashevskiy tbl = pe->table_group.tables[0]; 1418c035e37bSAlexey Kardashevskiy rc = pnv_pci_ioda2_unset_window(&pe->table_group, 0); 1419781a868fSWei Yang if (rc) 1420781a868fSWei Yang pe_warn(pe, "OPAL error %ld release DMA window\n", rc); 1421781a868fSWei Yang 1422c035e37bSAlexey Kardashevskiy pnv_pci_ioda2_set_bypass(pe, false); 14230eaf4defSAlexey Kardashevskiy if (pe->table_group.group) { 14240eaf4defSAlexey Kardashevskiy iommu_group_put(pe->table_group.group); 14250eaf4defSAlexey Kardashevskiy BUG_ON(pe->table_group.group); 1426ac9a5889SAlexey Kardashevskiy } 1427e5afdf9dSAlexey Kardashevskiy iommu_tce_table_put(tbl); 1428781a868fSWei Yang } 1429781a868fSWei Yang 1430ee8222feSWei Yang static void pnv_ioda_release_vf_PE(struct pci_dev *pdev) 1431781a868fSWei Yang { 1432781a868fSWei Yang struct pci_bus *bus; 1433781a868fSWei Yang struct pci_controller *hose; 1434781a868fSWei Yang struct pnv_phb *phb; 1435781a868fSWei Yang struct pnv_ioda_pe *pe, *pe_n; 1436781a868fSWei Yang struct pci_dn *pdn; 1437781a868fSWei Yang 1438781a868fSWei Yang bus = pdev->bus; 1439781a868fSWei Yang hose = pci_bus_to_host(bus); 1440781a868fSWei Yang phb = hose->private_data; 144102639b0eSWei Yang pdn = pci_get_pdn(pdev); 1442781a868fSWei Yang 1443781a868fSWei Yang if (!pdev->is_physfn) 1444781a868fSWei Yang return; 1445781a868fSWei Yang 1446781a868fSWei Yang list_for_each_entry_safe(pe, pe_n, &phb->ioda.pe_list, list) { 1447781a868fSWei Yang if (pe->parent_dev != pdev) 1448781a868fSWei Yang continue; 1449781a868fSWei Yang 1450781a868fSWei Yang pnv_pci_ioda2_release_dma_pe(pdev, pe); 1451781a868fSWei Yang 1452781a868fSWei Yang /* Remove from list */ 1453781a868fSWei Yang mutex_lock(&phb->ioda.pe_list_mutex); 1454781a868fSWei Yang list_del(&pe->list); 1455781a868fSWei Yang mutex_unlock(&phb->ioda.pe_list_mutex); 1456781a868fSWei Yang 1457781a868fSWei Yang pnv_ioda_deconfigure_pe(phb, pe); 1458781a868fSWei Yang 14591e916772SGavin Shan pnv_ioda_free_pe(pe); 1460781a868fSWei Yang } 1461781a868fSWei Yang } 1462781a868fSWei Yang 1463781a868fSWei Yang void pnv_pci_sriov_disable(struct pci_dev *pdev) 1464781a868fSWei Yang { 1465781a868fSWei Yang struct pci_bus *bus; 1466781a868fSWei Yang struct pci_controller *hose; 1467781a868fSWei Yang struct pnv_phb *phb; 14681e916772SGavin Shan struct pnv_ioda_pe *pe; 1469781a868fSWei Yang struct pci_dn *pdn; 1470be283eebSWei Yang u16 num_vfs, i; 1471781a868fSWei Yang 1472781a868fSWei Yang bus = pdev->bus; 1473781a868fSWei Yang hose = pci_bus_to_host(bus); 1474781a868fSWei Yang phb = hose->private_data; 1475781a868fSWei Yang pdn = pci_get_pdn(pdev); 1476781a868fSWei Yang num_vfs = pdn->num_vfs; 1477781a868fSWei Yang 1478781a868fSWei Yang /* Release VF PEs */ 1479ee8222feSWei Yang pnv_ioda_release_vf_PE(pdev); 1480781a868fSWei Yang 1481781a868fSWei Yang if (phb->type == PNV_PHB_IODA2) { 1482ee8222feSWei Yang if (!pdn->m64_single_mode) 1483be283eebSWei Yang pnv_pci_vf_resource_shift(pdev, -*pdn->pe_num_map); 1484781a868fSWei Yang 1485781a868fSWei Yang /* Release M64 windows */ 1486ee8222feSWei Yang pnv_pci_vf_release_m64(pdev, num_vfs); 1487781a868fSWei Yang 1488781a868fSWei Yang /* Release PE numbers */ 1489be283eebSWei Yang if (pdn->m64_single_mode) { 1490be283eebSWei Yang for (i = 0; i < num_vfs; i++) { 14911e916772SGavin Shan if (pdn->pe_num_map[i] == IODA_INVALID_PE) 14921e916772SGavin Shan continue; 14931e916772SGavin Shan 14941e916772SGavin Shan pe = &phb->ioda.pe_array[pdn->pe_num_map[i]]; 14951e916772SGavin Shan pnv_ioda_free_pe(pe); 1496be283eebSWei Yang } 1497be283eebSWei Yang } else 1498be283eebSWei Yang bitmap_clear(phb->ioda.pe_alloc, *pdn->pe_num_map, num_vfs); 1499be283eebSWei Yang /* Releasing pe_num_map */ 1500be283eebSWei Yang kfree(pdn->pe_num_map); 1501781a868fSWei Yang } 1502781a868fSWei Yang } 1503781a868fSWei Yang 1504781a868fSWei Yang static void pnv_pci_ioda2_setup_dma_pe(struct pnv_phb *phb, 1505781a868fSWei Yang struct pnv_ioda_pe *pe); 1506781a868fSWei Yang static void pnv_ioda_setup_vf_PE(struct pci_dev *pdev, u16 num_vfs) 1507781a868fSWei Yang { 1508781a868fSWei Yang struct pci_bus *bus; 1509781a868fSWei Yang struct pci_controller *hose; 1510781a868fSWei Yang struct pnv_phb *phb; 1511781a868fSWei Yang struct pnv_ioda_pe *pe; 1512781a868fSWei Yang int pe_num; 1513781a868fSWei Yang u16 vf_index; 1514781a868fSWei Yang struct pci_dn *pdn; 1515781a868fSWei Yang 1516781a868fSWei Yang bus = pdev->bus; 1517781a868fSWei Yang hose = pci_bus_to_host(bus); 1518781a868fSWei Yang phb = hose->private_data; 1519781a868fSWei Yang pdn = pci_get_pdn(pdev); 1520781a868fSWei Yang 1521781a868fSWei Yang if (!pdev->is_physfn) 1522781a868fSWei Yang return; 1523781a868fSWei Yang 1524781a868fSWei Yang /* Reserve PE for each VF */ 1525781a868fSWei Yang for (vf_index = 0; vf_index < num_vfs; vf_index++) { 1526be283eebSWei Yang if (pdn->m64_single_mode) 1527be283eebSWei Yang pe_num = pdn->pe_num_map[vf_index]; 1528be283eebSWei Yang else 1529be283eebSWei Yang pe_num = *pdn->pe_num_map + vf_index; 1530781a868fSWei Yang 1531781a868fSWei Yang pe = &phb->ioda.pe_array[pe_num]; 1532781a868fSWei Yang pe->pe_number = pe_num; 1533781a868fSWei Yang pe->phb = phb; 1534781a868fSWei Yang pe->flags = PNV_IODA_PE_VF; 1535781a868fSWei Yang pe->pbus = NULL; 1536781a868fSWei Yang pe->parent_dev = pdev; 1537781a868fSWei Yang pe->mve_number = -1; 1538781a868fSWei Yang pe->rid = (pci_iov_virtfn_bus(pdev, vf_index) << 8) | 1539781a868fSWei Yang pci_iov_virtfn_devfn(pdev, vf_index); 1540781a868fSWei Yang 15411f52f176SRussell Currey pe_info(pe, "VF %04d:%02d:%02d.%d associated with PE#%x\n", 1542781a868fSWei Yang hose->global_number, pdev->bus->number, 1543781a868fSWei Yang PCI_SLOT(pci_iov_virtfn_devfn(pdev, vf_index)), 1544781a868fSWei Yang PCI_FUNC(pci_iov_virtfn_devfn(pdev, vf_index)), pe_num); 1545781a868fSWei Yang 1546781a868fSWei Yang if (pnv_ioda_configure_pe(phb, pe)) { 1547781a868fSWei Yang /* XXX What do we do here ? */ 15481e916772SGavin Shan pnv_ioda_free_pe(pe); 1549781a868fSWei Yang pe->pdev = NULL; 1550781a868fSWei Yang continue; 1551781a868fSWei Yang } 1552781a868fSWei Yang 1553781a868fSWei Yang /* Put PE to the list */ 1554781a868fSWei Yang mutex_lock(&phb->ioda.pe_list_mutex); 1555781a868fSWei Yang list_add_tail(&pe->list, &phb->ioda.pe_list); 1556781a868fSWei Yang mutex_unlock(&phb->ioda.pe_list_mutex); 1557781a868fSWei Yang 1558781a868fSWei Yang pnv_pci_ioda2_setup_dma_pe(phb, pe); 1559781a868fSWei Yang } 1560781a868fSWei Yang } 1561781a868fSWei Yang 1562781a868fSWei Yang int pnv_pci_sriov_enable(struct pci_dev *pdev, u16 num_vfs) 1563781a868fSWei Yang { 1564781a868fSWei Yang struct pci_bus *bus; 1565781a868fSWei Yang struct pci_controller *hose; 1566781a868fSWei Yang struct pnv_phb *phb; 15671e916772SGavin Shan struct pnv_ioda_pe *pe; 1568781a868fSWei Yang struct pci_dn *pdn; 1569781a868fSWei Yang int ret; 1570be283eebSWei Yang u16 i; 1571781a868fSWei Yang 1572781a868fSWei Yang bus = pdev->bus; 1573781a868fSWei Yang hose = pci_bus_to_host(bus); 1574781a868fSWei Yang phb = hose->private_data; 1575781a868fSWei Yang pdn = pci_get_pdn(pdev); 1576781a868fSWei Yang 1577781a868fSWei Yang if (phb->type == PNV_PHB_IODA2) { 1578b0331854SWei Yang if (!pdn->vfs_expanded) { 1579b0331854SWei Yang dev_info(&pdev->dev, "don't support this SRIOV device" 1580b0331854SWei Yang " with non 64bit-prefetchable IOV BAR\n"); 1581b0331854SWei Yang return -ENOSPC; 1582b0331854SWei Yang } 1583b0331854SWei Yang 1584ee8222feSWei Yang /* 1585ee8222feSWei Yang * When M64 BARs functions in Single PE mode, the number of VFs 1586ee8222feSWei Yang * could be enabled must be less than the number of M64 BARs. 1587ee8222feSWei Yang */ 1588ee8222feSWei Yang if (pdn->m64_single_mode && num_vfs > phb->ioda.m64_bar_idx) { 1589ee8222feSWei Yang dev_info(&pdev->dev, "Not enough M64 BAR for VFs\n"); 1590ee8222feSWei Yang return -EBUSY; 1591ee8222feSWei Yang } 1592ee8222feSWei Yang 1593be283eebSWei Yang /* Allocating pe_num_map */ 1594be283eebSWei Yang if (pdn->m64_single_mode) 1595fb37e128SMarkus Elfring pdn->pe_num_map = kmalloc_array(num_vfs, 1596fb37e128SMarkus Elfring sizeof(*pdn->pe_num_map), 1597be283eebSWei Yang GFP_KERNEL); 1598be283eebSWei Yang else 1599be283eebSWei Yang pdn->pe_num_map = kmalloc(sizeof(*pdn->pe_num_map), GFP_KERNEL); 1600be283eebSWei Yang 1601be283eebSWei Yang if (!pdn->pe_num_map) 1602be283eebSWei Yang return -ENOMEM; 1603be283eebSWei Yang 1604be283eebSWei Yang if (pdn->m64_single_mode) 1605be283eebSWei Yang for (i = 0; i < num_vfs; i++) 1606be283eebSWei Yang pdn->pe_num_map[i] = IODA_INVALID_PE; 1607be283eebSWei Yang 1608781a868fSWei Yang /* Calculate available PE for required VFs */ 1609be283eebSWei Yang if (pdn->m64_single_mode) { 1610be283eebSWei Yang for (i = 0; i < num_vfs; i++) { 16111e916772SGavin Shan pe = pnv_ioda_alloc_pe(phb); 16121e916772SGavin Shan if (!pe) { 1613be283eebSWei Yang ret = -EBUSY; 1614be283eebSWei Yang goto m64_failed; 1615be283eebSWei Yang } 16161e916772SGavin Shan 16171e916772SGavin Shan pdn->pe_num_map[i] = pe->pe_number; 1618be283eebSWei Yang } 1619be283eebSWei Yang } else { 1620781a868fSWei Yang mutex_lock(&phb->ioda.pe_alloc_mutex); 1621be283eebSWei Yang *pdn->pe_num_map = bitmap_find_next_zero_area( 162292b8f137SGavin Shan phb->ioda.pe_alloc, phb->ioda.total_pe_num, 1623781a868fSWei Yang 0, num_vfs, 0); 162492b8f137SGavin Shan if (*pdn->pe_num_map >= phb->ioda.total_pe_num) { 1625781a868fSWei Yang mutex_unlock(&phb->ioda.pe_alloc_mutex); 1626781a868fSWei Yang dev_info(&pdev->dev, "Failed to enable VF%d\n", num_vfs); 1627be283eebSWei Yang kfree(pdn->pe_num_map); 1628781a868fSWei Yang return -EBUSY; 1629781a868fSWei Yang } 1630be283eebSWei Yang bitmap_set(phb->ioda.pe_alloc, *pdn->pe_num_map, num_vfs); 1631781a868fSWei Yang mutex_unlock(&phb->ioda.pe_alloc_mutex); 1632be283eebSWei Yang } 1633be283eebSWei Yang pdn->num_vfs = num_vfs; 1634781a868fSWei Yang 1635781a868fSWei Yang /* Assign M64 window accordingly */ 163602639b0eSWei Yang ret = pnv_pci_vf_assign_m64(pdev, num_vfs); 1637781a868fSWei Yang if (ret) { 1638781a868fSWei Yang dev_info(&pdev->dev, "Not enough M64 window resources\n"); 1639781a868fSWei Yang goto m64_failed; 1640781a868fSWei Yang } 1641781a868fSWei Yang 1642781a868fSWei Yang /* 1643781a868fSWei Yang * When using one M64 BAR to map one IOV BAR, we need to shift 1644781a868fSWei Yang * the IOV BAR according to the PE# allocated to the VFs. 1645781a868fSWei Yang * Otherwise, the PE# for the VF will conflict with others. 1646781a868fSWei Yang */ 1647ee8222feSWei Yang if (!pdn->m64_single_mode) { 1648be283eebSWei Yang ret = pnv_pci_vf_resource_shift(pdev, *pdn->pe_num_map); 1649781a868fSWei Yang if (ret) 1650781a868fSWei Yang goto m64_failed; 1651781a868fSWei Yang } 165202639b0eSWei Yang } 1653781a868fSWei Yang 1654781a868fSWei Yang /* Setup VF PEs */ 1655781a868fSWei Yang pnv_ioda_setup_vf_PE(pdev, num_vfs); 1656781a868fSWei Yang 1657781a868fSWei Yang return 0; 1658781a868fSWei Yang 1659781a868fSWei Yang m64_failed: 1660be283eebSWei Yang if (pdn->m64_single_mode) { 1661be283eebSWei Yang for (i = 0; i < num_vfs; i++) { 16621e916772SGavin Shan if (pdn->pe_num_map[i] == IODA_INVALID_PE) 16631e916772SGavin Shan continue; 16641e916772SGavin Shan 16651e916772SGavin Shan pe = &phb->ioda.pe_array[pdn->pe_num_map[i]]; 16661e916772SGavin Shan pnv_ioda_free_pe(pe); 1667be283eebSWei Yang } 1668be283eebSWei Yang } else 1669be283eebSWei Yang bitmap_clear(phb->ioda.pe_alloc, *pdn->pe_num_map, num_vfs); 1670be283eebSWei Yang 1671be283eebSWei Yang /* Releasing pe_num_map */ 1672be283eebSWei Yang kfree(pdn->pe_num_map); 1673781a868fSWei Yang 1674781a868fSWei Yang return ret; 1675781a868fSWei Yang } 1676781a868fSWei Yang 1677a8b2f828SGavin Shan int pcibios_sriov_disable(struct pci_dev *pdev) 1678a8b2f828SGavin Shan { 1679781a868fSWei Yang pnv_pci_sriov_disable(pdev); 1680781a868fSWei Yang 1681a8b2f828SGavin Shan /* Release PCI data */ 1682a8b2f828SGavin Shan remove_dev_pci_data(pdev); 1683a8b2f828SGavin Shan return 0; 1684a8b2f828SGavin Shan } 1685a8b2f828SGavin Shan 1686a8b2f828SGavin Shan int pcibios_sriov_enable(struct pci_dev *pdev, u16 num_vfs) 1687a8b2f828SGavin Shan { 1688a8b2f828SGavin Shan /* Allocate PCI data */ 1689a8b2f828SGavin Shan add_dev_pci_data(pdev); 1690781a868fSWei Yang 1691ee8222feSWei Yang return pnv_pci_sriov_enable(pdev, num_vfs); 1692a8b2f828SGavin Shan } 1693a8b2f828SGavin Shan #endif /* CONFIG_PCI_IOV */ 1694a8b2f828SGavin Shan 1695959c9bddSGavin Shan static void pnv_pci_ioda_dma_dev_setup(struct pnv_phb *phb, struct pci_dev *pdev) 1696184cd4a3SBenjamin Herrenschmidt { 1697b72c1f65SBenjamin Herrenschmidt struct pci_dn *pdn = pci_get_pdn(pdev); 1698959c9bddSGavin Shan struct pnv_ioda_pe *pe; 1699184cd4a3SBenjamin Herrenschmidt 1700959c9bddSGavin Shan /* 1701959c9bddSGavin Shan * The function can be called while the PE# 1702959c9bddSGavin Shan * hasn't been assigned. Do nothing for the 1703959c9bddSGavin Shan * case. 1704959c9bddSGavin Shan */ 1705959c9bddSGavin Shan if (!pdn || pdn->pe_number == IODA_INVALID_PE) 1706959c9bddSGavin Shan return; 1707184cd4a3SBenjamin Herrenschmidt 1708959c9bddSGavin Shan pe = &phb->ioda.pe_array[pdn->pe_number]; 1709cd15b048SBenjamin Herrenschmidt WARN_ON(get_dma_ops(&pdev->dev) != &dma_iommu_ops); 17100e1ffef0SAlexey Kardashevskiy set_dma_offset(&pdev->dev, pe->tce_bypass_base); 1711b348aa65SAlexey Kardashevskiy set_iommu_table_base(&pdev->dev, pe->table_group.tables[0]); 17124617082eSAlexey Kardashevskiy /* 17134617082eSAlexey Kardashevskiy * Note: iommu_add_device() will fail here as 17144617082eSAlexey Kardashevskiy * for physical PE: the device is already added by now; 17154617082eSAlexey Kardashevskiy * for virtual PE: sysfs entries are not ready yet and 17164617082eSAlexey Kardashevskiy * tce_iommu_bus_notifier will add the device to a group later. 17174617082eSAlexey Kardashevskiy */ 1718184cd4a3SBenjamin Herrenschmidt } 1719184cd4a3SBenjamin Herrenschmidt 1720a0f98629SRussell Currey static bool pnv_pci_ioda_pe_single_vendor(struct pnv_ioda_pe *pe) 1721a0f98629SRussell Currey { 1722a0f98629SRussell Currey unsigned short vendor = 0; 1723a0f98629SRussell Currey struct pci_dev *pdev; 1724a0f98629SRussell Currey 1725a0f98629SRussell Currey if (pe->device_count == 1) 1726a0f98629SRussell Currey return true; 1727a0f98629SRussell Currey 1728a0f98629SRussell Currey /* pe->pdev should be set if it's a single device, pe->pbus if not */ 1729a0f98629SRussell Currey if (!pe->pbus) 1730a0f98629SRussell Currey return true; 1731a0f98629SRussell Currey 1732a0f98629SRussell Currey list_for_each_entry(pdev, &pe->pbus->devices, bus_list) { 1733a0f98629SRussell Currey if (!vendor) { 1734a0f98629SRussell Currey vendor = pdev->vendor; 1735a0f98629SRussell Currey continue; 1736a0f98629SRussell Currey } 1737a0f98629SRussell Currey 1738a0f98629SRussell Currey if (pdev->vendor != vendor) 1739a0f98629SRussell Currey return false; 1740a0f98629SRussell Currey } 1741a0f98629SRussell Currey 1742a0f98629SRussell Currey return true; 1743a0f98629SRussell Currey } 1744a0f98629SRussell Currey 17458e3f1b1dSRussell Currey /* 17468e3f1b1dSRussell Currey * Reconfigure TVE#0 to be usable as 64-bit DMA space. 17478e3f1b1dSRussell Currey * 17488e3f1b1dSRussell Currey * The first 4GB of virtual memory for a PE is reserved for 32-bit accesses. 17498e3f1b1dSRussell Currey * Devices can only access more than that if bit 59 of the PCI address is set 17508e3f1b1dSRussell Currey * by hardware, which indicates TVE#1 should be used instead of TVE#0. 17518e3f1b1dSRussell Currey * Many PCI devices are not capable of addressing that many bits, and as a 17528e3f1b1dSRussell Currey * result are limited to the 4GB of virtual memory made available to 32-bit 17538e3f1b1dSRussell Currey * devices in TVE#0. 17548e3f1b1dSRussell Currey * 17558e3f1b1dSRussell Currey * In order to work around this, reconfigure TVE#0 to be suitable for 64-bit 17568e3f1b1dSRussell Currey * devices by configuring the virtual memory past the first 4GB inaccessible 17578e3f1b1dSRussell Currey * by 64-bit DMAs. This should only be used by devices that want more than 17588e3f1b1dSRussell Currey * 4GB, and only on PEs that have no 32-bit devices. 17598e3f1b1dSRussell Currey * 17608e3f1b1dSRussell Currey * Currently this will only work on PHB3 (POWER8). 17618e3f1b1dSRussell Currey */ 17628e3f1b1dSRussell Currey static int pnv_pci_ioda_dma_64bit_bypass(struct pnv_ioda_pe *pe) 17638e3f1b1dSRussell Currey { 17648e3f1b1dSRussell Currey u64 window_size, table_size, tce_count, addr; 17658e3f1b1dSRussell Currey struct page *table_pages; 17668e3f1b1dSRussell Currey u64 tce_order = 28; /* 256MB TCEs */ 17678e3f1b1dSRussell Currey __be64 *tces; 17688e3f1b1dSRussell Currey s64 rc; 17698e3f1b1dSRussell Currey 17708e3f1b1dSRussell Currey /* 17718e3f1b1dSRussell Currey * Window size needs to be a power of two, but needs to account for 17728e3f1b1dSRussell Currey * shifting memory by the 4GB offset required to skip 32bit space. 17738e3f1b1dSRussell Currey */ 17748e3f1b1dSRussell Currey window_size = roundup_pow_of_two(memory_hotplug_max() + (1ULL << 32)); 17758e3f1b1dSRussell Currey tce_count = window_size >> tce_order; 17768e3f1b1dSRussell Currey table_size = tce_count << 3; 17778e3f1b1dSRussell Currey 17788e3f1b1dSRussell Currey if (table_size < PAGE_SIZE) 17798e3f1b1dSRussell Currey table_size = PAGE_SIZE; 17808e3f1b1dSRussell Currey 17818e3f1b1dSRussell Currey table_pages = alloc_pages_node(pe->phb->hose->node, GFP_KERNEL, 17828e3f1b1dSRussell Currey get_order(table_size)); 17838e3f1b1dSRussell Currey if (!table_pages) 17848e3f1b1dSRussell Currey goto err; 17858e3f1b1dSRussell Currey 17868e3f1b1dSRussell Currey tces = page_address(table_pages); 17878e3f1b1dSRussell Currey if (!tces) 17888e3f1b1dSRussell Currey goto err; 17898e3f1b1dSRussell Currey 17908e3f1b1dSRussell Currey memset(tces, 0, table_size); 17918e3f1b1dSRussell Currey 17928e3f1b1dSRussell Currey for (addr = 0; addr < memory_hotplug_max(); addr += (1 << tce_order)) { 17938e3f1b1dSRussell Currey tces[(addr + (1ULL << 32)) >> tce_order] = 17948e3f1b1dSRussell Currey cpu_to_be64(addr | TCE_PCI_READ | TCE_PCI_WRITE); 17958e3f1b1dSRussell Currey } 17968e3f1b1dSRussell Currey 17978e3f1b1dSRussell Currey rc = opal_pci_map_pe_dma_window(pe->phb->opal_id, 17988e3f1b1dSRussell Currey pe->pe_number, 17998e3f1b1dSRussell Currey /* reconfigure window 0 */ 18008e3f1b1dSRussell Currey (pe->pe_number << 1) + 0, 18018e3f1b1dSRussell Currey 1, 18028e3f1b1dSRussell Currey __pa(tces), 18038e3f1b1dSRussell Currey table_size, 18048e3f1b1dSRussell Currey 1 << tce_order); 18058e3f1b1dSRussell Currey if (rc == OPAL_SUCCESS) { 18068e3f1b1dSRussell Currey pe_info(pe, "Using 64-bit DMA iommu bypass (through TVE#0)\n"); 18078e3f1b1dSRussell Currey return 0; 18088e3f1b1dSRussell Currey } 18098e3f1b1dSRussell Currey err: 18108e3f1b1dSRussell Currey pe_err(pe, "Error configuring 64-bit DMA bypass\n"); 18118e3f1b1dSRussell Currey return -EIO; 18128e3f1b1dSRussell Currey } 18138e3f1b1dSRussell Currey 1814763d2d8dSDaniel Axtens static int pnv_pci_ioda_dma_set_mask(struct pci_dev *pdev, u64 dma_mask) 1815cd15b048SBenjamin Herrenschmidt { 1816763d2d8dSDaniel Axtens struct pci_controller *hose = pci_bus_to_host(pdev->bus); 1817763d2d8dSDaniel Axtens struct pnv_phb *phb = hose->private_data; 1818cd15b048SBenjamin Herrenschmidt struct pci_dn *pdn = pci_get_pdn(pdev); 1819cd15b048SBenjamin Herrenschmidt struct pnv_ioda_pe *pe; 1820cd15b048SBenjamin Herrenschmidt uint64_t top; 1821cd15b048SBenjamin Herrenschmidt bool bypass = false; 18228e3f1b1dSRussell Currey s64 rc; 1823cd15b048SBenjamin Herrenschmidt 1824cd15b048SBenjamin Herrenschmidt if (WARN_ON(!pdn || pdn->pe_number == IODA_INVALID_PE)) 1825cd15b048SBenjamin Herrenschmidt return -ENODEV;; 1826cd15b048SBenjamin Herrenschmidt 1827cd15b048SBenjamin Herrenschmidt pe = &phb->ioda.pe_array[pdn->pe_number]; 1828cd15b048SBenjamin Herrenschmidt if (pe->tce_bypass_enabled) { 1829cd15b048SBenjamin Herrenschmidt top = pe->tce_bypass_base + memblock_end_of_DRAM() - 1; 1830cd15b048SBenjamin Herrenschmidt bypass = (dma_mask >= top); 1831cd15b048SBenjamin Herrenschmidt } 1832cd15b048SBenjamin Herrenschmidt 1833cd15b048SBenjamin Herrenschmidt if (bypass) { 1834cd15b048SBenjamin Herrenschmidt dev_info(&pdev->dev, "Using 64-bit DMA iommu bypass\n"); 1835cd15b048SBenjamin Herrenschmidt set_dma_ops(&pdev->dev, &dma_direct_ops); 1836cd15b048SBenjamin Herrenschmidt } else { 18378e3f1b1dSRussell Currey /* 18388e3f1b1dSRussell Currey * If the device can't set the TCE bypass bit but still wants 18398e3f1b1dSRussell Currey * to access 4GB or more, on PHB3 we can reconfigure TVE#0 to 18408e3f1b1dSRussell Currey * bypass the 32-bit region and be usable for 64-bit DMAs. 18418e3f1b1dSRussell Currey * The device needs to be able to address all of this space. 18428e3f1b1dSRussell Currey */ 18438e3f1b1dSRussell Currey if (dma_mask >> 32 && 18448e3f1b1dSRussell Currey dma_mask > (memory_hotplug_max() + (1ULL << 32)) && 18458e3f1b1dSRussell Currey pnv_pci_ioda_pe_single_vendor(pe) && 18468e3f1b1dSRussell Currey phb->model == PNV_PHB_MODEL_PHB3) { 18478e3f1b1dSRussell Currey /* Configure the bypass mode */ 18488e3f1b1dSRussell Currey rc = pnv_pci_ioda_dma_64bit_bypass(pe); 18498e3f1b1dSRussell Currey if (rc) 18508e3f1b1dSRussell Currey return rc; 18518e3f1b1dSRussell Currey /* 4GB offset bypasses 32-bit space */ 18528e3f1b1dSRussell Currey set_dma_offset(&pdev->dev, (1ULL << 32)); 18538e3f1b1dSRussell Currey set_dma_ops(&pdev->dev, &dma_direct_ops); 1854253fd51eSAlistair Popple } else if (dma_mask >> 32 && dma_mask != DMA_BIT_MASK(64)) { 1855253fd51eSAlistair Popple /* 1856253fd51eSAlistair Popple * Fail the request if a DMA mask between 32 and 64 bits 1857253fd51eSAlistair Popple * was requested but couldn't be fulfilled. Ideally we 1858253fd51eSAlistair Popple * would do this for 64-bits but historically we have 1859253fd51eSAlistair Popple * always fallen back to 32-bits. 1860253fd51eSAlistair Popple */ 1861253fd51eSAlistair Popple return -ENOMEM; 18628e3f1b1dSRussell Currey } else { 1863cd15b048SBenjamin Herrenschmidt dev_info(&pdev->dev, "Using 32-bit DMA via iommu\n"); 1864cd15b048SBenjamin Herrenschmidt set_dma_ops(&pdev->dev, &dma_iommu_ops); 1865cd15b048SBenjamin Herrenschmidt } 18668e3f1b1dSRussell Currey } 1867a32305bfSBrian W Hart *pdev->dev.dma_mask = dma_mask; 18685d2aa710SAlistair Popple 18695d2aa710SAlistair Popple /* Update peer npu devices */ 1870f9f83456SAlexey Kardashevskiy pnv_npu_try_dma_set_bypass(pdev, bypass); 18715d2aa710SAlistair Popple 1872cd15b048SBenjamin Herrenschmidt return 0; 1873cd15b048SBenjamin Herrenschmidt } 1874cd15b048SBenjamin Herrenschmidt 187553522982SAndrew Donnellan static u64 pnv_pci_ioda_dma_get_required_mask(struct pci_dev *pdev) 1876fe7e85c6SGavin Shan { 187753522982SAndrew Donnellan struct pci_controller *hose = pci_bus_to_host(pdev->bus); 187853522982SAndrew Donnellan struct pnv_phb *phb = hose->private_data; 1879fe7e85c6SGavin Shan struct pci_dn *pdn = pci_get_pdn(pdev); 1880fe7e85c6SGavin Shan struct pnv_ioda_pe *pe; 1881fe7e85c6SGavin Shan u64 end, mask; 1882fe7e85c6SGavin Shan 1883fe7e85c6SGavin Shan if (WARN_ON(!pdn || pdn->pe_number == IODA_INVALID_PE)) 1884fe7e85c6SGavin Shan return 0; 1885fe7e85c6SGavin Shan 1886fe7e85c6SGavin Shan pe = &phb->ioda.pe_array[pdn->pe_number]; 1887fe7e85c6SGavin Shan if (!pe->tce_bypass_enabled) 1888fe7e85c6SGavin Shan return __dma_get_required_mask(&pdev->dev); 1889fe7e85c6SGavin Shan 1890fe7e85c6SGavin Shan 1891fe7e85c6SGavin Shan end = pe->tce_bypass_base + memblock_end_of_DRAM(); 1892fe7e85c6SGavin Shan mask = 1ULL << (fls64(end) - 1); 1893fe7e85c6SGavin Shan mask += mask - 1; 1894fe7e85c6SGavin Shan 1895fe7e85c6SGavin Shan return mask; 1896fe7e85c6SGavin Shan } 1897fe7e85c6SGavin Shan 1898dff4a39eSGavin Shan static void pnv_ioda_setup_bus_dma(struct pnv_ioda_pe *pe, 1899db08e1d5SAlexey Kardashevskiy struct pci_bus *bus, 1900db08e1d5SAlexey Kardashevskiy bool add_to_group) 190174251fe2SBenjamin Herrenschmidt { 190274251fe2SBenjamin Herrenschmidt struct pci_dev *dev; 190374251fe2SBenjamin Herrenschmidt 190474251fe2SBenjamin Herrenschmidt list_for_each_entry(dev, &bus->devices, bus_list) { 1905b348aa65SAlexey Kardashevskiy set_iommu_table_base(&dev->dev, pe->table_group.tables[0]); 1906e91c2511SBenjamin Herrenschmidt set_dma_offset(&dev->dev, pe->tce_bypass_base); 1907db08e1d5SAlexey Kardashevskiy if (add_to_group) 19084617082eSAlexey Kardashevskiy iommu_add_device(&dev->dev); 1909dff4a39eSGavin Shan 19105c89a87dSAlexey Kardashevskiy if ((pe->flags & PNV_IODA_PE_BUS_ALL) && dev->subordinate) 1911db08e1d5SAlexey Kardashevskiy pnv_ioda_setup_bus_dma(pe, dev->subordinate, 1912db08e1d5SAlexey Kardashevskiy add_to_group); 191374251fe2SBenjamin Herrenschmidt } 191474251fe2SBenjamin Herrenschmidt } 191574251fe2SBenjamin Herrenschmidt 1916fd141d1aSBenjamin Herrenschmidt static inline __be64 __iomem *pnv_ioda_get_inval_reg(struct pnv_phb *phb, 1917fd141d1aSBenjamin Herrenschmidt bool real_mode) 1918fd141d1aSBenjamin Herrenschmidt { 1919fd141d1aSBenjamin Herrenschmidt return real_mode ? (__be64 __iomem *)(phb->regs_phys + 0x210) : 1920fd141d1aSBenjamin Herrenschmidt (phb->regs + 0x210); 1921fd141d1aSBenjamin Herrenschmidt } 1922fd141d1aSBenjamin Herrenschmidt 1923a34ab7c3SBenjamin Herrenschmidt static void pnv_pci_p7ioc_tce_invalidate(struct iommu_table *tbl, 1924decbda25SAlexey Kardashevskiy unsigned long index, unsigned long npages, bool rm) 19254cce9550SGavin Shan { 19260eaf4defSAlexey Kardashevskiy struct iommu_table_group_link *tgl = list_first_entry_or_null( 19270eaf4defSAlexey Kardashevskiy &tbl->it_group_list, struct iommu_table_group_link, 19280eaf4defSAlexey Kardashevskiy next); 19290eaf4defSAlexey Kardashevskiy struct pnv_ioda_pe *pe = container_of(tgl->table_group, 1930b348aa65SAlexey Kardashevskiy struct pnv_ioda_pe, table_group); 1931fd141d1aSBenjamin Herrenschmidt __be64 __iomem *invalidate = pnv_ioda_get_inval_reg(pe->phb, rm); 19324cce9550SGavin Shan unsigned long start, end, inc; 19334cce9550SGavin Shan 1934decbda25SAlexey Kardashevskiy start = __pa(((__be64 *)tbl->it_base) + index - tbl->it_offset); 1935decbda25SAlexey Kardashevskiy end = __pa(((__be64 *)tbl->it_base) + index - tbl->it_offset + 1936decbda25SAlexey Kardashevskiy npages - 1); 19374cce9550SGavin Shan 19384cce9550SGavin Shan /* p7ioc-style invalidation, 2 TCEs per write */ 19394cce9550SGavin Shan start |= (1ull << 63); 19404cce9550SGavin Shan end |= (1ull << 63); 19414cce9550SGavin Shan inc = 16; 19424cce9550SGavin Shan end |= inc - 1; /* round up end to be different than start */ 19434cce9550SGavin Shan 19444cce9550SGavin Shan mb(); /* Ensure above stores are visible */ 19454cce9550SGavin Shan while (start <= end) { 19468e0a1611SAlexey Kardashevskiy if (rm) 19473ad26e5cSBenjamin Herrenschmidt __raw_rm_writeq(cpu_to_be64(start), invalidate); 19488e0a1611SAlexey Kardashevskiy else 19493a1a4661SBenjamin Herrenschmidt __raw_writeq(cpu_to_be64(start), invalidate); 19504cce9550SGavin Shan start += inc; 19514cce9550SGavin Shan } 19524cce9550SGavin Shan 19534cce9550SGavin Shan /* 19544cce9550SGavin Shan * The iommu layer will do another mb() for us on build() 19554cce9550SGavin Shan * and we don't care on free() 19564cce9550SGavin Shan */ 19574cce9550SGavin Shan } 19584cce9550SGavin Shan 1959decbda25SAlexey Kardashevskiy static int pnv_ioda1_tce_build(struct iommu_table *tbl, long index, 1960decbda25SAlexey Kardashevskiy long npages, unsigned long uaddr, 1961decbda25SAlexey Kardashevskiy enum dma_data_direction direction, 196200085f1eSKrzysztof Kozlowski unsigned long attrs) 1963decbda25SAlexey Kardashevskiy { 1964decbda25SAlexey Kardashevskiy int ret = pnv_tce_build(tbl, index, npages, uaddr, direction, 1965decbda25SAlexey Kardashevskiy attrs); 1966decbda25SAlexey Kardashevskiy 196708acce1cSBenjamin Herrenschmidt if (!ret) 1968a34ab7c3SBenjamin Herrenschmidt pnv_pci_p7ioc_tce_invalidate(tbl, index, npages, false); 1969decbda25SAlexey Kardashevskiy 1970decbda25SAlexey Kardashevskiy return ret; 1971decbda25SAlexey Kardashevskiy } 1972decbda25SAlexey Kardashevskiy 197305c6cfb9SAlexey Kardashevskiy #ifdef CONFIG_IOMMU_API 197405c6cfb9SAlexey Kardashevskiy static int pnv_ioda1_tce_xchg(struct iommu_table *tbl, long index, 197505c6cfb9SAlexey Kardashevskiy unsigned long *hpa, enum dma_data_direction *direction) 197605c6cfb9SAlexey Kardashevskiy { 197705c6cfb9SAlexey Kardashevskiy long ret = pnv_tce_xchg(tbl, index, hpa, direction); 197805c6cfb9SAlexey Kardashevskiy 197908acce1cSBenjamin Herrenschmidt if (!ret) 1980a34ab7c3SBenjamin Herrenschmidt pnv_pci_p7ioc_tce_invalidate(tbl, index, 1, false); 198105c6cfb9SAlexey Kardashevskiy 198205c6cfb9SAlexey Kardashevskiy return ret; 198305c6cfb9SAlexey Kardashevskiy } 1984a540aa56SAlexey Kardashevskiy 1985a540aa56SAlexey Kardashevskiy static int pnv_ioda1_tce_xchg_rm(struct iommu_table *tbl, long index, 1986a540aa56SAlexey Kardashevskiy unsigned long *hpa, enum dma_data_direction *direction) 1987a540aa56SAlexey Kardashevskiy { 1988a540aa56SAlexey Kardashevskiy long ret = pnv_tce_xchg(tbl, index, hpa, direction); 1989a540aa56SAlexey Kardashevskiy 1990a540aa56SAlexey Kardashevskiy if (!ret) 1991a540aa56SAlexey Kardashevskiy pnv_pci_p7ioc_tce_invalidate(tbl, index, 1, true); 1992a540aa56SAlexey Kardashevskiy 1993a540aa56SAlexey Kardashevskiy return ret; 1994a540aa56SAlexey Kardashevskiy } 199505c6cfb9SAlexey Kardashevskiy #endif 199605c6cfb9SAlexey Kardashevskiy 1997decbda25SAlexey Kardashevskiy static void pnv_ioda1_tce_free(struct iommu_table *tbl, long index, 1998decbda25SAlexey Kardashevskiy long npages) 1999decbda25SAlexey Kardashevskiy { 2000decbda25SAlexey Kardashevskiy pnv_tce_free(tbl, index, npages); 2001decbda25SAlexey Kardashevskiy 2002a34ab7c3SBenjamin Herrenschmidt pnv_pci_p7ioc_tce_invalidate(tbl, index, npages, false); 2003decbda25SAlexey Kardashevskiy } 2004decbda25SAlexey Kardashevskiy 2005da004c36SAlexey Kardashevskiy static struct iommu_table_ops pnv_ioda1_iommu_ops = { 2006decbda25SAlexey Kardashevskiy .set = pnv_ioda1_tce_build, 200705c6cfb9SAlexey Kardashevskiy #ifdef CONFIG_IOMMU_API 200805c6cfb9SAlexey Kardashevskiy .exchange = pnv_ioda1_tce_xchg, 2009a540aa56SAlexey Kardashevskiy .exchange_rm = pnv_ioda1_tce_xchg_rm, 201005c6cfb9SAlexey Kardashevskiy #endif 2011decbda25SAlexey Kardashevskiy .clear = pnv_ioda1_tce_free, 2012da004c36SAlexey Kardashevskiy .get = pnv_tce_get, 2013da004c36SAlexey Kardashevskiy }; 2014da004c36SAlexey Kardashevskiy 2015a34ab7c3SBenjamin Herrenschmidt #define PHB3_TCE_KILL_INVAL_ALL PPC_BIT(0) 2016a34ab7c3SBenjamin Herrenschmidt #define PHB3_TCE_KILL_INVAL_PE PPC_BIT(1) 2017a34ab7c3SBenjamin Herrenschmidt #define PHB3_TCE_KILL_INVAL_ONE PPC_BIT(2) 2018bef9253fSAlexey Kardashevskiy 20196b3d12a9SAlistair Popple static void pnv_pci_phb3_tce_invalidate_entire(struct pnv_phb *phb, bool rm) 20200bbcdb43SAlexey Kardashevskiy { 2021fd141d1aSBenjamin Herrenschmidt __be64 __iomem *invalidate = pnv_ioda_get_inval_reg(phb, rm); 2022a34ab7c3SBenjamin Herrenschmidt const unsigned long val = PHB3_TCE_KILL_INVAL_ALL; 20230bbcdb43SAlexey Kardashevskiy 20240bbcdb43SAlexey Kardashevskiy mb(); /* Ensure previous TCE table stores are visible */ 20250bbcdb43SAlexey Kardashevskiy if (rm) 2026fd141d1aSBenjamin Herrenschmidt __raw_rm_writeq(cpu_to_be64(val), invalidate); 20270bbcdb43SAlexey Kardashevskiy else 2028fd141d1aSBenjamin Herrenschmidt __raw_writeq(cpu_to_be64(val), invalidate); 20290bbcdb43SAlexey Kardashevskiy } 20300bbcdb43SAlexey Kardashevskiy 2031a34ab7c3SBenjamin Herrenschmidt static inline void pnv_pci_phb3_tce_invalidate_pe(struct pnv_ioda_pe *pe) 20325780fb04SAlexey Kardashevskiy { 20335780fb04SAlexey Kardashevskiy /* 01xb - invalidate TCEs that match the specified PE# */ 2034fd141d1aSBenjamin Herrenschmidt __be64 __iomem *invalidate = pnv_ioda_get_inval_reg(pe->phb, false); 2035a34ab7c3SBenjamin Herrenschmidt unsigned long val = PHB3_TCE_KILL_INVAL_PE | (pe->pe_number & 0xFF); 20365780fb04SAlexey Kardashevskiy 20375780fb04SAlexey Kardashevskiy mb(); /* Ensure above stores are visible */ 2038fd141d1aSBenjamin Herrenschmidt __raw_writeq(cpu_to_be64(val), invalidate); 20395780fb04SAlexey Kardashevskiy } 20405780fb04SAlexey Kardashevskiy 2041fd141d1aSBenjamin Herrenschmidt static void pnv_pci_phb3_tce_invalidate(struct pnv_ioda_pe *pe, bool rm, 2042fd141d1aSBenjamin Herrenschmidt unsigned shift, unsigned long index, 2043fd141d1aSBenjamin Herrenschmidt unsigned long npages) 20444cce9550SGavin Shan { 20454d902195SAlexey Kardashevskiy __be64 __iomem *invalidate = pnv_ioda_get_inval_reg(pe->phb, rm); 20464cce9550SGavin Shan unsigned long start, end, inc; 20474cce9550SGavin Shan 20484cce9550SGavin Shan /* We'll invalidate DMA address in PE scope */ 2049a34ab7c3SBenjamin Herrenschmidt start = PHB3_TCE_KILL_INVAL_ONE; 2050fd141d1aSBenjamin Herrenschmidt start |= (pe->pe_number & 0xFF); 20514cce9550SGavin Shan end = start; 20524cce9550SGavin Shan 20534cce9550SGavin Shan /* Figure out the start, end and step */ 2054decbda25SAlexey Kardashevskiy start |= (index << shift); 2055decbda25SAlexey Kardashevskiy end |= ((index + npages - 1) << shift); 2056b0376c9bSAlexey Kardashevskiy inc = (0x1ull << shift); 20574cce9550SGavin Shan mb(); 20584cce9550SGavin Shan 20594cce9550SGavin Shan while (start <= end) { 20608e0a1611SAlexey Kardashevskiy if (rm) 20613ad26e5cSBenjamin Herrenschmidt __raw_rm_writeq(cpu_to_be64(start), invalidate); 20628e0a1611SAlexey Kardashevskiy else 20633a1a4661SBenjamin Herrenschmidt __raw_writeq(cpu_to_be64(start), invalidate); 20644cce9550SGavin Shan start += inc; 20654cce9550SGavin Shan } 20664cce9550SGavin Shan } 20674cce9550SGavin Shan 2068f0228c41SBenjamin Herrenschmidt static inline void pnv_pci_ioda2_tce_invalidate_pe(struct pnv_ioda_pe *pe) 2069f0228c41SBenjamin Herrenschmidt { 2070f0228c41SBenjamin Herrenschmidt struct pnv_phb *phb = pe->phb; 2071f0228c41SBenjamin Herrenschmidt 2072f0228c41SBenjamin Herrenschmidt if (phb->model == PNV_PHB_MODEL_PHB3 && phb->regs) 2073f0228c41SBenjamin Herrenschmidt pnv_pci_phb3_tce_invalidate_pe(pe); 2074f0228c41SBenjamin Herrenschmidt else 2075f0228c41SBenjamin Herrenschmidt opal_pci_tce_kill(phb->opal_id, OPAL_PCI_TCE_KILL_PE, 2076f0228c41SBenjamin Herrenschmidt pe->pe_number, 0, 0, 0); 2077f0228c41SBenjamin Herrenschmidt } 2078f0228c41SBenjamin Herrenschmidt 2079e57080f1SAlexey Kardashevskiy static void pnv_pci_ioda2_tce_invalidate(struct iommu_table *tbl, 2080e57080f1SAlexey Kardashevskiy unsigned long index, unsigned long npages, bool rm) 2081e57080f1SAlexey Kardashevskiy { 2082e57080f1SAlexey Kardashevskiy struct iommu_table_group_link *tgl; 2083e57080f1SAlexey Kardashevskiy 2084a540aa56SAlexey Kardashevskiy list_for_each_entry_lockless(tgl, &tbl->it_group_list, next) { 2085e57080f1SAlexey Kardashevskiy struct pnv_ioda_pe *pe = container_of(tgl->table_group, 2086e57080f1SAlexey Kardashevskiy struct pnv_ioda_pe, table_group); 2087f0228c41SBenjamin Herrenschmidt struct pnv_phb *phb = pe->phb; 2088f0228c41SBenjamin Herrenschmidt unsigned int shift = tbl->it_page_shift; 2089f0228c41SBenjamin Herrenschmidt 2090616badd2SAlistair Popple /* 2091616badd2SAlistair Popple * NVLink1 can use the TCE kill register directly as 2092616badd2SAlistair Popple * it's the same as PHB3. NVLink2 is different and 2093616badd2SAlistair Popple * should go via the OPAL call. 2094616badd2SAlistair Popple */ 2095616badd2SAlistair Popple if (phb->model == PNV_PHB_MODEL_NPU) { 20960bbcdb43SAlexey Kardashevskiy /* 20970bbcdb43SAlexey Kardashevskiy * The NVLink hardware does not support TCE kill 20980bbcdb43SAlexey Kardashevskiy * per TCE entry so we have to invalidate 20990bbcdb43SAlexey Kardashevskiy * the entire cache for it. 21000bbcdb43SAlexey Kardashevskiy */ 2101f0228c41SBenjamin Herrenschmidt pnv_pci_phb3_tce_invalidate_entire(phb, rm); 21025d2aa710SAlistair Popple continue; 21035d2aa710SAlistair Popple } 2104f0228c41SBenjamin Herrenschmidt if (phb->model == PNV_PHB_MODEL_PHB3 && phb->regs) 2105f0228c41SBenjamin Herrenschmidt pnv_pci_phb3_tce_invalidate(pe, rm, shift, 210685674868SAlexey Kardashevskiy index, npages); 2107f0228c41SBenjamin Herrenschmidt else 2108f0228c41SBenjamin Herrenschmidt opal_pci_tce_kill(phb->opal_id, 2109f0228c41SBenjamin Herrenschmidt OPAL_PCI_TCE_KILL_PAGES, 2110f0228c41SBenjamin Herrenschmidt pe->pe_number, 1u << shift, 2111f0228c41SBenjamin Herrenschmidt index << shift, npages); 2112e57080f1SAlexey Kardashevskiy } 2113e57080f1SAlexey Kardashevskiy } 2114e57080f1SAlexey Kardashevskiy 21156b3d12a9SAlistair Popple void pnv_pci_ioda2_tce_invalidate_entire(struct pnv_phb *phb, bool rm) 21166b3d12a9SAlistair Popple { 21176b3d12a9SAlistair Popple if (phb->model == PNV_PHB_MODEL_NPU || phb->model == PNV_PHB_MODEL_PHB3) 21186b3d12a9SAlistair Popple pnv_pci_phb3_tce_invalidate_entire(phb, rm); 21196b3d12a9SAlistair Popple else 21206b3d12a9SAlistair Popple opal_pci_tce_kill(phb->opal_id, OPAL_PCI_TCE_KILL, 0, 0, 0, 0); 21216b3d12a9SAlistair Popple } 21226b3d12a9SAlistair Popple 2123decbda25SAlexey Kardashevskiy static int pnv_ioda2_tce_build(struct iommu_table *tbl, long index, 2124decbda25SAlexey Kardashevskiy long npages, unsigned long uaddr, 2125decbda25SAlexey Kardashevskiy enum dma_data_direction direction, 212600085f1eSKrzysztof Kozlowski unsigned long attrs) 21274cce9550SGavin Shan { 2128decbda25SAlexey Kardashevskiy int ret = pnv_tce_build(tbl, index, npages, uaddr, direction, 2129decbda25SAlexey Kardashevskiy attrs); 21304cce9550SGavin Shan 213108acce1cSBenjamin Herrenschmidt if (!ret) 2132decbda25SAlexey Kardashevskiy pnv_pci_ioda2_tce_invalidate(tbl, index, npages, false); 2133decbda25SAlexey Kardashevskiy 2134decbda25SAlexey Kardashevskiy return ret; 2135decbda25SAlexey Kardashevskiy } 2136decbda25SAlexey Kardashevskiy 213705c6cfb9SAlexey Kardashevskiy #ifdef CONFIG_IOMMU_API 213805c6cfb9SAlexey Kardashevskiy static int pnv_ioda2_tce_xchg(struct iommu_table *tbl, long index, 213905c6cfb9SAlexey Kardashevskiy unsigned long *hpa, enum dma_data_direction *direction) 214005c6cfb9SAlexey Kardashevskiy { 214105c6cfb9SAlexey Kardashevskiy long ret = pnv_tce_xchg(tbl, index, hpa, direction); 214205c6cfb9SAlexey Kardashevskiy 214308acce1cSBenjamin Herrenschmidt if (!ret) 214405c6cfb9SAlexey Kardashevskiy pnv_pci_ioda2_tce_invalidate(tbl, index, 1, false); 214505c6cfb9SAlexey Kardashevskiy 214605c6cfb9SAlexey Kardashevskiy return ret; 214705c6cfb9SAlexey Kardashevskiy } 2148a540aa56SAlexey Kardashevskiy 2149a540aa56SAlexey Kardashevskiy static int pnv_ioda2_tce_xchg_rm(struct iommu_table *tbl, long index, 2150a540aa56SAlexey Kardashevskiy unsigned long *hpa, enum dma_data_direction *direction) 2151a540aa56SAlexey Kardashevskiy { 2152a540aa56SAlexey Kardashevskiy long ret = pnv_tce_xchg(tbl, index, hpa, direction); 2153a540aa56SAlexey Kardashevskiy 2154a540aa56SAlexey Kardashevskiy if (!ret) 2155a540aa56SAlexey Kardashevskiy pnv_pci_ioda2_tce_invalidate(tbl, index, 1, true); 2156a540aa56SAlexey Kardashevskiy 2157a540aa56SAlexey Kardashevskiy return ret; 2158a540aa56SAlexey Kardashevskiy } 215905c6cfb9SAlexey Kardashevskiy #endif 216005c6cfb9SAlexey Kardashevskiy 2161decbda25SAlexey Kardashevskiy static void pnv_ioda2_tce_free(struct iommu_table *tbl, long index, 2162decbda25SAlexey Kardashevskiy long npages) 2163decbda25SAlexey Kardashevskiy { 2164decbda25SAlexey Kardashevskiy pnv_tce_free(tbl, index, npages); 2165decbda25SAlexey Kardashevskiy 2166decbda25SAlexey Kardashevskiy pnv_pci_ioda2_tce_invalidate(tbl, index, npages, false); 21674cce9550SGavin Shan } 21684cce9550SGavin Shan 21694793d65dSAlexey Kardashevskiy static void pnv_ioda2_table_free(struct iommu_table *tbl) 21704793d65dSAlexey Kardashevskiy { 21714793d65dSAlexey Kardashevskiy pnv_pci_ioda2_table_free_pages(tbl); 21724793d65dSAlexey Kardashevskiy } 21734793d65dSAlexey Kardashevskiy 2174da004c36SAlexey Kardashevskiy static struct iommu_table_ops pnv_ioda2_iommu_ops = { 2175decbda25SAlexey Kardashevskiy .set = pnv_ioda2_tce_build, 217605c6cfb9SAlexey Kardashevskiy #ifdef CONFIG_IOMMU_API 217705c6cfb9SAlexey Kardashevskiy .exchange = pnv_ioda2_tce_xchg, 2178a540aa56SAlexey Kardashevskiy .exchange_rm = pnv_ioda2_tce_xchg_rm, 217905c6cfb9SAlexey Kardashevskiy #endif 2180decbda25SAlexey Kardashevskiy .clear = pnv_ioda2_tce_free, 2181da004c36SAlexey Kardashevskiy .get = pnv_tce_get, 21824793d65dSAlexey Kardashevskiy .free = pnv_ioda2_table_free, 2183da004c36SAlexey Kardashevskiy }; 2184da004c36SAlexey Kardashevskiy 2185801846d1SGavin Shan static int pnv_pci_ioda_dev_dma_weight(struct pci_dev *dev, void *data) 2186801846d1SGavin Shan { 2187801846d1SGavin Shan unsigned int *weight = (unsigned int *)data; 2188801846d1SGavin Shan 2189801846d1SGavin Shan /* This is quite simplistic. The "base" weight of a device 2190801846d1SGavin Shan * is 10. 0 means no DMA is to be accounted for it. 2191801846d1SGavin Shan */ 2192801846d1SGavin Shan if (dev->hdr_type != PCI_HEADER_TYPE_NORMAL) 2193801846d1SGavin Shan return 0; 2194801846d1SGavin Shan 2195801846d1SGavin Shan if (dev->class == PCI_CLASS_SERIAL_USB_UHCI || 2196801846d1SGavin Shan dev->class == PCI_CLASS_SERIAL_USB_OHCI || 2197801846d1SGavin Shan dev->class == PCI_CLASS_SERIAL_USB_EHCI) 2198801846d1SGavin Shan *weight += 3; 2199801846d1SGavin Shan else if ((dev->class >> 8) == PCI_CLASS_STORAGE_RAID) 2200801846d1SGavin Shan *weight += 15; 2201801846d1SGavin Shan else 2202801846d1SGavin Shan *weight += 10; 2203801846d1SGavin Shan 2204801846d1SGavin Shan return 0; 2205801846d1SGavin Shan } 2206801846d1SGavin Shan 2207801846d1SGavin Shan static unsigned int pnv_pci_ioda_pe_dma_weight(struct pnv_ioda_pe *pe) 2208801846d1SGavin Shan { 2209801846d1SGavin Shan unsigned int weight = 0; 2210801846d1SGavin Shan 2211801846d1SGavin Shan /* SRIOV VF has same DMA32 weight as its PF */ 2212801846d1SGavin Shan #ifdef CONFIG_PCI_IOV 2213801846d1SGavin Shan if ((pe->flags & PNV_IODA_PE_VF) && pe->parent_dev) { 2214801846d1SGavin Shan pnv_pci_ioda_dev_dma_weight(pe->parent_dev, &weight); 2215801846d1SGavin Shan return weight; 2216801846d1SGavin Shan } 2217801846d1SGavin Shan #endif 2218801846d1SGavin Shan 2219801846d1SGavin Shan if ((pe->flags & PNV_IODA_PE_DEV) && pe->pdev) { 2220801846d1SGavin Shan pnv_pci_ioda_dev_dma_weight(pe->pdev, &weight); 2221801846d1SGavin Shan } else if ((pe->flags & PNV_IODA_PE_BUS) && pe->pbus) { 2222801846d1SGavin Shan struct pci_dev *pdev; 2223801846d1SGavin Shan 2224801846d1SGavin Shan list_for_each_entry(pdev, &pe->pbus->devices, bus_list) 2225801846d1SGavin Shan pnv_pci_ioda_dev_dma_weight(pdev, &weight); 2226801846d1SGavin Shan } else if ((pe->flags & PNV_IODA_PE_BUS_ALL) && pe->pbus) { 2227801846d1SGavin Shan pci_walk_bus(pe->pbus, pnv_pci_ioda_dev_dma_weight, &weight); 2228801846d1SGavin Shan } 2229801846d1SGavin Shan 2230801846d1SGavin Shan return weight; 2231801846d1SGavin Shan } 2232801846d1SGavin Shan 2233b30d936fSGavin Shan static void pnv_pci_ioda1_setup_dma_pe(struct pnv_phb *phb, 22342b923ed1SGavin Shan struct pnv_ioda_pe *pe) 2235184cd4a3SBenjamin Herrenschmidt { 2236184cd4a3SBenjamin Herrenschmidt 2237184cd4a3SBenjamin Herrenschmidt struct page *tce_mem = NULL; 2238184cd4a3SBenjamin Herrenschmidt struct iommu_table *tbl; 22392b923ed1SGavin Shan unsigned int weight, total_weight = 0; 22402b923ed1SGavin Shan unsigned int tce32_segsz, base, segs, avail, i; 2241184cd4a3SBenjamin Herrenschmidt int64_t rc; 2242184cd4a3SBenjamin Herrenschmidt void *addr; 2243184cd4a3SBenjamin Herrenschmidt 2244184cd4a3SBenjamin Herrenschmidt /* XXX FIXME: Handle 64-bit only DMA devices */ 2245184cd4a3SBenjamin Herrenschmidt /* XXX FIXME: Provide 64-bit DMA facilities & non-4K TCE tables etc.. */ 2246184cd4a3SBenjamin Herrenschmidt /* XXX FIXME: Allocate multi-level tables on PHB3 */ 22472b923ed1SGavin Shan weight = pnv_pci_ioda_pe_dma_weight(pe); 22482b923ed1SGavin Shan if (!weight) 22492b923ed1SGavin Shan return; 2250184cd4a3SBenjamin Herrenschmidt 22512b923ed1SGavin Shan pci_walk_bus(phb->hose->bus, pnv_pci_ioda_dev_dma_weight, 22522b923ed1SGavin Shan &total_weight); 22532b923ed1SGavin Shan segs = (weight * phb->ioda.dma32_count) / total_weight; 22542b923ed1SGavin Shan if (!segs) 22552b923ed1SGavin Shan segs = 1; 22562b923ed1SGavin Shan 22572b923ed1SGavin Shan /* 22582b923ed1SGavin Shan * Allocate contiguous DMA32 segments. We begin with the expected 22592b923ed1SGavin Shan * number of segments. With one more attempt, the number of DMA32 22602b923ed1SGavin Shan * segments to be allocated is decreased by one until one segment 22612b923ed1SGavin Shan * is allocated successfully. 22622b923ed1SGavin Shan */ 22632b923ed1SGavin Shan do { 22642b923ed1SGavin Shan for (base = 0; base <= phb->ioda.dma32_count - segs; base++) { 22652b923ed1SGavin Shan for (avail = 0, i = base; i < base + segs; i++) { 22662b923ed1SGavin Shan if (phb->ioda.dma32_segmap[i] == 22672b923ed1SGavin Shan IODA_INVALID_PE) 22682b923ed1SGavin Shan avail++; 22692b923ed1SGavin Shan } 22702b923ed1SGavin Shan 22712b923ed1SGavin Shan if (avail == segs) 22722b923ed1SGavin Shan goto found; 22732b923ed1SGavin Shan } 22742b923ed1SGavin Shan } while (--segs); 22752b923ed1SGavin Shan 22762b923ed1SGavin Shan if (!segs) { 22772b923ed1SGavin Shan pe_warn(pe, "No available DMA32 segments\n"); 22782b923ed1SGavin Shan return; 22792b923ed1SGavin Shan } 22802b923ed1SGavin Shan 22812b923ed1SGavin Shan found: 22820eaf4defSAlexey Kardashevskiy tbl = pnv_pci_table_alloc(phb->hose->node); 228382eae1afSAlexey Kardashevskiy if (WARN_ON(!tbl)) 228482eae1afSAlexey Kardashevskiy return; 228582eae1afSAlexey Kardashevskiy 2286b348aa65SAlexey Kardashevskiy iommu_register_group(&pe->table_group, phb->hose->global_number, 2287b348aa65SAlexey Kardashevskiy pe->pe_number); 22880eaf4defSAlexey Kardashevskiy pnv_pci_link_table_and_group(phb->hose->node, 0, tbl, &pe->table_group); 2289c5773822SAlexey Kardashevskiy 2290184cd4a3SBenjamin Herrenschmidt /* Grab a 32-bit TCE table */ 22912b923ed1SGavin Shan pe_info(pe, "DMA weight %d (%d), assigned (%d) %d DMA32 segments\n", 22922b923ed1SGavin Shan weight, total_weight, base, segs); 2293184cd4a3SBenjamin Herrenschmidt pe_info(pe, " Setting up 32-bit TCE table at %08x..%08x\n", 2294acce971cSGavin Shan base * PNV_IODA1_DMA32_SEGSIZE, 2295acce971cSGavin Shan (base + segs) * PNV_IODA1_DMA32_SEGSIZE - 1); 2296184cd4a3SBenjamin Herrenschmidt 2297184cd4a3SBenjamin Herrenschmidt /* XXX Currently, we allocate one big contiguous table for the 2298184cd4a3SBenjamin Herrenschmidt * TCEs. We only really need one chunk per 256M of TCE space 2299184cd4a3SBenjamin Herrenschmidt * (ie per segment) but that's an optimization for later, it 2300184cd4a3SBenjamin Herrenschmidt * requires some added smarts with our get/put_tce implementation 2301acce971cSGavin Shan * 2302acce971cSGavin Shan * Each TCE page is 4KB in size and each TCE entry occupies 8 2303acce971cSGavin Shan * bytes 2304184cd4a3SBenjamin Herrenschmidt */ 2305acce971cSGavin Shan tce32_segsz = PNV_IODA1_DMA32_SEGSIZE >> (IOMMU_PAGE_SHIFT_4K - 3); 2306184cd4a3SBenjamin Herrenschmidt tce_mem = alloc_pages_node(phb->hose->node, GFP_KERNEL, 2307acce971cSGavin Shan get_order(tce32_segsz * segs)); 2308184cd4a3SBenjamin Herrenschmidt if (!tce_mem) { 2309184cd4a3SBenjamin Herrenschmidt pe_err(pe, " Failed to allocate a 32-bit TCE memory\n"); 2310184cd4a3SBenjamin Herrenschmidt goto fail; 2311184cd4a3SBenjamin Herrenschmidt } 2312184cd4a3SBenjamin Herrenschmidt addr = page_address(tce_mem); 2313acce971cSGavin Shan memset(addr, 0, tce32_segsz * segs); 2314184cd4a3SBenjamin Herrenschmidt 2315184cd4a3SBenjamin Herrenschmidt /* Configure HW */ 2316184cd4a3SBenjamin Herrenschmidt for (i = 0; i < segs; i++) { 2317184cd4a3SBenjamin Herrenschmidt rc = opal_pci_map_pe_dma_window(phb->opal_id, 2318184cd4a3SBenjamin Herrenschmidt pe->pe_number, 2319184cd4a3SBenjamin Herrenschmidt base + i, 1, 2320acce971cSGavin Shan __pa(addr) + tce32_segsz * i, 2321acce971cSGavin Shan tce32_segsz, IOMMU_PAGE_SIZE_4K); 2322184cd4a3SBenjamin Herrenschmidt if (rc) { 2323184cd4a3SBenjamin Herrenschmidt pe_err(pe, " Failed to configure 32-bit TCE table," 2324184cd4a3SBenjamin Herrenschmidt " err %ld\n", rc); 2325184cd4a3SBenjamin Herrenschmidt goto fail; 2326184cd4a3SBenjamin Herrenschmidt } 2327184cd4a3SBenjamin Herrenschmidt } 2328184cd4a3SBenjamin Herrenschmidt 23292b923ed1SGavin Shan /* Setup DMA32 segment mapping */ 23302b923ed1SGavin Shan for (i = base; i < base + segs; i++) 23312b923ed1SGavin Shan phb->ioda.dma32_segmap[i] = pe->pe_number; 23322b923ed1SGavin Shan 2333184cd4a3SBenjamin Herrenschmidt /* Setup linux iommu table */ 2334acce971cSGavin Shan pnv_pci_setup_iommu_table(tbl, addr, tce32_segsz * segs, 2335acce971cSGavin Shan base * PNV_IODA1_DMA32_SEGSIZE, 2336acce971cSGavin Shan IOMMU_PAGE_SHIFT_4K); 2337184cd4a3SBenjamin Herrenschmidt 2338da004c36SAlexey Kardashevskiy tbl->it_ops = &pnv_ioda1_iommu_ops; 23394793d65dSAlexey Kardashevskiy pe->table_group.tce32_start = tbl->it_offset << tbl->it_page_shift; 23404793d65dSAlexey Kardashevskiy pe->table_group.tce32_size = tbl->it_size << tbl->it_page_shift; 2341184cd4a3SBenjamin Herrenschmidt iommu_init_table(tbl, phb->hose->node); 2342184cd4a3SBenjamin Herrenschmidt 2343781a868fSWei Yang if (pe->flags & PNV_IODA_PE_DEV) { 23444617082eSAlexey Kardashevskiy /* 23454617082eSAlexey Kardashevskiy * Setting table base here only for carrying iommu_group 23464617082eSAlexey Kardashevskiy * further down to let iommu_add_device() do the job. 23474617082eSAlexey Kardashevskiy * pnv_pci_ioda_dma_dev_setup will override it later anyway. 23484617082eSAlexey Kardashevskiy */ 23494617082eSAlexey Kardashevskiy set_iommu_table_base(&pe->pdev->dev, tbl); 23504617082eSAlexey Kardashevskiy iommu_add_device(&pe->pdev->dev); 2351c5773822SAlexey Kardashevskiy } else if (pe->flags & (PNV_IODA_PE_BUS | PNV_IODA_PE_BUS_ALL)) 2352db08e1d5SAlexey Kardashevskiy pnv_ioda_setup_bus_dma(pe, pe->pbus, true); 235374251fe2SBenjamin Herrenschmidt 2354184cd4a3SBenjamin Herrenschmidt return; 2355184cd4a3SBenjamin Herrenschmidt fail: 2356184cd4a3SBenjamin Herrenschmidt /* XXX Failure: Try to fallback to 64-bit only ? */ 2357184cd4a3SBenjamin Herrenschmidt if (tce_mem) 2358acce971cSGavin Shan __free_pages(tce_mem, get_order(tce32_segsz * segs)); 23590eaf4defSAlexey Kardashevskiy if (tbl) { 23600eaf4defSAlexey Kardashevskiy pnv_pci_unlink_table_and_group(tbl, &pe->table_group); 2361e5afdf9dSAlexey Kardashevskiy iommu_tce_table_put(tbl); 23620eaf4defSAlexey Kardashevskiy } 2363184cd4a3SBenjamin Herrenschmidt } 2364184cd4a3SBenjamin Herrenschmidt 236543cb60abSAlexey Kardashevskiy static long pnv_pci_ioda2_set_window(struct iommu_table_group *table_group, 236643cb60abSAlexey Kardashevskiy int num, struct iommu_table *tbl) 236743cb60abSAlexey Kardashevskiy { 236843cb60abSAlexey Kardashevskiy struct pnv_ioda_pe *pe = container_of(table_group, struct pnv_ioda_pe, 236943cb60abSAlexey Kardashevskiy table_group); 237043cb60abSAlexey Kardashevskiy struct pnv_phb *phb = pe->phb; 237143cb60abSAlexey Kardashevskiy int64_t rc; 2372bbb845c4SAlexey Kardashevskiy const unsigned long size = tbl->it_indirect_levels ? 2373bbb845c4SAlexey Kardashevskiy tbl->it_level_size : tbl->it_size; 237443cb60abSAlexey Kardashevskiy const __u64 start_addr = tbl->it_offset << tbl->it_page_shift; 237543cb60abSAlexey Kardashevskiy const __u64 win_size = tbl->it_size << tbl->it_page_shift; 237643cb60abSAlexey Kardashevskiy 23774793d65dSAlexey Kardashevskiy pe_info(pe, "Setting up window#%d %llx..%llx pg=%x\n", num, 237843cb60abSAlexey Kardashevskiy start_addr, start_addr + win_size - 1, 237943cb60abSAlexey Kardashevskiy IOMMU_PAGE_SIZE(tbl)); 238043cb60abSAlexey Kardashevskiy 238143cb60abSAlexey Kardashevskiy /* 238243cb60abSAlexey Kardashevskiy * Map TCE table through TVT. The TVE index is the PE number 238343cb60abSAlexey Kardashevskiy * shifted by 1 bit for 32-bits DMA space. 238443cb60abSAlexey Kardashevskiy */ 238543cb60abSAlexey Kardashevskiy rc = opal_pci_map_pe_dma_window(phb->opal_id, 238643cb60abSAlexey Kardashevskiy pe->pe_number, 23874793d65dSAlexey Kardashevskiy (pe->pe_number << 1) + num, 2388bbb845c4SAlexey Kardashevskiy tbl->it_indirect_levels + 1, 238943cb60abSAlexey Kardashevskiy __pa(tbl->it_base), 2390bbb845c4SAlexey Kardashevskiy size << 3, 239143cb60abSAlexey Kardashevskiy IOMMU_PAGE_SIZE(tbl)); 239243cb60abSAlexey Kardashevskiy if (rc) { 239343cb60abSAlexey Kardashevskiy pe_err(pe, "Failed to configure TCE table, err %ld\n", rc); 239443cb60abSAlexey Kardashevskiy return rc; 239543cb60abSAlexey Kardashevskiy } 239643cb60abSAlexey Kardashevskiy 239743cb60abSAlexey Kardashevskiy pnv_pci_link_table_and_group(phb->hose->node, num, 239843cb60abSAlexey Kardashevskiy tbl, &pe->table_group); 2399ed7d9a1dSMichael Ellerman pnv_pci_ioda2_tce_invalidate_pe(pe); 240043cb60abSAlexey Kardashevskiy 240143cb60abSAlexey Kardashevskiy return 0; 240243cb60abSAlexey Kardashevskiy } 240343cb60abSAlexey Kardashevskiy 240425529100SFrederic Barrat void pnv_pci_ioda2_set_bypass(struct pnv_ioda_pe *pe, bool enable) 2405cd15b048SBenjamin Herrenschmidt { 2406cd15b048SBenjamin Herrenschmidt uint16_t window_id = (pe->pe_number << 1 ) + 1; 2407cd15b048SBenjamin Herrenschmidt int64_t rc; 2408cd15b048SBenjamin Herrenschmidt 2409cd15b048SBenjamin Herrenschmidt pe_info(pe, "%sabling 64-bit DMA bypass\n", enable ? "En" : "Dis"); 2410cd15b048SBenjamin Herrenschmidt if (enable) { 2411cd15b048SBenjamin Herrenschmidt phys_addr_t top = memblock_end_of_DRAM(); 2412cd15b048SBenjamin Herrenschmidt 2413cd15b048SBenjamin Herrenschmidt top = roundup_pow_of_two(top); 2414cd15b048SBenjamin Herrenschmidt rc = opal_pci_map_pe_dma_window_real(pe->phb->opal_id, 2415cd15b048SBenjamin Herrenschmidt pe->pe_number, 2416cd15b048SBenjamin Herrenschmidt window_id, 2417cd15b048SBenjamin Herrenschmidt pe->tce_bypass_base, 2418cd15b048SBenjamin Herrenschmidt top); 2419cd15b048SBenjamin Herrenschmidt } else { 2420cd15b048SBenjamin Herrenschmidt rc = opal_pci_map_pe_dma_window_real(pe->phb->opal_id, 2421cd15b048SBenjamin Herrenschmidt pe->pe_number, 2422cd15b048SBenjamin Herrenschmidt window_id, 2423cd15b048SBenjamin Herrenschmidt pe->tce_bypass_base, 2424cd15b048SBenjamin Herrenschmidt 0); 2425cd15b048SBenjamin Herrenschmidt } 2426cd15b048SBenjamin Herrenschmidt if (rc) 2427cd15b048SBenjamin Herrenschmidt pe_err(pe, "OPAL error %lld configuring bypass window\n", rc); 2428cd15b048SBenjamin Herrenschmidt else 2429cd15b048SBenjamin Herrenschmidt pe->tce_bypass_enabled = enable; 2430cd15b048SBenjamin Herrenschmidt } 2431cd15b048SBenjamin Herrenschmidt 24324793d65dSAlexey Kardashevskiy static long pnv_pci_ioda2_table_alloc_pages(int nid, __u64 bus_offset, 24334793d65dSAlexey Kardashevskiy __u32 page_shift, __u64 window_size, __u32 levels, 24344793d65dSAlexey Kardashevskiy struct iommu_table *tbl); 24354793d65dSAlexey Kardashevskiy 24364793d65dSAlexey Kardashevskiy static long pnv_pci_ioda2_create_table(struct iommu_table_group *table_group, 24374793d65dSAlexey Kardashevskiy int num, __u32 page_shift, __u64 window_size, __u32 levels, 24384793d65dSAlexey Kardashevskiy struct iommu_table **ptbl) 24394793d65dSAlexey Kardashevskiy { 24404793d65dSAlexey Kardashevskiy struct pnv_ioda_pe *pe = container_of(table_group, struct pnv_ioda_pe, 24414793d65dSAlexey Kardashevskiy table_group); 24424793d65dSAlexey Kardashevskiy int nid = pe->phb->hose->node; 24434793d65dSAlexey Kardashevskiy __u64 bus_offset = num ? pe->tce_bypass_base : table_group->tce32_start; 24444793d65dSAlexey Kardashevskiy long ret; 24454793d65dSAlexey Kardashevskiy struct iommu_table *tbl; 24464793d65dSAlexey Kardashevskiy 24474793d65dSAlexey Kardashevskiy tbl = pnv_pci_table_alloc(nid); 24484793d65dSAlexey Kardashevskiy if (!tbl) 24494793d65dSAlexey Kardashevskiy return -ENOMEM; 24504793d65dSAlexey Kardashevskiy 245111edf116SAlexey Kardashevskiy tbl->it_ops = &pnv_ioda2_iommu_ops; 245211edf116SAlexey Kardashevskiy 24534793d65dSAlexey Kardashevskiy ret = pnv_pci_ioda2_table_alloc_pages(nid, 24544793d65dSAlexey Kardashevskiy bus_offset, page_shift, window_size, 24554793d65dSAlexey Kardashevskiy levels, tbl); 24564793d65dSAlexey Kardashevskiy if (ret) { 2457e5afdf9dSAlexey Kardashevskiy iommu_tce_table_put(tbl); 24584793d65dSAlexey Kardashevskiy return ret; 24594793d65dSAlexey Kardashevskiy } 24604793d65dSAlexey Kardashevskiy 24614793d65dSAlexey Kardashevskiy *ptbl = tbl; 24624793d65dSAlexey Kardashevskiy 24634793d65dSAlexey Kardashevskiy return 0; 24644793d65dSAlexey Kardashevskiy } 24654793d65dSAlexey Kardashevskiy 246646d3e1e1SAlexey Kardashevskiy static long pnv_pci_ioda2_setup_default_config(struct pnv_ioda_pe *pe) 246746d3e1e1SAlexey Kardashevskiy { 246846d3e1e1SAlexey Kardashevskiy struct iommu_table *tbl = NULL; 246946d3e1e1SAlexey Kardashevskiy long rc; 247046d3e1e1SAlexey Kardashevskiy 2471bb005455SNishanth Aravamudan /* 2472fa144869SNishanth Aravamudan * crashkernel= specifies the kdump kernel's maximum memory at 2473fa144869SNishanth Aravamudan * some offset and there is no guaranteed the result is a power 2474fa144869SNishanth Aravamudan * of 2, which will cause errors later. 2475fa144869SNishanth Aravamudan */ 2476fa144869SNishanth Aravamudan const u64 max_memory = __rounddown_pow_of_two(memory_hotplug_max()); 2477fa144869SNishanth Aravamudan 2478fa144869SNishanth Aravamudan /* 2479bb005455SNishanth Aravamudan * In memory constrained environments, e.g. kdump kernel, the 2480bb005455SNishanth Aravamudan * DMA window can be larger than available memory, which will 2481bb005455SNishanth Aravamudan * cause errors later. 2482bb005455SNishanth Aravamudan */ 2483fa144869SNishanth Aravamudan const u64 window_size = min((u64)pe->table_group.tce32_size, max_memory); 2484bb005455SNishanth Aravamudan 248546d3e1e1SAlexey Kardashevskiy rc = pnv_pci_ioda2_create_table(&pe->table_group, 0, 248646d3e1e1SAlexey Kardashevskiy IOMMU_PAGE_SHIFT_4K, 2487bb005455SNishanth Aravamudan window_size, 248846d3e1e1SAlexey Kardashevskiy POWERNV_IOMMU_DEFAULT_LEVELS, &tbl); 248946d3e1e1SAlexey Kardashevskiy if (rc) { 249046d3e1e1SAlexey Kardashevskiy pe_err(pe, "Failed to create 32-bit TCE table, err %ld", 249146d3e1e1SAlexey Kardashevskiy rc); 249246d3e1e1SAlexey Kardashevskiy return rc; 249346d3e1e1SAlexey Kardashevskiy } 249446d3e1e1SAlexey Kardashevskiy 249546d3e1e1SAlexey Kardashevskiy iommu_init_table(tbl, pe->phb->hose->node); 249646d3e1e1SAlexey Kardashevskiy 249746d3e1e1SAlexey Kardashevskiy rc = pnv_pci_ioda2_set_window(&pe->table_group, 0, tbl); 249846d3e1e1SAlexey Kardashevskiy if (rc) { 249946d3e1e1SAlexey Kardashevskiy pe_err(pe, "Failed to configure 32-bit TCE table, err %ld\n", 250046d3e1e1SAlexey Kardashevskiy rc); 2501e5afdf9dSAlexey Kardashevskiy iommu_tce_table_put(tbl); 250246d3e1e1SAlexey Kardashevskiy return rc; 250346d3e1e1SAlexey Kardashevskiy } 250446d3e1e1SAlexey Kardashevskiy 250546d3e1e1SAlexey Kardashevskiy if (!pnv_iommu_bypass_disabled) 250646d3e1e1SAlexey Kardashevskiy pnv_pci_ioda2_set_bypass(pe, true); 250746d3e1e1SAlexey Kardashevskiy 250846d3e1e1SAlexey Kardashevskiy /* 250946d3e1e1SAlexey Kardashevskiy * Setting table base here only for carrying iommu_group 251046d3e1e1SAlexey Kardashevskiy * further down to let iommu_add_device() do the job. 251146d3e1e1SAlexey Kardashevskiy * pnv_pci_ioda_dma_dev_setup will override it later anyway. 251246d3e1e1SAlexey Kardashevskiy */ 251346d3e1e1SAlexey Kardashevskiy if (pe->flags & PNV_IODA_PE_DEV) 251446d3e1e1SAlexey Kardashevskiy set_iommu_table_base(&pe->pdev->dev, tbl); 251546d3e1e1SAlexey Kardashevskiy 251646d3e1e1SAlexey Kardashevskiy return 0; 251746d3e1e1SAlexey Kardashevskiy } 251846d3e1e1SAlexey Kardashevskiy 2519b5926430SAlexey Kardashevskiy #if defined(CONFIG_IOMMU_API) || defined(CONFIG_PCI_IOV) 2520b5926430SAlexey Kardashevskiy static long pnv_pci_ioda2_unset_window(struct iommu_table_group *table_group, 2521b5926430SAlexey Kardashevskiy int num) 2522b5926430SAlexey Kardashevskiy { 2523b5926430SAlexey Kardashevskiy struct pnv_ioda_pe *pe = container_of(table_group, struct pnv_ioda_pe, 2524b5926430SAlexey Kardashevskiy table_group); 2525b5926430SAlexey Kardashevskiy struct pnv_phb *phb = pe->phb; 2526b5926430SAlexey Kardashevskiy long ret; 2527b5926430SAlexey Kardashevskiy 2528b5926430SAlexey Kardashevskiy pe_info(pe, "Removing DMA window #%d\n", num); 2529b5926430SAlexey Kardashevskiy 2530b5926430SAlexey Kardashevskiy ret = opal_pci_map_pe_dma_window(phb->opal_id, pe->pe_number, 2531b5926430SAlexey Kardashevskiy (pe->pe_number << 1) + num, 2532b5926430SAlexey Kardashevskiy 0/* levels */, 0/* table address */, 2533b5926430SAlexey Kardashevskiy 0/* table size */, 0/* page size */); 2534b5926430SAlexey Kardashevskiy if (ret) 2535b5926430SAlexey Kardashevskiy pe_warn(pe, "Unmapping failed, ret = %ld\n", ret); 2536b5926430SAlexey Kardashevskiy else 2537ed7d9a1dSMichael Ellerman pnv_pci_ioda2_tce_invalidate_pe(pe); 2538b5926430SAlexey Kardashevskiy 2539b5926430SAlexey Kardashevskiy pnv_pci_unlink_table_and_group(table_group->tables[num], table_group); 2540b5926430SAlexey Kardashevskiy 2541b5926430SAlexey Kardashevskiy return ret; 2542b5926430SAlexey Kardashevskiy } 2543b5926430SAlexey Kardashevskiy #endif 2544b5926430SAlexey Kardashevskiy 2545f87a8864SAlexey Kardashevskiy #ifdef CONFIG_IOMMU_API 254600547193SAlexey Kardashevskiy static unsigned long pnv_pci_ioda2_get_table_size(__u32 page_shift, 254700547193SAlexey Kardashevskiy __u64 window_size, __u32 levels) 254800547193SAlexey Kardashevskiy { 254900547193SAlexey Kardashevskiy unsigned long bytes = 0; 255000547193SAlexey Kardashevskiy const unsigned window_shift = ilog2(window_size); 255100547193SAlexey Kardashevskiy unsigned entries_shift = window_shift - page_shift; 255200547193SAlexey Kardashevskiy unsigned table_shift = entries_shift + 3; 255300547193SAlexey Kardashevskiy unsigned long tce_table_size = max(0x1000UL, 1UL << table_shift); 255400547193SAlexey Kardashevskiy unsigned long direct_table_size; 255500547193SAlexey Kardashevskiy 255600547193SAlexey Kardashevskiy if (!levels || (levels > POWERNV_IOMMU_MAX_LEVELS) || 255700547193SAlexey Kardashevskiy (window_size > memory_hotplug_max()) || 255800547193SAlexey Kardashevskiy !is_power_of_2(window_size)) 255900547193SAlexey Kardashevskiy return 0; 256000547193SAlexey Kardashevskiy 256100547193SAlexey Kardashevskiy /* Calculate a direct table size from window_size and levels */ 256200547193SAlexey Kardashevskiy entries_shift = (entries_shift + levels - 1) / levels; 256300547193SAlexey Kardashevskiy table_shift = entries_shift + 3; 256400547193SAlexey Kardashevskiy table_shift = max_t(unsigned, table_shift, PAGE_SHIFT); 256500547193SAlexey Kardashevskiy direct_table_size = 1UL << table_shift; 256600547193SAlexey Kardashevskiy 256700547193SAlexey Kardashevskiy for ( ; levels; --levels) { 256800547193SAlexey Kardashevskiy bytes += _ALIGN_UP(tce_table_size, direct_table_size); 256900547193SAlexey Kardashevskiy 257000547193SAlexey Kardashevskiy tce_table_size /= direct_table_size; 257100547193SAlexey Kardashevskiy tce_table_size <<= 3; 2572e49a6a21SAlexey Kardashevskiy tce_table_size = max_t(unsigned long, 2573e49a6a21SAlexey Kardashevskiy tce_table_size, direct_table_size); 257400547193SAlexey Kardashevskiy } 257500547193SAlexey Kardashevskiy 257600547193SAlexey Kardashevskiy return bytes; 257700547193SAlexey Kardashevskiy } 257800547193SAlexey Kardashevskiy 2579f87a8864SAlexey Kardashevskiy static void pnv_ioda2_take_ownership(struct iommu_table_group *table_group) 2580cd15b048SBenjamin Herrenschmidt { 2581f87a8864SAlexey Kardashevskiy struct pnv_ioda_pe *pe = container_of(table_group, struct pnv_ioda_pe, 2582f87a8864SAlexey Kardashevskiy table_group); 258346d3e1e1SAlexey Kardashevskiy /* Store @tbl as pnv_pci_ioda2_unset_window() resets it */ 258446d3e1e1SAlexey Kardashevskiy struct iommu_table *tbl = pe->table_group.tables[0]; 2585cd15b048SBenjamin Herrenschmidt 2586f87a8864SAlexey Kardashevskiy pnv_pci_ioda2_set_bypass(pe, false); 258746d3e1e1SAlexey Kardashevskiy pnv_pci_ioda2_unset_window(&pe->table_group, 0); 2588db08e1d5SAlexey Kardashevskiy if (pe->pbus) 2589db08e1d5SAlexey Kardashevskiy pnv_ioda_setup_bus_dma(pe, pe->pbus, false); 2590e5afdf9dSAlexey Kardashevskiy iommu_tce_table_put(tbl); 2591cd15b048SBenjamin Herrenschmidt } 2592cd15b048SBenjamin Herrenschmidt 2593f87a8864SAlexey Kardashevskiy static void pnv_ioda2_release_ownership(struct iommu_table_group *table_group) 2594f87a8864SAlexey Kardashevskiy { 2595f87a8864SAlexey Kardashevskiy struct pnv_ioda_pe *pe = container_of(table_group, struct pnv_ioda_pe, 2596f87a8864SAlexey Kardashevskiy table_group); 2597f87a8864SAlexey Kardashevskiy 259846d3e1e1SAlexey Kardashevskiy pnv_pci_ioda2_setup_default_config(pe); 2599db08e1d5SAlexey Kardashevskiy if (pe->pbus) 2600db08e1d5SAlexey Kardashevskiy pnv_ioda_setup_bus_dma(pe, pe->pbus, false); 2601f87a8864SAlexey Kardashevskiy } 2602f87a8864SAlexey Kardashevskiy 2603f87a8864SAlexey Kardashevskiy static struct iommu_table_group_ops pnv_pci_ioda2_ops = { 260400547193SAlexey Kardashevskiy .get_table_size = pnv_pci_ioda2_get_table_size, 26054793d65dSAlexey Kardashevskiy .create_table = pnv_pci_ioda2_create_table, 26064793d65dSAlexey Kardashevskiy .set_window = pnv_pci_ioda2_set_window, 26074793d65dSAlexey Kardashevskiy .unset_window = pnv_pci_ioda2_unset_window, 2608f87a8864SAlexey Kardashevskiy .take_ownership = pnv_ioda2_take_ownership, 2609f87a8864SAlexey Kardashevskiy .release_ownership = pnv_ioda2_release_ownership, 2610f87a8864SAlexey Kardashevskiy }; 2611b5cb9ab1SAlexey Kardashevskiy 2612b5cb9ab1SAlexey Kardashevskiy static int gpe_table_group_to_npe_cb(struct device *dev, void *opaque) 2613b5cb9ab1SAlexey Kardashevskiy { 2614b5cb9ab1SAlexey Kardashevskiy struct pci_controller *hose; 2615b5cb9ab1SAlexey Kardashevskiy struct pnv_phb *phb; 2616b5cb9ab1SAlexey Kardashevskiy struct pnv_ioda_pe **ptmppe = opaque; 2617b5cb9ab1SAlexey Kardashevskiy struct pci_dev *pdev = container_of(dev, struct pci_dev, dev); 2618b5cb9ab1SAlexey Kardashevskiy struct pci_dn *pdn = pci_get_pdn(pdev); 2619b5cb9ab1SAlexey Kardashevskiy 2620b5cb9ab1SAlexey Kardashevskiy if (!pdn || pdn->pe_number == IODA_INVALID_PE) 2621b5cb9ab1SAlexey Kardashevskiy return 0; 2622b5cb9ab1SAlexey Kardashevskiy 2623b5cb9ab1SAlexey Kardashevskiy hose = pci_bus_to_host(pdev->bus); 2624b5cb9ab1SAlexey Kardashevskiy phb = hose->private_data; 2625b5cb9ab1SAlexey Kardashevskiy if (phb->type != PNV_PHB_NPU) 2626b5cb9ab1SAlexey Kardashevskiy return 0; 2627b5cb9ab1SAlexey Kardashevskiy 2628b5cb9ab1SAlexey Kardashevskiy *ptmppe = &phb->ioda.pe_array[pdn->pe_number]; 2629b5cb9ab1SAlexey Kardashevskiy 2630b5cb9ab1SAlexey Kardashevskiy return 1; 2631b5cb9ab1SAlexey Kardashevskiy } 2632b5cb9ab1SAlexey Kardashevskiy 2633b5cb9ab1SAlexey Kardashevskiy /* 2634b5cb9ab1SAlexey Kardashevskiy * This returns PE of associated NPU. 2635b5cb9ab1SAlexey Kardashevskiy * This assumes that NPU is in the same IOMMU group with GPU and there is 2636b5cb9ab1SAlexey Kardashevskiy * no other PEs. 2637b5cb9ab1SAlexey Kardashevskiy */ 2638b5cb9ab1SAlexey Kardashevskiy static struct pnv_ioda_pe *gpe_table_group_to_npe( 2639b5cb9ab1SAlexey Kardashevskiy struct iommu_table_group *table_group) 2640b5cb9ab1SAlexey Kardashevskiy { 2641b5cb9ab1SAlexey Kardashevskiy struct pnv_ioda_pe *npe = NULL; 2642b5cb9ab1SAlexey Kardashevskiy int ret = iommu_group_for_each_dev(table_group->group, &npe, 2643b5cb9ab1SAlexey Kardashevskiy gpe_table_group_to_npe_cb); 2644b5cb9ab1SAlexey Kardashevskiy 2645b5cb9ab1SAlexey Kardashevskiy BUG_ON(!ret || !npe); 2646b5cb9ab1SAlexey Kardashevskiy 2647b5cb9ab1SAlexey Kardashevskiy return npe; 2648b5cb9ab1SAlexey Kardashevskiy } 2649b5cb9ab1SAlexey Kardashevskiy 2650b5cb9ab1SAlexey Kardashevskiy static long pnv_pci_ioda2_npu_set_window(struct iommu_table_group *table_group, 2651b5cb9ab1SAlexey Kardashevskiy int num, struct iommu_table *tbl) 2652b5cb9ab1SAlexey Kardashevskiy { 2653b5cb9ab1SAlexey Kardashevskiy long ret = pnv_pci_ioda2_set_window(table_group, num, tbl); 2654b5cb9ab1SAlexey Kardashevskiy 2655b5cb9ab1SAlexey Kardashevskiy if (ret) 2656b5cb9ab1SAlexey Kardashevskiy return ret; 2657b5cb9ab1SAlexey Kardashevskiy 2658b5cb9ab1SAlexey Kardashevskiy ret = pnv_npu_set_window(gpe_table_group_to_npe(table_group), num, tbl); 2659b5cb9ab1SAlexey Kardashevskiy if (ret) 2660b5cb9ab1SAlexey Kardashevskiy pnv_pci_ioda2_unset_window(table_group, num); 2661b5cb9ab1SAlexey Kardashevskiy 2662b5cb9ab1SAlexey Kardashevskiy return ret; 2663b5cb9ab1SAlexey Kardashevskiy } 2664b5cb9ab1SAlexey Kardashevskiy 2665b5cb9ab1SAlexey Kardashevskiy static long pnv_pci_ioda2_npu_unset_window( 2666b5cb9ab1SAlexey Kardashevskiy struct iommu_table_group *table_group, 2667b5cb9ab1SAlexey Kardashevskiy int num) 2668b5cb9ab1SAlexey Kardashevskiy { 2669b5cb9ab1SAlexey Kardashevskiy long ret = pnv_pci_ioda2_unset_window(table_group, num); 2670b5cb9ab1SAlexey Kardashevskiy 2671b5cb9ab1SAlexey Kardashevskiy if (ret) 2672b5cb9ab1SAlexey Kardashevskiy return ret; 2673b5cb9ab1SAlexey Kardashevskiy 2674b5cb9ab1SAlexey Kardashevskiy return pnv_npu_unset_window(gpe_table_group_to_npe(table_group), num); 2675b5cb9ab1SAlexey Kardashevskiy } 2676b5cb9ab1SAlexey Kardashevskiy 2677b5cb9ab1SAlexey Kardashevskiy static void pnv_ioda2_npu_take_ownership(struct iommu_table_group *table_group) 2678b5cb9ab1SAlexey Kardashevskiy { 2679b5cb9ab1SAlexey Kardashevskiy /* 2680b5cb9ab1SAlexey Kardashevskiy * Detach NPU first as pnv_ioda2_take_ownership() will destroy 2681b5cb9ab1SAlexey Kardashevskiy * the iommu_table if 32bit DMA is enabled. 2682b5cb9ab1SAlexey Kardashevskiy */ 2683b5cb9ab1SAlexey Kardashevskiy pnv_npu_take_ownership(gpe_table_group_to_npe(table_group)); 2684b5cb9ab1SAlexey Kardashevskiy pnv_ioda2_take_ownership(table_group); 2685b5cb9ab1SAlexey Kardashevskiy } 2686b5cb9ab1SAlexey Kardashevskiy 2687b5cb9ab1SAlexey Kardashevskiy static struct iommu_table_group_ops pnv_pci_ioda2_npu_ops = { 2688b5cb9ab1SAlexey Kardashevskiy .get_table_size = pnv_pci_ioda2_get_table_size, 2689b5cb9ab1SAlexey Kardashevskiy .create_table = pnv_pci_ioda2_create_table, 2690b5cb9ab1SAlexey Kardashevskiy .set_window = pnv_pci_ioda2_npu_set_window, 2691b5cb9ab1SAlexey Kardashevskiy .unset_window = pnv_pci_ioda2_npu_unset_window, 2692b5cb9ab1SAlexey Kardashevskiy .take_ownership = pnv_ioda2_npu_take_ownership, 2693b5cb9ab1SAlexey Kardashevskiy .release_ownership = pnv_ioda2_release_ownership, 2694b5cb9ab1SAlexey Kardashevskiy }; 2695b5cb9ab1SAlexey Kardashevskiy 2696b5cb9ab1SAlexey Kardashevskiy static void pnv_pci_ioda_setup_iommu_api(void) 2697b5cb9ab1SAlexey Kardashevskiy { 2698b5cb9ab1SAlexey Kardashevskiy struct pci_controller *hose, *tmp; 2699b5cb9ab1SAlexey Kardashevskiy struct pnv_phb *phb; 2700b5cb9ab1SAlexey Kardashevskiy struct pnv_ioda_pe *pe, *gpe; 2701b5cb9ab1SAlexey Kardashevskiy 2702b5cb9ab1SAlexey Kardashevskiy /* 2703b5cb9ab1SAlexey Kardashevskiy * Now we have all PHBs discovered, time to add NPU devices to 2704b5cb9ab1SAlexey Kardashevskiy * the corresponding IOMMU groups. 2705b5cb9ab1SAlexey Kardashevskiy */ 2706b5cb9ab1SAlexey Kardashevskiy list_for_each_entry_safe(hose, tmp, &hose_list, list_node) { 2707b5cb9ab1SAlexey Kardashevskiy phb = hose->private_data; 2708b5cb9ab1SAlexey Kardashevskiy 2709b5cb9ab1SAlexey Kardashevskiy if (phb->type != PNV_PHB_NPU) 2710b5cb9ab1SAlexey Kardashevskiy continue; 2711b5cb9ab1SAlexey Kardashevskiy 2712b5cb9ab1SAlexey Kardashevskiy list_for_each_entry(pe, &phb->ioda.pe_list, list) { 2713b5cb9ab1SAlexey Kardashevskiy gpe = pnv_pci_npu_setup_iommu(pe); 2714b5cb9ab1SAlexey Kardashevskiy if (gpe) 2715b5cb9ab1SAlexey Kardashevskiy gpe->table_group.ops = &pnv_pci_ioda2_npu_ops; 2716b5cb9ab1SAlexey Kardashevskiy } 2717b5cb9ab1SAlexey Kardashevskiy } 2718b5cb9ab1SAlexey Kardashevskiy } 2719b5cb9ab1SAlexey Kardashevskiy #else /* !CONFIG_IOMMU_API */ 2720b5cb9ab1SAlexey Kardashevskiy static void pnv_pci_ioda_setup_iommu_api(void) { }; 2721f87a8864SAlexey Kardashevskiy #endif 2722f87a8864SAlexey Kardashevskiy 2723bbb845c4SAlexey Kardashevskiy static __be64 *pnv_pci_ioda2_table_do_alloc_pages(int nid, unsigned shift, 2724bbb845c4SAlexey Kardashevskiy unsigned levels, unsigned long limit, 27253ba3a73eSAlexey Kardashevskiy unsigned long *current_offset, unsigned long *total_allocated) 2726aca6913fSAlexey Kardashevskiy { 2727aca6913fSAlexey Kardashevskiy struct page *tce_mem = NULL; 2728bbb845c4SAlexey Kardashevskiy __be64 *addr, *tmp; 2729aca6913fSAlexey Kardashevskiy unsigned order = max_t(unsigned, shift, PAGE_SHIFT) - PAGE_SHIFT; 2730bbb845c4SAlexey Kardashevskiy unsigned long allocated = 1UL << (order + PAGE_SHIFT); 2731bbb845c4SAlexey Kardashevskiy unsigned entries = 1UL << (shift - 3); 2732bbb845c4SAlexey Kardashevskiy long i; 2733aca6913fSAlexey Kardashevskiy 2734aca6913fSAlexey Kardashevskiy tce_mem = alloc_pages_node(nid, GFP_KERNEL, order); 2735aca6913fSAlexey Kardashevskiy if (!tce_mem) { 2736aca6913fSAlexey Kardashevskiy pr_err("Failed to allocate a TCE memory, order=%d\n", order); 2737aca6913fSAlexey Kardashevskiy return NULL; 2738aca6913fSAlexey Kardashevskiy } 2739aca6913fSAlexey Kardashevskiy addr = page_address(tce_mem); 2740bbb845c4SAlexey Kardashevskiy memset(addr, 0, allocated); 27413ba3a73eSAlexey Kardashevskiy *total_allocated += allocated; 2742bbb845c4SAlexey Kardashevskiy 2743bbb845c4SAlexey Kardashevskiy --levels; 2744bbb845c4SAlexey Kardashevskiy if (!levels) { 2745bbb845c4SAlexey Kardashevskiy *current_offset += allocated; 2746bbb845c4SAlexey Kardashevskiy return addr; 2747bbb845c4SAlexey Kardashevskiy } 2748bbb845c4SAlexey Kardashevskiy 2749bbb845c4SAlexey Kardashevskiy for (i = 0; i < entries; ++i) { 2750bbb845c4SAlexey Kardashevskiy tmp = pnv_pci_ioda2_table_do_alloc_pages(nid, shift, 27513ba3a73eSAlexey Kardashevskiy levels, limit, current_offset, total_allocated); 2752bbb845c4SAlexey Kardashevskiy if (!tmp) 2753bbb845c4SAlexey Kardashevskiy break; 2754bbb845c4SAlexey Kardashevskiy 2755bbb845c4SAlexey Kardashevskiy addr[i] = cpu_to_be64(__pa(tmp) | 2756bbb845c4SAlexey Kardashevskiy TCE_PCI_READ | TCE_PCI_WRITE); 2757bbb845c4SAlexey Kardashevskiy 2758bbb845c4SAlexey Kardashevskiy if (*current_offset >= limit) 2759bbb845c4SAlexey Kardashevskiy break; 2760bbb845c4SAlexey Kardashevskiy } 2761aca6913fSAlexey Kardashevskiy 2762aca6913fSAlexey Kardashevskiy return addr; 2763aca6913fSAlexey Kardashevskiy } 2764aca6913fSAlexey Kardashevskiy 2765bbb845c4SAlexey Kardashevskiy static void pnv_pci_ioda2_table_do_free_pages(__be64 *addr, 2766bbb845c4SAlexey Kardashevskiy unsigned long size, unsigned level); 2767bbb845c4SAlexey Kardashevskiy 2768aca6913fSAlexey Kardashevskiy static long pnv_pci_ioda2_table_alloc_pages(int nid, __u64 bus_offset, 2769bbb845c4SAlexey Kardashevskiy __u32 page_shift, __u64 window_size, __u32 levels, 2770bbb845c4SAlexey Kardashevskiy struct iommu_table *tbl) 2771aca6913fSAlexey Kardashevskiy { 2772aca6913fSAlexey Kardashevskiy void *addr; 27733ba3a73eSAlexey Kardashevskiy unsigned long offset = 0, level_shift, total_allocated = 0; 2774aca6913fSAlexey Kardashevskiy const unsigned window_shift = ilog2(window_size); 2775aca6913fSAlexey Kardashevskiy unsigned entries_shift = window_shift - page_shift; 2776aca6913fSAlexey Kardashevskiy unsigned table_shift = max_t(unsigned, entries_shift + 3, PAGE_SHIFT); 2777aca6913fSAlexey Kardashevskiy const unsigned long tce_table_size = 1UL << table_shift; 2778aca6913fSAlexey Kardashevskiy 2779bbb845c4SAlexey Kardashevskiy if (!levels || (levels > POWERNV_IOMMU_MAX_LEVELS)) 2780bbb845c4SAlexey Kardashevskiy return -EINVAL; 2781bbb845c4SAlexey Kardashevskiy 2782aca6913fSAlexey Kardashevskiy if ((window_size > memory_hotplug_max()) || !is_power_of_2(window_size)) 2783aca6913fSAlexey Kardashevskiy return -EINVAL; 2784aca6913fSAlexey Kardashevskiy 2785bbb845c4SAlexey Kardashevskiy /* Adjust direct table size from window_size and levels */ 2786bbb845c4SAlexey Kardashevskiy entries_shift = (entries_shift + levels - 1) / levels; 2787bbb845c4SAlexey Kardashevskiy level_shift = entries_shift + 3; 2788bbb845c4SAlexey Kardashevskiy level_shift = max_t(unsigned, level_shift, PAGE_SHIFT); 2789bbb845c4SAlexey Kardashevskiy 27907aafac11SAlexey Kardashevskiy if ((level_shift - 3) * levels + page_shift >= 60) 27917aafac11SAlexey Kardashevskiy return -EINVAL; 27927aafac11SAlexey Kardashevskiy 2793aca6913fSAlexey Kardashevskiy /* Allocate TCE table */ 2794bbb845c4SAlexey Kardashevskiy addr = pnv_pci_ioda2_table_do_alloc_pages(nid, level_shift, 27953ba3a73eSAlexey Kardashevskiy levels, tce_table_size, &offset, &total_allocated); 2796bbb845c4SAlexey Kardashevskiy 2797bbb845c4SAlexey Kardashevskiy /* addr==NULL means that the first level allocation failed */ 2798aca6913fSAlexey Kardashevskiy if (!addr) 2799aca6913fSAlexey Kardashevskiy return -ENOMEM; 2800aca6913fSAlexey Kardashevskiy 2801bbb845c4SAlexey Kardashevskiy /* 2802bbb845c4SAlexey Kardashevskiy * First level was allocated but some lower level failed as 2803bbb845c4SAlexey Kardashevskiy * we did not allocate as much as we wanted, 2804bbb845c4SAlexey Kardashevskiy * release partially allocated table. 2805bbb845c4SAlexey Kardashevskiy */ 2806bbb845c4SAlexey Kardashevskiy if (offset < tce_table_size) { 2807bbb845c4SAlexey Kardashevskiy pnv_pci_ioda2_table_do_free_pages(addr, 2808bbb845c4SAlexey Kardashevskiy 1ULL << (level_shift - 3), levels - 1); 2809bbb845c4SAlexey Kardashevskiy return -ENOMEM; 2810bbb845c4SAlexey Kardashevskiy } 2811bbb845c4SAlexey Kardashevskiy 2812aca6913fSAlexey Kardashevskiy /* Setup linux iommu table */ 2813aca6913fSAlexey Kardashevskiy pnv_pci_setup_iommu_table(tbl, addr, tce_table_size, bus_offset, 2814aca6913fSAlexey Kardashevskiy page_shift); 2815bbb845c4SAlexey Kardashevskiy tbl->it_level_size = 1ULL << (level_shift - 3); 2816bbb845c4SAlexey Kardashevskiy tbl->it_indirect_levels = levels - 1; 28173ba3a73eSAlexey Kardashevskiy tbl->it_allocated_size = total_allocated; 2818aca6913fSAlexey Kardashevskiy 2819aca6913fSAlexey Kardashevskiy pr_devel("Created TCE table: ws=%08llx ts=%lx @%08llx\n", 2820aca6913fSAlexey Kardashevskiy window_size, tce_table_size, bus_offset); 2821aca6913fSAlexey Kardashevskiy 2822aca6913fSAlexey Kardashevskiy return 0; 2823aca6913fSAlexey Kardashevskiy } 2824aca6913fSAlexey Kardashevskiy 2825bbb845c4SAlexey Kardashevskiy static void pnv_pci_ioda2_table_do_free_pages(__be64 *addr, 2826bbb845c4SAlexey Kardashevskiy unsigned long size, unsigned level) 2827bbb845c4SAlexey Kardashevskiy { 2828bbb845c4SAlexey Kardashevskiy const unsigned long addr_ul = (unsigned long) addr & 2829bbb845c4SAlexey Kardashevskiy ~(TCE_PCI_READ | TCE_PCI_WRITE); 2830bbb845c4SAlexey Kardashevskiy 2831bbb845c4SAlexey Kardashevskiy if (level) { 2832bbb845c4SAlexey Kardashevskiy long i; 2833bbb845c4SAlexey Kardashevskiy u64 *tmp = (u64 *) addr_ul; 2834bbb845c4SAlexey Kardashevskiy 2835bbb845c4SAlexey Kardashevskiy for (i = 0; i < size; ++i) { 2836bbb845c4SAlexey Kardashevskiy unsigned long hpa = be64_to_cpu(tmp[i]); 2837bbb845c4SAlexey Kardashevskiy 2838bbb845c4SAlexey Kardashevskiy if (!(hpa & (TCE_PCI_READ | TCE_PCI_WRITE))) 2839bbb845c4SAlexey Kardashevskiy continue; 2840bbb845c4SAlexey Kardashevskiy 2841bbb845c4SAlexey Kardashevskiy pnv_pci_ioda2_table_do_free_pages(__va(hpa), size, 2842bbb845c4SAlexey Kardashevskiy level - 1); 2843bbb845c4SAlexey Kardashevskiy } 2844bbb845c4SAlexey Kardashevskiy } 2845bbb845c4SAlexey Kardashevskiy 2846bbb845c4SAlexey Kardashevskiy free_pages(addr_ul, get_order(size << 3)); 2847bbb845c4SAlexey Kardashevskiy } 2848bbb845c4SAlexey Kardashevskiy 2849aca6913fSAlexey Kardashevskiy static void pnv_pci_ioda2_table_free_pages(struct iommu_table *tbl) 2850aca6913fSAlexey Kardashevskiy { 2851bbb845c4SAlexey Kardashevskiy const unsigned long size = tbl->it_indirect_levels ? 2852bbb845c4SAlexey Kardashevskiy tbl->it_level_size : tbl->it_size; 2853bbb845c4SAlexey Kardashevskiy 2854aca6913fSAlexey Kardashevskiy if (!tbl->it_size) 2855aca6913fSAlexey Kardashevskiy return; 2856aca6913fSAlexey Kardashevskiy 2857bbb845c4SAlexey Kardashevskiy pnv_pci_ioda2_table_do_free_pages((__be64 *)tbl->it_base, size, 2858bbb845c4SAlexey Kardashevskiy tbl->it_indirect_levels); 2859aca6913fSAlexey Kardashevskiy } 2860aca6913fSAlexey Kardashevskiy 2861373f5657SGavin Shan static void pnv_pci_ioda2_setup_dma_pe(struct pnv_phb *phb, 2862373f5657SGavin Shan struct pnv_ioda_pe *pe) 2863373f5657SGavin Shan { 2864373f5657SGavin Shan int64_t rc; 2865373f5657SGavin Shan 2866ccd1c191SGavin Shan if (!pnv_pci_ioda_pe_dma_weight(pe)) 2867ccd1c191SGavin Shan return; 2868ccd1c191SGavin Shan 2869f87a8864SAlexey Kardashevskiy /* TVE #1 is selected by PCI address bit 59 */ 2870f87a8864SAlexey Kardashevskiy pe->tce_bypass_base = 1ull << 59; 2871f87a8864SAlexey Kardashevskiy 2872b348aa65SAlexey Kardashevskiy iommu_register_group(&pe->table_group, phb->hose->global_number, 2873b348aa65SAlexey Kardashevskiy pe->pe_number); 2874c5773822SAlexey Kardashevskiy 2875373f5657SGavin Shan /* The PE will reserve all possible 32-bits space */ 2876373f5657SGavin Shan pe_info(pe, "Setting up 32-bit TCE table at 0..%08x\n", 2877aca6913fSAlexey Kardashevskiy phb->ioda.m32_pci_base); 2878373f5657SGavin Shan 2879e5aad1e6SAlexey Kardashevskiy /* Setup linux iommu table */ 28804793d65dSAlexey Kardashevskiy pe->table_group.tce32_start = 0; 28814793d65dSAlexey Kardashevskiy pe->table_group.tce32_size = phb->ioda.m32_pci_base; 28824793d65dSAlexey Kardashevskiy pe->table_group.max_dynamic_windows_supported = 28834793d65dSAlexey Kardashevskiy IOMMU_TABLE_GROUP_MAX_TABLES; 28844793d65dSAlexey Kardashevskiy pe->table_group.max_levels = POWERNV_IOMMU_MAX_LEVELS; 28854793d65dSAlexey Kardashevskiy pe->table_group.pgsizes = SZ_4K | SZ_64K | SZ_16M; 2886e5aad1e6SAlexey Kardashevskiy #ifdef CONFIG_IOMMU_API 2887e5aad1e6SAlexey Kardashevskiy pe->table_group.ops = &pnv_pci_ioda2_ops; 2888e5aad1e6SAlexey Kardashevskiy #endif 2889e5aad1e6SAlexey Kardashevskiy 289046d3e1e1SAlexey Kardashevskiy rc = pnv_pci_ioda2_setup_default_config(pe); 2891801846d1SGavin Shan if (rc) 289246d3e1e1SAlexey Kardashevskiy return; 289346d3e1e1SAlexey Kardashevskiy 289420f13b95SAlexey Kardashevskiy if (pe->flags & (PNV_IODA_PE_BUS | PNV_IODA_PE_BUS_ALL)) 2895db08e1d5SAlexey Kardashevskiy pnv_ioda_setup_bus_dma(pe, pe->pbus, true); 2896373f5657SGavin Shan } 2897373f5657SGavin Shan 2898184cd4a3SBenjamin Herrenschmidt #ifdef CONFIG_PCI_MSI 28994ee11c1aSSuresh Warrier int64_t pnv_opal_pci_msi_eoi(struct irq_chip *chip, unsigned int hw_irq) 2900137436c9SGavin Shan { 2901137436c9SGavin Shan struct pnv_phb *phb = container_of(chip, struct pnv_phb, 2902137436c9SGavin Shan ioda.irq_chip); 2903137436c9SGavin Shan 29044ee11c1aSSuresh Warrier return opal_pci_msi_eoi(phb->opal_id, hw_irq); 29054ee11c1aSSuresh Warrier } 29064ee11c1aSSuresh Warrier 29074ee11c1aSSuresh Warrier static void pnv_ioda2_msi_eoi(struct irq_data *d) 29084ee11c1aSSuresh Warrier { 29094ee11c1aSSuresh Warrier int64_t rc; 29104ee11c1aSSuresh Warrier unsigned int hw_irq = (unsigned int)irqd_to_hwirq(d); 29114ee11c1aSSuresh Warrier struct irq_chip *chip = irq_data_get_irq_chip(d); 29124ee11c1aSSuresh Warrier 29134ee11c1aSSuresh Warrier rc = pnv_opal_pci_msi_eoi(chip, hw_irq); 2914137436c9SGavin Shan WARN_ON_ONCE(rc); 2915137436c9SGavin Shan 2916137436c9SGavin Shan icp_native_eoi(d); 2917137436c9SGavin Shan } 2918137436c9SGavin Shan 2919fd9a1c26SIan Munsie 2920f456834aSIan Munsie void pnv_set_msi_irq_chip(struct pnv_phb *phb, unsigned int virq) 2921fd9a1c26SIan Munsie { 2922fd9a1c26SIan Munsie struct irq_data *idata; 2923fd9a1c26SIan Munsie struct irq_chip *ichip; 2924fd9a1c26SIan Munsie 2925fb111334SBenjamin Herrenschmidt /* The MSI EOI OPAL call is only needed on PHB3 */ 2926fb111334SBenjamin Herrenschmidt if (phb->model != PNV_PHB_MODEL_PHB3) 2927fd9a1c26SIan Munsie return; 2928fd9a1c26SIan Munsie 2929fd9a1c26SIan Munsie if (!phb->ioda.irq_chip_init) { 2930fd9a1c26SIan Munsie /* 2931fd9a1c26SIan Munsie * First time we setup an MSI IRQ, we need to setup the 2932fd9a1c26SIan Munsie * corresponding IRQ chip to route correctly. 2933fd9a1c26SIan Munsie */ 2934fd9a1c26SIan Munsie idata = irq_get_irq_data(virq); 2935fd9a1c26SIan Munsie ichip = irq_data_get_irq_chip(idata); 2936fd9a1c26SIan Munsie phb->ioda.irq_chip_init = 1; 2937fd9a1c26SIan Munsie phb->ioda.irq_chip = *ichip; 2938fd9a1c26SIan Munsie phb->ioda.irq_chip.irq_eoi = pnv_ioda2_msi_eoi; 2939fd9a1c26SIan Munsie } 2940fd9a1c26SIan Munsie irq_set_chip(virq, &phb->ioda.irq_chip); 2941fd9a1c26SIan Munsie } 2942fd9a1c26SIan Munsie 29434ee11c1aSSuresh Warrier /* 29444ee11c1aSSuresh Warrier * Returns true iff chip is something that we could call 29454ee11c1aSSuresh Warrier * pnv_opal_pci_msi_eoi for. 29464ee11c1aSSuresh Warrier */ 29474ee11c1aSSuresh Warrier bool is_pnv_opal_msi(struct irq_chip *chip) 29484ee11c1aSSuresh Warrier { 29494ee11c1aSSuresh Warrier return chip->irq_eoi == pnv_ioda2_msi_eoi; 29504ee11c1aSSuresh Warrier } 29514ee11c1aSSuresh Warrier EXPORT_SYMBOL_GPL(is_pnv_opal_msi); 29524ee11c1aSSuresh Warrier 2953184cd4a3SBenjamin Herrenschmidt static int pnv_pci_ioda_msi_setup(struct pnv_phb *phb, struct pci_dev *dev, 2954137436c9SGavin Shan unsigned int hwirq, unsigned int virq, 2955137436c9SGavin Shan unsigned int is_64, struct msi_msg *msg) 2956184cd4a3SBenjamin Herrenschmidt { 2957184cd4a3SBenjamin Herrenschmidt struct pnv_ioda_pe *pe = pnv_ioda_get_pe(dev); 2958184cd4a3SBenjamin Herrenschmidt unsigned int xive_num = hwirq - phb->msi_base; 29593a1a4661SBenjamin Herrenschmidt __be32 data; 2960184cd4a3SBenjamin Herrenschmidt int rc; 2961184cd4a3SBenjamin Herrenschmidt 2962184cd4a3SBenjamin Herrenschmidt /* No PE assigned ? bail out ... no MSI for you ! */ 2963184cd4a3SBenjamin Herrenschmidt if (pe == NULL) 2964184cd4a3SBenjamin Herrenschmidt return -ENXIO; 2965184cd4a3SBenjamin Herrenschmidt 2966184cd4a3SBenjamin Herrenschmidt /* Check if we have an MVE */ 2967184cd4a3SBenjamin Herrenschmidt if (pe->mve_number < 0) 2968184cd4a3SBenjamin Herrenschmidt return -ENXIO; 2969184cd4a3SBenjamin Herrenschmidt 2970b72c1f65SBenjamin Herrenschmidt /* Force 32-bit MSI on some broken devices */ 297136074381SBenjamin Herrenschmidt if (dev->no_64bit_msi) 2972b72c1f65SBenjamin Herrenschmidt is_64 = 0; 2973b72c1f65SBenjamin Herrenschmidt 2974184cd4a3SBenjamin Herrenschmidt /* Assign XIVE to PE */ 2975184cd4a3SBenjamin Herrenschmidt rc = opal_pci_set_xive_pe(phb->opal_id, pe->pe_number, xive_num); 2976184cd4a3SBenjamin Herrenschmidt if (rc) { 2977184cd4a3SBenjamin Herrenschmidt pr_warn("%s: OPAL error %d setting XIVE %d PE\n", 2978184cd4a3SBenjamin Herrenschmidt pci_name(dev), rc, xive_num); 2979184cd4a3SBenjamin Herrenschmidt return -EIO; 2980184cd4a3SBenjamin Herrenschmidt } 2981184cd4a3SBenjamin Herrenschmidt 2982184cd4a3SBenjamin Herrenschmidt if (is_64) { 29833a1a4661SBenjamin Herrenschmidt __be64 addr64; 29843a1a4661SBenjamin Herrenschmidt 2985184cd4a3SBenjamin Herrenschmidt rc = opal_get_msi_64(phb->opal_id, pe->mve_number, xive_num, 1, 2986184cd4a3SBenjamin Herrenschmidt &addr64, &data); 2987184cd4a3SBenjamin Herrenschmidt if (rc) { 2988184cd4a3SBenjamin Herrenschmidt pr_warn("%s: OPAL error %d getting 64-bit MSI data\n", 2989184cd4a3SBenjamin Herrenschmidt pci_name(dev), rc); 2990184cd4a3SBenjamin Herrenschmidt return -EIO; 2991184cd4a3SBenjamin Herrenschmidt } 29923a1a4661SBenjamin Herrenschmidt msg->address_hi = be64_to_cpu(addr64) >> 32; 29933a1a4661SBenjamin Herrenschmidt msg->address_lo = be64_to_cpu(addr64) & 0xfffffffful; 2994184cd4a3SBenjamin Herrenschmidt } else { 29953a1a4661SBenjamin Herrenschmidt __be32 addr32; 29963a1a4661SBenjamin Herrenschmidt 2997184cd4a3SBenjamin Herrenschmidt rc = opal_get_msi_32(phb->opal_id, pe->mve_number, xive_num, 1, 2998184cd4a3SBenjamin Herrenschmidt &addr32, &data); 2999184cd4a3SBenjamin Herrenschmidt if (rc) { 3000184cd4a3SBenjamin Herrenschmidt pr_warn("%s: OPAL error %d getting 32-bit MSI data\n", 3001184cd4a3SBenjamin Herrenschmidt pci_name(dev), rc); 3002184cd4a3SBenjamin Herrenschmidt return -EIO; 3003184cd4a3SBenjamin Herrenschmidt } 3004184cd4a3SBenjamin Herrenschmidt msg->address_hi = 0; 30053a1a4661SBenjamin Herrenschmidt msg->address_lo = be32_to_cpu(addr32); 3006184cd4a3SBenjamin Herrenschmidt } 30073a1a4661SBenjamin Herrenschmidt msg->data = be32_to_cpu(data); 3008184cd4a3SBenjamin Herrenschmidt 3009f456834aSIan Munsie pnv_set_msi_irq_chip(phb, virq); 3010137436c9SGavin Shan 3011184cd4a3SBenjamin Herrenschmidt pr_devel("%s: %s-bit MSI on hwirq %x (xive #%d)," 30121f52f176SRussell Currey " address=%x_%08x data=%x PE# %x\n", 3013184cd4a3SBenjamin Herrenschmidt pci_name(dev), is_64 ? "64" : "32", hwirq, xive_num, 3014184cd4a3SBenjamin Herrenschmidt msg->address_hi, msg->address_lo, data, pe->pe_number); 3015184cd4a3SBenjamin Herrenschmidt 3016184cd4a3SBenjamin Herrenschmidt return 0; 3017184cd4a3SBenjamin Herrenschmidt } 3018184cd4a3SBenjamin Herrenschmidt 3019184cd4a3SBenjamin Herrenschmidt static void pnv_pci_init_ioda_msis(struct pnv_phb *phb) 3020184cd4a3SBenjamin Herrenschmidt { 3021fb1b55d6SGavin Shan unsigned int count; 3022184cd4a3SBenjamin Herrenschmidt const __be32 *prop = of_get_property(phb->hose->dn, 3023184cd4a3SBenjamin Herrenschmidt "ibm,opal-msi-ranges", NULL); 3024184cd4a3SBenjamin Herrenschmidt if (!prop) { 3025184cd4a3SBenjamin Herrenschmidt /* BML Fallback */ 3026184cd4a3SBenjamin Herrenschmidt prop = of_get_property(phb->hose->dn, "msi-ranges", NULL); 3027184cd4a3SBenjamin Herrenschmidt } 3028184cd4a3SBenjamin Herrenschmidt if (!prop) 3029184cd4a3SBenjamin Herrenschmidt return; 3030184cd4a3SBenjamin Herrenschmidt 3031184cd4a3SBenjamin Herrenschmidt phb->msi_base = be32_to_cpup(prop); 3032fb1b55d6SGavin Shan count = be32_to_cpup(prop + 1); 3033fb1b55d6SGavin Shan if (msi_bitmap_alloc(&phb->msi_bmp, count, phb->hose->dn)) { 3034184cd4a3SBenjamin Herrenschmidt pr_err("PCI %d: Failed to allocate MSI bitmap !\n", 3035184cd4a3SBenjamin Herrenschmidt phb->hose->global_number); 3036184cd4a3SBenjamin Herrenschmidt return; 3037184cd4a3SBenjamin Herrenschmidt } 3038fb1b55d6SGavin Shan 3039184cd4a3SBenjamin Herrenschmidt phb->msi_setup = pnv_pci_ioda_msi_setup; 3040184cd4a3SBenjamin Herrenschmidt phb->msi32_support = 1; 3041184cd4a3SBenjamin Herrenschmidt pr_info(" Allocated bitmap for %d MSIs (base IRQ 0x%x)\n", 3042fb1b55d6SGavin Shan count, phb->msi_base); 3043184cd4a3SBenjamin Herrenschmidt } 3044184cd4a3SBenjamin Herrenschmidt #else 3045184cd4a3SBenjamin Herrenschmidt static void pnv_pci_init_ioda_msis(struct pnv_phb *phb) { } 3046184cd4a3SBenjamin Herrenschmidt #endif /* CONFIG_PCI_MSI */ 3047184cd4a3SBenjamin Herrenschmidt 30486e628c7dSWei Yang #ifdef CONFIG_PCI_IOV 30496e628c7dSWei Yang static void pnv_pci_ioda_fixup_iov_resources(struct pci_dev *pdev) 30506e628c7dSWei Yang { 3051f2dd0afeSWei Yang struct pci_controller *hose = pci_bus_to_host(pdev->bus); 3052f2dd0afeSWei Yang struct pnv_phb *phb = hose->private_data; 3053f2dd0afeSWei Yang const resource_size_t gate = phb->ioda.m64_segsize >> 2; 30546e628c7dSWei Yang struct resource *res; 30556e628c7dSWei Yang int i; 3056dfcc8d45SWei Yang resource_size_t size, total_vf_bar_sz; 30576e628c7dSWei Yang struct pci_dn *pdn; 30585b88ec22SWei Yang int mul, total_vfs; 30596e628c7dSWei Yang 30606e628c7dSWei Yang if (!pdev->is_physfn || pdev->is_added) 30616e628c7dSWei Yang return; 30626e628c7dSWei Yang 30636e628c7dSWei Yang pdn = pci_get_pdn(pdev); 30646e628c7dSWei Yang pdn->vfs_expanded = 0; 3065ee8222feSWei Yang pdn->m64_single_mode = false; 30666e628c7dSWei Yang 30675b88ec22SWei Yang total_vfs = pci_sriov_get_totalvfs(pdev); 306892b8f137SGavin Shan mul = phb->ioda.total_pe_num; 3069dfcc8d45SWei Yang total_vf_bar_sz = 0; 30705b88ec22SWei Yang 30715b88ec22SWei Yang for (i = 0; i < PCI_SRIOV_NUM_BARS; i++) { 30725b88ec22SWei Yang res = &pdev->resource[i + PCI_IOV_RESOURCES]; 30735b88ec22SWei Yang if (!res->flags || res->parent) 30745b88ec22SWei Yang continue; 3075b79331a5SRussell Currey if (!pnv_pci_is_m64_flags(res->flags)) { 3076b0331854SWei Yang dev_warn(&pdev->dev, "Don't support SR-IOV with" 3077b0331854SWei Yang " non M64 VF BAR%d: %pR. \n", 30785b88ec22SWei Yang i, res); 3079b0331854SWei Yang goto truncate_iov; 30805b88ec22SWei Yang } 30815b88ec22SWei Yang 3082dfcc8d45SWei Yang total_vf_bar_sz += pci_iov_resource_size(pdev, 3083dfcc8d45SWei Yang i + PCI_IOV_RESOURCES); 30845b88ec22SWei Yang 3085f2dd0afeSWei Yang /* 3086f2dd0afeSWei Yang * If bigger than quarter of M64 segment size, just round up 3087f2dd0afeSWei Yang * power of two. 3088f2dd0afeSWei Yang * 3089f2dd0afeSWei Yang * Generally, one M64 BAR maps one IOV BAR. To avoid conflict 3090f2dd0afeSWei Yang * with other devices, IOV BAR size is expanded to be 3091f2dd0afeSWei Yang * (total_pe * VF_BAR_size). When VF_BAR_size is half of M64 3092f2dd0afeSWei Yang * segment size , the expanded size would equal to half of the 3093f2dd0afeSWei Yang * whole M64 space size, which will exhaust the M64 Space and 3094f2dd0afeSWei Yang * limit the system flexibility. This is a design decision to 3095f2dd0afeSWei Yang * set the boundary to quarter of the M64 segment size. 3096f2dd0afeSWei Yang */ 3097dfcc8d45SWei Yang if (total_vf_bar_sz > gate) { 30985b88ec22SWei Yang mul = roundup_pow_of_two(total_vfs); 3099dfcc8d45SWei Yang dev_info(&pdev->dev, 3100dfcc8d45SWei Yang "VF BAR Total IOV size %llx > %llx, roundup to %d VFs\n", 3101dfcc8d45SWei Yang total_vf_bar_sz, gate, mul); 3102ee8222feSWei Yang pdn->m64_single_mode = true; 31035b88ec22SWei Yang break; 31045b88ec22SWei Yang } 31055b88ec22SWei Yang } 31065b88ec22SWei Yang 31076e628c7dSWei Yang for (i = 0; i < PCI_SRIOV_NUM_BARS; i++) { 31086e628c7dSWei Yang res = &pdev->resource[i + PCI_IOV_RESOURCES]; 31096e628c7dSWei Yang if (!res->flags || res->parent) 31106e628c7dSWei Yang continue; 31116e628c7dSWei Yang 31126e628c7dSWei Yang size = pci_iov_resource_size(pdev, i + PCI_IOV_RESOURCES); 3113ee8222feSWei Yang /* 3114ee8222feSWei Yang * On PHB3, the minimum size alignment of M64 BAR in single 3115ee8222feSWei Yang * mode is 32MB. 3116ee8222feSWei Yang */ 3117ee8222feSWei Yang if (pdn->m64_single_mode && (size < SZ_32M)) 3118ee8222feSWei Yang goto truncate_iov; 3119ee8222feSWei Yang dev_dbg(&pdev->dev, " Fixing VF BAR%d: %pR to\n", i, res); 31205b88ec22SWei Yang res->end = res->start + size * mul - 1; 31216e628c7dSWei Yang dev_dbg(&pdev->dev, " %pR\n", res); 31226e628c7dSWei Yang dev_info(&pdev->dev, "VF BAR%d: %pR (expanded to %d VFs for PE alignment)", 31235b88ec22SWei Yang i, res, mul); 31246e628c7dSWei Yang } 31255b88ec22SWei Yang pdn->vfs_expanded = mul; 3126b0331854SWei Yang 3127b0331854SWei Yang return; 3128b0331854SWei Yang 3129b0331854SWei Yang truncate_iov: 3130b0331854SWei Yang /* To save MMIO space, IOV BAR is truncated. */ 3131b0331854SWei Yang for (i = 0; i < PCI_SRIOV_NUM_BARS; i++) { 3132b0331854SWei Yang res = &pdev->resource[i + PCI_IOV_RESOURCES]; 3133b0331854SWei Yang res->flags = 0; 3134b0331854SWei Yang res->end = res->start - 1; 3135b0331854SWei Yang } 31366e628c7dSWei Yang } 31376e628c7dSWei Yang #endif /* CONFIG_PCI_IOV */ 31386e628c7dSWei Yang 313923e79425SGavin Shan static void pnv_ioda_setup_pe_res(struct pnv_ioda_pe *pe, 314023e79425SGavin Shan struct resource *res) 314111685becSGavin Shan { 314223e79425SGavin Shan struct pnv_phb *phb = pe->phb; 314311685becSGavin Shan struct pci_bus_region region; 314423e79425SGavin Shan int index; 314523e79425SGavin Shan int64_t rc; 314611685becSGavin Shan 314723e79425SGavin Shan if (!res || !res->flags || res->start > res->end) 314823e79425SGavin Shan return; 314911685becSGavin Shan 315011685becSGavin Shan if (res->flags & IORESOURCE_IO) { 315111685becSGavin Shan region.start = res->start - phb->ioda.io_pci_base; 315211685becSGavin Shan region.end = res->end - phb->ioda.io_pci_base; 315311685becSGavin Shan index = region.start / phb->ioda.io_segsize; 315411685becSGavin Shan 315592b8f137SGavin Shan while (index < phb->ioda.total_pe_num && 315611685becSGavin Shan region.start <= region.end) { 315711685becSGavin Shan phb->ioda.io_segmap[index] = pe->pe_number; 315811685becSGavin Shan rc = opal_pci_map_pe_mmio_window(phb->opal_id, 315911685becSGavin Shan pe->pe_number, OPAL_IO_WINDOW_TYPE, 0, index); 316011685becSGavin Shan if (rc != OPAL_SUCCESS) { 31611f52f176SRussell Currey pr_err("%s: Error %lld mapping IO segment#%d to PE#%x\n", 316211685becSGavin Shan __func__, rc, index, pe->pe_number); 316311685becSGavin Shan break; 316411685becSGavin Shan } 316511685becSGavin Shan 316611685becSGavin Shan region.start += phb->ioda.io_segsize; 316711685becSGavin Shan index++; 316811685becSGavin Shan } 3169027fa02fSGavin Shan } else if ((res->flags & IORESOURCE_MEM) && 31705958d19aSBenjamin Herrenschmidt !pnv_pci_is_m64(phb, res)) { 317111685becSGavin Shan region.start = res->start - 317223e79425SGavin Shan phb->hose->mem_offset[0] - 317311685becSGavin Shan phb->ioda.m32_pci_base; 317411685becSGavin Shan region.end = res->end - 317523e79425SGavin Shan phb->hose->mem_offset[0] - 317611685becSGavin Shan phb->ioda.m32_pci_base; 317711685becSGavin Shan index = region.start / phb->ioda.m32_segsize; 317811685becSGavin Shan 317992b8f137SGavin Shan while (index < phb->ioda.total_pe_num && 318011685becSGavin Shan region.start <= region.end) { 318111685becSGavin Shan phb->ioda.m32_segmap[index] = pe->pe_number; 318211685becSGavin Shan rc = opal_pci_map_pe_mmio_window(phb->opal_id, 318311685becSGavin Shan pe->pe_number, OPAL_M32_WINDOW_TYPE, 0, index); 318411685becSGavin Shan if (rc != OPAL_SUCCESS) { 31851f52f176SRussell Currey pr_err("%s: Error %lld mapping M32 segment#%d to PE#%x", 318611685becSGavin Shan __func__, rc, index, pe->pe_number); 318711685becSGavin Shan break; 318811685becSGavin Shan } 318911685becSGavin Shan 319011685becSGavin Shan region.start += phb->ioda.m32_segsize; 319111685becSGavin Shan index++; 319211685becSGavin Shan } 319311685becSGavin Shan } 319411685becSGavin Shan } 319523e79425SGavin Shan 319623e79425SGavin Shan /* 319723e79425SGavin Shan * This function is supposed to be called on basis of PE from top 319823e79425SGavin Shan * to bottom style. So the the I/O or MMIO segment assigned to 319903671057SMasahiro Yamada * parent PE could be overridden by its child PEs if necessary. 320023e79425SGavin Shan */ 320123e79425SGavin Shan static void pnv_ioda_setup_pe_seg(struct pnv_ioda_pe *pe) 320223e79425SGavin Shan { 320369d733e7SGavin Shan struct pci_dev *pdev; 320423e79425SGavin Shan int i; 320523e79425SGavin Shan 320623e79425SGavin Shan /* 320723e79425SGavin Shan * NOTE: We only care PCI bus based PE for now. For PCI 320823e79425SGavin Shan * device based PE, for example SRIOV sensitive VF should 320923e79425SGavin Shan * be figured out later. 321023e79425SGavin Shan */ 321123e79425SGavin Shan BUG_ON(!(pe->flags & (PNV_IODA_PE_BUS | PNV_IODA_PE_BUS_ALL))); 321223e79425SGavin Shan 321369d733e7SGavin Shan list_for_each_entry(pdev, &pe->pbus->devices, bus_list) { 321469d733e7SGavin Shan for (i = 0; i <= PCI_ROM_RESOURCE; i++) 321569d733e7SGavin Shan pnv_ioda_setup_pe_res(pe, &pdev->resource[i]); 321669d733e7SGavin Shan 321769d733e7SGavin Shan /* 321869d733e7SGavin Shan * If the PE contains all subordinate PCI buses, the 321969d733e7SGavin Shan * windows of the child bridges should be mapped to 322069d733e7SGavin Shan * the PE as well. 322169d733e7SGavin Shan */ 322269d733e7SGavin Shan if (!(pe->flags & PNV_IODA_PE_BUS_ALL) || !pci_is_bridge(pdev)) 322369d733e7SGavin Shan continue; 322469d733e7SGavin Shan for (i = 0; i < PCI_BRIDGE_RESOURCE_NUM; i++) 322569d733e7SGavin Shan pnv_ioda_setup_pe_res(pe, 322669d733e7SGavin Shan &pdev->resource[PCI_BRIDGE_RESOURCES + i]); 322769d733e7SGavin Shan } 322811685becSGavin Shan } 322911685becSGavin Shan 323098b665daSRussell Currey #ifdef CONFIG_DEBUG_FS 323198b665daSRussell Currey static int pnv_pci_diag_data_set(void *data, u64 val) 323298b665daSRussell Currey { 323398b665daSRussell Currey struct pci_controller *hose; 323498b665daSRussell Currey struct pnv_phb *phb; 323598b665daSRussell Currey s64 ret; 323698b665daSRussell Currey 323798b665daSRussell Currey if (val != 1ULL) 323898b665daSRussell Currey return -EINVAL; 323998b665daSRussell Currey 324098b665daSRussell Currey hose = (struct pci_controller *)data; 324198b665daSRussell Currey if (!hose || !hose->private_data) 324298b665daSRussell Currey return -ENODEV; 324398b665daSRussell Currey 324498b665daSRussell Currey phb = hose->private_data; 324598b665daSRussell Currey 324698b665daSRussell Currey /* Retrieve the diag data from firmware */ 32475cb1f8fdSRussell Currey ret = opal_pci_get_phb_diag_data2(phb->opal_id, phb->diag_data, 32485cb1f8fdSRussell Currey phb->diag_data_size); 324998b665daSRussell Currey if (ret != OPAL_SUCCESS) 325098b665daSRussell Currey return -EIO; 325198b665daSRussell Currey 325298b665daSRussell Currey /* Print the diag data to the kernel log */ 32535cb1f8fdSRussell Currey pnv_pci_dump_phb_diag_data(phb->hose, phb->diag_data); 325498b665daSRussell Currey return 0; 325598b665daSRussell Currey } 325698b665daSRussell Currey 325798b665daSRussell Currey DEFINE_SIMPLE_ATTRIBUTE(pnv_pci_diag_data_fops, NULL, 325898b665daSRussell Currey pnv_pci_diag_data_set, "%llu\n"); 325998b665daSRussell Currey 326098b665daSRussell Currey #endif /* CONFIG_DEBUG_FS */ 326198b665daSRussell Currey 326237c367f2SGavin Shan static void pnv_pci_ioda_create_dbgfs(void) 326337c367f2SGavin Shan { 326437c367f2SGavin Shan #ifdef CONFIG_DEBUG_FS 326537c367f2SGavin Shan struct pci_controller *hose, *tmp; 326637c367f2SGavin Shan struct pnv_phb *phb; 326737c367f2SGavin Shan char name[16]; 326837c367f2SGavin Shan 326937c367f2SGavin Shan list_for_each_entry_safe(hose, tmp, &hose_list, list_node) { 327037c367f2SGavin Shan phb = hose->private_data; 327137c367f2SGavin Shan 3272ccd1c191SGavin Shan /* Notify initialization of PHB done */ 3273ccd1c191SGavin Shan phb->initialized = 1; 3274ccd1c191SGavin Shan 327537c367f2SGavin Shan sprintf(name, "PCI%04x", hose->global_number); 327637c367f2SGavin Shan phb->dbgfs = debugfs_create_dir(name, powerpc_debugfs_root); 327798b665daSRussell Currey if (!phb->dbgfs) { 327837c367f2SGavin Shan pr_warning("%s: Error on creating debugfs on PHB#%x\n", 327937c367f2SGavin Shan __func__, hose->global_number); 328098b665daSRussell Currey continue; 328198b665daSRussell Currey } 328298b665daSRussell Currey 328398b665daSRussell Currey debugfs_create_file("dump_diag_regs", 0200, phb->dbgfs, hose, 328498b665daSRussell Currey &pnv_pci_diag_data_fops); 328537c367f2SGavin Shan } 328637c367f2SGavin Shan #endif /* CONFIG_DEBUG_FS */ 328737c367f2SGavin Shan } 328837c367f2SGavin Shan 3289cad5cef6SGreg Kroah-Hartman static void pnv_pci_ioda_fixup(void) 3290fb446ad0SGavin Shan { 3291fb446ad0SGavin Shan pnv_pci_ioda_setup_PEs(); 3292ccd1c191SGavin Shan pnv_pci_ioda_setup_iommu_api(); 329337c367f2SGavin Shan pnv_pci_ioda_create_dbgfs(); 329437c367f2SGavin Shan 3295e9cc17d4SGavin Shan #ifdef CONFIG_EEH 3296e9cc17d4SGavin Shan eeh_init(); 3297dadcd6d6SMike Qiu eeh_addr_cache_build(); 3298e9cc17d4SGavin Shan #endif 3299fb446ad0SGavin Shan } 3300fb446ad0SGavin Shan 3301271fd03aSGavin Shan /* 3302271fd03aSGavin Shan * Returns the alignment for I/O or memory windows for P2P 3303271fd03aSGavin Shan * bridges. That actually depends on how PEs are segmented. 3304271fd03aSGavin Shan * For now, we return I/O or M32 segment size for PE sensitive 3305271fd03aSGavin Shan * P2P bridges. Otherwise, the default values (4KiB for I/O, 3306271fd03aSGavin Shan * 1MiB for memory) will be returned. 3307271fd03aSGavin Shan * 3308271fd03aSGavin Shan * The current PCI bus might be put into one PE, which was 3309271fd03aSGavin Shan * create against the parent PCI bridge. For that case, we 3310271fd03aSGavin Shan * needn't enlarge the alignment so that we can save some 3311271fd03aSGavin Shan * resources. 3312271fd03aSGavin Shan */ 3313271fd03aSGavin Shan static resource_size_t pnv_pci_window_alignment(struct pci_bus *bus, 3314271fd03aSGavin Shan unsigned long type) 3315271fd03aSGavin Shan { 3316271fd03aSGavin Shan struct pci_dev *bridge; 3317271fd03aSGavin Shan struct pci_controller *hose = pci_bus_to_host(bus); 3318271fd03aSGavin Shan struct pnv_phb *phb = hose->private_data; 3319271fd03aSGavin Shan int num_pci_bridges = 0; 3320271fd03aSGavin Shan 3321271fd03aSGavin Shan bridge = bus->self; 3322271fd03aSGavin Shan while (bridge) { 3323271fd03aSGavin Shan if (pci_pcie_type(bridge) == PCI_EXP_TYPE_PCI_BRIDGE) { 3324271fd03aSGavin Shan num_pci_bridges++; 3325271fd03aSGavin Shan if (num_pci_bridges >= 2) 3326271fd03aSGavin Shan return 1; 3327271fd03aSGavin Shan } 3328271fd03aSGavin Shan 3329271fd03aSGavin Shan bridge = bridge->bus->self; 3330271fd03aSGavin Shan } 3331271fd03aSGavin Shan 33325958d19aSBenjamin Herrenschmidt /* 33335958d19aSBenjamin Herrenschmidt * We fall back to M32 if M64 isn't supported. We enforce the M64 33345958d19aSBenjamin Herrenschmidt * alignment for any 64-bit resource, PCIe doesn't care and 33355958d19aSBenjamin Herrenschmidt * bridges only do 64-bit prefetchable anyway. 33365958d19aSBenjamin Herrenschmidt */ 3337b79331a5SRussell Currey if (phb->ioda.m64_segsize && pnv_pci_is_m64_flags(type)) 3338262af557SGuo Chao return phb->ioda.m64_segsize; 3339271fd03aSGavin Shan if (type & IORESOURCE_MEM) 3340271fd03aSGavin Shan return phb->ioda.m32_segsize; 3341271fd03aSGavin Shan 3342271fd03aSGavin Shan return phb->ioda.io_segsize; 3343271fd03aSGavin Shan } 3344271fd03aSGavin Shan 334540e2a47eSGavin Shan /* 334640e2a47eSGavin Shan * We are updating root port or the upstream port of the 334740e2a47eSGavin Shan * bridge behind the root port with PHB's windows in order 334840e2a47eSGavin Shan * to accommodate the changes on required resources during 334940e2a47eSGavin Shan * PCI (slot) hotplug, which is connected to either root 335040e2a47eSGavin Shan * port or the downstream ports of PCIe switch behind the 335140e2a47eSGavin Shan * root port. 335240e2a47eSGavin Shan */ 335340e2a47eSGavin Shan static void pnv_pci_fixup_bridge_resources(struct pci_bus *bus, 335440e2a47eSGavin Shan unsigned long type) 335540e2a47eSGavin Shan { 335640e2a47eSGavin Shan struct pci_controller *hose = pci_bus_to_host(bus); 335740e2a47eSGavin Shan struct pnv_phb *phb = hose->private_data; 335840e2a47eSGavin Shan struct pci_dev *bridge = bus->self; 335940e2a47eSGavin Shan struct resource *r, *w; 336040e2a47eSGavin Shan bool msi_region = false; 336140e2a47eSGavin Shan int i; 336240e2a47eSGavin Shan 336340e2a47eSGavin Shan /* Check if we need apply fixup to the bridge's windows */ 336440e2a47eSGavin Shan if (!pci_is_root_bus(bridge->bus) && 336540e2a47eSGavin Shan !pci_is_root_bus(bridge->bus->self->bus)) 336640e2a47eSGavin Shan return; 336740e2a47eSGavin Shan 336840e2a47eSGavin Shan /* Fixup the resources */ 336940e2a47eSGavin Shan for (i = 0; i < PCI_BRIDGE_RESOURCE_NUM; i++) { 337040e2a47eSGavin Shan r = &bridge->resource[PCI_BRIDGE_RESOURCES + i]; 337140e2a47eSGavin Shan if (!r->flags || !r->parent) 337240e2a47eSGavin Shan continue; 337340e2a47eSGavin Shan 337440e2a47eSGavin Shan w = NULL; 337540e2a47eSGavin Shan if (r->flags & type & IORESOURCE_IO) 337640e2a47eSGavin Shan w = &hose->io_resource; 33775958d19aSBenjamin Herrenschmidt else if (pnv_pci_is_m64(phb, r) && 337840e2a47eSGavin Shan (type & IORESOURCE_PREFETCH) && 337940e2a47eSGavin Shan phb->ioda.m64_segsize) 338040e2a47eSGavin Shan w = &hose->mem_resources[1]; 338140e2a47eSGavin Shan else if (r->flags & type & IORESOURCE_MEM) { 338240e2a47eSGavin Shan w = &hose->mem_resources[0]; 338340e2a47eSGavin Shan msi_region = true; 338440e2a47eSGavin Shan } 338540e2a47eSGavin Shan 338640e2a47eSGavin Shan r->start = w->start; 338740e2a47eSGavin Shan r->end = w->end; 338840e2a47eSGavin Shan 338940e2a47eSGavin Shan /* The 64KB 32-bits MSI region shouldn't be included in 339040e2a47eSGavin Shan * the 32-bits bridge window. Otherwise, we can see strange 339140e2a47eSGavin Shan * issues. One of them is EEH error observed on Garrison. 339240e2a47eSGavin Shan * 339340e2a47eSGavin Shan * Exclude top 1MB region which is the minimal alignment of 339440e2a47eSGavin Shan * 32-bits bridge window. 339540e2a47eSGavin Shan */ 339640e2a47eSGavin Shan if (msi_region) { 339740e2a47eSGavin Shan r->end += 0x10000; 339840e2a47eSGavin Shan r->end -= 0x100000; 339940e2a47eSGavin Shan } 340040e2a47eSGavin Shan } 340140e2a47eSGavin Shan } 340240e2a47eSGavin Shan 3403ccd1c191SGavin Shan static void pnv_pci_setup_bridge(struct pci_bus *bus, unsigned long type) 3404ccd1c191SGavin Shan { 3405ccd1c191SGavin Shan struct pci_controller *hose = pci_bus_to_host(bus); 3406ccd1c191SGavin Shan struct pnv_phb *phb = hose->private_data; 3407ccd1c191SGavin Shan struct pci_dev *bridge = bus->self; 3408ccd1c191SGavin Shan struct pnv_ioda_pe *pe; 3409ccd1c191SGavin Shan bool all = (pci_pcie_type(bridge) == PCI_EXP_TYPE_PCI_BRIDGE); 3410ccd1c191SGavin Shan 341140e2a47eSGavin Shan /* Extend bridge's windows if necessary */ 341240e2a47eSGavin Shan pnv_pci_fixup_bridge_resources(bus, type); 341340e2a47eSGavin Shan 341463803c39SGavin Shan /* The PE for root bus should be realized before any one else */ 341563803c39SGavin Shan if (!phb->ioda.root_pe_populated) { 341663803c39SGavin Shan pe = pnv_ioda_setup_bus_PE(phb->hose->bus, false); 341763803c39SGavin Shan if (pe) { 341863803c39SGavin Shan phb->ioda.root_pe_idx = pe->pe_number; 341963803c39SGavin Shan phb->ioda.root_pe_populated = true; 342063803c39SGavin Shan } 342163803c39SGavin Shan } 342263803c39SGavin Shan 3423ccd1c191SGavin Shan /* Don't assign PE to PCI bus, which doesn't have subordinate devices */ 3424ccd1c191SGavin Shan if (list_empty(&bus->devices)) 3425ccd1c191SGavin Shan return; 3426ccd1c191SGavin Shan 3427ccd1c191SGavin Shan /* Reserve PEs according to used M64 resources */ 3428ccd1c191SGavin Shan if (phb->reserve_m64_pe) 3429ccd1c191SGavin Shan phb->reserve_m64_pe(bus, NULL, all); 3430ccd1c191SGavin Shan 3431ccd1c191SGavin Shan /* 3432ccd1c191SGavin Shan * Assign PE. We might run here because of partial hotplug. 3433ccd1c191SGavin Shan * For the case, we just pick up the existing PE and should 3434ccd1c191SGavin Shan * not allocate resources again. 3435ccd1c191SGavin Shan */ 3436ccd1c191SGavin Shan pe = pnv_ioda_setup_bus_PE(bus, all); 3437ccd1c191SGavin Shan if (!pe) 3438ccd1c191SGavin Shan return; 3439ccd1c191SGavin Shan 3440ccd1c191SGavin Shan pnv_ioda_setup_pe_seg(pe); 3441ccd1c191SGavin Shan switch (phb->type) { 3442ccd1c191SGavin Shan case PNV_PHB_IODA1: 3443ccd1c191SGavin Shan pnv_pci_ioda1_setup_dma_pe(phb, pe); 3444ccd1c191SGavin Shan break; 3445ccd1c191SGavin Shan case PNV_PHB_IODA2: 3446ccd1c191SGavin Shan pnv_pci_ioda2_setup_dma_pe(phb, pe); 3447ccd1c191SGavin Shan break; 3448ccd1c191SGavin Shan default: 34491f52f176SRussell Currey pr_warn("%s: No DMA for PHB#%x (type %d)\n", 3450ccd1c191SGavin Shan __func__, phb->hose->global_number, phb->type); 3451ccd1c191SGavin Shan } 3452ccd1c191SGavin Shan } 3453ccd1c191SGavin Shan 345438274637SYongji Xie static resource_size_t pnv_pci_default_alignment(void) 345538274637SYongji Xie { 345638274637SYongji Xie return PAGE_SIZE; 345738274637SYongji Xie } 345838274637SYongji Xie 34595350ab3fSWei Yang #ifdef CONFIG_PCI_IOV 34605350ab3fSWei Yang static resource_size_t pnv_pci_iov_resource_alignment(struct pci_dev *pdev, 34615350ab3fSWei Yang int resno) 34625350ab3fSWei Yang { 3463ee8222feSWei Yang struct pci_controller *hose = pci_bus_to_host(pdev->bus); 3464ee8222feSWei Yang struct pnv_phb *phb = hose->private_data; 34655350ab3fSWei Yang struct pci_dn *pdn = pci_get_pdn(pdev); 34667fbe7a93SWei Yang resource_size_t align; 34675350ab3fSWei Yang 34687fbe7a93SWei Yang /* 34697fbe7a93SWei Yang * On PowerNV platform, IOV BAR is mapped by M64 BAR to enable the 34707fbe7a93SWei Yang * SR-IOV. While from hardware perspective, the range mapped by M64 34717fbe7a93SWei Yang * BAR should be size aligned. 34727fbe7a93SWei Yang * 3473ee8222feSWei Yang * When IOV BAR is mapped with M64 BAR in Single PE mode, the extra 3474ee8222feSWei Yang * powernv-specific hardware restriction is gone. But if just use the 3475ee8222feSWei Yang * VF BAR size as the alignment, PF BAR / VF BAR may be allocated with 3476ee8222feSWei Yang * in one segment of M64 #15, which introduces the PE conflict between 3477ee8222feSWei Yang * PF and VF. Based on this, the minimum alignment of an IOV BAR is 3478ee8222feSWei Yang * m64_segsize. 3479ee8222feSWei Yang * 34807fbe7a93SWei Yang * This function returns the total IOV BAR size if M64 BAR is in 34817fbe7a93SWei Yang * Shared PE mode or just VF BAR size if not. 3482ee8222feSWei Yang * If the M64 BAR is in Single PE mode, return the VF BAR size or 3483ee8222feSWei Yang * M64 segment size if IOV BAR size is less. 34847fbe7a93SWei Yang */ 34855350ab3fSWei Yang align = pci_iov_resource_size(pdev, resno); 34867fbe7a93SWei Yang if (!pdn->vfs_expanded) 34875350ab3fSWei Yang return align; 3488ee8222feSWei Yang if (pdn->m64_single_mode) 3489ee8222feSWei Yang return max(align, (resource_size_t)phb->ioda.m64_segsize); 34907fbe7a93SWei Yang 34917fbe7a93SWei Yang return pdn->vfs_expanded * align; 34925350ab3fSWei Yang } 34935350ab3fSWei Yang #endif /* CONFIG_PCI_IOV */ 34945350ab3fSWei Yang 3495184cd4a3SBenjamin Herrenschmidt /* Prevent enabling devices for which we couldn't properly 3496184cd4a3SBenjamin Herrenschmidt * assign a PE 3497184cd4a3SBenjamin Herrenschmidt */ 34984361b034SIan Munsie bool pnv_pci_enable_device_hook(struct pci_dev *dev) 3499184cd4a3SBenjamin Herrenschmidt { 3500db1266c8SGavin Shan struct pci_controller *hose = pci_bus_to_host(dev->bus); 3501db1266c8SGavin Shan struct pnv_phb *phb = hose->private_data; 3502db1266c8SGavin Shan struct pci_dn *pdn; 3503184cd4a3SBenjamin Herrenschmidt 3504db1266c8SGavin Shan /* The function is probably called while the PEs have 3505db1266c8SGavin Shan * not be created yet. For example, resource reassignment 3506db1266c8SGavin Shan * during PCI probe period. We just skip the check if 3507db1266c8SGavin Shan * PEs isn't ready. 3508db1266c8SGavin Shan */ 3509db1266c8SGavin Shan if (!phb->initialized) 3510c88c2a18SDaniel Axtens return true; 3511db1266c8SGavin Shan 3512b72c1f65SBenjamin Herrenschmidt pdn = pci_get_pdn(dev); 3513184cd4a3SBenjamin Herrenschmidt if (!pdn || pdn->pe_number == IODA_INVALID_PE) 3514c88c2a18SDaniel Axtens return false; 3515db1266c8SGavin Shan 3516c88c2a18SDaniel Axtens return true; 3517184cd4a3SBenjamin Herrenschmidt } 3518184cd4a3SBenjamin Herrenschmidt 3519c5f7700bSGavin Shan static long pnv_pci_ioda1_unset_window(struct iommu_table_group *table_group, 3520c5f7700bSGavin Shan int num) 3521c5f7700bSGavin Shan { 3522c5f7700bSGavin Shan struct pnv_ioda_pe *pe = container_of(table_group, 3523c5f7700bSGavin Shan struct pnv_ioda_pe, table_group); 3524c5f7700bSGavin Shan struct pnv_phb *phb = pe->phb; 3525c5f7700bSGavin Shan unsigned int idx; 3526c5f7700bSGavin Shan long rc; 3527c5f7700bSGavin Shan 3528c5f7700bSGavin Shan pe_info(pe, "Removing DMA window #%d\n", num); 3529c5f7700bSGavin Shan for (idx = 0; idx < phb->ioda.dma32_count; idx++) { 3530c5f7700bSGavin Shan if (phb->ioda.dma32_segmap[idx] != pe->pe_number) 3531c5f7700bSGavin Shan continue; 3532c5f7700bSGavin Shan 3533c5f7700bSGavin Shan rc = opal_pci_map_pe_dma_window(phb->opal_id, pe->pe_number, 3534c5f7700bSGavin Shan idx, 0, 0ul, 0ul, 0ul); 3535c5f7700bSGavin Shan if (rc != OPAL_SUCCESS) { 3536c5f7700bSGavin Shan pe_warn(pe, "Failure %ld unmapping DMA32 segment#%d\n", 3537c5f7700bSGavin Shan rc, idx); 3538c5f7700bSGavin Shan return rc; 3539c5f7700bSGavin Shan } 3540c5f7700bSGavin Shan 3541c5f7700bSGavin Shan phb->ioda.dma32_segmap[idx] = IODA_INVALID_PE; 3542c5f7700bSGavin Shan } 3543c5f7700bSGavin Shan 3544c5f7700bSGavin Shan pnv_pci_unlink_table_and_group(table_group->tables[num], table_group); 3545c5f7700bSGavin Shan return OPAL_SUCCESS; 3546c5f7700bSGavin Shan } 3547c5f7700bSGavin Shan 3548c5f7700bSGavin Shan static void pnv_pci_ioda1_release_pe_dma(struct pnv_ioda_pe *pe) 3549c5f7700bSGavin Shan { 3550c5f7700bSGavin Shan unsigned int weight = pnv_pci_ioda_pe_dma_weight(pe); 3551c5f7700bSGavin Shan struct iommu_table *tbl = pe->table_group.tables[0]; 3552c5f7700bSGavin Shan int64_t rc; 3553c5f7700bSGavin Shan 3554c5f7700bSGavin Shan if (!weight) 3555c5f7700bSGavin Shan return; 3556c5f7700bSGavin Shan 3557c5f7700bSGavin Shan rc = pnv_pci_ioda1_unset_window(&pe->table_group, 0); 3558c5f7700bSGavin Shan if (rc != OPAL_SUCCESS) 3559c5f7700bSGavin Shan return; 3560c5f7700bSGavin Shan 3561a34ab7c3SBenjamin Herrenschmidt pnv_pci_p7ioc_tce_invalidate(tbl, tbl->it_offset, tbl->it_size, false); 3562c5f7700bSGavin Shan if (pe->table_group.group) { 3563c5f7700bSGavin Shan iommu_group_put(pe->table_group.group); 3564c5f7700bSGavin Shan WARN_ON(pe->table_group.group); 3565c5f7700bSGavin Shan } 3566c5f7700bSGavin Shan 3567c5f7700bSGavin Shan free_pages(tbl->it_base, get_order(tbl->it_size << 3)); 3568e5afdf9dSAlexey Kardashevskiy iommu_tce_table_put(tbl); 3569c5f7700bSGavin Shan } 3570c5f7700bSGavin Shan 3571c5f7700bSGavin Shan static void pnv_pci_ioda2_release_pe_dma(struct pnv_ioda_pe *pe) 3572c5f7700bSGavin Shan { 3573c5f7700bSGavin Shan struct iommu_table *tbl = pe->table_group.tables[0]; 3574c5f7700bSGavin Shan unsigned int weight = pnv_pci_ioda_pe_dma_weight(pe); 3575c5f7700bSGavin Shan #ifdef CONFIG_IOMMU_API 3576c5f7700bSGavin Shan int64_t rc; 3577c5f7700bSGavin Shan #endif 3578c5f7700bSGavin Shan 3579c5f7700bSGavin Shan if (!weight) 3580c5f7700bSGavin Shan return; 3581c5f7700bSGavin Shan 3582c5f7700bSGavin Shan #ifdef CONFIG_IOMMU_API 3583c5f7700bSGavin Shan rc = pnv_pci_ioda2_unset_window(&pe->table_group, 0); 3584c5f7700bSGavin Shan if (rc) 3585c5f7700bSGavin Shan pe_warn(pe, "OPAL error %ld release DMA window\n", rc); 3586c5f7700bSGavin Shan #endif 3587c5f7700bSGavin Shan 3588c5f7700bSGavin Shan pnv_pci_ioda2_set_bypass(pe, false); 3589c5f7700bSGavin Shan if (pe->table_group.group) { 3590c5f7700bSGavin Shan iommu_group_put(pe->table_group.group); 3591c5f7700bSGavin Shan WARN_ON(pe->table_group.group); 3592c5f7700bSGavin Shan } 3593c5f7700bSGavin Shan 3594c5f7700bSGavin Shan pnv_pci_ioda2_table_free_pages(tbl); 3595e5afdf9dSAlexey Kardashevskiy iommu_tce_table_put(tbl); 3596c5f7700bSGavin Shan } 3597c5f7700bSGavin Shan 3598c5f7700bSGavin Shan static void pnv_ioda_free_pe_seg(struct pnv_ioda_pe *pe, 3599c5f7700bSGavin Shan unsigned short win, 3600c5f7700bSGavin Shan unsigned int *map) 3601c5f7700bSGavin Shan { 3602c5f7700bSGavin Shan struct pnv_phb *phb = pe->phb; 3603c5f7700bSGavin Shan int idx; 3604c5f7700bSGavin Shan int64_t rc; 3605c5f7700bSGavin Shan 3606c5f7700bSGavin Shan for (idx = 0; idx < phb->ioda.total_pe_num; idx++) { 3607c5f7700bSGavin Shan if (map[idx] != pe->pe_number) 3608c5f7700bSGavin Shan continue; 3609c5f7700bSGavin Shan 3610c5f7700bSGavin Shan if (win == OPAL_M64_WINDOW_TYPE) 3611c5f7700bSGavin Shan rc = opal_pci_map_pe_mmio_window(phb->opal_id, 3612c5f7700bSGavin Shan phb->ioda.reserved_pe_idx, win, 3613c5f7700bSGavin Shan idx / PNV_IODA1_M64_SEGS, 3614c5f7700bSGavin Shan idx % PNV_IODA1_M64_SEGS); 3615c5f7700bSGavin Shan else 3616c5f7700bSGavin Shan rc = opal_pci_map_pe_mmio_window(phb->opal_id, 3617c5f7700bSGavin Shan phb->ioda.reserved_pe_idx, win, 0, idx); 3618c5f7700bSGavin Shan 3619c5f7700bSGavin Shan if (rc != OPAL_SUCCESS) 3620c5f7700bSGavin Shan pe_warn(pe, "Error %ld unmapping (%d) segment#%d\n", 3621c5f7700bSGavin Shan rc, win, idx); 3622c5f7700bSGavin Shan 3623c5f7700bSGavin Shan map[idx] = IODA_INVALID_PE; 3624c5f7700bSGavin Shan } 3625c5f7700bSGavin Shan } 3626c5f7700bSGavin Shan 3627c5f7700bSGavin Shan static void pnv_ioda_release_pe_seg(struct pnv_ioda_pe *pe) 3628c5f7700bSGavin Shan { 3629c5f7700bSGavin Shan struct pnv_phb *phb = pe->phb; 3630c5f7700bSGavin Shan 3631c5f7700bSGavin Shan if (phb->type == PNV_PHB_IODA1) { 3632c5f7700bSGavin Shan pnv_ioda_free_pe_seg(pe, OPAL_IO_WINDOW_TYPE, 3633c5f7700bSGavin Shan phb->ioda.io_segmap); 3634c5f7700bSGavin Shan pnv_ioda_free_pe_seg(pe, OPAL_M32_WINDOW_TYPE, 3635c5f7700bSGavin Shan phb->ioda.m32_segmap); 3636c5f7700bSGavin Shan pnv_ioda_free_pe_seg(pe, OPAL_M64_WINDOW_TYPE, 3637c5f7700bSGavin Shan phb->ioda.m64_segmap); 3638c5f7700bSGavin Shan } else if (phb->type == PNV_PHB_IODA2) { 3639c5f7700bSGavin Shan pnv_ioda_free_pe_seg(pe, OPAL_M32_WINDOW_TYPE, 3640c5f7700bSGavin Shan phb->ioda.m32_segmap); 3641c5f7700bSGavin Shan } 3642c5f7700bSGavin Shan } 3643c5f7700bSGavin Shan 3644c5f7700bSGavin Shan static void pnv_ioda_release_pe(struct pnv_ioda_pe *pe) 3645c5f7700bSGavin Shan { 3646c5f7700bSGavin Shan struct pnv_phb *phb = pe->phb; 3647c5f7700bSGavin Shan struct pnv_ioda_pe *slave, *tmp; 3648c5f7700bSGavin Shan 3649c5f7700bSGavin Shan list_del(&pe->list); 3650c5f7700bSGavin Shan switch (phb->type) { 3651c5f7700bSGavin Shan case PNV_PHB_IODA1: 3652c5f7700bSGavin Shan pnv_pci_ioda1_release_pe_dma(pe); 3653c5f7700bSGavin Shan break; 3654c5f7700bSGavin Shan case PNV_PHB_IODA2: 3655c5f7700bSGavin Shan pnv_pci_ioda2_release_pe_dma(pe); 3656c5f7700bSGavin Shan break; 3657c5f7700bSGavin Shan default: 3658c5f7700bSGavin Shan WARN_ON(1); 3659c5f7700bSGavin Shan } 3660c5f7700bSGavin Shan 3661c5f7700bSGavin Shan pnv_ioda_release_pe_seg(pe); 3662c5f7700bSGavin Shan pnv_ioda_deconfigure_pe(pe->phb, pe); 3663b314427aSGavin Shan 3664b314427aSGavin Shan /* Release slave PEs in the compound PE */ 3665b314427aSGavin Shan if (pe->flags & PNV_IODA_PE_MASTER) { 3666b314427aSGavin Shan list_for_each_entry_safe(slave, tmp, &pe->slaves, list) { 3667b314427aSGavin Shan list_del(&slave->list); 3668b314427aSGavin Shan pnv_ioda_free_pe(slave); 3669b314427aSGavin Shan } 3670b314427aSGavin Shan } 3671b314427aSGavin Shan 36726eaed166SGavin Shan /* 36736eaed166SGavin Shan * The PE for root bus can be removed because of hotplug in EEH 36746eaed166SGavin Shan * recovery for fenced PHB error. We need to mark the PE dead so 36756eaed166SGavin Shan * that it can be populated again in PCI hot add path. The PE 36766eaed166SGavin Shan * shouldn't be destroyed as it's the global reserved resource. 36776eaed166SGavin Shan */ 36786eaed166SGavin Shan if (phb->ioda.root_pe_populated && 36796eaed166SGavin Shan phb->ioda.root_pe_idx == pe->pe_number) 36806eaed166SGavin Shan phb->ioda.root_pe_populated = false; 36816eaed166SGavin Shan else 3682c5f7700bSGavin Shan pnv_ioda_free_pe(pe); 3683c5f7700bSGavin Shan } 3684c5f7700bSGavin Shan 3685c5f7700bSGavin Shan static void pnv_pci_release_device(struct pci_dev *pdev) 3686c5f7700bSGavin Shan { 3687c5f7700bSGavin Shan struct pci_controller *hose = pci_bus_to_host(pdev->bus); 3688c5f7700bSGavin Shan struct pnv_phb *phb = hose->private_data; 3689c5f7700bSGavin Shan struct pci_dn *pdn = pci_get_pdn(pdev); 3690c5f7700bSGavin Shan struct pnv_ioda_pe *pe; 3691c5f7700bSGavin Shan 3692c5f7700bSGavin Shan if (pdev->is_virtfn) 3693c5f7700bSGavin Shan return; 3694c5f7700bSGavin Shan 3695c5f7700bSGavin Shan if (!pdn || pdn->pe_number == IODA_INVALID_PE) 3696c5f7700bSGavin Shan return; 3697c5f7700bSGavin Shan 369829bf282dSGavin Shan /* 369929bf282dSGavin Shan * PCI hotplug can happen as part of EEH error recovery. The @pdn 370029bf282dSGavin Shan * isn't removed and added afterwards in this scenario. We should 370129bf282dSGavin Shan * set the PE number in @pdn to an invalid one. Otherwise, the PE's 370229bf282dSGavin Shan * device count is decreased on removing devices while failing to 370329bf282dSGavin Shan * be increased on adding devices. It leads to unbalanced PE's device 370429bf282dSGavin Shan * count and eventually make normal PCI hotplug path broken. 370529bf282dSGavin Shan */ 3706c5f7700bSGavin Shan pe = &phb->ioda.pe_array[pdn->pe_number]; 370729bf282dSGavin Shan pdn->pe_number = IODA_INVALID_PE; 370829bf282dSGavin Shan 3709c5f7700bSGavin Shan WARN_ON(--pe->device_count < 0); 3710c5f7700bSGavin Shan if (pe->device_count == 0) 3711c5f7700bSGavin Shan pnv_ioda_release_pe(pe); 3712c5f7700bSGavin Shan } 3713c5f7700bSGavin Shan 37147a8e6bbfSMichael Neuling static void pnv_pci_ioda_shutdown(struct pci_controller *hose) 371573ed148aSBenjamin Herrenschmidt { 37167a8e6bbfSMichael Neuling struct pnv_phb *phb = hose->private_data; 37177a8e6bbfSMichael Neuling 3718d1a85eeeSGavin Shan opal_pci_reset(phb->opal_id, OPAL_RESET_PCI_IODA_TABLE, 371973ed148aSBenjamin Herrenschmidt OPAL_ASSERT_RESET); 372073ed148aSBenjamin Herrenschmidt } 372173ed148aSBenjamin Herrenschmidt 372292ae0353SDaniel Axtens static const struct pci_controller_ops pnv_pci_ioda_controller_ops = { 372392ae0353SDaniel Axtens .dma_dev_setup = pnv_pci_dma_dev_setup, 37241bc74f1cSGavin Shan .dma_bus_setup = pnv_pci_dma_bus_setup, 372592ae0353SDaniel Axtens #ifdef CONFIG_PCI_MSI 372692ae0353SDaniel Axtens .setup_msi_irqs = pnv_setup_msi_irqs, 372792ae0353SDaniel Axtens .teardown_msi_irqs = pnv_teardown_msi_irqs, 372892ae0353SDaniel Axtens #endif 372992ae0353SDaniel Axtens .enable_device_hook = pnv_pci_enable_device_hook, 3730c5f7700bSGavin Shan .release_device = pnv_pci_release_device, 373192ae0353SDaniel Axtens .window_alignment = pnv_pci_window_alignment, 3732ccd1c191SGavin Shan .setup_bridge = pnv_pci_setup_bridge, 373392ae0353SDaniel Axtens .reset_secondary_bus = pnv_pci_reset_secondary_bus, 3734763d2d8dSDaniel Axtens .dma_set_mask = pnv_pci_ioda_dma_set_mask, 373553522982SAndrew Donnellan .dma_get_required_mask = pnv_pci_ioda_dma_get_required_mask, 37367a8e6bbfSMichael Neuling .shutdown = pnv_pci_ioda_shutdown, 373792ae0353SDaniel Axtens }; 373892ae0353SDaniel Axtens 3739f9f83456SAlexey Kardashevskiy static int pnv_npu_dma_set_mask(struct pci_dev *npdev, u64 dma_mask) 3740f9f83456SAlexey Kardashevskiy { 3741f9f83456SAlexey Kardashevskiy dev_err_once(&npdev->dev, 3742f9f83456SAlexey Kardashevskiy "%s operation unsupported for NVLink devices\n", 3743f9f83456SAlexey Kardashevskiy __func__); 3744f9f83456SAlexey Kardashevskiy return -EPERM; 3745f9f83456SAlexey Kardashevskiy } 3746f9f83456SAlexey Kardashevskiy 37475d2aa710SAlistair Popple static const struct pci_controller_ops pnv_npu_ioda_controller_ops = { 37485d2aa710SAlistair Popple .dma_dev_setup = pnv_pci_dma_dev_setup, 37495d2aa710SAlistair Popple #ifdef CONFIG_PCI_MSI 37505d2aa710SAlistair Popple .setup_msi_irqs = pnv_setup_msi_irqs, 37515d2aa710SAlistair Popple .teardown_msi_irqs = pnv_teardown_msi_irqs, 37525d2aa710SAlistair Popple #endif 37535d2aa710SAlistair Popple .enable_device_hook = pnv_pci_enable_device_hook, 37545d2aa710SAlistair Popple .window_alignment = pnv_pci_window_alignment, 37555d2aa710SAlistair Popple .reset_secondary_bus = pnv_pci_reset_secondary_bus, 37565d2aa710SAlistair Popple .dma_set_mask = pnv_npu_dma_set_mask, 37575d2aa710SAlistair Popple .shutdown = pnv_pci_ioda_shutdown, 37585d2aa710SAlistair Popple }; 37595d2aa710SAlistair Popple 37604361b034SIan Munsie #ifdef CONFIG_CXL_BASE 37614361b034SIan Munsie const struct pci_controller_ops pnv_cxl_cx4_ioda_controller_ops = { 37624361b034SIan Munsie .dma_dev_setup = pnv_pci_dma_dev_setup, 37634361b034SIan Munsie .dma_bus_setup = pnv_pci_dma_bus_setup, 3764a2f67d5eSIan Munsie #ifdef CONFIG_PCI_MSI 3765a2f67d5eSIan Munsie .setup_msi_irqs = pnv_cxl_cx4_setup_msi_irqs, 3766a2f67d5eSIan Munsie .teardown_msi_irqs = pnv_cxl_cx4_teardown_msi_irqs, 3767a2f67d5eSIan Munsie #endif 37684361b034SIan Munsie .enable_device_hook = pnv_cxl_enable_device_hook, 37694361b034SIan Munsie .disable_device = pnv_cxl_disable_device, 37704361b034SIan Munsie .release_device = pnv_pci_release_device, 37714361b034SIan Munsie .window_alignment = pnv_pci_window_alignment, 37724361b034SIan Munsie .setup_bridge = pnv_pci_setup_bridge, 37734361b034SIan Munsie .reset_secondary_bus = pnv_pci_reset_secondary_bus, 37744361b034SIan Munsie .dma_set_mask = pnv_pci_ioda_dma_set_mask, 37754361b034SIan Munsie .dma_get_required_mask = pnv_pci_ioda_dma_get_required_mask, 37764361b034SIan Munsie .shutdown = pnv_pci_ioda_shutdown, 37774361b034SIan Munsie }; 37784361b034SIan Munsie #endif 37794361b034SIan Munsie 3780e51df2c1SAnton Blanchard static void __init pnv_pci_init_ioda_phb(struct device_node *np, 3781e9cc17d4SGavin Shan u64 hub_id, int ioda_type) 3782184cd4a3SBenjamin Herrenschmidt { 3783184cd4a3SBenjamin Herrenschmidt struct pci_controller *hose; 3784184cd4a3SBenjamin Herrenschmidt struct pnv_phb *phb; 37852b923ed1SGavin Shan unsigned long size, m64map_off, m32map_off, pemap_off; 37862b923ed1SGavin Shan unsigned long iomap_off = 0, dma32map_off = 0; 3787fd141d1aSBenjamin Herrenschmidt struct resource r; 3788c681b93cSAlistair Popple const __be64 *prop64; 37893a1a4661SBenjamin Herrenschmidt const __be32 *prop32; 3790f1b7cc3eSGavin Shan int len; 37913fa23ff8SGavin Shan unsigned int segno; 3792184cd4a3SBenjamin Herrenschmidt u64 phb_id; 3793184cd4a3SBenjamin Herrenschmidt void *aux; 3794184cd4a3SBenjamin Herrenschmidt long rc; 3795184cd4a3SBenjamin Herrenschmidt 379608a45b32SBenjamin Herrenschmidt if (!of_device_is_available(np)) 379708a45b32SBenjamin Herrenschmidt return; 379808a45b32SBenjamin Herrenschmidt 3799b7c670d6SRob Herring pr_info("Initializing %s PHB (%pOF)\n", pnv_phb_names[ioda_type], np); 3800184cd4a3SBenjamin Herrenschmidt 3801184cd4a3SBenjamin Herrenschmidt prop64 = of_get_property(np, "ibm,opal-phbid", NULL); 3802184cd4a3SBenjamin Herrenschmidt if (!prop64) { 3803184cd4a3SBenjamin Herrenschmidt pr_err(" Missing \"ibm,opal-phbid\" property !\n"); 3804184cd4a3SBenjamin Herrenschmidt return; 3805184cd4a3SBenjamin Herrenschmidt } 3806184cd4a3SBenjamin Herrenschmidt phb_id = be64_to_cpup(prop64); 3807184cd4a3SBenjamin Herrenschmidt pr_debug(" PHB-ID : 0x%016llx\n", phb_id); 3808184cd4a3SBenjamin Herrenschmidt 3809e39f223fSMichael Ellerman phb = memblock_virt_alloc(sizeof(struct pnv_phb), 0); 381058d714ecSGavin Shan 381158d714ecSGavin Shan /* Allocate PCI controller */ 3812184cd4a3SBenjamin Herrenschmidt phb->hose = hose = pcibios_alloc_controller(np); 381358d714ecSGavin Shan if (!phb->hose) { 3814b7c670d6SRob Herring pr_err(" Can't allocate PCI controller for %pOF\n", 3815b7c670d6SRob Herring np); 3816e39f223fSMichael Ellerman memblock_free(__pa(phb), sizeof(struct pnv_phb)); 3817184cd4a3SBenjamin Herrenschmidt return; 3818184cd4a3SBenjamin Herrenschmidt } 3819184cd4a3SBenjamin Herrenschmidt 3820184cd4a3SBenjamin Herrenschmidt spin_lock_init(&phb->lock); 3821f1b7cc3eSGavin Shan prop32 = of_get_property(np, "bus-range", &len); 3822f1b7cc3eSGavin Shan if (prop32 && len == 8) { 38233a1a4661SBenjamin Herrenschmidt hose->first_busno = be32_to_cpu(prop32[0]); 38243a1a4661SBenjamin Herrenschmidt hose->last_busno = be32_to_cpu(prop32[1]); 3825f1b7cc3eSGavin Shan } else { 3826b7c670d6SRob Herring pr_warn(" Broken <bus-range> on %pOF\n", np); 3827184cd4a3SBenjamin Herrenschmidt hose->first_busno = 0; 3828184cd4a3SBenjamin Herrenschmidt hose->last_busno = 0xff; 3829f1b7cc3eSGavin Shan } 3830184cd4a3SBenjamin Herrenschmidt hose->private_data = phb; 3831e9cc17d4SGavin Shan phb->hub_id = hub_id; 3832184cd4a3SBenjamin Herrenschmidt phb->opal_id = phb_id; 3833aa0c033fSGavin Shan phb->type = ioda_type; 3834781a868fSWei Yang mutex_init(&phb->ioda.pe_alloc_mutex); 3835184cd4a3SBenjamin Herrenschmidt 3836cee72d5bSBenjamin Herrenschmidt /* Detect specific models for error handling */ 3837cee72d5bSBenjamin Herrenschmidt if (of_device_is_compatible(np, "ibm,p7ioc-pciex")) 3838cee72d5bSBenjamin Herrenschmidt phb->model = PNV_PHB_MODEL_P7IOC; 3839f3d40c25SBenjamin Herrenschmidt else if (of_device_is_compatible(np, "ibm,power8-pciex")) 3840aa0c033fSGavin Shan phb->model = PNV_PHB_MODEL_PHB3; 38415d2aa710SAlistair Popple else if (of_device_is_compatible(np, "ibm,power8-npu-pciex")) 38425d2aa710SAlistair Popple phb->model = PNV_PHB_MODEL_NPU; 3843616badd2SAlistair Popple else if (of_device_is_compatible(np, "ibm,power9-npu-pciex")) 3844616badd2SAlistair Popple phb->model = PNV_PHB_MODEL_NPU2; 3845cee72d5bSBenjamin Herrenschmidt else 3846cee72d5bSBenjamin Herrenschmidt phb->model = PNV_PHB_MODEL_UNKNOWN; 3847cee72d5bSBenjamin Herrenschmidt 38485cb1f8fdSRussell Currey /* Initialize diagnostic data buffer */ 38495cb1f8fdSRussell Currey prop32 = of_get_property(np, "ibm,phb-diag-data-size", NULL); 38505cb1f8fdSRussell Currey if (prop32) 38515cb1f8fdSRussell Currey phb->diag_data_size = be32_to_cpup(prop32); 38525cb1f8fdSRussell Currey else 38535cb1f8fdSRussell Currey phb->diag_data_size = PNV_PCI_DIAG_BUF_SIZE; 38545cb1f8fdSRussell Currey 38555cb1f8fdSRussell Currey phb->diag_data = memblock_virt_alloc(phb->diag_data_size, 0); 38565cb1f8fdSRussell Currey 3857aa0c033fSGavin Shan /* Parse 32-bit and IO ranges (if any) */ 38582f1ec02eSGavin Shan pci_process_bridge_OF_ranges(hose, np, !hose->global_number); 3859184cd4a3SBenjamin Herrenschmidt 3860aa0c033fSGavin Shan /* Get registers */ 3861fd141d1aSBenjamin Herrenschmidt if (!of_address_to_resource(np, 0, &r)) { 3862fd141d1aSBenjamin Herrenschmidt phb->regs_phys = r.start; 3863fd141d1aSBenjamin Herrenschmidt phb->regs = ioremap(r.start, resource_size(&r)); 3864184cd4a3SBenjamin Herrenschmidt if (phb->regs == NULL) 3865184cd4a3SBenjamin Herrenschmidt pr_err(" Failed to map registers !\n"); 3866fd141d1aSBenjamin Herrenschmidt } 3867577c8c88SGavin Shan 3868184cd4a3SBenjamin Herrenschmidt /* Initialize more IODA stuff */ 386992b8f137SGavin Shan phb->ioda.total_pe_num = 1; 387036954dc7SGavin Shan prop32 = of_get_property(np, "ibm,opal-num-pes", NULL); 387136954dc7SGavin Shan if (prop32) 387292b8f137SGavin Shan phb->ioda.total_pe_num = be32_to_cpup(prop32); 387336954dc7SGavin Shan prop32 = of_get_property(np, "ibm,opal-reserved-pe", NULL); 387436954dc7SGavin Shan if (prop32) 387592b8f137SGavin Shan phb->ioda.reserved_pe_idx = be32_to_cpup(prop32); 3876262af557SGuo Chao 3877c127562aSGavin Shan /* Invalidate RID to PE# mapping */ 3878c127562aSGavin Shan for (segno = 0; segno < ARRAY_SIZE(phb->ioda.pe_rmap); segno++) 3879c127562aSGavin Shan phb->ioda.pe_rmap[segno] = IODA_INVALID_PE; 3880c127562aSGavin Shan 3881262af557SGuo Chao /* Parse 64-bit MMIO range */ 3882262af557SGuo Chao pnv_ioda_parse_m64_window(phb); 3883262af557SGuo Chao 3884184cd4a3SBenjamin Herrenschmidt phb->ioda.m32_size = resource_size(&hose->mem_resources[0]); 3885aa0c033fSGavin Shan /* FW Has already off top 64k of M32 space (MSI space) */ 3886184cd4a3SBenjamin Herrenschmidt phb->ioda.m32_size += 0x10000; 3887184cd4a3SBenjamin Herrenschmidt 388892b8f137SGavin Shan phb->ioda.m32_segsize = phb->ioda.m32_size / phb->ioda.total_pe_num; 38893fd47f06SBenjamin Herrenschmidt phb->ioda.m32_pci_base = hose->mem_resources[0].start - hose->mem_offset[0]; 3890184cd4a3SBenjamin Herrenschmidt phb->ioda.io_size = hose->pci_io_size; 389192b8f137SGavin Shan phb->ioda.io_segsize = phb->ioda.io_size / phb->ioda.total_pe_num; 3892184cd4a3SBenjamin Herrenschmidt phb->ioda.io_pci_base = 0; /* XXX calculate this ? */ 3893184cd4a3SBenjamin Herrenschmidt 38942b923ed1SGavin Shan /* Calculate how many 32-bit TCE segments we have */ 38952b923ed1SGavin Shan phb->ioda.dma32_count = phb->ioda.m32_pci_base / 38962b923ed1SGavin Shan PNV_IODA1_DMA32_SEGSIZE; 38972b923ed1SGavin Shan 3898c35d2a8cSGavin Shan /* Allocate aux data & arrays. We don't have IO ports on PHB3 */ 389992a86756SAlexey Kardashevskiy size = _ALIGN_UP(max_t(unsigned, phb->ioda.total_pe_num, 8) / 8, 390092a86756SAlexey Kardashevskiy sizeof(unsigned long)); 390193289d8cSGavin Shan m64map_off = size; 390293289d8cSGavin Shan size += phb->ioda.total_pe_num * sizeof(phb->ioda.m64_segmap[0]); 3903184cd4a3SBenjamin Herrenschmidt m32map_off = size; 390492b8f137SGavin Shan size += phb->ioda.total_pe_num * sizeof(phb->ioda.m32_segmap[0]); 3905c35d2a8cSGavin Shan if (phb->type == PNV_PHB_IODA1) { 3906c35d2a8cSGavin Shan iomap_off = size; 390792b8f137SGavin Shan size += phb->ioda.total_pe_num * sizeof(phb->ioda.io_segmap[0]); 39082b923ed1SGavin Shan dma32map_off = size; 39092b923ed1SGavin Shan size += phb->ioda.dma32_count * 39102b923ed1SGavin Shan sizeof(phb->ioda.dma32_segmap[0]); 3911c35d2a8cSGavin Shan } 3912184cd4a3SBenjamin Herrenschmidt pemap_off = size; 391392b8f137SGavin Shan size += phb->ioda.total_pe_num * sizeof(struct pnv_ioda_pe); 3914e39f223fSMichael Ellerman aux = memblock_virt_alloc(size, 0); 3915184cd4a3SBenjamin Herrenschmidt phb->ioda.pe_alloc = aux; 391693289d8cSGavin Shan phb->ioda.m64_segmap = aux + m64map_off; 3917184cd4a3SBenjamin Herrenschmidt phb->ioda.m32_segmap = aux + m32map_off; 391893289d8cSGavin Shan for (segno = 0; segno < phb->ioda.total_pe_num; segno++) { 391993289d8cSGavin Shan phb->ioda.m64_segmap[segno] = IODA_INVALID_PE; 39203fa23ff8SGavin Shan phb->ioda.m32_segmap[segno] = IODA_INVALID_PE; 392193289d8cSGavin Shan } 39223fa23ff8SGavin Shan if (phb->type == PNV_PHB_IODA1) { 3923184cd4a3SBenjamin Herrenschmidt phb->ioda.io_segmap = aux + iomap_off; 39243fa23ff8SGavin Shan for (segno = 0; segno < phb->ioda.total_pe_num; segno++) 39253fa23ff8SGavin Shan phb->ioda.io_segmap[segno] = IODA_INVALID_PE; 39262b923ed1SGavin Shan 39272b923ed1SGavin Shan phb->ioda.dma32_segmap = aux + dma32map_off; 39282b923ed1SGavin Shan for (segno = 0; segno < phb->ioda.dma32_count; segno++) 39292b923ed1SGavin Shan phb->ioda.dma32_segmap[segno] = IODA_INVALID_PE; 39303fa23ff8SGavin Shan } 3931184cd4a3SBenjamin Herrenschmidt phb->ioda.pe_array = aux + pemap_off; 393263803c39SGavin Shan 393363803c39SGavin Shan /* 393463803c39SGavin Shan * Choose PE number for root bus, which shouldn't have 393563803c39SGavin Shan * M64 resources consumed by its child devices. To pick 393663803c39SGavin Shan * the PE number adjacent to the reserved one if possible. 393763803c39SGavin Shan */ 393863803c39SGavin Shan pnv_ioda_reserve_pe(phb, phb->ioda.reserved_pe_idx); 393963803c39SGavin Shan if (phb->ioda.reserved_pe_idx == 0) { 394063803c39SGavin Shan phb->ioda.root_pe_idx = 1; 394163803c39SGavin Shan pnv_ioda_reserve_pe(phb, phb->ioda.root_pe_idx); 394263803c39SGavin Shan } else if (phb->ioda.reserved_pe_idx == (phb->ioda.total_pe_num - 1)) { 394363803c39SGavin Shan phb->ioda.root_pe_idx = phb->ioda.reserved_pe_idx - 1; 394463803c39SGavin Shan pnv_ioda_reserve_pe(phb, phb->ioda.root_pe_idx); 394563803c39SGavin Shan } else { 394663803c39SGavin Shan phb->ioda.root_pe_idx = IODA_INVALID_PE; 394763803c39SGavin Shan } 3948184cd4a3SBenjamin Herrenschmidt 3949184cd4a3SBenjamin Herrenschmidt INIT_LIST_HEAD(&phb->ioda.pe_list); 3950781a868fSWei Yang mutex_init(&phb->ioda.pe_list_mutex); 3951184cd4a3SBenjamin Herrenschmidt 3952184cd4a3SBenjamin Herrenschmidt /* Calculate how many 32-bit TCE segments we have */ 39532b923ed1SGavin Shan phb->ioda.dma32_count = phb->ioda.m32_pci_base / 3954acce971cSGavin Shan PNV_IODA1_DMA32_SEGSIZE; 3955184cd4a3SBenjamin Herrenschmidt 3956aa0c033fSGavin Shan #if 0 /* We should really do that ... */ 3957184cd4a3SBenjamin Herrenschmidt rc = opal_pci_set_phb_mem_window(opal->phb_id, 3958184cd4a3SBenjamin Herrenschmidt window_type, 3959184cd4a3SBenjamin Herrenschmidt window_num, 3960184cd4a3SBenjamin Herrenschmidt starting_real_address, 3961184cd4a3SBenjamin Herrenschmidt starting_pci_address, 3962184cd4a3SBenjamin Herrenschmidt segment_size); 3963184cd4a3SBenjamin Herrenschmidt #endif 3964184cd4a3SBenjamin Herrenschmidt 3965262af557SGuo Chao pr_info(" %03d (%03d) PE's M32: 0x%x [segment=0x%x]\n", 396692b8f137SGavin Shan phb->ioda.total_pe_num, phb->ioda.reserved_pe_idx, 3967262af557SGuo Chao phb->ioda.m32_size, phb->ioda.m32_segsize); 3968262af557SGuo Chao if (phb->ioda.m64_size) 3969262af557SGuo Chao pr_info(" M64: 0x%lx [segment=0x%lx]\n", 3970262af557SGuo Chao phb->ioda.m64_size, phb->ioda.m64_segsize); 3971262af557SGuo Chao if (phb->ioda.io_size) 3972262af557SGuo Chao pr_info(" IO: 0x%x [segment=0x%x]\n", 3973184cd4a3SBenjamin Herrenschmidt phb->ioda.io_size, phb->ioda.io_segsize); 3974184cd4a3SBenjamin Herrenschmidt 3975262af557SGuo Chao 3976184cd4a3SBenjamin Herrenschmidt phb->hose->ops = &pnv_pci_ops; 397749dec922SGavin Shan phb->get_pe_state = pnv_ioda_get_pe_state; 397849dec922SGavin Shan phb->freeze_pe = pnv_ioda_freeze_pe; 397949dec922SGavin Shan phb->unfreeze_pe = pnv_ioda_unfreeze_pe; 3980184cd4a3SBenjamin Herrenschmidt 3981184cd4a3SBenjamin Herrenschmidt /* Setup MSI support */ 3982184cd4a3SBenjamin Herrenschmidt pnv_pci_init_ioda_msis(phb); 3983184cd4a3SBenjamin Herrenschmidt 3984c40a4210SGavin Shan /* 3985c40a4210SGavin Shan * We pass the PCI probe flag PCI_REASSIGN_ALL_RSRC here 3986c40a4210SGavin Shan * to let the PCI core do resource assignment. It's supposed 3987c40a4210SGavin Shan * that the PCI core will do correct I/O and MMIO alignment 3988c40a4210SGavin Shan * for the P2P bridge bars so that each PCI bus (excluding 3989c40a4210SGavin Shan * the child P2P bridges) can form individual PE. 3990184cd4a3SBenjamin Herrenschmidt */ 3991fb446ad0SGavin Shan ppc_md.pcibios_fixup = pnv_pci_ioda_fixup; 39925d2aa710SAlistair Popple 3993f9f83456SAlexey Kardashevskiy if (phb->type == PNV_PHB_NPU) { 39945d2aa710SAlistair Popple hose->controller_ops = pnv_npu_ioda_controller_ops; 3995f9f83456SAlexey Kardashevskiy } else { 3996f9f83456SAlexey Kardashevskiy phb->dma_dev_setup = pnv_pci_ioda_dma_dev_setup; 399792ae0353SDaniel Axtens hose->controller_ops = pnv_pci_ioda_controller_ops; 3998f9f83456SAlexey Kardashevskiy } 3999ad30cb99SMichael Ellerman 400038274637SYongji Xie ppc_md.pcibios_default_alignment = pnv_pci_default_alignment; 400138274637SYongji Xie 40026e628c7dSWei Yang #ifdef CONFIG_PCI_IOV 40036e628c7dSWei Yang ppc_md.pcibios_fixup_sriov = pnv_pci_ioda_fixup_iov_resources; 40045350ab3fSWei Yang ppc_md.pcibios_iov_resource_alignment = pnv_pci_iov_resource_alignment; 4005ad30cb99SMichael Ellerman #endif 4006ad30cb99SMichael Ellerman 4007c40a4210SGavin Shan pci_add_flags(PCI_REASSIGN_ALL_RSRC); 4008184cd4a3SBenjamin Herrenschmidt 4009184cd4a3SBenjamin Herrenschmidt /* Reset IODA tables to a clean state */ 4010d1a85eeeSGavin Shan rc = opal_pci_reset(phb_id, OPAL_RESET_PCI_IODA_TABLE, OPAL_ASSERT_RESET); 4011184cd4a3SBenjamin Herrenschmidt if (rc) 4012f11fe552SBenjamin Herrenschmidt pr_warning(" OPAL Error %ld performing IODA table reset !\n", rc); 4013361f2a2aSGavin Shan 40146060e9eaSAndrew Donnellan /* 40156060e9eaSAndrew Donnellan * If we're running in kdump kernel, the previous kernel never 4016361f2a2aSGavin Shan * shutdown PCI devices correctly. We already got IODA table 4017361f2a2aSGavin Shan * cleaned out. So we have to issue PHB reset to stop all PCI 40186060e9eaSAndrew Donnellan * transactions from previous kernel. 4019361f2a2aSGavin Shan */ 4020361f2a2aSGavin Shan if (is_kdump_kernel()) { 4021361f2a2aSGavin Shan pr_info(" Issue PHB reset ...\n"); 4022cadf364dSGavin Shan pnv_eeh_phb_reset(hose, EEH_RESET_FUNDAMENTAL); 4023cadf364dSGavin Shan pnv_eeh_phb_reset(hose, EEH_RESET_DEACTIVATE); 4024361f2a2aSGavin Shan } 4025262af557SGuo Chao 40269e9e8935SGavin Shan /* Remove M64 resource if we can't configure it successfully */ 40279e9e8935SGavin Shan if (!phb->init_m64 || phb->init_m64(phb)) 4028262af557SGuo Chao hose->mem_resources[1].flags = 0; 4029184cd4a3SBenjamin Herrenschmidt } 4030184cd4a3SBenjamin Herrenschmidt 403167975005SBjorn Helgaas void __init pnv_pci_init_ioda2_phb(struct device_node *np) 4032aa0c033fSGavin Shan { 4033e9cc17d4SGavin Shan pnv_pci_init_ioda_phb(np, 0, PNV_PHB_IODA2); 4034aa0c033fSGavin Shan } 4035aa0c033fSGavin Shan 40365d2aa710SAlistair Popple void __init pnv_pci_init_npu_phb(struct device_node *np) 40375d2aa710SAlistair Popple { 40385d2aa710SAlistair Popple pnv_pci_init_ioda_phb(np, 0, PNV_PHB_NPU); 40395d2aa710SAlistair Popple } 40405d2aa710SAlistair Popple 4041184cd4a3SBenjamin Herrenschmidt void __init pnv_pci_init_ioda_hub(struct device_node *np) 4042184cd4a3SBenjamin Herrenschmidt { 4043184cd4a3SBenjamin Herrenschmidt struct device_node *phbn; 4044c681b93cSAlistair Popple const __be64 *prop64; 4045184cd4a3SBenjamin Herrenschmidt u64 hub_id; 4046184cd4a3SBenjamin Herrenschmidt 4047b7c670d6SRob Herring pr_info("Probing IODA IO-Hub %pOF\n", np); 4048184cd4a3SBenjamin Herrenschmidt 4049184cd4a3SBenjamin Herrenschmidt prop64 = of_get_property(np, "ibm,opal-hubid", NULL); 4050184cd4a3SBenjamin Herrenschmidt if (!prop64) { 4051184cd4a3SBenjamin Herrenschmidt pr_err(" Missing \"ibm,opal-hubid\" property !\n"); 4052184cd4a3SBenjamin Herrenschmidt return; 4053184cd4a3SBenjamin Herrenschmidt } 4054184cd4a3SBenjamin Herrenschmidt hub_id = be64_to_cpup(prop64); 4055184cd4a3SBenjamin Herrenschmidt pr_devel(" HUB-ID : 0x%016llx\n", hub_id); 4056184cd4a3SBenjamin Herrenschmidt 4057184cd4a3SBenjamin Herrenschmidt /* Count child PHBs */ 4058184cd4a3SBenjamin Herrenschmidt for_each_child_of_node(np, phbn) { 4059184cd4a3SBenjamin Herrenschmidt /* Look for IODA1 PHBs */ 4060184cd4a3SBenjamin Herrenschmidt if (of_device_is_compatible(phbn, "ibm,ioda-phb")) 4061e9cc17d4SGavin Shan pnv_pci_init_ioda_phb(phbn, hub_id, PNV_PHB_IODA1); 4062184cd4a3SBenjamin Herrenschmidt } 4063184cd4a3SBenjamin Herrenschmidt } 4064