1184cd4a3SBenjamin Herrenschmidt /* 2184cd4a3SBenjamin Herrenschmidt * Support PCI/PCIe on PowerNV platforms 3184cd4a3SBenjamin Herrenschmidt * 4184cd4a3SBenjamin Herrenschmidt * Copyright 2011 Benjamin Herrenschmidt, IBM Corp. 5184cd4a3SBenjamin Herrenschmidt * 6184cd4a3SBenjamin Herrenschmidt * This program is free software; you can redistribute it and/or 7184cd4a3SBenjamin Herrenschmidt * modify it under the terms of the GNU General Public License 8184cd4a3SBenjamin Herrenschmidt * as published by the Free Software Foundation; either version 9184cd4a3SBenjamin Herrenschmidt * 2 of the License, or (at your option) any later version. 10184cd4a3SBenjamin Herrenschmidt */ 11184cd4a3SBenjamin Herrenschmidt 12cee72d5bSBenjamin Herrenschmidt #undef DEBUG 13184cd4a3SBenjamin Herrenschmidt 14184cd4a3SBenjamin Herrenschmidt #include <linux/kernel.h> 15184cd4a3SBenjamin Herrenschmidt #include <linux/pci.h> 16361f2a2aSGavin Shan #include <linux/crash_dump.h> 1737c367f2SGavin Shan #include <linux/debugfs.h> 18184cd4a3SBenjamin Herrenschmidt #include <linux/delay.h> 19184cd4a3SBenjamin Herrenschmidt #include <linux/string.h> 20184cd4a3SBenjamin Herrenschmidt #include <linux/init.h> 21184cd4a3SBenjamin Herrenschmidt #include <linux/bootmem.h> 22184cd4a3SBenjamin Herrenschmidt #include <linux/irq.h> 23184cd4a3SBenjamin Herrenschmidt #include <linux/io.h> 24184cd4a3SBenjamin Herrenschmidt #include <linux/msi.h> 25cd15b048SBenjamin Herrenschmidt #include <linux/memblock.h> 26ac9a5889SAlexey Kardashevskiy #include <linux/iommu.h> 27e57080f1SAlexey Kardashevskiy #include <linux/rculist.h> 284793d65dSAlexey Kardashevskiy #include <linux/sizes.h> 29184cd4a3SBenjamin Herrenschmidt 30184cd4a3SBenjamin Herrenschmidt #include <asm/sections.h> 31184cd4a3SBenjamin Herrenschmidt #include <asm/io.h> 32184cd4a3SBenjamin Herrenschmidt #include <asm/prom.h> 33184cd4a3SBenjamin Herrenschmidt #include <asm/pci-bridge.h> 34184cd4a3SBenjamin Herrenschmidt #include <asm/machdep.h> 35fb1b55d6SGavin Shan #include <asm/msi_bitmap.h> 36184cd4a3SBenjamin Herrenschmidt #include <asm/ppc-pci.h> 37184cd4a3SBenjamin Herrenschmidt #include <asm/opal.h> 38184cd4a3SBenjamin Herrenschmidt #include <asm/iommu.h> 39184cd4a3SBenjamin Herrenschmidt #include <asm/tce.h> 40137436c9SGavin Shan #include <asm/xics.h> 4137c367f2SGavin Shan #include <asm/debug.h> 42262af557SGuo Chao #include <asm/firmware.h> 4380c49c7eSIan Munsie #include <asm/pnv-pci.h> 44aca6913fSAlexey Kardashevskiy #include <asm/mmzone.h> 4580c49c7eSIan Munsie 46ec249dd8SMichael Neuling #include <misc/cxl-base.h> 47184cd4a3SBenjamin Herrenschmidt 48184cd4a3SBenjamin Herrenschmidt #include "powernv.h" 49184cd4a3SBenjamin Herrenschmidt #include "pci.h" 50184cd4a3SBenjamin Herrenschmidt 5199451551SGavin Shan #define PNV_IODA1_M64_NUM 16 /* Number of M64 BARs */ 5299451551SGavin Shan #define PNV_IODA1_M64_SEGS 8 /* Segments per M64 BAR */ 5399451551SGavin Shan 54781a868fSWei Yang /* 256M DMA window, 4K TCE pages, 8 bytes TCE */ 55781a868fSWei Yang #define TCE32_TABLE_SIZE ((0x10000000 / 0x1000) * 8) 56781a868fSWei Yang 57bbb845c4SAlexey Kardashevskiy #define POWERNV_IOMMU_DEFAULT_LEVELS 1 58bbb845c4SAlexey Kardashevskiy #define POWERNV_IOMMU_MAX_LEVELS 5 59bbb845c4SAlexey Kardashevskiy 60aca6913fSAlexey Kardashevskiy static void pnv_pci_ioda2_table_free_pages(struct iommu_table *tbl); 61aca6913fSAlexey Kardashevskiy 626d31c2faSJoe Perches static void pe_level_printk(const struct pnv_ioda_pe *pe, const char *level, 636d31c2faSJoe Perches const char *fmt, ...) 646d31c2faSJoe Perches { 656d31c2faSJoe Perches struct va_format vaf; 666d31c2faSJoe Perches va_list args; 676d31c2faSJoe Perches char pfix[32]; 68184cd4a3SBenjamin Herrenschmidt 696d31c2faSJoe Perches va_start(args, fmt); 706d31c2faSJoe Perches 716d31c2faSJoe Perches vaf.fmt = fmt; 726d31c2faSJoe Perches vaf.va = &args; 736d31c2faSJoe Perches 74781a868fSWei Yang if (pe->flags & PNV_IODA_PE_DEV) 756d31c2faSJoe Perches strlcpy(pfix, dev_name(&pe->pdev->dev), sizeof(pfix)); 76781a868fSWei Yang else if (pe->flags & (PNV_IODA_PE_BUS | PNV_IODA_PE_BUS_ALL)) 776d31c2faSJoe Perches sprintf(pfix, "%04x:%02x ", 786d31c2faSJoe Perches pci_domain_nr(pe->pbus), pe->pbus->number); 79781a868fSWei Yang #ifdef CONFIG_PCI_IOV 80781a868fSWei Yang else if (pe->flags & PNV_IODA_PE_VF) 81781a868fSWei Yang sprintf(pfix, "%04x:%02x:%2x.%d", 82781a868fSWei Yang pci_domain_nr(pe->parent_dev->bus), 83781a868fSWei Yang (pe->rid & 0xff00) >> 8, 84781a868fSWei Yang PCI_SLOT(pe->rid), PCI_FUNC(pe->rid)); 85781a868fSWei Yang #endif /* CONFIG_PCI_IOV*/ 866d31c2faSJoe Perches 876d31c2faSJoe Perches printk("%spci %s: [PE# %.3d] %pV", 886d31c2faSJoe Perches level, pfix, pe->pe_number, &vaf); 896d31c2faSJoe Perches 906d31c2faSJoe Perches va_end(args); 916d31c2faSJoe Perches } 926d31c2faSJoe Perches 936d31c2faSJoe Perches #define pe_err(pe, fmt, ...) \ 946d31c2faSJoe Perches pe_level_printk(pe, KERN_ERR, fmt, ##__VA_ARGS__) 956d31c2faSJoe Perches #define pe_warn(pe, fmt, ...) \ 966d31c2faSJoe Perches pe_level_printk(pe, KERN_WARNING, fmt, ##__VA_ARGS__) 976d31c2faSJoe Perches #define pe_info(pe, fmt, ...) \ 986d31c2faSJoe Perches pe_level_printk(pe, KERN_INFO, fmt, ##__VA_ARGS__) 99184cd4a3SBenjamin Herrenschmidt 1004e287840SThadeu Lima de Souza Cascardo static bool pnv_iommu_bypass_disabled __read_mostly; 1014e287840SThadeu Lima de Souza Cascardo 1024e287840SThadeu Lima de Souza Cascardo static int __init iommu_setup(char *str) 1034e287840SThadeu Lima de Souza Cascardo { 1044e287840SThadeu Lima de Souza Cascardo if (!str) 1054e287840SThadeu Lima de Souza Cascardo return -EINVAL; 1064e287840SThadeu Lima de Souza Cascardo 1074e287840SThadeu Lima de Souza Cascardo while (*str) { 1084e287840SThadeu Lima de Souza Cascardo if (!strncmp(str, "nobypass", 8)) { 1094e287840SThadeu Lima de Souza Cascardo pnv_iommu_bypass_disabled = true; 1104e287840SThadeu Lima de Souza Cascardo pr_info("PowerNV: IOMMU bypass window disabled.\n"); 1114e287840SThadeu Lima de Souza Cascardo break; 1124e287840SThadeu Lima de Souza Cascardo } 1134e287840SThadeu Lima de Souza Cascardo str += strcspn(str, ","); 1144e287840SThadeu Lima de Souza Cascardo if (*str == ',') 1154e287840SThadeu Lima de Souza Cascardo str++; 1164e287840SThadeu Lima de Souza Cascardo } 1174e287840SThadeu Lima de Souza Cascardo 1184e287840SThadeu Lima de Souza Cascardo return 0; 1194e287840SThadeu Lima de Souza Cascardo } 1204e287840SThadeu Lima de Souza Cascardo early_param("iommu", iommu_setup); 1214e287840SThadeu Lima de Souza Cascardo 122262af557SGuo Chao static inline bool pnv_pci_is_mem_pref_64(unsigned long flags) 123262af557SGuo Chao { 124262af557SGuo Chao return ((flags & (IORESOURCE_MEM_64 | IORESOURCE_PREFETCH)) == 125262af557SGuo Chao (IORESOURCE_MEM_64 | IORESOURCE_PREFETCH)); 126262af557SGuo Chao } 127262af557SGuo Chao 1284b82ab18SGavin Shan static void pnv_ioda_reserve_pe(struct pnv_phb *phb, int pe_no) 1294b82ab18SGavin Shan { 13092b8f137SGavin Shan if (!(pe_no >= 0 && pe_no < phb->ioda.total_pe_num)) { 1314b82ab18SGavin Shan pr_warn("%s: Invalid PE %d on PHB#%x\n", 1324b82ab18SGavin Shan __func__, pe_no, phb->hose->global_number); 1334b82ab18SGavin Shan return; 1344b82ab18SGavin Shan } 1354b82ab18SGavin Shan 136e9dc4d7fSGavin Shan if (test_and_set_bit(pe_no, phb->ioda.pe_alloc)) 137e9dc4d7fSGavin Shan pr_debug("%s: PE %d was reserved on PHB#%x\n", 1384b82ab18SGavin Shan __func__, pe_no, phb->hose->global_number); 1394b82ab18SGavin Shan 1404b82ab18SGavin Shan phb->ioda.pe_array[pe_no].phb = phb; 1414b82ab18SGavin Shan phb->ioda.pe_array[pe_no].pe_number = pe_no; 1424b82ab18SGavin Shan } 1434b82ab18SGavin Shan 144689ee8c9SGavin Shan static unsigned int pnv_ioda_alloc_pe(struct pnv_phb *phb) 145184cd4a3SBenjamin Herrenschmidt { 146184cd4a3SBenjamin Herrenschmidt unsigned long pe; 147184cd4a3SBenjamin Herrenschmidt 148184cd4a3SBenjamin Herrenschmidt do { 149184cd4a3SBenjamin Herrenschmidt pe = find_next_zero_bit(phb->ioda.pe_alloc, 15092b8f137SGavin Shan phb->ioda.total_pe_num, 0); 15192b8f137SGavin Shan if (pe >= phb->ioda.total_pe_num) 152184cd4a3SBenjamin Herrenschmidt return IODA_INVALID_PE; 153184cd4a3SBenjamin Herrenschmidt } while(test_and_set_bit(pe, phb->ioda.pe_alloc)); 154184cd4a3SBenjamin Herrenschmidt 1554cce9550SGavin Shan phb->ioda.pe_array[pe].phb = phb; 156184cd4a3SBenjamin Herrenschmidt phb->ioda.pe_array[pe].pe_number = pe; 157184cd4a3SBenjamin Herrenschmidt return pe; 158184cd4a3SBenjamin Herrenschmidt } 159184cd4a3SBenjamin Herrenschmidt 160cad5cef6SGreg Kroah-Hartman static void pnv_ioda_free_pe(struct pnv_phb *phb, int pe) 161184cd4a3SBenjamin Herrenschmidt { 162184cd4a3SBenjamin Herrenschmidt WARN_ON(phb->ioda.pe_array[pe].pdev); 163184cd4a3SBenjamin Herrenschmidt 164184cd4a3SBenjamin Herrenschmidt memset(&phb->ioda.pe_array[pe], 0, sizeof(struct pnv_ioda_pe)); 165184cd4a3SBenjamin Herrenschmidt clear_bit(pe, phb->ioda.pe_alloc); 166184cd4a3SBenjamin Herrenschmidt } 167184cd4a3SBenjamin Herrenschmidt 168262af557SGuo Chao /* The default M64 BAR is shared by all PEs */ 169262af557SGuo Chao static int pnv_ioda2_init_m64(struct pnv_phb *phb) 170262af557SGuo Chao { 171262af557SGuo Chao const char *desc; 172262af557SGuo Chao struct resource *r; 173262af557SGuo Chao s64 rc; 174262af557SGuo Chao 175262af557SGuo Chao /* Configure the default M64 BAR */ 176262af557SGuo Chao rc = opal_pci_set_phb_mem_window(phb->opal_id, 177262af557SGuo Chao OPAL_M64_WINDOW_TYPE, 178262af557SGuo Chao phb->ioda.m64_bar_idx, 179262af557SGuo Chao phb->ioda.m64_base, 180262af557SGuo Chao 0, /* unused */ 181262af557SGuo Chao phb->ioda.m64_size); 182262af557SGuo Chao if (rc != OPAL_SUCCESS) { 183262af557SGuo Chao desc = "configuring"; 184262af557SGuo Chao goto fail; 185262af557SGuo Chao } 186262af557SGuo Chao 187262af557SGuo Chao /* Enable the default M64 BAR */ 188262af557SGuo Chao rc = opal_pci_phb_mmio_enable(phb->opal_id, 189262af557SGuo Chao OPAL_M64_WINDOW_TYPE, 190262af557SGuo Chao phb->ioda.m64_bar_idx, 191262af557SGuo Chao OPAL_ENABLE_M64_SPLIT); 192262af557SGuo Chao if (rc != OPAL_SUCCESS) { 193262af557SGuo Chao desc = "enabling"; 194262af557SGuo Chao goto fail; 195262af557SGuo Chao } 196262af557SGuo Chao 197262af557SGuo Chao /* Mark the M64 BAR assigned */ 198262af557SGuo Chao set_bit(phb->ioda.m64_bar_idx, &phb->ioda.m64_bar_alloc); 199262af557SGuo Chao 200262af557SGuo Chao /* 201262af557SGuo Chao * Strip off the segment used by the reserved PE, which is 202262af557SGuo Chao * expected to be 0 or last one of PE capabicity. 203262af557SGuo Chao */ 204262af557SGuo Chao r = &phb->hose->mem_resources[1]; 20592b8f137SGavin Shan if (phb->ioda.reserved_pe_idx == 0) 206262af557SGuo Chao r->start += phb->ioda.m64_segsize; 20792b8f137SGavin Shan else if (phb->ioda.reserved_pe_idx == (phb->ioda.total_pe_num - 1)) 208262af557SGuo Chao r->end -= phb->ioda.m64_segsize; 209262af557SGuo Chao else 210262af557SGuo Chao pr_warn(" Cannot strip M64 segment for reserved PE#%d\n", 21192b8f137SGavin Shan phb->ioda.reserved_pe_idx); 212262af557SGuo Chao 213262af557SGuo Chao return 0; 214262af557SGuo Chao 215262af557SGuo Chao fail: 216262af557SGuo Chao pr_warn(" Failure %lld %s M64 BAR#%d\n", 217262af557SGuo Chao rc, desc, phb->ioda.m64_bar_idx); 218262af557SGuo Chao opal_pci_phb_mmio_enable(phb->opal_id, 219262af557SGuo Chao OPAL_M64_WINDOW_TYPE, 220262af557SGuo Chao phb->ioda.m64_bar_idx, 221262af557SGuo Chao OPAL_DISABLE_M64); 222262af557SGuo Chao return -EIO; 223262af557SGuo Chao } 224262af557SGuo Chao 225c430670aSGavin Shan static void pnv_ioda_reserve_dev_m64_pe(struct pci_dev *pdev, 22696a2f92bSGavin Shan unsigned long *pe_bitmap) 227262af557SGuo Chao { 22896a2f92bSGavin Shan struct pci_controller *hose = pci_bus_to_host(pdev->bus); 22996a2f92bSGavin Shan struct pnv_phb *phb = hose->private_data; 230262af557SGuo Chao struct resource *r; 23196a2f92bSGavin Shan resource_size_t base, sgsz, start, end; 23296a2f92bSGavin Shan int segno, i; 233262af557SGuo Chao 23496a2f92bSGavin Shan base = phb->ioda.m64_base; 23596a2f92bSGavin Shan sgsz = phb->ioda.m64_segsize; 23696a2f92bSGavin Shan for (i = 0; i <= PCI_ROM_RESOURCE; i++) { 23796a2f92bSGavin Shan r = &pdev->resource[i]; 23896a2f92bSGavin Shan if (!r->parent || !pnv_pci_is_mem_pref_64(r->flags)) 239262af557SGuo Chao continue; 240262af557SGuo Chao 24196a2f92bSGavin Shan start = _ALIGN_DOWN(r->start - base, sgsz); 24296a2f92bSGavin Shan end = _ALIGN_UP(r->end - base, sgsz); 24396a2f92bSGavin Shan for (segno = start / sgsz; segno < end / sgsz; segno++) { 24496a2f92bSGavin Shan if (pe_bitmap) 24596a2f92bSGavin Shan set_bit(segno, pe_bitmap); 24696a2f92bSGavin Shan else 24796a2f92bSGavin Shan pnv_ioda_reserve_pe(phb, segno); 248262af557SGuo Chao } 249262af557SGuo Chao } 250262af557SGuo Chao } 251262af557SGuo Chao 25299451551SGavin Shan static int pnv_ioda1_init_m64(struct pnv_phb *phb) 25399451551SGavin Shan { 25499451551SGavin Shan struct resource *r; 25599451551SGavin Shan int index; 25699451551SGavin Shan 25799451551SGavin Shan /* 25899451551SGavin Shan * There are 16 M64 BARs, each of which has 8 segments. So 25999451551SGavin Shan * there are as many M64 segments as the maximum number of 26099451551SGavin Shan * PEs, which is 128. 26199451551SGavin Shan */ 26299451551SGavin Shan for (index = 0; index < PNV_IODA1_M64_NUM; index++) { 26399451551SGavin Shan unsigned long base, segsz = phb->ioda.m64_segsize; 26499451551SGavin Shan int64_t rc; 26599451551SGavin Shan 26699451551SGavin Shan base = phb->ioda.m64_base + 26799451551SGavin Shan index * PNV_IODA1_M64_SEGS * segsz; 26899451551SGavin Shan rc = opal_pci_set_phb_mem_window(phb->opal_id, 26999451551SGavin Shan OPAL_M64_WINDOW_TYPE, index, base, 0, 27099451551SGavin Shan PNV_IODA1_M64_SEGS * segsz); 27199451551SGavin Shan if (rc != OPAL_SUCCESS) { 27299451551SGavin Shan pr_warn(" Error %lld setting M64 PHB#%d-BAR#%d\n", 27399451551SGavin Shan rc, phb->hose->global_number, index); 27499451551SGavin Shan goto fail; 27599451551SGavin Shan } 27699451551SGavin Shan 27799451551SGavin Shan rc = opal_pci_phb_mmio_enable(phb->opal_id, 27899451551SGavin Shan OPAL_M64_WINDOW_TYPE, index, 27999451551SGavin Shan OPAL_ENABLE_M64_SPLIT); 28099451551SGavin Shan if (rc != OPAL_SUCCESS) { 28199451551SGavin Shan pr_warn(" Error %lld enabling M64 PHB#%d-BAR#%d\n", 28299451551SGavin Shan rc, phb->hose->global_number, index); 28399451551SGavin Shan goto fail; 28499451551SGavin Shan } 28599451551SGavin Shan } 28699451551SGavin Shan 28799451551SGavin Shan /* 28899451551SGavin Shan * Exclude the segment used by the reserved PE, which 28999451551SGavin Shan * is expected to be 0 or last supported PE#. 29099451551SGavin Shan */ 29199451551SGavin Shan r = &phb->hose->mem_resources[1]; 29299451551SGavin Shan if (phb->ioda.reserved_pe_idx == 0) 29399451551SGavin Shan r->start += phb->ioda.m64_segsize; 29499451551SGavin Shan else if (phb->ioda.reserved_pe_idx == (phb->ioda.total_pe_num - 1)) 29599451551SGavin Shan r->end -= phb->ioda.m64_segsize; 29699451551SGavin Shan else 29799451551SGavin Shan WARN(1, "Wrong reserved PE#%d on PHB#%d\n", 29899451551SGavin Shan phb->ioda.reserved_pe_idx, phb->hose->global_number); 29999451551SGavin Shan 30099451551SGavin Shan return 0; 30199451551SGavin Shan 30299451551SGavin Shan fail: 30399451551SGavin Shan for ( ; index >= 0; index--) 30499451551SGavin Shan opal_pci_phb_mmio_enable(phb->opal_id, 30599451551SGavin Shan OPAL_M64_WINDOW_TYPE, index, OPAL_DISABLE_M64); 30699451551SGavin Shan 30799451551SGavin Shan return -EIO; 30899451551SGavin Shan } 30999451551SGavin Shan 310c430670aSGavin Shan static void pnv_ioda_reserve_m64_pe(struct pci_bus *bus, 31196a2f92bSGavin Shan unsigned long *pe_bitmap, 31296a2f92bSGavin Shan bool all) 313262af557SGuo Chao { 314262af557SGuo Chao struct pci_dev *pdev; 31596a2f92bSGavin Shan 31696a2f92bSGavin Shan list_for_each_entry(pdev, &bus->devices, bus_list) { 317c430670aSGavin Shan pnv_ioda_reserve_dev_m64_pe(pdev, pe_bitmap); 31896a2f92bSGavin Shan 31996a2f92bSGavin Shan if (all && pdev->subordinate) 320c430670aSGavin Shan pnv_ioda_reserve_m64_pe(pdev->subordinate, 32196a2f92bSGavin Shan pe_bitmap, all); 32296a2f92bSGavin Shan } 32396a2f92bSGavin Shan } 32496a2f92bSGavin Shan 325c430670aSGavin Shan static unsigned int pnv_ioda_pick_m64_pe(struct pci_bus *bus, bool all) 326262af557SGuo Chao { 32726ba248dSGavin Shan struct pci_controller *hose = pci_bus_to_host(bus); 32826ba248dSGavin Shan struct pnv_phb *phb = hose->private_data; 329262af557SGuo Chao struct pnv_ioda_pe *master_pe, *pe; 330262af557SGuo Chao unsigned long size, *pe_alloc; 33126ba248dSGavin Shan int i; 332262af557SGuo Chao 333262af557SGuo Chao /* Root bus shouldn't use M64 */ 334262af557SGuo Chao if (pci_is_root_bus(bus)) 335262af557SGuo Chao return IODA_INVALID_PE; 336262af557SGuo Chao 337262af557SGuo Chao /* Allocate bitmap */ 33892b8f137SGavin Shan size = _ALIGN_UP(phb->ioda.total_pe_num / 8, sizeof(unsigned long)); 339262af557SGuo Chao pe_alloc = kzalloc(size, GFP_KERNEL); 340262af557SGuo Chao if (!pe_alloc) { 341262af557SGuo Chao pr_warn("%s: Out of memory !\n", 342262af557SGuo Chao __func__); 343262af557SGuo Chao return IODA_INVALID_PE; 344262af557SGuo Chao } 345262af557SGuo Chao 34626ba248dSGavin Shan /* Figure out reserved PE numbers by the PE */ 347c430670aSGavin Shan pnv_ioda_reserve_m64_pe(bus, pe_alloc, all); 348262af557SGuo Chao 349262af557SGuo Chao /* 350262af557SGuo Chao * the current bus might not own M64 window and that's all 351262af557SGuo Chao * contributed by its child buses. For the case, we needn't 352262af557SGuo Chao * pick M64 dependent PE#. 353262af557SGuo Chao */ 35492b8f137SGavin Shan if (bitmap_empty(pe_alloc, phb->ioda.total_pe_num)) { 355262af557SGuo Chao kfree(pe_alloc); 356262af557SGuo Chao return IODA_INVALID_PE; 357262af557SGuo Chao } 358262af557SGuo Chao 359262af557SGuo Chao /* 360262af557SGuo Chao * Figure out the master PE and put all slave PEs to master 361262af557SGuo Chao * PE's list to form compound PE. 362262af557SGuo Chao */ 363262af557SGuo Chao master_pe = NULL; 364262af557SGuo Chao i = -1; 36592b8f137SGavin Shan while ((i = find_next_bit(pe_alloc, phb->ioda.total_pe_num, i + 1)) < 36692b8f137SGavin Shan phb->ioda.total_pe_num) { 367262af557SGuo Chao pe = &phb->ioda.pe_array[i]; 368262af557SGuo Chao 36993289d8cSGavin Shan phb->ioda.m64_segmap[pe->pe_number] = pe->pe_number; 370262af557SGuo Chao if (!master_pe) { 371262af557SGuo Chao pe->flags |= PNV_IODA_PE_MASTER; 372262af557SGuo Chao INIT_LIST_HEAD(&pe->slaves); 373262af557SGuo Chao master_pe = pe; 374262af557SGuo Chao } else { 375262af557SGuo Chao pe->flags |= PNV_IODA_PE_SLAVE; 376262af557SGuo Chao pe->master = master_pe; 377262af557SGuo Chao list_add_tail(&pe->list, &master_pe->slaves); 378262af557SGuo Chao } 37999451551SGavin Shan 38099451551SGavin Shan /* 38199451551SGavin Shan * P7IOC supports M64DT, which helps mapping M64 segment 38299451551SGavin Shan * to one particular PE#. However, PHB3 has fixed mapping 38399451551SGavin Shan * between M64 segment and PE#. In order to have same logic 38499451551SGavin Shan * for P7IOC and PHB3, we enforce fixed mapping between M64 38599451551SGavin Shan * segment and PE# on P7IOC. 38699451551SGavin Shan */ 38799451551SGavin Shan if (phb->type == PNV_PHB_IODA1) { 38899451551SGavin Shan int64_t rc; 38999451551SGavin Shan 39099451551SGavin Shan rc = opal_pci_map_pe_mmio_window(phb->opal_id, 39199451551SGavin Shan pe->pe_number, OPAL_M64_WINDOW_TYPE, 39299451551SGavin Shan pe->pe_number / PNV_IODA1_M64_SEGS, 39399451551SGavin Shan pe->pe_number % PNV_IODA1_M64_SEGS); 39499451551SGavin Shan if (rc != OPAL_SUCCESS) 39599451551SGavin Shan pr_warn("%s: Error %lld mapping M64 for PHB#%d-PE#%d\n", 39699451551SGavin Shan __func__, rc, phb->hose->global_number, 39799451551SGavin Shan pe->pe_number); 39899451551SGavin Shan } 399262af557SGuo Chao } 400262af557SGuo Chao 401262af557SGuo Chao kfree(pe_alloc); 402262af557SGuo Chao return master_pe->pe_number; 403262af557SGuo Chao } 404262af557SGuo Chao 405262af557SGuo Chao static void __init pnv_ioda_parse_m64_window(struct pnv_phb *phb) 406262af557SGuo Chao { 407262af557SGuo Chao struct pci_controller *hose = phb->hose; 408262af557SGuo Chao struct device_node *dn = hose->dn; 409262af557SGuo Chao struct resource *res; 410262af557SGuo Chao const u32 *r; 411262af557SGuo Chao u64 pci_addr; 412262af557SGuo Chao 41399451551SGavin Shan if (phb->type != PNV_PHB_IODA1 && phb->type != PNV_PHB_IODA2) { 4141665c4a8SGavin Shan pr_info(" Not support M64 window\n"); 4151665c4a8SGavin Shan return; 4161665c4a8SGavin Shan } 4171665c4a8SGavin Shan 418e4d54f71SStewart Smith if (!firmware_has_feature(FW_FEATURE_OPAL)) { 419262af557SGuo Chao pr_info(" Firmware too old to support M64 window\n"); 420262af557SGuo Chao return; 421262af557SGuo Chao } 422262af557SGuo Chao 423262af557SGuo Chao r = of_get_property(dn, "ibm,opal-m64-window", NULL); 424262af557SGuo Chao if (!r) { 425262af557SGuo Chao pr_info(" No <ibm,opal-m64-window> on %s\n", 426262af557SGuo Chao dn->full_name); 427262af557SGuo Chao return; 428262af557SGuo Chao } 429262af557SGuo Chao 430262af557SGuo Chao res = &hose->mem_resources[1]; 431e80c4e7cSGavin Shan res->name = dn->full_name; 432262af557SGuo Chao res->start = of_translate_address(dn, r + 2); 433262af557SGuo Chao res->end = res->start + of_read_number(r + 4, 2) - 1; 434262af557SGuo Chao res->flags = (IORESOURCE_MEM | IORESOURCE_MEM_64 | IORESOURCE_PREFETCH); 435262af557SGuo Chao pci_addr = of_read_number(r, 2); 436262af557SGuo Chao hose->mem_offset[1] = res->start - pci_addr; 437262af557SGuo Chao 438262af557SGuo Chao phb->ioda.m64_size = resource_size(res); 43992b8f137SGavin Shan phb->ioda.m64_segsize = phb->ioda.m64_size / phb->ioda.total_pe_num; 440262af557SGuo Chao phb->ioda.m64_base = pci_addr; 441262af557SGuo Chao 442e9863e68SWei Yang pr_info(" MEM64 0x%016llx..0x%016llx -> 0x%016llx\n", 443e9863e68SWei Yang res->start, res->end, pci_addr); 444e9863e68SWei Yang 445262af557SGuo Chao /* Use last M64 BAR to cover M64 window */ 446262af557SGuo Chao phb->ioda.m64_bar_idx = 15; 44799451551SGavin Shan if (phb->type == PNV_PHB_IODA1) 44899451551SGavin Shan phb->init_m64 = pnv_ioda1_init_m64; 44999451551SGavin Shan else 450262af557SGuo Chao phb->init_m64 = pnv_ioda2_init_m64; 451c430670aSGavin Shan phb->reserve_m64_pe = pnv_ioda_reserve_m64_pe; 452c430670aSGavin Shan phb->pick_m64_pe = pnv_ioda_pick_m64_pe; 453262af557SGuo Chao } 454262af557SGuo Chao 45549dec922SGavin Shan static void pnv_ioda_freeze_pe(struct pnv_phb *phb, int pe_no) 45649dec922SGavin Shan { 45749dec922SGavin Shan struct pnv_ioda_pe *pe = &phb->ioda.pe_array[pe_no]; 45849dec922SGavin Shan struct pnv_ioda_pe *slave; 45949dec922SGavin Shan s64 rc; 46049dec922SGavin Shan 46149dec922SGavin Shan /* Fetch master PE */ 46249dec922SGavin Shan if (pe->flags & PNV_IODA_PE_SLAVE) { 46349dec922SGavin Shan pe = pe->master; 464ec8e4e9dSGavin Shan if (WARN_ON(!pe || !(pe->flags & PNV_IODA_PE_MASTER))) 465ec8e4e9dSGavin Shan return; 466ec8e4e9dSGavin Shan 46749dec922SGavin Shan pe_no = pe->pe_number; 46849dec922SGavin Shan } 46949dec922SGavin Shan 47049dec922SGavin Shan /* Freeze master PE */ 47149dec922SGavin Shan rc = opal_pci_eeh_freeze_set(phb->opal_id, 47249dec922SGavin Shan pe_no, 47349dec922SGavin Shan OPAL_EEH_ACTION_SET_FREEZE_ALL); 47449dec922SGavin Shan if (rc != OPAL_SUCCESS) { 47549dec922SGavin Shan pr_warn("%s: Failure %lld freezing PHB#%x-PE#%x\n", 47649dec922SGavin Shan __func__, rc, phb->hose->global_number, pe_no); 47749dec922SGavin Shan return; 47849dec922SGavin Shan } 47949dec922SGavin Shan 48049dec922SGavin Shan /* Freeze slave PEs */ 48149dec922SGavin Shan if (!(pe->flags & PNV_IODA_PE_MASTER)) 48249dec922SGavin Shan return; 48349dec922SGavin Shan 48449dec922SGavin Shan list_for_each_entry(slave, &pe->slaves, list) { 48549dec922SGavin Shan rc = opal_pci_eeh_freeze_set(phb->opal_id, 48649dec922SGavin Shan slave->pe_number, 48749dec922SGavin Shan OPAL_EEH_ACTION_SET_FREEZE_ALL); 48849dec922SGavin Shan if (rc != OPAL_SUCCESS) 48949dec922SGavin Shan pr_warn("%s: Failure %lld freezing PHB#%x-PE#%x\n", 49049dec922SGavin Shan __func__, rc, phb->hose->global_number, 49149dec922SGavin Shan slave->pe_number); 49249dec922SGavin Shan } 49349dec922SGavin Shan } 49449dec922SGavin Shan 495e51df2c1SAnton Blanchard static int pnv_ioda_unfreeze_pe(struct pnv_phb *phb, int pe_no, int opt) 49649dec922SGavin Shan { 49749dec922SGavin Shan struct pnv_ioda_pe *pe, *slave; 49849dec922SGavin Shan s64 rc; 49949dec922SGavin Shan 50049dec922SGavin Shan /* Find master PE */ 50149dec922SGavin Shan pe = &phb->ioda.pe_array[pe_no]; 50249dec922SGavin Shan if (pe->flags & PNV_IODA_PE_SLAVE) { 50349dec922SGavin Shan pe = pe->master; 50449dec922SGavin Shan WARN_ON(!pe || !(pe->flags & PNV_IODA_PE_MASTER)); 50549dec922SGavin Shan pe_no = pe->pe_number; 50649dec922SGavin Shan } 50749dec922SGavin Shan 50849dec922SGavin Shan /* Clear frozen state for master PE */ 50949dec922SGavin Shan rc = opal_pci_eeh_freeze_clear(phb->opal_id, pe_no, opt); 51049dec922SGavin Shan if (rc != OPAL_SUCCESS) { 51149dec922SGavin Shan pr_warn("%s: Failure %lld clear %d on PHB#%x-PE#%x\n", 51249dec922SGavin Shan __func__, rc, opt, phb->hose->global_number, pe_no); 51349dec922SGavin Shan return -EIO; 51449dec922SGavin Shan } 51549dec922SGavin Shan 51649dec922SGavin Shan if (!(pe->flags & PNV_IODA_PE_MASTER)) 51749dec922SGavin Shan return 0; 51849dec922SGavin Shan 51949dec922SGavin Shan /* Clear frozen state for slave PEs */ 52049dec922SGavin Shan list_for_each_entry(slave, &pe->slaves, list) { 52149dec922SGavin Shan rc = opal_pci_eeh_freeze_clear(phb->opal_id, 52249dec922SGavin Shan slave->pe_number, 52349dec922SGavin Shan opt); 52449dec922SGavin Shan if (rc != OPAL_SUCCESS) { 52549dec922SGavin Shan pr_warn("%s: Failure %lld clear %d on PHB#%x-PE#%x\n", 52649dec922SGavin Shan __func__, rc, opt, phb->hose->global_number, 52749dec922SGavin Shan slave->pe_number); 52849dec922SGavin Shan return -EIO; 52949dec922SGavin Shan } 53049dec922SGavin Shan } 53149dec922SGavin Shan 53249dec922SGavin Shan return 0; 53349dec922SGavin Shan } 53449dec922SGavin Shan 53549dec922SGavin Shan static int pnv_ioda_get_pe_state(struct pnv_phb *phb, int pe_no) 53649dec922SGavin Shan { 53749dec922SGavin Shan struct pnv_ioda_pe *slave, *pe; 53849dec922SGavin Shan u8 fstate, state; 53949dec922SGavin Shan __be16 pcierr; 54049dec922SGavin Shan s64 rc; 54149dec922SGavin Shan 54249dec922SGavin Shan /* Sanity check on PE number */ 54392b8f137SGavin Shan if (pe_no < 0 || pe_no >= phb->ioda.total_pe_num) 54449dec922SGavin Shan return OPAL_EEH_STOPPED_PERM_UNAVAIL; 54549dec922SGavin Shan 54649dec922SGavin Shan /* 54749dec922SGavin Shan * Fetch the master PE and the PE instance might be 54849dec922SGavin Shan * not initialized yet. 54949dec922SGavin Shan */ 55049dec922SGavin Shan pe = &phb->ioda.pe_array[pe_no]; 55149dec922SGavin Shan if (pe->flags & PNV_IODA_PE_SLAVE) { 55249dec922SGavin Shan pe = pe->master; 55349dec922SGavin Shan WARN_ON(!pe || !(pe->flags & PNV_IODA_PE_MASTER)); 55449dec922SGavin Shan pe_no = pe->pe_number; 55549dec922SGavin Shan } 55649dec922SGavin Shan 55749dec922SGavin Shan /* Check the master PE */ 55849dec922SGavin Shan rc = opal_pci_eeh_freeze_status(phb->opal_id, pe_no, 55949dec922SGavin Shan &state, &pcierr, NULL); 56049dec922SGavin Shan if (rc != OPAL_SUCCESS) { 56149dec922SGavin Shan pr_warn("%s: Failure %lld getting " 56249dec922SGavin Shan "PHB#%x-PE#%x state\n", 56349dec922SGavin Shan __func__, rc, 56449dec922SGavin Shan phb->hose->global_number, pe_no); 56549dec922SGavin Shan return OPAL_EEH_STOPPED_TEMP_UNAVAIL; 56649dec922SGavin Shan } 56749dec922SGavin Shan 56849dec922SGavin Shan /* Check the slave PE */ 56949dec922SGavin Shan if (!(pe->flags & PNV_IODA_PE_MASTER)) 57049dec922SGavin Shan return state; 57149dec922SGavin Shan 57249dec922SGavin Shan list_for_each_entry(slave, &pe->slaves, list) { 57349dec922SGavin Shan rc = opal_pci_eeh_freeze_status(phb->opal_id, 57449dec922SGavin Shan slave->pe_number, 57549dec922SGavin Shan &fstate, 57649dec922SGavin Shan &pcierr, 57749dec922SGavin Shan NULL); 57849dec922SGavin Shan if (rc != OPAL_SUCCESS) { 57949dec922SGavin Shan pr_warn("%s: Failure %lld getting " 58049dec922SGavin Shan "PHB#%x-PE#%x state\n", 58149dec922SGavin Shan __func__, rc, 58249dec922SGavin Shan phb->hose->global_number, slave->pe_number); 58349dec922SGavin Shan return OPAL_EEH_STOPPED_TEMP_UNAVAIL; 58449dec922SGavin Shan } 58549dec922SGavin Shan 58649dec922SGavin Shan /* 58749dec922SGavin Shan * Override the result based on the ascending 58849dec922SGavin Shan * priority. 58949dec922SGavin Shan */ 59049dec922SGavin Shan if (fstate > state) 59149dec922SGavin Shan state = fstate; 59249dec922SGavin Shan } 59349dec922SGavin Shan 59449dec922SGavin Shan return state; 59549dec922SGavin Shan } 59649dec922SGavin Shan 597184cd4a3SBenjamin Herrenschmidt /* Currently those 2 are only used when MSIs are enabled, this will change 598184cd4a3SBenjamin Herrenschmidt * but in the meantime, we need to protect them to avoid warnings 599184cd4a3SBenjamin Herrenschmidt */ 600184cd4a3SBenjamin Herrenschmidt #ifdef CONFIG_PCI_MSI 601cad5cef6SGreg Kroah-Hartman static struct pnv_ioda_pe *pnv_ioda_get_pe(struct pci_dev *dev) 602184cd4a3SBenjamin Herrenschmidt { 603184cd4a3SBenjamin Herrenschmidt struct pci_controller *hose = pci_bus_to_host(dev->bus); 604184cd4a3SBenjamin Herrenschmidt struct pnv_phb *phb = hose->private_data; 605b72c1f65SBenjamin Herrenschmidt struct pci_dn *pdn = pci_get_pdn(dev); 606184cd4a3SBenjamin Herrenschmidt 607184cd4a3SBenjamin Herrenschmidt if (!pdn) 608184cd4a3SBenjamin Herrenschmidt return NULL; 609184cd4a3SBenjamin Herrenschmidt if (pdn->pe_number == IODA_INVALID_PE) 610184cd4a3SBenjamin Herrenschmidt return NULL; 611184cd4a3SBenjamin Herrenschmidt return &phb->ioda.pe_array[pdn->pe_number]; 612184cd4a3SBenjamin Herrenschmidt } 613184cd4a3SBenjamin Herrenschmidt #endif /* CONFIG_PCI_MSI */ 614184cd4a3SBenjamin Herrenschmidt 615b131a842SGavin Shan static int pnv_ioda_set_one_peltv(struct pnv_phb *phb, 616b131a842SGavin Shan struct pnv_ioda_pe *parent, 617b131a842SGavin Shan struct pnv_ioda_pe *child, 618b131a842SGavin Shan bool is_add) 619b131a842SGavin Shan { 620b131a842SGavin Shan const char *desc = is_add ? "adding" : "removing"; 621b131a842SGavin Shan uint8_t op = is_add ? OPAL_ADD_PE_TO_DOMAIN : 622b131a842SGavin Shan OPAL_REMOVE_PE_FROM_DOMAIN; 623b131a842SGavin Shan struct pnv_ioda_pe *slave; 624b131a842SGavin Shan long rc; 625b131a842SGavin Shan 626b131a842SGavin Shan /* Parent PE affects child PE */ 627b131a842SGavin Shan rc = opal_pci_set_peltv(phb->opal_id, parent->pe_number, 628b131a842SGavin Shan child->pe_number, op); 629b131a842SGavin Shan if (rc != OPAL_SUCCESS) { 630b131a842SGavin Shan pe_warn(child, "OPAL error %ld %s to parent PELTV\n", 631b131a842SGavin Shan rc, desc); 632b131a842SGavin Shan return -ENXIO; 633b131a842SGavin Shan } 634b131a842SGavin Shan 635b131a842SGavin Shan if (!(child->flags & PNV_IODA_PE_MASTER)) 636b131a842SGavin Shan return 0; 637b131a842SGavin Shan 638b131a842SGavin Shan /* Compound case: parent PE affects slave PEs */ 639b131a842SGavin Shan list_for_each_entry(slave, &child->slaves, list) { 640b131a842SGavin Shan rc = opal_pci_set_peltv(phb->opal_id, parent->pe_number, 641b131a842SGavin Shan slave->pe_number, op); 642b131a842SGavin Shan if (rc != OPAL_SUCCESS) { 643b131a842SGavin Shan pe_warn(slave, "OPAL error %ld %s to parent PELTV\n", 644b131a842SGavin Shan rc, desc); 645b131a842SGavin Shan return -ENXIO; 646b131a842SGavin Shan } 647b131a842SGavin Shan } 648b131a842SGavin Shan 649b131a842SGavin Shan return 0; 650b131a842SGavin Shan } 651b131a842SGavin Shan 652b131a842SGavin Shan static int pnv_ioda_set_peltv(struct pnv_phb *phb, 653b131a842SGavin Shan struct pnv_ioda_pe *pe, 654b131a842SGavin Shan bool is_add) 655b131a842SGavin Shan { 656b131a842SGavin Shan struct pnv_ioda_pe *slave; 657781a868fSWei Yang struct pci_dev *pdev = NULL; 658b131a842SGavin Shan int ret; 659b131a842SGavin Shan 660b131a842SGavin Shan /* 661b131a842SGavin Shan * Clear PE frozen state. If it's master PE, we need 662b131a842SGavin Shan * clear slave PE frozen state as well. 663b131a842SGavin Shan */ 664b131a842SGavin Shan if (is_add) { 665b131a842SGavin Shan opal_pci_eeh_freeze_clear(phb->opal_id, pe->pe_number, 666b131a842SGavin Shan OPAL_EEH_ACTION_CLEAR_FREEZE_ALL); 667b131a842SGavin Shan if (pe->flags & PNV_IODA_PE_MASTER) { 668b131a842SGavin Shan list_for_each_entry(slave, &pe->slaves, list) 669b131a842SGavin Shan opal_pci_eeh_freeze_clear(phb->opal_id, 670b131a842SGavin Shan slave->pe_number, 671b131a842SGavin Shan OPAL_EEH_ACTION_CLEAR_FREEZE_ALL); 672b131a842SGavin Shan } 673b131a842SGavin Shan } 674b131a842SGavin Shan 675b131a842SGavin Shan /* 676b131a842SGavin Shan * Associate PE in PELT. We need add the PE into the 677b131a842SGavin Shan * corresponding PELT-V as well. Otherwise, the error 678b131a842SGavin Shan * originated from the PE might contribute to other 679b131a842SGavin Shan * PEs. 680b131a842SGavin Shan */ 681b131a842SGavin Shan ret = pnv_ioda_set_one_peltv(phb, pe, pe, is_add); 682b131a842SGavin Shan if (ret) 683b131a842SGavin Shan return ret; 684b131a842SGavin Shan 685b131a842SGavin Shan /* For compound PEs, any one affects all of them */ 686b131a842SGavin Shan if (pe->flags & PNV_IODA_PE_MASTER) { 687b131a842SGavin Shan list_for_each_entry(slave, &pe->slaves, list) { 688b131a842SGavin Shan ret = pnv_ioda_set_one_peltv(phb, slave, pe, is_add); 689b131a842SGavin Shan if (ret) 690b131a842SGavin Shan return ret; 691b131a842SGavin Shan } 692b131a842SGavin Shan } 693b131a842SGavin Shan 694b131a842SGavin Shan if (pe->flags & (PNV_IODA_PE_BUS_ALL | PNV_IODA_PE_BUS)) 695b131a842SGavin Shan pdev = pe->pbus->self; 696781a868fSWei Yang else if (pe->flags & PNV_IODA_PE_DEV) 697b131a842SGavin Shan pdev = pe->pdev->bus->self; 698781a868fSWei Yang #ifdef CONFIG_PCI_IOV 699781a868fSWei Yang else if (pe->flags & PNV_IODA_PE_VF) 700283e2d8aSGavin Shan pdev = pe->parent_dev; 701781a868fSWei Yang #endif /* CONFIG_PCI_IOV */ 702b131a842SGavin Shan while (pdev) { 703b131a842SGavin Shan struct pci_dn *pdn = pci_get_pdn(pdev); 704b131a842SGavin Shan struct pnv_ioda_pe *parent; 705b131a842SGavin Shan 706b131a842SGavin Shan if (pdn && pdn->pe_number != IODA_INVALID_PE) { 707b131a842SGavin Shan parent = &phb->ioda.pe_array[pdn->pe_number]; 708b131a842SGavin Shan ret = pnv_ioda_set_one_peltv(phb, parent, pe, is_add); 709b131a842SGavin Shan if (ret) 710b131a842SGavin Shan return ret; 711b131a842SGavin Shan } 712b131a842SGavin Shan 713b131a842SGavin Shan pdev = pdev->bus->self; 714b131a842SGavin Shan } 715b131a842SGavin Shan 716b131a842SGavin Shan return 0; 717b131a842SGavin Shan } 718b131a842SGavin Shan 719781a868fSWei Yang #ifdef CONFIG_PCI_IOV 720781a868fSWei Yang static int pnv_ioda_deconfigure_pe(struct pnv_phb *phb, struct pnv_ioda_pe *pe) 721781a868fSWei Yang { 722781a868fSWei Yang struct pci_dev *parent; 723781a868fSWei Yang uint8_t bcomp, dcomp, fcomp; 724781a868fSWei Yang int64_t rc; 725781a868fSWei Yang long rid_end, rid; 726781a868fSWei Yang 727781a868fSWei Yang /* Currently, we just deconfigure VF PE. Bus PE will always there.*/ 728781a868fSWei Yang if (pe->pbus) { 729781a868fSWei Yang int count; 730781a868fSWei Yang 731781a868fSWei Yang dcomp = OPAL_IGNORE_RID_DEVICE_NUMBER; 732781a868fSWei Yang fcomp = OPAL_IGNORE_RID_FUNCTION_NUMBER; 733781a868fSWei Yang parent = pe->pbus->self; 734781a868fSWei Yang if (pe->flags & PNV_IODA_PE_BUS_ALL) 735781a868fSWei Yang count = pe->pbus->busn_res.end - pe->pbus->busn_res.start + 1; 736781a868fSWei Yang else 737781a868fSWei Yang count = 1; 738781a868fSWei Yang 739781a868fSWei Yang switch(count) { 740781a868fSWei Yang case 1: bcomp = OpalPciBusAll; break; 741781a868fSWei Yang case 2: bcomp = OpalPciBus7Bits; break; 742781a868fSWei Yang case 4: bcomp = OpalPciBus6Bits; break; 743781a868fSWei Yang case 8: bcomp = OpalPciBus5Bits; break; 744781a868fSWei Yang case 16: bcomp = OpalPciBus4Bits; break; 745781a868fSWei Yang case 32: bcomp = OpalPciBus3Bits; break; 746781a868fSWei Yang default: 747781a868fSWei Yang dev_err(&pe->pbus->dev, "Number of subordinate buses %d unsupported\n", 748781a868fSWei Yang count); 749781a868fSWei Yang /* Do an exact match only */ 750781a868fSWei Yang bcomp = OpalPciBusAll; 751781a868fSWei Yang } 752781a868fSWei Yang rid_end = pe->rid + (count << 8); 753781a868fSWei Yang } else { 754781a868fSWei Yang if (pe->flags & PNV_IODA_PE_VF) 755781a868fSWei Yang parent = pe->parent_dev; 756781a868fSWei Yang else 757781a868fSWei Yang parent = pe->pdev->bus->self; 758781a868fSWei Yang bcomp = OpalPciBusAll; 759781a868fSWei Yang dcomp = OPAL_COMPARE_RID_DEVICE_NUMBER; 760781a868fSWei Yang fcomp = OPAL_COMPARE_RID_FUNCTION_NUMBER; 761781a868fSWei Yang rid_end = pe->rid + 1; 762781a868fSWei Yang } 763781a868fSWei Yang 764781a868fSWei Yang /* Clear the reverse map */ 765781a868fSWei Yang for (rid = pe->rid; rid < rid_end; rid++) 766781a868fSWei Yang phb->ioda.pe_rmap[rid] = 0; 767781a868fSWei Yang 768781a868fSWei Yang /* Release from all parents PELT-V */ 769781a868fSWei Yang while (parent) { 770781a868fSWei Yang struct pci_dn *pdn = pci_get_pdn(parent); 771781a868fSWei Yang if (pdn && pdn->pe_number != IODA_INVALID_PE) { 772781a868fSWei Yang rc = opal_pci_set_peltv(phb->opal_id, pdn->pe_number, 773781a868fSWei Yang pe->pe_number, OPAL_REMOVE_PE_FROM_DOMAIN); 774781a868fSWei Yang /* XXX What to do in case of error ? */ 775781a868fSWei Yang } 776781a868fSWei Yang parent = parent->bus->self; 777781a868fSWei Yang } 778781a868fSWei Yang 779f951e510SGavin Shan opal_pci_eeh_freeze_clear(phb->opal_id, pe->pe_number, 780781a868fSWei Yang OPAL_EEH_ACTION_CLEAR_FREEZE_ALL); 781781a868fSWei Yang 782781a868fSWei Yang /* Disassociate PE in PELT */ 783781a868fSWei Yang rc = opal_pci_set_peltv(phb->opal_id, pe->pe_number, 784781a868fSWei Yang pe->pe_number, OPAL_REMOVE_PE_FROM_DOMAIN); 785781a868fSWei Yang if (rc) 786781a868fSWei Yang pe_warn(pe, "OPAL error %ld remove self from PELTV\n", rc); 787781a868fSWei Yang rc = opal_pci_set_pe(phb->opal_id, pe->pe_number, pe->rid, 788781a868fSWei Yang bcomp, dcomp, fcomp, OPAL_UNMAP_PE); 789781a868fSWei Yang if (rc) 790781a868fSWei Yang pe_err(pe, "OPAL error %ld trying to setup PELT table\n", rc); 791781a868fSWei Yang 792781a868fSWei Yang pe->pbus = NULL; 793781a868fSWei Yang pe->pdev = NULL; 794781a868fSWei Yang pe->parent_dev = NULL; 795781a868fSWei Yang 796781a868fSWei Yang return 0; 797781a868fSWei Yang } 798781a868fSWei Yang #endif /* CONFIG_PCI_IOV */ 799781a868fSWei Yang 800cad5cef6SGreg Kroah-Hartman static int pnv_ioda_configure_pe(struct pnv_phb *phb, struct pnv_ioda_pe *pe) 801184cd4a3SBenjamin Herrenschmidt { 802184cd4a3SBenjamin Herrenschmidt struct pci_dev *parent; 803184cd4a3SBenjamin Herrenschmidt uint8_t bcomp, dcomp, fcomp; 804184cd4a3SBenjamin Herrenschmidt long rc, rid_end, rid; 805184cd4a3SBenjamin Herrenschmidt 806184cd4a3SBenjamin Herrenschmidt /* Bus validation ? */ 807184cd4a3SBenjamin Herrenschmidt if (pe->pbus) { 808184cd4a3SBenjamin Herrenschmidt int count; 809184cd4a3SBenjamin Herrenschmidt 810184cd4a3SBenjamin Herrenschmidt dcomp = OPAL_IGNORE_RID_DEVICE_NUMBER; 811184cd4a3SBenjamin Herrenschmidt fcomp = OPAL_IGNORE_RID_FUNCTION_NUMBER; 812184cd4a3SBenjamin Herrenschmidt parent = pe->pbus->self; 813fb446ad0SGavin Shan if (pe->flags & PNV_IODA_PE_BUS_ALL) 814b918c62eSYinghai Lu count = pe->pbus->busn_res.end - pe->pbus->busn_res.start + 1; 815fb446ad0SGavin Shan else 816fb446ad0SGavin Shan count = 1; 817fb446ad0SGavin Shan 818184cd4a3SBenjamin Herrenschmidt switch(count) { 819184cd4a3SBenjamin Herrenschmidt case 1: bcomp = OpalPciBusAll; break; 820184cd4a3SBenjamin Herrenschmidt case 2: bcomp = OpalPciBus7Bits; break; 821184cd4a3SBenjamin Herrenschmidt case 4: bcomp = OpalPciBus6Bits; break; 822184cd4a3SBenjamin Herrenschmidt case 8: bcomp = OpalPciBus5Bits; break; 823184cd4a3SBenjamin Herrenschmidt case 16: bcomp = OpalPciBus4Bits; break; 824184cd4a3SBenjamin Herrenschmidt case 32: bcomp = OpalPciBus3Bits; break; 825184cd4a3SBenjamin Herrenschmidt default: 826781a868fSWei Yang dev_err(&pe->pbus->dev, "Number of subordinate buses %d unsupported\n", 827781a868fSWei Yang count); 828184cd4a3SBenjamin Herrenschmidt /* Do an exact match only */ 829184cd4a3SBenjamin Herrenschmidt bcomp = OpalPciBusAll; 830184cd4a3SBenjamin Herrenschmidt } 831184cd4a3SBenjamin Herrenschmidt rid_end = pe->rid + (count << 8); 832184cd4a3SBenjamin Herrenschmidt } else { 833781a868fSWei Yang #ifdef CONFIG_PCI_IOV 834781a868fSWei Yang if (pe->flags & PNV_IODA_PE_VF) 835781a868fSWei Yang parent = pe->parent_dev; 836781a868fSWei Yang else 837781a868fSWei Yang #endif /* CONFIG_PCI_IOV */ 838184cd4a3SBenjamin Herrenschmidt parent = pe->pdev->bus->self; 839184cd4a3SBenjamin Herrenschmidt bcomp = OpalPciBusAll; 840184cd4a3SBenjamin Herrenschmidt dcomp = OPAL_COMPARE_RID_DEVICE_NUMBER; 841184cd4a3SBenjamin Herrenschmidt fcomp = OPAL_COMPARE_RID_FUNCTION_NUMBER; 842184cd4a3SBenjamin Herrenschmidt rid_end = pe->rid + 1; 843184cd4a3SBenjamin Herrenschmidt } 844184cd4a3SBenjamin Herrenschmidt 845631ad691SGavin Shan /* 846631ad691SGavin Shan * Associate PE in PELT. We need add the PE into the 847631ad691SGavin Shan * corresponding PELT-V as well. Otherwise, the error 848631ad691SGavin Shan * originated from the PE might contribute to other 849631ad691SGavin Shan * PEs. 850631ad691SGavin Shan */ 851184cd4a3SBenjamin Herrenschmidt rc = opal_pci_set_pe(phb->opal_id, pe->pe_number, pe->rid, 852184cd4a3SBenjamin Herrenschmidt bcomp, dcomp, fcomp, OPAL_MAP_PE); 853184cd4a3SBenjamin Herrenschmidt if (rc) { 854184cd4a3SBenjamin Herrenschmidt pe_err(pe, "OPAL error %ld trying to setup PELT table\n", rc); 855184cd4a3SBenjamin Herrenschmidt return -ENXIO; 856184cd4a3SBenjamin Herrenschmidt } 857631ad691SGavin Shan 8585d2aa710SAlistair Popple /* 8595d2aa710SAlistair Popple * Configure PELTV. NPUs don't have a PELTV table so skip 8605d2aa710SAlistair Popple * configuration on them. 8615d2aa710SAlistair Popple */ 8625d2aa710SAlistair Popple if (phb->type != PNV_PHB_NPU) 863b131a842SGavin Shan pnv_ioda_set_peltv(phb, pe, true); 864184cd4a3SBenjamin Herrenschmidt 865184cd4a3SBenjamin Herrenschmidt /* Setup reverse map */ 866184cd4a3SBenjamin Herrenschmidt for (rid = pe->rid; rid < rid_end; rid++) 867184cd4a3SBenjamin Herrenschmidt phb->ioda.pe_rmap[rid] = pe->pe_number; 868184cd4a3SBenjamin Herrenschmidt 869184cd4a3SBenjamin Herrenschmidt /* Setup one MVTs on IODA1 */ 8704773f76bSGavin Shan if (phb->type != PNV_PHB_IODA1) { 8714773f76bSGavin Shan pe->mve_number = 0; 8724773f76bSGavin Shan goto out; 8734773f76bSGavin Shan } 8744773f76bSGavin Shan 875184cd4a3SBenjamin Herrenschmidt pe->mve_number = pe->pe_number; 8764773f76bSGavin Shan rc = opal_pci_set_mve(phb->opal_id, pe->mve_number, pe->pe_number); 8774773f76bSGavin Shan if (rc != OPAL_SUCCESS) { 878184cd4a3SBenjamin Herrenschmidt pe_err(pe, "OPAL error %ld setting up MVE %d\n", 879184cd4a3SBenjamin Herrenschmidt rc, pe->mve_number); 880184cd4a3SBenjamin Herrenschmidt pe->mve_number = -1; 881184cd4a3SBenjamin Herrenschmidt } else { 882184cd4a3SBenjamin Herrenschmidt rc = opal_pci_set_mve_enable(phb->opal_id, 883cee72d5bSBenjamin Herrenschmidt pe->mve_number, OPAL_ENABLE_MVE); 884184cd4a3SBenjamin Herrenschmidt if (rc) { 885184cd4a3SBenjamin Herrenschmidt pe_err(pe, "OPAL error %ld enabling MVE %d\n", 886184cd4a3SBenjamin Herrenschmidt rc, pe->mve_number); 887184cd4a3SBenjamin Herrenschmidt pe->mve_number = -1; 888184cd4a3SBenjamin Herrenschmidt } 889184cd4a3SBenjamin Herrenschmidt } 890184cd4a3SBenjamin Herrenschmidt 8914773f76bSGavin Shan out: 892184cd4a3SBenjamin Herrenschmidt return 0; 893184cd4a3SBenjamin Herrenschmidt } 894184cd4a3SBenjamin Herrenschmidt 895cad5cef6SGreg Kroah-Hartman static void pnv_ioda_link_pe_by_weight(struct pnv_phb *phb, 896184cd4a3SBenjamin Herrenschmidt struct pnv_ioda_pe *pe) 897184cd4a3SBenjamin Herrenschmidt { 898184cd4a3SBenjamin Herrenschmidt struct pnv_ioda_pe *lpe; 899184cd4a3SBenjamin Herrenschmidt 9007ebdf956SGavin Shan list_for_each_entry(lpe, &phb->ioda.pe_dma_list, dma_link) { 901184cd4a3SBenjamin Herrenschmidt if (lpe->dma_weight < pe->dma_weight) { 9027ebdf956SGavin Shan list_add_tail(&pe->dma_link, &lpe->dma_link); 903184cd4a3SBenjamin Herrenschmidt return; 904184cd4a3SBenjamin Herrenschmidt } 905184cd4a3SBenjamin Herrenschmidt } 9067ebdf956SGavin Shan list_add_tail(&pe->dma_link, &phb->ioda.pe_dma_list); 907184cd4a3SBenjamin Herrenschmidt } 908184cd4a3SBenjamin Herrenschmidt 909184cd4a3SBenjamin Herrenschmidt static unsigned int pnv_ioda_dma_weight(struct pci_dev *dev) 910184cd4a3SBenjamin Herrenschmidt { 911184cd4a3SBenjamin Herrenschmidt /* This is quite simplistic. The "base" weight of a device 912184cd4a3SBenjamin Herrenschmidt * is 10. 0 means no DMA is to be accounted for it. 913184cd4a3SBenjamin Herrenschmidt */ 914184cd4a3SBenjamin Herrenschmidt 915184cd4a3SBenjamin Herrenschmidt /* If it's a bridge, no DMA */ 916184cd4a3SBenjamin Herrenschmidt if (dev->hdr_type != PCI_HEADER_TYPE_NORMAL) 917184cd4a3SBenjamin Herrenschmidt return 0; 918184cd4a3SBenjamin Herrenschmidt 919184cd4a3SBenjamin Herrenschmidt /* Reduce the weight of slow USB controllers */ 920184cd4a3SBenjamin Herrenschmidt if (dev->class == PCI_CLASS_SERIAL_USB_UHCI || 921184cd4a3SBenjamin Herrenschmidt dev->class == PCI_CLASS_SERIAL_USB_OHCI || 922184cd4a3SBenjamin Herrenschmidt dev->class == PCI_CLASS_SERIAL_USB_EHCI) 923184cd4a3SBenjamin Herrenschmidt return 3; 924184cd4a3SBenjamin Herrenschmidt 925184cd4a3SBenjamin Herrenschmidt /* Increase the weight of RAID (includes Obsidian) */ 926184cd4a3SBenjamin Herrenschmidt if ((dev->class >> 8) == PCI_CLASS_STORAGE_RAID) 927184cd4a3SBenjamin Herrenschmidt return 15; 928184cd4a3SBenjamin Herrenschmidt 929184cd4a3SBenjamin Herrenschmidt /* Default */ 930184cd4a3SBenjamin Herrenschmidt return 10; 931184cd4a3SBenjamin Herrenschmidt } 932184cd4a3SBenjamin Herrenschmidt 933781a868fSWei Yang #ifdef CONFIG_PCI_IOV 934781a868fSWei Yang static int pnv_pci_vf_resource_shift(struct pci_dev *dev, int offset) 935781a868fSWei Yang { 936781a868fSWei Yang struct pci_dn *pdn = pci_get_pdn(dev); 937781a868fSWei Yang int i; 938781a868fSWei Yang struct resource *res, res2; 939781a868fSWei Yang resource_size_t size; 940781a868fSWei Yang u16 num_vfs; 941781a868fSWei Yang 942781a868fSWei Yang if (!dev->is_physfn) 943781a868fSWei Yang return -EINVAL; 944781a868fSWei Yang 945781a868fSWei Yang /* 946781a868fSWei Yang * "offset" is in VFs. The M64 windows are sized so that when they 947781a868fSWei Yang * are segmented, each segment is the same size as the IOV BAR. 948781a868fSWei Yang * Each segment is in a separate PE, and the high order bits of the 949781a868fSWei Yang * address are the PE number. Therefore, each VF's BAR is in a 950781a868fSWei Yang * separate PE, and changing the IOV BAR start address changes the 951781a868fSWei Yang * range of PEs the VFs are in. 952781a868fSWei Yang */ 953781a868fSWei Yang num_vfs = pdn->num_vfs; 954781a868fSWei Yang for (i = 0; i < PCI_SRIOV_NUM_BARS; i++) { 955781a868fSWei Yang res = &dev->resource[i + PCI_IOV_RESOURCES]; 956781a868fSWei Yang if (!res->flags || !res->parent) 957781a868fSWei Yang continue; 958781a868fSWei Yang 959781a868fSWei Yang /* 960781a868fSWei Yang * The actual IOV BAR range is determined by the start address 961781a868fSWei Yang * and the actual size for num_vfs VFs BAR. This check is to 962781a868fSWei Yang * make sure that after shifting, the range will not overlap 963781a868fSWei Yang * with another device. 964781a868fSWei Yang */ 965781a868fSWei Yang size = pci_iov_resource_size(dev, i + PCI_IOV_RESOURCES); 966781a868fSWei Yang res2.flags = res->flags; 967781a868fSWei Yang res2.start = res->start + (size * offset); 968781a868fSWei Yang res2.end = res2.start + (size * num_vfs) - 1; 969781a868fSWei Yang 970781a868fSWei Yang if (res2.end > res->end) { 971781a868fSWei Yang dev_err(&dev->dev, "VF BAR%d: %pR would extend past %pR (trying to enable %d VFs shifted by %d)\n", 972781a868fSWei Yang i, &res2, res, num_vfs, offset); 973781a868fSWei Yang return -EBUSY; 974781a868fSWei Yang } 975781a868fSWei Yang } 976781a868fSWei Yang 977781a868fSWei Yang /* 978781a868fSWei Yang * After doing so, there would be a "hole" in the /proc/iomem when 979781a868fSWei Yang * offset is a positive value. It looks like the device return some 980781a868fSWei Yang * mmio back to the system, which actually no one could use it. 981781a868fSWei Yang */ 982781a868fSWei Yang for (i = 0; i < PCI_SRIOV_NUM_BARS; i++) { 983781a868fSWei Yang res = &dev->resource[i + PCI_IOV_RESOURCES]; 984781a868fSWei Yang if (!res->flags || !res->parent) 985781a868fSWei Yang continue; 986781a868fSWei Yang 987781a868fSWei Yang size = pci_iov_resource_size(dev, i + PCI_IOV_RESOURCES); 988781a868fSWei Yang res2 = *res; 989781a868fSWei Yang res->start += size * offset; 990781a868fSWei Yang 99174703cc4SWei Yang dev_info(&dev->dev, "VF BAR%d: %pR shifted to %pR (%sabling %d VFs shifted by %d)\n", 99274703cc4SWei Yang i, &res2, res, (offset > 0) ? "En" : "Dis", 99374703cc4SWei Yang num_vfs, offset); 994781a868fSWei Yang pci_update_resource(dev, i + PCI_IOV_RESOURCES); 995781a868fSWei Yang } 996781a868fSWei Yang return 0; 997781a868fSWei Yang } 998781a868fSWei Yang #endif /* CONFIG_PCI_IOV */ 999781a868fSWei Yang 1000cad5cef6SGreg Kroah-Hartman static struct pnv_ioda_pe *pnv_ioda_setup_dev_PE(struct pci_dev *dev) 1001184cd4a3SBenjamin Herrenschmidt { 1002184cd4a3SBenjamin Herrenschmidt struct pci_controller *hose = pci_bus_to_host(dev->bus); 1003184cd4a3SBenjamin Herrenschmidt struct pnv_phb *phb = hose->private_data; 1004b72c1f65SBenjamin Herrenschmidt struct pci_dn *pdn = pci_get_pdn(dev); 1005184cd4a3SBenjamin Herrenschmidt struct pnv_ioda_pe *pe; 1006689ee8c9SGavin Shan unsigned int pe_num; 1007184cd4a3SBenjamin Herrenschmidt 1008184cd4a3SBenjamin Herrenschmidt if (!pdn) { 1009184cd4a3SBenjamin Herrenschmidt pr_err("%s: Device tree node not associated properly\n", 1010184cd4a3SBenjamin Herrenschmidt pci_name(dev)); 1011184cd4a3SBenjamin Herrenschmidt return NULL; 1012184cd4a3SBenjamin Herrenschmidt } 1013184cd4a3SBenjamin Herrenschmidt if (pdn->pe_number != IODA_INVALID_PE) 1014184cd4a3SBenjamin Herrenschmidt return NULL; 1015184cd4a3SBenjamin Herrenschmidt 1016184cd4a3SBenjamin Herrenschmidt pe_num = pnv_ioda_alloc_pe(phb); 1017184cd4a3SBenjamin Herrenschmidt if (pe_num == IODA_INVALID_PE) { 1018184cd4a3SBenjamin Herrenschmidt pr_warning("%s: Not enough PE# available, disabling device\n", 1019184cd4a3SBenjamin Herrenschmidt pci_name(dev)); 1020184cd4a3SBenjamin Herrenschmidt return NULL; 1021184cd4a3SBenjamin Herrenschmidt } 1022184cd4a3SBenjamin Herrenschmidt 1023184cd4a3SBenjamin Herrenschmidt /* NOTE: We get only one ref to the pci_dev for the pdn, not for the 1024184cd4a3SBenjamin Herrenschmidt * pointer in the PE data structure, both should be destroyed at the 1025184cd4a3SBenjamin Herrenschmidt * same time. However, this needs to be looked at more closely again 1026184cd4a3SBenjamin Herrenschmidt * once we actually start removing things (Hotplug, SR-IOV, ...) 1027184cd4a3SBenjamin Herrenschmidt * 1028184cd4a3SBenjamin Herrenschmidt * At some point we want to remove the PDN completely anyways 1029184cd4a3SBenjamin Herrenschmidt */ 1030184cd4a3SBenjamin Herrenschmidt pe = &phb->ioda.pe_array[pe_num]; 1031184cd4a3SBenjamin Herrenschmidt pci_dev_get(dev); 1032184cd4a3SBenjamin Herrenschmidt pdn->pcidev = dev; 1033184cd4a3SBenjamin Herrenschmidt pdn->pe_number = pe_num; 10345d2aa710SAlistair Popple pe->flags = PNV_IODA_PE_DEV; 1035184cd4a3SBenjamin Herrenschmidt pe->pdev = dev; 1036184cd4a3SBenjamin Herrenschmidt pe->pbus = NULL; 1037184cd4a3SBenjamin Herrenschmidt pe->tce32_seg = -1; 1038184cd4a3SBenjamin Herrenschmidt pe->mve_number = -1; 1039184cd4a3SBenjamin Herrenschmidt pe->rid = dev->bus->number << 8 | pdn->devfn; 1040184cd4a3SBenjamin Herrenschmidt 1041184cd4a3SBenjamin Herrenschmidt pe_info(pe, "Associated device to PE\n"); 1042184cd4a3SBenjamin Herrenschmidt 1043184cd4a3SBenjamin Herrenschmidt if (pnv_ioda_configure_pe(phb, pe)) { 1044184cd4a3SBenjamin Herrenschmidt /* XXX What do we do here ? */ 1045184cd4a3SBenjamin Herrenschmidt if (pe_num) 1046184cd4a3SBenjamin Herrenschmidt pnv_ioda_free_pe(phb, pe_num); 1047184cd4a3SBenjamin Herrenschmidt pdn->pe_number = IODA_INVALID_PE; 1048184cd4a3SBenjamin Herrenschmidt pe->pdev = NULL; 1049184cd4a3SBenjamin Herrenschmidt pci_dev_put(dev); 1050184cd4a3SBenjamin Herrenschmidt return NULL; 1051184cd4a3SBenjamin Herrenschmidt } 1052184cd4a3SBenjamin Herrenschmidt 1053184cd4a3SBenjamin Herrenschmidt /* Assign a DMA weight to the device */ 1054184cd4a3SBenjamin Herrenschmidt pe->dma_weight = pnv_ioda_dma_weight(dev); 1055184cd4a3SBenjamin Herrenschmidt if (pe->dma_weight != 0) { 1056184cd4a3SBenjamin Herrenschmidt phb->ioda.dma_weight += pe->dma_weight; 1057184cd4a3SBenjamin Herrenschmidt phb->ioda.dma_pe_count++; 1058184cd4a3SBenjamin Herrenschmidt } 1059184cd4a3SBenjamin Herrenschmidt 1060184cd4a3SBenjamin Herrenschmidt /* Link the PE */ 1061184cd4a3SBenjamin Herrenschmidt pnv_ioda_link_pe_by_weight(phb, pe); 1062184cd4a3SBenjamin Herrenschmidt 1063184cd4a3SBenjamin Herrenschmidt return pe; 1064184cd4a3SBenjamin Herrenschmidt } 1065184cd4a3SBenjamin Herrenschmidt 1066184cd4a3SBenjamin Herrenschmidt static void pnv_ioda_setup_same_PE(struct pci_bus *bus, struct pnv_ioda_pe *pe) 1067184cd4a3SBenjamin Herrenschmidt { 1068184cd4a3SBenjamin Herrenschmidt struct pci_dev *dev; 1069184cd4a3SBenjamin Herrenschmidt 1070184cd4a3SBenjamin Herrenschmidt list_for_each_entry(dev, &bus->devices, bus_list) { 1071b72c1f65SBenjamin Herrenschmidt struct pci_dn *pdn = pci_get_pdn(dev); 1072184cd4a3SBenjamin Herrenschmidt 1073184cd4a3SBenjamin Herrenschmidt if (pdn == NULL) { 1074184cd4a3SBenjamin Herrenschmidt pr_warn("%s: No device node associated with device !\n", 1075184cd4a3SBenjamin Herrenschmidt pci_name(dev)); 1076184cd4a3SBenjamin Herrenschmidt continue; 1077184cd4a3SBenjamin Herrenschmidt } 107894973b24SAlistair Popple pdn->pcidev = dev; 1079184cd4a3SBenjamin Herrenschmidt pdn->pe_number = pe->pe_number; 1080184cd4a3SBenjamin Herrenschmidt pe->dma_weight += pnv_ioda_dma_weight(dev); 1081fb446ad0SGavin Shan if ((pe->flags & PNV_IODA_PE_BUS_ALL) && dev->subordinate) 1082184cd4a3SBenjamin Herrenschmidt pnv_ioda_setup_same_PE(dev->subordinate, pe); 1083184cd4a3SBenjamin Herrenschmidt } 1084184cd4a3SBenjamin Herrenschmidt } 1085184cd4a3SBenjamin Herrenschmidt 1086fb446ad0SGavin Shan /* 1087fb446ad0SGavin Shan * There're 2 types of PCI bus sensitive PEs: One that is compromised of 1088fb446ad0SGavin Shan * single PCI bus. Another one that contains the primary PCI bus and its 1089fb446ad0SGavin Shan * subordinate PCI devices and buses. The second type of PE is normally 1090fb446ad0SGavin Shan * orgiriated by PCIe-to-PCI bridge or PLX switch downstream ports. 1091fb446ad0SGavin Shan */ 1092d1203852SGavin Shan static void pnv_ioda_setup_bus_PE(struct pci_bus *bus, bool all) 1093184cd4a3SBenjamin Herrenschmidt { 1094fb446ad0SGavin Shan struct pci_controller *hose = pci_bus_to_host(bus); 1095184cd4a3SBenjamin Herrenschmidt struct pnv_phb *phb = hose->private_data; 1096184cd4a3SBenjamin Herrenschmidt struct pnv_ioda_pe *pe; 1097689ee8c9SGavin Shan unsigned int pe_num = IODA_INVALID_PE; 1098184cd4a3SBenjamin Herrenschmidt 1099262af557SGuo Chao /* Check if PE is determined by M64 */ 1100262af557SGuo Chao if (phb->pick_m64_pe) 110126ba248dSGavin Shan pe_num = phb->pick_m64_pe(bus, all); 1102262af557SGuo Chao 1103262af557SGuo Chao /* The PE number isn't pinned by M64 */ 1104262af557SGuo Chao if (pe_num == IODA_INVALID_PE) 1105184cd4a3SBenjamin Herrenschmidt pe_num = pnv_ioda_alloc_pe(phb); 1106262af557SGuo Chao 1107184cd4a3SBenjamin Herrenschmidt if (pe_num == IODA_INVALID_PE) { 1108fb446ad0SGavin Shan pr_warning("%s: Not enough PE# available for PCI bus %04x:%02x\n", 1109fb446ad0SGavin Shan __func__, pci_domain_nr(bus), bus->number); 1110184cd4a3SBenjamin Herrenschmidt return; 1111184cd4a3SBenjamin Herrenschmidt } 1112184cd4a3SBenjamin Herrenschmidt 1113184cd4a3SBenjamin Herrenschmidt pe = &phb->ioda.pe_array[pe_num]; 1114262af557SGuo Chao pe->flags |= (all ? PNV_IODA_PE_BUS_ALL : PNV_IODA_PE_BUS); 1115184cd4a3SBenjamin Herrenschmidt pe->pbus = bus; 1116184cd4a3SBenjamin Herrenschmidt pe->pdev = NULL; 1117184cd4a3SBenjamin Herrenschmidt pe->tce32_seg = -1; 1118184cd4a3SBenjamin Herrenschmidt pe->mve_number = -1; 1119b918c62eSYinghai Lu pe->rid = bus->busn_res.start << 8; 1120184cd4a3SBenjamin Herrenschmidt pe->dma_weight = 0; 1121184cd4a3SBenjamin Herrenschmidt 1122fb446ad0SGavin Shan if (all) 1123fb446ad0SGavin Shan pe_info(pe, "Secondary bus %d..%d associated with PE#%d\n", 1124fb446ad0SGavin Shan bus->busn_res.start, bus->busn_res.end, pe_num); 1125fb446ad0SGavin Shan else 1126fb446ad0SGavin Shan pe_info(pe, "Secondary bus %d associated with PE#%d\n", 1127fb446ad0SGavin Shan bus->busn_res.start, pe_num); 1128184cd4a3SBenjamin Herrenschmidt 1129184cd4a3SBenjamin Herrenschmidt if (pnv_ioda_configure_pe(phb, pe)) { 1130184cd4a3SBenjamin Herrenschmidt /* XXX What do we do here ? */ 1131184cd4a3SBenjamin Herrenschmidt if (pe_num) 1132184cd4a3SBenjamin Herrenschmidt pnv_ioda_free_pe(phb, pe_num); 1133184cd4a3SBenjamin Herrenschmidt pe->pbus = NULL; 1134184cd4a3SBenjamin Herrenschmidt return; 1135184cd4a3SBenjamin Herrenschmidt } 1136184cd4a3SBenjamin Herrenschmidt 1137184cd4a3SBenjamin Herrenschmidt /* Associate it with all child devices */ 1138184cd4a3SBenjamin Herrenschmidt pnv_ioda_setup_same_PE(bus, pe); 1139184cd4a3SBenjamin Herrenschmidt 11407ebdf956SGavin Shan /* Put PE to the list */ 11417ebdf956SGavin Shan list_add_tail(&pe->list, &phb->ioda.pe_list); 11427ebdf956SGavin Shan 1143184cd4a3SBenjamin Herrenschmidt /* Account for one DMA PE if at least one DMA capable device exist 1144184cd4a3SBenjamin Herrenschmidt * below the bridge 1145184cd4a3SBenjamin Herrenschmidt */ 1146184cd4a3SBenjamin Herrenschmidt if (pe->dma_weight != 0) { 1147184cd4a3SBenjamin Herrenschmidt phb->ioda.dma_weight += pe->dma_weight; 1148184cd4a3SBenjamin Herrenschmidt phb->ioda.dma_pe_count++; 1149184cd4a3SBenjamin Herrenschmidt } 1150184cd4a3SBenjamin Herrenschmidt 1151184cd4a3SBenjamin Herrenschmidt /* Link the PE */ 1152184cd4a3SBenjamin Herrenschmidt pnv_ioda_link_pe_by_weight(phb, pe); 1153184cd4a3SBenjamin Herrenschmidt } 1154184cd4a3SBenjamin Herrenschmidt 1155b521549aSAlistair Popple static struct pnv_ioda_pe *pnv_ioda_setup_npu_PE(struct pci_dev *npu_pdev) 11565d2aa710SAlistair Popple { 1157b521549aSAlistair Popple int pe_num, found_pe = false, rc; 1158b521549aSAlistair Popple long rid; 1159b521549aSAlistair Popple struct pnv_ioda_pe *pe; 1160b521549aSAlistair Popple struct pci_dev *gpu_pdev; 1161b521549aSAlistair Popple struct pci_dn *npu_pdn; 1162b521549aSAlistair Popple struct pci_controller *hose = pci_bus_to_host(npu_pdev->bus); 1163b521549aSAlistair Popple struct pnv_phb *phb = hose->private_data; 1164b521549aSAlistair Popple 1165b521549aSAlistair Popple /* 1166b521549aSAlistair Popple * Due to a hardware errata PE#0 on the NPU is reserved for 1167b521549aSAlistair Popple * error handling. This means we only have three PEs remaining 1168b521549aSAlistair Popple * which need to be assigned to four links, implying some 1169b521549aSAlistair Popple * links must share PEs. 1170b521549aSAlistair Popple * 1171b521549aSAlistair Popple * To achieve this we assign PEs such that NPUs linking the 1172b521549aSAlistair Popple * same GPU get assigned the same PE. 1173b521549aSAlistair Popple */ 1174b521549aSAlistair Popple gpu_pdev = pnv_pci_get_gpu_dev(npu_pdev); 117592b8f137SGavin Shan for (pe_num = 0; pe_num < phb->ioda.total_pe_num; pe_num++) { 1176b521549aSAlistair Popple pe = &phb->ioda.pe_array[pe_num]; 1177b521549aSAlistair Popple if (!pe->pdev) 1178b521549aSAlistair Popple continue; 1179b521549aSAlistair Popple 1180b521549aSAlistair Popple if (pnv_pci_get_gpu_dev(pe->pdev) == gpu_pdev) { 1181b521549aSAlistair Popple /* 1182b521549aSAlistair Popple * This device has the same peer GPU so should 1183b521549aSAlistair Popple * be assigned the same PE as the existing 1184b521549aSAlistair Popple * peer NPU. 1185b521549aSAlistair Popple */ 1186b521549aSAlistair Popple dev_info(&npu_pdev->dev, 1187b521549aSAlistair Popple "Associating to existing PE %d\n", pe_num); 1188b521549aSAlistair Popple pci_dev_get(npu_pdev); 1189b521549aSAlistair Popple npu_pdn = pci_get_pdn(npu_pdev); 1190b521549aSAlistair Popple rid = npu_pdev->bus->number << 8 | npu_pdn->devfn; 1191b521549aSAlistair Popple npu_pdn->pcidev = npu_pdev; 1192b521549aSAlistair Popple npu_pdn->pe_number = pe_num; 1193b521549aSAlistair Popple pe->dma_weight += pnv_ioda_dma_weight(npu_pdev); 1194b521549aSAlistair Popple phb->ioda.pe_rmap[rid] = pe->pe_number; 1195b521549aSAlistair Popple 1196b521549aSAlistair Popple /* Map the PE to this link */ 1197b521549aSAlistair Popple rc = opal_pci_set_pe(phb->opal_id, pe_num, rid, 1198b521549aSAlistair Popple OpalPciBusAll, 1199b521549aSAlistair Popple OPAL_COMPARE_RID_DEVICE_NUMBER, 1200b521549aSAlistair Popple OPAL_COMPARE_RID_FUNCTION_NUMBER, 1201b521549aSAlistair Popple OPAL_MAP_PE); 1202b521549aSAlistair Popple WARN_ON(rc != OPAL_SUCCESS); 1203b521549aSAlistair Popple found_pe = true; 1204b521549aSAlistair Popple break; 1205b521549aSAlistair Popple } 1206b521549aSAlistair Popple } 1207b521549aSAlistair Popple 1208b521549aSAlistair Popple if (!found_pe) 1209b521549aSAlistair Popple /* 1210b521549aSAlistair Popple * Could not find an existing PE so allocate a new 1211b521549aSAlistair Popple * one. 1212b521549aSAlistair Popple */ 1213b521549aSAlistair Popple return pnv_ioda_setup_dev_PE(npu_pdev); 1214b521549aSAlistair Popple else 1215b521549aSAlistair Popple return pe; 1216b521549aSAlistair Popple } 1217b521549aSAlistair Popple 1218b521549aSAlistair Popple static void pnv_ioda_setup_npu_PEs(struct pci_bus *bus) 1219b521549aSAlistair Popple { 12205d2aa710SAlistair Popple struct pci_dev *pdev; 12215d2aa710SAlistair Popple 12225d2aa710SAlistair Popple list_for_each_entry(pdev, &bus->devices, bus_list) 1223b521549aSAlistair Popple pnv_ioda_setup_npu_PE(pdev); 12245d2aa710SAlistair Popple } 12255d2aa710SAlistair Popple 1226cad5cef6SGreg Kroah-Hartman static void pnv_ioda_setup_PEs(struct pci_bus *bus) 1227184cd4a3SBenjamin Herrenschmidt { 1228184cd4a3SBenjamin Herrenschmidt struct pci_dev *dev; 1229fb446ad0SGavin Shan 1230d1203852SGavin Shan pnv_ioda_setup_bus_PE(bus, false); 1231184cd4a3SBenjamin Herrenschmidt 1232184cd4a3SBenjamin Herrenschmidt list_for_each_entry(dev, &bus->devices, bus_list) { 1233fb446ad0SGavin Shan if (dev->subordinate) { 123462f87c0eSYijing Wang if (pci_pcie_type(dev) == PCI_EXP_TYPE_PCI_BRIDGE) 1235d1203852SGavin Shan pnv_ioda_setup_bus_PE(dev->subordinate, true); 1236fb446ad0SGavin Shan else 1237184cd4a3SBenjamin Herrenschmidt pnv_ioda_setup_PEs(dev->subordinate); 1238184cd4a3SBenjamin Herrenschmidt } 1239184cd4a3SBenjamin Herrenschmidt } 1240fb446ad0SGavin Shan } 1241fb446ad0SGavin Shan 1242fb446ad0SGavin Shan /* 1243fb446ad0SGavin Shan * Configure PEs so that the downstream PCI buses and devices 1244fb446ad0SGavin Shan * could have their associated PE#. Unfortunately, we didn't 1245fb446ad0SGavin Shan * figure out the way to identify the PLX bridge yet. So we 1246fb446ad0SGavin Shan * simply put the PCI bus and the subordinate behind the root 1247fb446ad0SGavin Shan * port to PE# here. The game rule here is expected to be changed 1248fb446ad0SGavin Shan * as soon as we can detected PLX bridge correctly. 1249fb446ad0SGavin Shan */ 1250cad5cef6SGreg Kroah-Hartman static void pnv_pci_ioda_setup_PEs(void) 1251fb446ad0SGavin Shan { 1252fb446ad0SGavin Shan struct pci_controller *hose, *tmp; 1253262af557SGuo Chao struct pnv_phb *phb; 1254fb446ad0SGavin Shan 1255fb446ad0SGavin Shan list_for_each_entry_safe(hose, tmp, &hose_list, list_node) { 1256262af557SGuo Chao phb = hose->private_data; 1257262af557SGuo Chao 1258262af557SGuo Chao /* M64 layout might affect PE allocation */ 12595ef73567SGavin Shan if (phb->reserve_m64_pe) 126096a2f92bSGavin Shan phb->reserve_m64_pe(hose->bus, NULL, true); 1261262af557SGuo Chao 12625d2aa710SAlistair Popple /* 12635d2aa710SAlistair Popple * On NPU PHB, we expect separate PEs for individual PCI 12645d2aa710SAlistair Popple * functions. PCI bus dependent PEs are required for the 12655d2aa710SAlistair Popple * remaining types of PHBs. 12665d2aa710SAlistair Popple */ 126708f48f32SAlistair Popple if (phb->type == PNV_PHB_NPU) { 126808f48f32SAlistair Popple /* PE#0 is needed for error reporting */ 126908f48f32SAlistair Popple pnv_ioda_reserve_pe(phb, 0); 1270b521549aSAlistair Popple pnv_ioda_setup_npu_PEs(hose->bus); 127108f48f32SAlistair Popple } else 1272fb446ad0SGavin Shan pnv_ioda_setup_PEs(hose->bus); 1273fb446ad0SGavin Shan } 1274fb446ad0SGavin Shan } 1275184cd4a3SBenjamin Herrenschmidt 1276a8b2f828SGavin Shan #ifdef CONFIG_PCI_IOV 1277ee8222feSWei Yang static int pnv_pci_vf_release_m64(struct pci_dev *pdev, u16 num_vfs) 1278781a868fSWei Yang { 1279781a868fSWei Yang struct pci_bus *bus; 1280781a868fSWei Yang struct pci_controller *hose; 1281781a868fSWei Yang struct pnv_phb *phb; 1282781a868fSWei Yang struct pci_dn *pdn; 128302639b0eSWei Yang int i, j; 1284ee8222feSWei Yang int m64_bars; 1285781a868fSWei Yang 1286781a868fSWei Yang bus = pdev->bus; 1287781a868fSWei Yang hose = pci_bus_to_host(bus); 1288781a868fSWei Yang phb = hose->private_data; 1289781a868fSWei Yang pdn = pci_get_pdn(pdev); 1290781a868fSWei Yang 1291ee8222feSWei Yang if (pdn->m64_single_mode) 1292ee8222feSWei Yang m64_bars = num_vfs; 1293ee8222feSWei Yang else 1294ee8222feSWei Yang m64_bars = 1; 1295ee8222feSWei Yang 129602639b0eSWei Yang for (i = 0; i < PCI_SRIOV_NUM_BARS; i++) 1297ee8222feSWei Yang for (j = 0; j < m64_bars; j++) { 1298ee8222feSWei Yang if (pdn->m64_map[j][i] == IODA_INVALID_M64) 1299781a868fSWei Yang continue; 1300781a868fSWei Yang opal_pci_phb_mmio_enable(phb->opal_id, 1301ee8222feSWei Yang OPAL_M64_WINDOW_TYPE, pdn->m64_map[j][i], 0); 1302ee8222feSWei Yang clear_bit(pdn->m64_map[j][i], &phb->ioda.m64_bar_alloc); 1303ee8222feSWei Yang pdn->m64_map[j][i] = IODA_INVALID_M64; 1304781a868fSWei Yang } 1305781a868fSWei Yang 1306ee8222feSWei Yang kfree(pdn->m64_map); 1307781a868fSWei Yang return 0; 1308781a868fSWei Yang } 1309781a868fSWei Yang 131002639b0eSWei Yang static int pnv_pci_vf_assign_m64(struct pci_dev *pdev, u16 num_vfs) 1311781a868fSWei Yang { 1312781a868fSWei Yang struct pci_bus *bus; 1313781a868fSWei Yang struct pci_controller *hose; 1314781a868fSWei Yang struct pnv_phb *phb; 1315781a868fSWei Yang struct pci_dn *pdn; 1316781a868fSWei Yang unsigned int win; 1317781a868fSWei Yang struct resource *res; 131802639b0eSWei Yang int i, j; 1319781a868fSWei Yang int64_t rc; 132002639b0eSWei Yang int total_vfs; 132102639b0eSWei Yang resource_size_t size, start; 132202639b0eSWei Yang int pe_num; 1323ee8222feSWei Yang int m64_bars; 1324781a868fSWei Yang 1325781a868fSWei Yang bus = pdev->bus; 1326781a868fSWei Yang hose = pci_bus_to_host(bus); 1327781a868fSWei Yang phb = hose->private_data; 1328781a868fSWei Yang pdn = pci_get_pdn(pdev); 132902639b0eSWei Yang total_vfs = pci_sriov_get_totalvfs(pdev); 1330781a868fSWei Yang 1331ee8222feSWei Yang if (pdn->m64_single_mode) 1332ee8222feSWei Yang m64_bars = num_vfs; 1333ee8222feSWei Yang else 1334ee8222feSWei Yang m64_bars = 1; 133502639b0eSWei Yang 1336ee8222feSWei Yang pdn->m64_map = kmalloc(sizeof(*pdn->m64_map) * m64_bars, GFP_KERNEL); 1337ee8222feSWei Yang if (!pdn->m64_map) 1338ee8222feSWei Yang return -ENOMEM; 1339ee8222feSWei Yang /* Initialize the m64_map to IODA_INVALID_M64 */ 1340ee8222feSWei Yang for (i = 0; i < m64_bars ; i++) 1341ee8222feSWei Yang for (j = 0; j < PCI_SRIOV_NUM_BARS; j++) 1342ee8222feSWei Yang pdn->m64_map[i][j] = IODA_INVALID_M64; 1343ee8222feSWei Yang 1344781a868fSWei Yang 1345781a868fSWei Yang for (i = 0; i < PCI_SRIOV_NUM_BARS; i++) { 1346781a868fSWei Yang res = &pdev->resource[i + PCI_IOV_RESOURCES]; 1347781a868fSWei Yang if (!res->flags || !res->parent) 1348781a868fSWei Yang continue; 1349781a868fSWei Yang 1350ee8222feSWei Yang for (j = 0; j < m64_bars; j++) { 1351781a868fSWei Yang do { 1352781a868fSWei Yang win = find_next_zero_bit(&phb->ioda.m64_bar_alloc, 1353781a868fSWei Yang phb->ioda.m64_bar_idx + 1, 0); 1354781a868fSWei Yang 1355781a868fSWei Yang if (win >= phb->ioda.m64_bar_idx + 1) 1356781a868fSWei Yang goto m64_failed; 1357781a868fSWei Yang } while (test_and_set_bit(win, &phb->ioda.m64_bar_alloc)); 1358781a868fSWei Yang 1359ee8222feSWei Yang pdn->m64_map[j][i] = win; 136002639b0eSWei Yang 1361ee8222feSWei Yang if (pdn->m64_single_mode) { 136202639b0eSWei Yang size = pci_iov_resource_size(pdev, 136302639b0eSWei Yang PCI_IOV_RESOURCES + i); 136402639b0eSWei Yang start = res->start + size * j; 136502639b0eSWei Yang } else { 136602639b0eSWei Yang size = resource_size(res); 136702639b0eSWei Yang start = res->start; 136802639b0eSWei Yang } 1369781a868fSWei Yang 1370781a868fSWei Yang /* Map the M64 here */ 1371ee8222feSWei Yang if (pdn->m64_single_mode) { 1372be283eebSWei Yang pe_num = pdn->pe_num_map[j]; 137302639b0eSWei Yang rc = opal_pci_map_pe_mmio_window(phb->opal_id, 137402639b0eSWei Yang pe_num, OPAL_M64_WINDOW_TYPE, 1375ee8222feSWei Yang pdn->m64_map[j][i], 0); 137602639b0eSWei Yang } 137702639b0eSWei Yang 1378781a868fSWei Yang rc = opal_pci_set_phb_mem_window(phb->opal_id, 1379781a868fSWei Yang OPAL_M64_WINDOW_TYPE, 1380ee8222feSWei Yang pdn->m64_map[j][i], 138102639b0eSWei Yang start, 1382781a868fSWei Yang 0, /* unused */ 138302639b0eSWei Yang size); 138402639b0eSWei Yang 138502639b0eSWei Yang 1386781a868fSWei Yang if (rc != OPAL_SUCCESS) { 1387781a868fSWei Yang dev_err(&pdev->dev, "Failed to map M64 window #%d: %lld\n", 1388781a868fSWei Yang win, rc); 1389781a868fSWei Yang goto m64_failed; 1390781a868fSWei Yang } 1391781a868fSWei Yang 1392ee8222feSWei Yang if (pdn->m64_single_mode) 1393781a868fSWei Yang rc = opal_pci_phb_mmio_enable(phb->opal_id, 1394ee8222feSWei Yang OPAL_M64_WINDOW_TYPE, pdn->m64_map[j][i], 2); 139502639b0eSWei Yang else 139602639b0eSWei Yang rc = opal_pci_phb_mmio_enable(phb->opal_id, 1397ee8222feSWei Yang OPAL_M64_WINDOW_TYPE, pdn->m64_map[j][i], 1); 139802639b0eSWei Yang 1399781a868fSWei Yang if (rc != OPAL_SUCCESS) { 1400781a868fSWei Yang dev_err(&pdev->dev, "Failed to enable M64 window #%d: %llx\n", 1401781a868fSWei Yang win, rc); 1402781a868fSWei Yang goto m64_failed; 1403781a868fSWei Yang } 1404781a868fSWei Yang } 140502639b0eSWei Yang } 1406781a868fSWei Yang return 0; 1407781a868fSWei Yang 1408781a868fSWei Yang m64_failed: 1409ee8222feSWei Yang pnv_pci_vf_release_m64(pdev, num_vfs); 1410781a868fSWei Yang return -EBUSY; 1411781a868fSWei Yang } 1412781a868fSWei Yang 1413c035e37bSAlexey Kardashevskiy static long pnv_pci_ioda2_unset_window(struct iommu_table_group *table_group, 1414c035e37bSAlexey Kardashevskiy int num); 1415c035e37bSAlexey Kardashevskiy static void pnv_pci_ioda2_set_bypass(struct pnv_ioda_pe *pe, bool enable); 1416c035e37bSAlexey Kardashevskiy 1417781a868fSWei Yang static void pnv_pci_ioda2_release_dma_pe(struct pci_dev *dev, struct pnv_ioda_pe *pe) 1418781a868fSWei Yang { 1419781a868fSWei Yang struct iommu_table *tbl; 1420781a868fSWei Yang int64_t rc; 1421781a868fSWei Yang 1422b348aa65SAlexey Kardashevskiy tbl = pe->table_group.tables[0]; 1423c035e37bSAlexey Kardashevskiy rc = pnv_pci_ioda2_unset_window(&pe->table_group, 0); 1424781a868fSWei Yang if (rc) 1425781a868fSWei Yang pe_warn(pe, "OPAL error %ld release DMA window\n", rc); 1426781a868fSWei Yang 1427c035e37bSAlexey Kardashevskiy pnv_pci_ioda2_set_bypass(pe, false); 14280eaf4defSAlexey Kardashevskiy if (pe->table_group.group) { 14290eaf4defSAlexey Kardashevskiy iommu_group_put(pe->table_group.group); 14300eaf4defSAlexey Kardashevskiy BUG_ON(pe->table_group.group); 1431ac9a5889SAlexey Kardashevskiy } 1432aca6913fSAlexey Kardashevskiy pnv_pci_ioda2_table_free_pages(tbl); 1433781a868fSWei Yang iommu_free_table(tbl, of_node_full_name(dev->dev.of_node)); 1434781a868fSWei Yang } 1435781a868fSWei Yang 1436ee8222feSWei Yang static void pnv_ioda_release_vf_PE(struct pci_dev *pdev) 1437781a868fSWei Yang { 1438781a868fSWei Yang struct pci_bus *bus; 1439781a868fSWei Yang struct pci_controller *hose; 1440781a868fSWei Yang struct pnv_phb *phb; 1441781a868fSWei Yang struct pnv_ioda_pe *pe, *pe_n; 1442781a868fSWei Yang struct pci_dn *pdn; 1443781a868fSWei Yang 1444781a868fSWei Yang bus = pdev->bus; 1445781a868fSWei Yang hose = pci_bus_to_host(bus); 1446781a868fSWei Yang phb = hose->private_data; 144702639b0eSWei Yang pdn = pci_get_pdn(pdev); 1448781a868fSWei Yang 1449781a868fSWei Yang if (!pdev->is_physfn) 1450781a868fSWei Yang return; 1451781a868fSWei Yang 1452781a868fSWei Yang list_for_each_entry_safe(pe, pe_n, &phb->ioda.pe_list, list) { 1453781a868fSWei Yang if (pe->parent_dev != pdev) 1454781a868fSWei Yang continue; 1455781a868fSWei Yang 1456781a868fSWei Yang pnv_pci_ioda2_release_dma_pe(pdev, pe); 1457781a868fSWei Yang 1458781a868fSWei Yang /* Remove from list */ 1459781a868fSWei Yang mutex_lock(&phb->ioda.pe_list_mutex); 1460781a868fSWei Yang list_del(&pe->list); 1461781a868fSWei Yang mutex_unlock(&phb->ioda.pe_list_mutex); 1462781a868fSWei Yang 1463781a868fSWei Yang pnv_ioda_deconfigure_pe(phb, pe); 1464781a868fSWei Yang 1465781a868fSWei Yang pnv_ioda_free_pe(phb, pe->pe_number); 1466781a868fSWei Yang } 1467781a868fSWei Yang } 1468781a868fSWei Yang 1469781a868fSWei Yang void pnv_pci_sriov_disable(struct pci_dev *pdev) 1470781a868fSWei Yang { 1471781a868fSWei Yang struct pci_bus *bus; 1472781a868fSWei Yang struct pci_controller *hose; 1473781a868fSWei Yang struct pnv_phb *phb; 1474781a868fSWei Yang struct pci_dn *pdn; 1475781a868fSWei Yang struct pci_sriov *iov; 1476be283eebSWei Yang u16 num_vfs, i; 1477781a868fSWei Yang 1478781a868fSWei Yang bus = pdev->bus; 1479781a868fSWei Yang hose = pci_bus_to_host(bus); 1480781a868fSWei Yang phb = hose->private_data; 1481781a868fSWei Yang pdn = pci_get_pdn(pdev); 1482781a868fSWei Yang iov = pdev->sriov; 1483781a868fSWei Yang num_vfs = pdn->num_vfs; 1484781a868fSWei Yang 1485781a868fSWei Yang /* Release VF PEs */ 1486ee8222feSWei Yang pnv_ioda_release_vf_PE(pdev); 1487781a868fSWei Yang 1488781a868fSWei Yang if (phb->type == PNV_PHB_IODA2) { 1489ee8222feSWei Yang if (!pdn->m64_single_mode) 1490be283eebSWei Yang pnv_pci_vf_resource_shift(pdev, -*pdn->pe_num_map); 1491781a868fSWei Yang 1492781a868fSWei Yang /* Release M64 windows */ 1493ee8222feSWei Yang pnv_pci_vf_release_m64(pdev, num_vfs); 1494781a868fSWei Yang 1495781a868fSWei Yang /* Release PE numbers */ 1496be283eebSWei Yang if (pdn->m64_single_mode) { 1497be283eebSWei Yang for (i = 0; i < num_vfs; i++) { 1498be283eebSWei Yang if (pdn->pe_num_map[i] != IODA_INVALID_PE) 1499be283eebSWei Yang pnv_ioda_free_pe(phb, pdn->pe_num_map[i]); 1500be283eebSWei Yang } 1501be283eebSWei Yang } else 1502be283eebSWei Yang bitmap_clear(phb->ioda.pe_alloc, *pdn->pe_num_map, num_vfs); 1503be283eebSWei Yang /* Releasing pe_num_map */ 1504be283eebSWei Yang kfree(pdn->pe_num_map); 1505781a868fSWei Yang } 1506781a868fSWei Yang } 1507781a868fSWei Yang 1508781a868fSWei Yang static void pnv_pci_ioda2_setup_dma_pe(struct pnv_phb *phb, 1509781a868fSWei Yang struct pnv_ioda_pe *pe); 1510781a868fSWei Yang static void pnv_ioda_setup_vf_PE(struct pci_dev *pdev, u16 num_vfs) 1511781a868fSWei Yang { 1512781a868fSWei Yang struct pci_bus *bus; 1513781a868fSWei Yang struct pci_controller *hose; 1514781a868fSWei Yang struct pnv_phb *phb; 1515781a868fSWei Yang struct pnv_ioda_pe *pe; 1516781a868fSWei Yang int pe_num; 1517781a868fSWei Yang u16 vf_index; 1518781a868fSWei Yang struct pci_dn *pdn; 1519781a868fSWei Yang 1520781a868fSWei Yang bus = pdev->bus; 1521781a868fSWei Yang hose = pci_bus_to_host(bus); 1522781a868fSWei Yang phb = hose->private_data; 1523781a868fSWei Yang pdn = pci_get_pdn(pdev); 1524781a868fSWei Yang 1525781a868fSWei Yang if (!pdev->is_physfn) 1526781a868fSWei Yang return; 1527781a868fSWei Yang 1528781a868fSWei Yang /* Reserve PE for each VF */ 1529781a868fSWei Yang for (vf_index = 0; vf_index < num_vfs; vf_index++) { 1530be283eebSWei Yang if (pdn->m64_single_mode) 1531be283eebSWei Yang pe_num = pdn->pe_num_map[vf_index]; 1532be283eebSWei Yang else 1533be283eebSWei Yang pe_num = *pdn->pe_num_map + vf_index; 1534781a868fSWei Yang 1535781a868fSWei Yang pe = &phb->ioda.pe_array[pe_num]; 1536781a868fSWei Yang pe->pe_number = pe_num; 1537781a868fSWei Yang pe->phb = phb; 1538781a868fSWei Yang pe->flags = PNV_IODA_PE_VF; 1539781a868fSWei Yang pe->pbus = NULL; 1540781a868fSWei Yang pe->parent_dev = pdev; 1541781a868fSWei Yang pe->tce32_seg = -1; 1542781a868fSWei Yang pe->mve_number = -1; 1543781a868fSWei Yang pe->rid = (pci_iov_virtfn_bus(pdev, vf_index) << 8) | 1544781a868fSWei Yang pci_iov_virtfn_devfn(pdev, vf_index); 1545781a868fSWei Yang 1546781a868fSWei Yang pe_info(pe, "VF %04d:%02d:%02d.%d associated with PE#%d\n", 1547781a868fSWei Yang hose->global_number, pdev->bus->number, 1548781a868fSWei Yang PCI_SLOT(pci_iov_virtfn_devfn(pdev, vf_index)), 1549781a868fSWei Yang PCI_FUNC(pci_iov_virtfn_devfn(pdev, vf_index)), pe_num); 1550781a868fSWei Yang 1551781a868fSWei Yang if (pnv_ioda_configure_pe(phb, pe)) { 1552781a868fSWei Yang /* XXX What do we do here ? */ 1553781a868fSWei Yang if (pe_num) 1554781a868fSWei Yang pnv_ioda_free_pe(phb, pe_num); 1555781a868fSWei Yang pe->pdev = NULL; 1556781a868fSWei Yang continue; 1557781a868fSWei Yang } 1558781a868fSWei Yang 1559781a868fSWei Yang /* Put PE to the list */ 1560781a868fSWei Yang mutex_lock(&phb->ioda.pe_list_mutex); 1561781a868fSWei Yang list_add_tail(&pe->list, &phb->ioda.pe_list); 1562781a868fSWei Yang mutex_unlock(&phb->ioda.pe_list_mutex); 1563781a868fSWei Yang 1564781a868fSWei Yang pnv_pci_ioda2_setup_dma_pe(phb, pe); 1565781a868fSWei Yang } 1566781a868fSWei Yang } 1567781a868fSWei Yang 1568781a868fSWei Yang int pnv_pci_sriov_enable(struct pci_dev *pdev, u16 num_vfs) 1569781a868fSWei Yang { 1570781a868fSWei Yang struct pci_bus *bus; 1571781a868fSWei Yang struct pci_controller *hose; 1572781a868fSWei Yang struct pnv_phb *phb; 1573781a868fSWei Yang struct pci_dn *pdn; 1574781a868fSWei Yang int ret; 1575be283eebSWei Yang u16 i; 1576781a868fSWei Yang 1577781a868fSWei Yang bus = pdev->bus; 1578781a868fSWei Yang hose = pci_bus_to_host(bus); 1579781a868fSWei Yang phb = hose->private_data; 1580781a868fSWei Yang pdn = pci_get_pdn(pdev); 1581781a868fSWei Yang 1582781a868fSWei Yang if (phb->type == PNV_PHB_IODA2) { 1583b0331854SWei Yang if (!pdn->vfs_expanded) { 1584b0331854SWei Yang dev_info(&pdev->dev, "don't support this SRIOV device" 1585b0331854SWei Yang " with non 64bit-prefetchable IOV BAR\n"); 1586b0331854SWei Yang return -ENOSPC; 1587b0331854SWei Yang } 1588b0331854SWei Yang 1589ee8222feSWei Yang /* 1590ee8222feSWei Yang * When M64 BARs functions in Single PE mode, the number of VFs 1591ee8222feSWei Yang * could be enabled must be less than the number of M64 BARs. 1592ee8222feSWei Yang */ 1593ee8222feSWei Yang if (pdn->m64_single_mode && num_vfs > phb->ioda.m64_bar_idx) { 1594ee8222feSWei Yang dev_info(&pdev->dev, "Not enough M64 BAR for VFs\n"); 1595ee8222feSWei Yang return -EBUSY; 1596ee8222feSWei Yang } 1597ee8222feSWei Yang 1598be283eebSWei Yang /* Allocating pe_num_map */ 1599be283eebSWei Yang if (pdn->m64_single_mode) 1600be283eebSWei Yang pdn->pe_num_map = kmalloc(sizeof(*pdn->pe_num_map) * num_vfs, 1601be283eebSWei Yang GFP_KERNEL); 1602be283eebSWei Yang else 1603be283eebSWei Yang pdn->pe_num_map = kmalloc(sizeof(*pdn->pe_num_map), GFP_KERNEL); 1604be283eebSWei Yang 1605be283eebSWei Yang if (!pdn->pe_num_map) 1606be283eebSWei Yang return -ENOMEM; 1607be283eebSWei Yang 1608be283eebSWei Yang if (pdn->m64_single_mode) 1609be283eebSWei Yang for (i = 0; i < num_vfs; i++) 1610be283eebSWei Yang pdn->pe_num_map[i] = IODA_INVALID_PE; 1611be283eebSWei Yang 1612781a868fSWei Yang /* Calculate available PE for required VFs */ 1613be283eebSWei Yang if (pdn->m64_single_mode) { 1614be283eebSWei Yang for (i = 0; i < num_vfs; i++) { 1615be283eebSWei Yang pdn->pe_num_map[i] = pnv_ioda_alloc_pe(phb); 1616be283eebSWei Yang if (pdn->pe_num_map[i] == IODA_INVALID_PE) { 1617be283eebSWei Yang ret = -EBUSY; 1618be283eebSWei Yang goto m64_failed; 1619be283eebSWei Yang } 1620be283eebSWei Yang } 1621be283eebSWei Yang } else { 1622781a868fSWei Yang mutex_lock(&phb->ioda.pe_alloc_mutex); 1623be283eebSWei Yang *pdn->pe_num_map = bitmap_find_next_zero_area( 162492b8f137SGavin Shan phb->ioda.pe_alloc, phb->ioda.total_pe_num, 1625781a868fSWei Yang 0, num_vfs, 0); 162692b8f137SGavin Shan if (*pdn->pe_num_map >= phb->ioda.total_pe_num) { 1627781a868fSWei Yang mutex_unlock(&phb->ioda.pe_alloc_mutex); 1628781a868fSWei Yang dev_info(&pdev->dev, "Failed to enable VF%d\n", num_vfs); 1629be283eebSWei Yang kfree(pdn->pe_num_map); 1630781a868fSWei Yang return -EBUSY; 1631781a868fSWei Yang } 1632be283eebSWei Yang bitmap_set(phb->ioda.pe_alloc, *pdn->pe_num_map, num_vfs); 1633781a868fSWei Yang mutex_unlock(&phb->ioda.pe_alloc_mutex); 1634be283eebSWei Yang } 1635be283eebSWei Yang pdn->num_vfs = num_vfs; 1636781a868fSWei Yang 1637781a868fSWei Yang /* Assign M64 window accordingly */ 163802639b0eSWei Yang ret = pnv_pci_vf_assign_m64(pdev, num_vfs); 1639781a868fSWei Yang if (ret) { 1640781a868fSWei Yang dev_info(&pdev->dev, "Not enough M64 window resources\n"); 1641781a868fSWei Yang goto m64_failed; 1642781a868fSWei Yang } 1643781a868fSWei Yang 1644781a868fSWei Yang /* 1645781a868fSWei Yang * When using one M64 BAR to map one IOV BAR, we need to shift 1646781a868fSWei Yang * the IOV BAR according to the PE# allocated to the VFs. 1647781a868fSWei Yang * Otherwise, the PE# for the VF will conflict with others. 1648781a868fSWei Yang */ 1649ee8222feSWei Yang if (!pdn->m64_single_mode) { 1650be283eebSWei Yang ret = pnv_pci_vf_resource_shift(pdev, *pdn->pe_num_map); 1651781a868fSWei Yang if (ret) 1652781a868fSWei Yang goto m64_failed; 1653781a868fSWei Yang } 165402639b0eSWei Yang } 1655781a868fSWei Yang 1656781a868fSWei Yang /* Setup VF PEs */ 1657781a868fSWei Yang pnv_ioda_setup_vf_PE(pdev, num_vfs); 1658781a868fSWei Yang 1659781a868fSWei Yang return 0; 1660781a868fSWei Yang 1661781a868fSWei Yang m64_failed: 1662be283eebSWei Yang if (pdn->m64_single_mode) { 1663be283eebSWei Yang for (i = 0; i < num_vfs; i++) { 1664be283eebSWei Yang if (pdn->pe_num_map[i] != IODA_INVALID_PE) 1665be283eebSWei Yang pnv_ioda_free_pe(phb, pdn->pe_num_map[i]); 1666be283eebSWei Yang } 1667be283eebSWei Yang } else 1668be283eebSWei Yang bitmap_clear(phb->ioda.pe_alloc, *pdn->pe_num_map, num_vfs); 1669be283eebSWei Yang 1670be283eebSWei Yang /* Releasing pe_num_map */ 1671be283eebSWei Yang kfree(pdn->pe_num_map); 1672781a868fSWei Yang 1673781a868fSWei Yang return ret; 1674781a868fSWei Yang } 1675781a868fSWei Yang 1676a8b2f828SGavin Shan int pcibios_sriov_disable(struct pci_dev *pdev) 1677a8b2f828SGavin Shan { 1678781a868fSWei Yang pnv_pci_sriov_disable(pdev); 1679781a868fSWei Yang 1680a8b2f828SGavin Shan /* Release PCI data */ 1681a8b2f828SGavin Shan remove_dev_pci_data(pdev); 1682a8b2f828SGavin Shan return 0; 1683a8b2f828SGavin Shan } 1684a8b2f828SGavin Shan 1685a8b2f828SGavin Shan int pcibios_sriov_enable(struct pci_dev *pdev, u16 num_vfs) 1686a8b2f828SGavin Shan { 1687a8b2f828SGavin Shan /* Allocate PCI data */ 1688a8b2f828SGavin Shan add_dev_pci_data(pdev); 1689781a868fSWei Yang 1690ee8222feSWei Yang return pnv_pci_sriov_enable(pdev, num_vfs); 1691a8b2f828SGavin Shan } 1692a8b2f828SGavin Shan #endif /* CONFIG_PCI_IOV */ 1693a8b2f828SGavin Shan 1694959c9bddSGavin Shan static void pnv_pci_ioda_dma_dev_setup(struct pnv_phb *phb, struct pci_dev *pdev) 1695184cd4a3SBenjamin Herrenschmidt { 1696b72c1f65SBenjamin Herrenschmidt struct pci_dn *pdn = pci_get_pdn(pdev); 1697959c9bddSGavin Shan struct pnv_ioda_pe *pe; 1698184cd4a3SBenjamin Herrenschmidt 1699959c9bddSGavin Shan /* 1700959c9bddSGavin Shan * The function can be called while the PE# 1701959c9bddSGavin Shan * hasn't been assigned. Do nothing for the 1702959c9bddSGavin Shan * case. 1703959c9bddSGavin Shan */ 1704959c9bddSGavin Shan if (!pdn || pdn->pe_number == IODA_INVALID_PE) 1705959c9bddSGavin Shan return; 1706184cd4a3SBenjamin Herrenschmidt 1707959c9bddSGavin Shan pe = &phb->ioda.pe_array[pdn->pe_number]; 1708cd15b048SBenjamin Herrenschmidt WARN_ON(get_dma_ops(&pdev->dev) != &dma_iommu_ops); 17090e1ffef0SAlexey Kardashevskiy set_dma_offset(&pdev->dev, pe->tce_bypass_base); 1710b348aa65SAlexey Kardashevskiy set_iommu_table_base(&pdev->dev, pe->table_group.tables[0]); 17114617082eSAlexey Kardashevskiy /* 17124617082eSAlexey Kardashevskiy * Note: iommu_add_device() will fail here as 17134617082eSAlexey Kardashevskiy * for physical PE: the device is already added by now; 17144617082eSAlexey Kardashevskiy * for virtual PE: sysfs entries are not ready yet and 17154617082eSAlexey Kardashevskiy * tce_iommu_bus_notifier will add the device to a group later. 17164617082eSAlexey Kardashevskiy */ 1717184cd4a3SBenjamin Herrenschmidt } 1718184cd4a3SBenjamin Herrenschmidt 1719763d2d8dSDaniel Axtens static int pnv_pci_ioda_dma_set_mask(struct pci_dev *pdev, u64 dma_mask) 1720cd15b048SBenjamin Herrenschmidt { 1721763d2d8dSDaniel Axtens struct pci_controller *hose = pci_bus_to_host(pdev->bus); 1722763d2d8dSDaniel Axtens struct pnv_phb *phb = hose->private_data; 1723cd15b048SBenjamin Herrenschmidt struct pci_dn *pdn = pci_get_pdn(pdev); 1724cd15b048SBenjamin Herrenschmidt struct pnv_ioda_pe *pe; 1725cd15b048SBenjamin Herrenschmidt uint64_t top; 1726cd15b048SBenjamin Herrenschmidt bool bypass = false; 17275d2aa710SAlistair Popple struct pci_dev *linked_npu_dev; 17285d2aa710SAlistair Popple int i; 1729cd15b048SBenjamin Herrenschmidt 1730cd15b048SBenjamin Herrenschmidt if (WARN_ON(!pdn || pdn->pe_number == IODA_INVALID_PE)) 1731cd15b048SBenjamin Herrenschmidt return -ENODEV;; 1732cd15b048SBenjamin Herrenschmidt 1733cd15b048SBenjamin Herrenschmidt pe = &phb->ioda.pe_array[pdn->pe_number]; 1734cd15b048SBenjamin Herrenschmidt if (pe->tce_bypass_enabled) { 1735cd15b048SBenjamin Herrenschmidt top = pe->tce_bypass_base + memblock_end_of_DRAM() - 1; 1736cd15b048SBenjamin Herrenschmidt bypass = (dma_mask >= top); 1737cd15b048SBenjamin Herrenschmidt } 1738cd15b048SBenjamin Herrenschmidt 1739cd15b048SBenjamin Herrenschmidt if (bypass) { 1740cd15b048SBenjamin Herrenschmidt dev_info(&pdev->dev, "Using 64-bit DMA iommu bypass\n"); 1741cd15b048SBenjamin Herrenschmidt set_dma_ops(&pdev->dev, &dma_direct_ops); 1742cd15b048SBenjamin Herrenschmidt } else { 1743cd15b048SBenjamin Herrenschmidt dev_info(&pdev->dev, "Using 32-bit DMA via iommu\n"); 1744cd15b048SBenjamin Herrenschmidt set_dma_ops(&pdev->dev, &dma_iommu_ops); 1745cd15b048SBenjamin Herrenschmidt } 1746a32305bfSBrian W Hart *pdev->dev.dma_mask = dma_mask; 17475d2aa710SAlistair Popple 17485d2aa710SAlistair Popple /* Update peer npu devices */ 17495d2aa710SAlistair Popple if (pe->flags & PNV_IODA_PE_PEER) 1750419dbd5eSAlistair Popple for (i = 0; i < PNV_IODA_MAX_PEER_PES; i++) { 1751419dbd5eSAlistair Popple if (!pe->peers[i]) 1752419dbd5eSAlistair Popple continue; 1753419dbd5eSAlistair Popple 17545d2aa710SAlistair Popple linked_npu_dev = pe->peers[i]->pdev; 17555d2aa710SAlistair Popple if (dma_get_mask(&linked_npu_dev->dev) != dma_mask) 17565d2aa710SAlistair Popple dma_set_mask(&linked_npu_dev->dev, dma_mask); 17575d2aa710SAlistair Popple } 17585d2aa710SAlistair Popple 1759cd15b048SBenjamin Herrenschmidt return 0; 1760cd15b048SBenjamin Herrenschmidt } 1761cd15b048SBenjamin Herrenschmidt 176253522982SAndrew Donnellan static u64 pnv_pci_ioda_dma_get_required_mask(struct pci_dev *pdev) 1763fe7e85c6SGavin Shan { 176453522982SAndrew Donnellan struct pci_controller *hose = pci_bus_to_host(pdev->bus); 176553522982SAndrew Donnellan struct pnv_phb *phb = hose->private_data; 1766fe7e85c6SGavin Shan struct pci_dn *pdn = pci_get_pdn(pdev); 1767fe7e85c6SGavin Shan struct pnv_ioda_pe *pe; 1768fe7e85c6SGavin Shan u64 end, mask; 1769fe7e85c6SGavin Shan 1770fe7e85c6SGavin Shan if (WARN_ON(!pdn || pdn->pe_number == IODA_INVALID_PE)) 1771fe7e85c6SGavin Shan return 0; 1772fe7e85c6SGavin Shan 1773fe7e85c6SGavin Shan pe = &phb->ioda.pe_array[pdn->pe_number]; 1774fe7e85c6SGavin Shan if (!pe->tce_bypass_enabled) 1775fe7e85c6SGavin Shan return __dma_get_required_mask(&pdev->dev); 1776fe7e85c6SGavin Shan 1777fe7e85c6SGavin Shan 1778fe7e85c6SGavin Shan end = pe->tce_bypass_base + memblock_end_of_DRAM(); 1779fe7e85c6SGavin Shan mask = 1ULL << (fls64(end) - 1); 1780fe7e85c6SGavin Shan mask += mask - 1; 1781fe7e85c6SGavin Shan 1782fe7e85c6SGavin Shan return mask; 1783fe7e85c6SGavin Shan } 1784fe7e85c6SGavin Shan 1785dff4a39eSGavin Shan static void pnv_ioda_setup_bus_dma(struct pnv_ioda_pe *pe, 1786ea30e99eSAlexey Kardashevskiy struct pci_bus *bus) 178774251fe2SBenjamin Herrenschmidt { 178874251fe2SBenjamin Herrenschmidt struct pci_dev *dev; 178974251fe2SBenjamin Herrenschmidt 179074251fe2SBenjamin Herrenschmidt list_for_each_entry(dev, &bus->devices, bus_list) { 1791b348aa65SAlexey Kardashevskiy set_iommu_table_base(&dev->dev, pe->table_group.tables[0]); 1792e91c2511SBenjamin Herrenschmidt set_dma_offset(&dev->dev, pe->tce_bypass_base); 17934617082eSAlexey Kardashevskiy iommu_add_device(&dev->dev); 1794dff4a39eSGavin Shan 17955c89a87dSAlexey Kardashevskiy if ((pe->flags & PNV_IODA_PE_BUS_ALL) && dev->subordinate) 1796ea30e99eSAlexey Kardashevskiy pnv_ioda_setup_bus_dma(pe, dev->subordinate); 179774251fe2SBenjamin Herrenschmidt } 179874251fe2SBenjamin Herrenschmidt } 179974251fe2SBenjamin Herrenschmidt 1800decbda25SAlexey Kardashevskiy static void pnv_pci_ioda1_tce_invalidate(struct iommu_table *tbl, 1801decbda25SAlexey Kardashevskiy unsigned long index, unsigned long npages, bool rm) 18024cce9550SGavin Shan { 18030eaf4defSAlexey Kardashevskiy struct iommu_table_group_link *tgl = list_first_entry_or_null( 18040eaf4defSAlexey Kardashevskiy &tbl->it_group_list, struct iommu_table_group_link, 18050eaf4defSAlexey Kardashevskiy next); 18060eaf4defSAlexey Kardashevskiy struct pnv_ioda_pe *pe = container_of(tgl->table_group, 1807b348aa65SAlexey Kardashevskiy struct pnv_ioda_pe, table_group); 18083ad26e5cSBenjamin Herrenschmidt __be64 __iomem *invalidate = rm ? 18095780fb04SAlexey Kardashevskiy (__be64 __iomem *)pe->phb->ioda.tce_inval_reg_phys : 18105780fb04SAlexey Kardashevskiy pe->phb->ioda.tce_inval_reg; 18114cce9550SGavin Shan unsigned long start, end, inc; 1812b0376c9bSAlexey Kardashevskiy const unsigned shift = tbl->it_page_shift; 18134cce9550SGavin Shan 1814decbda25SAlexey Kardashevskiy start = __pa(((__be64 *)tbl->it_base) + index - tbl->it_offset); 1815decbda25SAlexey Kardashevskiy end = __pa(((__be64 *)tbl->it_base) + index - tbl->it_offset + 1816decbda25SAlexey Kardashevskiy npages - 1); 18174cce9550SGavin Shan 18184cce9550SGavin Shan /* BML uses this case for p6/p7/galaxy2: Shift addr and put in node */ 18194cce9550SGavin Shan if (tbl->it_busno) { 1820b0376c9bSAlexey Kardashevskiy start <<= shift; 1821b0376c9bSAlexey Kardashevskiy end <<= shift; 1822b0376c9bSAlexey Kardashevskiy inc = 128ull << shift; 18234cce9550SGavin Shan start |= tbl->it_busno; 18244cce9550SGavin Shan end |= tbl->it_busno; 18254cce9550SGavin Shan } else if (tbl->it_type & TCE_PCI_SWINV_PAIR) { 18264cce9550SGavin Shan /* p7ioc-style invalidation, 2 TCEs per write */ 18274cce9550SGavin Shan start |= (1ull << 63); 18284cce9550SGavin Shan end |= (1ull << 63); 18294cce9550SGavin Shan inc = 16; 18304cce9550SGavin Shan } else { 18314cce9550SGavin Shan /* Default (older HW) */ 18324cce9550SGavin Shan inc = 128; 18334cce9550SGavin Shan } 18344cce9550SGavin Shan 18354cce9550SGavin Shan end |= inc - 1; /* round up end to be different than start */ 18364cce9550SGavin Shan 18374cce9550SGavin Shan mb(); /* Ensure above stores are visible */ 18384cce9550SGavin Shan while (start <= end) { 18398e0a1611SAlexey Kardashevskiy if (rm) 18403ad26e5cSBenjamin Herrenschmidt __raw_rm_writeq(cpu_to_be64(start), invalidate); 18418e0a1611SAlexey Kardashevskiy else 18423a1a4661SBenjamin Herrenschmidt __raw_writeq(cpu_to_be64(start), invalidate); 18434cce9550SGavin Shan start += inc; 18444cce9550SGavin Shan } 18454cce9550SGavin Shan 18464cce9550SGavin Shan /* 18474cce9550SGavin Shan * The iommu layer will do another mb() for us on build() 18484cce9550SGavin Shan * and we don't care on free() 18494cce9550SGavin Shan */ 18504cce9550SGavin Shan } 18514cce9550SGavin Shan 1852decbda25SAlexey Kardashevskiy static int pnv_ioda1_tce_build(struct iommu_table *tbl, long index, 1853decbda25SAlexey Kardashevskiy long npages, unsigned long uaddr, 1854decbda25SAlexey Kardashevskiy enum dma_data_direction direction, 1855decbda25SAlexey Kardashevskiy struct dma_attrs *attrs) 1856decbda25SAlexey Kardashevskiy { 1857decbda25SAlexey Kardashevskiy int ret = pnv_tce_build(tbl, index, npages, uaddr, direction, 1858decbda25SAlexey Kardashevskiy attrs); 1859decbda25SAlexey Kardashevskiy 1860decbda25SAlexey Kardashevskiy if (!ret && (tbl->it_type & TCE_PCI_SWINV_CREATE)) 1861decbda25SAlexey Kardashevskiy pnv_pci_ioda1_tce_invalidate(tbl, index, npages, false); 1862decbda25SAlexey Kardashevskiy 1863decbda25SAlexey Kardashevskiy return ret; 1864decbda25SAlexey Kardashevskiy } 1865decbda25SAlexey Kardashevskiy 186605c6cfb9SAlexey Kardashevskiy #ifdef CONFIG_IOMMU_API 186705c6cfb9SAlexey Kardashevskiy static int pnv_ioda1_tce_xchg(struct iommu_table *tbl, long index, 186805c6cfb9SAlexey Kardashevskiy unsigned long *hpa, enum dma_data_direction *direction) 186905c6cfb9SAlexey Kardashevskiy { 187005c6cfb9SAlexey Kardashevskiy long ret = pnv_tce_xchg(tbl, index, hpa, direction); 187105c6cfb9SAlexey Kardashevskiy 187205c6cfb9SAlexey Kardashevskiy if (!ret && (tbl->it_type & 187305c6cfb9SAlexey Kardashevskiy (TCE_PCI_SWINV_CREATE | TCE_PCI_SWINV_FREE))) 187405c6cfb9SAlexey Kardashevskiy pnv_pci_ioda1_tce_invalidate(tbl, index, 1, false); 187505c6cfb9SAlexey Kardashevskiy 187605c6cfb9SAlexey Kardashevskiy return ret; 187705c6cfb9SAlexey Kardashevskiy } 187805c6cfb9SAlexey Kardashevskiy #endif 187905c6cfb9SAlexey Kardashevskiy 1880decbda25SAlexey Kardashevskiy static void pnv_ioda1_tce_free(struct iommu_table *tbl, long index, 1881decbda25SAlexey Kardashevskiy long npages) 1882decbda25SAlexey Kardashevskiy { 1883decbda25SAlexey Kardashevskiy pnv_tce_free(tbl, index, npages); 1884decbda25SAlexey Kardashevskiy 1885decbda25SAlexey Kardashevskiy if (tbl->it_type & TCE_PCI_SWINV_FREE) 1886decbda25SAlexey Kardashevskiy pnv_pci_ioda1_tce_invalidate(tbl, index, npages, false); 1887decbda25SAlexey Kardashevskiy } 1888decbda25SAlexey Kardashevskiy 1889da004c36SAlexey Kardashevskiy static struct iommu_table_ops pnv_ioda1_iommu_ops = { 1890decbda25SAlexey Kardashevskiy .set = pnv_ioda1_tce_build, 189105c6cfb9SAlexey Kardashevskiy #ifdef CONFIG_IOMMU_API 189205c6cfb9SAlexey Kardashevskiy .exchange = pnv_ioda1_tce_xchg, 189305c6cfb9SAlexey Kardashevskiy #endif 1894decbda25SAlexey Kardashevskiy .clear = pnv_ioda1_tce_free, 1895da004c36SAlexey Kardashevskiy .get = pnv_tce_get, 1896da004c36SAlexey Kardashevskiy }; 1897da004c36SAlexey Kardashevskiy 18985780fb04SAlexey Kardashevskiy static inline void pnv_pci_ioda2_tce_invalidate_entire(struct pnv_ioda_pe *pe) 18995780fb04SAlexey Kardashevskiy { 19005780fb04SAlexey Kardashevskiy /* 01xb - invalidate TCEs that match the specified PE# */ 19015780fb04SAlexey Kardashevskiy unsigned long val = (0x4ull << 60) | (pe->pe_number & 0xFF); 19025780fb04SAlexey Kardashevskiy struct pnv_phb *phb = pe->phb; 19035d2aa710SAlistair Popple struct pnv_ioda_pe *npe; 19045d2aa710SAlistair Popple int i; 19055780fb04SAlexey Kardashevskiy 19065780fb04SAlexey Kardashevskiy if (!phb->ioda.tce_inval_reg) 19075780fb04SAlexey Kardashevskiy return; 19085780fb04SAlexey Kardashevskiy 19095780fb04SAlexey Kardashevskiy mb(); /* Ensure above stores are visible */ 19105780fb04SAlexey Kardashevskiy __raw_writeq(cpu_to_be64(val), phb->ioda.tce_inval_reg); 19115d2aa710SAlistair Popple 19125d2aa710SAlistair Popple if (pe->flags & PNV_IODA_PE_PEER) 19135d2aa710SAlistair Popple for (i = 0; i < PNV_IODA_MAX_PEER_PES; i++) { 19145d2aa710SAlistair Popple npe = pe->peers[i]; 19155d2aa710SAlistair Popple if (!npe || npe->phb->type != PNV_PHB_NPU) 19165d2aa710SAlistair Popple continue; 19175d2aa710SAlistair Popple 19185d2aa710SAlistair Popple pnv_npu_tce_invalidate_entire(npe); 19195d2aa710SAlistair Popple } 19205780fb04SAlexey Kardashevskiy } 19215780fb04SAlexey Kardashevskiy 1922e57080f1SAlexey Kardashevskiy static void pnv_pci_ioda2_do_tce_invalidate(unsigned pe_number, bool rm, 1923e57080f1SAlexey Kardashevskiy __be64 __iomem *invalidate, unsigned shift, 1924e57080f1SAlexey Kardashevskiy unsigned long index, unsigned long npages) 19254cce9550SGavin Shan { 19264cce9550SGavin Shan unsigned long start, end, inc; 19274cce9550SGavin Shan 19284cce9550SGavin Shan /* We'll invalidate DMA address in PE scope */ 1929b0376c9bSAlexey Kardashevskiy start = 0x2ull << 60; 1930e57080f1SAlexey Kardashevskiy start |= (pe_number & 0xFF); 19314cce9550SGavin Shan end = start; 19324cce9550SGavin Shan 19334cce9550SGavin Shan /* Figure out the start, end and step */ 1934decbda25SAlexey Kardashevskiy start |= (index << shift); 1935decbda25SAlexey Kardashevskiy end |= ((index + npages - 1) << shift); 1936b0376c9bSAlexey Kardashevskiy inc = (0x1ull << shift); 19374cce9550SGavin Shan mb(); 19384cce9550SGavin Shan 19394cce9550SGavin Shan while (start <= end) { 19408e0a1611SAlexey Kardashevskiy if (rm) 19413ad26e5cSBenjamin Herrenschmidt __raw_rm_writeq(cpu_to_be64(start), invalidate); 19428e0a1611SAlexey Kardashevskiy else 19433a1a4661SBenjamin Herrenschmidt __raw_writeq(cpu_to_be64(start), invalidate); 19444cce9550SGavin Shan start += inc; 19454cce9550SGavin Shan } 19464cce9550SGavin Shan } 19474cce9550SGavin Shan 1948e57080f1SAlexey Kardashevskiy static void pnv_pci_ioda2_tce_invalidate(struct iommu_table *tbl, 1949e57080f1SAlexey Kardashevskiy unsigned long index, unsigned long npages, bool rm) 1950e57080f1SAlexey Kardashevskiy { 1951e57080f1SAlexey Kardashevskiy struct iommu_table_group_link *tgl; 1952e57080f1SAlexey Kardashevskiy 1953e57080f1SAlexey Kardashevskiy list_for_each_entry_rcu(tgl, &tbl->it_group_list, next) { 19545d2aa710SAlistair Popple struct pnv_ioda_pe *npe; 1955e57080f1SAlexey Kardashevskiy struct pnv_ioda_pe *pe = container_of(tgl->table_group, 1956e57080f1SAlexey Kardashevskiy struct pnv_ioda_pe, table_group); 1957e57080f1SAlexey Kardashevskiy __be64 __iomem *invalidate = rm ? 1958e57080f1SAlexey Kardashevskiy (__be64 __iomem *)pe->phb->ioda.tce_inval_reg_phys : 1959e57080f1SAlexey Kardashevskiy pe->phb->ioda.tce_inval_reg; 19605d2aa710SAlistair Popple int i; 1961e57080f1SAlexey Kardashevskiy 1962e57080f1SAlexey Kardashevskiy pnv_pci_ioda2_do_tce_invalidate(pe->pe_number, rm, 1963e57080f1SAlexey Kardashevskiy invalidate, tbl->it_page_shift, 1964e57080f1SAlexey Kardashevskiy index, npages); 19655d2aa710SAlistair Popple 19665d2aa710SAlistair Popple if (pe->flags & PNV_IODA_PE_PEER) 19675d2aa710SAlistair Popple /* Invalidate PEs using the same TCE table */ 19685d2aa710SAlistair Popple for (i = 0; i < PNV_IODA_MAX_PEER_PES; i++) { 19695d2aa710SAlistair Popple npe = pe->peers[i]; 19705d2aa710SAlistair Popple if (!npe || npe->phb->type != PNV_PHB_NPU) 19715d2aa710SAlistair Popple continue; 19725d2aa710SAlistair Popple 19735d2aa710SAlistair Popple pnv_npu_tce_invalidate(npe, tbl, index, 19745d2aa710SAlistair Popple npages, rm); 19755d2aa710SAlistair Popple } 1976e57080f1SAlexey Kardashevskiy } 1977e57080f1SAlexey Kardashevskiy } 1978e57080f1SAlexey Kardashevskiy 1979decbda25SAlexey Kardashevskiy static int pnv_ioda2_tce_build(struct iommu_table *tbl, long index, 1980decbda25SAlexey Kardashevskiy long npages, unsigned long uaddr, 1981decbda25SAlexey Kardashevskiy enum dma_data_direction direction, 1982decbda25SAlexey Kardashevskiy struct dma_attrs *attrs) 19834cce9550SGavin Shan { 1984decbda25SAlexey Kardashevskiy int ret = pnv_tce_build(tbl, index, npages, uaddr, direction, 1985decbda25SAlexey Kardashevskiy attrs); 19864cce9550SGavin Shan 1987decbda25SAlexey Kardashevskiy if (!ret && (tbl->it_type & TCE_PCI_SWINV_CREATE)) 1988decbda25SAlexey Kardashevskiy pnv_pci_ioda2_tce_invalidate(tbl, index, npages, false); 1989decbda25SAlexey Kardashevskiy 1990decbda25SAlexey Kardashevskiy return ret; 1991decbda25SAlexey Kardashevskiy } 1992decbda25SAlexey Kardashevskiy 199305c6cfb9SAlexey Kardashevskiy #ifdef CONFIG_IOMMU_API 199405c6cfb9SAlexey Kardashevskiy static int pnv_ioda2_tce_xchg(struct iommu_table *tbl, long index, 199505c6cfb9SAlexey Kardashevskiy unsigned long *hpa, enum dma_data_direction *direction) 199605c6cfb9SAlexey Kardashevskiy { 199705c6cfb9SAlexey Kardashevskiy long ret = pnv_tce_xchg(tbl, index, hpa, direction); 199805c6cfb9SAlexey Kardashevskiy 199905c6cfb9SAlexey Kardashevskiy if (!ret && (tbl->it_type & 200005c6cfb9SAlexey Kardashevskiy (TCE_PCI_SWINV_CREATE | TCE_PCI_SWINV_FREE))) 200105c6cfb9SAlexey Kardashevskiy pnv_pci_ioda2_tce_invalidate(tbl, index, 1, false); 200205c6cfb9SAlexey Kardashevskiy 200305c6cfb9SAlexey Kardashevskiy return ret; 200405c6cfb9SAlexey Kardashevskiy } 200505c6cfb9SAlexey Kardashevskiy #endif 200605c6cfb9SAlexey Kardashevskiy 2007decbda25SAlexey Kardashevskiy static void pnv_ioda2_tce_free(struct iommu_table *tbl, long index, 2008decbda25SAlexey Kardashevskiy long npages) 2009decbda25SAlexey Kardashevskiy { 2010decbda25SAlexey Kardashevskiy pnv_tce_free(tbl, index, npages); 2011decbda25SAlexey Kardashevskiy 2012decbda25SAlexey Kardashevskiy if (tbl->it_type & TCE_PCI_SWINV_FREE) 2013decbda25SAlexey Kardashevskiy pnv_pci_ioda2_tce_invalidate(tbl, index, npages, false); 20144cce9550SGavin Shan } 20154cce9550SGavin Shan 20164793d65dSAlexey Kardashevskiy static void pnv_ioda2_table_free(struct iommu_table *tbl) 20174793d65dSAlexey Kardashevskiy { 20184793d65dSAlexey Kardashevskiy pnv_pci_ioda2_table_free_pages(tbl); 20194793d65dSAlexey Kardashevskiy iommu_free_table(tbl, "pnv"); 20204793d65dSAlexey Kardashevskiy } 20214793d65dSAlexey Kardashevskiy 2022da004c36SAlexey Kardashevskiy static struct iommu_table_ops pnv_ioda2_iommu_ops = { 2023decbda25SAlexey Kardashevskiy .set = pnv_ioda2_tce_build, 202405c6cfb9SAlexey Kardashevskiy #ifdef CONFIG_IOMMU_API 202505c6cfb9SAlexey Kardashevskiy .exchange = pnv_ioda2_tce_xchg, 202605c6cfb9SAlexey Kardashevskiy #endif 2027decbda25SAlexey Kardashevskiy .clear = pnv_ioda2_tce_free, 2028da004c36SAlexey Kardashevskiy .get = pnv_tce_get, 20294793d65dSAlexey Kardashevskiy .free = pnv_ioda2_table_free, 2030da004c36SAlexey Kardashevskiy }; 2031da004c36SAlexey Kardashevskiy 2032b30d936fSGavin Shan static void pnv_pci_ioda1_setup_dma_pe(struct pnv_phb *phb, 2033b30d936fSGavin Shan struct pnv_ioda_pe *pe, 2034b30d936fSGavin Shan unsigned int base, 2035184cd4a3SBenjamin Herrenschmidt unsigned int segs) 2036184cd4a3SBenjamin Herrenschmidt { 2037184cd4a3SBenjamin Herrenschmidt 2038184cd4a3SBenjamin Herrenschmidt struct page *tce_mem = NULL; 2039184cd4a3SBenjamin Herrenschmidt struct iommu_table *tbl; 2040184cd4a3SBenjamin Herrenschmidt unsigned int i; 2041184cd4a3SBenjamin Herrenschmidt int64_t rc; 2042184cd4a3SBenjamin Herrenschmidt void *addr; 2043184cd4a3SBenjamin Herrenschmidt 2044184cd4a3SBenjamin Herrenschmidt /* XXX FIXME: Handle 64-bit only DMA devices */ 2045184cd4a3SBenjamin Herrenschmidt /* XXX FIXME: Provide 64-bit DMA facilities & non-4K TCE tables etc.. */ 2046184cd4a3SBenjamin Herrenschmidt /* XXX FIXME: Allocate multi-level tables on PHB3 */ 2047184cd4a3SBenjamin Herrenschmidt 2048184cd4a3SBenjamin Herrenschmidt /* We shouldn't already have a 32-bit DMA associated */ 2049184cd4a3SBenjamin Herrenschmidt if (WARN_ON(pe->tce32_seg >= 0)) 2050184cd4a3SBenjamin Herrenschmidt return; 2051184cd4a3SBenjamin Herrenschmidt 20520eaf4defSAlexey Kardashevskiy tbl = pnv_pci_table_alloc(phb->hose->node); 2053b348aa65SAlexey Kardashevskiy iommu_register_group(&pe->table_group, phb->hose->global_number, 2054b348aa65SAlexey Kardashevskiy pe->pe_number); 20550eaf4defSAlexey Kardashevskiy pnv_pci_link_table_and_group(phb->hose->node, 0, tbl, &pe->table_group); 2056c5773822SAlexey Kardashevskiy 2057184cd4a3SBenjamin Herrenschmidt /* Grab a 32-bit TCE table */ 2058184cd4a3SBenjamin Herrenschmidt pe->tce32_seg = base; 2059184cd4a3SBenjamin Herrenschmidt pe_info(pe, " Setting up 32-bit TCE table at %08x..%08x\n", 2060184cd4a3SBenjamin Herrenschmidt (base << 28), ((base + segs) << 28) - 1); 2061184cd4a3SBenjamin Herrenschmidt 2062184cd4a3SBenjamin Herrenschmidt /* XXX Currently, we allocate one big contiguous table for the 2063184cd4a3SBenjamin Herrenschmidt * TCEs. We only really need one chunk per 256M of TCE space 2064184cd4a3SBenjamin Herrenschmidt * (ie per segment) but that's an optimization for later, it 2065184cd4a3SBenjamin Herrenschmidt * requires some added smarts with our get/put_tce implementation 2066184cd4a3SBenjamin Herrenschmidt */ 2067184cd4a3SBenjamin Herrenschmidt tce_mem = alloc_pages_node(phb->hose->node, GFP_KERNEL, 2068184cd4a3SBenjamin Herrenschmidt get_order(TCE32_TABLE_SIZE * segs)); 2069184cd4a3SBenjamin Herrenschmidt if (!tce_mem) { 2070184cd4a3SBenjamin Herrenschmidt pe_err(pe, " Failed to allocate a 32-bit TCE memory\n"); 2071184cd4a3SBenjamin Herrenschmidt goto fail; 2072184cd4a3SBenjamin Herrenschmidt } 2073184cd4a3SBenjamin Herrenschmidt addr = page_address(tce_mem); 2074184cd4a3SBenjamin Herrenschmidt memset(addr, 0, TCE32_TABLE_SIZE * segs); 2075184cd4a3SBenjamin Herrenschmidt 2076184cd4a3SBenjamin Herrenschmidt /* Configure HW */ 2077184cd4a3SBenjamin Herrenschmidt for (i = 0; i < segs; i++) { 2078184cd4a3SBenjamin Herrenschmidt rc = opal_pci_map_pe_dma_window(phb->opal_id, 2079184cd4a3SBenjamin Herrenschmidt pe->pe_number, 2080184cd4a3SBenjamin Herrenschmidt base + i, 1, 2081184cd4a3SBenjamin Herrenschmidt __pa(addr) + TCE32_TABLE_SIZE * i, 2082184cd4a3SBenjamin Herrenschmidt TCE32_TABLE_SIZE, 0x1000); 2083184cd4a3SBenjamin Herrenschmidt if (rc) { 2084184cd4a3SBenjamin Herrenschmidt pe_err(pe, " Failed to configure 32-bit TCE table," 2085184cd4a3SBenjamin Herrenschmidt " err %ld\n", rc); 2086184cd4a3SBenjamin Herrenschmidt goto fail; 2087184cd4a3SBenjamin Herrenschmidt } 2088184cd4a3SBenjamin Herrenschmidt } 2089184cd4a3SBenjamin Herrenschmidt 2090184cd4a3SBenjamin Herrenschmidt /* Setup linux iommu table */ 2091184cd4a3SBenjamin Herrenschmidt pnv_pci_setup_iommu_table(tbl, addr, TCE32_TABLE_SIZE * segs, 20928fa5d454SAlexey Kardashevskiy base << 28, IOMMU_PAGE_SHIFT_4K); 2093184cd4a3SBenjamin Herrenschmidt 2094184cd4a3SBenjamin Herrenschmidt /* OPAL variant of P7IOC SW invalidated TCEs */ 20955780fb04SAlexey Kardashevskiy if (phb->ioda.tce_inval_reg) 209665fd766bSGavin Shan tbl->it_type |= (TCE_PCI_SWINV_CREATE | 209765fd766bSGavin Shan TCE_PCI_SWINV_FREE | 209865fd766bSGavin Shan TCE_PCI_SWINV_PAIR); 20995780fb04SAlexey Kardashevskiy 2100da004c36SAlexey Kardashevskiy tbl->it_ops = &pnv_ioda1_iommu_ops; 21014793d65dSAlexey Kardashevskiy pe->table_group.tce32_start = tbl->it_offset << tbl->it_page_shift; 21024793d65dSAlexey Kardashevskiy pe->table_group.tce32_size = tbl->it_size << tbl->it_page_shift; 2103184cd4a3SBenjamin Herrenschmidt iommu_init_table(tbl, phb->hose->node); 2104184cd4a3SBenjamin Herrenschmidt 2105781a868fSWei Yang if (pe->flags & PNV_IODA_PE_DEV) { 21064617082eSAlexey Kardashevskiy /* 21074617082eSAlexey Kardashevskiy * Setting table base here only for carrying iommu_group 21084617082eSAlexey Kardashevskiy * further down to let iommu_add_device() do the job. 21094617082eSAlexey Kardashevskiy * pnv_pci_ioda_dma_dev_setup will override it later anyway. 21104617082eSAlexey Kardashevskiy */ 21114617082eSAlexey Kardashevskiy set_iommu_table_base(&pe->pdev->dev, tbl); 21124617082eSAlexey Kardashevskiy iommu_add_device(&pe->pdev->dev); 2113c5773822SAlexey Kardashevskiy } else if (pe->flags & (PNV_IODA_PE_BUS | PNV_IODA_PE_BUS_ALL)) 2114ea30e99eSAlexey Kardashevskiy pnv_ioda_setup_bus_dma(pe, pe->pbus); 211574251fe2SBenjamin Herrenschmidt 2116184cd4a3SBenjamin Herrenschmidt return; 2117184cd4a3SBenjamin Herrenschmidt fail: 2118184cd4a3SBenjamin Herrenschmidt /* XXX Failure: Try to fallback to 64-bit only ? */ 2119184cd4a3SBenjamin Herrenschmidt if (pe->tce32_seg >= 0) 2120184cd4a3SBenjamin Herrenschmidt pe->tce32_seg = -1; 2121184cd4a3SBenjamin Herrenschmidt if (tce_mem) 2122184cd4a3SBenjamin Herrenschmidt __free_pages(tce_mem, get_order(TCE32_TABLE_SIZE * segs)); 21230eaf4defSAlexey Kardashevskiy if (tbl) { 21240eaf4defSAlexey Kardashevskiy pnv_pci_unlink_table_and_group(tbl, &pe->table_group); 21250eaf4defSAlexey Kardashevskiy iommu_free_table(tbl, "pnv"); 21260eaf4defSAlexey Kardashevskiy } 2127184cd4a3SBenjamin Herrenschmidt } 2128184cd4a3SBenjamin Herrenschmidt 212943cb60abSAlexey Kardashevskiy static long pnv_pci_ioda2_set_window(struct iommu_table_group *table_group, 213043cb60abSAlexey Kardashevskiy int num, struct iommu_table *tbl) 213143cb60abSAlexey Kardashevskiy { 213243cb60abSAlexey Kardashevskiy struct pnv_ioda_pe *pe = container_of(table_group, struct pnv_ioda_pe, 213343cb60abSAlexey Kardashevskiy table_group); 213443cb60abSAlexey Kardashevskiy struct pnv_phb *phb = pe->phb; 213543cb60abSAlexey Kardashevskiy int64_t rc; 2136bbb845c4SAlexey Kardashevskiy const unsigned long size = tbl->it_indirect_levels ? 2137bbb845c4SAlexey Kardashevskiy tbl->it_level_size : tbl->it_size; 213843cb60abSAlexey Kardashevskiy const __u64 start_addr = tbl->it_offset << tbl->it_page_shift; 213943cb60abSAlexey Kardashevskiy const __u64 win_size = tbl->it_size << tbl->it_page_shift; 214043cb60abSAlexey Kardashevskiy 21414793d65dSAlexey Kardashevskiy pe_info(pe, "Setting up window#%d %llx..%llx pg=%x\n", num, 214243cb60abSAlexey Kardashevskiy start_addr, start_addr + win_size - 1, 214343cb60abSAlexey Kardashevskiy IOMMU_PAGE_SIZE(tbl)); 214443cb60abSAlexey Kardashevskiy 214543cb60abSAlexey Kardashevskiy /* 214643cb60abSAlexey Kardashevskiy * Map TCE table through TVT. The TVE index is the PE number 214743cb60abSAlexey Kardashevskiy * shifted by 1 bit for 32-bits DMA space. 214843cb60abSAlexey Kardashevskiy */ 214943cb60abSAlexey Kardashevskiy rc = opal_pci_map_pe_dma_window(phb->opal_id, 215043cb60abSAlexey Kardashevskiy pe->pe_number, 21514793d65dSAlexey Kardashevskiy (pe->pe_number << 1) + num, 2152bbb845c4SAlexey Kardashevskiy tbl->it_indirect_levels + 1, 215343cb60abSAlexey Kardashevskiy __pa(tbl->it_base), 2154bbb845c4SAlexey Kardashevskiy size << 3, 215543cb60abSAlexey Kardashevskiy IOMMU_PAGE_SIZE(tbl)); 215643cb60abSAlexey Kardashevskiy if (rc) { 215743cb60abSAlexey Kardashevskiy pe_err(pe, "Failed to configure TCE table, err %ld\n", rc); 215843cb60abSAlexey Kardashevskiy return rc; 215943cb60abSAlexey Kardashevskiy } 216043cb60abSAlexey Kardashevskiy 216143cb60abSAlexey Kardashevskiy pnv_pci_link_table_and_group(phb->hose->node, num, 216243cb60abSAlexey Kardashevskiy tbl, &pe->table_group); 216343cb60abSAlexey Kardashevskiy pnv_pci_ioda2_tce_invalidate_entire(pe); 216443cb60abSAlexey Kardashevskiy 216543cb60abSAlexey Kardashevskiy return 0; 216643cb60abSAlexey Kardashevskiy } 216743cb60abSAlexey Kardashevskiy 2168f87a8864SAlexey Kardashevskiy static void pnv_pci_ioda2_set_bypass(struct pnv_ioda_pe *pe, bool enable) 2169cd15b048SBenjamin Herrenschmidt { 2170cd15b048SBenjamin Herrenschmidt uint16_t window_id = (pe->pe_number << 1 ) + 1; 2171cd15b048SBenjamin Herrenschmidt int64_t rc; 2172cd15b048SBenjamin Herrenschmidt 2173cd15b048SBenjamin Herrenschmidt pe_info(pe, "%sabling 64-bit DMA bypass\n", enable ? "En" : "Dis"); 2174cd15b048SBenjamin Herrenschmidt if (enable) { 2175cd15b048SBenjamin Herrenschmidt phys_addr_t top = memblock_end_of_DRAM(); 2176cd15b048SBenjamin Herrenschmidt 2177cd15b048SBenjamin Herrenschmidt top = roundup_pow_of_two(top); 2178cd15b048SBenjamin Herrenschmidt rc = opal_pci_map_pe_dma_window_real(pe->phb->opal_id, 2179cd15b048SBenjamin Herrenschmidt pe->pe_number, 2180cd15b048SBenjamin Herrenschmidt window_id, 2181cd15b048SBenjamin Herrenschmidt pe->tce_bypass_base, 2182cd15b048SBenjamin Herrenschmidt top); 2183cd15b048SBenjamin Herrenschmidt } else { 2184cd15b048SBenjamin Herrenschmidt rc = opal_pci_map_pe_dma_window_real(pe->phb->opal_id, 2185cd15b048SBenjamin Herrenschmidt pe->pe_number, 2186cd15b048SBenjamin Herrenschmidt window_id, 2187cd15b048SBenjamin Herrenschmidt pe->tce_bypass_base, 2188cd15b048SBenjamin Herrenschmidt 0); 2189cd15b048SBenjamin Herrenschmidt } 2190cd15b048SBenjamin Herrenschmidt if (rc) 2191cd15b048SBenjamin Herrenschmidt pe_err(pe, "OPAL error %lld configuring bypass window\n", rc); 2192cd15b048SBenjamin Herrenschmidt else 2193cd15b048SBenjamin Herrenschmidt pe->tce_bypass_enabled = enable; 2194cd15b048SBenjamin Herrenschmidt } 2195cd15b048SBenjamin Herrenschmidt 21964793d65dSAlexey Kardashevskiy static long pnv_pci_ioda2_table_alloc_pages(int nid, __u64 bus_offset, 21974793d65dSAlexey Kardashevskiy __u32 page_shift, __u64 window_size, __u32 levels, 21984793d65dSAlexey Kardashevskiy struct iommu_table *tbl); 21994793d65dSAlexey Kardashevskiy 22004793d65dSAlexey Kardashevskiy static long pnv_pci_ioda2_create_table(struct iommu_table_group *table_group, 22014793d65dSAlexey Kardashevskiy int num, __u32 page_shift, __u64 window_size, __u32 levels, 22024793d65dSAlexey Kardashevskiy struct iommu_table **ptbl) 22034793d65dSAlexey Kardashevskiy { 22044793d65dSAlexey Kardashevskiy struct pnv_ioda_pe *pe = container_of(table_group, struct pnv_ioda_pe, 22054793d65dSAlexey Kardashevskiy table_group); 22064793d65dSAlexey Kardashevskiy int nid = pe->phb->hose->node; 22074793d65dSAlexey Kardashevskiy __u64 bus_offset = num ? pe->tce_bypass_base : table_group->tce32_start; 22084793d65dSAlexey Kardashevskiy long ret; 22094793d65dSAlexey Kardashevskiy struct iommu_table *tbl; 22104793d65dSAlexey Kardashevskiy 22114793d65dSAlexey Kardashevskiy tbl = pnv_pci_table_alloc(nid); 22124793d65dSAlexey Kardashevskiy if (!tbl) 22134793d65dSAlexey Kardashevskiy return -ENOMEM; 22144793d65dSAlexey Kardashevskiy 22154793d65dSAlexey Kardashevskiy ret = pnv_pci_ioda2_table_alloc_pages(nid, 22164793d65dSAlexey Kardashevskiy bus_offset, page_shift, window_size, 22174793d65dSAlexey Kardashevskiy levels, tbl); 22184793d65dSAlexey Kardashevskiy if (ret) { 22194793d65dSAlexey Kardashevskiy iommu_free_table(tbl, "pnv"); 22204793d65dSAlexey Kardashevskiy return ret; 22214793d65dSAlexey Kardashevskiy } 22224793d65dSAlexey Kardashevskiy 22234793d65dSAlexey Kardashevskiy tbl->it_ops = &pnv_ioda2_iommu_ops; 22244793d65dSAlexey Kardashevskiy if (pe->phb->ioda.tce_inval_reg) 22254793d65dSAlexey Kardashevskiy tbl->it_type |= (TCE_PCI_SWINV_CREATE | TCE_PCI_SWINV_FREE); 22264793d65dSAlexey Kardashevskiy 22274793d65dSAlexey Kardashevskiy *ptbl = tbl; 22284793d65dSAlexey Kardashevskiy 22294793d65dSAlexey Kardashevskiy return 0; 22304793d65dSAlexey Kardashevskiy } 22314793d65dSAlexey Kardashevskiy 223246d3e1e1SAlexey Kardashevskiy static long pnv_pci_ioda2_setup_default_config(struct pnv_ioda_pe *pe) 223346d3e1e1SAlexey Kardashevskiy { 223446d3e1e1SAlexey Kardashevskiy struct iommu_table *tbl = NULL; 223546d3e1e1SAlexey Kardashevskiy long rc; 223646d3e1e1SAlexey Kardashevskiy 2237bb005455SNishanth Aravamudan /* 2238fa144869SNishanth Aravamudan * crashkernel= specifies the kdump kernel's maximum memory at 2239fa144869SNishanth Aravamudan * some offset and there is no guaranteed the result is a power 2240fa144869SNishanth Aravamudan * of 2, which will cause errors later. 2241fa144869SNishanth Aravamudan */ 2242fa144869SNishanth Aravamudan const u64 max_memory = __rounddown_pow_of_two(memory_hotplug_max()); 2243fa144869SNishanth Aravamudan 2244fa144869SNishanth Aravamudan /* 2245bb005455SNishanth Aravamudan * In memory constrained environments, e.g. kdump kernel, the 2246bb005455SNishanth Aravamudan * DMA window can be larger than available memory, which will 2247bb005455SNishanth Aravamudan * cause errors later. 2248bb005455SNishanth Aravamudan */ 2249fa144869SNishanth Aravamudan const u64 window_size = min((u64)pe->table_group.tce32_size, max_memory); 2250bb005455SNishanth Aravamudan 225146d3e1e1SAlexey Kardashevskiy rc = pnv_pci_ioda2_create_table(&pe->table_group, 0, 225246d3e1e1SAlexey Kardashevskiy IOMMU_PAGE_SHIFT_4K, 2253bb005455SNishanth Aravamudan window_size, 225446d3e1e1SAlexey Kardashevskiy POWERNV_IOMMU_DEFAULT_LEVELS, &tbl); 225546d3e1e1SAlexey Kardashevskiy if (rc) { 225646d3e1e1SAlexey Kardashevskiy pe_err(pe, "Failed to create 32-bit TCE table, err %ld", 225746d3e1e1SAlexey Kardashevskiy rc); 225846d3e1e1SAlexey Kardashevskiy return rc; 225946d3e1e1SAlexey Kardashevskiy } 226046d3e1e1SAlexey Kardashevskiy 226146d3e1e1SAlexey Kardashevskiy iommu_init_table(tbl, pe->phb->hose->node); 226246d3e1e1SAlexey Kardashevskiy 226346d3e1e1SAlexey Kardashevskiy rc = pnv_pci_ioda2_set_window(&pe->table_group, 0, tbl); 226446d3e1e1SAlexey Kardashevskiy if (rc) { 226546d3e1e1SAlexey Kardashevskiy pe_err(pe, "Failed to configure 32-bit TCE table, err %ld\n", 226646d3e1e1SAlexey Kardashevskiy rc); 226746d3e1e1SAlexey Kardashevskiy pnv_ioda2_table_free(tbl); 226846d3e1e1SAlexey Kardashevskiy return rc; 226946d3e1e1SAlexey Kardashevskiy } 227046d3e1e1SAlexey Kardashevskiy 227146d3e1e1SAlexey Kardashevskiy if (!pnv_iommu_bypass_disabled) 227246d3e1e1SAlexey Kardashevskiy pnv_pci_ioda2_set_bypass(pe, true); 227346d3e1e1SAlexey Kardashevskiy 227446d3e1e1SAlexey Kardashevskiy /* OPAL variant of PHB3 invalidated TCEs */ 227546d3e1e1SAlexey Kardashevskiy if (pe->phb->ioda.tce_inval_reg) 227646d3e1e1SAlexey Kardashevskiy tbl->it_type |= (TCE_PCI_SWINV_CREATE | TCE_PCI_SWINV_FREE); 227746d3e1e1SAlexey Kardashevskiy 227846d3e1e1SAlexey Kardashevskiy /* 227946d3e1e1SAlexey Kardashevskiy * Setting table base here only for carrying iommu_group 228046d3e1e1SAlexey Kardashevskiy * further down to let iommu_add_device() do the job. 228146d3e1e1SAlexey Kardashevskiy * pnv_pci_ioda_dma_dev_setup will override it later anyway. 228246d3e1e1SAlexey Kardashevskiy */ 228346d3e1e1SAlexey Kardashevskiy if (pe->flags & PNV_IODA_PE_DEV) 228446d3e1e1SAlexey Kardashevskiy set_iommu_table_base(&pe->pdev->dev, tbl); 228546d3e1e1SAlexey Kardashevskiy 228646d3e1e1SAlexey Kardashevskiy return 0; 228746d3e1e1SAlexey Kardashevskiy } 228846d3e1e1SAlexey Kardashevskiy 2289b5926430SAlexey Kardashevskiy #if defined(CONFIG_IOMMU_API) || defined(CONFIG_PCI_IOV) 2290b5926430SAlexey Kardashevskiy static long pnv_pci_ioda2_unset_window(struct iommu_table_group *table_group, 2291b5926430SAlexey Kardashevskiy int num) 2292b5926430SAlexey Kardashevskiy { 2293b5926430SAlexey Kardashevskiy struct pnv_ioda_pe *pe = container_of(table_group, struct pnv_ioda_pe, 2294b5926430SAlexey Kardashevskiy table_group); 2295b5926430SAlexey Kardashevskiy struct pnv_phb *phb = pe->phb; 2296b5926430SAlexey Kardashevskiy long ret; 2297b5926430SAlexey Kardashevskiy 2298b5926430SAlexey Kardashevskiy pe_info(pe, "Removing DMA window #%d\n", num); 2299b5926430SAlexey Kardashevskiy 2300b5926430SAlexey Kardashevskiy ret = opal_pci_map_pe_dma_window(phb->opal_id, pe->pe_number, 2301b5926430SAlexey Kardashevskiy (pe->pe_number << 1) + num, 2302b5926430SAlexey Kardashevskiy 0/* levels */, 0/* table address */, 2303b5926430SAlexey Kardashevskiy 0/* table size */, 0/* page size */); 2304b5926430SAlexey Kardashevskiy if (ret) 2305b5926430SAlexey Kardashevskiy pe_warn(pe, "Unmapping failed, ret = %ld\n", ret); 2306b5926430SAlexey Kardashevskiy else 2307b5926430SAlexey Kardashevskiy pnv_pci_ioda2_tce_invalidate_entire(pe); 2308b5926430SAlexey Kardashevskiy 2309b5926430SAlexey Kardashevskiy pnv_pci_unlink_table_and_group(table_group->tables[num], table_group); 2310b5926430SAlexey Kardashevskiy 2311b5926430SAlexey Kardashevskiy return ret; 2312b5926430SAlexey Kardashevskiy } 2313b5926430SAlexey Kardashevskiy #endif 2314b5926430SAlexey Kardashevskiy 2315f87a8864SAlexey Kardashevskiy #ifdef CONFIG_IOMMU_API 231600547193SAlexey Kardashevskiy static unsigned long pnv_pci_ioda2_get_table_size(__u32 page_shift, 231700547193SAlexey Kardashevskiy __u64 window_size, __u32 levels) 231800547193SAlexey Kardashevskiy { 231900547193SAlexey Kardashevskiy unsigned long bytes = 0; 232000547193SAlexey Kardashevskiy const unsigned window_shift = ilog2(window_size); 232100547193SAlexey Kardashevskiy unsigned entries_shift = window_shift - page_shift; 232200547193SAlexey Kardashevskiy unsigned table_shift = entries_shift + 3; 232300547193SAlexey Kardashevskiy unsigned long tce_table_size = max(0x1000UL, 1UL << table_shift); 232400547193SAlexey Kardashevskiy unsigned long direct_table_size; 232500547193SAlexey Kardashevskiy 232600547193SAlexey Kardashevskiy if (!levels || (levels > POWERNV_IOMMU_MAX_LEVELS) || 232700547193SAlexey Kardashevskiy (window_size > memory_hotplug_max()) || 232800547193SAlexey Kardashevskiy !is_power_of_2(window_size)) 232900547193SAlexey Kardashevskiy return 0; 233000547193SAlexey Kardashevskiy 233100547193SAlexey Kardashevskiy /* Calculate a direct table size from window_size and levels */ 233200547193SAlexey Kardashevskiy entries_shift = (entries_shift + levels - 1) / levels; 233300547193SAlexey Kardashevskiy table_shift = entries_shift + 3; 233400547193SAlexey Kardashevskiy table_shift = max_t(unsigned, table_shift, PAGE_SHIFT); 233500547193SAlexey Kardashevskiy direct_table_size = 1UL << table_shift; 233600547193SAlexey Kardashevskiy 233700547193SAlexey Kardashevskiy for ( ; levels; --levels) { 233800547193SAlexey Kardashevskiy bytes += _ALIGN_UP(tce_table_size, direct_table_size); 233900547193SAlexey Kardashevskiy 234000547193SAlexey Kardashevskiy tce_table_size /= direct_table_size; 234100547193SAlexey Kardashevskiy tce_table_size <<= 3; 234200547193SAlexey Kardashevskiy tce_table_size = _ALIGN_UP(tce_table_size, direct_table_size); 234300547193SAlexey Kardashevskiy } 234400547193SAlexey Kardashevskiy 234500547193SAlexey Kardashevskiy return bytes; 234600547193SAlexey Kardashevskiy } 234700547193SAlexey Kardashevskiy 2348f87a8864SAlexey Kardashevskiy static void pnv_ioda2_take_ownership(struct iommu_table_group *table_group) 2349cd15b048SBenjamin Herrenschmidt { 2350f87a8864SAlexey Kardashevskiy struct pnv_ioda_pe *pe = container_of(table_group, struct pnv_ioda_pe, 2351f87a8864SAlexey Kardashevskiy table_group); 235246d3e1e1SAlexey Kardashevskiy /* Store @tbl as pnv_pci_ioda2_unset_window() resets it */ 235346d3e1e1SAlexey Kardashevskiy struct iommu_table *tbl = pe->table_group.tables[0]; 2354cd15b048SBenjamin Herrenschmidt 2355f87a8864SAlexey Kardashevskiy pnv_pci_ioda2_set_bypass(pe, false); 235646d3e1e1SAlexey Kardashevskiy pnv_pci_ioda2_unset_window(&pe->table_group, 0); 235746d3e1e1SAlexey Kardashevskiy pnv_ioda2_table_free(tbl); 2358cd15b048SBenjamin Herrenschmidt } 2359cd15b048SBenjamin Herrenschmidt 2360f87a8864SAlexey Kardashevskiy static void pnv_ioda2_release_ownership(struct iommu_table_group *table_group) 2361f87a8864SAlexey Kardashevskiy { 2362f87a8864SAlexey Kardashevskiy struct pnv_ioda_pe *pe = container_of(table_group, struct pnv_ioda_pe, 2363f87a8864SAlexey Kardashevskiy table_group); 2364f87a8864SAlexey Kardashevskiy 236546d3e1e1SAlexey Kardashevskiy pnv_pci_ioda2_setup_default_config(pe); 2366f87a8864SAlexey Kardashevskiy } 2367f87a8864SAlexey Kardashevskiy 2368f87a8864SAlexey Kardashevskiy static struct iommu_table_group_ops pnv_pci_ioda2_ops = { 236900547193SAlexey Kardashevskiy .get_table_size = pnv_pci_ioda2_get_table_size, 23704793d65dSAlexey Kardashevskiy .create_table = pnv_pci_ioda2_create_table, 23714793d65dSAlexey Kardashevskiy .set_window = pnv_pci_ioda2_set_window, 23724793d65dSAlexey Kardashevskiy .unset_window = pnv_pci_ioda2_unset_window, 2373f87a8864SAlexey Kardashevskiy .take_ownership = pnv_ioda2_take_ownership, 2374f87a8864SAlexey Kardashevskiy .release_ownership = pnv_ioda2_release_ownership, 2375f87a8864SAlexey Kardashevskiy }; 2376f87a8864SAlexey Kardashevskiy #endif 2377f87a8864SAlexey Kardashevskiy 23785780fb04SAlexey Kardashevskiy static void pnv_pci_ioda_setup_opal_tce_kill(struct pnv_phb *phb) 23795780fb04SAlexey Kardashevskiy { 23805780fb04SAlexey Kardashevskiy const __be64 *swinvp; 23815780fb04SAlexey Kardashevskiy 23825780fb04SAlexey Kardashevskiy /* OPAL variant of PHB3 invalidated TCEs */ 23835780fb04SAlexey Kardashevskiy swinvp = of_get_property(phb->hose->dn, "ibm,opal-tce-kill", NULL); 23845780fb04SAlexey Kardashevskiy if (!swinvp) 23855780fb04SAlexey Kardashevskiy return; 23865780fb04SAlexey Kardashevskiy 23875780fb04SAlexey Kardashevskiy phb->ioda.tce_inval_reg_phys = be64_to_cpup(swinvp); 23885780fb04SAlexey Kardashevskiy phb->ioda.tce_inval_reg = ioremap(phb->ioda.tce_inval_reg_phys, 8); 23895780fb04SAlexey Kardashevskiy } 23905780fb04SAlexey Kardashevskiy 2391bbb845c4SAlexey Kardashevskiy static __be64 *pnv_pci_ioda2_table_do_alloc_pages(int nid, unsigned shift, 2392bbb845c4SAlexey Kardashevskiy unsigned levels, unsigned long limit, 23933ba3a73eSAlexey Kardashevskiy unsigned long *current_offset, unsigned long *total_allocated) 2394aca6913fSAlexey Kardashevskiy { 2395aca6913fSAlexey Kardashevskiy struct page *tce_mem = NULL; 2396bbb845c4SAlexey Kardashevskiy __be64 *addr, *tmp; 2397aca6913fSAlexey Kardashevskiy unsigned order = max_t(unsigned, shift, PAGE_SHIFT) - PAGE_SHIFT; 2398bbb845c4SAlexey Kardashevskiy unsigned long allocated = 1UL << (order + PAGE_SHIFT); 2399bbb845c4SAlexey Kardashevskiy unsigned entries = 1UL << (shift - 3); 2400bbb845c4SAlexey Kardashevskiy long i; 2401aca6913fSAlexey Kardashevskiy 2402aca6913fSAlexey Kardashevskiy tce_mem = alloc_pages_node(nid, GFP_KERNEL, order); 2403aca6913fSAlexey Kardashevskiy if (!tce_mem) { 2404aca6913fSAlexey Kardashevskiy pr_err("Failed to allocate a TCE memory, order=%d\n", order); 2405aca6913fSAlexey Kardashevskiy return NULL; 2406aca6913fSAlexey Kardashevskiy } 2407aca6913fSAlexey Kardashevskiy addr = page_address(tce_mem); 2408bbb845c4SAlexey Kardashevskiy memset(addr, 0, allocated); 24093ba3a73eSAlexey Kardashevskiy *total_allocated += allocated; 2410bbb845c4SAlexey Kardashevskiy 2411bbb845c4SAlexey Kardashevskiy --levels; 2412bbb845c4SAlexey Kardashevskiy if (!levels) { 2413bbb845c4SAlexey Kardashevskiy *current_offset += allocated; 2414bbb845c4SAlexey Kardashevskiy return addr; 2415bbb845c4SAlexey Kardashevskiy } 2416bbb845c4SAlexey Kardashevskiy 2417bbb845c4SAlexey Kardashevskiy for (i = 0; i < entries; ++i) { 2418bbb845c4SAlexey Kardashevskiy tmp = pnv_pci_ioda2_table_do_alloc_pages(nid, shift, 24193ba3a73eSAlexey Kardashevskiy levels, limit, current_offset, total_allocated); 2420bbb845c4SAlexey Kardashevskiy if (!tmp) 2421bbb845c4SAlexey Kardashevskiy break; 2422bbb845c4SAlexey Kardashevskiy 2423bbb845c4SAlexey Kardashevskiy addr[i] = cpu_to_be64(__pa(tmp) | 2424bbb845c4SAlexey Kardashevskiy TCE_PCI_READ | TCE_PCI_WRITE); 2425bbb845c4SAlexey Kardashevskiy 2426bbb845c4SAlexey Kardashevskiy if (*current_offset >= limit) 2427bbb845c4SAlexey Kardashevskiy break; 2428bbb845c4SAlexey Kardashevskiy } 2429aca6913fSAlexey Kardashevskiy 2430aca6913fSAlexey Kardashevskiy return addr; 2431aca6913fSAlexey Kardashevskiy } 2432aca6913fSAlexey Kardashevskiy 2433bbb845c4SAlexey Kardashevskiy static void pnv_pci_ioda2_table_do_free_pages(__be64 *addr, 2434bbb845c4SAlexey Kardashevskiy unsigned long size, unsigned level); 2435bbb845c4SAlexey Kardashevskiy 2436aca6913fSAlexey Kardashevskiy static long pnv_pci_ioda2_table_alloc_pages(int nid, __u64 bus_offset, 2437bbb845c4SAlexey Kardashevskiy __u32 page_shift, __u64 window_size, __u32 levels, 2438bbb845c4SAlexey Kardashevskiy struct iommu_table *tbl) 2439aca6913fSAlexey Kardashevskiy { 2440aca6913fSAlexey Kardashevskiy void *addr; 24413ba3a73eSAlexey Kardashevskiy unsigned long offset = 0, level_shift, total_allocated = 0; 2442aca6913fSAlexey Kardashevskiy const unsigned window_shift = ilog2(window_size); 2443aca6913fSAlexey Kardashevskiy unsigned entries_shift = window_shift - page_shift; 2444aca6913fSAlexey Kardashevskiy unsigned table_shift = max_t(unsigned, entries_shift + 3, PAGE_SHIFT); 2445aca6913fSAlexey Kardashevskiy const unsigned long tce_table_size = 1UL << table_shift; 2446aca6913fSAlexey Kardashevskiy 2447bbb845c4SAlexey Kardashevskiy if (!levels || (levels > POWERNV_IOMMU_MAX_LEVELS)) 2448bbb845c4SAlexey Kardashevskiy return -EINVAL; 2449bbb845c4SAlexey Kardashevskiy 2450aca6913fSAlexey Kardashevskiy if ((window_size > memory_hotplug_max()) || !is_power_of_2(window_size)) 2451aca6913fSAlexey Kardashevskiy return -EINVAL; 2452aca6913fSAlexey Kardashevskiy 2453bbb845c4SAlexey Kardashevskiy /* Adjust direct table size from window_size and levels */ 2454bbb845c4SAlexey Kardashevskiy entries_shift = (entries_shift + levels - 1) / levels; 2455bbb845c4SAlexey Kardashevskiy level_shift = entries_shift + 3; 2456bbb845c4SAlexey Kardashevskiy level_shift = max_t(unsigned, level_shift, PAGE_SHIFT); 2457bbb845c4SAlexey Kardashevskiy 2458aca6913fSAlexey Kardashevskiy /* Allocate TCE table */ 2459bbb845c4SAlexey Kardashevskiy addr = pnv_pci_ioda2_table_do_alloc_pages(nid, level_shift, 24603ba3a73eSAlexey Kardashevskiy levels, tce_table_size, &offset, &total_allocated); 2461bbb845c4SAlexey Kardashevskiy 2462bbb845c4SAlexey Kardashevskiy /* addr==NULL means that the first level allocation failed */ 2463aca6913fSAlexey Kardashevskiy if (!addr) 2464aca6913fSAlexey Kardashevskiy return -ENOMEM; 2465aca6913fSAlexey Kardashevskiy 2466bbb845c4SAlexey Kardashevskiy /* 2467bbb845c4SAlexey Kardashevskiy * First level was allocated but some lower level failed as 2468bbb845c4SAlexey Kardashevskiy * we did not allocate as much as we wanted, 2469bbb845c4SAlexey Kardashevskiy * release partially allocated table. 2470bbb845c4SAlexey Kardashevskiy */ 2471bbb845c4SAlexey Kardashevskiy if (offset < tce_table_size) { 2472bbb845c4SAlexey Kardashevskiy pnv_pci_ioda2_table_do_free_pages(addr, 2473bbb845c4SAlexey Kardashevskiy 1ULL << (level_shift - 3), levels - 1); 2474bbb845c4SAlexey Kardashevskiy return -ENOMEM; 2475bbb845c4SAlexey Kardashevskiy } 2476bbb845c4SAlexey Kardashevskiy 2477aca6913fSAlexey Kardashevskiy /* Setup linux iommu table */ 2478aca6913fSAlexey Kardashevskiy pnv_pci_setup_iommu_table(tbl, addr, tce_table_size, bus_offset, 2479aca6913fSAlexey Kardashevskiy page_shift); 2480bbb845c4SAlexey Kardashevskiy tbl->it_level_size = 1ULL << (level_shift - 3); 2481bbb845c4SAlexey Kardashevskiy tbl->it_indirect_levels = levels - 1; 24823ba3a73eSAlexey Kardashevskiy tbl->it_allocated_size = total_allocated; 2483aca6913fSAlexey Kardashevskiy 2484aca6913fSAlexey Kardashevskiy pr_devel("Created TCE table: ws=%08llx ts=%lx @%08llx\n", 2485aca6913fSAlexey Kardashevskiy window_size, tce_table_size, bus_offset); 2486aca6913fSAlexey Kardashevskiy 2487aca6913fSAlexey Kardashevskiy return 0; 2488aca6913fSAlexey Kardashevskiy } 2489aca6913fSAlexey Kardashevskiy 2490bbb845c4SAlexey Kardashevskiy static void pnv_pci_ioda2_table_do_free_pages(__be64 *addr, 2491bbb845c4SAlexey Kardashevskiy unsigned long size, unsigned level) 2492bbb845c4SAlexey Kardashevskiy { 2493bbb845c4SAlexey Kardashevskiy const unsigned long addr_ul = (unsigned long) addr & 2494bbb845c4SAlexey Kardashevskiy ~(TCE_PCI_READ | TCE_PCI_WRITE); 2495bbb845c4SAlexey Kardashevskiy 2496bbb845c4SAlexey Kardashevskiy if (level) { 2497bbb845c4SAlexey Kardashevskiy long i; 2498bbb845c4SAlexey Kardashevskiy u64 *tmp = (u64 *) addr_ul; 2499bbb845c4SAlexey Kardashevskiy 2500bbb845c4SAlexey Kardashevskiy for (i = 0; i < size; ++i) { 2501bbb845c4SAlexey Kardashevskiy unsigned long hpa = be64_to_cpu(tmp[i]); 2502bbb845c4SAlexey Kardashevskiy 2503bbb845c4SAlexey Kardashevskiy if (!(hpa & (TCE_PCI_READ | TCE_PCI_WRITE))) 2504bbb845c4SAlexey Kardashevskiy continue; 2505bbb845c4SAlexey Kardashevskiy 2506bbb845c4SAlexey Kardashevskiy pnv_pci_ioda2_table_do_free_pages(__va(hpa), size, 2507bbb845c4SAlexey Kardashevskiy level - 1); 2508bbb845c4SAlexey Kardashevskiy } 2509bbb845c4SAlexey Kardashevskiy } 2510bbb845c4SAlexey Kardashevskiy 2511bbb845c4SAlexey Kardashevskiy free_pages(addr_ul, get_order(size << 3)); 2512bbb845c4SAlexey Kardashevskiy } 2513bbb845c4SAlexey Kardashevskiy 2514aca6913fSAlexey Kardashevskiy static void pnv_pci_ioda2_table_free_pages(struct iommu_table *tbl) 2515aca6913fSAlexey Kardashevskiy { 2516bbb845c4SAlexey Kardashevskiy const unsigned long size = tbl->it_indirect_levels ? 2517bbb845c4SAlexey Kardashevskiy tbl->it_level_size : tbl->it_size; 2518bbb845c4SAlexey Kardashevskiy 2519aca6913fSAlexey Kardashevskiy if (!tbl->it_size) 2520aca6913fSAlexey Kardashevskiy return; 2521aca6913fSAlexey Kardashevskiy 2522bbb845c4SAlexey Kardashevskiy pnv_pci_ioda2_table_do_free_pages((__be64 *)tbl->it_base, size, 2523bbb845c4SAlexey Kardashevskiy tbl->it_indirect_levels); 2524aca6913fSAlexey Kardashevskiy } 2525aca6913fSAlexey Kardashevskiy 2526373f5657SGavin Shan static void pnv_pci_ioda2_setup_dma_pe(struct pnv_phb *phb, 2527373f5657SGavin Shan struct pnv_ioda_pe *pe) 2528373f5657SGavin Shan { 2529373f5657SGavin Shan int64_t rc; 2530373f5657SGavin Shan 2531373f5657SGavin Shan /* We shouldn't already have a 32-bit DMA associated */ 2532373f5657SGavin Shan if (WARN_ON(pe->tce32_seg >= 0)) 2533373f5657SGavin Shan return; 2534373f5657SGavin Shan 2535f87a8864SAlexey Kardashevskiy /* TVE #1 is selected by PCI address bit 59 */ 2536f87a8864SAlexey Kardashevskiy pe->tce_bypass_base = 1ull << 59; 2537f87a8864SAlexey Kardashevskiy 2538b348aa65SAlexey Kardashevskiy iommu_register_group(&pe->table_group, phb->hose->global_number, 2539b348aa65SAlexey Kardashevskiy pe->pe_number); 2540c5773822SAlexey Kardashevskiy 2541373f5657SGavin Shan /* The PE will reserve all possible 32-bits space */ 2542373f5657SGavin Shan pe->tce32_seg = 0; 2543373f5657SGavin Shan pe_info(pe, "Setting up 32-bit TCE table at 0..%08x\n", 2544aca6913fSAlexey Kardashevskiy phb->ioda.m32_pci_base); 2545373f5657SGavin Shan 2546e5aad1e6SAlexey Kardashevskiy /* Setup linux iommu table */ 25474793d65dSAlexey Kardashevskiy pe->table_group.tce32_start = 0; 25484793d65dSAlexey Kardashevskiy pe->table_group.tce32_size = phb->ioda.m32_pci_base; 25494793d65dSAlexey Kardashevskiy pe->table_group.max_dynamic_windows_supported = 25504793d65dSAlexey Kardashevskiy IOMMU_TABLE_GROUP_MAX_TABLES; 25514793d65dSAlexey Kardashevskiy pe->table_group.max_levels = POWERNV_IOMMU_MAX_LEVELS; 25524793d65dSAlexey Kardashevskiy pe->table_group.pgsizes = SZ_4K | SZ_64K | SZ_16M; 2553e5aad1e6SAlexey Kardashevskiy #ifdef CONFIG_IOMMU_API 2554e5aad1e6SAlexey Kardashevskiy pe->table_group.ops = &pnv_pci_ioda2_ops; 2555e5aad1e6SAlexey Kardashevskiy #endif 2556e5aad1e6SAlexey Kardashevskiy 255746d3e1e1SAlexey Kardashevskiy rc = pnv_pci_ioda2_setup_default_config(pe); 2558373f5657SGavin Shan if (rc) { 2559373f5657SGavin Shan if (pe->tce32_seg >= 0) 2560373f5657SGavin Shan pe->tce32_seg = -1; 256146d3e1e1SAlexey Kardashevskiy return; 25620eaf4defSAlexey Kardashevskiy } 256346d3e1e1SAlexey Kardashevskiy 256446d3e1e1SAlexey Kardashevskiy if (pe->flags & PNV_IODA_PE_DEV) 256546d3e1e1SAlexey Kardashevskiy iommu_add_device(&pe->pdev->dev); 256646d3e1e1SAlexey Kardashevskiy else if (pe->flags & (PNV_IODA_PE_BUS | PNV_IODA_PE_BUS_ALL)) 256746d3e1e1SAlexey Kardashevskiy pnv_ioda_setup_bus_dma(pe, pe->pbus); 2568373f5657SGavin Shan } 2569373f5657SGavin Shan 2570cad5cef6SGreg Kroah-Hartman static void pnv_ioda_setup_dma(struct pnv_phb *phb) 2571184cd4a3SBenjamin Herrenschmidt { 2572184cd4a3SBenjamin Herrenschmidt struct pci_controller *hose = phb->hose; 2573184cd4a3SBenjamin Herrenschmidt unsigned int residual, remaining, segs, tw, base; 2574184cd4a3SBenjamin Herrenschmidt struct pnv_ioda_pe *pe; 2575184cd4a3SBenjamin Herrenschmidt 2576184cd4a3SBenjamin Herrenschmidt /* If we have more PE# than segments available, hand out one 2577184cd4a3SBenjamin Herrenschmidt * per PE until we run out and let the rest fail. If not, 2578184cd4a3SBenjamin Herrenschmidt * then we assign at least one segment per PE, plus more based 2579184cd4a3SBenjamin Herrenschmidt * on the amount of devices under that PE 2580184cd4a3SBenjamin Herrenschmidt */ 2581184cd4a3SBenjamin Herrenschmidt if (phb->ioda.dma_pe_count > phb->ioda.tce32_count) 2582184cd4a3SBenjamin Herrenschmidt residual = 0; 2583184cd4a3SBenjamin Herrenschmidt else 2584184cd4a3SBenjamin Herrenschmidt residual = phb->ioda.tce32_count - 2585184cd4a3SBenjamin Herrenschmidt phb->ioda.dma_pe_count; 2586184cd4a3SBenjamin Herrenschmidt 2587184cd4a3SBenjamin Herrenschmidt pr_info("PCI: Domain %04x has %ld available 32-bit DMA segments\n", 2588184cd4a3SBenjamin Herrenschmidt hose->global_number, phb->ioda.tce32_count); 2589184cd4a3SBenjamin Herrenschmidt pr_info("PCI: %d PE# for a total weight of %d\n", 2590184cd4a3SBenjamin Herrenschmidt phb->ioda.dma_pe_count, phb->ioda.dma_weight); 2591184cd4a3SBenjamin Herrenschmidt 25925780fb04SAlexey Kardashevskiy pnv_pci_ioda_setup_opal_tce_kill(phb); 25935780fb04SAlexey Kardashevskiy 2594184cd4a3SBenjamin Herrenschmidt /* Walk our PE list and configure their DMA segments, hand them 2595184cd4a3SBenjamin Herrenschmidt * out one base segment plus any residual segments based on 2596184cd4a3SBenjamin Herrenschmidt * weight 2597184cd4a3SBenjamin Herrenschmidt */ 2598184cd4a3SBenjamin Herrenschmidt remaining = phb->ioda.tce32_count; 2599184cd4a3SBenjamin Herrenschmidt tw = phb->ioda.dma_weight; 2600184cd4a3SBenjamin Herrenschmidt base = 0; 26017ebdf956SGavin Shan list_for_each_entry(pe, &phb->ioda.pe_dma_list, dma_link) { 2602184cd4a3SBenjamin Herrenschmidt if (!pe->dma_weight) 2603184cd4a3SBenjamin Herrenschmidt continue; 2604184cd4a3SBenjamin Herrenschmidt if (!remaining) { 2605184cd4a3SBenjamin Herrenschmidt pe_warn(pe, "No DMA32 resources available\n"); 2606184cd4a3SBenjamin Herrenschmidt continue; 2607184cd4a3SBenjamin Herrenschmidt } 2608184cd4a3SBenjamin Herrenschmidt segs = 1; 2609184cd4a3SBenjamin Herrenschmidt if (residual) { 2610184cd4a3SBenjamin Herrenschmidt segs += ((pe->dma_weight * residual) + (tw / 2)) / tw; 2611184cd4a3SBenjamin Herrenschmidt if (segs > remaining) 2612184cd4a3SBenjamin Herrenschmidt segs = remaining; 2613184cd4a3SBenjamin Herrenschmidt } 2614373f5657SGavin Shan 2615373f5657SGavin Shan /* 2616373f5657SGavin Shan * For IODA2 compliant PHB3, we needn't care about the weight. 2617373f5657SGavin Shan * The all available 32-bits DMA space will be assigned to 2618373f5657SGavin Shan * the specific PE. 2619373f5657SGavin Shan */ 2620373f5657SGavin Shan if (phb->type == PNV_PHB_IODA1) { 2621184cd4a3SBenjamin Herrenschmidt pe_info(pe, "DMA weight %d, assigned %d DMA32 segments\n", 2622184cd4a3SBenjamin Herrenschmidt pe->dma_weight, segs); 2623b30d936fSGavin Shan pnv_pci_ioda1_setup_dma_pe(phb, pe, base, segs); 26245d2aa710SAlistair Popple } else if (phb->type == PNV_PHB_IODA2) { 2625373f5657SGavin Shan pe_info(pe, "Assign DMA32 space\n"); 2626373f5657SGavin Shan segs = 0; 2627373f5657SGavin Shan pnv_pci_ioda2_setup_dma_pe(phb, pe); 26285d2aa710SAlistair Popple } else if (phb->type == PNV_PHB_NPU) { 26295d2aa710SAlistair Popple /* 26305d2aa710SAlistair Popple * We initialise the DMA space for an NPU PHB 26315d2aa710SAlistair Popple * after setup of the PHB is complete as we 26325d2aa710SAlistair Popple * point the NPU TVT to the the same location 26335d2aa710SAlistair Popple * as the PHB3 TVT. 26345d2aa710SAlistair Popple */ 2635373f5657SGavin Shan } 2636373f5657SGavin Shan 2637184cd4a3SBenjamin Herrenschmidt remaining -= segs; 2638184cd4a3SBenjamin Herrenschmidt base += segs; 2639184cd4a3SBenjamin Herrenschmidt } 2640184cd4a3SBenjamin Herrenschmidt } 2641184cd4a3SBenjamin Herrenschmidt 2642184cd4a3SBenjamin Herrenschmidt #ifdef CONFIG_PCI_MSI 2643137436c9SGavin Shan static void pnv_ioda2_msi_eoi(struct irq_data *d) 2644137436c9SGavin Shan { 2645137436c9SGavin Shan unsigned int hw_irq = (unsigned int)irqd_to_hwirq(d); 2646137436c9SGavin Shan struct irq_chip *chip = irq_data_get_irq_chip(d); 2647137436c9SGavin Shan struct pnv_phb *phb = container_of(chip, struct pnv_phb, 2648137436c9SGavin Shan ioda.irq_chip); 2649137436c9SGavin Shan int64_t rc; 2650137436c9SGavin Shan 2651137436c9SGavin Shan rc = opal_pci_msi_eoi(phb->opal_id, hw_irq); 2652137436c9SGavin Shan WARN_ON_ONCE(rc); 2653137436c9SGavin Shan 2654137436c9SGavin Shan icp_native_eoi(d); 2655137436c9SGavin Shan } 2656137436c9SGavin Shan 2657fd9a1c26SIan Munsie 2658fd9a1c26SIan Munsie static void set_msi_irq_chip(struct pnv_phb *phb, unsigned int virq) 2659fd9a1c26SIan Munsie { 2660fd9a1c26SIan Munsie struct irq_data *idata; 2661fd9a1c26SIan Munsie struct irq_chip *ichip; 2662fd9a1c26SIan Munsie 2663fd9a1c26SIan Munsie if (phb->type != PNV_PHB_IODA2) 2664fd9a1c26SIan Munsie return; 2665fd9a1c26SIan Munsie 2666fd9a1c26SIan Munsie if (!phb->ioda.irq_chip_init) { 2667fd9a1c26SIan Munsie /* 2668fd9a1c26SIan Munsie * First time we setup an MSI IRQ, we need to setup the 2669fd9a1c26SIan Munsie * corresponding IRQ chip to route correctly. 2670fd9a1c26SIan Munsie */ 2671fd9a1c26SIan Munsie idata = irq_get_irq_data(virq); 2672fd9a1c26SIan Munsie ichip = irq_data_get_irq_chip(idata); 2673fd9a1c26SIan Munsie phb->ioda.irq_chip_init = 1; 2674fd9a1c26SIan Munsie phb->ioda.irq_chip = *ichip; 2675fd9a1c26SIan Munsie phb->ioda.irq_chip.irq_eoi = pnv_ioda2_msi_eoi; 2676fd9a1c26SIan Munsie } 2677fd9a1c26SIan Munsie irq_set_chip(virq, &phb->ioda.irq_chip); 2678fd9a1c26SIan Munsie } 2679fd9a1c26SIan Munsie 268080c49c7eSIan Munsie #ifdef CONFIG_CXL_BASE 268180c49c7eSIan Munsie 26826f963ec2SRyan Grimm struct device_node *pnv_pci_get_phb_node(struct pci_dev *dev) 268380c49c7eSIan Munsie { 268480c49c7eSIan Munsie struct pci_controller *hose = pci_bus_to_host(dev->bus); 268580c49c7eSIan Munsie 26866f963ec2SRyan Grimm return of_node_get(hose->dn); 268780c49c7eSIan Munsie } 26886f963ec2SRyan Grimm EXPORT_SYMBOL(pnv_pci_get_phb_node); 268980c49c7eSIan Munsie 26901212aa1cSRyan Grimm int pnv_phb_to_cxl_mode(struct pci_dev *dev, uint64_t mode) 269180c49c7eSIan Munsie { 269280c49c7eSIan Munsie struct pci_controller *hose = pci_bus_to_host(dev->bus); 269380c49c7eSIan Munsie struct pnv_phb *phb = hose->private_data; 269480c49c7eSIan Munsie struct pnv_ioda_pe *pe; 269580c49c7eSIan Munsie int rc; 269680c49c7eSIan Munsie 269780c49c7eSIan Munsie pe = pnv_ioda_get_pe(dev); 269880c49c7eSIan Munsie if (!pe) 269980c49c7eSIan Munsie return -ENODEV; 270080c49c7eSIan Munsie 270180c49c7eSIan Munsie pe_info(pe, "Switching PHB to CXL\n"); 270280c49c7eSIan Munsie 27031212aa1cSRyan Grimm rc = opal_pci_set_phb_cxl_mode(phb->opal_id, mode, pe->pe_number); 270480c49c7eSIan Munsie if (rc) 270580c49c7eSIan Munsie dev_err(&dev->dev, "opal_pci_set_phb_cxl_mode failed: %i\n", rc); 270680c49c7eSIan Munsie 270780c49c7eSIan Munsie return rc; 270880c49c7eSIan Munsie } 27091212aa1cSRyan Grimm EXPORT_SYMBOL(pnv_phb_to_cxl_mode); 271080c49c7eSIan Munsie 271180c49c7eSIan Munsie /* Find PHB for cxl dev and allocate MSI hwirqs? 271280c49c7eSIan Munsie * Returns the absolute hardware IRQ number 271380c49c7eSIan Munsie */ 271480c49c7eSIan Munsie int pnv_cxl_alloc_hwirqs(struct pci_dev *dev, int num) 271580c49c7eSIan Munsie { 271680c49c7eSIan Munsie struct pci_controller *hose = pci_bus_to_host(dev->bus); 271780c49c7eSIan Munsie struct pnv_phb *phb = hose->private_data; 271880c49c7eSIan Munsie int hwirq = msi_bitmap_alloc_hwirqs(&phb->msi_bmp, num); 271980c49c7eSIan Munsie 272080c49c7eSIan Munsie if (hwirq < 0) { 272180c49c7eSIan Munsie dev_warn(&dev->dev, "Failed to find a free MSI\n"); 272280c49c7eSIan Munsie return -ENOSPC; 272380c49c7eSIan Munsie } 272480c49c7eSIan Munsie 272580c49c7eSIan Munsie return phb->msi_base + hwirq; 272680c49c7eSIan Munsie } 272780c49c7eSIan Munsie EXPORT_SYMBOL(pnv_cxl_alloc_hwirqs); 272880c49c7eSIan Munsie 272980c49c7eSIan Munsie void pnv_cxl_release_hwirqs(struct pci_dev *dev, int hwirq, int num) 273080c49c7eSIan Munsie { 273180c49c7eSIan Munsie struct pci_controller *hose = pci_bus_to_host(dev->bus); 273280c49c7eSIan Munsie struct pnv_phb *phb = hose->private_data; 273380c49c7eSIan Munsie 273480c49c7eSIan Munsie msi_bitmap_free_hwirqs(&phb->msi_bmp, hwirq - phb->msi_base, num); 273580c49c7eSIan Munsie } 273680c49c7eSIan Munsie EXPORT_SYMBOL(pnv_cxl_release_hwirqs); 273780c49c7eSIan Munsie 273880c49c7eSIan Munsie void pnv_cxl_release_hwirq_ranges(struct cxl_irq_ranges *irqs, 273980c49c7eSIan Munsie struct pci_dev *dev) 274080c49c7eSIan Munsie { 274180c49c7eSIan Munsie struct pci_controller *hose = pci_bus_to_host(dev->bus); 274280c49c7eSIan Munsie struct pnv_phb *phb = hose->private_data; 274380c49c7eSIan Munsie int i, hwirq; 274480c49c7eSIan Munsie 274580c49c7eSIan Munsie for (i = 1; i < CXL_IRQ_RANGES; i++) { 274680c49c7eSIan Munsie if (!irqs->range[i]) 274780c49c7eSIan Munsie continue; 274880c49c7eSIan Munsie pr_devel("cxl release irq range 0x%x: offset: 0x%lx limit: %ld\n", 274980c49c7eSIan Munsie i, irqs->offset[i], 275080c49c7eSIan Munsie irqs->range[i]); 275180c49c7eSIan Munsie hwirq = irqs->offset[i] - phb->msi_base; 275280c49c7eSIan Munsie msi_bitmap_free_hwirqs(&phb->msi_bmp, hwirq, 275380c49c7eSIan Munsie irqs->range[i]); 275480c49c7eSIan Munsie } 275580c49c7eSIan Munsie } 275680c49c7eSIan Munsie EXPORT_SYMBOL(pnv_cxl_release_hwirq_ranges); 275780c49c7eSIan Munsie 275880c49c7eSIan Munsie int pnv_cxl_alloc_hwirq_ranges(struct cxl_irq_ranges *irqs, 275980c49c7eSIan Munsie struct pci_dev *dev, int num) 276080c49c7eSIan Munsie { 276180c49c7eSIan Munsie struct pci_controller *hose = pci_bus_to_host(dev->bus); 276280c49c7eSIan Munsie struct pnv_phb *phb = hose->private_data; 276380c49c7eSIan Munsie int i, hwirq, try; 276480c49c7eSIan Munsie 276580c49c7eSIan Munsie memset(irqs, 0, sizeof(struct cxl_irq_ranges)); 276680c49c7eSIan Munsie 276780c49c7eSIan Munsie /* 0 is reserved for the multiplexed PSL DSI interrupt */ 276880c49c7eSIan Munsie for (i = 1; i < CXL_IRQ_RANGES && num; i++) { 276980c49c7eSIan Munsie try = num; 277080c49c7eSIan Munsie while (try) { 277180c49c7eSIan Munsie hwirq = msi_bitmap_alloc_hwirqs(&phb->msi_bmp, try); 277280c49c7eSIan Munsie if (hwirq >= 0) 277380c49c7eSIan Munsie break; 277480c49c7eSIan Munsie try /= 2; 277580c49c7eSIan Munsie } 277680c49c7eSIan Munsie if (!try) 277780c49c7eSIan Munsie goto fail; 277880c49c7eSIan Munsie 277980c49c7eSIan Munsie irqs->offset[i] = phb->msi_base + hwirq; 278080c49c7eSIan Munsie irqs->range[i] = try; 278180c49c7eSIan Munsie pr_devel("cxl alloc irq range 0x%x: offset: 0x%lx limit: %li\n", 278280c49c7eSIan Munsie i, irqs->offset[i], irqs->range[i]); 278380c49c7eSIan Munsie num -= try; 278480c49c7eSIan Munsie } 278580c49c7eSIan Munsie if (num) 278680c49c7eSIan Munsie goto fail; 278780c49c7eSIan Munsie 278880c49c7eSIan Munsie return 0; 278980c49c7eSIan Munsie fail: 279080c49c7eSIan Munsie pnv_cxl_release_hwirq_ranges(irqs, dev); 279180c49c7eSIan Munsie return -ENOSPC; 279280c49c7eSIan Munsie } 279380c49c7eSIan Munsie EXPORT_SYMBOL(pnv_cxl_alloc_hwirq_ranges); 279480c49c7eSIan Munsie 279580c49c7eSIan Munsie int pnv_cxl_get_irq_count(struct pci_dev *dev) 279680c49c7eSIan Munsie { 279780c49c7eSIan Munsie struct pci_controller *hose = pci_bus_to_host(dev->bus); 279880c49c7eSIan Munsie struct pnv_phb *phb = hose->private_data; 279980c49c7eSIan Munsie 280080c49c7eSIan Munsie return phb->msi_bmp.irq_count; 280180c49c7eSIan Munsie } 280280c49c7eSIan Munsie EXPORT_SYMBOL(pnv_cxl_get_irq_count); 280380c49c7eSIan Munsie 280480c49c7eSIan Munsie int pnv_cxl_ioda_msi_setup(struct pci_dev *dev, unsigned int hwirq, 280580c49c7eSIan Munsie unsigned int virq) 280680c49c7eSIan Munsie { 280780c49c7eSIan Munsie struct pci_controller *hose = pci_bus_to_host(dev->bus); 280880c49c7eSIan Munsie struct pnv_phb *phb = hose->private_data; 280980c49c7eSIan Munsie unsigned int xive_num = hwirq - phb->msi_base; 281080c49c7eSIan Munsie struct pnv_ioda_pe *pe; 281180c49c7eSIan Munsie int rc; 281280c49c7eSIan Munsie 281380c49c7eSIan Munsie if (!(pe = pnv_ioda_get_pe(dev))) 281480c49c7eSIan Munsie return -ENODEV; 281580c49c7eSIan Munsie 281680c49c7eSIan Munsie /* Assign XIVE to PE */ 281780c49c7eSIan Munsie rc = opal_pci_set_xive_pe(phb->opal_id, pe->pe_number, xive_num); 281880c49c7eSIan Munsie if (rc) { 281980c49c7eSIan Munsie pe_warn(pe, "%s: OPAL error %d setting msi_base 0x%x " 282080c49c7eSIan Munsie "hwirq 0x%x XIVE 0x%x PE\n", 282180c49c7eSIan Munsie pci_name(dev), rc, phb->msi_base, hwirq, xive_num); 282280c49c7eSIan Munsie return -EIO; 282380c49c7eSIan Munsie } 282480c49c7eSIan Munsie set_msi_irq_chip(phb, virq); 282580c49c7eSIan Munsie 282680c49c7eSIan Munsie return 0; 282780c49c7eSIan Munsie } 282880c49c7eSIan Munsie EXPORT_SYMBOL(pnv_cxl_ioda_msi_setup); 282980c49c7eSIan Munsie #endif 283080c49c7eSIan Munsie 2831184cd4a3SBenjamin Herrenschmidt static int pnv_pci_ioda_msi_setup(struct pnv_phb *phb, struct pci_dev *dev, 2832137436c9SGavin Shan unsigned int hwirq, unsigned int virq, 2833137436c9SGavin Shan unsigned int is_64, struct msi_msg *msg) 2834184cd4a3SBenjamin Herrenschmidt { 2835184cd4a3SBenjamin Herrenschmidt struct pnv_ioda_pe *pe = pnv_ioda_get_pe(dev); 2836184cd4a3SBenjamin Herrenschmidt unsigned int xive_num = hwirq - phb->msi_base; 28373a1a4661SBenjamin Herrenschmidt __be32 data; 2838184cd4a3SBenjamin Herrenschmidt int rc; 2839184cd4a3SBenjamin Herrenschmidt 2840184cd4a3SBenjamin Herrenschmidt /* No PE assigned ? bail out ... no MSI for you ! */ 2841184cd4a3SBenjamin Herrenschmidt if (pe == NULL) 2842184cd4a3SBenjamin Herrenschmidt return -ENXIO; 2843184cd4a3SBenjamin Herrenschmidt 2844184cd4a3SBenjamin Herrenschmidt /* Check if we have an MVE */ 2845184cd4a3SBenjamin Herrenschmidt if (pe->mve_number < 0) 2846184cd4a3SBenjamin Herrenschmidt return -ENXIO; 2847184cd4a3SBenjamin Herrenschmidt 2848b72c1f65SBenjamin Herrenschmidt /* Force 32-bit MSI on some broken devices */ 284936074381SBenjamin Herrenschmidt if (dev->no_64bit_msi) 2850b72c1f65SBenjamin Herrenschmidt is_64 = 0; 2851b72c1f65SBenjamin Herrenschmidt 2852184cd4a3SBenjamin Herrenschmidt /* Assign XIVE to PE */ 2853184cd4a3SBenjamin Herrenschmidt rc = opal_pci_set_xive_pe(phb->opal_id, pe->pe_number, xive_num); 2854184cd4a3SBenjamin Herrenschmidt if (rc) { 2855184cd4a3SBenjamin Herrenschmidt pr_warn("%s: OPAL error %d setting XIVE %d PE\n", 2856184cd4a3SBenjamin Herrenschmidt pci_name(dev), rc, xive_num); 2857184cd4a3SBenjamin Herrenschmidt return -EIO; 2858184cd4a3SBenjamin Herrenschmidt } 2859184cd4a3SBenjamin Herrenschmidt 2860184cd4a3SBenjamin Herrenschmidt if (is_64) { 28613a1a4661SBenjamin Herrenschmidt __be64 addr64; 28623a1a4661SBenjamin Herrenschmidt 2863184cd4a3SBenjamin Herrenschmidt rc = opal_get_msi_64(phb->opal_id, pe->mve_number, xive_num, 1, 2864184cd4a3SBenjamin Herrenschmidt &addr64, &data); 2865184cd4a3SBenjamin Herrenschmidt if (rc) { 2866184cd4a3SBenjamin Herrenschmidt pr_warn("%s: OPAL error %d getting 64-bit MSI data\n", 2867184cd4a3SBenjamin Herrenschmidt pci_name(dev), rc); 2868184cd4a3SBenjamin Herrenschmidt return -EIO; 2869184cd4a3SBenjamin Herrenschmidt } 28703a1a4661SBenjamin Herrenschmidt msg->address_hi = be64_to_cpu(addr64) >> 32; 28713a1a4661SBenjamin Herrenschmidt msg->address_lo = be64_to_cpu(addr64) & 0xfffffffful; 2872184cd4a3SBenjamin Herrenschmidt } else { 28733a1a4661SBenjamin Herrenschmidt __be32 addr32; 28743a1a4661SBenjamin Herrenschmidt 2875184cd4a3SBenjamin Herrenschmidt rc = opal_get_msi_32(phb->opal_id, pe->mve_number, xive_num, 1, 2876184cd4a3SBenjamin Herrenschmidt &addr32, &data); 2877184cd4a3SBenjamin Herrenschmidt if (rc) { 2878184cd4a3SBenjamin Herrenschmidt pr_warn("%s: OPAL error %d getting 32-bit MSI data\n", 2879184cd4a3SBenjamin Herrenschmidt pci_name(dev), rc); 2880184cd4a3SBenjamin Herrenschmidt return -EIO; 2881184cd4a3SBenjamin Herrenschmidt } 2882184cd4a3SBenjamin Herrenschmidt msg->address_hi = 0; 28833a1a4661SBenjamin Herrenschmidt msg->address_lo = be32_to_cpu(addr32); 2884184cd4a3SBenjamin Herrenschmidt } 28853a1a4661SBenjamin Herrenschmidt msg->data = be32_to_cpu(data); 2886184cd4a3SBenjamin Herrenschmidt 2887fd9a1c26SIan Munsie set_msi_irq_chip(phb, virq); 2888137436c9SGavin Shan 2889184cd4a3SBenjamin Herrenschmidt pr_devel("%s: %s-bit MSI on hwirq %x (xive #%d)," 2890184cd4a3SBenjamin Herrenschmidt " address=%x_%08x data=%x PE# %d\n", 2891184cd4a3SBenjamin Herrenschmidt pci_name(dev), is_64 ? "64" : "32", hwirq, xive_num, 2892184cd4a3SBenjamin Herrenschmidt msg->address_hi, msg->address_lo, data, pe->pe_number); 2893184cd4a3SBenjamin Herrenschmidt 2894184cd4a3SBenjamin Herrenschmidt return 0; 2895184cd4a3SBenjamin Herrenschmidt } 2896184cd4a3SBenjamin Herrenschmidt 2897184cd4a3SBenjamin Herrenschmidt static void pnv_pci_init_ioda_msis(struct pnv_phb *phb) 2898184cd4a3SBenjamin Herrenschmidt { 2899fb1b55d6SGavin Shan unsigned int count; 2900184cd4a3SBenjamin Herrenschmidt const __be32 *prop = of_get_property(phb->hose->dn, 2901184cd4a3SBenjamin Herrenschmidt "ibm,opal-msi-ranges", NULL); 2902184cd4a3SBenjamin Herrenschmidt if (!prop) { 2903184cd4a3SBenjamin Herrenschmidt /* BML Fallback */ 2904184cd4a3SBenjamin Herrenschmidt prop = of_get_property(phb->hose->dn, "msi-ranges", NULL); 2905184cd4a3SBenjamin Herrenschmidt } 2906184cd4a3SBenjamin Herrenschmidt if (!prop) 2907184cd4a3SBenjamin Herrenschmidt return; 2908184cd4a3SBenjamin Herrenschmidt 2909184cd4a3SBenjamin Herrenschmidt phb->msi_base = be32_to_cpup(prop); 2910fb1b55d6SGavin Shan count = be32_to_cpup(prop + 1); 2911fb1b55d6SGavin Shan if (msi_bitmap_alloc(&phb->msi_bmp, count, phb->hose->dn)) { 2912184cd4a3SBenjamin Herrenschmidt pr_err("PCI %d: Failed to allocate MSI bitmap !\n", 2913184cd4a3SBenjamin Herrenschmidt phb->hose->global_number); 2914184cd4a3SBenjamin Herrenschmidt return; 2915184cd4a3SBenjamin Herrenschmidt } 2916fb1b55d6SGavin Shan 2917184cd4a3SBenjamin Herrenschmidt phb->msi_setup = pnv_pci_ioda_msi_setup; 2918184cd4a3SBenjamin Herrenschmidt phb->msi32_support = 1; 2919184cd4a3SBenjamin Herrenschmidt pr_info(" Allocated bitmap for %d MSIs (base IRQ 0x%x)\n", 2920fb1b55d6SGavin Shan count, phb->msi_base); 2921184cd4a3SBenjamin Herrenschmidt } 2922184cd4a3SBenjamin Herrenschmidt #else 2923184cd4a3SBenjamin Herrenschmidt static void pnv_pci_init_ioda_msis(struct pnv_phb *phb) { } 2924184cd4a3SBenjamin Herrenschmidt #endif /* CONFIG_PCI_MSI */ 2925184cd4a3SBenjamin Herrenschmidt 29266e628c7dSWei Yang #ifdef CONFIG_PCI_IOV 29276e628c7dSWei Yang static void pnv_pci_ioda_fixup_iov_resources(struct pci_dev *pdev) 29286e628c7dSWei Yang { 2929f2dd0afeSWei Yang struct pci_controller *hose = pci_bus_to_host(pdev->bus); 2930f2dd0afeSWei Yang struct pnv_phb *phb = hose->private_data; 2931f2dd0afeSWei Yang const resource_size_t gate = phb->ioda.m64_segsize >> 2; 29326e628c7dSWei Yang struct resource *res; 29336e628c7dSWei Yang int i; 2934dfcc8d45SWei Yang resource_size_t size, total_vf_bar_sz; 29356e628c7dSWei Yang struct pci_dn *pdn; 29365b88ec22SWei Yang int mul, total_vfs; 29376e628c7dSWei Yang 29386e628c7dSWei Yang if (!pdev->is_physfn || pdev->is_added) 29396e628c7dSWei Yang return; 29406e628c7dSWei Yang 29416e628c7dSWei Yang pdn = pci_get_pdn(pdev); 29426e628c7dSWei Yang pdn->vfs_expanded = 0; 2943ee8222feSWei Yang pdn->m64_single_mode = false; 29446e628c7dSWei Yang 29455b88ec22SWei Yang total_vfs = pci_sriov_get_totalvfs(pdev); 294692b8f137SGavin Shan mul = phb->ioda.total_pe_num; 2947dfcc8d45SWei Yang total_vf_bar_sz = 0; 29485b88ec22SWei Yang 29495b88ec22SWei Yang for (i = 0; i < PCI_SRIOV_NUM_BARS; i++) { 29505b88ec22SWei Yang res = &pdev->resource[i + PCI_IOV_RESOURCES]; 29515b88ec22SWei Yang if (!res->flags || res->parent) 29525b88ec22SWei Yang continue; 29535b88ec22SWei Yang if (!pnv_pci_is_mem_pref_64(res->flags)) { 2954b0331854SWei Yang dev_warn(&pdev->dev, "Don't support SR-IOV with" 2955b0331854SWei Yang " non M64 VF BAR%d: %pR. \n", 29565b88ec22SWei Yang i, res); 2957b0331854SWei Yang goto truncate_iov; 29585b88ec22SWei Yang } 29595b88ec22SWei Yang 2960dfcc8d45SWei Yang total_vf_bar_sz += pci_iov_resource_size(pdev, 2961dfcc8d45SWei Yang i + PCI_IOV_RESOURCES); 29625b88ec22SWei Yang 2963f2dd0afeSWei Yang /* 2964f2dd0afeSWei Yang * If bigger than quarter of M64 segment size, just round up 2965f2dd0afeSWei Yang * power of two. 2966f2dd0afeSWei Yang * 2967f2dd0afeSWei Yang * Generally, one M64 BAR maps one IOV BAR. To avoid conflict 2968f2dd0afeSWei Yang * with other devices, IOV BAR size is expanded to be 2969f2dd0afeSWei Yang * (total_pe * VF_BAR_size). When VF_BAR_size is half of M64 2970f2dd0afeSWei Yang * segment size , the expanded size would equal to half of the 2971f2dd0afeSWei Yang * whole M64 space size, which will exhaust the M64 Space and 2972f2dd0afeSWei Yang * limit the system flexibility. This is a design decision to 2973f2dd0afeSWei Yang * set the boundary to quarter of the M64 segment size. 2974f2dd0afeSWei Yang */ 2975dfcc8d45SWei Yang if (total_vf_bar_sz > gate) { 29765b88ec22SWei Yang mul = roundup_pow_of_two(total_vfs); 2977dfcc8d45SWei Yang dev_info(&pdev->dev, 2978dfcc8d45SWei Yang "VF BAR Total IOV size %llx > %llx, roundup to %d VFs\n", 2979dfcc8d45SWei Yang total_vf_bar_sz, gate, mul); 2980ee8222feSWei Yang pdn->m64_single_mode = true; 29815b88ec22SWei Yang break; 29825b88ec22SWei Yang } 29835b88ec22SWei Yang } 29845b88ec22SWei Yang 29856e628c7dSWei Yang for (i = 0; i < PCI_SRIOV_NUM_BARS; i++) { 29866e628c7dSWei Yang res = &pdev->resource[i + PCI_IOV_RESOURCES]; 29876e628c7dSWei Yang if (!res->flags || res->parent) 29886e628c7dSWei Yang continue; 29896e628c7dSWei Yang 29906e628c7dSWei Yang size = pci_iov_resource_size(pdev, i + PCI_IOV_RESOURCES); 2991ee8222feSWei Yang /* 2992ee8222feSWei Yang * On PHB3, the minimum size alignment of M64 BAR in single 2993ee8222feSWei Yang * mode is 32MB. 2994ee8222feSWei Yang */ 2995ee8222feSWei Yang if (pdn->m64_single_mode && (size < SZ_32M)) 2996ee8222feSWei Yang goto truncate_iov; 2997ee8222feSWei Yang dev_dbg(&pdev->dev, " Fixing VF BAR%d: %pR to\n", i, res); 29985b88ec22SWei Yang res->end = res->start + size * mul - 1; 29996e628c7dSWei Yang dev_dbg(&pdev->dev, " %pR\n", res); 30006e628c7dSWei Yang dev_info(&pdev->dev, "VF BAR%d: %pR (expanded to %d VFs for PE alignment)", 30015b88ec22SWei Yang i, res, mul); 30026e628c7dSWei Yang } 30035b88ec22SWei Yang pdn->vfs_expanded = mul; 3004b0331854SWei Yang 3005b0331854SWei Yang return; 3006b0331854SWei Yang 3007b0331854SWei Yang truncate_iov: 3008b0331854SWei Yang /* To save MMIO space, IOV BAR is truncated. */ 3009b0331854SWei Yang for (i = 0; i < PCI_SRIOV_NUM_BARS; i++) { 3010b0331854SWei Yang res = &pdev->resource[i + PCI_IOV_RESOURCES]; 3011b0331854SWei Yang res->flags = 0; 3012b0331854SWei Yang res->end = res->start - 1; 3013b0331854SWei Yang } 30146e628c7dSWei Yang } 30156e628c7dSWei Yang #endif /* CONFIG_PCI_IOV */ 30166e628c7dSWei Yang 301723e79425SGavin Shan static void pnv_ioda_setup_pe_res(struct pnv_ioda_pe *pe, 301823e79425SGavin Shan struct resource *res) 301911685becSGavin Shan { 302023e79425SGavin Shan struct pnv_phb *phb = pe->phb; 302111685becSGavin Shan struct pci_bus_region region; 302223e79425SGavin Shan int index; 302323e79425SGavin Shan int64_t rc; 302411685becSGavin Shan 302523e79425SGavin Shan if (!res || !res->flags || res->start > res->end) 302623e79425SGavin Shan return; 302711685becSGavin Shan 302811685becSGavin Shan if (res->flags & IORESOURCE_IO) { 302911685becSGavin Shan region.start = res->start - phb->ioda.io_pci_base; 303011685becSGavin Shan region.end = res->end - phb->ioda.io_pci_base; 303111685becSGavin Shan index = region.start / phb->ioda.io_segsize; 303211685becSGavin Shan 303392b8f137SGavin Shan while (index < phb->ioda.total_pe_num && 303411685becSGavin Shan region.start <= region.end) { 303511685becSGavin Shan phb->ioda.io_segmap[index] = pe->pe_number; 303611685becSGavin Shan rc = opal_pci_map_pe_mmio_window(phb->opal_id, 303711685becSGavin Shan pe->pe_number, OPAL_IO_WINDOW_TYPE, 0, index); 303811685becSGavin Shan if (rc != OPAL_SUCCESS) { 303923e79425SGavin Shan pr_err("%s: Error %lld mapping IO segment#%d to PE#%d\n", 304011685becSGavin Shan __func__, rc, index, pe->pe_number); 304111685becSGavin Shan break; 304211685becSGavin Shan } 304311685becSGavin Shan 304411685becSGavin Shan region.start += phb->ioda.io_segsize; 304511685becSGavin Shan index++; 304611685becSGavin Shan } 3047027fa02fSGavin Shan } else if ((res->flags & IORESOURCE_MEM) && 3048027fa02fSGavin Shan !pnv_pci_is_mem_pref_64(res->flags)) { 304911685becSGavin Shan region.start = res->start - 305023e79425SGavin Shan phb->hose->mem_offset[0] - 305111685becSGavin Shan phb->ioda.m32_pci_base; 305211685becSGavin Shan region.end = res->end - 305323e79425SGavin Shan phb->hose->mem_offset[0] - 305411685becSGavin Shan phb->ioda.m32_pci_base; 305511685becSGavin Shan index = region.start / phb->ioda.m32_segsize; 305611685becSGavin Shan 305792b8f137SGavin Shan while (index < phb->ioda.total_pe_num && 305811685becSGavin Shan region.start <= region.end) { 305911685becSGavin Shan phb->ioda.m32_segmap[index] = pe->pe_number; 306011685becSGavin Shan rc = opal_pci_map_pe_mmio_window(phb->opal_id, 306111685becSGavin Shan pe->pe_number, OPAL_M32_WINDOW_TYPE, 0, index); 306211685becSGavin Shan if (rc != OPAL_SUCCESS) { 306323e79425SGavin Shan pr_err("%s: Error %lld mapping M32 segment#%d to PE#%d", 306411685becSGavin Shan __func__, rc, index, pe->pe_number); 306511685becSGavin Shan break; 306611685becSGavin Shan } 306711685becSGavin Shan 306811685becSGavin Shan region.start += phb->ioda.m32_segsize; 306911685becSGavin Shan index++; 307011685becSGavin Shan } 307111685becSGavin Shan } 307211685becSGavin Shan } 307323e79425SGavin Shan 307423e79425SGavin Shan /* 307523e79425SGavin Shan * This function is supposed to be called on basis of PE from top 307623e79425SGavin Shan * to bottom style. So the the I/O or MMIO segment assigned to 307723e79425SGavin Shan * parent PE could be overrided by its child PEs if necessary. 307823e79425SGavin Shan */ 307923e79425SGavin Shan static void pnv_ioda_setup_pe_seg(struct pnv_ioda_pe *pe) 308023e79425SGavin Shan { 308169d733e7SGavin Shan struct pci_dev *pdev; 308223e79425SGavin Shan int i; 308323e79425SGavin Shan 308423e79425SGavin Shan /* 308523e79425SGavin Shan * NOTE: We only care PCI bus based PE for now. For PCI 308623e79425SGavin Shan * device based PE, for example SRIOV sensitive VF should 308723e79425SGavin Shan * be figured out later. 308823e79425SGavin Shan */ 308923e79425SGavin Shan BUG_ON(!(pe->flags & (PNV_IODA_PE_BUS | PNV_IODA_PE_BUS_ALL))); 309023e79425SGavin Shan 309169d733e7SGavin Shan list_for_each_entry(pdev, &pe->pbus->devices, bus_list) { 309269d733e7SGavin Shan for (i = 0; i <= PCI_ROM_RESOURCE; i++) 309369d733e7SGavin Shan pnv_ioda_setup_pe_res(pe, &pdev->resource[i]); 309469d733e7SGavin Shan 309569d733e7SGavin Shan /* 309669d733e7SGavin Shan * If the PE contains all subordinate PCI buses, the 309769d733e7SGavin Shan * windows of the child bridges should be mapped to 309869d733e7SGavin Shan * the PE as well. 309969d733e7SGavin Shan */ 310069d733e7SGavin Shan if (!(pe->flags & PNV_IODA_PE_BUS_ALL) || !pci_is_bridge(pdev)) 310169d733e7SGavin Shan continue; 310269d733e7SGavin Shan for (i = 0; i < PCI_BRIDGE_RESOURCE_NUM; i++) 310369d733e7SGavin Shan pnv_ioda_setup_pe_res(pe, 310469d733e7SGavin Shan &pdev->resource[PCI_BRIDGE_RESOURCES + i]); 310569d733e7SGavin Shan } 310611685becSGavin Shan } 310711685becSGavin Shan 3108cad5cef6SGreg Kroah-Hartman static void pnv_pci_ioda_setup_seg(void) 310911685becSGavin Shan { 311011685becSGavin Shan struct pci_controller *tmp, *hose; 311111685becSGavin Shan struct pnv_phb *phb; 311211685becSGavin Shan struct pnv_ioda_pe *pe; 311311685becSGavin Shan 311411685becSGavin Shan list_for_each_entry_safe(hose, tmp, &hose_list, list_node) { 311511685becSGavin Shan phb = hose->private_data; 31165d2aa710SAlistair Popple 31175d2aa710SAlistair Popple /* NPU PHB does not support IO or MMIO segmentation */ 31185d2aa710SAlistair Popple if (phb->type == PNV_PHB_NPU) 31195d2aa710SAlistair Popple continue; 31205d2aa710SAlistair Popple 312111685becSGavin Shan list_for_each_entry(pe, &phb->ioda.pe_list, list) { 312223e79425SGavin Shan pnv_ioda_setup_pe_seg(pe); 312311685becSGavin Shan } 312411685becSGavin Shan } 312511685becSGavin Shan } 312611685becSGavin Shan 3127cad5cef6SGreg Kroah-Hartman static void pnv_pci_ioda_setup_DMA(void) 312813395c48SGavin Shan { 312913395c48SGavin Shan struct pci_controller *hose, *tmp; 3130db1266c8SGavin Shan struct pnv_phb *phb; 313113395c48SGavin Shan 313213395c48SGavin Shan list_for_each_entry_safe(hose, tmp, &hose_list, list_node) { 313313395c48SGavin Shan pnv_ioda_setup_dma(hose->private_data); 3134db1266c8SGavin Shan 3135db1266c8SGavin Shan /* Mark the PHB initialization done */ 3136db1266c8SGavin Shan phb = hose->private_data; 3137db1266c8SGavin Shan phb->initialized = 1; 313813395c48SGavin Shan } 313913395c48SGavin Shan } 314013395c48SGavin Shan 314137c367f2SGavin Shan static void pnv_pci_ioda_create_dbgfs(void) 314237c367f2SGavin Shan { 314337c367f2SGavin Shan #ifdef CONFIG_DEBUG_FS 314437c367f2SGavin Shan struct pci_controller *hose, *tmp; 314537c367f2SGavin Shan struct pnv_phb *phb; 314637c367f2SGavin Shan char name[16]; 314737c367f2SGavin Shan 314837c367f2SGavin Shan list_for_each_entry_safe(hose, tmp, &hose_list, list_node) { 314937c367f2SGavin Shan phb = hose->private_data; 315037c367f2SGavin Shan 315137c367f2SGavin Shan sprintf(name, "PCI%04x", hose->global_number); 315237c367f2SGavin Shan phb->dbgfs = debugfs_create_dir(name, powerpc_debugfs_root); 315337c367f2SGavin Shan if (!phb->dbgfs) 315437c367f2SGavin Shan pr_warning("%s: Error on creating debugfs on PHB#%x\n", 315537c367f2SGavin Shan __func__, hose->global_number); 315637c367f2SGavin Shan } 315737c367f2SGavin Shan #endif /* CONFIG_DEBUG_FS */ 315837c367f2SGavin Shan } 315937c367f2SGavin Shan 31605d2aa710SAlistair Popple static void pnv_npu_ioda_fixup(void) 31615d2aa710SAlistair Popple { 31625d2aa710SAlistair Popple bool enable_bypass; 31635d2aa710SAlistair Popple struct pci_controller *hose, *tmp; 31645d2aa710SAlistair Popple struct pnv_phb *phb; 31655d2aa710SAlistair Popple struct pnv_ioda_pe *pe; 31665d2aa710SAlistair Popple 31675d2aa710SAlistair Popple list_for_each_entry_safe(hose, tmp, &hose_list, list_node) { 31685d2aa710SAlistair Popple phb = hose->private_data; 31695d2aa710SAlistair Popple if (phb->type != PNV_PHB_NPU) 31705d2aa710SAlistair Popple continue; 31715d2aa710SAlistair Popple 31725d2aa710SAlistair Popple list_for_each_entry(pe, &phb->ioda.pe_dma_list, dma_link) { 31735d2aa710SAlistair Popple enable_bypass = dma_get_mask(&pe->pdev->dev) == 31745d2aa710SAlistair Popple DMA_BIT_MASK(64); 31755d2aa710SAlistair Popple pnv_npu_init_dma_pe(pe); 31765d2aa710SAlistair Popple pnv_npu_dma_set_bypass(pe, enable_bypass); 31775d2aa710SAlistair Popple } 31785d2aa710SAlistair Popple } 31795d2aa710SAlistair Popple } 31805d2aa710SAlistair Popple 3181cad5cef6SGreg Kroah-Hartman static void pnv_pci_ioda_fixup(void) 3182fb446ad0SGavin Shan { 3183fb446ad0SGavin Shan pnv_pci_ioda_setup_PEs(); 318411685becSGavin Shan pnv_pci_ioda_setup_seg(); 318513395c48SGavin Shan pnv_pci_ioda_setup_DMA(); 3186e9cc17d4SGavin Shan 318737c367f2SGavin Shan pnv_pci_ioda_create_dbgfs(); 318837c367f2SGavin Shan 3189e9cc17d4SGavin Shan #ifdef CONFIG_EEH 3190e9cc17d4SGavin Shan eeh_init(); 3191dadcd6d6SMike Qiu eeh_addr_cache_build(); 3192e9cc17d4SGavin Shan #endif 31935d2aa710SAlistair Popple 31945d2aa710SAlistair Popple /* Link NPU IODA tables to their PCI devices. */ 31955d2aa710SAlistair Popple pnv_npu_ioda_fixup(); 3196fb446ad0SGavin Shan } 3197fb446ad0SGavin Shan 3198271fd03aSGavin Shan /* 3199271fd03aSGavin Shan * Returns the alignment for I/O or memory windows for P2P 3200271fd03aSGavin Shan * bridges. That actually depends on how PEs are segmented. 3201271fd03aSGavin Shan * For now, we return I/O or M32 segment size for PE sensitive 3202271fd03aSGavin Shan * P2P bridges. Otherwise, the default values (4KiB for I/O, 3203271fd03aSGavin Shan * 1MiB for memory) will be returned. 3204271fd03aSGavin Shan * 3205271fd03aSGavin Shan * The current PCI bus might be put into one PE, which was 3206271fd03aSGavin Shan * create against the parent PCI bridge. For that case, we 3207271fd03aSGavin Shan * needn't enlarge the alignment so that we can save some 3208271fd03aSGavin Shan * resources. 3209271fd03aSGavin Shan */ 3210271fd03aSGavin Shan static resource_size_t pnv_pci_window_alignment(struct pci_bus *bus, 3211271fd03aSGavin Shan unsigned long type) 3212271fd03aSGavin Shan { 3213271fd03aSGavin Shan struct pci_dev *bridge; 3214271fd03aSGavin Shan struct pci_controller *hose = pci_bus_to_host(bus); 3215271fd03aSGavin Shan struct pnv_phb *phb = hose->private_data; 3216271fd03aSGavin Shan int num_pci_bridges = 0; 3217271fd03aSGavin Shan 3218271fd03aSGavin Shan bridge = bus->self; 3219271fd03aSGavin Shan while (bridge) { 3220271fd03aSGavin Shan if (pci_pcie_type(bridge) == PCI_EXP_TYPE_PCI_BRIDGE) { 3221271fd03aSGavin Shan num_pci_bridges++; 3222271fd03aSGavin Shan if (num_pci_bridges >= 2) 3223271fd03aSGavin Shan return 1; 3224271fd03aSGavin Shan } 3225271fd03aSGavin Shan 3226271fd03aSGavin Shan bridge = bridge->bus->self; 3227271fd03aSGavin Shan } 3228271fd03aSGavin Shan 3229262af557SGuo Chao /* We fail back to M32 if M64 isn't supported */ 3230262af557SGuo Chao if (phb->ioda.m64_segsize && 3231262af557SGuo Chao pnv_pci_is_mem_pref_64(type)) 3232262af557SGuo Chao return phb->ioda.m64_segsize; 3233271fd03aSGavin Shan if (type & IORESOURCE_MEM) 3234271fd03aSGavin Shan return phb->ioda.m32_segsize; 3235271fd03aSGavin Shan 3236271fd03aSGavin Shan return phb->ioda.io_segsize; 3237271fd03aSGavin Shan } 3238271fd03aSGavin Shan 32395350ab3fSWei Yang #ifdef CONFIG_PCI_IOV 32405350ab3fSWei Yang static resource_size_t pnv_pci_iov_resource_alignment(struct pci_dev *pdev, 32415350ab3fSWei Yang int resno) 32425350ab3fSWei Yang { 3243ee8222feSWei Yang struct pci_controller *hose = pci_bus_to_host(pdev->bus); 3244ee8222feSWei Yang struct pnv_phb *phb = hose->private_data; 32455350ab3fSWei Yang struct pci_dn *pdn = pci_get_pdn(pdev); 32467fbe7a93SWei Yang resource_size_t align; 32475350ab3fSWei Yang 32487fbe7a93SWei Yang /* 32497fbe7a93SWei Yang * On PowerNV platform, IOV BAR is mapped by M64 BAR to enable the 32507fbe7a93SWei Yang * SR-IOV. While from hardware perspective, the range mapped by M64 32517fbe7a93SWei Yang * BAR should be size aligned. 32527fbe7a93SWei Yang * 3253ee8222feSWei Yang * When IOV BAR is mapped with M64 BAR in Single PE mode, the extra 3254ee8222feSWei Yang * powernv-specific hardware restriction is gone. But if just use the 3255ee8222feSWei Yang * VF BAR size as the alignment, PF BAR / VF BAR may be allocated with 3256ee8222feSWei Yang * in one segment of M64 #15, which introduces the PE conflict between 3257ee8222feSWei Yang * PF and VF. Based on this, the minimum alignment of an IOV BAR is 3258ee8222feSWei Yang * m64_segsize. 3259ee8222feSWei Yang * 32607fbe7a93SWei Yang * This function returns the total IOV BAR size if M64 BAR is in 32617fbe7a93SWei Yang * Shared PE mode or just VF BAR size if not. 3262ee8222feSWei Yang * If the M64 BAR is in Single PE mode, return the VF BAR size or 3263ee8222feSWei Yang * M64 segment size if IOV BAR size is less. 32647fbe7a93SWei Yang */ 32655350ab3fSWei Yang align = pci_iov_resource_size(pdev, resno); 32667fbe7a93SWei Yang if (!pdn->vfs_expanded) 32675350ab3fSWei Yang return align; 3268ee8222feSWei Yang if (pdn->m64_single_mode) 3269ee8222feSWei Yang return max(align, (resource_size_t)phb->ioda.m64_segsize); 32707fbe7a93SWei Yang 32717fbe7a93SWei Yang return pdn->vfs_expanded * align; 32725350ab3fSWei Yang } 32735350ab3fSWei Yang #endif /* CONFIG_PCI_IOV */ 32745350ab3fSWei Yang 3275184cd4a3SBenjamin Herrenschmidt /* Prevent enabling devices for which we couldn't properly 3276184cd4a3SBenjamin Herrenschmidt * assign a PE 3277184cd4a3SBenjamin Herrenschmidt */ 3278c88c2a18SDaniel Axtens static bool pnv_pci_enable_device_hook(struct pci_dev *dev) 3279184cd4a3SBenjamin Herrenschmidt { 3280db1266c8SGavin Shan struct pci_controller *hose = pci_bus_to_host(dev->bus); 3281db1266c8SGavin Shan struct pnv_phb *phb = hose->private_data; 3282db1266c8SGavin Shan struct pci_dn *pdn; 3283184cd4a3SBenjamin Herrenschmidt 3284db1266c8SGavin Shan /* The function is probably called while the PEs have 3285db1266c8SGavin Shan * not be created yet. For example, resource reassignment 3286db1266c8SGavin Shan * during PCI probe period. We just skip the check if 3287db1266c8SGavin Shan * PEs isn't ready. 3288db1266c8SGavin Shan */ 3289db1266c8SGavin Shan if (!phb->initialized) 3290c88c2a18SDaniel Axtens return true; 3291db1266c8SGavin Shan 3292b72c1f65SBenjamin Herrenschmidt pdn = pci_get_pdn(dev); 3293184cd4a3SBenjamin Herrenschmidt if (!pdn || pdn->pe_number == IODA_INVALID_PE) 3294c88c2a18SDaniel Axtens return false; 3295db1266c8SGavin Shan 3296c88c2a18SDaniel Axtens return true; 3297184cd4a3SBenjamin Herrenschmidt } 3298184cd4a3SBenjamin Herrenschmidt 32997a8e6bbfSMichael Neuling static void pnv_pci_ioda_shutdown(struct pci_controller *hose) 330073ed148aSBenjamin Herrenschmidt { 33017a8e6bbfSMichael Neuling struct pnv_phb *phb = hose->private_data; 33027a8e6bbfSMichael Neuling 3303d1a85eeeSGavin Shan opal_pci_reset(phb->opal_id, OPAL_RESET_PCI_IODA_TABLE, 330473ed148aSBenjamin Herrenschmidt OPAL_ASSERT_RESET); 330573ed148aSBenjamin Herrenschmidt } 330673ed148aSBenjamin Herrenschmidt 330792ae0353SDaniel Axtens static const struct pci_controller_ops pnv_pci_ioda_controller_ops = { 330892ae0353SDaniel Axtens .dma_dev_setup = pnv_pci_dma_dev_setup, 33091bc74f1cSGavin Shan .dma_bus_setup = pnv_pci_dma_bus_setup, 331092ae0353SDaniel Axtens #ifdef CONFIG_PCI_MSI 331192ae0353SDaniel Axtens .setup_msi_irqs = pnv_setup_msi_irqs, 331292ae0353SDaniel Axtens .teardown_msi_irqs = pnv_teardown_msi_irqs, 331392ae0353SDaniel Axtens #endif 331492ae0353SDaniel Axtens .enable_device_hook = pnv_pci_enable_device_hook, 331592ae0353SDaniel Axtens .window_alignment = pnv_pci_window_alignment, 331692ae0353SDaniel Axtens .reset_secondary_bus = pnv_pci_reset_secondary_bus, 3317763d2d8dSDaniel Axtens .dma_set_mask = pnv_pci_ioda_dma_set_mask, 331853522982SAndrew Donnellan .dma_get_required_mask = pnv_pci_ioda_dma_get_required_mask, 33197a8e6bbfSMichael Neuling .shutdown = pnv_pci_ioda_shutdown, 332092ae0353SDaniel Axtens }; 332192ae0353SDaniel Axtens 33225d2aa710SAlistair Popple static const struct pci_controller_ops pnv_npu_ioda_controller_ops = { 33235d2aa710SAlistair Popple .dma_dev_setup = pnv_pci_dma_dev_setup, 33245d2aa710SAlistair Popple #ifdef CONFIG_PCI_MSI 33255d2aa710SAlistair Popple .setup_msi_irqs = pnv_setup_msi_irqs, 33265d2aa710SAlistair Popple .teardown_msi_irqs = pnv_teardown_msi_irqs, 33275d2aa710SAlistair Popple #endif 33285d2aa710SAlistair Popple .enable_device_hook = pnv_pci_enable_device_hook, 33295d2aa710SAlistair Popple .window_alignment = pnv_pci_window_alignment, 33305d2aa710SAlistair Popple .reset_secondary_bus = pnv_pci_reset_secondary_bus, 33315d2aa710SAlistair Popple .dma_set_mask = pnv_npu_dma_set_mask, 33325d2aa710SAlistair Popple .shutdown = pnv_pci_ioda_shutdown, 33335d2aa710SAlistair Popple }; 33345d2aa710SAlistair Popple 3335e51df2c1SAnton Blanchard static void __init pnv_pci_init_ioda_phb(struct device_node *np, 3336e9cc17d4SGavin Shan u64 hub_id, int ioda_type) 3337184cd4a3SBenjamin Herrenschmidt { 3338184cd4a3SBenjamin Herrenschmidt struct pci_controller *hose; 3339184cd4a3SBenjamin Herrenschmidt struct pnv_phb *phb; 334093289d8cSGavin Shan unsigned long size, m64map_off, m32map_off, pemap_off, iomap_off = 0; 3341c681b93cSAlistair Popple const __be64 *prop64; 33423a1a4661SBenjamin Herrenschmidt const __be32 *prop32; 3343f1b7cc3eSGavin Shan int len; 33443fa23ff8SGavin Shan unsigned int segno; 3345184cd4a3SBenjamin Herrenschmidt u64 phb_id; 3346184cd4a3SBenjamin Herrenschmidt void *aux; 3347184cd4a3SBenjamin Herrenschmidt long rc; 3348184cd4a3SBenjamin Herrenschmidt 3349aa0c033fSGavin Shan pr_info("Initializing IODA%d OPAL PHB %s\n", ioda_type, np->full_name); 3350184cd4a3SBenjamin Herrenschmidt 3351184cd4a3SBenjamin Herrenschmidt prop64 = of_get_property(np, "ibm,opal-phbid", NULL); 3352184cd4a3SBenjamin Herrenschmidt if (!prop64) { 3353184cd4a3SBenjamin Herrenschmidt pr_err(" Missing \"ibm,opal-phbid\" property !\n"); 3354184cd4a3SBenjamin Herrenschmidt return; 3355184cd4a3SBenjamin Herrenschmidt } 3356184cd4a3SBenjamin Herrenschmidt phb_id = be64_to_cpup(prop64); 3357184cd4a3SBenjamin Herrenschmidt pr_debug(" PHB-ID : 0x%016llx\n", phb_id); 3358184cd4a3SBenjamin Herrenschmidt 3359e39f223fSMichael Ellerman phb = memblock_virt_alloc(sizeof(struct pnv_phb), 0); 336058d714ecSGavin Shan 336158d714ecSGavin Shan /* Allocate PCI controller */ 3362184cd4a3SBenjamin Herrenschmidt phb->hose = hose = pcibios_alloc_controller(np); 336358d714ecSGavin Shan if (!phb->hose) { 336458d714ecSGavin Shan pr_err(" Can't allocate PCI controller for %s\n", 3365184cd4a3SBenjamin Herrenschmidt np->full_name); 3366e39f223fSMichael Ellerman memblock_free(__pa(phb), sizeof(struct pnv_phb)); 3367184cd4a3SBenjamin Herrenschmidt return; 3368184cd4a3SBenjamin Herrenschmidt } 3369184cd4a3SBenjamin Herrenschmidt 3370184cd4a3SBenjamin Herrenschmidt spin_lock_init(&phb->lock); 3371f1b7cc3eSGavin Shan prop32 = of_get_property(np, "bus-range", &len); 3372f1b7cc3eSGavin Shan if (prop32 && len == 8) { 33733a1a4661SBenjamin Herrenschmidt hose->first_busno = be32_to_cpu(prop32[0]); 33743a1a4661SBenjamin Herrenschmidt hose->last_busno = be32_to_cpu(prop32[1]); 3375f1b7cc3eSGavin Shan } else { 3376f1b7cc3eSGavin Shan pr_warn(" Broken <bus-range> on %s\n", np->full_name); 3377184cd4a3SBenjamin Herrenschmidt hose->first_busno = 0; 3378184cd4a3SBenjamin Herrenschmidt hose->last_busno = 0xff; 3379f1b7cc3eSGavin Shan } 3380184cd4a3SBenjamin Herrenschmidt hose->private_data = phb; 3381e9cc17d4SGavin Shan phb->hub_id = hub_id; 3382184cd4a3SBenjamin Herrenschmidt phb->opal_id = phb_id; 3383aa0c033fSGavin Shan phb->type = ioda_type; 3384781a868fSWei Yang mutex_init(&phb->ioda.pe_alloc_mutex); 3385184cd4a3SBenjamin Herrenschmidt 3386cee72d5bSBenjamin Herrenschmidt /* Detect specific models for error handling */ 3387cee72d5bSBenjamin Herrenschmidt if (of_device_is_compatible(np, "ibm,p7ioc-pciex")) 3388cee72d5bSBenjamin Herrenschmidt phb->model = PNV_PHB_MODEL_P7IOC; 3389f3d40c25SBenjamin Herrenschmidt else if (of_device_is_compatible(np, "ibm,power8-pciex")) 3390aa0c033fSGavin Shan phb->model = PNV_PHB_MODEL_PHB3; 33915d2aa710SAlistair Popple else if (of_device_is_compatible(np, "ibm,power8-npu-pciex")) 33925d2aa710SAlistair Popple phb->model = PNV_PHB_MODEL_NPU; 3393cee72d5bSBenjamin Herrenschmidt else 3394cee72d5bSBenjamin Herrenschmidt phb->model = PNV_PHB_MODEL_UNKNOWN; 3395cee72d5bSBenjamin Herrenschmidt 3396aa0c033fSGavin Shan /* Parse 32-bit and IO ranges (if any) */ 33972f1ec02eSGavin Shan pci_process_bridge_OF_ranges(hose, np, !hose->global_number); 3398184cd4a3SBenjamin Herrenschmidt 3399aa0c033fSGavin Shan /* Get registers */ 3400184cd4a3SBenjamin Herrenschmidt phb->regs = of_iomap(np, 0); 3401184cd4a3SBenjamin Herrenschmidt if (phb->regs == NULL) 3402184cd4a3SBenjamin Herrenschmidt pr_err(" Failed to map registers !\n"); 3403184cd4a3SBenjamin Herrenschmidt 3404184cd4a3SBenjamin Herrenschmidt /* Initialize more IODA stuff */ 340592b8f137SGavin Shan phb->ioda.total_pe_num = 1; 340636954dc7SGavin Shan prop32 = of_get_property(np, "ibm,opal-num-pes", NULL); 340736954dc7SGavin Shan if (prop32) 340892b8f137SGavin Shan phb->ioda.total_pe_num = be32_to_cpup(prop32); 340936954dc7SGavin Shan prop32 = of_get_property(np, "ibm,opal-reserved-pe", NULL); 341036954dc7SGavin Shan if (prop32) 341192b8f137SGavin Shan phb->ioda.reserved_pe_idx = be32_to_cpup(prop32); 3412262af557SGuo Chao 3413262af557SGuo Chao /* Parse 64-bit MMIO range */ 3414262af557SGuo Chao pnv_ioda_parse_m64_window(phb); 3415262af557SGuo Chao 3416184cd4a3SBenjamin Herrenschmidt phb->ioda.m32_size = resource_size(&hose->mem_resources[0]); 3417aa0c033fSGavin Shan /* FW Has already off top 64k of M32 space (MSI space) */ 3418184cd4a3SBenjamin Herrenschmidt phb->ioda.m32_size += 0x10000; 3419184cd4a3SBenjamin Herrenschmidt 342092b8f137SGavin Shan phb->ioda.m32_segsize = phb->ioda.m32_size / phb->ioda.total_pe_num; 34213fd47f06SBenjamin Herrenschmidt phb->ioda.m32_pci_base = hose->mem_resources[0].start - hose->mem_offset[0]; 3422184cd4a3SBenjamin Herrenschmidt phb->ioda.io_size = hose->pci_io_size; 342392b8f137SGavin Shan phb->ioda.io_segsize = phb->ioda.io_size / phb->ioda.total_pe_num; 3424184cd4a3SBenjamin Herrenschmidt phb->ioda.io_pci_base = 0; /* XXX calculate this ? */ 3425184cd4a3SBenjamin Herrenschmidt 3426c35d2a8cSGavin Shan /* Allocate aux data & arrays. We don't have IO ports on PHB3 */ 342792b8f137SGavin Shan size = _ALIGN_UP(phb->ioda.total_pe_num / 8, sizeof(unsigned long)); 342893289d8cSGavin Shan m64map_off = size; 342993289d8cSGavin Shan size += phb->ioda.total_pe_num * sizeof(phb->ioda.m64_segmap[0]); 3430184cd4a3SBenjamin Herrenschmidt m32map_off = size; 343192b8f137SGavin Shan size += phb->ioda.total_pe_num * sizeof(phb->ioda.m32_segmap[0]); 3432c35d2a8cSGavin Shan if (phb->type == PNV_PHB_IODA1) { 3433c35d2a8cSGavin Shan iomap_off = size; 343492b8f137SGavin Shan size += phb->ioda.total_pe_num * sizeof(phb->ioda.io_segmap[0]); 3435c35d2a8cSGavin Shan } 3436184cd4a3SBenjamin Herrenschmidt pemap_off = size; 343792b8f137SGavin Shan size += phb->ioda.total_pe_num * sizeof(struct pnv_ioda_pe); 3438e39f223fSMichael Ellerman aux = memblock_virt_alloc(size, 0); 3439184cd4a3SBenjamin Herrenschmidt phb->ioda.pe_alloc = aux; 344093289d8cSGavin Shan phb->ioda.m64_segmap = aux + m64map_off; 3441184cd4a3SBenjamin Herrenschmidt phb->ioda.m32_segmap = aux + m32map_off; 344293289d8cSGavin Shan for (segno = 0; segno < phb->ioda.total_pe_num; segno++) { 344393289d8cSGavin Shan phb->ioda.m64_segmap[segno] = IODA_INVALID_PE; 34443fa23ff8SGavin Shan phb->ioda.m32_segmap[segno] = IODA_INVALID_PE; 344593289d8cSGavin Shan } 34463fa23ff8SGavin Shan if (phb->type == PNV_PHB_IODA1) { 3447184cd4a3SBenjamin Herrenschmidt phb->ioda.io_segmap = aux + iomap_off; 34483fa23ff8SGavin Shan for (segno = 0; segno < phb->ioda.total_pe_num; segno++) 34493fa23ff8SGavin Shan phb->ioda.io_segmap[segno] = IODA_INVALID_PE; 34503fa23ff8SGavin Shan } 3451184cd4a3SBenjamin Herrenschmidt phb->ioda.pe_array = aux + pemap_off; 345292b8f137SGavin Shan set_bit(phb->ioda.reserved_pe_idx, phb->ioda.pe_alloc); 3453184cd4a3SBenjamin Herrenschmidt 34547ebdf956SGavin Shan INIT_LIST_HEAD(&phb->ioda.pe_dma_list); 3455184cd4a3SBenjamin Herrenschmidt INIT_LIST_HEAD(&phb->ioda.pe_list); 3456781a868fSWei Yang mutex_init(&phb->ioda.pe_list_mutex); 3457184cd4a3SBenjamin Herrenschmidt 3458184cd4a3SBenjamin Herrenschmidt /* Calculate how many 32-bit TCE segments we have */ 3459184cd4a3SBenjamin Herrenschmidt phb->ioda.tce32_count = phb->ioda.m32_pci_base >> 28; 3460184cd4a3SBenjamin Herrenschmidt 3461aa0c033fSGavin Shan #if 0 /* We should really do that ... */ 3462184cd4a3SBenjamin Herrenschmidt rc = opal_pci_set_phb_mem_window(opal->phb_id, 3463184cd4a3SBenjamin Herrenschmidt window_type, 3464184cd4a3SBenjamin Herrenschmidt window_num, 3465184cd4a3SBenjamin Herrenschmidt starting_real_address, 3466184cd4a3SBenjamin Herrenschmidt starting_pci_address, 3467184cd4a3SBenjamin Herrenschmidt segment_size); 3468184cd4a3SBenjamin Herrenschmidt #endif 3469184cd4a3SBenjamin Herrenschmidt 3470262af557SGuo Chao pr_info(" %03d (%03d) PE's M32: 0x%x [segment=0x%x]\n", 347192b8f137SGavin Shan phb->ioda.total_pe_num, phb->ioda.reserved_pe_idx, 3472262af557SGuo Chao phb->ioda.m32_size, phb->ioda.m32_segsize); 3473262af557SGuo Chao if (phb->ioda.m64_size) 3474262af557SGuo Chao pr_info(" M64: 0x%lx [segment=0x%lx]\n", 3475262af557SGuo Chao phb->ioda.m64_size, phb->ioda.m64_segsize); 3476262af557SGuo Chao if (phb->ioda.io_size) 3477262af557SGuo Chao pr_info(" IO: 0x%x [segment=0x%x]\n", 3478184cd4a3SBenjamin Herrenschmidt phb->ioda.io_size, phb->ioda.io_segsize); 3479184cd4a3SBenjamin Herrenschmidt 3480262af557SGuo Chao 3481184cd4a3SBenjamin Herrenschmidt phb->hose->ops = &pnv_pci_ops; 348249dec922SGavin Shan phb->get_pe_state = pnv_ioda_get_pe_state; 348349dec922SGavin Shan phb->freeze_pe = pnv_ioda_freeze_pe; 348449dec922SGavin Shan phb->unfreeze_pe = pnv_ioda_unfreeze_pe; 3485184cd4a3SBenjamin Herrenschmidt 3486184cd4a3SBenjamin Herrenschmidt /* Setup TCEs */ 3487184cd4a3SBenjamin Herrenschmidt phb->dma_dev_setup = pnv_pci_ioda_dma_dev_setup; 3488184cd4a3SBenjamin Herrenschmidt 3489184cd4a3SBenjamin Herrenschmidt /* Setup MSI support */ 3490184cd4a3SBenjamin Herrenschmidt pnv_pci_init_ioda_msis(phb); 3491184cd4a3SBenjamin Herrenschmidt 3492c40a4210SGavin Shan /* 3493c40a4210SGavin Shan * We pass the PCI probe flag PCI_REASSIGN_ALL_RSRC here 3494c40a4210SGavin Shan * to let the PCI core do resource assignment. It's supposed 3495c40a4210SGavin Shan * that the PCI core will do correct I/O and MMIO alignment 3496c40a4210SGavin Shan * for the P2P bridge bars so that each PCI bus (excluding 3497c40a4210SGavin Shan * the child P2P bridges) can form individual PE. 3498184cd4a3SBenjamin Herrenschmidt */ 3499fb446ad0SGavin Shan ppc_md.pcibios_fixup = pnv_pci_ioda_fixup; 35005d2aa710SAlistair Popple 35015d2aa710SAlistair Popple if (phb->type == PNV_PHB_NPU) 35025d2aa710SAlistair Popple hose->controller_ops = pnv_npu_ioda_controller_ops; 35035d2aa710SAlistair Popple else 350492ae0353SDaniel Axtens hose->controller_ops = pnv_pci_ioda_controller_ops; 3505ad30cb99SMichael Ellerman 35066e628c7dSWei Yang #ifdef CONFIG_PCI_IOV 35076e628c7dSWei Yang ppc_md.pcibios_fixup_sriov = pnv_pci_ioda_fixup_iov_resources; 35085350ab3fSWei Yang ppc_md.pcibios_iov_resource_alignment = pnv_pci_iov_resource_alignment; 3509ad30cb99SMichael Ellerman #endif 3510ad30cb99SMichael Ellerman 3511c40a4210SGavin Shan pci_add_flags(PCI_REASSIGN_ALL_RSRC); 3512184cd4a3SBenjamin Herrenschmidt 3513184cd4a3SBenjamin Herrenschmidt /* Reset IODA tables to a clean state */ 3514d1a85eeeSGavin Shan rc = opal_pci_reset(phb_id, OPAL_RESET_PCI_IODA_TABLE, OPAL_ASSERT_RESET); 3515184cd4a3SBenjamin Herrenschmidt if (rc) 3516f11fe552SBenjamin Herrenschmidt pr_warning(" OPAL Error %ld performing IODA table reset !\n", rc); 3517361f2a2aSGavin Shan 3518361f2a2aSGavin Shan /* If we're running in kdump kerenl, the previous kerenl never 3519361f2a2aSGavin Shan * shutdown PCI devices correctly. We already got IODA table 3520361f2a2aSGavin Shan * cleaned out. So we have to issue PHB reset to stop all PCI 3521361f2a2aSGavin Shan * transactions from previous kerenl. 3522361f2a2aSGavin Shan */ 3523361f2a2aSGavin Shan if (is_kdump_kernel()) { 3524361f2a2aSGavin Shan pr_info(" Issue PHB reset ...\n"); 3525cadf364dSGavin Shan pnv_eeh_phb_reset(hose, EEH_RESET_FUNDAMENTAL); 3526cadf364dSGavin Shan pnv_eeh_phb_reset(hose, EEH_RESET_DEACTIVATE); 3527361f2a2aSGavin Shan } 3528262af557SGuo Chao 35299e9e8935SGavin Shan /* Remove M64 resource if we can't configure it successfully */ 35309e9e8935SGavin Shan if (!phb->init_m64 || phb->init_m64(phb)) 3531262af557SGuo Chao hose->mem_resources[1].flags = 0; 3532184cd4a3SBenjamin Herrenschmidt } 3533184cd4a3SBenjamin Herrenschmidt 353467975005SBjorn Helgaas void __init pnv_pci_init_ioda2_phb(struct device_node *np) 3535aa0c033fSGavin Shan { 3536e9cc17d4SGavin Shan pnv_pci_init_ioda_phb(np, 0, PNV_PHB_IODA2); 3537aa0c033fSGavin Shan } 3538aa0c033fSGavin Shan 35395d2aa710SAlistair Popple void __init pnv_pci_init_npu_phb(struct device_node *np) 35405d2aa710SAlistair Popple { 35415d2aa710SAlistair Popple pnv_pci_init_ioda_phb(np, 0, PNV_PHB_NPU); 35425d2aa710SAlistair Popple } 35435d2aa710SAlistair Popple 3544184cd4a3SBenjamin Herrenschmidt void __init pnv_pci_init_ioda_hub(struct device_node *np) 3545184cd4a3SBenjamin Herrenschmidt { 3546184cd4a3SBenjamin Herrenschmidt struct device_node *phbn; 3547c681b93cSAlistair Popple const __be64 *prop64; 3548184cd4a3SBenjamin Herrenschmidt u64 hub_id; 3549184cd4a3SBenjamin Herrenschmidt 3550184cd4a3SBenjamin Herrenschmidt pr_info("Probing IODA IO-Hub %s\n", np->full_name); 3551184cd4a3SBenjamin Herrenschmidt 3552184cd4a3SBenjamin Herrenschmidt prop64 = of_get_property(np, "ibm,opal-hubid", NULL); 3553184cd4a3SBenjamin Herrenschmidt if (!prop64) { 3554184cd4a3SBenjamin Herrenschmidt pr_err(" Missing \"ibm,opal-hubid\" property !\n"); 3555184cd4a3SBenjamin Herrenschmidt return; 3556184cd4a3SBenjamin Herrenschmidt } 3557184cd4a3SBenjamin Herrenschmidt hub_id = be64_to_cpup(prop64); 3558184cd4a3SBenjamin Herrenschmidt pr_devel(" HUB-ID : 0x%016llx\n", hub_id); 3559184cd4a3SBenjamin Herrenschmidt 3560184cd4a3SBenjamin Herrenschmidt /* Count child PHBs */ 3561184cd4a3SBenjamin Herrenschmidt for_each_child_of_node(np, phbn) { 3562184cd4a3SBenjamin Herrenschmidt /* Look for IODA1 PHBs */ 3563184cd4a3SBenjamin Herrenschmidt if (of_device_is_compatible(phbn, "ibm,ioda-phb")) 3564e9cc17d4SGavin Shan pnv_pci_init_ioda_phb(phbn, hub_id, PNV_PHB_IODA1); 3565184cd4a3SBenjamin Herrenschmidt } 3566184cd4a3SBenjamin Herrenschmidt } 3567