1184cd4a3SBenjamin Herrenschmidt /* 2184cd4a3SBenjamin Herrenschmidt * Support PCI/PCIe on PowerNV platforms 3184cd4a3SBenjamin Herrenschmidt * 4184cd4a3SBenjamin Herrenschmidt * Copyright 2011 Benjamin Herrenschmidt, IBM Corp. 5184cd4a3SBenjamin Herrenschmidt * 6184cd4a3SBenjamin Herrenschmidt * This program is free software; you can redistribute it and/or 7184cd4a3SBenjamin Herrenschmidt * modify it under the terms of the GNU General Public License 8184cd4a3SBenjamin Herrenschmidt * as published by the Free Software Foundation; either version 9184cd4a3SBenjamin Herrenschmidt * 2 of the License, or (at your option) any later version. 10184cd4a3SBenjamin Herrenschmidt */ 11184cd4a3SBenjamin Herrenschmidt 12cee72d5bSBenjamin Herrenschmidt #undef DEBUG 13184cd4a3SBenjamin Herrenschmidt 14184cd4a3SBenjamin Herrenschmidt #include <linux/kernel.h> 15184cd4a3SBenjamin Herrenschmidt #include <linux/pci.h> 16184cd4a3SBenjamin Herrenschmidt #include <linux/delay.h> 17184cd4a3SBenjamin Herrenschmidt #include <linux/string.h> 18184cd4a3SBenjamin Herrenschmidt #include <linux/init.h> 19184cd4a3SBenjamin Herrenschmidt #include <linux/bootmem.h> 20184cd4a3SBenjamin Herrenschmidt #include <linux/irq.h> 21184cd4a3SBenjamin Herrenschmidt #include <linux/io.h> 22184cd4a3SBenjamin Herrenschmidt #include <linux/msi.h> 23184cd4a3SBenjamin Herrenschmidt 24184cd4a3SBenjamin Herrenschmidt #include <asm/sections.h> 25184cd4a3SBenjamin Herrenschmidt #include <asm/io.h> 26184cd4a3SBenjamin Herrenschmidt #include <asm/prom.h> 27184cd4a3SBenjamin Herrenschmidt #include <asm/pci-bridge.h> 28184cd4a3SBenjamin Herrenschmidt #include <asm/machdep.h> 29fb1b55d6SGavin Shan #include <asm/msi_bitmap.h> 30184cd4a3SBenjamin Herrenschmidt #include <asm/ppc-pci.h> 31184cd4a3SBenjamin Herrenschmidt #include <asm/opal.h> 32184cd4a3SBenjamin Herrenschmidt #include <asm/iommu.h> 33184cd4a3SBenjamin Herrenschmidt #include <asm/tce.h> 34184cd4a3SBenjamin Herrenschmidt 35184cd4a3SBenjamin Herrenschmidt #include "powernv.h" 36184cd4a3SBenjamin Herrenschmidt #include "pci.h" 37184cd4a3SBenjamin Herrenschmidt 38184cd4a3SBenjamin Herrenschmidt #define define_pe_printk_level(func, kern_level) \ 39184cd4a3SBenjamin Herrenschmidt static int func(const struct pnv_ioda_pe *pe, const char *fmt, ...) \ 40184cd4a3SBenjamin Herrenschmidt { \ 41184cd4a3SBenjamin Herrenschmidt struct va_format vaf; \ 42184cd4a3SBenjamin Herrenschmidt va_list args; \ 43490e078dSGavin Shan char pfix[32]; \ 44184cd4a3SBenjamin Herrenschmidt int r; \ 45184cd4a3SBenjamin Herrenschmidt \ 46184cd4a3SBenjamin Herrenschmidt va_start(args, fmt); \ 47184cd4a3SBenjamin Herrenschmidt \ 48184cd4a3SBenjamin Herrenschmidt vaf.fmt = fmt; \ 49184cd4a3SBenjamin Herrenschmidt vaf.va = &args; \ 50184cd4a3SBenjamin Herrenschmidt \ 51490e078dSGavin Shan if (pe->pdev) \ 52490e078dSGavin Shan strlcpy(pfix, dev_name(&pe->pdev->dev), \ 53490e078dSGavin Shan sizeof(pfix)); \ 54490e078dSGavin Shan else \ 55490e078dSGavin Shan sprintf(pfix, "%04x:%02x ", \ 56490e078dSGavin Shan pci_domain_nr(pe->pbus), \ 57490e078dSGavin Shan pe->pbus->number); \ 58490e078dSGavin Shan r = printk(kern_level "pci %s: [PE# %.3d] %pV", \ 59490e078dSGavin Shan pfix, pe->pe_number, &vaf); \ 60490e078dSGavin Shan \ 61184cd4a3SBenjamin Herrenschmidt va_end(args); \ 62184cd4a3SBenjamin Herrenschmidt \ 63184cd4a3SBenjamin Herrenschmidt return r; \ 64184cd4a3SBenjamin Herrenschmidt } \ 65184cd4a3SBenjamin Herrenschmidt 66184cd4a3SBenjamin Herrenschmidt define_pe_printk_level(pe_err, KERN_ERR); 67184cd4a3SBenjamin Herrenschmidt define_pe_printk_level(pe_warn, KERN_WARNING); 68184cd4a3SBenjamin Herrenschmidt define_pe_printk_level(pe_info, KERN_INFO); 69184cd4a3SBenjamin Herrenschmidt 70184cd4a3SBenjamin Herrenschmidt static struct pci_dn *pnv_ioda_get_pdn(struct pci_dev *dev) 71184cd4a3SBenjamin Herrenschmidt { 72184cd4a3SBenjamin Herrenschmidt struct device_node *np; 73184cd4a3SBenjamin Herrenschmidt 74184cd4a3SBenjamin Herrenschmidt np = pci_device_to_OF_node(dev); 75184cd4a3SBenjamin Herrenschmidt if (!np) 76184cd4a3SBenjamin Herrenschmidt return NULL; 77184cd4a3SBenjamin Herrenschmidt return PCI_DN(np); 78184cd4a3SBenjamin Herrenschmidt } 79184cd4a3SBenjamin Herrenschmidt 80cad5cef6SGreg Kroah-Hartman static int pnv_ioda_alloc_pe(struct pnv_phb *phb) 81184cd4a3SBenjamin Herrenschmidt { 82184cd4a3SBenjamin Herrenschmidt unsigned long pe; 83184cd4a3SBenjamin Herrenschmidt 84184cd4a3SBenjamin Herrenschmidt do { 85184cd4a3SBenjamin Herrenschmidt pe = find_next_zero_bit(phb->ioda.pe_alloc, 86184cd4a3SBenjamin Herrenschmidt phb->ioda.total_pe, 0); 87184cd4a3SBenjamin Herrenschmidt if (pe >= phb->ioda.total_pe) 88184cd4a3SBenjamin Herrenschmidt return IODA_INVALID_PE; 89184cd4a3SBenjamin Herrenschmidt } while(test_and_set_bit(pe, phb->ioda.pe_alloc)); 90184cd4a3SBenjamin Herrenschmidt 91184cd4a3SBenjamin Herrenschmidt phb->ioda.pe_array[pe].pe_number = pe; 92184cd4a3SBenjamin Herrenschmidt return pe; 93184cd4a3SBenjamin Herrenschmidt } 94184cd4a3SBenjamin Herrenschmidt 95cad5cef6SGreg Kroah-Hartman static void pnv_ioda_free_pe(struct pnv_phb *phb, int pe) 96184cd4a3SBenjamin Herrenschmidt { 97184cd4a3SBenjamin Herrenschmidt WARN_ON(phb->ioda.pe_array[pe].pdev); 98184cd4a3SBenjamin Herrenschmidt 99184cd4a3SBenjamin Herrenschmidt memset(&phb->ioda.pe_array[pe], 0, sizeof(struct pnv_ioda_pe)); 100184cd4a3SBenjamin Herrenschmidt clear_bit(pe, phb->ioda.pe_alloc); 101184cd4a3SBenjamin Herrenschmidt } 102184cd4a3SBenjamin Herrenschmidt 103184cd4a3SBenjamin Herrenschmidt /* Currently those 2 are only used when MSIs are enabled, this will change 104184cd4a3SBenjamin Herrenschmidt * but in the meantime, we need to protect them to avoid warnings 105184cd4a3SBenjamin Herrenschmidt */ 106184cd4a3SBenjamin Herrenschmidt #ifdef CONFIG_PCI_MSI 107cad5cef6SGreg Kroah-Hartman static struct pnv_ioda_pe *pnv_ioda_get_pe(struct pci_dev *dev) 108184cd4a3SBenjamin Herrenschmidt { 109184cd4a3SBenjamin Herrenschmidt struct pci_controller *hose = pci_bus_to_host(dev->bus); 110184cd4a3SBenjamin Herrenschmidt struct pnv_phb *phb = hose->private_data; 111184cd4a3SBenjamin Herrenschmidt struct pci_dn *pdn = pnv_ioda_get_pdn(dev); 112184cd4a3SBenjamin Herrenschmidt 113184cd4a3SBenjamin Herrenschmidt if (!pdn) 114184cd4a3SBenjamin Herrenschmidt return NULL; 115184cd4a3SBenjamin Herrenschmidt if (pdn->pe_number == IODA_INVALID_PE) 116184cd4a3SBenjamin Herrenschmidt return NULL; 117184cd4a3SBenjamin Herrenschmidt return &phb->ioda.pe_array[pdn->pe_number]; 118184cd4a3SBenjamin Herrenschmidt } 119184cd4a3SBenjamin Herrenschmidt #endif /* CONFIG_PCI_MSI */ 120184cd4a3SBenjamin Herrenschmidt 121cad5cef6SGreg Kroah-Hartman static int pnv_ioda_configure_pe(struct pnv_phb *phb, struct pnv_ioda_pe *pe) 122184cd4a3SBenjamin Herrenschmidt { 123184cd4a3SBenjamin Herrenschmidt struct pci_dev *parent; 124184cd4a3SBenjamin Herrenschmidt uint8_t bcomp, dcomp, fcomp; 125184cd4a3SBenjamin Herrenschmidt long rc, rid_end, rid; 126184cd4a3SBenjamin Herrenschmidt 127184cd4a3SBenjamin Herrenschmidt /* Bus validation ? */ 128184cd4a3SBenjamin Herrenschmidt if (pe->pbus) { 129184cd4a3SBenjamin Herrenschmidt int count; 130184cd4a3SBenjamin Herrenschmidt 131184cd4a3SBenjamin Herrenschmidt dcomp = OPAL_IGNORE_RID_DEVICE_NUMBER; 132184cd4a3SBenjamin Herrenschmidt fcomp = OPAL_IGNORE_RID_FUNCTION_NUMBER; 133184cd4a3SBenjamin Herrenschmidt parent = pe->pbus->self; 134fb446ad0SGavin Shan if (pe->flags & PNV_IODA_PE_BUS_ALL) 135b918c62eSYinghai Lu count = pe->pbus->busn_res.end - pe->pbus->busn_res.start + 1; 136fb446ad0SGavin Shan else 137fb446ad0SGavin Shan count = 1; 138fb446ad0SGavin Shan 139184cd4a3SBenjamin Herrenschmidt switch(count) { 140184cd4a3SBenjamin Herrenschmidt case 1: bcomp = OpalPciBusAll; break; 141184cd4a3SBenjamin Herrenschmidt case 2: bcomp = OpalPciBus7Bits; break; 142184cd4a3SBenjamin Herrenschmidt case 4: bcomp = OpalPciBus6Bits; break; 143184cd4a3SBenjamin Herrenschmidt case 8: bcomp = OpalPciBus5Bits; break; 144184cd4a3SBenjamin Herrenschmidt case 16: bcomp = OpalPciBus4Bits; break; 145184cd4a3SBenjamin Herrenschmidt case 32: bcomp = OpalPciBus3Bits; break; 146184cd4a3SBenjamin Herrenschmidt default: 147184cd4a3SBenjamin Herrenschmidt pr_err("%s: Number of subordinate busses %d" 148184cd4a3SBenjamin Herrenschmidt " unsupported\n", 149184cd4a3SBenjamin Herrenschmidt pci_name(pe->pbus->self), count); 150184cd4a3SBenjamin Herrenschmidt /* Do an exact match only */ 151184cd4a3SBenjamin Herrenschmidt bcomp = OpalPciBusAll; 152184cd4a3SBenjamin Herrenschmidt } 153184cd4a3SBenjamin Herrenschmidt rid_end = pe->rid + (count << 8); 154184cd4a3SBenjamin Herrenschmidt } else { 155184cd4a3SBenjamin Herrenschmidt parent = pe->pdev->bus->self; 156184cd4a3SBenjamin Herrenschmidt bcomp = OpalPciBusAll; 157184cd4a3SBenjamin Herrenschmidt dcomp = OPAL_COMPARE_RID_DEVICE_NUMBER; 158184cd4a3SBenjamin Herrenschmidt fcomp = OPAL_COMPARE_RID_FUNCTION_NUMBER; 159184cd4a3SBenjamin Herrenschmidt rid_end = pe->rid + 1; 160184cd4a3SBenjamin Herrenschmidt } 161184cd4a3SBenjamin Herrenschmidt 162184cd4a3SBenjamin Herrenschmidt /* Associate PE in PELT */ 163184cd4a3SBenjamin Herrenschmidt rc = opal_pci_set_pe(phb->opal_id, pe->pe_number, pe->rid, 164184cd4a3SBenjamin Herrenschmidt bcomp, dcomp, fcomp, OPAL_MAP_PE); 165184cd4a3SBenjamin Herrenschmidt if (rc) { 166184cd4a3SBenjamin Herrenschmidt pe_err(pe, "OPAL error %ld trying to setup PELT table\n", rc); 167184cd4a3SBenjamin Herrenschmidt return -ENXIO; 168184cd4a3SBenjamin Herrenschmidt } 169184cd4a3SBenjamin Herrenschmidt opal_pci_eeh_freeze_clear(phb->opal_id, pe->pe_number, 170184cd4a3SBenjamin Herrenschmidt OPAL_EEH_ACTION_CLEAR_FREEZE_ALL); 171184cd4a3SBenjamin Herrenschmidt 172184cd4a3SBenjamin Herrenschmidt /* Add to all parents PELT-V */ 173184cd4a3SBenjamin Herrenschmidt while (parent) { 174184cd4a3SBenjamin Herrenschmidt struct pci_dn *pdn = pnv_ioda_get_pdn(parent); 175184cd4a3SBenjamin Herrenschmidt if (pdn && pdn->pe_number != IODA_INVALID_PE) { 176184cd4a3SBenjamin Herrenschmidt rc = opal_pci_set_peltv(phb->opal_id, pdn->pe_number, 177cee72d5bSBenjamin Herrenschmidt pe->pe_number, OPAL_ADD_PE_TO_DOMAIN); 178184cd4a3SBenjamin Herrenschmidt /* XXX What to do in case of error ? */ 179184cd4a3SBenjamin Herrenschmidt } 180184cd4a3SBenjamin Herrenschmidt parent = parent->bus->self; 181184cd4a3SBenjamin Herrenschmidt } 182184cd4a3SBenjamin Herrenschmidt /* Setup reverse map */ 183184cd4a3SBenjamin Herrenschmidt for (rid = pe->rid; rid < rid_end; rid++) 184184cd4a3SBenjamin Herrenschmidt phb->ioda.pe_rmap[rid] = pe->pe_number; 185184cd4a3SBenjamin Herrenschmidt 186184cd4a3SBenjamin Herrenschmidt /* Setup one MVTs on IODA1 */ 187184cd4a3SBenjamin Herrenschmidt if (phb->type == PNV_PHB_IODA1) { 188184cd4a3SBenjamin Herrenschmidt pe->mve_number = pe->pe_number; 189184cd4a3SBenjamin Herrenschmidt rc = opal_pci_set_mve(phb->opal_id, pe->mve_number, 190184cd4a3SBenjamin Herrenschmidt pe->pe_number); 191184cd4a3SBenjamin Herrenschmidt if (rc) { 192184cd4a3SBenjamin Herrenschmidt pe_err(pe, "OPAL error %ld setting up MVE %d\n", 193184cd4a3SBenjamin Herrenschmidt rc, pe->mve_number); 194184cd4a3SBenjamin Herrenschmidt pe->mve_number = -1; 195184cd4a3SBenjamin Herrenschmidt } else { 196184cd4a3SBenjamin Herrenschmidt rc = opal_pci_set_mve_enable(phb->opal_id, 197cee72d5bSBenjamin Herrenschmidt pe->mve_number, OPAL_ENABLE_MVE); 198184cd4a3SBenjamin Herrenschmidt if (rc) { 199184cd4a3SBenjamin Herrenschmidt pe_err(pe, "OPAL error %ld enabling MVE %d\n", 200184cd4a3SBenjamin Herrenschmidt rc, pe->mve_number); 201184cd4a3SBenjamin Herrenschmidt pe->mve_number = -1; 202184cd4a3SBenjamin Herrenschmidt } 203184cd4a3SBenjamin Herrenschmidt } 204184cd4a3SBenjamin Herrenschmidt } else if (phb->type == PNV_PHB_IODA2) 205184cd4a3SBenjamin Herrenschmidt pe->mve_number = 0; 206184cd4a3SBenjamin Herrenschmidt 207184cd4a3SBenjamin Herrenschmidt return 0; 208184cd4a3SBenjamin Herrenschmidt } 209184cd4a3SBenjamin Herrenschmidt 210cad5cef6SGreg Kroah-Hartman static void pnv_ioda_link_pe_by_weight(struct pnv_phb *phb, 211184cd4a3SBenjamin Herrenschmidt struct pnv_ioda_pe *pe) 212184cd4a3SBenjamin Herrenschmidt { 213184cd4a3SBenjamin Herrenschmidt struct pnv_ioda_pe *lpe; 214184cd4a3SBenjamin Herrenschmidt 2157ebdf956SGavin Shan list_for_each_entry(lpe, &phb->ioda.pe_dma_list, dma_link) { 216184cd4a3SBenjamin Herrenschmidt if (lpe->dma_weight < pe->dma_weight) { 2177ebdf956SGavin Shan list_add_tail(&pe->dma_link, &lpe->dma_link); 218184cd4a3SBenjamin Herrenschmidt return; 219184cd4a3SBenjamin Herrenschmidt } 220184cd4a3SBenjamin Herrenschmidt } 2217ebdf956SGavin Shan list_add_tail(&pe->dma_link, &phb->ioda.pe_dma_list); 222184cd4a3SBenjamin Herrenschmidt } 223184cd4a3SBenjamin Herrenschmidt 224184cd4a3SBenjamin Herrenschmidt static unsigned int pnv_ioda_dma_weight(struct pci_dev *dev) 225184cd4a3SBenjamin Herrenschmidt { 226184cd4a3SBenjamin Herrenschmidt /* This is quite simplistic. The "base" weight of a device 227184cd4a3SBenjamin Herrenschmidt * is 10. 0 means no DMA is to be accounted for it. 228184cd4a3SBenjamin Herrenschmidt */ 229184cd4a3SBenjamin Herrenschmidt 230184cd4a3SBenjamin Herrenschmidt /* If it's a bridge, no DMA */ 231184cd4a3SBenjamin Herrenschmidt if (dev->hdr_type != PCI_HEADER_TYPE_NORMAL) 232184cd4a3SBenjamin Herrenschmidt return 0; 233184cd4a3SBenjamin Herrenschmidt 234184cd4a3SBenjamin Herrenschmidt /* Reduce the weight of slow USB controllers */ 235184cd4a3SBenjamin Herrenschmidt if (dev->class == PCI_CLASS_SERIAL_USB_UHCI || 236184cd4a3SBenjamin Herrenschmidt dev->class == PCI_CLASS_SERIAL_USB_OHCI || 237184cd4a3SBenjamin Herrenschmidt dev->class == PCI_CLASS_SERIAL_USB_EHCI) 238184cd4a3SBenjamin Herrenschmidt return 3; 239184cd4a3SBenjamin Herrenschmidt 240184cd4a3SBenjamin Herrenschmidt /* Increase the weight of RAID (includes Obsidian) */ 241184cd4a3SBenjamin Herrenschmidt if ((dev->class >> 8) == PCI_CLASS_STORAGE_RAID) 242184cd4a3SBenjamin Herrenschmidt return 15; 243184cd4a3SBenjamin Herrenschmidt 244184cd4a3SBenjamin Herrenschmidt /* Default */ 245184cd4a3SBenjamin Herrenschmidt return 10; 246184cd4a3SBenjamin Herrenschmidt } 247184cd4a3SBenjamin Herrenschmidt 248fb446ad0SGavin Shan #if 0 249cad5cef6SGreg Kroah-Hartman static struct pnv_ioda_pe *pnv_ioda_setup_dev_PE(struct pci_dev *dev) 250184cd4a3SBenjamin Herrenschmidt { 251184cd4a3SBenjamin Herrenschmidt struct pci_controller *hose = pci_bus_to_host(dev->bus); 252184cd4a3SBenjamin Herrenschmidt struct pnv_phb *phb = hose->private_data; 253184cd4a3SBenjamin Herrenschmidt struct pci_dn *pdn = pnv_ioda_get_pdn(dev); 254184cd4a3SBenjamin Herrenschmidt struct pnv_ioda_pe *pe; 255184cd4a3SBenjamin Herrenschmidt int pe_num; 256184cd4a3SBenjamin Herrenschmidt 257184cd4a3SBenjamin Herrenschmidt if (!pdn) { 258184cd4a3SBenjamin Herrenschmidt pr_err("%s: Device tree node not associated properly\n", 259184cd4a3SBenjamin Herrenschmidt pci_name(dev)); 260184cd4a3SBenjamin Herrenschmidt return NULL; 261184cd4a3SBenjamin Herrenschmidt } 262184cd4a3SBenjamin Herrenschmidt if (pdn->pe_number != IODA_INVALID_PE) 263184cd4a3SBenjamin Herrenschmidt return NULL; 264184cd4a3SBenjamin Herrenschmidt 265184cd4a3SBenjamin Herrenschmidt /* PE#0 has been pre-set */ 266184cd4a3SBenjamin Herrenschmidt if (dev->bus->number == 0) 267184cd4a3SBenjamin Herrenschmidt pe_num = 0; 268184cd4a3SBenjamin Herrenschmidt else 269184cd4a3SBenjamin Herrenschmidt pe_num = pnv_ioda_alloc_pe(phb); 270184cd4a3SBenjamin Herrenschmidt if (pe_num == IODA_INVALID_PE) { 271184cd4a3SBenjamin Herrenschmidt pr_warning("%s: Not enough PE# available, disabling device\n", 272184cd4a3SBenjamin Herrenschmidt pci_name(dev)); 273184cd4a3SBenjamin Herrenschmidt return NULL; 274184cd4a3SBenjamin Herrenschmidt } 275184cd4a3SBenjamin Herrenschmidt 276184cd4a3SBenjamin Herrenschmidt /* NOTE: We get only one ref to the pci_dev for the pdn, not for the 277184cd4a3SBenjamin Herrenschmidt * pointer in the PE data structure, both should be destroyed at the 278184cd4a3SBenjamin Herrenschmidt * same time. However, this needs to be looked at more closely again 279184cd4a3SBenjamin Herrenschmidt * once we actually start removing things (Hotplug, SR-IOV, ...) 280184cd4a3SBenjamin Herrenschmidt * 281184cd4a3SBenjamin Herrenschmidt * At some point we want to remove the PDN completely anyways 282184cd4a3SBenjamin Herrenschmidt */ 283184cd4a3SBenjamin Herrenschmidt pe = &phb->ioda.pe_array[pe_num]; 284184cd4a3SBenjamin Herrenschmidt pci_dev_get(dev); 285184cd4a3SBenjamin Herrenschmidt pdn->pcidev = dev; 286184cd4a3SBenjamin Herrenschmidt pdn->pe_number = pe_num; 287184cd4a3SBenjamin Herrenschmidt pe->pdev = dev; 288184cd4a3SBenjamin Herrenschmidt pe->pbus = NULL; 289184cd4a3SBenjamin Herrenschmidt pe->tce32_seg = -1; 290184cd4a3SBenjamin Herrenschmidt pe->mve_number = -1; 291184cd4a3SBenjamin Herrenschmidt pe->rid = dev->bus->number << 8 | pdn->devfn; 292184cd4a3SBenjamin Herrenschmidt 293184cd4a3SBenjamin Herrenschmidt pe_info(pe, "Associated device to PE\n"); 294184cd4a3SBenjamin Herrenschmidt 295184cd4a3SBenjamin Herrenschmidt if (pnv_ioda_configure_pe(phb, pe)) { 296184cd4a3SBenjamin Herrenschmidt /* XXX What do we do here ? */ 297184cd4a3SBenjamin Herrenschmidt if (pe_num) 298184cd4a3SBenjamin Herrenschmidt pnv_ioda_free_pe(phb, pe_num); 299184cd4a3SBenjamin Herrenschmidt pdn->pe_number = IODA_INVALID_PE; 300184cd4a3SBenjamin Herrenschmidt pe->pdev = NULL; 301184cd4a3SBenjamin Herrenschmidt pci_dev_put(dev); 302184cd4a3SBenjamin Herrenschmidt return NULL; 303184cd4a3SBenjamin Herrenschmidt } 304184cd4a3SBenjamin Herrenschmidt 305184cd4a3SBenjamin Herrenschmidt /* Assign a DMA weight to the device */ 306184cd4a3SBenjamin Herrenschmidt pe->dma_weight = pnv_ioda_dma_weight(dev); 307184cd4a3SBenjamin Herrenschmidt if (pe->dma_weight != 0) { 308184cd4a3SBenjamin Herrenschmidt phb->ioda.dma_weight += pe->dma_weight; 309184cd4a3SBenjamin Herrenschmidt phb->ioda.dma_pe_count++; 310184cd4a3SBenjamin Herrenschmidt } 311184cd4a3SBenjamin Herrenschmidt 312184cd4a3SBenjamin Herrenschmidt /* Link the PE */ 313184cd4a3SBenjamin Herrenschmidt pnv_ioda_link_pe_by_weight(phb, pe); 314184cd4a3SBenjamin Herrenschmidt 315184cd4a3SBenjamin Herrenschmidt return pe; 316184cd4a3SBenjamin Herrenschmidt } 317fb446ad0SGavin Shan #endif /* Useful for SRIOV case */ 318184cd4a3SBenjamin Herrenschmidt 319184cd4a3SBenjamin Herrenschmidt static void pnv_ioda_setup_same_PE(struct pci_bus *bus, struct pnv_ioda_pe *pe) 320184cd4a3SBenjamin Herrenschmidt { 321184cd4a3SBenjamin Herrenschmidt struct pci_dev *dev; 322184cd4a3SBenjamin Herrenschmidt 323184cd4a3SBenjamin Herrenschmidt list_for_each_entry(dev, &bus->devices, bus_list) { 324184cd4a3SBenjamin Herrenschmidt struct pci_dn *pdn = pnv_ioda_get_pdn(dev); 325184cd4a3SBenjamin Herrenschmidt 326184cd4a3SBenjamin Herrenschmidt if (pdn == NULL) { 327184cd4a3SBenjamin Herrenschmidt pr_warn("%s: No device node associated with device !\n", 328184cd4a3SBenjamin Herrenschmidt pci_name(dev)); 329184cd4a3SBenjamin Herrenschmidt continue; 330184cd4a3SBenjamin Herrenschmidt } 331184cd4a3SBenjamin Herrenschmidt pci_dev_get(dev); 332184cd4a3SBenjamin Herrenschmidt pdn->pcidev = dev; 333184cd4a3SBenjamin Herrenschmidt pdn->pe_number = pe->pe_number; 334184cd4a3SBenjamin Herrenschmidt pe->dma_weight += pnv_ioda_dma_weight(dev); 335fb446ad0SGavin Shan if ((pe->flags & PNV_IODA_PE_BUS_ALL) && dev->subordinate) 336184cd4a3SBenjamin Herrenschmidt pnv_ioda_setup_same_PE(dev->subordinate, pe); 337184cd4a3SBenjamin Herrenschmidt } 338184cd4a3SBenjamin Herrenschmidt } 339184cd4a3SBenjamin Herrenschmidt 340fb446ad0SGavin Shan /* 341fb446ad0SGavin Shan * There're 2 types of PCI bus sensitive PEs: One that is compromised of 342fb446ad0SGavin Shan * single PCI bus. Another one that contains the primary PCI bus and its 343fb446ad0SGavin Shan * subordinate PCI devices and buses. The second type of PE is normally 344fb446ad0SGavin Shan * orgiriated by PCIe-to-PCI bridge or PLX switch downstream ports. 345fb446ad0SGavin Shan */ 346cad5cef6SGreg Kroah-Hartman static void pnv_ioda_setup_bus_PE(struct pci_bus *bus, int all) 347184cd4a3SBenjamin Herrenschmidt { 348fb446ad0SGavin Shan struct pci_controller *hose = pci_bus_to_host(bus); 349184cd4a3SBenjamin Herrenschmidt struct pnv_phb *phb = hose->private_data; 350184cd4a3SBenjamin Herrenschmidt struct pnv_ioda_pe *pe; 351184cd4a3SBenjamin Herrenschmidt int pe_num; 352184cd4a3SBenjamin Herrenschmidt 353184cd4a3SBenjamin Herrenschmidt pe_num = pnv_ioda_alloc_pe(phb); 354184cd4a3SBenjamin Herrenschmidt if (pe_num == IODA_INVALID_PE) { 355fb446ad0SGavin Shan pr_warning("%s: Not enough PE# available for PCI bus %04x:%02x\n", 356fb446ad0SGavin Shan __func__, pci_domain_nr(bus), bus->number); 357184cd4a3SBenjamin Herrenschmidt return; 358184cd4a3SBenjamin Herrenschmidt } 359184cd4a3SBenjamin Herrenschmidt 360184cd4a3SBenjamin Herrenschmidt pe = &phb->ioda.pe_array[pe_num]; 361fb446ad0SGavin Shan pe->flags = (all ? PNV_IODA_PE_BUS_ALL : PNV_IODA_PE_BUS); 362184cd4a3SBenjamin Herrenschmidt pe->pbus = bus; 363184cd4a3SBenjamin Herrenschmidt pe->pdev = NULL; 364184cd4a3SBenjamin Herrenschmidt pe->tce32_seg = -1; 365184cd4a3SBenjamin Herrenschmidt pe->mve_number = -1; 366b918c62eSYinghai Lu pe->rid = bus->busn_res.start << 8; 367184cd4a3SBenjamin Herrenschmidt pe->dma_weight = 0; 368184cd4a3SBenjamin Herrenschmidt 369fb446ad0SGavin Shan if (all) 370fb446ad0SGavin Shan pe_info(pe, "Secondary bus %d..%d associated with PE#%d\n", 371fb446ad0SGavin Shan bus->busn_res.start, bus->busn_res.end, pe_num); 372fb446ad0SGavin Shan else 373fb446ad0SGavin Shan pe_info(pe, "Secondary bus %d associated with PE#%d\n", 374fb446ad0SGavin Shan bus->busn_res.start, pe_num); 375184cd4a3SBenjamin Herrenschmidt 376184cd4a3SBenjamin Herrenschmidt if (pnv_ioda_configure_pe(phb, pe)) { 377184cd4a3SBenjamin Herrenschmidt /* XXX What do we do here ? */ 378184cd4a3SBenjamin Herrenschmidt if (pe_num) 379184cd4a3SBenjamin Herrenschmidt pnv_ioda_free_pe(phb, pe_num); 380184cd4a3SBenjamin Herrenschmidt pe->pbus = NULL; 381184cd4a3SBenjamin Herrenschmidt return; 382184cd4a3SBenjamin Herrenschmidt } 383184cd4a3SBenjamin Herrenschmidt 384184cd4a3SBenjamin Herrenschmidt /* Associate it with all child devices */ 385184cd4a3SBenjamin Herrenschmidt pnv_ioda_setup_same_PE(bus, pe); 386184cd4a3SBenjamin Herrenschmidt 3877ebdf956SGavin Shan /* Put PE to the list */ 3887ebdf956SGavin Shan list_add_tail(&pe->list, &phb->ioda.pe_list); 3897ebdf956SGavin Shan 390184cd4a3SBenjamin Herrenschmidt /* Account for one DMA PE if at least one DMA capable device exist 391184cd4a3SBenjamin Herrenschmidt * below the bridge 392184cd4a3SBenjamin Herrenschmidt */ 393184cd4a3SBenjamin Herrenschmidt if (pe->dma_weight != 0) { 394184cd4a3SBenjamin Herrenschmidt phb->ioda.dma_weight += pe->dma_weight; 395184cd4a3SBenjamin Herrenschmidt phb->ioda.dma_pe_count++; 396184cd4a3SBenjamin Herrenschmidt } 397184cd4a3SBenjamin Herrenschmidt 398184cd4a3SBenjamin Herrenschmidt /* Link the PE */ 399184cd4a3SBenjamin Herrenschmidt pnv_ioda_link_pe_by_weight(phb, pe); 400184cd4a3SBenjamin Herrenschmidt } 401184cd4a3SBenjamin Herrenschmidt 402cad5cef6SGreg Kroah-Hartman static void pnv_ioda_setup_PEs(struct pci_bus *bus) 403184cd4a3SBenjamin Herrenschmidt { 404184cd4a3SBenjamin Herrenschmidt struct pci_dev *dev; 405fb446ad0SGavin Shan 406fb446ad0SGavin Shan pnv_ioda_setup_bus_PE(bus, 0); 407184cd4a3SBenjamin Herrenschmidt 408184cd4a3SBenjamin Herrenschmidt list_for_each_entry(dev, &bus->devices, bus_list) { 409fb446ad0SGavin Shan if (dev->subordinate) { 41062f87c0eSYijing Wang if (pci_pcie_type(dev) == PCI_EXP_TYPE_PCI_BRIDGE) 411fb446ad0SGavin Shan pnv_ioda_setup_bus_PE(dev->subordinate, 1); 412fb446ad0SGavin Shan else 413184cd4a3SBenjamin Herrenschmidt pnv_ioda_setup_PEs(dev->subordinate); 414184cd4a3SBenjamin Herrenschmidt } 415184cd4a3SBenjamin Herrenschmidt } 416fb446ad0SGavin Shan } 417fb446ad0SGavin Shan 418fb446ad0SGavin Shan /* 419fb446ad0SGavin Shan * Configure PEs so that the downstream PCI buses and devices 420fb446ad0SGavin Shan * could have their associated PE#. Unfortunately, we didn't 421fb446ad0SGavin Shan * figure out the way to identify the PLX bridge yet. So we 422fb446ad0SGavin Shan * simply put the PCI bus and the subordinate behind the root 423fb446ad0SGavin Shan * port to PE# here. The game rule here is expected to be changed 424fb446ad0SGavin Shan * as soon as we can detected PLX bridge correctly. 425fb446ad0SGavin Shan */ 426cad5cef6SGreg Kroah-Hartman static void pnv_pci_ioda_setup_PEs(void) 427fb446ad0SGavin Shan { 428fb446ad0SGavin Shan struct pci_controller *hose, *tmp; 429fb446ad0SGavin Shan 430fb446ad0SGavin Shan list_for_each_entry_safe(hose, tmp, &hose_list, list_node) { 431fb446ad0SGavin Shan pnv_ioda_setup_PEs(hose->bus); 432fb446ad0SGavin Shan } 433fb446ad0SGavin Shan } 434184cd4a3SBenjamin Herrenschmidt 435cad5cef6SGreg Kroah-Hartman static void pnv_pci_ioda_dma_dev_setup(struct pnv_phb *phb, struct pci_dev *dev) 436184cd4a3SBenjamin Herrenschmidt { 437184cd4a3SBenjamin Herrenschmidt /* We delay DMA setup after we have assigned all PE# */ 438184cd4a3SBenjamin Herrenschmidt } 439184cd4a3SBenjamin Herrenschmidt 440cad5cef6SGreg Kroah-Hartman static void pnv_ioda_setup_bus_dma(struct pnv_ioda_pe *pe, struct pci_bus *bus) 441184cd4a3SBenjamin Herrenschmidt { 442184cd4a3SBenjamin Herrenschmidt struct pci_dev *dev; 443184cd4a3SBenjamin Herrenschmidt 444184cd4a3SBenjamin Herrenschmidt list_for_each_entry(dev, &bus->devices, bus_list) { 445184cd4a3SBenjamin Herrenschmidt set_iommu_table_base(&dev->dev, &pe->tce32_table); 446184cd4a3SBenjamin Herrenschmidt if (dev->subordinate) 447184cd4a3SBenjamin Herrenschmidt pnv_ioda_setup_bus_dma(pe, dev->subordinate); 448184cd4a3SBenjamin Herrenschmidt } 449184cd4a3SBenjamin Herrenschmidt } 450184cd4a3SBenjamin Herrenschmidt 451cad5cef6SGreg Kroah-Hartman static void pnv_pci_ioda_setup_dma_pe(struct pnv_phb *phb, 452cad5cef6SGreg Kroah-Hartman struct pnv_ioda_pe *pe, unsigned int base, 453184cd4a3SBenjamin Herrenschmidt unsigned int segs) 454184cd4a3SBenjamin Herrenschmidt { 455184cd4a3SBenjamin Herrenschmidt 456184cd4a3SBenjamin Herrenschmidt struct page *tce_mem = NULL; 457184cd4a3SBenjamin Herrenschmidt const __be64 *swinvp; 458184cd4a3SBenjamin Herrenschmidt struct iommu_table *tbl; 459184cd4a3SBenjamin Herrenschmidt unsigned int i; 460184cd4a3SBenjamin Herrenschmidt int64_t rc; 461184cd4a3SBenjamin Herrenschmidt void *addr; 462184cd4a3SBenjamin Herrenschmidt 463184cd4a3SBenjamin Herrenschmidt /* 256M DMA window, 4K TCE pages, 8 bytes TCE */ 464184cd4a3SBenjamin Herrenschmidt #define TCE32_TABLE_SIZE ((0x10000000 / 0x1000) * 8) 465184cd4a3SBenjamin Herrenschmidt 466184cd4a3SBenjamin Herrenschmidt /* XXX FIXME: Handle 64-bit only DMA devices */ 467184cd4a3SBenjamin Herrenschmidt /* XXX FIXME: Provide 64-bit DMA facilities & non-4K TCE tables etc.. */ 468184cd4a3SBenjamin Herrenschmidt /* XXX FIXME: Allocate multi-level tables on PHB3 */ 469184cd4a3SBenjamin Herrenschmidt 470184cd4a3SBenjamin Herrenschmidt /* We shouldn't already have a 32-bit DMA associated */ 471184cd4a3SBenjamin Herrenschmidt if (WARN_ON(pe->tce32_seg >= 0)) 472184cd4a3SBenjamin Herrenschmidt return; 473184cd4a3SBenjamin Herrenschmidt 474184cd4a3SBenjamin Herrenschmidt /* Grab a 32-bit TCE table */ 475184cd4a3SBenjamin Herrenschmidt pe->tce32_seg = base; 476184cd4a3SBenjamin Herrenschmidt pe_info(pe, " Setting up 32-bit TCE table at %08x..%08x\n", 477184cd4a3SBenjamin Herrenschmidt (base << 28), ((base + segs) << 28) - 1); 478184cd4a3SBenjamin Herrenschmidt 479184cd4a3SBenjamin Herrenschmidt /* XXX Currently, we allocate one big contiguous table for the 480184cd4a3SBenjamin Herrenschmidt * TCEs. We only really need one chunk per 256M of TCE space 481184cd4a3SBenjamin Herrenschmidt * (ie per segment) but that's an optimization for later, it 482184cd4a3SBenjamin Herrenschmidt * requires some added smarts with our get/put_tce implementation 483184cd4a3SBenjamin Herrenschmidt */ 484184cd4a3SBenjamin Herrenschmidt tce_mem = alloc_pages_node(phb->hose->node, GFP_KERNEL, 485184cd4a3SBenjamin Herrenschmidt get_order(TCE32_TABLE_SIZE * segs)); 486184cd4a3SBenjamin Herrenschmidt if (!tce_mem) { 487184cd4a3SBenjamin Herrenschmidt pe_err(pe, " Failed to allocate a 32-bit TCE memory\n"); 488184cd4a3SBenjamin Herrenschmidt goto fail; 489184cd4a3SBenjamin Herrenschmidt } 490184cd4a3SBenjamin Herrenschmidt addr = page_address(tce_mem); 491184cd4a3SBenjamin Herrenschmidt memset(addr, 0, TCE32_TABLE_SIZE * segs); 492184cd4a3SBenjamin Herrenschmidt 493184cd4a3SBenjamin Herrenschmidt /* Configure HW */ 494184cd4a3SBenjamin Herrenschmidt for (i = 0; i < segs; i++) { 495184cd4a3SBenjamin Herrenschmidt rc = opal_pci_map_pe_dma_window(phb->opal_id, 496184cd4a3SBenjamin Herrenschmidt pe->pe_number, 497184cd4a3SBenjamin Herrenschmidt base + i, 1, 498184cd4a3SBenjamin Herrenschmidt __pa(addr) + TCE32_TABLE_SIZE * i, 499184cd4a3SBenjamin Herrenschmidt TCE32_TABLE_SIZE, 0x1000); 500184cd4a3SBenjamin Herrenschmidt if (rc) { 501184cd4a3SBenjamin Herrenschmidt pe_err(pe, " Failed to configure 32-bit TCE table," 502184cd4a3SBenjamin Herrenschmidt " err %ld\n", rc); 503184cd4a3SBenjamin Herrenschmidt goto fail; 504184cd4a3SBenjamin Herrenschmidt } 505184cd4a3SBenjamin Herrenschmidt } 506184cd4a3SBenjamin Herrenschmidt 507184cd4a3SBenjamin Herrenschmidt /* Setup linux iommu table */ 508184cd4a3SBenjamin Herrenschmidt tbl = &pe->tce32_table; 509184cd4a3SBenjamin Herrenschmidt pnv_pci_setup_iommu_table(tbl, addr, TCE32_TABLE_SIZE * segs, 510184cd4a3SBenjamin Herrenschmidt base << 28); 511184cd4a3SBenjamin Herrenschmidt 512184cd4a3SBenjamin Herrenschmidt /* OPAL variant of P7IOC SW invalidated TCEs */ 513184cd4a3SBenjamin Herrenschmidt swinvp = of_get_property(phb->hose->dn, "ibm,opal-tce-kill", NULL); 514184cd4a3SBenjamin Herrenschmidt if (swinvp) { 515184cd4a3SBenjamin Herrenschmidt /* We need a couple more fields -- an address and a data 516184cd4a3SBenjamin Herrenschmidt * to or. Since the bus is only printed out on table free 517184cd4a3SBenjamin Herrenschmidt * errors, and on the first pass the data will be a relative 518184cd4a3SBenjamin Herrenschmidt * bus number, print that out instead. 519184cd4a3SBenjamin Herrenschmidt */ 520184cd4a3SBenjamin Herrenschmidt tbl->it_busno = 0; 521184cd4a3SBenjamin Herrenschmidt tbl->it_index = (unsigned long)ioremap(be64_to_cpup(swinvp), 8); 522184cd4a3SBenjamin Herrenschmidt tbl->it_type = TCE_PCI_SWINV_CREATE | TCE_PCI_SWINV_FREE 523184cd4a3SBenjamin Herrenschmidt | TCE_PCI_SWINV_PAIR; 524184cd4a3SBenjamin Herrenschmidt } 525184cd4a3SBenjamin Herrenschmidt iommu_init_table(tbl, phb->hose->node); 526184cd4a3SBenjamin Herrenschmidt 527184cd4a3SBenjamin Herrenschmidt if (pe->pdev) 528184cd4a3SBenjamin Herrenschmidt set_iommu_table_base(&pe->pdev->dev, tbl); 529184cd4a3SBenjamin Herrenschmidt else 530184cd4a3SBenjamin Herrenschmidt pnv_ioda_setup_bus_dma(pe, pe->pbus); 531184cd4a3SBenjamin Herrenschmidt 532184cd4a3SBenjamin Herrenschmidt return; 533184cd4a3SBenjamin Herrenschmidt fail: 534184cd4a3SBenjamin Herrenschmidt /* XXX Failure: Try to fallback to 64-bit only ? */ 535184cd4a3SBenjamin Herrenschmidt if (pe->tce32_seg >= 0) 536184cd4a3SBenjamin Herrenschmidt pe->tce32_seg = -1; 537184cd4a3SBenjamin Herrenschmidt if (tce_mem) 538184cd4a3SBenjamin Herrenschmidt __free_pages(tce_mem, get_order(TCE32_TABLE_SIZE * segs)); 539184cd4a3SBenjamin Herrenschmidt } 540184cd4a3SBenjamin Herrenschmidt 541cad5cef6SGreg Kroah-Hartman static void pnv_ioda_setup_dma(struct pnv_phb *phb) 542184cd4a3SBenjamin Herrenschmidt { 543184cd4a3SBenjamin Herrenschmidt struct pci_controller *hose = phb->hose; 544184cd4a3SBenjamin Herrenschmidt unsigned int residual, remaining, segs, tw, base; 545184cd4a3SBenjamin Herrenschmidt struct pnv_ioda_pe *pe; 546184cd4a3SBenjamin Herrenschmidt 547184cd4a3SBenjamin Herrenschmidt /* If we have more PE# than segments available, hand out one 548184cd4a3SBenjamin Herrenschmidt * per PE until we run out and let the rest fail. If not, 549184cd4a3SBenjamin Herrenschmidt * then we assign at least one segment per PE, plus more based 550184cd4a3SBenjamin Herrenschmidt * on the amount of devices under that PE 551184cd4a3SBenjamin Herrenschmidt */ 552184cd4a3SBenjamin Herrenschmidt if (phb->ioda.dma_pe_count > phb->ioda.tce32_count) 553184cd4a3SBenjamin Herrenschmidt residual = 0; 554184cd4a3SBenjamin Herrenschmidt else 555184cd4a3SBenjamin Herrenschmidt residual = phb->ioda.tce32_count - 556184cd4a3SBenjamin Herrenschmidt phb->ioda.dma_pe_count; 557184cd4a3SBenjamin Herrenschmidt 558184cd4a3SBenjamin Herrenschmidt pr_info("PCI: Domain %04x has %ld available 32-bit DMA segments\n", 559184cd4a3SBenjamin Herrenschmidt hose->global_number, phb->ioda.tce32_count); 560184cd4a3SBenjamin Herrenschmidt pr_info("PCI: %d PE# for a total weight of %d\n", 561184cd4a3SBenjamin Herrenschmidt phb->ioda.dma_pe_count, phb->ioda.dma_weight); 562184cd4a3SBenjamin Herrenschmidt 563184cd4a3SBenjamin Herrenschmidt /* Walk our PE list and configure their DMA segments, hand them 564184cd4a3SBenjamin Herrenschmidt * out one base segment plus any residual segments based on 565184cd4a3SBenjamin Herrenschmidt * weight 566184cd4a3SBenjamin Herrenschmidt */ 567184cd4a3SBenjamin Herrenschmidt remaining = phb->ioda.tce32_count; 568184cd4a3SBenjamin Herrenschmidt tw = phb->ioda.dma_weight; 569184cd4a3SBenjamin Herrenschmidt base = 0; 5707ebdf956SGavin Shan list_for_each_entry(pe, &phb->ioda.pe_dma_list, dma_link) { 571184cd4a3SBenjamin Herrenschmidt if (!pe->dma_weight) 572184cd4a3SBenjamin Herrenschmidt continue; 573184cd4a3SBenjamin Herrenschmidt if (!remaining) { 574184cd4a3SBenjamin Herrenschmidt pe_warn(pe, "No DMA32 resources available\n"); 575184cd4a3SBenjamin Herrenschmidt continue; 576184cd4a3SBenjamin Herrenschmidt } 577184cd4a3SBenjamin Herrenschmidt segs = 1; 578184cd4a3SBenjamin Herrenschmidt if (residual) { 579184cd4a3SBenjamin Herrenschmidt segs += ((pe->dma_weight * residual) + (tw / 2)) / tw; 580184cd4a3SBenjamin Herrenschmidt if (segs > remaining) 581184cd4a3SBenjamin Herrenschmidt segs = remaining; 582184cd4a3SBenjamin Herrenschmidt } 583184cd4a3SBenjamin Herrenschmidt pe_info(pe, "DMA weight %d, assigned %d DMA32 segments\n", 584184cd4a3SBenjamin Herrenschmidt pe->dma_weight, segs); 585184cd4a3SBenjamin Herrenschmidt pnv_pci_ioda_setup_dma_pe(phb, pe, base, segs); 586184cd4a3SBenjamin Herrenschmidt remaining -= segs; 587184cd4a3SBenjamin Herrenschmidt base += segs; 588184cd4a3SBenjamin Herrenschmidt } 589184cd4a3SBenjamin Herrenschmidt } 590184cd4a3SBenjamin Herrenschmidt 591184cd4a3SBenjamin Herrenschmidt #ifdef CONFIG_PCI_MSI 592184cd4a3SBenjamin Herrenschmidt static int pnv_pci_ioda_msi_setup(struct pnv_phb *phb, struct pci_dev *dev, 593184cd4a3SBenjamin Herrenschmidt unsigned int hwirq, unsigned int is_64, 594184cd4a3SBenjamin Herrenschmidt struct msi_msg *msg) 595184cd4a3SBenjamin Herrenschmidt { 596184cd4a3SBenjamin Herrenschmidt struct pnv_ioda_pe *pe = pnv_ioda_get_pe(dev); 597184cd4a3SBenjamin Herrenschmidt unsigned int xive_num = hwirq - phb->msi_base; 598184cd4a3SBenjamin Herrenschmidt uint64_t addr64; 599184cd4a3SBenjamin Herrenschmidt uint32_t addr32, data; 600184cd4a3SBenjamin Herrenschmidt int rc; 601184cd4a3SBenjamin Herrenschmidt 602184cd4a3SBenjamin Herrenschmidt /* No PE assigned ? bail out ... no MSI for you ! */ 603184cd4a3SBenjamin Herrenschmidt if (pe == NULL) 604184cd4a3SBenjamin Herrenschmidt return -ENXIO; 605184cd4a3SBenjamin Herrenschmidt 606184cd4a3SBenjamin Herrenschmidt /* Check if we have an MVE */ 607184cd4a3SBenjamin Herrenschmidt if (pe->mve_number < 0) 608184cd4a3SBenjamin Herrenschmidt return -ENXIO; 609184cd4a3SBenjamin Herrenschmidt 610184cd4a3SBenjamin Herrenschmidt /* Assign XIVE to PE */ 611184cd4a3SBenjamin Herrenschmidt rc = opal_pci_set_xive_pe(phb->opal_id, pe->pe_number, xive_num); 612184cd4a3SBenjamin Herrenschmidt if (rc) { 613184cd4a3SBenjamin Herrenschmidt pr_warn("%s: OPAL error %d setting XIVE %d PE\n", 614184cd4a3SBenjamin Herrenschmidt pci_name(dev), rc, xive_num); 615184cd4a3SBenjamin Herrenschmidt return -EIO; 616184cd4a3SBenjamin Herrenschmidt } 617184cd4a3SBenjamin Herrenschmidt 618184cd4a3SBenjamin Herrenschmidt if (is_64) { 619184cd4a3SBenjamin Herrenschmidt rc = opal_get_msi_64(phb->opal_id, pe->mve_number, xive_num, 1, 620184cd4a3SBenjamin Herrenschmidt &addr64, &data); 621184cd4a3SBenjamin Herrenschmidt if (rc) { 622184cd4a3SBenjamin Herrenschmidt pr_warn("%s: OPAL error %d getting 64-bit MSI data\n", 623184cd4a3SBenjamin Herrenschmidt pci_name(dev), rc); 624184cd4a3SBenjamin Herrenschmidt return -EIO; 625184cd4a3SBenjamin Herrenschmidt } 626184cd4a3SBenjamin Herrenschmidt msg->address_hi = addr64 >> 32; 627184cd4a3SBenjamin Herrenschmidt msg->address_lo = addr64 & 0xfffffffful; 628184cd4a3SBenjamin Herrenschmidt } else { 629184cd4a3SBenjamin Herrenschmidt rc = opal_get_msi_32(phb->opal_id, pe->mve_number, xive_num, 1, 630184cd4a3SBenjamin Herrenschmidt &addr32, &data); 631184cd4a3SBenjamin Herrenschmidt if (rc) { 632184cd4a3SBenjamin Herrenschmidt pr_warn("%s: OPAL error %d getting 32-bit MSI data\n", 633184cd4a3SBenjamin Herrenschmidt pci_name(dev), rc); 634184cd4a3SBenjamin Herrenschmidt return -EIO; 635184cd4a3SBenjamin Herrenschmidt } 636184cd4a3SBenjamin Herrenschmidt msg->address_hi = 0; 637184cd4a3SBenjamin Herrenschmidt msg->address_lo = addr32; 638184cd4a3SBenjamin Herrenschmidt } 639184cd4a3SBenjamin Herrenschmidt msg->data = data; 640184cd4a3SBenjamin Herrenschmidt 641184cd4a3SBenjamin Herrenschmidt pr_devel("%s: %s-bit MSI on hwirq %x (xive #%d)," 642184cd4a3SBenjamin Herrenschmidt " address=%x_%08x data=%x PE# %d\n", 643184cd4a3SBenjamin Herrenschmidt pci_name(dev), is_64 ? "64" : "32", hwirq, xive_num, 644184cd4a3SBenjamin Herrenschmidt msg->address_hi, msg->address_lo, data, pe->pe_number); 645184cd4a3SBenjamin Herrenschmidt 646184cd4a3SBenjamin Herrenschmidt return 0; 647184cd4a3SBenjamin Herrenschmidt } 648184cd4a3SBenjamin Herrenschmidt 649184cd4a3SBenjamin Herrenschmidt static void pnv_pci_init_ioda_msis(struct pnv_phb *phb) 650184cd4a3SBenjamin Herrenschmidt { 651fb1b55d6SGavin Shan unsigned int count; 652184cd4a3SBenjamin Herrenschmidt const __be32 *prop = of_get_property(phb->hose->dn, 653184cd4a3SBenjamin Herrenschmidt "ibm,opal-msi-ranges", NULL); 654184cd4a3SBenjamin Herrenschmidt if (!prop) { 655184cd4a3SBenjamin Herrenschmidt /* BML Fallback */ 656184cd4a3SBenjamin Herrenschmidt prop = of_get_property(phb->hose->dn, "msi-ranges", NULL); 657184cd4a3SBenjamin Herrenschmidt } 658184cd4a3SBenjamin Herrenschmidt if (!prop) 659184cd4a3SBenjamin Herrenschmidt return; 660184cd4a3SBenjamin Herrenschmidt 661184cd4a3SBenjamin Herrenschmidt phb->msi_base = be32_to_cpup(prop); 662fb1b55d6SGavin Shan count = be32_to_cpup(prop + 1); 663fb1b55d6SGavin Shan if (msi_bitmap_alloc(&phb->msi_bmp, count, phb->hose->dn)) { 664184cd4a3SBenjamin Herrenschmidt pr_err("PCI %d: Failed to allocate MSI bitmap !\n", 665184cd4a3SBenjamin Herrenschmidt phb->hose->global_number); 666184cd4a3SBenjamin Herrenschmidt return; 667184cd4a3SBenjamin Herrenschmidt } 668fb1b55d6SGavin Shan 669184cd4a3SBenjamin Herrenschmidt phb->msi_setup = pnv_pci_ioda_msi_setup; 670184cd4a3SBenjamin Herrenschmidt phb->msi32_support = 1; 671184cd4a3SBenjamin Herrenschmidt pr_info(" Allocated bitmap for %d MSIs (base IRQ 0x%x)\n", 672fb1b55d6SGavin Shan count, phb->msi_base); 673184cd4a3SBenjamin Herrenschmidt } 674184cd4a3SBenjamin Herrenschmidt #else 675184cd4a3SBenjamin Herrenschmidt static void pnv_pci_init_ioda_msis(struct pnv_phb *phb) { } 676184cd4a3SBenjamin Herrenschmidt #endif /* CONFIG_PCI_MSI */ 677184cd4a3SBenjamin Herrenschmidt 67811685becSGavin Shan /* 67911685becSGavin Shan * This function is supposed to be called on basis of PE from top 68011685becSGavin Shan * to bottom style. So the the I/O or MMIO segment assigned to 68111685becSGavin Shan * parent PE could be overrided by its child PEs if necessary. 68211685becSGavin Shan */ 683cad5cef6SGreg Kroah-Hartman static void pnv_ioda_setup_pe_seg(struct pci_controller *hose, 68411685becSGavin Shan struct pnv_ioda_pe *pe) 68511685becSGavin Shan { 68611685becSGavin Shan struct pnv_phb *phb = hose->private_data; 68711685becSGavin Shan struct pci_bus_region region; 68811685becSGavin Shan struct resource *res; 68911685becSGavin Shan int i, index; 69011685becSGavin Shan int rc; 69111685becSGavin Shan 69211685becSGavin Shan /* 69311685becSGavin Shan * NOTE: We only care PCI bus based PE for now. For PCI 69411685becSGavin Shan * device based PE, for example SRIOV sensitive VF should 69511685becSGavin Shan * be figured out later. 69611685becSGavin Shan */ 69711685becSGavin Shan BUG_ON(!(pe->flags & (PNV_IODA_PE_BUS | PNV_IODA_PE_BUS_ALL))); 69811685becSGavin Shan 69911685becSGavin Shan pci_bus_for_each_resource(pe->pbus, res, i) { 70011685becSGavin Shan if (!res || !res->flags || 70111685becSGavin Shan res->start > res->end) 70211685becSGavin Shan continue; 70311685becSGavin Shan 70411685becSGavin Shan if (res->flags & IORESOURCE_IO) { 70511685becSGavin Shan region.start = res->start - phb->ioda.io_pci_base; 70611685becSGavin Shan region.end = res->end - phb->ioda.io_pci_base; 70711685becSGavin Shan index = region.start / phb->ioda.io_segsize; 70811685becSGavin Shan 70911685becSGavin Shan while (index < phb->ioda.total_pe && 71011685becSGavin Shan region.start <= region.end) { 71111685becSGavin Shan phb->ioda.io_segmap[index] = pe->pe_number; 71211685becSGavin Shan rc = opal_pci_map_pe_mmio_window(phb->opal_id, 71311685becSGavin Shan pe->pe_number, OPAL_IO_WINDOW_TYPE, 0, index); 71411685becSGavin Shan if (rc != OPAL_SUCCESS) { 71511685becSGavin Shan pr_err("%s: OPAL error %d when mapping IO " 71611685becSGavin Shan "segment #%d to PE#%d\n", 71711685becSGavin Shan __func__, rc, index, pe->pe_number); 71811685becSGavin Shan break; 71911685becSGavin Shan } 72011685becSGavin Shan 72111685becSGavin Shan region.start += phb->ioda.io_segsize; 72211685becSGavin Shan index++; 72311685becSGavin Shan } 72411685becSGavin Shan } else if (res->flags & IORESOURCE_MEM) { 72511685becSGavin Shan region.start = res->start - 72611685becSGavin Shan hose->pci_mem_offset - 72711685becSGavin Shan phb->ioda.m32_pci_base; 72811685becSGavin Shan region.end = res->end - 72911685becSGavin Shan hose->pci_mem_offset - 73011685becSGavin Shan phb->ioda.m32_pci_base; 73111685becSGavin Shan index = region.start / phb->ioda.m32_segsize; 73211685becSGavin Shan 73311685becSGavin Shan while (index < phb->ioda.total_pe && 73411685becSGavin Shan region.start <= region.end) { 73511685becSGavin Shan phb->ioda.m32_segmap[index] = pe->pe_number; 73611685becSGavin Shan rc = opal_pci_map_pe_mmio_window(phb->opal_id, 73711685becSGavin Shan pe->pe_number, OPAL_M32_WINDOW_TYPE, 0, index); 73811685becSGavin Shan if (rc != OPAL_SUCCESS) { 73911685becSGavin Shan pr_err("%s: OPAL error %d when mapping M32 " 74011685becSGavin Shan "segment#%d to PE#%d", 74111685becSGavin Shan __func__, rc, index, pe->pe_number); 74211685becSGavin Shan break; 74311685becSGavin Shan } 74411685becSGavin Shan 74511685becSGavin Shan region.start += phb->ioda.m32_segsize; 74611685becSGavin Shan index++; 74711685becSGavin Shan } 74811685becSGavin Shan } 74911685becSGavin Shan } 75011685becSGavin Shan } 75111685becSGavin Shan 752cad5cef6SGreg Kroah-Hartman static void pnv_pci_ioda_setup_seg(void) 75311685becSGavin Shan { 75411685becSGavin Shan struct pci_controller *tmp, *hose; 75511685becSGavin Shan struct pnv_phb *phb; 75611685becSGavin Shan struct pnv_ioda_pe *pe; 75711685becSGavin Shan 75811685becSGavin Shan list_for_each_entry_safe(hose, tmp, &hose_list, list_node) { 75911685becSGavin Shan phb = hose->private_data; 76011685becSGavin Shan list_for_each_entry(pe, &phb->ioda.pe_list, list) { 76111685becSGavin Shan pnv_ioda_setup_pe_seg(hose, pe); 76211685becSGavin Shan } 76311685becSGavin Shan } 76411685becSGavin Shan } 76511685becSGavin Shan 766cad5cef6SGreg Kroah-Hartman static void pnv_pci_ioda_setup_DMA(void) 76713395c48SGavin Shan { 76813395c48SGavin Shan struct pci_controller *hose, *tmp; 769db1266c8SGavin Shan struct pnv_phb *phb; 77013395c48SGavin Shan 77113395c48SGavin Shan list_for_each_entry_safe(hose, tmp, &hose_list, list_node) { 77213395c48SGavin Shan pnv_ioda_setup_dma(hose->private_data); 773db1266c8SGavin Shan 774db1266c8SGavin Shan /* Mark the PHB initialization done */ 775db1266c8SGavin Shan phb = hose->private_data; 776db1266c8SGavin Shan phb->initialized = 1; 77713395c48SGavin Shan } 77813395c48SGavin Shan } 77913395c48SGavin Shan 780cad5cef6SGreg Kroah-Hartman static void pnv_pci_ioda_fixup(void) 781fb446ad0SGavin Shan { 782fb446ad0SGavin Shan pnv_pci_ioda_setup_PEs(); 78311685becSGavin Shan pnv_pci_ioda_setup_seg(); 78413395c48SGavin Shan pnv_pci_ioda_setup_DMA(); 785fb446ad0SGavin Shan } 786fb446ad0SGavin Shan 787271fd03aSGavin Shan /* 788271fd03aSGavin Shan * Returns the alignment for I/O or memory windows for P2P 789271fd03aSGavin Shan * bridges. That actually depends on how PEs are segmented. 790271fd03aSGavin Shan * For now, we return I/O or M32 segment size for PE sensitive 791271fd03aSGavin Shan * P2P bridges. Otherwise, the default values (4KiB for I/O, 792271fd03aSGavin Shan * 1MiB for memory) will be returned. 793271fd03aSGavin Shan * 794271fd03aSGavin Shan * The current PCI bus might be put into one PE, which was 795271fd03aSGavin Shan * create against the parent PCI bridge. For that case, we 796271fd03aSGavin Shan * needn't enlarge the alignment so that we can save some 797271fd03aSGavin Shan * resources. 798271fd03aSGavin Shan */ 799271fd03aSGavin Shan static resource_size_t pnv_pci_window_alignment(struct pci_bus *bus, 800271fd03aSGavin Shan unsigned long type) 801271fd03aSGavin Shan { 802271fd03aSGavin Shan struct pci_dev *bridge; 803271fd03aSGavin Shan struct pci_controller *hose = pci_bus_to_host(bus); 804271fd03aSGavin Shan struct pnv_phb *phb = hose->private_data; 805271fd03aSGavin Shan int num_pci_bridges = 0; 806271fd03aSGavin Shan 807271fd03aSGavin Shan bridge = bus->self; 808271fd03aSGavin Shan while (bridge) { 809271fd03aSGavin Shan if (pci_pcie_type(bridge) == PCI_EXP_TYPE_PCI_BRIDGE) { 810271fd03aSGavin Shan num_pci_bridges++; 811271fd03aSGavin Shan if (num_pci_bridges >= 2) 812271fd03aSGavin Shan return 1; 813271fd03aSGavin Shan } 814271fd03aSGavin Shan 815271fd03aSGavin Shan bridge = bridge->bus->self; 816271fd03aSGavin Shan } 817271fd03aSGavin Shan 818271fd03aSGavin Shan /* We need support prefetchable memory window later */ 819271fd03aSGavin Shan if (type & IORESOURCE_MEM) 820271fd03aSGavin Shan return phb->ioda.m32_segsize; 821271fd03aSGavin Shan 822271fd03aSGavin Shan return phb->ioda.io_segsize; 823271fd03aSGavin Shan } 824271fd03aSGavin Shan 825184cd4a3SBenjamin Herrenschmidt /* Prevent enabling devices for which we couldn't properly 826184cd4a3SBenjamin Herrenschmidt * assign a PE 827184cd4a3SBenjamin Herrenschmidt */ 828cad5cef6SGreg Kroah-Hartman static int pnv_pci_enable_device_hook(struct pci_dev *dev) 829184cd4a3SBenjamin Herrenschmidt { 830db1266c8SGavin Shan struct pci_controller *hose = pci_bus_to_host(dev->bus); 831db1266c8SGavin Shan struct pnv_phb *phb = hose->private_data; 832db1266c8SGavin Shan struct pci_dn *pdn; 833184cd4a3SBenjamin Herrenschmidt 834db1266c8SGavin Shan /* The function is probably called while the PEs have 835db1266c8SGavin Shan * not be created yet. For example, resource reassignment 836db1266c8SGavin Shan * during PCI probe period. We just skip the check if 837db1266c8SGavin Shan * PEs isn't ready. 838db1266c8SGavin Shan */ 839db1266c8SGavin Shan if (!phb->initialized) 840db1266c8SGavin Shan return 0; 841db1266c8SGavin Shan 842db1266c8SGavin Shan pdn = pnv_ioda_get_pdn(dev); 843184cd4a3SBenjamin Herrenschmidt if (!pdn || pdn->pe_number == IODA_INVALID_PE) 844184cd4a3SBenjamin Herrenschmidt return -EINVAL; 845db1266c8SGavin Shan 846184cd4a3SBenjamin Herrenschmidt return 0; 847184cd4a3SBenjamin Herrenschmidt } 848184cd4a3SBenjamin Herrenschmidt 849184cd4a3SBenjamin Herrenschmidt static u32 pnv_ioda_bdfn_to_pe(struct pnv_phb *phb, struct pci_bus *bus, 850184cd4a3SBenjamin Herrenschmidt u32 devfn) 851184cd4a3SBenjamin Herrenschmidt { 852184cd4a3SBenjamin Herrenschmidt return phb->ioda.pe_rmap[(bus->number << 8) | devfn]; 853184cd4a3SBenjamin Herrenschmidt } 854184cd4a3SBenjamin Herrenschmidt 855aa0c033fSGavin Shan void __init pnv_pci_init_ioda_phb(struct device_node *np, int ioda_type) 856184cd4a3SBenjamin Herrenschmidt { 857184cd4a3SBenjamin Herrenschmidt struct pci_controller *hose; 858184cd4a3SBenjamin Herrenschmidt static int primary = 1; 859184cd4a3SBenjamin Herrenschmidt struct pnv_phb *phb; 860184cd4a3SBenjamin Herrenschmidt unsigned long size, m32map_off, iomap_off, pemap_off; 861184cd4a3SBenjamin Herrenschmidt const u64 *prop64; 862aa0c033fSGavin Shan const u32 *prop32; 863184cd4a3SBenjamin Herrenschmidt u64 phb_id; 864184cd4a3SBenjamin Herrenschmidt void *aux; 865184cd4a3SBenjamin Herrenschmidt long rc; 866184cd4a3SBenjamin Herrenschmidt 867aa0c033fSGavin Shan pr_info(" Initializing IODA%d OPAL PHB %s\n", ioda_type, np->full_name); 868184cd4a3SBenjamin Herrenschmidt 869184cd4a3SBenjamin Herrenschmidt prop64 = of_get_property(np, "ibm,opal-phbid", NULL); 870184cd4a3SBenjamin Herrenschmidt if (!prop64) { 871184cd4a3SBenjamin Herrenschmidt pr_err(" Missing \"ibm,opal-phbid\" property !\n"); 872184cd4a3SBenjamin Herrenschmidt return; 873184cd4a3SBenjamin Herrenschmidt } 874184cd4a3SBenjamin Herrenschmidt phb_id = be64_to_cpup(prop64); 875184cd4a3SBenjamin Herrenschmidt pr_debug(" PHB-ID : 0x%016llx\n", phb_id); 876184cd4a3SBenjamin Herrenschmidt 877184cd4a3SBenjamin Herrenschmidt phb = alloc_bootmem(sizeof(struct pnv_phb)); 878184cd4a3SBenjamin Herrenschmidt if (phb) { 879184cd4a3SBenjamin Herrenschmidt memset(phb, 0, sizeof(struct pnv_phb)); 880184cd4a3SBenjamin Herrenschmidt phb->hose = hose = pcibios_alloc_controller(np); 881184cd4a3SBenjamin Herrenschmidt } 882184cd4a3SBenjamin Herrenschmidt if (!phb || !phb->hose) { 883184cd4a3SBenjamin Herrenschmidt pr_err("PCI: Failed to allocate PCI controller for %s\n", 884184cd4a3SBenjamin Herrenschmidt np->full_name); 885184cd4a3SBenjamin Herrenschmidt return; 886184cd4a3SBenjamin Herrenschmidt } 887184cd4a3SBenjamin Herrenschmidt 888184cd4a3SBenjamin Herrenschmidt spin_lock_init(&phb->lock); 889184cd4a3SBenjamin Herrenschmidt /* XXX Use device-tree */ 890184cd4a3SBenjamin Herrenschmidt hose->first_busno = 0; 891184cd4a3SBenjamin Herrenschmidt hose->last_busno = 0xff; 892184cd4a3SBenjamin Herrenschmidt hose->private_data = phb; 893184cd4a3SBenjamin Herrenschmidt phb->opal_id = phb_id; 894aa0c033fSGavin Shan phb->type = ioda_type; 895184cd4a3SBenjamin Herrenschmidt 896cee72d5bSBenjamin Herrenschmidt /* Detect specific models for error handling */ 897cee72d5bSBenjamin Herrenschmidt if (of_device_is_compatible(np, "ibm,p7ioc-pciex")) 898cee72d5bSBenjamin Herrenschmidt phb->model = PNV_PHB_MODEL_P7IOC; 899aa0c033fSGavin Shan else if (of_device_is_compatible(np, "ibm,p8-pciex")) 900aa0c033fSGavin Shan phb->model = PNV_PHB_MODEL_PHB3; 901cee72d5bSBenjamin Herrenschmidt else 902cee72d5bSBenjamin Herrenschmidt phb->model = PNV_PHB_MODEL_UNKNOWN; 903cee72d5bSBenjamin Herrenschmidt 904aa0c033fSGavin Shan /* Parse 32-bit and IO ranges (if any) */ 905184cd4a3SBenjamin Herrenschmidt pci_process_bridge_OF_ranges(phb->hose, np, primary); 906184cd4a3SBenjamin Herrenschmidt primary = 0; 907184cd4a3SBenjamin Herrenschmidt 908aa0c033fSGavin Shan /* Get registers */ 909184cd4a3SBenjamin Herrenschmidt phb->regs = of_iomap(np, 0); 910184cd4a3SBenjamin Herrenschmidt if (phb->regs == NULL) 911184cd4a3SBenjamin Herrenschmidt pr_err(" Failed to map registers !\n"); 912184cd4a3SBenjamin Herrenschmidt 913184cd4a3SBenjamin Herrenschmidt /* Initialize more IODA stuff */ 914aa0c033fSGavin Shan prop32 = of_get_property(np, "ibm,opal-num-pes", NULL); 915aa0c033fSGavin Shan if (!prop32) 916aa0c033fSGavin Shan phb->ioda.total_pe = 1; 917aa0c033fSGavin Shan else 918aa0c033fSGavin Shan phb->ioda.total_pe = *prop32; 919184cd4a3SBenjamin Herrenschmidt 920184cd4a3SBenjamin Herrenschmidt phb->ioda.m32_size = resource_size(&hose->mem_resources[0]); 921aa0c033fSGavin Shan /* FW Has already off top 64k of M32 space (MSI space) */ 922184cd4a3SBenjamin Herrenschmidt phb->ioda.m32_size += 0x10000; 923184cd4a3SBenjamin Herrenschmidt 924184cd4a3SBenjamin Herrenschmidt phb->ioda.m32_segsize = phb->ioda.m32_size / phb->ioda.total_pe; 925184cd4a3SBenjamin Herrenschmidt phb->ioda.m32_pci_base = hose->mem_resources[0].start - 926184cd4a3SBenjamin Herrenschmidt hose->pci_mem_offset; 927184cd4a3SBenjamin Herrenschmidt phb->ioda.io_size = hose->pci_io_size; 928184cd4a3SBenjamin Herrenschmidt phb->ioda.io_segsize = phb->ioda.io_size / phb->ioda.total_pe; 929184cd4a3SBenjamin Herrenschmidt phb->ioda.io_pci_base = 0; /* XXX calculate this ? */ 930184cd4a3SBenjamin Herrenschmidt 931aa0c033fSGavin Shan /* Allocate aux data & arrays 932aa0c033fSGavin Shan * 933aa0c033fSGavin Shan * XXX TODO: Don't allocate io segmap on PHB3 934aa0c033fSGavin Shan */ 935184cd4a3SBenjamin Herrenschmidt size = _ALIGN_UP(phb->ioda.total_pe / 8, sizeof(unsigned long)); 936184cd4a3SBenjamin Herrenschmidt m32map_off = size; 937e47747f4SGavin Shan size += phb->ioda.total_pe * sizeof(phb->ioda.m32_segmap[0]); 938184cd4a3SBenjamin Herrenschmidt iomap_off = size; 939e47747f4SGavin Shan size += phb->ioda.total_pe * sizeof(phb->ioda.io_segmap[0]); 940184cd4a3SBenjamin Herrenschmidt pemap_off = size; 941184cd4a3SBenjamin Herrenschmidt size += phb->ioda.total_pe * sizeof(struct pnv_ioda_pe); 942184cd4a3SBenjamin Herrenschmidt aux = alloc_bootmem(size); 943184cd4a3SBenjamin Herrenschmidt memset(aux, 0, size); 944184cd4a3SBenjamin Herrenschmidt phb->ioda.pe_alloc = aux; 945184cd4a3SBenjamin Herrenschmidt phb->ioda.m32_segmap = aux + m32map_off; 946184cd4a3SBenjamin Herrenschmidt phb->ioda.io_segmap = aux + iomap_off; 947184cd4a3SBenjamin Herrenschmidt phb->ioda.pe_array = aux + pemap_off; 948184cd4a3SBenjamin Herrenschmidt set_bit(0, phb->ioda.pe_alloc); 949184cd4a3SBenjamin Herrenschmidt 9507ebdf956SGavin Shan INIT_LIST_HEAD(&phb->ioda.pe_dma_list); 951184cd4a3SBenjamin Herrenschmidt INIT_LIST_HEAD(&phb->ioda.pe_list); 952184cd4a3SBenjamin Herrenschmidt 953184cd4a3SBenjamin Herrenschmidt /* Calculate how many 32-bit TCE segments we have */ 954184cd4a3SBenjamin Herrenschmidt phb->ioda.tce32_count = phb->ioda.m32_pci_base >> 28; 955184cd4a3SBenjamin Herrenschmidt 956184cd4a3SBenjamin Herrenschmidt /* Clear unusable m64 */ 957184cd4a3SBenjamin Herrenschmidt hose->mem_resources[1].flags = 0; 958184cd4a3SBenjamin Herrenschmidt hose->mem_resources[1].start = 0; 959184cd4a3SBenjamin Herrenschmidt hose->mem_resources[1].end = 0; 960184cd4a3SBenjamin Herrenschmidt hose->mem_resources[2].flags = 0; 961184cd4a3SBenjamin Herrenschmidt hose->mem_resources[2].start = 0; 962184cd4a3SBenjamin Herrenschmidt hose->mem_resources[2].end = 0; 963184cd4a3SBenjamin Herrenschmidt 964aa0c033fSGavin Shan #if 0 /* We should really do that ... */ 965184cd4a3SBenjamin Herrenschmidt rc = opal_pci_set_phb_mem_window(opal->phb_id, 966184cd4a3SBenjamin Herrenschmidt window_type, 967184cd4a3SBenjamin Herrenschmidt window_num, 968184cd4a3SBenjamin Herrenschmidt starting_real_address, 969184cd4a3SBenjamin Herrenschmidt starting_pci_address, 970184cd4a3SBenjamin Herrenschmidt segment_size); 971184cd4a3SBenjamin Herrenschmidt #endif 972184cd4a3SBenjamin Herrenschmidt 973184cd4a3SBenjamin Herrenschmidt pr_info(" %d PE's M32: 0x%x [segment=0x%x] IO: 0x%x [segment=0x%x]\n", 974184cd4a3SBenjamin Herrenschmidt phb->ioda.total_pe, 975184cd4a3SBenjamin Herrenschmidt phb->ioda.m32_size, phb->ioda.m32_segsize, 976184cd4a3SBenjamin Herrenschmidt phb->ioda.io_size, phb->ioda.io_segsize); 977184cd4a3SBenjamin Herrenschmidt 978184cd4a3SBenjamin Herrenschmidt phb->hose->ops = &pnv_pci_ops; 979184cd4a3SBenjamin Herrenschmidt 980184cd4a3SBenjamin Herrenschmidt /* Setup RID -> PE mapping function */ 981184cd4a3SBenjamin Herrenschmidt phb->bdfn_to_pe = pnv_ioda_bdfn_to_pe; 982184cd4a3SBenjamin Herrenschmidt 983184cd4a3SBenjamin Herrenschmidt /* Setup TCEs */ 984184cd4a3SBenjamin Herrenschmidt phb->dma_dev_setup = pnv_pci_ioda_dma_dev_setup; 985184cd4a3SBenjamin Herrenschmidt 986184cd4a3SBenjamin Herrenschmidt /* Setup MSI support */ 987184cd4a3SBenjamin Herrenschmidt pnv_pci_init_ioda_msis(phb); 988184cd4a3SBenjamin Herrenschmidt 989c40a4210SGavin Shan /* 990c40a4210SGavin Shan * We pass the PCI probe flag PCI_REASSIGN_ALL_RSRC here 991c40a4210SGavin Shan * to let the PCI core do resource assignment. It's supposed 992c40a4210SGavin Shan * that the PCI core will do correct I/O and MMIO alignment 993c40a4210SGavin Shan * for the P2P bridge bars so that each PCI bus (excluding 994c40a4210SGavin Shan * the child P2P bridges) can form individual PE. 995184cd4a3SBenjamin Herrenschmidt */ 996fb446ad0SGavin Shan ppc_md.pcibios_fixup = pnv_pci_ioda_fixup; 997184cd4a3SBenjamin Herrenschmidt ppc_md.pcibios_enable_device_hook = pnv_pci_enable_device_hook; 998271fd03aSGavin Shan ppc_md.pcibios_window_alignment = pnv_pci_window_alignment; 999c40a4210SGavin Shan pci_add_flags(PCI_REASSIGN_ALL_RSRC); 1000184cd4a3SBenjamin Herrenschmidt 1001184cd4a3SBenjamin Herrenschmidt /* Reset IODA tables to a clean state */ 1002f11fe552SBenjamin Herrenschmidt rc = opal_pci_reset(phb_id, OPAL_PCI_IODA_TABLE_RESET, OPAL_ASSERT_RESET); 1003184cd4a3SBenjamin Herrenschmidt if (rc) 1004f11fe552SBenjamin Herrenschmidt pr_warning(" OPAL Error %ld performing IODA table reset !\n", rc); 1005aa0c033fSGavin Shan 1006aa0c033fSGavin Shan /* 1007aa0c033fSGavin Shan * On IODA1 map everything to PE#0, on IODA2 we assume the IODA reset 1008aa0c033fSGavin Shan * has cleared the RTT which has the same effect 1009aa0c033fSGavin Shan */ 1010aa0c033fSGavin Shan if (ioda_type == PNV_PHB_IODA1) 1011184cd4a3SBenjamin Herrenschmidt opal_pci_set_pe(phb_id, 0, 0, 7, 1, 1 , OPAL_MAP_PE); 1012184cd4a3SBenjamin Herrenschmidt } 1013184cd4a3SBenjamin Herrenschmidt 1014aa0c033fSGavin Shan void pnv_pci_init_ioda2_phb(struct device_node *np) 1015aa0c033fSGavin Shan { 1016aa0c033fSGavin Shan pnv_pci_init_ioda_phb(np, PNV_PHB_IODA2); 1017aa0c033fSGavin Shan } 1018aa0c033fSGavin Shan 1019184cd4a3SBenjamin Herrenschmidt void __init pnv_pci_init_ioda_hub(struct device_node *np) 1020184cd4a3SBenjamin Herrenschmidt { 1021184cd4a3SBenjamin Herrenschmidt struct device_node *phbn; 1022184cd4a3SBenjamin Herrenschmidt const u64 *prop64; 1023184cd4a3SBenjamin Herrenschmidt u64 hub_id; 1024184cd4a3SBenjamin Herrenschmidt 1025184cd4a3SBenjamin Herrenschmidt pr_info("Probing IODA IO-Hub %s\n", np->full_name); 1026184cd4a3SBenjamin Herrenschmidt 1027184cd4a3SBenjamin Herrenschmidt prop64 = of_get_property(np, "ibm,opal-hubid", NULL); 1028184cd4a3SBenjamin Herrenschmidt if (!prop64) { 1029184cd4a3SBenjamin Herrenschmidt pr_err(" Missing \"ibm,opal-hubid\" property !\n"); 1030184cd4a3SBenjamin Herrenschmidt return; 1031184cd4a3SBenjamin Herrenschmidt } 1032184cd4a3SBenjamin Herrenschmidt hub_id = be64_to_cpup(prop64); 1033184cd4a3SBenjamin Herrenschmidt pr_devel(" HUB-ID : 0x%016llx\n", hub_id); 1034184cd4a3SBenjamin Herrenschmidt 1035184cd4a3SBenjamin Herrenschmidt /* Count child PHBs */ 1036184cd4a3SBenjamin Herrenschmidt for_each_child_of_node(np, phbn) { 1037184cd4a3SBenjamin Herrenschmidt /* Look for IODA1 PHBs */ 1038184cd4a3SBenjamin Herrenschmidt if (of_device_is_compatible(phbn, "ibm,ioda-phb")) 1039aa0c033fSGavin Shan pnv_pci_init_ioda_phb(phbn, PNV_PHB_IODA1); 1040184cd4a3SBenjamin Herrenschmidt } 1041184cd4a3SBenjamin Herrenschmidt } 1042