12874c5fdSThomas Gleixner // SPDX-License-Identifier: GPL-2.0-or-later 2184cd4a3SBenjamin Herrenschmidt /* 3184cd4a3SBenjamin Herrenschmidt * Support PCI/PCIe on PowerNV platforms 4184cd4a3SBenjamin Herrenschmidt * 5184cd4a3SBenjamin Herrenschmidt * Copyright 2011 Benjamin Herrenschmidt, IBM Corp. 6184cd4a3SBenjamin Herrenschmidt */ 7184cd4a3SBenjamin Herrenschmidt 8cee72d5bSBenjamin Herrenschmidt #undef DEBUG 9184cd4a3SBenjamin Herrenschmidt 10184cd4a3SBenjamin Herrenschmidt #include <linux/kernel.h> 11184cd4a3SBenjamin Herrenschmidt #include <linux/pci.h> 12361f2a2aSGavin Shan #include <linux/crash_dump.h> 13184cd4a3SBenjamin Herrenschmidt #include <linux/delay.h> 14184cd4a3SBenjamin Herrenschmidt #include <linux/string.h> 15184cd4a3SBenjamin Herrenschmidt #include <linux/init.h> 1657c8a661SMike Rapoport #include <linux/memblock.h> 17184cd4a3SBenjamin Herrenschmidt #include <linux/irq.h> 18184cd4a3SBenjamin Herrenschmidt #include <linux/io.h> 19184cd4a3SBenjamin Herrenschmidt #include <linux/msi.h> 20ac9a5889SAlexey Kardashevskiy #include <linux/iommu.h> 21e57080f1SAlexey Kardashevskiy #include <linux/rculist.h> 224793d65dSAlexey Kardashevskiy #include <linux/sizes.h> 23184cd4a3SBenjamin Herrenschmidt 24184cd4a3SBenjamin Herrenschmidt #include <asm/sections.h> 25184cd4a3SBenjamin Herrenschmidt #include <asm/io.h> 26184cd4a3SBenjamin Herrenschmidt #include <asm/prom.h> 27184cd4a3SBenjamin Herrenschmidt #include <asm/pci-bridge.h> 28184cd4a3SBenjamin Herrenschmidt #include <asm/machdep.h> 29fb1b55d6SGavin Shan #include <asm/msi_bitmap.h> 30184cd4a3SBenjamin Herrenschmidt #include <asm/ppc-pci.h> 31184cd4a3SBenjamin Herrenschmidt #include <asm/opal.h> 32184cd4a3SBenjamin Herrenschmidt #include <asm/iommu.h> 33184cd4a3SBenjamin Herrenschmidt #include <asm/tce.h> 34137436c9SGavin Shan #include <asm/xics.h> 357644d581SMichael Ellerman #include <asm/debugfs.h> 36262af557SGuo Chao #include <asm/firmware.h> 3780c49c7eSIan Munsie #include <asm/pnv-pci.h> 38aca6913fSAlexey Kardashevskiy #include <asm/mmzone.h> 3980c49c7eSIan Munsie 40ec249dd8SMichael Neuling #include <misc/cxl-base.h> 41184cd4a3SBenjamin Herrenschmidt 42184cd4a3SBenjamin Herrenschmidt #include "powernv.h" 43184cd4a3SBenjamin Herrenschmidt #include "pci.h" 4444bda4b7SHari Vyas #include "../../../../drivers/pci/pci.h" 45184cd4a3SBenjamin Herrenschmidt 4699451551SGavin Shan #define PNV_IODA1_M64_NUM 16 /* Number of M64 BARs */ 4799451551SGavin Shan #define PNV_IODA1_M64_SEGS 8 /* Segments per M64 BAR */ 48acce971cSGavin Shan #define PNV_IODA1_DMA32_SEGSIZE 0x10000000 49781a868fSWei Yang 507f2c39e9SFrederic Barrat static const char * const pnv_phb_names[] = { "IODA1", "IODA2", "NPU_NVLINK", 517f2c39e9SFrederic Barrat "NPU_OCAPI" }; 52aca6913fSAlexey Kardashevskiy 53c498a4f9SChristoph Hellwig static void pnv_pci_ioda2_set_bypass(struct pnv_ioda_pe *pe, bool enable); 54dc3d8f85SOliver O'Halloran static void pnv_pci_configure_bus(struct pci_bus *bus); 55c498a4f9SChristoph Hellwig 567d623e42SAlexey Kardashevskiy void pe_level_printk(const struct pnv_ioda_pe *pe, const char *level, 576d31c2faSJoe Perches const char *fmt, ...) 586d31c2faSJoe Perches { 596d31c2faSJoe Perches struct va_format vaf; 606d31c2faSJoe Perches va_list args; 616d31c2faSJoe Perches char pfix[32]; 62184cd4a3SBenjamin Herrenschmidt 636d31c2faSJoe Perches va_start(args, fmt); 646d31c2faSJoe Perches 656d31c2faSJoe Perches vaf.fmt = fmt; 666d31c2faSJoe Perches vaf.va = &args; 676d31c2faSJoe Perches 68781a868fSWei Yang if (pe->flags & PNV_IODA_PE_DEV) 696d31c2faSJoe Perches strlcpy(pfix, dev_name(&pe->pdev->dev), sizeof(pfix)); 70781a868fSWei Yang else if (pe->flags & (PNV_IODA_PE_BUS | PNV_IODA_PE_BUS_ALL)) 716d31c2faSJoe Perches sprintf(pfix, "%04x:%02x ", 726d31c2faSJoe Perches pci_domain_nr(pe->pbus), pe->pbus->number); 73781a868fSWei Yang #ifdef CONFIG_PCI_IOV 74781a868fSWei Yang else if (pe->flags & PNV_IODA_PE_VF) 75781a868fSWei Yang sprintf(pfix, "%04x:%02x:%2x.%d", 76781a868fSWei Yang pci_domain_nr(pe->parent_dev->bus), 77781a868fSWei Yang (pe->rid & 0xff00) >> 8, 78781a868fSWei Yang PCI_SLOT(pe->rid), PCI_FUNC(pe->rid)); 79781a868fSWei Yang #endif /* CONFIG_PCI_IOV*/ 806d31c2faSJoe Perches 811f52f176SRussell Currey printk("%spci %s: [PE# %.2x] %pV", 826d31c2faSJoe Perches level, pfix, pe->pe_number, &vaf); 836d31c2faSJoe Perches 846d31c2faSJoe Perches va_end(args); 856d31c2faSJoe Perches } 866d31c2faSJoe Perches 874e287840SThadeu Lima de Souza Cascardo static bool pnv_iommu_bypass_disabled __read_mostly; 8845baee14SGuilherme G. Piccoli static bool pci_reset_phbs __read_mostly; 894e287840SThadeu Lima de Souza Cascardo 904e287840SThadeu Lima de Souza Cascardo static int __init iommu_setup(char *str) 914e287840SThadeu Lima de Souza Cascardo { 924e287840SThadeu Lima de Souza Cascardo if (!str) 934e287840SThadeu Lima de Souza Cascardo return -EINVAL; 944e287840SThadeu Lima de Souza Cascardo 954e287840SThadeu Lima de Souza Cascardo while (*str) { 964e287840SThadeu Lima de Souza Cascardo if (!strncmp(str, "nobypass", 8)) { 974e287840SThadeu Lima de Souza Cascardo pnv_iommu_bypass_disabled = true; 984e287840SThadeu Lima de Souza Cascardo pr_info("PowerNV: IOMMU bypass window disabled.\n"); 994e287840SThadeu Lima de Souza Cascardo break; 1004e287840SThadeu Lima de Souza Cascardo } 1014e287840SThadeu Lima de Souza Cascardo str += strcspn(str, ","); 1024e287840SThadeu Lima de Souza Cascardo if (*str == ',') 1034e287840SThadeu Lima de Souza Cascardo str++; 1044e287840SThadeu Lima de Souza Cascardo } 1054e287840SThadeu Lima de Souza Cascardo 1064e287840SThadeu Lima de Souza Cascardo return 0; 1074e287840SThadeu Lima de Souza Cascardo } 1084e287840SThadeu Lima de Souza Cascardo early_param("iommu", iommu_setup); 1094e287840SThadeu Lima de Souza Cascardo 11045baee14SGuilherme G. Piccoli static int __init pci_reset_phbs_setup(char *str) 11145baee14SGuilherme G. Piccoli { 11245baee14SGuilherme G. Piccoli pci_reset_phbs = true; 11345baee14SGuilherme G. Piccoli return 0; 11445baee14SGuilherme G. Piccoli } 11545baee14SGuilherme G. Piccoli 11645baee14SGuilherme G. Piccoli early_param("ppc_pci_reset_phbs", pci_reset_phbs_setup); 11745baee14SGuilherme G. Piccoli 1181e916772SGavin Shan static struct pnv_ioda_pe *pnv_ioda_init_pe(struct pnv_phb *phb, int pe_no) 1191e916772SGavin Shan { 120313483ddSGavin Shan s64 rc; 121313483ddSGavin Shan 1221e916772SGavin Shan phb->ioda.pe_array[pe_no].phb = phb; 1231e916772SGavin Shan phb->ioda.pe_array[pe_no].pe_number = pe_no; 12401e12629SOliver O'Halloran phb->ioda.pe_array[pe_no].dma_setup_done = false; 1251e916772SGavin Shan 126313483ddSGavin Shan /* 127313483ddSGavin Shan * Clear the PE frozen state as it might be put into frozen state 128313483ddSGavin Shan * in the last PCI remove path. It's not harmful to do so when the 129313483ddSGavin Shan * PE is already in unfrozen state. 130313483ddSGavin Shan */ 131313483ddSGavin Shan rc = opal_pci_eeh_freeze_clear(phb->opal_id, pe_no, 132313483ddSGavin Shan OPAL_EEH_ACTION_CLEAR_FREEZE_ALL); 133d4791db5SRussell Currey if (rc != OPAL_SUCCESS && rc != OPAL_UNSUPPORTED) 1341f52f176SRussell Currey pr_warn("%s: Error %lld unfreezing PHB#%x-PE#%x\n", 135313483ddSGavin Shan __func__, rc, phb->hose->global_number, pe_no); 136313483ddSGavin Shan 1371e916772SGavin Shan return &phb->ioda.pe_array[pe_no]; 1381e916772SGavin Shan } 1391e916772SGavin Shan 1404b82ab18SGavin Shan static void pnv_ioda_reserve_pe(struct pnv_phb *phb, int pe_no) 1414b82ab18SGavin Shan { 14292b8f137SGavin Shan if (!(pe_no >= 0 && pe_no < phb->ioda.total_pe_num)) { 1431f52f176SRussell Currey pr_warn("%s: Invalid PE %x on PHB#%x\n", 1444b82ab18SGavin Shan __func__, pe_no, phb->hose->global_number); 1454b82ab18SGavin Shan return; 1464b82ab18SGavin Shan } 1474b82ab18SGavin Shan 148a4bc676eSOliver O'Halloran mutex_lock(&phb->ioda.pe_alloc_mutex); 149e9dc4d7fSGavin Shan if (test_and_set_bit(pe_no, phb->ioda.pe_alloc)) 1501f52f176SRussell Currey pr_debug("%s: PE %x was reserved on PHB#%x\n", 1514b82ab18SGavin Shan __func__, pe_no, phb->hose->global_number); 152a4bc676eSOliver O'Halloran mutex_unlock(&phb->ioda.pe_alloc_mutex); 1534b82ab18SGavin Shan 1541e916772SGavin Shan pnv_ioda_init_pe(phb, pe_no); 1554b82ab18SGavin Shan } 1564b82ab18SGavin Shan 157a4bc676eSOliver O'Halloran struct pnv_ioda_pe *pnv_ioda_alloc_pe(struct pnv_phb *phb, int count) 158184cd4a3SBenjamin Herrenschmidt { 159a4bc676eSOliver O'Halloran struct pnv_ioda_pe *ret = NULL; 160a4bc676eSOliver O'Halloran int run = 0, pe, i; 161184cd4a3SBenjamin Herrenschmidt 162a4bc676eSOliver O'Halloran mutex_lock(&phb->ioda.pe_alloc_mutex); 163a4bc676eSOliver O'Halloran 164a4bc676eSOliver O'Halloran /* scan backwards for a run of @count cleared bits */ 1659fcd6f4aSGavin Shan for (pe = phb->ioda.total_pe_num - 1; pe >= 0; pe--) { 166a4bc676eSOliver O'Halloran if (test_bit(pe, phb->ioda.pe_alloc)) { 167a4bc676eSOliver O'Halloran run = 0; 168a4bc676eSOliver O'Halloran continue; 169184cd4a3SBenjamin Herrenschmidt } 170184cd4a3SBenjamin Herrenschmidt 171a4bc676eSOliver O'Halloran run++; 172a4bc676eSOliver O'Halloran if (run == count) 173a4bc676eSOliver O'Halloran break; 174a4bc676eSOliver O'Halloran } 175a4bc676eSOliver O'Halloran if (run != count) 176a4bc676eSOliver O'Halloran goto out; 177a4bc676eSOliver O'Halloran 178a4bc676eSOliver O'Halloran for (i = pe; i < pe + count; i++) { 179a4bc676eSOliver O'Halloran set_bit(i, phb->ioda.pe_alloc); 180a4bc676eSOliver O'Halloran pnv_ioda_init_pe(phb, i); 181a4bc676eSOliver O'Halloran } 182a4bc676eSOliver O'Halloran ret = &phb->ioda.pe_array[pe]; 183a4bc676eSOliver O'Halloran 184a4bc676eSOliver O'Halloran out: 185a4bc676eSOliver O'Halloran mutex_unlock(&phb->ioda.pe_alloc_mutex); 186a4bc676eSOliver O'Halloran return ret; 1879fcd6f4aSGavin Shan } 1889fcd6f4aSGavin Shan 18937b59ef0SOliver O'Halloran void pnv_ioda_free_pe(struct pnv_ioda_pe *pe) 190184cd4a3SBenjamin Herrenschmidt { 1911e916772SGavin Shan struct pnv_phb *phb = pe->phb; 192caa58f80SGavin Shan unsigned int pe_num = pe->pe_number; 193184cd4a3SBenjamin Herrenschmidt 1941e916772SGavin Shan WARN_ON(pe->pdev); 195f724385fSFrederic Barrat WARN_ON(pe->npucomp); /* NPUs for nvlink are not supposed to be freed */ 1960bd97167SAlexey Kardashevskiy kfree(pe->npucomp); 1971e916772SGavin Shan memset(pe, 0, sizeof(struct pnv_ioda_pe)); 198a4bc676eSOliver O'Halloran 199a4bc676eSOliver O'Halloran mutex_lock(&phb->ioda.pe_alloc_mutex); 200caa58f80SGavin Shan clear_bit(pe_num, phb->ioda.pe_alloc); 201a4bc676eSOliver O'Halloran mutex_unlock(&phb->ioda.pe_alloc_mutex); 202184cd4a3SBenjamin Herrenschmidt } 203184cd4a3SBenjamin Herrenschmidt 204262af557SGuo Chao /* The default M64 BAR is shared by all PEs */ 205262af557SGuo Chao static int pnv_ioda2_init_m64(struct pnv_phb *phb) 206262af557SGuo Chao { 207262af557SGuo Chao const char *desc; 208262af557SGuo Chao struct resource *r; 209262af557SGuo Chao s64 rc; 210262af557SGuo Chao 211262af557SGuo Chao /* Configure the default M64 BAR */ 212262af557SGuo Chao rc = opal_pci_set_phb_mem_window(phb->opal_id, 213262af557SGuo Chao OPAL_M64_WINDOW_TYPE, 214262af557SGuo Chao phb->ioda.m64_bar_idx, 215262af557SGuo Chao phb->ioda.m64_base, 216262af557SGuo Chao 0, /* unused */ 217262af557SGuo Chao phb->ioda.m64_size); 218262af557SGuo Chao if (rc != OPAL_SUCCESS) { 219262af557SGuo Chao desc = "configuring"; 220262af557SGuo Chao goto fail; 221262af557SGuo Chao } 222262af557SGuo Chao 223262af557SGuo Chao /* Enable the default M64 BAR */ 224262af557SGuo Chao rc = opal_pci_phb_mmio_enable(phb->opal_id, 225262af557SGuo Chao OPAL_M64_WINDOW_TYPE, 226262af557SGuo Chao phb->ioda.m64_bar_idx, 227262af557SGuo Chao OPAL_ENABLE_M64_SPLIT); 228262af557SGuo Chao if (rc != OPAL_SUCCESS) { 229262af557SGuo Chao desc = "enabling"; 230262af557SGuo Chao goto fail; 231262af557SGuo Chao } 232262af557SGuo Chao 233262af557SGuo Chao /* 23463803c39SGavin Shan * Exclude the segments for reserved and root bus PE, which 23563803c39SGavin Shan * are first or last two PEs. 236262af557SGuo Chao */ 237262af557SGuo Chao r = &phb->hose->mem_resources[1]; 23892b8f137SGavin Shan if (phb->ioda.reserved_pe_idx == 0) 23963803c39SGavin Shan r->start += (2 * phb->ioda.m64_segsize); 24092b8f137SGavin Shan else if (phb->ioda.reserved_pe_idx == (phb->ioda.total_pe_num - 1)) 24163803c39SGavin Shan r->end -= (2 * phb->ioda.m64_segsize); 242262af557SGuo Chao else 2431f52f176SRussell Currey pr_warn(" Cannot strip M64 segment for reserved PE#%x\n", 24492b8f137SGavin Shan phb->ioda.reserved_pe_idx); 245262af557SGuo Chao 246262af557SGuo Chao return 0; 247262af557SGuo Chao 248262af557SGuo Chao fail: 249262af557SGuo Chao pr_warn(" Failure %lld %s M64 BAR#%d\n", 250262af557SGuo Chao rc, desc, phb->ioda.m64_bar_idx); 251262af557SGuo Chao opal_pci_phb_mmio_enable(phb->opal_id, 252262af557SGuo Chao OPAL_M64_WINDOW_TYPE, 253262af557SGuo Chao phb->ioda.m64_bar_idx, 254262af557SGuo Chao OPAL_DISABLE_M64); 255262af557SGuo Chao return -EIO; 256262af557SGuo Chao } 257262af557SGuo Chao 258c430670aSGavin Shan static void pnv_ioda_reserve_dev_m64_pe(struct pci_dev *pdev, 25996a2f92bSGavin Shan unsigned long *pe_bitmap) 260262af557SGuo Chao { 2615609ffddSOliver O'Halloran struct pnv_phb *phb = pci_bus_to_pnvhb(pdev->bus); 262262af557SGuo Chao struct resource *r; 26396a2f92bSGavin Shan resource_size_t base, sgsz, start, end; 26496a2f92bSGavin Shan int segno, i; 265262af557SGuo Chao 26696a2f92bSGavin Shan base = phb->ioda.m64_base; 26796a2f92bSGavin Shan sgsz = phb->ioda.m64_segsize; 26896a2f92bSGavin Shan for (i = 0; i <= PCI_ROM_RESOURCE; i++) { 26996a2f92bSGavin Shan r = &pdev->resource[i]; 2705958d19aSBenjamin Herrenschmidt if (!r->parent || !pnv_pci_is_m64(phb, r)) 271262af557SGuo Chao continue; 272262af557SGuo Chao 273e96d904eSChristophe Leroy start = ALIGN_DOWN(r->start - base, sgsz); 274b7115316SChristophe Leroy end = ALIGN(r->end - base, sgsz); 27596a2f92bSGavin Shan for (segno = start / sgsz; segno < end / sgsz; segno++) { 27696a2f92bSGavin Shan if (pe_bitmap) 27796a2f92bSGavin Shan set_bit(segno, pe_bitmap); 27896a2f92bSGavin Shan else 27996a2f92bSGavin Shan pnv_ioda_reserve_pe(phb, segno); 280262af557SGuo Chao } 281262af557SGuo Chao } 282262af557SGuo Chao } 283262af557SGuo Chao 28499451551SGavin Shan static int pnv_ioda1_init_m64(struct pnv_phb *phb) 28599451551SGavin Shan { 28699451551SGavin Shan struct resource *r; 28799451551SGavin Shan int index; 28899451551SGavin Shan 28999451551SGavin Shan /* 29099451551SGavin Shan * There are 16 M64 BARs, each of which has 8 segments. So 29199451551SGavin Shan * there are as many M64 segments as the maximum number of 29299451551SGavin Shan * PEs, which is 128. 29399451551SGavin Shan */ 29499451551SGavin Shan for (index = 0; index < PNV_IODA1_M64_NUM; index++) { 29599451551SGavin Shan unsigned long base, segsz = phb->ioda.m64_segsize; 29699451551SGavin Shan int64_t rc; 29799451551SGavin Shan 29899451551SGavin Shan base = phb->ioda.m64_base + 29999451551SGavin Shan index * PNV_IODA1_M64_SEGS * segsz; 30099451551SGavin Shan rc = opal_pci_set_phb_mem_window(phb->opal_id, 30199451551SGavin Shan OPAL_M64_WINDOW_TYPE, index, base, 0, 30299451551SGavin Shan PNV_IODA1_M64_SEGS * segsz); 30399451551SGavin Shan if (rc != OPAL_SUCCESS) { 3041f52f176SRussell Currey pr_warn(" Error %lld setting M64 PHB#%x-BAR#%d\n", 30599451551SGavin Shan rc, phb->hose->global_number, index); 30699451551SGavin Shan goto fail; 30799451551SGavin Shan } 30899451551SGavin Shan 30999451551SGavin Shan rc = opal_pci_phb_mmio_enable(phb->opal_id, 31099451551SGavin Shan OPAL_M64_WINDOW_TYPE, index, 31199451551SGavin Shan OPAL_ENABLE_M64_SPLIT); 31299451551SGavin Shan if (rc != OPAL_SUCCESS) { 3131f52f176SRussell Currey pr_warn(" Error %lld enabling M64 PHB#%x-BAR#%d\n", 31499451551SGavin Shan rc, phb->hose->global_number, index); 31599451551SGavin Shan goto fail; 31699451551SGavin Shan } 31799451551SGavin Shan } 31899451551SGavin Shan 31936963365SOliver O'Halloran for (index = 0; index < phb->ioda.total_pe_num; index++) { 32036963365SOliver O'Halloran int64_t rc; 32136963365SOliver O'Halloran 32236963365SOliver O'Halloran /* 32336963365SOliver O'Halloran * P7IOC supports M64DT, which helps mapping M64 segment 32436963365SOliver O'Halloran * to one particular PE#. However, PHB3 has fixed mapping 32536963365SOliver O'Halloran * between M64 segment and PE#. In order to have same logic 32636963365SOliver O'Halloran * for P7IOC and PHB3, we enforce fixed mapping between M64 32736963365SOliver O'Halloran * segment and PE# on P7IOC. 32836963365SOliver O'Halloran */ 32936963365SOliver O'Halloran rc = opal_pci_map_pe_mmio_window(phb->opal_id, 33036963365SOliver O'Halloran index, OPAL_M64_WINDOW_TYPE, 33136963365SOliver O'Halloran index / PNV_IODA1_M64_SEGS, 33236963365SOliver O'Halloran index % PNV_IODA1_M64_SEGS); 33336963365SOliver O'Halloran if (rc != OPAL_SUCCESS) { 33436963365SOliver O'Halloran pr_warn("%s: Error %lld mapping M64 for PHB#%x-PE#%x\n", 33536963365SOliver O'Halloran __func__, rc, phb->hose->global_number, 33636963365SOliver O'Halloran index); 33736963365SOliver O'Halloran goto fail; 33836963365SOliver O'Halloran } 33936963365SOliver O'Halloran } 34036963365SOliver O'Halloran 34199451551SGavin Shan /* 34263803c39SGavin Shan * Exclude the segments for reserved and root bus PE, which 34363803c39SGavin Shan * are first or last two PEs. 34499451551SGavin Shan */ 34599451551SGavin Shan r = &phb->hose->mem_resources[1]; 34699451551SGavin Shan if (phb->ioda.reserved_pe_idx == 0) 34763803c39SGavin Shan r->start += (2 * phb->ioda.m64_segsize); 34899451551SGavin Shan else if (phb->ioda.reserved_pe_idx == (phb->ioda.total_pe_num - 1)) 34963803c39SGavin Shan r->end -= (2 * phb->ioda.m64_segsize); 35099451551SGavin Shan else 3511f52f176SRussell Currey WARN(1, "Wrong reserved PE#%x on PHB#%x\n", 35299451551SGavin Shan phb->ioda.reserved_pe_idx, phb->hose->global_number); 35399451551SGavin Shan 35499451551SGavin Shan return 0; 35599451551SGavin Shan 35699451551SGavin Shan fail: 35799451551SGavin Shan for ( ; index >= 0; index--) 35899451551SGavin Shan opal_pci_phb_mmio_enable(phb->opal_id, 35999451551SGavin Shan OPAL_M64_WINDOW_TYPE, index, OPAL_DISABLE_M64); 36099451551SGavin Shan 36199451551SGavin Shan return -EIO; 36299451551SGavin Shan } 36399451551SGavin Shan 364c430670aSGavin Shan static void pnv_ioda_reserve_m64_pe(struct pci_bus *bus, 36596a2f92bSGavin Shan unsigned long *pe_bitmap, 36696a2f92bSGavin Shan bool all) 367262af557SGuo Chao { 368262af557SGuo Chao struct pci_dev *pdev; 36996a2f92bSGavin Shan 37096a2f92bSGavin Shan list_for_each_entry(pdev, &bus->devices, bus_list) { 371c430670aSGavin Shan pnv_ioda_reserve_dev_m64_pe(pdev, pe_bitmap); 37296a2f92bSGavin Shan 37396a2f92bSGavin Shan if (all && pdev->subordinate) 374c430670aSGavin Shan pnv_ioda_reserve_m64_pe(pdev->subordinate, 37596a2f92bSGavin Shan pe_bitmap, all); 37696a2f92bSGavin Shan } 37796a2f92bSGavin Shan } 37896a2f92bSGavin Shan 3791e916772SGavin Shan static struct pnv_ioda_pe *pnv_ioda_pick_m64_pe(struct pci_bus *bus, bool all) 380262af557SGuo Chao { 3815609ffddSOliver O'Halloran struct pnv_phb *phb = pci_bus_to_pnvhb(bus); 382262af557SGuo Chao struct pnv_ioda_pe *master_pe, *pe; 383262af557SGuo Chao unsigned long size, *pe_alloc; 38426ba248dSGavin Shan int i; 385262af557SGuo Chao 386262af557SGuo Chao /* Root bus shouldn't use M64 */ 387262af557SGuo Chao if (pci_is_root_bus(bus)) 3881e916772SGavin Shan return NULL; 389262af557SGuo Chao 390262af557SGuo Chao /* Allocate bitmap */ 391b7115316SChristophe Leroy size = ALIGN(phb->ioda.total_pe_num / 8, sizeof(unsigned long)); 392262af557SGuo Chao pe_alloc = kzalloc(size, GFP_KERNEL); 393262af557SGuo Chao if (!pe_alloc) { 394262af557SGuo Chao pr_warn("%s: Out of memory !\n", 395262af557SGuo Chao __func__); 3961e916772SGavin Shan return NULL; 397262af557SGuo Chao } 398262af557SGuo Chao 39926ba248dSGavin Shan /* Figure out reserved PE numbers by the PE */ 400c430670aSGavin Shan pnv_ioda_reserve_m64_pe(bus, pe_alloc, all); 401262af557SGuo Chao 402262af557SGuo Chao /* 403262af557SGuo Chao * the current bus might not own M64 window and that's all 404262af557SGuo Chao * contributed by its child buses. For the case, we needn't 405262af557SGuo Chao * pick M64 dependent PE#. 406262af557SGuo Chao */ 40792b8f137SGavin Shan if (bitmap_empty(pe_alloc, phb->ioda.total_pe_num)) { 408262af557SGuo Chao kfree(pe_alloc); 4091e916772SGavin Shan return NULL; 410262af557SGuo Chao } 411262af557SGuo Chao 412262af557SGuo Chao /* 413262af557SGuo Chao * Figure out the master PE and put all slave PEs to master 414262af557SGuo Chao * PE's list to form compound PE. 415262af557SGuo Chao */ 416262af557SGuo Chao master_pe = NULL; 417262af557SGuo Chao i = -1; 41892b8f137SGavin Shan while ((i = find_next_bit(pe_alloc, phb->ioda.total_pe_num, i + 1)) < 41992b8f137SGavin Shan phb->ioda.total_pe_num) { 420262af557SGuo Chao pe = &phb->ioda.pe_array[i]; 421262af557SGuo Chao 42293289d8cSGavin Shan phb->ioda.m64_segmap[pe->pe_number] = pe->pe_number; 423262af557SGuo Chao if (!master_pe) { 424262af557SGuo Chao pe->flags |= PNV_IODA_PE_MASTER; 425262af557SGuo Chao INIT_LIST_HEAD(&pe->slaves); 426262af557SGuo Chao master_pe = pe; 427262af557SGuo Chao } else { 428262af557SGuo Chao pe->flags |= PNV_IODA_PE_SLAVE; 429262af557SGuo Chao pe->master = master_pe; 430262af557SGuo Chao list_add_tail(&pe->list, &master_pe->slaves); 431262af557SGuo Chao } 432262af557SGuo Chao } 433262af557SGuo Chao 434262af557SGuo Chao kfree(pe_alloc); 4351e916772SGavin Shan return master_pe; 436262af557SGuo Chao } 437262af557SGuo Chao 438262af557SGuo Chao static void __init pnv_ioda_parse_m64_window(struct pnv_phb *phb) 439262af557SGuo Chao { 440262af557SGuo Chao struct pci_controller *hose = phb->hose; 441262af557SGuo Chao struct device_node *dn = hose->dn; 442262af557SGuo Chao struct resource *res; 443a1339fafSBenjamin Herrenschmidt u32 m64_range[2], i; 4440e7736c6SGavin Shan const __be32 *r; 445262af557SGuo Chao u64 pci_addr; 446262af557SGuo Chao 44799451551SGavin Shan if (phb->type != PNV_PHB_IODA1 && phb->type != PNV_PHB_IODA2) { 4481665c4a8SGavin Shan pr_info(" Not support M64 window\n"); 4491665c4a8SGavin Shan return; 4501665c4a8SGavin Shan } 4511665c4a8SGavin Shan 452e4d54f71SStewart Smith if (!firmware_has_feature(FW_FEATURE_OPAL)) { 453262af557SGuo Chao pr_info(" Firmware too old to support M64 window\n"); 454262af557SGuo Chao return; 455262af557SGuo Chao } 456262af557SGuo Chao 457262af557SGuo Chao r = of_get_property(dn, "ibm,opal-m64-window", NULL); 458262af557SGuo Chao if (!r) { 459b7c670d6SRob Herring pr_info(" No <ibm,opal-m64-window> on %pOF\n", 460b7c670d6SRob Herring dn); 461262af557SGuo Chao return; 462262af557SGuo Chao } 463262af557SGuo Chao 464a1339fafSBenjamin Herrenschmidt /* 465a1339fafSBenjamin Herrenschmidt * Find the available M64 BAR range and pickup the last one for 466a1339fafSBenjamin Herrenschmidt * covering the whole 64-bits space. We support only one range. 467a1339fafSBenjamin Herrenschmidt */ 468a1339fafSBenjamin Herrenschmidt if (of_property_read_u32_array(dn, "ibm,opal-available-m64-ranges", 469a1339fafSBenjamin Herrenschmidt m64_range, 2)) { 470a1339fafSBenjamin Herrenschmidt /* In absence of the property, assume 0..15 */ 471a1339fafSBenjamin Herrenschmidt m64_range[0] = 0; 472a1339fafSBenjamin Herrenschmidt m64_range[1] = 16; 473a1339fafSBenjamin Herrenschmidt } 474a1339fafSBenjamin Herrenschmidt /* We only support 64 bits in our allocator */ 475a1339fafSBenjamin Herrenschmidt if (m64_range[1] > 63) { 476a1339fafSBenjamin Herrenschmidt pr_warn("%s: Limiting M64 range to 63 (from %d) on PHB#%x\n", 477a1339fafSBenjamin Herrenschmidt __func__, m64_range[1], phb->hose->global_number); 478a1339fafSBenjamin Herrenschmidt m64_range[1] = 63; 479a1339fafSBenjamin Herrenschmidt } 480a1339fafSBenjamin Herrenschmidt /* Empty range, no m64 */ 481a1339fafSBenjamin Herrenschmidt if (m64_range[1] <= m64_range[0]) { 482a1339fafSBenjamin Herrenschmidt pr_warn("%s: M64 empty, disabling M64 usage on PHB#%x\n", 483a1339fafSBenjamin Herrenschmidt __func__, phb->hose->global_number); 484a1339fafSBenjamin Herrenschmidt return; 485a1339fafSBenjamin Herrenschmidt } 486a1339fafSBenjamin Herrenschmidt 487a1339fafSBenjamin Herrenschmidt /* Configure M64 informations */ 488262af557SGuo Chao res = &hose->mem_resources[1]; 489e80c4e7cSGavin Shan res->name = dn->full_name; 490262af557SGuo Chao res->start = of_translate_address(dn, r + 2); 491262af557SGuo Chao res->end = res->start + of_read_number(r + 4, 2) - 1; 492262af557SGuo Chao res->flags = (IORESOURCE_MEM | IORESOURCE_MEM_64 | IORESOURCE_PREFETCH); 493262af557SGuo Chao pci_addr = of_read_number(r, 2); 494262af557SGuo Chao hose->mem_offset[1] = res->start - pci_addr; 495262af557SGuo Chao 496262af557SGuo Chao phb->ioda.m64_size = resource_size(res); 49792b8f137SGavin Shan phb->ioda.m64_segsize = phb->ioda.m64_size / phb->ioda.total_pe_num; 498262af557SGuo Chao phb->ioda.m64_base = pci_addr; 499262af557SGuo Chao 500a1339fafSBenjamin Herrenschmidt /* This lines up nicely with the display from processing OF ranges */ 501a1339fafSBenjamin Herrenschmidt pr_info(" MEM 0x%016llx..0x%016llx -> 0x%016llx (M64 #%d..%d)\n", 502a1339fafSBenjamin Herrenschmidt res->start, res->end, pci_addr, m64_range[0], 503a1339fafSBenjamin Herrenschmidt m64_range[0] + m64_range[1] - 1); 504a1339fafSBenjamin Herrenschmidt 505a1339fafSBenjamin Herrenschmidt /* Mark all M64 used up by default */ 506a1339fafSBenjamin Herrenschmidt phb->ioda.m64_bar_alloc = (unsigned long)-1; 507e9863e68SWei Yang 508262af557SGuo Chao /* Use last M64 BAR to cover M64 window */ 509a1339fafSBenjamin Herrenschmidt m64_range[1]--; 510a1339fafSBenjamin Herrenschmidt phb->ioda.m64_bar_idx = m64_range[0] + m64_range[1]; 511a1339fafSBenjamin Herrenschmidt 512a1339fafSBenjamin Herrenschmidt pr_info(" Using M64 #%d as default window\n", phb->ioda.m64_bar_idx); 513a1339fafSBenjamin Herrenschmidt 514a1339fafSBenjamin Herrenschmidt /* Mark remaining ones free */ 515a1339fafSBenjamin Herrenschmidt for (i = m64_range[0]; i < m64_range[1]; i++) 516a1339fafSBenjamin Herrenschmidt clear_bit(i, &phb->ioda.m64_bar_alloc); 517a1339fafSBenjamin Herrenschmidt 518a1339fafSBenjamin Herrenschmidt /* 519a1339fafSBenjamin Herrenschmidt * Setup init functions for M64 based on IODA version, IODA3 uses 520a1339fafSBenjamin Herrenschmidt * the IODA2 code. 521a1339fafSBenjamin Herrenschmidt */ 52299451551SGavin Shan if (phb->type == PNV_PHB_IODA1) 52399451551SGavin Shan phb->init_m64 = pnv_ioda1_init_m64; 52499451551SGavin Shan else 525262af557SGuo Chao phb->init_m64 = pnv_ioda2_init_m64; 526262af557SGuo Chao } 527262af557SGuo Chao 52849dec922SGavin Shan static void pnv_ioda_freeze_pe(struct pnv_phb *phb, int pe_no) 52949dec922SGavin Shan { 53049dec922SGavin Shan struct pnv_ioda_pe *pe = &phb->ioda.pe_array[pe_no]; 53149dec922SGavin Shan struct pnv_ioda_pe *slave; 53249dec922SGavin Shan s64 rc; 53349dec922SGavin Shan 53449dec922SGavin Shan /* Fetch master PE */ 53549dec922SGavin Shan if (pe->flags & PNV_IODA_PE_SLAVE) { 53649dec922SGavin Shan pe = pe->master; 537ec8e4e9dSGavin Shan if (WARN_ON(!pe || !(pe->flags & PNV_IODA_PE_MASTER))) 538ec8e4e9dSGavin Shan return; 539ec8e4e9dSGavin Shan 54049dec922SGavin Shan pe_no = pe->pe_number; 54149dec922SGavin Shan } 54249dec922SGavin Shan 54349dec922SGavin Shan /* Freeze master PE */ 54449dec922SGavin Shan rc = opal_pci_eeh_freeze_set(phb->opal_id, 54549dec922SGavin Shan pe_no, 54649dec922SGavin Shan OPAL_EEH_ACTION_SET_FREEZE_ALL); 54749dec922SGavin Shan if (rc != OPAL_SUCCESS) { 54849dec922SGavin Shan pr_warn("%s: Failure %lld freezing PHB#%x-PE#%x\n", 54949dec922SGavin Shan __func__, rc, phb->hose->global_number, pe_no); 55049dec922SGavin Shan return; 55149dec922SGavin Shan } 55249dec922SGavin Shan 55349dec922SGavin Shan /* Freeze slave PEs */ 55449dec922SGavin Shan if (!(pe->flags & PNV_IODA_PE_MASTER)) 55549dec922SGavin Shan return; 55649dec922SGavin Shan 55749dec922SGavin Shan list_for_each_entry(slave, &pe->slaves, list) { 55849dec922SGavin Shan rc = opal_pci_eeh_freeze_set(phb->opal_id, 55949dec922SGavin Shan slave->pe_number, 56049dec922SGavin Shan OPAL_EEH_ACTION_SET_FREEZE_ALL); 56149dec922SGavin Shan if (rc != OPAL_SUCCESS) 56249dec922SGavin Shan pr_warn("%s: Failure %lld freezing PHB#%x-PE#%x\n", 56349dec922SGavin Shan __func__, rc, phb->hose->global_number, 56449dec922SGavin Shan slave->pe_number); 56549dec922SGavin Shan } 56649dec922SGavin Shan } 56749dec922SGavin Shan 568e51df2c1SAnton Blanchard static int pnv_ioda_unfreeze_pe(struct pnv_phb *phb, int pe_no, int opt) 56949dec922SGavin Shan { 57049dec922SGavin Shan struct pnv_ioda_pe *pe, *slave; 57149dec922SGavin Shan s64 rc; 57249dec922SGavin Shan 57349dec922SGavin Shan /* Find master PE */ 57449dec922SGavin Shan pe = &phb->ioda.pe_array[pe_no]; 57549dec922SGavin Shan if (pe->flags & PNV_IODA_PE_SLAVE) { 57649dec922SGavin Shan pe = pe->master; 57749dec922SGavin Shan WARN_ON(!pe || !(pe->flags & PNV_IODA_PE_MASTER)); 57849dec922SGavin Shan pe_no = pe->pe_number; 57949dec922SGavin Shan } 58049dec922SGavin Shan 58149dec922SGavin Shan /* Clear frozen state for master PE */ 58249dec922SGavin Shan rc = opal_pci_eeh_freeze_clear(phb->opal_id, pe_no, opt); 58349dec922SGavin Shan if (rc != OPAL_SUCCESS) { 58449dec922SGavin Shan pr_warn("%s: Failure %lld clear %d on PHB#%x-PE#%x\n", 58549dec922SGavin Shan __func__, rc, opt, phb->hose->global_number, pe_no); 58649dec922SGavin Shan return -EIO; 58749dec922SGavin Shan } 58849dec922SGavin Shan 58949dec922SGavin Shan if (!(pe->flags & PNV_IODA_PE_MASTER)) 59049dec922SGavin Shan return 0; 59149dec922SGavin Shan 59249dec922SGavin Shan /* Clear frozen state for slave PEs */ 59349dec922SGavin Shan list_for_each_entry(slave, &pe->slaves, list) { 59449dec922SGavin Shan rc = opal_pci_eeh_freeze_clear(phb->opal_id, 59549dec922SGavin Shan slave->pe_number, 59649dec922SGavin Shan opt); 59749dec922SGavin Shan if (rc != OPAL_SUCCESS) { 59849dec922SGavin Shan pr_warn("%s: Failure %lld clear %d on PHB#%x-PE#%x\n", 59949dec922SGavin Shan __func__, rc, opt, phb->hose->global_number, 60049dec922SGavin Shan slave->pe_number); 60149dec922SGavin Shan return -EIO; 60249dec922SGavin Shan } 60349dec922SGavin Shan } 60449dec922SGavin Shan 60549dec922SGavin Shan return 0; 60649dec922SGavin Shan } 60749dec922SGavin Shan 60849dec922SGavin Shan static int pnv_ioda_get_pe_state(struct pnv_phb *phb, int pe_no) 60949dec922SGavin Shan { 61049dec922SGavin Shan struct pnv_ioda_pe *slave, *pe; 611c2057701SAlexey Kardashevskiy u8 fstate = 0, state; 612c2057701SAlexey Kardashevskiy __be16 pcierr = 0; 61349dec922SGavin Shan s64 rc; 61449dec922SGavin Shan 61549dec922SGavin Shan /* Sanity check on PE number */ 61692b8f137SGavin Shan if (pe_no < 0 || pe_no >= phb->ioda.total_pe_num) 61749dec922SGavin Shan return OPAL_EEH_STOPPED_PERM_UNAVAIL; 61849dec922SGavin Shan 61949dec922SGavin Shan /* 62049dec922SGavin Shan * Fetch the master PE and the PE instance might be 62149dec922SGavin Shan * not initialized yet. 62249dec922SGavin Shan */ 62349dec922SGavin Shan pe = &phb->ioda.pe_array[pe_no]; 62449dec922SGavin Shan if (pe->flags & PNV_IODA_PE_SLAVE) { 62549dec922SGavin Shan pe = pe->master; 62649dec922SGavin Shan WARN_ON(!pe || !(pe->flags & PNV_IODA_PE_MASTER)); 62749dec922SGavin Shan pe_no = pe->pe_number; 62849dec922SGavin Shan } 62949dec922SGavin Shan 63049dec922SGavin Shan /* Check the master PE */ 63149dec922SGavin Shan rc = opal_pci_eeh_freeze_status(phb->opal_id, pe_no, 63249dec922SGavin Shan &state, &pcierr, NULL); 63349dec922SGavin Shan if (rc != OPAL_SUCCESS) { 63449dec922SGavin Shan pr_warn("%s: Failure %lld getting " 63549dec922SGavin Shan "PHB#%x-PE#%x state\n", 63649dec922SGavin Shan __func__, rc, 63749dec922SGavin Shan phb->hose->global_number, pe_no); 63849dec922SGavin Shan return OPAL_EEH_STOPPED_TEMP_UNAVAIL; 63949dec922SGavin Shan } 64049dec922SGavin Shan 64149dec922SGavin Shan /* Check the slave PE */ 64249dec922SGavin Shan if (!(pe->flags & PNV_IODA_PE_MASTER)) 64349dec922SGavin Shan return state; 64449dec922SGavin Shan 64549dec922SGavin Shan list_for_each_entry(slave, &pe->slaves, list) { 64649dec922SGavin Shan rc = opal_pci_eeh_freeze_status(phb->opal_id, 64749dec922SGavin Shan slave->pe_number, 64849dec922SGavin Shan &fstate, 64949dec922SGavin Shan &pcierr, 65049dec922SGavin Shan NULL); 65149dec922SGavin Shan if (rc != OPAL_SUCCESS) { 65249dec922SGavin Shan pr_warn("%s: Failure %lld getting " 65349dec922SGavin Shan "PHB#%x-PE#%x state\n", 65449dec922SGavin Shan __func__, rc, 65549dec922SGavin Shan phb->hose->global_number, slave->pe_number); 65649dec922SGavin Shan return OPAL_EEH_STOPPED_TEMP_UNAVAIL; 65749dec922SGavin Shan } 65849dec922SGavin Shan 65949dec922SGavin Shan /* 66049dec922SGavin Shan * Override the result based on the ascending 66149dec922SGavin Shan * priority. 66249dec922SGavin Shan */ 66349dec922SGavin Shan if (fstate > state) 66449dec922SGavin Shan state = fstate; 66549dec922SGavin Shan } 66649dec922SGavin Shan 66749dec922SGavin Shan return state; 66849dec922SGavin Shan } 66949dec922SGavin Shan 670a8d7d5fcSOliver O'Halloran struct pnv_ioda_pe *pnv_pci_bdfn_to_pe(struct pnv_phb *phb, u16 bdfn) 671a8d7d5fcSOliver O'Halloran { 672a8d7d5fcSOliver O'Halloran int pe_number = phb->ioda.pe_rmap[bdfn]; 673a8d7d5fcSOliver O'Halloran 674a8d7d5fcSOliver O'Halloran if (pe_number == IODA_INVALID_PE) 675a8d7d5fcSOliver O'Halloran return NULL; 676a8d7d5fcSOliver O'Halloran 677a8d7d5fcSOliver O'Halloran return &phb->ioda.pe_array[pe_number]; 678a8d7d5fcSOliver O'Halloran } 679a8d7d5fcSOliver O'Halloran 680f456834aSIan Munsie struct pnv_ioda_pe *pnv_ioda_get_pe(struct pci_dev *dev) 681184cd4a3SBenjamin Herrenschmidt { 6825609ffddSOliver O'Halloran struct pnv_phb *phb = pci_bus_to_pnvhb(dev->bus); 683b72c1f65SBenjamin Herrenschmidt struct pci_dn *pdn = pci_get_pdn(dev); 684184cd4a3SBenjamin Herrenschmidt 685184cd4a3SBenjamin Herrenschmidt if (!pdn) 686184cd4a3SBenjamin Herrenschmidt return NULL; 687184cd4a3SBenjamin Herrenschmidt if (pdn->pe_number == IODA_INVALID_PE) 688184cd4a3SBenjamin Herrenschmidt return NULL; 689184cd4a3SBenjamin Herrenschmidt return &phb->ioda.pe_array[pdn->pe_number]; 690184cd4a3SBenjamin Herrenschmidt } 691184cd4a3SBenjamin Herrenschmidt 692b131a842SGavin Shan static int pnv_ioda_set_one_peltv(struct pnv_phb *phb, 693b131a842SGavin Shan struct pnv_ioda_pe *parent, 694b131a842SGavin Shan struct pnv_ioda_pe *child, 695b131a842SGavin Shan bool is_add) 696b131a842SGavin Shan { 697b131a842SGavin Shan const char *desc = is_add ? "adding" : "removing"; 698b131a842SGavin Shan uint8_t op = is_add ? OPAL_ADD_PE_TO_DOMAIN : 699b131a842SGavin Shan OPAL_REMOVE_PE_FROM_DOMAIN; 700b131a842SGavin Shan struct pnv_ioda_pe *slave; 701b131a842SGavin Shan long rc; 702b131a842SGavin Shan 703b131a842SGavin Shan /* Parent PE affects child PE */ 704b131a842SGavin Shan rc = opal_pci_set_peltv(phb->opal_id, parent->pe_number, 705b131a842SGavin Shan child->pe_number, op); 706b131a842SGavin Shan if (rc != OPAL_SUCCESS) { 707b131a842SGavin Shan pe_warn(child, "OPAL error %ld %s to parent PELTV\n", 708b131a842SGavin Shan rc, desc); 709b131a842SGavin Shan return -ENXIO; 710b131a842SGavin Shan } 711b131a842SGavin Shan 712b131a842SGavin Shan if (!(child->flags & PNV_IODA_PE_MASTER)) 713b131a842SGavin Shan return 0; 714b131a842SGavin Shan 715b131a842SGavin Shan /* Compound case: parent PE affects slave PEs */ 716b131a842SGavin Shan list_for_each_entry(slave, &child->slaves, list) { 717b131a842SGavin Shan rc = opal_pci_set_peltv(phb->opal_id, parent->pe_number, 718b131a842SGavin Shan slave->pe_number, op); 719b131a842SGavin Shan if (rc != OPAL_SUCCESS) { 720b131a842SGavin Shan pe_warn(slave, "OPAL error %ld %s to parent PELTV\n", 721b131a842SGavin Shan rc, desc); 722b131a842SGavin Shan return -ENXIO; 723b131a842SGavin Shan } 724b131a842SGavin Shan } 725b131a842SGavin Shan 726b131a842SGavin Shan return 0; 727b131a842SGavin Shan } 728b131a842SGavin Shan 729b131a842SGavin Shan static int pnv_ioda_set_peltv(struct pnv_phb *phb, 730b131a842SGavin Shan struct pnv_ioda_pe *pe, 731b131a842SGavin Shan bool is_add) 732b131a842SGavin Shan { 733b131a842SGavin Shan struct pnv_ioda_pe *slave; 734781a868fSWei Yang struct pci_dev *pdev = NULL; 735b131a842SGavin Shan int ret; 736b131a842SGavin Shan 737b131a842SGavin Shan /* 738b131a842SGavin Shan * Clear PE frozen state. If it's master PE, we need 739b131a842SGavin Shan * clear slave PE frozen state as well. 740b131a842SGavin Shan */ 741b131a842SGavin Shan if (is_add) { 742b131a842SGavin Shan opal_pci_eeh_freeze_clear(phb->opal_id, pe->pe_number, 743b131a842SGavin Shan OPAL_EEH_ACTION_CLEAR_FREEZE_ALL); 744b131a842SGavin Shan if (pe->flags & PNV_IODA_PE_MASTER) { 745b131a842SGavin Shan list_for_each_entry(slave, &pe->slaves, list) 746b131a842SGavin Shan opal_pci_eeh_freeze_clear(phb->opal_id, 747b131a842SGavin Shan slave->pe_number, 748b131a842SGavin Shan OPAL_EEH_ACTION_CLEAR_FREEZE_ALL); 749b131a842SGavin Shan } 750b131a842SGavin Shan } 751b131a842SGavin Shan 752b131a842SGavin Shan /* 753b131a842SGavin Shan * Associate PE in PELT. We need add the PE into the 754b131a842SGavin Shan * corresponding PELT-V as well. Otherwise, the error 755b131a842SGavin Shan * originated from the PE might contribute to other 756b131a842SGavin Shan * PEs. 757b131a842SGavin Shan */ 758b131a842SGavin Shan ret = pnv_ioda_set_one_peltv(phb, pe, pe, is_add); 759b131a842SGavin Shan if (ret) 760b131a842SGavin Shan return ret; 761b131a842SGavin Shan 762b131a842SGavin Shan /* For compound PEs, any one affects all of them */ 763b131a842SGavin Shan if (pe->flags & PNV_IODA_PE_MASTER) { 764b131a842SGavin Shan list_for_each_entry(slave, &pe->slaves, list) { 765b131a842SGavin Shan ret = pnv_ioda_set_one_peltv(phb, slave, pe, is_add); 766b131a842SGavin Shan if (ret) 767b131a842SGavin Shan return ret; 768b131a842SGavin Shan } 769b131a842SGavin Shan } 770b131a842SGavin Shan 771b131a842SGavin Shan if (pe->flags & (PNV_IODA_PE_BUS_ALL | PNV_IODA_PE_BUS)) 772b131a842SGavin Shan pdev = pe->pbus->self; 773781a868fSWei Yang else if (pe->flags & PNV_IODA_PE_DEV) 774b131a842SGavin Shan pdev = pe->pdev->bus->self; 775781a868fSWei Yang #ifdef CONFIG_PCI_IOV 776781a868fSWei Yang else if (pe->flags & PNV_IODA_PE_VF) 777283e2d8aSGavin Shan pdev = pe->parent_dev; 778781a868fSWei Yang #endif /* CONFIG_PCI_IOV */ 779b131a842SGavin Shan while (pdev) { 780b131a842SGavin Shan struct pci_dn *pdn = pci_get_pdn(pdev); 781b131a842SGavin Shan struct pnv_ioda_pe *parent; 782b131a842SGavin Shan 783b131a842SGavin Shan if (pdn && pdn->pe_number != IODA_INVALID_PE) { 784b131a842SGavin Shan parent = &phb->ioda.pe_array[pdn->pe_number]; 785b131a842SGavin Shan ret = pnv_ioda_set_one_peltv(phb, parent, pe, is_add); 786b131a842SGavin Shan if (ret) 787b131a842SGavin Shan return ret; 788b131a842SGavin Shan } 789b131a842SGavin Shan 790b131a842SGavin Shan pdev = pdev->bus->self; 791b131a842SGavin Shan } 792b131a842SGavin Shan 793b131a842SGavin Shan return 0; 794b131a842SGavin Shan } 795b131a842SGavin Shan 796f724385fSFrederic Barrat static void pnv_ioda_unset_peltv(struct pnv_phb *phb, 797f724385fSFrederic Barrat struct pnv_ioda_pe *pe, 798f724385fSFrederic Barrat struct pci_dev *parent) 799f724385fSFrederic Barrat { 800f724385fSFrederic Barrat int64_t rc; 801f724385fSFrederic Barrat 802f724385fSFrederic Barrat while (parent) { 803f724385fSFrederic Barrat struct pci_dn *pdn = pci_get_pdn(parent); 804f724385fSFrederic Barrat 805f724385fSFrederic Barrat if (pdn && pdn->pe_number != IODA_INVALID_PE) { 806f724385fSFrederic Barrat rc = opal_pci_set_peltv(phb->opal_id, pdn->pe_number, 807f724385fSFrederic Barrat pe->pe_number, 808f724385fSFrederic Barrat OPAL_REMOVE_PE_FROM_DOMAIN); 809f724385fSFrederic Barrat /* XXX What to do in case of error ? */ 810f724385fSFrederic Barrat } 811f724385fSFrederic Barrat parent = parent->bus->self; 812f724385fSFrederic Barrat } 813f724385fSFrederic Barrat 814f724385fSFrederic Barrat opal_pci_eeh_freeze_clear(phb->opal_id, pe->pe_number, 815f724385fSFrederic Barrat OPAL_EEH_ACTION_CLEAR_FREEZE_ALL); 816f724385fSFrederic Barrat 817f724385fSFrederic Barrat /* Disassociate PE in PELT */ 818f724385fSFrederic Barrat rc = opal_pci_set_peltv(phb->opal_id, pe->pe_number, 819f724385fSFrederic Barrat pe->pe_number, OPAL_REMOVE_PE_FROM_DOMAIN); 820f724385fSFrederic Barrat if (rc) 821f724385fSFrederic Barrat pe_warn(pe, "OPAL error %lld remove self from PELTV\n", rc); 822f724385fSFrederic Barrat } 823f724385fSFrederic Barrat 82437b59ef0SOliver O'Halloran int pnv_ioda_deconfigure_pe(struct pnv_phb *phb, struct pnv_ioda_pe *pe) 825781a868fSWei Yang { 826781a868fSWei Yang struct pci_dev *parent; 827781a868fSWei Yang uint8_t bcomp, dcomp, fcomp; 828781a868fSWei Yang int64_t rc; 829781a868fSWei Yang long rid_end, rid; 830781a868fSWei Yang 831781a868fSWei Yang /* Currently, we just deconfigure VF PE. Bus PE will always there.*/ 832781a868fSWei Yang if (pe->pbus) { 833781a868fSWei Yang int count; 834781a868fSWei Yang 835781a868fSWei Yang dcomp = OPAL_IGNORE_RID_DEVICE_NUMBER; 836781a868fSWei Yang fcomp = OPAL_IGNORE_RID_FUNCTION_NUMBER; 837781a868fSWei Yang parent = pe->pbus->self; 838781a868fSWei Yang if (pe->flags & PNV_IODA_PE_BUS_ALL) 839552aa086SJulia Lawall count = resource_size(&pe->pbus->busn_res); 840781a868fSWei Yang else 841781a868fSWei Yang count = 1; 842781a868fSWei Yang 843781a868fSWei Yang switch(count) { 844781a868fSWei Yang case 1: bcomp = OpalPciBusAll; break; 845781a868fSWei Yang case 2: bcomp = OpalPciBus7Bits; break; 846781a868fSWei Yang case 4: bcomp = OpalPciBus6Bits; break; 847781a868fSWei Yang case 8: bcomp = OpalPciBus5Bits; break; 848781a868fSWei Yang case 16: bcomp = OpalPciBus4Bits; break; 849781a868fSWei Yang case 32: bcomp = OpalPciBus3Bits; break; 850781a868fSWei Yang default: 851781a868fSWei Yang dev_err(&pe->pbus->dev, "Number of subordinate buses %d unsupported\n", 852781a868fSWei Yang count); 853781a868fSWei Yang /* Do an exact match only */ 854781a868fSWei Yang bcomp = OpalPciBusAll; 855781a868fSWei Yang } 856781a868fSWei Yang rid_end = pe->rid + (count << 8); 857781a868fSWei Yang } else { 85893e01a50SGavin Shan #ifdef CONFIG_PCI_IOV 859781a868fSWei Yang if (pe->flags & PNV_IODA_PE_VF) 860781a868fSWei Yang parent = pe->parent_dev; 861781a868fSWei Yang else 86293e01a50SGavin Shan #endif 863781a868fSWei Yang parent = pe->pdev->bus->self; 864781a868fSWei Yang bcomp = OpalPciBusAll; 865781a868fSWei Yang dcomp = OPAL_COMPARE_RID_DEVICE_NUMBER; 866781a868fSWei Yang fcomp = OPAL_COMPARE_RID_FUNCTION_NUMBER; 867781a868fSWei Yang rid_end = pe->rid + 1; 868781a868fSWei Yang } 869781a868fSWei Yang 870781a868fSWei Yang /* Clear the reverse map */ 871781a868fSWei Yang for (rid = pe->rid; rid < rid_end; rid++) 872c127562aSGavin Shan phb->ioda.pe_rmap[rid] = IODA_INVALID_PE; 873781a868fSWei Yang 874f724385fSFrederic Barrat /* 875f724385fSFrederic Barrat * Release from all parents PELT-V. NPUs don't have a PELTV 876f724385fSFrederic Barrat * table 877f724385fSFrederic Barrat */ 878f724385fSFrederic Barrat if (phb->type != PNV_PHB_NPU_NVLINK && phb->type != PNV_PHB_NPU_OCAPI) 879f724385fSFrederic Barrat pnv_ioda_unset_peltv(phb, pe, parent); 880781a868fSWei Yang 881781a868fSWei Yang rc = opal_pci_set_pe(phb->opal_id, pe->pe_number, pe->rid, 882781a868fSWei Yang bcomp, dcomp, fcomp, OPAL_UNMAP_PE); 883781a868fSWei Yang if (rc) 8841e496391SJoe Perches pe_err(pe, "OPAL error %lld trying to setup PELT table\n", rc); 885781a868fSWei Yang 886781a868fSWei Yang pe->pbus = NULL; 887781a868fSWei Yang pe->pdev = NULL; 88893e01a50SGavin Shan #ifdef CONFIG_PCI_IOV 889781a868fSWei Yang pe->parent_dev = NULL; 89093e01a50SGavin Shan #endif 891781a868fSWei Yang 892781a868fSWei Yang return 0; 893781a868fSWei Yang } 894781a868fSWei Yang 89537b59ef0SOliver O'Halloran int pnv_ioda_configure_pe(struct pnv_phb *phb, struct pnv_ioda_pe *pe) 896184cd4a3SBenjamin Herrenschmidt { 897184cd4a3SBenjamin Herrenschmidt struct pci_dev *parent; 898184cd4a3SBenjamin Herrenschmidt uint8_t bcomp, dcomp, fcomp; 899184cd4a3SBenjamin Herrenschmidt long rc, rid_end, rid; 900184cd4a3SBenjamin Herrenschmidt 901184cd4a3SBenjamin Herrenschmidt /* Bus validation ? */ 902184cd4a3SBenjamin Herrenschmidt if (pe->pbus) { 903184cd4a3SBenjamin Herrenschmidt int count; 904184cd4a3SBenjamin Herrenschmidt 905184cd4a3SBenjamin Herrenschmidt dcomp = OPAL_IGNORE_RID_DEVICE_NUMBER; 906184cd4a3SBenjamin Herrenschmidt fcomp = OPAL_IGNORE_RID_FUNCTION_NUMBER; 907184cd4a3SBenjamin Herrenschmidt parent = pe->pbus->self; 908fb446ad0SGavin Shan if (pe->flags & PNV_IODA_PE_BUS_ALL) 909552aa086SJulia Lawall count = resource_size(&pe->pbus->busn_res); 910fb446ad0SGavin Shan else 911fb446ad0SGavin Shan count = 1; 912fb446ad0SGavin Shan 913184cd4a3SBenjamin Herrenschmidt switch(count) { 914184cd4a3SBenjamin Herrenschmidt case 1: bcomp = OpalPciBusAll; break; 915184cd4a3SBenjamin Herrenschmidt case 2: bcomp = OpalPciBus7Bits; break; 916184cd4a3SBenjamin Herrenschmidt case 4: bcomp = OpalPciBus6Bits; break; 917184cd4a3SBenjamin Herrenschmidt case 8: bcomp = OpalPciBus5Bits; break; 918184cd4a3SBenjamin Herrenschmidt case 16: bcomp = OpalPciBus4Bits; break; 919184cd4a3SBenjamin Herrenschmidt case 32: bcomp = OpalPciBus3Bits; break; 920184cd4a3SBenjamin Herrenschmidt default: 921781a868fSWei Yang dev_err(&pe->pbus->dev, "Number of subordinate buses %d unsupported\n", 922781a868fSWei Yang count); 923184cd4a3SBenjamin Herrenschmidt /* Do an exact match only */ 924184cd4a3SBenjamin Herrenschmidt bcomp = OpalPciBusAll; 925184cd4a3SBenjamin Herrenschmidt } 926184cd4a3SBenjamin Herrenschmidt rid_end = pe->rid + (count << 8); 927184cd4a3SBenjamin Herrenschmidt } else { 928781a868fSWei Yang #ifdef CONFIG_PCI_IOV 929781a868fSWei Yang if (pe->flags & PNV_IODA_PE_VF) 930781a868fSWei Yang parent = pe->parent_dev; 931781a868fSWei Yang else 932781a868fSWei Yang #endif /* CONFIG_PCI_IOV */ 933184cd4a3SBenjamin Herrenschmidt parent = pe->pdev->bus->self; 934184cd4a3SBenjamin Herrenschmidt bcomp = OpalPciBusAll; 935184cd4a3SBenjamin Herrenschmidt dcomp = OPAL_COMPARE_RID_DEVICE_NUMBER; 936184cd4a3SBenjamin Herrenschmidt fcomp = OPAL_COMPARE_RID_FUNCTION_NUMBER; 937184cd4a3SBenjamin Herrenschmidt rid_end = pe->rid + 1; 938184cd4a3SBenjamin Herrenschmidt } 939184cd4a3SBenjamin Herrenschmidt 940631ad691SGavin Shan /* 941631ad691SGavin Shan * Associate PE in PELT. We need add the PE into the 942631ad691SGavin Shan * corresponding PELT-V as well. Otherwise, the error 943631ad691SGavin Shan * originated from the PE might contribute to other 944631ad691SGavin Shan * PEs. 945631ad691SGavin Shan */ 946184cd4a3SBenjamin Herrenschmidt rc = opal_pci_set_pe(phb->opal_id, pe->pe_number, pe->rid, 947184cd4a3SBenjamin Herrenschmidt bcomp, dcomp, fcomp, OPAL_MAP_PE); 948184cd4a3SBenjamin Herrenschmidt if (rc) { 949184cd4a3SBenjamin Herrenschmidt pe_err(pe, "OPAL error %ld trying to setup PELT table\n", rc); 950184cd4a3SBenjamin Herrenschmidt return -ENXIO; 951184cd4a3SBenjamin Herrenschmidt } 952631ad691SGavin Shan 9535d2aa710SAlistair Popple /* 9545d2aa710SAlistair Popple * Configure PELTV. NPUs don't have a PELTV table so skip 9555d2aa710SAlistair Popple * configuration on them. 9565d2aa710SAlistair Popple */ 9577f2c39e9SFrederic Barrat if (phb->type != PNV_PHB_NPU_NVLINK && phb->type != PNV_PHB_NPU_OCAPI) 958b131a842SGavin Shan pnv_ioda_set_peltv(phb, pe, true); 959184cd4a3SBenjamin Herrenschmidt 960184cd4a3SBenjamin Herrenschmidt /* Setup reverse map */ 961184cd4a3SBenjamin Herrenschmidt for (rid = pe->rid; rid < rid_end; rid++) 962184cd4a3SBenjamin Herrenschmidt phb->ioda.pe_rmap[rid] = pe->pe_number; 963184cd4a3SBenjamin Herrenschmidt 964184cd4a3SBenjamin Herrenschmidt /* Setup one MVTs on IODA1 */ 9654773f76bSGavin Shan if (phb->type != PNV_PHB_IODA1) { 9664773f76bSGavin Shan pe->mve_number = 0; 9674773f76bSGavin Shan goto out; 9684773f76bSGavin Shan } 9694773f76bSGavin Shan 970184cd4a3SBenjamin Herrenschmidt pe->mve_number = pe->pe_number; 9714773f76bSGavin Shan rc = opal_pci_set_mve(phb->opal_id, pe->mve_number, pe->pe_number); 9724773f76bSGavin Shan if (rc != OPAL_SUCCESS) { 9731f52f176SRussell Currey pe_err(pe, "OPAL error %ld setting up MVE %x\n", 974184cd4a3SBenjamin Herrenschmidt rc, pe->mve_number); 975184cd4a3SBenjamin Herrenschmidt pe->mve_number = -1; 976184cd4a3SBenjamin Herrenschmidt } else { 977184cd4a3SBenjamin Herrenschmidt rc = opal_pci_set_mve_enable(phb->opal_id, 978cee72d5bSBenjamin Herrenschmidt pe->mve_number, OPAL_ENABLE_MVE); 979184cd4a3SBenjamin Herrenschmidt if (rc) { 9801f52f176SRussell Currey pe_err(pe, "OPAL error %ld enabling MVE %x\n", 981184cd4a3SBenjamin Herrenschmidt rc, pe->mve_number); 982184cd4a3SBenjamin Herrenschmidt pe->mve_number = -1; 983184cd4a3SBenjamin Herrenschmidt } 984184cd4a3SBenjamin Herrenschmidt } 985184cd4a3SBenjamin Herrenschmidt 9864773f76bSGavin Shan out: 987184cd4a3SBenjamin Herrenschmidt return 0; 988184cd4a3SBenjamin Herrenschmidt } 989184cd4a3SBenjamin Herrenschmidt 990cad5cef6SGreg Kroah-Hartman static struct pnv_ioda_pe *pnv_ioda_setup_dev_PE(struct pci_dev *dev) 991184cd4a3SBenjamin Herrenschmidt { 9925609ffddSOliver O'Halloran struct pnv_phb *phb = pci_bus_to_pnvhb(dev->bus); 993b72c1f65SBenjamin Herrenschmidt struct pci_dn *pdn = pci_get_pdn(dev); 994184cd4a3SBenjamin Herrenschmidt struct pnv_ioda_pe *pe; 995184cd4a3SBenjamin Herrenschmidt 996184cd4a3SBenjamin Herrenschmidt if (!pdn) { 997184cd4a3SBenjamin Herrenschmidt pr_err("%s: Device tree node not associated properly\n", 998184cd4a3SBenjamin Herrenschmidt pci_name(dev)); 999184cd4a3SBenjamin Herrenschmidt return NULL; 1000184cd4a3SBenjamin Herrenschmidt } 1001184cd4a3SBenjamin Herrenschmidt if (pdn->pe_number != IODA_INVALID_PE) 1002184cd4a3SBenjamin Herrenschmidt return NULL; 1003184cd4a3SBenjamin Herrenschmidt 1004a4bc676eSOliver O'Halloran pe = pnv_ioda_alloc_pe(phb, 1); 10051e916772SGavin Shan if (!pe) { 1006f2c2cbccSJoe Perches pr_warn("%s: Not enough PE# available, disabling device\n", 1007184cd4a3SBenjamin Herrenschmidt pci_name(dev)); 1008184cd4a3SBenjamin Herrenschmidt return NULL; 1009184cd4a3SBenjamin Herrenschmidt } 1010184cd4a3SBenjamin Herrenschmidt 101105dd7da7SFrederic Barrat /* NOTE: We don't get a reference for the pointer in the PE 101205dd7da7SFrederic Barrat * data structure, both the device and PE structures should be 101305dd7da7SFrederic Barrat * destroyed at the same time. However, removing nvlink 101405dd7da7SFrederic Barrat * devices will need some work. 1015184cd4a3SBenjamin Herrenschmidt * 1016184cd4a3SBenjamin Herrenschmidt * At some point we want to remove the PDN completely anyways 1017184cd4a3SBenjamin Herrenschmidt */ 10181e916772SGavin Shan pdn->pe_number = pe->pe_number; 10195d2aa710SAlistair Popple pe->flags = PNV_IODA_PE_DEV; 1020184cd4a3SBenjamin Herrenschmidt pe->pdev = dev; 1021184cd4a3SBenjamin Herrenschmidt pe->pbus = NULL; 1022184cd4a3SBenjamin Herrenschmidt pe->mve_number = -1; 1023184cd4a3SBenjamin Herrenschmidt pe->rid = dev->bus->number << 8 | pdn->devfn; 1024f724385fSFrederic Barrat pe->device_count++; 1025184cd4a3SBenjamin Herrenschmidt 1026184cd4a3SBenjamin Herrenschmidt pe_info(pe, "Associated device to PE\n"); 1027184cd4a3SBenjamin Herrenschmidt 1028184cd4a3SBenjamin Herrenschmidt if (pnv_ioda_configure_pe(phb, pe)) { 1029184cd4a3SBenjamin Herrenschmidt /* XXX What do we do here ? */ 10301e916772SGavin Shan pnv_ioda_free_pe(pe); 1031184cd4a3SBenjamin Herrenschmidt pdn->pe_number = IODA_INVALID_PE; 1032184cd4a3SBenjamin Herrenschmidt pe->pdev = NULL; 1033184cd4a3SBenjamin Herrenschmidt return NULL; 1034184cd4a3SBenjamin Herrenschmidt } 1035184cd4a3SBenjamin Herrenschmidt 10361d4e89cfSAlexey Kardashevskiy /* Put PE to the list */ 103780f1ff83SFrederic Barrat mutex_lock(&phb->ioda.pe_list_mutex); 10381d4e89cfSAlexey Kardashevskiy list_add_tail(&pe->list, &phb->ioda.pe_list); 103980f1ff83SFrederic Barrat mutex_unlock(&phb->ioda.pe_list_mutex); 1040184cd4a3SBenjamin Herrenschmidt return pe; 1041184cd4a3SBenjamin Herrenschmidt } 1042184cd4a3SBenjamin Herrenschmidt 1043fb446ad0SGavin Shan /* 1044fb446ad0SGavin Shan * There're 2 types of PCI bus sensitive PEs: One that is compromised of 1045fb446ad0SGavin Shan * single PCI bus. Another one that contains the primary PCI bus and its 1046fb446ad0SGavin Shan * subordinate PCI devices and buses. The second type of PE is normally 1047fb446ad0SGavin Shan * orgiriated by PCIe-to-PCI bridge or PLX switch downstream ports. 1048fb446ad0SGavin Shan */ 10491e916772SGavin Shan static struct pnv_ioda_pe *pnv_ioda_setup_bus_PE(struct pci_bus *bus, bool all) 1050184cd4a3SBenjamin Herrenschmidt { 10515609ffddSOliver O'Halloran struct pnv_phb *phb = pci_bus_to_pnvhb(bus); 10521e916772SGavin Shan struct pnv_ioda_pe *pe = NULL; 1053ccd1c191SGavin Shan unsigned int pe_num; 1054ccd1c191SGavin Shan 1055ccd1c191SGavin Shan /* 1056ccd1c191SGavin Shan * In partial hotplug case, the PE instance might be still alive. 1057ccd1c191SGavin Shan * We should reuse it instead of allocating a new one. 1058ccd1c191SGavin Shan */ 1059ccd1c191SGavin Shan pe_num = phb->ioda.pe_rmap[bus->number << 8]; 10606ae8aedfSOliver O'Halloran if (WARN_ON(pe_num != IODA_INVALID_PE)) { 1061ccd1c191SGavin Shan pe = &phb->ioda.pe_array[pe_num]; 1062ccd1c191SGavin Shan return NULL; 1063ccd1c191SGavin Shan } 1064184cd4a3SBenjamin Herrenschmidt 106563803c39SGavin Shan /* PE number for root bus should have been reserved */ 1066718d249aSOliver O'Halloran if (pci_is_root_bus(bus)) 106763803c39SGavin Shan pe = &phb->ioda.pe_array[phb->ioda.root_pe_idx]; 106863803c39SGavin Shan 1069262af557SGuo Chao /* Check if PE is determined by M64 */ 1070a25de7afSAlexey Kardashevskiy if (!pe) 1071a25de7afSAlexey Kardashevskiy pe = pnv_ioda_pick_m64_pe(bus, all); 1072262af557SGuo Chao 1073262af557SGuo Chao /* The PE number isn't pinned by M64 */ 10741e916772SGavin Shan if (!pe) 1075a4bc676eSOliver O'Halloran pe = pnv_ioda_alloc_pe(phb, 1); 1076262af557SGuo Chao 10771e916772SGavin Shan if (!pe) { 1078f2c2cbccSJoe Perches pr_warn("%s: Not enough PE# available for PCI bus %04x:%02x\n", 1079fb446ad0SGavin Shan __func__, pci_domain_nr(bus), bus->number); 10801e916772SGavin Shan return NULL; 1081184cd4a3SBenjamin Herrenschmidt } 1082184cd4a3SBenjamin Herrenschmidt 1083262af557SGuo Chao pe->flags |= (all ? PNV_IODA_PE_BUS_ALL : PNV_IODA_PE_BUS); 1084184cd4a3SBenjamin Herrenschmidt pe->pbus = bus; 1085184cd4a3SBenjamin Herrenschmidt pe->pdev = NULL; 1086184cd4a3SBenjamin Herrenschmidt pe->mve_number = -1; 1087b918c62eSYinghai Lu pe->rid = bus->busn_res.start << 8; 1088184cd4a3SBenjamin Herrenschmidt 1089fb446ad0SGavin Shan if (all) 10901e496391SJoe Perches pe_info(pe, "Secondary bus %pad..%pad associated with PE#%x\n", 10911e496391SJoe Perches &bus->busn_res.start, &bus->busn_res.end, 10921e496391SJoe Perches pe->pe_number); 1093fb446ad0SGavin Shan else 10941e496391SJoe Perches pe_info(pe, "Secondary bus %pad associated with PE#%x\n", 10951e496391SJoe Perches &bus->busn_res.start, pe->pe_number); 1096184cd4a3SBenjamin Herrenschmidt 1097184cd4a3SBenjamin Herrenschmidt if (pnv_ioda_configure_pe(phb, pe)) { 1098184cd4a3SBenjamin Herrenschmidt /* XXX What do we do here ? */ 10991e916772SGavin Shan pnv_ioda_free_pe(pe); 1100184cd4a3SBenjamin Herrenschmidt pe->pbus = NULL; 11011e916772SGavin Shan return NULL; 1102184cd4a3SBenjamin Herrenschmidt } 1103184cd4a3SBenjamin Herrenschmidt 11047ebdf956SGavin Shan /* Put PE to the list */ 11057ebdf956SGavin Shan list_add_tail(&pe->list, &phb->ioda.pe_list); 11061e916772SGavin Shan 11071e916772SGavin Shan return pe; 1108184cd4a3SBenjamin Herrenschmidt } 1109184cd4a3SBenjamin Herrenschmidt 1110b521549aSAlistair Popple static struct pnv_ioda_pe *pnv_ioda_setup_npu_PE(struct pci_dev *npu_pdev) 11115d2aa710SAlistair Popple { 1112b521549aSAlistair Popple int pe_num, found_pe = false, rc; 1113b521549aSAlistair Popple long rid; 1114b521549aSAlistair Popple struct pnv_ioda_pe *pe; 1115b521549aSAlistair Popple struct pci_dev *gpu_pdev; 1116b521549aSAlistair Popple struct pci_dn *npu_pdn; 11175609ffddSOliver O'Halloran struct pnv_phb *phb = pci_bus_to_pnvhb(npu_pdev->bus); 1118b521549aSAlistair Popple 1119b521549aSAlistair Popple /* 112005dd7da7SFrederic Barrat * Intentionally leak a reference on the npu device (for 112105dd7da7SFrederic Barrat * nvlink only; this is not an opencapi path) to make sure it 112205dd7da7SFrederic Barrat * never goes away, as it's been the case all along and some 112305dd7da7SFrederic Barrat * work is needed otherwise. 112405dd7da7SFrederic Barrat */ 112505dd7da7SFrederic Barrat pci_dev_get(npu_pdev); 112605dd7da7SFrederic Barrat 112705dd7da7SFrederic Barrat /* 1128b521549aSAlistair Popple * Due to a hardware errata PE#0 on the NPU is reserved for 1129b521549aSAlistair Popple * error handling. This means we only have three PEs remaining 1130b521549aSAlistair Popple * which need to be assigned to four links, implying some 1131b521549aSAlistair Popple * links must share PEs. 1132b521549aSAlistair Popple * 1133b521549aSAlistair Popple * To achieve this we assign PEs such that NPUs linking the 1134b521549aSAlistair Popple * same GPU get assigned the same PE. 1135b521549aSAlistair Popple */ 1136b521549aSAlistair Popple gpu_pdev = pnv_pci_get_gpu_dev(npu_pdev); 113792b8f137SGavin Shan for (pe_num = 0; pe_num < phb->ioda.total_pe_num; pe_num++) { 1138b521549aSAlistair Popple pe = &phb->ioda.pe_array[pe_num]; 1139b521549aSAlistair Popple if (!pe->pdev) 1140b521549aSAlistair Popple continue; 1141b521549aSAlistair Popple 1142b521549aSAlistair Popple if (pnv_pci_get_gpu_dev(pe->pdev) == gpu_pdev) { 1143b521549aSAlistair Popple /* 1144b521549aSAlistair Popple * This device has the same peer GPU so should 1145b521549aSAlistair Popple * be assigned the same PE as the existing 1146b521549aSAlistair Popple * peer NPU. 1147b521549aSAlistair Popple */ 1148b521549aSAlistair Popple dev_info(&npu_pdev->dev, 11491f52f176SRussell Currey "Associating to existing PE %x\n", pe_num); 1150b521549aSAlistair Popple npu_pdn = pci_get_pdn(npu_pdev); 1151b521549aSAlistair Popple rid = npu_pdev->bus->number << 8 | npu_pdn->devfn; 1152b521549aSAlistair Popple npu_pdn->pe_number = pe_num; 1153b521549aSAlistair Popple phb->ioda.pe_rmap[rid] = pe->pe_number; 1154f724385fSFrederic Barrat pe->device_count++; 1155b521549aSAlistair Popple 1156b521549aSAlistair Popple /* Map the PE to this link */ 1157b521549aSAlistair Popple rc = opal_pci_set_pe(phb->opal_id, pe_num, rid, 1158b521549aSAlistair Popple OpalPciBusAll, 1159b521549aSAlistair Popple OPAL_COMPARE_RID_DEVICE_NUMBER, 1160b521549aSAlistair Popple OPAL_COMPARE_RID_FUNCTION_NUMBER, 1161b521549aSAlistair Popple OPAL_MAP_PE); 1162b521549aSAlistair Popple WARN_ON(rc != OPAL_SUCCESS); 1163b521549aSAlistair Popple found_pe = true; 1164b521549aSAlistair Popple break; 1165b521549aSAlistair Popple } 1166b521549aSAlistair Popple } 1167b521549aSAlistair Popple 1168b521549aSAlistair Popple if (!found_pe) 1169b521549aSAlistair Popple /* 1170b521549aSAlistair Popple * Could not find an existing PE so allocate a new 1171b521549aSAlistair Popple * one. 1172b521549aSAlistair Popple */ 1173b521549aSAlistair Popple return pnv_ioda_setup_dev_PE(npu_pdev); 1174b521549aSAlistair Popple else 1175b521549aSAlistair Popple return pe; 1176b521549aSAlistair Popple } 1177b521549aSAlistair Popple 1178b521549aSAlistair Popple static void pnv_ioda_setup_npu_PEs(struct pci_bus *bus) 1179b521549aSAlistair Popple { 11805d2aa710SAlistair Popple struct pci_dev *pdev; 11815d2aa710SAlistair Popple 11825d2aa710SAlistair Popple list_for_each_entry(pdev, &bus->devices, bus_list) 1183b521549aSAlistair Popple pnv_ioda_setup_npu_PE(pdev); 11845d2aa710SAlistair Popple } 11855d2aa710SAlistair Popple 118603b7bf34SOliver O'Halloran static void pnv_pci_ioda_setup_nvlink(void) 1187fb446ad0SGavin Shan { 11880e759bd7SAlexey Kardashevskiy struct pci_controller *hose; 1189262af557SGuo Chao struct pnv_phb *phb; 11900e759bd7SAlexey Kardashevskiy struct pnv_ioda_pe *pe; 1191fb446ad0SGavin Shan 11920e759bd7SAlexey Kardashevskiy list_for_each_entry(hose, &hose_list, list_node) { 1193262af557SGuo Chao phb = hose->private_data; 11947f2c39e9SFrederic Barrat if (phb->type == PNV_PHB_NPU_NVLINK) { 119508f48f32SAlistair Popple /* PE#0 is needed for error reporting */ 119608f48f32SAlistair Popple pnv_ioda_reserve_pe(phb, 0); 1197b521549aSAlistair Popple pnv_ioda_setup_npu_PEs(hose->bus); 11981ab66d1fSAlistair Popple if (phb->model == PNV_PHB_MODEL_NPU2) 11990e759bd7SAlexey Kardashevskiy WARN_ON_ONCE(pnv_npu2_init(hose)); 1200ccd1c191SGavin Shan } 1201fb446ad0SGavin Shan } 12020e759bd7SAlexey Kardashevskiy list_for_each_entry(hose, &hose_list, list_node) { 12030e759bd7SAlexey Kardashevskiy phb = hose->private_data; 12040e759bd7SAlexey Kardashevskiy if (phb->type != PNV_PHB_IODA2) 12050e759bd7SAlexey Kardashevskiy continue; 12060e759bd7SAlexey Kardashevskiy 12070e759bd7SAlexey Kardashevskiy list_for_each_entry(pe, &phb->ioda.pe_list, list) 12080e759bd7SAlexey Kardashevskiy pnv_npu2_map_lpar(pe, MSR_DR | MSR_PR | MSR_HV); 12090e759bd7SAlexey Kardashevskiy } 121003b7bf34SOliver O'Halloran 121103b7bf34SOliver O'Halloran #ifdef CONFIG_IOMMU_API 121203b7bf34SOliver O'Halloran /* setup iommu groups so we can do nvlink pass-thru */ 121303b7bf34SOliver O'Halloran pnv_pci_npu_setup_iommu_groups(); 121403b7bf34SOliver O'Halloran #endif 1215fb446ad0SGavin Shan } 1216184cd4a3SBenjamin Herrenschmidt 121701e12629SOliver O'Halloran static void pnv_pci_ioda1_setup_dma_pe(struct pnv_phb *phb, 121801e12629SOliver O'Halloran struct pnv_ioda_pe *pe); 121901e12629SOliver O'Halloran 12200a25d9c4SOliver O'Halloran static void pnv_pci_ioda_dma_dev_setup(struct pci_dev *pdev) 1221184cd4a3SBenjamin Herrenschmidt { 12225609ffddSOliver O'Halloran struct pnv_phb *phb = pci_bus_to_pnvhb(pdev->bus); 1223b72c1f65SBenjamin Herrenschmidt struct pci_dn *pdn = pci_get_pdn(pdev); 1224959c9bddSGavin Shan struct pnv_ioda_pe *pe; 1225184cd4a3SBenjamin Herrenschmidt 1226dc3d8f85SOliver O'Halloran /* Check if the BDFN for this device is associated with a PE yet */ 1227dc3d8f85SOliver O'Halloran pe = pnv_pci_bdfn_to_pe(phb, pdev->devfn | (pdev->bus->number << 8)); 1228dc3d8f85SOliver O'Halloran if (!pe) { 1229dc3d8f85SOliver O'Halloran /* VF PEs should be pre-configured in pnv_pci_sriov_enable() */ 1230dc3d8f85SOliver O'Halloran if (WARN_ON(pdev->is_virtfn)) 1231959c9bddSGavin Shan return; 1232184cd4a3SBenjamin Herrenschmidt 1233dc3d8f85SOliver O'Halloran pnv_pci_configure_bus(pdev->bus); 1234dc3d8f85SOliver O'Halloran pe = pnv_pci_bdfn_to_pe(phb, pdev->devfn | (pdev->bus->number << 8)); 1235dc3d8f85SOliver O'Halloran pci_info(pdev, "Configured PE#%x\n", pe ? pe->pe_number : 0xfffff); 1236dc3d8f85SOliver O'Halloran 1237dc3d8f85SOliver O'Halloran 1238dc3d8f85SOliver O'Halloran /* 1239dc3d8f85SOliver O'Halloran * If we can't setup the IODA PE something has gone horribly 1240dc3d8f85SOliver O'Halloran * wrong and we can't enable DMA for the device. 1241dc3d8f85SOliver O'Halloran */ 1242dc3d8f85SOliver O'Halloran if (WARN_ON(!pe)) 1243dc3d8f85SOliver O'Halloran return; 1244dc3d8f85SOliver O'Halloran } else { 1245dc3d8f85SOliver O'Halloran pci_info(pdev, "Added to existing PE#%x\n", pe->pe_number); 1246dc3d8f85SOliver O'Halloran } 1247dc3d8f85SOliver O'Halloran 124801e12629SOliver O'Halloran /* 124901e12629SOliver O'Halloran * We assume that bridges *probably* don't need to do any DMA so we can 125001e12629SOliver O'Halloran * skip allocating a TCE table, etc unless we get a non-bridge device. 125101e12629SOliver O'Halloran */ 125201e12629SOliver O'Halloran if (!pe->dma_setup_done && !pci_is_bridge(pdev)) { 125301e12629SOliver O'Halloran switch (phb->type) { 125401e12629SOliver O'Halloran case PNV_PHB_IODA1: 125501e12629SOliver O'Halloran pnv_pci_ioda1_setup_dma_pe(phb, pe); 125601e12629SOliver O'Halloran break; 125701e12629SOliver O'Halloran case PNV_PHB_IODA2: 125801e12629SOliver O'Halloran pnv_pci_ioda2_setup_dma_pe(phb, pe); 125901e12629SOliver O'Halloran break; 126001e12629SOliver O'Halloran default: 126101e12629SOliver O'Halloran pr_warn("%s: No DMA for PHB#%x (type %d)\n", 126201e12629SOliver O'Halloran __func__, phb->hose->global_number, phb->type); 126301e12629SOliver O'Halloran } 126401e12629SOliver O'Halloran } 126501e12629SOliver O'Halloran 1266dc3d8f85SOliver O'Halloran if (pdn) 1267dc3d8f85SOliver O'Halloran pdn->pe_number = pe->pe_number; 1268dc3d8f85SOliver O'Halloran pe->device_count++; 1269dc3d8f85SOliver O'Halloran 1270cd15b048SBenjamin Herrenschmidt WARN_ON(get_dma_ops(&pdev->dev) != &dma_iommu_ops); 12710617fc0cSChristoph Hellwig pdev->dev.archdata.dma_offset = pe->tce_bypass_base; 1272b348aa65SAlexey Kardashevskiy set_iommu_table_base(&pdev->dev, pe->table_group.tables[0]); 127384d8cc07SOliver O'Halloran 127484d8cc07SOliver O'Halloran /* PEs with a DMA weight of zero won't have a group */ 127584d8cc07SOliver O'Halloran if (pe->table_group.group) 127684d8cc07SOliver O'Halloran iommu_add_device(&pe->table_group, &pdev->dev); 1277184cd4a3SBenjamin Herrenschmidt } 1278184cd4a3SBenjamin Herrenschmidt 12798e3f1b1dSRussell Currey /* 12808e3f1b1dSRussell Currey * Reconfigure TVE#0 to be usable as 64-bit DMA space. 12818e3f1b1dSRussell Currey * 12828e3f1b1dSRussell Currey * The first 4GB of virtual memory for a PE is reserved for 32-bit accesses. 12838e3f1b1dSRussell Currey * Devices can only access more than that if bit 59 of the PCI address is set 12848e3f1b1dSRussell Currey * by hardware, which indicates TVE#1 should be used instead of TVE#0. 12858e3f1b1dSRussell Currey * Many PCI devices are not capable of addressing that many bits, and as a 12868e3f1b1dSRussell Currey * result are limited to the 4GB of virtual memory made available to 32-bit 12878e3f1b1dSRussell Currey * devices in TVE#0. 12888e3f1b1dSRussell Currey * 12898e3f1b1dSRussell Currey * In order to work around this, reconfigure TVE#0 to be suitable for 64-bit 12908e3f1b1dSRussell Currey * devices by configuring the virtual memory past the first 4GB inaccessible 12918e3f1b1dSRussell Currey * by 64-bit DMAs. This should only be used by devices that want more than 12928e3f1b1dSRussell Currey * 4GB, and only on PEs that have no 32-bit devices. 12938e3f1b1dSRussell Currey * 12948e3f1b1dSRussell Currey * Currently this will only work on PHB3 (POWER8). 12958e3f1b1dSRussell Currey */ 12968e3f1b1dSRussell Currey static int pnv_pci_ioda_dma_64bit_bypass(struct pnv_ioda_pe *pe) 12978e3f1b1dSRussell Currey { 12988e3f1b1dSRussell Currey u64 window_size, table_size, tce_count, addr; 12998e3f1b1dSRussell Currey struct page *table_pages; 13008e3f1b1dSRussell Currey u64 tce_order = 28; /* 256MB TCEs */ 13018e3f1b1dSRussell Currey __be64 *tces; 13028e3f1b1dSRussell Currey s64 rc; 13038e3f1b1dSRussell Currey 13048e3f1b1dSRussell Currey /* 13058e3f1b1dSRussell Currey * Window size needs to be a power of two, but needs to account for 13068e3f1b1dSRussell Currey * shifting memory by the 4GB offset required to skip 32bit space. 13078e3f1b1dSRussell Currey */ 13088e3f1b1dSRussell Currey window_size = roundup_pow_of_two(memory_hotplug_max() + (1ULL << 32)); 13098e3f1b1dSRussell Currey tce_count = window_size >> tce_order; 13108e3f1b1dSRussell Currey table_size = tce_count << 3; 13118e3f1b1dSRussell Currey 13128e3f1b1dSRussell Currey if (table_size < PAGE_SIZE) 13138e3f1b1dSRussell Currey table_size = PAGE_SIZE; 13148e3f1b1dSRussell Currey 13158e3f1b1dSRussell Currey table_pages = alloc_pages_node(pe->phb->hose->node, GFP_KERNEL, 13168e3f1b1dSRussell Currey get_order(table_size)); 13178e3f1b1dSRussell Currey if (!table_pages) 13188e3f1b1dSRussell Currey goto err; 13198e3f1b1dSRussell Currey 13208e3f1b1dSRussell Currey tces = page_address(table_pages); 13218e3f1b1dSRussell Currey if (!tces) 13228e3f1b1dSRussell Currey goto err; 13238e3f1b1dSRussell Currey 13248e3f1b1dSRussell Currey memset(tces, 0, table_size); 13258e3f1b1dSRussell Currey 13268e3f1b1dSRussell Currey for (addr = 0; addr < memory_hotplug_max(); addr += (1 << tce_order)) { 13278e3f1b1dSRussell Currey tces[(addr + (1ULL << 32)) >> tce_order] = 13288e3f1b1dSRussell Currey cpu_to_be64(addr | TCE_PCI_READ | TCE_PCI_WRITE); 13298e3f1b1dSRussell Currey } 13308e3f1b1dSRussell Currey 13318e3f1b1dSRussell Currey rc = opal_pci_map_pe_dma_window(pe->phb->opal_id, 13328e3f1b1dSRussell Currey pe->pe_number, 13338e3f1b1dSRussell Currey /* reconfigure window 0 */ 13348e3f1b1dSRussell Currey (pe->pe_number << 1) + 0, 13358e3f1b1dSRussell Currey 1, 13368e3f1b1dSRussell Currey __pa(tces), 13378e3f1b1dSRussell Currey table_size, 13388e3f1b1dSRussell Currey 1 << tce_order); 13398e3f1b1dSRussell Currey if (rc == OPAL_SUCCESS) { 13408e3f1b1dSRussell Currey pe_info(pe, "Using 64-bit DMA iommu bypass (through TVE#0)\n"); 13418e3f1b1dSRussell Currey return 0; 13428e3f1b1dSRussell Currey } 13438e3f1b1dSRussell Currey err: 13448e3f1b1dSRussell Currey pe_err(pe, "Error configuring 64-bit DMA bypass\n"); 13458e3f1b1dSRussell Currey return -EIO; 13468e3f1b1dSRussell Currey } 13478e3f1b1dSRussell Currey 13482d6ad41bSChristoph Hellwig static bool pnv_pci_ioda_iommu_bypass_supported(struct pci_dev *pdev, 13492d6ad41bSChristoph Hellwig u64 dma_mask) 1350cd15b048SBenjamin Herrenschmidt { 13515609ffddSOliver O'Halloran struct pnv_phb *phb = pci_bus_to_pnvhb(pdev->bus); 1352cd15b048SBenjamin Herrenschmidt struct pci_dn *pdn = pci_get_pdn(pdev); 1353cd15b048SBenjamin Herrenschmidt struct pnv_ioda_pe *pe; 1354cd15b048SBenjamin Herrenschmidt 1355cd15b048SBenjamin Herrenschmidt if (WARN_ON(!pdn || pdn->pe_number == IODA_INVALID_PE)) 1356b511cdd1SAlexey Kardashevskiy return false; 1357cd15b048SBenjamin Herrenschmidt 1358cd15b048SBenjamin Herrenschmidt pe = &phb->ioda.pe_array[pdn->pe_number]; 1359cd15b048SBenjamin Herrenschmidt if (pe->tce_bypass_enabled) { 13602d6ad41bSChristoph Hellwig u64 top = pe->tce_bypass_base + memblock_end_of_DRAM() - 1; 13612d6ad41bSChristoph Hellwig if (dma_mask >= top) 13622d6ad41bSChristoph Hellwig return true; 1363cd15b048SBenjamin Herrenschmidt } 1364cd15b048SBenjamin Herrenschmidt 13658e3f1b1dSRussell Currey /* 13668e3f1b1dSRussell Currey * If the device can't set the TCE bypass bit but still wants 13678e3f1b1dSRussell Currey * to access 4GB or more, on PHB3 we can reconfigure TVE#0 to 13688e3f1b1dSRussell Currey * bypass the 32-bit region and be usable for 64-bit DMAs. 13698e3f1b1dSRussell Currey * The device needs to be able to address all of this space. 13708e3f1b1dSRussell Currey */ 13718e3f1b1dSRussell Currey if (dma_mask >> 32 && 13728e3f1b1dSRussell Currey dma_mask > (memory_hotplug_max() + (1ULL << 32)) && 1373661fcb45SChristoph Hellwig /* pe->pdev should be set if it's a single device, pe->pbus if not */ 1374661fcb45SChristoph Hellwig (pe->device_count == 1 || !pe->pbus) && 13758e3f1b1dSRussell Currey phb->model == PNV_PHB_MODEL_PHB3) { 13768e3f1b1dSRussell Currey /* Configure the bypass mode */ 13772d6ad41bSChristoph Hellwig s64 rc = pnv_pci_ioda_dma_64bit_bypass(pe); 13788e3f1b1dSRussell Currey if (rc) 1379b511cdd1SAlexey Kardashevskiy return false; 13808e3f1b1dSRussell Currey /* 4GB offset bypasses 32-bit space */ 13810617fc0cSChristoph Hellwig pdev->dev.archdata.dma_offset = (1ULL << 32); 13822d6ad41bSChristoph Hellwig return true; 1383cd15b048SBenjamin Herrenschmidt } 1384cd15b048SBenjamin Herrenschmidt 13852d6ad41bSChristoph Hellwig return false; 1386fe7e85c6SGavin Shan } 1387fe7e85c6SGavin Shan 1388fd141d1aSBenjamin Herrenschmidt static inline __be64 __iomem *pnv_ioda_get_inval_reg(struct pnv_phb *phb, 1389fd141d1aSBenjamin Herrenschmidt bool real_mode) 1390fd141d1aSBenjamin Herrenschmidt { 1391fd141d1aSBenjamin Herrenschmidt return real_mode ? (__be64 __iomem *)(phb->regs_phys + 0x210) : 1392fd141d1aSBenjamin Herrenschmidt (phb->regs + 0x210); 1393fd141d1aSBenjamin Herrenschmidt } 1394fd141d1aSBenjamin Herrenschmidt 1395a34ab7c3SBenjamin Herrenschmidt static void pnv_pci_p7ioc_tce_invalidate(struct iommu_table *tbl, 1396decbda25SAlexey Kardashevskiy unsigned long index, unsigned long npages, bool rm) 13974cce9550SGavin Shan { 13980eaf4defSAlexey Kardashevskiy struct iommu_table_group_link *tgl = list_first_entry_or_null( 13990eaf4defSAlexey Kardashevskiy &tbl->it_group_list, struct iommu_table_group_link, 14000eaf4defSAlexey Kardashevskiy next); 14010eaf4defSAlexey Kardashevskiy struct pnv_ioda_pe *pe = container_of(tgl->table_group, 1402b348aa65SAlexey Kardashevskiy struct pnv_ioda_pe, table_group); 1403fd141d1aSBenjamin Herrenschmidt __be64 __iomem *invalidate = pnv_ioda_get_inval_reg(pe->phb, rm); 14044cce9550SGavin Shan unsigned long start, end, inc; 14054cce9550SGavin Shan 1406decbda25SAlexey Kardashevskiy start = __pa(((__be64 *)tbl->it_base) + index - tbl->it_offset); 1407decbda25SAlexey Kardashevskiy end = __pa(((__be64 *)tbl->it_base) + index - tbl->it_offset + 1408decbda25SAlexey Kardashevskiy npages - 1); 14094cce9550SGavin Shan 14104cce9550SGavin Shan /* p7ioc-style invalidation, 2 TCEs per write */ 14114cce9550SGavin Shan start |= (1ull << 63); 14124cce9550SGavin Shan end |= (1ull << 63); 14134cce9550SGavin Shan inc = 16; 14144cce9550SGavin Shan end |= inc - 1; /* round up end to be different than start */ 14154cce9550SGavin Shan 14164cce9550SGavin Shan mb(); /* Ensure above stores are visible */ 14174cce9550SGavin Shan while (start <= end) { 14188e0a1611SAlexey Kardashevskiy if (rm) 1419001ff2eeSMichael Ellerman __raw_rm_writeq_be(start, invalidate); 14208e0a1611SAlexey Kardashevskiy else 1421001ff2eeSMichael Ellerman __raw_writeq_be(start, invalidate); 1422001ff2eeSMichael Ellerman 14234cce9550SGavin Shan start += inc; 14244cce9550SGavin Shan } 14254cce9550SGavin Shan 14264cce9550SGavin Shan /* 14274cce9550SGavin Shan * The iommu layer will do another mb() for us on build() 14284cce9550SGavin Shan * and we don't care on free() 14294cce9550SGavin Shan */ 14304cce9550SGavin Shan } 14314cce9550SGavin Shan 1432decbda25SAlexey Kardashevskiy static int pnv_ioda1_tce_build(struct iommu_table *tbl, long index, 1433decbda25SAlexey Kardashevskiy long npages, unsigned long uaddr, 1434decbda25SAlexey Kardashevskiy enum dma_data_direction direction, 143500085f1eSKrzysztof Kozlowski unsigned long attrs) 1436decbda25SAlexey Kardashevskiy { 1437decbda25SAlexey Kardashevskiy int ret = pnv_tce_build(tbl, index, npages, uaddr, direction, 1438decbda25SAlexey Kardashevskiy attrs); 1439decbda25SAlexey Kardashevskiy 144008acce1cSBenjamin Herrenschmidt if (!ret) 1441a34ab7c3SBenjamin Herrenschmidt pnv_pci_p7ioc_tce_invalidate(tbl, index, npages, false); 1442decbda25SAlexey Kardashevskiy 1443decbda25SAlexey Kardashevskiy return ret; 1444decbda25SAlexey Kardashevskiy } 1445decbda25SAlexey Kardashevskiy 144605c6cfb9SAlexey Kardashevskiy #ifdef CONFIG_IOMMU_API 144735872480SAlexey Kardashevskiy /* Common for IODA1 and IODA2 */ 144835872480SAlexey Kardashevskiy static int pnv_ioda_tce_xchg_no_kill(struct iommu_table *tbl, long index, 144935872480SAlexey Kardashevskiy unsigned long *hpa, enum dma_data_direction *direction, 145035872480SAlexey Kardashevskiy bool realmode) 145105c6cfb9SAlexey Kardashevskiy { 145235872480SAlexey Kardashevskiy return pnv_tce_xchg(tbl, index, hpa, direction, !realmode); 1453a540aa56SAlexey Kardashevskiy } 145405c6cfb9SAlexey Kardashevskiy #endif 145505c6cfb9SAlexey Kardashevskiy 1456decbda25SAlexey Kardashevskiy static void pnv_ioda1_tce_free(struct iommu_table *tbl, long index, 1457decbda25SAlexey Kardashevskiy long npages) 1458decbda25SAlexey Kardashevskiy { 1459decbda25SAlexey Kardashevskiy pnv_tce_free(tbl, index, npages); 1460decbda25SAlexey Kardashevskiy 1461a34ab7c3SBenjamin Herrenschmidt pnv_pci_p7ioc_tce_invalidate(tbl, index, npages, false); 1462decbda25SAlexey Kardashevskiy } 1463decbda25SAlexey Kardashevskiy 1464da004c36SAlexey Kardashevskiy static struct iommu_table_ops pnv_ioda1_iommu_ops = { 1465decbda25SAlexey Kardashevskiy .set = pnv_ioda1_tce_build, 146605c6cfb9SAlexey Kardashevskiy #ifdef CONFIG_IOMMU_API 146735872480SAlexey Kardashevskiy .xchg_no_kill = pnv_ioda_tce_xchg_no_kill, 146835872480SAlexey Kardashevskiy .tce_kill = pnv_pci_p7ioc_tce_invalidate, 1469090bad39SAlexey Kardashevskiy .useraddrptr = pnv_tce_useraddrptr, 147005c6cfb9SAlexey Kardashevskiy #endif 1471decbda25SAlexey Kardashevskiy .clear = pnv_ioda1_tce_free, 1472da004c36SAlexey Kardashevskiy .get = pnv_tce_get, 1473da004c36SAlexey Kardashevskiy }; 1474da004c36SAlexey Kardashevskiy 1475a34ab7c3SBenjamin Herrenschmidt #define PHB3_TCE_KILL_INVAL_ALL PPC_BIT(0) 1476a34ab7c3SBenjamin Herrenschmidt #define PHB3_TCE_KILL_INVAL_PE PPC_BIT(1) 1477a34ab7c3SBenjamin Herrenschmidt #define PHB3_TCE_KILL_INVAL_ONE PPC_BIT(2) 1478bef9253fSAlexey Kardashevskiy 14796b3d12a9SAlistair Popple static void pnv_pci_phb3_tce_invalidate_entire(struct pnv_phb *phb, bool rm) 14800bbcdb43SAlexey Kardashevskiy { 1481fd141d1aSBenjamin Herrenschmidt __be64 __iomem *invalidate = pnv_ioda_get_inval_reg(phb, rm); 1482a34ab7c3SBenjamin Herrenschmidt const unsigned long val = PHB3_TCE_KILL_INVAL_ALL; 14830bbcdb43SAlexey Kardashevskiy 14840bbcdb43SAlexey Kardashevskiy mb(); /* Ensure previous TCE table stores are visible */ 14850bbcdb43SAlexey Kardashevskiy if (rm) 1486001ff2eeSMichael Ellerman __raw_rm_writeq_be(val, invalidate); 14870bbcdb43SAlexey Kardashevskiy else 1488001ff2eeSMichael Ellerman __raw_writeq_be(val, invalidate); 14890bbcdb43SAlexey Kardashevskiy } 14900bbcdb43SAlexey Kardashevskiy 1491a34ab7c3SBenjamin Herrenschmidt static inline void pnv_pci_phb3_tce_invalidate_pe(struct pnv_ioda_pe *pe) 14925780fb04SAlexey Kardashevskiy { 14935780fb04SAlexey Kardashevskiy /* 01xb - invalidate TCEs that match the specified PE# */ 1494fd141d1aSBenjamin Herrenschmidt __be64 __iomem *invalidate = pnv_ioda_get_inval_reg(pe->phb, false); 1495a34ab7c3SBenjamin Herrenschmidt unsigned long val = PHB3_TCE_KILL_INVAL_PE | (pe->pe_number & 0xFF); 14965780fb04SAlexey Kardashevskiy 14975780fb04SAlexey Kardashevskiy mb(); /* Ensure above stores are visible */ 1498001ff2eeSMichael Ellerman __raw_writeq_be(val, invalidate); 14995780fb04SAlexey Kardashevskiy } 15005780fb04SAlexey Kardashevskiy 1501fd141d1aSBenjamin Herrenschmidt static void pnv_pci_phb3_tce_invalidate(struct pnv_ioda_pe *pe, bool rm, 1502fd141d1aSBenjamin Herrenschmidt unsigned shift, unsigned long index, 1503fd141d1aSBenjamin Herrenschmidt unsigned long npages) 15044cce9550SGavin Shan { 15054d902195SAlexey Kardashevskiy __be64 __iomem *invalidate = pnv_ioda_get_inval_reg(pe->phb, rm); 15064cce9550SGavin Shan unsigned long start, end, inc; 15074cce9550SGavin Shan 15084cce9550SGavin Shan /* We'll invalidate DMA address in PE scope */ 1509a34ab7c3SBenjamin Herrenschmidt start = PHB3_TCE_KILL_INVAL_ONE; 1510fd141d1aSBenjamin Herrenschmidt start |= (pe->pe_number & 0xFF); 15114cce9550SGavin Shan end = start; 15124cce9550SGavin Shan 15134cce9550SGavin Shan /* Figure out the start, end and step */ 1514decbda25SAlexey Kardashevskiy start |= (index << shift); 1515decbda25SAlexey Kardashevskiy end |= ((index + npages - 1) << shift); 1516b0376c9bSAlexey Kardashevskiy inc = (0x1ull << shift); 15174cce9550SGavin Shan mb(); 15184cce9550SGavin Shan 15194cce9550SGavin Shan while (start <= end) { 15208e0a1611SAlexey Kardashevskiy if (rm) 1521001ff2eeSMichael Ellerman __raw_rm_writeq_be(start, invalidate); 15228e0a1611SAlexey Kardashevskiy else 1523001ff2eeSMichael Ellerman __raw_writeq_be(start, invalidate); 15244cce9550SGavin Shan start += inc; 15254cce9550SGavin Shan } 15264cce9550SGavin Shan } 15274cce9550SGavin Shan 1528f0228c41SBenjamin Herrenschmidt static inline void pnv_pci_ioda2_tce_invalidate_pe(struct pnv_ioda_pe *pe) 1529f0228c41SBenjamin Herrenschmidt { 1530f0228c41SBenjamin Herrenschmidt struct pnv_phb *phb = pe->phb; 1531f0228c41SBenjamin Herrenschmidt 1532f0228c41SBenjamin Herrenschmidt if (phb->model == PNV_PHB_MODEL_PHB3 && phb->regs) 1533f0228c41SBenjamin Herrenschmidt pnv_pci_phb3_tce_invalidate_pe(pe); 1534f0228c41SBenjamin Herrenschmidt else 1535f0228c41SBenjamin Herrenschmidt opal_pci_tce_kill(phb->opal_id, OPAL_PCI_TCE_KILL_PE, 1536f0228c41SBenjamin Herrenschmidt pe->pe_number, 0, 0, 0); 1537f0228c41SBenjamin Herrenschmidt } 1538f0228c41SBenjamin Herrenschmidt 1539e57080f1SAlexey Kardashevskiy static void pnv_pci_ioda2_tce_invalidate(struct iommu_table *tbl, 1540e57080f1SAlexey Kardashevskiy unsigned long index, unsigned long npages, bool rm) 1541e57080f1SAlexey Kardashevskiy { 1542e57080f1SAlexey Kardashevskiy struct iommu_table_group_link *tgl; 1543e57080f1SAlexey Kardashevskiy 1544a540aa56SAlexey Kardashevskiy list_for_each_entry_lockless(tgl, &tbl->it_group_list, next) { 1545e57080f1SAlexey Kardashevskiy struct pnv_ioda_pe *pe = container_of(tgl->table_group, 1546e57080f1SAlexey Kardashevskiy struct pnv_ioda_pe, table_group); 1547f0228c41SBenjamin Herrenschmidt struct pnv_phb *phb = pe->phb; 1548f0228c41SBenjamin Herrenschmidt unsigned int shift = tbl->it_page_shift; 1549f0228c41SBenjamin Herrenschmidt 1550616badd2SAlistair Popple /* 1551616badd2SAlistair Popple * NVLink1 can use the TCE kill register directly as 1552616badd2SAlistair Popple * it's the same as PHB3. NVLink2 is different and 1553616badd2SAlistair Popple * should go via the OPAL call. 1554616badd2SAlistair Popple */ 1555616badd2SAlistair Popple if (phb->model == PNV_PHB_MODEL_NPU) { 15560bbcdb43SAlexey Kardashevskiy /* 15570bbcdb43SAlexey Kardashevskiy * The NVLink hardware does not support TCE kill 15580bbcdb43SAlexey Kardashevskiy * per TCE entry so we have to invalidate 15590bbcdb43SAlexey Kardashevskiy * the entire cache for it. 15600bbcdb43SAlexey Kardashevskiy */ 1561f0228c41SBenjamin Herrenschmidt pnv_pci_phb3_tce_invalidate_entire(phb, rm); 15625d2aa710SAlistair Popple continue; 15635d2aa710SAlistair Popple } 1564f0228c41SBenjamin Herrenschmidt if (phb->model == PNV_PHB_MODEL_PHB3 && phb->regs) 1565f0228c41SBenjamin Herrenschmidt pnv_pci_phb3_tce_invalidate(pe, rm, shift, 156685674868SAlexey Kardashevskiy index, npages); 1567f0228c41SBenjamin Herrenschmidt else 1568f0228c41SBenjamin Herrenschmidt opal_pci_tce_kill(phb->opal_id, 1569f0228c41SBenjamin Herrenschmidt OPAL_PCI_TCE_KILL_PAGES, 1570f0228c41SBenjamin Herrenschmidt pe->pe_number, 1u << shift, 1571f0228c41SBenjamin Herrenschmidt index << shift, npages); 1572e57080f1SAlexey Kardashevskiy } 1573e57080f1SAlexey Kardashevskiy } 1574e57080f1SAlexey Kardashevskiy 15756b3d12a9SAlistair Popple void pnv_pci_ioda2_tce_invalidate_entire(struct pnv_phb *phb, bool rm) 15766b3d12a9SAlistair Popple { 15776b3d12a9SAlistair Popple if (phb->model == PNV_PHB_MODEL_NPU || phb->model == PNV_PHB_MODEL_PHB3) 15786b3d12a9SAlistair Popple pnv_pci_phb3_tce_invalidate_entire(phb, rm); 15796b3d12a9SAlistair Popple else 15806b3d12a9SAlistair Popple opal_pci_tce_kill(phb->opal_id, OPAL_PCI_TCE_KILL, 0, 0, 0, 0); 15816b3d12a9SAlistair Popple } 15826b3d12a9SAlistair Popple 1583decbda25SAlexey Kardashevskiy static int pnv_ioda2_tce_build(struct iommu_table *tbl, long index, 1584decbda25SAlexey Kardashevskiy long npages, unsigned long uaddr, 1585decbda25SAlexey Kardashevskiy enum dma_data_direction direction, 158600085f1eSKrzysztof Kozlowski unsigned long attrs) 15874cce9550SGavin Shan { 1588decbda25SAlexey Kardashevskiy int ret = pnv_tce_build(tbl, index, npages, uaddr, direction, 1589decbda25SAlexey Kardashevskiy attrs); 15904cce9550SGavin Shan 159108acce1cSBenjamin Herrenschmidt if (!ret) 1592decbda25SAlexey Kardashevskiy pnv_pci_ioda2_tce_invalidate(tbl, index, npages, false); 1593decbda25SAlexey Kardashevskiy 1594decbda25SAlexey Kardashevskiy return ret; 1595decbda25SAlexey Kardashevskiy } 1596decbda25SAlexey Kardashevskiy 1597decbda25SAlexey Kardashevskiy static void pnv_ioda2_tce_free(struct iommu_table *tbl, long index, 1598decbda25SAlexey Kardashevskiy long npages) 1599decbda25SAlexey Kardashevskiy { 1600decbda25SAlexey Kardashevskiy pnv_tce_free(tbl, index, npages); 1601decbda25SAlexey Kardashevskiy 1602decbda25SAlexey Kardashevskiy pnv_pci_ioda2_tce_invalidate(tbl, index, npages, false); 16034cce9550SGavin Shan } 16044cce9550SGavin Shan 1605da004c36SAlexey Kardashevskiy static struct iommu_table_ops pnv_ioda2_iommu_ops = { 1606decbda25SAlexey Kardashevskiy .set = pnv_ioda2_tce_build, 160705c6cfb9SAlexey Kardashevskiy #ifdef CONFIG_IOMMU_API 160835872480SAlexey Kardashevskiy .xchg_no_kill = pnv_ioda_tce_xchg_no_kill, 160935872480SAlexey Kardashevskiy .tce_kill = pnv_pci_ioda2_tce_invalidate, 1610090bad39SAlexey Kardashevskiy .useraddrptr = pnv_tce_useraddrptr, 161105c6cfb9SAlexey Kardashevskiy #endif 1612decbda25SAlexey Kardashevskiy .clear = pnv_ioda2_tce_free, 1613da004c36SAlexey Kardashevskiy .get = pnv_tce_get, 1614da2bb0daSAlexey Kardashevskiy .free = pnv_pci_ioda2_table_free_pages, 1615da004c36SAlexey Kardashevskiy }; 1616da004c36SAlexey Kardashevskiy 1617801846d1SGavin Shan static int pnv_pci_ioda_dev_dma_weight(struct pci_dev *dev, void *data) 1618801846d1SGavin Shan { 1619801846d1SGavin Shan unsigned int *weight = (unsigned int *)data; 1620801846d1SGavin Shan 1621801846d1SGavin Shan /* This is quite simplistic. The "base" weight of a device 1622801846d1SGavin Shan * is 10. 0 means no DMA is to be accounted for it. 1623801846d1SGavin Shan */ 1624801846d1SGavin Shan if (dev->hdr_type != PCI_HEADER_TYPE_NORMAL) 1625801846d1SGavin Shan return 0; 1626801846d1SGavin Shan 1627801846d1SGavin Shan if (dev->class == PCI_CLASS_SERIAL_USB_UHCI || 1628801846d1SGavin Shan dev->class == PCI_CLASS_SERIAL_USB_OHCI || 1629801846d1SGavin Shan dev->class == PCI_CLASS_SERIAL_USB_EHCI) 1630801846d1SGavin Shan *weight += 3; 1631801846d1SGavin Shan else if ((dev->class >> 8) == PCI_CLASS_STORAGE_RAID) 1632801846d1SGavin Shan *weight += 15; 1633801846d1SGavin Shan else 1634801846d1SGavin Shan *weight += 10; 1635801846d1SGavin Shan 1636801846d1SGavin Shan return 0; 1637801846d1SGavin Shan } 1638801846d1SGavin Shan 1639801846d1SGavin Shan static unsigned int pnv_pci_ioda_pe_dma_weight(struct pnv_ioda_pe *pe) 1640801846d1SGavin Shan { 1641801846d1SGavin Shan unsigned int weight = 0; 1642801846d1SGavin Shan 1643801846d1SGavin Shan /* SRIOV VF has same DMA32 weight as its PF */ 1644801846d1SGavin Shan #ifdef CONFIG_PCI_IOV 1645801846d1SGavin Shan if ((pe->flags & PNV_IODA_PE_VF) && pe->parent_dev) { 1646801846d1SGavin Shan pnv_pci_ioda_dev_dma_weight(pe->parent_dev, &weight); 1647801846d1SGavin Shan return weight; 1648801846d1SGavin Shan } 1649801846d1SGavin Shan #endif 1650801846d1SGavin Shan 1651801846d1SGavin Shan if ((pe->flags & PNV_IODA_PE_DEV) && pe->pdev) { 1652801846d1SGavin Shan pnv_pci_ioda_dev_dma_weight(pe->pdev, &weight); 1653801846d1SGavin Shan } else if ((pe->flags & PNV_IODA_PE_BUS) && pe->pbus) { 1654801846d1SGavin Shan struct pci_dev *pdev; 1655801846d1SGavin Shan 1656801846d1SGavin Shan list_for_each_entry(pdev, &pe->pbus->devices, bus_list) 1657801846d1SGavin Shan pnv_pci_ioda_dev_dma_weight(pdev, &weight); 1658801846d1SGavin Shan } else if ((pe->flags & PNV_IODA_PE_BUS_ALL) && pe->pbus) { 1659801846d1SGavin Shan pci_walk_bus(pe->pbus, pnv_pci_ioda_dev_dma_weight, &weight); 1660801846d1SGavin Shan } 1661801846d1SGavin Shan 1662801846d1SGavin Shan return weight; 1663801846d1SGavin Shan } 1664801846d1SGavin Shan 1665b30d936fSGavin Shan static void pnv_pci_ioda1_setup_dma_pe(struct pnv_phb *phb, 16662b923ed1SGavin Shan struct pnv_ioda_pe *pe) 1667184cd4a3SBenjamin Herrenschmidt { 1668184cd4a3SBenjamin Herrenschmidt 1669184cd4a3SBenjamin Herrenschmidt struct page *tce_mem = NULL; 1670184cd4a3SBenjamin Herrenschmidt struct iommu_table *tbl; 16712b923ed1SGavin Shan unsigned int weight, total_weight = 0; 16722b923ed1SGavin Shan unsigned int tce32_segsz, base, segs, avail, i; 1673184cd4a3SBenjamin Herrenschmidt int64_t rc; 1674184cd4a3SBenjamin Herrenschmidt void *addr; 1675184cd4a3SBenjamin Herrenschmidt 1676184cd4a3SBenjamin Herrenschmidt /* XXX FIXME: Handle 64-bit only DMA devices */ 1677184cd4a3SBenjamin Herrenschmidt /* XXX FIXME: Provide 64-bit DMA facilities & non-4K TCE tables etc.. */ 1678184cd4a3SBenjamin Herrenschmidt /* XXX FIXME: Allocate multi-level tables on PHB3 */ 16792b923ed1SGavin Shan weight = pnv_pci_ioda_pe_dma_weight(pe); 16802b923ed1SGavin Shan if (!weight) 16812b923ed1SGavin Shan return; 1682184cd4a3SBenjamin Herrenschmidt 16832b923ed1SGavin Shan pci_walk_bus(phb->hose->bus, pnv_pci_ioda_dev_dma_weight, 16842b923ed1SGavin Shan &total_weight); 16852b923ed1SGavin Shan segs = (weight * phb->ioda.dma32_count) / total_weight; 16862b923ed1SGavin Shan if (!segs) 16872b923ed1SGavin Shan segs = 1; 16882b923ed1SGavin Shan 16892b923ed1SGavin Shan /* 16902b923ed1SGavin Shan * Allocate contiguous DMA32 segments. We begin with the expected 16912b923ed1SGavin Shan * number of segments. With one more attempt, the number of DMA32 16922b923ed1SGavin Shan * segments to be allocated is decreased by one until one segment 16932b923ed1SGavin Shan * is allocated successfully. 16942b923ed1SGavin Shan */ 16952b923ed1SGavin Shan do { 16962b923ed1SGavin Shan for (base = 0; base <= phb->ioda.dma32_count - segs; base++) { 16972b923ed1SGavin Shan for (avail = 0, i = base; i < base + segs; i++) { 16982b923ed1SGavin Shan if (phb->ioda.dma32_segmap[i] == 16992b923ed1SGavin Shan IODA_INVALID_PE) 17002b923ed1SGavin Shan avail++; 17012b923ed1SGavin Shan } 17022b923ed1SGavin Shan 17032b923ed1SGavin Shan if (avail == segs) 17042b923ed1SGavin Shan goto found; 17052b923ed1SGavin Shan } 17062b923ed1SGavin Shan } while (--segs); 17072b923ed1SGavin Shan 17082b923ed1SGavin Shan if (!segs) { 17092b923ed1SGavin Shan pe_warn(pe, "No available DMA32 segments\n"); 17102b923ed1SGavin Shan return; 17112b923ed1SGavin Shan } 17122b923ed1SGavin Shan 17132b923ed1SGavin Shan found: 17140eaf4defSAlexey Kardashevskiy tbl = pnv_pci_table_alloc(phb->hose->node); 171582eae1afSAlexey Kardashevskiy if (WARN_ON(!tbl)) 171682eae1afSAlexey Kardashevskiy return; 171782eae1afSAlexey Kardashevskiy 1718b348aa65SAlexey Kardashevskiy iommu_register_group(&pe->table_group, phb->hose->global_number, 1719b348aa65SAlexey Kardashevskiy pe->pe_number); 17200eaf4defSAlexey Kardashevskiy pnv_pci_link_table_and_group(phb->hose->node, 0, tbl, &pe->table_group); 1721c5773822SAlexey Kardashevskiy 1722184cd4a3SBenjamin Herrenschmidt /* Grab a 32-bit TCE table */ 17232b923ed1SGavin Shan pe_info(pe, "DMA weight %d (%d), assigned (%d) %d DMA32 segments\n", 17242b923ed1SGavin Shan weight, total_weight, base, segs); 1725184cd4a3SBenjamin Herrenschmidt pe_info(pe, " Setting up 32-bit TCE table at %08x..%08x\n", 1726acce971cSGavin Shan base * PNV_IODA1_DMA32_SEGSIZE, 1727acce971cSGavin Shan (base + segs) * PNV_IODA1_DMA32_SEGSIZE - 1); 1728184cd4a3SBenjamin Herrenschmidt 1729184cd4a3SBenjamin Herrenschmidt /* XXX Currently, we allocate one big contiguous table for the 1730184cd4a3SBenjamin Herrenschmidt * TCEs. We only really need one chunk per 256M of TCE space 1731184cd4a3SBenjamin Herrenschmidt * (ie per segment) but that's an optimization for later, it 1732184cd4a3SBenjamin Herrenschmidt * requires some added smarts with our get/put_tce implementation 1733acce971cSGavin Shan * 1734acce971cSGavin Shan * Each TCE page is 4KB in size and each TCE entry occupies 8 1735acce971cSGavin Shan * bytes 1736184cd4a3SBenjamin Herrenschmidt */ 1737acce971cSGavin Shan tce32_segsz = PNV_IODA1_DMA32_SEGSIZE >> (IOMMU_PAGE_SHIFT_4K - 3); 1738184cd4a3SBenjamin Herrenschmidt tce_mem = alloc_pages_node(phb->hose->node, GFP_KERNEL, 1739acce971cSGavin Shan get_order(tce32_segsz * segs)); 1740184cd4a3SBenjamin Herrenschmidt if (!tce_mem) { 1741184cd4a3SBenjamin Herrenschmidt pe_err(pe, " Failed to allocate a 32-bit TCE memory\n"); 1742184cd4a3SBenjamin Herrenschmidt goto fail; 1743184cd4a3SBenjamin Herrenschmidt } 1744184cd4a3SBenjamin Herrenschmidt addr = page_address(tce_mem); 1745acce971cSGavin Shan memset(addr, 0, tce32_segsz * segs); 1746184cd4a3SBenjamin Herrenschmidt 1747184cd4a3SBenjamin Herrenschmidt /* Configure HW */ 1748184cd4a3SBenjamin Herrenschmidt for (i = 0; i < segs; i++) { 1749184cd4a3SBenjamin Herrenschmidt rc = opal_pci_map_pe_dma_window(phb->opal_id, 1750184cd4a3SBenjamin Herrenschmidt pe->pe_number, 1751184cd4a3SBenjamin Herrenschmidt base + i, 1, 1752acce971cSGavin Shan __pa(addr) + tce32_segsz * i, 1753acce971cSGavin Shan tce32_segsz, IOMMU_PAGE_SIZE_4K); 1754184cd4a3SBenjamin Herrenschmidt if (rc) { 17551e496391SJoe Perches pe_err(pe, " Failed to configure 32-bit TCE table, err %lld\n", 17561e496391SJoe Perches rc); 1757184cd4a3SBenjamin Herrenschmidt goto fail; 1758184cd4a3SBenjamin Herrenschmidt } 1759184cd4a3SBenjamin Herrenschmidt } 1760184cd4a3SBenjamin Herrenschmidt 17612b923ed1SGavin Shan /* Setup DMA32 segment mapping */ 17622b923ed1SGavin Shan for (i = base; i < base + segs; i++) 17632b923ed1SGavin Shan phb->ioda.dma32_segmap[i] = pe->pe_number; 17642b923ed1SGavin Shan 1765184cd4a3SBenjamin Herrenschmidt /* Setup linux iommu table */ 1766acce971cSGavin Shan pnv_pci_setup_iommu_table(tbl, addr, tce32_segsz * segs, 1767acce971cSGavin Shan base * PNV_IODA1_DMA32_SEGSIZE, 1768acce971cSGavin Shan IOMMU_PAGE_SHIFT_4K); 1769184cd4a3SBenjamin Herrenschmidt 1770da004c36SAlexey Kardashevskiy tbl->it_ops = &pnv_ioda1_iommu_ops; 17714793d65dSAlexey Kardashevskiy pe->table_group.tce32_start = tbl->it_offset << tbl->it_page_shift; 17724793d65dSAlexey Kardashevskiy pe->table_group.tce32_size = tbl->it_size << tbl->it_page_shift; 1773201ed7f3SAlexey Kardashevskiy iommu_init_table(tbl, phb->hose->node, 0, 0); 1774184cd4a3SBenjamin Herrenschmidt 177501e12629SOliver O'Halloran pe->dma_setup_done = true; 1776184cd4a3SBenjamin Herrenschmidt return; 1777184cd4a3SBenjamin Herrenschmidt fail: 1778184cd4a3SBenjamin Herrenschmidt /* XXX Failure: Try to fallback to 64-bit only ? */ 1779184cd4a3SBenjamin Herrenschmidt if (tce_mem) 1780acce971cSGavin Shan __free_pages(tce_mem, get_order(tce32_segsz * segs)); 17810eaf4defSAlexey Kardashevskiy if (tbl) { 17820eaf4defSAlexey Kardashevskiy pnv_pci_unlink_table_and_group(tbl, &pe->table_group); 1783e5afdf9dSAlexey Kardashevskiy iommu_tce_table_put(tbl); 17840eaf4defSAlexey Kardashevskiy } 1785184cd4a3SBenjamin Herrenschmidt } 1786184cd4a3SBenjamin Herrenschmidt 178743cb60abSAlexey Kardashevskiy static long pnv_pci_ioda2_set_window(struct iommu_table_group *table_group, 178843cb60abSAlexey Kardashevskiy int num, struct iommu_table *tbl) 178943cb60abSAlexey Kardashevskiy { 179043cb60abSAlexey Kardashevskiy struct pnv_ioda_pe *pe = container_of(table_group, struct pnv_ioda_pe, 179143cb60abSAlexey Kardashevskiy table_group); 179243cb60abSAlexey Kardashevskiy struct pnv_phb *phb = pe->phb; 179343cb60abSAlexey Kardashevskiy int64_t rc; 1794bbb845c4SAlexey Kardashevskiy const unsigned long size = tbl->it_indirect_levels ? 1795bbb845c4SAlexey Kardashevskiy tbl->it_level_size : tbl->it_size; 179643cb60abSAlexey Kardashevskiy const __u64 start_addr = tbl->it_offset << tbl->it_page_shift; 179743cb60abSAlexey Kardashevskiy const __u64 win_size = tbl->it_size << tbl->it_page_shift; 179843cb60abSAlexey Kardashevskiy 17991e496391SJoe Perches pe_info(pe, "Setting up window#%d %llx..%llx pg=%lx\n", 18001e496391SJoe Perches num, start_addr, start_addr + win_size - 1, 180143cb60abSAlexey Kardashevskiy IOMMU_PAGE_SIZE(tbl)); 180243cb60abSAlexey Kardashevskiy 180343cb60abSAlexey Kardashevskiy /* 180443cb60abSAlexey Kardashevskiy * Map TCE table through TVT. The TVE index is the PE number 180543cb60abSAlexey Kardashevskiy * shifted by 1 bit for 32-bits DMA space. 180643cb60abSAlexey Kardashevskiy */ 180743cb60abSAlexey Kardashevskiy rc = opal_pci_map_pe_dma_window(phb->opal_id, 180843cb60abSAlexey Kardashevskiy pe->pe_number, 18094793d65dSAlexey Kardashevskiy (pe->pe_number << 1) + num, 1810bbb845c4SAlexey Kardashevskiy tbl->it_indirect_levels + 1, 181143cb60abSAlexey Kardashevskiy __pa(tbl->it_base), 1812bbb845c4SAlexey Kardashevskiy size << 3, 181343cb60abSAlexey Kardashevskiy IOMMU_PAGE_SIZE(tbl)); 181443cb60abSAlexey Kardashevskiy if (rc) { 18151e496391SJoe Perches pe_err(pe, "Failed to configure TCE table, err %lld\n", rc); 181643cb60abSAlexey Kardashevskiy return rc; 181743cb60abSAlexey Kardashevskiy } 181843cb60abSAlexey Kardashevskiy 181943cb60abSAlexey Kardashevskiy pnv_pci_link_table_and_group(phb->hose->node, num, 182043cb60abSAlexey Kardashevskiy tbl, &pe->table_group); 1821ed7d9a1dSMichael Ellerman pnv_pci_ioda2_tce_invalidate_pe(pe); 182243cb60abSAlexey Kardashevskiy 182343cb60abSAlexey Kardashevskiy return 0; 182443cb60abSAlexey Kardashevskiy } 182543cb60abSAlexey Kardashevskiy 1826c498a4f9SChristoph Hellwig static void pnv_pci_ioda2_set_bypass(struct pnv_ioda_pe *pe, bool enable) 1827cd15b048SBenjamin Herrenschmidt { 1828cd15b048SBenjamin Herrenschmidt uint16_t window_id = (pe->pe_number << 1 ) + 1; 1829cd15b048SBenjamin Herrenschmidt int64_t rc; 1830cd15b048SBenjamin Herrenschmidt 1831cd15b048SBenjamin Herrenschmidt pe_info(pe, "%sabling 64-bit DMA bypass\n", enable ? "En" : "Dis"); 1832cd15b048SBenjamin Herrenschmidt if (enable) { 1833cd15b048SBenjamin Herrenschmidt phys_addr_t top = memblock_end_of_DRAM(); 1834cd15b048SBenjamin Herrenschmidt 1835cd15b048SBenjamin Herrenschmidt top = roundup_pow_of_two(top); 1836cd15b048SBenjamin Herrenschmidt rc = opal_pci_map_pe_dma_window_real(pe->phb->opal_id, 1837cd15b048SBenjamin Herrenschmidt pe->pe_number, 1838cd15b048SBenjamin Herrenschmidt window_id, 1839cd15b048SBenjamin Herrenschmidt pe->tce_bypass_base, 1840cd15b048SBenjamin Herrenschmidt top); 1841cd15b048SBenjamin Herrenschmidt } else { 1842cd15b048SBenjamin Herrenschmidt rc = opal_pci_map_pe_dma_window_real(pe->phb->opal_id, 1843cd15b048SBenjamin Herrenschmidt pe->pe_number, 1844cd15b048SBenjamin Herrenschmidt window_id, 1845cd15b048SBenjamin Herrenschmidt pe->tce_bypass_base, 1846cd15b048SBenjamin Herrenschmidt 0); 1847cd15b048SBenjamin Herrenschmidt } 1848cd15b048SBenjamin Herrenschmidt if (rc) 1849cd15b048SBenjamin Herrenschmidt pe_err(pe, "OPAL error %lld configuring bypass window\n", rc); 1850cd15b048SBenjamin Herrenschmidt else 1851cd15b048SBenjamin Herrenschmidt pe->tce_bypass_enabled = enable; 1852cd15b048SBenjamin Herrenschmidt } 1853cd15b048SBenjamin Herrenschmidt 18544793d65dSAlexey Kardashevskiy static long pnv_pci_ioda2_create_table(struct iommu_table_group *table_group, 18554793d65dSAlexey Kardashevskiy int num, __u32 page_shift, __u64 window_size, __u32 levels, 1856090bad39SAlexey Kardashevskiy bool alloc_userspace_copy, struct iommu_table **ptbl) 18574793d65dSAlexey Kardashevskiy { 18584793d65dSAlexey Kardashevskiy struct pnv_ioda_pe *pe = container_of(table_group, struct pnv_ioda_pe, 18594793d65dSAlexey Kardashevskiy table_group); 18604793d65dSAlexey Kardashevskiy int nid = pe->phb->hose->node; 18614793d65dSAlexey Kardashevskiy __u64 bus_offset = num ? pe->tce_bypass_base : table_group->tce32_start; 18624793d65dSAlexey Kardashevskiy long ret; 18634793d65dSAlexey Kardashevskiy struct iommu_table *tbl; 18644793d65dSAlexey Kardashevskiy 18654793d65dSAlexey Kardashevskiy tbl = pnv_pci_table_alloc(nid); 18664793d65dSAlexey Kardashevskiy if (!tbl) 18674793d65dSAlexey Kardashevskiy return -ENOMEM; 18684793d65dSAlexey Kardashevskiy 186911edf116SAlexey Kardashevskiy tbl->it_ops = &pnv_ioda2_iommu_ops; 187011edf116SAlexey Kardashevskiy 18714793d65dSAlexey Kardashevskiy ret = pnv_pci_ioda2_table_alloc_pages(nid, 18724793d65dSAlexey Kardashevskiy bus_offset, page_shift, window_size, 1873090bad39SAlexey Kardashevskiy levels, alloc_userspace_copy, tbl); 18744793d65dSAlexey Kardashevskiy if (ret) { 1875e5afdf9dSAlexey Kardashevskiy iommu_tce_table_put(tbl); 18764793d65dSAlexey Kardashevskiy return ret; 18774793d65dSAlexey Kardashevskiy } 18784793d65dSAlexey Kardashevskiy 18794793d65dSAlexey Kardashevskiy *ptbl = tbl; 18804793d65dSAlexey Kardashevskiy 18814793d65dSAlexey Kardashevskiy return 0; 18824793d65dSAlexey Kardashevskiy } 18834793d65dSAlexey Kardashevskiy 188446d3e1e1SAlexey Kardashevskiy static long pnv_pci_ioda2_setup_default_config(struct pnv_ioda_pe *pe) 188546d3e1e1SAlexey Kardashevskiy { 188646d3e1e1SAlexey Kardashevskiy struct iommu_table *tbl = NULL; 188746d3e1e1SAlexey Kardashevskiy long rc; 1888201ed7f3SAlexey Kardashevskiy unsigned long res_start, res_end; 188946d3e1e1SAlexey Kardashevskiy 1890bb005455SNishanth Aravamudan /* 1891fa144869SNishanth Aravamudan * crashkernel= specifies the kdump kernel's maximum memory at 1892fa144869SNishanth Aravamudan * some offset and there is no guaranteed the result is a power 1893fa144869SNishanth Aravamudan * of 2, which will cause errors later. 1894fa144869SNishanth Aravamudan */ 1895fa144869SNishanth Aravamudan const u64 max_memory = __rounddown_pow_of_two(memory_hotplug_max()); 1896fa144869SNishanth Aravamudan 1897fa144869SNishanth Aravamudan /* 1898bb005455SNishanth Aravamudan * In memory constrained environments, e.g. kdump kernel, the 1899bb005455SNishanth Aravamudan * DMA window can be larger than available memory, which will 1900bb005455SNishanth Aravamudan * cause errors later. 1901bb005455SNishanth Aravamudan */ 1902201ed7f3SAlexey Kardashevskiy const u64 maxblock = 1UL << (PAGE_SHIFT + MAX_ORDER - 1); 1903bb005455SNishanth Aravamudan 1904201ed7f3SAlexey Kardashevskiy /* 1905201ed7f3SAlexey Kardashevskiy * We create the default window as big as we can. The constraint is 1906201ed7f3SAlexey Kardashevskiy * the max order of allocation possible. The TCE table is likely to 1907201ed7f3SAlexey Kardashevskiy * end up being multilevel and with on-demand allocation in place, 1908201ed7f3SAlexey Kardashevskiy * the initial use is not going to be huge as the default window aims 1909201ed7f3SAlexey Kardashevskiy * to support crippled devices (i.e. not fully 64bit DMAble) only. 1910201ed7f3SAlexey Kardashevskiy */ 1911201ed7f3SAlexey Kardashevskiy /* iommu_table::it_map uses 1 bit per IOMMU page, hence 8 */ 1912201ed7f3SAlexey Kardashevskiy const u64 window_size = min((maxblock * 8) << PAGE_SHIFT, max_memory); 1913201ed7f3SAlexey Kardashevskiy /* Each TCE level cannot exceed maxblock so go multilevel if needed */ 1914201ed7f3SAlexey Kardashevskiy unsigned long tces_order = ilog2(window_size >> PAGE_SHIFT); 1915201ed7f3SAlexey Kardashevskiy unsigned long tcelevel_order = ilog2(maxblock >> 3); 1916201ed7f3SAlexey Kardashevskiy unsigned int levels = tces_order / tcelevel_order; 1917201ed7f3SAlexey Kardashevskiy 1918201ed7f3SAlexey Kardashevskiy if (tces_order % tcelevel_order) 1919201ed7f3SAlexey Kardashevskiy levels += 1; 1920201ed7f3SAlexey Kardashevskiy /* 1921201ed7f3SAlexey Kardashevskiy * We try to stick to default levels (which is >1 at the moment) in 1922201ed7f3SAlexey Kardashevskiy * order to save memory by relying on on-demain TCE level allocation. 1923201ed7f3SAlexey Kardashevskiy */ 1924201ed7f3SAlexey Kardashevskiy levels = max_t(unsigned int, levels, POWERNV_IOMMU_DEFAULT_LEVELS); 1925201ed7f3SAlexey Kardashevskiy 1926201ed7f3SAlexey Kardashevskiy rc = pnv_pci_ioda2_create_table(&pe->table_group, 0, PAGE_SHIFT, 1927201ed7f3SAlexey Kardashevskiy window_size, levels, false, &tbl); 192846d3e1e1SAlexey Kardashevskiy if (rc) { 192946d3e1e1SAlexey Kardashevskiy pe_err(pe, "Failed to create 32-bit TCE table, err %ld", 193046d3e1e1SAlexey Kardashevskiy rc); 193146d3e1e1SAlexey Kardashevskiy return rc; 193246d3e1e1SAlexey Kardashevskiy } 193346d3e1e1SAlexey Kardashevskiy 1934201ed7f3SAlexey Kardashevskiy /* We use top part of 32bit space for MMIO so exclude it from DMA */ 1935201ed7f3SAlexey Kardashevskiy res_start = 0; 1936201ed7f3SAlexey Kardashevskiy res_end = 0; 1937201ed7f3SAlexey Kardashevskiy if (window_size > pe->phb->ioda.m32_pci_base) { 1938201ed7f3SAlexey Kardashevskiy res_start = pe->phb->ioda.m32_pci_base >> tbl->it_page_shift; 1939201ed7f3SAlexey Kardashevskiy res_end = min(window_size, SZ_4G) >> tbl->it_page_shift; 1940201ed7f3SAlexey Kardashevskiy } 1941201ed7f3SAlexey Kardashevskiy iommu_init_table(tbl, pe->phb->hose->node, res_start, res_end); 194246d3e1e1SAlexey Kardashevskiy 194346d3e1e1SAlexey Kardashevskiy rc = pnv_pci_ioda2_set_window(&pe->table_group, 0, tbl); 194446d3e1e1SAlexey Kardashevskiy if (rc) { 194546d3e1e1SAlexey Kardashevskiy pe_err(pe, "Failed to configure 32-bit TCE table, err %ld\n", 194646d3e1e1SAlexey Kardashevskiy rc); 1947e5afdf9dSAlexey Kardashevskiy iommu_tce_table_put(tbl); 194846d3e1e1SAlexey Kardashevskiy return rc; 194946d3e1e1SAlexey Kardashevskiy } 195046d3e1e1SAlexey Kardashevskiy 195146d3e1e1SAlexey Kardashevskiy if (!pnv_iommu_bypass_disabled) 195246d3e1e1SAlexey Kardashevskiy pnv_pci_ioda2_set_bypass(pe, true); 195346d3e1e1SAlexey Kardashevskiy 19545636427dSAlexey Kardashevskiy /* 19555636427dSAlexey Kardashevskiy * Set table base for the case of IOMMU DMA use. Usually this is done 19565636427dSAlexey Kardashevskiy * from dma_dev_setup() which is not called when a device is returned 19575636427dSAlexey Kardashevskiy * from VFIO so do it here. 19585636427dSAlexey Kardashevskiy */ 19595636427dSAlexey Kardashevskiy if (pe->pdev) 19605636427dSAlexey Kardashevskiy set_iommu_table_base(&pe->pdev->dev, tbl); 19615636427dSAlexey Kardashevskiy 196246d3e1e1SAlexey Kardashevskiy return 0; 196346d3e1e1SAlexey Kardashevskiy } 196446d3e1e1SAlexey Kardashevskiy 1965b5926430SAlexey Kardashevskiy static long pnv_pci_ioda2_unset_window(struct iommu_table_group *table_group, 1966b5926430SAlexey Kardashevskiy int num) 1967b5926430SAlexey Kardashevskiy { 1968b5926430SAlexey Kardashevskiy struct pnv_ioda_pe *pe = container_of(table_group, struct pnv_ioda_pe, 1969b5926430SAlexey Kardashevskiy table_group); 1970b5926430SAlexey Kardashevskiy struct pnv_phb *phb = pe->phb; 1971b5926430SAlexey Kardashevskiy long ret; 1972b5926430SAlexey Kardashevskiy 1973b5926430SAlexey Kardashevskiy pe_info(pe, "Removing DMA window #%d\n", num); 1974b5926430SAlexey Kardashevskiy 1975b5926430SAlexey Kardashevskiy ret = opal_pci_map_pe_dma_window(phb->opal_id, pe->pe_number, 1976b5926430SAlexey Kardashevskiy (pe->pe_number << 1) + num, 1977b5926430SAlexey Kardashevskiy 0/* levels */, 0/* table address */, 1978b5926430SAlexey Kardashevskiy 0/* table size */, 0/* page size */); 1979b5926430SAlexey Kardashevskiy if (ret) 1980b5926430SAlexey Kardashevskiy pe_warn(pe, "Unmapping failed, ret = %ld\n", ret); 1981b5926430SAlexey Kardashevskiy else 1982ed7d9a1dSMichael Ellerman pnv_pci_ioda2_tce_invalidate_pe(pe); 1983b5926430SAlexey Kardashevskiy 1984b5926430SAlexey Kardashevskiy pnv_pci_unlink_table_and_group(table_group->tables[num], table_group); 1985b5926430SAlexey Kardashevskiy 1986b5926430SAlexey Kardashevskiy return ret; 1987b5926430SAlexey Kardashevskiy } 1988b5926430SAlexey Kardashevskiy 1989f87a8864SAlexey Kardashevskiy #ifdef CONFIG_IOMMU_API 19900bd97167SAlexey Kardashevskiy unsigned long pnv_pci_ioda2_get_table_size(__u32 page_shift, 199100547193SAlexey Kardashevskiy __u64 window_size, __u32 levels) 199200547193SAlexey Kardashevskiy { 199300547193SAlexey Kardashevskiy unsigned long bytes = 0; 199400547193SAlexey Kardashevskiy const unsigned window_shift = ilog2(window_size); 199500547193SAlexey Kardashevskiy unsigned entries_shift = window_shift - page_shift; 199600547193SAlexey Kardashevskiy unsigned table_shift = entries_shift + 3; 199700547193SAlexey Kardashevskiy unsigned long tce_table_size = max(0x1000UL, 1UL << table_shift); 199800547193SAlexey Kardashevskiy unsigned long direct_table_size; 199900547193SAlexey Kardashevskiy 200000547193SAlexey Kardashevskiy if (!levels || (levels > POWERNV_IOMMU_MAX_LEVELS) || 200100547193SAlexey Kardashevskiy !is_power_of_2(window_size)) 200200547193SAlexey Kardashevskiy return 0; 200300547193SAlexey Kardashevskiy 200400547193SAlexey Kardashevskiy /* Calculate a direct table size from window_size and levels */ 200500547193SAlexey Kardashevskiy entries_shift = (entries_shift + levels - 1) / levels; 200600547193SAlexey Kardashevskiy table_shift = entries_shift + 3; 200700547193SAlexey Kardashevskiy table_shift = max_t(unsigned, table_shift, PAGE_SHIFT); 200800547193SAlexey Kardashevskiy direct_table_size = 1UL << table_shift; 200900547193SAlexey Kardashevskiy 201000547193SAlexey Kardashevskiy for ( ; levels; --levels) { 2011b7115316SChristophe Leroy bytes += ALIGN(tce_table_size, direct_table_size); 201200547193SAlexey Kardashevskiy 201300547193SAlexey Kardashevskiy tce_table_size /= direct_table_size; 201400547193SAlexey Kardashevskiy tce_table_size <<= 3; 2015e49a6a21SAlexey Kardashevskiy tce_table_size = max_t(unsigned long, 2016e49a6a21SAlexey Kardashevskiy tce_table_size, direct_table_size); 201700547193SAlexey Kardashevskiy } 201800547193SAlexey Kardashevskiy 2019090bad39SAlexey Kardashevskiy return bytes + bytes; /* one for HW table, one for userspace copy */ 2020090bad39SAlexey Kardashevskiy } 2021090bad39SAlexey Kardashevskiy 2022090bad39SAlexey Kardashevskiy static long pnv_pci_ioda2_create_table_userspace( 2023090bad39SAlexey Kardashevskiy struct iommu_table_group *table_group, 2024090bad39SAlexey Kardashevskiy int num, __u32 page_shift, __u64 window_size, __u32 levels, 2025090bad39SAlexey Kardashevskiy struct iommu_table **ptbl) 2026090bad39SAlexey Kardashevskiy { 202711f5acceSAlexey Kardashevskiy long ret = pnv_pci_ioda2_create_table(table_group, 2028090bad39SAlexey Kardashevskiy num, page_shift, window_size, levels, true, ptbl); 202911f5acceSAlexey Kardashevskiy 203011f5acceSAlexey Kardashevskiy if (!ret) 203111f5acceSAlexey Kardashevskiy (*ptbl)->it_allocated_size = pnv_pci_ioda2_get_table_size( 203211f5acceSAlexey Kardashevskiy page_shift, window_size, levels); 203311f5acceSAlexey Kardashevskiy return ret; 203400547193SAlexey Kardashevskiy } 203500547193SAlexey Kardashevskiy 2036e3417faeSOliver O'Halloran static void pnv_ioda_setup_bus_dma(struct pnv_ioda_pe *pe, struct pci_bus *bus) 2037e3417faeSOliver O'Halloran { 2038e3417faeSOliver O'Halloran struct pci_dev *dev; 2039e3417faeSOliver O'Halloran 2040e3417faeSOliver O'Halloran list_for_each_entry(dev, &bus->devices, bus_list) { 2041e3417faeSOliver O'Halloran set_iommu_table_base(&dev->dev, pe->table_group.tables[0]); 2042e3417faeSOliver O'Halloran dev->dev.archdata.dma_offset = pe->tce_bypass_base; 2043e3417faeSOliver O'Halloran 2044e3417faeSOliver O'Halloran if ((pe->flags & PNV_IODA_PE_BUS_ALL) && dev->subordinate) 2045e3417faeSOliver O'Halloran pnv_ioda_setup_bus_dma(pe, dev->subordinate); 2046e3417faeSOliver O'Halloran } 2047e3417faeSOliver O'Halloran } 2048e3417faeSOliver O'Halloran 2049f87a8864SAlexey Kardashevskiy static void pnv_ioda2_take_ownership(struct iommu_table_group *table_group) 2050cd15b048SBenjamin Herrenschmidt { 2051f87a8864SAlexey Kardashevskiy struct pnv_ioda_pe *pe = container_of(table_group, struct pnv_ioda_pe, 2052f87a8864SAlexey Kardashevskiy table_group); 205346d3e1e1SAlexey Kardashevskiy /* Store @tbl as pnv_pci_ioda2_unset_window() resets it */ 205446d3e1e1SAlexey Kardashevskiy struct iommu_table *tbl = pe->table_group.tables[0]; 2055cd15b048SBenjamin Herrenschmidt 2056f87a8864SAlexey Kardashevskiy pnv_pci_ioda2_set_bypass(pe, false); 205746d3e1e1SAlexey Kardashevskiy pnv_pci_ioda2_unset_window(&pe->table_group, 0); 2058db08e1d5SAlexey Kardashevskiy if (pe->pbus) 20595eada8a3SAlexey Kardashevskiy pnv_ioda_setup_bus_dma(pe, pe->pbus); 20605636427dSAlexey Kardashevskiy else if (pe->pdev) 20615636427dSAlexey Kardashevskiy set_iommu_table_base(&pe->pdev->dev, NULL); 2062e5afdf9dSAlexey Kardashevskiy iommu_tce_table_put(tbl); 2063cd15b048SBenjamin Herrenschmidt } 2064cd15b048SBenjamin Herrenschmidt 2065f87a8864SAlexey Kardashevskiy static void pnv_ioda2_release_ownership(struct iommu_table_group *table_group) 2066f87a8864SAlexey Kardashevskiy { 2067f87a8864SAlexey Kardashevskiy struct pnv_ioda_pe *pe = container_of(table_group, struct pnv_ioda_pe, 2068f87a8864SAlexey Kardashevskiy table_group); 2069f87a8864SAlexey Kardashevskiy 207046d3e1e1SAlexey Kardashevskiy pnv_pci_ioda2_setup_default_config(pe); 2071db08e1d5SAlexey Kardashevskiy if (pe->pbus) 20725eada8a3SAlexey Kardashevskiy pnv_ioda_setup_bus_dma(pe, pe->pbus); 2073f87a8864SAlexey Kardashevskiy } 2074f87a8864SAlexey Kardashevskiy 2075f87a8864SAlexey Kardashevskiy static struct iommu_table_group_ops pnv_pci_ioda2_ops = { 207600547193SAlexey Kardashevskiy .get_table_size = pnv_pci_ioda2_get_table_size, 2077090bad39SAlexey Kardashevskiy .create_table = pnv_pci_ioda2_create_table_userspace, 20784793d65dSAlexey Kardashevskiy .set_window = pnv_pci_ioda2_set_window, 20794793d65dSAlexey Kardashevskiy .unset_window = pnv_pci_ioda2_unset_window, 2080f87a8864SAlexey Kardashevskiy .take_ownership = pnv_ioda2_take_ownership, 2081f87a8864SAlexey Kardashevskiy .release_ownership = pnv_ioda2_release_ownership, 2082f87a8864SAlexey Kardashevskiy }; 2083f87a8864SAlexey Kardashevskiy #endif 2084f87a8864SAlexey Kardashevskiy 208537b59ef0SOliver O'Halloran void pnv_pci_ioda2_setup_dma_pe(struct pnv_phb *phb, 2086373f5657SGavin Shan struct pnv_ioda_pe *pe) 2087373f5657SGavin Shan { 2088373f5657SGavin Shan int64_t rc; 2089373f5657SGavin Shan 2090f87a8864SAlexey Kardashevskiy /* TVE #1 is selected by PCI address bit 59 */ 2091f87a8864SAlexey Kardashevskiy pe->tce_bypass_base = 1ull << 59; 2092f87a8864SAlexey Kardashevskiy 2093373f5657SGavin Shan /* The PE will reserve all possible 32-bits space */ 2094373f5657SGavin Shan pe_info(pe, "Setting up 32-bit TCE table at 0..%08x\n", 2095aca6913fSAlexey Kardashevskiy phb->ioda.m32_pci_base); 2096373f5657SGavin Shan 2097e5aad1e6SAlexey Kardashevskiy /* Setup linux iommu table */ 20984793d65dSAlexey Kardashevskiy pe->table_group.tce32_start = 0; 20994793d65dSAlexey Kardashevskiy pe->table_group.tce32_size = phb->ioda.m32_pci_base; 21004793d65dSAlexey Kardashevskiy pe->table_group.max_dynamic_windows_supported = 21014793d65dSAlexey Kardashevskiy IOMMU_TABLE_GROUP_MAX_TABLES; 21024793d65dSAlexey Kardashevskiy pe->table_group.max_levels = POWERNV_IOMMU_MAX_LEVELS; 21037ef73cd3SAlexey Kardashevskiy pe->table_group.pgsizes = pnv_ioda_parse_tce_sizes(phb); 2104e5aad1e6SAlexey Kardashevskiy 210546d3e1e1SAlexey Kardashevskiy rc = pnv_pci_ioda2_setup_default_config(pe); 2106801846d1SGavin Shan if (rc) 210746d3e1e1SAlexey Kardashevskiy return; 210846d3e1e1SAlexey Kardashevskiy 21099b9408c5SOliver O'Halloran #ifdef CONFIG_IOMMU_API 21109b9408c5SOliver O'Halloran pe->table_group.ops = &pnv_pci_ioda2_ops; 21119b9408c5SOliver O'Halloran iommu_register_group(&pe->table_group, phb->hose->global_number, 21129b9408c5SOliver O'Halloran pe->pe_number); 21139b9408c5SOliver O'Halloran #endif 211401e12629SOliver O'Halloran pe->dma_setup_done = true; 2115373f5657SGavin Shan } 2116373f5657SGavin Shan 21174ee11c1aSSuresh Warrier int64_t pnv_opal_pci_msi_eoi(struct irq_chip *chip, unsigned int hw_irq) 2118137436c9SGavin Shan { 2119137436c9SGavin Shan struct pnv_phb *phb = container_of(chip, struct pnv_phb, 2120137436c9SGavin Shan ioda.irq_chip); 2121137436c9SGavin Shan 21224ee11c1aSSuresh Warrier return opal_pci_msi_eoi(phb->opal_id, hw_irq); 21234ee11c1aSSuresh Warrier } 21244ee11c1aSSuresh Warrier 21254ee11c1aSSuresh Warrier static void pnv_ioda2_msi_eoi(struct irq_data *d) 21264ee11c1aSSuresh Warrier { 21274ee11c1aSSuresh Warrier int64_t rc; 21284ee11c1aSSuresh Warrier unsigned int hw_irq = (unsigned int)irqd_to_hwirq(d); 21294ee11c1aSSuresh Warrier struct irq_chip *chip = irq_data_get_irq_chip(d); 21304ee11c1aSSuresh Warrier 21314ee11c1aSSuresh Warrier rc = pnv_opal_pci_msi_eoi(chip, hw_irq); 2132137436c9SGavin Shan WARN_ON_ONCE(rc); 2133137436c9SGavin Shan 2134137436c9SGavin Shan icp_native_eoi(d); 2135137436c9SGavin Shan } 2136137436c9SGavin Shan 2137fd9a1c26SIan Munsie 2138f456834aSIan Munsie void pnv_set_msi_irq_chip(struct pnv_phb *phb, unsigned int virq) 2139fd9a1c26SIan Munsie { 2140fd9a1c26SIan Munsie struct irq_data *idata; 2141fd9a1c26SIan Munsie struct irq_chip *ichip; 2142fd9a1c26SIan Munsie 2143fb111334SBenjamin Herrenschmidt /* The MSI EOI OPAL call is only needed on PHB3 */ 2144fb111334SBenjamin Herrenschmidt if (phb->model != PNV_PHB_MODEL_PHB3) 2145fd9a1c26SIan Munsie return; 2146fd9a1c26SIan Munsie 2147fd9a1c26SIan Munsie if (!phb->ioda.irq_chip_init) { 2148fd9a1c26SIan Munsie /* 2149fd9a1c26SIan Munsie * First time we setup an MSI IRQ, we need to setup the 2150fd9a1c26SIan Munsie * corresponding IRQ chip to route correctly. 2151fd9a1c26SIan Munsie */ 2152fd9a1c26SIan Munsie idata = irq_get_irq_data(virq); 2153fd9a1c26SIan Munsie ichip = irq_data_get_irq_chip(idata); 2154fd9a1c26SIan Munsie phb->ioda.irq_chip_init = 1; 2155fd9a1c26SIan Munsie phb->ioda.irq_chip = *ichip; 2156fd9a1c26SIan Munsie phb->ioda.irq_chip.irq_eoi = pnv_ioda2_msi_eoi; 2157fd9a1c26SIan Munsie } 2158fd9a1c26SIan Munsie irq_set_chip(virq, &phb->ioda.irq_chip); 2159fd9a1c26SIan Munsie } 2160fd9a1c26SIan Munsie 21614ee11c1aSSuresh Warrier /* 21624ee11c1aSSuresh Warrier * Returns true iff chip is something that we could call 21634ee11c1aSSuresh Warrier * pnv_opal_pci_msi_eoi for. 21644ee11c1aSSuresh Warrier */ 21654ee11c1aSSuresh Warrier bool is_pnv_opal_msi(struct irq_chip *chip) 21664ee11c1aSSuresh Warrier { 21674ee11c1aSSuresh Warrier return chip->irq_eoi == pnv_ioda2_msi_eoi; 21684ee11c1aSSuresh Warrier } 21694ee11c1aSSuresh Warrier EXPORT_SYMBOL_GPL(is_pnv_opal_msi); 21704ee11c1aSSuresh Warrier 2171184cd4a3SBenjamin Herrenschmidt static int pnv_pci_ioda_msi_setup(struct pnv_phb *phb, struct pci_dev *dev, 2172137436c9SGavin Shan unsigned int hwirq, unsigned int virq, 2173137436c9SGavin Shan unsigned int is_64, struct msi_msg *msg) 2174184cd4a3SBenjamin Herrenschmidt { 2175184cd4a3SBenjamin Herrenschmidt struct pnv_ioda_pe *pe = pnv_ioda_get_pe(dev); 2176184cd4a3SBenjamin Herrenschmidt unsigned int xive_num = hwirq - phb->msi_base; 21773a1a4661SBenjamin Herrenschmidt __be32 data; 2178184cd4a3SBenjamin Herrenschmidt int rc; 2179184cd4a3SBenjamin Herrenschmidt 2180184cd4a3SBenjamin Herrenschmidt /* No PE assigned ? bail out ... no MSI for you ! */ 2181184cd4a3SBenjamin Herrenschmidt if (pe == NULL) 2182184cd4a3SBenjamin Herrenschmidt return -ENXIO; 2183184cd4a3SBenjamin Herrenschmidt 2184184cd4a3SBenjamin Herrenschmidt /* Check if we have an MVE */ 2185184cd4a3SBenjamin Herrenschmidt if (pe->mve_number < 0) 2186184cd4a3SBenjamin Herrenschmidt return -ENXIO; 2187184cd4a3SBenjamin Herrenschmidt 2188b72c1f65SBenjamin Herrenschmidt /* Force 32-bit MSI on some broken devices */ 218936074381SBenjamin Herrenschmidt if (dev->no_64bit_msi) 2190b72c1f65SBenjamin Herrenschmidt is_64 = 0; 2191b72c1f65SBenjamin Herrenschmidt 2192184cd4a3SBenjamin Herrenschmidt /* Assign XIVE to PE */ 2193184cd4a3SBenjamin Herrenschmidt rc = opal_pci_set_xive_pe(phb->opal_id, pe->pe_number, xive_num); 2194184cd4a3SBenjamin Herrenschmidt if (rc) { 2195184cd4a3SBenjamin Herrenschmidt pr_warn("%s: OPAL error %d setting XIVE %d PE\n", 2196184cd4a3SBenjamin Herrenschmidt pci_name(dev), rc, xive_num); 2197184cd4a3SBenjamin Herrenschmidt return -EIO; 2198184cd4a3SBenjamin Herrenschmidt } 2199184cd4a3SBenjamin Herrenschmidt 2200184cd4a3SBenjamin Herrenschmidt if (is_64) { 22013a1a4661SBenjamin Herrenschmidt __be64 addr64; 22023a1a4661SBenjamin Herrenschmidt 2203184cd4a3SBenjamin Herrenschmidt rc = opal_get_msi_64(phb->opal_id, pe->mve_number, xive_num, 1, 2204184cd4a3SBenjamin Herrenschmidt &addr64, &data); 2205184cd4a3SBenjamin Herrenschmidt if (rc) { 2206184cd4a3SBenjamin Herrenschmidt pr_warn("%s: OPAL error %d getting 64-bit MSI data\n", 2207184cd4a3SBenjamin Herrenschmidt pci_name(dev), rc); 2208184cd4a3SBenjamin Herrenschmidt return -EIO; 2209184cd4a3SBenjamin Herrenschmidt } 22103a1a4661SBenjamin Herrenschmidt msg->address_hi = be64_to_cpu(addr64) >> 32; 22113a1a4661SBenjamin Herrenschmidt msg->address_lo = be64_to_cpu(addr64) & 0xfffffffful; 2212184cd4a3SBenjamin Herrenschmidt } else { 22133a1a4661SBenjamin Herrenschmidt __be32 addr32; 22143a1a4661SBenjamin Herrenschmidt 2215184cd4a3SBenjamin Herrenschmidt rc = opal_get_msi_32(phb->opal_id, pe->mve_number, xive_num, 1, 2216184cd4a3SBenjamin Herrenschmidt &addr32, &data); 2217184cd4a3SBenjamin Herrenschmidt if (rc) { 2218184cd4a3SBenjamin Herrenschmidt pr_warn("%s: OPAL error %d getting 32-bit MSI data\n", 2219184cd4a3SBenjamin Herrenschmidt pci_name(dev), rc); 2220184cd4a3SBenjamin Herrenschmidt return -EIO; 2221184cd4a3SBenjamin Herrenschmidt } 2222184cd4a3SBenjamin Herrenschmidt msg->address_hi = 0; 22233a1a4661SBenjamin Herrenschmidt msg->address_lo = be32_to_cpu(addr32); 2224184cd4a3SBenjamin Herrenschmidt } 22253a1a4661SBenjamin Herrenschmidt msg->data = be32_to_cpu(data); 2226184cd4a3SBenjamin Herrenschmidt 2227f456834aSIan Munsie pnv_set_msi_irq_chip(phb, virq); 2228137436c9SGavin Shan 2229184cd4a3SBenjamin Herrenschmidt pr_devel("%s: %s-bit MSI on hwirq %x (xive #%d)," 22301f52f176SRussell Currey " address=%x_%08x data=%x PE# %x\n", 2231184cd4a3SBenjamin Herrenschmidt pci_name(dev), is_64 ? "64" : "32", hwirq, xive_num, 2232184cd4a3SBenjamin Herrenschmidt msg->address_hi, msg->address_lo, data, pe->pe_number); 2233184cd4a3SBenjamin Herrenschmidt 2234184cd4a3SBenjamin Herrenschmidt return 0; 2235184cd4a3SBenjamin Herrenschmidt } 2236184cd4a3SBenjamin Herrenschmidt 2237184cd4a3SBenjamin Herrenschmidt static void pnv_pci_init_ioda_msis(struct pnv_phb *phb) 2238184cd4a3SBenjamin Herrenschmidt { 2239fb1b55d6SGavin Shan unsigned int count; 2240184cd4a3SBenjamin Herrenschmidt const __be32 *prop = of_get_property(phb->hose->dn, 2241184cd4a3SBenjamin Herrenschmidt "ibm,opal-msi-ranges", NULL); 2242184cd4a3SBenjamin Herrenschmidt if (!prop) { 2243184cd4a3SBenjamin Herrenschmidt /* BML Fallback */ 2244184cd4a3SBenjamin Herrenschmidt prop = of_get_property(phb->hose->dn, "msi-ranges", NULL); 2245184cd4a3SBenjamin Herrenschmidt } 2246184cd4a3SBenjamin Herrenschmidt if (!prop) 2247184cd4a3SBenjamin Herrenschmidt return; 2248184cd4a3SBenjamin Herrenschmidt 2249184cd4a3SBenjamin Herrenschmidt phb->msi_base = be32_to_cpup(prop); 2250fb1b55d6SGavin Shan count = be32_to_cpup(prop + 1); 2251fb1b55d6SGavin Shan if (msi_bitmap_alloc(&phb->msi_bmp, count, phb->hose->dn)) { 2252184cd4a3SBenjamin Herrenschmidt pr_err("PCI %d: Failed to allocate MSI bitmap !\n", 2253184cd4a3SBenjamin Herrenschmidt phb->hose->global_number); 2254184cd4a3SBenjamin Herrenschmidt return; 2255184cd4a3SBenjamin Herrenschmidt } 2256fb1b55d6SGavin Shan 2257184cd4a3SBenjamin Herrenschmidt phb->msi_setup = pnv_pci_ioda_msi_setup; 2258184cd4a3SBenjamin Herrenschmidt phb->msi32_support = 1; 2259184cd4a3SBenjamin Herrenschmidt pr_info(" Allocated bitmap for %d MSIs (base IRQ 0x%x)\n", 2260fb1b55d6SGavin Shan count, phb->msi_base); 2261184cd4a3SBenjamin Herrenschmidt } 2262184cd4a3SBenjamin Herrenschmidt 226323e79425SGavin Shan static void pnv_ioda_setup_pe_res(struct pnv_ioda_pe *pe, 226423e79425SGavin Shan struct resource *res) 226511685becSGavin Shan { 226623e79425SGavin Shan struct pnv_phb *phb = pe->phb; 226711685becSGavin Shan struct pci_bus_region region; 226823e79425SGavin Shan int index; 226923e79425SGavin Shan int64_t rc; 227011685becSGavin Shan 227123e79425SGavin Shan if (!res || !res->flags || res->start > res->end) 227223e79425SGavin Shan return; 227311685becSGavin Shan 227411685becSGavin Shan if (res->flags & IORESOURCE_IO) { 227511685becSGavin Shan region.start = res->start - phb->ioda.io_pci_base; 227611685becSGavin Shan region.end = res->end - phb->ioda.io_pci_base; 227711685becSGavin Shan index = region.start / phb->ioda.io_segsize; 227811685becSGavin Shan 227992b8f137SGavin Shan while (index < phb->ioda.total_pe_num && 228011685becSGavin Shan region.start <= region.end) { 228111685becSGavin Shan phb->ioda.io_segmap[index] = pe->pe_number; 228211685becSGavin Shan rc = opal_pci_map_pe_mmio_window(phb->opal_id, 228311685becSGavin Shan pe->pe_number, OPAL_IO_WINDOW_TYPE, 0, index); 228411685becSGavin Shan if (rc != OPAL_SUCCESS) { 22851f52f176SRussell Currey pr_err("%s: Error %lld mapping IO segment#%d to PE#%x\n", 228611685becSGavin Shan __func__, rc, index, pe->pe_number); 228711685becSGavin Shan break; 228811685becSGavin Shan } 228911685becSGavin Shan 229011685becSGavin Shan region.start += phb->ioda.io_segsize; 229111685becSGavin Shan index++; 229211685becSGavin Shan } 2293027fa02fSGavin Shan } else if ((res->flags & IORESOURCE_MEM) && 22945958d19aSBenjamin Herrenschmidt !pnv_pci_is_m64(phb, res)) { 229511685becSGavin Shan region.start = res->start - 229623e79425SGavin Shan phb->hose->mem_offset[0] - 229711685becSGavin Shan phb->ioda.m32_pci_base; 229811685becSGavin Shan region.end = res->end - 229923e79425SGavin Shan phb->hose->mem_offset[0] - 230011685becSGavin Shan phb->ioda.m32_pci_base; 230111685becSGavin Shan index = region.start / phb->ioda.m32_segsize; 230211685becSGavin Shan 230392b8f137SGavin Shan while (index < phb->ioda.total_pe_num && 230411685becSGavin Shan region.start <= region.end) { 230511685becSGavin Shan phb->ioda.m32_segmap[index] = pe->pe_number; 230611685becSGavin Shan rc = opal_pci_map_pe_mmio_window(phb->opal_id, 230711685becSGavin Shan pe->pe_number, OPAL_M32_WINDOW_TYPE, 0, index); 230811685becSGavin Shan if (rc != OPAL_SUCCESS) { 23091f52f176SRussell Currey pr_err("%s: Error %lld mapping M32 segment#%d to PE#%x", 231011685becSGavin Shan __func__, rc, index, pe->pe_number); 231111685becSGavin Shan break; 231211685becSGavin Shan } 231311685becSGavin Shan 231411685becSGavin Shan region.start += phb->ioda.m32_segsize; 231511685becSGavin Shan index++; 231611685becSGavin Shan } 231711685becSGavin Shan } 231811685becSGavin Shan } 231923e79425SGavin Shan 232023e79425SGavin Shan /* 232123e79425SGavin Shan * This function is supposed to be called on basis of PE from top 232223e79425SGavin Shan * to bottom style. So the the I/O or MMIO segment assigned to 232303671057SMasahiro Yamada * parent PE could be overridden by its child PEs if necessary. 232423e79425SGavin Shan */ 232523e79425SGavin Shan static void pnv_ioda_setup_pe_seg(struct pnv_ioda_pe *pe) 232623e79425SGavin Shan { 232769d733e7SGavin Shan struct pci_dev *pdev; 232823e79425SGavin Shan int i; 232923e79425SGavin Shan 233023e79425SGavin Shan /* 233123e79425SGavin Shan * NOTE: We only care PCI bus based PE for now. For PCI 233223e79425SGavin Shan * device based PE, for example SRIOV sensitive VF should 233323e79425SGavin Shan * be figured out later. 233423e79425SGavin Shan */ 233523e79425SGavin Shan BUG_ON(!(pe->flags & (PNV_IODA_PE_BUS | PNV_IODA_PE_BUS_ALL))); 233623e79425SGavin Shan 233769d733e7SGavin Shan list_for_each_entry(pdev, &pe->pbus->devices, bus_list) { 233869d733e7SGavin Shan for (i = 0; i <= PCI_ROM_RESOURCE; i++) 233969d733e7SGavin Shan pnv_ioda_setup_pe_res(pe, &pdev->resource[i]); 234069d733e7SGavin Shan 234169d733e7SGavin Shan /* 234269d733e7SGavin Shan * If the PE contains all subordinate PCI buses, the 234369d733e7SGavin Shan * windows of the child bridges should be mapped to 234469d733e7SGavin Shan * the PE as well. 234569d733e7SGavin Shan */ 234669d733e7SGavin Shan if (!(pe->flags & PNV_IODA_PE_BUS_ALL) || !pci_is_bridge(pdev)) 234769d733e7SGavin Shan continue; 234869d733e7SGavin Shan for (i = 0; i < PCI_BRIDGE_RESOURCE_NUM; i++) 234969d733e7SGavin Shan pnv_ioda_setup_pe_res(pe, 235069d733e7SGavin Shan &pdev->resource[PCI_BRIDGE_RESOURCES + i]); 235169d733e7SGavin Shan } 235211685becSGavin Shan } 235311685becSGavin Shan 235498b665daSRussell Currey #ifdef CONFIG_DEBUG_FS 235598b665daSRussell Currey static int pnv_pci_diag_data_set(void *data, u64 val) 235698b665daSRussell Currey { 235722ba7289SOliver O'Halloran struct pnv_phb *phb = data; 235898b665daSRussell Currey s64 ret; 235998b665daSRussell Currey 236098b665daSRussell Currey /* Retrieve the diag data from firmware */ 23615cb1f8fdSRussell Currey ret = opal_pci_get_phb_diag_data2(phb->opal_id, phb->diag_data, 23625cb1f8fdSRussell Currey phb->diag_data_size); 236398b665daSRussell Currey if (ret != OPAL_SUCCESS) 236498b665daSRussell Currey return -EIO; 236598b665daSRussell Currey 236698b665daSRussell Currey /* Print the diag data to the kernel log */ 23675cb1f8fdSRussell Currey pnv_pci_dump_phb_diag_data(phb->hose, phb->diag_data); 236898b665daSRussell Currey return 0; 236998b665daSRussell Currey } 237098b665daSRussell Currey 2371bfa2325eSYueHaibing DEFINE_DEBUGFS_ATTRIBUTE(pnv_pci_diag_data_fops, NULL, pnv_pci_diag_data_set, 2372bfa2325eSYueHaibing "%llu\n"); 237398b665daSRussell Currey 237418697d2bSOliver O'Halloran static int pnv_pci_ioda_pe_dump(void *data, u64 val) 237518697d2bSOliver O'Halloran { 237618697d2bSOliver O'Halloran struct pnv_phb *phb = data; 237718697d2bSOliver O'Halloran int pe_num; 237818697d2bSOliver O'Halloran 237918697d2bSOliver O'Halloran for (pe_num = 0; pe_num < phb->ioda.total_pe_num; pe_num++) { 238018697d2bSOliver O'Halloran struct pnv_ioda_pe *pe = &phb->ioda.pe_array[pe_num]; 238118697d2bSOliver O'Halloran 238218697d2bSOliver O'Halloran if (!test_bit(pe_num, phb->ioda.pe_alloc)) 238318697d2bSOliver O'Halloran continue; 238418697d2bSOliver O'Halloran 238518697d2bSOliver O'Halloran pe_warn(pe, "rid: %04x dev count: %2d flags: %s%s%s%s%s%s\n", 238618697d2bSOliver O'Halloran pe->rid, pe->device_count, 238718697d2bSOliver O'Halloran (pe->flags & PNV_IODA_PE_DEV) ? "dev " : "", 238818697d2bSOliver O'Halloran (pe->flags & PNV_IODA_PE_BUS) ? "bus " : "", 238918697d2bSOliver O'Halloran (pe->flags & PNV_IODA_PE_BUS_ALL) ? "all " : "", 239018697d2bSOliver O'Halloran (pe->flags & PNV_IODA_PE_MASTER) ? "master " : "", 239118697d2bSOliver O'Halloran (pe->flags & PNV_IODA_PE_SLAVE) ? "slave " : "", 239218697d2bSOliver O'Halloran (pe->flags & PNV_IODA_PE_VF) ? "vf " : ""); 239318697d2bSOliver O'Halloran } 239418697d2bSOliver O'Halloran 239518697d2bSOliver O'Halloran return 0; 239618697d2bSOliver O'Halloran } 239718697d2bSOliver O'Halloran 239818697d2bSOliver O'Halloran DEFINE_DEBUGFS_ATTRIBUTE(pnv_pci_ioda_pe_dump_fops, NULL, 239918697d2bSOliver O'Halloran pnv_pci_ioda_pe_dump, "%llu\n"); 240018697d2bSOliver O'Halloran 240198b665daSRussell Currey #endif /* CONFIG_DEBUG_FS */ 240298b665daSRussell Currey 240337c367f2SGavin Shan static void pnv_pci_ioda_create_dbgfs(void) 240437c367f2SGavin Shan { 240537c367f2SGavin Shan #ifdef CONFIG_DEBUG_FS 240637c367f2SGavin Shan struct pci_controller *hose, *tmp; 240737c367f2SGavin Shan struct pnv_phb *phb; 240837c367f2SGavin Shan char name[16]; 240937c367f2SGavin Shan 241037c367f2SGavin Shan list_for_each_entry_safe(hose, tmp, &hose_list, list_node) { 241137c367f2SGavin Shan phb = hose->private_data; 241237c367f2SGavin Shan 2413ccd1c191SGavin Shan /* Notify initialization of PHB done */ 2414ccd1c191SGavin Shan phb->initialized = 1; 2415ccd1c191SGavin Shan 241637c367f2SGavin Shan sprintf(name, "PCI%04x", hose->global_number); 241737c367f2SGavin Shan phb->dbgfs = debugfs_create_dir(name, powerpc_debugfs_root); 241898b665daSRussell Currey 2419bfa2325eSYueHaibing debugfs_create_file_unsafe("dump_diag_regs", 0200, phb->dbgfs, 242022ba7289SOliver O'Halloran phb, &pnv_pci_diag_data_fops); 242118697d2bSOliver O'Halloran debugfs_create_file_unsafe("dump_ioda_pe_state", 0200, phb->dbgfs, 242218697d2bSOliver O'Halloran phb, &pnv_pci_ioda_pe_dump_fops); 242337c367f2SGavin Shan } 242437c367f2SGavin Shan #endif /* CONFIG_DEBUG_FS */ 242537c367f2SGavin Shan } 242637c367f2SGavin Shan 2427db217319SBenjamin Herrenschmidt static void pnv_pci_enable_bridge(struct pci_bus *bus) 2428db217319SBenjamin Herrenschmidt { 2429db217319SBenjamin Herrenschmidt struct pci_dev *dev = bus->self; 2430db217319SBenjamin Herrenschmidt struct pci_bus *child; 2431db217319SBenjamin Herrenschmidt 2432db217319SBenjamin Herrenschmidt /* Empty bus ? bail */ 2433db217319SBenjamin Herrenschmidt if (list_empty(&bus->devices)) 2434db217319SBenjamin Herrenschmidt return; 2435db217319SBenjamin Herrenschmidt 2436db217319SBenjamin Herrenschmidt /* 2437db217319SBenjamin Herrenschmidt * If there's a bridge associated with that bus enable it. This works 2438db217319SBenjamin Herrenschmidt * around races in the generic code if the enabling is done during 2439db217319SBenjamin Herrenschmidt * parallel probing. This can be removed once those races have been 2440db217319SBenjamin Herrenschmidt * fixed. 2441db217319SBenjamin Herrenschmidt */ 2442db217319SBenjamin Herrenschmidt if (dev) { 2443db217319SBenjamin Herrenschmidt int rc = pci_enable_device(dev); 2444db217319SBenjamin Herrenschmidt if (rc) 2445db217319SBenjamin Herrenschmidt pci_err(dev, "Error enabling bridge (%d)\n", rc); 2446db217319SBenjamin Herrenschmidt pci_set_master(dev); 2447db217319SBenjamin Herrenschmidt } 2448db217319SBenjamin Herrenschmidt 2449db217319SBenjamin Herrenschmidt /* Perform the same to child busses */ 2450db217319SBenjamin Herrenschmidt list_for_each_entry(child, &bus->children, node) 2451db217319SBenjamin Herrenschmidt pnv_pci_enable_bridge(child); 2452db217319SBenjamin Herrenschmidt } 2453db217319SBenjamin Herrenschmidt 2454db217319SBenjamin Herrenschmidt static void pnv_pci_enable_bridges(void) 2455db217319SBenjamin Herrenschmidt { 2456db217319SBenjamin Herrenschmidt struct pci_controller *hose; 2457db217319SBenjamin Herrenschmidt 2458db217319SBenjamin Herrenschmidt list_for_each_entry(hose, &hose_list, list_node) 2459db217319SBenjamin Herrenschmidt pnv_pci_enable_bridge(hose->bus); 2460db217319SBenjamin Herrenschmidt } 2461db217319SBenjamin Herrenschmidt 2462cad5cef6SGreg Kroah-Hartman static void pnv_pci_ioda_fixup(void) 2463fb446ad0SGavin Shan { 246403b7bf34SOliver O'Halloran pnv_pci_ioda_setup_nvlink(); 246537c367f2SGavin Shan pnv_pci_ioda_create_dbgfs(); 246637c367f2SGavin Shan 2467db217319SBenjamin Herrenschmidt pnv_pci_enable_bridges(); 2468db217319SBenjamin Herrenschmidt 2469e9cc17d4SGavin Shan #ifdef CONFIG_EEH 2470b9fde58dSBenjamin Herrenschmidt pnv_eeh_post_init(); 2471e9cc17d4SGavin Shan #endif 2472fb446ad0SGavin Shan } 2473fb446ad0SGavin Shan 2474271fd03aSGavin Shan /* 2475271fd03aSGavin Shan * Returns the alignment for I/O or memory windows for P2P 2476271fd03aSGavin Shan * bridges. That actually depends on how PEs are segmented. 2477271fd03aSGavin Shan * For now, we return I/O or M32 segment size for PE sensitive 2478271fd03aSGavin Shan * P2P bridges. Otherwise, the default values (4KiB for I/O, 2479271fd03aSGavin Shan * 1MiB for memory) will be returned. 2480271fd03aSGavin Shan * 2481271fd03aSGavin Shan * The current PCI bus might be put into one PE, which was 2482271fd03aSGavin Shan * create against the parent PCI bridge. For that case, we 2483271fd03aSGavin Shan * needn't enlarge the alignment so that we can save some 2484271fd03aSGavin Shan * resources. 2485271fd03aSGavin Shan */ 2486271fd03aSGavin Shan static resource_size_t pnv_pci_window_alignment(struct pci_bus *bus, 2487271fd03aSGavin Shan unsigned long type) 2488271fd03aSGavin Shan { 24895609ffddSOliver O'Halloran struct pnv_phb *phb = pci_bus_to_pnvhb(bus); 2490271fd03aSGavin Shan int num_pci_bridges = 0; 24915609ffddSOliver O'Halloran struct pci_dev *bridge; 2492271fd03aSGavin Shan 2493271fd03aSGavin Shan bridge = bus->self; 2494271fd03aSGavin Shan while (bridge) { 2495271fd03aSGavin Shan if (pci_pcie_type(bridge) == PCI_EXP_TYPE_PCI_BRIDGE) { 2496271fd03aSGavin Shan num_pci_bridges++; 2497271fd03aSGavin Shan if (num_pci_bridges >= 2) 2498271fd03aSGavin Shan return 1; 2499271fd03aSGavin Shan } 2500271fd03aSGavin Shan 2501271fd03aSGavin Shan bridge = bridge->bus->self; 2502271fd03aSGavin Shan } 2503271fd03aSGavin Shan 25045958d19aSBenjamin Herrenschmidt /* 25055958d19aSBenjamin Herrenschmidt * We fall back to M32 if M64 isn't supported. We enforce the M64 25065958d19aSBenjamin Herrenschmidt * alignment for any 64-bit resource, PCIe doesn't care and 25075958d19aSBenjamin Herrenschmidt * bridges only do 64-bit prefetchable anyway. 25085958d19aSBenjamin Herrenschmidt */ 2509b79331a5SRussell Currey if (phb->ioda.m64_segsize && pnv_pci_is_m64_flags(type)) 2510262af557SGuo Chao return phb->ioda.m64_segsize; 2511271fd03aSGavin Shan if (type & IORESOURCE_MEM) 2512271fd03aSGavin Shan return phb->ioda.m32_segsize; 2513271fd03aSGavin Shan 2514271fd03aSGavin Shan return phb->ioda.io_segsize; 2515271fd03aSGavin Shan } 2516271fd03aSGavin Shan 251740e2a47eSGavin Shan /* 251840e2a47eSGavin Shan * We are updating root port or the upstream port of the 251940e2a47eSGavin Shan * bridge behind the root port with PHB's windows in order 252040e2a47eSGavin Shan * to accommodate the changes on required resources during 252140e2a47eSGavin Shan * PCI (slot) hotplug, which is connected to either root 252240e2a47eSGavin Shan * port or the downstream ports of PCIe switch behind the 252340e2a47eSGavin Shan * root port. 252440e2a47eSGavin Shan */ 252540e2a47eSGavin Shan static void pnv_pci_fixup_bridge_resources(struct pci_bus *bus, 252640e2a47eSGavin Shan unsigned long type) 252740e2a47eSGavin Shan { 252840e2a47eSGavin Shan struct pci_controller *hose = pci_bus_to_host(bus); 252940e2a47eSGavin Shan struct pnv_phb *phb = hose->private_data; 253040e2a47eSGavin Shan struct pci_dev *bridge = bus->self; 253140e2a47eSGavin Shan struct resource *r, *w; 253240e2a47eSGavin Shan bool msi_region = false; 253340e2a47eSGavin Shan int i; 253440e2a47eSGavin Shan 253540e2a47eSGavin Shan /* Check if we need apply fixup to the bridge's windows */ 253640e2a47eSGavin Shan if (!pci_is_root_bus(bridge->bus) && 253740e2a47eSGavin Shan !pci_is_root_bus(bridge->bus->self->bus)) 253840e2a47eSGavin Shan return; 253940e2a47eSGavin Shan 254040e2a47eSGavin Shan /* Fixup the resources */ 254140e2a47eSGavin Shan for (i = 0; i < PCI_BRIDGE_RESOURCE_NUM; i++) { 254240e2a47eSGavin Shan r = &bridge->resource[PCI_BRIDGE_RESOURCES + i]; 254340e2a47eSGavin Shan if (!r->flags || !r->parent) 254440e2a47eSGavin Shan continue; 254540e2a47eSGavin Shan 254640e2a47eSGavin Shan w = NULL; 254740e2a47eSGavin Shan if (r->flags & type & IORESOURCE_IO) 254840e2a47eSGavin Shan w = &hose->io_resource; 25495958d19aSBenjamin Herrenschmidt else if (pnv_pci_is_m64(phb, r) && 255040e2a47eSGavin Shan (type & IORESOURCE_PREFETCH) && 255140e2a47eSGavin Shan phb->ioda.m64_segsize) 255240e2a47eSGavin Shan w = &hose->mem_resources[1]; 255340e2a47eSGavin Shan else if (r->flags & type & IORESOURCE_MEM) { 255440e2a47eSGavin Shan w = &hose->mem_resources[0]; 255540e2a47eSGavin Shan msi_region = true; 255640e2a47eSGavin Shan } 255740e2a47eSGavin Shan 255840e2a47eSGavin Shan r->start = w->start; 255940e2a47eSGavin Shan r->end = w->end; 256040e2a47eSGavin Shan 256140e2a47eSGavin Shan /* The 64KB 32-bits MSI region shouldn't be included in 256240e2a47eSGavin Shan * the 32-bits bridge window. Otherwise, we can see strange 256340e2a47eSGavin Shan * issues. One of them is EEH error observed on Garrison. 256440e2a47eSGavin Shan * 256540e2a47eSGavin Shan * Exclude top 1MB region which is the minimal alignment of 256640e2a47eSGavin Shan * 32-bits bridge window. 256740e2a47eSGavin Shan */ 256840e2a47eSGavin Shan if (msi_region) { 256940e2a47eSGavin Shan r->end += 0x10000; 257040e2a47eSGavin Shan r->end -= 0x100000; 257140e2a47eSGavin Shan } 257240e2a47eSGavin Shan } 257340e2a47eSGavin Shan } 257440e2a47eSGavin Shan 2575dc3d8f85SOliver O'Halloran static void pnv_pci_configure_bus(struct pci_bus *bus) 2576ccd1c191SGavin Shan { 2577ccd1c191SGavin Shan struct pci_dev *bridge = bus->self; 2578ccd1c191SGavin Shan struct pnv_ioda_pe *pe; 2579dc3d8f85SOliver O'Halloran bool all = (bridge && pci_pcie_type(bridge) == PCI_EXP_TYPE_PCI_BRIDGE); 2580ccd1c191SGavin Shan 2581dc3d8f85SOliver O'Halloran dev_info(&bus->dev, "Configuring PE for bus\n"); 258240e2a47eSGavin Shan 2583ccd1c191SGavin Shan /* Don't assign PE to PCI bus, which doesn't have subordinate devices */ 25846ae8aedfSOliver O'Halloran if (WARN_ON(list_empty(&bus->devices))) 2585ccd1c191SGavin Shan return; 2586ccd1c191SGavin Shan 2587ccd1c191SGavin Shan /* Reserve PEs according to used M64 resources */ 2588a25de7afSAlexey Kardashevskiy pnv_ioda_reserve_m64_pe(bus, NULL, all); 2589ccd1c191SGavin Shan 2590ccd1c191SGavin Shan /* 2591ccd1c191SGavin Shan * Assign PE. We might run here because of partial hotplug. 2592ccd1c191SGavin Shan * For the case, we just pick up the existing PE and should 2593ccd1c191SGavin Shan * not allocate resources again. 2594ccd1c191SGavin Shan */ 2595ccd1c191SGavin Shan pe = pnv_ioda_setup_bus_PE(bus, all); 2596ccd1c191SGavin Shan if (!pe) 2597ccd1c191SGavin Shan return; 2598ccd1c191SGavin Shan 2599ccd1c191SGavin Shan pnv_ioda_setup_pe_seg(pe); 2600ccd1c191SGavin Shan } 2601ccd1c191SGavin Shan 260238274637SYongji Xie static resource_size_t pnv_pci_default_alignment(void) 260338274637SYongji Xie { 260438274637SYongji Xie return PAGE_SIZE; 260538274637SYongji Xie } 260638274637SYongji Xie 2607184cd4a3SBenjamin Herrenschmidt /* Prevent enabling devices for which we couldn't properly 2608184cd4a3SBenjamin Herrenschmidt * assign a PE 2609184cd4a3SBenjamin Herrenschmidt */ 26108bf6b91aSAlastair D'Silva static bool pnv_pci_enable_device_hook(struct pci_dev *dev) 2611184cd4a3SBenjamin Herrenschmidt { 26125609ffddSOliver O'Halloran struct pnv_phb *phb = pci_bus_to_pnvhb(dev->bus); 2613db1266c8SGavin Shan struct pci_dn *pdn; 2614184cd4a3SBenjamin Herrenschmidt 2615db1266c8SGavin Shan /* The function is probably called while the PEs have 2616db1266c8SGavin Shan * not be created yet. For example, resource reassignment 2617db1266c8SGavin Shan * during PCI probe period. We just skip the check if 2618db1266c8SGavin Shan * PEs isn't ready. 2619db1266c8SGavin Shan */ 2620db1266c8SGavin Shan if (!phb->initialized) 2621c88c2a18SDaniel Axtens return true; 2622db1266c8SGavin Shan 2623b72c1f65SBenjamin Herrenschmidt pdn = pci_get_pdn(dev); 2624184cd4a3SBenjamin Herrenschmidt if (!pdn || pdn->pe_number == IODA_INVALID_PE) 2625c88c2a18SDaniel Axtens return false; 2626db1266c8SGavin Shan 2627c88c2a18SDaniel Axtens return true; 2628184cd4a3SBenjamin Herrenschmidt } 2629184cd4a3SBenjamin Herrenschmidt 2630c1a2feadSFrederic Barrat static bool pnv_ocapi_enable_device_hook(struct pci_dev *dev) 2631c1a2feadSFrederic Barrat { 2632c1a2feadSFrederic Barrat struct pci_controller *hose = pci_bus_to_host(dev->bus); 2633c1a2feadSFrederic Barrat struct pnv_phb *phb = hose->private_data; 2634c1a2feadSFrederic Barrat struct pci_dn *pdn; 2635c1a2feadSFrederic Barrat struct pnv_ioda_pe *pe; 2636c1a2feadSFrederic Barrat 2637c1a2feadSFrederic Barrat if (!phb->initialized) 2638c1a2feadSFrederic Barrat return true; 2639c1a2feadSFrederic Barrat 2640c1a2feadSFrederic Barrat pdn = pci_get_pdn(dev); 2641c1a2feadSFrederic Barrat if (!pdn) 2642c1a2feadSFrederic Barrat return false; 2643c1a2feadSFrederic Barrat 2644c1a2feadSFrederic Barrat if (pdn->pe_number == IODA_INVALID_PE) { 2645c1a2feadSFrederic Barrat pe = pnv_ioda_setup_dev_PE(dev); 2646c1a2feadSFrederic Barrat if (!pe) 2647c1a2feadSFrederic Barrat return false; 2648c1a2feadSFrederic Barrat } 2649c1a2feadSFrederic Barrat return true; 2650c1a2feadSFrederic Barrat } 2651c1a2feadSFrederic Barrat 2652c5f7700bSGavin Shan static long pnv_pci_ioda1_unset_window(struct iommu_table_group *table_group, 2653c5f7700bSGavin Shan int num) 2654c5f7700bSGavin Shan { 2655c5f7700bSGavin Shan struct pnv_ioda_pe *pe = container_of(table_group, 2656c5f7700bSGavin Shan struct pnv_ioda_pe, table_group); 2657c5f7700bSGavin Shan struct pnv_phb *phb = pe->phb; 2658c5f7700bSGavin Shan unsigned int idx; 2659c5f7700bSGavin Shan long rc; 2660c5f7700bSGavin Shan 2661c5f7700bSGavin Shan pe_info(pe, "Removing DMA window #%d\n", num); 2662c5f7700bSGavin Shan for (idx = 0; idx < phb->ioda.dma32_count; idx++) { 2663c5f7700bSGavin Shan if (phb->ioda.dma32_segmap[idx] != pe->pe_number) 2664c5f7700bSGavin Shan continue; 2665c5f7700bSGavin Shan 2666c5f7700bSGavin Shan rc = opal_pci_map_pe_dma_window(phb->opal_id, pe->pe_number, 2667c5f7700bSGavin Shan idx, 0, 0ul, 0ul, 0ul); 2668c5f7700bSGavin Shan if (rc != OPAL_SUCCESS) { 2669c5f7700bSGavin Shan pe_warn(pe, "Failure %ld unmapping DMA32 segment#%d\n", 2670c5f7700bSGavin Shan rc, idx); 2671c5f7700bSGavin Shan return rc; 2672c5f7700bSGavin Shan } 2673c5f7700bSGavin Shan 2674c5f7700bSGavin Shan phb->ioda.dma32_segmap[idx] = IODA_INVALID_PE; 2675c5f7700bSGavin Shan } 2676c5f7700bSGavin Shan 2677c5f7700bSGavin Shan pnv_pci_unlink_table_and_group(table_group->tables[num], table_group); 2678c5f7700bSGavin Shan return OPAL_SUCCESS; 2679c5f7700bSGavin Shan } 2680c5f7700bSGavin Shan 2681c5f7700bSGavin Shan static void pnv_pci_ioda1_release_pe_dma(struct pnv_ioda_pe *pe) 2682c5f7700bSGavin Shan { 2683c5f7700bSGavin Shan struct iommu_table *tbl = pe->table_group.tables[0]; 2684c5f7700bSGavin Shan int64_t rc; 2685c5f7700bSGavin Shan 268601e12629SOliver O'Halloran if (!pe->dma_setup_done) 2687c5f7700bSGavin Shan return; 2688c5f7700bSGavin Shan 2689c5f7700bSGavin Shan rc = pnv_pci_ioda1_unset_window(&pe->table_group, 0); 2690c5f7700bSGavin Shan if (rc != OPAL_SUCCESS) 2691c5f7700bSGavin Shan return; 2692c5f7700bSGavin Shan 2693a34ab7c3SBenjamin Herrenschmidt pnv_pci_p7ioc_tce_invalidate(tbl, tbl->it_offset, tbl->it_size, false); 2694c5f7700bSGavin Shan if (pe->table_group.group) { 2695c5f7700bSGavin Shan iommu_group_put(pe->table_group.group); 2696c5f7700bSGavin Shan WARN_ON(pe->table_group.group); 2697c5f7700bSGavin Shan } 2698c5f7700bSGavin Shan 2699c5f7700bSGavin Shan free_pages(tbl->it_base, get_order(tbl->it_size << 3)); 2700e5afdf9dSAlexey Kardashevskiy iommu_tce_table_put(tbl); 2701c5f7700bSGavin Shan } 2702c5f7700bSGavin Shan 270337b59ef0SOliver O'Halloran void pnv_pci_ioda2_release_pe_dma(struct pnv_ioda_pe *pe) 2704c5f7700bSGavin Shan { 2705c5f7700bSGavin Shan struct iommu_table *tbl = pe->table_group.tables[0]; 2706c5f7700bSGavin Shan int64_t rc; 2707c5f7700bSGavin Shan 270801e12629SOliver O'Halloran if (pe->dma_setup_done) 2709c5f7700bSGavin Shan return; 2710c5f7700bSGavin Shan 2711c5f7700bSGavin Shan rc = pnv_pci_ioda2_unset_window(&pe->table_group, 0); 2712c5f7700bSGavin Shan if (rc) 27131e496391SJoe Perches pe_warn(pe, "OPAL error %lld release DMA window\n", rc); 2714c5f7700bSGavin Shan 2715c5f7700bSGavin Shan pnv_pci_ioda2_set_bypass(pe, false); 2716c5f7700bSGavin Shan if (pe->table_group.group) { 2717c5f7700bSGavin Shan iommu_group_put(pe->table_group.group); 2718c5f7700bSGavin Shan WARN_ON(pe->table_group.group); 2719c5f7700bSGavin Shan } 2720c5f7700bSGavin Shan 2721e5afdf9dSAlexey Kardashevskiy iommu_tce_table_put(tbl); 2722c5f7700bSGavin Shan } 2723c5f7700bSGavin Shan 2724c5f7700bSGavin Shan static void pnv_ioda_free_pe_seg(struct pnv_ioda_pe *pe, 2725c5f7700bSGavin Shan unsigned short win, 2726c5f7700bSGavin Shan unsigned int *map) 2727c5f7700bSGavin Shan { 2728c5f7700bSGavin Shan struct pnv_phb *phb = pe->phb; 2729c5f7700bSGavin Shan int idx; 2730c5f7700bSGavin Shan int64_t rc; 2731c5f7700bSGavin Shan 2732c5f7700bSGavin Shan for (idx = 0; idx < phb->ioda.total_pe_num; idx++) { 2733c5f7700bSGavin Shan if (map[idx] != pe->pe_number) 2734c5f7700bSGavin Shan continue; 2735c5f7700bSGavin Shan 2736c5f7700bSGavin Shan rc = opal_pci_map_pe_mmio_window(phb->opal_id, 2737c5f7700bSGavin Shan phb->ioda.reserved_pe_idx, win, 0, idx); 2738c5f7700bSGavin Shan 2739c5f7700bSGavin Shan if (rc != OPAL_SUCCESS) 27401e496391SJoe Perches pe_warn(pe, "Error %lld unmapping (%d) segment#%d\n", 2741c5f7700bSGavin Shan rc, win, idx); 2742c5f7700bSGavin Shan 2743c5f7700bSGavin Shan map[idx] = IODA_INVALID_PE; 2744c5f7700bSGavin Shan } 2745c5f7700bSGavin Shan } 2746c5f7700bSGavin Shan 2747c5f7700bSGavin Shan static void pnv_ioda_release_pe_seg(struct pnv_ioda_pe *pe) 2748c5f7700bSGavin Shan { 2749c5f7700bSGavin Shan struct pnv_phb *phb = pe->phb; 2750c5f7700bSGavin Shan 2751c5f7700bSGavin Shan if (phb->type == PNV_PHB_IODA1) { 2752c5f7700bSGavin Shan pnv_ioda_free_pe_seg(pe, OPAL_IO_WINDOW_TYPE, 2753c5f7700bSGavin Shan phb->ioda.io_segmap); 2754c5f7700bSGavin Shan pnv_ioda_free_pe_seg(pe, OPAL_M32_WINDOW_TYPE, 2755c5f7700bSGavin Shan phb->ioda.m32_segmap); 275636963365SOliver O'Halloran /* M64 is pre-configured by pnv_ioda1_init_m64() */ 2757c5f7700bSGavin Shan } else if (phb->type == PNV_PHB_IODA2) { 2758c5f7700bSGavin Shan pnv_ioda_free_pe_seg(pe, OPAL_M32_WINDOW_TYPE, 2759c5f7700bSGavin Shan phb->ioda.m32_segmap); 2760c5f7700bSGavin Shan } 2761c5f7700bSGavin Shan } 2762c5f7700bSGavin Shan 2763c5f7700bSGavin Shan static void pnv_ioda_release_pe(struct pnv_ioda_pe *pe) 2764c5f7700bSGavin Shan { 2765c5f7700bSGavin Shan struct pnv_phb *phb = pe->phb; 2766c5f7700bSGavin Shan struct pnv_ioda_pe *slave, *tmp; 2767c5f7700bSGavin Shan 2768e5500ab6SOliver O'Halloran pe_info(pe, "Releasing PE\n"); 2769e5500ab6SOliver O'Halloran 277080f1ff83SFrederic Barrat mutex_lock(&phb->ioda.pe_list_mutex); 2771c5f7700bSGavin Shan list_del(&pe->list); 277280f1ff83SFrederic Barrat mutex_unlock(&phb->ioda.pe_list_mutex); 277380f1ff83SFrederic Barrat 2774c5f7700bSGavin Shan switch (phb->type) { 2775c5f7700bSGavin Shan case PNV_PHB_IODA1: 2776c5f7700bSGavin Shan pnv_pci_ioda1_release_pe_dma(pe); 2777c5f7700bSGavin Shan break; 2778c5f7700bSGavin Shan case PNV_PHB_IODA2: 2779c5f7700bSGavin Shan pnv_pci_ioda2_release_pe_dma(pe); 2780c5f7700bSGavin Shan break; 2781f724385fSFrederic Barrat case PNV_PHB_NPU_OCAPI: 2782f724385fSFrederic Barrat break; 2783c5f7700bSGavin Shan default: 2784c5f7700bSGavin Shan WARN_ON(1); 2785c5f7700bSGavin Shan } 2786c5f7700bSGavin Shan 2787c5f7700bSGavin Shan pnv_ioda_release_pe_seg(pe); 2788c5f7700bSGavin Shan pnv_ioda_deconfigure_pe(pe->phb, pe); 2789b314427aSGavin Shan 2790b314427aSGavin Shan /* Release slave PEs in the compound PE */ 2791b314427aSGavin Shan if (pe->flags & PNV_IODA_PE_MASTER) { 2792b314427aSGavin Shan list_for_each_entry_safe(slave, tmp, &pe->slaves, list) { 2793b314427aSGavin Shan list_del(&slave->list); 2794b314427aSGavin Shan pnv_ioda_free_pe(slave); 2795b314427aSGavin Shan } 2796b314427aSGavin Shan } 2797b314427aSGavin Shan 27986eaed166SGavin Shan /* 27996eaed166SGavin Shan * The PE for root bus can be removed because of hotplug in EEH 28006eaed166SGavin Shan * recovery for fenced PHB error. We need to mark the PE dead so 28016eaed166SGavin Shan * that it can be populated again in PCI hot add path. The PE 28026eaed166SGavin Shan * shouldn't be destroyed as it's the global reserved resource. 28036eaed166SGavin Shan */ 2804718d249aSOliver O'Halloran if (phb->ioda.root_pe_idx == pe->pe_number) 2805718d249aSOliver O'Halloran return; 2806718d249aSOliver O'Halloran 2807c5f7700bSGavin Shan pnv_ioda_free_pe(pe); 2808c5f7700bSGavin Shan } 2809c5f7700bSGavin Shan 2810c5f7700bSGavin Shan static void pnv_pci_release_device(struct pci_dev *pdev) 2811c5f7700bSGavin Shan { 28125609ffddSOliver O'Halloran struct pnv_phb *phb = pci_bus_to_pnvhb(pdev->bus); 2813c5f7700bSGavin Shan struct pci_dn *pdn = pci_get_pdn(pdev); 2814c5f7700bSGavin Shan struct pnv_ioda_pe *pe; 2815c5f7700bSGavin Shan 281637b59ef0SOliver O'Halloran /* The VF PE state is torn down when sriov_disable() is called */ 2817c5f7700bSGavin Shan if (pdev->is_virtfn) 2818c5f7700bSGavin Shan return; 2819c5f7700bSGavin Shan 2820c5f7700bSGavin Shan if (!pdn || pdn->pe_number == IODA_INVALID_PE) 2821c5f7700bSGavin Shan return; 2822c5f7700bSGavin Shan 282337b59ef0SOliver O'Halloran #ifdef CONFIG_PCI_IOV 282437b59ef0SOliver O'Halloran /* 282537b59ef0SOliver O'Halloran * FIXME: Try move this to sriov_disable(). It's here since we allocate 282637b59ef0SOliver O'Halloran * the iov state at probe time since we need to fiddle with the IOV 282737b59ef0SOliver O'Halloran * resources. 282837b59ef0SOliver O'Halloran */ 282937b59ef0SOliver O'Halloran if (pdev->is_physfn) 283037b59ef0SOliver O'Halloran kfree(pdev->dev.archdata.iov_data); 283137b59ef0SOliver O'Halloran #endif 283237b59ef0SOliver O'Halloran 283329bf282dSGavin Shan /* 283429bf282dSGavin Shan * PCI hotplug can happen as part of EEH error recovery. The @pdn 283529bf282dSGavin Shan * isn't removed and added afterwards in this scenario. We should 283629bf282dSGavin Shan * set the PE number in @pdn to an invalid one. Otherwise, the PE's 283729bf282dSGavin Shan * device count is decreased on removing devices while failing to 283829bf282dSGavin Shan * be increased on adding devices. It leads to unbalanced PE's device 283929bf282dSGavin Shan * count and eventually make normal PCI hotplug path broken. 284029bf282dSGavin Shan */ 2841c5f7700bSGavin Shan pe = &phb->ioda.pe_array[pdn->pe_number]; 284229bf282dSGavin Shan pdn->pe_number = IODA_INVALID_PE; 284329bf282dSGavin Shan 2844c5f7700bSGavin Shan WARN_ON(--pe->device_count < 0); 2845c5f7700bSGavin Shan if (pe->device_count == 0) 2846c5f7700bSGavin Shan pnv_ioda_release_pe(pe); 2847c5f7700bSGavin Shan } 2848c5f7700bSGavin Shan 2849ab7032e7SAlexey Kardashevskiy static void pnv_npu_disable_device(struct pci_dev *pdev) 2850ab7032e7SAlexey Kardashevskiy { 2851ab7032e7SAlexey Kardashevskiy struct eeh_dev *edev = pci_dev_to_eeh_dev(pdev); 2852ab7032e7SAlexey Kardashevskiy struct eeh_pe *eehpe = edev ? edev->pe : NULL; 2853ab7032e7SAlexey Kardashevskiy 2854ab7032e7SAlexey Kardashevskiy if (eehpe && eeh_ops && eeh_ops->reset) 2855ab7032e7SAlexey Kardashevskiy eeh_ops->reset(eehpe, EEH_RESET_HOT); 2856ab7032e7SAlexey Kardashevskiy } 2857ab7032e7SAlexey Kardashevskiy 28587a8e6bbfSMichael Neuling static void pnv_pci_ioda_shutdown(struct pci_controller *hose) 285973ed148aSBenjamin Herrenschmidt { 28607a8e6bbfSMichael Neuling struct pnv_phb *phb = hose->private_data; 28617a8e6bbfSMichael Neuling 2862d1a85eeeSGavin Shan opal_pci_reset(phb->opal_id, OPAL_RESET_PCI_IODA_TABLE, 286373ed148aSBenjamin Herrenschmidt OPAL_ASSERT_RESET); 286473ed148aSBenjamin Herrenschmidt } 286573ed148aSBenjamin Herrenschmidt 2866946743d0SOliver O'Halloran static void pnv_pci_ioda_dma_bus_setup(struct pci_bus *bus) 2867946743d0SOliver O'Halloran { 28685609ffddSOliver O'Halloran struct pnv_phb *phb = pci_bus_to_pnvhb(bus); 2869946743d0SOliver O'Halloran struct pnv_ioda_pe *pe; 2870946743d0SOliver O'Halloran 2871946743d0SOliver O'Halloran list_for_each_entry(pe, &phb->ioda.pe_list, list) { 2872946743d0SOliver O'Halloran if (!(pe->flags & (PNV_IODA_PE_BUS | PNV_IODA_PE_BUS_ALL))) 2873946743d0SOliver O'Halloran continue; 2874946743d0SOliver O'Halloran 2875946743d0SOliver O'Halloran if (!pe->pbus) 2876946743d0SOliver O'Halloran continue; 2877946743d0SOliver O'Halloran 2878946743d0SOliver O'Halloran if (bus->number == ((pe->rid >> 8) & 0xFF)) { 2879946743d0SOliver O'Halloran pe->pbus = bus; 2880946743d0SOliver O'Halloran break; 2881946743d0SOliver O'Halloran } 2882946743d0SOliver O'Halloran } 2883946743d0SOliver O'Halloran } 2884946743d0SOliver O'Halloran 288592ae0353SDaniel Axtens static const struct pci_controller_ops pnv_pci_ioda_controller_ops = { 28860a25d9c4SOliver O'Halloran .dma_dev_setup = pnv_pci_ioda_dma_dev_setup, 2887946743d0SOliver O'Halloran .dma_bus_setup = pnv_pci_ioda_dma_bus_setup, 28882d6ad41bSChristoph Hellwig .iommu_bypass_supported = pnv_pci_ioda_iommu_bypass_supported, 288992ae0353SDaniel Axtens .setup_msi_irqs = pnv_setup_msi_irqs, 289092ae0353SDaniel Axtens .teardown_msi_irqs = pnv_teardown_msi_irqs, 289192ae0353SDaniel Axtens .enable_device_hook = pnv_pci_enable_device_hook, 2892c5f7700bSGavin Shan .release_device = pnv_pci_release_device, 289392ae0353SDaniel Axtens .window_alignment = pnv_pci_window_alignment, 2894dc3d8f85SOliver O'Halloran .setup_bridge = pnv_pci_fixup_bridge_resources, 289592ae0353SDaniel Axtens .reset_secondary_bus = pnv_pci_reset_secondary_bus, 28967a8e6bbfSMichael Neuling .shutdown = pnv_pci_ioda_shutdown, 289792ae0353SDaniel Axtens }; 289892ae0353SDaniel Axtens 28995d2aa710SAlistair Popple static const struct pci_controller_ops pnv_npu_ioda_controller_ops = { 29005d2aa710SAlistair Popple .setup_msi_irqs = pnv_setup_msi_irqs, 29015d2aa710SAlistair Popple .teardown_msi_irqs = pnv_teardown_msi_irqs, 29025d2aa710SAlistair Popple .enable_device_hook = pnv_pci_enable_device_hook, 29035d2aa710SAlistair Popple .window_alignment = pnv_pci_window_alignment, 29045d2aa710SAlistair Popple .reset_secondary_bus = pnv_pci_reset_secondary_bus, 29055d2aa710SAlistair Popple .shutdown = pnv_pci_ioda_shutdown, 2906ab7032e7SAlexey Kardashevskiy .disable_device = pnv_npu_disable_device, 29075d2aa710SAlistair Popple }; 29085d2aa710SAlistair Popple 29097f2c39e9SFrederic Barrat static const struct pci_controller_ops pnv_npu_ocapi_ioda_controller_ops = { 2910c1a2feadSFrederic Barrat .enable_device_hook = pnv_ocapi_enable_device_hook, 2911f724385fSFrederic Barrat .release_device = pnv_pci_release_device, 29127f2c39e9SFrederic Barrat .window_alignment = pnv_pci_window_alignment, 29137f2c39e9SFrederic Barrat .reset_secondary_bus = pnv_pci_reset_secondary_bus, 29147f2c39e9SFrederic Barrat .shutdown = pnv_pci_ioda_shutdown, 29157f2c39e9SFrederic Barrat }; 29167f2c39e9SFrederic Barrat 2917e51df2c1SAnton Blanchard static void __init pnv_pci_init_ioda_phb(struct device_node *np, 2918e9cc17d4SGavin Shan u64 hub_id, int ioda_type) 2919184cd4a3SBenjamin Herrenschmidt { 2920184cd4a3SBenjamin Herrenschmidt struct pci_controller *hose; 2921184cd4a3SBenjamin Herrenschmidt struct pnv_phb *phb; 29222b923ed1SGavin Shan unsigned long size, m64map_off, m32map_off, pemap_off; 29232b923ed1SGavin Shan unsigned long iomap_off = 0, dma32map_off = 0; 2924718d249aSOliver O'Halloran struct pnv_ioda_pe *root_pe; 2925fd141d1aSBenjamin Herrenschmidt struct resource r; 2926c681b93cSAlistair Popple const __be64 *prop64; 29273a1a4661SBenjamin Herrenschmidt const __be32 *prop32; 2928f1b7cc3eSGavin Shan int len; 29293fa23ff8SGavin Shan unsigned int segno; 2930184cd4a3SBenjamin Herrenschmidt u64 phb_id; 2931184cd4a3SBenjamin Herrenschmidt void *aux; 2932184cd4a3SBenjamin Herrenschmidt long rc; 2933184cd4a3SBenjamin Herrenschmidt 293408a45b32SBenjamin Herrenschmidt if (!of_device_is_available(np)) 293508a45b32SBenjamin Herrenschmidt return; 293608a45b32SBenjamin Herrenschmidt 2937b7c670d6SRob Herring pr_info("Initializing %s PHB (%pOF)\n", pnv_phb_names[ioda_type], np); 2938184cd4a3SBenjamin Herrenschmidt 2939184cd4a3SBenjamin Herrenschmidt prop64 = of_get_property(np, "ibm,opal-phbid", NULL); 2940184cd4a3SBenjamin Herrenschmidt if (!prop64) { 2941184cd4a3SBenjamin Herrenschmidt pr_err(" Missing \"ibm,opal-phbid\" property !\n"); 2942184cd4a3SBenjamin Herrenschmidt return; 2943184cd4a3SBenjamin Herrenschmidt } 2944184cd4a3SBenjamin Herrenschmidt phb_id = be64_to_cpup(prop64); 2945184cd4a3SBenjamin Herrenschmidt pr_debug(" PHB-ID : 0x%016llx\n", phb_id); 2946184cd4a3SBenjamin Herrenschmidt 29477e1c4e27SMike Rapoport phb = memblock_alloc(sizeof(*phb), SMP_CACHE_BYTES); 29488a7f97b9SMike Rapoport if (!phb) 29498a7f97b9SMike Rapoport panic("%s: Failed to allocate %zu bytes\n", __func__, 29508a7f97b9SMike Rapoport sizeof(*phb)); 295158d714ecSGavin Shan 295258d714ecSGavin Shan /* Allocate PCI controller */ 2953184cd4a3SBenjamin Herrenschmidt phb->hose = hose = pcibios_alloc_controller(np); 295458d714ecSGavin Shan if (!phb->hose) { 2955b7c670d6SRob Herring pr_err(" Can't allocate PCI controller for %pOF\n", 2956b7c670d6SRob Herring np); 2957e39f223fSMichael Ellerman memblock_free(__pa(phb), sizeof(struct pnv_phb)); 2958184cd4a3SBenjamin Herrenschmidt return; 2959184cd4a3SBenjamin Herrenschmidt } 2960184cd4a3SBenjamin Herrenschmidt 2961184cd4a3SBenjamin Herrenschmidt spin_lock_init(&phb->lock); 2962f1b7cc3eSGavin Shan prop32 = of_get_property(np, "bus-range", &len); 2963f1b7cc3eSGavin Shan if (prop32 && len == 8) { 29643a1a4661SBenjamin Herrenschmidt hose->first_busno = be32_to_cpu(prop32[0]); 29653a1a4661SBenjamin Herrenschmidt hose->last_busno = be32_to_cpu(prop32[1]); 2966f1b7cc3eSGavin Shan } else { 2967b7c670d6SRob Herring pr_warn(" Broken <bus-range> on %pOF\n", np); 2968184cd4a3SBenjamin Herrenschmidt hose->first_busno = 0; 2969184cd4a3SBenjamin Herrenschmidt hose->last_busno = 0xff; 2970f1b7cc3eSGavin Shan } 2971184cd4a3SBenjamin Herrenschmidt hose->private_data = phb; 2972e9cc17d4SGavin Shan phb->hub_id = hub_id; 2973184cd4a3SBenjamin Herrenschmidt phb->opal_id = phb_id; 2974aa0c033fSGavin Shan phb->type = ioda_type; 2975781a868fSWei Yang mutex_init(&phb->ioda.pe_alloc_mutex); 2976184cd4a3SBenjamin Herrenschmidt 2977cee72d5bSBenjamin Herrenschmidt /* Detect specific models for error handling */ 2978cee72d5bSBenjamin Herrenschmidt if (of_device_is_compatible(np, "ibm,p7ioc-pciex")) 2979cee72d5bSBenjamin Herrenschmidt phb->model = PNV_PHB_MODEL_P7IOC; 2980f3d40c25SBenjamin Herrenschmidt else if (of_device_is_compatible(np, "ibm,power8-pciex")) 2981aa0c033fSGavin Shan phb->model = PNV_PHB_MODEL_PHB3; 29825d2aa710SAlistair Popple else if (of_device_is_compatible(np, "ibm,power8-npu-pciex")) 29835d2aa710SAlistair Popple phb->model = PNV_PHB_MODEL_NPU; 2984616badd2SAlistair Popple else if (of_device_is_compatible(np, "ibm,power9-npu-pciex")) 2985616badd2SAlistair Popple phb->model = PNV_PHB_MODEL_NPU2; 2986cee72d5bSBenjamin Herrenschmidt else 2987cee72d5bSBenjamin Herrenschmidt phb->model = PNV_PHB_MODEL_UNKNOWN; 2988cee72d5bSBenjamin Herrenschmidt 29895cb1f8fdSRussell Currey /* Initialize diagnostic data buffer */ 29905cb1f8fdSRussell Currey prop32 = of_get_property(np, "ibm,phb-diag-data-size", NULL); 29915cb1f8fdSRussell Currey if (prop32) 29925cb1f8fdSRussell Currey phb->diag_data_size = be32_to_cpup(prop32); 29935cb1f8fdSRussell Currey else 29945cb1f8fdSRussell Currey phb->diag_data_size = PNV_PCI_DIAG_BUF_SIZE; 29955cb1f8fdSRussell Currey 29967e1c4e27SMike Rapoport phb->diag_data = memblock_alloc(phb->diag_data_size, SMP_CACHE_BYTES); 29978a7f97b9SMike Rapoport if (!phb->diag_data) 29988a7f97b9SMike Rapoport panic("%s: Failed to allocate %u bytes\n", __func__, 29998a7f97b9SMike Rapoport phb->diag_data_size); 30005cb1f8fdSRussell Currey 3001aa0c033fSGavin Shan /* Parse 32-bit and IO ranges (if any) */ 30022f1ec02eSGavin Shan pci_process_bridge_OF_ranges(hose, np, !hose->global_number); 3003184cd4a3SBenjamin Herrenschmidt 3004aa0c033fSGavin Shan /* Get registers */ 3005fd141d1aSBenjamin Herrenschmidt if (!of_address_to_resource(np, 0, &r)) { 3006fd141d1aSBenjamin Herrenschmidt phb->regs_phys = r.start; 3007fd141d1aSBenjamin Herrenschmidt phb->regs = ioremap(r.start, resource_size(&r)); 3008184cd4a3SBenjamin Herrenschmidt if (phb->regs == NULL) 3009184cd4a3SBenjamin Herrenschmidt pr_err(" Failed to map registers !\n"); 3010fd141d1aSBenjamin Herrenschmidt } 3011577c8c88SGavin Shan 3012184cd4a3SBenjamin Herrenschmidt /* Initialize more IODA stuff */ 301392b8f137SGavin Shan phb->ioda.total_pe_num = 1; 301436954dc7SGavin Shan prop32 = of_get_property(np, "ibm,opal-num-pes", NULL); 301536954dc7SGavin Shan if (prop32) 301692b8f137SGavin Shan phb->ioda.total_pe_num = be32_to_cpup(prop32); 301736954dc7SGavin Shan prop32 = of_get_property(np, "ibm,opal-reserved-pe", NULL); 301836954dc7SGavin Shan if (prop32) 301992b8f137SGavin Shan phb->ioda.reserved_pe_idx = be32_to_cpup(prop32); 3020262af557SGuo Chao 3021c127562aSGavin Shan /* Invalidate RID to PE# mapping */ 3022c127562aSGavin Shan for (segno = 0; segno < ARRAY_SIZE(phb->ioda.pe_rmap); segno++) 3023c127562aSGavin Shan phb->ioda.pe_rmap[segno] = IODA_INVALID_PE; 3024c127562aSGavin Shan 3025262af557SGuo Chao /* Parse 64-bit MMIO range */ 3026262af557SGuo Chao pnv_ioda_parse_m64_window(phb); 3027262af557SGuo Chao 3028184cd4a3SBenjamin Herrenschmidt phb->ioda.m32_size = resource_size(&hose->mem_resources[0]); 3029aa0c033fSGavin Shan /* FW Has already off top 64k of M32 space (MSI space) */ 3030184cd4a3SBenjamin Herrenschmidt phb->ioda.m32_size += 0x10000; 3031184cd4a3SBenjamin Herrenschmidt 303292b8f137SGavin Shan phb->ioda.m32_segsize = phb->ioda.m32_size / phb->ioda.total_pe_num; 30333fd47f06SBenjamin Herrenschmidt phb->ioda.m32_pci_base = hose->mem_resources[0].start - hose->mem_offset[0]; 3034184cd4a3SBenjamin Herrenschmidt phb->ioda.io_size = hose->pci_io_size; 303592b8f137SGavin Shan phb->ioda.io_segsize = phb->ioda.io_size / phb->ioda.total_pe_num; 3036184cd4a3SBenjamin Herrenschmidt phb->ioda.io_pci_base = 0; /* XXX calculate this ? */ 3037184cd4a3SBenjamin Herrenschmidt 30382b923ed1SGavin Shan /* Calculate how many 32-bit TCE segments we have */ 30392b923ed1SGavin Shan phb->ioda.dma32_count = phb->ioda.m32_pci_base / 30402b923ed1SGavin Shan PNV_IODA1_DMA32_SEGSIZE; 30412b923ed1SGavin Shan 3042c35d2a8cSGavin Shan /* Allocate aux data & arrays. We don't have IO ports on PHB3 */ 3043b7115316SChristophe Leroy size = ALIGN(max_t(unsigned, phb->ioda.total_pe_num, 8) / 8, 304492a86756SAlexey Kardashevskiy sizeof(unsigned long)); 304593289d8cSGavin Shan m64map_off = size; 304693289d8cSGavin Shan size += phb->ioda.total_pe_num * sizeof(phb->ioda.m64_segmap[0]); 3047184cd4a3SBenjamin Herrenschmidt m32map_off = size; 304892b8f137SGavin Shan size += phb->ioda.total_pe_num * sizeof(phb->ioda.m32_segmap[0]); 3049c35d2a8cSGavin Shan if (phb->type == PNV_PHB_IODA1) { 3050c35d2a8cSGavin Shan iomap_off = size; 305192b8f137SGavin Shan size += phb->ioda.total_pe_num * sizeof(phb->ioda.io_segmap[0]); 30522b923ed1SGavin Shan dma32map_off = size; 30532b923ed1SGavin Shan size += phb->ioda.dma32_count * 30542b923ed1SGavin Shan sizeof(phb->ioda.dma32_segmap[0]); 3055c35d2a8cSGavin Shan } 3056184cd4a3SBenjamin Herrenschmidt pemap_off = size; 305792b8f137SGavin Shan size += phb->ioda.total_pe_num * sizeof(struct pnv_ioda_pe); 30587e1c4e27SMike Rapoport aux = memblock_alloc(size, SMP_CACHE_BYTES); 30598a7f97b9SMike Rapoport if (!aux) 30608a7f97b9SMike Rapoport panic("%s: Failed to allocate %lu bytes\n", __func__, size); 3061184cd4a3SBenjamin Herrenschmidt phb->ioda.pe_alloc = aux; 306293289d8cSGavin Shan phb->ioda.m64_segmap = aux + m64map_off; 3063184cd4a3SBenjamin Herrenschmidt phb->ioda.m32_segmap = aux + m32map_off; 306493289d8cSGavin Shan for (segno = 0; segno < phb->ioda.total_pe_num; segno++) { 306593289d8cSGavin Shan phb->ioda.m64_segmap[segno] = IODA_INVALID_PE; 30663fa23ff8SGavin Shan phb->ioda.m32_segmap[segno] = IODA_INVALID_PE; 306793289d8cSGavin Shan } 30683fa23ff8SGavin Shan if (phb->type == PNV_PHB_IODA1) { 3069184cd4a3SBenjamin Herrenschmidt phb->ioda.io_segmap = aux + iomap_off; 30703fa23ff8SGavin Shan for (segno = 0; segno < phb->ioda.total_pe_num; segno++) 30713fa23ff8SGavin Shan phb->ioda.io_segmap[segno] = IODA_INVALID_PE; 30722b923ed1SGavin Shan 30732b923ed1SGavin Shan phb->ioda.dma32_segmap = aux + dma32map_off; 30742b923ed1SGavin Shan for (segno = 0; segno < phb->ioda.dma32_count; segno++) 30752b923ed1SGavin Shan phb->ioda.dma32_segmap[segno] = IODA_INVALID_PE; 30763fa23ff8SGavin Shan } 3077184cd4a3SBenjamin Herrenschmidt phb->ioda.pe_array = aux + pemap_off; 307863803c39SGavin Shan 307963803c39SGavin Shan /* 308063803c39SGavin Shan * Choose PE number for root bus, which shouldn't have 308163803c39SGavin Shan * M64 resources consumed by its child devices. To pick 308263803c39SGavin Shan * the PE number adjacent to the reserved one if possible. 308363803c39SGavin Shan */ 308463803c39SGavin Shan pnv_ioda_reserve_pe(phb, phb->ioda.reserved_pe_idx); 308563803c39SGavin Shan if (phb->ioda.reserved_pe_idx == 0) { 308663803c39SGavin Shan phb->ioda.root_pe_idx = 1; 308763803c39SGavin Shan pnv_ioda_reserve_pe(phb, phb->ioda.root_pe_idx); 308863803c39SGavin Shan } else if (phb->ioda.reserved_pe_idx == (phb->ioda.total_pe_num - 1)) { 308963803c39SGavin Shan phb->ioda.root_pe_idx = phb->ioda.reserved_pe_idx - 1; 309063803c39SGavin Shan pnv_ioda_reserve_pe(phb, phb->ioda.root_pe_idx); 309163803c39SGavin Shan } else { 3092718d249aSOliver O'Halloran /* otherwise just allocate one */ 3093a4bc676eSOliver O'Halloran root_pe = pnv_ioda_alloc_pe(phb, 1); 3094718d249aSOliver O'Halloran phb->ioda.root_pe_idx = root_pe->pe_number; 309563803c39SGavin Shan } 3096184cd4a3SBenjamin Herrenschmidt 3097184cd4a3SBenjamin Herrenschmidt INIT_LIST_HEAD(&phb->ioda.pe_list); 3098781a868fSWei Yang mutex_init(&phb->ioda.pe_list_mutex); 3099184cd4a3SBenjamin Herrenschmidt 3100184cd4a3SBenjamin Herrenschmidt /* Calculate how many 32-bit TCE segments we have */ 31012b923ed1SGavin Shan phb->ioda.dma32_count = phb->ioda.m32_pci_base / 3102acce971cSGavin Shan PNV_IODA1_DMA32_SEGSIZE; 3103184cd4a3SBenjamin Herrenschmidt 3104aa0c033fSGavin Shan #if 0 /* We should really do that ... */ 3105184cd4a3SBenjamin Herrenschmidt rc = opal_pci_set_phb_mem_window(opal->phb_id, 3106184cd4a3SBenjamin Herrenschmidt window_type, 3107184cd4a3SBenjamin Herrenschmidt window_num, 3108184cd4a3SBenjamin Herrenschmidt starting_real_address, 3109184cd4a3SBenjamin Herrenschmidt starting_pci_address, 3110184cd4a3SBenjamin Herrenschmidt segment_size); 3111184cd4a3SBenjamin Herrenschmidt #endif 3112184cd4a3SBenjamin Herrenschmidt 3113262af557SGuo Chao pr_info(" %03d (%03d) PE's M32: 0x%x [segment=0x%x]\n", 311492b8f137SGavin Shan phb->ioda.total_pe_num, phb->ioda.reserved_pe_idx, 3115262af557SGuo Chao phb->ioda.m32_size, phb->ioda.m32_segsize); 3116262af557SGuo Chao if (phb->ioda.m64_size) 3117262af557SGuo Chao pr_info(" M64: 0x%lx [segment=0x%lx]\n", 3118262af557SGuo Chao phb->ioda.m64_size, phb->ioda.m64_segsize); 3119262af557SGuo Chao if (phb->ioda.io_size) 3120262af557SGuo Chao pr_info(" IO: 0x%x [segment=0x%x]\n", 3121184cd4a3SBenjamin Herrenschmidt phb->ioda.io_size, phb->ioda.io_segsize); 3122184cd4a3SBenjamin Herrenschmidt 3123262af557SGuo Chao 3124184cd4a3SBenjamin Herrenschmidt phb->hose->ops = &pnv_pci_ops; 312549dec922SGavin Shan phb->get_pe_state = pnv_ioda_get_pe_state; 312649dec922SGavin Shan phb->freeze_pe = pnv_ioda_freeze_pe; 312749dec922SGavin Shan phb->unfreeze_pe = pnv_ioda_unfreeze_pe; 3128184cd4a3SBenjamin Herrenschmidt 3129184cd4a3SBenjamin Herrenschmidt /* Setup MSI support */ 3130184cd4a3SBenjamin Herrenschmidt pnv_pci_init_ioda_msis(phb); 3131184cd4a3SBenjamin Herrenschmidt 3132c40a4210SGavin Shan /* 3133c40a4210SGavin Shan * We pass the PCI probe flag PCI_REASSIGN_ALL_RSRC here 3134c40a4210SGavin Shan * to let the PCI core do resource assignment. It's supposed 3135c40a4210SGavin Shan * that the PCI core will do correct I/O and MMIO alignment 3136c40a4210SGavin Shan * for the P2P bridge bars so that each PCI bus (excluding 3137c40a4210SGavin Shan * the child P2P bridges) can form individual PE. 3138184cd4a3SBenjamin Herrenschmidt */ 3139fb446ad0SGavin Shan ppc_md.pcibios_fixup = pnv_pci_ioda_fixup; 31405d2aa710SAlistair Popple 31417f2c39e9SFrederic Barrat switch (phb->type) { 31427f2c39e9SFrederic Barrat case PNV_PHB_NPU_NVLINK: 31435d2aa710SAlistair Popple hose->controller_ops = pnv_npu_ioda_controller_ops; 31447f2c39e9SFrederic Barrat break; 31457f2c39e9SFrederic Barrat case PNV_PHB_NPU_OCAPI: 31467f2c39e9SFrederic Barrat hose->controller_ops = pnv_npu_ocapi_ioda_controller_ops; 31477f2c39e9SFrederic Barrat break; 31487f2c39e9SFrederic Barrat default: 314992ae0353SDaniel Axtens hose->controller_ops = pnv_pci_ioda_controller_ops; 3150f9f83456SAlexey Kardashevskiy } 3151ad30cb99SMichael Ellerman 315238274637SYongji Xie ppc_md.pcibios_default_alignment = pnv_pci_default_alignment; 315338274637SYongji Xie 31546e628c7dSWei Yang #ifdef CONFIG_PCI_IOV 3155965c94f3SOliver O'Halloran ppc_md.pcibios_fixup_sriov = pnv_pci_ioda_fixup_iov; 31565350ab3fSWei Yang ppc_md.pcibios_iov_resource_alignment = pnv_pci_iov_resource_alignment; 3157988fc3baSBryant G. Ly ppc_md.pcibios_sriov_enable = pnv_pcibios_sriov_enable; 3158988fc3baSBryant G. Ly ppc_md.pcibios_sriov_disable = pnv_pcibios_sriov_disable; 3159ad30cb99SMichael Ellerman #endif 3160ad30cb99SMichael Ellerman 3161c40a4210SGavin Shan pci_add_flags(PCI_REASSIGN_ALL_RSRC); 3162184cd4a3SBenjamin Herrenschmidt 3163184cd4a3SBenjamin Herrenschmidt /* Reset IODA tables to a clean state */ 3164d1a85eeeSGavin Shan rc = opal_pci_reset(phb_id, OPAL_RESET_PCI_IODA_TABLE, OPAL_ASSERT_RESET); 3165184cd4a3SBenjamin Herrenschmidt if (rc) 3166f2c2cbccSJoe Perches pr_warn(" OPAL Error %ld performing IODA table reset !\n", rc); 3167361f2a2aSGavin Shan 31686060e9eaSAndrew Donnellan /* 31696060e9eaSAndrew Donnellan * If we're running in kdump kernel, the previous kernel never 3170361f2a2aSGavin Shan * shutdown PCI devices correctly. We already got IODA table 3171361f2a2aSGavin Shan * cleaned out. So we have to issue PHB reset to stop all PCI 317245baee14SGuilherme G. Piccoli * transactions from previous kernel. The ppc_pci_reset_phbs 3173b174b4fbSOliver O'Halloran * kernel parameter will force this reset too. Additionally, 3174b174b4fbSOliver O'Halloran * if the IODA reset above failed then use a bigger hammer. 3175b174b4fbSOliver O'Halloran * This can happen if we get a PHB fatal error in very early 3176b174b4fbSOliver O'Halloran * boot. 3177361f2a2aSGavin Shan */ 3178b174b4fbSOliver O'Halloran if (is_kdump_kernel() || pci_reset_phbs || rc) { 3179361f2a2aSGavin Shan pr_info(" Issue PHB reset ...\n"); 3180cadf364dSGavin Shan pnv_eeh_phb_reset(hose, EEH_RESET_FUNDAMENTAL); 3181cadf364dSGavin Shan pnv_eeh_phb_reset(hose, EEH_RESET_DEACTIVATE); 3182361f2a2aSGavin Shan } 3183262af557SGuo Chao 31849e9e8935SGavin Shan /* Remove M64 resource if we can't configure it successfully */ 31859e9e8935SGavin Shan if (!phb->init_m64 || phb->init_m64(phb)) 3186262af557SGuo Chao hose->mem_resources[1].flags = 0; 3187184cd4a3SBenjamin Herrenschmidt } 3188184cd4a3SBenjamin Herrenschmidt 318967975005SBjorn Helgaas void __init pnv_pci_init_ioda2_phb(struct device_node *np) 3190aa0c033fSGavin Shan { 3191e9cc17d4SGavin Shan pnv_pci_init_ioda_phb(np, 0, PNV_PHB_IODA2); 3192aa0c033fSGavin Shan } 3193aa0c033fSGavin Shan 31945d2aa710SAlistair Popple void __init pnv_pci_init_npu_phb(struct device_node *np) 31955d2aa710SAlistair Popple { 31967f2c39e9SFrederic Barrat pnv_pci_init_ioda_phb(np, 0, PNV_PHB_NPU_NVLINK); 31975d2aa710SAlistair Popple } 31985d2aa710SAlistair Popple 31997f2c39e9SFrederic Barrat void __init pnv_pci_init_npu2_opencapi_phb(struct device_node *np) 32007f2c39e9SFrederic Barrat { 32017f2c39e9SFrederic Barrat pnv_pci_init_ioda_phb(np, 0, PNV_PHB_NPU_OCAPI); 3202184cd4a3SBenjamin Herrenschmidt } 3203184cd4a3SBenjamin Herrenschmidt 3204228c2f41SAndrew Donnellan static void pnv_npu2_opencapi_cfg_size_fixup(struct pci_dev *dev) 3205228c2f41SAndrew Donnellan { 32065609ffddSOliver O'Halloran struct pnv_phb *phb = pci_bus_to_pnvhb(dev->bus); 3207228c2f41SAndrew Donnellan 3208228c2f41SAndrew Donnellan if (!machine_is(powernv)) 3209228c2f41SAndrew Donnellan return; 3210228c2f41SAndrew Donnellan 3211228c2f41SAndrew Donnellan if (phb->type == PNV_PHB_NPU_OCAPI) 3212228c2f41SAndrew Donnellan dev->cfg_size = PCI_CFG_SPACE_EXP_SIZE; 3213228c2f41SAndrew Donnellan } 3214228c2f41SAndrew Donnellan DECLARE_PCI_FIXUP_EARLY(PCI_ANY_ID, PCI_ANY_ID, pnv_npu2_opencapi_cfg_size_fixup); 3215228c2f41SAndrew Donnellan 3216184cd4a3SBenjamin Herrenschmidt void __init pnv_pci_init_ioda_hub(struct device_node *np) 3217184cd4a3SBenjamin Herrenschmidt { 3218184cd4a3SBenjamin Herrenschmidt struct device_node *phbn; 3219184cd4a3SBenjamin Herrenschmidt const __be64 *prop64; 3220184cd4a3SBenjamin Herrenschmidt u64 hub_id; 3221184cd4a3SBenjamin Herrenschmidt 3222b7c670d6SRob Herring pr_info("Probing IODA IO-Hub %pOF\n", np); 3223184cd4a3SBenjamin Herrenschmidt 3224184cd4a3SBenjamin Herrenschmidt prop64 = of_get_property(np, "ibm,opal-hubid", NULL); 3225184cd4a3SBenjamin Herrenschmidt if (!prop64) { 3226184cd4a3SBenjamin Herrenschmidt pr_err(" Missing \"ibm,opal-hubid\" property !\n"); 3227184cd4a3SBenjamin Herrenschmidt return; 3228184cd4a3SBenjamin Herrenschmidt } 3229184cd4a3SBenjamin Herrenschmidt hub_id = be64_to_cpup(prop64); 3230184cd4a3SBenjamin Herrenschmidt pr_devel(" HUB-ID : 0x%016llx\n", hub_id); 3231184cd4a3SBenjamin Herrenschmidt 3232184cd4a3SBenjamin Herrenschmidt /* Count child PHBs */ 3233184cd4a3SBenjamin Herrenschmidt for_each_child_of_node(np, phbn) { 3234184cd4a3SBenjamin Herrenschmidt /* Look for IODA1 PHBs */ 3235184cd4a3SBenjamin Herrenschmidt if (of_device_is_compatible(phbn, "ibm,ioda-phb")) 3236184cd4a3SBenjamin Herrenschmidt pnv_pci_init_ioda_phb(phbn, hub_id, PNV_PHB_IODA1); 3237184cd4a3SBenjamin Herrenschmidt } 3238184cd4a3SBenjamin Herrenschmidt } 3239