1184cd4a3SBenjamin Herrenschmidt /* 2184cd4a3SBenjamin Herrenschmidt * Support PCI/PCIe on PowerNV platforms 3184cd4a3SBenjamin Herrenschmidt * 4184cd4a3SBenjamin Herrenschmidt * Copyright 2011 Benjamin Herrenschmidt, IBM Corp. 5184cd4a3SBenjamin Herrenschmidt * 6184cd4a3SBenjamin Herrenschmidt * This program is free software; you can redistribute it and/or 7184cd4a3SBenjamin Herrenschmidt * modify it under the terms of the GNU General Public License 8184cd4a3SBenjamin Herrenschmidt * as published by the Free Software Foundation; either version 9184cd4a3SBenjamin Herrenschmidt * 2 of the License, or (at your option) any later version. 10184cd4a3SBenjamin Herrenschmidt */ 11184cd4a3SBenjamin Herrenschmidt 12cee72d5bSBenjamin Herrenschmidt #undef DEBUG 13184cd4a3SBenjamin Herrenschmidt 14184cd4a3SBenjamin Herrenschmidt #include <linux/kernel.h> 15184cd4a3SBenjamin Herrenschmidt #include <linux/pci.h> 16361f2a2aSGavin Shan #include <linux/crash_dump.h> 17184cd4a3SBenjamin Herrenschmidt #include <linux/delay.h> 18184cd4a3SBenjamin Herrenschmidt #include <linux/string.h> 19184cd4a3SBenjamin Herrenschmidt #include <linux/init.h> 20184cd4a3SBenjamin Herrenschmidt #include <linux/bootmem.h> 21184cd4a3SBenjamin Herrenschmidt #include <linux/irq.h> 22184cd4a3SBenjamin Herrenschmidt #include <linux/io.h> 23184cd4a3SBenjamin Herrenschmidt #include <linux/msi.h> 24cd15b048SBenjamin Herrenschmidt #include <linux/memblock.h> 25ac9a5889SAlexey Kardashevskiy #include <linux/iommu.h> 26e57080f1SAlexey Kardashevskiy #include <linux/rculist.h> 274793d65dSAlexey Kardashevskiy #include <linux/sizes.h> 28184cd4a3SBenjamin Herrenschmidt 29184cd4a3SBenjamin Herrenschmidt #include <asm/sections.h> 30184cd4a3SBenjamin Herrenschmidt #include <asm/io.h> 31184cd4a3SBenjamin Herrenschmidt #include <asm/prom.h> 32184cd4a3SBenjamin Herrenschmidt #include <asm/pci-bridge.h> 33184cd4a3SBenjamin Herrenschmidt #include <asm/machdep.h> 34fb1b55d6SGavin Shan #include <asm/msi_bitmap.h> 35184cd4a3SBenjamin Herrenschmidt #include <asm/ppc-pci.h> 36184cd4a3SBenjamin Herrenschmidt #include <asm/opal.h> 37184cd4a3SBenjamin Herrenschmidt #include <asm/iommu.h> 38184cd4a3SBenjamin Herrenschmidt #include <asm/tce.h> 39137436c9SGavin Shan #include <asm/xics.h> 407644d581SMichael Ellerman #include <asm/debugfs.h> 41262af557SGuo Chao #include <asm/firmware.h> 4280c49c7eSIan Munsie #include <asm/pnv-pci.h> 43aca6913fSAlexey Kardashevskiy #include <asm/mmzone.h> 4480c49c7eSIan Munsie 45ec249dd8SMichael Neuling #include <misc/cxl-base.h> 46184cd4a3SBenjamin Herrenschmidt 47184cd4a3SBenjamin Herrenschmidt #include "powernv.h" 48184cd4a3SBenjamin Herrenschmidt #include "pci.h" 49184cd4a3SBenjamin Herrenschmidt 5099451551SGavin Shan #define PNV_IODA1_M64_NUM 16 /* Number of M64 BARs */ 5199451551SGavin Shan #define PNV_IODA1_M64_SEGS 8 /* Segments per M64 BAR */ 52acce971cSGavin Shan #define PNV_IODA1_DMA32_SEGSIZE 0x10000000 53781a868fSWei Yang 54bbb845c4SAlexey Kardashevskiy #define POWERNV_IOMMU_DEFAULT_LEVELS 1 55bbb845c4SAlexey Kardashevskiy #define POWERNV_IOMMU_MAX_LEVELS 5 56bbb845c4SAlexey Kardashevskiy 579497a1c1SGavin Shan static const char * const pnv_phb_names[] = { "IODA1", "IODA2", "NPU" }; 58aca6913fSAlexey Kardashevskiy static void pnv_pci_ioda2_table_free_pages(struct iommu_table *tbl); 59aca6913fSAlexey Kardashevskiy 607d623e42SAlexey Kardashevskiy void pe_level_printk(const struct pnv_ioda_pe *pe, const char *level, 616d31c2faSJoe Perches const char *fmt, ...) 626d31c2faSJoe Perches { 636d31c2faSJoe Perches struct va_format vaf; 646d31c2faSJoe Perches va_list args; 656d31c2faSJoe Perches char pfix[32]; 66184cd4a3SBenjamin Herrenschmidt 676d31c2faSJoe Perches va_start(args, fmt); 686d31c2faSJoe Perches 696d31c2faSJoe Perches vaf.fmt = fmt; 706d31c2faSJoe Perches vaf.va = &args; 716d31c2faSJoe Perches 72781a868fSWei Yang if (pe->flags & PNV_IODA_PE_DEV) 736d31c2faSJoe Perches strlcpy(pfix, dev_name(&pe->pdev->dev), sizeof(pfix)); 74781a868fSWei Yang else if (pe->flags & (PNV_IODA_PE_BUS | PNV_IODA_PE_BUS_ALL)) 756d31c2faSJoe Perches sprintf(pfix, "%04x:%02x ", 766d31c2faSJoe Perches pci_domain_nr(pe->pbus), pe->pbus->number); 77781a868fSWei Yang #ifdef CONFIG_PCI_IOV 78781a868fSWei Yang else if (pe->flags & PNV_IODA_PE_VF) 79781a868fSWei Yang sprintf(pfix, "%04x:%02x:%2x.%d", 80781a868fSWei Yang pci_domain_nr(pe->parent_dev->bus), 81781a868fSWei Yang (pe->rid & 0xff00) >> 8, 82781a868fSWei Yang PCI_SLOT(pe->rid), PCI_FUNC(pe->rid)); 83781a868fSWei Yang #endif /* CONFIG_PCI_IOV*/ 846d31c2faSJoe Perches 851f52f176SRussell Currey printk("%spci %s: [PE# %.2x] %pV", 866d31c2faSJoe Perches level, pfix, pe->pe_number, &vaf); 876d31c2faSJoe Perches 886d31c2faSJoe Perches va_end(args); 896d31c2faSJoe Perches } 906d31c2faSJoe Perches 914e287840SThadeu Lima de Souza Cascardo static bool pnv_iommu_bypass_disabled __read_mostly; 924e287840SThadeu Lima de Souza Cascardo 934e287840SThadeu Lima de Souza Cascardo static int __init iommu_setup(char *str) 944e287840SThadeu Lima de Souza Cascardo { 954e287840SThadeu Lima de Souza Cascardo if (!str) 964e287840SThadeu Lima de Souza Cascardo return -EINVAL; 974e287840SThadeu Lima de Souza Cascardo 984e287840SThadeu Lima de Souza Cascardo while (*str) { 994e287840SThadeu Lima de Souza Cascardo if (!strncmp(str, "nobypass", 8)) { 1004e287840SThadeu Lima de Souza Cascardo pnv_iommu_bypass_disabled = true; 1014e287840SThadeu Lima de Souza Cascardo pr_info("PowerNV: IOMMU bypass window disabled.\n"); 1024e287840SThadeu Lima de Souza Cascardo break; 1034e287840SThadeu Lima de Souza Cascardo } 1044e287840SThadeu Lima de Souza Cascardo str += strcspn(str, ","); 1054e287840SThadeu Lima de Souza Cascardo if (*str == ',') 1064e287840SThadeu Lima de Souza Cascardo str++; 1074e287840SThadeu Lima de Souza Cascardo } 1084e287840SThadeu Lima de Souza Cascardo 1094e287840SThadeu Lima de Souza Cascardo return 0; 1104e287840SThadeu Lima de Souza Cascardo } 1114e287840SThadeu Lima de Souza Cascardo early_param("iommu", iommu_setup); 1124e287840SThadeu Lima de Souza Cascardo 1135958d19aSBenjamin Herrenschmidt static inline bool pnv_pci_is_m64(struct pnv_phb *phb, struct resource *r) 114262af557SGuo Chao { 1155958d19aSBenjamin Herrenschmidt /* 1165958d19aSBenjamin Herrenschmidt * WARNING: We cannot rely on the resource flags. The Linux PCI 1175958d19aSBenjamin Herrenschmidt * allocation code sometimes decides to put a 64-bit prefetchable 1185958d19aSBenjamin Herrenschmidt * BAR in the 32-bit window, so we have to compare the addresses. 1195958d19aSBenjamin Herrenschmidt * 1205958d19aSBenjamin Herrenschmidt * For simplicity we only test resource start. 1215958d19aSBenjamin Herrenschmidt */ 1225958d19aSBenjamin Herrenschmidt return (r->start >= phb->ioda.m64_base && 1235958d19aSBenjamin Herrenschmidt r->start < (phb->ioda.m64_base + phb->ioda.m64_size)); 124262af557SGuo Chao } 125262af557SGuo Chao 126b79331a5SRussell Currey static inline bool pnv_pci_is_m64_flags(unsigned long resource_flags) 127b79331a5SRussell Currey { 128b79331a5SRussell Currey unsigned long flags = (IORESOURCE_MEM_64 | IORESOURCE_PREFETCH); 129b79331a5SRussell Currey 130b79331a5SRussell Currey return (resource_flags & flags) == flags; 131b79331a5SRussell Currey } 132b79331a5SRussell Currey 1331e916772SGavin Shan static struct pnv_ioda_pe *pnv_ioda_init_pe(struct pnv_phb *phb, int pe_no) 1341e916772SGavin Shan { 135313483ddSGavin Shan s64 rc; 136313483ddSGavin Shan 1371e916772SGavin Shan phb->ioda.pe_array[pe_no].phb = phb; 1381e916772SGavin Shan phb->ioda.pe_array[pe_no].pe_number = pe_no; 1391e916772SGavin Shan 140313483ddSGavin Shan /* 141313483ddSGavin Shan * Clear the PE frozen state as it might be put into frozen state 142313483ddSGavin Shan * in the last PCI remove path. It's not harmful to do so when the 143313483ddSGavin Shan * PE is already in unfrozen state. 144313483ddSGavin Shan */ 145313483ddSGavin Shan rc = opal_pci_eeh_freeze_clear(phb->opal_id, pe_no, 146313483ddSGavin Shan OPAL_EEH_ACTION_CLEAR_FREEZE_ALL); 147d4791db5SRussell Currey if (rc != OPAL_SUCCESS && rc != OPAL_UNSUPPORTED) 1481f52f176SRussell Currey pr_warn("%s: Error %lld unfreezing PHB#%x-PE#%x\n", 149313483ddSGavin Shan __func__, rc, phb->hose->global_number, pe_no); 150313483ddSGavin Shan 1511e916772SGavin Shan return &phb->ioda.pe_array[pe_no]; 1521e916772SGavin Shan } 1531e916772SGavin Shan 1544b82ab18SGavin Shan static void pnv_ioda_reserve_pe(struct pnv_phb *phb, int pe_no) 1554b82ab18SGavin Shan { 15692b8f137SGavin Shan if (!(pe_no >= 0 && pe_no < phb->ioda.total_pe_num)) { 1571f52f176SRussell Currey pr_warn("%s: Invalid PE %x on PHB#%x\n", 1584b82ab18SGavin Shan __func__, pe_no, phb->hose->global_number); 1594b82ab18SGavin Shan return; 1604b82ab18SGavin Shan } 1614b82ab18SGavin Shan 162e9dc4d7fSGavin Shan if (test_and_set_bit(pe_no, phb->ioda.pe_alloc)) 1631f52f176SRussell Currey pr_debug("%s: PE %x was reserved on PHB#%x\n", 1644b82ab18SGavin Shan __func__, pe_no, phb->hose->global_number); 1654b82ab18SGavin Shan 1661e916772SGavin Shan pnv_ioda_init_pe(phb, pe_no); 1674b82ab18SGavin Shan } 1684b82ab18SGavin Shan 1691e916772SGavin Shan static struct pnv_ioda_pe *pnv_ioda_alloc_pe(struct pnv_phb *phb) 170184cd4a3SBenjamin Herrenschmidt { 17160964816SAndrzej Hajda long pe; 172184cd4a3SBenjamin Herrenschmidt 1739fcd6f4aSGavin Shan for (pe = phb->ioda.total_pe_num - 1; pe >= 0; pe--) { 1749fcd6f4aSGavin Shan if (!test_and_set_bit(pe, phb->ioda.pe_alloc)) 1751e916772SGavin Shan return pnv_ioda_init_pe(phb, pe); 176184cd4a3SBenjamin Herrenschmidt } 177184cd4a3SBenjamin Herrenschmidt 1789fcd6f4aSGavin Shan return NULL; 1799fcd6f4aSGavin Shan } 1809fcd6f4aSGavin Shan 1811e916772SGavin Shan static void pnv_ioda_free_pe(struct pnv_ioda_pe *pe) 182184cd4a3SBenjamin Herrenschmidt { 1831e916772SGavin Shan struct pnv_phb *phb = pe->phb; 184caa58f80SGavin Shan unsigned int pe_num = pe->pe_number; 185184cd4a3SBenjamin Herrenschmidt 1861e916772SGavin Shan WARN_ON(pe->pdev); 1871e916772SGavin Shan 1881e916772SGavin Shan memset(pe, 0, sizeof(struct pnv_ioda_pe)); 189caa58f80SGavin Shan clear_bit(pe_num, phb->ioda.pe_alloc); 190184cd4a3SBenjamin Herrenschmidt } 191184cd4a3SBenjamin Herrenschmidt 192262af557SGuo Chao /* The default M64 BAR is shared by all PEs */ 193262af557SGuo Chao static int pnv_ioda2_init_m64(struct pnv_phb *phb) 194262af557SGuo Chao { 195262af557SGuo Chao const char *desc; 196262af557SGuo Chao struct resource *r; 197262af557SGuo Chao s64 rc; 198262af557SGuo Chao 199262af557SGuo Chao /* Configure the default M64 BAR */ 200262af557SGuo Chao rc = opal_pci_set_phb_mem_window(phb->opal_id, 201262af557SGuo Chao OPAL_M64_WINDOW_TYPE, 202262af557SGuo Chao phb->ioda.m64_bar_idx, 203262af557SGuo Chao phb->ioda.m64_base, 204262af557SGuo Chao 0, /* unused */ 205262af557SGuo Chao phb->ioda.m64_size); 206262af557SGuo Chao if (rc != OPAL_SUCCESS) { 207262af557SGuo Chao desc = "configuring"; 208262af557SGuo Chao goto fail; 209262af557SGuo Chao } 210262af557SGuo Chao 211262af557SGuo Chao /* Enable the default M64 BAR */ 212262af557SGuo Chao rc = opal_pci_phb_mmio_enable(phb->opal_id, 213262af557SGuo Chao OPAL_M64_WINDOW_TYPE, 214262af557SGuo Chao phb->ioda.m64_bar_idx, 215262af557SGuo Chao OPAL_ENABLE_M64_SPLIT); 216262af557SGuo Chao if (rc != OPAL_SUCCESS) { 217262af557SGuo Chao desc = "enabling"; 218262af557SGuo Chao goto fail; 219262af557SGuo Chao } 220262af557SGuo Chao 221262af557SGuo Chao /* 22263803c39SGavin Shan * Exclude the segments for reserved and root bus PE, which 22363803c39SGavin Shan * are first or last two PEs. 224262af557SGuo Chao */ 225262af557SGuo Chao r = &phb->hose->mem_resources[1]; 22692b8f137SGavin Shan if (phb->ioda.reserved_pe_idx == 0) 22763803c39SGavin Shan r->start += (2 * phb->ioda.m64_segsize); 22892b8f137SGavin Shan else if (phb->ioda.reserved_pe_idx == (phb->ioda.total_pe_num - 1)) 22963803c39SGavin Shan r->end -= (2 * phb->ioda.m64_segsize); 230262af557SGuo Chao else 2311f52f176SRussell Currey pr_warn(" Cannot strip M64 segment for reserved PE#%x\n", 23292b8f137SGavin Shan phb->ioda.reserved_pe_idx); 233262af557SGuo Chao 234262af557SGuo Chao return 0; 235262af557SGuo Chao 236262af557SGuo Chao fail: 237262af557SGuo Chao pr_warn(" Failure %lld %s M64 BAR#%d\n", 238262af557SGuo Chao rc, desc, phb->ioda.m64_bar_idx); 239262af557SGuo Chao opal_pci_phb_mmio_enable(phb->opal_id, 240262af557SGuo Chao OPAL_M64_WINDOW_TYPE, 241262af557SGuo Chao phb->ioda.m64_bar_idx, 242262af557SGuo Chao OPAL_DISABLE_M64); 243262af557SGuo Chao return -EIO; 244262af557SGuo Chao } 245262af557SGuo Chao 246c430670aSGavin Shan static void pnv_ioda_reserve_dev_m64_pe(struct pci_dev *pdev, 24796a2f92bSGavin Shan unsigned long *pe_bitmap) 248262af557SGuo Chao { 24996a2f92bSGavin Shan struct pci_controller *hose = pci_bus_to_host(pdev->bus); 25096a2f92bSGavin Shan struct pnv_phb *phb = hose->private_data; 251262af557SGuo Chao struct resource *r; 25296a2f92bSGavin Shan resource_size_t base, sgsz, start, end; 25396a2f92bSGavin Shan int segno, i; 254262af557SGuo Chao 25596a2f92bSGavin Shan base = phb->ioda.m64_base; 25696a2f92bSGavin Shan sgsz = phb->ioda.m64_segsize; 25796a2f92bSGavin Shan for (i = 0; i <= PCI_ROM_RESOURCE; i++) { 25896a2f92bSGavin Shan r = &pdev->resource[i]; 2595958d19aSBenjamin Herrenschmidt if (!r->parent || !pnv_pci_is_m64(phb, r)) 260262af557SGuo Chao continue; 261262af557SGuo Chao 26296a2f92bSGavin Shan start = _ALIGN_DOWN(r->start - base, sgsz); 26396a2f92bSGavin Shan end = _ALIGN_UP(r->end - base, sgsz); 26496a2f92bSGavin Shan for (segno = start / sgsz; segno < end / sgsz; segno++) { 26596a2f92bSGavin Shan if (pe_bitmap) 26696a2f92bSGavin Shan set_bit(segno, pe_bitmap); 26796a2f92bSGavin Shan else 26896a2f92bSGavin Shan pnv_ioda_reserve_pe(phb, segno); 269262af557SGuo Chao } 270262af557SGuo Chao } 271262af557SGuo Chao } 272262af557SGuo Chao 27399451551SGavin Shan static int pnv_ioda1_init_m64(struct pnv_phb *phb) 27499451551SGavin Shan { 27599451551SGavin Shan struct resource *r; 27699451551SGavin Shan int index; 27799451551SGavin Shan 27899451551SGavin Shan /* 27999451551SGavin Shan * There are 16 M64 BARs, each of which has 8 segments. So 28099451551SGavin Shan * there are as many M64 segments as the maximum number of 28199451551SGavin Shan * PEs, which is 128. 28299451551SGavin Shan */ 28399451551SGavin Shan for (index = 0; index < PNV_IODA1_M64_NUM; index++) { 28499451551SGavin Shan unsigned long base, segsz = phb->ioda.m64_segsize; 28599451551SGavin Shan int64_t rc; 28699451551SGavin Shan 28799451551SGavin Shan base = phb->ioda.m64_base + 28899451551SGavin Shan index * PNV_IODA1_M64_SEGS * segsz; 28999451551SGavin Shan rc = opal_pci_set_phb_mem_window(phb->opal_id, 29099451551SGavin Shan OPAL_M64_WINDOW_TYPE, index, base, 0, 29199451551SGavin Shan PNV_IODA1_M64_SEGS * segsz); 29299451551SGavin Shan if (rc != OPAL_SUCCESS) { 2931f52f176SRussell Currey pr_warn(" Error %lld setting M64 PHB#%x-BAR#%d\n", 29499451551SGavin Shan rc, phb->hose->global_number, index); 29599451551SGavin Shan goto fail; 29699451551SGavin Shan } 29799451551SGavin Shan 29899451551SGavin Shan rc = opal_pci_phb_mmio_enable(phb->opal_id, 29999451551SGavin Shan OPAL_M64_WINDOW_TYPE, index, 30099451551SGavin Shan OPAL_ENABLE_M64_SPLIT); 30199451551SGavin Shan if (rc != OPAL_SUCCESS) { 3021f52f176SRussell Currey pr_warn(" Error %lld enabling M64 PHB#%x-BAR#%d\n", 30399451551SGavin Shan rc, phb->hose->global_number, index); 30499451551SGavin Shan goto fail; 30599451551SGavin Shan } 30699451551SGavin Shan } 30799451551SGavin Shan 30899451551SGavin Shan /* 30963803c39SGavin Shan * Exclude the segments for reserved and root bus PE, which 31063803c39SGavin Shan * are first or last two PEs. 31199451551SGavin Shan */ 31299451551SGavin Shan r = &phb->hose->mem_resources[1]; 31399451551SGavin Shan if (phb->ioda.reserved_pe_idx == 0) 31463803c39SGavin Shan r->start += (2 * phb->ioda.m64_segsize); 31599451551SGavin Shan else if (phb->ioda.reserved_pe_idx == (phb->ioda.total_pe_num - 1)) 31663803c39SGavin Shan r->end -= (2 * phb->ioda.m64_segsize); 31799451551SGavin Shan else 3181f52f176SRussell Currey WARN(1, "Wrong reserved PE#%x on PHB#%x\n", 31999451551SGavin Shan phb->ioda.reserved_pe_idx, phb->hose->global_number); 32099451551SGavin Shan 32199451551SGavin Shan return 0; 32299451551SGavin Shan 32399451551SGavin Shan fail: 32499451551SGavin Shan for ( ; index >= 0; index--) 32599451551SGavin Shan opal_pci_phb_mmio_enable(phb->opal_id, 32699451551SGavin Shan OPAL_M64_WINDOW_TYPE, index, OPAL_DISABLE_M64); 32799451551SGavin Shan 32899451551SGavin Shan return -EIO; 32999451551SGavin Shan } 33099451551SGavin Shan 331c430670aSGavin Shan static void pnv_ioda_reserve_m64_pe(struct pci_bus *bus, 33296a2f92bSGavin Shan unsigned long *pe_bitmap, 33396a2f92bSGavin Shan bool all) 334262af557SGuo Chao { 335262af557SGuo Chao struct pci_dev *pdev; 33696a2f92bSGavin Shan 33796a2f92bSGavin Shan list_for_each_entry(pdev, &bus->devices, bus_list) { 338c430670aSGavin Shan pnv_ioda_reserve_dev_m64_pe(pdev, pe_bitmap); 33996a2f92bSGavin Shan 34096a2f92bSGavin Shan if (all && pdev->subordinate) 341c430670aSGavin Shan pnv_ioda_reserve_m64_pe(pdev->subordinate, 34296a2f92bSGavin Shan pe_bitmap, all); 34396a2f92bSGavin Shan } 34496a2f92bSGavin Shan } 34596a2f92bSGavin Shan 3461e916772SGavin Shan static struct pnv_ioda_pe *pnv_ioda_pick_m64_pe(struct pci_bus *bus, bool all) 347262af557SGuo Chao { 34826ba248dSGavin Shan struct pci_controller *hose = pci_bus_to_host(bus); 34926ba248dSGavin Shan struct pnv_phb *phb = hose->private_data; 350262af557SGuo Chao struct pnv_ioda_pe *master_pe, *pe; 351262af557SGuo Chao unsigned long size, *pe_alloc; 35226ba248dSGavin Shan int i; 353262af557SGuo Chao 354262af557SGuo Chao /* Root bus shouldn't use M64 */ 355262af557SGuo Chao if (pci_is_root_bus(bus)) 3561e916772SGavin Shan return NULL; 357262af557SGuo Chao 358262af557SGuo Chao /* Allocate bitmap */ 35992b8f137SGavin Shan size = _ALIGN_UP(phb->ioda.total_pe_num / 8, sizeof(unsigned long)); 360262af557SGuo Chao pe_alloc = kzalloc(size, GFP_KERNEL); 361262af557SGuo Chao if (!pe_alloc) { 362262af557SGuo Chao pr_warn("%s: Out of memory !\n", 363262af557SGuo Chao __func__); 3641e916772SGavin Shan return NULL; 365262af557SGuo Chao } 366262af557SGuo Chao 36726ba248dSGavin Shan /* Figure out reserved PE numbers by the PE */ 368c430670aSGavin Shan pnv_ioda_reserve_m64_pe(bus, pe_alloc, all); 369262af557SGuo Chao 370262af557SGuo Chao /* 371262af557SGuo Chao * the current bus might not own M64 window and that's all 372262af557SGuo Chao * contributed by its child buses. For the case, we needn't 373262af557SGuo Chao * pick M64 dependent PE#. 374262af557SGuo Chao */ 37592b8f137SGavin Shan if (bitmap_empty(pe_alloc, phb->ioda.total_pe_num)) { 376262af557SGuo Chao kfree(pe_alloc); 3771e916772SGavin Shan return NULL; 378262af557SGuo Chao } 379262af557SGuo Chao 380262af557SGuo Chao /* 381262af557SGuo Chao * Figure out the master PE and put all slave PEs to master 382262af557SGuo Chao * PE's list to form compound PE. 383262af557SGuo Chao */ 384262af557SGuo Chao master_pe = NULL; 385262af557SGuo Chao i = -1; 38692b8f137SGavin Shan while ((i = find_next_bit(pe_alloc, phb->ioda.total_pe_num, i + 1)) < 38792b8f137SGavin Shan phb->ioda.total_pe_num) { 388262af557SGuo Chao pe = &phb->ioda.pe_array[i]; 389262af557SGuo Chao 39093289d8cSGavin Shan phb->ioda.m64_segmap[pe->pe_number] = pe->pe_number; 391262af557SGuo Chao if (!master_pe) { 392262af557SGuo Chao pe->flags |= PNV_IODA_PE_MASTER; 393262af557SGuo Chao INIT_LIST_HEAD(&pe->slaves); 394262af557SGuo Chao master_pe = pe; 395262af557SGuo Chao } else { 396262af557SGuo Chao pe->flags |= PNV_IODA_PE_SLAVE; 397262af557SGuo Chao pe->master = master_pe; 398262af557SGuo Chao list_add_tail(&pe->list, &master_pe->slaves); 399262af557SGuo Chao } 40099451551SGavin Shan 40199451551SGavin Shan /* 40299451551SGavin Shan * P7IOC supports M64DT, which helps mapping M64 segment 40399451551SGavin Shan * to one particular PE#. However, PHB3 has fixed mapping 40499451551SGavin Shan * between M64 segment and PE#. In order to have same logic 40599451551SGavin Shan * for P7IOC and PHB3, we enforce fixed mapping between M64 40699451551SGavin Shan * segment and PE# on P7IOC. 40799451551SGavin Shan */ 40899451551SGavin Shan if (phb->type == PNV_PHB_IODA1) { 40999451551SGavin Shan int64_t rc; 41099451551SGavin Shan 41199451551SGavin Shan rc = opal_pci_map_pe_mmio_window(phb->opal_id, 41299451551SGavin Shan pe->pe_number, OPAL_M64_WINDOW_TYPE, 41399451551SGavin Shan pe->pe_number / PNV_IODA1_M64_SEGS, 41499451551SGavin Shan pe->pe_number % PNV_IODA1_M64_SEGS); 41599451551SGavin Shan if (rc != OPAL_SUCCESS) 4161f52f176SRussell Currey pr_warn("%s: Error %lld mapping M64 for PHB#%x-PE#%x\n", 41799451551SGavin Shan __func__, rc, phb->hose->global_number, 41899451551SGavin Shan pe->pe_number); 41999451551SGavin Shan } 420262af557SGuo Chao } 421262af557SGuo Chao 422262af557SGuo Chao kfree(pe_alloc); 4231e916772SGavin Shan return master_pe; 424262af557SGuo Chao } 425262af557SGuo Chao 426262af557SGuo Chao static void __init pnv_ioda_parse_m64_window(struct pnv_phb *phb) 427262af557SGuo Chao { 428262af557SGuo Chao struct pci_controller *hose = phb->hose; 429262af557SGuo Chao struct device_node *dn = hose->dn; 430262af557SGuo Chao struct resource *res; 431a1339fafSBenjamin Herrenschmidt u32 m64_range[2], i; 4320e7736c6SGavin Shan const __be32 *r; 433262af557SGuo Chao u64 pci_addr; 434262af557SGuo Chao 43599451551SGavin Shan if (phb->type != PNV_PHB_IODA1 && phb->type != PNV_PHB_IODA2) { 4361665c4a8SGavin Shan pr_info(" Not support M64 window\n"); 4371665c4a8SGavin Shan return; 4381665c4a8SGavin Shan } 4391665c4a8SGavin Shan 440e4d54f71SStewart Smith if (!firmware_has_feature(FW_FEATURE_OPAL)) { 441262af557SGuo Chao pr_info(" Firmware too old to support M64 window\n"); 442262af557SGuo Chao return; 443262af557SGuo Chao } 444262af557SGuo Chao 445262af557SGuo Chao r = of_get_property(dn, "ibm,opal-m64-window", NULL); 446262af557SGuo Chao if (!r) { 447262af557SGuo Chao pr_info(" No <ibm,opal-m64-window> on %s\n", 448262af557SGuo Chao dn->full_name); 449262af557SGuo Chao return; 450262af557SGuo Chao } 451262af557SGuo Chao 452a1339fafSBenjamin Herrenschmidt /* 453a1339fafSBenjamin Herrenschmidt * Find the available M64 BAR range and pickup the last one for 454a1339fafSBenjamin Herrenschmidt * covering the whole 64-bits space. We support only one range. 455a1339fafSBenjamin Herrenschmidt */ 456a1339fafSBenjamin Herrenschmidt if (of_property_read_u32_array(dn, "ibm,opal-available-m64-ranges", 457a1339fafSBenjamin Herrenschmidt m64_range, 2)) { 458a1339fafSBenjamin Herrenschmidt /* In absence of the property, assume 0..15 */ 459a1339fafSBenjamin Herrenschmidt m64_range[0] = 0; 460a1339fafSBenjamin Herrenschmidt m64_range[1] = 16; 461a1339fafSBenjamin Herrenschmidt } 462a1339fafSBenjamin Herrenschmidt /* We only support 64 bits in our allocator */ 463a1339fafSBenjamin Herrenschmidt if (m64_range[1] > 63) { 464a1339fafSBenjamin Herrenschmidt pr_warn("%s: Limiting M64 range to 63 (from %d) on PHB#%x\n", 465a1339fafSBenjamin Herrenschmidt __func__, m64_range[1], phb->hose->global_number); 466a1339fafSBenjamin Herrenschmidt m64_range[1] = 63; 467a1339fafSBenjamin Herrenschmidt } 468a1339fafSBenjamin Herrenschmidt /* Empty range, no m64 */ 469a1339fafSBenjamin Herrenschmidt if (m64_range[1] <= m64_range[0]) { 470a1339fafSBenjamin Herrenschmidt pr_warn("%s: M64 empty, disabling M64 usage on PHB#%x\n", 471a1339fafSBenjamin Herrenschmidt __func__, phb->hose->global_number); 472a1339fafSBenjamin Herrenschmidt return; 473a1339fafSBenjamin Herrenschmidt } 474a1339fafSBenjamin Herrenschmidt 475a1339fafSBenjamin Herrenschmidt /* Configure M64 informations */ 476262af557SGuo Chao res = &hose->mem_resources[1]; 477e80c4e7cSGavin Shan res->name = dn->full_name; 478262af557SGuo Chao res->start = of_translate_address(dn, r + 2); 479262af557SGuo Chao res->end = res->start + of_read_number(r + 4, 2) - 1; 480262af557SGuo Chao res->flags = (IORESOURCE_MEM | IORESOURCE_MEM_64 | IORESOURCE_PREFETCH); 481262af557SGuo Chao pci_addr = of_read_number(r, 2); 482262af557SGuo Chao hose->mem_offset[1] = res->start - pci_addr; 483262af557SGuo Chao 484262af557SGuo Chao phb->ioda.m64_size = resource_size(res); 48592b8f137SGavin Shan phb->ioda.m64_segsize = phb->ioda.m64_size / phb->ioda.total_pe_num; 486262af557SGuo Chao phb->ioda.m64_base = pci_addr; 487262af557SGuo Chao 488a1339fafSBenjamin Herrenschmidt /* This lines up nicely with the display from processing OF ranges */ 489a1339fafSBenjamin Herrenschmidt pr_info(" MEM 0x%016llx..0x%016llx -> 0x%016llx (M64 #%d..%d)\n", 490a1339fafSBenjamin Herrenschmidt res->start, res->end, pci_addr, m64_range[0], 491a1339fafSBenjamin Herrenschmidt m64_range[0] + m64_range[1] - 1); 492a1339fafSBenjamin Herrenschmidt 493a1339fafSBenjamin Herrenschmidt /* Mark all M64 used up by default */ 494a1339fafSBenjamin Herrenschmidt phb->ioda.m64_bar_alloc = (unsigned long)-1; 495e9863e68SWei Yang 496262af557SGuo Chao /* Use last M64 BAR to cover M64 window */ 497a1339fafSBenjamin Herrenschmidt m64_range[1]--; 498a1339fafSBenjamin Herrenschmidt phb->ioda.m64_bar_idx = m64_range[0] + m64_range[1]; 499a1339fafSBenjamin Herrenschmidt 500a1339fafSBenjamin Herrenschmidt pr_info(" Using M64 #%d as default window\n", phb->ioda.m64_bar_idx); 501a1339fafSBenjamin Herrenschmidt 502a1339fafSBenjamin Herrenschmidt /* Mark remaining ones free */ 503a1339fafSBenjamin Herrenschmidt for (i = m64_range[0]; i < m64_range[1]; i++) 504a1339fafSBenjamin Herrenschmidt clear_bit(i, &phb->ioda.m64_bar_alloc); 505a1339fafSBenjamin Herrenschmidt 506a1339fafSBenjamin Herrenschmidt /* 507a1339fafSBenjamin Herrenschmidt * Setup init functions for M64 based on IODA version, IODA3 uses 508a1339fafSBenjamin Herrenschmidt * the IODA2 code. 509a1339fafSBenjamin Herrenschmidt */ 51099451551SGavin Shan if (phb->type == PNV_PHB_IODA1) 51199451551SGavin Shan phb->init_m64 = pnv_ioda1_init_m64; 51299451551SGavin Shan else 513262af557SGuo Chao phb->init_m64 = pnv_ioda2_init_m64; 514c430670aSGavin Shan phb->reserve_m64_pe = pnv_ioda_reserve_m64_pe; 515c430670aSGavin Shan phb->pick_m64_pe = pnv_ioda_pick_m64_pe; 516262af557SGuo Chao } 517262af557SGuo Chao 51849dec922SGavin Shan static void pnv_ioda_freeze_pe(struct pnv_phb *phb, int pe_no) 51949dec922SGavin Shan { 52049dec922SGavin Shan struct pnv_ioda_pe *pe = &phb->ioda.pe_array[pe_no]; 52149dec922SGavin Shan struct pnv_ioda_pe *slave; 52249dec922SGavin Shan s64 rc; 52349dec922SGavin Shan 52449dec922SGavin Shan /* Fetch master PE */ 52549dec922SGavin Shan if (pe->flags & PNV_IODA_PE_SLAVE) { 52649dec922SGavin Shan pe = pe->master; 527ec8e4e9dSGavin Shan if (WARN_ON(!pe || !(pe->flags & PNV_IODA_PE_MASTER))) 528ec8e4e9dSGavin Shan return; 529ec8e4e9dSGavin Shan 53049dec922SGavin Shan pe_no = pe->pe_number; 53149dec922SGavin Shan } 53249dec922SGavin Shan 53349dec922SGavin Shan /* Freeze master PE */ 53449dec922SGavin Shan rc = opal_pci_eeh_freeze_set(phb->opal_id, 53549dec922SGavin Shan pe_no, 53649dec922SGavin Shan OPAL_EEH_ACTION_SET_FREEZE_ALL); 53749dec922SGavin Shan if (rc != OPAL_SUCCESS) { 53849dec922SGavin Shan pr_warn("%s: Failure %lld freezing PHB#%x-PE#%x\n", 53949dec922SGavin Shan __func__, rc, phb->hose->global_number, pe_no); 54049dec922SGavin Shan return; 54149dec922SGavin Shan } 54249dec922SGavin Shan 54349dec922SGavin Shan /* Freeze slave PEs */ 54449dec922SGavin Shan if (!(pe->flags & PNV_IODA_PE_MASTER)) 54549dec922SGavin Shan return; 54649dec922SGavin Shan 54749dec922SGavin Shan list_for_each_entry(slave, &pe->slaves, list) { 54849dec922SGavin Shan rc = opal_pci_eeh_freeze_set(phb->opal_id, 54949dec922SGavin Shan slave->pe_number, 55049dec922SGavin Shan OPAL_EEH_ACTION_SET_FREEZE_ALL); 55149dec922SGavin Shan if (rc != OPAL_SUCCESS) 55249dec922SGavin Shan pr_warn("%s: Failure %lld freezing PHB#%x-PE#%x\n", 55349dec922SGavin Shan __func__, rc, phb->hose->global_number, 55449dec922SGavin Shan slave->pe_number); 55549dec922SGavin Shan } 55649dec922SGavin Shan } 55749dec922SGavin Shan 558e51df2c1SAnton Blanchard static int pnv_ioda_unfreeze_pe(struct pnv_phb *phb, int pe_no, int opt) 55949dec922SGavin Shan { 56049dec922SGavin Shan struct pnv_ioda_pe *pe, *slave; 56149dec922SGavin Shan s64 rc; 56249dec922SGavin Shan 56349dec922SGavin Shan /* Find master PE */ 56449dec922SGavin Shan pe = &phb->ioda.pe_array[pe_no]; 56549dec922SGavin Shan if (pe->flags & PNV_IODA_PE_SLAVE) { 56649dec922SGavin Shan pe = pe->master; 56749dec922SGavin Shan WARN_ON(!pe || !(pe->flags & PNV_IODA_PE_MASTER)); 56849dec922SGavin Shan pe_no = pe->pe_number; 56949dec922SGavin Shan } 57049dec922SGavin Shan 57149dec922SGavin Shan /* Clear frozen state for master PE */ 57249dec922SGavin Shan rc = opal_pci_eeh_freeze_clear(phb->opal_id, pe_no, opt); 57349dec922SGavin Shan if (rc != OPAL_SUCCESS) { 57449dec922SGavin Shan pr_warn("%s: Failure %lld clear %d on PHB#%x-PE#%x\n", 57549dec922SGavin Shan __func__, rc, opt, phb->hose->global_number, pe_no); 57649dec922SGavin Shan return -EIO; 57749dec922SGavin Shan } 57849dec922SGavin Shan 57949dec922SGavin Shan if (!(pe->flags & PNV_IODA_PE_MASTER)) 58049dec922SGavin Shan return 0; 58149dec922SGavin Shan 58249dec922SGavin Shan /* Clear frozen state for slave PEs */ 58349dec922SGavin Shan list_for_each_entry(slave, &pe->slaves, list) { 58449dec922SGavin Shan rc = opal_pci_eeh_freeze_clear(phb->opal_id, 58549dec922SGavin Shan slave->pe_number, 58649dec922SGavin Shan opt); 58749dec922SGavin Shan if (rc != OPAL_SUCCESS) { 58849dec922SGavin Shan pr_warn("%s: Failure %lld clear %d on PHB#%x-PE#%x\n", 58949dec922SGavin Shan __func__, rc, opt, phb->hose->global_number, 59049dec922SGavin Shan slave->pe_number); 59149dec922SGavin Shan return -EIO; 59249dec922SGavin Shan } 59349dec922SGavin Shan } 59449dec922SGavin Shan 59549dec922SGavin Shan return 0; 59649dec922SGavin Shan } 59749dec922SGavin Shan 59849dec922SGavin Shan static int pnv_ioda_get_pe_state(struct pnv_phb *phb, int pe_no) 59949dec922SGavin Shan { 60049dec922SGavin Shan struct pnv_ioda_pe *slave, *pe; 60149dec922SGavin Shan u8 fstate, state; 60249dec922SGavin Shan __be16 pcierr; 60349dec922SGavin Shan s64 rc; 60449dec922SGavin Shan 60549dec922SGavin Shan /* Sanity check on PE number */ 60692b8f137SGavin Shan if (pe_no < 0 || pe_no >= phb->ioda.total_pe_num) 60749dec922SGavin Shan return OPAL_EEH_STOPPED_PERM_UNAVAIL; 60849dec922SGavin Shan 60949dec922SGavin Shan /* 61049dec922SGavin Shan * Fetch the master PE and the PE instance might be 61149dec922SGavin Shan * not initialized yet. 61249dec922SGavin Shan */ 61349dec922SGavin Shan pe = &phb->ioda.pe_array[pe_no]; 61449dec922SGavin Shan if (pe->flags & PNV_IODA_PE_SLAVE) { 61549dec922SGavin Shan pe = pe->master; 61649dec922SGavin Shan WARN_ON(!pe || !(pe->flags & PNV_IODA_PE_MASTER)); 61749dec922SGavin Shan pe_no = pe->pe_number; 61849dec922SGavin Shan } 61949dec922SGavin Shan 62049dec922SGavin Shan /* Check the master PE */ 62149dec922SGavin Shan rc = opal_pci_eeh_freeze_status(phb->opal_id, pe_no, 62249dec922SGavin Shan &state, &pcierr, NULL); 62349dec922SGavin Shan if (rc != OPAL_SUCCESS) { 62449dec922SGavin Shan pr_warn("%s: Failure %lld getting " 62549dec922SGavin Shan "PHB#%x-PE#%x state\n", 62649dec922SGavin Shan __func__, rc, 62749dec922SGavin Shan phb->hose->global_number, pe_no); 62849dec922SGavin Shan return OPAL_EEH_STOPPED_TEMP_UNAVAIL; 62949dec922SGavin Shan } 63049dec922SGavin Shan 63149dec922SGavin Shan /* Check the slave PE */ 63249dec922SGavin Shan if (!(pe->flags & PNV_IODA_PE_MASTER)) 63349dec922SGavin Shan return state; 63449dec922SGavin Shan 63549dec922SGavin Shan list_for_each_entry(slave, &pe->slaves, list) { 63649dec922SGavin Shan rc = opal_pci_eeh_freeze_status(phb->opal_id, 63749dec922SGavin Shan slave->pe_number, 63849dec922SGavin Shan &fstate, 63949dec922SGavin Shan &pcierr, 64049dec922SGavin Shan NULL); 64149dec922SGavin Shan if (rc != OPAL_SUCCESS) { 64249dec922SGavin Shan pr_warn("%s: Failure %lld getting " 64349dec922SGavin Shan "PHB#%x-PE#%x state\n", 64449dec922SGavin Shan __func__, rc, 64549dec922SGavin Shan phb->hose->global_number, slave->pe_number); 64649dec922SGavin Shan return OPAL_EEH_STOPPED_TEMP_UNAVAIL; 64749dec922SGavin Shan } 64849dec922SGavin Shan 64949dec922SGavin Shan /* 65049dec922SGavin Shan * Override the result based on the ascending 65149dec922SGavin Shan * priority. 65249dec922SGavin Shan */ 65349dec922SGavin Shan if (fstate > state) 65449dec922SGavin Shan state = fstate; 65549dec922SGavin Shan } 65649dec922SGavin Shan 65749dec922SGavin Shan return state; 65849dec922SGavin Shan } 65949dec922SGavin Shan 660184cd4a3SBenjamin Herrenschmidt /* Currently those 2 are only used when MSIs are enabled, this will change 661184cd4a3SBenjamin Herrenschmidt * but in the meantime, we need to protect them to avoid warnings 662184cd4a3SBenjamin Herrenschmidt */ 663184cd4a3SBenjamin Herrenschmidt #ifdef CONFIG_PCI_MSI 664f456834aSIan Munsie struct pnv_ioda_pe *pnv_ioda_get_pe(struct pci_dev *dev) 665184cd4a3SBenjamin Herrenschmidt { 666184cd4a3SBenjamin Herrenschmidt struct pci_controller *hose = pci_bus_to_host(dev->bus); 667184cd4a3SBenjamin Herrenschmidt struct pnv_phb *phb = hose->private_data; 668b72c1f65SBenjamin Herrenschmidt struct pci_dn *pdn = pci_get_pdn(dev); 669184cd4a3SBenjamin Herrenschmidt 670184cd4a3SBenjamin Herrenschmidt if (!pdn) 671184cd4a3SBenjamin Herrenschmidt return NULL; 672184cd4a3SBenjamin Herrenschmidt if (pdn->pe_number == IODA_INVALID_PE) 673184cd4a3SBenjamin Herrenschmidt return NULL; 674184cd4a3SBenjamin Herrenschmidt return &phb->ioda.pe_array[pdn->pe_number]; 675184cd4a3SBenjamin Herrenschmidt } 676184cd4a3SBenjamin Herrenschmidt #endif /* CONFIG_PCI_MSI */ 677184cd4a3SBenjamin Herrenschmidt 678b131a842SGavin Shan static int pnv_ioda_set_one_peltv(struct pnv_phb *phb, 679b131a842SGavin Shan struct pnv_ioda_pe *parent, 680b131a842SGavin Shan struct pnv_ioda_pe *child, 681b131a842SGavin Shan bool is_add) 682b131a842SGavin Shan { 683b131a842SGavin Shan const char *desc = is_add ? "adding" : "removing"; 684b131a842SGavin Shan uint8_t op = is_add ? OPAL_ADD_PE_TO_DOMAIN : 685b131a842SGavin Shan OPAL_REMOVE_PE_FROM_DOMAIN; 686b131a842SGavin Shan struct pnv_ioda_pe *slave; 687b131a842SGavin Shan long rc; 688b131a842SGavin Shan 689b131a842SGavin Shan /* Parent PE affects child PE */ 690b131a842SGavin Shan rc = opal_pci_set_peltv(phb->opal_id, parent->pe_number, 691b131a842SGavin Shan child->pe_number, op); 692b131a842SGavin Shan if (rc != OPAL_SUCCESS) { 693b131a842SGavin Shan pe_warn(child, "OPAL error %ld %s to parent PELTV\n", 694b131a842SGavin Shan rc, desc); 695b131a842SGavin Shan return -ENXIO; 696b131a842SGavin Shan } 697b131a842SGavin Shan 698b131a842SGavin Shan if (!(child->flags & PNV_IODA_PE_MASTER)) 699b131a842SGavin Shan return 0; 700b131a842SGavin Shan 701b131a842SGavin Shan /* Compound case: parent PE affects slave PEs */ 702b131a842SGavin Shan list_for_each_entry(slave, &child->slaves, list) { 703b131a842SGavin Shan rc = opal_pci_set_peltv(phb->opal_id, parent->pe_number, 704b131a842SGavin Shan slave->pe_number, op); 705b131a842SGavin Shan if (rc != OPAL_SUCCESS) { 706b131a842SGavin Shan pe_warn(slave, "OPAL error %ld %s to parent PELTV\n", 707b131a842SGavin Shan rc, desc); 708b131a842SGavin Shan return -ENXIO; 709b131a842SGavin Shan } 710b131a842SGavin Shan } 711b131a842SGavin Shan 712b131a842SGavin Shan return 0; 713b131a842SGavin Shan } 714b131a842SGavin Shan 715b131a842SGavin Shan static int pnv_ioda_set_peltv(struct pnv_phb *phb, 716b131a842SGavin Shan struct pnv_ioda_pe *pe, 717b131a842SGavin Shan bool is_add) 718b131a842SGavin Shan { 719b131a842SGavin Shan struct pnv_ioda_pe *slave; 720781a868fSWei Yang struct pci_dev *pdev = NULL; 721b131a842SGavin Shan int ret; 722b131a842SGavin Shan 723b131a842SGavin Shan /* 724b131a842SGavin Shan * Clear PE frozen state. If it's master PE, we need 725b131a842SGavin Shan * clear slave PE frozen state as well. 726b131a842SGavin Shan */ 727b131a842SGavin Shan if (is_add) { 728b131a842SGavin Shan opal_pci_eeh_freeze_clear(phb->opal_id, pe->pe_number, 729b131a842SGavin Shan OPAL_EEH_ACTION_CLEAR_FREEZE_ALL); 730b131a842SGavin Shan if (pe->flags & PNV_IODA_PE_MASTER) { 731b131a842SGavin Shan list_for_each_entry(slave, &pe->slaves, list) 732b131a842SGavin Shan opal_pci_eeh_freeze_clear(phb->opal_id, 733b131a842SGavin Shan slave->pe_number, 734b131a842SGavin Shan OPAL_EEH_ACTION_CLEAR_FREEZE_ALL); 735b131a842SGavin Shan } 736b131a842SGavin Shan } 737b131a842SGavin Shan 738b131a842SGavin Shan /* 739b131a842SGavin Shan * Associate PE in PELT. We need add the PE into the 740b131a842SGavin Shan * corresponding PELT-V as well. Otherwise, the error 741b131a842SGavin Shan * originated from the PE might contribute to other 742b131a842SGavin Shan * PEs. 743b131a842SGavin Shan */ 744b131a842SGavin Shan ret = pnv_ioda_set_one_peltv(phb, pe, pe, is_add); 745b131a842SGavin Shan if (ret) 746b131a842SGavin Shan return ret; 747b131a842SGavin Shan 748b131a842SGavin Shan /* For compound PEs, any one affects all of them */ 749b131a842SGavin Shan if (pe->flags & PNV_IODA_PE_MASTER) { 750b131a842SGavin Shan list_for_each_entry(slave, &pe->slaves, list) { 751b131a842SGavin Shan ret = pnv_ioda_set_one_peltv(phb, slave, pe, is_add); 752b131a842SGavin Shan if (ret) 753b131a842SGavin Shan return ret; 754b131a842SGavin Shan } 755b131a842SGavin Shan } 756b131a842SGavin Shan 757b131a842SGavin Shan if (pe->flags & (PNV_IODA_PE_BUS_ALL | PNV_IODA_PE_BUS)) 758b131a842SGavin Shan pdev = pe->pbus->self; 759781a868fSWei Yang else if (pe->flags & PNV_IODA_PE_DEV) 760b131a842SGavin Shan pdev = pe->pdev->bus->self; 761781a868fSWei Yang #ifdef CONFIG_PCI_IOV 762781a868fSWei Yang else if (pe->flags & PNV_IODA_PE_VF) 763283e2d8aSGavin Shan pdev = pe->parent_dev; 764781a868fSWei Yang #endif /* CONFIG_PCI_IOV */ 765b131a842SGavin Shan while (pdev) { 766b131a842SGavin Shan struct pci_dn *pdn = pci_get_pdn(pdev); 767b131a842SGavin Shan struct pnv_ioda_pe *parent; 768b131a842SGavin Shan 769b131a842SGavin Shan if (pdn && pdn->pe_number != IODA_INVALID_PE) { 770b131a842SGavin Shan parent = &phb->ioda.pe_array[pdn->pe_number]; 771b131a842SGavin Shan ret = pnv_ioda_set_one_peltv(phb, parent, pe, is_add); 772b131a842SGavin Shan if (ret) 773b131a842SGavin Shan return ret; 774b131a842SGavin Shan } 775b131a842SGavin Shan 776b131a842SGavin Shan pdev = pdev->bus->self; 777b131a842SGavin Shan } 778b131a842SGavin Shan 779b131a842SGavin Shan return 0; 780b131a842SGavin Shan } 781b131a842SGavin Shan 782781a868fSWei Yang static int pnv_ioda_deconfigure_pe(struct pnv_phb *phb, struct pnv_ioda_pe *pe) 783781a868fSWei Yang { 784781a868fSWei Yang struct pci_dev *parent; 785781a868fSWei Yang uint8_t bcomp, dcomp, fcomp; 786781a868fSWei Yang int64_t rc; 787781a868fSWei Yang long rid_end, rid; 788781a868fSWei Yang 789781a868fSWei Yang /* Currently, we just deconfigure VF PE. Bus PE will always there.*/ 790781a868fSWei Yang if (pe->pbus) { 791781a868fSWei Yang int count; 792781a868fSWei Yang 793781a868fSWei Yang dcomp = OPAL_IGNORE_RID_DEVICE_NUMBER; 794781a868fSWei Yang fcomp = OPAL_IGNORE_RID_FUNCTION_NUMBER; 795781a868fSWei Yang parent = pe->pbus->self; 796781a868fSWei Yang if (pe->flags & PNV_IODA_PE_BUS_ALL) 797781a868fSWei Yang count = pe->pbus->busn_res.end - pe->pbus->busn_res.start + 1; 798781a868fSWei Yang else 799781a868fSWei Yang count = 1; 800781a868fSWei Yang 801781a868fSWei Yang switch(count) { 802781a868fSWei Yang case 1: bcomp = OpalPciBusAll; break; 803781a868fSWei Yang case 2: bcomp = OpalPciBus7Bits; break; 804781a868fSWei Yang case 4: bcomp = OpalPciBus6Bits; break; 805781a868fSWei Yang case 8: bcomp = OpalPciBus5Bits; break; 806781a868fSWei Yang case 16: bcomp = OpalPciBus4Bits; break; 807781a868fSWei Yang case 32: bcomp = OpalPciBus3Bits; break; 808781a868fSWei Yang default: 809781a868fSWei Yang dev_err(&pe->pbus->dev, "Number of subordinate buses %d unsupported\n", 810781a868fSWei Yang count); 811781a868fSWei Yang /* Do an exact match only */ 812781a868fSWei Yang bcomp = OpalPciBusAll; 813781a868fSWei Yang } 814781a868fSWei Yang rid_end = pe->rid + (count << 8); 815781a868fSWei Yang } else { 81693e01a50SGavin Shan #ifdef CONFIG_PCI_IOV 817781a868fSWei Yang if (pe->flags & PNV_IODA_PE_VF) 818781a868fSWei Yang parent = pe->parent_dev; 819781a868fSWei Yang else 82093e01a50SGavin Shan #endif 821781a868fSWei Yang parent = pe->pdev->bus->self; 822781a868fSWei Yang bcomp = OpalPciBusAll; 823781a868fSWei Yang dcomp = OPAL_COMPARE_RID_DEVICE_NUMBER; 824781a868fSWei Yang fcomp = OPAL_COMPARE_RID_FUNCTION_NUMBER; 825781a868fSWei Yang rid_end = pe->rid + 1; 826781a868fSWei Yang } 827781a868fSWei Yang 828781a868fSWei Yang /* Clear the reverse map */ 829781a868fSWei Yang for (rid = pe->rid; rid < rid_end; rid++) 830c127562aSGavin Shan phb->ioda.pe_rmap[rid] = IODA_INVALID_PE; 831781a868fSWei Yang 832781a868fSWei Yang /* Release from all parents PELT-V */ 833781a868fSWei Yang while (parent) { 834781a868fSWei Yang struct pci_dn *pdn = pci_get_pdn(parent); 835781a868fSWei Yang if (pdn && pdn->pe_number != IODA_INVALID_PE) { 836781a868fSWei Yang rc = opal_pci_set_peltv(phb->opal_id, pdn->pe_number, 837781a868fSWei Yang pe->pe_number, OPAL_REMOVE_PE_FROM_DOMAIN); 838781a868fSWei Yang /* XXX What to do in case of error ? */ 839781a868fSWei Yang } 840781a868fSWei Yang parent = parent->bus->self; 841781a868fSWei Yang } 842781a868fSWei Yang 843f951e510SGavin Shan opal_pci_eeh_freeze_clear(phb->opal_id, pe->pe_number, 844781a868fSWei Yang OPAL_EEH_ACTION_CLEAR_FREEZE_ALL); 845781a868fSWei Yang 846781a868fSWei Yang /* Disassociate PE in PELT */ 847781a868fSWei Yang rc = opal_pci_set_peltv(phb->opal_id, pe->pe_number, 848781a868fSWei Yang pe->pe_number, OPAL_REMOVE_PE_FROM_DOMAIN); 849781a868fSWei Yang if (rc) 850781a868fSWei Yang pe_warn(pe, "OPAL error %ld remove self from PELTV\n", rc); 851781a868fSWei Yang rc = opal_pci_set_pe(phb->opal_id, pe->pe_number, pe->rid, 852781a868fSWei Yang bcomp, dcomp, fcomp, OPAL_UNMAP_PE); 853781a868fSWei Yang if (rc) 854781a868fSWei Yang pe_err(pe, "OPAL error %ld trying to setup PELT table\n", rc); 855781a868fSWei Yang 856781a868fSWei Yang pe->pbus = NULL; 857781a868fSWei Yang pe->pdev = NULL; 85893e01a50SGavin Shan #ifdef CONFIG_PCI_IOV 859781a868fSWei Yang pe->parent_dev = NULL; 86093e01a50SGavin Shan #endif 861781a868fSWei Yang 862781a868fSWei Yang return 0; 863781a868fSWei Yang } 864781a868fSWei Yang 865cad5cef6SGreg Kroah-Hartman static int pnv_ioda_configure_pe(struct pnv_phb *phb, struct pnv_ioda_pe *pe) 866184cd4a3SBenjamin Herrenschmidt { 867184cd4a3SBenjamin Herrenschmidt struct pci_dev *parent; 868184cd4a3SBenjamin Herrenschmidt uint8_t bcomp, dcomp, fcomp; 869184cd4a3SBenjamin Herrenschmidt long rc, rid_end, rid; 870184cd4a3SBenjamin Herrenschmidt 871184cd4a3SBenjamin Herrenschmidt /* Bus validation ? */ 872184cd4a3SBenjamin Herrenschmidt if (pe->pbus) { 873184cd4a3SBenjamin Herrenschmidt int count; 874184cd4a3SBenjamin Herrenschmidt 875184cd4a3SBenjamin Herrenschmidt dcomp = OPAL_IGNORE_RID_DEVICE_NUMBER; 876184cd4a3SBenjamin Herrenschmidt fcomp = OPAL_IGNORE_RID_FUNCTION_NUMBER; 877184cd4a3SBenjamin Herrenschmidt parent = pe->pbus->self; 878fb446ad0SGavin Shan if (pe->flags & PNV_IODA_PE_BUS_ALL) 879b918c62eSYinghai Lu count = pe->pbus->busn_res.end - pe->pbus->busn_res.start + 1; 880fb446ad0SGavin Shan else 881fb446ad0SGavin Shan count = 1; 882fb446ad0SGavin Shan 883184cd4a3SBenjamin Herrenschmidt switch(count) { 884184cd4a3SBenjamin Herrenschmidt case 1: bcomp = OpalPciBusAll; break; 885184cd4a3SBenjamin Herrenschmidt case 2: bcomp = OpalPciBus7Bits; break; 886184cd4a3SBenjamin Herrenschmidt case 4: bcomp = OpalPciBus6Bits; break; 887184cd4a3SBenjamin Herrenschmidt case 8: bcomp = OpalPciBus5Bits; break; 888184cd4a3SBenjamin Herrenschmidt case 16: bcomp = OpalPciBus4Bits; break; 889184cd4a3SBenjamin Herrenschmidt case 32: bcomp = OpalPciBus3Bits; break; 890184cd4a3SBenjamin Herrenschmidt default: 891781a868fSWei Yang dev_err(&pe->pbus->dev, "Number of subordinate buses %d unsupported\n", 892781a868fSWei Yang count); 893184cd4a3SBenjamin Herrenschmidt /* Do an exact match only */ 894184cd4a3SBenjamin Herrenschmidt bcomp = OpalPciBusAll; 895184cd4a3SBenjamin Herrenschmidt } 896184cd4a3SBenjamin Herrenschmidt rid_end = pe->rid + (count << 8); 897184cd4a3SBenjamin Herrenschmidt } else { 898781a868fSWei Yang #ifdef CONFIG_PCI_IOV 899781a868fSWei Yang if (pe->flags & PNV_IODA_PE_VF) 900781a868fSWei Yang parent = pe->parent_dev; 901781a868fSWei Yang else 902781a868fSWei Yang #endif /* CONFIG_PCI_IOV */ 903184cd4a3SBenjamin Herrenschmidt parent = pe->pdev->bus->self; 904184cd4a3SBenjamin Herrenschmidt bcomp = OpalPciBusAll; 905184cd4a3SBenjamin Herrenschmidt dcomp = OPAL_COMPARE_RID_DEVICE_NUMBER; 906184cd4a3SBenjamin Herrenschmidt fcomp = OPAL_COMPARE_RID_FUNCTION_NUMBER; 907184cd4a3SBenjamin Herrenschmidt rid_end = pe->rid + 1; 908184cd4a3SBenjamin Herrenschmidt } 909184cd4a3SBenjamin Herrenschmidt 910631ad691SGavin Shan /* 911631ad691SGavin Shan * Associate PE in PELT. We need add the PE into the 912631ad691SGavin Shan * corresponding PELT-V as well. Otherwise, the error 913631ad691SGavin Shan * originated from the PE might contribute to other 914631ad691SGavin Shan * PEs. 915631ad691SGavin Shan */ 916184cd4a3SBenjamin Herrenschmidt rc = opal_pci_set_pe(phb->opal_id, pe->pe_number, pe->rid, 917184cd4a3SBenjamin Herrenschmidt bcomp, dcomp, fcomp, OPAL_MAP_PE); 918184cd4a3SBenjamin Herrenschmidt if (rc) { 919184cd4a3SBenjamin Herrenschmidt pe_err(pe, "OPAL error %ld trying to setup PELT table\n", rc); 920184cd4a3SBenjamin Herrenschmidt return -ENXIO; 921184cd4a3SBenjamin Herrenschmidt } 922631ad691SGavin Shan 9235d2aa710SAlistair Popple /* 9245d2aa710SAlistair Popple * Configure PELTV. NPUs don't have a PELTV table so skip 9255d2aa710SAlistair Popple * configuration on them. 9265d2aa710SAlistair Popple */ 9275d2aa710SAlistair Popple if (phb->type != PNV_PHB_NPU) 928b131a842SGavin Shan pnv_ioda_set_peltv(phb, pe, true); 929184cd4a3SBenjamin Herrenschmidt 930184cd4a3SBenjamin Herrenschmidt /* Setup reverse map */ 931184cd4a3SBenjamin Herrenschmidt for (rid = pe->rid; rid < rid_end; rid++) 932184cd4a3SBenjamin Herrenschmidt phb->ioda.pe_rmap[rid] = pe->pe_number; 933184cd4a3SBenjamin Herrenschmidt 934184cd4a3SBenjamin Herrenschmidt /* Setup one MVTs on IODA1 */ 9354773f76bSGavin Shan if (phb->type != PNV_PHB_IODA1) { 9364773f76bSGavin Shan pe->mve_number = 0; 9374773f76bSGavin Shan goto out; 9384773f76bSGavin Shan } 9394773f76bSGavin Shan 940184cd4a3SBenjamin Herrenschmidt pe->mve_number = pe->pe_number; 9414773f76bSGavin Shan rc = opal_pci_set_mve(phb->opal_id, pe->mve_number, pe->pe_number); 9424773f76bSGavin Shan if (rc != OPAL_SUCCESS) { 9431f52f176SRussell Currey pe_err(pe, "OPAL error %ld setting up MVE %x\n", 944184cd4a3SBenjamin Herrenschmidt rc, pe->mve_number); 945184cd4a3SBenjamin Herrenschmidt pe->mve_number = -1; 946184cd4a3SBenjamin Herrenschmidt } else { 947184cd4a3SBenjamin Herrenschmidt rc = opal_pci_set_mve_enable(phb->opal_id, 948cee72d5bSBenjamin Herrenschmidt pe->mve_number, OPAL_ENABLE_MVE); 949184cd4a3SBenjamin Herrenschmidt if (rc) { 9501f52f176SRussell Currey pe_err(pe, "OPAL error %ld enabling MVE %x\n", 951184cd4a3SBenjamin Herrenschmidt rc, pe->mve_number); 952184cd4a3SBenjamin Herrenschmidt pe->mve_number = -1; 953184cd4a3SBenjamin Herrenschmidt } 954184cd4a3SBenjamin Herrenschmidt } 955184cd4a3SBenjamin Herrenschmidt 9564773f76bSGavin Shan out: 957184cd4a3SBenjamin Herrenschmidt return 0; 958184cd4a3SBenjamin Herrenschmidt } 959184cd4a3SBenjamin Herrenschmidt 960781a868fSWei Yang #ifdef CONFIG_PCI_IOV 961781a868fSWei Yang static int pnv_pci_vf_resource_shift(struct pci_dev *dev, int offset) 962781a868fSWei Yang { 963781a868fSWei Yang struct pci_dn *pdn = pci_get_pdn(dev); 964781a868fSWei Yang int i; 965781a868fSWei Yang struct resource *res, res2; 966781a868fSWei Yang resource_size_t size; 967781a868fSWei Yang u16 num_vfs; 968781a868fSWei Yang 969781a868fSWei Yang if (!dev->is_physfn) 970781a868fSWei Yang return -EINVAL; 971781a868fSWei Yang 972781a868fSWei Yang /* 973781a868fSWei Yang * "offset" is in VFs. The M64 windows are sized so that when they 974781a868fSWei Yang * are segmented, each segment is the same size as the IOV BAR. 975781a868fSWei Yang * Each segment is in a separate PE, and the high order bits of the 976781a868fSWei Yang * address are the PE number. Therefore, each VF's BAR is in a 977781a868fSWei Yang * separate PE, and changing the IOV BAR start address changes the 978781a868fSWei Yang * range of PEs the VFs are in. 979781a868fSWei Yang */ 980781a868fSWei Yang num_vfs = pdn->num_vfs; 981781a868fSWei Yang for (i = 0; i < PCI_SRIOV_NUM_BARS; i++) { 982781a868fSWei Yang res = &dev->resource[i + PCI_IOV_RESOURCES]; 983781a868fSWei Yang if (!res->flags || !res->parent) 984781a868fSWei Yang continue; 985781a868fSWei Yang 986781a868fSWei Yang /* 987781a868fSWei Yang * The actual IOV BAR range is determined by the start address 988781a868fSWei Yang * and the actual size for num_vfs VFs BAR. This check is to 989781a868fSWei Yang * make sure that after shifting, the range will not overlap 990781a868fSWei Yang * with another device. 991781a868fSWei Yang */ 992781a868fSWei Yang size = pci_iov_resource_size(dev, i + PCI_IOV_RESOURCES); 993781a868fSWei Yang res2.flags = res->flags; 994781a868fSWei Yang res2.start = res->start + (size * offset); 995781a868fSWei Yang res2.end = res2.start + (size * num_vfs) - 1; 996781a868fSWei Yang 997781a868fSWei Yang if (res2.end > res->end) { 998781a868fSWei Yang dev_err(&dev->dev, "VF BAR%d: %pR would extend past %pR (trying to enable %d VFs shifted by %d)\n", 999781a868fSWei Yang i, &res2, res, num_vfs, offset); 1000781a868fSWei Yang return -EBUSY; 1001781a868fSWei Yang } 1002781a868fSWei Yang } 1003781a868fSWei Yang 1004781a868fSWei Yang /* 1005781a868fSWei Yang * After doing so, there would be a "hole" in the /proc/iomem when 1006781a868fSWei Yang * offset is a positive value. It looks like the device return some 1007781a868fSWei Yang * mmio back to the system, which actually no one could use it. 1008781a868fSWei Yang */ 1009781a868fSWei Yang for (i = 0; i < PCI_SRIOV_NUM_BARS; i++) { 1010781a868fSWei Yang res = &dev->resource[i + PCI_IOV_RESOURCES]; 1011781a868fSWei Yang if (!res->flags || !res->parent) 1012781a868fSWei Yang continue; 1013781a868fSWei Yang 1014781a868fSWei Yang size = pci_iov_resource_size(dev, i + PCI_IOV_RESOURCES); 1015781a868fSWei Yang res2 = *res; 1016781a868fSWei Yang res->start += size * offset; 1017781a868fSWei Yang 101874703cc4SWei Yang dev_info(&dev->dev, "VF BAR%d: %pR shifted to %pR (%sabling %d VFs shifted by %d)\n", 101974703cc4SWei Yang i, &res2, res, (offset > 0) ? "En" : "Dis", 102074703cc4SWei Yang num_vfs, offset); 1021781a868fSWei Yang pci_update_resource(dev, i + PCI_IOV_RESOURCES); 1022781a868fSWei Yang } 1023781a868fSWei Yang return 0; 1024781a868fSWei Yang } 1025781a868fSWei Yang #endif /* CONFIG_PCI_IOV */ 1026781a868fSWei Yang 1027cad5cef6SGreg Kroah-Hartman static struct pnv_ioda_pe *pnv_ioda_setup_dev_PE(struct pci_dev *dev) 1028184cd4a3SBenjamin Herrenschmidt { 1029184cd4a3SBenjamin Herrenschmidt struct pci_controller *hose = pci_bus_to_host(dev->bus); 1030184cd4a3SBenjamin Herrenschmidt struct pnv_phb *phb = hose->private_data; 1031b72c1f65SBenjamin Herrenschmidt struct pci_dn *pdn = pci_get_pdn(dev); 1032184cd4a3SBenjamin Herrenschmidt struct pnv_ioda_pe *pe; 1033184cd4a3SBenjamin Herrenschmidt 1034184cd4a3SBenjamin Herrenschmidt if (!pdn) { 1035184cd4a3SBenjamin Herrenschmidt pr_err("%s: Device tree node not associated properly\n", 1036184cd4a3SBenjamin Herrenschmidt pci_name(dev)); 1037184cd4a3SBenjamin Herrenschmidt return NULL; 1038184cd4a3SBenjamin Herrenschmidt } 1039184cd4a3SBenjamin Herrenschmidt if (pdn->pe_number != IODA_INVALID_PE) 1040184cd4a3SBenjamin Herrenschmidt return NULL; 1041184cd4a3SBenjamin Herrenschmidt 10421e916772SGavin Shan pe = pnv_ioda_alloc_pe(phb); 10431e916772SGavin Shan if (!pe) { 1044184cd4a3SBenjamin Herrenschmidt pr_warning("%s: Not enough PE# available, disabling device\n", 1045184cd4a3SBenjamin Herrenschmidt pci_name(dev)); 1046184cd4a3SBenjamin Herrenschmidt return NULL; 1047184cd4a3SBenjamin Herrenschmidt } 1048184cd4a3SBenjamin Herrenschmidt 1049184cd4a3SBenjamin Herrenschmidt /* NOTE: We get only one ref to the pci_dev for the pdn, not for the 1050184cd4a3SBenjamin Herrenschmidt * pointer in the PE data structure, both should be destroyed at the 1051184cd4a3SBenjamin Herrenschmidt * same time. However, this needs to be looked at more closely again 1052184cd4a3SBenjamin Herrenschmidt * once we actually start removing things (Hotplug, SR-IOV, ...) 1053184cd4a3SBenjamin Herrenschmidt * 1054184cd4a3SBenjamin Herrenschmidt * At some point we want to remove the PDN completely anyways 1055184cd4a3SBenjamin Herrenschmidt */ 1056184cd4a3SBenjamin Herrenschmidt pci_dev_get(dev); 1057184cd4a3SBenjamin Herrenschmidt pdn->pcidev = dev; 10581e916772SGavin Shan pdn->pe_number = pe->pe_number; 10595d2aa710SAlistair Popple pe->flags = PNV_IODA_PE_DEV; 1060184cd4a3SBenjamin Herrenschmidt pe->pdev = dev; 1061184cd4a3SBenjamin Herrenschmidt pe->pbus = NULL; 1062184cd4a3SBenjamin Herrenschmidt pe->mve_number = -1; 1063184cd4a3SBenjamin Herrenschmidt pe->rid = dev->bus->number << 8 | pdn->devfn; 1064184cd4a3SBenjamin Herrenschmidt 1065184cd4a3SBenjamin Herrenschmidt pe_info(pe, "Associated device to PE\n"); 1066184cd4a3SBenjamin Herrenschmidt 1067184cd4a3SBenjamin Herrenschmidt if (pnv_ioda_configure_pe(phb, pe)) { 1068184cd4a3SBenjamin Herrenschmidt /* XXX What do we do here ? */ 10691e916772SGavin Shan pnv_ioda_free_pe(pe); 1070184cd4a3SBenjamin Herrenschmidt pdn->pe_number = IODA_INVALID_PE; 1071184cd4a3SBenjamin Herrenschmidt pe->pdev = NULL; 1072184cd4a3SBenjamin Herrenschmidt pci_dev_put(dev); 1073184cd4a3SBenjamin Herrenschmidt return NULL; 1074184cd4a3SBenjamin Herrenschmidt } 1075184cd4a3SBenjamin Herrenschmidt 10761d4e89cfSAlexey Kardashevskiy /* Put PE to the list */ 10771d4e89cfSAlexey Kardashevskiy list_add_tail(&pe->list, &phb->ioda.pe_list); 10781d4e89cfSAlexey Kardashevskiy 1079184cd4a3SBenjamin Herrenschmidt return pe; 1080184cd4a3SBenjamin Herrenschmidt } 1081184cd4a3SBenjamin Herrenschmidt 1082184cd4a3SBenjamin Herrenschmidt static void pnv_ioda_setup_same_PE(struct pci_bus *bus, struct pnv_ioda_pe *pe) 1083184cd4a3SBenjamin Herrenschmidt { 1084184cd4a3SBenjamin Herrenschmidt struct pci_dev *dev; 1085184cd4a3SBenjamin Herrenschmidt 1086184cd4a3SBenjamin Herrenschmidt list_for_each_entry(dev, &bus->devices, bus_list) { 1087b72c1f65SBenjamin Herrenschmidt struct pci_dn *pdn = pci_get_pdn(dev); 1088184cd4a3SBenjamin Herrenschmidt 1089184cd4a3SBenjamin Herrenschmidt if (pdn == NULL) { 1090184cd4a3SBenjamin Herrenschmidt pr_warn("%s: No device node associated with device !\n", 1091184cd4a3SBenjamin Herrenschmidt pci_name(dev)); 1092184cd4a3SBenjamin Herrenschmidt continue; 1093184cd4a3SBenjamin Herrenschmidt } 1094ccd1c191SGavin Shan 1095ccd1c191SGavin Shan /* 1096ccd1c191SGavin Shan * In partial hotplug case, the PCI device might be still 1097ccd1c191SGavin Shan * associated with the PE and needn't attach it to the PE 1098ccd1c191SGavin Shan * again. 1099ccd1c191SGavin Shan */ 1100ccd1c191SGavin Shan if (pdn->pe_number != IODA_INVALID_PE) 1101ccd1c191SGavin Shan continue; 1102ccd1c191SGavin Shan 1103c5f7700bSGavin Shan pe->device_count++; 110494973b24SAlistair Popple pdn->pcidev = dev; 1105184cd4a3SBenjamin Herrenschmidt pdn->pe_number = pe->pe_number; 1106fb446ad0SGavin Shan if ((pe->flags & PNV_IODA_PE_BUS_ALL) && dev->subordinate) 1107184cd4a3SBenjamin Herrenschmidt pnv_ioda_setup_same_PE(dev->subordinate, pe); 1108184cd4a3SBenjamin Herrenschmidt } 1109184cd4a3SBenjamin Herrenschmidt } 1110184cd4a3SBenjamin Herrenschmidt 1111fb446ad0SGavin Shan /* 1112fb446ad0SGavin Shan * There're 2 types of PCI bus sensitive PEs: One that is compromised of 1113fb446ad0SGavin Shan * single PCI bus. Another one that contains the primary PCI bus and its 1114fb446ad0SGavin Shan * subordinate PCI devices and buses. The second type of PE is normally 1115fb446ad0SGavin Shan * orgiriated by PCIe-to-PCI bridge or PLX switch downstream ports. 1116fb446ad0SGavin Shan */ 11171e916772SGavin Shan static struct pnv_ioda_pe *pnv_ioda_setup_bus_PE(struct pci_bus *bus, bool all) 1118184cd4a3SBenjamin Herrenschmidt { 1119fb446ad0SGavin Shan struct pci_controller *hose = pci_bus_to_host(bus); 1120184cd4a3SBenjamin Herrenschmidt struct pnv_phb *phb = hose->private_data; 11211e916772SGavin Shan struct pnv_ioda_pe *pe = NULL; 1122ccd1c191SGavin Shan unsigned int pe_num; 1123ccd1c191SGavin Shan 1124ccd1c191SGavin Shan /* 1125ccd1c191SGavin Shan * In partial hotplug case, the PE instance might be still alive. 1126ccd1c191SGavin Shan * We should reuse it instead of allocating a new one. 1127ccd1c191SGavin Shan */ 1128ccd1c191SGavin Shan pe_num = phb->ioda.pe_rmap[bus->number << 8]; 1129ccd1c191SGavin Shan if (pe_num != IODA_INVALID_PE) { 1130ccd1c191SGavin Shan pe = &phb->ioda.pe_array[pe_num]; 1131ccd1c191SGavin Shan pnv_ioda_setup_same_PE(bus, pe); 1132ccd1c191SGavin Shan return NULL; 1133ccd1c191SGavin Shan } 1134184cd4a3SBenjamin Herrenschmidt 113563803c39SGavin Shan /* PE number for root bus should have been reserved */ 113663803c39SGavin Shan if (pci_is_root_bus(bus) && 113763803c39SGavin Shan phb->ioda.root_pe_idx != IODA_INVALID_PE) 113863803c39SGavin Shan pe = &phb->ioda.pe_array[phb->ioda.root_pe_idx]; 113963803c39SGavin Shan 1140262af557SGuo Chao /* Check if PE is determined by M64 */ 114163803c39SGavin Shan if (!pe && phb->pick_m64_pe) 11421e916772SGavin Shan pe = phb->pick_m64_pe(bus, all); 1143262af557SGuo Chao 1144262af557SGuo Chao /* The PE number isn't pinned by M64 */ 11451e916772SGavin Shan if (!pe) 11461e916772SGavin Shan pe = pnv_ioda_alloc_pe(phb); 1147262af557SGuo Chao 11481e916772SGavin Shan if (!pe) { 1149fb446ad0SGavin Shan pr_warning("%s: Not enough PE# available for PCI bus %04x:%02x\n", 1150fb446ad0SGavin Shan __func__, pci_domain_nr(bus), bus->number); 11511e916772SGavin Shan return NULL; 1152184cd4a3SBenjamin Herrenschmidt } 1153184cd4a3SBenjamin Herrenschmidt 1154262af557SGuo Chao pe->flags |= (all ? PNV_IODA_PE_BUS_ALL : PNV_IODA_PE_BUS); 1155184cd4a3SBenjamin Herrenschmidt pe->pbus = bus; 1156184cd4a3SBenjamin Herrenschmidt pe->pdev = NULL; 1157184cd4a3SBenjamin Herrenschmidt pe->mve_number = -1; 1158b918c62eSYinghai Lu pe->rid = bus->busn_res.start << 8; 1159184cd4a3SBenjamin Herrenschmidt 1160fb446ad0SGavin Shan if (all) 11611f52f176SRussell Currey pe_info(pe, "Secondary bus %d..%d associated with PE#%x\n", 11621e916772SGavin Shan bus->busn_res.start, bus->busn_res.end, pe->pe_number); 1163fb446ad0SGavin Shan else 11641f52f176SRussell Currey pe_info(pe, "Secondary bus %d associated with PE#%x\n", 11651e916772SGavin Shan bus->busn_res.start, pe->pe_number); 1166184cd4a3SBenjamin Herrenschmidt 1167184cd4a3SBenjamin Herrenschmidt if (pnv_ioda_configure_pe(phb, pe)) { 1168184cd4a3SBenjamin Herrenschmidt /* XXX What do we do here ? */ 11691e916772SGavin Shan pnv_ioda_free_pe(pe); 1170184cd4a3SBenjamin Herrenschmidt pe->pbus = NULL; 11711e916772SGavin Shan return NULL; 1172184cd4a3SBenjamin Herrenschmidt } 1173184cd4a3SBenjamin Herrenschmidt 1174184cd4a3SBenjamin Herrenschmidt /* Associate it with all child devices */ 1175184cd4a3SBenjamin Herrenschmidt pnv_ioda_setup_same_PE(bus, pe); 1176184cd4a3SBenjamin Herrenschmidt 11777ebdf956SGavin Shan /* Put PE to the list */ 11787ebdf956SGavin Shan list_add_tail(&pe->list, &phb->ioda.pe_list); 11791e916772SGavin Shan 11801e916772SGavin Shan return pe; 1181184cd4a3SBenjamin Herrenschmidt } 1182184cd4a3SBenjamin Herrenschmidt 1183b521549aSAlistair Popple static struct pnv_ioda_pe *pnv_ioda_setup_npu_PE(struct pci_dev *npu_pdev) 11845d2aa710SAlistair Popple { 1185b521549aSAlistair Popple int pe_num, found_pe = false, rc; 1186b521549aSAlistair Popple long rid; 1187b521549aSAlistair Popple struct pnv_ioda_pe *pe; 1188b521549aSAlistair Popple struct pci_dev *gpu_pdev; 1189b521549aSAlistair Popple struct pci_dn *npu_pdn; 1190b521549aSAlistair Popple struct pci_controller *hose = pci_bus_to_host(npu_pdev->bus); 1191b521549aSAlistair Popple struct pnv_phb *phb = hose->private_data; 1192b521549aSAlistair Popple 1193b521549aSAlistair Popple /* 1194b521549aSAlistair Popple * Due to a hardware errata PE#0 on the NPU is reserved for 1195b521549aSAlistair Popple * error handling. This means we only have three PEs remaining 1196b521549aSAlistair Popple * which need to be assigned to four links, implying some 1197b521549aSAlistair Popple * links must share PEs. 1198b521549aSAlistair Popple * 1199b521549aSAlistair Popple * To achieve this we assign PEs such that NPUs linking the 1200b521549aSAlistair Popple * same GPU get assigned the same PE. 1201b521549aSAlistair Popple */ 1202b521549aSAlistair Popple gpu_pdev = pnv_pci_get_gpu_dev(npu_pdev); 120392b8f137SGavin Shan for (pe_num = 0; pe_num < phb->ioda.total_pe_num; pe_num++) { 1204b521549aSAlistair Popple pe = &phb->ioda.pe_array[pe_num]; 1205b521549aSAlistair Popple if (!pe->pdev) 1206b521549aSAlistair Popple continue; 1207b521549aSAlistair Popple 1208b521549aSAlistair Popple if (pnv_pci_get_gpu_dev(pe->pdev) == gpu_pdev) { 1209b521549aSAlistair Popple /* 1210b521549aSAlistair Popple * This device has the same peer GPU so should 1211b521549aSAlistair Popple * be assigned the same PE as the existing 1212b521549aSAlistair Popple * peer NPU. 1213b521549aSAlistair Popple */ 1214b521549aSAlistair Popple dev_info(&npu_pdev->dev, 12151f52f176SRussell Currey "Associating to existing PE %x\n", pe_num); 1216b521549aSAlistair Popple pci_dev_get(npu_pdev); 1217b521549aSAlistair Popple npu_pdn = pci_get_pdn(npu_pdev); 1218b521549aSAlistair Popple rid = npu_pdev->bus->number << 8 | npu_pdn->devfn; 1219b521549aSAlistair Popple npu_pdn->pcidev = npu_pdev; 1220b521549aSAlistair Popple npu_pdn->pe_number = pe_num; 1221b521549aSAlistair Popple phb->ioda.pe_rmap[rid] = pe->pe_number; 1222b521549aSAlistair Popple 1223b521549aSAlistair Popple /* Map the PE to this link */ 1224b521549aSAlistair Popple rc = opal_pci_set_pe(phb->opal_id, pe_num, rid, 1225b521549aSAlistair Popple OpalPciBusAll, 1226b521549aSAlistair Popple OPAL_COMPARE_RID_DEVICE_NUMBER, 1227b521549aSAlistair Popple OPAL_COMPARE_RID_FUNCTION_NUMBER, 1228b521549aSAlistair Popple OPAL_MAP_PE); 1229b521549aSAlistair Popple WARN_ON(rc != OPAL_SUCCESS); 1230b521549aSAlistair Popple found_pe = true; 1231b521549aSAlistair Popple break; 1232b521549aSAlistair Popple } 1233b521549aSAlistair Popple } 1234b521549aSAlistair Popple 1235b521549aSAlistair Popple if (!found_pe) 1236b521549aSAlistair Popple /* 1237b521549aSAlistair Popple * Could not find an existing PE so allocate a new 1238b521549aSAlistair Popple * one. 1239b521549aSAlistair Popple */ 1240b521549aSAlistair Popple return pnv_ioda_setup_dev_PE(npu_pdev); 1241b521549aSAlistair Popple else 1242b521549aSAlistair Popple return pe; 1243b521549aSAlistair Popple } 1244b521549aSAlistair Popple 1245b521549aSAlistair Popple static void pnv_ioda_setup_npu_PEs(struct pci_bus *bus) 1246b521549aSAlistair Popple { 12475d2aa710SAlistair Popple struct pci_dev *pdev; 12485d2aa710SAlistair Popple 12495d2aa710SAlistair Popple list_for_each_entry(pdev, &bus->devices, bus_list) 1250b521549aSAlistair Popple pnv_ioda_setup_npu_PE(pdev); 12515d2aa710SAlistair Popple } 12525d2aa710SAlistair Popple 1253cad5cef6SGreg Kroah-Hartman static void pnv_pci_ioda_setup_PEs(void) 1254fb446ad0SGavin Shan { 1255fb446ad0SGavin Shan struct pci_controller *hose, *tmp; 1256262af557SGuo Chao struct pnv_phb *phb; 1257fb446ad0SGavin Shan 1258fb446ad0SGavin Shan list_for_each_entry_safe(hose, tmp, &hose_list, list_node) { 1259262af557SGuo Chao phb = hose->private_data; 126008f48f32SAlistair Popple if (phb->type == PNV_PHB_NPU) { 126108f48f32SAlistair Popple /* PE#0 is needed for error reporting */ 126208f48f32SAlistair Popple pnv_ioda_reserve_pe(phb, 0); 1263b521549aSAlistair Popple pnv_ioda_setup_npu_PEs(hose->bus); 12641ab66d1fSAlistair Popple if (phb->model == PNV_PHB_MODEL_NPU2) 12651ab66d1fSAlistair Popple pnv_npu2_init(phb); 1266ccd1c191SGavin Shan } 1267fb446ad0SGavin Shan } 1268fb446ad0SGavin Shan } 1269184cd4a3SBenjamin Herrenschmidt 1270a8b2f828SGavin Shan #ifdef CONFIG_PCI_IOV 1271ee8222feSWei Yang static int pnv_pci_vf_release_m64(struct pci_dev *pdev, u16 num_vfs) 1272781a868fSWei Yang { 1273781a868fSWei Yang struct pci_bus *bus; 1274781a868fSWei Yang struct pci_controller *hose; 1275781a868fSWei Yang struct pnv_phb *phb; 1276781a868fSWei Yang struct pci_dn *pdn; 127702639b0eSWei Yang int i, j; 1278ee8222feSWei Yang int m64_bars; 1279781a868fSWei Yang 1280781a868fSWei Yang bus = pdev->bus; 1281781a868fSWei Yang hose = pci_bus_to_host(bus); 1282781a868fSWei Yang phb = hose->private_data; 1283781a868fSWei Yang pdn = pci_get_pdn(pdev); 1284781a868fSWei Yang 1285ee8222feSWei Yang if (pdn->m64_single_mode) 1286ee8222feSWei Yang m64_bars = num_vfs; 1287ee8222feSWei Yang else 1288ee8222feSWei Yang m64_bars = 1; 1289ee8222feSWei Yang 129002639b0eSWei Yang for (i = 0; i < PCI_SRIOV_NUM_BARS; i++) 1291ee8222feSWei Yang for (j = 0; j < m64_bars; j++) { 1292ee8222feSWei Yang if (pdn->m64_map[j][i] == IODA_INVALID_M64) 1293781a868fSWei Yang continue; 1294781a868fSWei Yang opal_pci_phb_mmio_enable(phb->opal_id, 1295ee8222feSWei Yang OPAL_M64_WINDOW_TYPE, pdn->m64_map[j][i], 0); 1296ee8222feSWei Yang clear_bit(pdn->m64_map[j][i], &phb->ioda.m64_bar_alloc); 1297ee8222feSWei Yang pdn->m64_map[j][i] = IODA_INVALID_M64; 1298781a868fSWei Yang } 1299781a868fSWei Yang 1300ee8222feSWei Yang kfree(pdn->m64_map); 1301781a868fSWei Yang return 0; 1302781a868fSWei Yang } 1303781a868fSWei Yang 130402639b0eSWei Yang static int pnv_pci_vf_assign_m64(struct pci_dev *pdev, u16 num_vfs) 1305781a868fSWei Yang { 1306781a868fSWei Yang struct pci_bus *bus; 1307781a868fSWei Yang struct pci_controller *hose; 1308781a868fSWei Yang struct pnv_phb *phb; 1309781a868fSWei Yang struct pci_dn *pdn; 1310781a868fSWei Yang unsigned int win; 1311781a868fSWei Yang struct resource *res; 131202639b0eSWei Yang int i, j; 1313781a868fSWei Yang int64_t rc; 131402639b0eSWei Yang int total_vfs; 131502639b0eSWei Yang resource_size_t size, start; 131602639b0eSWei Yang int pe_num; 1317ee8222feSWei Yang int m64_bars; 1318781a868fSWei Yang 1319781a868fSWei Yang bus = pdev->bus; 1320781a868fSWei Yang hose = pci_bus_to_host(bus); 1321781a868fSWei Yang phb = hose->private_data; 1322781a868fSWei Yang pdn = pci_get_pdn(pdev); 132302639b0eSWei Yang total_vfs = pci_sriov_get_totalvfs(pdev); 1324781a868fSWei Yang 1325ee8222feSWei Yang if (pdn->m64_single_mode) 1326ee8222feSWei Yang m64_bars = num_vfs; 1327ee8222feSWei Yang else 1328ee8222feSWei Yang m64_bars = 1; 132902639b0eSWei Yang 1330fb37e128SMarkus Elfring pdn->m64_map = kmalloc_array(m64_bars, 1331fb37e128SMarkus Elfring sizeof(*pdn->m64_map), 1332fb37e128SMarkus Elfring GFP_KERNEL); 1333ee8222feSWei Yang if (!pdn->m64_map) 1334ee8222feSWei Yang return -ENOMEM; 1335ee8222feSWei Yang /* Initialize the m64_map to IODA_INVALID_M64 */ 1336ee8222feSWei Yang for (i = 0; i < m64_bars ; i++) 1337ee8222feSWei Yang for (j = 0; j < PCI_SRIOV_NUM_BARS; j++) 1338ee8222feSWei Yang pdn->m64_map[i][j] = IODA_INVALID_M64; 1339ee8222feSWei Yang 1340781a868fSWei Yang 1341781a868fSWei Yang for (i = 0; i < PCI_SRIOV_NUM_BARS; i++) { 1342781a868fSWei Yang res = &pdev->resource[i + PCI_IOV_RESOURCES]; 1343781a868fSWei Yang if (!res->flags || !res->parent) 1344781a868fSWei Yang continue; 1345781a868fSWei Yang 1346ee8222feSWei Yang for (j = 0; j < m64_bars; j++) { 1347781a868fSWei Yang do { 1348781a868fSWei Yang win = find_next_zero_bit(&phb->ioda.m64_bar_alloc, 1349781a868fSWei Yang phb->ioda.m64_bar_idx + 1, 0); 1350781a868fSWei Yang 1351781a868fSWei Yang if (win >= phb->ioda.m64_bar_idx + 1) 1352781a868fSWei Yang goto m64_failed; 1353781a868fSWei Yang } while (test_and_set_bit(win, &phb->ioda.m64_bar_alloc)); 1354781a868fSWei Yang 1355ee8222feSWei Yang pdn->m64_map[j][i] = win; 135602639b0eSWei Yang 1357ee8222feSWei Yang if (pdn->m64_single_mode) { 135802639b0eSWei Yang size = pci_iov_resource_size(pdev, 135902639b0eSWei Yang PCI_IOV_RESOURCES + i); 136002639b0eSWei Yang start = res->start + size * j; 136102639b0eSWei Yang } else { 136202639b0eSWei Yang size = resource_size(res); 136302639b0eSWei Yang start = res->start; 136402639b0eSWei Yang } 1365781a868fSWei Yang 1366781a868fSWei Yang /* Map the M64 here */ 1367ee8222feSWei Yang if (pdn->m64_single_mode) { 1368be283eebSWei Yang pe_num = pdn->pe_num_map[j]; 136902639b0eSWei Yang rc = opal_pci_map_pe_mmio_window(phb->opal_id, 137002639b0eSWei Yang pe_num, OPAL_M64_WINDOW_TYPE, 1371ee8222feSWei Yang pdn->m64_map[j][i], 0); 137202639b0eSWei Yang } 137302639b0eSWei Yang 1374781a868fSWei Yang rc = opal_pci_set_phb_mem_window(phb->opal_id, 1375781a868fSWei Yang OPAL_M64_WINDOW_TYPE, 1376ee8222feSWei Yang pdn->m64_map[j][i], 137702639b0eSWei Yang start, 1378781a868fSWei Yang 0, /* unused */ 137902639b0eSWei Yang size); 138002639b0eSWei Yang 138102639b0eSWei Yang 1382781a868fSWei Yang if (rc != OPAL_SUCCESS) { 1383781a868fSWei Yang dev_err(&pdev->dev, "Failed to map M64 window #%d: %lld\n", 1384781a868fSWei Yang win, rc); 1385781a868fSWei Yang goto m64_failed; 1386781a868fSWei Yang } 1387781a868fSWei Yang 1388ee8222feSWei Yang if (pdn->m64_single_mode) 1389781a868fSWei Yang rc = opal_pci_phb_mmio_enable(phb->opal_id, 1390ee8222feSWei Yang OPAL_M64_WINDOW_TYPE, pdn->m64_map[j][i], 2); 139102639b0eSWei Yang else 139202639b0eSWei Yang rc = opal_pci_phb_mmio_enable(phb->opal_id, 1393ee8222feSWei Yang OPAL_M64_WINDOW_TYPE, pdn->m64_map[j][i], 1); 139402639b0eSWei Yang 1395781a868fSWei Yang if (rc != OPAL_SUCCESS) { 1396781a868fSWei Yang dev_err(&pdev->dev, "Failed to enable M64 window #%d: %llx\n", 1397781a868fSWei Yang win, rc); 1398781a868fSWei Yang goto m64_failed; 1399781a868fSWei Yang } 1400781a868fSWei Yang } 140102639b0eSWei Yang } 1402781a868fSWei Yang return 0; 1403781a868fSWei Yang 1404781a868fSWei Yang m64_failed: 1405ee8222feSWei Yang pnv_pci_vf_release_m64(pdev, num_vfs); 1406781a868fSWei Yang return -EBUSY; 1407781a868fSWei Yang } 1408781a868fSWei Yang 1409c035e37bSAlexey Kardashevskiy static long pnv_pci_ioda2_unset_window(struct iommu_table_group *table_group, 1410c035e37bSAlexey Kardashevskiy int num); 1411c035e37bSAlexey Kardashevskiy static void pnv_pci_ioda2_set_bypass(struct pnv_ioda_pe *pe, bool enable); 1412c035e37bSAlexey Kardashevskiy 1413781a868fSWei Yang static void pnv_pci_ioda2_release_dma_pe(struct pci_dev *dev, struct pnv_ioda_pe *pe) 1414781a868fSWei Yang { 1415781a868fSWei Yang struct iommu_table *tbl; 1416781a868fSWei Yang int64_t rc; 1417781a868fSWei Yang 1418b348aa65SAlexey Kardashevskiy tbl = pe->table_group.tables[0]; 1419c035e37bSAlexey Kardashevskiy rc = pnv_pci_ioda2_unset_window(&pe->table_group, 0); 1420781a868fSWei Yang if (rc) 1421781a868fSWei Yang pe_warn(pe, "OPAL error %ld release DMA window\n", rc); 1422781a868fSWei Yang 1423c035e37bSAlexey Kardashevskiy pnv_pci_ioda2_set_bypass(pe, false); 14240eaf4defSAlexey Kardashevskiy if (pe->table_group.group) { 14250eaf4defSAlexey Kardashevskiy iommu_group_put(pe->table_group.group); 14260eaf4defSAlexey Kardashevskiy BUG_ON(pe->table_group.group); 1427ac9a5889SAlexey Kardashevskiy } 1428e5afdf9dSAlexey Kardashevskiy iommu_tce_table_put(tbl); 1429781a868fSWei Yang } 1430781a868fSWei Yang 1431ee8222feSWei Yang static void pnv_ioda_release_vf_PE(struct pci_dev *pdev) 1432781a868fSWei Yang { 1433781a868fSWei Yang struct pci_bus *bus; 1434781a868fSWei Yang struct pci_controller *hose; 1435781a868fSWei Yang struct pnv_phb *phb; 1436781a868fSWei Yang struct pnv_ioda_pe *pe, *pe_n; 1437781a868fSWei Yang struct pci_dn *pdn; 1438781a868fSWei Yang 1439781a868fSWei Yang bus = pdev->bus; 1440781a868fSWei Yang hose = pci_bus_to_host(bus); 1441781a868fSWei Yang phb = hose->private_data; 144202639b0eSWei Yang pdn = pci_get_pdn(pdev); 1443781a868fSWei Yang 1444781a868fSWei Yang if (!pdev->is_physfn) 1445781a868fSWei Yang return; 1446781a868fSWei Yang 1447781a868fSWei Yang list_for_each_entry_safe(pe, pe_n, &phb->ioda.pe_list, list) { 1448781a868fSWei Yang if (pe->parent_dev != pdev) 1449781a868fSWei Yang continue; 1450781a868fSWei Yang 1451781a868fSWei Yang pnv_pci_ioda2_release_dma_pe(pdev, pe); 1452781a868fSWei Yang 1453781a868fSWei Yang /* Remove from list */ 1454781a868fSWei Yang mutex_lock(&phb->ioda.pe_list_mutex); 1455781a868fSWei Yang list_del(&pe->list); 1456781a868fSWei Yang mutex_unlock(&phb->ioda.pe_list_mutex); 1457781a868fSWei Yang 1458781a868fSWei Yang pnv_ioda_deconfigure_pe(phb, pe); 1459781a868fSWei Yang 14601e916772SGavin Shan pnv_ioda_free_pe(pe); 1461781a868fSWei Yang } 1462781a868fSWei Yang } 1463781a868fSWei Yang 1464781a868fSWei Yang void pnv_pci_sriov_disable(struct pci_dev *pdev) 1465781a868fSWei Yang { 1466781a868fSWei Yang struct pci_bus *bus; 1467781a868fSWei Yang struct pci_controller *hose; 1468781a868fSWei Yang struct pnv_phb *phb; 14691e916772SGavin Shan struct pnv_ioda_pe *pe; 1470781a868fSWei Yang struct pci_dn *pdn; 1471be283eebSWei Yang u16 num_vfs, i; 1472781a868fSWei Yang 1473781a868fSWei Yang bus = pdev->bus; 1474781a868fSWei Yang hose = pci_bus_to_host(bus); 1475781a868fSWei Yang phb = hose->private_data; 1476781a868fSWei Yang pdn = pci_get_pdn(pdev); 1477781a868fSWei Yang num_vfs = pdn->num_vfs; 1478781a868fSWei Yang 1479781a868fSWei Yang /* Release VF PEs */ 1480ee8222feSWei Yang pnv_ioda_release_vf_PE(pdev); 1481781a868fSWei Yang 1482781a868fSWei Yang if (phb->type == PNV_PHB_IODA2) { 1483ee8222feSWei Yang if (!pdn->m64_single_mode) 1484be283eebSWei Yang pnv_pci_vf_resource_shift(pdev, -*pdn->pe_num_map); 1485781a868fSWei Yang 1486781a868fSWei Yang /* Release M64 windows */ 1487ee8222feSWei Yang pnv_pci_vf_release_m64(pdev, num_vfs); 1488781a868fSWei Yang 1489781a868fSWei Yang /* Release PE numbers */ 1490be283eebSWei Yang if (pdn->m64_single_mode) { 1491be283eebSWei Yang for (i = 0; i < num_vfs; i++) { 14921e916772SGavin Shan if (pdn->pe_num_map[i] == IODA_INVALID_PE) 14931e916772SGavin Shan continue; 14941e916772SGavin Shan 14951e916772SGavin Shan pe = &phb->ioda.pe_array[pdn->pe_num_map[i]]; 14961e916772SGavin Shan pnv_ioda_free_pe(pe); 1497be283eebSWei Yang } 1498be283eebSWei Yang } else 1499be283eebSWei Yang bitmap_clear(phb->ioda.pe_alloc, *pdn->pe_num_map, num_vfs); 1500be283eebSWei Yang /* Releasing pe_num_map */ 1501be283eebSWei Yang kfree(pdn->pe_num_map); 1502781a868fSWei Yang } 1503781a868fSWei Yang } 1504781a868fSWei Yang 1505781a868fSWei Yang static void pnv_pci_ioda2_setup_dma_pe(struct pnv_phb *phb, 1506781a868fSWei Yang struct pnv_ioda_pe *pe); 1507781a868fSWei Yang static void pnv_ioda_setup_vf_PE(struct pci_dev *pdev, u16 num_vfs) 1508781a868fSWei Yang { 1509781a868fSWei Yang struct pci_bus *bus; 1510781a868fSWei Yang struct pci_controller *hose; 1511781a868fSWei Yang struct pnv_phb *phb; 1512781a868fSWei Yang struct pnv_ioda_pe *pe; 1513781a868fSWei Yang int pe_num; 1514781a868fSWei Yang u16 vf_index; 1515781a868fSWei Yang struct pci_dn *pdn; 1516781a868fSWei Yang 1517781a868fSWei Yang bus = pdev->bus; 1518781a868fSWei Yang hose = pci_bus_to_host(bus); 1519781a868fSWei Yang phb = hose->private_data; 1520781a868fSWei Yang pdn = pci_get_pdn(pdev); 1521781a868fSWei Yang 1522781a868fSWei Yang if (!pdev->is_physfn) 1523781a868fSWei Yang return; 1524781a868fSWei Yang 1525781a868fSWei Yang /* Reserve PE for each VF */ 1526781a868fSWei Yang for (vf_index = 0; vf_index < num_vfs; vf_index++) { 1527be283eebSWei Yang if (pdn->m64_single_mode) 1528be283eebSWei Yang pe_num = pdn->pe_num_map[vf_index]; 1529be283eebSWei Yang else 1530be283eebSWei Yang pe_num = *pdn->pe_num_map + vf_index; 1531781a868fSWei Yang 1532781a868fSWei Yang pe = &phb->ioda.pe_array[pe_num]; 1533781a868fSWei Yang pe->pe_number = pe_num; 1534781a868fSWei Yang pe->phb = phb; 1535781a868fSWei Yang pe->flags = PNV_IODA_PE_VF; 1536781a868fSWei Yang pe->pbus = NULL; 1537781a868fSWei Yang pe->parent_dev = pdev; 1538781a868fSWei Yang pe->mve_number = -1; 1539781a868fSWei Yang pe->rid = (pci_iov_virtfn_bus(pdev, vf_index) << 8) | 1540781a868fSWei Yang pci_iov_virtfn_devfn(pdev, vf_index); 1541781a868fSWei Yang 15421f52f176SRussell Currey pe_info(pe, "VF %04d:%02d:%02d.%d associated with PE#%x\n", 1543781a868fSWei Yang hose->global_number, pdev->bus->number, 1544781a868fSWei Yang PCI_SLOT(pci_iov_virtfn_devfn(pdev, vf_index)), 1545781a868fSWei Yang PCI_FUNC(pci_iov_virtfn_devfn(pdev, vf_index)), pe_num); 1546781a868fSWei Yang 1547781a868fSWei Yang if (pnv_ioda_configure_pe(phb, pe)) { 1548781a868fSWei Yang /* XXX What do we do here ? */ 15491e916772SGavin Shan pnv_ioda_free_pe(pe); 1550781a868fSWei Yang pe->pdev = NULL; 1551781a868fSWei Yang continue; 1552781a868fSWei Yang } 1553781a868fSWei Yang 1554781a868fSWei Yang /* Put PE to the list */ 1555781a868fSWei Yang mutex_lock(&phb->ioda.pe_list_mutex); 1556781a868fSWei Yang list_add_tail(&pe->list, &phb->ioda.pe_list); 1557781a868fSWei Yang mutex_unlock(&phb->ioda.pe_list_mutex); 1558781a868fSWei Yang 1559781a868fSWei Yang pnv_pci_ioda2_setup_dma_pe(phb, pe); 1560781a868fSWei Yang } 1561781a868fSWei Yang } 1562781a868fSWei Yang 1563781a868fSWei Yang int pnv_pci_sriov_enable(struct pci_dev *pdev, u16 num_vfs) 1564781a868fSWei Yang { 1565781a868fSWei Yang struct pci_bus *bus; 1566781a868fSWei Yang struct pci_controller *hose; 1567781a868fSWei Yang struct pnv_phb *phb; 15681e916772SGavin Shan struct pnv_ioda_pe *pe; 1569781a868fSWei Yang struct pci_dn *pdn; 1570781a868fSWei Yang int ret; 1571be283eebSWei Yang u16 i; 1572781a868fSWei Yang 1573781a868fSWei Yang bus = pdev->bus; 1574781a868fSWei Yang hose = pci_bus_to_host(bus); 1575781a868fSWei Yang phb = hose->private_data; 1576781a868fSWei Yang pdn = pci_get_pdn(pdev); 1577781a868fSWei Yang 1578781a868fSWei Yang if (phb->type == PNV_PHB_IODA2) { 1579b0331854SWei Yang if (!pdn->vfs_expanded) { 1580b0331854SWei Yang dev_info(&pdev->dev, "don't support this SRIOV device" 1581b0331854SWei Yang " with non 64bit-prefetchable IOV BAR\n"); 1582b0331854SWei Yang return -ENOSPC; 1583b0331854SWei Yang } 1584b0331854SWei Yang 1585ee8222feSWei Yang /* 1586ee8222feSWei Yang * When M64 BARs functions in Single PE mode, the number of VFs 1587ee8222feSWei Yang * could be enabled must be less than the number of M64 BARs. 1588ee8222feSWei Yang */ 1589ee8222feSWei Yang if (pdn->m64_single_mode && num_vfs > phb->ioda.m64_bar_idx) { 1590ee8222feSWei Yang dev_info(&pdev->dev, "Not enough M64 BAR for VFs\n"); 1591ee8222feSWei Yang return -EBUSY; 1592ee8222feSWei Yang } 1593ee8222feSWei Yang 1594be283eebSWei Yang /* Allocating pe_num_map */ 1595be283eebSWei Yang if (pdn->m64_single_mode) 1596fb37e128SMarkus Elfring pdn->pe_num_map = kmalloc_array(num_vfs, 1597fb37e128SMarkus Elfring sizeof(*pdn->pe_num_map), 1598be283eebSWei Yang GFP_KERNEL); 1599be283eebSWei Yang else 1600be283eebSWei Yang pdn->pe_num_map = kmalloc(sizeof(*pdn->pe_num_map), GFP_KERNEL); 1601be283eebSWei Yang 1602be283eebSWei Yang if (!pdn->pe_num_map) 1603be283eebSWei Yang return -ENOMEM; 1604be283eebSWei Yang 1605be283eebSWei Yang if (pdn->m64_single_mode) 1606be283eebSWei Yang for (i = 0; i < num_vfs; i++) 1607be283eebSWei Yang pdn->pe_num_map[i] = IODA_INVALID_PE; 1608be283eebSWei Yang 1609781a868fSWei Yang /* Calculate available PE for required VFs */ 1610be283eebSWei Yang if (pdn->m64_single_mode) { 1611be283eebSWei Yang for (i = 0; i < num_vfs; i++) { 16121e916772SGavin Shan pe = pnv_ioda_alloc_pe(phb); 16131e916772SGavin Shan if (!pe) { 1614be283eebSWei Yang ret = -EBUSY; 1615be283eebSWei Yang goto m64_failed; 1616be283eebSWei Yang } 16171e916772SGavin Shan 16181e916772SGavin Shan pdn->pe_num_map[i] = pe->pe_number; 1619be283eebSWei Yang } 1620be283eebSWei Yang } else { 1621781a868fSWei Yang mutex_lock(&phb->ioda.pe_alloc_mutex); 1622be283eebSWei Yang *pdn->pe_num_map = bitmap_find_next_zero_area( 162392b8f137SGavin Shan phb->ioda.pe_alloc, phb->ioda.total_pe_num, 1624781a868fSWei Yang 0, num_vfs, 0); 162592b8f137SGavin Shan if (*pdn->pe_num_map >= phb->ioda.total_pe_num) { 1626781a868fSWei Yang mutex_unlock(&phb->ioda.pe_alloc_mutex); 1627781a868fSWei Yang dev_info(&pdev->dev, "Failed to enable VF%d\n", num_vfs); 1628be283eebSWei Yang kfree(pdn->pe_num_map); 1629781a868fSWei Yang return -EBUSY; 1630781a868fSWei Yang } 1631be283eebSWei Yang bitmap_set(phb->ioda.pe_alloc, *pdn->pe_num_map, num_vfs); 1632781a868fSWei Yang mutex_unlock(&phb->ioda.pe_alloc_mutex); 1633be283eebSWei Yang } 1634be283eebSWei Yang pdn->num_vfs = num_vfs; 1635781a868fSWei Yang 1636781a868fSWei Yang /* Assign M64 window accordingly */ 163702639b0eSWei Yang ret = pnv_pci_vf_assign_m64(pdev, num_vfs); 1638781a868fSWei Yang if (ret) { 1639781a868fSWei Yang dev_info(&pdev->dev, "Not enough M64 window resources\n"); 1640781a868fSWei Yang goto m64_failed; 1641781a868fSWei Yang } 1642781a868fSWei Yang 1643781a868fSWei Yang /* 1644781a868fSWei Yang * When using one M64 BAR to map one IOV BAR, we need to shift 1645781a868fSWei Yang * the IOV BAR according to the PE# allocated to the VFs. 1646781a868fSWei Yang * Otherwise, the PE# for the VF will conflict with others. 1647781a868fSWei Yang */ 1648ee8222feSWei Yang if (!pdn->m64_single_mode) { 1649be283eebSWei Yang ret = pnv_pci_vf_resource_shift(pdev, *pdn->pe_num_map); 1650781a868fSWei Yang if (ret) 1651781a868fSWei Yang goto m64_failed; 1652781a868fSWei Yang } 165302639b0eSWei Yang } 1654781a868fSWei Yang 1655781a868fSWei Yang /* Setup VF PEs */ 1656781a868fSWei Yang pnv_ioda_setup_vf_PE(pdev, num_vfs); 1657781a868fSWei Yang 1658781a868fSWei Yang return 0; 1659781a868fSWei Yang 1660781a868fSWei Yang m64_failed: 1661be283eebSWei Yang if (pdn->m64_single_mode) { 1662be283eebSWei Yang for (i = 0; i < num_vfs; i++) { 16631e916772SGavin Shan if (pdn->pe_num_map[i] == IODA_INVALID_PE) 16641e916772SGavin Shan continue; 16651e916772SGavin Shan 16661e916772SGavin Shan pe = &phb->ioda.pe_array[pdn->pe_num_map[i]]; 16671e916772SGavin Shan pnv_ioda_free_pe(pe); 1668be283eebSWei Yang } 1669be283eebSWei Yang } else 1670be283eebSWei Yang bitmap_clear(phb->ioda.pe_alloc, *pdn->pe_num_map, num_vfs); 1671be283eebSWei Yang 1672be283eebSWei Yang /* Releasing pe_num_map */ 1673be283eebSWei Yang kfree(pdn->pe_num_map); 1674781a868fSWei Yang 1675781a868fSWei Yang return ret; 1676781a868fSWei Yang } 1677781a868fSWei Yang 1678a8b2f828SGavin Shan int pcibios_sriov_disable(struct pci_dev *pdev) 1679a8b2f828SGavin Shan { 1680781a868fSWei Yang pnv_pci_sriov_disable(pdev); 1681781a868fSWei Yang 1682a8b2f828SGavin Shan /* Release PCI data */ 1683a8b2f828SGavin Shan remove_dev_pci_data(pdev); 1684a8b2f828SGavin Shan return 0; 1685a8b2f828SGavin Shan } 1686a8b2f828SGavin Shan 1687a8b2f828SGavin Shan int pcibios_sriov_enable(struct pci_dev *pdev, u16 num_vfs) 1688a8b2f828SGavin Shan { 1689a8b2f828SGavin Shan /* Allocate PCI data */ 1690a8b2f828SGavin Shan add_dev_pci_data(pdev); 1691781a868fSWei Yang 1692ee8222feSWei Yang return pnv_pci_sriov_enable(pdev, num_vfs); 1693a8b2f828SGavin Shan } 1694a8b2f828SGavin Shan #endif /* CONFIG_PCI_IOV */ 1695a8b2f828SGavin Shan 1696959c9bddSGavin Shan static void pnv_pci_ioda_dma_dev_setup(struct pnv_phb *phb, struct pci_dev *pdev) 1697184cd4a3SBenjamin Herrenschmidt { 1698b72c1f65SBenjamin Herrenschmidt struct pci_dn *pdn = pci_get_pdn(pdev); 1699959c9bddSGavin Shan struct pnv_ioda_pe *pe; 1700184cd4a3SBenjamin Herrenschmidt 1701959c9bddSGavin Shan /* 1702959c9bddSGavin Shan * The function can be called while the PE# 1703959c9bddSGavin Shan * hasn't been assigned. Do nothing for the 1704959c9bddSGavin Shan * case. 1705959c9bddSGavin Shan */ 1706959c9bddSGavin Shan if (!pdn || pdn->pe_number == IODA_INVALID_PE) 1707959c9bddSGavin Shan return; 1708184cd4a3SBenjamin Herrenschmidt 1709959c9bddSGavin Shan pe = &phb->ioda.pe_array[pdn->pe_number]; 1710cd15b048SBenjamin Herrenschmidt WARN_ON(get_dma_ops(&pdev->dev) != &dma_iommu_ops); 17110e1ffef0SAlexey Kardashevskiy set_dma_offset(&pdev->dev, pe->tce_bypass_base); 1712b348aa65SAlexey Kardashevskiy set_iommu_table_base(&pdev->dev, pe->table_group.tables[0]); 17134617082eSAlexey Kardashevskiy /* 17144617082eSAlexey Kardashevskiy * Note: iommu_add_device() will fail here as 17154617082eSAlexey Kardashevskiy * for physical PE: the device is already added by now; 17164617082eSAlexey Kardashevskiy * for virtual PE: sysfs entries are not ready yet and 17174617082eSAlexey Kardashevskiy * tce_iommu_bus_notifier will add the device to a group later. 17184617082eSAlexey Kardashevskiy */ 1719184cd4a3SBenjamin Herrenschmidt } 1720184cd4a3SBenjamin Herrenschmidt 1721a0f98629SRussell Currey static bool pnv_pci_ioda_pe_single_vendor(struct pnv_ioda_pe *pe) 1722a0f98629SRussell Currey { 1723a0f98629SRussell Currey unsigned short vendor = 0; 1724a0f98629SRussell Currey struct pci_dev *pdev; 1725a0f98629SRussell Currey 1726a0f98629SRussell Currey if (pe->device_count == 1) 1727a0f98629SRussell Currey return true; 1728a0f98629SRussell Currey 1729a0f98629SRussell Currey /* pe->pdev should be set if it's a single device, pe->pbus if not */ 1730a0f98629SRussell Currey if (!pe->pbus) 1731a0f98629SRussell Currey return true; 1732a0f98629SRussell Currey 1733a0f98629SRussell Currey list_for_each_entry(pdev, &pe->pbus->devices, bus_list) { 1734a0f98629SRussell Currey if (!vendor) { 1735a0f98629SRussell Currey vendor = pdev->vendor; 1736a0f98629SRussell Currey continue; 1737a0f98629SRussell Currey } 1738a0f98629SRussell Currey 1739a0f98629SRussell Currey if (pdev->vendor != vendor) 1740a0f98629SRussell Currey return false; 1741a0f98629SRussell Currey } 1742a0f98629SRussell Currey 1743a0f98629SRussell Currey return true; 1744a0f98629SRussell Currey } 1745a0f98629SRussell Currey 1746763d2d8dSDaniel Axtens static int pnv_pci_ioda_dma_set_mask(struct pci_dev *pdev, u64 dma_mask) 1747cd15b048SBenjamin Herrenschmidt { 1748763d2d8dSDaniel Axtens struct pci_controller *hose = pci_bus_to_host(pdev->bus); 1749763d2d8dSDaniel Axtens struct pnv_phb *phb = hose->private_data; 1750cd15b048SBenjamin Herrenschmidt struct pci_dn *pdn = pci_get_pdn(pdev); 1751cd15b048SBenjamin Herrenschmidt struct pnv_ioda_pe *pe; 1752cd15b048SBenjamin Herrenschmidt uint64_t top; 1753cd15b048SBenjamin Herrenschmidt bool bypass = false; 1754cd15b048SBenjamin Herrenschmidt 1755cd15b048SBenjamin Herrenschmidt if (WARN_ON(!pdn || pdn->pe_number == IODA_INVALID_PE)) 1756cd15b048SBenjamin Herrenschmidt return -ENODEV;; 1757cd15b048SBenjamin Herrenschmidt 1758cd15b048SBenjamin Herrenschmidt pe = &phb->ioda.pe_array[pdn->pe_number]; 1759cd15b048SBenjamin Herrenschmidt if (pe->tce_bypass_enabled) { 1760cd15b048SBenjamin Herrenschmidt top = pe->tce_bypass_base + memblock_end_of_DRAM() - 1; 1761cd15b048SBenjamin Herrenschmidt bypass = (dma_mask >= top); 1762cd15b048SBenjamin Herrenschmidt } 1763cd15b048SBenjamin Herrenschmidt 1764cd15b048SBenjamin Herrenschmidt if (bypass) { 1765cd15b048SBenjamin Herrenschmidt dev_info(&pdev->dev, "Using 64-bit DMA iommu bypass\n"); 1766cd15b048SBenjamin Herrenschmidt set_dma_ops(&pdev->dev, &dma_direct_ops); 1767cd15b048SBenjamin Herrenschmidt } else { 1768cd15b048SBenjamin Herrenschmidt dev_info(&pdev->dev, "Using 32-bit DMA via iommu\n"); 1769cd15b048SBenjamin Herrenschmidt set_dma_ops(&pdev->dev, &dma_iommu_ops); 1770cd15b048SBenjamin Herrenschmidt } 1771a32305bfSBrian W Hart *pdev->dev.dma_mask = dma_mask; 17725d2aa710SAlistair Popple 17735d2aa710SAlistair Popple /* Update peer npu devices */ 1774f9f83456SAlexey Kardashevskiy pnv_npu_try_dma_set_bypass(pdev, bypass); 17755d2aa710SAlistair Popple 1776cd15b048SBenjamin Herrenschmidt return 0; 1777cd15b048SBenjamin Herrenschmidt } 1778cd15b048SBenjamin Herrenschmidt 177953522982SAndrew Donnellan static u64 pnv_pci_ioda_dma_get_required_mask(struct pci_dev *pdev) 1780fe7e85c6SGavin Shan { 178153522982SAndrew Donnellan struct pci_controller *hose = pci_bus_to_host(pdev->bus); 178253522982SAndrew Donnellan struct pnv_phb *phb = hose->private_data; 1783fe7e85c6SGavin Shan struct pci_dn *pdn = pci_get_pdn(pdev); 1784fe7e85c6SGavin Shan struct pnv_ioda_pe *pe; 1785fe7e85c6SGavin Shan u64 end, mask; 1786fe7e85c6SGavin Shan 1787fe7e85c6SGavin Shan if (WARN_ON(!pdn || pdn->pe_number == IODA_INVALID_PE)) 1788fe7e85c6SGavin Shan return 0; 1789fe7e85c6SGavin Shan 1790fe7e85c6SGavin Shan pe = &phb->ioda.pe_array[pdn->pe_number]; 1791fe7e85c6SGavin Shan if (!pe->tce_bypass_enabled) 1792fe7e85c6SGavin Shan return __dma_get_required_mask(&pdev->dev); 1793fe7e85c6SGavin Shan 1794fe7e85c6SGavin Shan 1795fe7e85c6SGavin Shan end = pe->tce_bypass_base + memblock_end_of_DRAM(); 1796fe7e85c6SGavin Shan mask = 1ULL << (fls64(end) - 1); 1797fe7e85c6SGavin Shan mask += mask - 1; 1798fe7e85c6SGavin Shan 1799fe7e85c6SGavin Shan return mask; 1800fe7e85c6SGavin Shan } 1801fe7e85c6SGavin Shan 1802dff4a39eSGavin Shan static void pnv_ioda_setup_bus_dma(struct pnv_ioda_pe *pe, 1803db08e1d5SAlexey Kardashevskiy struct pci_bus *bus, 1804db08e1d5SAlexey Kardashevskiy bool add_to_group) 180574251fe2SBenjamin Herrenschmidt { 180674251fe2SBenjamin Herrenschmidt struct pci_dev *dev; 180774251fe2SBenjamin Herrenschmidt 180874251fe2SBenjamin Herrenschmidt list_for_each_entry(dev, &bus->devices, bus_list) { 1809b348aa65SAlexey Kardashevskiy set_iommu_table_base(&dev->dev, pe->table_group.tables[0]); 1810e91c2511SBenjamin Herrenschmidt set_dma_offset(&dev->dev, pe->tce_bypass_base); 1811db08e1d5SAlexey Kardashevskiy if (add_to_group) 18124617082eSAlexey Kardashevskiy iommu_add_device(&dev->dev); 1813dff4a39eSGavin Shan 18145c89a87dSAlexey Kardashevskiy if ((pe->flags & PNV_IODA_PE_BUS_ALL) && dev->subordinate) 1815db08e1d5SAlexey Kardashevskiy pnv_ioda_setup_bus_dma(pe, dev->subordinate, 1816db08e1d5SAlexey Kardashevskiy add_to_group); 181774251fe2SBenjamin Herrenschmidt } 181874251fe2SBenjamin Herrenschmidt } 181974251fe2SBenjamin Herrenschmidt 1820fd141d1aSBenjamin Herrenschmidt static inline __be64 __iomem *pnv_ioda_get_inval_reg(struct pnv_phb *phb, 1821fd141d1aSBenjamin Herrenschmidt bool real_mode) 1822fd141d1aSBenjamin Herrenschmidt { 1823fd141d1aSBenjamin Herrenschmidt return real_mode ? (__be64 __iomem *)(phb->regs_phys + 0x210) : 1824fd141d1aSBenjamin Herrenschmidt (phb->regs + 0x210); 1825fd141d1aSBenjamin Herrenschmidt } 1826fd141d1aSBenjamin Herrenschmidt 1827a34ab7c3SBenjamin Herrenschmidt static void pnv_pci_p7ioc_tce_invalidate(struct iommu_table *tbl, 1828decbda25SAlexey Kardashevskiy unsigned long index, unsigned long npages, bool rm) 18294cce9550SGavin Shan { 18300eaf4defSAlexey Kardashevskiy struct iommu_table_group_link *tgl = list_first_entry_or_null( 18310eaf4defSAlexey Kardashevskiy &tbl->it_group_list, struct iommu_table_group_link, 18320eaf4defSAlexey Kardashevskiy next); 18330eaf4defSAlexey Kardashevskiy struct pnv_ioda_pe *pe = container_of(tgl->table_group, 1834b348aa65SAlexey Kardashevskiy struct pnv_ioda_pe, table_group); 1835fd141d1aSBenjamin Herrenschmidt __be64 __iomem *invalidate = pnv_ioda_get_inval_reg(pe->phb, rm); 18364cce9550SGavin Shan unsigned long start, end, inc; 18374cce9550SGavin Shan 1838decbda25SAlexey Kardashevskiy start = __pa(((__be64 *)tbl->it_base) + index - tbl->it_offset); 1839decbda25SAlexey Kardashevskiy end = __pa(((__be64 *)tbl->it_base) + index - tbl->it_offset + 1840decbda25SAlexey Kardashevskiy npages - 1); 18414cce9550SGavin Shan 18424cce9550SGavin Shan /* p7ioc-style invalidation, 2 TCEs per write */ 18434cce9550SGavin Shan start |= (1ull << 63); 18444cce9550SGavin Shan end |= (1ull << 63); 18454cce9550SGavin Shan inc = 16; 18464cce9550SGavin Shan end |= inc - 1; /* round up end to be different than start */ 18474cce9550SGavin Shan 18484cce9550SGavin Shan mb(); /* Ensure above stores are visible */ 18494cce9550SGavin Shan while (start <= end) { 18508e0a1611SAlexey Kardashevskiy if (rm) 18513ad26e5cSBenjamin Herrenschmidt __raw_rm_writeq(cpu_to_be64(start), invalidate); 18528e0a1611SAlexey Kardashevskiy else 18533a1a4661SBenjamin Herrenschmidt __raw_writeq(cpu_to_be64(start), invalidate); 18544cce9550SGavin Shan start += inc; 18554cce9550SGavin Shan } 18564cce9550SGavin Shan 18574cce9550SGavin Shan /* 18584cce9550SGavin Shan * The iommu layer will do another mb() for us on build() 18594cce9550SGavin Shan * and we don't care on free() 18604cce9550SGavin Shan */ 18614cce9550SGavin Shan } 18624cce9550SGavin Shan 1863decbda25SAlexey Kardashevskiy static int pnv_ioda1_tce_build(struct iommu_table *tbl, long index, 1864decbda25SAlexey Kardashevskiy long npages, unsigned long uaddr, 1865decbda25SAlexey Kardashevskiy enum dma_data_direction direction, 186600085f1eSKrzysztof Kozlowski unsigned long attrs) 1867decbda25SAlexey Kardashevskiy { 1868decbda25SAlexey Kardashevskiy int ret = pnv_tce_build(tbl, index, npages, uaddr, direction, 1869decbda25SAlexey Kardashevskiy attrs); 1870decbda25SAlexey Kardashevskiy 187108acce1cSBenjamin Herrenschmidt if (!ret) 1872a34ab7c3SBenjamin Herrenschmidt pnv_pci_p7ioc_tce_invalidate(tbl, index, npages, false); 1873decbda25SAlexey Kardashevskiy 1874decbda25SAlexey Kardashevskiy return ret; 1875decbda25SAlexey Kardashevskiy } 1876decbda25SAlexey Kardashevskiy 187705c6cfb9SAlexey Kardashevskiy #ifdef CONFIG_IOMMU_API 187805c6cfb9SAlexey Kardashevskiy static int pnv_ioda1_tce_xchg(struct iommu_table *tbl, long index, 187905c6cfb9SAlexey Kardashevskiy unsigned long *hpa, enum dma_data_direction *direction) 188005c6cfb9SAlexey Kardashevskiy { 188105c6cfb9SAlexey Kardashevskiy long ret = pnv_tce_xchg(tbl, index, hpa, direction); 188205c6cfb9SAlexey Kardashevskiy 188308acce1cSBenjamin Herrenschmidt if (!ret) 1884a34ab7c3SBenjamin Herrenschmidt pnv_pci_p7ioc_tce_invalidate(tbl, index, 1, false); 188505c6cfb9SAlexey Kardashevskiy 188605c6cfb9SAlexey Kardashevskiy return ret; 188705c6cfb9SAlexey Kardashevskiy } 1888a540aa56SAlexey Kardashevskiy 1889a540aa56SAlexey Kardashevskiy static int pnv_ioda1_tce_xchg_rm(struct iommu_table *tbl, long index, 1890a540aa56SAlexey Kardashevskiy unsigned long *hpa, enum dma_data_direction *direction) 1891a540aa56SAlexey Kardashevskiy { 1892a540aa56SAlexey Kardashevskiy long ret = pnv_tce_xchg(tbl, index, hpa, direction); 1893a540aa56SAlexey Kardashevskiy 1894a540aa56SAlexey Kardashevskiy if (!ret) 1895a540aa56SAlexey Kardashevskiy pnv_pci_p7ioc_tce_invalidate(tbl, index, 1, true); 1896a540aa56SAlexey Kardashevskiy 1897a540aa56SAlexey Kardashevskiy return ret; 1898a540aa56SAlexey Kardashevskiy } 189905c6cfb9SAlexey Kardashevskiy #endif 190005c6cfb9SAlexey Kardashevskiy 1901decbda25SAlexey Kardashevskiy static void pnv_ioda1_tce_free(struct iommu_table *tbl, long index, 1902decbda25SAlexey Kardashevskiy long npages) 1903decbda25SAlexey Kardashevskiy { 1904decbda25SAlexey Kardashevskiy pnv_tce_free(tbl, index, npages); 1905decbda25SAlexey Kardashevskiy 1906a34ab7c3SBenjamin Herrenschmidt pnv_pci_p7ioc_tce_invalidate(tbl, index, npages, false); 1907decbda25SAlexey Kardashevskiy } 1908decbda25SAlexey Kardashevskiy 1909da004c36SAlexey Kardashevskiy static struct iommu_table_ops pnv_ioda1_iommu_ops = { 1910decbda25SAlexey Kardashevskiy .set = pnv_ioda1_tce_build, 191105c6cfb9SAlexey Kardashevskiy #ifdef CONFIG_IOMMU_API 191205c6cfb9SAlexey Kardashevskiy .exchange = pnv_ioda1_tce_xchg, 1913a540aa56SAlexey Kardashevskiy .exchange_rm = pnv_ioda1_tce_xchg_rm, 191405c6cfb9SAlexey Kardashevskiy #endif 1915decbda25SAlexey Kardashevskiy .clear = pnv_ioda1_tce_free, 1916da004c36SAlexey Kardashevskiy .get = pnv_tce_get, 1917da004c36SAlexey Kardashevskiy }; 1918da004c36SAlexey Kardashevskiy 1919a34ab7c3SBenjamin Herrenschmidt #define PHB3_TCE_KILL_INVAL_ALL PPC_BIT(0) 1920a34ab7c3SBenjamin Herrenschmidt #define PHB3_TCE_KILL_INVAL_PE PPC_BIT(1) 1921a34ab7c3SBenjamin Herrenschmidt #define PHB3_TCE_KILL_INVAL_ONE PPC_BIT(2) 1922bef9253fSAlexey Kardashevskiy 19236b3d12a9SAlistair Popple static void pnv_pci_phb3_tce_invalidate_entire(struct pnv_phb *phb, bool rm) 19240bbcdb43SAlexey Kardashevskiy { 1925fd141d1aSBenjamin Herrenschmidt __be64 __iomem *invalidate = pnv_ioda_get_inval_reg(phb, rm); 1926a34ab7c3SBenjamin Herrenschmidt const unsigned long val = PHB3_TCE_KILL_INVAL_ALL; 19270bbcdb43SAlexey Kardashevskiy 19280bbcdb43SAlexey Kardashevskiy mb(); /* Ensure previous TCE table stores are visible */ 19290bbcdb43SAlexey Kardashevskiy if (rm) 1930fd141d1aSBenjamin Herrenschmidt __raw_rm_writeq(cpu_to_be64(val), invalidate); 19310bbcdb43SAlexey Kardashevskiy else 1932fd141d1aSBenjamin Herrenschmidt __raw_writeq(cpu_to_be64(val), invalidate); 19330bbcdb43SAlexey Kardashevskiy } 19340bbcdb43SAlexey Kardashevskiy 1935a34ab7c3SBenjamin Herrenschmidt static inline void pnv_pci_phb3_tce_invalidate_pe(struct pnv_ioda_pe *pe) 19365780fb04SAlexey Kardashevskiy { 19375780fb04SAlexey Kardashevskiy /* 01xb - invalidate TCEs that match the specified PE# */ 1938fd141d1aSBenjamin Herrenschmidt __be64 __iomem *invalidate = pnv_ioda_get_inval_reg(pe->phb, false); 1939a34ab7c3SBenjamin Herrenschmidt unsigned long val = PHB3_TCE_KILL_INVAL_PE | (pe->pe_number & 0xFF); 19405780fb04SAlexey Kardashevskiy 19415780fb04SAlexey Kardashevskiy mb(); /* Ensure above stores are visible */ 1942fd141d1aSBenjamin Herrenschmidt __raw_writeq(cpu_to_be64(val), invalidate); 19435780fb04SAlexey Kardashevskiy } 19445780fb04SAlexey Kardashevskiy 1945fd141d1aSBenjamin Herrenschmidt static void pnv_pci_phb3_tce_invalidate(struct pnv_ioda_pe *pe, bool rm, 1946fd141d1aSBenjamin Herrenschmidt unsigned shift, unsigned long index, 1947fd141d1aSBenjamin Herrenschmidt unsigned long npages) 19484cce9550SGavin Shan { 19494d902195SAlexey Kardashevskiy __be64 __iomem *invalidate = pnv_ioda_get_inval_reg(pe->phb, rm); 19504cce9550SGavin Shan unsigned long start, end, inc; 19514cce9550SGavin Shan 19524cce9550SGavin Shan /* We'll invalidate DMA address in PE scope */ 1953a34ab7c3SBenjamin Herrenschmidt start = PHB3_TCE_KILL_INVAL_ONE; 1954fd141d1aSBenjamin Herrenschmidt start |= (pe->pe_number & 0xFF); 19554cce9550SGavin Shan end = start; 19564cce9550SGavin Shan 19574cce9550SGavin Shan /* Figure out the start, end and step */ 1958decbda25SAlexey Kardashevskiy start |= (index << shift); 1959decbda25SAlexey Kardashevskiy end |= ((index + npages - 1) << shift); 1960b0376c9bSAlexey Kardashevskiy inc = (0x1ull << shift); 19614cce9550SGavin Shan mb(); 19624cce9550SGavin Shan 19634cce9550SGavin Shan while (start <= end) { 19648e0a1611SAlexey Kardashevskiy if (rm) 19653ad26e5cSBenjamin Herrenschmidt __raw_rm_writeq(cpu_to_be64(start), invalidate); 19668e0a1611SAlexey Kardashevskiy else 19673a1a4661SBenjamin Herrenschmidt __raw_writeq(cpu_to_be64(start), invalidate); 19684cce9550SGavin Shan start += inc; 19694cce9550SGavin Shan } 19704cce9550SGavin Shan } 19714cce9550SGavin Shan 1972f0228c41SBenjamin Herrenschmidt static inline void pnv_pci_ioda2_tce_invalidate_pe(struct pnv_ioda_pe *pe) 1973f0228c41SBenjamin Herrenschmidt { 1974f0228c41SBenjamin Herrenschmidt struct pnv_phb *phb = pe->phb; 1975f0228c41SBenjamin Herrenschmidt 1976f0228c41SBenjamin Herrenschmidt if (phb->model == PNV_PHB_MODEL_PHB3 && phb->regs) 1977f0228c41SBenjamin Herrenschmidt pnv_pci_phb3_tce_invalidate_pe(pe); 1978f0228c41SBenjamin Herrenschmidt else 1979f0228c41SBenjamin Herrenschmidt opal_pci_tce_kill(phb->opal_id, OPAL_PCI_TCE_KILL_PE, 1980f0228c41SBenjamin Herrenschmidt pe->pe_number, 0, 0, 0); 1981f0228c41SBenjamin Herrenschmidt } 1982f0228c41SBenjamin Herrenschmidt 1983e57080f1SAlexey Kardashevskiy static void pnv_pci_ioda2_tce_invalidate(struct iommu_table *tbl, 1984e57080f1SAlexey Kardashevskiy unsigned long index, unsigned long npages, bool rm) 1985e57080f1SAlexey Kardashevskiy { 1986e57080f1SAlexey Kardashevskiy struct iommu_table_group_link *tgl; 1987e57080f1SAlexey Kardashevskiy 1988a540aa56SAlexey Kardashevskiy list_for_each_entry_lockless(tgl, &tbl->it_group_list, next) { 1989e57080f1SAlexey Kardashevskiy struct pnv_ioda_pe *pe = container_of(tgl->table_group, 1990e57080f1SAlexey Kardashevskiy struct pnv_ioda_pe, table_group); 1991f0228c41SBenjamin Herrenschmidt struct pnv_phb *phb = pe->phb; 1992f0228c41SBenjamin Herrenschmidt unsigned int shift = tbl->it_page_shift; 1993f0228c41SBenjamin Herrenschmidt 1994616badd2SAlistair Popple /* 1995616badd2SAlistair Popple * NVLink1 can use the TCE kill register directly as 1996616badd2SAlistair Popple * it's the same as PHB3. NVLink2 is different and 1997616badd2SAlistair Popple * should go via the OPAL call. 1998616badd2SAlistair Popple */ 1999616badd2SAlistair Popple if (phb->model == PNV_PHB_MODEL_NPU) { 20000bbcdb43SAlexey Kardashevskiy /* 20010bbcdb43SAlexey Kardashevskiy * The NVLink hardware does not support TCE kill 20020bbcdb43SAlexey Kardashevskiy * per TCE entry so we have to invalidate 20030bbcdb43SAlexey Kardashevskiy * the entire cache for it. 20040bbcdb43SAlexey Kardashevskiy */ 2005f0228c41SBenjamin Herrenschmidt pnv_pci_phb3_tce_invalidate_entire(phb, rm); 20065d2aa710SAlistair Popple continue; 20075d2aa710SAlistair Popple } 2008f0228c41SBenjamin Herrenschmidt if (phb->model == PNV_PHB_MODEL_PHB3 && phb->regs) 2009f0228c41SBenjamin Herrenschmidt pnv_pci_phb3_tce_invalidate(pe, rm, shift, 201085674868SAlexey Kardashevskiy index, npages); 2011f0228c41SBenjamin Herrenschmidt else 2012f0228c41SBenjamin Herrenschmidt opal_pci_tce_kill(phb->opal_id, 2013f0228c41SBenjamin Herrenschmidt OPAL_PCI_TCE_KILL_PAGES, 2014f0228c41SBenjamin Herrenschmidt pe->pe_number, 1u << shift, 2015f0228c41SBenjamin Herrenschmidt index << shift, npages); 2016e57080f1SAlexey Kardashevskiy } 2017e57080f1SAlexey Kardashevskiy } 2018e57080f1SAlexey Kardashevskiy 20196b3d12a9SAlistair Popple void pnv_pci_ioda2_tce_invalidate_entire(struct pnv_phb *phb, bool rm) 20206b3d12a9SAlistair Popple { 20216b3d12a9SAlistair Popple if (phb->model == PNV_PHB_MODEL_NPU || phb->model == PNV_PHB_MODEL_PHB3) 20226b3d12a9SAlistair Popple pnv_pci_phb3_tce_invalidate_entire(phb, rm); 20236b3d12a9SAlistair Popple else 20246b3d12a9SAlistair Popple opal_pci_tce_kill(phb->opal_id, OPAL_PCI_TCE_KILL, 0, 0, 0, 0); 20256b3d12a9SAlistair Popple } 20266b3d12a9SAlistair Popple 2027decbda25SAlexey Kardashevskiy static int pnv_ioda2_tce_build(struct iommu_table *tbl, long index, 2028decbda25SAlexey Kardashevskiy long npages, unsigned long uaddr, 2029decbda25SAlexey Kardashevskiy enum dma_data_direction direction, 203000085f1eSKrzysztof Kozlowski unsigned long attrs) 20314cce9550SGavin Shan { 2032decbda25SAlexey Kardashevskiy int ret = pnv_tce_build(tbl, index, npages, uaddr, direction, 2033decbda25SAlexey Kardashevskiy attrs); 20344cce9550SGavin Shan 203508acce1cSBenjamin Herrenschmidt if (!ret) 2036decbda25SAlexey Kardashevskiy pnv_pci_ioda2_tce_invalidate(tbl, index, npages, false); 2037decbda25SAlexey Kardashevskiy 2038decbda25SAlexey Kardashevskiy return ret; 2039decbda25SAlexey Kardashevskiy } 2040decbda25SAlexey Kardashevskiy 204105c6cfb9SAlexey Kardashevskiy #ifdef CONFIG_IOMMU_API 204205c6cfb9SAlexey Kardashevskiy static int pnv_ioda2_tce_xchg(struct iommu_table *tbl, long index, 204305c6cfb9SAlexey Kardashevskiy unsigned long *hpa, enum dma_data_direction *direction) 204405c6cfb9SAlexey Kardashevskiy { 204505c6cfb9SAlexey Kardashevskiy long ret = pnv_tce_xchg(tbl, index, hpa, direction); 204605c6cfb9SAlexey Kardashevskiy 204708acce1cSBenjamin Herrenschmidt if (!ret) 204805c6cfb9SAlexey Kardashevskiy pnv_pci_ioda2_tce_invalidate(tbl, index, 1, false); 204905c6cfb9SAlexey Kardashevskiy 205005c6cfb9SAlexey Kardashevskiy return ret; 205105c6cfb9SAlexey Kardashevskiy } 2052a540aa56SAlexey Kardashevskiy 2053a540aa56SAlexey Kardashevskiy static int pnv_ioda2_tce_xchg_rm(struct iommu_table *tbl, long index, 2054a540aa56SAlexey Kardashevskiy unsigned long *hpa, enum dma_data_direction *direction) 2055a540aa56SAlexey Kardashevskiy { 2056a540aa56SAlexey Kardashevskiy long ret = pnv_tce_xchg(tbl, index, hpa, direction); 2057a540aa56SAlexey Kardashevskiy 2058a540aa56SAlexey Kardashevskiy if (!ret) 2059a540aa56SAlexey Kardashevskiy pnv_pci_ioda2_tce_invalidate(tbl, index, 1, true); 2060a540aa56SAlexey Kardashevskiy 2061a540aa56SAlexey Kardashevskiy return ret; 2062a540aa56SAlexey Kardashevskiy } 206305c6cfb9SAlexey Kardashevskiy #endif 206405c6cfb9SAlexey Kardashevskiy 2065decbda25SAlexey Kardashevskiy static void pnv_ioda2_tce_free(struct iommu_table *tbl, long index, 2066decbda25SAlexey Kardashevskiy long npages) 2067decbda25SAlexey Kardashevskiy { 2068decbda25SAlexey Kardashevskiy pnv_tce_free(tbl, index, npages); 2069decbda25SAlexey Kardashevskiy 2070decbda25SAlexey Kardashevskiy pnv_pci_ioda2_tce_invalidate(tbl, index, npages, false); 20714cce9550SGavin Shan } 20724cce9550SGavin Shan 20734793d65dSAlexey Kardashevskiy static void pnv_ioda2_table_free(struct iommu_table *tbl) 20744793d65dSAlexey Kardashevskiy { 20754793d65dSAlexey Kardashevskiy pnv_pci_ioda2_table_free_pages(tbl); 20764793d65dSAlexey Kardashevskiy } 20774793d65dSAlexey Kardashevskiy 2078da004c36SAlexey Kardashevskiy static struct iommu_table_ops pnv_ioda2_iommu_ops = { 2079decbda25SAlexey Kardashevskiy .set = pnv_ioda2_tce_build, 208005c6cfb9SAlexey Kardashevskiy #ifdef CONFIG_IOMMU_API 208105c6cfb9SAlexey Kardashevskiy .exchange = pnv_ioda2_tce_xchg, 2082a540aa56SAlexey Kardashevskiy .exchange_rm = pnv_ioda2_tce_xchg_rm, 208305c6cfb9SAlexey Kardashevskiy #endif 2084decbda25SAlexey Kardashevskiy .clear = pnv_ioda2_tce_free, 2085da004c36SAlexey Kardashevskiy .get = pnv_tce_get, 20864793d65dSAlexey Kardashevskiy .free = pnv_ioda2_table_free, 2087da004c36SAlexey Kardashevskiy }; 2088da004c36SAlexey Kardashevskiy 2089801846d1SGavin Shan static int pnv_pci_ioda_dev_dma_weight(struct pci_dev *dev, void *data) 2090801846d1SGavin Shan { 2091801846d1SGavin Shan unsigned int *weight = (unsigned int *)data; 2092801846d1SGavin Shan 2093801846d1SGavin Shan /* This is quite simplistic. The "base" weight of a device 2094801846d1SGavin Shan * is 10. 0 means no DMA is to be accounted for it. 2095801846d1SGavin Shan */ 2096801846d1SGavin Shan if (dev->hdr_type != PCI_HEADER_TYPE_NORMAL) 2097801846d1SGavin Shan return 0; 2098801846d1SGavin Shan 2099801846d1SGavin Shan if (dev->class == PCI_CLASS_SERIAL_USB_UHCI || 2100801846d1SGavin Shan dev->class == PCI_CLASS_SERIAL_USB_OHCI || 2101801846d1SGavin Shan dev->class == PCI_CLASS_SERIAL_USB_EHCI) 2102801846d1SGavin Shan *weight += 3; 2103801846d1SGavin Shan else if ((dev->class >> 8) == PCI_CLASS_STORAGE_RAID) 2104801846d1SGavin Shan *weight += 15; 2105801846d1SGavin Shan else 2106801846d1SGavin Shan *weight += 10; 2107801846d1SGavin Shan 2108801846d1SGavin Shan return 0; 2109801846d1SGavin Shan } 2110801846d1SGavin Shan 2111801846d1SGavin Shan static unsigned int pnv_pci_ioda_pe_dma_weight(struct pnv_ioda_pe *pe) 2112801846d1SGavin Shan { 2113801846d1SGavin Shan unsigned int weight = 0; 2114801846d1SGavin Shan 2115801846d1SGavin Shan /* SRIOV VF has same DMA32 weight as its PF */ 2116801846d1SGavin Shan #ifdef CONFIG_PCI_IOV 2117801846d1SGavin Shan if ((pe->flags & PNV_IODA_PE_VF) && pe->parent_dev) { 2118801846d1SGavin Shan pnv_pci_ioda_dev_dma_weight(pe->parent_dev, &weight); 2119801846d1SGavin Shan return weight; 2120801846d1SGavin Shan } 2121801846d1SGavin Shan #endif 2122801846d1SGavin Shan 2123801846d1SGavin Shan if ((pe->flags & PNV_IODA_PE_DEV) && pe->pdev) { 2124801846d1SGavin Shan pnv_pci_ioda_dev_dma_weight(pe->pdev, &weight); 2125801846d1SGavin Shan } else if ((pe->flags & PNV_IODA_PE_BUS) && pe->pbus) { 2126801846d1SGavin Shan struct pci_dev *pdev; 2127801846d1SGavin Shan 2128801846d1SGavin Shan list_for_each_entry(pdev, &pe->pbus->devices, bus_list) 2129801846d1SGavin Shan pnv_pci_ioda_dev_dma_weight(pdev, &weight); 2130801846d1SGavin Shan } else if ((pe->flags & PNV_IODA_PE_BUS_ALL) && pe->pbus) { 2131801846d1SGavin Shan pci_walk_bus(pe->pbus, pnv_pci_ioda_dev_dma_weight, &weight); 2132801846d1SGavin Shan } 2133801846d1SGavin Shan 2134801846d1SGavin Shan return weight; 2135801846d1SGavin Shan } 2136801846d1SGavin Shan 2137b30d936fSGavin Shan static void pnv_pci_ioda1_setup_dma_pe(struct pnv_phb *phb, 21382b923ed1SGavin Shan struct pnv_ioda_pe *pe) 2139184cd4a3SBenjamin Herrenschmidt { 2140184cd4a3SBenjamin Herrenschmidt 2141184cd4a3SBenjamin Herrenschmidt struct page *tce_mem = NULL; 2142184cd4a3SBenjamin Herrenschmidt struct iommu_table *tbl; 21432b923ed1SGavin Shan unsigned int weight, total_weight = 0; 21442b923ed1SGavin Shan unsigned int tce32_segsz, base, segs, avail, i; 2145184cd4a3SBenjamin Herrenschmidt int64_t rc; 2146184cd4a3SBenjamin Herrenschmidt void *addr; 2147184cd4a3SBenjamin Herrenschmidt 2148184cd4a3SBenjamin Herrenschmidt /* XXX FIXME: Handle 64-bit only DMA devices */ 2149184cd4a3SBenjamin Herrenschmidt /* XXX FIXME: Provide 64-bit DMA facilities & non-4K TCE tables etc.. */ 2150184cd4a3SBenjamin Herrenschmidt /* XXX FIXME: Allocate multi-level tables on PHB3 */ 21512b923ed1SGavin Shan weight = pnv_pci_ioda_pe_dma_weight(pe); 21522b923ed1SGavin Shan if (!weight) 21532b923ed1SGavin Shan return; 2154184cd4a3SBenjamin Herrenschmidt 21552b923ed1SGavin Shan pci_walk_bus(phb->hose->bus, pnv_pci_ioda_dev_dma_weight, 21562b923ed1SGavin Shan &total_weight); 21572b923ed1SGavin Shan segs = (weight * phb->ioda.dma32_count) / total_weight; 21582b923ed1SGavin Shan if (!segs) 21592b923ed1SGavin Shan segs = 1; 21602b923ed1SGavin Shan 21612b923ed1SGavin Shan /* 21622b923ed1SGavin Shan * Allocate contiguous DMA32 segments. We begin with the expected 21632b923ed1SGavin Shan * number of segments. With one more attempt, the number of DMA32 21642b923ed1SGavin Shan * segments to be allocated is decreased by one until one segment 21652b923ed1SGavin Shan * is allocated successfully. 21662b923ed1SGavin Shan */ 21672b923ed1SGavin Shan do { 21682b923ed1SGavin Shan for (base = 0; base <= phb->ioda.dma32_count - segs; base++) { 21692b923ed1SGavin Shan for (avail = 0, i = base; i < base + segs; i++) { 21702b923ed1SGavin Shan if (phb->ioda.dma32_segmap[i] == 21712b923ed1SGavin Shan IODA_INVALID_PE) 21722b923ed1SGavin Shan avail++; 21732b923ed1SGavin Shan } 21742b923ed1SGavin Shan 21752b923ed1SGavin Shan if (avail == segs) 21762b923ed1SGavin Shan goto found; 21772b923ed1SGavin Shan } 21782b923ed1SGavin Shan } while (--segs); 21792b923ed1SGavin Shan 21802b923ed1SGavin Shan if (!segs) { 21812b923ed1SGavin Shan pe_warn(pe, "No available DMA32 segments\n"); 21822b923ed1SGavin Shan return; 21832b923ed1SGavin Shan } 21842b923ed1SGavin Shan 21852b923ed1SGavin Shan found: 21860eaf4defSAlexey Kardashevskiy tbl = pnv_pci_table_alloc(phb->hose->node); 218782eae1afSAlexey Kardashevskiy if (WARN_ON(!tbl)) 218882eae1afSAlexey Kardashevskiy return; 218982eae1afSAlexey Kardashevskiy 2190b348aa65SAlexey Kardashevskiy iommu_register_group(&pe->table_group, phb->hose->global_number, 2191b348aa65SAlexey Kardashevskiy pe->pe_number); 21920eaf4defSAlexey Kardashevskiy pnv_pci_link_table_and_group(phb->hose->node, 0, tbl, &pe->table_group); 2193c5773822SAlexey Kardashevskiy 2194184cd4a3SBenjamin Herrenschmidt /* Grab a 32-bit TCE table */ 21952b923ed1SGavin Shan pe_info(pe, "DMA weight %d (%d), assigned (%d) %d DMA32 segments\n", 21962b923ed1SGavin Shan weight, total_weight, base, segs); 2197184cd4a3SBenjamin Herrenschmidt pe_info(pe, " Setting up 32-bit TCE table at %08x..%08x\n", 2198acce971cSGavin Shan base * PNV_IODA1_DMA32_SEGSIZE, 2199acce971cSGavin Shan (base + segs) * PNV_IODA1_DMA32_SEGSIZE - 1); 2200184cd4a3SBenjamin Herrenschmidt 2201184cd4a3SBenjamin Herrenschmidt /* XXX Currently, we allocate one big contiguous table for the 2202184cd4a3SBenjamin Herrenschmidt * TCEs. We only really need one chunk per 256M of TCE space 2203184cd4a3SBenjamin Herrenschmidt * (ie per segment) but that's an optimization for later, it 2204184cd4a3SBenjamin Herrenschmidt * requires some added smarts with our get/put_tce implementation 2205acce971cSGavin Shan * 2206acce971cSGavin Shan * Each TCE page is 4KB in size and each TCE entry occupies 8 2207acce971cSGavin Shan * bytes 2208184cd4a3SBenjamin Herrenschmidt */ 2209acce971cSGavin Shan tce32_segsz = PNV_IODA1_DMA32_SEGSIZE >> (IOMMU_PAGE_SHIFT_4K - 3); 2210184cd4a3SBenjamin Herrenschmidt tce_mem = alloc_pages_node(phb->hose->node, GFP_KERNEL, 2211acce971cSGavin Shan get_order(tce32_segsz * segs)); 2212184cd4a3SBenjamin Herrenschmidt if (!tce_mem) { 2213184cd4a3SBenjamin Herrenschmidt pe_err(pe, " Failed to allocate a 32-bit TCE memory\n"); 2214184cd4a3SBenjamin Herrenschmidt goto fail; 2215184cd4a3SBenjamin Herrenschmidt } 2216184cd4a3SBenjamin Herrenschmidt addr = page_address(tce_mem); 2217acce971cSGavin Shan memset(addr, 0, tce32_segsz * segs); 2218184cd4a3SBenjamin Herrenschmidt 2219184cd4a3SBenjamin Herrenschmidt /* Configure HW */ 2220184cd4a3SBenjamin Herrenschmidt for (i = 0; i < segs; i++) { 2221184cd4a3SBenjamin Herrenschmidt rc = opal_pci_map_pe_dma_window(phb->opal_id, 2222184cd4a3SBenjamin Herrenschmidt pe->pe_number, 2223184cd4a3SBenjamin Herrenschmidt base + i, 1, 2224acce971cSGavin Shan __pa(addr) + tce32_segsz * i, 2225acce971cSGavin Shan tce32_segsz, IOMMU_PAGE_SIZE_4K); 2226184cd4a3SBenjamin Herrenschmidt if (rc) { 2227184cd4a3SBenjamin Herrenschmidt pe_err(pe, " Failed to configure 32-bit TCE table," 2228184cd4a3SBenjamin Herrenschmidt " err %ld\n", rc); 2229184cd4a3SBenjamin Herrenschmidt goto fail; 2230184cd4a3SBenjamin Herrenschmidt } 2231184cd4a3SBenjamin Herrenschmidt } 2232184cd4a3SBenjamin Herrenschmidt 22332b923ed1SGavin Shan /* Setup DMA32 segment mapping */ 22342b923ed1SGavin Shan for (i = base; i < base + segs; i++) 22352b923ed1SGavin Shan phb->ioda.dma32_segmap[i] = pe->pe_number; 22362b923ed1SGavin Shan 2237184cd4a3SBenjamin Herrenschmidt /* Setup linux iommu table */ 2238acce971cSGavin Shan pnv_pci_setup_iommu_table(tbl, addr, tce32_segsz * segs, 2239acce971cSGavin Shan base * PNV_IODA1_DMA32_SEGSIZE, 2240acce971cSGavin Shan IOMMU_PAGE_SHIFT_4K); 2241184cd4a3SBenjamin Herrenschmidt 2242da004c36SAlexey Kardashevskiy tbl->it_ops = &pnv_ioda1_iommu_ops; 22434793d65dSAlexey Kardashevskiy pe->table_group.tce32_start = tbl->it_offset << tbl->it_page_shift; 22444793d65dSAlexey Kardashevskiy pe->table_group.tce32_size = tbl->it_size << tbl->it_page_shift; 2245184cd4a3SBenjamin Herrenschmidt iommu_init_table(tbl, phb->hose->node); 2246184cd4a3SBenjamin Herrenschmidt 2247781a868fSWei Yang if (pe->flags & PNV_IODA_PE_DEV) { 22484617082eSAlexey Kardashevskiy /* 22494617082eSAlexey Kardashevskiy * Setting table base here only for carrying iommu_group 22504617082eSAlexey Kardashevskiy * further down to let iommu_add_device() do the job. 22514617082eSAlexey Kardashevskiy * pnv_pci_ioda_dma_dev_setup will override it later anyway. 22524617082eSAlexey Kardashevskiy */ 22534617082eSAlexey Kardashevskiy set_iommu_table_base(&pe->pdev->dev, tbl); 22544617082eSAlexey Kardashevskiy iommu_add_device(&pe->pdev->dev); 2255c5773822SAlexey Kardashevskiy } else if (pe->flags & (PNV_IODA_PE_BUS | PNV_IODA_PE_BUS_ALL)) 2256db08e1d5SAlexey Kardashevskiy pnv_ioda_setup_bus_dma(pe, pe->pbus, true); 225774251fe2SBenjamin Herrenschmidt 2258184cd4a3SBenjamin Herrenschmidt return; 2259184cd4a3SBenjamin Herrenschmidt fail: 2260184cd4a3SBenjamin Herrenschmidt /* XXX Failure: Try to fallback to 64-bit only ? */ 2261184cd4a3SBenjamin Herrenschmidt if (tce_mem) 2262acce971cSGavin Shan __free_pages(tce_mem, get_order(tce32_segsz * segs)); 22630eaf4defSAlexey Kardashevskiy if (tbl) { 22640eaf4defSAlexey Kardashevskiy pnv_pci_unlink_table_and_group(tbl, &pe->table_group); 2265e5afdf9dSAlexey Kardashevskiy iommu_tce_table_put(tbl); 22660eaf4defSAlexey Kardashevskiy } 2267184cd4a3SBenjamin Herrenschmidt } 2268184cd4a3SBenjamin Herrenschmidt 226943cb60abSAlexey Kardashevskiy static long pnv_pci_ioda2_set_window(struct iommu_table_group *table_group, 227043cb60abSAlexey Kardashevskiy int num, struct iommu_table *tbl) 227143cb60abSAlexey Kardashevskiy { 227243cb60abSAlexey Kardashevskiy struct pnv_ioda_pe *pe = container_of(table_group, struct pnv_ioda_pe, 227343cb60abSAlexey Kardashevskiy table_group); 227443cb60abSAlexey Kardashevskiy struct pnv_phb *phb = pe->phb; 227543cb60abSAlexey Kardashevskiy int64_t rc; 2276bbb845c4SAlexey Kardashevskiy const unsigned long size = tbl->it_indirect_levels ? 2277bbb845c4SAlexey Kardashevskiy tbl->it_level_size : tbl->it_size; 227843cb60abSAlexey Kardashevskiy const __u64 start_addr = tbl->it_offset << tbl->it_page_shift; 227943cb60abSAlexey Kardashevskiy const __u64 win_size = tbl->it_size << tbl->it_page_shift; 228043cb60abSAlexey Kardashevskiy 22814793d65dSAlexey Kardashevskiy pe_info(pe, "Setting up window#%d %llx..%llx pg=%x\n", num, 228243cb60abSAlexey Kardashevskiy start_addr, start_addr + win_size - 1, 228343cb60abSAlexey Kardashevskiy IOMMU_PAGE_SIZE(tbl)); 228443cb60abSAlexey Kardashevskiy 228543cb60abSAlexey Kardashevskiy /* 228643cb60abSAlexey Kardashevskiy * Map TCE table through TVT. The TVE index is the PE number 228743cb60abSAlexey Kardashevskiy * shifted by 1 bit for 32-bits DMA space. 228843cb60abSAlexey Kardashevskiy */ 228943cb60abSAlexey Kardashevskiy rc = opal_pci_map_pe_dma_window(phb->opal_id, 229043cb60abSAlexey Kardashevskiy pe->pe_number, 22914793d65dSAlexey Kardashevskiy (pe->pe_number << 1) + num, 2292bbb845c4SAlexey Kardashevskiy tbl->it_indirect_levels + 1, 229343cb60abSAlexey Kardashevskiy __pa(tbl->it_base), 2294bbb845c4SAlexey Kardashevskiy size << 3, 229543cb60abSAlexey Kardashevskiy IOMMU_PAGE_SIZE(tbl)); 229643cb60abSAlexey Kardashevskiy if (rc) { 229743cb60abSAlexey Kardashevskiy pe_err(pe, "Failed to configure TCE table, err %ld\n", rc); 229843cb60abSAlexey Kardashevskiy return rc; 229943cb60abSAlexey Kardashevskiy } 230043cb60abSAlexey Kardashevskiy 230143cb60abSAlexey Kardashevskiy pnv_pci_link_table_and_group(phb->hose->node, num, 230243cb60abSAlexey Kardashevskiy tbl, &pe->table_group); 2303ed7d9a1dSMichael Ellerman pnv_pci_ioda2_tce_invalidate_pe(pe); 230443cb60abSAlexey Kardashevskiy 230543cb60abSAlexey Kardashevskiy return 0; 230643cb60abSAlexey Kardashevskiy } 230743cb60abSAlexey Kardashevskiy 2308f87a8864SAlexey Kardashevskiy static void pnv_pci_ioda2_set_bypass(struct pnv_ioda_pe *pe, bool enable) 2309cd15b048SBenjamin Herrenschmidt { 2310cd15b048SBenjamin Herrenschmidt uint16_t window_id = (pe->pe_number << 1 ) + 1; 2311cd15b048SBenjamin Herrenschmidt int64_t rc; 2312cd15b048SBenjamin Herrenschmidt 2313cd15b048SBenjamin Herrenschmidt pe_info(pe, "%sabling 64-bit DMA bypass\n", enable ? "En" : "Dis"); 2314cd15b048SBenjamin Herrenschmidt if (enable) { 2315cd15b048SBenjamin Herrenschmidt phys_addr_t top = memblock_end_of_DRAM(); 2316cd15b048SBenjamin Herrenschmidt 2317cd15b048SBenjamin Herrenschmidt top = roundup_pow_of_two(top); 2318cd15b048SBenjamin Herrenschmidt rc = opal_pci_map_pe_dma_window_real(pe->phb->opal_id, 2319cd15b048SBenjamin Herrenschmidt pe->pe_number, 2320cd15b048SBenjamin Herrenschmidt window_id, 2321cd15b048SBenjamin Herrenschmidt pe->tce_bypass_base, 2322cd15b048SBenjamin Herrenschmidt top); 2323cd15b048SBenjamin Herrenschmidt } else { 2324cd15b048SBenjamin Herrenschmidt rc = opal_pci_map_pe_dma_window_real(pe->phb->opal_id, 2325cd15b048SBenjamin Herrenschmidt pe->pe_number, 2326cd15b048SBenjamin Herrenschmidt window_id, 2327cd15b048SBenjamin Herrenschmidt pe->tce_bypass_base, 2328cd15b048SBenjamin Herrenschmidt 0); 2329cd15b048SBenjamin Herrenschmidt } 2330cd15b048SBenjamin Herrenschmidt if (rc) 2331cd15b048SBenjamin Herrenschmidt pe_err(pe, "OPAL error %lld configuring bypass window\n", rc); 2332cd15b048SBenjamin Herrenschmidt else 2333cd15b048SBenjamin Herrenschmidt pe->tce_bypass_enabled = enable; 2334cd15b048SBenjamin Herrenschmidt } 2335cd15b048SBenjamin Herrenschmidt 23364793d65dSAlexey Kardashevskiy static long pnv_pci_ioda2_table_alloc_pages(int nid, __u64 bus_offset, 23374793d65dSAlexey Kardashevskiy __u32 page_shift, __u64 window_size, __u32 levels, 23384793d65dSAlexey Kardashevskiy struct iommu_table *tbl); 23394793d65dSAlexey Kardashevskiy 23404793d65dSAlexey Kardashevskiy static long pnv_pci_ioda2_create_table(struct iommu_table_group *table_group, 23414793d65dSAlexey Kardashevskiy int num, __u32 page_shift, __u64 window_size, __u32 levels, 23424793d65dSAlexey Kardashevskiy struct iommu_table **ptbl) 23434793d65dSAlexey Kardashevskiy { 23444793d65dSAlexey Kardashevskiy struct pnv_ioda_pe *pe = container_of(table_group, struct pnv_ioda_pe, 23454793d65dSAlexey Kardashevskiy table_group); 23464793d65dSAlexey Kardashevskiy int nid = pe->phb->hose->node; 23474793d65dSAlexey Kardashevskiy __u64 bus_offset = num ? pe->tce_bypass_base : table_group->tce32_start; 23484793d65dSAlexey Kardashevskiy long ret; 23494793d65dSAlexey Kardashevskiy struct iommu_table *tbl; 23504793d65dSAlexey Kardashevskiy 23514793d65dSAlexey Kardashevskiy tbl = pnv_pci_table_alloc(nid); 23524793d65dSAlexey Kardashevskiy if (!tbl) 23534793d65dSAlexey Kardashevskiy return -ENOMEM; 23544793d65dSAlexey Kardashevskiy 235511edf116SAlexey Kardashevskiy tbl->it_ops = &pnv_ioda2_iommu_ops; 235611edf116SAlexey Kardashevskiy 23574793d65dSAlexey Kardashevskiy ret = pnv_pci_ioda2_table_alloc_pages(nid, 23584793d65dSAlexey Kardashevskiy bus_offset, page_shift, window_size, 23594793d65dSAlexey Kardashevskiy levels, tbl); 23604793d65dSAlexey Kardashevskiy if (ret) { 2361e5afdf9dSAlexey Kardashevskiy iommu_tce_table_put(tbl); 23624793d65dSAlexey Kardashevskiy return ret; 23634793d65dSAlexey Kardashevskiy } 23644793d65dSAlexey Kardashevskiy 23654793d65dSAlexey Kardashevskiy *ptbl = tbl; 23664793d65dSAlexey Kardashevskiy 23674793d65dSAlexey Kardashevskiy return 0; 23684793d65dSAlexey Kardashevskiy } 23694793d65dSAlexey Kardashevskiy 237046d3e1e1SAlexey Kardashevskiy static long pnv_pci_ioda2_setup_default_config(struct pnv_ioda_pe *pe) 237146d3e1e1SAlexey Kardashevskiy { 237246d3e1e1SAlexey Kardashevskiy struct iommu_table *tbl = NULL; 237346d3e1e1SAlexey Kardashevskiy long rc; 237446d3e1e1SAlexey Kardashevskiy 2375bb005455SNishanth Aravamudan /* 2376fa144869SNishanth Aravamudan * crashkernel= specifies the kdump kernel's maximum memory at 2377fa144869SNishanth Aravamudan * some offset and there is no guaranteed the result is a power 2378fa144869SNishanth Aravamudan * of 2, which will cause errors later. 2379fa144869SNishanth Aravamudan */ 2380fa144869SNishanth Aravamudan const u64 max_memory = __rounddown_pow_of_two(memory_hotplug_max()); 2381fa144869SNishanth Aravamudan 2382fa144869SNishanth Aravamudan /* 2383bb005455SNishanth Aravamudan * In memory constrained environments, e.g. kdump kernel, the 2384bb005455SNishanth Aravamudan * DMA window can be larger than available memory, which will 2385bb005455SNishanth Aravamudan * cause errors later. 2386bb005455SNishanth Aravamudan */ 2387fa144869SNishanth Aravamudan const u64 window_size = min((u64)pe->table_group.tce32_size, max_memory); 2388bb005455SNishanth Aravamudan 238946d3e1e1SAlexey Kardashevskiy rc = pnv_pci_ioda2_create_table(&pe->table_group, 0, 239046d3e1e1SAlexey Kardashevskiy IOMMU_PAGE_SHIFT_4K, 2391bb005455SNishanth Aravamudan window_size, 239246d3e1e1SAlexey Kardashevskiy POWERNV_IOMMU_DEFAULT_LEVELS, &tbl); 239346d3e1e1SAlexey Kardashevskiy if (rc) { 239446d3e1e1SAlexey Kardashevskiy pe_err(pe, "Failed to create 32-bit TCE table, err %ld", 239546d3e1e1SAlexey Kardashevskiy rc); 239646d3e1e1SAlexey Kardashevskiy return rc; 239746d3e1e1SAlexey Kardashevskiy } 239846d3e1e1SAlexey Kardashevskiy 239946d3e1e1SAlexey Kardashevskiy iommu_init_table(tbl, pe->phb->hose->node); 240046d3e1e1SAlexey Kardashevskiy 240146d3e1e1SAlexey Kardashevskiy rc = pnv_pci_ioda2_set_window(&pe->table_group, 0, tbl); 240246d3e1e1SAlexey Kardashevskiy if (rc) { 240346d3e1e1SAlexey Kardashevskiy pe_err(pe, "Failed to configure 32-bit TCE table, err %ld\n", 240446d3e1e1SAlexey Kardashevskiy rc); 2405e5afdf9dSAlexey Kardashevskiy iommu_tce_table_put(tbl); 240646d3e1e1SAlexey Kardashevskiy return rc; 240746d3e1e1SAlexey Kardashevskiy } 240846d3e1e1SAlexey Kardashevskiy 240946d3e1e1SAlexey Kardashevskiy if (!pnv_iommu_bypass_disabled) 241046d3e1e1SAlexey Kardashevskiy pnv_pci_ioda2_set_bypass(pe, true); 241146d3e1e1SAlexey Kardashevskiy 241246d3e1e1SAlexey Kardashevskiy /* 241346d3e1e1SAlexey Kardashevskiy * Setting table base here only for carrying iommu_group 241446d3e1e1SAlexey Kardashevskiy * further down to let iommu_add_device() do the job. 241546d3e1e1SAlexey Kardashevskiy * pnv_pci_ioda_dma_dev_setup will override it later anyway. 241646d3e1e1SAlexey Kardashevskiy */ 241746d3e1e1SAlexey Kardashevskiy if (pe->flags & PNV_IODA_PE_DEV) 241846d3e1e1SAlexey Kardashevskiy set_iommu_table_base(&pe->pdev->dev, tbl); 241946d3e1e1SAlexey Kardashevskiy 242046d3e1e1SAlexey Kardashevskiy return 0; 242146d3e1e1SAlexey Kardashevskiy } 242246d3e1e1SAlexey Kardashevskiy 2423b5926430SAlexey Kardashevskiy #if defined(CONFIG_IOMMU_API) || defined(CONFIG_PCI_IOV) 2424b5926430SAlexey Kardashevskiy static long pnv_pci_ioda2_unset_window(struct iommu_table_group *table_group, 2425b5926430SAlexey Kardashevskiy int num) 2426b5926430SAlexey Kardashevskiy { 2427b5926430SAlexey Kardashevskiy struct pnv_ioda_pe *pe = container_of(table_group, struct pnv_ioda_pe, 2428b5926430SAlexey Kardashevskiy table_group); 2429b5926430SAlexey Kardashevskiy struct pnv_phb *phb = pe->phb; 2430b5926430SAlexey Kardashevskiy long ret; 2431b5926430SAlexey Kardashevskiy 2432b5926430SAlexey Kardashevskiy pe_info(pe, "Removing DMA window #%d\n", num); 2433b5926430SAlexey Kardashevskiy 2434b5926430SAlexey Kardashevskiy ret = opal_pci_map_pe_dma_window(phb->opal_id, pe->pe_number, 2435b5926430SAlexey Kardashevskiy (pe->pe_number << 1) + num, 2436b5926430SAlexey Kardashevskiy 0/* levels */, 0/* table address */, 2437b5926430SAlexey Kardashevskiy 0/* table size */, 0/* page size */); 2438b5926430SAlexey Kardashevskiy if (ret) 2439b5926430SAlexey Kardashevskiy pe_warn(pe, "Unmapping failed, ret = %ld\n", ret); 2440b5926430SAlexey Kardashevskiy else 2441ed7d9a1dSMichael Ellerman pnv_pci_ioda2_tce_invalidate_pe(pe); 2442b5926430SAlexey Kardashevskiy 2443b5926430SAlexey Kardashevskiy pnv_pci_unlink_table_and_group(table_group->tables[num], table_group); 2444b5926430SAlexey Kardashevskiy 2445b5926430SAlexey Kardashevskiy return ret; 2446b5926430SAlexey Kardashevskiy } 2447b5926430SAlexey Kardashevskiy #endif 2448b5926430SAlexey Kardashevskiy 2449f87a8864SAlexey Kardashevskiy #ifdef CONFIG_IOMMU_API 245000547193SAlexey Kardashevskiy static unsigned long pnv_pci_ioda2_get_table_size(__u32 page_shift, 245100547193SAlexey Kardashevskiy __u64 window_size, __u32 levels) 245200547193SAlexey Kardashevskiy { 245300547193SAlexey Kardashevskiy unsigned long bytes = 0; 245400547193SAlexey Kardashevskiy const unsigned window_shift = ilog2(window_size); 245500547193SAlexey Kardashevskiy unsigned entries_shift = window_shift - page_shift; 245600547193SAlexey Kardashevskiy unsigned table_shift = entries_shift + 3; 245700547193SAlexey Kardashevskiy unsigned long tce_table_size = max(0x1000UL, 1UL << table_shift); 245800547193SAlexey Kardashevskiy unsigned long direct_table_size; 245900547193SAlexey Kardashevskiy 246000547193SAlexey Kardashevskiy if (!levels || (levels > POWERNV_IOMMU_MAX_LEVELS) || 246100547193SAlexey Kardashevskiy (window_size > memory_hotplug_max()) || 246200547193SAlexey Kardashevskiy !is_power_of_2(window_size)) 246300547193SAlexey Kardashevskiy return 0; 246400547193SAlexey Kardashevskiy 246500547193SAlexey Kardashevskiy /* Calculate a direct table size from window_size and levels */ 246600547193SAlexey Kardashevskiy entries_shift = (entries_shift + levels - 1) / levels; 246700547193SAlexey Kardashevskiy table_shift = entries_shift + 3; 246800547193SAlexey Kardashevskiy table_shift = max_t(unsigned, table_shift, PAGE_SHIFT); 246900547193SAlexey Kardashevskiy direct_table_size = 1UL << table_shift; 247000547193SAlexey Kardashevskiy 247100547193SAlexey Kardashevskiy for ( ; levels; --levels) { 247200547193SAlexey Kardashevskiy bytes += _ALIGN_UP(tce_table_size, direct_table_size); 247300547193SAlexey Kardashevskiy 247400547193SAlexey Kardashevskiy tce_table_size /= direct_table_size; 247500547193SAlexey Kardashevskiy tce_table_size <<= 3; 2476e49a6a21SAlexey Kardashevskiy tce_table_size = max_t(unsigned long, 2477e49a6a21SAlexey Kardashevskiy tce_table_size, direct_table_size); 247800547193SAlexey Kardashevskiy } 247900547193SAlexey Kardashevskiy 248000547193SAlexey Kardashevskiy return bytes; 248100547193SAlexey Kardashevskiy } 248200547193SAlexey Kardashevskiy 2483f87a8864SAlexey Kardashevskiy static void pnv_ioda2_take_ownership(struct iommu_table_group *table_group) 2484cd15b048SBenjamin Herrenschmidt { 2485f87a8864SAlexey Kardashevskiy struct pnv_ioda_pe *pe = container_of(table_group, struct pnv_ioda_pe, 2486f87a8864SAlexey Kardashevskiy table_group); 248746d3e1e1SAlexey Kardashevskiy /* Store @tbl as pnv_pci_ioda2_unset_window() resets it */ 248846d3e1e1SAlexey Kardashevskiy struct iommu_table *tbl = pe->table_group.tables[0]; 2489cd15b048SBenjamin Herrenschmidt 2490f87a8864SAlexey Kardashevskiy pnv_pci_ioda2_set_bypass(pe, false); 249146d3e1e1SAlexey Kardashevskiy pnv_pci_ioda2_unset_window(&pe->table_group, 0); 2492db08e1d5SAlexey Kardashevskiy if (pe->pbus) 2493db08e1d5SAlexey Kardashevskiy pnv_ioda_setup_bus_dma(pe, pe->pbus, false); 2494e5afdf9dSAlexey Kardashevskiy iommu_tce_table_put(tbl); 2495cd15b048SBenjamin Herrenschmidt } 2496cd15b048SBenjamin Herrenschmidt 2497f87a8864SAlexey Kardashevskiy static void pnv_ioda2_release_ownership(struct iommu_table_group *table_group) 2498f87a8864SAlexey Kardashevskiy { 2499f87a8864SAlexey Kardashevskiy struct pnv_ioda_pe *pe = container_of(table_group, struct pnv_ioda_pe, 2500f87a8864SAlexey Kardashevskiy table_group); 2501f87a8864SAlexey Kardashevskiy 250246d3e1e1SAlexey Kardashevskiy pnv_pci_ioda2_setup_default_config(pe); 2503db08e1d5SAlexey Kardashevskiy if (pe->pbus) 2504db08e1d5SAlexey Kardashevskiy pnv_ioda_setup_bus_dma(pe, pe->pbus, false); 2505f87a8864SAlexey Kardashevskiy } 2506f87a8864SAlexey Kardashevskiy 2507f87a8864SAlexey Kardashevskiy static struct iommu_table_group_ops pnv_pci_ioda2_ops = { 250800547193SAlexey Kardashevskiy .get_table_size = pnv_pci_ioda2_get_table_size, 25094793d65dSAlexey Kardashevskiy .create_table = pnv_pci_ioda2_create_table, 25104793d65dSAlexey Kardashevskiy .set_window = pnv_pci_ioda2_set_window, 25114793d65dSAlexey Kardashevskiy .unset_window = pnv_pci_ioda2_unset_window, 2512f87a8864SAlexey Kardashevskiy .take_ownership = pnv_ioda2_take_ownership, 2513f87a8864SAlexey Kardashevskiy .release_ownership = pnv_ioda2_release_ownership, 2514f87a8864SAlexey Kardashevskiy }; 2515b5cb9ab1SAlexey Kardashevskiy 2516b5cb9ab1SAlexey Kardashevskiy static int gpe_table_group_to_npe_cb(struct device *dev, void *opaque) 2517b5cb9ab1SAlexey Kardashevskiy { 2518b5cb9ab1SAlexey Kardashevskiy struct pci_controller *hose; 2519b5cb9ab1SAlexey Kardashevskiy struct pnv_phb *phb; 2520b5cb9ab1SAlexey Kardashevskiy struct pnv_ioda_pe **ptmppe = opaque; 2521b5cb9ab1SAlexey Kardashevskiy struct pci_dev *pdev = container_of(dev, struct pci_dev, dev); 2522b5cb9ab1SAlexey Kardashevskiy struct pci_dn *pdn = pci_get_pdn(pdev); 2523b5cb9ab1SAlexey Kardashevskiy 2524b5cb9ab1SAlexey Kardashevskiy if (!pdn || pdn->pe_number == IODA_INVALID_PE) 2525b5cb9ab1SAlexey Kardashevskiy return 0; 2526b5cb9ab1SAlexey Kardashevskiy 2527b5cb9ab1SAlexey Kardashevskiy hose = pci_bus_to_host(pdev->bus); 2528b5cb9ab1SAlexey Kardashevskiy phb = hose->private_data; 2529b5cb9ab1SAlexey Kardashevskiy if (phb->type != PNV_PHB_NPU) 2530b5cb9ab1SAlexey Kardashevskiy return 0; 2531b5cb9ab1SAlexey Kardashevskiy 2532b5cb9ab1SAlexey Kardashevskiy *ptmppe = &phb->ioda.pe_array[pdn->pe_number]; 2533b5cb9ab1SAlexey Kardashevskiy 2534b5cb9ab1SAlexey Kardashevskiy return 1; 2535b5cb9ab1SAlexey Kardashevskiy } 2536b5cb9ab1SAlexey Kardashevskiy 2537b5cb9ab1SAlexey Kardashevskiy /* 2538b5cb9ab1SAlexey Kardashevskiy * This returns PE of associated NPU. 2539b5cb9ab1SAlexey Kardashevskiy * This assumes that NPU is in the same IOMMU group with GPU and there is 2540b5cb9ab1SAlexey Kardashevskiy * no other PEs. 2541b5cb9ab1SAlexey Kardashevskiy */ 2542b5cb9ab1SAlexey Kardashevskiy static struct pnv_ioda_pe *gpe_table_group_to_npe( 2543b5cb9ab1SAlexey Kardashevskiy struct iommu_table_group *table_group) 2544b5cb9ab1SAlexey Kardashevskiy { 2545b5cb9ab1SAlexey Kardashevskiy struct pnv_ioda_pe *npe = NULL; 2546b5cb9ab1SAlexey Kardashevskiy int ret = iommu_group_for_each_dev(table_group->group, &npe, 2547b5cb9ab1SAlexey Kardashevskiy gpe_table_group_to_npe_cb); 2548b5cb9ab1SAlexey Kardashevskiy 2549b5cb9ab1SAlexey Kardashevskiy BUG_ON(!ret || !npe); 2550b5cb9ab1SAlexey Kardashevskiy 2551b5cb9ab1SAlexey Kardashevskiy return npe; 2552b5cb9ab1SAlexey Kardashevskiy } 2553b5cb9ab1SAlexey Kardashevskiy 2554b5cb9ab1SAlexey Kardashevskiy static long pnv_pci_ioda2_npu_set_window(struct iommu_table_group *table_group, 2555b5cb9ab1SAlexey Kardashevskiy int num, struct iommu_table *tbl) 2556b5cb9ab1SAlexey Kardashevskiy { 2557b5cb9ab1SAlexey Kardashevskiy long ret = pnv_pci_ioda2_set_window(table_group, num, tbl); 2558b5cb9ab1SAlexey Kardashevskiy 2559b5cb9ab1SAlexey Kardashevskiy if (ret) 2560b5cb9ab1SAlexey Kardashevskiy return ret; 2561b5cb9ab1SAlexey Kardashevskiy 2562b5cb9ab1SAlexey Kardashevskiy ret = pnv_npu_set_window(gpe_table_group_to_npe(table_group), num, tbl); 2563b5cb9ab1SAlexey Kardashevskiy if (ret) 2564b5cb9ab1SAlexey Kardashevskiy pnv_pci_ioda2_unset_window(table_group, num); 2565b5cb9ab1SAlexey Kardashevskiy 2566b5cb9ab1SAlexey Kardashevskiy return ret; 2567b5cb9ab1SAlexey Kardashevskiy } 2568b5cb9ab1SAlexey Kardashevskiy 2569b5cb9ab1SAlexey Kardashevskiy static long pnv_pci_ioda2_npu_unset_window( 2570b5cb9ab1SAlexey Kardashevskiy struct iommu_table_group *table_group, 2571b5cb9ab1SAlexey Kardashevskiy int num) 2572b5cb9ab1SAlexey Kardashevskiy { 2573b5cb9ab1SAlexey Kardashevskiy long ret = pnv_pci_ioda2_unset_window(table_group, num); 2574b5cb9ab1SAlexey Kardashevskiy 2575b5cb9ab1SAlexey Kardashevskiy if (ret) 2576b5cb9ab1SAlexey Kardashevskiy return ret; 2577b5cb9ab1SAlexey Kardashevskiy 2578b5cb9ab1SAlexey Kardashevskiy return pnv_npu_unset_window(gpe_table_group_to_npe(table_group), num); 2579b5cb9ab1SAlexey Kardashevskiy } 2580b5cb9ab1SAlexey Kardashevskiy 2581b5cb9ab1SAlexey Kardashevskiy static void pnv_ioda2_npu_take_ownership(struct iommu_table_group *table_group) 2582b5cb9ab1SAlexey Kardashevskiy { 2583b5cb9ab1SAlexey Kardashevskiy /* 2584b5cb9ab1SAlexey Kardashevskiy * Detach NPU first as pnv_ioda2_take_ownership() will destroy 2585b5cb9ab1SAlexey Kardashevskiy * the iommu_table if 32bit DMA is enabled. 2586b5cb9ab1SAlexey Kardashevskiy */ 2587b5cb9ab1SAlexey Kardashevskiy pnv_npu_take_ownership(gpe_table_group_to_npe(table_group)); 2588b5cb9ab1SAlexey Kardashevskiy pnv_ioda2_take_ownership(table_group); 2589b5cb9ab1SAlexey Kardashevskiy } 2590b5cb9ab1SAlexey Kardashevskiy 2591b5cb9ab1SAlexey Kardashevskiy static struct iommu_table_group_ops pnv_pci_ioda2_npu_ops = { 2592b5cb9ab1SAlexey Kardashevskiy .get_table_size = pnv_pci_ioda2_get_table_size, 2593b5cb9ab1SAlexey Kardashevskiy .create_table = pnv_pci_ioda2_create_table, 2594b5cb9ab1SAlexey Kardashevskiy .set_window = pnv_pci_ioda2_npu_set_window, 2595b5cb9ab1SAlexey Kardashevskiy .unset_window = pnv_pci_ioda2_npu_unset_window, 2596b5cb9ab1SAlexey Kardashevskiy .take_ownership = pnv_ioda2_npu_take_ownership, 2597b5cb9ab1SAlexey Kardashevskiy .release_ownership = pnv_ioda2_release_ownership, 2598b5cb9ab1SAlexey Kardashevskiy }; 2599b5cb9ab1SAlexey Kardashevskiy 2600b5cb9ab1SAlexey Kardashevskiy static void pnv_pci_ioda_setup_iommu_api(void) 2601b5cb9ab1SAlexey Kardashevskiy { 2602b5cb9ab1SAlexey Kardashevskiy struct pci_controller *hose, *tmp; 2603b5cb9ab1SAlexey Kardashevskiy struct pnv_phb *phb; 2604b5cb9ab1SAlexey Kardashevskiy struct pnv_ioda_pe *pe, *gpe; 2605b5cb9ab1SAlexey Kardashevskiy 2606b5cb9ab1SAlexey Kardashevskiy /* 2607b5cb9ab1SAlexey Kardashevskiy * Now we have all PHBs discovered, time to add NPU devices to 2608b5cb9ab1SAlexey Kardashevskiy * the corresponding IOMMU groups. 2609b5cb9ab1SAlexey Kardashevskiy */ 2610b5cb9ab1SAlexey Kardashevskiy list_for_each_entry_safe(hose, tmp, &hose_list, list_node) { 2611b5cb9ab1SAlexey Kardashevskiy phb = hose->private_data; 2612b5cb9ab1SAlexey Kardashevskiy 2613b5cb9ab1SAlexey Kardashevskiy if (phb->type != PNV_PHB_NPU) 2614b5cb9ab1SAlexey Kardashevskiy continue; 2615b5cb9ab1SAlexey Kardashevskiy 2616b5cb9ab1SAlexey Kardashevskiy list_for_each_entry(pe, &phb->ioda.pe_list, list) { 2617b5cb9ab1SAlexey Kardashevskiy gpe = pnv_pci_npu_setup_iommu(pe); 2618b5cb9ab1SAlexey Kardashevskiy if (gpe) 2619b5cb9ab1SAlexey Kardashevskiy gpe->table_group.ops = &pnv_pci_ioda2_npu_ops; 2620b5cb9ab1SAlexey Kardashevskiy } 2621b5cb9ab1SAlexey Kardashevskiy } 2622b5cb9ab1SAlexey Kardashevskiy } 2623b5cb9ab1SAlexey Kardashevskiy #else /* !CONFIG_IOMMU_API */ 2624b5cb9ab1SAlexey Kardashevskiy static void pnv_pci_ioda_setup_iommu_api(void) { }; 2625f87a8864SAlexey Kardashevskiy #endif 2626f87a8864SAlexey Kardashevskiy 2627bbb845c4SAlexey Kardashevskiy static __be64 *pnv_pci_ioda2_table_do_alloc_pages(int nid, unsigned shift, 2628bbb845c4SAlexey Kardashevskiy unsigned levels, unsigned long limit, 26293ba3a73eSAlexey Kardashevskiy unsigned long *current_offset, unsigned long *total_allocated) 2630aca6913fSAlexey Kardashevskiy { 2631aca6913fSAlexey Kardashevskiy struct page *tce_mem = NULL; 2632bbb845c4SAlexey Kardashevskiy __be64 *addr, *tmp; 2633aca6913fSAlexey Kardashevskiy unsigned order = max_t(unsigned, shift, PAGE_SHIFT) - PAGE_SHIFT; 2634bbb845c4SAlexey Kardashevskiy unsigned long allocated = 1UL << (order + PAGE_SHIFT); 2635bbb845c4SAlexey Kardashevskiy unsigned entries = 1UL << (shift - 3); 2636bbb845c4SAlexey Kardashevskiy long i; 2637aca6913fSAlexey Kardashevskiy 2638aca6913fSAlexey Kardashevskiy tce_mem = alloc_pages_node(nid, GFP_KERNEL, order); 2639aca6913fSAlexey Kardashevskiy if (!tce_mem) { 2640aca6913fSAlexey Kardashevskiy pr_err("Failed to allocate a TCE memory, order=%d\n", order); 2641aca6913fSAlexey Kardashevskiy return NULL; 2642aca6913fSAlexey Kardashevskiy } 2643aca6913fSAlexey Kardashevskiy addr = page_address(tce_mem); 2644bbb845c4SAlexey Kardashevskiy memset(addr, 0, allocated); 26453ba3a73eSAlexey Kardashevskiy *total_allocated += allocated; 2646bbb845c4SAlexey Kardashevskiy 2647bbb845c4SAlexey Kardashevskiy --levels; 2648bbb845c4SAlexey Kardashevskiy if (!levels) { 2649bbb845c4SAlexey Kardashevskiy *current_offset += allocated; 2650bbb845c4SAlexey Kardashevskiy return addr; 2651bbb845c4SAlexey Kardashevskiy } 2652bbb845c4SAlexey Kardashevskiy 2653bbb845c4SAlexey Kardashevskiy for (i = 0; i < entries; ++i) { 2654bbb845c4SAlexey Kardashevskiy tmp = pnv_pci_ioda2_table_do_alloc_pages(nid, shift, 26553ba3a73eSAlexey Kardashevskiy levels, limit, current_offset, total_allocated); 2656bbb845c4SAlexey Kardashevskiy if (!tmp) 2657bbb845c4SAlexey Kardashevskiy break; 2658bbb845c4SAlexey Kardashevskiy 2659bbb845c4SAlexey Kardashevskiy addr[i] = cpu_to_be64(__pa(tmp) | 2660bbb845c4SAlexey Kardashevskiy TCE_PCI_READ | TCE_PCI_WRITE); 2661bbb845c4SAlexey Kardashevskiy 2662bbb845c4SAlexey Kardashevskiy if (*current_offset >= limit) 2663bbb845c4SAlexey Kardashevskiy break; 2664bbb845c4SAlexey Kardashevskiy } 2665aca6913fSAlexey Kardashevskiy 2666aca6913fSAlexey Kardashevskiy return addr; 2667aca6913fSAlexey Kardashevskiy } 2668aca6913fSAlexey Kardashevskiy 2669bbb845c4SAlexey Kardashevskiy static void pnv_pci_ioda2_table_do_free_pages(__be64 *addr, 2670bbb845c4SAlexey Kardashevskiy unsigned long size, unsigned level); 2671bbb845c4SAlexey Kardashevskiy 2672aca6913fSAlexey Kardashevskiy static long pnv_pci_ioda2_table_alloc_pages(int nid, __u64 bus_offset, 2673bbb845c4SAlexey Kardashevskiy __u32 page_shift, __u64 window_size, __u32 levels, 2674bbb845c4SAlexey Kardashevskiy struct iommu_table *tbl) 2675aca6913fSAlexey Kardashevskiy { 2676aca6913fSAlexey Kardashevskiy void *addr; 26773ba3a73eSAlexey Kardashevskiy unsigned long offset = 0, level_shift, total_allocated = 0; 2678aca6913fSAlexey Kardashevskiy const unsigned window_shift = ilog2(window_size); 2679aca6913fSAlexey Kardashevskiy unsigned entries_shift = window_shift - page_shift; 2680aca6913fSAlexey Kardashevskiy unsigned table_shift = max_t(unsigned, entries_shift + 3, PAGE_SHIFT); 2681aca6913fSAlexey Kardashevskiy const unsigned long tce_table_size = 1UL << table_shift; 2682aca6913fSAlexey Kardashevskiy 2683bbb845c4SAlexey Kardashevskiy if (!levels || (levels > POWERNV_IOMMU_MAX_LEVELS)) 2684bbb845c4SAlexey Kardashevskiy return -EINVAL; 2685bbb845c4SAlexey Kardashevskiy 2686aca6913fSAlexey Kardashevskiy if ((window_size > memory_hotplug_max()) || !is_power_of_2(window_size)) 2687aca6913fSAlexey Kardashevskiy return -EINVAL; 2688aca6913fSAlexey Kardashevskiy 2689bbb845c4SAlexey Kardashevskiy /* Adjust direct table size from window_size and levels */ 2690bbb845c4SAlexey Kardashevskiy entries_shift = (entries_shift + levels - 1) / levels; 2691bbb845c4SAlexey Kardashevskiy level_shift = entries_shift + 3; 2692bbb845c4SAlexey Kardashevskiy level_shift = max_t(unsigned, level_shift, PAGE_SHIFT); 2693bbb845c4SAlexey Kardashevskiy 26947aafac11SAlexey Kardashevskiy if ((level_shift - 3) * levels + page_shift >= 60) 26957aafac11SAlexey Kardashevskiy return -EINVAL; 26967aafac11SAlexey Kardashevskiy 2697aca6913fSAlexey Kardashevskiy /* Allocate TCE table */ 2698bbb845c4SAlexey Kardashevskiy addr = pnv_pci_ioda2_table_do_alloc_pages(nid, level_shift, 26993ba3a73eSAlexey Kardashevskiy levels, tce_table_size, &offset, &total_allocated); 2700bbb845c4SAlexey Kardashevskiy 2701bbb845c4SAlexey Kardashevskiy /* addr==NULL means that the first level allocation failed */ 2702aca6913fSAlexey Kardashevskiy if (!addr) 2703aca6913fSAlexey Kardashevskiy return -ENOMEM; 2704aca6913fSAlexey Kardashevskiy 2705bbb845c4SAlexey Kardashevskiy /* 2706bbb845c4SAlexey Kardashevskiy * First level was allocated but some lower level failed as 2707bbb845c4SAlexey Kardashevskiy * we did not allocate as much as we wanted, 2708bbb845c4SAlexey Kardashevskiy * release partially allocated table. 2709bbb845c4SAlexey Kardashevskiy */ 2710bbb845c4SAlexey Kardashevskiy if (offset < tce_table_size) { 2711bbb845c4SAlexey Kardashevskiy pnv_pci_ioda2_table_do_free_pages(addr, 2712bbb845c4SAlexey Kardashevskiy 1ULL << (level_shift - 3), levels - 1); 2713bbb845c4SAlexey Kardashevskiy return -ENOMEM; 2714bbb845c4SAlexey Kardashevskiy } 2715bbb845c4SAlexey Kardashevskiy 2716aca6913fSAlexey Kardashevskiy /* Setup linux iommu table */ 2717aca6913fSAlexey Kardashevskiy pnv_pci_setup_iommu_table(tbl, addr, tce_table_size, bus_offset, 2718aca6913fSAlexey Kardashevskiy page_shift); 2719bbb845c4SAlexey Kardashevskiy tbl->it_level_size = 1ULL << (level_shift - 3); 2720bbb845c4SAlexey Kardashevskiy tbl->it_indirect_levels = levels - 1; 27213ba3a73eSAlexey Kardashevskiy tbl->it_allocated_size = total_allocated; 2722aca6913fSAlexey Kardashevskiy 2723aca6913fSAlexey Kardashevskiy pr_devel("Created TCE table: ws=%08llx ts=%lx @%08llx\n", 2724aca6913fSAlexey Kardashevskiy window_size, tce_table_size, bus_offset); 2725aca6913fSAlexey Kardashevskiy 2726aca6913fSAlexey Kardashevskiy return 0; 2727aca6913fSAlexey Kardashevskiy } 2728aca6913fSAlexey Kardashevskiy 2729bbb845c4SAlexey Kardashevskiy static void pnv_pci_ioda2_table_do_free_pages(__be64 *addr, 2730bbb845c4SAlexey Kardashevskiy unsigned long size, unsigned level) 2731bbb845c4SAlexey Kardashevskiy { 2732bbb845c4SAlexey Kardashevskiy const unsigned long addr_ul = (unsigned long) addr & 2733bbb845c4SAlexey Kardashevskiy ~(TCE_PCI_READ | TCE_PCI_WRITE); 2734bbb845c4SAlexey Kardashevskiy 2735bbb845c4SAlexey Kardashevskiy if (level) { 2736bbb845c4SAlexey Kardashevskiy long i; 2737bbb845c4SAlexey Kardashevskiy u64 *tmp = (u64 *) addr_ul; 2738bbb845c4SAlexey Kardashevskiy 2739bbb845c4SAlexey Kardashevskiy for (i = 0; i < size; ++i) { 2740bbb845c4SAlexey Kardashevskiy unsigned long hpa = be64_to_cpu(tmp[i]); 2741bbb845c4SAlexey Kardashevskiy 2742bbb845c4SAlexey Kardashevskiy if (!(hpa & (TCE_PCI_READ | TCE_PCI_WRITE))) 2743bbb845c4SAlexey Kardashevskiy continue; 2744bbb845c4SAlexey Kardashevskiy 2745bbb845c4SAlexey Kardashevskiy pnv_pci_ioda2_table_do_free_pages(__va(hpa), size, 2746bbb845c4SAlexey Kardashevskiy level - 1); 2747bbb845c4SAlexey Kardashevskiy } 2748bbb845c4SAlexey Kardashevskiy } 2749bbb845c4SAlexey Kardashevskiy 2750bbb845c4SAlexey Kardashevskiy free_pages(addr_ul, get_order(size << 3)); 2751bbb845c4SAlexey Kardashevskiy } 2752bbb845c4SAlexey Kardashevskiy 2753aca6913fSAlexey Kardashevskiy static void pnv_pci_ioda2_table_free_pages(struct iommu_table *tbl) 2754aca6913fSAlexey Kardashevskiy { 2755bbb845c4SAlexey Kardashevskiy const unsigned long size = tbl->it_indirect_levels ? 2756bbb845c4SAlexey Kardashevskiy tbl->it_level_size : tbl->it_size; 2757bbb845c4SAlexey Kardashevskiy 2758aca6913fSAlexey Kardashevskiy if (!tbl->it_size) 2759aca6913fSAlexey Kardashevskiy return; 2760aca6913fSAlexey Kardashevskiy 2761bbb845c4SAlexey Kardashevskiy pnv_pci_ioda2_table_do_free_pages((__be64 *)tbl->it_base, size, 2762bbb845c4SAlexey Kardashevskiy tbl->it_indirect_levels); 2763aca6913fSAlexey Kardashevskiy } 2764aca6913fSAlexey Kardashevskiy 2765373f5657SGavin Shan static void pnv_pci_ioda2_setup_dma_pe(struct pnv_phb *phb, 2766373f5657SGavin Shan struct pnv_ioda_pe *pe) 2767373f5657SGavin Shan { 2768373f5657SGavin Shan int64_t rc; 2769373f5657SGavin Shan 2770ccd1c191SGavin Shan if (!pnv_pci_ioda_pe_dma_weight(pe)) 2771ccd1c191SGavin Shan return; 2772ccd1c191SGavin Shan 2773f87a8864SAlexey Kardashevskiy /* TVE #1 is selected by PCI address bit 59 */ 2774f87a8864SAlexey Kardashevskiy pe->tce_bypass_base = 1ull << 59; 2775f87a8864SAlexey Kardashevskiy 2776b348aa65SAlexey Kardashevskiy iommu_register_group(&pe->table_group, phb->hose->global_number, 2777b348aa65SAlexey Kardashevskiy pe->pe_number); 2778c5773822SAlexey Kardashevskiy 2779373f5657SGavin Shan /* The PE will reserve all possible 32-bits space */ 2780373f5657SGavin Shan pe_info(pe, "Setting up 32-bit TCE table at 0..%08x\n", 2781aca6913fSAlexey Kardashevskiy phb->ioda.m32_pci_base); 2782373f5657SGavin Shan 2783e5aad1e6SAlexey Kardashevskiy /* Setup linux iommu table */ 27844793d65dSAlexey Kardashevskiy pe->table_group.tce32_start = 0; 27854793d65dSAlexey Kardashevskiy pe->table_group.tce32_size = phb->ioda.m32_pci_base; 27864793d65dSAlexey Kardashevskiy pe->table_group.max_dynamic_windows_supported = 27874793d65dSAlexey Kardashevskiy IOMMU_TABLE_GROUP_MAX_TABLES; 27884793d65dSAlexey Kardashevskiy pe->table_group.max_levels = POWERNV_IOMMU_MAX_LEVELS; 27894793d65dSAlexey Kardashevskiy pe->table_group.pgsizes = SZ_4K | SZ_64K | SZ_16M; 2790e5aad1e6SAlexey Kardashevskiy #ifdef CONFIG_IOMMU_API 2791e5aad1e6SAlexey Kardashevskiy pe->table_group.ops = &pnv_pci_ioda2_ops; 2792e5aad1e6SAlexey Kardashevskiy #endif 2793e5aad1e6SAlexey Kardashevskiy 279446d3e1e1SAlexey Kardashevskiy rc = pnv_pci_ioda2_setup_default_config(pe); 2795801846d1SGavin Shan if (rc) 279646d3e1e1SAlexey Kardashevskiy return; 279746d3e1e1SAlexey Kardashevskiy 279820f13b95SAlexey Kardashevskiy if (pe->flags & (PNV_IODA_PE_BUS | PNV_IODA_PE_BUS_ALL)) 2799db08e1d5SAlexey Kardashevskiy pnv_ioda_setup_bus_dma(pe, pe->pbus, true); 2800373f5657SGavin Shan } 2801373f5657SGavin Shan 2802184cd4a3SBenjamin Herrenschmidt #ifdef CONFIG_PCI_MSI 28034ee11c1aSSuresh Warrier int64_t pnv_opal_pci_msi_eoi(struct irq_chip *chip, unsigned int hw_irq) 2804137436c9SGavin Shan { 2805137436c9SGavin Shan struct pnv_phb *phb = container_of(chip, struct pnv_phb, 2806137436c9SGavin Shan ioda.irq_chip); 2807137436c9SGavin Shan 28084ee11c1aSSuresh Warrier return opal_pci_msi_eoi(phb->opal_id, hw_irq); 28094ee11c1aSSuresh Warrier } 28104ee11c1aSSuresh Warrier 28114ee11c1aSSuresh Warrier static void pnv_ioda2_msi_eoi(struct irq_data *d) 28124ee11c1aSSuresh Warrier { 28134ee11c1aSSuresh Warrier int64_t rc; 28144ee11c1aSSuresh Warrier unsigned int hw_irq = (unsigned int)irqd_to_hwirq(d); 28154ee11c1aSSuresh Warrier struct irq_chip *chip = irq_data_get_irq_chip(d); 28164ee11c1aSSuresh Warrier 28174ee11c1aSSuresh Warrier rc = pnv_opal_pci_msi_eoi(chip, hw_irq); 2818137436c9SGavin Shan WARN_ON_ONCE(rc); 2819137436c9SGavin Shan 2820137436c9SGavin Shan icp_native_eoi(d); 2821137436c9SGavin Shan } 2822137436c9SGavin Shan 2823fd9a1c26SIan Munsie 2824f456834aSIan Munsie void pnv_set_msi_irq_chip(struct pnv_phb *phb, unsigned int virq) 2825fd9a1c26SIan Munsie { 2826fd9a1c26SIan Munsie struct irq_data *idata; 2827fd9a1c26SIan Munsie struct irq_chip *ichip; 2828fd9a1c26SIan Munsie 2829fb111334SBenjamin Herrenschmidt /* The MSI EOI OPAL call is only needed on PHB3 */ 2830fb111334SBenjamin Herrenschmidt if (phb->model != PNV_PHB_MODEL_PHB3) 2831fd9a1c26SIan Munsie return; 2832fd9a1c26SIan Munsie 2833fd9a1c26SIan Munsie if (!phb->ioda.irq_chip_init) { 2834fd9a1c26SIan Munsie /* 2835fd9a1c26SIan Munsie * First time we setup an MSI IRQ, we need to setup the 2836fd9a1c26SIan Munsie * corresponding IRQ chip to route correctly. 2837fd9a1c26SIan Munsie */ 2838fd9a1c26SIan Munsie idata = irq_get_irq_data(virq); 2839fd9a1c26SIan Munsie ichip = irq_data_get_irq_chip(idata); 2840fd9a1c26SIan Munsie phb->ioda.irq_chip_init = 1; 2841fd9a1c26SIan Munsie phb->ioda.irq_chip = *ichip; 2842fd9a1c26SIan Munsie phb->ioda.irq_chip.irq_eoi = pnv_ioda2_msi_eoi; 2843fd9a1c26SIan Munsie } 2844fd9a1c26SIan Munsie irq_set_chip(virq, &phb->ioda.irq_chip); 2845fd9a1c26SIan Munsie } 2846fd9a1c26SIan Munsie 28474ee11c1aSSuresh Warrier /* 28484ee11c1aSSuresh Warrier * Returns true iff chip is something that we could call 28494ee11c1aSSuresh Warrier * pnv_opal_pci_msi_eoi for. 28504ee11c1aSSuresh Warrier */ 28514ee11c1aSSuresh Warrier bool is_pnv_opal_msi(struct irq_chip *chip) 28524ee11c1aSSuresh Warrier { 28534ee11c1aSSuresh Warrier return chip->irq_eoi == pnv_ioda2_msi_eoi; 28544ee11c1aSSuresh Warrier } 28554ee11c1aSSuresh Warrier EXPORT_SYMBOL_GPL(is_pnv_opal_msi); 28564ee11c1aSSuresh Warrier 2857184cd4a3SBenjamin Herrenschmidt static int pnv_pci_ioda_msi_setup(struct pnv_phb *phb, struct pci_dev *dev, 2858137436c9SGavin Shan unsigned int hwirq, unsigned int virq, 2859137436c9SGavin Shan unsigned int is_64, struct msi_msg *msg) 2860184cd4a3SBenjamin Herrenschmidt { 2861184cd4a3SBenjamin Herrenschmidt struct pnv_ioda_pe *pe = pnv_ioda_get_pe(dev); 2862184cd4a3SBenjamin Herrenschmidt unsigned int xive_num = hwirq - phb->msi_base; 28633a1a4661SBenjamin Herrenschmidt __be32 data; 2864184cd4a3SBenjamin Herrenschmidt int rc; 2865184cd4a3SBenjamin Herrenschmidt 2866184cd4a3SBenjamin Herrenschmidt /* No PE assigned ? bail out ... no MSI for you ! */ 2867184cd4a3SBenjamin Herrenschmidt if (pe == NULL) 2868184cd4a3SBenjamin Herrenschmidt return -ENXIO; 2869184cd4a3SBenjamin Herrenschmidt 2870184cd4a3SBenjamin Herrenschmidt /* Check if we have an MVE */ 2871184cd4a3SBenjamin Herrenschmidt if (pe->mve_number < 0) 2872184cd4a3SBenjamin Herrenschmidt return -ENXIO; 2873184cd4a3SBenjamin Herrenschmidt 2874b72c1f65SBenjamin Herrenschmidt /* Force 32-bit MSI on some broken devices */ 287536074381SBenjamin Herrenschmidt if (dev->no_64bit_msi) 2876b72c1f65SBenjamin Herrenschmidt is_64 = 0; 2877b72c1f65SBenjamin Herrenschmidt 2878184cd4a3SBenjamin Herrenschmidt /* Assign XIVE to PE */ 2879184cd4a3SBenjamin Herrenschmidt rc = opal_pci_set_xive_pe(phb->opal_id, pe->pe_number, xive_num); 2880184cd4a3SBenjamin Herrenschmidt if (rc) { 2881184cd4a3SBenjamin Herrenschmidt pr_warn("%s: OPAL error %d setting XIVE %d PE\n", 2882184cd4a3SBenjamin Herrenschmidt pci_name(dev), rc, xive_num); 2883184cd4a3SBenjamin Herrenschmidt return -EIO; 2884184cd4a3SBenjamin Herrenschmidt } 2885184cd4a3SBenjamin Herrenschmidt 2886184cd4a3SBenjamin Herrenschmidt if (is_64) { 28873a1a4661SBenjamin Herrenschmidt __be64 addr64; 28883a1a4661SBenjamin Herrenschmidt 2889184cd4a3SBenjamin Herrenschmidt rc = opal_get_msi_64(phb->opal_id, pe->mve_number, xive_num, 1, 2890184cd4a3SBenjamin Herrenschmidt &addr64, &data); 2891184cd4a3SBenjamin Herrenschmidt if (rc) { 2892184cd4a3SBenjamin Herrenschmidt pr_warn("%s: OPAL error %d getting 64-bit MSI data\n", 2893184cd4a3SBenjamin Herrenschmidt pci_name(dev), rc); 2894184cd4a3SBenjamin Herrenschmidt return -EIO; 2895184cd4a3SBenjamin Herrenschmidt } 28963a1a4661SBenjamin Herrenschmidt msg->address_hi = be64_to_cpu(addr64) >> 32; 28973a1a4661SBenjamin Herrenschmidt msg->address_lo = be64_to_cpu(addr64) & 0xfffffffful; 2898184cd4a3SBenjamin Herrenschmidt } else { 28993a1a4661SBenjamin Herrenschmidt __be32 addr32; 29003a1a4661SBenjamin Herrenschmidt 2901184cd4a3SBenjamin Herrenschmidt rc = opal_get_msi_32(phb->opal_id, pe->mve_number, xive_num, 1, 2902184cd4a3SBenjamin Herrenschmidt &addr32, &data); 2903184cd4a3SBenjamin Herrenschmidt if (rc) { 2904184cd4a3SBenjamin Herrenschmidt pr_warn("%s: OPAL error %d getting 32-bit MSI data\n", 2905184cd4a3SBenjamin Herrenschmidt pci_name(dev), rc); 2906184cd4a3SBenjamin Herrenschmidt return -EIO; 2907184cd4a3SBenjamin Herrenschmidt } 2908184cd4a3SBenjamin Herrenschmidt msg->address_hi = 0; 29093a1a4661SBenjamin Herrenschmidt msg->address_lo = be32_to_cpu(addr32); 2910184cd4a3SBenjamin Herrenschmidt } 29113a1a4661SBenjamin Herrenschmidt msg->data = be32_to_cpu(data); 2912184cd4a3SBenjamin Herrenschmidt 2913f456834aSIan Munsie pnv_set_msi_irq_chip(phb, virq); 2914137436c9SGavin Shan 2915184cd4a3SBenjamin Herrenschmidt pr_devel("%s: %s-bit MSI on hwirq %x (xive #%d)," 29161f52f176SRussell Currey " address=%x_%08x data=%x PE# %x\n", 2917184cd4a3SBenjamin Herrenschmidt pci_name(dev), is_64 ? "64" : "32", hwirq, xive_num, 2918184cd4a3SBenjamin Herrenschmidt msg->address_hi, msg->address_lo, data, pe->pe_number); 2919184cd4a3SBenjamin Herrenschmidt 2920184cd4a3SBenjamin Herrenschmidt return 0; 2921184cd4a3SBenjamin Herrenschmidt } 2922184cd4a3SBenjamin Herrenschmidt 2923184cd4a3SBenjamin Herrenschmidt static void pnv_pci_init_ioda_msis(struct pnv_phb *phb) 2924184cd4a3SBenjamin Herrenschmidt { 2925fb1b55d6SGavin Shan unsigned int count; 2926184cd4a3SBenjamin Herrenschmidt const __be32 *prop = of_get_property(phb->hose->dn, 2927184cd4a3SBenjamin Herrenschmidt "ibm,opal-msi-ranges", NULL); 2928184cd4a3SBenjamin Herrenschmidt if (!prop) { 2929184cd4a3SBenjamin Herrenschmidt /* BML Fallback */ 2930184cd4a3SBenjamin Herrenschmidt prop = of_get_property(phb->hose->dn, "msi-ranges", NULL); 2931184cd4a3SBenjamin Herrenschmidt } 2932184cd4a3SBenjamin Herrenschmidt if (!prop) 2933184cd4a3SBenjamin Herrenschmidt return; 2934184cd4a3SBenjamin Herrenschmidt 2935184cd4a3SBenjamin Herrenschmidt phb->msi_base = be32_to_cpup(prop); 2936fb1b55d6SGavin Shan count = be32_to_cpup(prop + 1); 2937fb1b55d6SGavin Shan if (msi_bitmap_alloc(&phb->msi_bmp, count, phb->hose->dn)) { 2938184cd4a3SBenjamin Herrenschmidt pr_err("PCI %d: Failed to allocate MSI bitmap !\n", 2939184cd4a3SBenjamin Herrenschmidt phb->hose->global_number); 2940184cd4a3SBenjamin Herrenschmidt return; 2941184cd4a3SBenjamin Herrenschmidt } 2942fb1b55d6SGavin Shan 2943184cd4a3SBenjamin Herrenschmidt phb->msi_setup = pnv_pci_ioda_msi_setup; 2944184cd4a3SBenjamin Herrenschmidt phb->msi32_support = 1; 2945184cd4a3SBenjamin Herrenschmidt pr_info(" Allocated bitmap for %d MSIs (base IRQ 0x%x)\n", 2946fb1b55d6SGavin Shan count, phb->msi_base); 2947184cd4a3SBenjamin Herrenschmidt } 2948184cd4a3SBenjamin Herrenschmidt #else 2949184cd4a3SBenjamin Herrenschmidt static void pnv_pci_init_ioda_msis(struct pnv_phb *phb) { } 2950184cd4a3SBenjamin Herrenschmidt #endif /* CONFIG_PCI_MSI */ 2951184cd4a3SBenjamin Herrenschmidt 29526e628c7dSWei Yang #ifdef CONFIG_PCI_IOV 29536e628c7dSWei Yang static void pnv_pci_ioda_fixup_iov_resources(struct pci_dev *pdev) 29546e628c7dSWei Yang { 2955f2dd0afeSWei Yang struct pci_controller *hose = pci_bus_to_host(pdev->bus); 2956f2dd0afeSWei Yang struct pnv_phb *phb = hose->private_data; 2957f2dd0afeSWei Yang const resource_size_t gate = phb->ioda.m64_segsize >> 2; 29586e628c7dSWei Yang struct resource *res; 29596e628c7dSWei Yang int i; 2960dfcc8d45SWei Yang resource_size_t size, total_vf_bar_sz; 29616e628c7dSWei Yang struct pci_dn *pdn; 29625b88ec22SWei Yang int mul, total_vfs; 29636e628c7dSWei Yang 29646e628c7dSWei Yang if (!pdev->is_physfn || pdev->is_added) 29656e628c7dSWei Yang return; 29666e628c7dSWei Yang 29676e628c7dSWei Yang pdn = pci_get_pdn(pdev); 29686e628c7dSWei Yang pdn->vfs_expanded = 0; 2969ee8222feSWei Yang pdn->m64_single_mode = false; 29706e628c7dSWei Yang 29715b88ec22SWei Yang total_vfs = pci_sriov_get_totalvfs(pdev); 297292b8f137SGavin Shan mul = phb->ioda.total_pe_num; 2973dfcc8d45SWei Yang total_vf_bar_sz = 0; 29745b88ec22SWei Yang 29755b88ec22SWei Yang for (i = 0; i < PCI_SRIOV_NUM_BARS; i++) { 29765b88ec22SWei Yang res = &pdev->resource[i + PCI_IOV_RESOURCES]; 29775b88ec22SWei Yang if (!res->flags || res->parent) 29785b88ec22SWei Yang continue; 2979b79331a5SRussell Currey if (!pnv_pci_is_m64_flags(res->flags)) { 2980b0331854SWei Yang dev_warn(&pdev->dev, "Don't support SR-IOV with" 2981b0331854SWei Yang " non M64 VF BAR%d: %pR. \n", 29825b88ec22SWei Yang i, res); 2983b0331854SWei Yang goto truncate_iov; 29845b88ec22SWei Yang } 29855b88ec22SWei Yang 2986dfcc8d45SWei Yang total_vf_bar_sz += pci_iov_resource_size(pdev, 2987dfcc8d45SWei Yang i + PCI_IOV_RESOURCES); 29885b88ec22SWei Yang 2989f2dd0afeSWei Yang /* 2990f2dd0afeSWei Yang * If bigger than quarter of M64 segment size, just round up 2991f2dd0afeSWei Yang * power of two. 2992f2dd0afeSWei Yang * 2993f2dd0afeSWei Yang * Generally, one M64 BAR maps one IOV BAR. To avoid conflict 2994f2dd0afeSWei Yang * with other devices, IOV BAR size is expanded to be 2995f2dd0afeSWei Yang * (total_pe * VF_BAR_size). When VF_BAR_size is half of M64 2996f2dd0afeSWei Yang * segment size , the expanded size would equal to half of the 2997f2dd0afeSWei Yang * whole M64 space size, which will exhaust the M64 Space and 2998f2dd0afeSWei Yang * limit the system flexibility. This is a design decision to 2999f2dd0afeSWei Yang * set the boundary to quarter of the M64 segment size. 3000f2dd0afeSWei Yang */ 3001dfcc8d45SWei Yang if (total_vf_bar_sz > gate) { 30025b88ec22SWei Yang mul = roundup_pow_of_two(total_vfs); 3003dfcc8d45SWei Yang dev_info(&pdev->dev, 3004dfcc8d45SWei Yang "VF BAR Total IOV size %llx > %llx, roundup to %d VFs\n", 3005dfcc8d45SWei Yang total_vf_bar_sz, gate, mul); 3006ee8222feSWei Yang pdn->m64_single_mode = true; 30075b88ec22SWei Yang break; 30085b88ec22SWei Yang } 30095b88ec22SWei Yang } 30105b88ec22SWei Yang 30116e628c7dSWei Yang for (i = 0; i < PCI_SRIOV_NUM_BARS; i++) { 30126e628c7dSWei Yang res = &pdev->resource[i + PCI_IOV_RESOURCES]; 30136e628c7dSWei Yang if (!res->flags || res->parent) 30146e628c7dSWei Yang continue; 30156e628c7dSWei Yang 30166e628c7dSWei Yang size = pci_iov_resource_size(pdev, i + PCI_IOV_RESOURCES); 3017ee8222feSWei Yang /* 3018ee8222feSWei Yang * On PHB3, the minimum size alignment of M64 BAR in single 3019ee8222feSWei Yang * mode is 32MB. 3020ee8222feSWei Yang */ 3021ee8222feSWei Yang if (pdn->m64_single_mode && (size < SZ_32M)) 3022ee8222feSWei Yang goto truncate_iov; 3023ee8222feSWei Yang dev_dbg(&pdev->dev, " Fixing VF BAR%d: %pR to\n", i, res); 30245b88ec22SWei Yang res->end = res->start + size * mul - 1; 30256e628c7dSWei Yang dev_dbg(&pdev->dev, " %pR\n", res); 30266e628c7dSWei Yang dev_info(&pdev->dev, "VF BAR%d: %pR (expanded to %d VFs for PE alignment)", 30275b88ec22SWei Yang i, res, mul); 30286e628c7dSWei Yang } 30295b88ec22SWei Yang pdn->vfs_expanded = mul; 3030b0331854SWei Yang 3031b0331854SWei Yang return; 3032b0331854SWei Yang 3033b0331854SWei Yang truncate_iov: 3034b0331854SWei Yang /* To save MMIO space, IOV BAR is truncated. */ 3035b0331854SWei Yang for (i = 0; i < PCI_SRIOV_NUM_BARS; i++) { 3036b0331854SWei Yang res = &pdev->resource[i + PCI_IOV_RESOURCES]; 3037b0331854SWei Yang res->flags = 0; 3038b0331854SWei Yang res->end = res->start - 1; 3039b0331854SWei Yang } 30406e628c7dSWei Yang } 30416e628c7dSWei Yang #endif /* CONFIG_PCI_IOV */ 30426e628c7dSWei Yang 304323e79425SGavin Shan static void pnv_ioda_setup_pe_res(struct pnv_ioda_pe *pe, 304423e79425SGavin Shan struct resource *res) 304511685becSGavin Shan { 304623e79425SGavin Shan struct pnv_phb *phb = pe->phb; 304711685becSGavin Shan struct pci_bus_region region; 304823e79425SGavin Shan int index; 304923e79425SGavin Shan int64_t rc; 305011685becSGavin Shan 305123e79425SGavin Shan if (!res || !res->flags || res->start > res->end) 305223e79425SGavin Shan return; 305311685becSGavin Shan 305411685becSGavin Shan if (res->flags & IORESOURCE_IO) { 305511685becSGavin Shan region.start = res->start - phb->ioda.io_pci_base; 305611685becSGavin Shan region.end = res->end - phb->ioda.io_pci_base; 305711685becSGavin Shan index = region.start / phb->ioda.io_segsize; 305811685becSGavin Shan 305992b8f137SGavin Shan while (index < phb->ioda.total_pe_num && 306011685becSGavin Shan region.start <= region.end) { 306111685becSGavin Shan phb->ioda.io_segmap[index] = pe->pe_number; 306211685becSGavin Shan rc = opal_pci_map_pe_mmio_window(phb->opal_id, 306311685becSGavin Shan pe->pe_number, OPAL_IO_WINDOW_TYPE, 0, index); 306411685becSGavin Shan if (rc != OPAL_SUCCESS) { 30651f52f176SRussell Currey pr_err("%s: Error %lld mapping IO segment#%d to PE#%x\n", 306611685becSGavin Shan __func__, rc, index, pe->pe_number); 306711685becSGavin Shan break; 306811685becSGavin Shan } 306911685becSGavin Shan 307011685becSGavin Shan region.start += phb->ioda.io_segsize; 307111685becSGavin Shan index++; 307211685becSGavin Shan } 3073027fa02fSGavin Shan } else if ((res->flags & IORESOURCE_MEM) && 30745958d19aSBenjamin Herrenschmidt !pnv_pci_is_m64(phb, res)) { 307511685becSGavin Shan region.start = res->start - 307623e79425SGavin Shan phb->hose->mem_offset[0] - 307711685becSGavin Shan phb->ioda.m32_pci_base; 307811685becSGavin Shan region.end = res->end - 307923e79425SGavin Shan phb->hose->mem_offset[0] - 308011685becSGavin Shan phb->ioda.m32_pci_base; 308111685becSGavin Shan index = region.start / phb->ioda.m32_segsize; 308211685becSGavin Shan 308392b8f137SGavin Shan while (index < phb->ioda.total_pe_num && 308411685becSGavin Shan region.start <= region.end) { 308511685becSGavin Shan phb->ioda.m32_segmap[index] = pe->pe_number; 308611685becSGavin Shan rc = opal_pci_map_pe_mmio_window(phb->opal_id, 308711685becSGavin Shan pe->pe_number, OPAL_M32_WINDOW_TYPE, 0, index); 308811685becSGavin Shan if (rc != OPAL_SUCCESS) { 30891f52f176SRussell Currey pr_err("%s: Error %lld mapping M32 segment#%d to PE#%x", 309011685becSGavin Shan __func__, rc, index, pe->pe_number); 309111685becSGavin Shan break; 309211685becSGavin Shan } 309311685becSGavin Shan 309411685becSGavin Shan region.start += phb->ioda.m32_segsize; 309511685becSGavin Shan index++; 309611685becSGavin Shan } 309711685becSGavin Shan } 309811685becSGavin Shan } 309923e79425SGavin Shan 310023e79425SGavin Shan /* 310123e79425SGavin Shan * This function is supposed to be called on basis of PE from top 310223e79425SGavin Shan * to bottom style. So the the I/O or MMIO segment assigned to 310303671057SMasahiro Yamada * parent PE could be overridden by its child PEs if necessary. 310423e79425SGavin Shan */ 310523e79425SGavin Shan static void pnv_ioda_setup_pe_seg(struct pnv_ioda_pe *pe) 310623e79425SGavin Shan { 310769d733e7SGavin Shan struct pci_dev *pdev; 310823e79425SGavin Shan int i; 310923e79425SGavin Shan 311023e79425SGavin Shan /* 311123e79425SGavin Shan * NOTE: We only care PCI bus based PE for now. For PCI 311223e79425SGavin Shan * device based PE, for example SRIOV sensitive VF should 311323e79425SGavin Shan * be figured out later. 311423e79425SGavin Shan */ 311523e79425SGavin Shan BUG_ON(!(pe->flags & (PNV_IODA_PE_BUS | PNV_IODA_PE_BUS_ALL))); 311623e79425SGavin Shan 311769d733e7SGavin Shan list_for_each_entry(pdev, &pe->pbus->devices, bus_list) { 311869d733e7SGavin Shan for (i = 0; i <= PCI_ROM_RESOURCE; i++) 311969d733e7SGavin Shan pnv_ioda_setup_pe_res(pe, &pdev->resource[i]); 312069d733e7SGavin Shan 312169d733e7SGavin Shan /* 312269d733e7SGavin Shan * If the PE contains all subordinate PCI buses, the 312369d733e7SGavin Shan * windows of the child bridges should be mapped to 312469d733e7SGavin Shan * the PE as well. 312569d733e7SGavin Shan */ 312669d733e7SGavin Shan if (!(pe->flags & PNV_IODA_PE_BUS_ALL) || !pci_is_bridge(pdev)) 312769d733e7SGavin Shan continue; 312869d733e7SGavin Shan for (i = 0; i < PCI_BRIDGE_RESOURCE_NUM; i++) 312969d733e7SGavin Shan pnv_ioda_setup_pe_res(pe, 313069d733e7SGavin Shan &pdev->resource[PCI_BRIDGE_RESOURCES + i]); 313169d733e7SGavin Shan } 313211685becSGavin Shan } 313311685becSGavin Shan 313498b665daSRussell Currey #ifdef CONFIG_DEBUG_FS 313598b665daSRussell Currey static int pnv_pci_diag_data_set(void *data, u64 val) 313698b665daSRussell Currey { 313798b665daSRussell Currey struct pci_controller *hose; 313898b665daSRussell Currey struct pnv_phb *phb; 313998b665daSRussell Currey s64 ret; 314098b665daSRussell Currey 314198b665daSRussell Currey if (val != 1ULL) 314298b665daSRussell Currey return -EINVAL; 314398b665daSRussell Currey 314498b665daSRussell Currey hose = (struct pci_controller *)data; 314598b665daSRussell Currey if (!hose || !hose->private_data) 314698b665daSRussell Currey return -ENODEV; 314798b665daSRussell Currey 314898b665daSRussell Currey phb = hose->private_data; 314998b665daSRussell Currey 315098b665daSRussell Currey /* Retrieve the diag data from firmware */ 31515cb1f8fdSRussell Currey ret = opal_pci_get_phb_diag_data2(phb->opal_id, phb->diag_data, 31525cb1f8fdSRussell Currey phb->diag_data_size); 315398b665daSRussell Currey if (ret != OPAL_SUCCESS) 315498b665daSRussell Currey return -EIO; 315598b665daSRussell Currey 315698b665daSRussell Currey /* Print the diag data to the kernel log */ 31575cb1f8fdSRussell Currey pnv_pci_dump_phb_diag_data(phb->hose, phb->diag_data); 315898b665daSRussell Currey return 0; 315998b665daSRussell Currey } 316098b665daSRussell Currey 316198b665daSRussell Currey DEFINE_SIMPLE_ATTRIBUTE(pnv_pci_diag_data_fops, NULL, 316298b665daSRussell Currey pnv_pci_diag_data_set, "%llu\n"); 316398b665daSRussell Currey 316498b665daSRussell Currey #endif /* CONFIG_DEBUG_FS */ 316598b665daSRussell Currey 316637c367f2SGavin Shan static void pnv_pci_ioda_create_dbgfs(void) 316737c367f2SGavin Shan { 316837c367f2SGavin Shan #ifdef CONFIG_DEBUG_FS 316937c367f2SGavin Shan struct pci_controller *hose, *tmp; 317037c367f2SGavin Shan struct pnv_phb *phb; 317137c367f2SGavin Shan char name[16]; 317237c367f2SGavin Shan 317337c367f2SGavin Shan list_for_each_entry_safe(hose, tmp, &hose_list, list_node) { 317437c367f2SGavin Shan phb = hose->private_data; 317537c367f2SGavin Shan 3176ccd1c191SGavin Shan /* Notify initialization of PHB done */ 3177ccd1c191SGavin Shan phb->initialized = 1; 3178ccd1c191SGavin Shan 317937c367f2SGavin Shan sprintf(name, "PCI%04x", hose->global_number); 318037c367f2SGavin Shan phb->dbgfs = debugfs_create_dir(name, powerpc_debugfs_root); 318198b665daSRussell Currey if (!phb->dbgfs) { 318237c367f2SGavin Shan pr_warning("%s: Error on creating debugfs on PHB#%x\n", 318337c367f2SGavin Shan __func__, hose->global_number); 318498b665daSRussell Currey continue; 318598b665daSRussell Currey } 318698b665daSRussell Currey 318798b665daSRussell Currey debugfs_create_file("dump_diag_regs", 0200, phb->dbgfs, hose, 318898b665daSRussell Currey &pnv_pci_diag_data_fops); 318937c367f2SGavin Shan } 319037c367f2SGavin Shan #endif /* CONFIG_DEBUG_FS */ 319137c367f2SGavin Shan } 319237c367f2SGavin Shan 3193cad5cef6SGreg Kroah-Hartman static void pnv_pci_ioda_fixup(void) 3194fb446ad0SGavin Shan { 3195fb446ad0SGavin Shan pnv_pci_ioda_setup_PEs(); 3196ccd1c191SGavin Shan pnv_pci_ioda_setup_iommu_api(); 319737c367f2SGavin Shan pnv_pci_ioda_create_dbgfs(); 319837c367f2SGavin Shan 3199e9cc17d4SGavin Shan #ifdef CONFIG_EEH 3200e9cc17d4SGavin Shan eeh_init(); 3201dadcd6d6SMike Qiu eeh_addr_cache_build(); 3202e9cc17d4SGavin Shan #endif 3203fb446ad0SGavin Shan } 3204fb446ad0SGavin Shan 3205271fd03aSGavin Shan /* 3206271fd03aSGavin Shan * Returns the alignment for I/O or memory windows for P2P 3207271fd03aSGavin Shan * bridges. That actually depends on how PEs are segmented. 3208271fd03aSGavin Shan * For now, we return I/O or M32 segment size for PE sensitive 3209271fd03aSGavin Shan * P2P bridges. Otherwise, the default values (4KiB for I/O, 3210271fd03aSGavin Shan * 1MiB for memory) will be returned. 3211271fd03aSGavin Shan * 3212271fd03aSGavin Shan * The current PCI bus might be put into one PE, which was 3213271fd03aSGavin Shan * create against the parent PCI bridge. For that case, we 3214271fd03aSGavin Shan * needn't enlarge the alignment so that we can save some 3215271fd03aSGavin Shan * resources. 3216271fd03aSGavin Shan */ 3217271fd03aSGavin Shan static resource_size_t pnv_pci_window_alignment(struct pci_bus *bus, 3218271fd03aSGavin Shan unsigned long type) 3219271fd03aSGavin Shan { 3220271fd03aSGavin Shan struct pci_dev *bridge; 3221271fd03aSGavin Shan struct pci_controller *hose = pci_bus_to_host(bus); 3222271fd03aSGavin Shan struct pnv_phb *phb = hose->private_data; 3223271fd03aSGavin Shan int num_pci_bridges = 0; 3224271fd03aSGavin Shan 3225271fd03aSGavin Shan bridge = bus->self; 3226271fd03aSGavin Shan while (bridge) { 3227271fd03aSGavin Shan if (pci_pcie_type(bridge) == PCI_EXP_TYPE_PCI_BRIDGE) { 3228271fd03aSGavin Shan num_pci_bridges++; 3229271fd03aSGavin Shan if (num_pci_bridges >= 2) 3230271fd03aSGavin Shan return 1; 3231271fd03aSGavin Shan } 3232271fd03aSGavin Shan 3233271fd03aSGavin Shan bridge = bridge->bus->self; 3234271fd03aSGavin Shan } 3235271fd03aSGavin Shan 32365958d19aSBenjamin Herrenschmidt /* 32375958d19aSBenjamin Herrenschmidt * We fall back to M32 if M64 isn't supported. We enforce the M64 32385958d19aSBenjamin Herrenschmidt * alignment for any 64-bit resource, PCIe doesn't care and 32395958d19aSBenjamin Herrenschmidt * bridges only do 64-bit prefetchable anyway. 32405958d19aSBenjamin Herrenschmidt */ 3241b79331a5SRussell Currey if (phb->ioda.m64_segsize && pnv_pci_is_m64_flags(type)) 3242262af557SGuo Chao return phb->ioda.m64_segsize; 3243271fd03aSGavin Shan if (type & IORESOURCE_MEM) 3244271fd03aSGavin Shan return phb->ioda.m32_segsize; 3245271fd03aSGavin Shan 3246271fd03aSGavin Shan return phb->ioda.io_segsize; 3247271fd03aSGavin Shan } 3248271fd03aSGavin Shan 324940e2a47eSGavin Shan /* 325040e2a47eSGavin Shan * We are updating root port or the upstream port of the 325140e2a47eSGavin Shan * bridge behind the root port with PHB's windows in order 325240e2a47eSGavin Shan * to accommodate the changes on required resources during 325340e2a47eSGavin Shan * PCI (slot) hotplug, which is connected to either root 325440e2a47eSGavin Shan * port or the downstream ports of PCIe switch behind the 325540e2a47eSGavin Shan * root port. 325640e2a47eSGavin Shan */ 325740e2a47eSGavin Shan static void pnv_pci_fixup_bridge_resources(struct pci_bus *bus, 325840e2a47eSGavin Shan unsigned long type) 325940e2a47eSGavin Shan { 326040e2a47eSGavin Shan struct pci_controller *hose = pci_bus_to_host(bus); 326140e2a47eSGavin Shan struct pnv_phb *phb = hose->private_data; 326240e2a47eSGavin Shan struct pci_dev *bridge = bus->self; 326340e2a47eSGavin Shan struct resource *r, *w; 326440e2a47eSGavin Shan bool msi_region = false; 326540e2a47eSGavin Shan int i; 326640e2a47eSGavin Shan 326740e2a47eSGavin Shan /* Check if we need apply fixup to the bridge's windows */ 326840e2a47eSGavin Shan if (!pci_is_root_bus(bridge->bus) && 326940e2a47eSGavin Shan !pci_is_root_bus(bridge->bus->self->bus)) 327040e2a47eSGavin Shan return; 327140e2a47eSGavin Shan 327240e2a47eSGavin Shan /* Fixup the resources */ 327340e2a47eSGavin Shan for (i = 0; i < PCI_BRIDGE_RESOURCE_NUM; i++) { 327440e2a47eSGavin Shan r = &bridge->resource[PCI_BRIDGE_RESOURCES + i]; 327540e2a47eSGavin Shan if (!r->flags || !r->parent) 327640e2a47eSGavin Shan continue; 327740e2a47eSGavin Shan 327840e2a47eSGavin Shan w = NULL; 327940e2a47eSGavin Shan if (r->flags & type & IORESOURCE_IO) 328040e2a47eSGavin Shan w = &hose->io_resource; 32815958d19aSBenjamin Herrenschmidt else if (pnv_pci_is_m64(phb, r) && 328240e2a47eSGavin Shan (type & IORESOURCE_PREFETCH) && 328340e2a47eSGavin Shan phb->ioda.m64_segsize) 328440e2a47eSGavin Shan w = &hose->mem_resources[1]; 328540e2a47eSGavin Shan else if (r->flags & type & IORESOURCE_MEM) { 328640e2a47eSGavin Shan w = &hose->mem_resources[0]; 328740e2a47eSGavin Shan msi_region = true; 328840e2a47eSGavin Shan } 328940e2a47eSGavin Shan 329040e2a47eSGavin Shan r->start = w->start; 329140e2a47eSGavin Shan r->end = w->end; 329240e2a47eSGavin Shan 329340e2a47eSGavin Shan /* The 64KB 32-bits MSI region shouldn't be included in 329440e2a47eSGavin Shan * the 32-bits bridge window. Otherwise, we can see strange 329540e2a47eSGavin Shan * issues. One of them is EEH error observed on Garrison. 329640e2a47eSGavin Shan * 329740e2a47eSGavin Shan * Exclude top 1MB region which is the minimal alignment of 329840e2a47eSGavin Shan * 32-bits bridge window. 329940e2a47eSGavin Shan */ 330040e2a47eSGavin Shan if (msi_region) { 330140e2a47eSGavin Shan r->end += 0x10000; 330240e2a47eSGavin Shan r->end -= 0x100000; 330340e2a47eSGavin Shan } 330440e2a47eSGavin Shan } 330540e2a47eSGavin Shan } 330640e2a47eSGavin Shan 3307ccd1c191SGavin Shan static void pnv_pci_setup_bridge(struct pci_bus *bus, unsigned long type) 3308ccd1c191SGavin Shan { 3309ccd1c191SGavin Shan struct pci_controller *hose = pci_bus_to_host(bus); 3310ccd1c191SGavin Shan struct pnv_phb *phb = hose->private_data; 3311ccd1c191SGavin Shan struct pci_dev *bridge = bus->self; 3312ccd1c191SGavin Shan struct pnv_ioda_pe *pe; 3313ccd1c191SGavin Shan bool all = (pci_pcie_type(bridge) == PCI_EXP_TYPE_PCI_BRIDGE); 3314ccd1c191SGavin Shan 331540e2a47eSGavin Shan /* Extend bridge's windows if necessary */ 331640e2a47eSGavin Shan pnv_pci_fixup_bridge_resources(bus, type); 331740e2a47eSGavin Shan 331863803c39SGavin Shan /* The PE for root bus should be realized before any one else */ 331963803c39SGavin Shan if (!phb->ioda.root_pe_populated) { 332063803c39SGavin Shan pe = pnv_ioda_setup_bus_PE(phb->hose->bus, false); 332163803c39SGavin Shan if (pe) { 332263803c39SGavin Shan phb->ioda.root_pe_idx = pe->pe_number; 332363803c39SGavin Shan phb->ioda.root_pe_populated = true; 332463803c39SGavin Shan } 332563803c39SGavin Shan } 332663803c39SGavin Shan 3327ccd1c191SGavin Shan /* Don't assign PE to PCI bus, which doesn't have subordinate devices */ 3328ccd1c191SGavin Shan if (list_empty(&bus->devices)) 3329ccd1c191SGavin Shan return; 3330ccd1c191SGavin Shan 3331ccd1c191SGavin Shan /* Reserve PEs according to used M64 resources */ 3332ccd1c191SGavin Shan if (phb->reserve_m64_pe) 3333ccd1c191SGavin Shan phb->reserve_m64_pe(bus, NULL, all); 3334ccd1c191SGavin Shan 3335ccd1c191SGavin Shan /* 3336ccd1c191SGavin Shan * Assign PE. We might run here because of partial hotplug. 3337ccd1c191SGavin Shan * For the case, we just pick up the existing PE and should 3338ccd1c191SGavin Shan * not allocate resources again. 3339ccd1c191SGavin Shan */ 3340ccd1c191SGavin Shan pe = pnv_ioda_setup_bus_PE(bus, all); 3341ccd1c191SGavin Shan if (!pe) 3342ccd1c191SGavin Shan return; 3343ccd1c191SGavin Shan 3344ccd1c191SGavin Shan pnv_ioda_setup_pe_seg(pe); 3345ccd1c191SGavin Shan switch (phb->type) { 3346ccd1c191SGavin Shan case PNV_PHB_IODA1: 3347ccd1c191SGavin Shan pnv_pci_ioda1_setup_dma_pe(phb, pe); 3348ccd1c191SGavin Shan break; 3349ccd1c191SGavin Shan case PNV_PHB_IODA2: 3350ccd1c191SGavin Shan pnv_pci_ioda2_setup_dma_pe(phb, pe); 3351ccd1c191SGavin Shan break; 3352ccd1c191SGavin Shan default: 33531f52f176SRussell Currey pr_warn("%s: No DMA for PHB#%x (type %d)\n", 3354ccd1c191SGavin Shan __func__, phb->hose->global_number, phb->type); 3355ccd1c191SGavin Shan } 3356ccd1c191SGavin Shan } 3357ccd1c191SGavin Shan 335838274637SYongji Xie static resource_size_t pnv_pci_default_alignment(void) 335938274637SYongji Xie { 336038274637SYongji Xie return PAGE_SIZE; 336138274637SYongji Xie } 336238274637SYongji Xie 33635350ab3fSWei Yang #ifdef CONFIG_PCI_IOV 33645350ab3fSWei Yang static resource_size_t pnv_pci_iov_resource_alignment(struct pci_dev *pdev, 33655350ab3fSWei Yang int resno) 33665350ab3fSWei Yang { 3367ee8222feSWei Yang struct pci_controller *hose = pci_bus_to_host(pdev->bus); 3368ee8222feSWei Yang struct pnv_phb *phb = hose->private_data; 33695350ab3fSWei Yang struct pci_dn *pdn = pci_get_pdn(pdev); 33707fbe7a93SWei Yang resource_size_t align; 33715350ab3fSWei Yang 33727fbe7a93SWei Yang /* 33737fbe7a93SWei Yang * On PowerNV platform, IOV BAR is mapped by M64 BAR to enable the 33747fbe7a93SWei Yang * SR-IOV. While from hardware perspective, the range mapped by M64 33757fbe7a93SWei Yang * BAR should be size aligned. 33767fbe7a93SWei Yang * 3377ee8222feSWei Yang * When IOV BAR is mapped with M64 BAR in Single PE mode, the extra 3378ee8222feSWei Yang * powernv-specific hardware restriction is gone. But if just use the 3379ee8222feSWei Yang * VF BAR size as the alignment, PF BAR / VF BAR may be allocated with 3380ee8222feSWei Yang * in one segment of M64 #15, which introduces the PE conflict between 3381ee8222feSWei Yang * PF and VF. Based on this, the minimum alignment of an IOV BAR is 3382ee8222feSWei Yang * m64_segsize. 3383ee8222feSWei Yang * 33847fbe7a93SWei Yang * This function returns the total IOV BAR size if M64 BAR is in 33857fbe7a93SWei Yang * Shared PE mode or just VF BAR size if not. 3386ee8222feSWei Yang * If the M64 BAR is in Single PE mode, return the VF BAR size or 3387ee8222feSWei Yang * M64 segment size if IOV BAR size is less. 33887fbe7a93SWei Yang */ 33895350ab3fSWei Yang align = pci_iov_resource_size(pdev, resno); 33907fbe7a93SWei Yang if (!pdn->vfs_expanded) 33915350ab3fSWei Yang return align; 3392ee8222feSWei Yang if (pdn->m64_single_mode) 3393ee8222feSWei Yang return max(align, (resource_size_t)phb->ioda.m64_segsize); 33947fbe7a93SWei Yang 33957fbe7a93SWei Yang return pdn->vfs_expanded * align; 33965350ab3fSWei Yang } 33975350ab3fSWei Yang #endif /* CONFIG_PCI_IOV */ 33985350ab3fSWei Yang 3399184cd4a3SBenjamin Herrenschmidt /* Prevent enabling devices for which we couldn't properly 3400184cd4a3SBenjamin Herrenschmidt * assign a PE 3401184cd4a3SBenjamin Herrenschmidt */ 34024361b034SIan Munsie bool pnv_pci_enable_device_hook(struct pci_dev *dev) 3403184cd4a3SBenjamin Herrenschmidt { 3404db1266c8SGavin Shan struct pci_controller *hose = pci_bus_to_host(dev->bus); 3405db1266c8SGavin Shan struct pnv_phb *phb = hose->private_data; 3406db1266c8SGavin Shan struct pci_dn *pdn; 3407184cd4a3SBenjamin Herrenschmidt 3408db1266c8SGavin Shan /* The function is probably called while the PEs have 3409db1266c8SGavin Shan * not be created yet. For example, resource reassignment 3410db1266c8SGavin Shan * during PCI probe period. We just skip the check if 3411db1266c8SGavin Shan * PEs isn't ready. 3412db1266c8SGavin Shan */ 3413db1266c8SGavin Shan if (!phb->initialized) 3414c88c2a18SDaniel Axtens return true; 3415db1266c8SGavin Shan 3416b72c1f65SBenjamin Herrenschmidt pdn = pci_get_pdn(dev); 3417184cd4a3SBenjamin Herrenschmidt if (!pdn || pdn->pe_number == IODA_INVALID_PE) 3418c88c2a18SDaniel Axtens return false; 3419db1266c8SGavin Shan 3420c88c2a18SDaniel Axtens return true; 3421184cd4a3SBenjamin Herrenschmidt } 3422184cd4a3SBenjamin Herrenschmidt 3423c5f7700bSGavin Shan static long pnv_pci_ioda1_unset_window(struct iommu_table_group *table_group, 3424c5f7700bSGavin Shan int num) 3425c5f7700bSGavin Shan { 3426c5f7700bSGavin Shan struct pnv_ioda_pe *pe = container_of(table_group, 3427c5f7700bSGavin Shan struct pnv_ioda_pe, table_group); 3428c5f7700bSGavin Shan struct pnv_phb *phb = pe->phb; 3429c5f7700bSGavin Shan unsigned int idx; 3430c5f7700bSGavin Shan long rc; 3431c5f7700bSGavin Shan 3432c5f7700bSGavin Shan pe_info(pe, "Removing DMA window #%d\n", num); 3433c5f7700bSGavin Shan for (idx = 0; idx < phb->ioda.dma32_count; idx++) { 3434c5f7700bSGavin Shan if (phb->ioda.dma32_segmap[idx] != pe->pe_number) 3435c5f7700bSGavin Shan continue; 3436c5f7700bSGavin Shan 3437c5f7700bSGavin Shan rc = opal_pci_map_pe_dma_window(phb->opal_id, pe->pe_number, 3438c5f7700bSGavin Shan idx, 0, 0ul, 0ul, 0ul); 3439c5f7700bSGavin Shan if (rc != OPAL_SUCCESS) { 3440c5f7700bSGavin Shan pe_warn(pe, "Failure %ld unmapping DMA32 segment#%d\n", 3441c5f7700bSGavin Shan rc, idx); 3442c5f7700bSGavin Shan return rc; 3443c5f7700bSGavin Shan } 3444c5f7700bSGavin Shan 3445c5f7700bSGavin Shan phb->ioda.dma32_segmap[idx] = IODA_INVALID_PE; 3446c5f7700bSGavin Shan } 3447c5f7700bSGavin Shan 3448c5f7700bSGavin Shan pnv_pci_unlink_table_and_group(table_group->tables[num], table_group); 3449c5f7700bSGavin Shan return OPAL_SUCCESS; 3450c5f7700bSGavin Shan } 3451c5f7700bSGavin Shan 3452c5f7700bSGavin Shan static void pnv_pci_ioda1_release_pe_dma(struct pnv_ioda_pe *pe) 3453c5f7700bSGavin Shan { 3454c5f7700bSGavin Shan unsigned int weight = pnv_pci_ioda_pe_dma_weight(pe); 3455c5f7700bSGavin Shan struct iommu_table *tbl = pe->table_group.tables[0]; 3456c5f7700bSGavin Shan int64_t rc; 3457c5f7700bSGavin Shan 3458c5f7700bSGavin Shan if (!weight) 3459c5f7700bSGavin Shan return; 3460c5f7700bSGavin Shan 3461c5f7700bSGavin Shan rc = pnv_pci_ioda1_unset_window(&pe->table_group, 0); 3462c5f7700bSGavin Shan if (rc != OPAL_SUCCESS) 3463c5f7700bSGavin Shan return; 3464c5f7700bSGavin Shan 3465a34ab7c3SBenjamin Herrenschmidt pnv_pci_p7ioc_tce_invalidate(tbl, tbl->it_offset, tbl->it_size, false); 3466c5f7700bSGavin Shan if (pe->table_group.group) { 3467c5f7700bSGavin Shan iommu_group_put(pe->table_group.group); 3468c5f7700bSGavin Shan WARN_ON(pe->table_group.group); 3469c5f7700bSGavin Shan } 3470c5f7700bSGavin Shan 3471c5f7700bSGavin Shan free_pages(tbl->it_base, get_order(tbl->it_size << 3)); 3472e5afdf9dSAlexey Kardashevskiy iommu_tce_table_put(tbl); 3473c5f7700bSGavin Shan } 3474c5f7700bSGavin Shan 3475c5f7700bSGavin Shan static void pnv_pci_ioda2_release_pe_dma(struct pnv_ioda_pe *pe) 3476c5f7700bSGavin Shan { 3477c5f7700bSGavin Shan struct iommu_table *tbl = pe->table_group.tables[0]; 3478c5f7700bSGavin Shan unsigned int weight = pnv_pci_ioda_pe_dma_weight(pe); 3479c5f7700bSGavin Shan #ifdef CONFIG_IOMMU_API 3480c5f7700bSGavin Shan int64_t rc; 3481c5f7700bSGavin Shan #endif 3482c5f7700bSGavin Shan 3483c5f7700bSGavin Shan if (!weight) 3484c5f7700bSGavin Shan return; 3485c5f7700bSGavin Shan 3486c5f7700bSGavin Shan #ifdef CONFIG_IOMMU_API 3487c5f7700bSGavin Shan rc = pnv_pci_ioda2_unset_window(&pe->table_group, 0); 3488c5f7700bSGavin Shan if (rc) 3489c5f7700bSGavin Shan pe_warn(pe, "OPAL error %ld release DMA window\n", rc); 3490c5f7700bSGavin Shan #endif 3491c5f7700bSGavin Shan 3492c5f7700bSGavin Shan pnv_pci_ioda2_set_bypass(pe, false); 3493c5f7700bSGavin Shan if (pe->table_group.group) { 3494c5f7700bSGavin Shan iommu_group_put(pe->table_group.group); 3495c5f7700bSGavin Shan WARN_ON(pe->table_group.group); 3496c5f7700bSGavin Shan } 3497c5f7700bSGavin Shan 3498c5f7700bSGavin Shan pnv_pci_ioda2_table_free_pages(tbl); 3499e5afdf9dSAlexey Kardashevskiy iommu_tce_table_put(tbl); 3500c5f7700bSGavin Shan } 3501c5f7700bSGavin Shan 3502c5f7700bSGavin Shan static void pnv_ioda_free_pe_seg(struct pnv_ioda_pe *pe, 3503c5f7700bSGavin Shan unsigned short win, 3504c5f7700bSGavin Shan unsigned int *map) 3505c5f7700bSGavin Shan { 3506c5f7700bSGavin Shan struct pnv_phb *phb = pe->phb; 3507c5f7700bSGavin Shan int idx; 3508c5f7700bSGavin Shan int64_t rc; 3509c5f7700bSGavin Shan 3510c5f7700bSGavin Shan for (idx = 0; idx < phb->ioda.total_pe_num; idx++) { 3511c5f7700bSGavin Shan if (map[idx] != pe->pe_number) 3512c5f7700bSGavin Shan continue; 3513c5f7700bSGavin Shan 3514c5f7700bSGavin Shan if (win == OPAL_M64_WINDOW_TYPE) 3515c5f7700bSGavin Shan rc = opal_pci_map_pe_mmio_window(phb->opal_id, 3516c5f7700bSGavin Shan phb->ioda.reserved_pe_idx, win, 3517c5f7700bSGavin Shan idx / PNV_IODA1_M64_SEGS, 3518c5f7700bSGavin Shan idx % PNV_IODA1_M64_SEGS); 3519c5f7700bSGavin Shan else 3520c5f7700bSGavin Shan rc = opal_pci_map_pe_mmio_window(phb->opal_id, 3521c5f7700bSGavin Shan phb->ioda.reserved_pe_idx, win, 0, idx); 3522c5f7700bSGavin Shan 3523c5f7700bSGavin Shan if (rc != OPAL_SUCCESS) 3524c5f7700bSGavin Shan pe_warn(pe, "Error %ld unmapping (%d) segment#%d\n", 3525c5f7700bSGavin Shan rc, win, idx); 3526c5f7700bSGavin Shan 3527c5f7700bSGavin Shan map[idx] = IODA_INVALID_PE; 3528c5f7700bSGavin Shan } 3529c5f7700bSGavin Shan } 3530c5f7700bSGavin Shan 3531c5f7700bSGavin Shan static void pnv_ioda_release_pe_seg(struct pnv_ioda_pe *pe) 3532c5f7700bSGavin Shan { 3533c5f7700bSGavin Shan struct pnv_phb *phb = pe->phb; 3534c5f7700bSGavin Shan 3535c5f7700bSGavin Shan if (phb->type == PNV_PHB_IODA1) { 3536c5f7700bSGavin Shan pnv_ioda_free_pe_seg(pe, OPAL_IO_WINDOW_TYPE, 3537c5f7700bSGavin Shan phb->ioda.io_segmap); 3538c5f7700bSGavin Shan pnv_ioda_free_pe_seg(pe, OPAL_M32_WINDOW_TYPE, 3539c5f7700bSGavin Shan phb->ioda.m32_segmap); 3540c5f7700bSGavin Shan pnv_ioda_free_pe_seg(pe, OPAL_M64_WINDOW_TYPE, 3541c5f7700bSGavin Shan phb->ioda.m64_segmap); 3542c5f7700bSGavin Shan } else if (phb->type == PNV_PHB_IODA2) { 3543c5f7700bSGavin Shan pnv_ioda_free_pe_seg(pe, OPAL_M32_WINDOW_TYPE, 3544c5f7700bSGavin Shan phb->ioda.m32_segmap); 3545c5f7700bSGavin Shan } 3546c5f7700bSGavin Shan } 3547c5f7700bSGavin Shan 3548c5f7700bSGavin Shan static void pnv_ioda_release_pe(struct pnv_ioda_pe *pe) 3549c5f7700bSGavin Shan { 3550c5f7700bSGavin Shan struct pnv_phb *phb = pe->phb; 3551c5f7700bSGavin Shan struct pnv_ioda_pe *slave, *tmp; 3552c5f7700bSGavin Shan 3553c5f7700bSGavin Shan list_del(&pe->list); 3554c5f7700bSGavin Shan switch (phb->type) { 3555c5f7700bSGavin Shan case PNV_PHB_IODA1: 3556c5f7700bSGavin Shan pnv_pci_ioda1_release_pe_dma(pe); 3557c5f7700bSGavin Shan break; 3558c5f7700bSGavin Shan case PNV_PHB_IODA2: 3559c5f7700bSGavin Shan pnv_pci_ioda2_release_pe_dma(pe); 3560c5f7700bSGavin Shan break; 3561c5f7700bSGavin Shan default: 3562c5f7700bSGavin Shan WARN_ON(1); 3563c5f7700bSGavin Shan } 3564c5f7700bSGavin Shan 3565c5f7700bSGavin Shan pnv_ioda_release_pe_seg(pe); 3566c5f7700bSGavin Shan pnv_ioda_deconfigure_pe(pe->phb, pe); 3567b314427aSGavin Shan 3568b314427aSGavin Shan /* Release slave PEs in the compound PE */ 3569b314427aSGavin Shan if (pe->flags & PNV_IODA_PE_MASTER) { 3570b314427aSGavin Shan list_for_each_entry_safe(slave, tmp, &pe->slaves, list) { 3571b314427aSGavin Shan list_del(&slave->list); 3572b314427aSGavin Shan pnv_ioda_free_pe(slave); 3573b314427aSGavin Shan } 3574b314427aSGavin Shan } 3575b314427aSGavin Shan 35766eaed166SGavin Shan /* 35776eaed166SGavin Shan * The PE for root bus can be removed because of hotplug in EEH 35786eaed166SGavin Shan * recovery for fenced PHB error. We need to mark the PE dead so 35796eaed166SGavin Shan * that it can be populated again in PCI hot add path. The PE 35806eaed166SGavin Shan * shouldn't be destroyed as it's the global reserved resource. 35816eaed166SGavin Shan */ 35826eaed166SGavin Shan if (phb->ioda.root_pe_populated && 35836eaed166SGavin Shan phb->ioda.root_pe_idx == pe->pe_number) 35846eaed166SGavin Shan phb->ioda.root_pe_populated = false; 35856eaed166SGavin Shan else 3586c5f7700bSGavin Shan pnv_ioda_free_pe(pe); 3587c5f7700bSGavin Shan } 3588c5f7700bSGavin Shan 3589c5f7700bSGavin Shan static void pnv_pci_release_device(struct pci_dev *pdev) 3590c5f7700bSGavin Shan { 3591c5f7700bSGavin Shan struct pci_controller *hose = pci_bus_to_host(pdev->bus); 3592c5f7700bSGavin Shan struct pnv_phb *phb = hose->private_data; 3593c5f7700bSGavin Shan struct pci_dn *pdn = pci_get_pdn(pdev); 3594c5f7700bSGavin Shan struct pnv_ioda_pe *pe; 3595c5f7700bSGavin Shan 3596c5f7700bSGavin Shan if (pdev->is_virtfn) 3597c5f7700bSGavin Shan return; 3598c5f7700bSGavin Shan 3599c5f7700bSGavin Shan if (!pdn || pdn->pe_number == IODA_INVALID_PE) 3600c5f7700bSGavin Shan return; 3601c5f7700bSGavin Shan 360229bf282dSGavin Shan /* 360329bf282dSGavin Shan * PCI hotplug can happen as part of EEH error recovery. The @pdn 360429bf282dSGavin Shan * isn't removed and added afterwards in this scenario. We should 360529bf282dSGavin Shan * set the PE number in @pdn to an invalid one. Otherwise, the PE's 360629bf282dSGavin Shan * device count is decreased on removing devices while failing to 360729bf282dSGavin Shan * be increased on adding devices. It leads to unbalanced PE's device 360829bf282dSGavin Shan * count and eventually make normal PCI hotplug path broken. 360929bf282dSGavin Shan */ 3610c5f7700bSGavin Shan pe = &phb->ioda.pe_array[pdn->pe_number]; 361129bf282dSGavin Shan pdn->pe_number = IODA_INVALID_PE; 361229bf282dSGavin Shan 3613c5f7700bSGavin Shan WARN_ON(--pe->device_count < 0); 3614c5f7700bSGavin Shan if (pe->device_count == 0) 3615c5f7700bSGavin Shan pnv_ioda_release_pe(pe); 3616c5f7700bSGavin Shan } 3617c5f7700bSGavin Shan 36187a8e6bbfSMichael Neuling static void pnv_pci_ioda_shutdown(struct pci_controller *hose) 361973ed148aSBenjamin Herrenschmidt { 36207a8e6bbfSMichael Neuling struct pnv_phb *phb = hose->private_data; 36217a8e6bbfSMichael Neuling 3622d1a85eeeSGavin Shan opal_pci_reset(phb->opal_id, OPAL_RESET_PCI_IODA_TABLE, 362373ed148aSBenjamin Herrenschmidt OPAL_ASSERT_RESET); 362473ed148aSBenjamin Herrenschmidt } 362573ed148aSBenjamin Herrenschmidt 362692ae0353SDaniel Axtens static const struct pci_controller_ops pnv_pci_ioda_controller_ops = { 362792ae0353SDaniel Axtens .dma_dev_setup = pnv_pci_dma_dev_setup, 36281bc74f1cSGavin Shan .dma_bus_setup = pnv_pci_dma_bus_setup, 362992ae0353SDaniel Axtens #ifdef CONFIG_PCI_MSI 363092ae0353SDaniel Axtens .setup_msi_irqs = pnv_setup_msi_irqs, 363192ae0353SDaniel Axtens .teardown_msi_irqs = pnv_teardown_msi_irqs, 363292ae0353SDaniel Axtens #endif 363392ae0353SDaniel Axtens .enable_device_hook = pnv_pci_enable_device_hook, 3634c5f7700bSGavin Shan .release_device = pnv_pci_release_device, 363592ae0353SDaniel Axtens .window_alignment = pnv_pci_window_alignment, 3636ccd1c191SGavin Shan .setup_bridge = pnv_pci_setup_bridge, 363792ae0353SDaniel Axtens .reset_secondary_bus = pnv_pci_reset_secondary_bus, 3638763d2d8dSDaniel Axtens .dma_set_mask = pnv_pci_ioda_dma_set_mask, 363953522982SAndrew Donnellan .dma_get_required_mask = pnv_pci_ioda_dma_get_required_mask, 36407a8e6bbfSMichael Neuling .shutdown = pnv_pci_ioda_shutdown, 364192ae0353SDaniel Axtens }; 364292ae0353SDaniel Axtens 3643f9f83456SAlexey Kardashevskiy static int pnv_npu_dma_set_mask(struct pci_dev *npdev, u64 dma_mask) 3644f9f83456SAlexey Kardashevskiy { 3645f9f83456SAlexey Kardashevskiy dev_err_once(&npdev->dev, 3646f9f83456SAlexey Kardashevskiy "%s operation unsupported for NVLink devices\n", 3647f9f83456SAlexey Kardashevskiy __func__); 3648f9f83456SAlexey Kardashevskiy return -EPERM; 3649f9f83456SAlexey Kardashevskiy } 3650f9f83456SAlexey Kardashevskiy 36515d2aa710SAlistair Popple static const struct pci_controller_ops pnv_npu_ioda_controller_ops = { 36525d2aa710SAlistair Popple .dma_dev_setup = pnv_pci_dma_dev_setup, 36535d2aa710SAlistair Popple #ifdef CONFIG_PCI_MSI 36545d2aa710SAlistair Popple .setup_msi_irqs = pnv_setup_msi_irqs, 36555d2aa710SAlistair Popple .teardown_msi_irqs = pnv_teardown_msi_irqs, 36565d2aa710SAlistair Popple #endif 36575d2aa710SAlistair Popple .enable_device_hook = pnv_pci_enable_device_hook, 36585d2aa710SAlistair Popple .window_alignment = pnv_pci_window_alignment, 36595d2aa710SAlistair Popple .reset_secondary_bus = pnv_pci_reset_secondary_bus, 36605d2aa710SAlistair Popple .dma_set_mask = pnv_npu_dma_set_mask, 36615d2aa710SAlistair Popple .shutdown = pnv_pci_ioda_shutdown, 36625d2aa710SAlistair Popple }; 36635d2aa710SAlistair Popple 36644361b034SIan Munsie #ifdef CONFIG_CXL_BASE 36654361b034SIan Munsie const struct pci_controller_ops pnv_cxl_cx4_ioda_controller_ops = { 36664361b034SIan Munsie .dma_dev_setup = pnv_pci_dma_dev_setup, 36674361b034SIan Munsie .dma_bus_setup = pnv_pci_dma_bus_setup, 3668a2f67d5eSIan Munsie #ifdef CONFIG_PCI_MSI 3669a2f67d5eSIan Munsie .setup_msi_irqs = pnv_cxl_cx4_setup_msi_irqs, 3670a2f67d5eSIan Munsie .teardown_msi_irqs = pnv_cxl_cx4_teardown_msi_irqs, 3671a2f67d5eSIan Munsie #endif 36724361b034SIan Munsie .enable_device_hook = pnv_cxl_enable_device_hook, 36734361b034SIan Munsie .disable_device = pnv_cxl_disable_device, 36744361b034SIan Munsie .release_device = pnv_pci_release_device, 36754361b034SIan Munsie .window_alignment = pnv_pci_window_alignment, 36764361b034SIan Munsie .setup_bridge = pnv_pci_setup_bridge, 36774361b034SIan Munsie .reset_secondary_bus = pnv_pci_reset_secondary_bus, 36784361b034SIan Munsie .dma_set_mask = pnv_pci_ioda_dma_set_mask, 36794361b034SIan Munsie .dma_get_required_mask = pnv_pci_ioda_dma_get_required_mask, 36804361b034SIan Munsie .shutdown = pnv_pci_ioda_shutdown, 36814361b034SIan Munsie }; 36824361b034SIan Munsie #endif 36834361b034SIan Munsie 3684e51df2c1SAnton Blanchard static void __init pnv_pci_init_ioda_phb(struct device_node *np, 3685e9cc17d4SGavin Shan u64 hub_id, int ioda_type) 3686184cd4a3SBenjamin Herrenschmidt { 3687184cd4a3SBenjamin Herrenschmidt struct pci_controller *hose; 3688184cd4a3SBenjamin Herrenschmidt struct pnv_phb *phb; 36892b923ed1SGavin Shan unsigned long size, m64map_off, m32map_off, pemap_off; 36902b923ed1SGavin Shan unsigned long iomap_off = 0, dma32map_off = 0; 3691fd141d1aSBenjamin Herrenschmidt struct resource r; 3692c681b93cSAlistair Popple const __be64 *prop64; 36933a1a4661SBenjamin Herrenschmidt const __be32 *prop32; 3694f1b7cc3eSGavin Shan int len; 36953fa23ff8SGavin Shan unsigned int segno; 3696184cd4a3SBenjamin Herrenschmidt u64 phb_id; 3697184cd4a3SBenjamin Herrenschmidt void *aux; 3698184cd4a3SBenjamin Herrenschmidt long rc; 3699184cd4a3SBenjamin Herrenschmidt 370008a45b32SBenjamin Herrenschmidt if (!of_device_is_available(np)) 370108a45b32SBenjamin Herrenschmidt return; 370208a45b32SBenjamin Herrenschmidt 37039497a1c1SGavin Shan pr_info("Initializing %s PHB (%s)\n", 37049497a1c1SGavin Shan pnv_phb_names[ioda_type], of_node_full_name(np)); 3705184cd4a3SBenjamin Herrenschmidt 3706184cd4a3SBenjamin Herrenschmidt prop64 = of_get_property(np, "ibm,opal-phbid", NULL); 3707184cd4a3SBenjamin Herrenschmidt if (!prop64) { 3708184cd4a3SBenjamin Herrenschmidt pr_err(" Missing \"ibm,opal-phbid\" property !\n"); 3709184cd4a3SBenjamin Herrenschmidt return; 3710184cd4a3SBenjamin Herrenschmidt } 3711184cd4a3SBenjamin Herrenschmidt phb_id = be64_to_cpup(prop64); 3712184cd4a3SBenjamin Herrenschmidt pr_debug(" PHB-ID : 0x%016llx\n", phb_id); 3713184cd4a3SBenjamin Herrenschmidt 3714e39f223fSMichael Ellerman phb = memblock_virt_alloc(sizeof(struct pnv_phb), 0); 371558d714ecSGavin Shan 371658d714ecSGavin Shan /* Allocate PCI controller */ 3717184cd4a3SBenjamin Herrenschmidt phb->hose = hose = pcibios_alloc_controller(np); 371858d714ecSGavin Shan if (!phb->hose) { 371958d714ecSGavin Shan pr_err(" Can't allocate PCI controller for %s\n", 3720184cd4a3SBenjamin Herrenschmidt np->full_name); 3721e39f223fSMichael Ellerman memblock_free(__pa(phb), sizeof(struct pnv_phb)); 3722184cd4a3SBenjamin Herrenschmidt return; 3723184cd4a3SBenjamin Herrenschmidt } 3724184cd4a3SBenjamin Herrenschmidt 3725184cd4a3SBenjamin Herrenschmidt spin_lock_init(&phb->lock); 3726f1b7cc3eSGavin Shan prop32 = of_get_property(np, "bus-range", &len); 3727f1b7cc3eSGavin Shan if (prop32 && len == 8) { 37283a1a4661SBenjamin Herrenschmidt hose->first_busno = be32_to_cpu(prop32[0]); 37293a1a4661SBenjamin Herrenschmidt hose->last_busno = be32_to_cpu(prop32[1]); 3730f1b7cc3eSGavin Shan } else { 3731f1b7cc3eSGavin Shan pr_warn(" Broken <bus-range> on %s\n", np->full_name); 3732184cd4a3SBenjamin Herrenschmidt hose->first_busno = 0; 3733184cd4a3SBenjamin Herrenschmidt hose->last_busno = 0xff; 3734f1b7cc3eSGavin Shan } 3735184cd4a3SBenjamin Herrenschmidt hose->private_data = phb; 3736e9cc17d4SGavin Shan phb->hub_id = hub_id; 3737184cd4a3SBenjamin Herrenschmidt phb->opal_id = phb_id; 3738aa0c033fSGavin Shan phb->type = ioda_type; 3739781a868fSWei Yang mutex_init(&phb->ioda.pe_alloc_mutex); 3740184cd4a3SBenjamin Herrenschmidt 3741cee72d5bSBenjamin Herrenschmidt /* Detect specific models for error handling */ 3742cee72d5bSBenjamin Herrenschmidt if (of_device_is_compatible(np, "ibm,p7ioc-pciex")) 3743cee72d5bSBenjamin Herrenschmidt phb->model = PNV_PHB_MODEL_P7IOC; 3744f3d40c25SBenjamin Herrenschmidt else if (of_device_is_compatible(np, "ibm,power8-pciex")) 3745aa0c033fSGavin Shan phb->model = PNV_PHB_MODEL_PHB3; 37465d2aa710SAlistair Popple else if (of_device_is_compatible(np, "ibm,power8-npu-pciex")) 37475d2aa710SAlistair Popple phb->model = PNV_PHB_MODEL_NPU; 3748616badd2SAlistair Popple else if (of_device_is_compatible(np, "ibm,power9-npu-pciex")) 3749616badd2SAlistair Popple phb->model = PNV_PHB_MODEL_NPU2; 3750cee72d5bSBenjamin Herrenschmidt else 3751cee72d5bSBenjamin Herrenschmidt phb->model = PNV_PHB_MODEL_UNKNOWN; 3752cee72d5bSBenjamin Herrenschmidt 37535cb1f8fdSRussell Currey /* Initialize diagnostic data buffer */ 37545cb1f8fdSRussell Currey prop32 = of_get_property(np, "ibm,phb-diag-data-size", NULL); 37555cb1f8fdSRussell Currey if (prop32) 37565cb1f8fdSRussell Currey phb->diag_data_size = be32_to_cpup(prop32); 37575cb1f8fdSRussell Currey else 37585cb1f8fdSRussell Currey phb->diag_data_size = PNV_PCI_DIAG_BUF_SIZE; 37595cb1f8fdSRussell Currey 37605cb1f8fdSRussell Currey phb->diag_data = memblock_virt_alloc(phb->diag_data_size, 0); 37615cb1f8fdSRussell Currey 3762aa0c033fSGavin Shan /* Parse 32-bit and IO ranges (if any) */ 37632f1ec02eSGavin Shan pci_process_bridge_OF_ranges(hose, np, !hose->global_number); 3764184cd4a3SBenjamin Herrenschmidt 3765aa0c033fSGavin Shan /* Get registers */ 3766fd141d1aSBenjamin Herrenschmidt if (!of_address_to_resource(np, 0, &r)) { 3767fd141d1aSBenjamin Herrenschmidt phb->regs_phys = r.start; 3768fd141d1aSBenjamin Herrenschmidt phb->regs = ioremap(r.start, resource_size(&r)); 3769184cd4a3SBenjamin Herrenschmidt if (phb->regs == NULL) 3770184cd4a3SBenjamin Herrenschmidt pr_err(" Failed to map registers !\n"); 3771fd141d1aSBenjamin Herrenschmidt } 3772577c8c88SGavin Shan 3773184cd4a3SBenjamin Herrenschmidt /* Initialize more IODA stuff */ 377492b8f137SGavin Shan phb->ioda.total_pe_num = 1; 377536954dc7SGavin Shan prop32 = of_get_property(np, "ibm,opal-num-pes", NULL); 377636954dc7SGavin Shan if (prop32) 377792b8f137SGavin Shan phb->ioda.total_pe_num = be32_to_cpup(prop32); 377836954dc7SGavin Shan prop32 = of_get_property(np, "ibm,opal-reserved-pe", NULL); 377936954dc7SGavin Shan if (prop32) 378092b8f137SGavin Shan phb->ioda.reserved_pe_idx = be32_to_cpup(prop32); 3781262af557SGuo Chao 3782c127562aSGavin Shan /* Invalidate RID to PE# mapping */ 3783c127562aSGavin Shan for (segno = 0; segno < ARRAY_SIZE(phb->ioda.pe_rmap); segno++) 3784c127562aSGavin Shan phb->ioda.pe_rmap[segno] = IODA_INVALID_PE; 3785c127562aSGavin Shan 3786262af557SGuo Chao /* Parse 64-bit MMIO range */ 3787262af557SGuo Chao pnv_ioda_parse_m64_window(phb); 3788262af557SGuo Chao 3789184cd4a3SBenjamin Herrenschmidt phb->ioda.m32_size = resource_size(&hose->mem_resources[0]); 3790aa0c033fSGavin Shan /* FW Has already off top 64k of M32 space (MSI space) */ 3791184cd4a3SBenjamin Herrenschmidt phb->ioda.m32_size += 0x10000; 3792184cd4a3SBenjamin Herrenschmidt 379392b8f137SGavin Shan phb->ioda.m32_segsize = phb->ioda.m32_size / phb->ioda.total_pe_num; 37943fd47f06SBenjamin Herrenschmidt phb->ioda.m32_pci_base = hose->mem_resources[0].start - hose->mem_offset[0]; 3795184cd4a3SBenjamin Herrenschmidt phb->ioda.io_size = hose->pci_io_size; 379692b8f137SGavin Shan phb->ioda.io_segsize = phb->ioda.io_size / phb->ioda.total_pe_num; 3797184cd4a3SBenjamin Herrenschmidt phb->ioda.io_pci_base = 0; /* XXX calculate this ? */ 3798184cd4a3SBenjamin Herrenschmidt 37992b923ed1SGavin Shan /* Calculate how many 32-bit TCE segments we have */ 38002b923ed1SGavin Shan phb->ioda.dma32_count = phb->ioda.m32_pci_base / 38012b923ed1SGavin Shan PNV_IODA1_DMA32_SEGSIZE; 38022b923ed1SGavin Shan 3803c35d2a8cSGavin Shan /* Allocate aux data & arrays. We don't have IO ports on PHB3 */ 380492a86756SAlexey Kardashevskiy size = _ALIGN_UP(max_t(unsigned, phb->ioda.total_pe_num, 8) / 8, 380592a86756SAlexey Kardashevskiy sizeof(unsigned long)); 380693289d8cSGavin Shan m64map_off = size; 380793289d8cSGavin Shan size += phb->ioda.total_pe_num * sizeof(phb->ioda.m64_segmap[0]); 3808184cd4a3SBenjamin Herrenschmidt m32map_off = size; 380992b8f137SGavin Shan size += phb->ioda.total_pe_num * sizeof(phb->ioda.m32_segmap[0]); 3810c35d2a8cSGavin Shan if (phb->type == PNV_PHB_IODA1) { 3811c35d2a8cSGavin Shan iomap_off = size; 381292b8f137SGavin Shan size += phb->ioda.total_pe_num * sizeof(phb->ioda.io_segmap[0]); 38132b923ed1SGavin Shan dma32map_off = size; 38142b923ed1SGavin Shan size += phb->ioda.dma32_count * 38152b923ed1SGavin Shan sizeof(phb->ioda.dma32_segmap[0]); 3816c35d2a8cSGavin Shan } 3817184cd4a3SBenjamin Herrenschmidt pemap_off = size; 381892b8f137SGavin Shan size += phb->ioda.total_pe_num * sizeof(struct pnv_ioda_pe); 3819e39f223fSMichael Ellerman aux = memblock_virt_alloc(size, 0); 3820184cd4a3SBenjamin Herrenschmidt phb->ioda.pe_alloc = aux; 382193289d8cSGavin Shan phb->ioda.m64_segmap = aux + m64map_off; 3822184cd4a3SBenjamin Herrenschmidt phb->ioda.m32_segmap = aux + m32map_off; 382393289d8cSGavin Shan for (segno = 0; segno < phb->ioda.total_pe_num; segno++) { 382493289d8cSGavin Shan phb->ioda.m64_segmap[segno] = IODA_INVALID_PE; 38253fa23ff8SGavin Shan phb->ioda.m32_segmap[segno] = IODA_INVALID_PE; 382693289d8cSGavin Shan } 38273fa23ff8SGavin Shan if (phb->type == PNV_PHB_IODA1) { 3828184cd4a3SBenjamin Herrenschmidt phb->ioda.io_segmap = aux + iomap_off; 38293fa23ff8SGavin Shan for (segno = 0; segno < phb->ioda.total_pe_num; segno++) 38303fa23ff8SGavin Shan phb->ioda.io_segmap[segno] = IODA_INVALID_PE; 38312b923ed1SGavin Shan 38322b923ed1SGavin Shan phb->ioda.dma32_segmap = aux + dma32map_off; 38332b923ed1SGavin Shan for (segno = 0; segno < phb->ioda.dma32_count; segno++) 38342b923ed1SGavin Shan phb->ioda.dma32_segmap[segno] = IODA_INVALID_PE; 38353fa23ff8SGavin Shan } 3836184cd4a3SBenjamin Herrenschmidt phb->ioda.pe_array = aux + pemap_off; 383763803c39SGavin Shan 383863803c39SGavin Shan /* 383963803c39SGavin Shan * Choose PE number for root bus, which shouldn't have 384063803c39SGavin Shan * M64 resources consumed by its child devices. To pick 384163803c39SGavin Shan * the PE number adjacent to the reserved one if possible. 384263803c39SGavin Shan */ 384363803c39SGavin Shan pnv_ioda_reserve_pe(phb, phb->ioda.reserved_pe_idx); 384463803c39SGavin Shan if (phb->ioda.reserved_pe_idx == 0) { 384563803c39SGavin Shan phb->ioda.root_pe_idx = 1; 384663803c39SGavin Shan pnv_ioda_reserve_pe(phb, phb->ioda.root_pe_idx); 384763803c39SGavin Shan } else if (phb->ioda.reserved_pe_idx == (phb->ioda.total_pe_num - 1)) { 384863803c39SGavin Shan phb->ioda.root_pe_idx = phb->ioda.reserved_pe_idx - 1; 384963803c39SGavin Shan pnv_ioda_reserve_pe(phb, phb->ioda.root_pe_idx); 385063803c39SGavin Shan } else { 385163803c39SGavin Shan phb->ioda.root_pe_idx = IODA_INVALID_PE; 385263803c39SGavin Shan } 3853184cd4a3SBenjamin Herrenschmidt 3854184cd4a3SBenjamin Herrenschmidt INIT_LIST_HEAD(&phb->ioda.pe_list); 3855781a868fSWei Yang mutex_init(&phb->ioda.pe_list_mutex); 3856184cd4a3SBenjamin Herrenschmidt 3857184cd4a3SBenjamin Herrenschmidt /* Calculate how many 32-bit TCE segments we have */ 38582b923ed1SGavin Shan phb->ioda.dma32_count = phb->ioda.m32_pci_base / 3859acce971cSGavin Shan PNV_IODA1_DMA32_SEGSIZE; 3860184cd4a3SBenjamin Herrenschmidt 3861aa0c033fSGavin Shan #if 0 /* We should really do that ... */ 3862184cd4a3SBenjamin Herrenschmidt rc = opal_pci_set_phb_mem_window(opal->phb_id, 3863184cd4a3SBenjamin Herrenschmidt window_type, 3864184cd4a3SBenjamin Herrenschmidt window_num, 3865184cd4a3SBenjamin Herrenschmidt starting_real_address, 3866184cd4a3SBenjamin Herrenschmidt starting_pci_address, 3867184cd4a3SBenjamin Herrenschmidt segment_size); 3868184cd4a3SBenjamin Herrenschmidt #endif 3869184cd4a3SBenjamin Herrenschmidt 3870262af557SGuo Chao pr_info(" %03d (%03d) PE's M32: 0x%x [segment=0x%x]\n", 387192b8f137SGavin Shan phb->ioda.total_pe_num, phb->ioda.reserved_pe_idx, 3872262af557SGuo Chao phb->ioda.m32_size, phb->ioda.m32_segsize); 3873262af557SGuo Chao if (phb->ioda.m64_size) 3874262af557SGuo Chao pr_info(" M64: 0x%lx [segment=0x%lx]\n", 3875262af557SGuo Chao phb->ioda.m64_size, phb->ioda.m64_segsize); 3876262af557SGuo Chao if (phb->ioda.io_size) 3877262af557SGuo Chao pr_info(" IO: 0x%x [segment=0x%x]\n", 3878184cd4a3SBenjamin Herrenschmidt phb->ioda.io_size, phb->ioda.io_segsize); 3879184cd4a3SBenjamin Herrenschmidt 3880262af557SGuo Chao 3881184cd4a3SBenjamin Herrenschmidt phb->hose->ops = &pnv_pci_ops; 388249dec922SGavin Shan phb->get_pe_state = pnv_ioda_get_pe_state; 388349dec922SGavin Shan phb->freeze_pe = pnv_ioda_freeze_pe; 388449dec922SGavin Shan phb->unfreeze_pe = pnv_ioda_unfreeze_pe; 3885184cd4a3SBenjamin Herrenschmidt 3886184cd4a3SBenjamin Herrenschmidt /* Setup MSI support */ 3887184cd4a3SBenjamin Herrenschmidt pnv_pci_init_ioda_msis(phb); 3888184cd4a3SBenjamin Herrenschmidt 3889c40a4210SGavin Shan /* 3890c40a4210SGavin Shan * We pass the PCI probe flag PCI_REASSIGN_ALL_RSRC here 3891c40a4210SGavin Shan * to let the PCI core do resource assignment. It's supposed 3892c40a4210SGavin Shan * that the PCI core will do correct I/O and MMIO alignment 3893c40a4210SGavin Shan * for the P2P bridge bars so that each PCI bus (excluding 3894c40a4210SGavin Shan * the child P2P bridges) can form individual PE. 3895184cd4a3SBenjamin Herrenschmidt */ 3896fb446ad0SGavin Shan ppc_md.pcibios_fixup = pnv_pci_ioda_fixup; 38975d2aa710SAlistair Popple 3898f9f83456SAlexey Kardashevskiy if (phb->type == PNV_PHB_NPU) { 38995d2aa710SAlistair Popple hose->controller_ops = pnv_npu_ioda_controller_ops; 3900f9f83456SAlexey Kardashevskiy } else { 3901f9f83456SAlexey Kardashevskiy phb->dma_dev_setup = pnv_pci_ioda_dma_dev_setup; 390292ae0353SDaniel Axtens hose->controller_ops = pnv_pci_ioda_controller_ops; 3903f9f83456SAlexey Kardashevskiy } 3904ad30cb99SMichael Ellerman 390538274637SYongji Xie ppc_md.pcibios_default_alignment = pnv_pci_default_alignment; 390638274637SYongji Xie 39076e628c7dSWei Yang #ifdef CONFIG_PCI_IOV 39086e628c7dSWei Yang ppc_md.pcibios_fixup_sriov = pnv_pci_ioda_fixup_iov_resources; 39095350ab3fSWei Yang ppc_md.pcibios_iov_resource_alignment = pnv_pci_iov_resource_alignment; 3910ad30cb99SMichael Ellerman #endif 3911ad30cb99SMichael Ellerman 3912c40a4210SGavin Shan pci_add_flags(PCI_REASSIGN_ALL_RSRC); 3913184cd4a3SBenjamin Herrenschmidt 3914184cd4a3SBenjamin Herrenschmidt /* Reset IODA tables to a clean state */ 3915d1a85eeeSGavin Shan rc = opal_pci_reset(phb_id, OPAL_RESET_PCI_IODA_TABLE, OPAL_ASSERT_RESET); 3916184cd4a3SBenjamin Herrenschmidt if (rc) 3917f11fe552SBenjamin Herrenschmidt pr_warning(" OPAL Error %ld performing IODA table reset !\n", rc); 3918361f2a2aSGavin Shan 39196060e9eaSAndrew Donnellan /* 39206060e9eaSAndrew Donnellan * If we're running in kdump kernel, the previous kernel never 3921361f2a2aSGavin Shan * shutdown PCI devices correctly. We already got IODA table 3922361f2a2aSGavin Shan * cleaned out. So we have to issue PHB reset to stop all PCI 39236060e9eaSAndrew Donnellan * transactions from previous kernel. 3924361f2a2aSGavin Shan */ 3925361f2a2aSGavin Shan if (is_kdump_kernel()) { 3926361f2a2aSGavin Shan pr_info(" Issue PHB reset ...\n"); 3927cadf364dSGavin Shan pnv_eeh_phb_reset(hose, EEH_RESET_FUNDAMENTAL); 3928cadf364dSGavin Shan pnv_eeh_phb_reset(hose, EEH_RESET_DEACTIVATE); 3929361f2a2aSGavin Shan } 3930262af557SGuo Chao 39319e9e8935SGavin Shan /* Remove M64 resource if we can't configure it successfully */ 39329e9e8935SGavin Shan if (!phb->init_m64 || phb->init_m64(phb)) 3933262af557SGuo Chao hose->mem_resources[1].flags = 0; 3934184cd4a3SBenjamin Herrenschmidt } 3935184cd4a3SBenjamin Herrenschmidt 393667975005SBjorn Helgaas void __init pnv_pci_init_ioda2_phb(struct device_node *np) 3937aa0c033fSGavin Shan { 3938e9cc17d4SGavin Shan pnv_pci_init_ioda_phb(np, 0, PNV_PHB_IODA2); 3939aa0c033fSGavin Shan } 3940aa0c033fSGavin Shan 39415d2aa710SAlistair Popple void __init pnv_pci_init_npu_phb(struct device_node *np) 39425d2aa710SAlistair Popple { 39435d2aa710SAlistair Popple pnv_pci_init_ioda_phb(np, 0, PNV_PHB_NPU); 39445d2aa710SAlistair Popple } 39455d2aa710SAlistair Popple 3946184cd4a3SBenjamin Herrenschmidt void __init pnv_pci_init_ioda_hub(struct device_node *np) 3947184cd4a3SBenjamin Herrenschmidt { 3948184cd4a3SBenjamin Herrenschmidt struct device_node *phbn; 3949c681b93cSAlistair Popple const __be64 *prop64; 3950184cd4a3SBenjamin Herrenschmidt u64 hub_id; 3951184cd4a3SBenjamin Herrenschmidt 3952184cd4a3SBenjamin Herrenschmidt pr_info("Probing IODA IO-Hub %s\n", np->full_name); 3953184cd4a3SBenjamin Herrenschmidt 3954184cd4a3SBenjamin Herrenschmidt prop64 = of_get_property(np, "ibm,opal-hubid", NULL); 3955184cd4a3SBenjamin Herrenschmidt if (!prop64) { 3956184cd4a3SBenjamin Herrenschmidt pr_err(" Missing \"ibm,opal-hubid\" property !\n"); 3957184cd4a3SBenjamin Herrenschmidt return; 3958184cd4a3SBenjamin Herrenschmidt } 3959184cd4a3SBenjamin Herrenschmidt hub_id = be64_to_cpup(prop64); 3960184cd4a3SBenjamin Herrenschmidt pr_devel(" HUB-ID : 0x%016llx\n", hub_id); 3961184cd4a3SBenjamin Herrenschmidt 3962184cd4a3SBenjamin Herrenschmidt /* Count child PHBs */ 3963184cd4a3SBenjamin Herrenschmidt for_each_child_of_node(np, phbn) { 3964184cd4a3SBenjamin Herrenschmidt /* Look for IODA1 PHBs */ 3965184cd4a3SBenjamin Herrenschmidt if (of_device_is_compatible(phbn, "ibm,ioda-phb")) 3966e9cc17d4SGavin Shan pnv_pci_init_ioda_phb(phbn, hub_id, PNV_PHB_IODA1); 3967184cd4a3SBenjamin Herrenschmidt } 3968184cd4a3SBenjamin Herrenschmidt } 3969