12874c5fdSThomas Gleixner // SPDX-License-Identifier: GPL-2.0-or-later 2184cd4a3SBenjamin Herrenschmidt /* 3184cd4a3SBenjamin Herrenschmidt * Support PCI/PCIe on PowerNV platforms 4184cd4a3SBenjamin Herrenschmidt * 5184cd4a3SBenjamin Herrenschmidt * Copyright 2011 Benjamin Herrenschmidt, IBM Corp. 6184cd4a3SBenjamin Herrenschmidt */ 7184cd4a3SBenjamin Herrenschmidt 8cee72d5bSBenjamin Herrenschmidt #undef DEBUG 9184cd4a3SBenjamin Herrenschmidt 10184cd4a3SBenjamin Herrenschmidt #include <linux/kernel.h> 11184cd4a3SBenjamin Herrenschmidt #include <linux/pci.h> 12361f2a2aSGavin Shan #include <linux/crash_dump.h> 13184cd4a3SBenjamin Herrenschmidt #include <linux/delay.h> 14184cd4a3SBenjamin Herrenschmidt #include <linux/string.h> 15184cd4a3SBenjamin Herrenschmidt #include <linux/init.h> 1657c8a661SMike Rapoport #include <linux/memblock.h> 17184cd4a3SBenjamin Herrenschmidt #include <linux/irq.h> 18184cd4a3SBenjamin Herrenschmidt #include <linux/io.h> 19184cd4a3SBenjamin Herrenschmidt #include <linux/msi.h> 20ac9a5889SAlexey Kardashevskiy #include <linux/iommu.h> 21e57080f1SAlexey Kardashevskiy #include <linux/rculist.h> 224793d65dSAlexey Kardashevskiy #include <linux/sizes.h> 23dbf77fedSAneesh Kumar K.V #include <linux/debugfs.h> 24e6f6390aSChristophe Leroy #include <linux/of_address.h> 25e6f6390aSChristophe Leroy #include <linux/of_irq.h> 26184cd4a3SBenjamin Herrenschmidt 27184cd4a3SBenjamin Herrenschmidt #include <asm/sections.h> 28184cd4a3SBenjamin Herrenschmidt #include <asm/io.h> 29184cd4a3SBenjamin Herrenschmidt #include <asm/pci-bridge.h> 30184cd4a3SBenjamin Herrenschmidt #include <asm/machdep.h> 31fb1b55d6SGavin Shan #include <asm/msi_bitmap.h> 32184cd4a3SBenjamin Herrenschmidt #include <asm/ppc-pci.h> 33184cd4a3SBenjamin Herrenschmidt #include <asm/opal.h> 34184cd4a3SBenjamin Herrenschmidt #include <asm/iommu.h> 35184cd4a3SBenjamin Herrenschmidt #include <asm/tce.h> 36137436c9SGavin Shan #include <asm/xics.h> 37262af557SGuo Chao #include <asm/firmware.h> 3880c49c7eSIan Munsie #include <asm/pnv-pci.h> 39aca6913fSAlexey Kardashevskiy #include <asm/mmzone.h> 400fcfe224SCédric Le Goater #include <asm/xive.h> 4180c49c7eSIan Munsie 42ec249dd8SMichael Neuling #include <misc/cxl-base.h> 43184cd4a3SBenjamin Herrenschmidt 44184cd4a3SBenjamin Herrenschmidt #include "powernv.h" 45184cd4a3SBenjamin Herrenschmidt #include "pci.h" 4644bda4b7SHari Vyas #include "../../../../drivers/pci/pci.h" 47184cd4a3SBenjamin Herrenschmidt 4899451551SGavin Shan #define PNV_IODA1_M64_NUM 16 /* Number of M64 BARs */ 4999451551SGavin Shan #define PNV_IODA1_M64_SEGS 8 /* Segments per M64 BAR */ 50acce971cSGavin Shan #define PNV_IODA1_DMA32_SEGSIZE 0x10000000 51781a868fSWei Yang 52562d1e20SChristoph Hellwig static const char * const pnv_phb_names[] = { "IODA1", "IODA2", "NPU_OCAPI" }; 53aca6913fSAlexey Kardashevskiy 54c498a4f9SChristoph Hellwig static void pnv_pci_ioda2_set_bypass(struct pnv_ioda_pe *pe, bool enable); 55dc3d8f85SOliver O'Halloran static void pnv_pci_configure_bus(struct pci_bus *bus); 56c498a4f9SChristoph Hellwig 577d623e42SAlexey Kardashevskiy void pe_level_printk(const struct pnv_ioda_pe *pe, const char *level, 586d31c2faSJoe Perches const char *fmt, ...) 596d31c2faSJoe Perches { 606d31c2faSJoe Perches struct va_format vaf; 616d31c2faSJoe Perches va_list args; 626d31c2faSJoe Perches char pfix[32]; 63184cd4a3SBenjamin Herrenschmidt 646d31c2faSJoe Perches va_start(args, fmt); 656d31c2faSJoe Perches 666d31c2faSJoe Perches vaf.fmt = fmt; 676d31c2faSJoe Perches vaf.va = &args; 686d31c2faSJoe Perches 69781a868fSWei Yang if (pe->flags & PNV_IODA_PE_DEV) 7014be3756SWolfram Sang strscpy(pfix, dev_name(&pe->pdev->dev), sizeof(pfix)); 71781a868fSWei Yang else if (pe->flags & (PNV_IODA_PE_BUS | PNV_IODA_PE_BUS_ALL)) 726d31c2faSJoe Perches sprintf(pfix, "%04x:%02x ", 736d31c2faSJoe Perches pci_domain_nr(pe->pbus), pe->pbus->number); 74781a868fSWei Yang #ifdef CONFIG_PCI_IOV 75781a868fSWei Yang else if (pe->flags & PNV_IODA_PE_VF) 76781a868fSWei Yang sprintf(pfix, "%04x:%02x:%2x.%d", 77781a868fSWei Yang pci_domain_nr(pe->parent_dev->bus), 78781a868fSWei Yang (pe->rid & 0xff00) >> 8, 79781a868fSWei Yang PCI_SLOT(pe->rid), PCI_FUNC(pe->rid)); 80781a868fSWei Yang #endif /* CONFIG_PCI_IOV*/ 816d31c2faSJoe Perches 821f52f176SRussell Currey printk("%spci %s: [PE# %.2x] %pV", 836d31c2faSJoe Perches level, pfix, pe->pe_number, &vaf); 846d31c2faSJoe Perches 856d31c2faSJoe Perches va_end(args); 866d31c2faSJoe Perches } 876d31c2faSJoe Perches 884e287840SThadeu Lima de Souza Cascardo static bool pnv_iommu_bypass_disabled __read_mostly; 8945baee14SGuilherme G. Piccoli static bool pci_reset_phbs __read_mostly; 904e287840SThadeu Lima de Souza Cascardo 914e287840SThadeu Lima de Souza Cascardo static int __init iommu_setup(char *str) 924e287840SThadeu Lima de Souza Cascardo { 934e287840SThadeu Lima de Souza Cascardo if (!str) 944e287840SThadeu Lima de Souza Cascardo return -EINVAL; 954e287840SThadeu Lima de Souza Cascardo 964e287840SThadeu Lima de Souza Cascardo while (*str) { 974e287840SThadeu Lima de Souza Cascardo if (!strncmp(str, "nobypass", 8)) { 984e287840SThadeu Lima de Souza Cascardo pnv_iommu_bypass_disabled = true; 994e287840SThadeu Lima de Souza Cascardo pr_info("PowerNV: IOMMU bypass window disabled.\n"); 1004e287840SThadeu Lima de Souza Cascardo break; 1014e287840SThadeu Lima de Souza Cascardo } 1024e287840SThadeu Lima de Souza Cascardo str += strcspn(str, ","); 1034e287840SThadeu Lima de Souza Cascardo if (*str == ',') 1044e287840SThadeu Lima de Souza Cascardo str++; 1054e287840SThadeu Lima de Souza Cascardo } 1064e287840SThadeu Lima de Souza Cascardo 1074e287840SThadeu Lima de Souza Cascardo return 0; 1084e287840SThadeu Lima de Souza Cascardo } 1094e287840SThadeu Lima de Souza Cascardo early_param("iommu", iommu_setup); 1104e287840SThadeu Lima de Souza Cascardo 11145baee14SGuilherme G. Piccoli static int __init pci_reset_phbs_setup(char *str) 11245baee14SGuilherme G. Piccoli { 11345baee14SGuilherme G. Piccoli pci_reset_phbs = true; 11445baee14SGuilherme G. Piccoli return 0; 11545baee14SGuilherme G. Piccoli } 11645baee14SGuilherme G. Piccoli 11745baee14SGuilherme G. Piccoli early_param("ppc_pci_reset_phbs", pci_reset_phbs_setup); 11845baee14SGuilherme G. Piccoli 1191e916772SGavin Shan static struct pnv_ioda_pe *pnv_ioda_init_pe(struct pnv_phb *phb, int pe_no) 1201e916772SGavin Shan { 121313483ddSGavin Shan s64 rc; 122313483ddSGavin Shan 1231e916772SGavin Shan phb->ioda.pe_array[pe_no].phb = phb; 1241e916772SGavin Shan phb->ioda.pe_array[pe_no].pe_number = pe_no; 12501e12629SOliver O'Halloran phb->ioda.pe_array[pe_no].dma_setup_done = false; 1261e916772SGavin Shan 127313483ddSGavin Shan /* 128313483ddSGavin Shan * Clear the PE frozen state as it might be put into frozen state 129313483ddSGavin Shan * in the last PCI remove path. It's not harmful to do so when the 130313483ddSGavin Shan * PE is already in unfrozen state. 131313483ddSGavin Shan */ 132313483ddSGavin Shan rc = opal_pci_eeh_freeze_clear(phb->opal_id, pe_no, 133313483ddSGavin Shan OPAL_EEH_ACTION_CLEAR_FREEZE_ALL); 134d4791db5SRussell Currey if (rc != OPAL_SUCCESS && rc != OPAL_UNSUPPORTED) 1351f52f176SRussell Currey pr_warn("%s: Error %lld unfreezing PHB#%x-PE#%x\n", 136313483ddSGavin Shan __func__, rc, phb->hose->global_number, pe_no); 137313483ddSGavin Shan 1381e916772SGavin Shan return &phb->ioda.pe_array[pe_no]; 1391e916772SGavin Shan } 1401e916772SGavin Shan 1414b82ab18SGavin Shan static void pnv_ioda_reserve_pe(struct pnv_phb *phb, int pe_no) 1424b82ab18SGavin Shan { 14392b8f137SGavin Shan if (!(pe_no >= 0 && pe_no < phb->ioda.total_pe_num)) { 1441f52f176SRussell Currey pr_warn("%s: Invalid PE %x on PHB#%x\n", 1454b82ab18SGavin Shan __func__, pe_no, phb->hose->global_number); 1464b82ab18SGavin Shan return; 1474b82ab18SGavin Shan } 1484b82ab18SGavin Shan 149a4bc676eSOliver O'Halloran mutex_lock(&phb->ioda.pe_alloc_mutex); 150e9dc4d7fSGavin Shan if (test_and_set_bit(pe_no, phb->ioda.pe_alloc)) 1511f52f176SRussell Currey pr_debug("%s: PE %x was reserved on PHB#%x\n", 1524b82ab18SGavin Shan __func__, pe_no, phb->hose->global_number); 153a4bc676eSOliver O'Halloran mutex_unlock(&phb->ioda.pe_alloc_mutex); 1544b82ab18SGavin Shan 1551e916772SGavin Shan pnv_ioda_init_pe(phb, pe_no); 1564b82ab18SGavin Shan } 1574b82ab18SGavin Shan 158a4bc676eSOliver O'Halloran struct pnv_ioda_pe *pnv_ioda_alloc_pe(struct pnv_phb *phb, int count) 159184cd4a3SBenjamin Herrenschmidt { 160a4bc676eSOliver O'Halloran struct pnv_ioda_pe *ret = NULL; 161a4bc676eSOliver O'Halloran int run = 0, pe, i; 162184cd4a3SBenjamin Herrenschmidt 163a4bc676eSOliver O'Halloran mutex_lock(&phb->ioda.pe_alloc_mutex); 164a4bc676eSOliver O'Halloran 165a4bc676eSOliver O'Halloran /* scan backwards for a run of @count cleared bits */ 1669fcd6f4aSGavin Shan for (pe = phb->ioda.total_pe_num - 1; pe >= 0; pe--) { 167a4bc676eSOliver O'Halloran if (test_bit(pe, phb->ioda.pe_alloc)) { 168a4bc676eSOliver O'Halloran run = 0; 169a4bc676eSOliver O'Halloran continue; 170184cd4a3SBenjamin Herrenschmidt } 171184cd4a3SBenjamin Herrenschmidt 172a4bc676eSOliver O'Halloran run++; 173a4bc676eSOliver O'Halloran if (run == count) 174a4bc676eSOliver O'Halloran break; 175a4bc676eSOliver O'Halloran } 176a4bc676eSOliver O'Halloran if (run != count) 177a4bc676eSOliver O'Halloran goto out; 178a4bc676eSOliver O'Halloran 179a4bc676eSOliver O'Halloran for (i = pe; i < pe + count; i++) { 180a4bc676eSOliver O'Halloran set_bit(i, phb->ioda.pe_alloc); 181a4bc676eSOliver O'Halloran pnv_ioda_init_pe(phb, i); 182a4bc676eSOliver O'Halloran } 183a4bc676eSOliver O'Halloran ret = &phb->ioda.pe_array[pe]; 184a4bc676eSOliver O'Halloran 185a4bc676eSOliver O'Halloran out: 186a4bc676eSOliver O'Halloran mutex_unlock(&phb->ioda.pe_alloc_mutex); 187a4bc676eSOliver O'Halloran return ret; 1889fcd6f4aSGavin Shan } 1899fcd6f4aSGavin Shan 19037b59ef0SOliver O'Halloran void pnv_ioda_free_pe(struct pnv_ioda_pe *pe) 191184cd4a3SBenjamin Herrenschmidt { 1921e916772SGavin Shan struct pnv_phb *phb = pe->phb; 193caa58f80SGavin Shan unsigned int pe_num = pe->pe_number; 194184cd4a3SBenjamin Herrenschmidt 1951e916772SGavin Shan WARN_ON(pe->pdev); 1961e916772SGavin Shan memset(pe, 0, sizeof(struct pnv_ioda_pe)); 197a4bc676eSOliver O'Halloran 198a4bc676eSOliver O'Halloran mutex_lock(&phb->ioda.pe_alloc_mutex); 199caa58f80SGavin Shan clear_bit(pe_num, phb->ioda.pe_alloc); 200a4bc676eSOliver O'Halloran mutex_unlock(&phb->ioda.pe_alloc_mutex); 201184cd4a3SBenjamin Herrenschmidt } 202184cd4a3SBenjamin Herrenschmidt 203262af557SGuo Chao /* The default M64 BAR is shared by all PEs */ 204262af557SGuo Chao static int pnv_ioda2_init_m64(struct pnv_phb *phb) 205262af557SGuo Chao { 206262af557SGuo Chao const char *desc; 207262af557SGuo Chao struct resource *r; 208262af557SGuo Chao s64 rc; 209262af557SGuo Chao 210262af557SGuo Chao /* Configure the default M64 BAR */ 211262af557SGuo Chao rc = opal_pci_set_phb_mem_window(phb->opal_id, 212262af557SGuo Chao OPAL_M64_WINDOW_TYPE, 213262af557SGuo Chao phb->ioda.m64_bar_idx, 214262af557SGuo Chao phb->ioda.m64_base, 215262af557SGuo Chao 0, /* unused */ 216262af557SGuo Chao phb->ioda.m64_size); 217262af557SGuo Chao if (rc != OPAL_SUCCESS) { 218262af557SGuo Chao desc = "configuring"; 219262af557SGuo Chao goto fail; 220262af557SGuo Chao } 221262af557SGuo Chao 222262af557SGuo Chao /* Enable the default M64 BAR */ 223262af557SGuo Chao rc = opal_pci_phb_mmio_enable(phb->opal_id, 224262af557SGuo Chao OPAL_M64_WINDOW_TYPE, 225262af557SGuo Chao phb->ioda.m64_bar_idx, 226262af557SGuo Chao OPAL_ENABLE_M64_SPLIT); 227262af557SGuo Chao if (rc != OPAL_SUCCESS) { 228262af557SGuo Chao desc = "enabling"; 229262af557SGuo Chao goto fail; 230262af557SGuo Chao } 231262af557SGuo Chao 232262af557SGuo Chao /* 23363803c39SGavin Shan * Exclude the segments for reserved and root bus PE, which 23463803c39SGavin Shan * are first or last two PEs. 235262af557SGuo Chao */ 236262af557SGuo Chao r = &phb->hose->mem_resources[1]; 23792b8f137SGavin Shan if (phb->ioda.reserved_pe_idx == 0) 23863803c39SGavin Shan r->start += (2 * phb->ioda.m64_segsize); 23992b8f137SGavin Shan else if (phb->ioda.reserved_pe_idx == (phb->ioda.total_pe_num - 1)) 24063803c39SGavin Shan r->end -= (2 * phb->ioda.m64_segsize); 241262af557SGuo Chao else 2421f52f176SRussell Currey pr_warn(" Cannot strip M64 segment for reserved PE#%x\n", 24392b8f137SGavin Shan phb->ioda.reserved_pe_idx); 244262af557SGuo Chao 245262af557SGuo Chao return 0; 246262af557SGuo Chao 247262af557SGuo Chao fail: 248262af557SGuo Chao pr_warn(" Failure %lld %s M64 BAR#%d\n", 249262af557SGuo Chao rc, desc, phb->ioda.m64_bar_idx); 250262af557SGuo Chao opal_pci_phb_mmio_enable(phb->opal_id, 251262af557SGuo Chao OPAL_M64_WINDOW_TYPE, 252262af557SGuo Chao phb->ioda.m64_bar_idx, 253262af557SGuo Chao OPAL_DISABLE_M64); 254262af557SGuo Chao return -EIO; 255262af557SGuo Chao } 256262af557SGuo Chao 257c430670aSGavin Shan static void pnv_ioda_reserve_dev_m64_pe(struct pci_dev *pdev, 25896a2f92bSGavin Shan unsigned long *pe_bitmap) 259262af557SGuo Chao { 2605609ffddSOliver O'Halloran struct pnv_phb *phb = pci_bus_to_pnvhb(pdev->bus); 261262af557SGuo Chao struct resource *r; 26296a2f92bSGavin Shan resource_size_t base, sgsz, start, end; 26396a2f92bSGavin Shan int segno, i; 264262af557SGuo Chao 26596a2f92bSGavin Shan base = phb->ioda.m64_base; 26696a2f92bSGavin Shan sgsz = phb->ioda.m64_segsize; 26796a2f92bSGavin Shan for (i = 0; i <= PCI_ROM_RESOURCE; i++) { 26896a2f92bSGavin Shan r = &pdev->resource[i]; 2695958d19aSBenjamin Herrenschmidt if (!r->parent || !pnv_pci_is_m64(phb, r)) 270262af557SGuo Chao continue; 271262af557SGuo Chao 272e96d904eSChristophe Leroy start = ALIGN_DOWN(r->start - base, sgsz); 273b7115316SChristophe Leroy end = ALIGN(r->end - base, sgsz); 27496a2f92bSGavin Shan for (segno = start / sgsz; segno < end / sgsz; segno++) { 27596a2f92bSGavin Shan if (pe_bitmap) 27696a2f92bSGavin Shan set_bit(segno, pe_bitmap); 27796a2f92bSGavin Shan else 27896a2f92bSGavin Shan pnv_ioda_reserve_pe(phb, segno); 279262af557SGuo Chao } 280262af557SGuo Chao } 281262af557SGuo Chao } 282262af557SGuo Chao 28399451551SGavin Shan static int pnv_ioda1_init_m64(struct pnv_phb *phb) 28499451551SGavin Shan { 28599451551SGavin Shan struct resource *r; 28699451551SGavin Shan int index; 28799451551SGavin Shan 28899451551SGavin Shan /* 28999451551SGavin Shan * There are 16 M64 BARs, each of which has 8 segments. So 29099451551SGavin Shan * there are as many M64 segments as the maximum number of 29199451551SGavin Shan * PEs, which is 128. 29299451551SGavin Shan */ 29399451551SGavin Shan for (index = 0; index < PNV_IODA1_M64_NUM; index++) { 29499451551SGavin Shan unsigned long base, segsz = phb->ioda.m64_segsize; 29599451551SGavin Shan int64_t rc; 29699451551SGavin Shan 29799451551SGavin Shan base = phb->ioda.m64_base + 29899451551SGavin Shan index * PNV_IODA1_M64_SEGS * segsz; 29999451551SGavin Shan rc = opal_pci_set_phb_mem_window(phb->opal_id, 30099451551SGavin Shan OPAL_M64_WINDOW_TYPE, index, base, 0, 30199451551SGavin Shan PNV_IODA1_M64_SEGS * segsz); 30299451551SGavin Shan if (rc != OPAL_SUCCESS) { 3031f52f176SRussell Currey pr_warn(" Error %lld setting M64 PHB#%x-BAR#%d\n", 30499451551SGavin Shan rc, phb->hose->global_number, index); 30599451551SGavin Shan goto fail; 30699451551SGavin Shan } 30799451551SGavin Shan 30899451551SGavin Shan rc = opal_pci_phb_mmio_enable(phb->opal_id, 30999451551SGavin Shan OPAL_M64_WINDOW_TYPE, index, 31099451551SGavin Shan OPAL_ENABLE_M64_SPLIT); 31199451551SGavin Shan if (rc != OPAL_SUCCESS) { 3121f52f176SRussell Currey pr_warn(" Error %lld enabling M64 PHB#%x-BAR#%d\n", 31399451551SGavin Shan rc, phb->hose->global_number, index); 31499451551SGavin Shan goto fail; 31599451551SGavin Shan } 31699451551SGavin Shan } 31799451551SGavin Shan 31836963365SOliver O'Halloran for (index = 0; index < phb->ioda.total_pe_num; index++) { 31936963365SOliver O'Halloran int64_t rc; 32036963365SOliver O'Halloran 32136963365SOliver O'Halloran /* 32236963365SOliver O'Halloran * P7IOC supports M64DT, which helps mapping M64 segment 32336963365SOliver O'Halloran * to one particular PE#. However, PHB3 has fixed mapping 32436963365SOliver O'Halloran * between M64 segment and PE#. In order to have same logic 32536963365SOliver O'Halloran * for P7IOC and PHB3, we enforce fixed mapping between M64 32636963365SOliver O'Halloran * segment and PE# on P7IOC. 32736963365SOliver O'Halloran */ 32836963365SOliver O'Halloran rc = opal_pci_map_pe_mmio_window(phb->opal_id, 32936963365SOliver O'Halloran index, OPAL_M64_WINDOW_TYPE, 33036963365SOliver O'Halloran index / PNV_IODA1_M64_SEGS, 33136963365SOliver O'Halloran index % PNV_IODA1_M64_SEGS); 33236963365SOliver O'Halloran if (rc != OPAL_SUCCESS) { 33336963365SOliver O'Halloran pr_warn("%s: Error %lld mapping M64 for PHB#%x-PE#%x\n", 33436963365SOliver O'Halloran __func__, rc, phb->hose->global_number, 33536963365SOliver O'Halloran index); 33636963365SOliver O'Halloran goto fail; 33736963365SOliver O'Halloran } 33836963365SOliver O'Halloran } 33936963365SOliver O'Halloran 34099451551SGavin Shan /* 34163803c39SGavin Shan * Exclude the segments for reserved and root bus PE, which 34263803c39SGavin Shan * are first or last two PEs. 34399451551SGavin Shan */ 34499451551SGavin Shan r = &phb->hose->mem_resources[1]; 34599451551SGavin Shan if (phb->ioda.reserved_pe_idx == 0) 34663803c39SGavin Shan r->start += (2 * phb->ioda.m64_segsize); 34799451551SGavin Shan else if (phb->ioda.reserved_pe_idx == (phb->ioda.total_pe_num - 1)) 34863803c39SGavin Shan r->end -= (2 * phb->ioda.m64_segsize); 34999451551SGavin Shan else 3501f52f176SRussell Currey WARN(1, "Wrong reserved PE#%x on PHB#%x\n", 35199451551SGavin Shan phb->ioda.reserved_pe_idx, phb->hose->global_number); 35299451551SGavin Shan 35399451551SGavin Shan return 0; 35499451551SGavin Shan 35599451551SGavin Shan fail: 35699451551SGavin Shan for ( ; index >= 0; index--) 35799451551SGavin Shan opal_pci_phb_mmio_enable(phb->opal_id, 35899451551SGavin Shan OPAL_M64_WINDOW_TYPE, index, OPAL_DISABLE_M64); 35999451551SGavin Shan 36099451551SGavin Shan return -EIO; 36199451551SGavin Shan } 36299451551SGavin Shan 363c430670aSGavin Shan static void pnv_ioda_reserve_m64_pe(struct pci_bus *bus, 36496a2f92bSGavin Shan unsigned long *pe_bitmap, 36596a2f92bSGavin Shan bool all) 366262af557SGuo Chao { 367262af557SGuo Chao struct pci_dev *pdev; 36896a2f92bSGavin Shan 36996a2f92bSGavin Shan list_for_each_entry(pdev, &bus->devices, bus_list) { 370c430670aSGavin Shan pnv_ioda_reserve_dev_m64_pe(pdev, pe_bitmap); 37196a2f92bSGavin Shan 37296a2f92bSGavin Shan if (all && pdev->subordinate) 373c430670aSGavin Shan pnv_ioda_reserve_m64_pe(pdev->subordinate, 37496a2f92bSGavin Shan pe_bitmap, all); 37596a2f92bSGavin Shan } 37696a2f92bSGavin Shan } 37796a2f92bSGavin Shan 3781e916772SGavin Shan static struct pnv_ioda_pe *pnv_ioda_pick_m64_pe(struct pci_bus *bus, bool all) 379262af557SGuo Chao { 3805609ffddSOliver O'Halloran struct pnv_phb *phb = pci_bus_to_pnvhb(bus); 381262af557SGuo Chao struct pnv_ioda_pe *master_pe, *pe; 382262af557SGuo Chao unsigned long size, *pe_alloc; 38326ba248dSGavin Shan int i; 384262af557SGuo Chao 385262af557SGuo Chao /* Root bus shouldn't use M64 */ 386262af557SGuo Chao if (pci_is_root_bus(bus)) 3871e916772SGavin Shan return NULL; 388262af557SGuo Chao 389262af557SGuo Chao /* Allocate bitmap */ 390b7115316SChristophe Leroy size = ALIGN(phb->ioda.total_pe_num / 8, sizeof(unsigned long)); 391262af557SGuo Chao pe_alloc = kzalloc(size, GFP_KERNEL); 392262af557SGuo Chao if (!pe_alloc) { 393262af557SGuo Chao pr_warn("%s: Out of memory !\n", 394262af557SGuo Chao __func__); 3951e916772SGavin Shan return NULL; 396262af557SGuo Chao } 397262af557SGuo Chao 39826ba248dSGavin Shan /* Figure out reserved PE numbers by the PE */ 399c430670aSGavin Shan pnv_ioda_reserve_m64_pe(bus, pe_alloc, all); 400262af557SGuo Chao 401262af557SGuo Chao /* 402262af557SGuo Chao * the current bus might not own M64 window and that's all 403262af557SGuo Chao * contributed by its child buses. For the case, we needn't 404262af557SGuo Chao * pick M64 dependent PE#. 405262af557SGuo Chao */ 40692b8f137SGavin Shan if (bitmap_empty(pe_alloc, phb->ioda.total_pe_num)) { 407262af557SGuo Chao kfree(pe_alloc); 4081e916772SGavin Shan return NULL; 409262af557SGuo Chao } 410262af557SGuo Chao 411262af557SGuo Chao /* 412262af557SGuo Chao * Figure out the master PE and put all slave PEs to master 413262af557SGuo Chao * PE's list to form compound PE. 414262af557SGuo Chao */ 415262af557SGuo Chao master_pe = NULL; 416262af557SGuo Chao i = -1; 41792b8f137SGavin Shan while ((i = find_next_bit(pe_alloc, phb->ioda.total_pe_num, i + 1)) < 41892b8f137SGavin Shan phb->ioda.total_pe_num) { 419262af557SGuo Chao pe = &phb->ioda.pe_array[i]; 420262af557SGuo Chao 42193289d8cSGavin Shan phb->ioda.m64_segmap[pe->pe_number] = pe->pe_number; 422262af557SGuo Chao if (!master_pe) { 423262af557SGuo Chao pe->flags |= PNV_IODA_PE_MASTER; 424262af557SGuo Chao INIT_LIST_HEAD(&pe->slaves); 425262af557SGuo Chao master_pe = pe; 426262af557SGuo Chao } else { 427262af557SGuo Chao pe->flags |= PNV_IODA_PE_SLAVE; 428262af557SGuo Chao pe->master = master_pe; 429262af557SGuo Chao list_add_tail(&pe->list, &master_pe->slaves); 430262af557SGuo Chao } 431262af557SGuo Chao } 432262af557SGuo Chao 433262af557SGuo Chao kfree(pe_alloc); 4341e916772SGavin Shan return master_pe; 435262af557SGuo Chao } 436262af557SGuo Chao 437262af557SGuo Chao static void __init pnv_ioda_parse_m64_window(struct pnv_phb *phb) 438262af557SGuo Chao { 439262af557SGuo Chao struct pci_controller *hose = phb->hose; 440262af557SGuo Chao struct device_node *dn = hose->dn; 441262af557SGuo Chao struct resource *res; 442a1339fafSBenjamin Herrenschmidt u32 m64_range[2], i; 4430e7736c6SGavin Shan const __be32 *r; 444262af557SGuo Chao u64 pci_addr; 445262af557SGuo Chao 44699451551SGavin Shan if (phb->type != PNV_PHB_IODA1 && phb->type != PNV_PHB_IODA2) { 4471665c4a8SGavin Shan pr_info(" Not support M64 window\n"); 4481665c4a8SGavin Shan return; 4491665c4a8SGavin Shan } 4501665c4a8SGavin Shan 451e4d54f71SStewart Smith if (!firmware_has_feature(FW_FEATURE_OPAL)) { 452262af557SGuo Chao pr_info(" Firmware too old to support M64 window\n"); 453262af557SGuo Chao return; 454262af557SGuo Chao } 455262af557SGuo Chao 456262af557SGuo Chao r = of_get_property(dn, "ibm,opal-m64-window", NULL); 457262af557SGuo Chao if (!r) { 458b7c670d6SRob Herring pr_info(" No <ibm,opal-m64-window> on %pOF\n", 459b7c670d6SRob Herring dn); 460262af557SGuo Chao return; 461262af557SGuo Chao } 462262af557SGuo Chao 463a1339fafSBenjamin Herrenschmidt /* 464a1339fafSBenjamin Herrenschmidt * Find the available M64 BAR range and pickup the last one for 465a1339fafSBenjamin Herrenschmidt * covering the whole 64-bits space. We support only one range. 466a1339fafSBenjamin Herrenschmidt */ 467a1339fafSBenjamin Herrenschmidt if (of_property_read_u32_array(dn, "ibm,opal-available-m64-ranges", 468a1339fafSBenjamin Herrenschmidt m64_range, 2)) { 469a1339fafSBenjamin Herrenschmidt /* In absence of the property, assume 0..15 */ 470a1339fafSBenjamin Herrenschmidt m64_range[0] = 0; 471a1339fafSBenjamin Herrenschmidt m64_range[1] = 16; 472a1339fafSBenjamin Herrenschmidt } 473a1339fafSBenjamin Herrenschmidt /* We only support 64 bits in our allocator */ 474a1339fafSBenjamin Herrenschmidt if (m64_range[1] > 63) { 475a1339fafSBenjamin Herrenschmidt pr_warn("%s: Limiting M64 range to 63 (from %d) on PHB#%x\n", 476a1339fafSBenjamin Herrenschmidt __func__, m64_range[1], phb->hose->global_number); 477a1339fafSBenjamin Herrenschmidt m64_range[1] = 63; 478a1339fafSBenjamin Herrenschmidt } 479a1339fafSBenjamin Herrenschmidt /* Empty range, no m64 */ 480a1339fafSBenjamin Herrenschmidt if (m64_range[1] <= m64_range[0]) { 481a1339fafSBenjamin Herrenschmidt pr_warn("%s: M64 empty, disabling M64 usage on PHB#%x\n", 482a1339fafSBenjamin Herrenschmidt __func__, phb->hose->global_number); 483a1339fafSBenjamin Herrenschmidt return; 484a1339fafSBenjamin Herrenschmidt } 485a1339fafSBenjamin Herrenschmidt 486a1339fafSBenjamin Herrenschmidt /* Configure M64 informations */ 487262af557SGuo Chao res = &hose->mem_resources[1]; 488e80c4e7cSGavin Shan res->name = dn->full_name; 489262af557SGuo Chao res->start = of_translate_address(dn, r + 2); 490262af557SGuo Chao res->end = res->start + of_read_number(r + 4, 2) - 1; 491262af557SGuo Chao res->flags = (IORESOURCE_MEM | IORESOURCE_MEM_64 | IORESOURCE_PREFETCH); 492262af557SGuo Chao pci_addr = of_read_number(r, 2); 493262af557SGuo Chao hose->mem_offset[1] = res->start - pci_addr; 494262af557SGuo Chao 495262af557SGuo Chao phb->ioda.m64_size = resource_size(res); 49692b8f137SGavin Shan phb->ioda.m64_segsize = phb->ioda.m64_size / phb->ioda.total_pe_num; 497262af557SGuo Chao phb->ioda.m64_base = pci_addr; 498262af557SGuo Chao 499a1339fafSBenjamin Herrenschmidt /* This lines up nicely with the display from processing OF ranges */ 500a1339fafSBenjamin Herrenschmidt pr_info(" MEM 0x%016llx..0x%016llx -> 0x%016llx (M64 #%d..%d)\n", 501a1339fafSBenjamin Herrenschmidt res->start, res->end, pci_addr, m64_range[0], 502a1339fafSBenjamin Herrenschmidt m64_range[0] + m64_range[1] - 1); 503a1339fafSBenjamin Herrenschmidt 504a1339fafSBenjamin Herrenschmidt /* Mark all M64 used up by default */ 505a1339fafSBenjamin Herrenschmidt phb->ioda.m64_bar_alloc = (unsigned long)-1; 506e9863e68SWei Yang 507262af557SGuo Chao /* Use last M64 BAR to cover M64 window */ 508a1339fafSBenjamin Herrenschmidt m64_range[1]--; 509a1339fafSBenjamin Herrenschmidt phb->ioda.m64_bar_idx = m64_range[0] + m64_range[1]; 510a1339fafSBenjamin Herrenschmidt 511a1339fafSBenjamin Herrenschmidt pr_info(" Using M64 #%d as default window\n", phb->ioda.m64_bar_idx); 512a1339fafSBenjamin Herrenschmidt 513a1339fafSBenjamin Herrenschmidt /* Mark remaining ones free */ 514a1339fafSBenjamin Herrenschmidt for (i = m64_range[0]; i < m64_range[1]; i++) 515a1339fafSBenjamin Herrenschmidt clear_bit(i, &phb->ioda.m64_bar_alloc); 516a1339fafSBenjamin Herrenschmidt 517a1339fafSBenjamin Herrenschmidt /* 518a1339fafSBenjamin Herrenschmidt * Setup init functions for M64 based on IODA version, IODA3 uses 519a1339fafSBenjamin Herrenschmidt * the IODA2 code. 520a1339fafSBenjamin Herrenschmidt */ 52199451551SGavin Shan if (phb->type == PNV_PHB_IODA1) 52299451551SGavin Shan phb->init_m64 = pnv_ioda1_init_m64; 52399451551SGavin Shan else 524262af557SGuo Chao phb->init_m64 = pnv_ioda2_init_m64; 525262af557SGuo Chao } 526262af557SGuo Chao 52749dec922SGavin Shan static void pnv_ioda_freeze_pe(struct pnv_phb *phb, int pe_no) 52849dec922SGavin Shan { 52949dec922SGavin Shan struct pnv_ioda_pe *pe = &phb->ioda.pe_array[pe_no]; 53049dec922SGavin Shan struct pnv_ioda_pe *slave; 53149dec922SGavin Shan s64 rc; 53249dec922SGavin Shan 53349dec922SGavin Shan /* Fetch master PE */ 53449dec922SGavin Shan if (pe->flags & PNV_IODA_PE_SLAVE) { 53549dec922SGavin Shan pe = pe->master; 536ec8e4e9dSGavin Shan if (WARN_ON(!pe || !(pe->flags & PNV_IODA_PE_MASTER))) 537ec8e4e9dSGavin Shan return; 538ec8e4e9dSGavin Shan 53949dec922SGavin Shan pe_no = pe->pe_number; 54049dec922SGavin Shan } 54149dec922SGavin Shan 54249dec922SGavin Shan /* Freeze master PE */ 54349dec922SGavin Shan rc = opal_pci_eeh_freeze_set(phb->opal_id, 54449dec922SGavin Shan pe_no, 54549dec922SGavin Shan OPAL_EEH_ACTION_SET_FREEZE_ALL); 54649dec922SGavin Shan if (rc != OPAL_SUCCESS) { 54749dec922SGavin Shan pr_warn("%s: Failure %lld freezing PHB#%x-PE#%x\n", 54849dec922SGavin Shan __func__, rc, phb->hose->global_number, pe_no); 54949dec922SGavin Shan return; 55049dec922SGavin Shan } 55149dec922SGavin Shan 55249dec922SGavin Shan /* Freeze slave PEs */ 55349dec922SGavin Shan if (!(pe->flags & PNV_IODA_PE_MASTER)) 55449dec922SGavin Shan return; 55549dec922SGavin Shan 55649dec922SGavin Shan list_for_each_entry(slave, &pe->slaves, list) { 55749dec922SGavin Shan rc = opal_pci_eeh_freeze_set(phb->opal_id, 55849dec922SGavin Shan slave->pe_number, 55949dec922SGavin Shan OPAL_EEH_ACTION_SET_FREEZE_ALL); 56049dec922SGavin Shan if (rc != OPAL_SUCCESS) 56149dec922SGavin Shan pr_warn("%s: Failure %lld freezing PHB#%x-PE#%x\n", 56249dec922SGavin Shan __func__, rc, phb->hose->global_number, 56349dec922SGavin Shan slave->pe_number); 56449dec922SGavin Shan } 56549dec922SGavin Shan } 56649dec922SGavin Shan 567e51df2c1SAnton Blanchard static int pnv_ioda_unfreeze_pe(struct pnv_phb *phb, int pe_no, int opt) 56849dec922SGavin Shan { 56949dec922SGavin Shan struct pnv_ioda_pe *pe, *slave; 57049dec922SGavin Shan s64 rc; 57149dec922SGavin Shan 57249dec922SGavin Shan /* Find master PE */ 57349dec922SGavin Shan pe = &phb->ioda.pe_array[pe_no]; 57449dec922SGavin Shan if (pe->flags & PNV_IODA_PE_SLAVE) { 57549dec922SGavin Shan pe = pe->master; 57649dec922SGavin Shan WARN_ON(!pe || !(pe->flags & PNV_IODA_PE_MASTER)); 57749dec922SGavin Shan pe_no = pe->pe_number; 57849dec922SGavin Shan } 57949dec922SGavin Shan 58049dec922SGavin Shan /* Clear frozen state for master PE */ 58149dec922SGavin Shan rc = opal_pci_eeh_freeze_clear(phb->opal_id, pe_no, opt); 58249dec922SGavin Shan if (rc != OPAL_SUCCESS) { 58349dec922SGavin Shan pr_warn("%s: Failure %lld clear %d on PHB#%x-PE#%x\n", 58449dec922SGavin Shan __func__, rc, opt, phb->hose->global_number, pe_no); 58549dec922SGavin Shan return -EIO; 58649dec922SGavin Shan } 58749dec922SGavin Shan 58849dec922SGavin Shan if (!(pe->flags & PNV_IODA_PE_MASTER)) 58949dec922SGavin Shan return 0; 59049dec922SGavin Shan 59149dec922SGavin Shan /* Clear frozen state for slave PEs */ 59249dec922SGavin Shan list_for_each_entry(slave, &pe->slaves, list) { 59349dec922SGavin Shan rc = opal_pci_eeh_freeze_clear(phb->opal_id, 59449dec922SGavin Shan slave->pe_number, 59549dec922SGavin Shan opt); 59649dec922SGavin Shan if (rc != OPAL_SUCCESS) { 59749dec922SGavin Shan pr_warn("%s: Failure %lld clear %d on PHB#%x-PE#%x\n", 59849dec922SGavin Shan __func__, rc, opt, phb->hose->global_number, 59949dec922SGavin Shan slave->pe_number); 60049dec922SGavin Shan return -EIO; 60149dec922SGavin Shan } 60249dec922SGavin Shan } 60349dec922SGavin Shan 60449dec922SGavin Shan return 0; 60549dec922SGavin Shan } 60649dec922SGavin Shan 60749dec922SGavin Shan static int pnv_ioda_get_pe_state(struct pnv_phb *phb, int pe_no) 60849dec922SGavin Shan { 60949dec922SGavin Shan struct pnv_ioda_pe *slave, *pe; 610c2057701SAlexey Kardashevskiy u8 fstate = 0, state; 611c2057701SAlexey Kardashevskiy __be16 pcierr = 0; 61249dec922SGavin Shan s64 rc; 61349dec922SGavin Shan 61449dec922SGavin Shan /* Sanity check on PE number */ 61592b8f137SGavin Shan if (pe_no < 0 || pe_no >= phb->ioda.total_pe_num) 61649dec922SGavin Shan return OPAL_EEH_STOPPED_PERM_UNAVAIL; 61749dec922SGavin Shan 61849dec922SGavin Shan /* 61949dec922SGavin Shan * Fetch the master PE and the PE instance might be 62049dec922SGavin Shan * not initialized yet. 62149dec922SGavin Shan */ 62249dec922SGavin Shan pe = &phb->ioda.pe_array[pe_no]; 62349dec922SGavin Shan if (pe->flags & PNV_IODA_PE_SLAVE) { 62449dec922SGavin Shan pe = pe->master; 62549dec922SGavin Shan WARN_ON(!pe || !(pe->flags & PNV_IODA_PE_MASTER)); 62649dec922SGavin Shan pe_no = pe->pe_number; 62749dec922SGavin Shan } 62849dec922SGavin Shan 62949dec922SGavin Shan /* Check the master PE */ 63049dec922SGavin Shan rc = opal_pci_eeh_freeze_status(phb->opal_id, pe_no, 63149dec922SGavin Shan &state, &pcierr, NULL); 63249dec922SGavin Shan if (rc != OPAL_SUCCESS) { 63349dec922SGavin Shan pr_warn("%s: Failure %lld getting " 63449dec922SGavin Shan "PHB#%x-PE#%x state\n", 63549dec922SGavin Shan __func__, rc, 63649dec922SGavin Shan phb->hose->global_number, pe_no); 63749dec922SGavin Shan return OPAL_EEH_STOPPED_TEMP_UNAVAIL; 63849dec922SGavin Shan } 63949dec922SGavin Shan 64049dec922SGavin Shan /* Check the slave PE */ 64149dec922SGavin Shan if (!(pe->flags & PNV_IODA_PE_MASTER)) 64249dec922SGavin Shan return state; 64349dec922SGavin Shan 64449dec922SGavin Shan list_for_each_entry(slave, &pe->slaves, list) { 64549dec922SGavin Shan rc = opal_pci_eeh_freeze_status(phb->opal_id, 64649dec922SGavin Shan slave->pe_number, 64749dec922SGavin Shan &fstate, 64849dec922SGavin Shan &pcierr, 64949dec922SGavin Shan NULL); 65049dec922SGavin Shan if (rc != OPAL_SUCCESS) { 65149dec922SGavin Shan pr_warn("%s: Failure %lld getting " 65249dec922SGavin Shan "PHB#%x-PE#%x state\n", 65349dec922SGavin Shan __func__, rc, 65449dec922SGavin Shan phb->hose->global_number, slave->pe_number); 65549dec922SGavin Shan return OPAL_EEH_STOPPED_TEMP_UNAVAIL; 65649dec922SGavin Shan } 65749dec922SGavin Shan 65849dec922SGavin Shan /* 65949dec922SGavin Shan * Override the result based on the ascending 66049dec922SGavin Shan * priority. 66149dec922SGavin Shan */ 66249dec922SGavin Shan if (fstate > state) 66349dec922SGavin Shan state = fstate; 66449dec922SGavin Shan } 66549dec922SGavin Shan 66649dec922SGavin Shan return state; 66749dec922SGavin Shan } 66849dec922SGavin Shan 669a8d7d5fcSOliver O'Halloran struct pnv_ioda_pe *pnv_pci_bdfn_to_pe(struct pnv_phb *phb, u16 bdfn) 670a8d7d5fcSOliver O'Halloran { 671a8d7d5fcSOliver O'Halloran int pe_number = phb->ioda.pe_rmap[bdfn]; 672a8d7d5fcSOliver O'Halloran 673a8d7d5fcSOliver O'Halloran if (pe_number == IODA_INVALID_PE) 674a8d7d5fcSOliver O'Halloran return NULL; 675a8d7d5fcSOliver O'Halloran 676a8d7d5fcSOliver O'Halloran return &phb->ioda.pe_array[pe_number]; 677a8d7d5fcSOliver O'Halloran } 678a8d7d5fcSOliver O'Halloran 679f456834aSIan Munsie struct pnv_ioda_pe *pnv_ioda_get_pe(struct pci_dev *dev) 680184cd4a3SBenjamin Herrenschmidt { 6815609ffddSOliver O'Halloran struct pnv_phb *phb = pci_bus_to_pnvhb(dev->bus); 682b72c1f65SBenjamin Herrenschmidt struct pci_dn *pdn = pci_get_pdn(dev); 683184cd4a3SBenjamin Herrenschmidt 684184cd4a3SBenjamin Herrenschmidt if (!pdn) 685184cd4a3SBenjamin Herrenschmidt return NULL; 686184cd4a3SBenjamin Herrenschmidt if (pdn->pe_number == IODA_INVALID_PE) 687184cd4a3SBenjamin Herrenschmidt return NULL; 688184cd4a3SBenjamin Herrenschmidt return &phb->ioda.pe_array[pdn->pe_number]; 689184cd4a3SBenjamin Herrenschmidt } 690184cd4a3SBenjamin Herrenschmidt 691b131a842SGavin Shan static int pnv_ioda_set_one_peltv(struct pnv_phb *phb, 692b131a842SGavin Shan struct pnv_ioda_pe *parent, 693b131a842SGavin Shan struct pnv_ioda_pe *child, 694b131a842SGavin Shan bool is_add) 695b131a842SGavin Shan { 696b131a842SGavin Shan const char *desc = is_add ? "adding" : "removing"; 697b131a842SGavin Shan uint8_t op = is_add ? OPAL_ADD_PE_TO_DOMAIN : 698b131a842SGavin Shan OPAL_REMOVE_PE_FROM_DOMAIN; 699b131a842SGavin Shan struct pnv_ioda_pe *slave; 700b131a842SGavin Shan long rc; 701b131a842SGavin Shan 702b131a842SGavin Shan /* Parent PE affects child PE */ 703b131a842SGavin Shan rc = opal_pci_set_peltv(phb->opal_id, parent->pe_number, 704b131a842SGavin Shan child->pe_number, op); 705b131a842SGavin Shan if (rc != OPAL_SUCCESS) { 706b131a842SGavin Shan pe_warn(child, "OPAL error %ld %s to parent PELTV\n", 707b131a842SGavin Shan rc, desc); 708b131a842SGavin Shan return -ENXIO; 709b131a842SGavin Shan } 710b131a842SGavin Shan 711b131a842SGavin Shan if (!(child->flags & PNV_IODA_PE_MASTER)) 712b131a842SGavin Shan return 0; 713b131a842SGavin Shan 714b131a842SGavin Shan /* Compound case: parent PE affects slave PEs */ 715b131a842SGavin Shan list_for_each_entry(slave, &child->slaves, list) { 716b131a842SGavin Shan rc = opal_pci_set_peltv(phb->opal_id, parent->pe_number, 717b131a842SGavin Shan slave->pe_number, op); 718b131a842SGavin Shan if (rc != OPAL_SUCCESS) { 719b131a842SGavin Shan pe_warn(slave, "OPAL error %ld %s to parent PELTV\n", 720b131a842SGavin Shan rc, desc); 721b131a842SGavin Shan return -ENXIO; 722b131a842SGavin Shan } 723b131a842SGavin Shan } 724b131a842SGavin Shan 725b131a842SGavin Shan return 0; 726b131a842SGavin Shan } 727b131a842SGavin Shan 728b131a842SGavin Shan static int pnv_ioda_set_peltv(struct pnv_phb *phb, 729b131a842SGavin Shan struct pnv_ioda_pe *pe, 730b131a842SGavin Shan bool is_add) 731b131a842SGavin Shan { 732b131a842SGavin Shan struct pnv_ioda_pe *slave; 733781a868fSWei Yang struct pci_dev *pdev = NULL; 734b131a842SGavin Shan int ret; 735b131a842SGavin Shan 736b131a842SGavin Shan /* 737b131a842SGavin Shan * Clear PE frozen state. If it's master PE, we need 738b131a842SGavin Shan * clear slave PE frozen state as well. 739b131a842SGavin Shan */ 740b131a842SGavin Shan if (is_add) { 741b131a842SGavin Shan opal_pci_eeh_freeze_clear(phb->opal_id, pe->pe_number, 742b131a842SGavin Shan OPAL_EEH_ACTION_CLEAR_FREEZE_ALL); 743b131a842SGavin Shan if (pe->flags & PNV_IODA_PE_MASTER) { 744b131a842SGavin Shan list_for_each_entry(slave, &pe->slaves, list) 745b131a842SGavin Shan opal_pci_eeh_freeze_clear(phb->opal_id, 746b131a842SGavin Shan slave->pe_number, 747b131a842SGavin Shan OPAL_EEH_ACTION_CLEAR_FREEZE_ALL); 748b131a842SGavin Shan } 749b131a842SGavin Shan } 750b131a842SGavin Shan 751b131a842SGavin Shan /* 752b131a842SGavin Shan * Associate PE in PELT. We need add the PE into the 753b131a842SGavin Shan * corresponding PELT-V as well. Otherwise, the error 754b131a842SGavin Shan * originated from the PE might contribute to other 755b131a842SGavin Shan * PEs. 756b131a842SGavin Shan */ 757b131a842SGavin Shan ret = pnv_ioda_set_one_peltv(phb, pe, pe, is_add); 758b131a842SGavin Shan if (ret) 759b131a842SGavin Shan return ret; 760b131a842SGavin Shan 761b131a842SGavin Shan /* For compound PEs, any one affects all of them */ 762b131a842SGavin Shan if (pe->flags & PNV_IODA_PE_MASTER) { 763b131a842SGavin Shan list_for_each_entry(slave, &pe->slaves, list) { 764b131a842SGavin Shan ret = pnv_ioda_set_one_peltv(phb, slave, pe, is_add); 765b131a842SGavin Shan if (ret) 766b131a842SGavin Shan return ret; 767b131a842SGavin Shan } 768b131a842SGavin Shan } 769b131a842SGavin Shan 770b131a842SGavin Shan if (pe->flags & (PNV_IODA_PE_BUS_ALL | PNV_IODA_PE_BUS)) 771b131a842SGavin Shan pdev = pe->pbus->self; 772781a868fSWei Yang else if (pe->flags & PNV_IODA_PE_DEV) 773b131a842SGavin Shan pdev = pe->pdev->bus->self; 774781a868fSWei Yang #ifdef CONFIG_PCI_IOV 775781a868fSWei Yang else if (pe->flags & PNV_IODA_PE_VF) 776283e2d8aSGavin Shan pdev = pe->parent_dev; 777781a868fSWei Yang #endif /* CONFIG_PCI_IOV */ 778b131a842SGavin Shan while (pdev) { 779b131a842SGavin Shan struct pci_dn *pdn = pci_get_pdn(pdev); 780b131a842SGavin Shan struct pnv_ioda_pe *parent; 781b131a842SGavin Shan 782b131a842SGavin Shan if (pdn && pdn->pe_number != IODA_INVALID_PE) { 783b131a842SGavin Shan parent = &phb->ioda.pe_array[pdn->pe_number]; 784b131a842SGavin Shan ret = pnv_ioda_set_one_peltv(phb, parent, pe, is_add); 785b131a842SGavin Shan if (ret) 786b131a842SGavin Shan return ret; 787b131a842SGavin Shan } 788b131a842SGavin Shan 789b131a842SGavin Shan pdev = pdev->bus->self; 790b131a842SGavin Shan } 791b131a842SGavin Shan 792b131a842SGavin Shan return 0; 793b131a842SGavin Shan } 794b131a842SGavin Shan 795f724385fSFrederic Barrat static void pnv_ioda_unset_peltv(struct pnv_phb *phb, 796f724385fSFrederic Barrat struct pnv_ioda_pe *pe, 797f724385fSFrederic Barrat struct pci_dev *parent) 798f724385fSFrederic Barrat { 799f724385fSFrederic Barrat int64_t rc; 800f724385fSFrederic Barrat 801f724385fSFrederic Barrat while (parent) { 802f724385fSFrederic Barrat struct pci_dn *pdn = pci_get_pdn(parent); 803f724385fSFrederic Barrat 804f724385fSFrederic Barrat if (pdn && pdn->pe_number != IODA_INVALID_PE) { 805f724385fSFrederic Barrat rc = opal_pci_set_peltv(phb->opal_id, pdn->pe_number, 806f724385fSFrederic Barrat pe->pe_number, 807f724385fSFrederic Barrat OPAL_REMOVE_PE_FROM_DOMAIN); 808f724385fSFrederic Barrat /* XXX What to do in case of error ? */ 809f724385fSFrederic Barrat } 810f724385fSFrederic Barrat parent = parent->bus->self; 811f724385fSFrederic Barrat } 812f724385fSFrederic Barrat 813f724385fSFrederic Barrat opal_pci_eeh_freeze_clear(phb->opal_id, pe->pe_number, 814f724385fSFrederic Barrat OPAL_EEH_ACTION_CLEAR_FREEZE_ALL); 815f724385fSFrederic Barrat 816f724385fSFrederic Barrat /* Disassociate PE in PELT */ 817f724385fSFrederic Barrat rc = opal_pci_set_peltv(phb->opal_id, pe->pe_number, 818f724385fSFrederic Barrat pe->pe_number, OPAL_REMOVE_PE_FROM_DOMAIN); 819f724385fSFrederic Barrat if (rc) 820f724385fSFrederic Barrat pe_warn(pe, "OPAL error %lld remove self from PELTV\n", rc); 821f724385fSFrederic Barrat } 822f724385fSFrederic Barrat 82337b59ef0SOliver O'Halloran int pnv_ioda_deconfigure_pe(struct pnv_phb *phb, struct pnv_ioda_pe *pe) 824781a868fSWei Yang { 825781a868fSWei Yang struct pci_dev *parent; 826781a868fSWei Yang uint8_t bcomp, dcomp, fcomp; 827781a868fSWei Yang int64_t rc; 828781a868fSWei Yang long rid_end, rid; 829781a868fSWei Yang 830781a868fSWei Yang /* Currently, we just deconfigure VF PE. Bus PE will always there.*/ 831781a868fSWei Yang if (pe->pbus) { 832781a868fSWei Yang int count; 833781a868fSWei Yang 834781a868fSWei Yang dcomp = OPAL_IGNORE_RID_DEVICE_NUMBER; 835781a868fSWei Yang fcomp = OPAL_IGNORE_RID_FUNCTION_NUMBER; 836781a868fSWei Yang parent = pe->pbus->self; 837781a868fSWei Yang if (pe->flags & PNV_IODA_PE_BUS_ALL) 838552aa086SJulia Lawall count = resource_size(&pe->pbus->busn_res); 839781a868fSWei Yang else 840781a868fSWei Yang count = 1; 841781a868fSWei Yang 842781a868fSWei Yang switch(count) { 843781a868fSWei Yang case 1: bcomp = OpalPciBusAll; break; 844781a868fSWei Yang case 2: bcomp = OpalPciBus7Bits; break; 845781a868fSWei Yang case 4: bcomp = OpalPciBus6Bits; break; 846781a868fSWei Yang case 8: bcomp = OpalPciBus5Bits; break; 847781a868fSWei Yang case 16: bcomp = OpalPciBus4Bits; break; 848781a868fSWei Yang case 32: bcomp = OpalPciBus3Bits; break; 849781a868fSWei Yang default: 850781a868fSWei Yang dev_err(&pe->pbus->dev, "Number of subordinate buses %d unsupported\n", 851781a868fSWei Yang count); 852781a868fSWei Yang /* Do an exact match only */ 853781a868fSWei Yang bcomp = OpalPciBusAll; 854781a868fSWei Yang } 855781a868fSWei Yang rid_end = pe->rid + (count << 8); 856781a868fSWei Yang } else { 85793e01a50SGavin Shan #ifdef CONFIG_PCI_IOV 858781a868fSWei Yang if (pe->flags & PNV_IODA_PE_VF) 859781a868fSWei Yang parent = pe->parent_dev; 860781a868fSWei Yang else 86193e01a50SGavin Shan #endif 862781a868fSWei Yang parent = pe->pdev->bus->self; 863781a868fSWei Yang bcomp = OpalPciBusAll; 864781a868fSWei Yang dcomp = OPAL_COMPARE_RID_DEVICE_NUMBER; 865781a868fSWei Yang fcomp = OPAL_COMPARE_RID_FUNCTION_NUMBER; 866781a868fSWei Yang rid_end = pe->rid + 1; 867781a868fSWei Yang } 868781a868fSWei Yang 869781a868fSWei Yang /* Clear the reverse map */ 870781a868fSWei Yang for (rid = pe->rid; rid < rid_end; rid++) 871c127562aSGavin Shan phb->ioda.pe_rmap[rid] = IODA_INVALID_PE; 872781a868fSWei Yang 873f724385fSFrederic Barrat /* 874f724385fSFrederic Barrat * Release from all parents PELT-V. NPUs don't have a PELTV 875f724385fSFrederic Barrat * table 876f724385fSFrederic Barrat */ 877562d1e20SChristoph Hellwig if (phb->type != PNV_PHB_NPU_OCAPI) 878f724385fSFrederic Barrat pnv_ioda_unset_peltv(phb, pe, parent); 879781a868fSWei Yang 880781a868fSWei Yang rc = opal_pci_set_pe(phb->opal_id, pe->pe_number, pe->rid, 881781a868fSWei Yang bcomp, dcomp, fcomp, OPAL_UNMAP_PE); 882781a868fSWei Yang if (rc) 8831e496391SJoe Perches pe_err(pe, "OPAL error %lld trying to setup PELT table\n", rc); 884781a868fSWei Yang 885781a868fSWei Yang pe->pbus = NULL; 886781a868fSWei Yang pe->pdev = NULL; 88793e01a50SGavin Shan #ifdef CONFIG_PCI_IOV 888781a868fSWei Yang pe->parent_dev = NULL; 88993e01a50SGavin Shan #endif 890781a868fSWei Yang 891781a868fSWei Yang return 0; 892781a868fSWei Yang } 893781a868fSWei Yang 89437b59ef0SOliver O'Halloran int pnv_ioda_configure_pe(struct pnv_phb *phb, struct pnv_ioda_pe *pe) 895184cd4a3SBenjamin Herrenschmidt { 896184cd4a3SBenjamin Herrenschmidt uint8_t bcomp, dcomp, fcomp; 897184cd4a3SBenjamin Herrenschmidt long rc, rid_end, rid; 898184cd4a3SBenjamin Herrenschmidt 899184cd4a3SBenjamin Herrenschmidt /* Bus validation ? */ 900184cd4a3SBenjamin Herrenschmidt if (pe->pbus) { 901184cd4a3SBenjamin Herrenschmidt int count; 902184cd4a3SBenjamin Herrenschmidt 903184cd4a3SBenjamin Herrenschmidt dcomp = OPAL_IGNORE_RID_DEVICE_NUMBER; 904184cd4a3SBenjamin Herrenschmidt fcomp = OPAL_IGNORE_RID_FUNCTION_NUMBER; 905fb446ad0SGavin Shan if (pe->flags & PNV_IODA_PE_BUS_ALL) 906552aa086SJulia Lawall count = resource_size(&pe->pbus->busn_res); 907fb446ad0SGavin Shan else 908fb446ad0SGavin Shan count = 1; 909fb446ad0SGavin Shan 910184cd4a3SBenjamin Herrenschmidt switch(count) { 911184cd4a3SBenjamin Herrenschmidt case 1: bcomp = OpalPciBusAll; break; 912184cd4a3SBenjamin Herrenschmidt case 2: bcomp = OpalPciBus7Bits; break; 913184cd4a3SBenjamin Herrenschmidt case 4: bcomp = OpalPciBus6Bits; break; 914184cd4a3SBenjamin Herrenschmidt case 8: bcomp = OpalPciBus5Bits; break; 915184cd4a3SBenjamin Herrenschmidt case 16: bcomp = OpalPciBus4Bits; break; 916184cd4a3SBenjamin Herrenschmidt case 32: bcomp = OpalPciBus3Bits; break; 917184cd4a3SBenjamin Herrenschmidt default: 918781a868fSWei Yang dev_err(&pe->pbus->dev, "Number of subordinate buses %d unsupported\n", 919781a868fSWei Yang count); 920184cd4a3SBenjamin Herrenschmidt /* Do an exact match only */ 921184cd4a3SBenjamin Herrenschmidt bcomp = OpalPciBusAll; 922184cd4a3SBenjamin Herrenschmidt } 923184cd4a3SBenjamin Herrenschmidt rid_end = pe->rid + (count << 8); 924184cd4a3SBenjamin Herrenschmidt } else { 925184cd4a3SBenjamin Herrenschmidt bcomp = OpalPciBusAll; 926184cd4a3SBenjamin Herrenschmidt dcomp = OPAL_COMPARE_RID_DEVICE_NUMBER; 927184cd4a3SBenjamin Herrenschmidt fcomp = OPAL_COMPARE_RID_FUNCTION_NUMBER; 928184cd4a3SBenjamin Herrenschmidt rid_end = pe->rid + 1; 929184cd4a3SBenjamin Herrenschmidt } 930184cd4a3SBenjamin Herrenschmidt 931631ad691SGavin Shan /* 932631ad691SGavin Shan * Associate PE in PELT. We need add the PE into the 933631ad691SGavin Shan * corresponding PELT-V as well. Otherwise, the error 934631ad691SGavin Shan * originated from the PE might contribute to other 935631ad691SGavin Shan * PEs. 936631ad691SGavin Shan */ 937184cd4a3SBenjamin Herrenschmidt rc = opal_pci_set_pe(phb->opal_id, pe->pe_number, pe->rid, 938184cd4a3SBenjamin Herrenschmidt bcomp, dcomp, fcomp, OPAL_MAP_PE); 939184cd4a3SBenjamin Herrenschmidt if (rc) { 940184cd4a3SBenjamin Herrenschmidt pe_err(pe, "OPAL error %ld trying to setup PELT table\n", rc); 941184cd4a3SBenjamin Herrenschmidt return -ENXIO; 942184cd4a3SBenjamin Herrenschmidt } 943631ad691SGavin Shan 9445d2aa710SAlistair Popple /* 9455d2aa710SAlistair Popple * Configure PELTV. NPUs don't have a PELTV table so skip 9465d2aa710SAlistair Popple * configuration on them. 9475d2aa710SAlistair Popple */ 948562d1e20SChristoph Hellwig if (phb->type != PNV_PHB_NPU_OCAPI) 949b131a842SGavin Shan pnv_ioda_set_peltv(phb, pe, true); 950184cd4a3SBenjamin Herrenschmidt 951184cd4a3SBenjamin Herrenschmidt /* Setup reverse map */ 952184cd4a3SBenjamin Herrenschmidt for (rid = pe->rid; rid < rid_end; rid++) 953184cd4a3SBenjamin Herrenschmidt phb->ioda.pe_rmap[rid] = pe->pe_number; 954184cd4a3SBenjamin Herrenschmidt 955184cd4a3SBenjamin Herrenschmidt /* Setup one MVTs on IODA1 */ 9564773f76bSGavin Shan if (phb->type != PNV_PHB_IODA1) { 9574773f76bSGavin Shan pe->mve_number = 0; 9584773f76bSGavin Shan goto out; 9594773f76bSGavin Shan } 9604773f76bSGavin Shan 961184cd4a3SBenjamin Herrenschmidt pe->mve_number = pe->pe_number; 9624773f76bSGavin Shan rc = opal_pci_set_mve(phb->opal_id, pe->mve_number, pe->pe_number); 9634773f76bSGavin Shan if (rc != OPAL_SUCCESS) { 9641f52f176SRussell Currey pe_err(pe, "OPAL error %ld setting up MVE %x\n", 965184cd4a3SBenjamin Herrenschmidt rc, pe->mve_number); 966184cd4a3SBenjamin Herrenschmidt pe->mve_number = -1; 967184cd4a3SBenjamin Herrenschmidt } else { 968184cd4a3SBenjamin Herrenschmidt rc = opal_pci_set_mve_enable(phb->opal_id, 969cee72d5bSBenjamin Herrenschmidt pe->mve_number, OPAL_ENABLE_MVE); 970184cd4a3SBenjamin Herrenschmidt if (rc) { 9711f52f176SRussell Currey pe_err(pe, "OPAL error %ld enabling MVE %x\n", 972184cd4a3SBenjamin Herrenschmidt rc, pe->mve_number); 973184cd4a3SBenjamin Herrenschmidt pe->mve_number = -1; 974184cd4a3SBenjamin Herrenschmidt } 975184cd4a3SBenjamin Herrenschmidt } 976184cd4a3SBenjamin Herrenschmidt 9774773f76bSGavin Shan out: 978184cd4a3SBenjamin Herrenschmidt return 0; 979184cd4a3SBenjamin Herrenschmidt } 980184cd4a3SBenjamin Herrenschmidt 981cad5cef6SGreg Kroah-Hartman static struct pnv_ioda_pe *pnv_ioda_setup_dev_PE(struct pci_dev *dev) 982184cd4a3SBenjamin Herrenschmidt { 9835609ffddSOliver O'Halloran struct pnv_phb *phb = pci_bus_to_pnvhb(dev->bus); 984b72c1f65SBenjamin Herrenschmidt struct pci_dn *pdn = pci_get_pdn(dev); 985184cd4a3SBenjamin Herrenschmidt struct pnv_ioda_pe *pe; 986184cd4a3SBenjamin Herrenschmidt 987184cd4a3SBenjamin Herrenschmidt if (!pdn) { 988184cd4a3SBenjamin Herrenschmidt pr_err("%s: Device tree node not associated properly\n", 989184cd4a3SBenjamin Herrenschmidt pci_name(dev)); 990184cd4a3SBenjamin Herrenschmidt return NULL; 991184cd4a3SBenjamin Herrenschmidt } 992184cd4a3SBenjamin Herrenschmidt if (pdn->pe_number != IODA_INVALID_PE) 993184cd4a3SBenjamin Herrenschmidt return NULL; 994184cd4a3SBenjamin Herrenschmidt 995a4bc676eSOliver O'Halloran pe = pnv_ioda_alloc_pe(phb, 1); 9961e916772SGavin Shan if (!pe) { 997f2c2cbccSJoe Perches pr_warn("%s: Not enough PE# available, disabling device\n", 998184cd4a3SBenjamin Herrenschmidt pci_name(dev)); 999184cd4a3SBenjamin Herrenschmidt return NULL; 1000184cd4a3SBenjamin Herrenschmidt } 1001184cd4a3SBenjamin Herrenschmidt 100205dd7da7SFrederic Barrat /* NOTE: We don't get a reference for the pointer in the PE 100305dd7da7SFrederic Barrat * data structure, both the device and PE structures should be 1004562d1e20SChristoph Hellwig * destroyed at the same time. 1005184cd4a3SBenjamin Herrenschmidt * 1006184cd4a3SBenjamin Herrenschmidt * At some point we want to remove the PDN completely anyways 1007184cd4a3SBenjamin Herrenschmidt */ 10081e916772SGavin Shan pdn->pe_number = pe->pe_number; 10095d2aa710SAlistair Popple pe->flags = PNV_IODA_PE_DEV; 1010184cd4a3SBenjamin Herrenschmidt pe->pdev = dev; 1011184cd4a3SBenjamin Herrenschmidt pe->pbus = NULL; 1012184cd4a3SBenjamin Herrenschmidt pe->mve_number = -1; 1013184cd4a3SBenjamin Herrenschmidt pe->rid = dev->bus->number << 8 | pdn->devfn; 1014f724385fSFrederic Barrat pe->device_count++; 1015184cd4a3SBenjamin Herrenschmidt 1016184cd4a3SBenjamin Herrenschmidt pe_info(pe, "Associated device to PE\n"); 1017184cd4a3SBenjamin Herrenschmidt 1018184cd4a3SBenjamin Herrenschmidt if (pnv_ioda_configure_pe(phb, pe)) { 1019184cd4a3SBenjamin Herrenschmidt /* XXX What do we do here ? */ 10201e916772SGavin Shan pnv_ioda_free_pe(pe); 1021184cd4a3SBenjamin Herrenschmidt pdn->pe_number = IODA_INVALID_PE; 1022184cd4a3SBenjamin Herrenschmidt pe->pdev = NULL; 1023184cd4a3SBenjamin Herrenschmidt return NULL; 1024184cd4a3SBenjamin Herrenschmidt } 1025184cd4a3SBenjamin Herrenschmidt 10261d4e89cfSAlexey Kardashevskiy /* Put PE to the list */ 102780f1ff83SFrederic Barrat mutex_lock(&phb->ioda.pe_list_mutex); 10281d4e89cfSAlexey Kardashevskiy list_add_tail(&pe->list, &phb->ioda.pe_list); 102980f1ff83SFrederic Barrat mutex_unlock(&phb->ioda.pe_list_mutex); 1030184cd4a3SBenjamin Herrenschmidt return pe; 1031184cd4a3SBenjamin Herrenschmidt } 1032184cd4a3SBenjamin Herrenschmidt 1033fb446ad0SGavin Shan /* 1034fb446ad0SGavin Shan * There're 2 types of PCI bus sensitive PEs: One that is compromised of 1035fb446ad0SGavin Shan * single PCI bus. Another one that contains the primary PCI bus and its 1036fb446ad0SGavin Shan * subordinate PCI devices and buses. The second type of PE is normally 1037fb446ad0SGavin Shan * orgiriated by PCIe-to-PCI bridge or PLX switch downstream ports. 1038fb446ad0SGavin Shan */ 10391e916772SGavin Shan static struct pnv_ioda_pe *pnv_ioda_setup_bus_PE(struct pci_bus *bus, bool all) 1040184cd4a3SBenjamin Herrenschmidt { 10415609ffddSOliver O'Halloran struct pnv_phb *phb = pci_bus_to_pnvhb(bus); 10421e916772SGavin Shan struct pnv_ioda_pe *pe = NULL; 1043ccd1c191SGavin Shan unsigned int pe_num; 1044ccd1c191SGavin Shan 1045ccd1c191SGavin Shan /* 1046ccd1c191SGavin Shan * In partial hotplug case, the PE instance might be still alive. 1047ccd1c191SGavin Shan * We should reuse it instead of allocating a new one. 1048ccd1c191SGavin Shan */ 1049ccd1c191SGavin Shan pe_num = phb->ioda.pe_rmap[bus->number << 8]; 10506ae8aedfSOliver O'Halloran if (WARN_ON(pe_num != IODA_INVALID_PE)) { 1051ccd1c191SGavin Shan pe = &phb->ioda.pe_array[pe_num]; 1052ccd1c191SGavin Shan return NULL; 1053ccd1c191SGavin Shan } 1054184cd4a3SBenjamin Herrenschmidt 105563803c39SGavin Shan /* PE number for root bus should have been reserved */ 1056718d249aSOliver O'Halloran if (pci_is_root_bus(bus)) 105763803c39SGavin Shan pe = &phb->ioda.pe_array[phb->ioda.root_pe_idx]; 105863803c39SGavin Shan 1059262af557SGuo Chao /* Check if PE is determined by M64 */ 1060a25de7afSAlexey Kardashevskiy if (!pe) 1061a25de7afSAlexey Kardashevskiy pe = pnv_ioda_pick_m64_pe(bus, all); 1062262af557SGuo Chao 1063262af557SGuo Chao /* The PE number isn't pinned by M64 */ 10641e916772SGavin Shan if (!pe) 1065a4bc676eSOliver O'Halloran pe = pnv_ioda_alloc_pe(phb, 1); 1066262af557SGuo Chao 10671e916772SGavin Shan if (!pe) { 1068f2c2cbccSJoe Perches pr_warn("%s: Not enough PE# available for PCI bus %04x:%02x\n", 1069fb446ad0SGavin Shan __func__, pci_domain_nr(bus), bus->number); 10701e916772SGavin Shan return NULL; 1071184cd4a3SBenjamin Herrenschmidt } 1072184cd4a3SBenjamin Herrenschmidt 1073262af557SGuo Chao pe->flags |= (all ? PNV_IODA_PE_BUS_ALL : PNV_IODA_PE_BUS); 1074184cd4a3SBenjamin Herrenschmidt pe->pbus = bus; 1075184cd4a3SBenjamin Herrenschmidt pe->pdev = NULL; 1076184cd4a3SBenjamin Herrenschmidt pe->mve_number = -1; 1077b918c62eSYinghai Lu pe->rid = bus->busn_res.start << 8; 1078184cd4a3SBenjamin Herrenschmidt 1079fb446ad0SGavin Shan if (all) 10801e496391SJoe Perches pe_info(pe, "Secondary bus %pad..%pad associated with PE#%x\n", 10811e496391SJoe Perches &bus->busn_res.start, &bus->busn_res.end, 10821e496391SJoe Perches pe->pe_number); 1083fb446ad0SGavin Shan else 10841e496391SJoe Perches pe_info(pe, "Secondary bus %pad associated with PE#%x\n", 10851e496391SJoe Perches &bus->busn_res.start, pe->pe_number); 1086184cd4a3SBenjamin Herrenschmidt 1087184cd4a3SBenjamin Herrenschmidt if (pnv_ioda_configure_pe(phb, pe)) { 1088184cd4a3SBenjamin Herrenschmidt /* XXX What do we do here ? */ 10891e916772SGavin Shan pnv_ioda_free_pe(pe); 1090184cd4a3SBenjamin Herrenschmidt pe->pbus = NULL; 10911e916772SGavin Shan return NULL; 1092184cd4a3SBenjamin Herrenschmidt } 1093184cd4a3SBenjamin Herrenschmidt 10947ebdf956SGavin Shan /* Put PE to the list */ 10957ebdf956SGavin Shan list_add_tail(&pe->list, &phb->ioda.pe_list); 10961e916772SGavin Shan 10971e916772SGavin Shan return pe; 1098184cd4a3SBenjamin Herrenschmidt } 1099184cd4a3SBenjamin Herrenschmidt 110001e12629SOliver O'Halloran static void pnv_pci_ioda1_setup_dma_pe(struct pnv_phb *phb, 110101e12629SOliver O'Halloran struct pnv_ioda_pe *pe); 110201e12629SOliver O'Halloran 11030a25d9c4SOliver O'Halloran static void pnv_pci_ioda_dma_dev_setup(struct pci_dev *pdev) 1104184cd4a3SBenjamin Herrenschmidt { 11055609ffddSOliver O'Halloran struct pnv_phb *phb = pci_bus_to_pnvhb(pdev->bus); 1106b72c1f65SBenjamin Herrenschmidt struct pci_dn *pdn = pci_get_pdn(pdev); 1107959c9bddSGavin Shan struct pnv_ioda_pe *pe; 1108184cd4a3SBenjamin Herrenschmidt 1109dc3d8f85SOliver O'Halloran /* Check if the BDFN for this device is associated with a PE yet */ 1110dc3d8f85SOliver O'Halloran pe = pnv_pci_bdfn_to_pe(phb, pdev->devfn | (pdev->bus->number << 8)); 1111dc3d8f85SOliver O'Halloran if (!pe) { 1112dc3d8f85SOliver O'Halloran /* VF PEs should be pre-configured in pnv_pci_sriov_enable() */ 1113dc3d8f85SOliver O'Halloran if (WARN_ON(pdev->is_virtfn)) 1114959c9bddSGavin Shan return; 1115184cd4a3SBenjamin Herrenschmidt 1116dc3d8f85SOliver O'Halloran pnv_pci_configure_bus(pdev->bus); 1117dc3d8f85SOliver O'Halloran pe = pnv_pci_bdfn_to_pe(phb, pdev->devfn | (pdev->bus->number << 8)); 1118dc3d8f85SOliver O'Halloran pci_info(pdev, "Configured PE#%x\n", pe ? pe->pe_number : 0xfffff); 1119dc3d8f85SOliver O'Halloran 1120dc3d8f85SOliver O'Halloran 1121dc3d8f85SOliver O'Halloran /* 1122dc3d8f85SOliver O'Halloran * If we can't setup the IODA PE something has gone horribly 1123dc3d8f85SOliver O'Halloran * wrong and we can't enable DMA for the device. 1124dc3d8f85SOliver O'Halloran */ 1125dc3d8f85SOliver O'Halloran if (WARN_ON(!pe)) 1126dc3d8f85SOliver O'Halloran return; 1127dc3d8f85SOliver O'Halloran } else { 1128dc3d8f85SOliver O'Halloran pci_info(pdev, "Added to existing PE#%x\n", pe->pe_number); 1129dc3d8f85SOliver O'Halloran } 1130dc3d8f85SOliver O'Halloran 113101e12629SOliver O'Halloran /* 113201e12629SOliver O'Halloran * We assume that bridges *probably* don't need to do any DMA so we can 113301e12629SOliver O'Halloran * skip allocating a TCE table, etc unless we get a non-bridge device. 113401e12629SOliver O'Halloran */ 113501e12629SOliver O'Halloran if (!pe->dma_setup_done && !pci_is_bridge(pdev)) { 113601e12629SOliver O'Halloran switch (phb->type) { 113701e12629SOliver O'Halloran case PNV_PHB_IODA1: 113801e12629SOliver O'Halloran pnv_pci_ioda1_setup_dma_pe(phb, pe); 113901e12629SOliver O'Halloran break; 114001e12629SOliver O'Halloran case PNV_PHB_IODA2: 114101e12629SOliver O'Halloran pnv_pci_ioda2_setup_dma_pe(phb, pe); 114201e12629SOliver O'Halloran break; 114301e12629SOliver O'Halloran default: 114401e12629SOliver O'Halloran pr_warn("%s: No DMA for PHB#%x (type %d)\n", 114501e12629SOliver O'Halloran __func__, phb->hose->global_number, phb->type); 114601e12629SOliver O'Halloran } 114701e12629SOliver O'Halloran } 114801e12629SOliver O'Halloran 1149dc3d8f85SOliver O'Halloran if (pdn) 1150dc3d8f85SOliver O'Halloran pdn->pe_number = pe->pe_number; 1151dc3d8f85SOliver O'Halloran pe->device_count++; 1152dc3d8f85SOliver O'Halloran 1153cd15b048SBenjamin Herrenschmidt WARN_ON(get_dma_ops(&pdev->dev) != &dma_iommu_ops); 11540617fc0cSChristoph Hellwig pdev->dev.archdata.dma_offset = pe->tce_bypass_base; 1155b348aa65SAlexey Kardashevskiy set_iommu_table_base(&pdev->dev, pe->table_group.tables[0]); 115684d8cc07SOliver O'Halloran 115784d8cc07SOliver O'Halloran /* PEs with a DMA weight of zero won't have a group */ 115884d8cc07SOliver O'Halloran if (pe->table_group.group) 115984d8cc07SOliver O'Halloran iommu_add_device(&pe->table_group, &pdev->dev); 1160184cd4a3SBenjamin Herrenschmidt } 1161184cd4a3SBenjamin Herrenschmidt 11628e3f1b1dSRussell Currey /* 11638e3f1b1dSRussell Currey * Reconfigure TVE#0 to be usable as 64-bit DMA space. 11648e3f1b1dSRussell Currey * 11658e3f1b1dSRussell Currey * The first 4GB of virtual memory for a PE is reserved for 32-bit accesses. 11668e3f1b1dSRussell Currey * Devices can only access more than that if bit 59 of the PCI address is set 11678e3f1b1dSRussell Currey * by hardware, which indicates TVE#1 should be used instead of TVE#0. 11688e3f1b1dSRussell Currey * Many PCI devices are not capable of addressing that many bits, and as a 11698e3f1b1dSRussell Currey * result are limited to the 4GB of virtual memory made available to 32-bit 11708e3f1b1dSRussell Currey * devices in TVE#0. 11718e3f1b1dSRussell Currey * 11728e3f1b1dSRussell Currey * In order to work around this, reconfigure TVE#0 to be suitable for 64-bit 11738e3f1b1dSRussell Currey * devices by configuring the virtual memory past the first 4GB inaccessible 11748e3f1b1dSRussell Currey * by 64-bit DMAs. This should only be used by devices that want more than 11758e3f1b1dSRussell Currey * 4GB, and only on PEs that have no 32-bit devices. 11768e3f1b1dSRussell Currey * 11778e3f1b1dSRussell Currey * Currently this will only work on PHB3 (POWER8). 11788e3f1b1dSRussell Currey */ 11798e3f1b1dSRussell Currey static int pnv_pci_ioda_dma_64bit_bypass(struct pnv_ioda_pe *pe) 11808e3f1b1dSRussell Currey { 11818e3f1b1dSRussell Currey u64 window_size, table_size, tce_count, addr; 11828e3f1b1dSRussell Currey struct page *table_pages; 11838e3f1b1dSRussell Currey u64 tce_order = 28; /* 256MB TCEs */ 11848e3f1b1dSRussell Currey __be64 *tces; 11858e3f1b1dSRussell Currey s64 rc; 11868e3f1b1dSRussell Currey 11878e3f1b1dSRussell Currey /* 11888e3f1b1dSRussell Currey * Window size needs to be a power of two, but needs to account for 11898e3f1b1dSRussell Currey * shifting memory by the 4GB offset required to skip 32bit space. 11908e3f1b1dSRussell Currey */ 11918e3f1b1dSRussell Currey window_size = roundup_pow_of_two(memory_hotplug_max() + (1ULL << 32)); 11928e3f1b1dSRussell Currey tce_count = window_size >> tce_order; 11938e3f1b1dSRussell Currey table_size = tce_count << 3; 11948e3f1b1dSRussell Currey 11958e3f1b1dSRussell Currey if (table_size < PAGE_SIZE) 11968e3f1b1dSRussell Currey table_size = PAGE_SIZE; 11978e3f1b1dSRussell Currey 11988e3f1b1dSRussell Currey table_pages = alloc_pages_node(pe->phb->hose->node, GFP_KERNEL, 11998e3f1b1dSRussell Currey get_order(table_size)); 12008e3f1b1dSRussell Currey if (!table_pages) 12018e3f1b1dSRussell Currey goto err; 12028e3f1b1dSRussell Currey 12038e3f1b1dSRussell Currey tces = page_address(table_pages); 12048e3f1b1dSRussell Currey if (!tces) 12058e3f1b1dSRussell Currey goto err; 12068e3f1b1dSRussell Currey 12078e3f1b1dSRussell Currey memset(tces, 0, table_size); 12088e3f1b1dSRussell Currey 12098e3f1b1dSRussell Currey for (addr = 0; addr < memory_hotplug_max(); addr += (1 << tce_order)) { 12108e3f1b1dSRussell Currey tces[(addr + (1ULL << 32)) >> tce_order] = 12118e3f1b1dSRussell Currey cpu_to_be64(addr | TCE_PCI_READ | TCE_PCI_WRITE); 12128e3f1b1dSRussell Currey } 12138e3f1b1dSRussell Currey 12148e3f1b1dSRussell Currey rc = opal_pci_map_pe_dma_window(pe->phb->opal_id, 12158e3f1b1dSRussell Currey pe->pe_number, 12168e3f1b1dSRussell Currey /* reconfigure window 0 */ 12178e3f1b1dSRussell Currey (pe->pe_number << 1) + 0, 12188e3f1b1dSRussell Currey 1, 12198e3f1b1dSRussell Currey __pa(tces), 12208e3f1b1dSRussell Currey table_size, 12218e3f1b1dSRussell Currey 1 << tce_order); 12228e3f1b1dSRussell Currey if (rc == OPAL_SUCCESS) { 12238e3f1b1dSRussell Currey pe_info(pe, "Using 64-bit DMA iommu bypass (through TVE#0)\n"); 12248e3f1b1dSRussell Currey return 0; 12258e3f1b1dSRussell Currey } 12268e3f1b1dSRussell Currey err: 12278e3f1b1dSRussell Currey pe_err(pe, "Error configuring 64-bit DMA bypass\n"); 12288e3f1b1dSRussell Currey return -EIO; 12298e3f1b1dSRussell Currey } 12308e3f1b1dSRussell Currey 12312d6ad41bSChristoph Hellwig static bool pnv_pci_ioda_iommu_bypass_supported(struct pci_dev *pdev, 12322d6ad41bSChristoph Hellwig u64 dma_mask) 1233cd15b048SBenjamin Herrenschmidt { 12345609ffddSOliver O'Halloran struct pnv_phb *phb = pci_bus_to_pnvhb(pdev->bus); 1235cd15b048SBenjamin Herrenschmidt struct pci_dn *pdn = pci_get_pdn(pdev); 1236cd15b048SBenjamin Herrenschmidt struct pnv_ioda_pe *pe; 1237cd15b048SBenjamin Herrenschmidt 1238cd15b048SBenjamin Herrenschmidt if (WARN_ON(!pdn || pdn->pe_number == IODA_INVALID_PE)) 1239b511cdd1SAlexey Kardashevskiy return false; 1240cd15b048SBenjamin Herrenschmidt 1241cd15b048SBenjamin Herrenschmidt pe = &phb->ioda.pe_array[pdn->pe_number]; 1242cd15b048SBenjamin Herrenschmidt if (pe->tce_bypass_enabled) { 12432d6ad41bSChristoph Hellwig u64 top = pe->tce_bypass_base + memblock_end_of_DRAM() - 1; 12442d6ad41bSChristoph Hellwig if (dma_mask >= top) 12452d6ad41bSChristoph Hellwig return true; 1246cd15b048SBenjamin Herrenschmidt } 1247cd15b048SBenjamin Herrenschmidt 12488e3f1b1dSRussell Currey /* 12498e3f1b1dSRussell Currey * If the device can't set the TCE bypass bit but still wants 12508e3f1b1dSRussell Currey * to access 4GB or more, on PHB3 we can reconfigure TVE#0 to 12518e3f1b1dSRussell Currey * bypass the 32-bit region and be usable for 64-bit DMAs. 12528e3f1b1dSRussell Currey * The device needs to be able to address all of this space. 12538e3f1b1dSRussell Currey */ 12548e3f1b1dSRussell Currey if (dma_mask >> 32 && 12558e3f1b1dSRussell Currey dma_mask > (memory_hotplug_max() + (1ULL << 32)) && 1256661fcb45SChristoph Hellwig /* pe->pdev should be set if it's a single device, pe->pbus if not */ 1257661fcb45SChristoph Hellwig (pe->device_count == 1 || !pe->pbus) && 12588e3f1b1dSRussell Currey phb->model == PNV_PHB_MODEL_PHB3) { 12598e3f1b1dSRussell Currey /* Configure the bypass mode */ 12602d6ad41bSChristoph Hellwig s64 rc = pnv_pci_ioda_dma_64bit_bypass(pe); 12618e3f1b1dSRussell Currey if (rc) 1262b511cdd1SAlexey Kardashevskiy return false; 12638e3f1b1dSRussell Currey /* 4GB offset bypasses 32-bit space */ 12640617fc0cSChristoph Hellwig pdev->dev.archdata.dma_offset = (1ULL << 32); 12652d6ad41bSChristoph Hellwig return true; 1266cd15b048SBenjamin Herrenschmidt } 1267cd15b048SBenjamin Herrenschmidt 12682d6ad41bSChristoph Hellwig return false; 1269fe7e85c6SGavin Shan } 1270fe7e85c6SGavin Shan 1271cad32d9dSAlexey Kardashevskiy static inline __be64 __iomem *pnv_ioda_get_inval_reg(struct pnv_phb *phb) 1272fd141d1aSBenjamin Herrenschmidt { 1273cad32d9dSAlexey Kardashevskiy return phb->regs + 0x210; 1274fd141d1aSBenjamin Herrenschmidt } 1275fd141d1aSBenjamin Herrenschmidt 1276a34ab7c3SBenjamin Herrenschmidt static void pnv_pci_p7ioc_tce_invalidate(struct iommu_table *tbl, 1277cad32d9dSAlexey Kardashevskiy unsigned long index, unsigned long npages) 12784cce9550SGavin Shan { 12790eaf4defSAlexey Kardashevskiy struct iommu_table_group_link *tgl = list_first_entry_or_null( 12800eaf4defSAlexey Kardashevskiy &tbl->it_group_list, struct iommu_table_group_link, 12810eaf4defSAlexey Kardashevskiy next); 12820eaf4defSAlexey Kardashevskiy struct pnv_ioda_pe *pe = container_of(tgl->table_group, 1283b348aa65SAlexey Kardashevskiy struct pnv_ioda_pe, table_group); 1284cad32d9dSAlexey Kardashevskiy __be64 __iomem *invalidate = pnv_ioda_get_inval_reg(pe->phb); 12854cce9550SGavin Shan unsigned long start, end, inc; 12864cce9550SGavin Shan 1287decbda25SAlexey Kardashevskiy start = __pa(((__be64 *)tbl->it_base) + index - tbl->it_offset); 1288decbda25SAlexey Kardashevskiy end = __pa(((__be64 *)tbl->it_base) + index - tbl->it_offset + 1289decbda25SAlexey Kardashevskiy npages - 1); 12904cce9550SGavin Shan 12914cce9550SGavin Shan /* p7ioc-style invalidation, 2 TCEs per write */ 12924cce9550SGavin Shan start |= (1ull << 63); 12934cce9550SGavin Shan end |= (1ull << 63); 12944cce9550SGavin Shan inc = 16; 12954cce9550SGavin Shan end |= inc - 1; /* round up end to be different than start */ 12964cce9550SGavin Shan 12974cce9550SGavin Shan mb(); /* Ensure above stores are visible */ 12984cce9550SGavin Shan while (start <= end) { 1299001ff2eeSMichael Ellerman __raw_writeq_be(start, invalidate); 13004cce9550SGavin Shan start += inc; 13014cce9550SGavin Shan } 13024cce9550SGavin Shan 13034cce9550SGavin Shan /* 13044cce9550SGavin Shan * The iommu layer will do another mb() for us on build() 13054cce9550SGavin Shan * and we don't care on free() 13064cce9550SGavin Shan */ 13074cce9550SGavin Shan } 13084cce9550SGavin Shan 1309decbda25SAlexey Kardashevskiy static int pnv_ioda1_tce_build(struct iommu_table *tbl, long index, 1310decbda25SAlexey Kardashevskiy long npages, unsigned long uaddr, 1311decbda25SAlexey Kardashevskiy enum dma_data_direction direction, 131200085f1eSKrzysztof Kozlowski unsigned long attrs) 1313decbda25SAlexey Kardashevskiy { 1314decbda25SAlexey Kardashevskiy int ret = pnv_tce_build(tbl, index, npages, uaddr, direction, 1315decbda25SAlexey Kardashevskiy attrs); 1316decbda25SAlexey Kardashevskiy 131708acce1cSBenjamin Herrenschmidt if (!ret) 1318cad32d9dSAlexey Kardashevskiy pnv_pci_p7ioc_tce_invalidate(tbl, index, npages); 1319decbda25SAlexey Kardashevskiy 1320decbda25SAlexey Kardashevskiy return ret; 1321decbda25SAlexey Kardashevskiy } 1322decbda25SAlexey Kardashevskiy 132305c6cfb9SAlexey Kardashevskiy #ifdef CONFIG_IOMMU_API 132435872480SAlexey Kardashevskiy /* Common for IODA1 and IODA2 */ 132535872480SAlexey Kardashevskiy static int pnv_ioda_tce_xchg_no_kill(struct iommu_table *tbl, long index, 1326cad32d9dSAlexey Kardashevskiy unsigned long *hpa, enum dma_data_direction *direction) 132705c6cfb9SAlexey Kardashevskiy { 1328cad32d9dSAlexey Kardashevskiy return pnv_tce_xchg(tbl, index, hpa, direction); 1329a540aa56SAlexey Kardashevskiy } 133005c6cfb9SAlexey Kardashevskiy #endif 133105c6cfb9SAlexey Kardashevskiy 1332decbda25SAlexey Kardashevskiy static void pnv_ioda1_tce_free(struct iommu_table *tbl, long index, 1333decbda25SAlexey Kardashevskiy long npages) 1334decbda25SAlexey Kardashevskiy { 1335decbda25SAlexey Kardashevskiy pnv_tce_free(tbl, index, npages); 1336decbda25SAlexey Kardashevskiy 1337cad32d9dSAlexey Kardashevskiy pnv_pci_p7ioc_tce_invalidate(tbl, index, npages); 1338decbda25SAlexey Kardashevskiy } 1339decbda25SAlexey Kardashevskiy 1340da004c36SAlexey Kardashevskiy static struct iommu_table_ops pnv_ioda1_iommu_ops = { 1341decbda25SAlexey Kardashevskiy .set = pnv_ioda1_tce_build, 134205c6cfb9SAlexey Kardashevskiy #ifdef CONFIG_IOMMU_API 134335872480SAlexey Kardashevskiy .xchg_no_kill = pnv_ioda_tce_xchg_no_kill, 134435872480SAlexey Kardashevskiy .tce_kill = pnv_pci_p7ioc_tce_invalidate, 1345090bad39SAlexey Kardashevskiy .useraddrptr = pnv_tce_useraddrptr, 134605c6cfb9SAlexey Kardashevskiy #endif 1347decbda25SAlexey Kardashevskiy .clear = pnv_ioda1_tce_free, 1348da004c36SAlexey Kardashevskiy .get = pnv_tce_get, 1349da004c36SAlexey Kardashevskiy }; 1350da004c36SAlexey Kardashevskiy 1351a34ab7c3SBenjamin Herrenschmidt #define PHB3_TCE_KILL_INVAL_ALL PPC_BIT(0) 1352a34ab7c3SBenjamin Herrenschmidt #define PHB3_TCE_KILL_INVAL_PE PPC_BIT(1) 1353a34ab7c3SBenjamin Herrenschmidt #define PHB3_TCE_KILL_INVAL_ONE PPC_BIT(2) 1354bef9253fSAlexey Kardashevskiy 1355a34ab7c3SBenjamin Herrenschmidt static inline void pnv_pci_phb3_tce_invalidate_pe(struct pnv_ioda_pe *pe) 13565780fb04SAlexey Kardashevskiy { 13575780fb04SAlexey Kardashevskiy /* 01xb - invalidate TCEs that match the specified PE# */ 1358cad32d9dSAlexey Kardashevskiy __be64 __iomem *invalidate = pnv_ioda_get_inval_reg(pe->phb); 1359a34ab7c3SBenjamin Herrenschmidt unsigned long val = PHB3_TCE_KILL_INVAL_PE | (pe->pe_number & 0xFF); 13605780fb04SAlexey Kardashevskiy 13615780fb04SAlexey Kardashevskiy mb(); /* Ensure above stores are visible */ 1362001ff2eeSMichael Ellerman __raw_writeq_be(val, invalidate); 13635780fb04SAlexey Kardashevskiy } 13645780fb04SAlexey Kardashevskiy 1365cad32d9dSAlexey Kardashevskiy static void pnv_pci_phb3_tce_invalidate(struct pnv_ioda_pe *pe, 1366fd141d1aSBenjamin Herrenschmidt unsigned shift, unsigned long index, 1367fd141d1aSBenjamin Herrenschmidt unsigned long npages) 13684cce9550SGavin Shan { 1369cad32d9dSAlexey Kardashevskiy __be64 __iomem *invalidate = pnv_ioda_get_inval_reg(pe->phb); 13704cce9550SGavin Shan unsigned long start, end, inc; 13714cce9550SGavin Shan 13724cce9550SGavin Shan /* We'll invalidate DMA address in PE scope */ 1373a34ab7c3SBenjamin Herrenschmidt start = PHB3_TCE_KILL_INVAL_ONE; 1374fd141d1aSBenjamin Herrenschmidt start |= (pe->pe_number & 0xFF); 13754cce9550SGavin Shan end = start; 13764cce9550SGavin Shan 13774cce9550SGavin Shan /* Figure out the start, end and step */ 1378decbda25SAlexey Kardashevskiy start |= (index << shift); 1379decbda25SAlexey Kardashevskiy end |= ((index + npages - 1) << shift); 1380b0376c9bSAlexey Kardashevskiy inc = (0x1ull << shift); 13814cce9550SGavin Shan mb(); 13824cce9550SGavin Shan 13834cce9550SGavin Shan while (start <= end) { 1384001ff2eeSMichael Ellerman __raw_writeq_be(start, invalidate); 13854cce9550SGavin Shan start += inc; 13864cce9550SGavin Shan } 13874cce9550SGavin Shan } 13884cce9550SGavin Shan 1389f0228c41SBenjamin Herrenschmidt static inline void pnv_pci_ioda2_tce_invalidate_pe(struct pnv_ioda_pe *pe) 1390f0228c41SBenjamin Herrenschmidt { 1391f0228c41SBenjamin Herrenschmidt struct pnv_phb *phb = pe->phb; 1392f0228c41SBenjamin Herrenschmidt 1393f0228c41SBenjamin Herrenschmidt if (phb->model == PNV_PHB_MODEL_PHB3 && phb->regs) 1394f0228c41SBenjamin Herrenschmidt pnv_pci_phb3_tce_invalidate_pe(pe); 1395f0228c41SBenjamin Herrenschmidt else 1396f0228c41SBenjamin Herrenschmidt opal_pci_tce_kill(phb->opal_id, OPAL_PCI_TCE_KILL_PE, 1397f0228c41SBenjamin Herrenschmidt pe->pe_number, 0, 0, 0); 1398f0228c41SBenjamin Herrenschmidt } 1399f0228c41SBenjamin Herrenschmidt 1400e57080f1SAlexey Kardashevskiy static void pnv_pci_ioda2_tce_invalidate(struct iommu_table *tbl, 1401cad32d9dSAlexey Kardashevskiy unsigned long index, unsigned long npages) 1402e57080f1SAlexey Kardashevskiy { 1403e57080f1SAlexey Kardashevskiy struct iommu_table_group_link *tgl; 1404e57080f1SAlexey Kardashevskiy 1405a540aa56SAlexey Kardashevskiy list_for_each_entry_lockless(tgl, &tbl->it_group_list, next) { 1406e57080f1SAlexey Kardashevskiy struct pnv_ioda_pe *pe = container_of(tgl->table_group, 1407e57080f1SAlexey Kardashevskiy struct pnv_ioda_pe, table_group); 1408f0228c41SBenjamin Herrenschmidt struct pnv_phb *phb = pe->phb; 1409f0228c41SBenjamin Herrenschmidt unsigned int shift = tbl->it_page_shift; 1410f0228c41SBenjamin Herrenschmidt 1411f0228c41SBenjamin Herrenschmidt if (phb->model == PNV_PHB_MODEL_PHB3 && phb->regs) 1412cad32d9dSAlexey Kardashevskiy pnv_pci_phb3_tce_invalidate(pe, shift, 141385674868SAlexey Kardashevskiy index, npages); 1414f0228c41SBenjamin Herrenschmidt else 1415f0228c41SBenjamin Herrenschmidt opal_pci_tce_kill(phb->opal_id, 1416f0228c41SBenjamin Herrenschmidt OPAL_PCI_TCE_KILL_PAGES, 1417f0228c41SBenjamin Herrenschmidt pe->pe_number, 1u << shift, 1418f0228c41SBenjamin Herrenschmidt index << shift, npages); 1419e57080f1SAlexey Kardashevskiy } 1420e57080f1SAlexey Kardashevskiy } 1421e57080f1SAlexey Kardashevskiy 1422decbda25SAlexey Kardashevskiy static int pnv_ioda2_tce_build(struct iommu_table *tbl, long index, 1423decbda25SAlexey Kardashevskiy long npages, unsigned long uaddr, 1424decbda25SAlexey Kardashevskiy enum dma_data_direction direction, 142500085f1eSKrzysztof Kozlowski unsigned long attrs) 14264cce9550SGavin Shan { 1427decbda25SAlexey Kardashevskiy int ret = pnv_tce_build(tbl, index, npages, uaddr, direction, 1428decbda25SAlexey Kardashevskiy attrs); 14294cce9550SGavin Shan 143008acce1cSBenjamin Herrenschmidt if (!ret) 1431cad32d9dSAlexey Kardashevskiy pnv_pci_ioda2_tce_invalidate(tbl, index, npages); 1432decbda25SAlexey Kardashevskiy 1433decbda25SAlexey Kardashevskiy return ret; 1434decbda25SAlexey Kardashevskiy } 1435decbda25SAlexey Kardashevskiy 1436decbda25SAlexey Kardashevskiy static void pnv_ioda2_tce_free(struct iommu_table *tbl, long index, 1437decbda25SAlexey Kardashevskiy long npages) 1438decbda25SAlexey Kardashevskiy { 1439decbda25SAlexey Kardashevskiy pnv_tce_free(tbl, index, npages); 1440decbda25SAlexey Kardashevskiy 1441cad32d9dSAlexey Kardashevskiy pnv_pci_ioda2_tce_invalidate(tbl, index, npages); 14424cce9550SGavin Shan } 14434cce9550SGavin Shan 1444da004c36SAlexey Kardashevskiy static struct iommu_table_ops pnv_ioda2_iommu_ops = { 1445decbda25SAlexey Kardashevskiy .set = pnv_ioda2_tce_build, 144605c6cfb9SAlexey Kardashevskiy #ifdef CONFIG_IOMMU_API 144735872480SAlexey Kardashevskiy .xchg_no_kill = pnv_ioda_tce_xchg_no_kill, 144835872480SAlexey Kardashevskiy .tce_kill = pnv_pci_ioda2_tce_invalidate, 1449090bad39SAlexey Kardashevskiy .useraddrptr = pnv_tce_useraddrptr, 145005c6cfb9SAlexey Kardashevskiy #endif 1451decbda25SAlexey Kardashevskiy .clear = pnv_ioda2_tce_free, 1452da004c36SAlexey Kardashevskiy .get = pnv_tce_get, 1453da2bb0daSAlexey Kardashevskiy .free = pnv_pci_ioda2_table_free_pages, 1454da004c36SAlexey Kardashevskiy }; 1455da004c36SAlexey Kardashevskiy 1456801846d1SGavin Shan static int pnv_pci_ioda_dev_dma_weight(struct pci_dev *dev, void *data) 1457801846d1SGavin Shan { 1458801846d1SGavin Shan unsigned int *weight = (unsigned int *)data; 1459801846d1SGavin Shan 1460801846d1SGavin Shan /* This is quite simplistic. The "base" weight of a device 1461801846d1SGavin Shan * is 10. 0 means no DMA is to be accounted for it. 1462801846d1SGavin Shan */ 1463801846d1SGavin Shan if (dev->hdr_type != PCI_HEADER_TYPE_NORMAL) 1464801846d1SGavin Shan return 0; 1465801846d1SGavin Shan 1466801846d1SGavin Shan if (dev->class == PCI_CLASS_SERIAL_USB_UHCI || 1467801846d1SGavin Shan dev->class == PCI_CLASS_SERIAL_USB_OHCI || 1468801846d1SGavin Shan dev->class == PCI_CLASS_SERIAL_USB_EHCI) 1469801846d1SGavin Shan *weight += 3; 1470801846d1SGavin Shan else if ((dev->class >> 8) == PCI_CLASS_STORAGE_RAID) 1471801846d1SGavin Shan *weight += 15; 1472801846d1SGavin Shan else 1473801846d1SGavin Shan *weight += 10; 1474801846d1SGavin Shan 1475801846d1SGavin Shan return 0; 1476801846d1SGavin Shan } 1477801846d1SGavin Shan 1478801846d1SGavin Shan static unsigned int pnv_pci_ioda_pe_dma_weight(struct pnv_ioda_pe *pe) 1479801846d1SGavin Shan { 1480801846d1SGavin Shan unsigned int weight = 0; 1481801846d1SGavin Shan 1482801846d1SGavin Shan /* SRIOV VF has same DMA32 weight as its PF */ 1483801846d1SGavin Shan #ifdef CONFIG_PCI_IOV 1484801846d1SGavin Shan if ((pe->flags & PNV_IODA_PE_VF) && pe->parent_dev) { 1485801846d1SGavin Shan pnv_pci_ioda_dev_dma_weight(pe->parent_dev, &weight); 1486801846d1SGavin Shan return weight; 1487801846d1SGavin Shan } 1488801846d1SGavin Shan #endif 1489801846d1SGavin Shan 1490801846d1SGavin Shan if ((pe->flags & PNV_IODA_PE_DEV) && pe->pdev) { 1491801846d1SGavin Shan pnv_pci_ioda_dev_dma_weight(pe->pdev, &weight); 1492801846d1SGavin Shan } else if ((pe->flags & PNV_IODA_PE_BUS) && pe->pbus) { 1493801846d1SGavin Shan struct pci_dev *pdev; 1494801846d1SGavin Shan 1495801846d1SGavin Shan list_for_each_entry(pdev, &pe->pbus->devices, bus_list) 1496801846d1SGavin Shan pnv_pci_ioda_dev_dma_weight(pdev, &weight); 1497801846d1SGavin Shan } else if ((pe->flags & PNV_IODA_PE_BUS_ALL) && pe->pbus) { 1498801846d1SGavin Shan pci_walk_bus(pe->pbus, pnv_pci_ioda_dev_dma_weight, &weight); 1499801846d1SGavin Shan } 1500801846d1SGavin Shan 1501801846d1SGavin Shan return weight; 1502801846d1SGavin Shan } 1503801846d1SGavin Shan 1504b30d936fSGavin Shan static void pnv_pci_ioda1_setup_dma_pe(struct pnv_phb *phb, 15052b923ed1SGavin Shan struct pnv_ioda_pe *pe) 1506184cd4a3SBenjamin Herrenschmidt { 1507184cd4a3SBenjamin Herrenschmidt 1508184cd4a3SBenjamin Herrenschmidt struct page *tce_mem = NULL; 1509184cd4a3SBenjamin Herrenschmidt struct iommu_table *tbl; 15102b923ed1SGavin Shan unsigned int weight, total_weight = 0; 15112b923ed1SGavin Shan unsigned int tce32_segsz, base, segs, avail, i; 1512184cd4a3SBenjamin Herrenschmidt int64_t rc; 1513184cd4a3SBenjamin Herrenschmidt void *addr; 1514184cd4a3SBenjamin Herrenschmidt 1515184cd4a3SBenjamin Herrenschmidt /* XXX FIXME: Handle 64-bit only DMA devices */ 1516184cd4a3SBenjamin Herrenschmidt /* XXX FIXME: Provide 64-bit DMA facilities & non-4K TCE tables etc.. */ 1517184cd4a3SBenjamin Herrenschmidt /* XXX FIXME: Allocate multi-level tables on PHB3 */ 15182b923ed1SGavin Shan weight = pnv_pci_ioda_pe_dma_weight(pe); 15192b923ed1SGavin Shan if (!weight) 15202b923ed1SGavin Shan return; 1521184cd4a3SBenjamin Herrenschmidt 15222b923ed1SGavin Shan pci_walk_bus(phb->hose->bus, pnv_pci_ioda_dev_dma_weight, 15232b923ed1SGavin Shan &total_weight); 15242b923ed1SGavin Shan segs = (weight * phb->ioda.dma32_count) / total_weight; 15252b923ed1SGavin Shan if (!segs) 15262b923ed1SGavin Shan segs = 1; 15272b923ed1SGavin Shan 15282b923ed1SGavin Shan /* 15292b923ed1SGavin Shan * Allocate contiguous DMA32 segments. We begin with the expected 15302b923ed1SGavin Shan * number of segments. With one more attempt, the number of DMA32 15312b923ed1SGavin Shan * segments to be allocated is decreased by one until one segment 15322b923ed1SGavin Shan * is allocated successfully. 15332b923ed1SGavin Shan */ 15342b923ed1SGavin Shan do { 15352b923ed1SGavin Shan for (base = 0; base <= phb->ioda.dma32_count - segs; base++) { 15362b923ed1SGavin Shan for (avail = 0, i = base; i < base + segs; i++) { 15372b923ed1SGavin Shan if (phb->ioda.dma32_segmap[i] == 15382b923ed1SGavin Shan IODA_INVALID_PE) 15392b923ed1SGavin Shan avail++; 15402b923ed1SGavin Shan } 15412b923ed1SGavin Shan 15422b923ed1SGavin Shan if (avail == segs) 15432b923ed1SGavin Shan goto found; 15442b923ed1SGavin Shan } 15452b923ed1SGavin Shan } while (--segs); 15462b923ed1SGavin Shan 15472b923ed1SGavin Shan if (!segs) { 15482b923ed1SGavin Shan pe_warn(pe, "No available DMA32 segments\n"); 15492b923ed1SGavin Shan return; 15502b923ed1SGavin Shan } 15512b923ed1SGavin Shan 15522b923ed1SGavin Shan found: 15530eaf4defSAlexey Kardashevskiy tbl = pnv_pci_table_alloc(phb->hose->node); 155482eae1afSAlexey Kardashevskiy if (WARN_ON(!tbl)) 155582eae1afSAlexey Kardashevskiy return; 155682eae1afSAlexey Kardashevskiy 1557*9d67c943SAlexey Kardashevskiy #ifdef CONFIG_IOMMU_API 1558*9d67c943SAlexey Kardashevskiy pe->table_group.ops = &spapr_tce_table_group_ops; 1559*9d67c943SAlexey Kardashevskiy pe->table_group.pgsizes = SZ_4K; 1560*9d67c943SAlexey Kardashevskiy #endif 1561b348aa65SAlexey Kardashevskiy iommu_register_group(&pe->table_group, phb->hose->global_number, 1562b348aa65SAlexey Kardashevskiy pe->pe_number); 15630eaf4defSAlexey Kardashevskiy pnv_pci_link_table_and_group(phb->hose->node, 0, tbl, &pe->table_group); 1564c5773822SAlexey Kardashevskiy 1565184cd4a3SBenjamin Herrenschmidt /* Grab a 32-bit TCE table */ 15662b923ed1SGavin Shan pe_info(pe, "DMA weight %d (%d), assigned (%d) %d DMA32 segments\n", 15672b923ed1SGavin Shan weight, total_weight, base, segs); 1568184cd4a3SBenjamin Herrenschmidt pe_info(pe, " Setting up 32-bit TCE table at %08x..%08x\n", 1569acce971cSGavin Shan base * PNV_IODA1_DMA32_SEGSIZE, 1570acce971cSGavin Shan (base + segs) * PNV_IODA1_DMA32_SEGSIZE - 1); 1571184cd4a3SBenjamin Herrenschmidt 1572184cd4a3SBenjamin Herrenschmidt /* XXX Currently, we allocate one big contiguous table for the 1573184cd4a3SBenjamin Herrenschmidt * TCEs. We only really need one chunk per 256M of TCE space 1574184cd4a3SBenjamin Herrenschmidt * (ie per segment) but that's an optimization for later, it 1575184cd4a3SBenjamin Herrenschmidt * requires some added smarts with our get/put_tce implementation 1576acce971cSGavin Shan * 1577acce971cSGavin Shan * Each TCE page is 4KB in size and each TCE entry occupies 8 1578acce971cSGavin Shan * bytes 1579184cd4a3SBenjamin Herrenschmidt */ 1580acce971cSGavin Shan tce32_segsz = PNV_IODA1_DMA32_SEGSIZE >> (IOMMU_PAGE_SHIFT_4K - 3); 1581184cd4a3SBenjamin Herrenschmidt tce_mem = alloc_pages_node(phb->hose->node, GFP_KERNEL, 1582acce971cSGavin Shan get_order(tce32_segsz * segs)); 1583184cd4a3SBenjamin Herrenschmidt if (!tce_mem) { 1584184cd4a3SBenjamin Herrenschmidt pe_err(pe, " Failed to allocate a 32-bit TCE memory\n"); 1585184cd4a3SBenjamin Herrenschmidt goto fail; 1586184cd4a3SBenjamin Herrenschmidt } 1587184cd4a3SBenjamin Herrenschmidt addr = page_address(tce_mem); 1588acce971cSGavin Shan memset(addr, 0, tce32_segsz * segs); 1589184cd4a3SBenjamin Herrenschmidt 1590184cd4a3SBenjamin Herrenschmidt /* Configure HW */ 1591184cd4a3SBenjamin Herrenschmidt for (i = 0; i < segs; i++) { 1592184cd4a3SBenjamin Herrenschmidt rc = opal_pci_map_pe_dma_window(phb->opal_id, 1593184cd4a3SBenjamin Herrenschmidt pe->pe_number, 1594184cd4a3SBenjamin Herrenschmidt base + i, 1, 1595acce971cSGavin Shan __pa(addr) + tce32_segsz * i, 1596acce971cSGavin Shan tce32_segsz, IOMMU_PAGE_SIZE_4K); 1597184cd4a3SBenjamin Herrenschmidt if (rc) { 15981e496391SJoe Perches pe_err(pe, " Failed to configure 32-bit TCE table, err %lld\n", 15991e496391SJoe Perches rc); 1600184cd4a3SBenjamin Herrenschmidt goto fail; 1601184cd4a3SBenjamin Herrenschmidt } 1602184cd4a3SBenjamin Herrenschmidt } 1603184cd4a3SBenjamin Herrenschmidt 16042b923ed1SGavin Shan /* Setup DMA32 segment mapping */ 16052b923ed1SGavin Shan for (i = base; i < base + segs; i++) 16062b923ed1SGavin Shan phb->ioda.dma32_segmap[i] = pe->pe_number; 16072b923ed1SGavin Shan 1608184cd4a3SBenjamin Herrenschmidt /* Setup linux iommu table */ 1609acce971cSGavin Shan pnv_pci_setup_iommu_table(tbl, addr, tce32_segsz * segs, 1610acce971cSGavin Shan base * PNV_IODA1_DMA32_SEGSIZE, 1611acce971cSGavin Shan IOMMU_PAGE_SHIFT_4K); 1612184cd4a3SBenjamin Herrenschmidt 1613da004c36SAlexey Kardashevskiy tbl->it_ops = &pnv_ioda1_iommu_ops; 16144793d65dSAlexey Kardashevskiy pe->table_group.tce32_start = tbl->it_offset << tbl->it_page_shift; 16154793d65dSAlexey Kardashevskiy pe->table_group.tce32_size = tbl->it_size << tbl->it_page_shift; 1616d73b46c3SAlexey Kardashevskiy tbl->it_index = (phb->hose->global_number << 16) | pe->pe_number; 16174be518d8SAlexey Kardashevskiy if (!iommu_init_table(tbl, phb->hose->node, 0, 0)) 16184be518d8SAlexey Kardashevskiy panic("Failed to initialize iommu table"); 1619184cd4a3SBenjamin Herrenschmidt 162001e12629SOliver O'Halloran pe->dma_setup_done = true; 1621184cd4a3SBenjamin Herrenschmidt return; 1622184cd4a3SBenjamin Herrenschmidt fail: 1623184cd4a3SBenjamin Herrenschmidt /* XXX Failure: Try to fallback to 64-bit only ? */ 1624184cd4a3SBenjamin Herrenschmidt if (tce_mem) 1625acce971cSGavin Shan __free_pages(tce_mem, get_order(tce32_segsz * segs)); 16260eaf4defSAlexey Kardashevskiy if (tbl) { 16270eaf4defSAlexey Kardashevskiy pnv_pci_unlink_table_and_group(tbl, &pe->table_group); 1628e5afdf9dSAlexey Kardashevskiy iommu_tce_table_put(tbl); 16290eaf4defSAlexey Kardashevskiy } 1630184cd4a3SBenjamin Herrenschmidt } 1631184cd4a3SBenjamin Herrenschmidt 163243cb60abSAlexey Kardashevskiy static long pnv_pci_ioda2_set_window(struct iommu_table_group *table_group, 163343cb60abSAlexey Kardashevskiy int num, struct iommu_table *tbl) 163443cb60abSAlexey Kardashevskiy { 163543cb60abSAlexey Kardashevskiy struct pnv_ioda_pe *pe = container_of(table_group, struct pnv_ioda_pe, 163643cb60abSAlexey Kardashevskiy table_group); 163743cb60abSAlexey Kardashevskiy struct pnv_phb *phb = pe->phb; 163843cb60abSAlexey Kardashevskiy int64_t rc; 1639bbb845c4SAlexey Kardashevskiy const unsigned long size = tbl->it_indirect_levels ? 1640bbb845c4SAlexey Kardashevskiy tbl->it_level_size : tbl->it_size; 164143cb60abSAlexey Kardashevskiy const __u64 start_addr = tbl->it_offset << tbl->it_page_shift; 164243cb60abSAlexey Kardashevskiy const __u64 win_size = tbl->it_size << tbl->it_page_shift; 164343cb60abSAlexey Kardashevskiy 16441e496391SJoe Perches pe_info(pe, "Setting up window#%d %llx..%llx pg=%lx\n", 16451e496391SJoe Perches num, start_addr, start_addr + win_size - 1, 164643cb60abSAlexey Kardashevskiy IOMMU_PAGE_SIZE(tbl)); 164743cb60abSAlexey Kardashevskiy 164843cb60abSAlexey Kardashevskiy /* 164943cb60abSAlexey Kardashevskiy * Map TCE table through TVT. The TVE index is the PE number 165043cb60abSAlexey Kardashevskiy * shifted by 1 bit for 32-bits DMA space. 165143cb60abSAlexey Kardashevskiy */ 165243cb60abSAlexey Kardashevskiy rc = opal_pci_map_pe_dma_window(phb->opal_id, 165343cb60abSAlexey Kardashevskiy pe->pe_number, 16544793d65dSAlexey Kardashevskiy (pe->pe_number << 1) + num, 1655bbb845c4SAlexey Kardashevskiy tbl->it_indirect_levels + 1, 165643cb60abSAlexey Kardashevskiy __pa(tbl->it_base), 1657bbb845c4SAlexey Kardashevskiy size << 3, 165843cb60abSAlexey Kardashevskiy IOMMU_PAGE_SIZE(tbl)); 165943cb60abSAlexey Kardashevskiy if (rc) { 16601e496391SJoe Perches pe_err(pe, "Failed to configure TCE table, err %lld\n", rc); 166143cb60abSAlexey Kardashevskiy return rc; 166243cb60abSAlexey Kardashevskiy } 166343cb60abSAlexey Kardashevskiy 166443cb60abSAlexey Kardashevskiy pnv_pci_link_table_and_group(phb->hose->node, num, 166543cb60abSAlexey Kardashevskiy tbl, &pe->table_group); 1666ed7d9a1dSMichael Ellerman pnv_pci_ioda2_tce_invalidate_pe(pe); 166743cb60abSAlexey Kardashevskiy 166843cb60abSAlexey Kardashevskiy return 0; 166943cb60abSAlexey Kardashevskiy } 167043cb60abSAlexey Kardashevskiy 1671c498a4f9SChristoph Hellwig static void pnv_pci_ioda2_set_bypass(struct pnv_ioda_pe *pe, bool enable) 1672cd15b048SBenjamin Herrenschmidt { 1673cd15b048SBenjamin Herrenschmidt uint16_t window_id = (pe->pe_number << 1 ) + 1; 1674cd15b048SBenjamin Herrenschmidt int64_t rc; 1675cd15b048SBenjamin Herrenschmidt 1676cd15b048SBenjamin Herrenschmidt pe_info(pe, "%sabling 64-bit DMA bypass\n", enable ? "En" : "Dis"); 1677cd15b048SBenjamin Herrenschmidt if (enable) { 1678cd15b048SBenjamin Herrenschmidt phys_addr_t top = memblock_end_of_DRAM(); 1679cd15b048SBenjamin Herrenschmidt 1680cd15b048SBenjamin Herrenschmidt top = roundup_pow_of_two(top); 1681cd15b048SBenjamin Herrenschmidt rc = opal_pci_map_pe_dma_window_real(pe->phb->opal_id, 1682cd15b048SBenjamin Herrenschmidt pe->pe_number, 1683cd15b048SBenjamin Herrenschmidt window_id, 1684cd15b048SBenjamin Herrenschmidt pe->tce_bypass_base, 1685cd15b048SBenjamin Herrenschmidt top); 1686cd15b048SBenjamin Herrenschmidt } else { 1687cd15b048SBenjamin Herrenschmidt rc = opal_pci_map_pe_dma_window_real(pe->phb->opal_id, 1688cd15b048SBenjamin Herrenschmidt pe->pe_number, 1689cd15b048SBenjamin Herrenschmidt window_id, 1690cd15b048SBenjamin Herrenschmidt pe->tce_bypass_base, 1691cd15b048SBenjamin Herrenschmidt 0); 1692cd15b048SBenjamin Herrenschmidt } 1693cd15b048SBenjamin Herrenschmidt if (rc) 1694cd15b048SBenjamin Herrenschmidt pe_err(pe, "OPAL error %lld configuring bypass window\n", rc); 1695cd15b048SBenjamin Herrenschmidt else 1696cd15b048SBenjamin Herrenschmidt pe->tce_bypass_enabled = enable; 1697cd15b048SBenjamin Herrenschmidt } 1698cd15b048SBenjamin Herrenschmidt 16994793d65dSAlexey Kardashevskiy static long pnv_pci_ioda2_create_table(struct iommu_table_group *table_group, 17004793d65dSAlexey Kardashevskiy int num, __u32 page_shift, __u64 window_size, __u32 levels, 1701090bad39SAlexey Kardashevskiy bool alloc_userspace_copy, struct iommu_table **ptbl) 17024793d65dSAlexey Kardashevskiy { 17034793d65dSAlexey Kardashevskiy struct pnv_ioda_pe *pe = container_of(table_group, struct pnv_ioda_pe, 17044793d65dSAlexey Kardashevskiy table_group); 17054793d65dSAlexey Kardashevskiy int nid = pe->phb->hose->node; 17064793d65dSAlexey Kardashevskiy __u64 bus_offset = num ? pe->tce_bypass_base : table_group->tce32_start; 17074793d65dSAlexey Kardashevskiy long ret; 17084793d65dSAlexey Kardashevskiy struct iommu_table *tbl; 17094793d65dSAlexey Kardashevskiy 17104793d65dSAlexey Kardashevskiy tbl = pnv_pci_table_alloc(nid); 17114793d65dSAlexey Kardashevskiy if (!tbl) 17124793d65dSAlexey Kardashevskiy return -ENOMEM; 17134793d65dSAlexey Kardashevskiy 171411edf116SAlexey Kardashevskiy tbl->it_ops = &pnv_ioda2_iommu_ops; 171511edf116SAlexey Kardashevskiy 17164793d65dSAlexey Kardashevskiy ret = pnv_pci_ioda2_table_alloc_pages(nid, 17174793d65dSAlexey Kardashevskiy bus_offset, page_shift, window_size, 1718090bad39SAlexey Kardashevskiy levels, alloc_userspace_copy, tbl); 17194793d65dSAlexey Kardashevskiy if (ret) { 1720e5afdf9dSAlexey Kardashevskiy iommu_tce_table_put(tbl); 17214793d65dSAlexey Kardashevskiy return ret; 17224793d65dSAlexey Kardashevskiy } 17234793d65dSAlexey Kardashevskiy 17244793d65dSAlexey Kardashevskiy *ptbl = tbl; 17254793d65dSAlexey Kardashevskiy 17264793d65dSAlexey Kardashevskiy return 0; 17274793d65dSAlexey Kardashevskiy } 17284793d65dSAlexey Kardashevskiy 172946d3e1e1SAlexey Kardashevskiy static long pnv_pci_ioda2_setup_default_config(struct pnv_ioda_pe *pe) 173046d3e1e1SAlexey Kardashevskiy { 173146d3e1e1SAlexey Kardashevskiy struct iommu_table *tbl = NULL; 173246d3e1e1SAlexey Kardashevskiy long rc; 1733201ed7f3SAlexey Kardashevskiy unsigned long res_start, res_end; 173446d3e1e1SAlexey Kardashevskiy 1735bb005455SNishanth Aravamudan /* 1736fa144869SNishanth Aravamudan * crashkernel= specifies the kdump kernel's maximum memory at 1737fa144869SNishanth Aravamudan * some offset and there is no guaranteed the result is a power 1738fa144869SNishanth Aravamudan * of 2, which will cause errors later. 1739fa144869SNishanth Aravamudan */ 1740fa144869SNishanth Aravamudan const u64 max_memory = __rounddown_pow_of_two(memory_hotplug_max()); 1741fa144869SNishanth Aravamudan 1742fa144869SNishanth Aravamudan /* 1743bb005455SNishanth Aravamudan * In memory constrained environments, e.g. kdump kernel, the 1744bb005455SNishanth Aravamudan * DMA window can be larger than available memory, which will 1745bb005455SNishanth Aravamudan * cause errors later. 1746bb005455SNishanth Aravamudan */ 1747201ed7f3SAlexey Kardashevskiy const u64 maxblock = 1UL << (PAGE_SHIFT + MAX_ORDER - 1); 1748bb005455SNishanth Aravamudan 1749201ed7f3SAlexey Kardashevskiy /* 1750201ed7f3SAlexey Kardashevskiy * We create the default window as big as we can. The constraint is 1751201ed7f3SAlexey Kardashevskiy * the max order of allocation possible. The TCE table is likely to 1752201ed7f3SAlexey Kardashevskiy * end up being multilevel and with on-demand allocation in place, 1753201ed7f3SAlexey Kardashevskiy * the initial use is not going to be huge as the default window aims 1754201ed7f3SAlexey Kardashevskiy * to support crippled devices (i.e. not fully 64bit DMAble) only. 1755201ed7f3SAlexey Kardashevskiy */ 1756201ed7f3SAlexey Kardashevskiy /* iommu_table::it_map uses 1 bit per IOMMU page, hence 8 */ 1757201ed7f3SAlexey Kardashevskiy const u64 window_size = min((maxblock * 8) << PAGE_SHIFT, max_memory); 1758201ed7f3SAlexey Kardashevskiy /* Each TCE level cannot exceed maxblock so go multilevel if needed */ 1759201ed7f3SAlexey Kardashevskiy unsigned long tces_order = ilog2(window_size >> PAGE_SHIFT); 1760201ed7f3SAlexey Kardashevskiy unsigned long tcelevel_order = ilog2(maxblock >> 3); 1761201ed7f3SAlexey Kardashevskiy unsigned int levels = tces_order / tcelevel_order; 1762201ed7f3SAlexey Kardashevskiy 1763201ed7f3SAlexey Kardashevskiy if (tces_order % tcelevel_order) 1764201ed7f3SAlexey Kardashevskiy levels += 1; 1765201ed7f3SAlexey Kardashevskiy /* 1766201ed7f3SAlexey Kardashevskiy * We try to stick to default levels (which is >1 at the moment) in 1767201ed7f3SAlexey Kardashevskiy * order to save memory by relying on on-demain TCE level allocation. 1768201ed7f3SAlexey Kardashevskiy */ 1769201ed7f3SAlexey Kardashevskiy levels = max_t(unsigned int, levels, POWERNV_IOMMU_DEFAULT_LEVELS); 1770201ed7f3SAlexey Kardashevskiy 1771201ed7f3SAlexey Kardashevskiy rc = pnv_pci_ioda2_create_table(&pe->table_group, 0, PAGE_SHIFT, 1772201ed7f3SAlexey Kardashevskiy window_size, levels, false, &tbl); 177346d3e1e1SAlexey Kardashevskiy if (rc) { 177446d3e1e1SAlexey Kardashevskiy pe_err(pe, "Failed to create 32-bit TCE table, err %ld", 177546d3e1e1SAlexey Kardashevskiy rc); 177646d3e1e1SAlexey Kardashevskiy return rc; 177746d3e1e1SAlexey Kardashevskiy } 177846d3e1e1SAlexey Kardashevskiy 1779201ed7f3SAlexey Kardashevskiy /* We use top part of 32bit space for MMIO so exclude it from DMA */ 1780201ed7f3SAlexey Kardashevskiy res_start = 0; 1781201ed7f3SAlexey Kardashevskiy res_end = 0; 1782201ed7f3SAlexey Kardashevskiy if (window_size > pe->phb->ioda.m32_pci_base) { 1783201ed7f3SAlexey Kardashevskiy res_start = pe->phb->ioda.m32_pci_base >> tbl->it_page_shift; 1784201ed7f3SAlexey Kardashevskiy res_end = min(window_size, SZ_4G) >> tbl->it_page_shift; 1785201ed7f3SAlexey Kardashevskiy } 178646d3e1e1SAlexey Kardashevskiy 1787d73b46c3SAlexey Kardashevskiy tbl->it_index = (pe->phb->hose->global_number << 16) | pe->pe_number; 17884be518d8SAlexey Kardashevskiy if (iommu_init_table(tbl, pe->phb->hose->node, res_start, res_end)) 178946d3e1e1SAlexey Kardashevskiy rc = pnv_pci_ioda2_set_window(&pe->table_group, 0, tbl); 17904be518d8SAlexey Kardashevskiy else 17914be518d8SAlexey Kardashevskiy rc = -ENOMEM; 179246d3e1e1SAlexey Kardashevskiy if (rc) { 17934be518d8SAlexey Kardashevskiy pe_err(pe, "Failed to configure 32-bit TCE table, err %ld\n", rc); 1794e5afdf9dSAlexey Kardashevskiy iommu_tce_table_put(tbl); 17954be518d8SAlexey Kardashevskiy tbl = NULL; /* This clears iommu_table_base below */ 179646d3e1e1SAlexey Kardashevskiy } 179746d3e1e1SAlexey Kardashevskiy if (!pnv_iommu_bypass_disabled) 179846d3e1e1SAlexey Kardashevskiy pnv_pci_ioda2_set_bypass(pe, true); 179946d3e1e1SAlexey Kardashevskiy 18005636427dSAlexey Kardashevskiy /* 18015636427dSAlexey Kardashevskiy * Set table base for the case of IOMMU DMA use. Usually this is done 18025636427dSAlexey Kardashevskiy * from dma_dev_setup() which is not called when a device is returned 18035636427dSAlexey Kardashevskiy * from VFIO so do it here. 18045636427dSAlexey Kardashevskiy */ 18055636427dSAlexey Kardashevskiy if (pe->pdev) 18065636427dSAlexey Kardashevskiy set_iommu_table_base(&pe->pdev->dev, tbl); 18075636427dSAlexey Kardashevskiy 180846d3e1e1SAlexey Kardashevskiy return 0; 180946d3e1e1SAlexey Kardashevskiy } 181046d3e1e1SAlexey Kardashevskiy 1811b5926430SAlexey Kardashevskiy static long pnv_pci_ioda2_unset_window(struct iommu_table_group *table_group, 1812b5926430SAlexey Kardashevskiy int num) 1813b5926430SAlexey Kardashevskiy { 1814b5926430SAlexey Kardashevskiy struct pnv_ioda_pe *pe = container_of(table_group, struct pnv_ioda_pe, 1815b5926430SAlexey Kardashevskiy table_group); 1816b5926430SAlexey Kardashevskiy struct pnv_phb *phb = pe->phb; 1817b5926430SAlexey Kardashevskiy long ret; 1818b5926430SAlexey Kardashevskiy 1819b5926430SAlexey Kardashevskiy pe_info(pe, "Removing DMA window #%d\n", num); 1820b5926430SAlexey Kardashevskiy 1821b5926430SAlexey Kardashevskiy ret = opal_pci_map_pe_dma_window(phb->opal_id, pe->pe_number, 1822b5926430SAlexey Kardashevskiy (pe->pe_number << 1) + num, 1823b5926430SAlexey Kardashevskiy 0/* levels */, 0/* table address */, 1824b5926430SAlexey Kardashevskiy 0/* table size */, 0/* page size */); 1825b5926430SAlexey Kardashevskiy if (ret) 1826b5926430SAlexey Kardashevskiy pe_warn(pe, "Unmapping failed, ret = %ld\n", ret); 1827b5926430SAlexey Kardashevskiy else 1828ed7d9a1dSMichael Ellerman pnv_pci_ioda2_tce_invalidate_pe(pe); 1829b5926430SAlexey Kardashevskiy 1830b5926430SAlexey Kardashevskiy pnv_pci_unlink_table_and_group(table_group->tables[num], table_group); 1831b5926430SAlexey Kardashevskiy 1832b5926430SAlexey Kardashevskiy return ret; 1833b5926430SAlexey Kardashevskiy } 1834b5926430SAlexey Kardashevskiy 1835f87a8864SAlexey Kardashevskiy #ifdef CONFIG_IOMMU_API 18360bd97167SAlexey Kardashevskiy unsigned long pnv_pci_ioda2_get_table_size(__u32 page_shift, 183700547193SAlexey Kardashevskiy __u64 window_size, __u32 levels) 183800547193SAlexey Kardashevskiy { 183900547193SAlexey Kardashevskiy unsigned long bytes = 0; 184000547193SAlexey Kardashevskiy const unsigned window_shift = ilog2(window_size); 184100547193SAlexey Kardashevskiy unsigned entries_shift = window_shift - page_shift; 184200547193SAlexey Kardashevskiy unsigned table_shift = entries_shift + 3; 184300547193SAlexey Kardashevskiy unsigned long tce_table_size = max(0x1000UL, 1UL << table_shift); 184400547193SAlexey Kardashevskiy unsigned long direct_table_size; 184500547193SAlexey Kardashevskiy 184600547193SAlexey Kardashevskiy if (!levels || (levels > POWERNV_IOMMU_MAX_LEVELS) || 184700547193SAlexey Kardashevskiy !is_power_of_2(window_size)) 184800547193SAlexey Kardashevskiy return 0; 184900547193SAlexey Kardashevskiy 185000547193SAlexey Kardashevskiy /* Calculate a direct table size from window_size and levels */ 185100547193SAlexey Kardashevskiy entries_shift = (entries_shift + levels - 1) / levels; 185200547193SAlexey Kardashevskiy table_shift = entries_shift + 3; 185300547193SAlexey Kardashevskiy table_shift = max_t(unsigned, table_shift, PAGE_SHIFT); 185400547193SAlexey Kardashevskiy direct_table_size = 1UL << table_shift; 185500547193SAlexey Kardashevskiy 185600547193SAlexey Kardashevskiy for ( ; levels; --levels) { 1857b7115316SChristophe Leroy bytes += ALIGN(tce_table_size, direct_table_size); 185800547193SAlexey Kardashevskiy 185900547193SAlexey Kardashevskiy tce_table_size /= direct_table_size; 186000547193SAlexey Kardashevskiy tce_table_size <<= 3; 1861e49a6a21SAlexey Kardashevskiy tce_table_size = max_t(unsigned long, 1862e49a6a21SAlexey Kardashevskiy tce_table_size, direct_table_size); 186300547193SAlexey Kardashevskiy } 186400547193SAlexey Kardashevskiy 1865090bad39SAlexey Kardashevskiy return bytes + bytes; /* one for HW table, one for userspace copy */ 1866090bad39SAlexey Kardashevskiy } 1867090bad39SAlexey Kardashevskiy 1868090bad39SAlexey Kardashevskiy static long pnv_pci_ioda2_create_table_userspace( 1869090bad39SAlexey Kardashevskiy struct iommu_table_group *table_group, 1870090bad39SAlexey Kardashevskiy int num, __u32 page_shift, __u64 window_size, __u32 levels, 1871090bad39SAlexey Kardashevskiy struct iommu_table **ptbl) 1872090bad39SAlexey Kardashevskiy { 187311f5acceSAlexey Kardashevskiy long ret = pnv_pci_ioda2_create_table(table_group, 1874090bad39SAlexey Kardashevskiy num, page_shift, window_size, levels, true, ptbl); 187511f5acceSAlexey Kardashevskiy 187611f5acceSAlexey Kardashevskiy if (!ret) 187711f5acceSAlexey Kardashevskiy (*ptbl)->it_allocated_size = pnv_pci_ioda2_get_table_size( 187811f5acceSAlexey Kardashevskiy page_shift, window_size, levels); 187911f5acceSAlexey Kardashevskiy return ret; 188000547193SAlexey Kardashevskiy } 188100547193SAlexey Kardashevskiy 1882e3417faeSOliver O'Halloran static void pnv_ioda_setup_bus_dma(struct pnv_ioda_pe *pe, struct pci_bus *bus) 1883e3417faeSOliver O'Halloran { 1884e3417faeSOliver O'Halloran struct pci_dev *dev; 1885e3417faeSOliver O'Halloran 1886e3417faeSOliver O'Halloran list_for_each_entry(dev, &bus->devices, bus_list) { 1887e3417faeSOliver O'Halloran set_iommu_table_base(&dev->dev, pe->table_group.tables[0]); 1888e3417faeSOliver O'Halloran dev->dev.archdata.dma_offset = pe->tce_bypass_base; 1889e3417faeSOliver O'Halloran 1890e3417faeSOliver O'Halloran if ((pe->flags & PNV_IODA_PE_BUS_ALL) && dev->subordinate) 1891e3417faeSOliver O'Halloran pnv_ioda_setup_bus_dma(pe, dev->subordinate); 1892e3417faeSOliver O'Halloran } 1893e3417faeSOliver O'Halloran } 1894e3417faeSOliver O'Halloran 1895*9d67c943SAlexey Kardashevskiy static long pnv_ioda2_take_ownership(struct iommu_table_group *table_group) 1896cd15b048SBenjamin Herrenschmidt { 1897f87a8864SAlexey Kardashevskiy struct pnv_ioda_pe *pe = container_of(table_group, struct pnv_ioda_pe, 1898f87a8864SAlexey Kardashevskiy table_group); 189946d3e1e1SAlexey Kardashevskiy /* Store @tbl as pnv_pci_ioda2_unset_window() resets it */ 190046d3e1e1SAlexey Kardashevskiy struct iommu_table *tbl = pe->table_group.tables[0]; 1901cd15b048SBenjamin Herrenschmidt 1902f87a8864SAlexey Kardashevskiy pnv_pci_ioda2_set_bypass(pe, false); 190346d3e1e1SAlexey Kardashevskiy pnv_pci_ioda2_unset_window(&pe->table_group, 0); 1904db08e1d5SAlexey Kardashevskiy if (pe->pbus) 19055eada8a3SAlexey Kardashevskiy pnv_ioda_setup_bus_dma(pe, pe->pbus); 19065636427dSAlexey Kardashevskiy else if (pe->pdev) 19075636427dSAlexey Kardashevskiy set_iommu_table_base(&pe->pdev->dev, NULL); 1908e5afdf9dSAlexey Kardashevskiy iommu_tce_table_put(tbl); 1909*9d67c943SAlexey Kardashevskiy 1910*9d67c943SAlexey Kardashevskiy return 0; 1911cd15b048SBenjamin Herrenschmidt } 1912cd15b048SBenjamin Herrenschmidt 1913f87a8864SAlexey Kardashevskiy static void pnv_ioda2_release_ownership(struct iommu_table_group *table_group) 1914f87a8864SAlexey Kardashevskiy { 1915f87a8864SAlexey Kardashevskiy struct pnv_ioda_pe *pe = container_of(table_group, struct pnv_ioda_pe, 1916f87a8864SAlexey Kardashevskiy table_group); 1917f87a8864SAlexey Kardashevskiy 191846d3e1e1SAlexey Kardashevskiy pnv_pci_ioda2_setup_default_config(pe); 1919db08e1d5SAlexey Kardashevskiy if (pe->pbus) 19205eada8a3SAlexey Kardashevskiy pnv_ioda_setup_bus_dma(pe, pe->pbus); 1921f87a8864SAlexey Kardashevskiy } 1922f87a8864SAlexey Kardashevskiy 1923f87a8864SAlexey Kardashevskiy static struct iommu_table_group_ops pnv_pci_ioda2_ops = { 192400547193SAlexey Kardashevskiy .get_table_size = pnv_pci_ioda2_get_table_size, 1925090bad39SAlexey Kardashevskiy .create_table = pnv_pci_ioda2_create_table_userspace, 19264793d65dSAlexey Kardashevskiy .set_window = pnv_pci_ioda2_set_window, 19274793d65dSAlexey Kardashevskiy .unset_window = pnv_pci_ioda2_unset_window, 1928f87a8864SAlexey Kardashevskiy .take_ownership = pnv_ioda2_take_ownership, 1929f87a8864SAlexey Kardashevskiy .release_ownership = pnv_ioda2_release_ownership, 1930f87a8864SAlexey Kardashevskiy }; 1931f87a8864SAlexey Kardashevskiy #endif 1932f87a8864SAlexey Kardashevskiy 193337b59ef0SOliver O'Halloran void pnv_pci_ioda2_setup_dma_pe(struct pnv_phb *phb, 1934373f5657SGavin Shan struct pnv_ioda_pe *pe) 1935373f5657SGavin Shan { 1936373f5657SGavin Shan int64_t rc; 1937373f5657SGavin Shan 1938f87a8864SAlexey Kardashevskiy /* TVE #1 is selected by PCI address bit 59 */ 1939f87a8864SAlexey Kardashevskiy pe->tce_bypass_base = 1ull << 59; 1940f87a8864SAlexey Kardashevskiy 1941373f5657SGavin Shan /* The PE will reserve all possible 32-bits space */ 1942373f5657SGavin Shan pe_info(pe, "Setting up 32-bit TCE table at 0..%08x\n", 1943aca6913fSAlexey Kardashevskiy phb->ioda.m32_pci_base); 1944373f5657SGavin Shan 1945e5aad1e6SAlexey Kardashevskiy /* Setup linux iommu table */ 19464793d65dSAlexey Kardashevskiy pe->table_group.tce32_start = 0; 19474793d65dSAlexey Kardashevskiy pe->table_group.tce32_size = phb->ioda.m32_pci_base; 19484793d65dSAlexey Kardashevskiy pe->table_group.max_dynamic_windows_supported = 19494793d65dSAlexey Kardashevskiy IOMMU_TABLE_GROUP_MAX_TABLES; 19504793d65dSAlexey Kardashevskiy pe->table_group.max_levels = POWERNV_IOMMU_MAX_LEVELS; 19517ef73cd3SAlexey Kardashevskiy pe->table_group.pgsizes = pnv_ioda_parse_tce_sizes(phb); 1952e5aad1e6SAlexey Kardashevskiy 195346d3e1e1SAlexey Kardashevskiy rc = pnv_pci_ioda2_setup_default_config(pe); 1954801846d1SGavin Shan if (rc) 195546d3e1e1SAlexey Kardashevskiy return; 195646d3e1e1SAlexey Kardashevskiy 19579b9408c5SOliver O'Halloran #ifdef CONFIG_IOMMU_API 19589b9408c5SOliver O'Halloran pe->table_group.ops = &pnv_pci_ioda2_ops; 19599b9408c5SOliver O'Halloran iommu_register_group(&pe->table_group, phb->hose->global_number, 19609b9408c5SOliver O'Halloran pe->pe_number); 19619b9408c5SOliver O'Halloran #endif 196201e12629SOliver O'Halloran pe->dma_setup_done = true; 1963373f5657SGavin Shan } 1964373f5657SGavin Shan 1965c325712bSCédric Le Goater /* 1966c325712bSCédric Le Goater * Called from KVM in real mode to EOI passthru interrupts. The ICP 1967c325712bSCédric Le Goater * EOI is handled directly in KVM in kvmppc_deliver_irq_passthru(). 1968c325712bSCédric Le Goater * 1969c325712bSCédric Le Goater * The IRQ data is mapped in the PCI-MSI domain and the EOI OPAL call 1970c325712bSCédric Le Goater * needs an HW IRQ number mapped in the XICS IRQ domain. The HW IRQ 1971c325712bSCédric Le Goater * numbers of the in-the-middle MSI domain are vector numbers and it's 1972c325712bSCédric Le Goater * good enough for OPAL. Use that. 1973c325712bSCédric Le Goater */ 1974c325712bSCédric Le Goater int64_t pnv_opal_pci_msi_eoi(struct irq_data *d) 1975137436c9SGavin Shan { 1976c325712bSCédric Le Goater struct pci_controller *hose = irq_data_get_irq_chip_data(d->parent_data); 1977c325712bSCédric Le Goater struct pnv_phb *phb = hose->private_data; 1978137436c9SGavin Shan 1979c325712bSCédric Le Goater return opal_pci_msi_eoi(phb->opal_id, d->parent_data->hwirq); 19804ee11c1aSSuresh Warrier } 19814ee11c1aSSuresh Warrier 19825cd69651SCédric Le Goater /* 19835cd69651SCédric Le Goater * The IRQ data is mapped in the XICS domain, with OPAL HW IRQ numbers 19845cd69651SCédric Le Goater */ 19854ee11c1aSSuresh Warrier static void pnv_ioda2_msi_eoi(struct irq_data *d) 19864ee11c1aSSuresh Warrier { 19874ee11c1aSSuresh Warrier int64_t rc; 19884ee11c1aSSuresh Warrier unsigned int hw_irq = (unsigned int)irqd_to_hwirq(d); 19895cd69651SCédric Le Goater struct pci_controller *hose = irq_data_get_irq_chip_data(d); 19905cd69651SCédric Le Goater struct pnv_phb *phb = hose->private_data; 19914ee11c1aSSuresh Warrier 19925cd69651SCédric Le Goater rc = opal_pci_msi_eoi(phb->opal_id, hw_irq); 1993137436c9SGavin Shan WARN_ON_ONCE(rc); 1994137436c9SGavin Shan 1995137436c9SGavin Shan icp_native_eoi(d); 1996137436c9SGavin Shan } 1997137436c9SGavin Shan 19985cd69651SCédric Le Goater /* P8/CXL only */ 1999f456834aSIan Munsie void pnv_set_msi_irq_chip(struct pnv_phb *phb, unsigned int virq) 2000fd9a1c26SIan Munsie { 2001fd9a1c26SIan Munsie struct irq_data *idata; 2002fd9a1c26SIan Munsie struct irq_chip *ichip; 2003fd9a1c26SIan Munsie 2004fb111334SBenjamin Herrenschmidt /* The MSI EOI OPAL call is only needed on PHB3 */ 2005fb111334SBenjamin Herrenschmidt if (phb->model != PNV_PHB_MODEL_PHB3) 2006fd9a1c26SIan Munsie return; 2007fd9a1c26SIan Munsie 2008fd9a1c26SIan Munsie if (!phb->ioda.irq_chip_init) { 2009fd9a1c26SIan Munsie /* 2010fd9a1c26SIan Munsie * First time we setup an MSI IRQ, we need to setup the 2011fd9a1c26SIan Munsie * corresponding IRQ chip to route correctly. 2012fd9a1c26SIan Munsie */ 2013fd9a1c26SIan Munsie idata = irq_get_irq_data(virq); 2014fd9a1c26SIan Munsie ichip = irq_data_get_irq_chip(idata); 2015fd9a1c26SIan Munsie phb->ioda.irq_chip_init = 1; 2016fd9a1c26SIan Munsie phb->ioda.irq_chip = *ichip; 2017fd9a1c26SIan Munsie phb->ioda.irq_chip.irq_eoi = pnv_ioda2_msi_eoi; 2018fd9a1c26SIan Munsie } 2019fd9a1c26SIan Munsie irq_set_chip(virq, &phb->ioda.irq_chip); 20205cd69651SCédric Le Goater irq_set_chip_data(virq, phb->hose); 2021fd9a1c26SIan Munsie } 2022fd9a1c26SIan Munsie 2023ba418a02SCédric Le Goater static struct irq_chip pnv_pci_msi_irq_chip; 2024ba418a02SCédric Le Goater 20254ee11c1aSSuresh Warrier /* 20264ee11c1aSSuresh Warrier * Returns true iff chip is something that we could call 20274ee11c1aSSuresh Warrier * pnv_opal_pci_msi_eoi for. 20284ee11c1aSSuresh Warrier */ 20294ee11c1aSSuresh Warrier bool is_pnv_opal_msi(struct irq_chip *chip) 20304ee11c1aSSuresh Warrier { 2031f1a377f8SCédric Le Goater return chip == &pnv_pci_msi_irq_chip; 20324ee11c1aSSuresh Warrier } 20334ee11c1aSSuresh Warrier EXPORT_SYMBOL_GPL(is_pnv_opal_msi); 20344ee11c1aSSuresh Warrier 20352c50d7e9SCédric Le Goater static int __pnv_pci_ioda_msi_setup(struct pnv_phb *phb, struct pci_dev *dev, 20362c50d7e9SCédric Le Goater unsigned int xive_num, 2037137436c9SGavin Shan unsigned int is_64, struct msi_msg *msg) 2038184cd4a3SBenjamin Herrenschmidt { 2039184cd4a3SBenjamin Herrenschmidt struct pnv_ioda_pe *pe = pnv_ioda_get_pe(dev); 20403a1a4661SBenjamin Herrenschmidt __be32 data; 2041184cd4a3SBenjamin Herrenschmidt int rc; 2042184cd4a3SBenjamin Herrenschmidt 20432c50d7e9SCédric Le Goater dev_dbg(&dev->dev, "%s: setup %s-bit MSI for vector #%d\n", __func__, 20442c50d7e9SCédric Le Goater is_64 ? "64" : "32", xive_num); 20452c50d7e9SCédric Le Goater 2046184cd4a3SBenjamin Herrenschmidt /* No PE assigned ? bail out ... no MSI for you ! */ 2047184cd4a3SBenjamin Herrenschmidt if (pe == NULL) 2048184cd4a3SBenjamin Herrenschmidt return -ENXIO; 2049184cd4a3SBenjamin Herrenschmidt 2050184cd4a3SBenjamin Herrenschmidt /* Check if we have an MVE */ 2051184cd4a3SBenjamin Herrenschmidt if (pe->mve_number < 0) 2052184cd4a3SBenjamin Herrenschmidt return -ENXIO; 2053184cd4a3SBenjamin Herrenschmidt 2054b72c1f65SBenjamin Herrenschmidt /* Force 32-bit MSI on some broken devices */ 205536074381SBenjamin Herrenschmidt if (dev->no_64bit_msi) 2056b72c1f65SBenjamin Herrenschmidt is_64 = 0; 2057b72c1f65SBenjamin Herrenschmidt 2058184cd4a3SBenjamin Herrenschmidt /* Assign XIVE to PE */ 2059184cd4a3SBenjamin Herrenschmidt rc = opal_pci_set_xive_pe(phb->opal_id, pe->pe_number, xive_num); 2060184cd4a3SBenjamin Herrenschmidt if (rc) { 2061184cd4a3SBenjamin Herrenschmidt pr_warn("%s: OPAL error %d setting XIVE %d PE\n", 2062184cd4a3SBenjamin Herrenschmidt pci_name(dev), rc, xive_num); 2063184cd4a3SBenjamin Herrenschmidt return -EIO; 2064184cd4a3SBenjamin Herrenschmidt } 2065184cd4a3SBenjamin Herrenschmidt 2066184cd4a3SBenjamin Herrenschmidt if (is_64) { 20673a1a4661SBenjamin Herrenschmidt __be64 addr64; 20683a1a4661SBenjamin Herrenschmidt 2069184cd4a3SBenjamin Herrenschmidt rc = opal_get_msi_64(phb->opal_id, pe->mve_number, xive_num, 1, 2070184cd4a3SBenjamin Herrenschmidt &addr64, &data); 2071184cd4a3SBenjamin Herrenschmidt if (rc) { 2072184cd4a3SBenjamin Herrenschmidt pr_warn("%s: OPAL error %d getting 64-bit MSI data\n", 2073184cd4a3SBenjamin Herrenschmidt pci_name(dev), rc); 2074184cd4a3SBenjamin Herrenschmidt return -EIO; 2075184cd4a3SBenjamin Herrenschmidt } 20763a1a4661SBenjamin Herrenschmidt msg->address_hi = be64_to_cpu(addr64) >> 32; 20773a1a4661SBenjamin Herrenschmidt msg->address_lo = be64_to_cpu(addr64) & 0xfffffffful; 2078184cd4a3SBenjamin Herrenschmidt } else { 20793a1a4661SBenjamin Herrenschmidt __be32 addr32; 20803a1a4661SBenjamin Herrenschmidt 2081184cd4a3SBenjamin Herrenschmidt rc = opal_get_msi_32(phb->opal_id, pe->mve_number, xive_num, 1, 2082184cd4a3SBenjamin Herrenschmidt &addr32, &data); 2083184cd4a3SBenjamin Herrenschmidt if (rc) { 2084184cd4a3SBenjamin Herrenschmidt pr_warn("%s: OPAL error %d getting 32-bit MSI data\n", 2085184cd4a3SBenjamin Herrenschmidt pci_name(dev), rc); 2086184cd4a3SBenjamin Herrenschmidt return -EIO; 2087184cd4a3SBenjamin Herrenschmidt } 2088184cd4a3SBenjamin Herrenschmidt msg->address_hi = 0; 20893a1a4661SBenjamin Herrenschmidt msg->address_lo = be32_to_cpu(addr32); 2090184cd4a3SBenjamin Herrenschmidt } 20913a1a4661SBenjamin Herrenschmidt msg->data = be32_to_cpu(data); 2092184cd4a3SBenjamin Herrenschmidt 20932c50d7e9SCédric Le Goater return 0; 20942c50d7e9SCédric Le Goater } 20952c50d7e9SCédric Le Goater 20960fcfe224SCédric Le Goater /* 20970fcfe224SCédric Le Goater * The msi_free() op is called before irq_domain_free_irqs_top() when 20980fcfe224SCédric Le Goater * the handler data is still available. Use that to clear the XIVE 20990fcfe224SCédric Le Goater * controller. 21000fcfe224SCédric Le Goater */ 21010fcfe224SCédric Le Goater static void pnv_msi_ops_msi_free(struct irq_domain *domain, 21020fcfe224SCédric Le Goater struct msi_domain_info *info, 21030fcfe224SCédric Le Goater unsigned int irq) 21040fcfe224SCédric Le Goater { 21050fcfe224SCédric Le Goater if (xive_enabled()) 21060fcfe224SCédric Le Goater xive_irq_free_data(irq); 21070fcfe224SCédric Le Goater } 21080fcfe224SCédric Le Goater 21090fcfe224SCédric Le Goater static struct msi_domain_ops pnv_pci_msi_domain_ops = { 21100fcfe224SCédric Le Goater .msi_free = pnv_msi_ops_msi_free, 21110fcfe224SCédric Le Goater }; 21120fcfe224SCédric Le Goater 21130fcfe224SCédric Le Goater static void pnv_msi_shutdown(struct irq_data *d) 21140fcfe224SCédric Le Goater { 21150fcfe224SCédric Le Goater d = d->parent_data; 21160fcfe224SCédric Le Goater if (d->chip->irq_shutdown) 21170fcfe224SCédric Le Goater d->chip->irq_shutdown(d); 21180fcfe224SCédric Le Goater } 21190fcfe224SCédric Le Goater 21200fcfe224SCédric Le Goater static void pnv_msi_mask(struct irq_data *d) 21210fcfe224SCédric Le Goater { 21220fcfe224SCédric Le Goater pci_msi_mask_irq(d); 21230fcfe224SCédric Le Goater irq_chip_mask_parent(d); 21240fcfe224SCédric Le Goater } 21250fcfe224SCédric Le Goater 21260fcfe224SCédric Le Goater static void pnv_msi_unmask(struct irq_data *d) 21270fcfe224SCédric Le Goater { 21280fcfe224SCédric Le Goater pci_msi_unmask_irq(d); 21290fcfe224SCédric Le Goater irq_chip_unmask_parent(d); 21300fcfe224SCédric Le Goater } 21310fcfe224SCédric Le Goater 21320fcfe224SCédric Le Goater static struct irq_chip pnv_pci_msi_irq_chip = { 21330fcfe224SCédric Le Goater .name = "PNV-PCI-MSI", 21340fcfe224SCédric Le Goater .irq_shutdown = pnv_msi_shutdown, 21350fcfe224SCédric Le Goater .irq_mask = pnv_msi_mask, 21360fcfe224SCédric Le Goater .irq_unmask = pnv_msi_unmask, 21370fcfe224SCédric Le Goater .irq_eoi = irq_chip_eoi_parent, 21380fcfe224SCédric Le Goater }; 21390fcfe224SCédric Le Goater 21400fcfe224SCédric Le Goater static struct msi_domain_info pnv_msi_domain_info = { 21410fcfe224SCédric Le Goater .flags = (MSI_FLAG_USE_DEF_DOM_OPS | MSI_FLAG_USE_DEF_CHIP_OPS | 21420fcfe224SCédric Le Goater MSI_FLAG_MULTI_PCI_MSI | MSI_FLAG_PCI_MSIX), 21430fcfe224SCédric Le Goater .ops = &pnv_pci_msi_domain_ops, 21440fcfe224SCédric Le Goater .chip = &pnv_pci_msi_irq_chip, 21450fcfe224SCédric Le Goater }; 21460fcfe224SCédric Le Goater 21470fcfe224SCédric Le Goater static void pnv_msi_compose_msg(struct irq_data *d, struct msi_msg *msg) 21480fcfe224SCédric Le Goater { 21490fcfe224SCédric Le Goater struct msi_desc *entry = irq_data_get_msi_desc(d); 21500fcfe224SCédric Le Goater struct pci_dev *pdev = msi_desc_to_pci_dev(entry); 21510fcfe224SCédric Le Goater struct pci_controller *hose = irq_data_get_irq_chip_data(d); 21520fcfe224SCédric Le Goater struct pnv_phb *phb = hose->private_data; 21530fcfe224SCédric Le Goater int rc; 21540fcfe224SCédric Le Goater 21550fcfe224SCédric Le Goater rc = __pnv_pci_ioda_msi_setup(phb, pdev, d->hwirq, 2156e58f2259SThomas Gleixner entry->pci.msi_attrib.is_64, msg); 21570fcfe224SCédric Le Goater if (rc) 21580fcfe224SCédric Le Goater dev_err(&pdev->dev, "Failed to setup %s-bit MSI #%ld : %d\n", 2159e58f2259SThomas Gleixner entry->pci.msi_attrib.is_64 ? "64" : "32", d->hwirq, rc); 21600fcfe224SCédric Le Goater } 21610fcfe224SCédric Le Goater 2162bbb25af8SCédric Le Goater /* 2163bbb25af8SCédric Le Goater * The IRQ data is mapped in the MSI domain in which HW IRQ numbers 2164bbb25af8SCédric Le Goater * correspond to vector numbers. 2165bbb25af8SCédric Le Goater */ 2166bbb25af8SCédric Le Goater static void pnv_msi_eoi(struct irq_data *d) 2167bbb25af8SCédric Le Goater { 2168bbb25af8SCédric Le Goater struct pci_controller *hose = irq_data_get_irq_chip_data(d); 2169bbb25af8SCédric Le Goater struct pnv_phb *phb = hose->private_data; 2170bbb25af8SCédric Le Goater 2171bbb25af8SCédric Le Goater if (phb->model == PNV_PHB_MODEL_PHB3) { 2172bbb25af8SCédric Le Goater /* 2173bbb25af8SCédric Le Goater * The EOI OPAL call takes an OPAL HW IRQ number but 2174bbb25af8SCédric Le Goater * since it is translated into a vector number in 2175bbb25af8SCédric Le Goater * OPAL, use that directly. 2176bbb25af8SCédric Le Goater */ 2177bbb25af8SCédric Le Goater WARN_ON_ONCE(opal_pci_msi_eoi(phb->opal_id, d->hwirq)); 2178bbb25af8SCédric Le Goater } 2179bbb25af8SCédric Le Goater 2180bbb25af8SCédric Le Goater irq_chip_eoi_parent(d); 2181bbb25af8SCédric Le Goater } 2182bbb25af8SCédric Le Goater 21830fcfe224SCédric Le Goater static struct irq_chip pnv_msi_irq_chip = { 21840fcfe224SCédric Le Goater .name = "PNV-MSI", 21850fcfe224SCédric Le Goater .irq_shutdown = pnv_msi_shutdown, 21860fcfe224SCédric Le Goater .irq_mask = irq_chip_mask_parent, 21870fcfe224SCédric Le Goater .irq_unmask = irq_chip_unmask_parent, 2188bbb25af8SCédric Le Goater .irq_eoi = pnv_msi_eoi, 21890fcfe224SCédric Le Goater .irq_set_affinity = irq_chip_set_affinity_parent, 21900fcfe224SCédric Le Goater .irq_compose_msi_msg = pnv_msi_compose_msg, 21910fcfe224SCédric Le Goater }; 21920fcfe224SCédric Le Goater 21930fcfe224SCédric Le Goater static int pnv_irq_parent_domain_alloc(struct irq_domain *domain, 21940fcfe224SCédric Le Goater unsigned int virq, int hwirq) 21950fcfe224SCédric Le Goater { 21960fcfe224SCédric Le Goater struct irq_fwspec parent_fwspec; 21970fcfe224SCédric Le Goater int ret; 21980fcfe224SCédric Le Goater 21990fcfe224SCédric Le Goater parent_fwspec.fwnode = domain->parent->fwnode; 22000fcfe224SCédric Le Goater parent_fwspec.param_count = 2; 22010fcfe224SCédric Le Goater parent_fwspec.param[0] = hwirq; 22020fcfe224SCédric Le Goater parent_fwspec.param[1] = IRQ_TYPE_EDGE_RISING; 22030fcfe224SCédric Le Goater 22040fcfe224SCédric Le Goater ret = irq_domain_alloc_irqs_parent(domain, virq, 1, &parent_fwspec); 22050fcfe224SCédric Le Goater if (ret) 22060fcfe224SCédric Le Goater return ret; 22070fcfe224SCédric Le Goater 22080fcfe224SCédric Le Goater return 0; 22090fcfe224SCédric Le Goater } 22100fcfe224SCédric Le Goater 22110fcfe224SCédric Le Goater static int pnv_irq_domain_alloc(struct irq_domain *domain, unsigned int virq, 22120fcfe224SCédric Le Goater unsigned int nr_irqs, void *arg) 22130fcfe224SCédric Le Goater { 22140fcfe224SCédric Le Goater struct pci_controller *hose = domain->host_data; 22150fcfe224SCédric Le Goater struct pnv_phb *phb = hose->private_data; 22160fcfe224SCédric Le Goater msi_alloc_info_t *info = arg; 22170fcfe224SCédric Le Goater struct pci_dev *pdev = msi_desc_to_pci_dev(info->desc); 22180fcfe224SCédric Le Goater int hwirq; 22190fcfe224SCédric Le Goater int i, ret; 22200fcfe224SCédric Le Goater 22210fcfe224SCédric Le Goater hwirq = msi_bitmap_alloc_hwirqs(&phb->msi_bmp, nr_irqs); 22220fcfe224SCédric Le Goater if (hwirq < 0) { 22230fcfe224SCédric Le Goater dev_warn(&pdev->dev, "failed to find a free MSI\n"); 22240fcfe224SCédric Le Goater return -ENOSPC; 22250fcfe224SCédric Le Goater } 22260fcfe224SCédric Le Goater 22270fcfe224SCédric Le Goater dev_dbg(&pdev->dev, "%s bridge %pOF %d/%x #%d\n", __func__, 22280fcfe224SCédric Le Goater hose->dn, virq, hwirq, nr_irqs); 22290fcfe224SCédric Le Goater 22300fcfe224SCédric Le Goater for (i = 0; i < nr_irqs; i++) { 22310fcfe224SCédric Le Goater ret = pnv_irq_parent_domain_alloc(domain, virq + i, 22320fcfe224SCédric Le Goater phb->msi_base + hwirq + i); 22330fcfe224SCédric Le Goater if (ret) 22340fcfe224SCédric Le Goater goto out; 22350fcfe224SCédric Le Goater 22360fcfe224SCédric Le Goater irq_domain_set_hwirq_and_chip(domain, virq + i, hwirq + i, 22370fcfe224SCédric Le Goater &pnv_msi_irq_chip, hose); 22380fcfe224SCédric Le Goater } 22390fcfe224SCédric Le Goater 22400fcfe224SCédric Le Goater return 0; 22410fcfe224SCédric Le Goater 22420fcfe224SCédric Le Goater out: 22430fcfe224SCédric Le Goater irq_domain_free_irqs_parent(domain, virq, i - 1); 22440fcfe224SCédric Le Goater msi_bitmap_free_hwirqs(&phb->msi_bmp, hwirq, nr_irqs); 22450fcfe224SCédric Le Goater return ret; 22460fcfe224SCédric Le Goater } 22470fcfe224SCédric Le Goater 22480fcfe224SCédric Le Goater static void pnv_irq_domain_free(struct irq_domain *domain, unsigned int virq, 22490fcfe224SCédric Le Goater unsigned int nr_irqs) 22500fcfe224SCédric Le Goater { 22510fcfe224SCédric Le Goater struct irq_data *d = irq_domain_get_irq_data(domain, virq); 22520fcfe224SCédric Le Goater struct pci_controller *hose = irq_data_get_irq_chip_data(d); 22530fcfe224SCédric Le Goater struct pnv_phb *phb = hose->private_data; 22540fcfe224SCédric Le Goater 22550fcfe224SCédric Le Goater pr_debug("%s bridge %pOF %d/%lx #%d\n", __func__, hose->dn, 22560fcfe224SCédric Le Goater virq, d->hwirq, nr_irqs); 22570fcfe224SCédric Le Goater 22580fcfe224SCédric Le Goater msi_bitmap_free_hwirqs(&phb->msi_bmp, d->hwirq, nr_irqs); 22590fcfe224SCédric Le Goater /* XIVE domain is cleared through ->msi_free() */ 22600fcfe224SCédric Le Goater } 22610fcfe224SCédric Le Goater 22620fcfe224SCédric Le Goater static const struct irq_domain_ops pnv_irq_domain_ops = { 22630fcfe224SCédric Le Goater .alloc = pnv_irq_domain_alloc, 22640fcfe224SCédric Le Goater .free = pnv_irq_domain_free, 22650fcfe224SCédric Le Goater }; 22660fcfe224SCédric Le Goater 2267e5913db1SNick Child static int __init pnv_msi_allocate_domains(struct pci_controller *hose, unsigned int count) 22680fcfe224SCédric Le Goater { 22690fcfe224SCédric Le Goater struct pnv_phb *phb = hose->private_data; 22700fcfe224SCédric Le Goater struct irq_domain *parent = irq_get_default_host(); 22710fcfe224SCédric Le Goater 22720fcfe224SCédric Le Goater hose->fwnode = irq_domain_alloc_named_id_fwnode("PNV-MSI", phb->opal_id); 22730fcfe224SCédric Le Goater if (!hose->fwnode) 22740fcfe224SCédric Le Goater return -ENOMEM; 22750fcfe224SCédric Le Goater 22760fcfe224SCédric Le Goater hose->dev_domain = irq_domain_create_hierarchy(parent, 0, count, 22770fcfe224SCédric Le Goater hose->fwnode, 22780fcfe224SCédric Le Goater &pnv_irq_domain_ops, hose); 22790fcfe224SCédric Le Goater if (!hose->dev_domain) { 22800fcfe224SCédric Le Goater pr_err("PCI: failed to create IRQ domain bridge %pOF (domain %d)\n", 22810fcfe224SCédric Le Goater hose->dn, hose->global_number); 22820fcfe224SCédric Le Goater irq_domain_free_fwnode(hose->fwnode); 22830fcfe224SCédric Le Goater return -ENOMEM; 22840fcfe224SCédric Le Goater } 22850fcfe224SCédric Le Goater 22860fcfe224SCédric Le Goater hose->msi_domain = pci_msi_create_irq_domain(of_node_to_fwnode(hose->dn), 22870fcfe224SCédric Le Goater &pnv_msi_domain_info, 22880fcfe224SCédric Le Goater hose->dev_domain); 22890fcfe224SCédric Le Goater if (!hose->msi_domain) { 22900fcfe224SCédric Le Goater pr_err("PCI: failed to create MSI IRQ domain bridge %pOF (domain %d)\n", 22910fcfe224SCédric Le Goater hose->dn, hose->global_number); 22920fcfe224SCédric Le Goater irq_domain_free_fwnode(hose->fwnode); 22930fcfe224SCédric Le Goater irq_domain_remove(hose->dev_domain); 22940fcfe224SCédric Le Goater return -ENOMEM; 22950fcfe224SCédric Le Goater } 22960fcfe224SCédric Le Goater 22970fcfe224SCédric Le Goater return 0; 22980fcfe224SCédric Le Goater } 22990fcfe224SCédric Le Goater 2300e5913db1SNick Child static void __init pnv_pci_init_ioda_msis(struct pnv_phb *phb) 2301184cd4a3SBenjamin Herrenschmidt { 2302fb1b55d6SGavin Shan unsigned int count; 2303184cd4a3SBenjamin Herrenschmidt const __be32 *prop = of_get_property(phb->hose->dn, 2304184cd4a3SBenjamin Herrenschmidt "ibm,opal-msi-ranges", NULL); 2305184cd4a3SBenjamin Herrenschmidt if (!prop) { 2306184cd4a3SBenjamin Herrenschmidt /* BML Fallback */ 2307184cd4a3SBenjamin Herrenschmidt prop = of_get_property(phb->hose->dn, "msi-ranges", NULL); 2308184cd4a3SBenjamin Herrenschmidt } 2309184cd4a3SBenjamin Herrenschmidt if (!prop) 2310184cd4a3SBenjamin Herrenschmidt return; 2311184cd4a3SBenjamin Herrenschmidt 2312184cd4a3SBenjamin Herrenschmidt phb->msi_base = be32_to_cpup(prop); 2313fb1b55d6SGavin Shan count = be32_to_cpup(prop + 1); 2314fb1b55d6SGavin Shan if (msi_bitmap_alloc(&phb->msi_bmp, count, phb->hose->dn)) { 2315184cd4a3SBenjamin Herrenschmidt pr_err("PCI %d: Failed to allocate MSI bitmap !\n", 2316184cd4a3SBenjamin Herrenschmidt phb->hose->global_number); 2317184cd4a3SBenjamin Herrenschmidt return; 2318184cd4a3SBenjamin Herrenschmidt } 2319fb1b55d6SGavin Shan 2320184cd4a3SBenjamin Herrenschmidt pr_info(" Allocated bitmap for %d MSIs (base IRQ 0x%x)\n", 2321fb1b55d6SGavin Shan count, phb->msi_base); 23220fcfe224SCédric Le Goater 23230fcfe224SCédric Le Goater pnv_msi_allocate_domains(phb->hose, count); 2324184cd4a3SBenjamin Herrenschmidt } 2325184cd4a3SBenjamin Herrenschmidt 232623e79425SGavin Shan static void pnv_ioda_setup_pe_res(struct pnv_ioda_pe *pe, 232723e79425SGavin Shan struct resource *res) 232811685becSGavin Shan { 232923e79425SGavin Shan struct pnv_phb *phb = pe->phb; 233011685becSGavin Shan struct pci_bus_region region; 233123e79425SGavin Shan int index; 233223e79425SGavin Shan int64_t rc; 233311685becSGavin Shan 2334e64e7105SFrederic Barrat if (!res || !res->flags || res->start > res->end || 2335e64e7105SFrederic Barrat res->flags & IORESOURCE_UNSET) 233623e79425SGavin Shan return; 233711685becSGavin Shan 233811685becSGavin Shan if (res->flags & IORESOURCE_IO) { 233911685becSGavin Shan region.start = res->start - phb->ioda.io_pci_base; 234011685becSGavin Shan region.end = res->end - phb->ioda.io_pci_base; 234111685becSGavin Shan index = region.start / phb->ioda.io_segsize; 234211685becSGavin Shan 234392b8f137SGavin Shan while (index < phb->ioda.total_pe_num && 234411685becSGavin Shan region.start <= region.end) { 234511685becSGavin Shan phb->ioda.io_segmap[index] = pe->pe_number; 234611685becSGavin Shan rc = opal_pci_map_pe_mmio_window(phb->opal_id, 234711685becSGavin Shan pe->pe_number, OPAL_IO_WINDOW_TYPE, 0, index); 234811685becSGavin Shan if (rc != OPAL_SUCCESS) { 23491f52f176SRussell Currey pr_err("%s: Error %lld mapping IO segment#%d to PE#%x\n", 235011685becSGavin Shan __func__, rc, index, pe->pe_number); 235111685becSGavin Shan break; 235211685becSGavin Shan } 235311685becSGavin Shan 235411685becSGavin Shan region.start += phb->ioda.io_segsize; 235511685becSGavin Shan index++; 235611685becSGavin Shan } 2357027fa02fSGavin Shan } else if ((res->flags & IORESOURCE_MEM) && 23585958d19aSBenjamin Herrenschmidt !pnv_pci_is_m64(phb, res)) { 235911685becSGavin Shan region.start = res->start - 236023e79425SGavin Shan phb->hose->mem_offset[0] - 236111685becSGavin Shan phb->ioda.m32_pci_base; 236211685becSGavin Shan region.end = res->end - 236323e79425SGavin Shan phb->hose->mem_offset[0] - 236411685becSGavin Shan phb->ioda.m32_pci_base; 236511685becSGavin Shan index = region.start / phb->ioda.m32_segsize; 236611685becSGavin Shan 236792b8f137SGavin Shan while (index < phb->ioda.total_pe_num && 236811685becSGavin Shan region.start <= region.end) { 236911685becSGavin Shan phb->ioda.m32_segmap[index] = pe->pe_number; 237011685becSGavin Shan rc = opal_pci_map_pe_mmio_window(phb->opal_id, 237111685becSGavin Shan pe->pe_number, OPAL_M32_WINDOW_TYPE, 0, index); 237211685becSGavin Shan if (rc != OPAL_SUCCESS) { 23731f52f176SRussell Currey pr_err("%s: Error %lld mapping M32 segment#%d to PE#%x", 237411685becSGavin Shan __func__, rc, index, pe->pe_number); 237511685becSGavin Shan break; 237611685becSGavin Shan } 237711685becSGavin Shan 237811685becSGavin Shan region.start += phb->ioda.m32_segsize; 237911685becSGavin Shan index++; 238011685becSGavin Shan } 238111685becSGavin Shan } 238211685becSGavin Shan } 238323e79425SGavin Shan 238423e79425SGavin Shan /* 238523e79425SGavin Shan * This function is supposed to be called on basis of PE from top 238687c78b61SMichael Ellerman * to bottom style. So the I/O or MMIO segment assigned to 238703671057SMasahiro Yamada * parent PE could be overridden by its child PEs if necessary. 238823e79425SGavin Shan */ 238923e79425SGavin Shan static void pnv_ioda_setup_pe_seg(struct pnv_ioda_pe *pe) 239023e79425SGavin Shan { 239169d733e7SGavin Shan struct pci_dev *pdev; 239223e79425SGavin Shan int i; 239323e79425SGavin Shan 239423e79425SGavin Shan /* 239523e79425SGavin Shan * NOTE: We only care PCI bus based PE for now. For PCI 239623e79425SGavin Shan * device based PE, for example SRIOV sensitive VF should 239723e79425SGavin Shan * be figured out later. 239823e79425SGavin Shan */ 239923e79425SGavin Shan BUG_ON(!(pe->flags & (PNV_IODA_PE_BUS | PNV_IODA_PE_BUS_ALL))); 240023e79425SGavin Shan 240169d733e7SGavin Shan list_for_each_entry(pdev, &pe->pbus->devices, bus_list) { 240269d733e7SGavin Shan for (i = 0; i <= PCI_ROM_RESOURCE; i++) 240369d733e7SGavin Shan pnv_ioda_setup_pe_res(pe, &pdev->resource[i]); 240469d733e7SGavin Shan 240569d733e7SGavin Shan /* 240669d733e7SGavin Shan * If the PE contains all subordinate PCI buses, the 240769d733e7SGavin Shan * windows of the child bridges should be mapped to 240869d733e7SGavin Shan * the PE as well. 240969d733e7SGavin Shan */ 241069d733e7SGavin Shan if (!(pe->flags & PNV_IODA_PE_BUS_ALL) || !pci_is_bridge(pdev)) 241169d733e7SGavin Shan continue; 241269d733e7SGavin Shan for (i = 0; i < PCI_BRIDGE_RESOURCE_NUM; i++) 241369d733e7SGavin Shan pnv_ioda_setup_pe_res(pe, 241469d733e7SGavin Shan &pdev->resource[PCI_BRIDGE_RESOURCES + i]); 241569d733e7SGavin Shan } 241611685becSGavin Shan } 241711685becSGavin Shan 241898b665daSRussell Currey #ifdef CONFIG_DEBUG_FS 241998b665daSRussell Currey static int pnv_pci_diag_data_set(void *data, u64 val) 242098b665daSRussell Currey { 242122ba7289SOliver O'Halloran struct pnv_phb *phb = data; 242298b665daSRussell Currey s64 ret; 242398b665daSRussell Currey 242498b665daSRussell Currey /* Retrieve the diag data from firmware */ 24255cb1f8fdSRussell Currey ret = opal_pci_get_phb_diag_data2(phb->opal_id, phb->diag_data, 24265cb1f8fdSRussell Currey phb->diag_data_size); 242798b665daSRussell Currey if (ret != OPAL_SUCCESS) 242898b665daSRussell Currey return -EIO; 242998b665daSRussell Currey 243098b665daSRussell Currey /* Print the diag data to the kernel log */ 24315cb1f8fdSRussell Currey pnv_pci_dump_phb_diag_data(phb->hose, phb->diag_data); 243298b665daSRussell Currey return 0; 243398b665daSRussell Currey } 243498b665daSRussell Currey 2435bfa2325eSYueHaibing DEFINE_DEBUGFS_ATTRIBUTE(pnv_pci_diag_data_fops, NULL, pnv_pci_diag_data_set, 2436bfa2325eSYueHaibing "%llu\n"); 243798b665daSRussell Currey 243818697d2bSOliver O'Halloran static int pnv_pci_ioda_pe_dump(void *data, u64 val) 243918697d2bSOliver O'Halloran { 244018697d2bSOliver O'Halloran struct pnv_phb *phb = data; 244118697d2bSOliver O'Halloran int pe_num; 244218697d2bSOliver O'Halloran 244318697d2bSOliver O'Halloran for (pe_num = 0; pe_num < phb->ioda.total_pe_num; pe_num++) { 244418697d2bSOliver O'Halloran struct pnv_ioda_pe *pe = &phb->ioda.pe_array[pe_num]; 244518697d2bSOliver O'Halloran 244618697d2bSOliver O'Halloran if (!test_bit(pe_num, phb->ioda.pe_alloc)) 244718697d2bSOliver O'Halloran continue; 244818697d2bSOliver O'Halloran 244918697d2bSOliver O'Halloran pe_warn(pe, "rid: %04x dev count: %2d flags: %s%s%s%s%s%s\n", 245018697d2bSOliver O'Halloran pe->rid, pe->device_count, 245118697d2bSOliver O'Halloran (pe->flags & PNV_IODA_PE_DEV) ? "dev " : "", 245218697d2bSOliver O'Halloran (pe->flags & PNV_IODA_PE_BUS) ? "bus " : "", 245318697d2bSOliver O'Halloran (pe->flags & PNV_IODA_PE_BUS_ALL) ? "all " : "", 245418697d2bSOliver O'Halloran (pe->flags & PNV_IODA_PE_MASTER) ? "master " : "", 245518697d2bSOliver O'Halloran (pe->flags & PNV_IODA_PE_SLAVE) ? "slave " : "", 245618697d2bSOliver O'Halloran (pe->flags & PNV_IODA_PE_VF) ? "vf " : ""); 245718697d2bSOliver O'Halloran } 245818697d2bSOliver O'Halloran 245918697d2bSOliver O'Halloran return 0; 246018697d2bSOliver O'Halloran } 246118697d2bSOliver O'Halloran 246218697d2bSOliver O'Halloran DEFINE_DEBUGFS_ATTRIBUTE(pnv_pci_ioda_pe_dump_fops, NULL, 246318697d2bSOliver O'Halloran pnv_pci_ioda_pe_dump, "%llu\n"); 246418697d2bSOliver O'Halloran 246598b665daSRussell Currey #endif /* CONFIG_DEBUG_FS */ 246698b665daSRussell Currey 246737c367f2SGavin Shan static void pnv_pci_ioda_create_dbgfs(void) 246837c367f2SGavin Shan { 246937c367f2SGavin Shan #ifdef CONFIG_DEBUG_FS 247037c367f2SGavin Shan struct pci_controller *hose, *tmp; 247137c367f2SGavin Shan struct pnv_phb *phb; 247237c367f2SGavin Shan char name[16]; 247337c367f2SGavin Shan 247437c367f2SGavin Shan list_for_each_entry_safe(hose, tmp, &hose_list, list_node) { 247537c367f2SGavin Shan phb = hose->private_data; 247637c367f2SGavin Shan 247737c367f2SGavin Shan sprintf(name, "PCI%04x", hose->global_number); 2478dbf77fedSAneesh Kumar K.V phb->dbgfs = debugfs_create_dir(name, arch_debugfs_dir); 247998b665daSRussell Currey 2480bfa2325eSYueHaibing debugfs_create_file_unsafe("dump_diag_regs", 0200, phb->dbgfs, 248122ba7289SOliver O'Halloran phb, &pnv_pci_diag_data_fops); 248218697d2bSOliver O'Halloran debugfs_create_file_unsafe("dump_ioda_pe_state", 0200, phb->dbgfs, 248318697d2bSOliver O'Halloran phb, &pnv_pci_ioda_pe_dump_fops); 248437c367f2SGavin Shan } 248537c367f2SGavin Shan #endif /* CONFIG_DEBUG_FS */ 248637c367f2SGavin Shan } 248737c367f2SGavin Shan 2488db217319SBenjamin Herrenschmidt static void pnv_pci_enable_bridge(struct pci_bus *bus) 2489db217319SBenjamin Herrenschmidt { 2490db217319SBenjamin Herrenschmidt struct pci_dev *dev = bus->self; 2491db217319SBenjamin Herrenschmidt struct pci_bus *child; 2492db217319SBenjamin Herrenschmidt 2493db217319SBenjamin Herrenschmidt /* Empty bus ? bail */ 2494db217319SBenjamin Herrenschmidt if (list_empty(&bus->devices)) 2495db217319SBenjamin Herrenschmidt return; 2496db217319SBenjamin Herrenschmidt 2497db217319SBenjamin Herrenschmidt /* 2498db217319SBenjamin Herrenschmidt * If there's a bridge associated with that bus enable it. This works 2499db217319SBenjamin Herrenschmidt * around races in the generic code if the enabling is done during 2500db217319SBenjamin Herrenschmidt * parallel probing. This can be removed once those races have been 2501db217319SBenjamin Herrenschmidt * fixed. 2502db217319SBenjamin Herrenschmidt */ 2503db217319SBenjamin Herrenschmidt if (dev) { 2504db217319SBenjamin Herrenschmidt int rc = pci_enable_device(dev); 2505db217319SBenjamin Herrenschmidt if (rc) 2506db217319SBenjamin Herrenschmidt pci_err(dev, "Error enabling bridge (%d)\n", rc); 2507db217319SBenjamin Herrenschmidt pci_set_master(dev); 2508db217319SBenjamin Herrenschmidt } 2509db217319SBenjamin Herrenschmidt 2510db217319SBenjamin Herrenschmidt /* Perform the same to child busses */ 2511db217319SBenjamin Herrenschmidt list_for_each_entry(child, &bus->children, node) 2512db217319SBenjamin Herrenschmidt pnv_pci_enable_bridge(child); 2513db217319SBenjamin Herrenschmidt } 2514db217319SBenjamin Herrenschmidt 2515db217319SBenjamin Herrenschmidt static void pnv_pci_enable_bridges(void) 2516db217319SBenjamin Herrenschmidt { 2517db217319SBenjamin Herrenschmidt struct pci_controller *hose; 2518db217319SBenjamin Herrenschmidt 2519db217319SBenjamin Herrenschmidt list_for_each_entry(hose, &hose_list, list_node) 2520db217319SBenjamin Herrenschmidt pnv_pci_enable_bridge(hose->bus); 2521db217319SBenjamin Herrenschmidt } 2522db217319SBenjamin Herrenschmidt 2523cad5cef6SGreg Kroah-Hartman static void pnv_pci_ioda_fixup(void) 2524fb446ad0SGavin Shan { 252537c367f2SGavin Shan pnv_pci_ioda_create_dbgfs(); 252637c367f2SGavin Shan 2527db217319SBenjamin Herrenschmidt pnv_pci_enable_bridges(); 2528db217319SBenjamin Herrenschmidt 2529e9cc17d4SGavin Shan #ifdef CONFIG_EEH 2530b9fde58dSBenjamin Herrenschmidt pnv_eeh_post_init(); 2531e9cc17d4SGavin Shan #endif 2532fb446ad0SGavin Shan } 2533fb446ad0SGavin Shan 2534271fd03aSGavin Shan /* 2535271fd03aSGavin Shan * Returns the alignment for I/O or memory windows for P2P 2536271fd03aSGavin Shan * bridges. That actually depends on how PEs are segmented. 2537271fd03aSGavin Shan * For now, we return I/O or M32 segment size for PE sensitive 2538271fd03aSGavin Shan * P2P bridges. Otherwise, the default values (4KiB for I/O, 2539271fd03aSGavin Shan * 1MiB for memory) will be returned. 2540271fd03aSGavin Shan * 2541271fd03aSGavin Shan * The current PCI bus might be put into one PE, which was 2542271fd03aSGavin Shan * create against the parent PCI bridge. For that case, we 2543271fd03aSGavin Shan * needn't enlarge the alignment so that we can save some 2544271fd03aSGavin Shan * resources. 2545271fd03aSGavin Shan */ 2546271fd03aSGavin Shan static resource_size_t pnv_pci_window_alignment(struct pci_bus *bus, 2547271fd03aSGavin Shan unsigned long type) 2548271fd03aSGavin Shan { 25495609ffddSOliver O'Halloran struct pnv_phb *phb = pci_bus_to_pnvhb(bus); 2550271fd03aSGavin Shan int num_pci_bridges = 0; 25515609ffddSOliver O'Halloran struct pci_dev *bridge; 2552271fd03aSGavin Shan 2553271fd03aSGavin Shan bridge = bus->self; 2554271fd03aSGavin Shan while (bridge) { 2555271fd03aSGavin Shan if (pci_pcie_type(bridge) == PCI_EXP_TYPE_PCI_BRIDGE) { 2556271fd03aSGavin Shan num_pci_bridges++; 2557271fd03aSGavin Shan if (num_pci_bridges >= 2) 2558271fd03aSGavin Shan return 1; 2559271fd03aSGavin Shan } 2560271fd03aSGavin Shan 2561271fd03aSGavin Shan bridge = bridge->bus->self; 2562271fd03aSGavin Shan } 2563271fd03aSGavin Shan 25645958d19aSBenjamin Herrenschmidt /* 25655958d19aSBenjamin Herrenschmidt * We fall back to M32 if M64 isn't supported. We enforce the M64 25665958d19aSBenjamin Herrenschmidt * alignment for any 64-bit resource, PCIe doesn't care and 25675958d19aSBenjamin Herrenschmidt * bridges only do 64-bit prefetchable anyway. 25685958d19aSBenjamin Herrenschmidt */ 2569b79331a5SRussell Currey if (phb->ioda.m64_segsize && pnv_pci_is_m64_flags(type)) 2570262af557SGuo Chao return phb->ioda.m64_segsize; 2571271fd03aSGavin Shan if (type & IORESOURCE_MEM) 2572271fd03aSGavin Shan return phb->ioda.m32_segsize; 2573271fd03aSGavin Shan 2574271fd03aSGavin Shan return phb->ioda.io_segsize; 2575271fd03aSGavin Shan } 2576271fd03aSGavin Shan 257740e2a47eSGavin Shan /* 257840e2a47eSGavin Shan * We are updating root port or the upstream port of the 257940e2a47eSGavin Shan * bridge behind the root port with PHB's windows in order 258040e2a47eSGavin Shan * to accommodate the changes on required resources during 258140e2a47eSGavin Shan * PCI (slot) hotplug, which is connected to either root 258240e2a47eSGavin Shan * port or the downstream ports of PCIe switch behind the 258340e2a47eSGavin Shan * root port. 258440e2a47eSGavin Shan */ 258540e2a47eSGavin Shan static void pnv_pci_fixup_bridge_resources(struct pci_bus *bus, 258640e2a47eSGavin Shan unsigned long type) 258740e2a47eSGavin Shan { 258840e2a47eSGavin Shan struct pci_controller *hose = pci_bus_to_host(bus); 258940e2a47eSGavin Shan struct pnv_phb *phb = hose->private_data; 259040e2a47eSGavin Shan struct pci_dev *bridge = bus->self; 259140e2a47eSGavin Shan struct resource *r, *w; 259240e2a47eSGavin Shan bool msi_region = false; 259340e2a47eSGavin Shan int i; 259440e2a47eSGavin Shan 259540e2a47eSGavin Shan /* Check if we need apply fixup to the bridge's windows */ 259640e2a47eSGavin Shan if (!pci_is_root_bus(bridge->bus) && 259740e2a47eSGavin Shan !pci_is_root_bus(bridge->bus->self->bus)) 259840e2a47eSGavin Shan return; 259940e2a47eSGavin Shan 260040e2a47eSGavin Shan /* Fixup the resources */ 260140e2a47eSGavin Shan for (i = 0; i < PCI_BRIDGE_RESOURCE_NUM; i++) { 260240e2a47eSGavin Shan r = &bridge->resource[PCI_BRIDGE_RESOURCES + i]; 260340e2a47eSGavin Shan if (!r->flags || !r->parent) 260440e2a47eSGavin Shan continue; 260540e2a47eSGavin Shan 260640e2a47eSGavin Shan w = NULL; 260740e2a47eSGavin Shan if (r->flags & type & IORESOURCE_IO) 260840e2a47eSGavin Shan w = &hose->io_resource; 26095958d19aSBenjamin Herrenschmidt else if (pnv_pci_is_m64(phb, r) && 261040e2a47eSGavin Shan (type & IORESOURCE_PREFETCH) && 261140e2a47eSGavin Shan phb->ioda.m64_segsize) 261240e2a47eSGavin Shan w = &hose->mem_resources[1]; 261340e2a47eSGavin Shan else if (r->flags & type & IORESOURCE_MEM) { 261440e2a47eSGavin Shan w = &hose->mem_resources[0]; 261540e2a47eSGavin Shan msi_region = true; 261640e2a47eSGavin Shan } 261740e2a47eSGavin Shan 261840e2a47eSGavin Shan r->start = w->start; 261940e2a47eSGavin Shan r->end = w->end; 262040e2a47eSGavin Shan 262140e2a47eSGavin Shan /* The 64KB 32-bits MSI region shouldn't be included in 262240e2a47eSGavin Shan * the 32-bits bridge window. Otherwise, we can see strange 262340e2a47eSGavin Shan * issues. One of them is EEH error observed on Garrison. 262440e2a47eSGavin Shan * 262540e2a47eSGavin Shan * Exclude top 1MB region which is the minimal alignment of 262640e2a47eSGavin Shan * 32-bits bridge window. 262740e2a47eSGavin Shan */ 262840e2a47eSGavin Shan if (msi_region) { 262940e2a47eSGavin Shan r->end += 0x10000; 263040e2a47eSGavin Shan r->end -= 0x100000; 263140e2a47eSGavin Shan } 263240e2a47eSGavin Shan } 263340e2a47eSGavin Shan } 263440e2a47eSGavin Shan 2635dc3d8f85SOliver O'Halloran static void pnv_pci_configure_bus(struct pci_bus *bus) 2636ccd1c191SGavin Shan { 2637ccd1c191SGavin Shan struct pci_dev *bridge = bus->self; 2638ccd1c191SGavin Shan struct pnv_ioda_pe *pe; 2639dc3d8f85SOliver O'Halloran bool all = (bridge && pci_pcie_type(bridge) == PCI_EXP_TYPE_PCI_BRIDGE); 2640ccd1c191SGavin Shan 2641dc3d8f85SOliver O'Halloran dev_info(&bus->dev, "Configuring PE for bus\n"); 264240e2a47eSGavin Shan 2643ccd1c191SGavin Shan /* Don't assign PE to PCI bus, which doesn't have subordinate devices */ 26446ae8aedfSOliver O'Halloran if (WARN_ON(list_empty(&bus->devices))) 2645ccd1c191SGavin Shan return; 2646ccd1c191SGavin Shan 2647ccd1c191SGavin Shan /* Reserve PEs according to used M64 resources */ 2648a25de7afSAlexey Kardashevskiy pnv_ioda_reserve_m64_pe(bus, NULL, all); 2649ccd1c191SGavin Shan 2650ccd1c191SGavin Shan /* 2651ccd1c191SGavin Shan * Assign PE. We might run here because of partial hotplug. 2652ccd1c191SGavin Shan * For the case, we just pick up the existing PE and should 2653ccd1c191SGavin Shan * not allocate resources again. 2654ccd1c191SGavin Shan */ 2655ccd1c191SGavin Shan pe = pnv_ioda_setup_bus_PE(bus, all); 2656ccd1c191SGavin Shan if (!pe) 2657ccd1c191SGavin Shan return; 2658ccd1c191SGavin Shan 2659ccd1c191SGavin Shan pnv_ioda_setup_pe_seg(pe); 2660ccd1c191SGavin Shan } 2661ccd1c191SGavin Shan 266238274637SYongji Xie static resource_size_t pnv_pci_default_alignment(void) 266338274637SYongji Xie { 266438274637SYongji Xie return PAGE_SIZE; 266538274637SYongji Xie } 266638274637SYongji Xie 2667184cd4a3SBenjamin Herrenschmidt /* Prevent enabling devices for which we couldn't properly 2668184cd4a3SBenjamin Herrenschmidt * assign a PE 2669184cd4a3SBenjamin Herrenschmidt */ 26708bf6b91aSAlastair D'Silva static bool pnv_pci_enable_device_hook(struct pci_dev *dev) 2671184cd4a3SBenjamin Herrenschmidt { 2672db1266c8SGavin Shan struct pci_dn *pdn; 2673184cd4a3SBenjamin Herrenschmidt 2674b72c1f65SBenjamin Herrenschmidt pdn = pci_get_pdn(dev); 26756c58b1b4SOliver O'Halloran if (!pdn || pdn->pe_number == IODA_INVALID_PE) { 26766c58b1b4SOliver O'Halloran pci_err(dev, "pci_enable_device() blocked, no PE assigned.\n"); 2677c88c2a18SDaniel Axtens return false; 26786c58b1b4SOliver O'Halloran } 2679db1266c8SGavin Shan 2680c88c2a18SDaniel Axtens return true; 2681184cd4a3SBenjamin Herrenschmidt } 2682184cd4a3SBenjamin Herrenschmidt 2683c1a2feadSFrederic Barrat static bool pnv_ocapi_enable_device_hook(struct pci_dev *dev) 2684c1a2feadSFrederic Barrat { 2685c1a2feadSFrederic Barrat struct pci_dn *pdn; 2686c1a2feadSFrederic Barrat struct pnv_ioda_pe *pe; 2687c1a2feadSFrederic Barrat 2688c1a2feadSFrederic Barrat pdn = pci_get_pdn(dev); 2689c1a2feadSFrederic Barrat if (!pdn) 2690c1a2feadSFrederic Barrat return false; 2691c1a2feadSFrederic Barrat 2692c1a2feadSFrederic Barrat if (pdn->pe_number == IODA_INVALID_PE) { 2693c1a2feadSFrederic Barrat pe = pnv_ioda_setup_dev_PE(dev); 2694c1a2feadSFrederic Barrat if (!pe) 2695c1a2feadSFrederic Barrat return false; 2696c1a2feadSFrederic Barrat } 2697c1a2feadSFrederic Barrat return true; 2698c1a2feadSFrederic Barrat } 2699c1a2feadSFrederic Barrat 2700c5f7700bSGavin Shan static long pnv_pci_ioda1_unset_window(struct iommu_table_group *table_group, 2701c5f7700bSGavin Shan int num) 2702c5f7700bSGavin Shan { 2703c5f7700bSGavin Shan struct pnv_ioda_pe *pe = container_of(table_group, 2704c5f7700bSGavin Shan struct pnv_ioda_pe, table_group); 2705c5f7700bSGavin Shan struct pnv_phb *phb = pe->phb; 2706c5f7700bSGavin Shan unsigned int idx; 2707c5f7700bSGavin Shan long rc; 2708c5f7700bSGavin Shan 2709c5f7700bSGavin Shan pe_info(pe, "Removing DMA window #%d\n", num); 2710c5f7700bSGavin Shan for (idx = 0; idx < phb->ioda.dma32_count; idx++) { 2711c5f7700bSGavin Shan if (phb->ioda.dma32_segmap[idx] != pe->pe_number) 2712c5f7700bSGavin Shan continue; 2713c5f7700bSGavin Shan 2714c5f7700bSGavin Shan rc = opal_pci_map_pe_dma_window(phb->opal_id, pe->pe_number, 2715c5f7700bSGavin Shan idx, 0, 0ul, 0ul, 0ul); 2716c5f7700bSGavin Shan if (rc != OPAL_SUCCESS) { 2717c5f7700bSGavin Shan pe_warn(pe, "Failure %ld unmapping DMA32 segment#%d\n", 2718c5f7700bSGavin Shan rc, idx); 2719c5f7700bSGavin Shan return rc; 2720c5f7700bSGavin Shan } 2721c5f7700bSGavin Shan 2722c5f7700bSGavin Shan phb->ioda.dma32_segmap[idx] = IODA_INVALID_PE; 2723c5f7700bSGavin Shan } 2724c5f7700bSGavin Shan 2725c5f7700bSGavin Shan pnv_pci_unlink_table_and_group(table_group->tables[num], table_group); 2726c5f7700bSGavin Shan return OPAL_SUCCESS; 2727c5f7700bSGavin Shan } 2728c5f7700bSGavin Shan 2729c5f7700bSGavin Shan static void pnv_pci_ioda1_release_pe_dma(struct pnv_ioda_pe *pe) 2730c5f7700bSGavin Shan { 2731c5f7700bSGavin Shan struct iommu_table *tbl = pe->table_group.tables[0]; 2732c5f7700bSGavin Shan int64_t rc; 2733c5f7700bSGavin Shan 273401e12629SOliver O'Halloran if (!pe->dma_setup_done) 2735c5f7700bSGavin Shan return; 2736c5f7700bSGavin Shan 2737c5f7700bSGavin Shan rc = pnv_pci_ioda1_unset_window(&pe->table_group, 0); 2738c5f7700bSGavin Shan if (rc != OPAL_SUCCESS) 2739c5f7700bSGavin Shan return; 2740c5f7700bSGavin Shan 2741cad32d9dSAlexey Kardashevskiy pnv_pci_p7ioc_tce_invalidate(tbl, tbl->it_offset, tbl->it_size); 2742c5f7700bSGavin Shan if (pe->table_group.group) { 2743c5f7700bSGavin Shan iommu_group_put(pe->table_group.group); 2744c5f7700bSGavin Shan WARN_ON(pe->table_group.group); 2745c5f7700bSGavin Shan } 2746c5f7700bSGavin Shan 2747c5f7700bSGavin Shan free_pages(tbl->it_base, get_order(tbl->it_size << 3)); 2748e5afdf9dSAlexey Kardashevskiy iommu_tce_table_put(tbl); 2749c5f7700bSGavin Shan } 2750c5f7700bSGavin Shan 275137b59ef0SOliver O'Halloran void pnv_pci_ioda2_release_pe_dma(struct pnv_ioda_pe *pe) 2752c5f7700bSGavin Shan { 2753c5f7700bSGavin Shan struct iommu_table *tbl = pe->table_group.tables[0]; 2754c5f7700bSGavin Shan int64_t rc; 2755c5f7700bSGavin Shan 2756e17a7c0eSFrederic Barrat if (!pe->dma_setup_done) 2757c5f7700bSGavin Shan return; 2758c5f7700bSGavin Shan 2759c5f7700bSGavin Shan rc = pnv_pci_ioda2_unset_window(&pe->table_group, 0); 2760c5f7700bSGavin Shan if (rc) 27611e496391SJoe Perches pe_warn(pe, "OPAL error %lld release DMA window\n", rc); 2762c5f7700bSGavin Shan 2763c5f7700bSGavin Shan pnv_pci_ioda2_set_bypass(pe, false); 2764c5f7700bSGavin Shan if (pe->table_group.group) { 2765c5f7700bSGavin Shan iommu_group_put(pe->table_group.group); 2766c5f7700bSGavin Shan WARN_ON(pe->table_group.group); 2767c5f7700bSGavin Shan } 2768c5f7700bSGavin Shan 2769e5afdf9dSAlexey Kardashevskiy iommu_tce_table_put(tbl); 2770c5f7700bSGavin Shan } 2771c5f7700bSGavin Shan 2772c5f7700bSGavin Shan static void pnv_ioda_free_pe_seg(struct pnv_ioda_pe *pe, 2773c5f7700bSGavin Shan unsigned short win, 2774c5f7700bSGavin Shan unsigned int *map) 2775c5f7700bSGavin Shan { 2776c5f7700bSGavin Shan struct pnv_phb *phb = pe->phb; 2777c5f7700bSGavin Shan int idx; 2778c5f7700bSGavin Shan int64_t rc; 2779c5f7700bSGavin Shan 2780c5f7700bSGavin Shan for (idx = 0; idx < phb->ioda.total_pe_num; idx++) { 2781c5f7700bSGavin Shan if (map[idx] != pe->pe_number) 2782c5f7700bSGavin Shan continue; 2783c5f7700bSGavin Shan 2784c5f7700bSGavin Shan rc = opal_pci_map_pe_mmio_window(phb->opal_id, 2785c5f7700bSGavin Shan phb->ioda.reserved_pe_idx, win, 0, idx); 2786c5f7700bSGavin Shan 2787c5f7700bSGavin Shan if (rc != OPAL_SUCCESS) 27881e496391SJoe Perches pe_warn(pe, "Error %lld unmapping (%d) segment#%d\n", 2789c5f7700bSGavin Shan rc, win, idx); 2790c5f7700bSGavin Shan 2791c5f7700bSGavin Shan map[idx] = IODA_INVALID_PE; 2792c5f7700bSGavin Shan } 2793c5f7700bSGavin Shan } 2794c5f7700bSGavin Shan 2795c5f7700bSGavin Shan static void pnv_ioda_release_pe_seg(struct pnv_ioda_pe *pe) 2796c5f7700bSGavin Shan { 2797c5f7700bSGavin Shan struct pnv_phb *phb = pe->phb; 2798c5f7700bSGavin Shan 2799c5f7700bSGavin Shan if (phb->type == PNV_PHB_IODA1) { 2800c5f7700bSGavin Shan pnv_ioda_free_pe_seg(pe, OPAL_IO_WINDOW_TYPE, 2801c5f7700bSGavin Shan phb->ioda.io_segmap); 2802c5f7700bSGavin Shan pnv_ioda_free_pe_seg(pe, OPAL_M32_WINDOW_TYPE, 2803c5f7700bSGavin Shan phb->ioda.m32_segmap); 280436963365SOliver O'Halloran /* M64 is pre-configured by pnv_ioda1_init_m64() */ 2805c5f7700bSGavin Shan } else if (phb->type == PNV_PHB_IODA2) { 2806c5f7700bSGavin Shan pnv_ioda_free_pe_seg(pe, OPAL_M32_WINDOW_TYPE, 2807c5f7700bSGavin Shan phb->ioda.m32_segmap); 2808c5f7700bSGavin Shan } 2809c5f7700bSGavin Shan } 2810c5f7700bSGavin Shan 2811c5f7700bSGavin Shan static void pnv_ioda_release_pe(struct pnv_ioda_pe *pe) 2812c5f7700bSGavin Shan { 2813c5f7700bSGavin Shan struct pnv_phb *phb = pe->phb; 2814c5f7700bSGavin Shan struct pnv_ioda_pe *slave, *tmp; 2815c5f7700bSGavin Shan 2816e5500ab6SOliver O'Halloran pe_info(pe, "Releasing PE\n"); 2817e5500ab6SOliver O'Halloran 281880f1ff83SFrederic Barrat mutex_lock(&phb->ioda.pe_list_mutex); 2819c5f7700bSGavin Shan list_del(&pe->list); 282080f1ff83SFrederic Barrat mutex_unlock(&phb->ioda.pe_list_mutex); 282180f1ff83SFrederic Barrat 2822c5f7700bSGavin Shan switch (phb->type) { 2823c5f7700bSGavin Shan case PNV_PHB_IODA1: 2824c5f7700bSGavin Shan pnv_pci_ioda1_release_pe_dma(pe); 2825c5f7700bSGavin Shan break; 2826c5f7700bSGavin Shan case PNV_PHB_IODA2: 2827c5f7700bSGavin Shan pnv_pci_ioda2_release_pe_dma(pe); 2828c5f7700bSGavin Shan break; 2829f724385fSFrederic Barrat case PNV_PHB_NPU_OCAPI: 2830f724385fSFrederic Barrat break; 2831c5f7700bSGavin Shan default: 2832c5f7700bSGavin Shan WARN_ON(1); 2833c5f7700bSGavin Shan } 2834c5f7700bSGavin Shan 2835c5f7700bSGavin Shan pnv_ioda_release_pe_seg(pe); 2836c5f7700bSGavin Shan pnv_ioda_deconfigure_pe(pe->phb, pe); 2837b314427aSGavin Shan 2838b314427aSGavin Shan /* Release slave PEs in the compound PE */ 2839b314427aSGavin Shan if (pe->flags & PNV_IODA_PE_MASTER) { 2840b314427aSGavin Shan list_for_each_entry_safe(slave, tmp, &pe->slaves, list) { 2841b314427aSGavin Shan list_del(&slave->list); 2842b314427aSGavin Shan pnv_ioda_free_pe(slave); 2843b314427aSGavin Shan } 2844b314427aSGavin Shan } 2845b314427aSGavin Shan 28466eaed166SGavin Shan /* 28476eaed166SGavin Shan * The PE for root bus can be removed because of hotplug in EEH 28486eaed166SGavin Shan * recovery for fenced PHB error. We need to mark the PE dead so 28496eaed166SGavin Shan * that it can be populated again in PCI hot add path. The PE 28506eaed166SGavin Shan * shouldn't be destroyed as it's the global reserved resource. 28516eaed166SGavin Shan */ 2852718d249aSOliver O'Halloran if (phb->ioda.root_pe_idx == pe->pe_number) 2853718d249aSOliver O'Halloran return; 2854718d249aSOliver O'Halloran 2855c5f7700bSGavin Shan pnv_ioda_free_pe(pe); 2856c5f7700bSGavin Shan } 2857c5f7700bSGavin Shan 2858c5f7700bSGavin Shan static void pnv_pci_release_device(struct pci_dev *pdev) 2859c5f7700bSGavin Shan { 28605609ffddSOliver O'Halloran struct pnv_phb *phb = pci_bus_to_pnvhb(pdev->bus); 2861c5f7700bSGavin Shan struct pci_dn *pdn = pci_get_pdn(pdev); 2862c5f7700bSGavin Shan struct pnv_ioda_pe *pe; 2863c5f7700bSGavin Shan 286437b59ef0SOliver O'Halloran /* The VF PE state is torn down when sriov_disable() is called */ 2865c5f7700bSGavin Shan if (pdev->is_virtfn) 2866c5f7700bSGavin Shan return; 2867c5f7700bSGavin Shan 2868c5f7700bSGavin Shan if (!pdn || pdn->pe_number == IODA_INVALID_PE) 2869c5f7700bSGavin Shan return; 2870c5f7700bSGavin Shan 287137b59ef0SOliver O'Halloran #ifdef CONFIG_PCI_IOV 287237b59ef0SOliver O'Halloran /* 287337b59ef0SOliver O'Halloran * FIXME: Try move this to sriov_disable(). It's here since we allocate 287437b59ef0SOliver O'Halloran * the iov state at probe time since we need to fiddle with the IOV 287537b59ef0SOliver O'Halloran * resources. 287637b59ef0SOliver O'Halloran */ 287737b59ef0SOliver O'Halloran if (pdev->is_physfn) 287837b59ef0SOliver O'Halloran kfree(pdev->dev.archdata.iov_data); 287937b59ef0SOliver O'Halloran #endif 288037b59ef0SOliver O'Halloran 288129bf282dSGavin Shan /* 288229bf282dSGavin Shan * PCI hotplug can happen as part of EEH error recovery. The @pdn 288329bf282dSGavin Shan * isn't removed and added afterwards in this scenario. We should 288429bf282dSGavin Shan * set the PE number in @pdn to an invalid one. Otherwise, the PE's 288529bf282dSGavin Shan * device count is decreased on removing devices while failing to 288629bf282dSGavin Shan * be increased on adding devices. It leads to unbalanced PE's device 288729bf282dSGavin Shan * count and eventually make normal PCI hotplug path broken. 288829bf282dSGavin Shan */ 2889c5f7700bSGavin Shan pe = &phb->ioda.pe_array[pdn->pe_number]; 289029bf282dSGavin Shan pdn->pe_number = IODA_INVALID_PE; 289129bf282dSGavin Shan 2892c5f7700bSGavin Shan WARN_ON(--pe->device_count < 0); 2893c5f7700bSGavin Shan if (pe->device_count == 0) 2894c5f7700bSGavin Shan pnv_ioda_release_pe(pe); 2895c5f7700bSGavin Shan } 2896c5f7700bSGavin Shan 28977a8e6bbfSMichael Neuling static void pnv_pci_ioda_shutdown(struct pci_controller *hose) 289873ed148aSBenjamin Herrenschmidt { 28997a8e6bbfSMichael Neuling struct pnv_phb *phb = hose->private_data; 29007a8e6bbfSMichael Neuling 2901d1a85eeeSGavin Shan opal_pci_reset(phb->opal_id, OPAL_RESET_PCI_IODA_TABLE, 290273ed148aSBenjamin Herrenschmidt OPAL_ASSERT_RESET); 290373ed148aSBenjamin Herrenschmidt } 290473ed148aSBenjamin Herrenschmidt 2905946743d0SOliver O'Halloran static void pnv_pci_ioda_dma_bus_setup(struct pci_bus *bus) 2906946743d0SOliver O'Halloran { 29075609ffddSOliver O'Halloran struct pnv_phb *phb = pci_bus_to_pnvhb(bus); 2908946743d0SOliver O'Halloran struct pnv_ioda_pe *pe; 2909946743d0SOliver O'Halloran 2910946743d0SOliver O'Halloran list_for_each_entry(pe, &phb->ioda.pe_list, list) { 2911946743d0SOliver O'Halloran if (!(pe->flags & (PNV_IODA_PE_BUS | PNV_IODA_PE_BUS_ALL))) 2912946743d0SOliver O'Halloran continue; 2913946743d0SOliver O'Halloran 2914946743d0SOliver O'Halloran if (!pe->pbus) 2915946743d0SOliver O'Halloran continue; 2916946743d0SOliver O'Halloran 2917946743d0SOliver O'Halloran if (bus->number == ((pe->rid >> 8) & 0xFF)) { 2918946743d0SOliver O'Halloran pe->pbus = bus; 2919946743d0SOliver O'Halloran break; 2920946743d0SOliver O'Halloran } 2921946743d0SOliver O'Halloran } 2922946743d0SOliver O'Halloran } 2923946743d0SOliver O'Halloran 292492ae0353SDaniel Axtens static const struct pci_controller_ops pnv_pci_ioda_controller_ops = { 29250a25d9c4SOliver O'Halloran .dma_dev_setup = pnv_pci_ioda_dma_dev_setup, 2926946743d0SOliver O'Halloran .dma_bus_setup = pnv_pci_ioda_dma_bus_setup, 29272d6ad41bSChristoph Hellwig .iommu_bypass_supported = pnv_pci_ioda_iommu_bypass_supported, 292892ae0353SDaniel Axtens .enable_device_hook = pnv_pci_enable_device_hook, 2929c5f7700bSGavin Shan .release_device = pnv_pci_release_device, 293092ae0353SDaniel Axtens .window_alignment = pnv_pci_window_alignment, 2931dc3d8f85SOliver O'Halloran .setup_bridge = pnv_pci_fixup_bridge_resources, 293292ae0353SDaniel Axtens .reset_secondary_bus = pnv_pci_reset_secondary_bus, 29337a8e6bbfSMichael Neuling .shutdown = pnv_pci_ioda_shutdown, 293492ae0353SDaniel Axtens }; 293592ae0353SDaniel Axtens 29367f2c39e9SFrederic Barrat static const struct pci_controller_ops pnv_npu_ocapi_ioda_controller_ops = { 2937c1a2feadSFrederic Barrat .enable_device_hook = pnv_ocapi_enable_device_hook, 2938f724385fSFrederic Barrat .release_device = pnv_pci_release_device, 29397f2c39e9SFrederic Barrat .window_alignment = pnv_pci_window_alignment, 29407f2c39e9SFrederic Barrat .reset_secondary_bus = pnv_pci_reset_secondary_bus, 29417f2c39e9SFrederic Barrat .shutdown = pnv_pci_ioda_shutdown, 29427f2c39e9SFrederic Barrat }; 29437f2c39e9SFrederic Barrat 2944e51df2c1SAnton Blanchard static void __init pnv_pci_init_ioda_phb(struct device_node *np, 2945e9cc17d4SGavin Shan u64 hub_id, int ioda_type) 2946184cd4a3SBenjamin Herrenschmidt { 2947184cd4a3SBenjamin Herrenschmidt struct pci_controller *hose; 2948184cd4a3SBenjamin Herrenschmidt struct pnv_phb *phb; 29492b923ed1SGavin Shan unsigned long size, m64map_off, m32map_off, pemap_off; 29502b923ed1SGavin Shan unsigned long iomap_off = 0, dma32map_off = 0; 2951718d249aSOliver O'Halloran struct pnv_ioda_pe *root_pe; 2952fd141d1aSBenjamin Herrenschmidt struct resource r; 2953c681b93cSAlistair Popple const __be64 *prop64; 29543a1a4661SBenjamin Herrenschmidt const __be32 *prop32; 2955f1b7cc3eSGavin Shan int len; 29563fa23ff8SGavin Shan unsigned int segno; 2957184cd4a3SBenjamin Herrenschmidt u64 phb_id; 2958184cd4a3SBenjamin Herrenschmidt void *aux; 2959184cd4a3SBenjamin Herrenschmidt long rc; 2960184cd4a3SBenjamin Herrenschmidt 296108a45b32SBenjamin Herrenschmidt if (!of_device_is_available(np)) 296208a45b32SBenjamin Herrenschmidt return; 296308a45b32SBenjamin Herrenschmidt 2964b7c670d6SRob Herring pr_info("Initializing %s PHB (%pOF)\n", pnv_phb_names[ioda_type], np); 2965184cd4a3SBenjamin Herrenschmidt 2966184cd4a3SBenjamin Herrenschmidt prop64 = of_get_property(np, "ibm,opal-phbid", NULL); 2967184cd4a3SBenjamin Herrenschmidt if (!prop64) { 2968184cd4a3SBenjamin Herrenschmidt pr_err(" Missing \"ibm,opal-phbid\" property !\n"); 2969184cd4a3SBenjamin Herrenschmidt return; 2970184cd4a3SBenjamin Herrenschmidt } 2971184cd4a3SBenjamin Herrenschmidt phb_id = be64_to_cpup(prop64); 2972184cd4a3SBenjamin Herrenschmidt pr_debug(" PHB-ID : 0x%016llx\n", phb_id); 2973184cd4a3SBenjamin Herrenschmidt 2974dea6f4c6SMichael Ellerman phb = kzalloc(sizeof(*phb), GFP_KERNEL); 29758a7f97b9SMike Rapoport if (!phb) 29768a7f97b9SMike Rapoport panic("%s: Failed to allocate %zu bytes\n", __func__, 29778a7f97b9SMike Rapoport sizeof(*phb)); 297858d714ecSGavin Shan 297958d714ecSGavin Shan /* Allocate PCI controller */ 2980184cd4a3SBenjamin Herrenschmidt phb->hose = hose = pcibios_alloc_controller(np); 298158d714ecSGavin Shan if (!phb->hose) { 2982b7c670d6SRob Herring pr_err(" Can't allocate PCI controller for %pOF\n", 2983b7c670d6SRob Herring np); 29844421cca0SMike Rapoport memblock_free(phb, sizeof(struct pnv_phb)); 2985184cd4a3SBenjamin Herrenschmidt return; 2986184cd4a3SBenjamin Herrenschmidt } 2987184cd4a3SBenjamin Herrenschmidt 2988184cd4a3SBenjamin Herrenschmidt spin_lock_init(&phb->lock); 2989f1b7cc3eSGavin Shan prop32 = of_get_property(np, "bus-range", &len); 2990f1b7cc3eSGavin Shan if (prop32 && len == 8) { 29913a1a4661SBenjamin Herrenschmidt hose->first_busno = be32_to_cpu(prop32[0]); 29923a1a4661SBenjamin Herrenschmidt hose->last_busno = be32_to_cpu(prop32[1]); 2993f1b7cc3eSGavin Shan } else { 2994b7c670d6SRob Herring pr_warn(" Broken <bus-range> on %pOF\n", np); 2995184cd4a3SBenjamin Herrenschmidt hose->first_busno = 0; 2996184cd4a3SBenjamin Herrenschmidt hose->last_busno = 0xff; 2997f1b7cc3eSGavin Shan } 2998184cd4a3SBenjamin Herrenschmidt hose->private_data = phb; 2999e9cc17d4SGavin Shan phb->hub_id = hub_id; 3000184cd4a3SBenjamin Herrenschmidt phb->opal_id = phb_id; 3001aa0c033fSGavin Shan phb->type = ioda_type; 3002781a868fSWei Yang mutex_init(&phb->ioda.pe_alloc_mutex); 3003184cd4a3SBenjamin Herrenschmidt 3004cee72d5bSBenjamin Herrenschmidt /* Detect specific models for error handling */ 3005cee72d5bSBenjamin Herrenschmidt if (of_device_is_compatible(np, "ibm,p7ioc-pciex")) 3006cee72d5bSBenjamin Herrenschmidt phb->model = PNV_PHB_MODEL_P7IOC; 3007f3d40c25SBenjamin Herrenschmidt else if (of_device_is_compatible(np, "ibm,power8-pciex")) 3008aa0c033fSGavin Shan phb->model = PNV_PHB_MODEL_PHB3; 3009cee72d5bSBenjamin Herrenschmidt else 3010cee72d5bSBenjamin Herrenschmidt phb->model = PNV_PHB_MODEL_UNKNOWN; 3011cee72d5bSBenjamin Herrenschmidt 30125cb1f8fdSRussell Currey /* Initialize diagnostic data buffer */ 30135cb1f8fdSRussell Currey prop32 = of_get_property(np, "ibm,phb-diag-data-size", NULL); 30145cb1f8fdSRussell Currey if (prop32) 30155cb1f8fdSRussell Currey phb->diag_data_size = be32_to_cpup(prop32); 30165cb1f8fdSRussell Currey else 30175cb1f8fdSRussell Currey phb->diag_data_size = PNV_PCI_DIAG_BUF_SIZE; 30185cb1f8fdSRussell Currey 3019dea6f4c6SMichael Ellerman phb->diag_data = kzalloc(phb->diag_data_size, GFP_KERNEL); 30208a7f97b9SMike Rapoport if (!phb->diag_data) 30218a7f97b9SMike Rapoport panic("%s: Failed to allocate %u bytes\n", __func__, 30228a7f97b9SMike Rapoport phb->diag_data_size); 30235cb1f8fdSRussell Currey 3024aa0c033fSGavin Shan /* Parse 32-bit and IO ranges (if any) */ 30252f1ec02eSGavin Shan pci_process_bridge_OF_ranges(hose, np, !hose->global_number); 3026184cd4a3SBenjamin Herrenschmidt 3027aa0c033fSGavin Shan /* Get registers */ 3028fd141d1aSBenjamin Herrenschmidt if (!of_address_to_resource(np, 0, &r)) { 3029fd141d1aSBenjamin Herrenschmidt phb->regs_phys = r.start; 3030fd141d1aSBenjamin Herrenschmidt phb->regs = ioremap(r.start, resource_size(&r)); 3031184cd4a3SBenjamin Herrenschmidt if (phb->regs == NULL) 3032184cd4a3SBenjamin Herrenschmidt pr_err(" Failed to map registers !\n"); 3033fd141d1aSBenjamin Herrenschmidt } 3034577c8c88SGavin Shan 3035184cd4a3SBenjamin Herrenschmidt /* Initialize more IODA stuff */ 303692b8f137SGavin Shan phb->ioda.total_pe_num = 1; 303736954dc7SGavin Shan prop32 = of_get_property(np, "ibm,opal-num-pes", NULL); 303836954dc7SGavin Shan if (prop32) 303992b8f137SGavin Shan phb->ioda.total_pe_num = be32_to_cpup(prop32); 304036954dc7SGavin Shan prop32 = of_get_property(np, "ibm,opal-reserved-pe", NULL); 304136954dc7SGavin Shan if (prop32) 304292b8f137SGavin Shan phb->ioda.reserved_pe_idx = be32_to_cpup(prop32); 3043262af557SGuo Chao 3044c127562aSGavin Shan /* Invalidate RID to PE# mapping */ 3045c127562aSGavin Shan for (segno = 0; segno < ARRAY_SIZE(phb->ioda.pe_rmap); segno++) 3046c127562aSGavin Shan phb->ioda.pe_rmap[segno] = IODA_INVALID_PE; 3047c127562aSGavin Shan 3048262af557SGuo Chao /* Parse 64-bit MMIO range */ 3049262af557SGuo Chao pnv_ioda_parse_m64_window(phb); 3050262af557SGuo Chao 3051184cd4a3SBenjamin Herrenschmidt phb->ioda.m32_size = resource_size(&hose->mem_resources[0]); 3052aa0c033fSGavin Shan /* FW Has already off top 64k of M32 space (MSI space) */ 3053184cd4a3SBenjamin Herrenschmidt phb->ioda.m32_size += 0x10000; 3054184cd4a3SBenjamin Herrenschmidt 305592b8f137SGavin Shan phb->ioda.m32_segsize = phb->ioda.m32_size / phb->ioda.total_pe_num; 30563fd47f06SBenjamin Herrenschmidt phb->ioda.m32_pci_base = hose->mem_resources[0].start - hose->mem_offset[0]; 3057184cd4a3SBenjamin Herrenschmidt phb->ioda.io_size = hose->pci_io_size; 305892b8f137SGavin Shan phb->ioda.io_segsize = phb->ioda.io_size / phb->ioda.total_pe_num; 3059184cd4a3SBenjamin Herrenschmidt phb->ioda.io_pci_base = 0; /* XXX calculate this ? */ 3060184cd4a3SBenjamin Herrenschmidt 30612b923ed1SGavin Shan /* Calculate how many 32-bit TCE segments we have */ 30622b923ed1SGavin Shan phb->ioda.dma32_count = phb->ioda.m32_pci_base / 30632b923ed1SGavin Shan PNV_IODA1_DMA32_SEGSIZE; 30642b923ed1SGavin Shan 3065c35d2a8cSGavin Shan /* Allocate aux data & arrays. We don't have IO ports on PHB3 */ 3066b7115316SChristophe Leroy size = ALIGN(max_t(unsigned, phb->ioda.total_pe_num, 8) / 8, 306792a86756SAlexey Kardashevskiy sizeof(unsigned long)); 306893289d8cSGavin Shan m64map_off = size; 306993289d8cSGavin Shan size += phb->ioda.total_pe_num * sizeof(phb->ioda.m64_segmap[0]); 3070184cd4a3SBenjamin Herrenschmidt m32map_off = size; 307192b8f137SGavin Shan size += phb->ioda.total_pe_num * sizeof(phb->ioda.m32_segmap[0]); 3072c35d2a8cSGavin Shan if (phb->type == PNV_PHB_IODA1) { 3073c35d2a8cSGavin Shan iomap_off = size; 307492b8f137SGavin Shan size += phb->ioda.total_pe_num * sizeof(phb->ioda.io_segmap[0]); 30752b923ed1SGavin Shan dma32map_off = size; 30762b923ed1SGavin Shan size += phb->ioda.dma32_count * 30772b923ed1SGavin Shan sizeof(phb->ioda.dma32_segmap[0]); 3078c35d2a8cSGavin Shan } 3079184cd4a3SBenjamin Herrenschmidt pemap_off = size; 308092b8f137SGavin Shan size += phb->ioda.total_pe_num * sizeof(struct pnv_ioda_pe); 3081dea6f4c6SMichael Ellerman aux = kzalloc(size, GFP_KERNEL); 30828a7f97b9SMike Rapoport if (!aux) 30838a7f97b9SMike Rapoport panic("%s: Failed to allocate %lu bytes\n", __func__, size); 3084fbbefb32SOliver O'Halloran 3085184cd4a3SBenjamin Herrenschmidt phb->ioda.pe_alloc = aux; 308693289d8cSGavin Shan phb->ioda.m64_segmap = aux + m64map_off; 3087184cd4a3SBenjamin Herrenschmidt phb->ioda.m32_segmap = aux + m32map_off; 308893289d8cSGavin Shan for (segno = 0; segno < phb->ioda.total_pe_num; segno++) { 308993289d8cSGavin Shan phb->ioda.m64_segmap[segno] = IODA_INVALID_PE; 30903fa23ff8SGavin Shan phb->ioda.m32_segmap[segno] = IODA_INVALID_PE; 309193289d8cSGavin Shan } 30923fa23ff8SGavin Shan if (phb->type == PNV_PHB_IODA1) { 3093184cd4a3SBenjamin Herrenschmidt phb->ioda.io_segmap = aux + iomap_off; 30943fa23ff8SGavin Shan for (segno = 0; segno < phb->ioda.total_pe_num; segno++) 30953fa23ff8SGavin Shan phb->ioda.io_segmap[segno] = IODA_INVALID_PE; 30962b923ed1SGavin Shan 30972b923ed1SGavin Shan phb->ioda.dma32_segmap = aux + dma32map_off; 30982b923ed1SGavin Shan for (segno = 0; segno < phb->ioda.dma32_count; segno++) 30992b923ed1SGavin Shan phb->ioda.dma32_segmap[segno] = IODA_INVALID_PE; 31003fa23ff8SGavin Shan } 3101184cd4a3SBenjamin Herrenschmidt phb->ioda.pe_array = aux + pemap_off; 310263803c39SGavin Shan 310363803c39SGavin Shan /* 310463803c39SGavin Shan * Choose PE number for root bus, which shouldn't have 310563803c39SGavin Shan * M64 resources consumed by its child devices. To pick 310663803c39SGavin Shan * the PE number adjacent to the reserved one if possible. 310763803c39SGavin Shan */ 310863803c39SGavin Shan pnv_ioda_reserve_pe(phb, phb->ioda.reserved_pe_idx); 310963803c39SGavin Shan if (phb->ioda.reserved_pe_idx == 0) { 311063803c39SGavin Shan phb->ioda.root_pe_idx = 1; 311163803c39SGavin Shan pnv_ioda_reserve_pe(phb, phb->ioda.root_pe_idx); 311263803c39SGavin Shan } else if (phb->ioda.reserved_pe_idx == (phb->ioda.total_pe_num - 1)) { 311363803c39SGavin Shan phb->ioda.root_pe_idx = phb->ioda.reserved_pe_idx - 1; 311463803c39SGavin Shan pnv_ioda_reserve_pe(phb, phb->ioda.root_pe_idx); 311563803c39SGavin Shan } else { 3116718d249aSOliver O'Halloran /* otherwise just allocate one */ 3117a4bc676eSOliver O'Halloran root_pe = pnv_ioda_alloc_pe(phb, 1); 3118718d249aSOliver O'Halloran phb->ioda.root_pe_idx = root_pe->pe_number; 311963803c39SGavin Shan } 3120184cd4a3SBenjamin Herrenschmidt 3121184cd4a3SBenjamin Herrenschmidt INIT_LIST_HEAD(&phb->ioda.pe_list); 3122781a868fSWei Yang mutex_init(&phb->ioda.pe_list_mutex); 3123184cd4a3SBenjamin Herrenschmidt 3124184cd4a3SBenjamin Herrenschmidt /* Calculate how many 32-bit TCE segments we have */ 31252b923ed1SGavin Shan phb->ioda.dma32_count = phb->ioda.m32_pci_base / 3126acce971cSGavin Shan PNV_IODA1_DMA32_SEGSIZE; 3127184cd4a3SBenjamin Herrenschmidt 3128aa0c033fSGavin Shan #if 0 /* We should really do that ... */ 3129184cd4a3SBenjamin Herrenschmidt rc = opal_pci_set_phb_mem_window(opal->phb_id, 3130184cd4a3SBenjamin Herrenschmidt window_type, 3131184cd4a3SBenjamin Herrenschmidt window_num, 3132184cd4a3SBenjamin Herrenschmidt starting_real_address, 3133184cd4a3SBenjamin Herrenschmidt starting_pci_address, 3134184cd4a3SBenjamin Herrenschmidt segment_size); 3135184cd4a3SBenjamin Herrenschmidt #endif 3136184cd4a3SBenjamin Herrenschmidt 3137262af557SGuo Chao pr_info(" %03d (%03d) PE's M32: 0x%x [segment=0x%x]\n", 313892b8f137SGavin Shan phb->ioda.total_pe_num, phb->ioda.reserved_pe_idx, 3139262af557SGuo Chao phb->ioda.m32_size, phb->ioda.m32_segsize); 3140262af557SGuo Chao if (phb->ioda.m64_size) 3141262af557SGuo Chao pr_info(" M64: 0x%lx [segment=0x%lx]\n", 3142262af557SGuo Chao phb->ioda.m64_size, phb->ioda.m64_segsize); 3143262af557SGuo Chao if (phb->ioda.io_size) 3144262af557SGuo Chao pr_info(" IO: 0x%x [segment=0x%x]\n", 3145184cd4a3SBenjamin Herrenschmidt phb->ioda.io_size, phb->ioda.io_segsize); 3146184cd4a3SBenjamin Herrenschmidt 3147262af557SGuo Chao 3148184cd4a3SBenjamin Herrenschmidt phb->hose->ops = &pnv_pci_ops; 314949dec922SGavin Shan phb->get_pe_state = pnv_ioda_get_pe_state; 315049dec922SGavin Shan phb->freeze_pe = pnv_ioda_freeze_pe; 315149dec922SGavin Shan phb->unfreeze_pe = pnv_ioda_unfreeze_pe; 3152184cd4a3SBenjamin Herrenschmidt 3153184cd4a3SBenjamin Herrenschmidt /* Setup MSI support */ 3154184cd4a3SBenjamin Herrenschmidt pnv_pci_init_ioda_msis(phb); 3155184cd4a3SBenjamin Herrenschmidt 3156c40a4210SGavin Shan /* 3157c40a4210SGavin Shan * We pass the PCI probe flag PCI_REASSIGN_ALL_RSRC here 3158c40a4210SGavin Shan * to let the PCI core do resource assignment. It's supposed 3159c40a4210SGavin Shan * that the PCI core will do correct I/O and MMIO alignment 3160c40a4210SGavin Shan * for the P2P bridge bars so that each PCI bus (excluding 3161c40a4210SGavin Shan * the child P2P bridges) can form individual PE. 3162184cd4a3SBenjamin Herrenschmidt */ 3163fb446ad0SGavin Shan ppc_md.pcibios_fixup = pnv_pci_ioda_fixup; 31645d2aa710SAlistair Popple 31657f2c39e9SFrederic Barrat switch (phb->type) { 31667f2c39e9SFrederic Barrat case PNV_PHB_NPU_OCAPI: 31677f2c39e9SFrederic Barrat hose->controller_ops = pnv_npu_ocapi_ioda_controller_ops; 31687f2c39e9SFrederic Barrat break; 31697f2c39e9SFrederic Barrat default: 317092ae0353SDaniel Axtens hose->controller_ops = pnv_pci_ioda_controller_ops; 3171f9f83456SAlexey Kardashevskiy } 3172ad30cb99SMichael Ellerman 317338274637SYongji Xie ppc_md.pcibios_default_alignment = pnv_pci_default_alignment; 317438274637SYongji Xie 31756e628c7dSWei Yang #ifdef CONFIG_PCI_IOV 3176965c94f3SOliver O'Halloran ppc_md.pcibios_fixup_sriov = pnv_pci_ioda_fixup_iov; 31775350ab3fSWei Yang ppc_md.pcibios_iov_resource_alignment = pnv_pci_iov_resource_alignment; 3178988fc3baSBryant G. Ly ppc_md.pcibios_sriov_enable = pnv_pcibios_sriov_enable; 3179988fc3baSBryant G. Ly ppc_md.pcibios_sriov_disable = pnv_pcibios_sriov_disable; 3180ad30cb99SMichael Ellerman #endif 3181ad30cb99SMichael Ellerman 3182c40a4210SGavin Shan pci_add_flags(PCI_REASSIGN_ALL_RSRC); 3183184cd4a3SBenjamin Herrenschmidt 3184184cd4a3SBenjamin Herrenschmidt /* Reset IODA tables to a clean state */ 3185d1a85eeeSGavin Shan rc = opal_pci_reset(phb_id, OPAL_RESET_PCI_IODA_TABLE, OPAL_ASSERT_RESET); 3186184cd4a3SBenjamin Herrenschmidt if (rc) 3187f2c2cbccSJoe Perches pr_warn(" OPAL Error %ld performing IODA table reset !\n", rc); 3188361f2a2aSGavin Shan 31896060e9eaSAndrew Donnellan /* 31906060e9eaSAndrew Donnellan * If we're running in kdump kernel, the previous kernel never 3191361f2a2aSGavin Shan * shutdown PCI devices correctly. We already got IODA table 3192361f2a2aSGavin Shan * cleaned out. So we have to issue PHB reset to stop all PCI 319345baee14SGuilherme G. Piccoli * transactions from previous kernel. The ppc_pci_reset_phbs 3194b174b4fbSOliver O'Halloran * kernel parameter will force this reset too. Additionally, 3195b174b4fbSOliver O'Halloran * if the IODA reset above failed then use a bigger hammer. 3196b174b4fbSOliver O'Halloran * This can happen if we get a PHB fatal error in very early 3197b174b4fbSOliver O'Halloran * boot. 3198361f2a2aSGavin Shan */ 3199b174b4fbSOliver O'Halloran if (is_kdump_kernel() || pci_reset_phbs || rc) { 3200361f2a2aSGavin Shan pr_info(" Issue PHB reset ...\n"); 3201cadf364dSGavin Shan pnv_eeh_phb_reset(hose, EEH_RESET_FUNDAMENTAL); 3202cadf364dSGavin Shan pnv_eeh_phb_reset(hose, EEH_RESET_DEACTIVATE); 3203361f2a2aSGavin Shan } 3204262af557SGuo Chao 32059e9e8935SGavin Shan /* Remove M64 resource if we can't configure it successfully */ 32069e9e8935SGavin Shan if (!phb->init_m64 || phb->init_m64(phb)) 3207262af557SGuo Chao hose->mem_resources[1].flags = 0; 3208fbbefb32SOliver O'Halloran 3209fbbefb32SOliver O'Halloran /* create pci_dn's for DT nodes under this PHB */ 3210fbbefb32SOliver O'Halloran pci_devs_phb_init_dynamic(hose); 3211184cd4a3SBenjamin Herrenschmidt } 3212184cd4a3SBenjamin Herrenschmidt 321367975005SBjorn Helgaas void __init pnv_pci_init_ioda2_phb(struct device_node *np) 3214aa0c033fSGavin Shan { 3215e9cc17d4SGavin Shan pnv_pci_init_ioda_phb(np, 0, PNV_PHB_IODA2); 3216aa0c033fSGavin Shan } 3217aa0c033fSGavin Shan 32187f2c39e9SFrederic Barrat void __init pnv_pci_init_npu2_opencapi_phb(struct device_node *np) 32197f2c39e9SFrederic Barrat { 32207f2c39e9SFrederic Barrat pnv_pci_init_ioda_phb(np, 0, PNV_PHB_NPU_OCAPI); 32215d2aa710SAlistair Popple } 32225d2aa710SAlistair Popple 3223228c2f41SAndrew Donnellan static void pnv_npu2_opencapi_cfg_size_fixup(struct pci_dev *dev) 3224228c2f41SAndrew Donnellan { 32255609ffddSOliver O'Halloran struct pnv_phb *phb = pci_bus_to_pnvhb(dev->bus); 3226228c2f41SAndrew Donnellan 3227228c2f41SAndrew Donnellan if (!machine_is(powernv)) 3228228c2f41SAndrew Donnellan return; 3229228c2f41SAndrew Donnellan 3230228c2f41SAndrew Donnellan if (phb->type == PNV_PHB_NPU_OCAPI) 3231228c2f41SAndrew Donnellan dev->cfg_size = PCI_CFG_SPACE_EXP_SIZE; 3232228c2f41SAndrew Donnellan } 3233228c2f41SAndrew Donnellan DECLARE_PCI_FIXUP_EARLY(PCI_ANY_ID, PCI_ANY_ID, pnv_npu2_opencapi_cfg_size_fixup); 3234228c2f41SAndrew Donnellan 3235184cd4a3SBenjamin Herrenschmidt void __init pnv_pci_init_ioda_hub(struct device_node *np) 3236184cd4a3SBenjamin Herrenschmidt { 3237184cd4a3SBenjamin Herrenschmidt struct device_node *phbn; 3238c681b93cSAlistair Popple const __be64 *prop64; 3239184cd4a3SBenjamin Herrenschmidt u64 hub_id; 3240184cd4a3SBenjamin Herrenschmidt 3241b7c670d6SRob Herring pr_info("Probing IODA IO-Hub %pOF\n", np); 3242184cd4a3SBenjamin Herrenschmidt 3243184cd4a3SBenjamin Herrenschmidt prop64 = of_get_property(np, "ibm,opal-hubid", NULL); 3244184cd4a3SBenjamin Herrenschmidt if (!prop64) { 3245184cd4a3SBenjamin Herrenschmidt pr_err(" Missing \"ibm,opal-hubid\" property !\n"); 3246184cd4a3SBenjamin Herrenschmidt return; 3247184cd4a3SBenjamin Herrenschmidt } 3248184cd4a3SBenjamin Herrenschmidt hub_id = be64_to_cpup(prop64); 3249184cd4a3SBenjamin Herrenschmidt pr_devel(" HUB-ID : 0x%016llx\n", hub_id); 3250184cd4a3SBenjamin Herrenschmidt 3251184cd4a3SBenjamin Herrenschmidt /* Count child PHBs */ 3252184cd4a3SBenjamin Herrenschmidt for_each_child_of_node(np, phbn) { 3253184cd4a3SBenjamin Herrenschmidt /* Look for IODA1 PHBs */ 3254184cd4a3SBenjamin Herrenschmidt if (of_device_is_compatible(phbn, "ibm,ioda-phb")) 3255e9cc17d4SGavin Shan pnv_pci_init_ioda_phb(phbn, hub_id, PNV_PHB_IODA1); 3256184cd4a3SBenjamin Herrenschmidt } 3257184cd4a3SBenjamin Herrenschmidt } 3258