12874c5fdSThomas Gleixner // SPDX-License-Identifier: GPL-2.0-or-later 2184cd4a3SBenjamin Herrenschmidt /* 3184cd4a3SBenjamin Herrenschmidt * Support PCI/PCIe on PowerNV platforms 4184cd4a3SBenjamin Herrenschmidt * 5184cd4a3SBenjamin Herrenschmidt * Copyright 2011 Benjamin Herrenschmidt, IBM Corp. 6184cd4a3SBenjamin Herrenschmidt */ 7184cd4a3SBenjamin Herrenschmidt 8cee72d5bSBenjamin Herrenschmidt #undef DEBUG 9184cd4a3SBenjamin Herrenschmidt 10184cd4a3SBenjamin Herrenschmidt #include <linux/kernel.h> 11184cd4a3SBenjamin Herrenschmidt #include <linux/pci.h> 12361f2a2aSGavin Shan #include <linux/crash_dump.h> 13184cd4a3SBenjamin Herrenschmidt #include <linux/delay.h> 14184cd4a3SBenjamin Herrenschmidt #include <linux/string.h> 15184cd4a3SBenjamin Herrenschmidt #include <linux/init.h> 1657c8a661SMike Rapoport #include <linux/memblock.h> 17184cd4a3SBenjamin Herrenschmidt #include <linux/irq.h> 18184cd4a3SBenjamin Herrenschmidt #include <linux/io.h> 19184cd4a3SBenjamin Herrenschmidt #include <linux/msi.h> 20ac9a5889SAlexey Kardashevskiy #include <linux/iommu.h> 21e57080f1SAlexey Kardashevskiy #include <linux/rculist.h> 224793d65dSAlexey Kardashevskiy #include <linux/sizes.h> 23184cd4a3SBenjamin Herrenschmidt 24184cd4a3SBenjamin Herrenschmidt #include <asm/sections.h> 25184cd4a3SBenjamin Herrenschmidt #include <asm/io.h> 26184cd4a3SBenjamin Herrenschmidt #include <asm/prom.h> 27184cd4a3SBenjamin Herrenschmidt #include <asm/pci-bridge.h> 28184cd4a3SBenjamin Herrenschmidt #include <asm/machdep.h> 29fb1b55d6SGavin Shan #include <asm/msi_bitmap.h> 30184cd4a3SBenjamin Herrenschmidt #include <asm/ppc-pci.h> 31184cd4a3SBenjamin Herrenschmidt #include <asm/opal.h> 32184cd4a3SBenjamin Herrenschmidt #include <asm/iommu.h> 33184cd4a3SBenjamin Herrenschmidt #include <asm/tce.h> 34137436c9SGavin Shan #include <asm/xics.h> 357644d581SMichael Ellerman #include <asm/debugfs.h> 36262af557SGuo Chao #include <asm/firmware.h> 3780c49c7eSIan Munsie #include <asm/pnv-pci.h> 38aca6913fSAlexey Kardashevskiy #include <asm/mmzone.h> 3980c49c7eSIan Munsie 40ec249dd8SMichael Neuling #include <misc/cxl-base.h> 41184cd4a3SBenjamin Herrenschmidt 42184cd4a3SBenjamin Herrenschmidt #include "powernv.h" 43184cd4a3SBenjamin Herrenschmidt #include "pci.h" 4444bda4b7SHari Vyas #include "../../../../drivers/pci/pci.h" 45184cd4a3SBenjamin Herrenschmidt 4699451551SGavin Shan #define PNV_IODA1_M64_NUM 16 /* Number of M64 BARs */ 4799451551SGavin Shan #define PNV_IODA1_M64_SEGS 8 /* Segments per M64 BAR */ 48acce971cSGavin Shan #define PNV_IODA1_DMA32_SEGSIZE 0x10000000 49781a868fSWei Yang 507f2c39e9SFrederic Barrat static const char * const pnv_phb_names[] = { "IODA1", "IODA2", "NPU_NVLINK", 517f2c39e9SFrederic Barrat "NPU_OCAPI" }; 52aca6913fSAlexey Kardashevskiy 53c498a4f9SChristoph Hellwig static void pnv_pci_ioda2_set_bypass(struct pnv_ioda_pe *pe, bool enable); 54c498a4f9SChristoph Hellwig 557d623e42SAlexey Kardashevskiy void pe_level_printk(const struct pnv_ioda_pe *pe, const char *level, 566d31c2faSJoe Perches const char *fmt, ...) 576d31c2faSJoe Perches { 586d31c2faSJoe Perches struct va_format vaf; 596d31c2faSJoe Perches va_list args; 606d31c2faSJoe Perches char pfix[32]; 61184cd4a3SBenjamin Herrenschmidt 626d31c2faSJoe Perches va_start(args, fmt); 636d31c2faSJoe Perches 646d31c2faSJoe Perches vaf.fmt = fmt; 656d31c2faSJoe Perches vaf.va = &args; 666d31c2faSJoe Perches 67781a868fSWei Yang if (pe->flags & PNV_IODA_PE_DEV) 686d31c2faSJoe Perches strlcpy(pfix, dev_name(&pe->pdev->dev), sizeof(pfix)); 69781a868fSWei Yang else if (pe->flags & (PNV_IODA_PE_BUS | PNV_IODA_PE_BUS_ALL)) 706d31c2faSJoe Perches sprintf(pfix, "%04x:%02x ", 716d31c2faSJoe Perches pci_domain_nr(pe->pbus), pe->pbus->number); 72781a868fSWei Yang #ifdef CONFIG_PCI_IOV 73781a868fSWei Yang else if (pe->flags & PNV_IODA_PE_VF) 74781a868fSWei Yang sprintf(pfix, "%04x:%02x:%2x.%d", 75781a868fSWei Yang pci_domain_nr(pe->parent_dev->bus), 76781a868fSWei Yang (pe->rid & 0xff00) >> 8, 77781a868fSWei Yang PCI_SLOT(pe->rid), PCI_FUNC(pe->rid)); 78781a868fSWei Yang #endif /* CONFIG_PCI_IOV*/ 796d31c2faSJoe Perches 801f52f176SRussell Currey printk("%spci %s: [PE# %.2x] %pV", 816d31c2faSJoe Perches level, pfix, pe->pe_number, &vaf); 826d31c2faSJoe Perches 836d31c2faSJoe Perches va_end(args); 846d31c2faSJoe Perches } 856d31c2faSJoe Perches 864e287840SThadeu Lima de Souza Cascardo static bool pnv_iommu_bypass_disabled __read_mostly; 8745baee14SGuilherme G. Piccoli static bool pci_reset_phbs __read_mostly; 884e287840SThadeu Lima de Souza Cascardo 894e287840SThadeu Lima de Souza Cascardo static int __init iommu_setup(char *str) 904e287840SThadeu Lima de Souza Cascardo { 914e287840SThadeu Lima de Souza Cascardo if (!str) 924e287840SThadeu Lima de Souza Cascardo return -EINVAL; 934e287840SThadeu Lima de Souza Cascardo 944e287840SThadeu Lima de Souza Cascardo while (*str) { 954e287840SThadeu Lima de Souza Cascardo if (!strncmp(str, "nobypass", 8)) { 964e287840SThadeu Lima de Souza Cascardo pnv_iommu_bypass_disabled = true; 974e287840SThadeu Lima de Souza Cascardo pr_info("PowerNV: IOMMU bypass window disabled.\n"); 984e287840SThadeu Lima de Souza Cascardo break; 994e287840SThadeu Lima de Souza Cascardo } 1004e287840SThadeu Lima de Souza Cascardo str += strcspn(str, ","); 1014e287840SThadeu Lima de Souza Cascardo if (*str == ',') 1024e287840SThadeu Lima de Souza Cascardo str++; 1034e287840SThadeu Lima de Souza Cascardo } 1044e287840SThadeu Lima de Souza Cascardo 1054e287840SThadeu Lima de Souza Cascardo return 0; 1064e287840SThadeu Lima de Souza Cascardo } 1074e287840SThadeu Lima de Souza Cascardo early_param("iommu", iommu_setup); 1084e287840SThadeu Lima de Souza Cascardo 10945baee14SGuilherme G. Piccoli static int __init pci_reset_phbs_setup(char *str) 11045baee14SGuilherme G. Piccoli { 11145baee14SGuilherme G. Piccoli pci_reset_phbs = true; 11245baee14SGuilherme G. Piccoli return 0; 11345baee14SGuilherme G. Piccoli } 11445baee14SGuilherme G. Piccoli 11545baee14SGuilherme G. Piccoli early_param("ppc_pci_reset_phbs", pci_reset_phbs_setup); 11645baee14SGuilherme G. Piccoli 1175958d19aSBenjamin Herrenschmidt static inline bool pnv_pci_is_m64(struct pnv_phb *phb, struct resource *r) 118262af557SGuo Chao { 1195958d19aSBenjamin Herrenschmidt /* 1205958d19aSBenjamin Herrenschmidt * WARNING: We cannot rely on the resource flags. The Linux PCI 1215958d19aSBenjamin Herrenschmidt * allocation code sometimes decides to put a 64-bit prefetchable 1225958d19aSBenjamin Herrenschmidt * BAR in the 32-bit window, so we have to compare the addresses. 1235958d19aSBenjamin Herrenschmidt * 1245958d19aSBenjamin Herrenschmidt * For simplicity we only test resource start. 1255958d19aSBenjamin Herrenschmidt */ 1265958d19aSBenjamin Herrenschmidt return (r->start >= phb->ioda.m64_base && 1275958d19aSBenjamin Herrenschmidt r->start < (phb->ioda.m64_base + phb->ioda.m64_size)); 128262af557SGuo Chao } 129262af557SGuo Chao 130b79331a5SRussell Currey static inline bool pnv_pci_is_m64_flags(unsigned long resource_flags) 131b79331a5SRussell Currey { 132b79331a5SRussell Currey unsigned long flags = (IORESOURCE_MEM_64 | IORESOURCE_PREFETCH); 133b79331a5SRussell Currey 134b79331a5SRussell Currey return (resource_flags & flags) == flags; 135b79331a5SRussell Currey } 136b79331a5SRussell Currey 1371e916772SGavin Shan static struct pnv_ioda_pe *pnv_ioda_init_pe(struct pnv_phb *phb, int pe_no) 1381e916772SGavin Shan { 139313483ddSGavin Shan s64 rc; 140313483ddSGavin Shan 1411e916772SGavin Shan phb->ioda.pe_array[pe_no].phb = phb; 1421e916772SGavin Shan phb->ioda.pe_array[pe_no].pe_number = pe_no; 1431e916772SGavin Shan 144313483ddSGavin Shan /* 145313483ddSGavin Shan * Clear the PE frozen state as it might be put into frozen state 146313483ddSGavin Shan * in the last PCI remove path. It's not harmful to do so when the 147313483ddSGavin Shan * PE is already in unfrozen state. 148313483ddSGavin Shan */ 149313483ddSGavin Shan rc = opal_pci_eeh_freeze_clear(phb->opal_id, pe_no, 150313483ddSGavin Shan OPAL_EEH_ACTION_CLEAR_FREEZE_ALL); 151d4791db5SRussell Currey if (rc != OPAL_SUCCESS && rc != OPAL_UNSUPPORTED) 1521f52f176SRussell Currey pr_warn("%s: Error %lld unfreezing PHB#%x-PE#%x\n", 153313483ddSGavin Shan __func__, rc, phb->hose->global_number, pe_no); 154313483ddSGavin Shan 1551e916772SGavin Shan return &phb->ioda.pe_array[pe_no]; 1561e916772SGavin Shan } 1571e916772SGavin Shan 1584b82ab18SGavin Shan static void pnv_ioda_reserve_pe(struct pnv_phb *phb, int pe_no) 1594b82ab18SGavin Shan { 16092b8f137SGavin Shan if (!(pe_no >= 0 && pe_no < phb->ioda.total_pe_num)) { 1611f52f176SRussell Currey pr_warn("%s: Invalid PE %x on PHB#%x\n", 1624b82ab18SGavin Shan __func__, pe_no, phb->hose->global_number); 1634b82ab18SGavin Shan return; 1644b82ab18SGavin Shan } 1654b82ab18SGavin Shan 166e9dc4d7fSGavin Shan if (test_and_set_bit(pe_no, phb->ioda.pe_alloc)) 1671f52f176SRussell Currey pr_debug("%s: PE %x was reserved on PHB#%x\n", 1684b82ab18SGavin Shan __func__, pe_no, phb->hose->global_number); 1694b82ab18SGavin Shan 1701e916772SGavin Shan pnv_ioda_init_pe(phb, pe_no); 1714b82ab18SGavin Shan } 1724b82ab18SGavin Shan 1731e916772SGavin Shan static struct pnv_ioda_pe *pnv_ioda_alloc_pe(struct pnv_phb *phb) 174184cd4a3SBenjamin Herrenschmidt { 17560964816SAndrzej Hajda long pe; 176184cd4a3SBenjamin Herrenschmidt 1779fcd6f4aSGavin Shan for (pe = phb->ioda.total_pe_num - 1; pe >= 0; pe--) { 1789fcd6f4aSGavin Shan if (!test_and_set_bit(pe, phb->ioda.pe_alloc)) 1791e916772SGavin Shan return pnv_ioda_init_pe(phb, pe); 180184cd4a3SBenjamin Herrenschmidt } 181184cd4a3SBenjamin Herrenschmidt 1829fcd6f4aSGavin Shan return NULL; 1839fcd6f4aSGavin Shan } 1849fcd6f4aSGavin Shan 1851e916772SGavin Shan static void pnv_ioda_free_pe(struct pnv_ioda_pe *pe) 186184cd4a3SBenjamin Herrenschmidt { 1871e916772SGavin Shan struct pnv_phb *phb = pe->phb; 188caa58f80SGavin Shan unsigned int pe_num = pe->pe_number; 189184cd4a3SBenjamin Herrenschmidt 1901e916772SGavin Shan WARN_ON(pe->pdev); 191f724385fSFrederic Barrat WARN_ON(pe->npucomp); /* NPUs for nvlink are not supposed to be freed */ 1920bd97167SAlexey Kardashevskiy kfree(pe->npucomp); 1931e916772SGavin Shan memset(pe, 0, sizeof(struct pnv_ioda_pe)); 194caa58f80SGavin Shan clear_bit(pe_num, phb->ioda.pe_alloc); 195184cd4a3SBenjamin Herrenschmidt } 196184cd4a3SBenjamin Herrenschmidt 197262af557SGuo Chao /* The default M64 BAR is shared by all PEs */ 198262af557SGuo Chao static int pnv_ioda2_init_m64(struct pnv_phb *phb) 199262af557SGuo Chao { 200262af557SGuo Chao const char *desc; 201262af557SGuo Chao struct resource *r; 202262af557SGuo Chao s64 rc; 203262af557SGuo Chao 204262af557SGuo Chao /* Configure the default M64 BAR */ 205262af557SGuo Chao rc = opal_pci_set_phb_mem_window(phb->opal_id, 206262af557SGuo Chao OPAL_M64_WINDOW_TYPE, 207262af557SGuo Chao phb->ioda.m64_bar_idx, 208262af557SGuo Chao phb->ioda.m64_base, 209262af557SGuo Chao 0, /* unused */ 210262af557SGuo Chao phb->ioda.m64_size); 211262af557SGuo Chao if (rc != OPAL_SUCCESS) { 212262af557SGuo Chao desc = "configuring"; 213262af557SGuo Chao goto fail; 214262af557SGuo Chao } 215262af557SGuo Chao 216262af557SGuo Chao /* Enable the default M64 BAR */ 217262af557SGuo Chao rc = opal_pci_phb_mmio_enable(phb->opal_id, 218262af557SGuo Chao OPAL_M64_WINDOW_TYPE, 219262af557SGuo Chao phb->ioda.m64_bar_idx, 220262af557SGuo Chao OPAL_ENABLE_M64_SPLIT); 221262af557SGuo Chao if (rc != OPAL_SUCCESS) { 222262af557SGuo Chao desc = "enabling"; 223262af557SGuo Chao goto fail; 224262af557SGuo Chao } 225262af557SGuo Chao 226262af557SGuo Chao /* 22763803c39SGavin Shan * Exclude the segments for reserved and root bus PE, which 22863803c39SGavin Shan * are first or last two PEs. 229262af557SGuo Chao */ 230262af557SGuo Chao r = &phb->hose->mem_resources[1]; 23192b8f137SGavin Shan if (phb->ioda.reserved_pe_idx == 0) 23263803c39SGavin Shan r->start += (2 * phb->ioda.m64_segsize); 23392b8f137SGavin Shan else if (phb->ioda.reserved_pe_idx == (phb->ioda.total_pe_num - 1)) 23463803c39SGavin Shan r->end -= (2 * phb->ioda.m64_segsize); 235262af557SGuo Chao else 2361f52f176SRussell Currey pr_warn(" Cannot strip M64 segment for reserved PE#%x\n", 23792b8f137SGavin Shan phb->ioda.reserved_pe_idx); 238262af557SGuo Chao 239262af557SGuo Chao return 0; 240262af557SGuo Chao 241262af557SGuo Chao fail: 242262af557SGuo Chao pr_warn(" Failure %lld %s M64 BAR#%d\n", 243262af557SGuo Chao rc, desc, phb->ioda.m64_bar_idx); 244262af557SGuo Chao opal_pci_phb_mmio_enable(phb->opal_id, 245262af557SGuo Chao OPAL_M64_WINDOW_TYPE, 246262af557SGuo Chao phb->ioda.m64_bar_idx, 247262af557SGuo Chao OPAL_DISABLE_M64); 248262af557SGuo Chao return -EIO; 249262af557SGuo Chao } 250262af557SGuo Chao 251c430670aSGavin Shan static void pnv_ioda_reserve_dev_m64_pe(struct pci_dev *pdev, 25296a2f92bSGavin Shan unsigned long *pe_bitmap) 253262af557SGuo Chao { 25496a2f92bSGavin Shan struct pci_controller *hose = pci_bus_to_host(pdev->bus); 25596a2f92bSGavin Shan struct pnv_phb *phb = hose->private_data; 256262af557SGuo Chao struct resource *r; 25796a2f92bSGavin Shan resource_size_t base, sgsz, start, end; 25896a2f92bSGavin Shan int segno, i; 259262af557SGuo Chao 26096a2f92bSGavin Shan base = phb->ioda.m64_base; 26196a2f92bSGavin Shan sgsz = phb->ioda.m64_segsize; 26296a2f92bSGavin Shan for (i = 0; i <= PCI_ROM_RESOURCE; i++) { 26396a2f92bSGavin Shan r = &pdev->resource[i]; 2645958d19aSBenjamin Herrenschmidt if (!r->parent || !pnv_pci_is_m64(phb, r)) 265262af557SGuo Chao continue; 266262af557SGuo Chao 267e96d904eSChristophe Leroy start = ALIGN_DOWN(r->start - base, sgsz); 268b7115316SChristophe Leroy end = ALIGN(r->end - base, sgsz); 26996a2f92bSGavin Shan for (segno = start / sgsz; segno < end / sgsz; segno++) { 27096a2f92bSGavin Shan if (pe_bitmap) 27196a2f92bSGavin Shan set_bit(segno, pe_bitmap); 27296a2f92bSGavin Shan else 27396a2f92bSGavin Shan pnv_ioda_reserve_pe(phb, segno); 274262af557SGuo Chao } 275262af557SGuo Chao } 276262af557SGuo Chao } 277262af557SGuo Chao 27899451551SGavin Shan static int pnv_ioda1_init_m64(struct pnv_phb *phb) 27999451551SGavin Shan { 28099451551SGavin Shan struct resource *r; 28199451551SGavin Shan int index; 28299451551SGavin Shan 28399451551SGavin Shan /* 28499451551SGavin Shan * There are 16 M64 BARs, each of which has 8 segments. So 28599451551SGavin Shan * there are as many M64 segments as the maximum number of 28699451551SGavin Shan * PEs, which is 128. 28799451551SGavin Shan */ 28899451551SGavin Shan for (index = 0; index < PNV_IODA1_M64_NUM; index++) { 28999451551SGavin Shan unsigned long base, segsz = phb->ioda.m64_segsize; 29099451551SGavin Shan int64_t rc; 29199451551SGavin Shan 29299451551SGavin Shan base = phb->ioda.m64_base + 29399451551SGavin Shan index * PNV_IODA1_M64_SEGS * segsz; 29499451551SGavin Shan rc = opal_pci_set_phb_mem_window(phb->opal_id, 29599451551SGavin Shan OPAL_M64_WINDOW_TYPE, index, base, 0, 29699451551SGavin Shan PNV_IODA1_M64_SEGS * segsz); 29799451551SGavin Shan if (rc != OPAL_SUCCESS) { 2981f52f176SRussell Currey pr_warn(" Error %lld setting M64 PHB#%x-BAR#%d\n", 29999451551SGavin Shan rc, phb->hose->global_number, index); 30099451551SGavin Shan goto fail; 30199451551SGavin Shan } 30299451551SGavin Shan 30399451551SGavin Shan rc = opal_pci_phb_mmio_enable(phb->opal_id, 30499451551SGavin Shan OPAL_M64_WINDOW_TYPE, index, 30599451551SGavin Shan OPAL_ENABLE_M64_SPLIT); 30699451551SGavin Shan if (rc != OPAL_SUCCESS) { 3071f52f176SRussell Currey pr_warn(" Error %lld enabling M64 PHB#%x-BAR#%d\n", 30899451551SGavin Shan rc, phb->hose->global_number, index); 30999451551SGavin Shan goto fail; 31099451551SGavin Shan } 31199451551SGavin Shan } 31299451551SGavin Shan 31399451551SGavin Shan /* 31463803c39SGavin Shan * Exclude the segments for reserved and root bus PE, which 31563803c39SGavin Shan * are first or last two PEs. 31699451551SGavin Shan */ 31799451551SGavin Shan r = &phb->hose->mem_resources[1]; 31899451551SGavin Shan if (phb->ioda.reserved_pe_idx == 0) 31963803c39SGavin Shan r->start += (2 * phb->ioda.m64_segsize); 32099451551SGavin Shan else if (phb->ioda.reserved_pe_idx == (phb->ioda.total_pe_num - 1)) 32163803c39SGavin Shan r->end -= (2 * phb->ioda.m64_segsize); 32299451551SGavin Shan else 3231f52f176SRussell Currey WARN(1, "Wrong reserved PE#%x on PHB#%x\n", 32499451551SGavin Shan phb->ioda.reserved_pe_idx, phb->hose->global_number); 32599451551SGavin Shan 32699451551SGavin Shan return 0; 32799451551SGavin Shan 32899451551SGavin Shan fail: 32999451551SGavin Shan for ( ; index >= 0; index--) 33099451551SGavin Shan opal_pci_phb_mmio_enable(phb->opal_id, 33199451551SGavin Shan OPAL_M64_WINDOW_TYPE, index, OPAL_DISABLE_M64); 33299451551SGavin Shan 33399451551SGavin Shan return -EIO; 33499451551SGavin Shan } 33599451551SGavin Shan 336c430670aSGavin Shan static void pnv_ioda_reserve_m64_pe(struct pci_bus *bus, 33796a2f92bSGavin Shan unsigned long *pe_bitmap, 33896a2f92bSGavin Shan bool all) 339262af557SGuo Chao { 340262af557SGuo Chao struct pci_dev *pdev; 34196a2f92bSGavin Shan 34296a2f92bSGavin Shan list_for_each_entry(pdev, &bus->devices, bus_list) { 343c430670aSGavin Shan pnv_ioda_reserve_dev_m64_pe(pdev, pe_bitmap); 34496a2f92bSGavin Shan 34596a2f92bSGavin Shan if (all && pdev->subordinate) 346c430670aSGavin Shan pnv_ioda_reserve_m64_pe(pdev->subordinate, 34796a2f92bSGavin Shan pe_bitmap, all); 34896a2f92bSGavin Shan } 34996a2f92bSGavin Shan } 35096a2f92bSGavin Shan 3511e916772SGavin Shan static struct pnv_ioda_pe *pnv_ioda_pick_m64_pe(struct pci_bus *bus, bool all) 352262af557SGuo Chao { 35326ba248dSGavin Shan struct pci_controller *hose = pci_bus_to_host(bus); 35426ba248dSGavin Shan struct pnv_phb *phb = hose->private_data; 355262af557SGuo Chao struct pnv_ioda_pe *master_pe, *pe; 356262af557SGuo Chao unsigned long size, *pe_alloc; 35726ba248dSGavin Shan int i; 358262af557SGuo Chao 359262af557SGuo Chao /* Root bus shouldn't use M64 */ 360262af557SGuo Chao if (pci_is_root_bus(bus)) 3611e916772SGavin Shan return NULL; 362262af557SGuo Chao 363262af557SGuo Chao /* Allocate bitmap */ 364b7115316SChristophe Leroy size = ALIGN(phb->ioda.total_pe_num / 8, sizeof(unsigned long)); 365262af557SGuo Chao pe_alloc = kzalloc(size, GFP_KERNEL); 366262af557SGuo Chao if (!pe_alloc) { 367262af557SGuo Chao pr_warn("%s: Out of memory !\n", 368262af557SGuo Chao __func__); 3691e916772SGavin Shan return NULL; 370262af557SGuo Chao } 371262af557SGuo Chao 37226ba248dSGavin Shan /* Figure out reserved PE numbers by the PE */ 373c430670aSGavin Shan pnv_ioda_reserve_m64_pe(bus, pe_alloc, all); 374262af557SGuo Chao 375262af557SGuo Chao /* 376262af557SGuo Chao * the current bus might not own M64 window and that's all 377262af557SGuo Chao * contributed by its child buses. For the case, we needn't 378262af557SGuo Chao * pick M64 dependent PE#. 379262af557SGuo Chao */ 38092b8f137SGavin Shan if (bitmap_empty(pe_alloc, phb->ioda.total_pe_num)) { 381262af557SGuo Chao kfree(pe_alloc); 3821e916772SGavin Shan return NULL; 383262af557SGuo Chao } 384262af557SGuo Chao 385262af557SGuo Chao /* 386262af557SGuo Chao * Figure out the master PE and put all slave PEs to master 387262af557SGuo Chao * PE's list to form compound PE. 388262af557SGuo Chao */ 389262af557SGuo Chao master_pe = NULL; 390262af557SGuo Chao i = -1; 39192b8f137SGavin Shan while ((i = find_next_bit(pe_alloc, phb->ioda.total_pe_num, i + 1)) < 39292b8f137SGavin Shan phb->ioda.total_pe_num) { 393262af557SGuo Chao pe = &phb->ioda.pe_array[i]; 394262af557SGuo Chao 39593289d8cSGavin Shan phb->ioda.m64_segmap[pe->pe_number] = pe->pe_number; 396262af557SGuo Chao if (!master_pe) { 397262af557SGuo Chao pe->flags |= PNV_IODA_PE_MASTER; 398262af557SGuo Chao INIT_LIST_HEAD(&pe->slaves); 399262af557SGuo Chao master_pe = pe; 400262af557SGuo Chao } else { 401262af557SGuo Chao pe->flags |= PNV_IODA_PE_SLAVE; 402262af557SGuo Chao pe->master = master_pe; 403262af557SGuo Chao list_add_tail(&pe->list, &master_pe->slaves); 404262af557SGuo Chao } 40599451551SGavin Shan 40699451551SGavin Shan /* 40799451551SGavin Shan * P7IOC supports M64DT, which helps mapping M64 segment 40899451551SGavin Shan * to one particular PE#. However, PHB3 has fixed mapping 40999451551SGavin Shan * between M64 segment and PE#. In order to have same logic 41099451551SGavin Shan * for P7IOC and PHB3, we enforce fixed mapping between M64 41199451551SGavin Shan * segment and PE# on P7IOC. 41299451551SGavin Shan */ 41399451551SGavin Shan if (phb->type == PNV_PHB_IODA1) { 41499451551SGavin Shan int64_t rc; 41599451551SGavin Shan 41699451551SGavin Shan rc = opal_pci_map_pe_mmio_window(phb->opal_id, 41799451551SGavin Shan pe->pe_number, OPAL_M64_WINDOW_TYPE, 41899451551SGavin Shan pe->pe_number / PNV_IODA1_M64_SEGS, 41999451551SGavin Shan pe->pe_number % PNV_IODA1_M64_SEGS); 42099451551SGavin Shan if (rc != OPAL_SUCCESS) 4211f52f176SRussell Currey pr_warn("%s: Error %lld mapping M64 for PHB#%x-PE#%x\n", 42299451551SGavin Shan __func__, rc, phb->hose->global_number, 42399451551SGavin Shan pe->pe_number); 42499451551SGavin Shan } 425262af557SGuo Chao } 426262af557SGuo Chao 427262af557SGuo Chao kfree(pe_alloc); 4281e916772SGavin Shan return master_pe; 429262af557SGuo Chao } 430262af557SGuo Chao 431262af557SGuo Chao static void __init pnv_ioda_parse_m64_window(struct pnv_phb *phb) 432262af557SGuo Chao { 433262af557SGuo Chao struct pci_controller *hose = phb->hose; 434262af557SGuo Chao struct device_node *dn = hose->dn; 435262af557SGuo Chao struct resource *res; 436a1339fafSBenjamin Herrenschmidt u32 m64_range[2], i; 4370e7736c6SGavin Shan const __be32 *r; 438262af557SGuo Chao u64 pci_addr; 439262af557SGuo Chao 44099451551SGavin Shan if (phb->type != PNV_PHB_IODA1 && phb->type != PNV_PHB_IODA2) { 4411665c4a8SGavin Shan pr_info(" Not support M64 window\n"); 4421665c4a8SGavin Shan return; 4431665c4a8SGavin Shan } 4441665c4a8SGavin Shan 445e4d54f71SStewart Smith if (!firmware_has_feature(FW_FEATURE_OPAL)) { 446262af557SGuo Chao pr_info(" Firmware too old to support M64 window\n"); 447262af557SGuo Chao return; 448262af557SGuo Chao } 449262af557SGuo Chao 450262af557SGuo Chao r = of_get_property(dn, "ibm,opal-m64-window", NULL); 451262af557SGuo Chao if (!r) { 452b7c670d6SRob Herring pr_info(" No <ibm,opal-m64-window> on %pOF\n", 453b7c670d6SRob Herring dn); 454262af557SGuo Chao return; 455262af557SGuo Chao } 456262af557SGuo Chao 457a1339fafSBenjamin Herrenschmidt /* 458a1339fafSBenjamin Herrenschmidt * Find the available M64 BAR range and pickup the last one for 459a1339fafSBenjamin Herrenschmidt * covering the whole 64-bits space. We support only one range. 460a1339fafSBenjamin Herrenschmidt */ 461a1339fafSBenjamin Herrenschmidt if (of_property_read_u32_array(dn, "ibm,opal-available-m64-ranges", 462a1339fafSBenjamin Herrenschmidt m64_range, 2)) { 463a1339fafSBenjamin Herrenschmidt /* In absence of the property, assume 0..15 */ 464a1339fafSBenjamin Herrenschmidt m64_range[0] = 0; 465a1339fafSBenjamin Herrenschmidt m64_range[1] = 16; 466a1339fafSBenjamin Herrenschmidt } 467a1339fafSBenjamin Herrenschmidt /* We only support 64 bits in our allocator */ 468a1339fafSBenjamin Herrenschmidt if (m64_range[1] > 63) { 469a1339fafSBenjamin Herrenschmidt pr_warn("%s: Limiting M64 range to 63 (from %d) on PHB#%x\n", 470a1339fafSBenjamin Herrenschmidt __func__, m64_range[1], phb->hose->global_number); 471a1339fafSBenjamin Herrenschmidt m64_range[1] = 63; 472a1339fafSBenjamin Herrenschmidt } 473a1339fafSBenjamin Herrenschmidt /* Empty range, no m64 */ 474a1339fafSBenjamin Herrenschmidt if (m64_range[1] <= m64_range[0]) { 475a1339fafSBenjamin Herrenschmidt pr_warn("%s: M64 empty, disabling M64 usage on PHB#%x\n", 476a1339fafSBenjamin Herrenschmidt __func__, phb->hose->global_number); 477a1339fafSBenjamin Herrenschmidt return; 478a1339fafSBenjamin Herrenschmidt } 479a1339fafSBenjamin Herrenschmidt 480a1339fafSBenjamin Herrenschmidt /* Configure M64 informations */ 481262af557SGuo Chao res = &hose->mem_resources[1]; 482e80c4e7cSGavin Shan res->name = dn->full_name; 483262af557SGuo Chao res->start = of_translate_address(dn, r + 2); 484262af557SGuo Chao res->end = res->start + of_read_number(r + 4, 2) - 1; 485262af557SGuo Chao res->flags = (IORESOURCE_MEM | IORESOURCE_MEM_64 | IORESOURCE_PREFETCH); 486262af557SGuo Chao pci_addr = of_read_number(r, 2); 487262af557SGuo Chao hose->mem_offset[1] = res->start - pci_addr; 488262af557SGuo Chao 489262af557SGuo Chao phb->ioda.m64_size = resource_size(res); 49092b8f137SGavin Shan phb->ioda.m64_segsize = phb->ioda.m64_size / phb->ioda.total_pe_num; 491262af557SGuo Chao phb->ioda.m64_base = pci_addr; 492262af557SGuo Chao 493a1339fafSBenjamin Herrenschmidt /* This lines up nicely with the display from processing OF ranges */ 494a1339fafSBenjamin Herrenschmidt pr_info(" MEM 0x%016llx..0x%016llx -> 0x%016llx (M64 #%d..%d)\n", 495a1339fafSBenjamin Herrenschmidt res->start, res->end, pci_addr, m64_range[0], 496a1339fafSBenjamin Herrenschmidt m64_range[0] + m64_range[1] - 1); 497a1339fafSBenjamin Herrenschmidt 498a1339fafSBenjamin Herrenschmidt /* Mark all M64 used up by default */ 499a1339fafSBenjamin Herrenschmidt phb->ioda.m64_bar_alloc = (unsigned long)-1; 500e9863e68SWei Yang 501262af557SGuo Chao /* Use last M64 BAR to cover M64 window */ 502a1339fafSBenjamin Herrenschmidt m64_range[1]--; 503a1339fafSBenjamin Herrenschmidt phb->ioda.m64_bar_idx = m64_range[0] + m64_range[1]; 504a1339fafSBenjamin Herrenschmidt 505a1339fafSBenjamin Herrenschmidt pr_info(" Using M64 #%d as default window\n", phb->ioda.m64_bar_idx); 506a1339fafSBenjamin Herrenschmidt 507a1339fafSBenjamin Herrenschmidt /* Mark remaining ones free */ 508a1339fafSBenjamin Herrenschmidt for (i = m64_range[0]; i < m64_range[1]; i++) 509a1339fafSBenjamin Herrenschmidt clear_bit(i, &phb->ioda.m64_bar_alloc); 510a1339fafSBenjamin Herrenschmidt 511a1339fafSBenjamin Herrenschmidt /* 512a1339fafSBenjamin Herrenschmidt * Setup init functions for M64 based on IODA version, IODA3 uses 513a1339fafSBenjamin Herrenschmidt * the IODA2 code. 514a1339fafSBenjamin Herrenschmidt */ 51599451551SGavin Shan if (phb->type == PNV_PHB_IODA1) 51699451551SGavin Shan phb->init_m64 = pnv_ioda1_init_m64; 51799451551SGavin Shan else 518262af557SGuo Chao phb->init_m64 = pnv_ioda2_init_m64; 519262af557SGuo Chao } 520262af557SGuo Chao 52149dec922SGavin Shan static void pnv_ioda_freeze_pe(struct pnv_phb *phb, int pe_no) 52249dec922SGavin Shan { 52349dec922SGavin Shan struct pnv_ioda_pe *pe = &phb->ioda.pe_array[pe_no]; 52449dec922SGavin Shan struct pnv_ioda_pe *slave; 52549dec922SGavin Shan s64 rc; 52649dec922SGavin Shan 52749dec922SGavin Shan /* Fetch master PE */ 52849dec922SGavin Shan if (pe->flags & PNV_IODA_PE_SLAVE) { 52949dec922SGavin Shan pe = pe->master; 530ec8e4e9dSGavin Shan if (WARN_ON(!pe || !(pe->flags & PNV_IODA_PE_MASTER))) 531ec8e4e9dSGavin Shan return; 532ec8e4e9dSGavin Shan 53349dec922SGavin Shan pe_no = pe->pe_number; 53449dec922SGavin Shan } 53549dec922SGavin Shan 53649dec922SGavin Shan /* Freeze master PE */ 53749dec922SGavin Shan rc = opal_pci_eeh_freeze_set(phb->opal_id, 53849dec922SGavin Shan pe_no, 53949dec922SGavin Shan OPAL_EEH_ACTION_SET_FREEZE_ALL); 54049dec922SGavin Shan if (rc != OPAL_SUCCESS) { 54149dec922SGavin Shan pr_warn("%s: Failure %lld freezing PHB#%x-PE#%x\n", 54249dec922SGavin Shan __func__, rc, phb->hose->global_number, pe_no); 54349dec922SGavin Shan return; 54449dec922SGavin Shan } 54549dec922SGavin Shan 54649dec922SGavin Shan /* Freeze slave PEs */ 54749dec922SGavin Shan if (!(pe->flags & PNV_IODA_PE_MASTER)) 54849dec922SGavin Shan return; 54949dec922SGavin Shan 55049dec922SGavin Shan list_for_each_entry(slave, &pe->slaves, list) { 55149dec922SGavin Shan rc = opal_pci_eeh_freeze_set(phb->opal_id, 55249dec922SGavin Shan slave->pe_number, 55349dec922SGavin Shan OPAL_EEH_ACTION_SET_FREEZE_ALL); 55449dec922SGavin Shan if (rc != OPAL_SUCCESS) 55549dec922SGavin Shan pr_warn("%s: Failure %lld freezing PHB#%x-PE#%x\n", 55649dec922SGavin Shan __func__, rc, phb->hose->global_number, 55749dec922SGavin Shan slave->pe_number); 55849dec922SGavin Shan } 55949dec922SGavin Shan } 56049dec922SGavin Shan 561e51df2c1SAnton Blanchard static int pnv_ioda_unfreeze_pe(struct pnv_phb *phb, int pe_no, int opt) 56249dec922SGavin Shan { 56349dec922SGavin Shan struct pnv_ioda_pe *pe, *slave; 56449dec922SGavin Shan s64 rc; 56549dec922SGavin Shan 56649dec922SGavin Shan /* Find master PE */ 56749dec922SGavin Shan pe = &phb->ioda.pe_array[pe_no]; 56849dec922SGavin Shan if (pe->flags & PNV_IODA_PE_SLAVE) { 56949dec922SGavin Shan pe = pe->master; 57049dec922SGavin Shan WARN_ON(!pe || !(pe->flags & PNV_IODA_PE_MASTER)); 57149dec922SGavin Shan pe_no = pe->pe_number; 57249dec922SGavin Shan } 57349dec922SGavin Shan 57449dec922SGavin Shan /* Clear frozen state for master PE */ 57549dec922SGavin Shan rc = opal_pci_eeh_freeze_clear(phb->opal_id, pe_no, opt); 57649dec922SGavin Shan if (rc != OPAL_SUCCESS) { 57749dec922SGavin Shan pr_warn("%s: Failure %lld clear %d on PHB#%x-PE#%x\n", 57849dec922SGavin Shan __func__, rc, opt, phb->hose->global_number, pe_no); 57949dec922SGavin Shan return -EIO; 58049dec922SGavin Shan } 58149dec922SGavin Shan 58249dec922SGavin Shan if (!(pe->flags & PNV_IODA_PE_MASTER)) 58349dec922SGavin Shan return 0; 58449dec922SGavin Shan 58549dec922SGavin Shan /* Clear frozen state for slave PEs */ 58649dec922SGavin Shan list_for_each_entry(slave, &pe->slaves, list) { 58749dec922SGavin Shan rc = opal_pci_eeh_freeze_clear(phb->opal_id, 58849dec922SGavin Shan slave->pe_number, 58949dec922SGavin Shan opt); 59049dec922SGavin Shan if (rc != OPAL_SUCCESS) { 59149dec922SGavin Shan pr_warn("%s: Failure %lld clear %d on PHB#%x-PE#%x\n", 59249dec922SGavin Shan __func__, rc, opt, phb->hose->global_number, 59349dec922SGavin Shan slave->pe_number); 59449dec922SGavin Shan return -EIO; 59549dec922SGavin Shan } 59649dec922SGavin Shan } 59749dec922SGavin Shan 59849dec922SGavin Shan return 0; 59949dec922SGavin Shan } 60049dec922SGavin Shan 60149dec922SGavin Shan static int pnv_ioda_get_pe_state(struct pnv_phb *phb, int pe_no) 60249dec922SGavin Shan { 60349dec922SGavin Shan struct pnv_ioda_pe *slave, *pe; 604c2057701SAlexey Kardashevskiy u8 fstate = 0, state; 605c2057701SAlexey Kardashevskiy __be16 pcierr = 0; 60649dec922SGavin Shan s64 rc; 60749dec922SGavin Shan 60849dec922SGavin Shan /* Sanity check on PE number */ 60992b8f137SGavin Shan if (pe_no < 0 || pe_no >= phb->ioda.total_pe_num) 61049dec922SGavin Shan return OPAL_EEH_STOPPED_PERM_UNAVAIL; 61149dec922SGavin Shan 61249dec922SGavin Shan /* 61349dec922SGavin Shan * Fetch the master PE and the PE instance might be 61449dec922SGavin Shan * not initialized yet. 61549dec922SGavin Shan */ 61649dec922SGavin Shan pe = &phb->ioda.pe_array[pe_no]; 61749dec922SGavin Shan if (pe->flags & PNV_IODA_PE_SLAVE) { 61849dec922SGavin Shan pe = pe->master; 61949dec922SGavin Shan WARN_ON(!pe || !(pe->flags & PNV_IODA_PE_MASTER)); 62049dec922SGavin Shan pe_no = pe->pe_number; 62149dec922SGavin Shan } 62249dec922SGavin Shan 62349dec922SGavin Shan /* Check the master PE */ 62449dec922SGavin Shan rc = opal_pci_eeh_freeze_status(phb->opal_id, pe_no, 62549dec922SGavin Shan &state, &pcierr, NULL); 62649dec922SGavin Shan if (rc != OPAL_SUCCESS) { 62749dec922SGavin Shan pr_warn("%s: Failure %lld getting " 62849dec922SGavin Shan "PHB#%x-PE#%x state\n", 62949dec922SGavin Shan __func__, rc, 63049dec922SGavin Shan phb->hose->global_number, pe_no); 63149dec922SGavin Shan return OPAL_EEH_STOPPED_TEMP_UNAVAIL; 63249dec922SGavin Shan } 63349dec922SGavin Shan 63449dec922SGavin Shan /* Check the slave PE */ 63549dec922SGavin Shan if (!(pe->flags & PNV_IODA_PE_MASTER)) 63649dec922SGavin Shan return state; 63749dec922SGavin Shan 63849dec922SGavin Shan list_for_each_entry(slave, &pe->slaves, list) { 63949dec922SGavin Shan rc = opal_pci_eeh_freeze_status(phb->opal_id, 64049dec922SGavin Shan slave->pe_number, 64149dec922SGavin Shan &fstate, 64249dec922SGavin Shan &pcierr, 64349dec922SGavin Shan NULL); 64449dec922SGavin Shan if (rc != OPAL_SUCCESS) { 64549dec922SGavin Shan pr_warn("%s: Failure %lld getting " 64649dec922SGavin Shan "PHB#%x-PE#%x state\n", 64749dec922SGavin Shan __func__, rc, 64849dec922SGavin Shan phb->hose->global_number, slave->pe_number); 64949dec922SGavin Shan return OPAL_EEH_STOPPED_TEMP_UNAVAIL; 65049dec922SGavin Shan } 65149dec922SGavin Shan 65249dec922SGavin Shan /* 65349dec922SGavin Shan * Override the result based on the ascending 65449dec922SGavin Shan * priority. 65549dec922SGavin Shan */ 65649dec922SGavin Shan if (fstate > state) 65749dec922SGavin Shan state = fstate; 65849dec922SGavin Shan } 65949dec922SGavin Shan 66049dec922SGavin Shan return state; 66149dec922SGavin Shan } 66249dec922SGavin Shan 663f456834aSIan Munsie struct pnv_ioda_pe *pnv_ioda_get_pe(struct pci_dev *dev) 664184cd4a3SBenjamin Herrenschmidt { 665184cd4a3SBenjamin Herrenschmidt struct pci_controller *hose = pci_bus_to_host(dev->bus); 666184cd4a3SBenjamin Herrenschmidt struct pnv_phb *phb = hose->private_data; 667b72c1f65SBenjamin Herrenschmidt struct pci_dn *pdn = pci_get_pdn(dev); 668184cd4a3SBenjamin Herrenschmidt 669184cd4a3SBenjamin Herrenschmidt if (!pdn) 670184cd4a3SBenjamin Herrenschmidt return NULL; 671184cd4a3SBenjamin Herrenschmidt if (pdn->pe_number == IODA_INVALID_PE) 672184cd4a3SBenjamin Herrenschmidt return NULL; 673184cd4a3SBenjamin Herrenschmidt return &phb->ioda.pe_array[pdn->pe_number]; 674184cd4a3SBenjamin Herrenschmidt } 675184cd4a3SBenjamin Herrenschmidt 676b131a842SGavin Shan static int pnv_ioda_set_one_peltv(struct pnv_phb *phb, 677b131a842SGavin Shan struct pnv_ioda_pe *parent, 678b131a842SGavin Shan struct pnv_ioda_pe *child, 679b131a842SGavin Shan bool is_add) 680b131a842SGavin Shan { 681b131a842SGavin Shan const char *desc = is_add ? "adding" : "removing"; 682b131a842SGavin Shan uint8_t op = is_add ? OPAL_ADD_PE_TO_DOMAIN : 683b131a842SGavin Shan OPAL_REMOVE_PE_FROM_DOMAIN; 684b131a842SGavin Shan struct pnv_ioda_pe *slave; 685b131a842SGavin Shan long rc; 686b131a842SGavin Shan 687b131a842SGavin Shan /* Parent PE affects child PE */ 688b131a842SGavin Shan rc = opal_pci_set_peltv(phb->opal_id, parent->pe_number, 689b131a842SGavin Shan child->pe_number, op); 690b131a842SGavin Shan if (rc != OPAL_SUCCESS) { 691b131a842SGavin Shan pe_warn(child, "OPAL error %ld %s to parent PELTV\n", 692b131a842SGavin Shan rc, desc); 693b131a842SGavin Shan return -ENXIO; 694b131a842SGavin Shan } 695b131a842SGavin Shan 696b131a842SGavin Shan if (!(child->flags & PNV_IODA_PE_MASTER)) 697b131a842SGavin Shan return 0; 698b131a842SGavin Shan 699b131a842SGavin Shan /* Compound case: parent PE affects slave PEs */ 700b131a842SGavin Shan list_for_each_entry(slave, &child->slaves, list) { 701b131a842SGavin Shan rc = opal_pci_set_peltv(phb->opal_id, parent->pe_number, 702b131a842SGavin Shan slave->pe_number, op); 703b131a842SGavin Shan if (rc != OPAL_SUCCESS) { 704b131a842SGavin Shan pe_warn(slave, "OPAL error %ld %s to parent PELTV\n", 705b131a842SGavin Shan rc, desc); 706b131a842SGavin Shan return -ENXIO; 707b131a842SGavin Shan } 708b131a842SGavin Shan } 709b131a842SGavin Shan 710b131a842SGavin Shan return 0; 711b131a842SGavin Shan } 712b131a842SGavin Shan 713b131a842SGavin Shan static int pnv_ioda_set_peltv(struct pnv_phb *phb, 714b131a842SGavin Shan struct pnv_ioda_pe *pe, 715b131a842SGavin Shan bool is_add) 716b131a842SGavin Shan { 717b131a842SGavin Shan struct pnv_ioda_pe *slave; 718781a868fSWei Yang struct pci_dev *pdev = NULL; 719b131a842SGavin Shan int ret; 720b131a842SGavin Shan 721b131a842SGavin Shan /* 722b131a842SGavin Shan * Clear PE frozen state. If it's master PE, we need 723b131a842SGavin Shan * clear slave PE frozen state as well. 724b131a842SGavin Shan */ 725b131a842SGavin Shan if (is_add) { 726b131a842SGavin Shan opal_pci_eeh_freeze_clear(phb->opal_id, pe->pe_number, 727b131a842SGavin Shan OPAL_EEH_ACTION_CLEAR_FREEZE_ALL); 728b131a842SGavin Shan if (pe->flags & PNV_IODA_PE_MASTER) { 729b131a842SGavin Shan list_for_each_entry(slave, &pe->slaves, list) 730b131a842SGavin Shan opal_pci_eeh_freeze_clear(phb->opal_id, 731b131a842SGavin Shan slave->pe_number, 732b131a842SGavin Shan OPAL_EEH_ACTION_CLEAR_FREEZE_ALL); 733b131a842SGavin Shan } 734b131a842SGavin Shan } 735b131a842SGavin Shan 736b131a842SGavin Shan /* 737b131a842SGavin Shan * Associate PE in PELT. We need add the PE into the 738b131a842SGavin Shan * corresponding PELT-V as well. Otherwise, the error 739b131a842SGavin Shan * originated from the PE might contribute to other 740b131a842SGavin Shan * PEs. 741b131a842SGavin Shan */ 742b131a842SGavin Shan ret = pnv_ioda_set_one_peltv(phb, pe, pe, is_add); 743b131a842SGavin Shan if (ret) 744b131a842SGavin Shan return ret; 745b131a842SGavin Shan 746b131a842SGavin Shan /* For compound PEs, any one affects all of them */ 747b131a842SGavin Shan if (pe->flags & PNV_IODA_PE_MASTER) { 748b131a842SGavin Shan list_for_each_entry(slave, &pe->slaves, list) { 749b131a842SGavin Shan ret = pnv_ioda_set_one_peltv(phb, slave, pe, is_add); 750b131a842SGavin Shan if (ret) 751b131a842SGavin Shan return ret; 752b131a842SGavin Shan } 753b131a842SGavin Shan } 754b131a842SGavin Shan 755b131a842SGavin Shan if (pe->flags & (PNV_IODA_PE_BUS_ALL | PNV_IODA_PE_BUS)) 756b131a842SGavin Shan pdev = pe->pbus->self; 757781a868fSWei Yang else if (pe->flags & PNV_IODA_PE_DEV) 758b131a842SGavin Shan pdev = pe->pdev->bus->self; 759781a868fSWei Yang #ifdef CONFIG_PCI_IOV 760781a868fSWei Yang else if (pe->flags & PNV_IODA_PE_VF) 761283e2d8aSGavin Shan pdev = pe->parent_dev; 762781a868fSWei Yang #endif /* CONFIG_PCI_IOV */ 763b131a842SGavin Shan while (pdev) { 764b131a842SGavin Shan struct pci_dn *pdn = pci_get_pdn(pdev); 765b131a842SGavin Shan struct pnv_ioda_pe *parent; 766b131a842SGavin Shan 767b131a842SGavin Shan if (pdn && pdn->pe_number != IODA_INVALID_PE) { 768b131a842SGavin Shan parent = &phb->ioda.pe_array[pdn->pe_number]; 769b131a842SGavin Shan ret = pnv_ioda_set_one_peltv(phb, parent, pe, is_add); 770b131a842SGavin Shan if (ret) 771b131a842SGavin Shan return ret; 772b131a842SGavin Shan } 773b131a842SGavin Shan 774b131a842SGavin Shan pdev = pdev->bus->self; 775b131a842SGavin Shan } 776b131a842SGavin Shan 777b131a842SGavin Shan return 0; 778b131a842SGavin Shan } 779b131a842SGavin Shan 780f724385fSFrederic Barrat static void pnv_ioda_unset_peltv(struct pnv_phb *phb, 781f724385fSFrederic Barrat struct pnv_ioda_pe *pe, 782f724385fSFrederic Barrat struct pci_dev *parent) 783f724385fSFrederic Barrat { 784f724385fSFrederic Barrat int64_t rc; 785f724385fSFrederic Barrat 786f724385fSFrederic Barrat while (parent) { 787f724385fSFrederic Barrat struct pci_dn *pdn = pci_get_pdn(parent); 788f724385fSFrederic Barrat 789f724385fSFrederic Barrat if (pdn && pdn->pe_number != IODA_INVALID_PE) { 790f724385fSFrederic Barrat rc = opal_pci_set_peltv(phb->opal_id, pdn->pe_number, 791f724385fSFrederic Barrat pe->pe_number, 792f724385fSFrederic Barrat OPAL_REMOVE_PE_FROM_DOMAIN); 793f724385fSFrederic Barrat /* XXX What to do in case of error ? */ 794f724385fSFrederic Barrat } 795f724385fSFrederic Barrat parent = parent->bus->self; 796f724385fSFrederic Barrat } 797f724385fSFrederic Barrat 798f724385fSFrederic Barrat opal_pci_eeh_freeze_clear(phb->opal_id, pe->pe_number, 799f724385fSFrederic Barrat OPAL_EEH_ACTION_CLEAR_FREEZE_ALL); 800f724385fSFrederic Barrat 801f724385fSFrederic Barrat /* Disassociate PE in PELT */ 802f724385fSFrederic Barrat rc = opal_pci_set_peltv(phb->opal_id, pe->pe_number, 803f724385fSFrederic Barrat pe->pe_number, OPAL_REMOVE_PE_FROM_DOMAIN); 804f724385fSFrederic Barrat if (rc) 805f724385fSFrederic Barrat pe_warn(pe, "OPAL error %lld remove self from PELTV\n", rc); 806f724385fSFrederic Barrat } 807f724385fSFrederic Barrat 808781a868fSWei Yang static int pnv_ioda_deconfigure_pe(struct pnv_phb *phb, struct pnv_ioda_pe *pe) 809781a868fSWei Yang { 810781a868fSWei Yang struct pci_dev *parent; 811781a868fSWei Yang uint8_t bcomp, dcomp, fcomp; 812781a868fSWei Yang int64_t rc; 813781a868fSWei Yang long rid_end, rid; 814781a868fSWei Yang 815781a868fSWei Yang /* Currently, we just deconfigure VF PE. Bus PE will always there.*/ 816781a868fSWei Yang if (pe->pbus) { 817781a868fSWei Yang int count; 818781a868fSWei Yang 819781a868fSWei Yang dcomp = OPAL_IGNORE_RID_DEVICE_NUMBER; 820781a868fSWei Yang fcomp = OPAL_IGNORE_RID_FUNCTION_NUMBER; 821781a868fSWei Yang parent = pe->pbus->self; 822781a868fSWei Yang if (pe->flags & PNV_IODA_PE_BUS_ALL) 823552aa086SJulia Lawall count = resource_size(&pe->pbus->busn_res); 824781a868fSWei Yang else 825781a868fSWei Yang count = 1; 826781a868fSWei Yang 827781a868fSWei Yang switch(count) { 828781a868fSWei Yang case 1: bcomp = OpalPciBusAll; break; 829781a868fSWei Yang case 2: bcomp = OpalPciBus7Bits; break; 830781a868fSWei Yang case 4: bcomp = OpalPciBus6Bits; break; 831781a868fSWei Yang case 8: bcomp = OpalPciBus5Bits; break; 832781a868fSWei Yang case 16: bcomp = OpalPciBus4Bits; break; 833781a868fSWei Yang case 32: bcomp = OpalPciBus3Bits; break; 834781a868fSWei Yang default: 835781a868fSWei Yang dev_err(&pe->pbus->dev, "Number of subordinate buses %d unsupported\n", 836781a868fSWei Yang count); 837781a868fSWei Yang /* Do an exact match only */ 838781a868fSWei Yang bcomp = OpalPciBusAll; 839781a868fSWei Yang } 840781a868fSWei Yang rid_end = pe->rid + (count << 8); 841781a868fSWei Yang } else { 84293e01a50SGavin Shan #ifdef CONFIG_PCI_IOV 843781a868fSWei Yang if (pe->flags & PNV_IODA_PE_VF) 844781a868fSWei Yang parent = pe->parent_dev; 845781a868fSWei Yang else 84693e01a50SGavin Shan #endif 847781a868fSWei Yang parent = pe->pdev->bus->self; 848781a868fSWei Yang bcomp = OpalPciBusAll; 849781a868fSWei Yang dcomp = OPAL_COMPARE_RID_DEVICE_NUMBER; 850781a868fSWei Yang fcomp = OPAL_COMPARE_RID_FUNCTION_NUMBER; 851781a868fSWei Yang rid_end = pe->rid + 1; 852781a868fSWei Yang } 853781a868fSWei Yang 854781a868fSWei Yang /* Clear the reverse map */ 855781a868fSWei Yang for (rid = pe->rid; rid < rid_end; rid++) 856c127562aSGavin Shan phb->ioda.pe_rmap[rid] = IODA_INVALID_PE; 857781a868fSWei Yang 858f724385fSFrederic Barrat /* 859f724385fSFrederic Barrat * Release from all parents PELT-V. NPUs don't have a PELTV 860f724385fSFrederic Barrat * table 861f724385fSFrederic Barrat */ 862f724385fSFrederic Barrat if (phb->type != PNV_PHB_NPU_NVLINK && phb->type != PNV_PHB_NPU_OCAPI) 863f724385fSFrederic Barrat pnv_ioda_unset_peltv(phb, pe, parent); 864781a868fSWei Yang 865781a868fSWei Yang rc = opal_pci_set_pe(phb->opal_id, pe->pe_number, pe->rid, 866781a868fSWei Yang bcomp, dcomp, fcomp, OPAL_UNMAP_PE); 867781a868fSWei Yang if (rc) 8681e496391SJoe Perches pe_err(pe, "OPAL error %lld trying to setup PELT table\n", rc); 869781a868fSWei Yang 870781a868fSWei Yang pe->pbus = NULL; 871781a868fSWei Yang pe->pdev = NULL; 87293e01a50SGavin Shan #ifdef CONFIG_PCI_IOV 873781a868fSWei Yang pe->parent_dev = NULL; 87493e01a50SGavin Shan #endif 875781a868fSWei Yang 876781a868fSWei Yang return 0; 877781a868fSWei Yang } 878781a868fSWei Yang 879cad5cef6SGreg Kroah-Hartman static int pnv_ioda_configure_pe(struct pnv_phb *phb, struct pnv_ioda_pe *pe) 880184cd4a3SBenjamin Herrenschmidt { 881184cd4a3SBenjamin Herrenschmidt struct pci_dev *parent; 882184cd4a3SBenjamin Herrenschmidt uint8_t bcomp, dcomp, fcomp; 883184cd4a3SBenjamin Herrenschmidt long rc, rid_end, rid; 884184cd4a3SBenjamin Herrenschmidt 885184cd4a3SBenjamin Herrenschmidt /* Bus validation ? */ 886184cd4a3SBenjamin Herrenschmidt if (pe->pbus) { 887184cd4a3SBenjamin Herrenschmidt int count; 888184cd4a3SBenjamin Herrenschmidt 889184cd4a3SBenjamin Herrenschmidt dcomp = OPAL_IGNORE_RID_DEVICE_NUMBER; 890184cd4a3SBenjamin Herrenschmidt fcomp = OPAL_IGNORE_RID_FUNCTION_NUMBER; 891184cd4a3SBenjamin Herrenschmidt parent = pe->pbus->self; 892fb446ad0SGavin Shan if (pe->flags & PNV_IODA_PE_BUS_ALL) 893552aa086SJulia Lawall count = resource_size(&pe->pbus->busn_res); 894fb446ad0SGavin Shan else 895fb446ad0SGavin Shan count = 1; 896fb446ad0SGavin Shan 897184cd4a3SBenjamin Herrenschmidt switch(count) { 898184cd4a3SBenjamin Herrenschmidt case 1: bcomp = OpalPciBusAll; break; 899184cd4a3SBenjamin Herrenschmidt case 2: bcomp = OpalPciBus7Bits; break; 900184cd4a3SBenjamin Herrenschmidt case 4: bcomp = OpalPciBus6Bits; break; 901184cd4a3SBenjamin Herrenschmidt case 8: bcomp = OpalPciBus5Bits; break; 902184cd4a3SBenjamin Herrenschmidt case 16: bcomp = OpalPciBus4Bits; break; 903184cd4a3SBenjamin Herrenschmidt case 32: bcomp = OpalPciBus3Bits; break; 904184cd4a3SBenjamin Herrenschmidt default: 905781a868fSWei Yang dev_err(&pe->pbus->dev, "Number of subordinate buses %d unsupported\n", 906781a868fSWei Yang count); 907184cd4a3SBenjamin Herrenschmidt /* Do an exact match only */ 908184cd4a3SBenjamin Herrenschmidt bcomp = OpalPciBusAll; 909184cd4a3SBenjamin Herrenschmidt } 910184cd4a3SBenjamin Herrenschmidt rid_end = pe->rid + (count << 8); 911184cd4a3SBenjamin Herrenschmidt } else { 912781a868fSWei Yang #ifdef CONFIG_PCI_IOV 913781a868fSWei Yang if (pe->flags & PNV_IODA_PE_VF) 914781a868fSWei Yang parent = pe->parent_dev; 915781a868fSWei Yang else 916781a868fSWei Yang #endif /* CONFIG_PCI_IOV */ 917184cd4a3SBenjamin Herrenschmidt parent = pe->pdev->bus->self; 918184cd4a3SBenjamin Herrenschmidt bcomp = OpalPciBusAll; 919184cd4a3SBenjamin Herrenschmidt dcomp = OPAL_COMPARE_RID_DEVICE_NUMBER; 920184cd4a3SBenjamin Herrenschmidt fcomp = OPAL_COMPARE_RID_FUNCTION_NUMBER; 921184cd4a3SBenjamin Herrenschmidt rid_end = pe->rid + 1; 922184cd4a3SBenjamin Herrenschmidt } 923184cd4a3SBenjamin Herrenschmidt 924631ad691SGavin Shan /* 925631ad691SGavin Shan * Associate PE in PELT. We need add the PE into the 926631ad691SGavin Shan * corresponding PELT-V as well. Otherwise, the error 927631ad691SGavin Shan * originated from the PE might contribute to other 928631ad691SGavin Shan * PEs. 929631ad691SGavin Shan */ 930184cd4a3SBenjamin Herrenschmidt rc = opal_pci_set_pe(phb->opal_id, pe->pe_number, pe->rid, 931184cd4a3SBenjamin Herrenschmidt bcomp, dcomp, fcomp, OPAL_MAP_PE); 932184cd4a3SBenjamin Herrenschmidt if (rc) { 933184cd4a3SBenjamin Herrenschmidt pe_err(pe, "OPAL error %ld trying to setup PELT table\n", rc); 934184cd4a3SBenjamin Herrenschmidt return -ENXIO; 935184cd4a3SBenjamin Herrenschmidt } 936631ad691SGavin Shan 9375d2aa710SAlistair Popple /* 9385d2aa710SAlistair Popple * Configure PELTV. NPUs don't have a PELTV table so skip 9395d2aa710SAlistair Popple * configuration on them. 9405d2aa710SAlistair Popple */ 9417f2c39e9SFrederic Barrat if (phb->type != PNV_PHB_NPU_NVLINK && phb->type != PNV_PHB_NPU_OCAPI) 942b131a842SGavin Shan pnv_ioda_set_peltv(phb, pe, true); 943184cd4a3SBenjamin Herrenschmidt 944184cd4a3SBenjamin Herrenschmidt /* Setup reverse map */ 945184cd4a3SBenjamin Herrenschmidt for (rid = pe->rid; rid < rid_end; rid++) 946184cd4a3SBenjamin Herrenschmidt phb->ioda.pe_rmap[rid] = pe->pe_number; 947184cd4a3SBenjamin Herrenschmidt 948184cd4a3SBenjamin Herrenschmidt /* Setup one MVTs on IODA1 */ 9494773f76bSGavin Shan if (phb->type != PNV_PHB_IODA1) { 9504773f76bSGavin Shan pe->mve_number = 0; 9514773f76bSGavin Shan goto out; 9524773f76bSGavin Shan } 9534773f76bSGavin Shan 954184cd4a3SBenjamin Herrenschmidt pe->mve_number = pe->pe_number; 9554773f76bSGavin Shan rc = opal_pci_set_mve(phb->opal_id, pe->mve_number, pe->pe_number); 9564773f76bSGavin Shan if (rc != OPAL_SUCCESS) { 9571f52f176SRussell Currey pe_err(pe, "OPAL error %ld setting up MVE %x\n", 958184cd4a3SBenjamin Herrenschmidt rc, pe->mve_number); 959184cd4a3SBenjamin Herrenschmidt pe->mve_number = -1; 960184cd4a3SBenjamin Herrenschmidt } else { 961184cd4a3SBenjamin Herrenschmidt rc = opal_pci_set_mve_enable(phb->opal_id, 962cee72d5bSBenjamin Herrenschmidt pe->mve_number, OPAL_ENABLE_MVE); 963184cd4a3SBenjamin Herrenschmidt if (rc) { 9641f52f176SRussell Currey pe_err(pe, "OPAL error %ld enabling MVE %x\n", 965184cd4a3SBenjamin Herrenschmidt rc, pe->mve_number); 966184cd4a3SBenjamin Herrenschmidt pe->mve_number = -1; 967184cd4a3SBenjamin Herrenschmidt } 968184cd4a3SBenjamin Herrenschmidt } 969184cd4a3SBenjamin Herrenschmidt 9704773f76bSGavin Shan out: 971184cd4a3SBenjamin Herrenschmidt return 0; 972184cd4a3SBenjamin Herrenschmidt } 973184cd4a3SBenjamin Herrenschmidt 974781a868fSWei Yang #ifdef CONFIG_PCI_IOV 975781a868fSWei Yang static int pnv_pci_vf_resource_shift(struct pci_dev *dev, int offset) 976781a868fSWei Yang { 977781a868fSWei Yang struct pci_dn *pdn = pci_get_pdn(dev); 978781a868fSWei Yang int i; 979781a868fSWei Yang struct resource *res, res2; 980781a868fSWei Yang resource_size_t size; 981781a868fSWei Yang u16 num_vfs; 982781a868fSWei Yang 983781a868fSWei Yang if (!dev->is_physfn) 984781a868fSWei Yang return -EINVAL; 985781a868fSWei Yang 986781a868fSWei Yang /* 987781a868fSWei Yang * "offset" is in VFs. The M64 windows are sized so that when they 988781a868fSWei Yang * are segmented, each segment is the same size as the IOV BAR. 989781a868fSWei Yang * Each segment is in a separate PE, and the high order bits of the 990781a868fSWei Yang * address are the PE number. Therefore, each VF's BAR is in a 991781a868fSWei Yang * separate PE, and changing the IOV BAR start address changes the 992781a868fSWei Yang * range of PEs the VFs are in. 993781a868fSWei Yang */ 994781a868fSWei Yang num_vfs = pdn->num_vfs; 995781a868fSWei Yang for (i = 0; i < PCI_SRIOV_NUM_BARS; i++) { 996781a868fSWei Yang res = &dev->resource[i + PCI_IOV_RESOURCES]; 997781a868fSWei Yang if (!res->flags || !res->parent) 998781a868fSWei Yang continue; 999781a868fSWei Yang 1000781a868fSWei Yang /* 1001781a868fSWei Yang * The actual IOV BAR range is determined by the start address 1002781a868fSWei Yang * and the actual size for num_vfs VFs BAR. This check is to 1003781a868fSWei Yang * make sure that after shifting, the range will not overlap 1004781a868fSWei Yang * with another device. 1005781a868fSWei Yang */ 1006781a868fSWei Yang size = pci_iov_resource_size(dev, i + PCI_IOV_RESOURCES); 1007781a868fSWei Yang res2.flags = res->flags; 1008781a868fSWei Yang res2.start = res->start + (size * offset); 1009781a868fSWei Yang res2.end = res2.start + (size * num_vfs) - 1; 1010781a868fSWei Yang 1011781a868fSWei Yang if (res2.end > res->end) { 1012781a868fSWei Yang dev_err(&dev->dev, "VF BAR%d: %pR would extend past %pR (trying to enable %d VFs shifted by %d)\n", 1013781a868fSWei Yang i, &res2, res, num_vfs, offset); 1014781a868fSWei Yang return -EBUSY; 1015781a868fSWei Yang } 1016781a868fSWei Yang } 1017781a868fSWei Yang 1018781a868fSWei Yang /* 1019d6f934fdSAlexey Kardashevskiy * Since M64 BAR shares segments among all possible 256 PEs, 1020d6f934fdSAlexey Kardashevskiy * we have to shift the beginning of PF IOV BAR to make it start from 1021d6f934fdSAlexey Kardashevskiy * the segment which belongs to the PE number assigned to the first VF. 1022d6f934fdSAlexey Kardashevskiy * This creates a "hole" in the /proc/iomem which could be used for 1023d6f934fdSAlexey Kardashevskiy * allocating other resources so we reserve this area below and 1024d6f934fdSAlexey Kardashevskiy * release when IOV is released. 1025781a868fSWei Yang */ 1026781a868fSWei Yang for (i = 0; i < PCI_SRIOV_NUM_BARS; i++) { 1027781a868fSWei Yang res = &dev->resource[i + PCI_IOV_RESOURCES]; 1028781a868fSWei Yang if (!res->flags || !res->parent) 1029781a868fSWei Yang continue; 1030781a868fSWei Yang 1031781a868fSWei Yang size = pci_iov_resource_size(dev, i + PCI_IOV_RESOURCES); 1032781a868fSWei Yang res2 = *res; 1033781a868fSWei Yang res->start += size * offset; 1034781a868fSWei Yang 103574703cc4SWei Yang dev_info(&dev->dev, "VF BAR%d: %pR shifted to %pR (%sabling %d VFs shifted by %d)\n", 103674703cc4SWei Yang i, &res2, res, (offset > 0) ? "En" : "Dis", 103774703cc4SWei Yang num_vfs, offset); 1038d6f934fdSAlexey Kardashevskiy 1039d6f934fdSAlexey Kardashevskiy if (offset < 0) { 1040d6f934fdSAlexey Kardashevskiy devm_release_resource(&dev->dev, &pdn->holes[i]); 1041d6f934fdSAlexey Kardashevskiy memset(&pdn->holes[i], 0, sizeof(pdn->holes[i])); 1042d6f934fdSAlexey Kardashevskiy } 1043d6f934fdSAlexey Kardashevskiy 1044781a868fSWei Yang pci_update_resource(dev, i + PCI_IOV_RESOURCES); 1045d6f934fdSAlexey Kardashevskiy 1046d6f934fdSAlexey Kardashevskiy if (offset > 0) { 1047d6f934fdSAlexey Kardashevskiy pdn->holes[i].start = res2.start; 1048d6f934fdSAlexey Kardashevskiy pdn->holes[i].end = res2.start + size * offset - 1; 1049d6f934fdSAlexey Kardashevskiy pdn->holes[i].flags = IORESOURCE_BUS; 1050d6f934fdSAlexey Kardashevskiy pdn->holes[i].name = "pnv_iov_reserved"; 1051d6f934fdSAlexey Kardashevskiy devm_request_resource(&dev->dev, res->parent, 1052d6f934fdSAlexey Kardashevskiy &pdn->holes[i]); 1053d6f934fdSAlexey Kardashevskiy } 1054781a868fSWei Yang } 1055781a868fSWei Yang return 0; 1056781a868fSWei Yang } 1057781a868fSWei Yang #endif /* CONFIG_PCI_IOV */ 1058781a868fSWei Yang 1059cad5cef6SGreg Kroah-Hartman static struct pnv_ioda_pe *pnv_ioda_setup_dev_PE(struct pci_dev *dev) 1060184cd4a3SBenjamin Herrenschmidt { 1061184cd4a3SBenjamin Herrenschmidt struct pci_controller *hose = pci_bus_to_host(dev->bus); 1062184cd4a3SBenjamin Herrenschmidt struct pnv_phb *phb = hose->private_data; 1063b72c1f65SBenjamin Herrenschmidt struct pci_dn *pdn = pci_get_pdn(dev); 1064184cd4a3SBenjamin Herrenschmidt struct pnv_ioda_pe *pe; 1065184cd4a3SBenjamin Herrenschmidt 1066184cd4a3SBenjamin Herrenschmidt if (!pdn) { 1067184cd4a3SBenjamin Herrenschmidt pr_err("%s: Device tree node not associated properly\n", 1068184cd4a3SBenjamin Herrenschmidt pci_name(dev)); 1069184cd4a3SBenjamin Herrenschmidt return NULL; 1070184cd4a3SBenjamin Herrenschmidt } 1071184cd4a3SBenjamin Herrenschmidt if (pdn->pe_number != IODA_INVALID_PE) 1072184cd4a3SBenjamin Herrenschmidt return NULL; 1073184cd4a3SBenjamin Herrenschmidt 10741e916772SGavin Shan pe = pnv_ioda_alloc_pe(phb); 10751e916772SGavin Shan if (!pe) { 1076f2c2cbccSJoe Perches pr_warn("%s: Not enough PE# available, disabling device\n", 1077184cd4a3SBenjamin Herrenschmidt pci_name(dev)); 1078184cd4a3SBenjamin Herrenschmidt return NULL; 1079184cd4a3SBenjamin Herrenschmidt } 1080184cd4a3SBenjamin Herrenschmidt 108105dd7da7SFrederic Barrat /* NOTE: We don't get a reference for the pointer in the PE 108205dd7da7SFrederic Barrat * data structure, both the device and PE structures should be 108305dd7da7SFrederic Barrat * destroyed at the same time. However, removing nvlink 108405dd7da7SFrederic Barrat * devices will need some work. 1085184cd4a3SBenjamin Herrenschmidt * 1086184cd4a3SBenjamin Herrenschmidt * At some point we want to remove the PDN completely anyways 1087184cd4a3SBenjamin Herrenschmidt */ 10881e916772SGavin Shan pdn->pe_number = pe->pe_number; 10895d2aa710SAlistair Popple pe->flags = PNV_IODA_PE_DEV; 1090184cd4a3SBenjamin Herrenschmidt pe->pdev = dev; 1091184cd4a3SBenjamin Herrenschmidt pe->pbus = NULL; 1092184cd4a3SBenjamin Herrenschmidt pe->mve_number = -1; 1093184cd4a3SBenjamin Herrenschmidt pe->rid = dev->bus->number << 8 | pdn->devfn; 1094f724385fSFrederic Barrat pe->device_count++; 1095184cd4a3SBenjamin Herrenschmidt 1096184cd4a3SBenjamin Herrenschmidt pe_info(pe, "Associated device to PE\n"); 1097184cd4a3SBenjamin Herrenschmidt 1098184cd4a3SBenjamin Herrenschmidt if (pnv_ioda_configure_pe(phb, pe)) { 1099184cd4a3SBenjamin Herrenschmidt /* XXX What do we do here ? */ 11001e916772SGavin Shan pnv_ioda_free_pe(pe); 1101184cd4a3SBenjamin Herrenschmidt pdn->pe_number = IODA_INVALID_PE; 1102184cd4a3SBenjamin Herrenschmidt pe->pdev = NULL; 1103184cd4a3SBenjamin Herrenschmidt return NULL; 1104184cd4a3SBenjamin Herrenschmidt } 1105184cd4a3SBenjamin Herrenschmidt 11061d4e89cfSAlexey Kardashevskiy /* Put PE to the list */ 110780f1ff83SFrederic Barrat mutex_lock(&phb->ioda.pe_list_mutex); 11081d4e89cfSAlexey Kardashevskiy list_add_tail(&pe->list, &phb->ioda.pe_list); 110980f1ff83SFrederic Barrat mutex_unlock(&phb->ioda.pe_list_mutex); 1110184cd4a3SBenjamin Herrenschmidt return pe; 1111184cd4a3SBenjamin Herrenschmidt } 1112184cd4a3SBenjamin Herrenschmidt 1113184cd4a3SBenjamin Herrenschmidt static void pnv_ioda_setup_same_PE(struct pci_bus *bus, struct pnv_ioda_pe *pe) 1114184cd4a3SBenjamin Herrenschmidt { 1115184cd4a3SBenjamin Herrenschmidt struct pci_dev *dev; 1116184cd4a3SBenjamin Herrenschmidt 1117184cd4a3SBenjamin Herrenschmidt list_for_each_entry(dev, &bus->devices, bus_list) { 1118b72c1f65SBenjamin Herrenschmidt struct pci_dn *pdn = pci_get_pdn(dev); 1119184cd4a3SBenjamin Herrenschmidt 1120184cd4a3SBenjamin Herrenschmidt if (pdn == NULL) { 1121184cd4a3SBenjamin Herrenschmidt pr_warn("%s: No device node associated with device !\n", 1122184cd4a3SBenjamin Herrenschmidt pci_name(dev)); 1123184cd4a3SBenjamin Herrenschmidt continue; 1124184cd4a3SBenjamin Herrenschmidt } 1125ccd1c191SGavin Shan 1126ccd1c191SGavin Shan /* 1127ccd1c191SGavin Shan * In partial hotplug case, the PCI device might be still 1128ccd1c191SGavin Shan * associated with the PE and needn't attach it to the PE 1129ccd1c191SGavin Shan * again. 1130ccd1c191SGavin Shan */ 1131ccd1c191SGavin Shan if (pdn->pe_number != IODA_INVALID_PE) 1132ccd1c191SGavin Shan continue; 1133ccd1c191SGavin Shan 1134c5f7700bSGavin Shan pe->device_count++; 1135184cd4a3SBenjamin Herrenschmidt pdn->pe_number = pe->pe_number; 1136fb446ad0SGavin Shan if ((pe->flags & PNV_IODA_PE_BUS_ALL) && dev->subordinate) 1137184cd4a3SBenjamin Herrenschmidt pnv_ioda_setup_same_PE(dev->subordinate, pe); 1138184cd4a3SBenjamin Herrenschmidt } 1139184cd4a3SBenjamin Herrenschmidt } 1140184cd4a3SBenjamin Herrenschmidt 1141fb446ad0SGavin Shan /* 1142fb446ad0SGavin Shan * There're 2 types of PCI bus sensitive PEs: One that is compromised of 1143fb446ad0SGavin Shan * single PCI bus. Another one that contains the primary PCI bus and its 1144fb446ad0SGavin Shan * subordinate PCI devices and buses. The second type of PE is normally 1145fb446ad0SGavin Shan * orgiriated by PCIe-to-PCI bridge or PLX switch downstream ports. 1146fb446ad0SGavin Shan */ 11471e916772SGavin Shan static struct pnv_ioda_pe *pnv_ioda_setup_bus_PE(struct pci_bus *bus, bool all) 1148184cd4a3SBenjamin Herrenschmidt { 1149fb446ad0SGavin Shan struct pci_controller *hose = pci_bus_to_host(bus); 1150184cd4a3SBenjamin Herrenschmidt struct pnv_phb *phb = hose->private_data; 11511e916772SGavin Shan struct pnv_ioda_pe *pe = NULL; 1152ccd1c191SGavin Shan unsigned int pe_num; 1153ccd1c191SGavin Shan 1154ccd1c191SGavin Shan /* 1155ccd1c191SGavin Shan * In partial hotplug case, the PE instance might be still alive. 1156ccd1c191SGavin Shan * We should reuse it instead of allocating a new one. 1157ccd1c191SGavin Shan */ 1158ccd1c191SGavin Shan pe_num = phb->ioda.pe_rmap[bus->number << 8]; 1159ccd1c191SGavin Shan if (pe_num != IODA_INVALID_PE) { 1160ccd1c191SGavin Shan pe = &phb->ioda.pe_array[pe_num]; 1161ccd1c191SGavin Shan pnv_ioda_setup_same_PE(bus, pe); 1162ccd1c191SGavin Shan return NULL; 1163ccd1c191SGavin Shan } 1164184cd4a3SBenjamin Herrenschmidt 116563803c39SGavin Shan /* PE number for root bus should have been reserved */ 116663803c39SGavin Shan if (pci_is_root_bus(bus) && 116763803c39SGavin Shan phb->ioda.root_pe_idx != IODA_INVALID_PE) 116863803c39SGavin Shan pe = &phb->ioda.pe_array[phb->ioda.root_pe_idx]; 116963803c39SGavin Shan 1170262af557SGuo Chao /* Check if PE is determined by M64 */ 1171a25de7afSAlexey Kardashevskiy if (!pe) 1172a25de7afSAlexey Kardashevskiy pe = pnv_ioda_pick_m64_pe(bus, all); 1173262af557SGuo Chao 1174262af557SGuo Chao /* The PE number isn't pinned by M64 */ 11751e916772SGavin Shan if (!pe) 11761e916772SGavin Shan pe = pnv_ioda_alloc_pe(phb); 1177262af557SGuo Chao 11781e916772SGavin Shan if (!pe) { 1179f2c2cbccSJoe Perches pr_warn("%s: Not enough PE# available for PCI bus %04x:%02x\n", 1180fb446ad0SGavin Shan __func__, pci_domain_nr(bus), bus->number); 11811e916772SGavin Shan return NULL; 1182184cd4a3SBenjamin Herrenschmidt } 1183184cd4a3SBenjamin Herrenschmidt 1184262af557SGuo Chao pe->flags |= (all ? PNV_IODA_PE_BUS_ALL : PNV_IODA_PE_BUS); 1185184cd4a3SBenjamin Herrenschmidt pe->pbus = bus; 1186184cd4a3SBenjamin Herrenschmidt pe->pdev = NULL; 1187184cd4a3SBenjamin Herrenschmidt pe->mve_number = -1; 1188b918c62eSYinghai Lu pe->rid = bus->busn_res.start << 8; 1189184cd4a3SBenjamin Herrenschmidt 1190fb446ad0SGavin Shan if (all) 11911e496391SJoe Perches pe_info(pe, "Secondary bus %pad..%pad associated with PE#%x\n", 11921e496391SJoe Perches &bus->busn_res.start, &bus->busn_res.end, 11931e496391SJoe Perches pe->pe_number); 1194fb446ad0SGavin Shan else 11951e496391SJoe Perches pe_info(pe, "Secondary bus %pad associated with PE#%x\n", 11961e496391SJoe Perches &bus->busn_res.start, pe->pe_number); 1197184cd4a3SBenjamin Herrenschmidt 1198184cd4a3SBenjamin Herrenschmidt if (pnv_ioda_configure_pe(phb, pe)) { 1199184cd4a3SBenjamin Herrenschmidt /* XXX What do we do here ? */ 12001e916772SGavin Shan pnv_ioda_free_pe(pe); 1201184cd4a3SBenjamin Herrenschmidt pe->pbus = NULL; 12021e916772SGavin Shan return NULL; 1203184cd4a3SBenjamin Herrenschmidt } 1204184cd4a3SBenjamin Herrenschmidt 1205184cd4a3SBenjamin Herrenschmidt /* Associate it with all child devices */ 1206184cd4a3SBenjamin Herrenschmidt pnv_ioda_setup_same_PE(bus, pe); 1207184cd4a3SBenjamin Herrenschmidt 12087ebdf956SGavin Shan /* Put PE to the list */ 12097ebdf956SGavin Shan list_add_tail(&pe->list, &phb->ioda.pe_list); 12101e916772SGavin Shan 12111e916772SGavin Shan return pe; 1212184cd4a3SBenjamin Herrenschmidt } 1213184cd4a3SBenjamin Herrenschmidt 1214b521549aSAlistair Popple static struct pnv_ioda_pe *pnv_ioda_setup_npu_PE(struct pci_dev *npu_pdev) 12155d2aa710SAlistair Popple { 1216b521549aSAlistair Popple int pe_num, found_pe = false, rc; 1217b521549aSAlistair Popple long rid; 1218b521549aSAlistair Popple struct pnv_ioda_pe *pe; 1219b521549aSAlistair Popple struct pci_dev *gpu_pdev; 1220b521549aSAlistair Popple struct pci_dn *npu_pdn; 1221b521549aSAlistair Popple struct pci_controller *hose = pci_bus_to_host(npu_pdev->bus); 1222b521549aSAlistair Popple struct pnv_phb *phb = hose->private_data; 1223b521549aSAlistair Popple 1224b521549aSAlistair Popple /* 122505dd7da7SFrederic Barrat * Intentionally leak a reference on the npu device (for 122605dd7da7SFrederic Barrat * nvlink only; this is not an opencapi path) to make sure it 122705dd7da7SFrederic Barrat * never goes away, as it's been the case all along and some 122805dd7da7SFrederic Barrat * work is needed otherwise. 122905dd7da7SFrederic Barrat */ 123005dd7da7SFrederic Barrat pci_dev_get(npu_pdev); 123105dd7da7SFrederic Barrat 123205dd7da7SFrederic Barrat /* 1233b521549aSAlistair Popple * Due to a hardware errata PE#0 on the NPU is reserved for 1234b521549aSAlistair Popple * error handling. This means we only have three PEs remaining 1235b521549aSAlistair Popple * which need to be assigned to four links, implying some 1236b521549aSAlistair Popple * links must share PEs. 1237b521549aSAlistair Popple * 1238b521549aSAlistair Popple * To achieve this we assign PEs such that NPUs linking the 1239b521549aSAlistair Popple * same GPU get assigned the same PE. 1240b521549aSAlistair Popple */ 1241b521549aSAlistair Popple gpu_pdev = pnv_pci_get_gpu_dev(npu_pdev); 124292b8f137SGavin Shan for (pe_num = 0; pe_num < phb->ioda.total_pe_num; pe_num++) { 1243b521549aSAlistair Popple pe = &phb->ioda.pe_array[pe_num]; 1244b521549aSAlistair Popple if (!pe->pdev) 1245b521549aSAlistair Popple continue; 1246b521549aSAlistair Popple 1247b521549aSAlistair Popple if (pnv_pci_get_gpu_dev(pe->pdev) == gpu_pdev) { 1248b521549aSAlistair Popple /* 1249b521549aSAlistair Popple * This device has the same peer GPU so should 1250b521549aSAlistair Popple * be assigned the same PE as the existing 1251b521549aSAlistair Popple * peer NPU. 1252b521549aSAlistair Popple */ 1253b521549aSAlistair Popple dev_info(&npu_pdev->dev, 12541f52f176SRussell Currey "Associating to existing PE %x\n", pe_num); 1255b521549aSAlistair Popple npu_pdn = pci_get_pdn(npu_pdev); 1256b521549aSAlistair Popple rid = npu_pdev->bus->number << 8 | npu_pdn->devfn; 1257b521549aSAlistair Popple npu_pdn->pe_number = pe_num; 1258b521549aSAlistair Popple phb->ioda.pe_rmap[rid] = pe->pe_number; 1259f724385fSFrederic Barrat pe->device_count++; 1260b521549aSAlistair Popple 1261b521549aSAlistair Popple /* Map the PE to this link */ 1262b521549aSAlistair Popple rc = opal_pci_set_pe(phb->opal_id, pe_num, rid, 1263b521549aSAlistair Popple OpalPciBusAll, 1264b521549aSAlistair Popple OPAL_COMPARE_RID_DEVICE_NUMBER, 1265b521549aSAlistair Popple OPAL_COMPARE_RID_FUNCTION_NUMBER, 1266b521549aSAlistair Popple OPAL_MAP_PE); 1267b521549aSAlistair Popple WARN_ON(rc != OPAL_SUCCESS); 1268b521549aSAlistair Popple found_pe = true; 1269b521549aSAlistair Popple break; 1270b521549aSAlistair Popple } 1271b521549aSAlistair Popple } 1272b521549aSAlistair Popple 1273b521549aSAlistair Popple if (!found_pe) 1274b521549aSAlistair Popple /* 1275b521549aSAlistair Popple * Could not find an existing PE so allocate a new 1276b521549aSAlistair Popple * one. 1277b521549aSAlistair Popple */ 1278b521549aSAlistair Popple return pnv_ioda_setup_dev_PE(npu_pdev); 1279b521549aSAlistair Popple else 1280b521549aSAlistair Popple return pe; 1281b521549aSAlistair Popple } 1282b521549aSAlistair Popple 1283b521549aSAlistair Popple static void pnv_ioda_setup_npu_PEs(struct pci_bus *bus) 1284b521549aSAlistair Popple { 12855d2aa710SAlistair Popple struct pci_dev *pdev; 12865d2aa710SAlistair Popple 12875d2aa710SAlistair Popple list_for_each_entry(pdev, &bus->devices, bus_list) 1288b521549aSAlistair Popple pnv_ioda_setup_npu_PE(pdev); 12895d2aa710SAlistair Popple } 12905d2aa710SAlistair Popple 1291cad5cef6SGreg Kroah-Hartman static void pnv_pci_ioda_setup_PEs(void) 1292fb446ad0SGavin Shan { 12930e759bd7SAlexey Kardashevskiy struct pci_controller *hose; 1294262af557SGuo Chao struct pnv_phb *phb; 12950e759bd7SAlexey Kardashevskiy struct pnv_ioda_pe *pe; 1296fb446ad0SGavin Shan 12970e759bd7SAlexey Kardashevskiy list_for_each_entry(hose, &hose_list, list_node) { 1298262af557SGuo Chao phb = hose->private_data; 12997f2c39e9SFrederic Barrat if (phb->type == PNV_PHB_NPU_NVLINK) { 130008f48f32SAlistair Popple /* PE#0 is needed for error reporting */ 130108f48f32SAlistair Popple pnv_ioda_reserve_pe(phb, 0); 1302b521549aSAlistair Popple pnv_ioda_setup_npu_PEs(hose->bus); 13031ab66d1fSAlistair Popple if (phb->model == PNV_PHB_MODEL_NPU2) 13040e759bd7SAlexey Kardashevskiy WARN_ON_ONCE(pnv_npu2_init(hose)); 1305ccd1c191SGavin Shan } 1306fb446ad0SGavin Shan } 13070e759bd7SAlexey Kardashevskiy list_for_each_entry(hose, &hose_list, list_node) { 13080e759bd7SAlexey Kardashevskiy phb = hose->private_data; 13090e759bd7SAlexey Kardashevskiy if (phb->type != PNV_PHB_IODA2) 13100e759bd7SAlexey Kardashevskiy continue; 13110e759bd7SAlexey Kardashevskiy 13120e759bd7SAlexey Kardashevskiy list_for_each_entry(pe, &phb->ioda.pe_list, list) 13130e759bd7SAlexey Kardashevskiy pnv_npu2_map_lpar(pe, MSR_DR | MSR_PR | MSR_HV); 13140e759bd7SAlexey Kardashevskiy } 1315fb446ad0SGavin Shan } 1316184cd4a3SBenjamin Herrenschmidt 1317a8b2f828SGavin Shan #ifdef CONFIG_PCI_IOV 1318ee8222feSWei Yang static int pnv_pci_vf_release_m64(struct pci_dev *pdev, u16 num_vfs) 1319781a868fSWei Yang { 1320781a868fSWei Yang struct pci_bus *bus; 1321781a868fSWei Yang struct pci_controller *hose; 1322781a868fSWei Yang struct pnv_phb *phb; 1323781a868fSWei Yang struct pci_dn *pdn; 132402639b0eSWei Yang int i, j; 1325ee8222feSWei Yang int m64_bars; 1326781a868fSWei Yang 1327781a868fSWei Yang bus = pdev->bus; 1328781a868fSWei Yang hose = pci_bus_to_host(bus); 1329781a868fSWei Yang phb = hose->private_data; 1330781a868fSWei Yang pdn = pci_get_pdn(pdev); 1331781a868fSWei Yang 1332ee8222feSWei Yang if (pdn->m64_single_mode) 1333ee8222feSWei Yang m64_bars = num_vfs; 1334ee8222feSWei Yang else 1335ee8222feSWei Yang m64_bars = 1; 1336ee8222feSWei Yang 133702639b0eSWei Yang for (i = 0; i < PCI_SRIOV_NUM_BARS; i++) 1338ee8222feSWei Yang for (j = 0; j < m64_bars; j++) { 1339ee8222feSWei Yang if (pdn->m64_map[j][i] == IODA_INVALID_M64) 1340781a868fSWei Yang continue; 1341781a868fSWei Yang opal_pci_phb_mmio_enable(phb->opal_id, 1342ee8222feSWei Yang OPAL_M64_WINDOW_TYPE, pdn->m64_map[j][i], 0); 1343ee8222feSWei Yang clear_bit(pdn->m64_map[j][i], &phb->ioda.m64_bar_alloc); 1344ee8222feSWei Yang pdn->m64_map[j][i] = IODA_INVALID_M64; 1345781a868fSWei Yang } 1346781a868fSWei Yang 1347ee8222feSWei Yang kfree(pdn->m64_map); 1348781a868fSWei Yang return 0; 1349781a868fSWei Yang } 1350781a868fSWei Yang 135102639b0eSWei Yang static int pnv_pci_vf_assign_m64(struct pci_dev *pdev, u16 num_vfs) 1352781a868fSWei Yang { 1353781a868fSWei Yang struct pci_bus *bus; 1354781a868fSWei Yang struct pci_controller *hose; 1355781a868fSWei Yang struct pnv_phb *phb; 1356781a868fSWei Yang struct pci_dn *pdn; 1357781a868fSWei Yang unsigned int win; 1358781a868fSWei Yang struct resource *res; 135902639b0eSWei Yang int i, j; 1360781a868fSWei Yang int64_t rc; 136102639b0eSWei Yang int total_vfs; 136202639b0eSWei Yang resource_size_t size, start; 136302639b0eSWei Yang int pe_num; 1364ee8222feSWei Yang int m64_bars; 1365781a868fSWei Yang 1366781a868fSWei Yang bus = pdev->bus; 1367781a868fSWei Yang hose = pci_bus_to_host(bus); 1368781a868fSWei Yang phb = hose->private_data; 1369781a868fSWei Yang pdn = pci_get_pdn(pdev); 137002639b0eSWei Yang total_vfs = pci_sriov_get_totalvfs(pdev); 1371781a868fSWei Yang 1372ee8222feSWei Yang if (pdn->m64_single_mode) 1373ee8222feSWei Yang m64_bars = num_vfs; 1374ee8222feSWei Yang else 1375ee8222feSWei Yang m64_bars = 1; 137602639b0eSWei Yang 1377fb37e128SMarkus Elfring pdn->m64_map = kmalloc_array(m64_bars, 1378fb37e128SMarkus Elfring sizeof(*pdn->m64_map), 1379fb37e128SMarkus Elfring GFP_KERNEL); 1380ee8222feSWei Yang if (!pdn->m64_map) 1381ee8222feSWei Yang return -ENOMEM; 1382ee8222feSWei Yang /* Initialize the m64_map to IODA_INVALID_M64 */ 1383ee8222feSWei Yang for (i = 0; i < m64_bars ; i++) 1384ee8222feSWei Yang for (j = 0; j < PCI_SRIOV_NUM_BARS; j++) 1385ee8222feSWei Yang pdn->m64_map[i][j] = IODA_INVALID_M64; 1386ee8222feSWei Yang 1387781a868fSWei Yang 1388781a868fSWei Yang for (i = 0; i < PCI_SRIOV_NUM_BARS; i++) { 1389781a868fSWei Yang res = &pdev->resource[i + PCI_IOV_RESOURCES]; 1390781a868fSWei Yang if (!res->flags || !res->parent) 1391781a868fSWei Yang continue; 1392781a868fSWei Yang 1393ee8222feSWei Yang for (j = 0; j < m64_bars; j++) { 1394781a868fSWei Yang do { 1395781a868fSWei Yang win = find_next_zero_bit(&phb->ioda.m64_bar_alloc, 1396781a868fSWei Yang phb->ioda.m64_bar_idx + 1, 0); 1397781a868fSWei Yang 1398781a868fSWei Yang if (win >= phb->ioda.m64_bar_idx + 1) 1399781a868fSWei Yang goto m64_failed; 1400781a868fSWei Yang } while (test_and_set_bit(win, &phb->ioda.m64_bar_alloc)); 1401781a868fSWei Yang 1402ee8222feSWei Yang pdn->m64_map[j][i] = win; 140302639b0eSWei Yang 1404ee8222feSWei Yang if (pdn->m64_single_mode) { 140502639b0eSWei Yang size = pci_iov_resource_size(pdev, 140602639b0eSWei Yang PCI_IOV_RESOURCES + i); 140702639b0eSWei Yang start = res->start + size * j; 140802639b0eSWei Yang } else { 140902639b0eSWei Yang size = resource_size(res); 141002639b0eSWei Yang start = res->start; 141102639b0eSWei Yang } 1412781a868fSWei Yang 1413781a868fSWei Yang /* Map the M64 here */ 1414ee8222feSWei Yang if (pdn->m64_single_mode) { 1415be283eebSWei Yang pe_num = pdn->pe_num_map[j]; 141602639b0eSWei Yang rc = opal_pci_map_pe_mmio_window(phb->opal_id, 141702639b0eSWei Yang pe_num, OPAL_M64_WINDOW_TYPE, 1418ee8222feSWei Yang pdn->m64_map[j][i], 0); 141902639b0eSWei Yang } 142002639b0eSWei Yang 1421781a868fSWei Yang rc = opal_pci_set_phb_mem_window(phb->opal_id, 1422781a868fSWei Yang OPAL_M64_WINDOW_TYPE, 1423ee8222feSWei Yang pdn->m64_map[j][i], 142402639b0eSWei Yang start, 1425781a868fSWei Yang 0, /* unused */ 142602639b0eSWei Yang size); 142702639b0eSWei Yang 142802639b0eSWei Yang 1429781a868fSWei Yang if (rc != OPAL_SUCCESS) { 1430781a868fSWei Yang dev_err(&pdev->dev, "Failed to map M64 window #%d: %lld\n", 1431781a868fSWei Yang win, rc); 1432781a868fSWei Yang goto m64_failed; 1433781a868fSWei Yang } 1434781a868fSWei Yang 1435ee8222feSWei Yang if (pdn->m64_single_mode) 1436781a868fSWei Yang rc = opal_pci_phb_mmio_enable(phb->opal_id, 1437ee8222feSWei Yang OPAL_M64_WINDOW_TYPE, pdn->m64_map[j][i], 2); 143802639b0eSWei Yang else 143902639b0eSWei Yang rc = opal_pci_phb_mmio_enable(phb->opal_id, 1440ee8222feSWei Yang OPAL_M64_WINDOW_TYPE, pdn->m64_map[j][i], 1); 144102639b0eSWei Yang 1442781a868fSWei Yang if (rc != OPAL_SUCCESS) { 1443781a868fSWei Yang dev_err(&pdev->dev, "Failed to enable M64 window #%d: %llx\n", 1444781a868fSWei Yang win, rc); 1445781a868fSWei Yang goto m64_failed; 1446781a868fSWei Yang } 1447781a868fSWei Yang } 144802639b0eSWei Yang } 1449781a868fSWei Yang return 0; 1450781a868fSWei Yang 1451781a868fSWei Yang m64_failed: 1452ee8222feSWei Yang pnv_pci_vf_release_m64(pdev, num_vfs); 1453781a868fSWei Yang return -EBUSY; 1454781a868fSWei Yang } 1455781a868fSWei Yang 1456c035e37bSAlexey Kardashevskiy static long pnv_pci_ioda2_unset_window(struct iommu_table_group *table_group, 1457c035e37bSAlexey Kardashevskiy int num); 1458c035e37bSAlexey Kardashevskiy 1459781a868fSWei Yang static void pnv_pci_ioda2_release_dma_pe(struct pci_dev *dev, struct pnv_ioda_pe *pe) 1460781a868fSWei Yang { 1461781a868fSWei Yang struct iommu_table *tbl; 1462781a868fSWei Yang int64_t rc; 1463781a868fSWei Yang 1464b348aa65SAlexey Kardashevskiy tbl = pe->table_group.tables[0]; 1465c035e37bSAlexey Kardashevskiy rc = pnv_pci_ioda2_unset_window(&pe->table_group, 0); 1466781a868fSWei Yang if (rc) 14671e496391SJoe Perches pe_warn(pe, "OPAL error %lld release DMA window\n", rc); 1468781a868fSWei Yang 1469c035e37bSAlexey Kardashevskiy pnv_pci_ioda2_set_bypass(pe, false); 14700eaf4defSAlexey Kardashevskiy if (pe->table_group.group) { 14710eaf4defSAlexey Kardashevskiy iommu_group_put(pe->table_group.group); 14720eaf4defSAlexey Kardashevskiy BUG_ON(pe->table_group.group); 1473ac9a5889SAlexey Kardashevskiy } 1474e5afdf9dSAlexey Kardashevskiy iommu_tce_table_put(tbl); 1475781a868fSWei Yang } 1476781a868fSWei Yang 1477ee8222feSWei Yang static void pnv_ioda_release_vf_PE(struct pci_dev *pdev) 1478781a868fSWei Yang { 1479781a868fSWei Yang struct pci_bus *bus; 1480781a868fSWei Yang struct pci_controller *hose; 1481781a868fSWei Yang struct pnv_phb *phb; 1482781a868fSWei Yang struct pnv_ioda_pe *pe, *pe_n; 1483781a868fSWei Yang struct pci_dn *pdn; 1484781a868fSWei Yang 1485781a868fSWei Yang bus = pdev->bus; 1486781a868fSWei Yang hose = pci_bus_to_host(bus); 1487781a868fSWei Yang phb = hose->private_data; 148802639b0eSWei Yang pdn = pci_get_pdn(pdev); 1489781a868fSWei Yang 1490781a868fSWei Yang if (!pdev->is_physfn) 1491781a868fSWei Yang return; 1492781a868fSWei Yang 1493781a868fSWei Yang list_for_each_entry_safe(pe, pe_n, &phb->ioda.pe_list, list) { 1494781a868fSWei Yang if (pe->parent_dev != pdev) 1495781a868fSWei Yang continue; 1496781a868fSWei Yang 1497781a868fSWei Yang pnv_pci_ioda2_release_dma_pe(pdev, pe); 1498781a868fSWei Yang 1499781a868fSWei Yang /* Remove from list */ 1500781a868fSWei Yang mutex_lock(&phb->ioda.pe_list_mutex); 1501781a868fSWei Yang list_del(&pe->list); 1502781a868fSWei Yang mutex_unlock(&phb->ioda.pe_list_mutex); 1503781a868fSWei Yang 1504781a868fSWei Yang pnv_ioda_deconfigure_pe(phb, pe); 1505781a868fSWei Yang 15061e916772SGavin Shan pnv_ioda_free_pe(pe); 1507781a868fSWei Yang } 1508781a868fSWei Yang } 1509781a868fSWei Yang 1510781a868fSWei Yang void pnv_pci_sriov_disable(struct pci_dev *pdev) 1511781a868fSWei Yang { 1512781a868fSWei Yang struct pci_bus *bus; 1513781a868fSWei Yang struct pci_controller *hose; 1514781a868fSWei Yang struct pnv_phb *phb; 15151e916772SGavin Shan struct pnv_ioda_pe *pe; 1516781a868fSWei Yang struct pci_dn *pdn; 1517be283eebSWei Yang u16 num_vfs, i; 1518781a868fSWei Yang 1519781a868fSWei Yang bus = pdev->bus; 1520781a868fSWei Yang hose = pci_bus_to_host(bus); 1521781a868fSWei Yang phb = hose->private_data; 1522781a868fSWei Yang pdn = pci_get_pdn(pdev); 1523781a868fSWei Yang num_vfs = pdn->num_vfs; 1524781a868fSWei Yang 1525781a868fSWei Yang /* Release VF PEs */ 1526ee8222feSWei Yang pnv_ioda_release_vf_PE(pdev); 1527781a868fSWei Yang 1528781a868fSWei Yang if (phb->type == PNV_PHB_IODA2) { 1529ee8222feSWei Yang if (!pdn->m64_single_mode) 1530be283eebSWei Yang pnv_pci_vf_resource_shift(pdev, -*pdn->pe_num_map); 1531781a868fSWei Yang 1532781a868fSWei Yang /* Release M64 windows */ 1533ee8222feSWei Yang pnv_pci_vf_release_m64(pdev, num_vfs); 1534781a868fSWei Yang 1535781a868fSWei Yang /* Release PE numbers */ 1536be283eebSWei Yang if (pdn->m64_single_mode) { 1537be283eebSWei Yang for (i = 0; i < num_vfs; i++) { 15381e916772SGavin Shan if (pdn->pe_num_map[i] == IODA_INVALID_PE) 15391e916772SGavin Shan continue; 15401e916772SGavin Shan 15411e916772SGavin Shan pe = &phb->ioda.pe_array[pdn->pe_num_map[i]]; 15421e916772SGavin Shan pnv_ioda_free_pe(pe); 1543be283eebSWei Yang } 1544be283eebSWei Yang } else 1545be283eebSWei Yang bitmap_clear(phb->ioda.pe_alloc, *pdn->pe_num_map, num_vfs); 1546be283eebSWei Yang /* Releasing pe_num_map */ 1547be283eebSWei Yang kfree(pdn->pe_num_map); 1548781a868fSWei Yang } 1549781a868fSWei Yang } 1550781a868fSWei Yang 1551781a868fSWei Yang static void pnv_pci_ioda2_setup_dma_pe(struct pnv_phb *phb, 1552781a868fSWei Yang struct pnv_ioda_pe *pe); 15535eada8a3SAlexey Kardashevskiy #ifdef CONFIG_IOMMU_API 15540bd97167SAlexey Kardashevskiy static void pnv_ioda_setup_bus_iommu_group(struct pnv_ioda_pe *pe, 15550bd97167SAlexey Kardashevskiy struct iommu_table_group *table_group, struct pci_bus *bus); 15560bd97167SAlexey Kardashevskiy 15575eada8a3SAlexey Kardashevskiy #endif 1558781a868fSWei Yang static void pnv_ioda_setup_vf_PE(struct pci_dev *pdev, u16 num_vfs) 1559781a868fSWei Yang { 1560781a868fSWei Yang struct pci_bus *bus; 1561781a868fSWei Yang struct pci_controller *hose; 1562781a868fSWei Yang struct pnv_phb *phb; 1563781a868fSWei Yang struct pnv_ioda_pe *pe; 1564781a868fSWei Yang int pe_num; 1565781a868fSWei Yang u16 vf_index; 1566781a868fSWei Yang struct pci_dn *pdn; 1567781a868fSWei Yang 1568781a868fSWei Yang bus = pdev->bus; 1569781a868fSWei Yang hose = pci_bus_to_host(bus); 1570781a868fSWei Yang phb = hose->private_data; 1571781a868fSWei Yang pdn = pci_get_pdn(pdev); 1572781a868fSWei Yang 1573781a868fSWei Yang if (!pdev->is_physfn) 1574781a868fSWei Yang return; 1575781a868fSWei Yang 1576781a868fSWei Yang /* Reserve PE for each VF */ 1577781a868fSWei Yang for (vf_index = 0; vf_index < num_vfs; vf_index++) { 15783b5b9997SOliver O'Halloran int vf_devfn = pci_iov_virtfn_devfn(pdev, vf_index); 15793b5b9997SOliver O'Halloran int vf_bus = pci_iov_virtfn_bus(pdev, vf_index); 15803b5b9997SOliver O'Halloran struct pci_dn *vf_pdn; 15813b5b9997SOliver O'Halloran 1582be283eebSWei Yang if (pdn->m64_single_mode) 1583be283eebSWei Yang pe_num = pdn->pe_num_map[vf_index]; 1584be283eebSWei Yang else 1585be283eebSWei Yang pe_num = *pdn->pe_num_map + vf_index; 1586781a868fSWei Yang 1587781a868fSWei Yang pe = &phb->ioda.pe_array[pe_num]; 1588781a868fSWei Yang pe->pe_number = pe_num; 1589781a868fSWei Yang pe->phb = phb; 1590781a868fSWei Yang pe->flags = PNV_IODA_PE_VF; 1591781a868fSWei Yang pe->pbus = NULL; 1592781a868fSWei Yang pe->parent_dev = pdev; 1593781a868fSWei Yang pe->mve_number = -1; 15943b5b9997SOliver O'Halloran pe->rid = (vf_bus << 8) | vf_devfn; 1595781a868fSWei Yang 15961f52f176SRussell Currey pe_info(pe, "VF %04d:%02d:%02d.%d associated with PE#%x\n", 1597781a868fSWei Yang hose->global_number, pdev->bus->number, 15983b5b9997SOliver O'Halloran PCI_SLOT(vf_devfn), PCI_FUNC(vf_devfn), pe_num); 1599781a868fSWei Yang 1600781a868fSWei Yang if (pnv_ioda_configure_pe(phb, pe)) { 1601781a868fSWei Yang /* XXX What do we do here ? */ 16021e916772SGavin Shan pnv_ioda_free_pe(pe); 1603781a868fSWei Yang pe->pdev = NULL; 1604781a868fSWei Yang continue; 1605781a868fSWei Yang } 1606781a868fSWei Yang 1607781a868fSWei Yang /* Put PE to the list */ 1608781a868fSWei Yang mutex_lock(&phb->ioda.pe_list_mutex); 1609781a868fSWei Yang list_add_tail(&pe->list, &phb->ioda.pe_list); 1610781a868fSWei Yang mutex_unlock(&phb->ioda.pe_list_mutex); 1611781a868fSWei Yang 16123b5b9997SOliver O'Halloran /* associate this pe to it's pdn */ 16133b5b9997SOliver O'Halloran list_for_each_entry(vf_pdn, &pdn->parent->child_list, list) { 16143b5b9997SOliver O'Halloran if (vf_pdn->busno == vf_bus && 16153b5b9997SOliver O'Halloran vf_pdn->devfn == vf_devfn) { 16163b5b9997SOliver O'Halloran vf_pdn->pe_number = pe_num; 16173b5b9997SOliver O'Halloran break; 16183b5b9997SOliver O'Halloran } 16193b5b9997SOliver O'Halloran } 16203b5b9997SOliver O'Halloran 1621781a868fSWei Yang pnv_pci_ioda2_setup_dma_pe(phb, pe); 1622781a868fSWei Yang } 1623781a868fSWei Yang } 1624781a868fSWei Yang 1625781a868fSWei Yang int pnv_pci_sriov_enable(struct pci_dev *pdev, u16 num_vfs) 1626781a868fSWei Yang { 1627781a868fSWei Yang struct pci_bus *bus; 1628781a868fSWei Yang struct pci_controller *hose; 1629781a868fSWei Yang struct pnv_phb *phb; 16301e916772SGavin Shan struct pnv_ioda_pe *pe; 1631781a868fSWei Yang struct pci_dn *pdn; 1632781a868fSWei Yang int ret; 1633be283eebSWei Yang u16 i; 1634781a868fSWei Yang 1635781a868fSWei Yang bus = pdev->bus; 1636781a868fSWei Yang hose = pci_bus_to_host(bus); 1637781a868fSWei Yang phb = hose->private_data; 1638781a868fSWei Yang pdn = pci_get_pdn(pdev); 1639781a868fSWei Yang 1640781a868fSWei Yang if (phb->type == PNV_PHB_IODA2) { 1641b0331854SWei Yang if (!pdn->vfs_expanded) { 1642b0331854SWei Yang dev_info(&pdev->dev, "don't support this SRIOV device" 1643b0331854SWei Yang " with non 64bit-prefetchable IOV BAR\n"); 1644b0331854SWei Yang return -ENOSPC; 1645b0331854SWei Yang } 1646b0331854SWei Yang 1647ee8222feSWei Yang /* 1648ee8222feSWei Yang * When M64 BARs functions in Single PE mode, the number of VFs 1649ee8222feSWei Yang * could be enabled must be less than the number of M64 BARs. 1650ee8222feSWei Yang */ 1651ee8222feSWei Yang if (pdn->m64_single_mode && num_vfs > phb->ioda.m64_bar_idx) { 1652ee8222feSWei Yang dev_info(&pdev->dev, "Not enough M64 BAR for VFs\n"); 1653ee8222feSWei Yang return -EBUSY; 1654ee8222feSWei Yang } 1655ee8222feSWei Yang 1656be283eebSWei Yang /* Allocating pe_num_map */ 1657be283eebSWei Yang if (pdn->m64_single_mode) 1658fb37e128SMarkus Elfring pdn->pe_num_map = kmalloc_array(num_vfs, 1659fb37e128SMarkus Elfring sizeof(*pdn->pe_num_map), 1660be283eebSWei Yang GFP_KERNEL); 1661be283eebSWei Yang else 1662be283eebSWei Yang pdn->pe_num_map = kmalloc(sizeof(*pdn->pe_num_map), GFP_KERNEL); 1663be283eebSWei Yang 1664be283eebSWei Yang if (!pdn->pe_num_map) 1665be283eebSWei Yang return -ENOMEM; 1666be283eebSWei Yang 1667be283eebSWei Yang if (pdn->m64_single_mode) 1668be283eebSWei Yang for (i = 0; i < num_vfs; i++) 1669be283eebSWei Yang pdn->pe_num_map[i] = IODA_INVALID_PE; 1670be283eebSWei Yang 1671781a868fSWei Yang /* Calculate available PE for required VFs */ 1672be283eebSWei Yang if (pdn->m64_single_mode) { 1673be283eebSWei Yang for (i = 0; i < num_vfs; i++) { 16741e916772SGavin Shan pe = pnv_ioda_alloc_pe(phb); 16751e916772SGavin Shan if (!pe) { 1676be283eebSWei Yang ret = -EBUSY; 1677be283eebSWei Yang goto m64_failed; 1678be283eebSWei Yang } 16791e916772SGavin Shan 16801e916772SGavin Shan pdn->pe_num_map[i] = pe->pe_number; 1681be283eebSWei Yang } 1682be283eebSWei Yang } else { 1683781a868fSWei Yang mutex_lock(&phb->ioda.pe_alloc_mutex); 1684be283eebSWei Yang *pdn->pe_num_map = bitmap_find_next_zero_area( 168592b8f137SGavin Shan phb->ioda.pe_alloc, phb->ioda.total_pe_num, 1686781a868fSWei Yang 0, num_vfs, 0); 168792b8f137SGavin Shan if (*pdn->pe_num_map >= phb->ioda.total_pe_num) { 1688781a868fSWei Yang mutex_unlock(&phb->ioda.pe_alloc_mutex); 1689781a868fSWei Yang dev_info(&pdev->dev, "Failed to enable VF%d\n", num_vfs); 1690be283eebSWei Yang kfree(pdn->pe_num_map); 1691781a868fSWei Yang return -EBUSY; 1692781a868fSWei Yang } 1693be283eebSWei Yang bitmap_set(phb->ioda.pe_alloc, *pdn->pe_num_map, num_vfs); 1694781a868fSWei Yang mutex_unlock(&phb->ioda.pe_alloc_mutex); 1695be283eebSWei Yang } 1696be283eebSWei Yang pdn->num_vfs = num_vfs; 1697781a868fSWei Yang 1698781a868fSWei Yang /* Assign M64 window accordingly */ 169902639b0eSWei Yang ret = pnv_pci_vf_assign_m64(pdev, num_vfs); 1700781a868fSWei Yang if (ret) { 1701781a868fSWei Yang dev_info(&pdev->dev, "Not enough M64 window resources\n"); 1702781a868fSWei Yang goto m64_failed; 1703781a868fSWei Yang } 1704781a868fSWei Yang 1705781a868fSWei Yang /* 1706781a868fSWei Yang * When using one M64 BAR to map one IOV BAR, we need to shift 1707781a868fSWei Yang * the IOV BAR according to the PE# allocated to the VFs. 1708781a868fSWei Yang * Otherwise, the PE# for the VF will conflict with others. 1709781a868fSWei Yang */ 1710ee8222feSWei Yang if (!pdn->m64_single_mode) { 1711be283eebSWei Yang ret = pnv_pci_vf_resource_shift(pdev, *pdn->pe_num_map); 1712781a868fSWei Yang if (ret) 1713781a868fSWei Yang goto m64_failed; 1714781a868fSWei Yang } 171502639b0eSWei Yang } 1716781a868fSWei Yang 1717781a868fSWei Yang /* Setup VF PEs */ 1718781a868fSWei Yang pnv_ioda_setup_vf_PE(pdev, num_vfs); 1719781a868fSWei Yang 1720781a868fSWei Yang return 0; 1721781a868fSWei Yang 1722781a868fSWei Yang m64_failed: 1723be283eebSWei Yang if (pdn->m64_single_mode) { 1724be283eebSWei Yang for (i = 0; i < num_vfs; i++) { 17251e916772SGavin Shan if (pdn->pe_num_map[i] == IODA_INVALID_PE) 17261e916772SGavin Shan continue; 17271e916772SGavin Shan 17281e916772SGavin Shan pe = &phb->ioda.pe_array[pdn->pe_num_map[i]]; 17291e916772SGavin Shan pnv_ioda_free_pe(pe); 1730be283eebSWei Yang } 1731be283eebSWei Yang } else 1732be283eebSWei Yang bitmap_clear(phb->ioda.pe_alloc, *pdn->pe_num_map, num_vfs); 1733be283eebSWei Yang 1734be283eebSWei Yang /* Releasing pe_num_map */ 1735be283eebSWei Yang kfree(pdn->pe_num_map); 1736781a868fSWei Yang 1737781a868fSWei Yang return ret; 1738781a868fSWei Yang } 1739781a868fSWei Yang 1740988fc3baSBryant G. Ly int pnv_pcibios_sriov_disable(struct pci_dev *pdev) 1741a8b2f828SGavin Shan { 1742781a868fSWei Yang pnv_pci_sriov_disable(pdev); 1743781a868fSWei Yang 1744a8b2f828SGavin Shan /* Release PCI data */ 17458cd6aaccSOliver O'Halloran remove_sriov_vf_pdns(pdev); 1746a8b2f828SGavin Shan return 0; 1747a8b2f828SGavin Shan } 1748a8b2f828SGavin Shan 1749988fc3baSBryant G. Ly int pnv_pcibios_sriov_enable(struct pci_dev *pdev, u16 num_vfs) 1750a8b2f828SGavin Shan { 1751a8b2f828SGavin Shan /* Allocate PCI data */ 17528cd6aaccSOliver O'Halloran add_sriov_vf_pdns(pdev); 1753781a868fSWei Yang 1754ee8222feSWei Yang return pnv_pci_sriov_enable(pdev, num_vfs); 1755a8b2f828SGavin Shan } 1756a8b2f828SGavin Shan #endif /* CONFIG_PCI_IOV */ 1757a8b2f828SGavin Shan 17580a25d9c4SOliver O'Halloran static void pnv_pci_ioda_dma_dev_setup(struct pci_dev *pdev) 1759184cd4a3SBenjamin Herrenschmidt { 17600a25d9c4SOliver O'Halloran struct pci_controller *hose = pci_bus_to_host(pdev->bus); 17610a25d9c4SOliver O'Halloran struct pnv_phb *phb = hose->private_data; 1762b72c1f65SBenjamin Herrenschmidt struct pci_dn *pdn = pci_get_pdn(pdev); 1763959c9bddSGavin Shan struct pnv_ioda_pe *pe; 1764184cd4a3SBenjamin Herrenschmidt 1765959c9bddSGavin Shan /* 1766959c9bddSGavin Shan * The function can be called while the PE# 1767959c9bddSGavin Shan * hasn't been assigned. Do nothing for the 1768959c9bddSGavin Shan * case. 1769959c9bddSGavin Shan */ 1770959c9bddSGavin Shan if (!pdn || pdn->pe_number == IODA_INVALID_PE) 1771959c9bddSGavin Shan return; 1772184cd4a3SBenjamin Herrenschmidt 1773959c9bddSGavin Shan pe = &phb->ioda.pe_array[pdn->pe_number]; 1774cd15b048SBenjamin Herrenschmidt WARN_ON(get_dma_ops(&pdev->dev) != &dma_iommu_ops); 17750617fc0cSChristoph Hellwig pdev->dev.archdata.dma_offset = pe->tce_bypass_base; 1776b348aa65SAlexey Kardashevskiy set_iommu_table_base(&pdev->dev, pe->table_group.tables[0]); 17774617082eSAlexey Kardashevskiy /* 17784617082eSAlexey Kardashevskiy * Note: iommu_add_device() will fail here as 17794617082eSAlexey Kardashevskiy * for physical PE: the device is already added by now; 17804617082eSAlexey Kardashevskiy * for virtual PE: sysfs entries are not ready yet and 17814617082eSAlexey Kardashevskiy * tce_iommu_bus_notifier will add the device to a group later. 17824617082eSAlexey Kardashevskiy */ 1783184cd4a3SBenjamin Herrenschmidt } 1784184cd4a3SBenjamin Herrenschmidt 17858e3f1b1dSRussell Currey /* 17868e3f1b1dSRussell Currey * Reconfigure TVE#0 to be usable as 64-bit DMA space. 17878e3f1b1dSRussell Currey * 17888e3f1b1dSRussell Currey * The first 4GB of virtual memory for a PE is reserved for 32-bit accesses. 17898e3f1b1dSRussell Currey * Devices can only access more than that if bit 59 of the PCI address is set 17908e3f1b1dSRussell Currey * by hardware, which indicates TVE#1 should be used instead of TVE#0. 17918e3f1b1dSRussell Currey * Many PCI devices are not capable of addressing that many bits, and as a 17928e3f1b1dSRussell Currey * result are limited to the 4GB of virtual memory made available to 32-bit 17938e3f1b1dSRussell Currey * devices in TVE#0. 17948e3f1b1dSRussell Currey * 17958e3f1b1dSRussell Currey * In order to work around this, reconfigure TVE#0 to be suitable for 64-bit 17968e3f1b1dSRussell Currey * devices by configuring the virtual memory past the first 4GB inaccessible 17978e3f1b1dSRussell Currey * by 64-bit DMAs. This should only be used by devices that want more than 17988e3f1b1dSRussell Currey * 4GB, and only on PEs that have no 32-bit devices. 17998e3f1b1dSRussell Currey * 18008e3f1b1dSRussell Currey * Currently this will only work on PHB3 (POWER8). 18018e3f1b1dSRussell Currey */ 18028e3f1b1dSRussell Currey static int pnv_pci_ioda_dma_64bit_bypass(struct pnv_ioda_pe *pe) 18038e3f1b1dSRussell Currey { 18048e3f1b1dSRussell Currey u64 window_size, table_size, tce_count, addr; 18058e3f1b1dSRussell Currey struct page *table_pages; 18068e3f1b1dSRussell Currey u64 tce_order = 28; /* 256MB TCEs */ 18078e3f1b1dSRussell Currey __be64 *tces; 18088e3f1b1dSRussell Currey s64 rc; 18098e3f1b1dSRussell Currey 18108e3f1b1dSRussell Currey /* 18118e3f1b1dSRussell Currey * Window size needs to be a power of two, but needs to account for 18128e3f1b1dSRussell Currey * shifting memory by the 4GB offset required to skip 32bit space. 18138e3f1b1dSRussell Currey */ 18148e3f1b1dSRussell Currey window_size = roundup_pow_of_two(memory_hotplug_max() + (1ULL << 32)); 18158e3f1b1dSRussell Currey tce_count = window_size >> tce_order; 18168e3f1b1dSRussell Currey table_size = tce_count << 3; 18178e3f1b1dSRussell Currey 18188e3f1b1dSRussell Currey if (table_size < PAGE_SIZE) 18198e3f1b1dSRussell Currey table_size = PAGE_SIZE; 18208e3f1b1dSRussell Currey 18218e3f1b1dSRussell Currey table_pages = alloc_pages_node(pe->phb->hose->node, GFP_KERNEL, 18228e3f1b1dSRussell Currey get_order(table_size)); 18238e3f1b1dSRussell Currey if (!table_pages) 18248e3f1b1dSRussell Currey goto err; 18258e3f1b1dSRussell Currey 18268e3f1b1dSRussell Currey tces = page_address(table_pages); 18278e3f1b1dSRussell Currey if (!tces) 18288e3f1b1dSRussell Currey goto err; 18298e3f1b1dSRussell Currey 18308e3f1b1dSRussell Currey memset(tces, 0, table_size); 18318e3f1b1dSRussell Currey 18328e3f1b1dSRussell Currey for (addr = 0; addr < memory_hotplug_max(); addr += (1 << tce_order)) { 18338e3f1b1dSRussell Currey tces[(addr + (1ULL << 32)) >> tce_order] = 18348e3f1b1dSRussell Currey cpu_to_be64(addr | TCE_PCI_READ | TCE_PCI_WRITE); 18358e3f1b1dSRussell Currey } 18368e3f1b1dSRussell Currey 18378e3f1b1dSRussell Currey rc = opal_pci_map_pe_dma_window(pe->phb->opal_id, 18388e3f1b1dSRussell Currey pe->pe_number, 18398e3f1b1dSRussell Currey /* reconfigure window 0 */ 18408e3f1b1dSRussell Currey (pe->pe_number << 1) + 0, 18418e3f1b1dSRussell Currey 1, 18428e3f1b1dSRussell Currey __pa(tces), 18438e3f1b1dSRussell Currey table_size, 18448e3f1b1dSRussell Currey 1 << tce_order); 18458e3f1b1dSRussell Currey if (rc == OPAL_SUCCESS) { 18468e3f1b1dSRussell Currey pe_info(pe, "Using 64-bit DMA iommu bypass (through TVE#0)\n"); 18478e3f1b1dSRussell Currey return 0; 18488e3f1b1dSRussell Currey } 18498e3f1b1dSRussell Currey err: 18508e3f1b1dSRussell Currey pe_err(pe, "Error configuring 64-bit DMA bypass\n"); 18518e3f1b1dSRussell Currey return -EIO; 18528e3f1b1dSRussell Currey } 18538e3f1b1dSRussell Currey 18542d6ad41bSChristoph Hellwig static bool pnv_pci_ioda_iommu_bypass_supported(struct pci_dev *pdev, 18552d6ad41bSChristoph Hellwig u64 dma_mask) 1856cd15b048SBenjamin Herrenschmidt { 1857763d2d8dSDaniel Axtens struct pci_controller *hose = pci_bus_to_host(pdev->bus); 1858763d2d8dSDaniel Axtens struct pnv_phb *phb = hose->private_data; 1859cd15b048SBenjamin Herrenschmidt struct pci_dn *pdn = pci_get_pdn(pdev); 1860cd15b048SBenjamin Herrenschmidt struct pnv_ioda_pe *pe; 1861cd15b048SBenjamin Herrenschmidt 1862cd15b048SBenjamin Herrenschmidt if (WARN_ON(!pdn || pdn->pe_number == IODA_INVALID_PE)) 1863b511cdd1SAlexey Kardashevskiy return false; 1864cd15b048SBenjamin Herrenschmidt 1865cd15b048SBenjamin Herrenschmidt pe = &phb->ioda.pe_array[pdn->pe_number]; 1866cd15b048SBenjamin Herrenschmidt if (pe->tce_bypass_enabled) { 18672d6ad41bSChristoph Hellwig u64 top = pe->tce_bypass_base + memblock_end_of_DRAM() - 1; 18682d6ad41bSChristoph Hellwig if (dma_mask >= top) 18692d6ad41bSChristoph Hellwig return true; 1870cd15b048SBenjamin Herrenschmidt } 1871cd15b048SBenjamin Herrenschmidt 18728e3f1b1dSRussell Currey /* 18738e3f1b1dSRussell Currey * If the device can't set the TCE bypass bit but still wants 18748e3f1b1dSRussell Currey * to access 4GB or more, on PHB3 we can reconfigure TVE#0 to 18758e3f1b1dSRussell Currey * bypass the 32-bit region and be usable for 64-bit DMAs. 18768e3f1b1dSRussell Currey * The device needs to be able to address all of this space. 18778e3f1b1dSRussell Currey */ 18788e3f1b1dSRussell Currey if (dma_mask >> 32 && 18798e3f1b1dSRussell Currey dma_mask > (memory_hotplug_max() + (1ULL << 32)) && 1880661fcb45SChristoph Hellwig /* pe->pdev should be set if it's a single device, pe->pbus if not */ 1881661fcb45SChristoph Hellwig (pe->device_count == 1 || !pe->pbus) && 18828e3f1b1dSRussell Currey phb->model == PNV_PHB_MODEL_PHB3) { 18838e3f1b1dSRussell Currey /* Configure the bypass mode */ 18842d6ad41bSChristoph Hellwig s64 rc = pnv_pci_ioda_dma_64bit_bypass(pe); 18858e3f1b1dSRussell Currey if (rc) 1886b511cdd1SAlexey Kardashevskiy return false; 18878e3f1b1dSRussell Currey /* 4GB offset bypasses 32-bit space */ 18880617fc0cSChristoph Hellwig pdev->dev.archdata.dma_offset = (1ULL << 32); 18892d6ad41bSChristoph Hellwig return true; 1890cd15b048SBenjamin Herrenschmidt } 1891cd15b048SBenjamin Herrenschmidt 18922d6ad41bSChristoph Hellwig return false; 1893fe7e85c6SGavin Shan } 1894fe7e85c6SGavin Shan 18955eada8a3SAlexey Kardashevskiy static void pnv_ioda_setup_bus_dma(struct pnv_ioda_pe *pe, struct pci_bus *bus) 189674251fe2SBenjamin Herrenschmidt { 189774251fe2SBenjamin Herrenschmidt struct pci_dev *dev; 189874251fe2SBenjamin Herrenschmidt 189974251fe2SBenjamin Herrenschmidt list_for_each_entry(dev, &bus->devices, bus_list) { 1900b348aa65SAlexey Kardashevskiy set_iommu_table_base(&dev->dev, pe->table_group.tables[0]); 19010617fc0cSChristoph Hellwig dev->dev.archdata.dma_offset = pe->tce_bypass_base; 1902dff4a39eSGavin Shan 19035c89a87dSAlexey Kardashevskiy if ((pe->flags & PNV_IODA_PE_BUS_ALL) && dev->subordinate) 19045eada8a3SAlexey Kardashevskiy pnv_ioda_setup_bus_dma(pe, dev->subordinate); 190574251fe2SBenjamin Herrenschmidt } 190674251fe2SBenjamin Herrenschmidt } 190774251fe2SBenjamin Herrenschmidt 1908fd141d1aSBenjamin Herrenschmidt static inline __be64 __iomem *pnv_ioda_get_inval_reg(struct pnv_phb *phb, 1909fd141d1aSBenjamin Herrenschmidt bool real_mode) 1910fd141d1aSBenjamin Herrenschmidt { 1911fd141d1aSBenjamin Herrenschmidt return real_mode ? (__be64 __iomem *)(phb->regs_phys + 0x210) : 1912fd141d1aSBenjamin Herrenschmidt (phb->regs + 0x210); 1913fd141d1aSBenjamin Herrenschmidt } 1914fd141d1aSBenjamin Herrenschmidt 1915a34ab7c3SBenjamin Herrenschmidt static void pnv_pci_p7ioc_tce_invalidate(struct iommu_table *tbl, 1916decbda25SAlexey Kardashevskiy unsigned long index, unsigned long npages, bool rm) 19174cce9550SGavin Shan { 19180eaf4defSAlexey Kardashevskiy struct iommu_table_group_link *tgl = list_first_entry_or_null( 19190eaf4defSAlexey Kardashevskiy &tbl->it_group_list, struct iommu_table_group_link, 19200eaf4defSAlexey Kardashevskiy next); 19210eaf4defSAlexey Kardashevskiy struct pnv_ioda_pe *pe = container_of(tgl->table_group, 1922b348aa65SAlexey Kardashevskiy struct pnv_ioda_pe, table_group); 1923fd141d1aSBenjamin Herrenschmidt __be64 __iomem *invalidate = pnv_ioda_get_inval_reg(pe->phb, rm); 19244cce9550SGavin Shan unsigned long start, end, inc; 19254cce9550SGavin Shan 1926decbda25SAlexey Kardashevskiy start = __pa(((__be64 *)tbl->it_base) + index - tbl->it_offset); 1927decbda25SAlexey Kardashevskiy end = __pa(((__be64 *)tbl->it_base) + index - tbl->it_offset + 1928decbda25SAlexey Kardashevskiy npages - 1); 19294cce9550SGavin Shan 19304cce9550SGavin Shan /* p7ioc-style invalidation, 2 TCEs per write */ 19314cce9550SGavin Shan start |= (1ull << 63); 19324cce9550SGavin Shan end |= (1ull << 63); 19334cce9550SGavin Shan inc = 16; 19344cce9550SGavin Shan end |= inc - 1; /* round up end to be different than start */ 19354cce9550SGavin Shan 19364cce9550SGavin Shan mb(); /* Ensure above stores are visible */ 19374cce9550SGavin Shan while (start <= end) { 19388e0a1611SAlexey Kardashevskiy if (rm) 1939001ff2eeSMichael Ellerman __raw_rm_writeq_be(start, invalidate); 19408e0a1611SAlexey Kardashevskiy else 1941001ff2eeSMichael Ellerman __raw_writeq_be(start, invalidate); 1942001ff2eeSMichael Ellerman 19434cce9550SGavin Shan start += inc; 19444cce9550SGavin Shan } 19454cce9550SGavin Shan 19464cce9550SGavin Shan /* 19474cce9550SGavin Shan * The iommu layer will do another mb() for us on build() 19484cce9550SGavin Shan * and we don't care on free() 19494cce9550SGavin Shan */ 19504cce9550SGavin Shan } 19514cce9550SGavin Shan 1952decbda25SAlexey Kardashevskiy static int pnv_ioda1_tce_build(struct iommu_table *tbl, long index, 1953decbda25SAlexey Kardashevskiy long npages, unsigned long uaddr, 1954decbda25SAlexey Kardashevskiy enum dma_data_direction direction, 195500085f1eSKrzysztof Kozlowski unsigned long attrs) 1956decbda25SAlexey Kardashevskiy { 1957decbda25SAlexey Kardashevskiy int ret = pnv_tce_build(tbl, index, npages, uaddr, direction, 1958decbda25SAlexey Kardashevskiy attrs); 1959decbda25SAlexey Kardashevskiy 196008acce1cSBenjamin Herrenschmidt if (!ret) 1961a34ab7c3SBenjamin Herrenschmidt pnv_pci_p7ioc_tce_invalidate(tbl, index, npages, false); 1962decbda25SAlexey Kardashevskiy 1963decbda25SAlexey Kardashevskiy return ret; 1964decbda25SAlexey Kardashevskiy } 1965decbda25SAlexey Kardashevskiy 196605c6cfb9SAlexey Kardashevskiy #ifdef CONFIG_IOMMU_API 196735872480SAlexey Kardashevskiy /* Common for IODA1 and IODA2 */ 196835872480SAlexey Kardashevskiy static int pnv_ioda_tce_xchg_no_kill(struct iommu_table *tbl, long index, 196935872480SAlexey Kardashevskiy unsigned long *hpa, enum dma_data_direction *direction, 197035872480SAlexey Kardashevskiy bool realmode) 197105c6cfb9SAlexey Kardashevskiy { 197235872480SAlexey Kardashevskiy return pnv_tce_xchg(tbl, index, hpa, direction, !realmode); 1973a540aa56SAlexey Kardashevskiy } 197405c6cfb9SAlexey Kardashevskiy #endif 197505c6cfb9SAlexey Kardashevskiy 1976decbda25SAlexey Kardashevskiy static void pnv_ioda1_tce_free(struct iommu_table *tbl, long index, 1977decbda25SAlexey Kardashevskiy long npages) 1978decbda25SAlexey Kardashevskiy { 1979decbda25SAlexey Kardashevskiy pnv_tce_free(tbl, index, npages); 1980decbda25SAlexey Kardashevskiy 1981a34ab7c3SBenjamin Herrenschmidt pnv_pci_p7ioc_tce_invalidate(tbl, index, npages, false); 1982decbda25SAlexey Kardashevskiy } 1983decbda25SAlexey Kardashevskiy 1984da004c36SAlexey Kardashevskiy static struct iommu_table_ops pnv_ioda1_iommu_ops = { 1985decbda25SAlexey Kardashevskiy .set = pnv_ioda1_tce_build, 198605c6cfb9SAlexey Kardashevskiy #ifdef CONFIG_IOMMU_API 198735872480SAlexey Kardashevskiy .xchg_no_kill = pnv_ioda_tce_xchg_no_kill, 198835872480SAlexey Kardashevskiy .tce_kill = pnv_pci_p7ioc_tce_invalidate, 1989090bad39SAlexey Kardashevskiy .useraddrptr = pnv_tce_useraddrptr, 199005c6cfb9SAlexey Kardashevskiy #endif 1991decbda25SAlexey Kardashevskiy .clear = pnv_ioda1_tce_free, 1992da004c36SAlexey Kardashevskiy .get = pnv_tce_get, 1993da004c36SAlexey Kardashevskiy }; 1994da004c36SAlexey Kardashevskiy 1995a34ab7c3SBenjamin Herrenschmidt #define PHB3_TCE_KILL_INVAL_ALL PPC_BIT(0) 1996a34ab7c3SBenjamin Herrenschmidt #define PHB3_TCE_KILL_INVAL_PE PPC_BIT(1) 1997a34ab7c3SBenjamin Herrenschmidt #define PHB3_TCE_KILL_INVAL_ONE PPC_BIT(2) 1998bef9253fSAlexey Kardashevskiy 19996b3d12a9SAlistair Popple static void pnv_pci_phb3_tce_invalidate_entire(struct pnv_phb *phb, bool rm) 20000bbcdb43SAlexey Kardashevskiy { 2001fd141d1aSBenjamin Herrenschmidt __be64 __iomem *invalidate = pnv_ioda_get_inval_reg(phb, rm); 2002a34ab7c3SBenjamin Herrenschmidt const unsigned long val = PHB3_TCE_KILL_INVAL_ALL; 20030bbcdb43SAlexey Kardashevskiy 20040bbcdb43SAlexey Kardashevskiy mb(); /* Ensure previous TCE table stores are visible */ 20050bbcdb43SAlexey Kardashevskiy if (rm) 2006001ff2eeSMichael Ellerman __raw_rm_writeq_be(val, invalidate); 20070bbcdb43SAlexey Kardashevskiy else 2008001ff2eeSMichael Ellerman __raw_writeq_be(val, invalidate); 20090bbcdb43SAlexey Kardashevskiy } 20100bbcdb43SAlexey Kardashevskiy 2011a34ab7c3SBenjamin Herrenschmidt static inline void pnv_pci_phb3_tce_invalidate_pe(struct pnv_ioda_pe *pe) 20125780fb04SAlexey Kardashevskiy { 20135780fb04SAlexey Kardashevskiy /* 01xb - invalidate TCEs that match the specified PE# */ 2014fd141d1aSBenjamin Herrenschmidt __be64 __iomem *invalidate = pnv_ioda_get_inval_reg(pe->phb, false); 2015a34ab7c3SBenjamin Herrenschmidt unsigned long val = PHB3_TCE_KILL_INVAL_PE | (pe->pe_number & 0xFF); 20165780fb04SAlexey Kardashevskiy 20175780fb04SAlexey Kardashevskiy mb(); /* Ensure above stores are visible */ 2018001ff2eeSMichael Ellerman __raw_writeq_be(val, invalidate); 20195780fb04SAlexey Kardashevskiy } 20205780fb04SAlexey Kardashevskiy 2021fd141d1aSBenjamin Herrenschmidt static void pnv_pci_phb3_tce_invalidate(struct pnv_ioda_pe *pe, bool rm, 2022fd141d1aSBenjamin Herrenschmidt unsigned shift, unsigned long index, 2023fd141d1aSBenjamin Herrenschmidt unsigned long npages) 20244cce9550SGavin Shan { 20254d902195SAlexey Kardashevskiy __be64 __iomem *invalidate = pnv_ioda_get_inval_reg(pe->phb, rm); 20264cce9550SGavin Shan unsigned long start, end, inc; 20274cce9550SGavin Shan 20284cce9550SGavin Shan /* We'll invalidate DMA address in PE scope */ 2029a34ab7c3SBenjamin Herrenschmidt start = PHB3_TCE_KILL_INVAL_ONE; 2030fd141d1aSBenjamin Herrenschmidt start |= (pe->pe_number & 0xFF); 20314cce9550SGavin Shan end = start; 20324cce9550SGavin Shan 20334cce9550SGavin Shan /* Figure out the start, end and step */ 2034decbda25SAlexey Kardashevskiy start |= (index << shift); 2035decbda25SAlexey Kardashevskiy end |= ((index + npages - 1) << shift); 2036b0376c9bSAlexey Kardashevskiy inc = (0x1ull << shift); 20374cce9550SGavin Shan mb(); 20384cce9550SGavin Shan 20394cce9550SGavin Shan while (start <= end) { 20408e0a1611SAlexey Kardashevskiy if (rm) 2041001ff2eeSMichael Ellerman __raw_rm_writeq_be(start, invalidate); 20428e0a1611SAlexey Kardashevskiy else 2043001ff2eeSMichael Ellerman __raw_writeq_be(start, invalidate); 20444cce9550SGavin Shan start += inc; 20454cce9550SGavin Shan } 20464cce9550SGavin Shan } 20474cce9550SGavin Shan 2048f0228c41SBenjamin Herrenschmidt static inline void pnv_pci_ioda2_tce_invalidate_pe(struct pnv_ioda_pe *pe) 2049f0228c41SBenjamin Herrenschmidt { 2050f0228c41SBenjamin Herrenschmidt struct pnv_phb *phb = pe->phb; 2051f0228c41SBenjamin Herrenschmidt 2052f0228c41SBenjamin Herrenschmidt if (phb->model == PNV_PHB_MODEL_PHB3 && phb->regs) 2053f0228c41SBenjamin Herrenschmidt pnv_pci_phb3_tce_invalidate_pe(pe); 2054f0228c41SBenjamin Herrenschmidt else 2055f0228c41SBenjamin Herrenschmidt opal_pci_tce_kill(phb->opal_id, OPAL_PCI_TCE_KILL_PE, 2056f0228c41SBenjamin Herrenschmidt pe->pe_number, 0, 0, 0); 2057f0228c41SBenjamin Herrenschmidt } 2058f0228c41SBenjamin Herrenschmidt 2059e57080f1SAlexey Kardashevskiy static void pnv_pci_ioda2_tce_invalidate(struct iommu_table *tbl, 2060e57080f1SAlexey Kardashevskiy unsigned long index, unsigned long npages, bool rm) 2061e57080f1SAlexey Kardashevskiy { 2062e57080f1SAlexey Kardashevskiy struct iommu_table_group_link *tgl; 2063e57080f1SAlexey Kardashevskiy 2064a540aa56SAlexey Kardashevskiy list_for_each_entry_lockless(tgl, &tbl->it_group_list, next) { 2065e57080f1SAlexey Kardashevskiy struct pnv_ioda_pe *pe = container_of(tgl->table_group, 2066e57080f1SAlexey Kardashevskiy struct pnv_ioda_pe, table_group); 2067f0228c41SBenjamin Herrenschmidt struct pnv_phb *phb = pe->phb; 2068f0228c41SBenjamin Herrenschmidt unsigned int shift = tbl->it_page_shift; 2069f0228c41SBenjamin Herrenschmidt 2070616badd2SAlistair Popple /* 2071616badd2SAlistair Popple * NVLink1 can use the TCE kill register directly as 2072616badd2SAlistair Popple * it's the same as PHB3. NVLink2 is different and 2073616badd2SAlistair Popple * should go via the OPAL call. 2074616badd2SAlistair Popple */ 2075616badd2SAlistair Popple if (phb->model == PNV_PHB_MODEL_NPU) { 20760bbcdb43SAlexey Kardashevskiy /* 20770bbcdb43SAlexey Kardashevskiy * The NVLink hardware does not support TCE kill 20780bbcdb43SAlexey Kardashevskiy * per TCE entry so we have to invalidate 20790bbcdb43SAlexey Kardashevskiy * the entire cache for it. 20800bbcdb43SAlexey Kardashevskiy */ 2081f0228c41SBenjamin Herrenschmidt pnv_pci_phb3_tce_invalidate_entire(phb, rm); 20825d2aa710SAlistair Popple continue; 20835d2aa710SAlistair Popple } 2084f0228c41SBenjamin Herrenschmidt if (phb->model == PNV_PHB_MODEL_PHB3 && phb->regs) 2085f0228c41SBenjamin Herrenschmidt pnv_pci_phb3_tce_invalidate(pe, rm, shift, 208685674868SAlexey Kardashevskiy index, npages); 2087f0228c41SBenjamin Herrenschmidt else 2088f0228c41SBenjamin Herrenschmidt opal_pci_tce_kill(phb->opal_id, 2089f0228c41SBenjamin Herrenschmidt OPAL_PCI_TCE_KILL_PAGES, 2090f0228c41SBenjamin Herrenschmidt pe->pe_number, 1u << shift, 2091f0228c41SBenjamin Herrenschmidt index << shift, npages); 2092e57080f1SAlexey Kardashevskiy } 2093e57080f1SAlexey Kardashevskiy } 2094e57080f1SAlexey Kardashevskiy 20956b3d12a9SAlistair Popple void pnv_pci_ioda2_tce_invalidate_entire(struct pnv_phb *phb, bool rm) 20966b3d12a9SAlistair Popple { 20976b3d12a9SAlistair Popple if (phb->model == PNV_PHB_MODEL_NPU || phb->model == PNV_PHB_MODEL_PHB3) 20986b3d12a9SAlistair Popple pnv_pci_phb3_tce_invalidate_entire(phb, rm); 20996b3d12a9SAlistair Popple else 21006b3d12a9SAlistair Popple opal_pci_tce_kill(phb->opal_id, OPAL_PCI_TCE_KILL, 0, 0, 0, 0); 21016b3d12a9SAlistair Popple } 21026b3d12a9SAlistair Popple 2103decbda25SAlexey Kardashevskiy static int pnv_ioda2_tce_build(struct iommu_table *tbl, long index, 2104decbda25SAlexey Kardashevskiy long npages, unsigned long uaddr, 2105decbda25SAlexey Kardashevskiy enum dma_data_direction direction, 210600085f1eSKrzysztof Kozlowski unsigned long attrs) 21074cce9550SGavin Shan { 2108decbda25SAlexey Kardashevskiy int ret = pnv_tce_build(tbl, index, npages, uaddr, direction, 2109decbda25SAlexey Kardashevskiy attrs); 21104cce9550SGavin Shan 211108acce1cSBenjamin Herrenschmidt if (!ret) 2112decbda25SAlexey Kardashevskiy pnv_pci_ioda2_tce_invalidate(tbl, index, npages, false); 2113decbda25SAlexey Kardashevskiy 2114decbda25SAlexey Kardashevskiy return ret; 2115decbda25SAlexey Kardashevskiy } 2116decbda25SAlexey Kardashevskiy 2117decbda25SAlexey Kardashevskiy static void pnv_ioda2_tce_free(struct iommu_table *tbl, long index, 2118decbda25SAlexey Kardashevskiy long npages) 2119decbda25SAlexey Kardashevskiy { 2120decbda25SAlexey Kardashevskiy pnv_tce_free(tbl, index, npages); 2121decbda25SAlexey Kardashevskiy 2122decbda25SAlexey Kardashevskiy pnv_pci_ioda2_tce_invalidate(tbl, index, npages, false); 21234cce9550SGavin Shan } 21244cce9550SGavin Shan 2125da004c36SAlexey Kardashevskiy static struct iommu_table_ops pnv_ioda2_iommu_ops = { 2126decbda25SAlexey Kardashevskiy .set = pnv_ioda2_tce_build, 212705c6cfb9SAlexey Kardashevskiy #ifdef CONFIG_IOMMU_API 212835872480SAlexey Kardashevskiy .xchg_no_kill = pnv_ioda_tce_xchg_no_kill, 212935872480SAlexey Kardashevskiy .tce_kill = pnv_pci_ioda2_tce_invalidate, 2130090bad39SAlexey Kardashevskiy .useraddrptr = pnv_tce_useraddrptr, 213105c6cfb9SAlexey Kardashevskiy #endif 2132decbda25SAlexey Kardashevskiy .clear = pnv_ioda2_tce_free, 2133da004c36SAlexey Kardashevskiy .get = pnv_tce_get, 2134da2bb0daSAlexey Kardashevskiy .free = pnv_pci_ioda2_table_free_pages, 2135da004c36SAlexey Kardashevskiy }; 2136da004c36SAlexey Kardashevskiy 2137801846d1SGavin Shan static int pnv_pci_ioda_dev_dma_weight(struct pci_dev *dev, void *data) 2138801846d1SGavin Shan { 2139801846d1SGavin Shan unsigned int *weight = (unsigned int *)data; 2140801846d1SGavin Shan 2141801846d1SGavin Shan /* This is quite simplistic. The "base" weight of a device 2142801846d1SGavin Shan * is 10. 0 means no DMA is to be accounted for it. 2143801846d1SGavin Shan */ 2144801846d1SGavin Shan if (dev->hdr_type != PCI_HEADER_TYPE_NORMAL) 2145801846d1SGavin Shan return 0; 2146801846d1SGavin Shan 2147801846d1SGavin Shan if (dev->class == PCI_CLASS_SERIAL_USB_UHCI || 2148801846d1SGavin Shan dev->class == PCI_CLASS_SERIAL_USB_OHCI || 2149801846d1SGavin Shan dev->class == PCI_CLASS_SERIAL_USB_EHCI) 2150801846d1SGavin Shan *weight += 3; 2151801846d1SGavin Shan else if ((dev->class >> 8) == PCI_CLASS_STORAGE_RAID) 2152801846d1SGavin Shan *weight += 15; 2153801846d1SGavin Shan else 2154801846d1SGavin Shan *weight += 10; 2155801846d1SGavin Shan 2156801846d1SGavin Shan return 0; 2157801846d1SGavin Shan } 2158801846d1SGavin Shan 2159801846d1SGavin Shan static unsigned int pnv_pci_ioda_pe_dma_weight(struct pnv_ioda_pe *pe) 2160801846d1SGavin Shan { 2161801846d1SGavin Shan unsigned int weight = 0; 2162801846d1SGavin Shan 2163801846d1SGavin Shan /* SRIOV VF has same DMA32 weight as its PF */ 2164801846d1SGavin Shan #ifdef CONFIG_PCI_IOV 2165801846d1SGavin Shan if ((pe->flags & PNV_IODA_PE_VF) && pe->parent_dev) { 2166801846d1SGavin Shan pnv_pci_ioda_dev_dma_weight(pe->parent_dev, &weight); 2167801846d1SGavin Shan return weight; 2168801846d1SGavin Shan } 2169801846d1SGavin Shan #endif 2170801846d1SGavin Shan 2171801846d1SGavin Shan if ((pe->flags & PNV_IODA_PE_DEV) && pe->pdev) { 2172801846d1SGavin Shan pnv_pci_ioda_dev_dma_weight(pe->pdev, &weight); 2173801846d1SGavin Shan } else if ((pe->flags & PNV_IODA_PE_BUS) && pe->pbus) { 2174801846d1SGavin Shan struct pci_dev *pdev; 2175801846d1SGavin Shan 2176801846d1SGavin Shan list_for_each_entry(pdev, &pe->pbus->devices, bus_list) 2177801846d1SGavin Shan pnv_pci_ioda_dev_dma_weight(pdev, &weight); 2178801846d1SGavin Shan } else if ((pe->flags & PNV_IODA_PE_BUS_ALL) && pe->pbus) { 2179801846d1SGavin Shan pci_walk_bus(pe->pbus, pnv_pci_ioda_dev_dma_weight, &weight); 2180801846d1SGavin Shan } 2181801846d1SGavin Shan 2182801846d1SGavin Shan return weight; 2183801846d1SGavin Shan } 2184801846d1SGavin Shan 2185b30d936fSGavin Shan static void pnv_pci_ioda1_setup_dma_pe(struct pnv_phb *phb, 21862b923ed1SGavin Shan struct pnv_ioda_pe *pe) 2187184cd4a3SBenjamin Herrenschmidt { 2188184cd4a3SBenjamin Herrenschmidt 2189184cd4a3SBenjamin Herrenschmidt struct page *tce_mem = NULL; 2190184cd4a3SBenjamin Herrenschmidt struct iommu_table *tbl; 21912b923ed1SGavin Shan unsigned int weight, total_weight = 0; 21922b923ed1SGavin Shan unsigned int tce32_segsz, base, segs, avail, i; 2193184cd4a3SBenjamin Herrenschmidt int64_t rc; 2194184cd4a3SBenjamin Herrenschmidt void *addr; 2195184cd4a3SBenjamin Herrenschmidt 2196184cd4a3SBenjamin Herrenschmidt /* XXX FIXME: Handle 64-bit only DMA devices */ 2197184cd4a3SBenjamin Herrenschmidt /* XXX FIXME: Provide 64-bit DMA facilities & non-4K TCE tables etc.. */ 2198184cd4a3SBenjamin Herrenschmidt /* XXX FIXME: Allocate multi-level tables on PHB3 */ 21992b923ed1SGavin Shan weight = pnv_pci_ioda_pe_dma_weight(pe); 22002b923ed1SGavin Shan if (!weight) 22012b923ed1SGavin Shan return; 2202184cd4a3SBenjamin Herrenschmidt 22032b923ed1SGavin Shan pci_walk_bus(phb->hose->bus, pnv_pci_ioda_dev_dma_weight, 22042b923ed1SGavin Shan &total_weight); 22052b923ed1SGavin Shan segs = (weight * phb->ioda.dma32_count) / total_weight; 22062b923ed1SGavin Shan if (!segs) 22072b923ed1SGavin Shan segs = 1; 22082b923ed1SGavin Shan 22092b923ed1SGavin Shan /* 22102b923ed1SGavin Shan * Allocate contiguous DMA32 segments. We begin with the expected 22112b923ed1SGavin Shan * number of segments. With one more attempt, the number of DMA32 22122b923ed1SGavin Shan * segments to be allocated is decreased by one until one segment 22132b923ed1SGavin Shan * is allocated successfully. 22142b923ed1SGavin Shan */ 22152b923ed1SGavin Shan do { 22162b923ed1SGavin Shan for (base = 0; base <= phb->ioda.dma32_count - segs; base++) { 22172b923ed1SGavin Shan for (avail = 0, i = base; i < base + segs; i++) { 22182b923ed1SGavin Shan if (phb->ioda.dma32_segmap[i] == 22192b923ed1SGavin Shan IODA_INVALID_PE) 22202b923ed1SGavin Shan avail++; 22212b923ed1SGavin Shan } 22222b923ed1SGavin Shan 22232b923ed1SGavin Shan if (avail == segs) 22242b923ed1SGavin Shan goto found; 22252b923ed1SGavin Shan } 22262b923ed1SGavin Shan } while (--segs); 22272b923ed1SGavin Shan 22282b923ed1SGavin Shan if (!segs) { 22292b923ed1SGavin Shan pe_warn(pe, "No available DMA32 segments\n"); 22302b923ed1SGavin Shan return; 22312b923ed1SGavin Shan } 22322b923ed1SGavin Shan 22332b923ed1SGavin Shan found: 22340eaf4defSAlexey Kardashevskiy tbl = pnv_pci_table_alloc(phb->hose->node); 223582eae1afSAlexey Kardashevskiy if (WARN_ON(!tbl)) 223682eae1afSAlexey Kardashevskiy return; 223782eae1afSAlexey Kardashevskiy 2238b348aa65SAlexey Kardashevskiy iommu_register_group(&pe->table_group, phb->hose->global_number, 2239b348aa65SAlexey Kardashevskiy pe->pe_number); 22400eaf4defSAlexey Kardashevskiy pnv_pci_link_table_and_group(phb->hose->node, 0, tbl, &pe->table_group); 2241c5773822SAlexey Kardashevskiy 2242184cd4a3SBenjamin Herrenschmidt /* Grab a 32-bit TCE table */ 22432b923ed1SGavin Shan pe_info(pe, "DMA weight %d (%d), assigned (%d) %d DMA32 segments\n", 22442b923ed1SGavin Shan weight, total_weight, base, segs); 2245184cd4a3SBenjamin Herrenschmidt pe_info(pe, " Setting up 32-bit TCE table at %08x..%08x\n", 2246acce971cSGavin Shan base * PNV_IODA1_DMA32_SEGSIZE, 2247acce971cSGavin Shan (base + segs) * PNV_IODA1_DMA32_SEGSIZE - 1); 2248184cd4a3SBenjamin Herrenschmidt 2249184cd4a3SBenjamin Herrenschmidt /* XXX Currently, we allocate one big contiguous table for the 2250184cd4a3SBenjamin Herrenschmidt * TCEs. We only really need one chunk per 256M of TCE space 2251184cd4a3SBenjamin Herrenschmidt * (ie per segment) but that's an optimization for later, it 2252184cd4a3SBenjamin Herrenschmidt * requires some added smarts with our get/put_tce implementation 2253acce971cSGavin Shan * 2254acce971cSGavin Shan * Each TCE page is 4KB in size and each TCE entry occupies 8 2255acce971cSGavin Shan * bytes 2256184cd4a3SBenjamin Herrenschmidt */ 2257acce971cSGavin Shan tce32_segsz = PNV_IODA1_DMA32_SEGSIZE >> (IOMMU_PAGE_SHIFT_4K - 3); 2258184cd4a3SBenjamin Herrenschmidt tce_mem = alloc_pages_node(phb->hose->node, GFP_KERNEL, 2259acce971cSGavin Shan get_order(tce32_segsz * segs)); 2260184cd4a3SBenjamin Herrenschmidt if (!tce_mem) { 2261184cd4a3SBenjamin Herrenschmidt pe_err(pe, " Failed to allocate a 32-bit TCE memory\n"); 2262184cd4a3SBenjamin Herrenschmidt goto fail; 2263184cd4a3SBenjamin Herrenschmidt } 2264184cd4a3SBenjamin Herrenschmidt addr = page_address(tce_mem); 2265acce971cSGavin Shan memset(addr, 0, tce32_segsz * segs); 2266184cd4a3SBenjamin Herrenschmidt 2267184cd4a3SBenjamin Herrenschmidt /* Configure HW */ 2268184cd4a3SBenjamin Herrenschmidt for (i = 0; i < segs; i++) { 2269184cd4a3SBenjamin Herrenschmidt rc = opal_pci_map_pe_dma_window(phb->opal_id, 2270184cd4a3SBenjamin Herrenschmidt pe->pe_number, 2271184cd4a3SBenjamin Herrenschmidt base + i, 1, 2272acce971cSGavin Shan __pa(addr) + tce32_segsz * i, 2273acce971cSGavin Shan tce32_segsz, IOMMU_PAGE_SIZE_4K); 2274184cd4a3SBenjamin Herrenschmidt if (rc) { 22751e496391SJoe Perches pe_err(pe, " Failed to configure 32-bit TCE table, err %lld\n", 22761e496391SJoe Perches rc); 2277184cd4a3SBenjamin Herrenschmidt goto fail; 2278184cd4a3SBenjamin Herrenschmidt } 2279184cd4a3SBenjamin Herrenschmidt } 2280184cd4a3SBenjamin Herrenschmidt 22812b923ed1SGavin Shan /* Setup DMA32 segment mapping */ 22822b923ed1SGavin Shan for (i = base; i < base + segs; i++) 22832b923ed1SGavin Shan phb->ioda.dma32_segmap[i] = pe->pe_number; 22842b923ed1SGavin Shan 2285184cd4a3SBenjamin Herrenschmidt /* Setup linux iommu table */ 2286acce971cSGavin Shan pnv_pci_setup_iommu_table(tbl, addr, tce32_segsz * segs, 2287acce971cSGavin Shan base * PNV_IODA1_DMA32_SEGSIZE, 2288acce971cSGavin Shan IOMMU_PAGE_SHIFT_4K); 2289184cd4a3SBenjamin Herrenschmidt 2290da004c36SAlexey Kardashevskiy tbl->it_ops = &pnv_ioda1_iommu_ops; 22914793d65dSAlexey Kardashevskiy pe->table_group.tce32_start = tbl->it_offset << tbl->it_page_shift; 22924793d65dSAlexey Kardashevskiy pe->table_group.tce32_size = tbl->it_size << tbl->it_page_shift; 2293201ed7f3SAlexey Kardashevskiy iommu_init_table(tbl, phb->hose->node, 0, 0); 2294184cd4a3SBenjamin Herrenschmidt 2295f21b0a45SAlexey Kardashevskiy if (pe->flags & (PNV_IODA_PE_BUS | PNV_IODA_PE_BUS_ALL)) 22965eada8a3SAlexey Kardashevskiy pnv_ioda_setup_bus_dma(pe, pe->pbus); 229774251fe2SBenjamin Herrenschmidt 2298184cd4a3SBenjamin Herrenschmidt return; 2299184cd4a3SBenjamin Herrenschmidt fail: 2300184cd4a3SBenjamin Herrenschmidt /* XXX Failure: Try to fallback to 64-bit only ? */ 2301184cd4a3SBenjamin Herrenschmidt if (tce_mem) 2302acce971cSGavin Shan __free_pages(tce_mem, get_order(tce32_segsz * segs)); 23030eaf4defSAlexey Kardashevskiy if (tbl) { 23040eaf4defSAlexey Kardashevskiy pnv_pci_unlink_table_and_group(tbl, &pe->table_group); 2305e5afdf9dSAlexey Kardashevskiy iommu_tce_table_put(tbl); 23060eaf4defSAlexey Kardashevskiy } 2307184cd4a3SBenjamin Herrenschmidt } 2308184cd4a3SBenjamin Herrenschmidt 230943cb60abSAlexey Kardashevskiy static long pnv_pci_ioda2_set_window(struct iommu_table_group *table_group, 231043cb60abSAlexey Kardashevskiy int num, struct iommu_table *tbl) 231143cb60abSAlexey Kardashevskiy { 231243cb60abSAlexey Kardashevskiy struct pnv_ioda_pe *pe = container_of(table_group, struct pnv_ioda_pe, 231343cb60abSAlexey Kardashevskiy table_group); 231443cb60abSAlexey Kardashevskiy struct pnv_phb *phb = pe->phb; 231543cb60abSAlexey Kardashevskiy int64_t rc; 2316bbb845c4SAlexey Kardashevskiy const unsigned long size = tbl->it_indirect_levels ? 2317bbb845c4SAlexey Kardashevskiy tbl->it_level_size : tbl->it_size; 231843cb60abSAlexey Kardashevskiy const __u64 start_addr = tbl->it_offset << tbl->it_page_shift; 231943cb60abSAlexey Kardashevskiy const __u64 win_size = tbl->it_size << tbl->it_page_shift; 232043cb60abSAlexey Kardashevskiy 23211e496391SJoe Perches pe_info(pe, "Setting up window#%d %llx..%llx pg=%lx\n", 23221e496391SJoe Perches num, start_addr, start_addr + win_size - 1, 232343cb60abSAlexey Kardashevskiy IOMMU_PAGE_SIZE(tbl)); 232443cb60abSAlexey Kardashevskiy 232543cb60abSAlexey Kardashevskiy /* 232643cb60abSAlexey Kardashevskiy * Map TCE table through TVT. The TVE index is the PE number 232743cb60abSAlexey Kardashevskiy * shifted by 1 bit for 32-bits DMA space. 232843cb60abSAlexey Kardashevskiy */ 232943cb60abSAlexey Kardashevskiy rc = opal_pci_map_pe_dma_window(phb->opal_id, 233043cb60abSAlexey Kardashevskiy pe->pe_number, 23314793d65dSAlexey Kardashevskiy (pe->pe_number << 1) + num, 2332bbb845c4SAlexey Kardashevskiy tbl->it_indirect_levels + 1, 233343cb60abSAlexey Kardashevskiy __pa(tbl->it_base), 2334bbb845c4SAlexey Kardashevskiy size << 3, 233543cb60abSAlexey Kardashevskiy IOMMU_PAGE_SIZE(tbl)); 233643cb60abSAlexey Kardashevskiy if (rc) { 23371e496391SJoe Perches pe_err(pe, "Failed to configure TCE table, err %lld\n", rc); 233843cb60abSAlexey Kardashevskiy return rc; 233943cb60abSAlexey Kardashevskiy } 234043cb60abSAlexey Kardashevskiy 234143cb60abSAlexey Kardashevskiy pnv_pci_link_table_and_group(phb->hose->node, num, 234243cb60abSAlexey Kardashevskiy tbl, &pe->table_group); 2343ed7d9a1dSMichael Ellerman pnv_pci_ioda2_tce_invalidate_pe(pe); 234443cb60abSAlexey Kardashevskiy 234543cb60abSAlexey Kardashevskiy return 0; 234643cb60abSAlexey Kardashevskiy } 234743cb60abSAlexey Kardashevskiy 2348c498a4f9SChristoph Hellwig static void pnv_pci_ioda2_set_bypass(struct pnv_ioda_pe *pe, bool enable) 2349cd15b048SBenjamin Herrenschmidt { 2350cd15b048SBenjamin Herrenschmidt uint16_t window_id = (pe->pe_number << 1 ) + 1; 2351cd15b048SBenjamin Herrenschmidt int64_t rc; 2352cd15b048SBenjamin Herrenschmidt 2353cd15b048SBenjamin Herrenschmidt pe_info(pe, "%sabling 64-bit DMA bypass\n", enable ? "En" : "Dis"); 2354cd15b048SBenjamin Herrenschmidt if (enable) { 2355cd15b048SBenjamin Herrenschmidt phys_addr_t top = memblock_end_of_DRAM(); 2356cd15b048SBenjamin Herrenschmidt 2357cd15b048SBenjamin Herrenschmidt top = roundup_pow_of_two(top); 2358cd15b048SBenjamin Herrenschmidt rc = opal_pci_map_pe_dma_window_real(pe->phb->opal_id, 2359cd15b048SBenjamin Herrenschmidt pe->pe_number, 2360cd15b048SBenjamin Herrenschmidt window_id, 2361cd15b048SBenjamin Herrenschmidt pe->tce_bypass_base, 2362cd15b048SBenjamin Herrenschmidt top); 2363cd15b048SBenjamin Herrenschmidt } else { 2364cd15b048SBenjamin Herrenschmidt rc = opal_pci_map_pe_dma_window_real(pe->phb->opal_id, 2365cd15b048SBenjamin Herrenschmidt pe->pe_number, 2366cd15b048SBenjamin Herrenschmidt window_id, 2367cd15b048SBenjamin Herrenschmidt pe->tce_bypass_base, 2368cd15b048SBenjamin Herrenschmidt 0); 2369cd15b048SBenjamin Herrenschmidt } 2370cd15b048SBenjamin Herrenschmidt if (rc) 2371cd15b048SBenjamin Herrenschmidt pe_err(pe, "OPAL error %lld configuring bypass window\n", rc); 2372cd15b048SBenjamin Herrenschmidt else 2373cd15b048SBenjamin Herrenschmidt pe->tce_bypass_enabled = enable; 2374cd15b048SBenjamin Herrenschmidt } 2375cd15b048SBenjamin Herrenschmidt 23764793d65dSAlexey Kardashevskiy static long pnv_pci_ioda2_create_table(struct iommu_table_group *table_group, 23774793d65dSAlexey Kardashevskiy int num, __u32 page_shift, __u64 window_size, __u32 levels, 2378090bad39SAlexey Kardashevskiy bool alloc_userspace_copy, struct iommu_table **ptbl) 23794793d65dSAlexey Kardashevskiy { 23804793d65dSAlexey Kardashevskiy struct pnv_ioda_pe *pe = container_of(table_group, struct pnv_ioda_pe, 23814793d65dSAlexey Kardashevskiy table_group); 23824793d65dSAlexey Kardashevskiy int nid = pe->phb->hose->node; 23834793d65dSAlexey Kardashevskiy __u64 bus_offset = num ? pe->tce_bypass_base : table_group->tce32_start; 23844793d65dSAlexey Kardashevskiy long ret; 23854793d65dSAlexey Kardashevskiy struct iommu_table *tbl; 23864793d65dSAlexey Kardashevskiy 23874793d65dSAlexey Kardashevskiy tbl = pnv_pci_table_alloc(nid); 23884793d65dSAlexey Kardashevskiy if (!tbl) 23894793d65dSAlexey Kardashevskiy return -ENOMEM; 23904793d65dSAlexey Kardashevskiy 239111edf116SAlexey Kardashevskiy tbl->it_ops = &pnv_ioda2_iommu_ops; 239211edf116SAlexey Kardashevskiy 23934793d65dSAlexey Kardashevskiy ret = pnv_pci_ioda2_table_alloc_pages(nid, 23944793d65dSAlexey Kardashevskiy bus_offset, page_shift, window_size, 2395090bad39SAlexey Kardashevskiy levels, alloc_userspace_copy, tbl); 23964793d65dSAlexey Kardashevskiy if (ret) { 2397e5afdf9dSAlexey Kardashevskiy iommu_tce_table_put(tbl); 23984793d65dSAlexey Kardashevskiy return ret; 23994793d65dSAlexey Kardashevskiy } 24004793d65dSAlexey Kardashevskiy 24014793d65dSAlexey Kardashevskiy *ptbl = tbl; 24024793d65dSAlexey Kardashevskiy 24034793d65dSAlexey Kardashevskiy return 0; 24044793d65dSAlexey Kardashevskiy } 24054793d65dSAlexey Kardashevskiy 240646d3e1e1SAlexey Kardashevskiy static long pnv_pci_ioda2_setup_default_config(struct pnv_ioda_pe *pe) 240746d3e1e1SAlexey Kardashevskiy { 240846d3e1e1SAlexey Kardashevskiy struct iommu_table *tbl = NULL; 240946d3e1e1SAlexey Kardashevskiy long rc; 2410201ed7f3SAlexey Kardashevskiy unsigned long res_start, res_end; 241146d3e1e1SAlexey Kardashevskiy 2412bb005455SNishanth Aravamudan /* 2413fa144869SNishanth Aravamudan * crashkernel= specifies the kdump kernel's maximum memory at 2414fa144869SNishanth Aravamudan * some offset and there is no guaranteed the result is a power 2415fa144869SNishanth Aravamudan * of 2, which will cause errors later. 2416fa144869SNishanth Aravamudan */ 2417fa144869SNishanth Aravamudan const u64 max_memory = __rounddown_pow_of_two(memory_hotplug_max()); 2418fa144869SNishanth Aravamudan 2419fa144869SNishanth Aravamudan /* 2420bb005455SNishanth Aravamudan * In memory constrained environments, e.g. kdump kernel, the 2421bb005455SNishanth Aravamudan * DMA window can be larger than available memory, which will 2422bb005455SNishanth Aravamudan * cause errors later. 2423bb005455SNishanth Aravamudan */ 2424201ed7f3SAlexey Kardashevskiy const u64 maxblock = 1UL << (PAGE_SHIFT + MAX_ORDER - 1); 2425bb005455SNishanth Aravamudan 2426201ed7f3SAlexey Kardashevskiy /* 2427201ed7f3SAlexey Kardashevskiy * We create the default window as big as we can. The constraint is 2428201ed7f3SAlexey Kardashevskiy * the max order of allocation possible. The TCE table is likely to 2429201ed7f3SAlexey Kardashevskiy * end up being multilevel and with on-demand allocation in place, 2430201ed7f3SAlexey Kardashevskiy * the initial use is not going to be huge as the default window aims 2431201ed7f3SAlexey Kardashevskiy * to support crippled devices (i.e. not fully 64bit DMAble) only. 2432201ed7f3SAlexey Kardashevskiy */ 2433201ed7f3SAlexey Kardashevskiy /* iommu_table::it_map uses 1 bit per IOMMU page, hence 8 */ 2434201ed7f3SAlexey Kardashevskiy const u64 window_size = min((maxblock * 8) << PAGE_SHIFT, max_memory); 2435201ed7f3SAlexey Kardashevskiy /* Each TCE level cannot exceed maxblock so go multilevel if needed */ 2436201ed7f3SAlexey Kardashevskiy unsigned long tces_order = ilog2(window_size >> PAGE_SHIFT); 2437201ed7f3SAlexey Kardashevskiy unsigned long tcelevel_order = ilog2(maxblock >> 3); 2438201ed7f3SAlexey Kardashevskiy unsigned int levels = tces_order / tcelevel_order; 2439201ed7f3SAlexey Kardashevskiy 2440201ed7f3SAlexey Kardashevskiy if (tces_order % tcelevel_order) 2441201ed7f3SAlexey Kardashevskiy levels += 1; 2442201ed7f3SAlexey Kardashevskiy /* 2443201ed7f3SAlexey Kardashevskiy * We try to stick to default levels (which is >1 at the moment) in 2444201ed7f3SAlexey Kardashevskiy * order to save memory by relying on on-demain TCE level allocation. 2445201ed7f3SAlexey Kardashevskiy */ 2446201ed7f3SAlexey Kardashevskiy levels = max_t(unsigned int, levels, POWERNV_IOMMU_DEFAULT_LEVELS); 2447201ed7f3SAlexey Kardashevskiy 2448201ed7f3SAlexey Kardashevskiy rc = pnv_pci_ioda2_create_table(&pe->table_group, 0, PAGE_SHIFT, 2449201ed7f3SAlexey Kardashevskiy window_size, levels, false, &tbl); 245046d3e1e1SAlexey Kardashevskiy if (rc) { 245146d3e1e1SAlexey Kardashevskiy pe_err(pe, "Failed to create 32-bit TCE table, err %ld", 245246d3e1e1SAlexey Kardashevskiy rc); 245346d3e1e1SAlexey Kardashevskiy return rc; 245446d3e1e1SAlexey Kardashevskiy } 245546d3e1e1SAlexey Kardashevskiy 2456201ed7f3SAlexey Kardashevskiy /* We use top part of 32bit space for MMIO so exclude it from DMA */ 2457201ed7f3SAlexey Kardashevskiy res_start = 0; 2458201ed7f3SAlexey Kardashevskiy res_end = 0; 2459201ed7f3SAlexey Kardashevskiy if (window_size > pe->phb->ioda.m32_pci_base) { 2460201ed7f3SAlexey Kardashevskiy res_start = pe->phb->ioda.m32_pci_base >> tbl->it_page_shift; 2461201ed7f3SAlexey Kardashevskiy res_end = min(window_size, SZ_4G) >> tbl->it_page_shift; 2462201ed7f3SAlexey Kardashevskiy } 2463201ed7f3SAlexey Kardashevskiy iommu_init_table(tbl, pe->phb->hose->node, res_start, res_end); 246446d3e1e1SAlexey Kardashevskiy 246546d3e1e1SAlexey Kardashevskiy rc = pnv_pci_ioda2_set_window(&pe->table_group, 0, tbl); 246646d3e1e1SAlexey Kardashevskiy if (rc) { 246746d3e1e1SAlexey Kardashevskiy pe_err(pe, "Failed to configure 32-bit TCE table, err %ld\n", 246846d3e1e1SAlexey Kardashevskiy rc); 2469e5afdf9dSAlexey Kardashevskiy iommu_tce_table_put(tbl); 247046d3e1e1SAlexey Kardashevskiy return rc; 247146d3e1e1SAlexey Kardashevskiy } 247246d3e1e1SAlexey Kardashevskiy 247346d3e1e1SAlexey Kardashevskiy if (!pnv_iommu_bypass_disabled) 247446d3e1e1SAlexey Kardashevskiy pnv_pci_ioda2_set_bypass(pe, true); 247546d3e1e1SAlexey Kardashevskiy 24765636427dSAlexey Kardashevskiy /* 24775636427dSAlexey Kardashevskiy * Set table base for the case of IOMMU DMA use. Usually this is done 24785636427dSAlexey Kardashevskiy * from dma_dev_setup() which is not called when a device is returned 24795636427dSAlexey Kardashevskiy * from VFIO so do it here. 24805636427dSAlexey Kardashevskiy */ 24815636427dSAlexey Kardashevskiy if (pe->pdev) 24825636427dSAlexey Kardashevskiy set_iommu_table_base(&pe->pdev->dev, tbl); 24835636427dSAlexey Kardashevskiy 248446d3e1e1SAlexey Kardashevskiy return 0; 248546d3e1e1SAlexey Kardashevskiy } 248646d3e1e1SAlexey Kardashevskiy 2487b5926430SAlexey Kardashevskiy #if defined(CONFIG_IOMMU_API) || defined(CONFIG_PCI_IOV) 2488b5926430SAlexey Kardashevskiy static long pnv_pci_ioda2_unset_window(struct iommu_table_group *table_group, 2489b5926430SAlexey Kardashevskiy int num) 2490b5926430SAlexey Kardashevskiy { 2491b5926430SAlexey Kardashevskiy struct pnv_ioda_pe *pe = container_of(table_group, struct pnv_ioda_pe, 2492b5926430SAlexey Kardashevskiy table_group); 2493b5926430SAlexey Kardashevskiy struct pnv_phb *phb = pe->phb; 2494b5926430SAlexey Kardashevskiy long ret; 2495b5926430SAlexey Kardashevskiy 2496b5926430SAlexey Kardashevskiy pe_info(pe, "Removing DMA window #%d\n", num); 2497b5926430SAlexey Kardashevskiy 2498b5926430SAlexey Kardashevskiy ret = opal_pci_map_pe_dma_window(phb->opal_id, pe->pe_number, 2499b5926430SAlexey Kardashevskiy (pe->pe_number << 1) + num, 2500b5926430SAlexey Kardashevskiy 0/* levels */, 0/* table address */, 2501b5926430SAlexey Kardashevskiy 0/* table size */, 0/* page size */); 2502b5926430SAlexey Kardashevskiy if (ret) 2503b5926430SAlexey Kardashevskiy pe_warn(pe, "Unmapping failed, ret = %ld\n", ret); 2504b5926430SAlexey Kardashevskiy else 2505ed7d9a1dSMichael Ellerman pnv_pci_ioda2_tce_invalidate_pe(pe); 2506b5926430SAlexey Kardashevskiy 2507b5926430SAlexey Kardashevskiy pnv_pci_unlink_table_and_group(table_group->tables[num], table_group); 2508b5926430SAlexey Kardashevskiy 2509b5926430SAlexey Kardashevskiy return ret; 2510b5926430SAlexey Kardashevskiy } 2511b5926430SAlexey Kardashevskiy #endif 2512b5926430SAlexey Kardashevskiy 2513f87a8864SAlexey Kardashevskiy #ifdef CONFIG_IOMMU_API 25140bd97167SAlexey Kardashevskiy unsigned long pnv_pci_ioda2_get_table_size(__u32 page_shift, 251500547193SAlexey Kardashevskiy __u64 window_size, __u32 levels) 251600547193SAlexey Kardashevskiy { 251700547193SAlexey Kardashevskiy unsigned long bytes = 0; 251800547193SAlexey Kardashevskiy const unsigned window_shift = ilog2(window_size); 251900547193SAlexey Kardashevskiy unsigned entries_shift = window_shift - page_shift; 252000547193SAlexey Kardashevskiy unsigned table_shift = entries_shift + 3; 252100547193SAlexey Kardashevskiy unsigned long tce_table_size = max(0x1000UL, 1UL << table_shift); 252200547193SAlexey Kardashevskiy unsigned long direct_table_size; 252300547193SAlexey Kardashevskiy 252400547193SAlexey Kardashevskiy if (!levels || (levels > POWERNV_IOMMU_MAX_LEVELS) || 252500547193SAlexey Kardashevskiy !is_power_of_2(window_size)) 252600547193SAlexey Kardashevskiy return 0; 252700547193SAlexey Kardashevskiy 252800547193SAlexey Kardashevskiy /* Calculate a direct table size from window_size and levels */ 252900547193SAlexey Kardashevskiy entries_shift = (entries_shift + levels - 1) / levels; 253000547193SAlexey Kardashevskiy table_shift = entries_shift + 3; 253100547193SAlexey Kardashevskiy table_shift = max_t(unsigned, table_shift, PAGE_SHIFT); 253200547193SAlexey Kardashevskiy direct_table_size = 1UL << table_shift; 253300547193SAlexey Kardashevskiy 253400547193SAlexey Kardashevskiy for ( ; levels; --levels) { 2535b7115316SChristophe Leroy bytes += ALIGN(tce_table_size, direct_table_size); 253600547193SAlexey Kardashevskiy 253700547193SAlexey Kardashevskiy tce_table_size /= direct_table_size; 253800547193SAlexey Kardashevskiy tce_table_size <<= 3; 2539e49a6a21SAlexey Kardashevskiy tce_table_size = max_t(unsigned long, 2540e49a6a21SAlexey Kardashevskiy tce_table_size, direct_table_size); 254100547193SAlexey Kardashevskiy } 254200547193SAlexey Kardashevskiy 2543090bad39SAlexey Kardashevskiy return bytes + bytes; /* one for HW table, one for userspace copy */ 2544090bad39SAlexey Kardashevskiy } 2545090bad39SAlexey Kardashevskiy 2546090bad39SAlexey Kardashevskiy static long pnv_pci_ioda2_create_table_userspace( 2547090bad39SAlexey Kardashevskiy struct iommu_table_group *table_group, 2548090bad39SAlexey Kardashevskiy int num, __u32 page_shift, __u64 window_size, __u32 levels, 2549090bad39SAlexey Kardashevskiy struct iommu_table **ptbl) 2550090bad39SAlexey Kardashevskiy { 255111f5acceSAlexey Kardashevskiy long ret = pnv_pci_ioda2_create_table(table_group, 2552090bad39SAlexey Kardashevskiy num, page_shift, window_size, levels, true, ptbl); 255311f5acceSAlexey Kardashevskiy 255411f5acceSAlexey Kardashevskiy if (!ret) 255511f5acceSAlexey Kardashevskiy (*ptbl)->it_allocated_size = pnv_pci_ioda2_get_table_size( 255611f5acceSAlexey Kardashevskiy page_shift, window_size, levels); 255711f5acceSAlexey Kardashevskiy return ret; 255800547193SAlexey Kardashevskiy } 255900547193SAlexey Kardashevskiy 2560f87a8864SAlexey Kardashevskiy static void pnv_ioda2_take_ownership(struct iommu_table_group *table_group) 2561cd15b048SBenjamin Herrenschmidt { 2562f87a8864SAlexey Kardashevskiy struct pnv_ioda_pe *pe = container_of(table_group, struct pnv_ioda_pe, 2563f87a8864SAlexey Kardashevskiy table_group); 256446d3e1e1SAlexey Kardashevskiy /* Store @tbl as pnv_pci_ioda2_unset_window() resets it */ 256546d3e1e1SAlexey Kardashevskiy struct iommu_table *tbl = pe->table_group.tables[0]; 2566cd15b048SBenjamin Herrenschmidt 2567f87a8864SAlexey Kardashevskiy pnv_pci_ioda2_set_bypass(pe, false); 256846d3e1e1SAlexey Kardashevskiy pnv_pci_ioda2_unset_window(&pe->table_group, 0); 2569db08e1d5SAlexey Kardashevskiy if (pe->pbus) 25705eada8a3SAlexey Kardashevskiy pnv_ioda_setup_bus_dma(pe, pe->pbus); 25715636427dSAlexey Kardashevskiy else if (pe->pdev) 25725636427dSAlexey Kardashevskiy set_iommu_table_base(&pe->pdev->dev, NULL); 2573e5afdf9dSAlexey Kardashevskiy iommu_tce_table_put(tbl); 2574cd15b048SBenjamin Herrenschmidt } 2575cd15b048SBenjamin Herrenschmidt 2576f87a8864SAlexey Kardashevskiy static void pnv_ioda2_release_ownership(struct iommu_table_group *table_group) 2577f87a8864SAlexey Kardashevskiy { 2578f87a8864SAlexey Kardashevskiy struct pnv_ioda_pe *pe = container_of(table_group, struct pnv_ioda_pe, 2579f87a8864SAlexey Kardashevskiy table_group); 2580f87a8864SAlexey Kardashevskiy 258146d3e1e1SAlexey Kardashevskiy pnv_pci_ioda2_setup_default_config(pe); 2582db08e1d5SAlexey Kardashevskiy if (pe->pbus) 25835eada8a3SAlexey Kardashevskiy pnv_ioda_setup_bus_dma(pe, pe->pbus); 2584f87a8864SAlexey Kardashevskiy } 2585f87a8864SAlexey Kardashevskiy 2586f87a8864SAlexey Kardashevskiy static struct iommu_table_group_ops pnv_pci_ioda2_ops = { 258700547193SAlexey Kardashevskiy .get_table_size = pnv_pci_ioda2_get_table_size, 2588090bad39SAlexey Kardashevskiy .create_table = pnv_pci_ioda2_create_table_userspace, 25894793d65dSAlexey Kardashevskiy .set_window = pnv_pci_ioda2_set_window, 25904793d65dSAlexey Kardashevskiy .unset_window = pnv_pci_ioda2_unset_window, 2591f87a8864SAlexey Kardashevskiy .take_ownership = pnv_ioda2_take_ownership, 2592f87a8864SAlexey Kardashevskiy .release_ownership = pnv_ioda2_release_ownership, 2593f87a8864SAlexey Kardashevskiy }; 2594b5cb9ab1SAlexey Kardashevskiy 25955eada8a3SAlexey Kardashevskiy static void pnv_ioda_setup_bus_iommu_group_add_devices(struct pnv_ioda_pe *pe, 25960bd97167SAlexey Kardashevskiy struct iommu_table_group *table_group, 25975eada8a3SAlexey Kardashevskiy struct pci_bus *bus) 25985eada8a3SAlexey Kardashevskiy { 25995eada8a3SAlexey Kardashevskiy struct pci_dev *dev; 26005eada8a3SAlexey Kardashevskiy 26015eada8a3SAlexey Kardashevskiy list_for_each_entry(dev, &bus->devices, bus_list) { 26020bd97167SAlexey Kardashevskiy iommu_add_device(table_group, &dev->dev); 26035eada8a3SAlexey Kardashevskiy 26045eada8a3SAlexey Kardashevskiy if ((pe->flags & PNV_IODA_PE_BUS_ALL) && dev->subordinate) 26055eada8a3SAlexey Kardashevskiy pnv_ioda_setup_bus_iommu_group_add_devices(pe, 26060bd97167SAlexey Kardashevskiy table_group, dev->subordinate); 26075eada8a3SAlexey Kardashevskiy } 26085eada8a3SAlexey Kardashevskiy } 26095eada8a3SAlexey Kardashevskiy 26100bd97167SAlexey Kardashevskiy static void pnv_ioda_setup_bus_iommu_group(struct pnv_ioda_pe *pe, 26110bd97167SAlexey Kardashevskiy struct iommu_table_group *table_group, struct pci_bus *bus) 26125eada8a3SAlexey Kardashevskiy { 26135eada8a3SAlexey Kardashevskiy 26145eada8a3SAlexey Kardashevskiy if (pe->flags & PNV_IODA_PE_DEV) 26150bd97167SAlexey Kardashevskiy iommu_add_device(table_group, &pe->pdev->dev); 26160bd97167SAlexey Kardashevskiy 26170bd97167SAlexey Kardashevskiy if ((pe->flags & (PNV_IODA_PE_BUS | PNV_IODA_PE_BUS_ALL)) || bus) 26180bd97167SAlexey Kardashevskiy pnv_ioda_setup_bus_iommu_group_add_devices(pe, table_group, 26190bd97167SAlexey Kardashevskiy bus); 26205eada8a3SAlexey Kardashevskiy } 26215eada8a3SAlexey Kardashevskiy 26220bd97167SAlexey Kardashevskiy static unsigned long pnv_ioda_parse_tce_sizes(struct pnv_phb *phb); 26230bd97167SAlexey Kardashevskiy 2624b5cb9ab1SAlexey Kardashevskiy static void pnv_pci_ioda_setup_iommu_api(void) 2625b5cb9ab1SAlexey Kardashevskiy { 26260bd97167SAlexey Kardashevskiy struct pci_controller *hose; 2627b5cb9ab1SAlexey Kardashevskiy struct pnv_phb *phb; 26280bd97167SAlexey Kardashevskiy struct pnv_ioda_pe *pe; 2629b5cb9ab1SAlexey Kardashevskiy 2630b5cb9ab1SAlexey Kardashevskiy /* 26315eada8a3SAlexey Kardashevskiy * There are 4 types of PEs: 26325eada8a3SAlexey Kardashevskiy * - PNV_IODA_PE_BUS: a downstream port with an adapter, 26335eada8a3SAlexey Kardashevskiy * created from pnv_pci_setup_bridge(); 26345eada8a3SAlexey Kardashevskiy * - PNV_IODA_PE_BUS_ALL: a PCI-PCIX bridge with devices behind it, 26355eada8a3SAlexey Kardashevskiy * created from pnv_pci_setup_bridge(); 26365eada8a3SAlexey Kardashevskiy * - PNV_IODA_PE_VF: a SRIOV virtual function, 26375eada8a3SAlexey Kardashevskiy * created from pnv_pcibios_sriov_enable(); 26385eada8a3SAlexey Kardashevskiy * - PNV_IODA_PE_DEV: an NPU or OCAPI device, 26395eada8a3SAlexey Kardashevskiy * created from pnv_pci_ioda_fixup(). 26405eada8a3SAlexey Kardashevskiy * 26415eada8a3SAlexey Kardashevskiy * Normally a PE is represented by an IOMMU group, however for 26425eada8a3SAlexey Kardashevskiy * devices with side channels the groups need to be more strict. 26435eada8a3SAlexey Kardashevskiy */ 26445eada8a3SAlexey Kardashevskiy list_for_each_entry(hose, &hose_list, list_node) { 26455eada8a3SAlexey Kardashevskiy phb = hose->private_data; 26465eada8a3SAlexey Kardashevskiy 26476bca5159SFrederic Barrat if (phb->type == PNV_PHB_NPU_NVLINK || 26486bca5159SFrederic Barrat phb->type == PNV_PHB_NPU_OCAPI) 26495eada8a3SAlexey Kardashevskiy continue; 26505eada8a3SAlexey Kardashevskiy 26510bd97167SAlexey Kardashevskiy list_for_each_entry(pe, &phb->ioda.pe_list, list) { 26520bd97167SAlexey Kardashevskiy struct iommu_table_group *table_group; 26530bd97167SAlexey Kardashevskiy 26540bd97167SAlexey Kardashevskiy table_group = pnv_try_setup_npu_table_group(pe); 26550bd97167SAlexey Kardashevskiy if (!table_group) { 26560bd97167SAlexey Kardashevskiy if (!pnv_pci_ioda_pe_dma_weight(pe)) 26570bd97167SAlexey Kardashevskiy continue; 26580bd97167SAlexey Kardashevskiy 26590bd97167SAlexey Kardashevskiy table_group = &pe->table_group; 26600bd97167SAlexey Kardashevskiy } 26610bd97167SAlexey Kardashevskiy pnv_ioda_setup_bus_iommu_group(pe, table_group, 26620bd97167SAlexey Kardashevskiy pe->pbus); 26630bd97167SAlexey Kardashevskiy } 26645eada8a3SAlexey Kardashevskiy } 26655eada8a3SAlexey Kardashevskiy 26665eada8a3SAlexey Kardashevskiy /* 2667b5cb9ab1SAlexey Kardashevskiy * Now we have all PHBs discovered, time to add NPU devices to 2668b5cb9ab1SAlexey Kardashevskiy * the corresponding IOMMU groups. 2669b5cb9ab1SAlexey Kardashevskiy */ 26700bd97167SAlexey Kardashevskiy list_for_each_entry(hose, &hose_list, list_node) { 26710bd97167SAlexey Kardashevskiy unsigned long pgsizes; 26720bd97167SAlexey Kardashevskiy 2673b5cb9ab1SAlexey Kardashevskiy phb = hose->private_data; 2674b5cb9ab1SAlexey Kardashevskiy 26757f2c39e9SFrederic Barrat if (phb->type != PNV_PHB_NPU_NVLINK) 2676b5cb9ab1SAlexey Kardashevskiy continue; 2677b5cb9ab1SAlexey Kardashevskiy 26780bd97167SAlexey Kardashevskiy pgsizes = pnv_ioda_parse_tce_sizes(phb); 2679b5cb9ab1SAlexey Kardashevskiy list_for_each_entry(pe, &phb->ioda.pe_list, list) { 26800bd97167SAlexey Kardashevskiy /* 26810bd97167SAlexey Kardashevskiy * IODA2 bridges get this set up from 26820bd97167SAlexey Kardashevskiy * pci_controller_ops::setup_bridge but NPU bridges 26830bd97167SAlexey Kardashevskiy * do not have this hook defined so we do it here. 26840bd97167SAlexey Kardashevskiy */ 26850bd97167SAlexey Kardashevskiy pe->table_group.pgsizes = pgsizes; 26860bd97167SAlexey Kardashevskiy pnv_npu_compound_attach(pe); 2687b5cb9ab1SAlexey Kardashevskiy } 2688b5cb9ab1SAlexey Kardashevskiy } 2689b5cb9ab1SAlexey Kardashevskiy } 2690b5cb9ab1SAlexey Kardashevskiy #else /* !CONFIG_IOMMU_API */ 2691b5cb9ab1SAlexey Kardashevskiy static void pnv_pci_ioda_setup_iommu_api(void) { }; 2692f87a8864SAlexey Kardashevskiy #endif 2693f87a8864SAlexey Kardashevskiy 26947ef73cd3SAlexey Kardashevskiy static unsigned long pnv_ioda_parse_tce_sizes(struct pnv_phb *phb) 26957ef73cd3SAlexey Kardashevskiy { 26967ef73cd3SAlexey Kardashevskiy struct pci_controller *hose = phb->hose; 26977ef73cd3SAlexey Kardashevskiy struct device_node *dn = hose->dn; 26987ef73cd3SAlexey Kardashevskiy unsigned long mask = 0; 26997ef73cd3SAlexey Kardashevskiy int i, rc, count; 27007ef73cd3SAlexey Kardashevskiy u32 val; 27017ef73cd3SAlexey Kardashevskiy 27027ef73cd3SAlexey Kardashevskiy count = of_property_count_u32_elems(dn, "ibm,supported-tce-sizes"); 27037ef73cd3SAlexey Kardashevskiy if (count <= 0) { 27047ef73cd3SAlexey Kardashevskiy mask = SZ_4K | SZ_64K; 27057ef73cd3SAlexey Kardashevskiy /* Add 16M for POWER8 by default */ 27067ef73cd3SAlexey Kardashevskiy if (cpu_has_feature(CPU_FTR_ARCH_207S) && 27077ef73cd3SAlexey Kardashevskiy !cpu_has_feature(CPU_FTR_ARCH_300)) 270800c376fdSAlexey Kardashevskiy mask |= SZ_16M | SZ_256M; 27097ef73cd3SAlexey Kardashevskiy return mask; 27107ef73cd3SAlexey Kardashevskiy } 27117ef73cd3SAlexey Kardashevskiy 27127ef73cd3SAlexey Kardashevskiy for (i = 0; i < count; i++) { 27137ef73cd3SAlexey Kardashevskiy rc = of_property_read_u32_index(dn, "ibm,supported-tce-sizes", 27147ef73cd3SAlexey Kardashevskiy i, &val); 27157ef73cd3SAlexey Kardashevskiy if (rc == 0) 27167ef73cd3SAlexey Kardashevskiy mask |= 1ULL << val; 27177ef73cd3SAlexey Kardashevskiy } 27187ef73cd3SAlexey Kardashevskiy 27197ef73cd3SAlexey Kardashevskiy return mask; 27207ef73cd3SAlexey Kardashevskiy } 27217ef73cd3SAlexey Kardashevskiy 2722373f5657SGavin Shan static void pnv_pci_ioda2_setup_dma_pe(struct pnv_phb *phb, 2723373f5657SGavin Shan struct pnv_ioda_pe *pe) 2724373f5657SGavin Shan { 2725373f5657SGavin Shan int64_t rc; 2726373f5657SGavin Shan 2727ccd1c191SGavin Shan if (!pnv_pci_ioda_pe_dma_weight(pe)) 2728ccd1c191SGavin Shan return; 2729ccd1c191SGavin Shan 2730f87a8864SAlexey Kardashevskiy /* TVE #1 is selected by PCI address bit 59 */ 2731f87a8864SAlexey Kardashevskiy pe->tce_bypass_base = 1ull << 59; 2732f87a8864SAlexey Kardashevskiy 2733373f5657SGavin Shan /* The PE will reserve all possible 32-bits space */ 2734373f5657SGavin Shan pe_info(pe, "Setting up 32-bit TCE table at 0..%08x\n", 2735aca6913fSAlexey Kardashevskiy phb->ioda.m32_pci_base); 2736373f5657SGavin Shan 2737e5aad1e6SAlexey Kardashevskiy /* Setup linux iommu table */ 27384793d65dSAlexey Kardashevskiy pe->table_group.tce32_start = 0; 27394793d65dSAlexey Kardashevskiy pe->table_group.tce32_size = phb->ioda.m32_pci_base; 27404793d65dSAlexey Kardashevskiy pe->table_group.max_dynamic_windows_supported = 27414793d65dSAlexey Kardashevskiy IOMMU_TABLE_GROUP_MAX_TABLES; 27424793d65dSAlexey Kardashevskiy pe->table_group.max_levels = POWERNV_IOMMU_MAX_LEVELS; 27437ef73cd3SAlexey Kardashevskiy pe->table_group.pgsizes = pnv_ioda_parse_tce_sizes(phb); 2744e5aad1e6SAlexey Kardashevskiy 274546d3e1e1SAlexey Kardashevskiy rc = pnv_pci_ioda2_setup_default_config(pe); 2746801846d1SGavin Shan if (rc) 274746d3e1e1SAlexey Kardashevskiy return; 274846d3e1e1SAlexey Kardashevskiy 27499b9408c5SOliver O'Halloran #ifdef CONFIG_IOMMU_API 27509b9408c5SOliver O'Halloran pe->table_group.ops = &pnv_pci_ioda2_ops; 27519b9408c5SOliver O'Halloran iommu_register_group(&pe->table_group, phb->hose->global_number, 27529b9408c5SOliver O'Halloran pe->pe_number); 27539b9408c5SOliver O'Halloran #endif 27549b9408c5SOliver O'Halloran 275520f13b95SAlexey Kardashevskiy if (pe->flags & (PNV_IODA_PE_BUS | PNV_IODA_PE_BUS_ALL)) 27565eada8a3SAlexey Kardashevskiy pnv_ioda_setup_bus_dma(pe, pe->pbus); 2757373f5657SGavin Shan } 2758373f5657SGavin Shan 27594ee11c1aSSuresh Warrier int64_t pnv_opal_pci_msi_eoi(struct irq_chip *chip, unsigned int hw_irq) 2760137436c9SGavin Shan { 2761137436c9SGavin Shan struct pnv_phb *phb = container_of(chip, struct pnv_phb, 2762137436c9SGavin Shan ioda.irq_chip); 2763137436c9SGavin Shan 27644ee11c1aSSuresh Warrier return opal_pci_msi_eoi(phb->opal_id, hw_irq); 27654ee11c1aSSuresh Warrier } 27664ee11c1aSSuresh Warrier 27674ee11c1aSSuresh Warrier static void pnv_ioda2_msi_eoi(struct irq_data *d) 27684ee11c1aSSuresh Warrier { 27694ee11c1aSSuresh Warrier int64_t rc; 27704ee11c1aSSuresh Warrier unsigned int hw_irq = (unsigned int)irqd_to_hwirq(d); 27714ee11c1aSSuresh Warrier struct irq_chip *chip = irq_data_get_irq_chip(d); 27724ee11c1aSSuresh Warrier 27734ee11c1aSSuresh Warrier rc = pnv_opal_pci_msi_eoi(chip, hw_irq); 2774137436c9SGavin Shan WARN_ON_ONCE(rc); 2775137436c9SGavin Shan 2776137436c9SGavin Shan icp_native_eoi(d); 2777137436c9SGavin Shan } 2778137436c9SGavin Shan 2779fd9a1c26SIan Munsie 2780f456834aSIan Munsie void pnv_set_msi_irq_chip(struct pnv_phb *phb, unsigned int virq) 2781fd9a1c26SIan Munsie { 2782fd9a1c26SIan Munsie struct irq_data *idata; 2783fd9a1c26SIan Munsie struct irq_chip *ichip; 2784fd9a1c26SIan Munsie 2785fb111334SBenjamin Herrenschmidt /* The MSI EOI OPAL call is only needed on PHB3 */ 2786fb111334SBenjamin Herrenschmidt if (phb->model != PNV_PHB_MODEL_PHB3) 2787fd9a1c26SIan Munsie return; 2788fd9a1c26SIan Munsie 2789fd9a1c26SIan Munsie if (!phb->ioda.irq_chip_init) { 2790fd9a1c26SIan Munsie /* 2791fd9a1c26SIan Munsie * First time we setup an MSI IRQ, we need to setup the 2792fd9a1c26SIan Munsie * corresponding IRQ chip to route correctly. 2793fd9a1c26SIan Munsie */ 2794fd9a1c26SIan Munsie idata = irq_get_irq_data(virq); 2795fd9a1c26SIan Munsie ichip = irq_data_get_irq_chip(idata); 2796fd9a1c26SIan Munsie phb->ioda.irq_chip_init = 1; 2797fd9a1c26SIan Munsie phb->ioda.irq_chip = *ichip; 2798fd9a1c26SIan Munsie phb->ioda.irq_chip.irq_eoi = pnv_ioda2_msi_eoi; 2799fd9a1c26SIan Munsie } 2800fd9a1c26SIan Munsie irq_set_chip(virq, &phb->ioda.irq_chip); 2801fd9a1c26SIan Munsie } 2802fd9a1c26SIan Munsie 28034ee11c1aSSuresh Warrier /* 28044ee11c1aSSuresh Warrier * Returns true iff chip is something that we could call 28054ee11c1aSSuresh Warrier * pnv_opal_pci_msi_eoi for. 28064ee11c1aSSuresh Warrier */ 28074ee11c1aSSuresh Warrier bool is_pnv_opal_msi(struct irq_chip *chip) 28084ee11c1aSSuresh Warrier { 28094ee11c1aSSuresh Warrier return chip->irq_eoi == pnv_ioda2_msi_eoi; 28104ee11c1aSSuresh Warrier } 28114ee11c1aSSuresh Warrier EXPORT_SYMBOL_GPL(is_pnv_opal_msi); 28124ee11c1aSSuresh Warrier 2813184cd4a3SBenjamin Herrenschmidt static int pnv_pci_ioda_msi_setup(struct pnv_phb *phb, struct pci_dev *dev, 2814137436c9SGavin Shan unsigned int hwirq, unsigned int virq, 2815137436c9SGavin Shan unsigned int is_64, struct msi_msg *msg) 2816184cd4a3SBenjamin Herrenschmidt { 2817184cd4a3SBenjamin Herrenschmidt struct pnv_ioda_pe *pe = pnv_ioda_get_pe(dev); 2818184cd4a3SBenjamin Herrenschmidt unsigned int xive_num = hwirq - phb->msi_base; 28193a1a4661SBenjamin Herrenschmidt __be32 data; 2820184cd4a3SBenjamin Herrenschmidt int rc; 2821184cd4a3SBenjamin Herrenschmidt 2822184cd4a3SBenjamin Herrenschmidt /* No PE assigned ? bail out ... no MSI for you ! */ 2823184cd4a3SBenjamin Herrenschmidt if (pe == NULL) 2824184cd4a3SBenjamin Herrenschmidt return -ENXIO; 2825184cd4a3SBenjamin Herrenschmidt 2826184cd4a3SBenjamin Herrenschmidt /* Check if we have an MVE */ 2827184cd4a3SBenjamin Herrenschmidt if (pe->mve_number < 0) 2828184cd4a3SBenjamin Herrenschmidt return -ENXIO; 2829184cd4a3SBenjamin Herrenschmidt 2830b72c1f65SBenjamin Herrenschmidt /* Force 32-bit MSI on some broken devices */ 283136074381SBenjamin Herrenschmidt if (dev->no_64bit_msi) 2832b72c1f65SBenjamin Herrenschmidt is_64 = 0; 2833b72c1f65SBenjamin Herrenschmidt 2834184cd4a3SBenjamin Herrenschmidt /* Assign XIVE to PE */ 2835184cd4a3SBenjamin Herrenschmidt rc = opal_pci_set_xive_pe(phb->opal_id, pe->pe_number, xive_num); 2836184cd4a3SBenjamin Herrenschmidt if (rc) { 2837184cd4a3SBenjamin Herrenschmidt pr_warn("%s: OPAL error %d setting XIVE %d PE\n", 2838184cd4a3SBenjamin Herrenschmidt pci_name(dev), rc, xive_num); 2839184cd4a3SBenjamin Herrenschmidt return -EIO; 2840184cd4a3SBenjamin Herrenschmidt } 2841184cd4a3SBenjamin Herrenschmidt 2842184cd4a3SBenjamin Herrenschmidt if (is_64) { 28433a1a4661SBenjamin Herrenschmidt __be64 addr64; 28443a1a4661SBenjamin Herrenschmidt 2845184cd4a3SBenjamin Herrenschmidt rc = opal_get_msi_64(phb->opal_id, pe->mve_number, xive_num, 1, 2846184cd4a3SBenjamin Herrenschmidt &addr64, &data); 2847184cd4a3SBenjamin Herrenschmidt if (rc) { 2848184cd4a3SBenjamin Herrenschmidt pr_warn("%s: OPAL error %d getting 64-bit MSI data\n", 2849184cd4a3SBenjamin Herrenschmidt pci_name(dev), rc); 2850184cd4a3SBenjamin Herrenschmidt return -EIO; 2851184cd4a3SBenjamin Herrenschmidt } 28523a1a4661SBenjamin Herrenschmidt msg->address_hi = be64_to_cpu(addr64) >> 32; 28533a1a4661SBenjamin Herrenschmidt msg->address_lo = be64_to_cpu(addr64) & 0xfffffffful; 2854184cd4a3SBenjamin Herrenschmidt } else { 28553a1a4661SBenjamin Herrenschmidt __be32 addr32; 28563a1a4661SBenjamin Herrenschmidt 2857184cd4a3SBenjamin Herrenschmidt rc = opal_get_msi_32(phb->opal_id, pe->mve_number, xive_num, 1, 2858184cd4a3SBenjamin Herrenschmidt &addr32, &data); 2859184cd4a3SBenjamin Herrenschmidt if (rc) { 2860184cd4a3SBenjamin Herrenschmidt pr_warn("%s: OPAL error %d getting 32-bit MSI data\n", 2861184cd4a3SBenjamin Herrenschmidt pci_name(dev), rc); 2862184cd4a3SBenjamin Herrenschmidt return -EIO; 2863184cd4a3SBenjamin Herrenschmidt } 2864184cd4a3SBenjamin Herrenschmidt msg->address_hi = 0; 28653a1a4661SBenjamin Herrenschmidt msg->address_lo = be32_to_cpu(addr32); 2866184cd4a3SBenjamin Herrenschmidt } 28673a1a4661SBenjamin Herrenschmidt msg->data = be32_to_cpu(data); 2868184cd4a3SBenjamin Herrenschmidt 2869f456834aSIan Munsie pnv_set_msi_irq_chip(phb, virq); 2870137436c9SGavin Shan 2871184cd4a3SBenjamin Herrenschmidt pr_devel("%s: %s-bit MSI on hwirq %x (xive #%d)," 28721f52f176SRussell Currey " address=%x_%08x data=%x PE# %x\n", 2873184cd4a3SBenjamin Herrenschmidt pci_name(dev), is_64 ? "64" : "32", hwirq, xive_num, 2874184cd4a3SBenjamin Herrenschmidt msg->address_hi, msg->address_lo, data, pe->pe_number); 2875184cd4a3SBenjamin Herrenschmidt 2876184cd4a3SBenjamin Herrenschmidt return 0; 2877184cd4a3SBenjamin Herrenschmidt } 2878184cd4a3SBenjamin Herrenschmidt 2879184cd4a3SBenjamin Herrenschmidt static void pnv_pci_init_ioda_msis(struct pnv_phb *phb) 2880184cd4a3SBenjamin Herrenschmidt { 2881fb1b55d6SGavin Shan unsigned int count; 2882184cd4a3SBenjamin Herrenschmidt const __be32 *prop = of_get_property(phb->hose->dn, 2883184cd4a3SBenjamin Herrenschmidt "ibm,opal-msi-ranges", NULL); 2884184cd4a3SBenjamin Herrenschmidt if (!prop) { 2885184cd4a3SBenjamin Herrenschmidt /* BML Fallback */ 2886184cd4a3SBenjamin Herrenschmidt prop = of_get_property(phb->hose->dn, "msi-ranges", NULL); 2887184cd4a3SBenjamin Herrenschmidt } 2888184cd4a3SBenjamin Herrenschmidt if (!prop) 2889184cd4a3SBenjamin Herrenschmidt return; 2890184cd4a3SBenjamin Herrenschmidt 2891184cd4a3SBenjamin Herrenschmidt phb->msi_base = be32_to_cpup(prop); 2892fb1b55d6SGavin Shan count = be32_to_cpup(prop + 1); 2893fb1b55d6SGavin Shan if (msi_bitmap_alloc(&phb->msi_bmp, count, phb->hose->dn)) { 2894184cd4a3SBenjamin Herrenschmidt pr_err("PCI %d: Failed to allocate MSI bitmap !\n", 2895184cd4a3SBenjamin Herrenschmidt phb->hose->global_number); 2896184cd4a3SBenjamin Herrenschmidt return; 2897184cd4a3SBenjamin Herrenschmidt } 2898fb1b55d6SGavin Shan 2899184cd4a3SBenjamin Herrenschmidt phb->msi_setup = pnv_pci_ioda_msi_setup; 2900184cd4a3SBenjamin Herrenschmidt phb->msi32_support = 1; 2901184cd4a3SBenjamin Herrenschmidt pr_info(" Allocated bitmap for %d MSIs (base IRQ 0x%x)\n", 2902fb1b55d6SGavin Shan count, phb->msi_base); 2903184cd4a3SBenjamin Herrenschmidt } 2904184cd4a3SBenjamin Herrenschmidt 29056e628c7dSWei Yang #ifdef CONFIG_PCI_IOV 29066e628c7dSWei Yang static void pnv_pci_ioda_fixup_iov_resources(struct pci_dev *pdev) 29076e628c7dSWei Yang { 2908f2dd0afeSWei Yang struct pci_controller *hose = pci_bus_to_host(pdev->bus); 2909f2dd0afeSWei Yang struct pnv_phb *phb = hose->private_data; 2910f2dd0afeSWei Yang const resource_size_t gate = phb->ioda.m64_segsize >> 2; 29116e628c7dSWei Yang struct resource *res; 29126e628c7dSWei Yang int i; 2913dfcc8d45SWei Yang resource_size_t size, total_vf_bar_sz; 29146e628c7dSWei Yang struct pci_dn *pdn; 29155b88ec22SWei Yang int mul, total_vfs; 29166e628c7dSWei Yang 29176e628c7dSWei Yang pdn = pci_get_pdn(pdev); 29186e628c7dSWei Yang pdn->vfs_expanded = 0; 2919ee8222feSWei Yang pdn->m64_single_mode = false; 29206e628c7dSWei Yang 29215b88ec22SWei Yang total_vfs = pci_sriov_get_totalvfs(pdev); 292292b8f137SGavin Shan mul = phb->ioda.total_pe_num; 2923dfcc8d45SWei Yang total_vf_bar_sz = 0; 29245b88ec22SWei Yang 29255b88ec22SWei Yang for (i = 0; i < PCI_SRIOV_NUM_BARS; i++) { 29265b88ec22SWei Yang res = &pdev->resource[i + PCI_IOV_RESOURCES]; 29275b88ec22SWei Yang if (!res->flags || res->parent) 29285b88ec22SWei Yang continue; 2929b79331a5SRussell Currey if (!pnv_pci_is_m64_flags(res->flags)) { 2930b0331854SWei Yang dev_warn(&pdev->dev, "Don't support SR-IOV with" 2931b0331854SWei Yang " non M64 VF BAR%d: %pR. \n", 29325b88ec22SWei Yang i, res); 2933b0331854SWei Yang goto truncate_iov; 29345b88ec22SWei Yang } 29355b88ec22SWei Yang 2936dfcc8d45SWei Yang total_vf_bar_sz += pci_iov_resource_size(pdev, 2937dfcc8d45SWei Yang i + PCI_IOV_RESOURCES); 29385b88ec22SWei Yang 2939f2dd0afeSWei Yang /* 2940f2dd0afeSWei Yang * If bigger than quarter of M64 segment size, just round up 2941f2dd0afeSWei Yang * power of two. 2942f2dd0afeSWei Yang * 2943f2dd0afeSWei Yang * Generally, one M64 BAR maps one IOV BAR. To avoid conflict 2944f2dd0afeSWei Yang * with other devices, IOV BAR size is expanded to be 2945f2dd0afeSWei Yang * (total_pe * VF_BAR_size). When VF_BAR_size is half of M64 2946f2dd0afeSWei Yang * segment size , the expanded size would equal to half of the 2947f2dd0afeSWei Yang * whole M64 space size, which will exhaust the M64 Space and 2948f2dd0afeSWei Yang * limit the system flexibility. This is a design decision to 2949f2dd0afeSWei Yang * set the boundary to quarter of the M64 segment size. 2950f2dd0afeSWei Yang */ 2951dfcc8d45SWei Yang if (total_vf_bar_sz > gate) { 29525b88ec22SWei Yang mul = roundup_pow_of_two(total_vfs); 2953dfcc8d45SWei Yang dev_info(&pdev->dev, 2954dfcc8d45SWei Yang "VF BAR Total IOV size %llx > %llx, roundup to %d VFs\n", 2955dfcc8d45SWei Yang total_vf_bar_sz, gate, mul); 2956ee8222feSWei Yang pdn->m64_single_mode = true; 29575b88ec22SWei Yang break; 29585b88ec22SWei Yang } 29595b88ec22SWei Yang } 29605b88ec22SWei Yang 29616e628c7dSWei Yang for (i = 0; i < PCI_SRIOV_NUM_BARS; i++) { 29626e628c7dSWei Yang res = &pdev->resource[i + PCI_IOV_RESOURCES]; 29636e628c7dSWei Yang if (!res->flags || res->parent) 29646e628c7dSWei Yang continue; 29656e628c7dSWei Yang 29666e628c7dSWei Yang size = pci_iov_resource_size(pdev, i + PCI_IOV_RESOURCES); 2967ee8222feSWei Yang /* 2968ee8222feSWei Yang * On PHB3, the minimum size alignment of M64 BAR in single 2969ee8222feSWei Yang * mode is 32MB. 2970ee8222feSWei Yang */ 2971ee8222feSWei Yang if (pdn->m64_single_mode && (size < SZ_32M)) 2972ee8222feSWei Yang goto truncate_iov; 2973ee8222feSWei Yang dev_dbg(&pdev->dev, " Fixing VF BAR%d: %pR to\n", i, res); 29745b88ec22SWei Yang res->end = res->start + size * mul - 1; 29756e628c7dSWei Yang dev_dbg(&pdev->dev, " %pR\n", res); 29766e628c7dSWei Yang dev_info(&pdev->dev, "VF BAR%d: %pR (expanded to %d VFs for PE alignment)", 29775b88ec22SWei Yang i, res, mul); 29786e628c7dSWei Yang } 29795b88ec22SWei Yang pdn->vfs_expanded = mul; 2980b0331854SWei Yang 2981b0331854SWei Yang return; 2982b0331854SWei Yang 2983b0331854SWei Yang truncate_iov: 2984b0331854SWei Yang /* To save MMIO space, IOV BAR is truncated. */ 2985b0331854SWei Yang for (i = 0; i < PCI_SRIOV_NUM_BARS; i++) { 2986b0331854SWei Yang res = &pdev->resource[i + PCI_IOV_RESOURCES]; 2987b0331854SWei Yang res->flags = 0; 2988b0331854SWei Yang res->end = res->start - 1; 2989b0331854SWei Yang } 29906e628c7dSWei Yang } 2991965c94f3SOliver O'Halloran 2992965c94f3SOliver O'Halloran static void pnv_pci_ioda_fixup_iov(struct pci_dev *pdev) 2993965c94f3SOliver O'Halloran { 2994965c94f3SOliver O'Halloran if (WARN_ON(pci_dev_is_added(pdev))) 2995965c94f3SOliver O'Halloran return; 2996965c94f3SOliver O'Halloran 2997965c94f3SOliver O'Halloran if (pdev->is_virtfn) { 2998965c94f3SOliver O'Halloran struct pnv_ioda_pe *pe = pnv_ioda_get_pe(pdev); 2999965c94f3SOliver O'Halloran 3000965c94f3SOliver O'Halloran /* 3001965c94f3SOliver O'Halloran * VF PEs are single-device PEs so their pdev pointer needs to 3002965c94f3SOliver O'Halloran * be set. The pdev doesn't exist when the PE is allocated (in 3003965c94f3SOliver O'Halloran * (pcibios_sriov_enable()) so we fix it up here. 3004965c94f3SOliver O'Halloran */ 3005965c94f3SOliver O'Halloran pe->pdev = pdev; 3006965c94f3SOliver O'Halloran WARN_ON(!(pe->flags & PNV_IODA_PE_VF)); 3007965c94f3SOliver O'Halloran } else if (pdev->is_physfn) { 3008965c94f3SOliver O'Halloran /* 3009965c94f3SOliver O'Halloran * For PFs adjust their allocated IOV resources to match what 3010965c94f3SOliver O'Halloran * the PHB can support using it's M64 BAR table. 3011965c94f3SOliver O'Halloran */ 3012965c94f3SOliver O'Halloran pnv_pci_ioda_fixup_iov_resources(pdev); 3013965c94f3SOliver O'Halloran } 3014965c94f3SOliver O'Halloran } 30156e628c7dSWei Yang #endif /* CONFIG_PCI_IOV */ 30166e628c7dSWei Yang 301723e79425SGavin Shan static void pnv_ioda_setup_pe_res(struct pnv_ioda_pe *pe, 301823e79425SGavin Shan struct resource *res) 301911685becSGavin Shan { 302023e79425SGavin Shan struct pnv_phb *phb = pe->phb; 302111685becSGavin Shan struct pci_bus_region region; 302223e79425SGavin Shan int index; 302323e79425SGavin Shan int64_t rc; 302411685becSGavin Shan 302523e79425SGavin Shan if (!res || !res->flags || res->start > res->end) 302623e79425SGavin Shan return; 302711685becSGavin Shan 302811685becSGavin Shan if (res->flags & IORESOURCE_IO) { 302911685becSGavin Shan region.start = res->start - phb->ioda.io_pci_base; 303011685becSGavin Shan region.end = res->end - phb->ioda.io_pci_base; 303111685becSGavin Shan index = region.start / phb->ioda.io_segsize; 303211685becSGavin Shan 303392b8f137SGavin Shan while (index < phb->ioda.total_pe_num && 303411685becSGavin Shan region.start <= region.end) { 303511685becSGavin Shan phb->ioda.io_segmap[index] = pe->pe_number; 303611685becSGavin Shan rc = opal_pci_map_pe_mmio_window(phb->opal_id, 303711685becSGavin Shan pe->pe_number, OPAL_IO_WINDOW_TYPE, 0, index); 303811685becSGavin Shan if (rc != OPAL_SUCCESS) { 30391f52f176SRussell Currey pr_err("%s: Error %lld mapping IO segment#%d to PE#%x\n", 304011685becSGavin Shan __func__, rc, index, pe->pe_number); 304111685becSGavin Shan break; 304211685becSGavin Shan } 304311685becSGavin Shan 304411685becSGavin Shan region.start += phb->ioda.io_segsize; 304511685becSGavin Shan index++; 304611685becSGavin Shan } 3047027fa02fSGavin Shan } else if ((res->flags & IORESOURCE_MEM) && 30485958d19aSBenjamin Herrenschmidt !pnv_pci_is_m64(phb, res)) { 304911685becSGavin Shan region.start = res->start - 305023e79425SGavin Shan phb->hose->mem_offset[0] - 305111685becSGavin Shan phb->ioda.m32_pci_base; 305211685becSGavin Shan region.end = res->end - 305323e79425SGavin Shan phb->hose->mem_offset[0] - 305411685becSGavin Shan phb->ioda.m32_pci_base; 305511685becSGavin Shan index = region.start / phb->ioda.m32_segsize; 305611685becSGavin Shan 305792b8f137SGavin Shan while (index < phb->ioda.total_pe_num && 305811685becSGavin Shan region.start <= region.end) { 305911685becSGavin Shan phb->ioda.m32_segmap[index] = pe->pe_number; 306011685becSGavin Shan rc = opal_pci_map_pe_mmio_window(phb->opal_id, 306111685becSGavin Shan pe->pe_number, OPAL_M32_WINDOW_TYPE, 0, index); 306211685becSGavin Shan if (rc != OPAL_SUCCESS) { 30631f52f176SRussell Currey pr_err("%s: Error %lld mapping M32 segment#%d to PE#%x", 306411685becSGavin Shan __func__, rc, index, pe->pe_number); 306511685becSGavin Shan break; 306611685becSGavin Shan } 306711685becSGavin Shan 306811685becSGavin Shan region.start += phb->ioda.m32_segsize; 306911685becSGavin Shan index++; 307011685becSGavin Shan } 307111685becSGavin Shan } 307211685becSGavin Shan } 307323e79425SGavin Shan 307423e79425SGavin Shan /* 307523e79425SGavin Shan * This function is supposed to be called on basis of PE from top 307623e79425SGavin Shan * to bottom style. So the the I/O or MMIO segment assigned to 307703671057SMasahiro Yamada * parent PE could be overridden by its child PEs if necessary. 307823e79425SGavin Shan */ 307923e79425SGavin Shan static void pnv_ioda_setup_pe_seg(struct pnv_ioda_pe *pe) 308023e79425SGavin Shan { 308169d733e7SGavin Shan struct pci_dev *pdev; 308223e79425SGavin Shan int i; 308323e79425SGavin Shan 308423e79425SGavin Shan /* 308523e79425SGavin Shan * NOTE: We only care PCI bus based PE for now. For PCI 308623e79425SGavin Shan * device based PE, for example SRIOV sensitive VF should 308723e79425SGavin Shan * be figured out later. 308823e79425SGavin Shan */ 308923e79425SGavin Shan BUG_ON(!(pe->flags & (PNV_IODA_PE_BUS | PNV_IODA_PE_BUS_ALL))); 309023e79425SGavin Shan 309169d733e7SGavin Shan list_for_each_entry(pdev, &pe->pbus->devices, bus_list) { 309269d733e7SGavin Shan for (i = 0; i <= PCI_ROM_RESOURCE; i++) 309369d733e7SGavin Shan pnv_ioda_setup_pe_res(pe, &pdev->resource[i]); 309469d733e7SGavin Shan 309569d733e7SGavin Shan /* 309669d733e7SGavin Shan * If the PE contains all subordinate PCI buses, the 309769d733e7SGavin Shan * windows of the child bridges should be mapped to 309869d733e7SGavin Shan * the PE as well. 309969d733e7SGavin Shan */ 310069d733e7SGavin Shan if (!(pe->flags & PNV_IODA_PE_BUS_ALL) || !pci_is_bridge(pdev)) 310169d733e7SGavin Shan continue; 310269d733e7SGavin Shan for (i = 0; i < PCI_BRIDGE_RESOURCE_NUM; i++) 310369d733e7SGavin Shan pnv_ioda_setup_pe_res(pe, 310469d733e7SGavin Shan &pdev->resource[PCI_BRIDGE_RESOURCES + i]); 310569d733e7SGavin Shan } 310611685becSGavin Shan } 310711685becSGavin Shan 310898b665daSRussell Currey #ifdef CONFIG_DEBUG_FS 310998b665daSRussell Currey static int pnv_pci_diag_data_set(void *data, u64 val) 311098b665daSRussell Currey { 311122ba7289SOliver O'Halloran struct pnv_phb *phb = data; 311298b665daSRussell Currey s64 ret; 311398b665daSRussell Currey 311498b665daSRussell Currey /* Retrieve the diag data from firmware */ 31155cb1f8fdSRussell Currey ret = opal_pci_get_phb_diag_data2(phb->opal_id, phb->diag_data, 31165cb1f8fdSRussell Currey phb->diag_data_size); 311798b665daSRussell Currey if (ret != OPAL_SUCCESS) 311898b665daSRussell Currey return -EIO; 311998b665daSRussell Currey 312098b665daSRussell Currey /* Print the diag data to the kernel log */ 31215cb1f8fdSRussell Currey pnv_pci_dump_phb_diag_data(phb->hose, phb->diag_data); 312298b665daSRussell Currey return 0; 312398b665daSRussell Currey } 312498b665daSRussell Currey 3125bfa2325eSYueHaibing DEFINE_DEBUGFS_ATTRIBUTE(pnv_pci_diag_data_fops, NULL, pnv_pci_diag_data_set, 3126bfa2325eSYueHaibing "%llu\n"); 312798b665daSRussell Currey 312818697d2bSOliver O'Halloran static int pnv_pci_ioda_pe_dump(void *data, u64 val) 312918697d2bSOliver O'Halloran { 313018697d2bSOliver O'Halloran struct pnv_phb *phb = data; 313118697d2bSOliver O'Halloran int pe_num; 313218697d2bSOliver O'Halloran 313318697d2bSOliver O'Halloran for (pe_num = 0; pe_num < phb->ioda.total_pe_num; pe_num++) { 313418697d2bSOliver O'Halloran struct pnv_ioda_pe *pe = &phb->ioda.pe_array[pe_num]; 313518697d2bSOliver O'Halloran 313618697d2bSOliver O'Halloran if (!test_bit(pe_num, phb->ioda.pe_alloc)) 313718697d2bSOliver O'Halloran continue; 313818697d2bSOliver O'Halloran 313918697d2bSOliver O'Halloran pe_warn(pe, "rid: %04x dev count: %2d flags: %s%s%s%s%s%s\n", 314018697d2bSOliver O'Halloran pe->rid, pe->device_count, 314118697d2bSOliver O'Halloran (pe->flags & PNV_IODA_PE_DEV) ? "dev " : "", 314218697d2bSOliver O'Halloran (pe->flags & PNV_IODA_PE_BUS) ? "bus " : "", 314318697d2bSOliver O'Halloran (pe->flags & PNV_IODA_PE_BUS_ALL) ? "all " : "", 314418697d2bSOliver O'Halloran (pe->flags & PNV_IODA_PE_MASTER) ? "master " : "", 314518697d2bSOliver O'Halloran (pe->flags & PNV_IODA_PE_SLAVE) ? "slave " : "", 314618697d2bSOliver O'Halloran (pe->flags & PNV_IODA_PE_VF) ? "vf " : ""); 314718697d2bSOliver O'Halloran } 314818697d2bSOliver O'Halloran 314918697d2bSOliver O'Halloran return 0; 315018697d2bSOliver O'Halloran } 315118697d2bSOliver O'Halloran 315218697d2bSOliver O'Halloran DEFINE_DEBUGFS_ATTRIBUTE(pnv_pci_ioda_pe_dump_fops, NULL, 315318697d2bSOliver O'Halloran pnv_pci_ioda_pe_dump, "%llu\n"); 315418697d2bSOliver O'Halloran 315598b665daSRussell Currey #endif /* CONFIG_DEBUG_FS */ 315698b665daSRussell Currey 315737c367f2SGavin Shan static void pnv_pci_ioda_create_dbgfs(void) 315837c367f2SGavin Shan { 315937c367f2SGavin Shan #ifdef CONFIG_DEBUG_FS 316037c367f2SGavin Shan struct pci_controller *hose, *tmp; 316137c367f2SGavin Shan struct pnv_phb *phb; 316237c367f2SGavin Shan char name[16]; 316337c367f2SGavin Shan 316437c367f2SGavin Shan list_for_each_entry_safe(hose, tmp, &hose_list, list_node) { 316537c367f2SGavin Shan phb = hose->private_data; 316637c367f2SGavin Shan 3167ccd1c191SGavin Shan /* Notify initialization of PHB done */ 3168ccd1c191SGavin Shan phb->initialized = 1; 3169ccd1c191SGavin Shan 317037c367f2SGavin Shan sprintf(name, "PCI%04x", hose->global_number); 317137c367f2SGavin Shan phb->dbgfs = debugfs_create_dir(name, powerpc_debugfs_root); 317298b665daSRussell Currey 3173bfa2325eSYueHaibing debugfs_create_file_unsafe("dump_diag_regs", 0200, phb->dbgfs, 317422ba7289SOliver O'Halloran phb, &pnv_pci_diag_data_fops); 317518697d2bSOliver O'Halloran debugfs_create_file_unsafe("dump_ioda_pe_state", 0200, phb->dbgfs, 317618697d2bSOliver O'Halloran phb, &pnv_pci_ioda_pe_dump_fops); 317737c367f2SGavin Shan } 317837c367f2SGavin Shan #endif /* CONFIG_DEBUG_FS */ 317937c367f2SGavin Shan } 318037c367f2SGavin Shan 3181db217319SBenjamin Herrenschmidt static void pnv_pci_enable_bridge(struct pci_bus *bus) 3182db217319SBenjamin Herrenschmidt { 3183db217319SBenjamin Herrenschmidt struct pci_dev *dev = bus->self; 3184db217319SBenjamin Herrenschmidt struct pci_bus *child; 3185db217319SBenjamin Herrenschmidt 3186db217319SBenjamin Herrenschmidt /* Empty bus ? bail */ 3187db217319SBenjamin Herrenschmidt if (list_empty(&bus->devices)) 3188db217319SBenjamin Herrenschmidt return; 3189db217319SBenjamin Herrenschmidt 3190db217319SBenjamin Herrenschmidt /* 3191db217319SBenjamin Herrenschmidt * If there's a bridge associated with that bus enable it. This works 3192db217319SBenjamin Herrenschmidt * around races in the generic code if the enabling is done during 3193db217319SBenjamin Herrenschmidt * parallel probing. This can be removed once those races have been 3194db217319SBenjamin Herrenschmidt * fixed. 3195db217319SBenjamin Herrenschmidt */ 3196db217319SBenjamin Herrenschmidt if (dev) { 3197db217319SBenjamin Herrenschmidt int rc = pci_enable_device(dev); 3198db217319SBenjamin Herrenschmidt if (rc) 3199db217319SBenjamin Herrenschmidt pci_err(dev, "Error enabling bridge (%d)\n", rc); 3200db217319SBenjamin Herrenschmidt pci_set_master(dev); 3201db217319SBenjamin Herrenschmidt } 3202db217319SBenjamin Herrenschmidt 3203db217319SBenjamin Herrenschmidt /* Perform the same to child busses */ 3204db217319SBenjamin Herrenschmidt list_for_each_entry(child, &bus->children, node) 3205db217319SBenjamin Herrenschmidt pnv_pci_enable_bridge(child); 3206db217319SBenjamin Herrenschmidt } 3207db217319SBenjamin Herrenschmidt 3208db217319SBenjamin Herrenschmidt static void pnv_pci_enable_bridges(void) 3209db217319SBenjamin Herrenschmidt { 3210db217319SBenjamin Herrenschmidt struct pci_controller *hose; 3211db217319SBenjamin Herrenschmidt 3212db217319SBenjamin Herrenschmidt list_for_each_entry(hose, &hose_list, list_node) 3213db217319SBenjamin Herrenschmidt pnv_pci_enable_bridge(hose->bus); 3214db217319SBenjamin Herrenschmidt } 3215db217319SBenjamin Herrenschmidt 3216cad5cef6SGreg Kroah-Hartman static void pnv_pci_ioda_fixup(void) 3217fb446ad0SGavin Shan { 3218fb446ad0SGavin Shan pnv_pci_ioda_setup_PEs(); 3219ccd1c191SGavin Shan pnv_pci_ioda_setup_iommu_api(); 322037c367f2SGavin Shan pnv_pci_ioda_create_dbgfs(); 322137c367f2SGavin Shan 3222db217319SBenjamin Herrenschmidt pnv_pci_enable_bridges(); 3223db217319SBenjamin Herrenschmidt 3224e9cc17d4SGavin Shan #ifdef CONFIG_EEH 3225b9fde58dSBenjamin Herrenschmidt pnv_eeh_post_init(); 3226e9cc17d4SGavin Shan #endif 3227fb446ad0SGavin Shan } 3228fb446ad0SGavin Shan 3229271fd03aSGavin Shan /* 3230271fd03aSGavin Shan * Returns the alignment for I/O or memory windows for P2P 3231271fd03aSGavin Shan * bridges. That actually depends on how PEs are segmented. 3232271fd03aSGavin Shan * For now, we return I/O or M32 segment size for PE sensitive 3233271fd03aSGavin Shan * P2P bridges. Otherwise, the default values (4KiB for I/O, 3234271fd03aSGavin Shan * 1MiB for memory) will be returned. 3235271fd03aSGavin Shan * 3236271fd03aSGavin Shan * The current PCI bus might be put into one PE, which was 3237271fd03aSGavin Shan * create against the parent PCI bridge. For that case, we 3238271fd03aSGavin Shan * needn't enlarge the alignment so that we can save some 3239271fd03aSGavin Shan * resources. 3240271fd03aSGavin Shan */ 3241271fd03aSGavin Shan static resource_size_t pnv_pci_window_alignment(struct pci_bus *bus, 3242271fd03aSGavin Shan unsigned long type) 3243271fd03aSGavin Shan { 3244271fd03aSGavin Shan struct pci_dev *bridge; 3245271fd03aSGavin Shan struct pci_controller *hose = pci_bus_to_host(bus); 3246271fd03aSGavin Shan struct pnv_phb *phb = hose->private_data; 3247271fd03aSGavin Shan int num_pci_bridges = 0; 3248271fd03aSGavin Shan 3249271fd03aSGavin Shan bridge = bus->self; 3250271fd03aSGavin Shan while (bridge) { 3251271fd03aSGavin Shan if (pci_pcie_type(bridge) == PCI_EXP_TYPE_PCI_BRIDGE) { 3252271fd03aSGavin Shan num_pci_bridges++; 3253271fd03aSGavin Shan if (num_pci_bridges >= 2) 3254271fd03aSGavin Shan return 1; 3255271fd03aSGavin Shan } 3256271fd03aSGavin Shan 3257271fd03aSGavin Shan bridge = bridge->bus->self; 3258271fd03aSGavin Shan } 3259271fd03aSGavin Shan 32605958d19aSBenjamin Herrenschmidt /* 32615958d19aSBenjamin Herrenschmidt * We fall back to M32 if M64 isn't supported. We enforce the M64 32625958d19aSBenjamin Herrenschmidt * alignment for any 64-bit resource, PCIe doesn't care and 32635958d19aSBenjamin Herrenschmidt * bridges only do 64-bit prefetchable anyway. 32645958d19aSBenjamin Herrenschmidt */ 3265b79331a5SRussell Currey if (phb->ioda.m64_segsize && pnv_pci_is_m64_flags(type)) 3266262af557SGuo Chao return phb->ioda.m64_segsize; 3267271fd03aSGavin Shan if (type & IORESOURCE_MEM) 3268271fd03aSGavin Shan return phb->ioda.m32_segsize; 3269271fd03aSGavin Shan 3270271fd03aSGavin Shan return phb->ioda.io_segsize; 3271271fd03aSGavin Shan } 3272271fd03aSGavin Shan 327340e2a47eSGavin Shan /* 327440e2a47eSGavin Shan * We are updating root port or the upstream port of the 327540e2a47eSGavin Shan * bridge behind the root port with PHB's windows in order 327640e2a47eSGavin Shan * to accommodate the changes on required resources during 327740e2a47eSGavin Shan * PCI (slot) hotplug, which is connected to either root 327840e2a47eSGavin Shan * port or the downstream ports of PCIe switch behind the 327940e2a47eSGavin Shan * root port. 328040e2a47eSGavin Shan */ 328140e2a47eSGavin Shan static void pnv_pci_fixup_bridge_resources(struct pci_bus *bus, 328240e2a47eSGavin Shan unsigned long type) 328340e2a47eSGavin Shan { 328440e2a47eSGavin Shan struct pci_controller *hose = pci_bus_to_host(bus); 328540e2a47eSGavin Shan struct pnv_phb *phb = hose->private_data; 328640e2a47eSGavin Shan struct pci_dev *bridge = bus->self; 328740e2a47eSGavin Shan struct resource *r, *w; 328840e2a47eSGavin Shan bool msi_region = false; 328940e2a47eSGavin Shan int i; 329040e2a47eSGavin Shan 329140e2a47eSGavin Shan /* Check if we need apply fixup to the bridge's windows */ 329240e2a47eSGavin Shan if (!pci_is_root_bus(bridge->bus) && 329340e2a47eSGavin Shan !pci_is_root_bus(bridge->bus->self->bus)) 329440e2a47eSGavin Shan return; 329540e2a47eSGavin Shan 329640e2a47eSGavin Shan /* Fixup the resources */ 329740e2a47eSGavin Shan for (i = 0; i < PCI_BRIDGE_RESOURCE_NUM; i++) { 329840e2a47eSGavin Shan r = &bridge->resource[PCI_BRIDGE_RESOURCES + i]; 329940e2a47eSGavin Shan if (!r->flags || !r->parent) 330040e2a47eSGavin Shan continue; 330140e2a47eSGavin Shan 330240e2a47eSGavin Shan w = NULL; 330340e2a47eSGavin Shan if (r->flags & type & IORESOURCE_IO) 330440e2a47eSGavin Shan w = &hose->io_resource; 33055958d19aSBenjamin Herrenschmidt else if (pnv_pci_is_m64(phb, r) && 330640e2a47eSGavin Shan (type & IORESOURCE_PREFETCH) && 330740e2a47eSGavin Shan phb->ioda.m64_segsize) 330840e2a47eSGavin Shan w = &hose->mem_resources[1]; 330940e2a47eSGavin Shan else if (r->flags & type & IORESOURCE_MEM) { 331040e2a47eSGavin Shan w = &hose->mem_resources[0]; 331140e2a47eSGavin Shan msi_region = true; 331240e2a47eSGavin Shan } 331340e2a47eSGavin Shan 331440e2a47eSGavin Shan r->start = w->start; 331540e2a47eSGavin Shan r->end = w->end; 331640e2a47eSGavin Shan 331740e2a47eSGavin Shan /* The 64KB 32-bits MSI region shouldn't be included in 331840e2a47eSGavin Shan * the 32-bits bridge window. Otherwise, we can see strange 331940e2a47eSGavin Shan * issues. One of them is EEH error observed on Garrison. 332040e2a47eSGavin Shan * 332140e2a47eSGavin Shan * Exclude top 1MB region which is the minimal alignment of 332240e2a47eSGavin Shan * 32-bits bridge window. 332340e2a47eSGavin Shan */ 332440e2a47eSGavin Shan if (msi_region) { 332540e2a47eSGavin Shan r->end += 0x10000; 332640e2a47eSGavin Shan r->end -= 0x100000; 332740e2a47eSGavin Shan } 332840e2a47eSGavin Shan } 332940e2a47eSGavin Shan } 333040e2a47eSGavin Shan 3331ccd1c191SGavin Shan static void pnv_pci_setup_bridge(struct pci_bus *bus, unsigned long type) 3332ccd1c191SGavin Shan { 3333ccd1c191SGavin Shan struct pci_controller *hose = pci_bus_to_host(bus); 3334ccd1c191SGavin Shan struct pnv_phb *phb = hose->private_data; 3335ccd1c191SGavin Shan struct pci_dev *bridge = bus->self; 3336ccd1c191SGavin Shan struct pnv_ioda_pe *pe; 3337ccd1c191SGavin Shan bool all = (pci_pcie_type(bridge) == PCI_EXP_TYPE_PCI_BRIDGE); 3338ccd1c191SGavin Shan 333940e2a47eSGavin Shan /* Extend bridge's windows if necessary */ 334040e2a47eSGavin Shan pnv_pci_fixup_bridge_resources(bus, type); 334140e2a47eSGavin Shan 334263803c39SGavin Shan /* The PE for root bus should be realized before any one else */ 334363803c39SGavin Shan if (!phb->ioda.root_pe_populated) { 334463803c39SGavin Shan pe = pnv_ioda_setup_bus_PE(phb->hose->bus, false); 334563803c39SGavin Shan if (pe) { 334663803c39SGavin Shan phb->ioda.root_pe_idx = pe->pe_number; 334763803c39SGavin Shan phb->ioda.root_pe_populated = true; 334863803c39SGavin Shan } 334963803c39SGavin Shan } 335063803c39SGavin Shan 3351ccd1c191SGavin Shan /* Don't assign PE to PCI bus, which doesn't have subordinate devices */ 3352ccd1c191SGavin Shan if (list_empty(&bus->devices)) 3353ccd1c191SGavin Shan return; 3354ccd1c191SGavin Shan 3355ccd1c191SGavin Shan /* Reserve PEs according to used M64 resources */ 3356a25de7afSAlexey Kardashevskiy pnv_ioda_reserve_m64_pe(bus, NULL, all); 3357ccd1c191SGavin Shan 3358ccd1c191SGavin Shan /* 3359ccd1c191SGavin Shan * Assign PE. We might run here because of partial hotplug. 3360ccd1c191SGavin Shan * For the case, we just pick up the existing PE and should 3361ccd1c191SGavin Shan * not allocate resources again. 3362ccd1c191SGavin Shan */ 3363ccd1c191SGavin Shan pe = pnv_ioda_setup_bus_PE(bus, all); 3364ccd1c191SGavin Shan if (!pe) 3365ccd1c191SGavin Shan return; 3366ccd1c191SGavin Shan 3367ccd1c191SGavin Shan pnv_ioda_setup_pe_seg(pe); 3368ccd1c191SGavin Shan switch (phb->type) { 3369ccd1c191SGavin Shan case PNV_PHB_IODA1: 3370ccd1c191SGavin Shan pnv_pci_ioda1_setup_dma_pe(phb, pe); 3371ccd1c191SGavin Shan break; 3372ccd1c191SGavin Shan case PNV_PHB_IODA2: 3373ccd1c191SGavin Shan pnv_pci_ioda2_setup_dma_pe(phb, pe); 3374ccd1c191SGavin Shan break; 3375ccd1c191SGavin Shan default: 33761f52f176SRussell Currey pr_warn("%s: No DMA for PHB#%x (type %d)\n", 3377ccd1c191SGavin Shan __func__, phb->hose->global_number, phb->type); 3378ccd1c191SGavin Shan } 3379ccd1c191SGavin Shan } 3380ccd1c191SGavin Shan 338138274637SYongji Xie static resource_size_t pnv_pci_default_alignment(void) 338238274637SYongji Xie { 338338274637SYongji Xie return PAGE_SIZE; 338438274637SYongji Xie } 338538274637SYongji Xie 33865350ab3fSWei Yang #ifdef CONFIG_PCI_IOV 33875350ab3fSWei Yang static resource_size_t pnv_pci_iov_resource_alignment(struct pci_dev *pdev, 33885350ab3fSWei Yang int resno) 33895350ab3fSWei Yang { 3390ee8222feSWei Yang struct pci_controller *hose = pci_bus_to_host(pdev->bus); 3391ee8222feSWei Yang struct pnv_phb *phb = hose->private_data; 33925350ab3fSWei Yang struct pci_dn *pdn = pci_get_pdn(pdev); 33937fbe7a93SWei Yang resource_size_t align; 33945350ab3fSWei Yang 33957fbe7a93SWei Yang /* 33967fbe7a93SWei Yang * On PowerNV platform, IOV BAR is mapped by M64 BAR to enable the 33977fbe7a93SWei Yang * SR-IOV. While from hardware perspective, the range mapped by M64 33987fbe7a93SWei Yang * BAR should be size aligned. 33997fbe7a93SWei Yang * 3400ee8222feSWei Yang * When IOV BAR is mapped with M64 BAR in Single PE mode, the extra 3401ee8222feSWei Yang * powernv-specific hardware restriction is gone. But if just use the 3402ee8222feSWei Yang * VF BAR size as the alignment, PF BAR / VF BAR may be allocated with 3403ee8222feSWei Yang * in one segment of M64 #15, which introduces the PE conflict between 3404ee8222feSWei Yang * PF and VF. Based on this, the minimum alignment of an IOV BAR is 3405ee8222feSWei Yang * m64_segsize. 3406ee8222feSWei Yang * 34077fbe7a93SWei Yang * This function returns the total IOV BAR size if M64 BAR is in 34087fbe7a93SWei Yang * Shared PE mode or just VF BAR size if not. 3409ee8222feSWei Yang * If the M64 BAR is in Single PE mode, return the VF BAR size or 3410ee8222feSWei Yang * M64 segment size if IOV BAR size is less. 34117fbe7a93SWei Yang */ 34125350ab3fSWei Yang align = pci_iov_resource_size(pdev, resno); 34137fbe7a93SWei Yang if (!pdn->vfs_expanded) 34145350ab3fSWei Yang return align; 3415ee8222feSWei Yang if (pdn->m64_single_mode) 3416ee8222feSWei Yang return max(align, (resource_size_t)phb->ioda.m64_segsize); 34177fbe7a93SWei Yang 34187fbe7a93SWei Yang return pdn->vfs_expanded * align; 34195350ab3fSWei Yang } 34205350ab3fSWei Yang #endif /* CONFIG_PCI_IOV */ 34215350ab3fSWei Yang 3422184cd4a3SBenjamin Herrenschmidt /* Prevent enabling devices for which we couldn't properly 3423184cd4a3SBenjamin Herrenschmidt * assign a PE 3424184cd4a3SBenjamin Herrenschmidt */ 34258bf6b91aSAlastair D'Silva static bool pnv_pci_enable_device_hook(struct pci_dev *dev) 3426184cd4a3SBenjamin Herrenschmidt { 3427db1266c8SGavin Shan struct pci_controller *hose = pci_bus_to_host(dev->bus); 3428db1266c8SGavin Shan struct pnv_phb *phb = hose->private_data; 3429db1266c8SGavin Shan struct pci_dn *pdn; 3430184cd4a3SBenjamin Herrenschmidt 3431db1266c8SGavin Shan /* The function is probably called while the PEs have 3432db1266c8SGavin Shan * not be created yet. For example, resource reassignment 3433db1266c8SGavin Shan * during PCI probe period. We just skip the check if 3434db1266c8SGavin Shan * PEs isn't ready. 3435db1266c8SGavin Shan */ 3436db1266c8SGavin Shan if (!phb->initialized) 3437c88c2a18SDaniel Axtens return true; 3438db1266c8SGavin Shan 3439b72c1f65SBenjamin Herrenschmidt pdn = pci_get_pdn(dev); 3440184cd4a3SBenjamin Herrenschmidt if (!pdn || pdn->pe_number == IODA_INVALID_PE) 3441c88c2a18SDaniel Axtens return false; 3442db1266c8SGavin Shan 3443c88c2a18SDaniel Axtens return true; 3444184cd4a3SBenjamin Herrenschmidt } 3445184cd4a3SBenjamin Herrenschmidt 3446c1a2feadSFrederic Barrat static bool pnv_ocapi_enable_device_hook(struct pci_dev *dev) 3447c1a2feadSFrederic Barrat { 3448c1a2feadSFrederic Barrat struct pci_controller *hose = pci_bus_to_host(dev->bus); 3449c1a2feadSFrederic Barrat struct pnv_phb *phb = hose->private_data; 3450c1a2feadSFrederic Barrat struct pci_dn *pdn; 3451c1a2feadSFrederic Barrat struct pnv_ioda_pe *pe; 3452c1a2feadSFrederic Barrat 3453c1a2feadSFrederic Barrat if (!phb->initialized) 3454c1a2feadSFrederic Barrat return true; 3455c1a2feadSFrederic Barrat 3456c1a2feadSFrederic Barrat pdn = pci_get_pdn(dev); 3457c1a2feadSFrederic Barrat if (!pdn) 3458c1a2feadSFrederic Barrat return false; 3459c1a2feadSFrederic Barrat 3460c1a2feadSFrederic Barrat if (pdn->pe_number == IODA_INVALID_PE) { 3461c1a2feadSFrederic Barrat pe = pnv_ioda_setup_dev_PE(dev); 3462c1a2feadSFrederic Barrat if (!pe) 3463c1a2feadSFrederic Barrat return false; 3464c1a2feadSFrederic Barrat } 3465c1a2feadSFrederic Barrat return true; 3466c1a2feadSFrederic Barrat } 3467c1a2feadSFrederic Barrat 3468c5f7700bSGavin Shan static long pnv_pci_ioda1_unset_window(struct iommu_table_group *table_group, 3469c5f7700bSGavin Shan int num) 3470c5f7700bSGavin Shan { 3471c5f7700bSGavin Shan struct pnv_ioda_pe *pe = container_of(table_group, 3472c5f7700bSGavin Shan struct pnv_ioda_pe, table_group); 3473c5f7700bSGavin Shan struct pnv_phb *phb = pe->phb; 3474c5f7700bSGavin Shan unsigned int idx; 3475c5f7700bSGavin Shan long rc; 3476c5f7700bSGavin Shan 3477c5f7700bSGavin Shan pe_info(pe, "Removing DMA window #%d\n", num); 3478c5f7700bSGavin Shan for (idx = 0; idx < phb->ioda.dma32_count; idx++) { 3479c5f7700bSGavin Shan if (phb->ioda.dma32_segmap[idx] != pe->pe_number) 3480c5f7700bSGavin Shan continue; 3481c5f7700bSGavin Shan 3482c5f7700bSGavin Shan rc = opal_pci_map_pe_dma_window(phb->opal_id, pe->pe_number, 3483c5f7700bSGavin Shan idx, 0, 0ul, 0ul, 0ul); 3484c5f7700bSGavin Shan if (rc != OPAL_SUCCESS) { 3485c5f7700bSGavin Shan pe_warn(pe, "Failure %ld unmapping DMA32 segment#%d\n", 3486c5f7700bSGavin Shan rc, idx); 3487c5f7700bSGavin Shan return rc; 3488c5f7700bSGavin Shan } 3489c5f7700bSGavin Shan 3490c5f7700bSGavin Shan phb->ioda.dma32_segmap[idx] = IODA_INVALID_PE; 3491c5f7700bSGavin Shan } 3492c5f7700bSGavin Shan 3493c5f7700bSGavin Shan pnv_pci_unlink_table_and_group(table_group->tables[num], table_group); 3494c5f7700bSGavin Shan return OPAL_SUCCESS; 3495c5f7700bSGavin Shan } 3496c5f7700bSGavin Shan 3497c5f7700bSGavin Shan static void pnv_pci_ioda1_release_pe_dma(struct pnv_ioda_pe *pe) 3498c5f7700bSGavin Shan { 3499c5f7700bSGavin Shan unsigned int weight = pnv_pci_ioda_pe_dma_weight(pe); 3500c5f7700bSGavin Shan struct iommu_table *tbl = pe->table_group.tables[0]; 3501c5f7700bSGavin Shan int64_t rc; 3502c5f7700bSGavin Shan 3503c5f7700bSGavin Shan if (!weight) 3504c5f7700bSGavin Shan return; 3505c5f7700bSGavin Shan 3506c5f7700bSGavin Shan rc = pnv_pci_ioda1_unset_window(&pe->table_group, 0); 3507c5f7700bSGavin Shan if (rc != OPAL_SUCCESS) 3508c5f7700bSGavin Shan return; 3509c5f7700bSGavin Shan 3510a34ab7c3SBenjamin Herrenschmidt pnv_pci_p7ioc_tce_invalidate(tbl, tbl->it_offset, tbl->it_size, false); 3511c5f7700bSGavin Shan if (pe->table_group.group) { 3512c5f7700bSGavin Shan iommu_group_put(pe->table_group.group); 3513c5f7700bSGavin Shan WARN_ON(pe->table_group.group); 3514c5f7700bSGavin Shan } 3515c5f7700bSGavin Shan 3516c5f7700bSGavin Shan free_pages(tbl->it_base, get_order(tbl->it_size << 3)); 3517e5afdf9dSAlexey Kardashevskiy iommu_tce_table_put(tbl); 3518c5f7700bSGavin Shan } 3519c5f7700bSGavin Shan 3520c5f7700bSGavin Shan static void pnv_pci_ioda2_release_pe_dma(struct pnv_ioda_pe *pe) 3521c5f7700bSGavin Shan { 3522c5f7700bSGavin Shan struct iommu_table *tbl = pe->table_group.tables[0]; 3523c5f7700bSGavin Shan unsigned int weight = pnv_pci_ioda_pe_dma_weight(pe); 3524c5f7700bSGavin Shan #ifdef CONFIG_IOMMU_API 3525c5f7700bSGavin Shan int64_t rc; 3526c5f7700bSGavin Shan #endif 3527c5f7700bSGavin Shan 3528c5f7700bSGavin Shan if (!weight) 3529c5f7700bSGavin Shan return; 3530c5f7700bSGavin Shan 3531c5f7700bSGavin Shan #ifdef CONFIG_IOMMU_API 3532c5f7700bSGavin Shan rc = pnv_pci_ioda2_unset_window(&pe->table_group, 0); 3533c5f7700bSGavin Shan if (rc) 35341e496391SJoe Perches pe_warn(pe, "OPAL error %lld release DMA window\n", rc); 3535c5f7700bSGavin Shan #endif 3536c5f7700bSGavin Shan 3537c5f7700bSGavin Shan pnv_pci_ioda2_set_bypass(pe, false); 3538c5f7700bSGavin Shan if (pe->table_group.group) { 3539c5f7700bSGavin Shan iommu_group_put(pe->table_group.group); 3540c5f7700bSGavin Shan WARN_ON(pe->table_group.group); 3541c5f7700bSGavin Shan } 3542c5f7700bSGavin Shan 3543e5afdf9dSAlexey Kardashevskiy iommu_tce_table_put(tbl); 3544c5f7700bSGavin Shan } 3545c5f7700bSGavin Shan 3546c5f7700bSGavin Shan static void pnv_ioda_free_pe_seg(struct pnv_ioda_pe *pe, 3547c5f7700bSGavin Shan unsigned short win, 3548c5f7700bSGavin Shan unsigned int *map) 3549c5f7700bSGavin Shan { 3550c5f7700bSGavin Shan struct pnv_phb *phb = pe->phb; 3551c5f7700bSGavin Shan int idx; 3552c5f7700bSGavin Shan int64_t rc; 3553c5f7700bSGavin Shan 3554c5f7700bSGavin Shan for (idx = 0; idx < phb->ioda.total_pe_num; idx++) { 3555c5f7700bSGavin Shan if (map[idx] != pe->pe_number) 3556c5f7700bSGavin Shan continue; 3557c5f7700bSGavin Shan 3558c5f7700bSGavin Shan if (win == OPAL_M64_WINDOW_TYPE) 3559c5f7700bSGavin Shan rc = opal_pci_map_pe_mmio_window(phb->opal_id, 3560c5f7700bSGavin Shan phb->ioda.reserved_pe_idx, win, 3561c5f7700bSGavin Shan idx / PNV_IODA1_M64_SEGS, 3562c5f7700bSGavin Shan idx % PNV_IODA1_M64_SEGS); 3563c5f7700bSGavin Shan else 3564c5f7700bSGavin Shan rc = opal_pci_map_pe_mmio_window(phb->opal_id, 3565c5f7700bSGavin Shan phb->ioda.reserved_pe_idx, win, 0, idx); 3566c5f7700bSGavin Shan 3567c5f7700bSGavin Shan if (rc != OPAL_SUCCESS) 35681e496391SJoe Perches pe_warn(pe, "Error %lld unmapping (%d) segment#%d\n", 3569c5f7700bSGavin Shan rc, win, idx); 3570c5f7700bSGavin Shan 3571c5f7700bSGavin Shan map[idx] = IODA_INVALID_PE; 3572c5f7700bSGavin Shan } 3573c5f7700bSGavin Shan } 3574c5f7700bSGavin Shan 3575c5f7700bSGavin Shan static void pnv_ioda_release_pe_seg(struct pnv_ioda_pe *pe) 3576c5f7700bSGavin Shan { 3577c5f7700bSGavin Shan struct pnv_phb *phb = pe->phb; 3578c5f7700bSGavin Shan 3579c5f7700bSGavin Shan if (phb->type == PNV_PHB_IODA1) { 3580c5f7700bSGavin Shan pnv_ioda_free_pe_seg(pe, OPAL_IO_WINDOW_TYPE, 3581c5f7700bSGavin Shan phb->ioda.io_segmap); 3582c5f7700bSGavin Shan pnv_ioda_free_pe_seg(pe, OPAL_M32_WINDOW_TYPE, 3583c5f7700bSGavin Shan phb->ioda.m32_segmap); 3584c5f7700bSGavin Shan pnv_ioda_free_pe_seg(pe, OPAL_M64_WINDOW_TYPE, 3585c5f7700bSGavin Shan phb->ioda.m64_segmap); 3586c5f7700bSGavin Shan } else if (phb->type == PNV_PHB_IODA2) { 3587c5f7700bSGavin Shan pnv_ioda_free_pe_seg(pe, OPAL_M32_WINDOW_TYPE, 3588c5f7700bSGavin Shan phb->ioda.m32_segmap); 3589c5f7700bSGavin Shan } 3590c5f7700bSGavin Shan } 3591c5f7700bSGavin Shan 3592c5f7700bSGavin Shan static void pnv_ioda_release_pe(struct pnv_ioda_pe *pe) 3593c5f7700bSGavin Shan { 3594c5f7700bSGavin Shan struct pnv_phb *phb = pe->phb; 3595c5f7700bSGavin Shan struct pnv_ioda_pe *slave, *tmp; 3596c5f7700bSGavin Shan 359780f1ff83SFrederic Barrat mutex_lock(&phb->ioda.pe_list_mutex); 3598c5f7700bSGavin Shan list_del(&pe->list); 359980f1ff83SFrederic Barrat mutex_unlock(&phb->ioda.pe_list_mutex); 360080f1ff83SFrederic Barrat 3601c5f7700bSGavin Shan switch (phb->type) { 3602c5f7700bSGavin Shan case PNV_PHB_IODA1: 3603c5f7700bSGavin Shan pnv_pci_ioda1_release_pe_dma(pe); 3604c5f7700bSGavin Shan break; 3605c5f7700bSGavin Shan case PNV_PHB_IODA2: 3606c5f7700bSGavin Shan pnv_pci_ioda2_release_pe_dma(pe); 3607c5f7700bSGavin Shan break; 3608f724385fSFrederic Barrat case PNV_PHB_NPU_OCAPI: 3609f724385fSFrederic Barrat break; 3610c5f7700bSGavin Shan default: 3611c5f7700bSGavin Shan WARN_ON(1); 3612c5f7700bSGavin Shan } 3613c5f7700bSGavin Shan 3614c5f7700bSGavin Shan pnv_ioda_release_pe_seg(pe); 3615c5f7700bSGavin Shan pnv_ioda_deconfigure_pe(pe->phb, pe); 3616b314427aSGavin Shan 3617b314427aSGavin Shan /* Release slave PEs in the compound PE */ 3618b314427aSGavin Shan if (pe->flags & PNV_IODA_PE_MASTER) { 3619b314427aSGavin Shan list_for_each_entry_safe(slave, tmp, &pe->slaves, list) { 3620b314427aSGavin Shan list_del(&slave->list); 3621b314427aSGavin Shan pnv_ioda_free_pe(slave); 3622b314427aSGavin Shan } 3623b314427aSGavin Shan } 3624b314427aSGavin Shan 36256eaed166SGavin Shan /* 36266eaed166SGavin Shan * The PE for root bus can be removed because of hotplug in EEH 36276eaed166SGavin Shan * recovery for fenced PHB error. We need to mark the PE dead so 36286eaed166SGavin Shan * that it can be populated again in PCI hot add path. The PE 36296eaed166SGavin Shan * shouldn't be destroyed as it's the global reserved resource. 36306eaed166SGavin Shan */ 36316eaed166SGavin Shan if (phb->ioda.root_pe_populated && 36326eaed166SGavin Shan phb->ioda.root_pe_idx == pe->pe_number) 36336eaed166SGavin Shan phb->ioda.root_pe_populated = false; 36346eaed166SGavin Shan else 3635c5f7700bSGavin Shan pnv_ioda_free_pe(pe); 3636c5f7700bSGavin Shan } 3637c5f7700bSGavin Shan 3638c5f7700bSGavin Shan static void pnv_pci_release_device(struct pci_dev *pdev) 3639c5f7700bSGavin Shan { 3640c5f7700bSGavin Shan struct pci_controller *hose = pci_bus_to_host(pdev->bus); 3641c5f7700bSGavin Shan struct pnv_phb *phb = hose->private_data; 3642c5f7700bSGavin Shan struct pci_dn *pdn = pci_get_pdn(pdev); 3643c5f7700bSGavin Shan struct pnv_ioda_pe *pe; 3644c5f7700bSGavin Shan 3645c5f7700bSGavin Shan if (pdev->is_virtfn) 3646c5f7700bSGavin Shan return; 3647c5f7700bSGavin Shan 3648c5f7700bSGavin Shan if (!pdn || pdn->pe_number == IODA_INVALID_PE) 3649c5f7700bSGavin Shan return; 3650c5f7700bSGavin Shan 365129bf282dSGavin Shan /* 365229bf282dSGavin Shan * PCI hotplug can happen as part of EEH error recovery. The @pdn 365329bf282dSGavin Shan * isn't removed and added afterwards in this scenario. We should 365429bf282dSGavin Shan * set the PE number in @pdn to an invalid one. Otherwise, the PE's 365529bf282dSGavin Shan * device count is decreased on removing devices while failing to 365629bf282dSGavin Shan * be increased on adding devices. It leads to unbalanced PE's device 365729bf282dSGavin Shan * count and eventually make normal PCI hotplug path broken. 365829bf282dSGavin Shan */ 3659c5f7700bSGavin Shan pe = &phb->ioda.pe_array[pdn->pe_number]; 366029bf282dSGavin Shan pdn->pe_number = IODA_INVALID_PE; 366129bf282dSGavin Shan 3662c5f7700bSGavin Shan WARN_ON(--pe->device_count < 0); 3663c5f7700bSGavin Shan if (pe->device_count == 0) 3664c5f7700bSGavin Shan pnv_ioda_release_pe(pe); 3665c5f7700bSGavin Shan } 3666c5f7700bSGavin Shan 3667ab7032e7SAlexey Kardashevskiy static void pnv_npu_disable_device(struct pci_dev *pdev) 3668ab7032e7SAlexey Kardashevskiy { 3669ab7032e7SAlexey Kardashevskiy struct eeh_dev *edev = pci_dev_to_eeh_dev(pdev); 3670ab7032e7SAlexey Kardashevskiy struct eeh_pe *eehpe = edev ? edev->pe : NULL; 3671ab7032e7SAlexey Kardashevskiy 3672ab7032e7SAlexey Kardashevskiy if (eehpe && eeh_ops && eeh_ops->reset) 3673ab7032e7SAlexey Kardashevskiy eeh_ops->reset(eehpe, EEH_RESET_HOT); 3674ab7032e7SAlexey Kardashevskiy } 3675ab7032e7SAlexey Kardashevskiy 36767a8e6bbfSMichael Neuling static void pnv_pci_ioda_shutdown(struct pci_controller *hose) 367773ed148aSBenjamin Herrenschmidt { 36787a8e6bbfSMichael Neuling struct pnv_phb *phb = hose->private_data; 36797a8e6bbfSMichael Neuling 3680d1a85eeeSGavin Shan opal_pci_reset(phb->opal_id, OPAL_RESET_PCI_IODA_TABLE, 368173ed148aSBenjamin Herrenschmidt OPAL_ASSERT_RESET); 368273ed148aSBenjamin Herrenschmidt } 368373ed148aSBenjamin Herrenschmidt 3684946743d0SOliver O'Halloran static void pnv_pci_ioda_dma_bus_setup(struct pci_bus *bus) 3685946743d0SOliver O'Halloran { 3686946743d0SOliver O'Halloran struct pci_controller *hose = bus->sysdata; 3687946743d0SOliver O'Halloran struct pnv_phb *phb = hose->private_data; 3688946743d0SOliver O'Halloran struct pnv_ioda_pe *pe; 3689946743d0SOliver O'Halloran 3690946743d0SOliver O'Halloran list_for_each_entry(pe, &phb->ioda.pe_list, list) { 3691946743d0SOliver O'Halloran if (!(pe->flags & (PNV_IODA_PE_BUS | PNV_IODA_PE_BUS_ALL))) 3692946743d0SOliver O'Halloran continue; 3693946743d0SOliver O'Halloran 3694946743d0SOliver O'Halloran if (!pe->pbus) 3695946743d0SOliver O'Halloran continue; 3696946743d0SOliver O'Halloran 3697946743d0SOliver O'Halloran if (bus->number == ((pe->rid >> 8) & 0xFF)) { 3698946743d0SOliver O'Halloran pe->pbus = bus; 3699946743d0SOliver O'Halloran break; 3700946743d0SOliver O'Halloran } 3701946743d0SOliver O'Halloran } 3702946743d0SOliver O'Halloran } 3703946743d0SOliver O'Halloran 370492ae0353SDaniel Axtens static const struct pci_controller_ops pnv_pci_ioda_controller_ops = { 37050a25d9c4SOliver O'Halloran .dma_dev_setup = pnv_pci_ioda_dma_dev_setup, 3706946743d0SOliver O'Halloran .dma_bus_setup = pnv_pci_ioda_dma_bus_setup, 37072d6ad41bSChristoph Hellwig .iommu_bypass_supported = pnv_pci_ioda_iommu_bypass_supported, 370892ae0353SDaniel Axtens .setup_msi_irqs = pnv_setup_msi_irqs, 370992ae0353SDaniel Axtens .teardown_msi_irqs = pnv_teardown_msi_irqs, 371092ae0353SDaniel Axtens .enable_device_hook = pnv_pci_enable_device_hook, 3711c5f7700bSGavin Shan .release_device = pnv_pci_release_device, 371292ae0353SDaniel Axtens .window_alignment = pnv_pci_window_alignment, 3713ccd1c191SGavin Shan .setup_bridge = pnv_pci_setup_bridge, 371492ae0353SDaniel Axtens .reset_secondary_bus = pnv_pci_reset_secondary_bus, 37157a8e6bbfSMichael Neuling .shutdown = pnv_pci_ioda_shutdown, 371692ae0353SDaniel Axtens }; 371792ae0353SDaniel Axtens 37185d2aa710SAlistair Popple static const struct pci_controller_ops pnv_npu_ioda_controller_ops = { 37195d2aa710SAlistair Popple .setup_msi_irqs = pnv_setup_msi_irqs, 37205d2aa710SAlistair Popple .teardown_msi_irqs = pnv_teardown_msi_irqs, 37215d2aa710SAlistair Popple .enable_device_hook = pnv_pci_enable_device_hook, 37225d2aa710SAlistair Popple .window_alignment = pnv_pci_window_alignment, 37235d2aa710SAlistair Popple .reset_secondary_bus = pnv_pci_reset_secondary_bus, 37245d2aa710SAlistair Popple .shutdown = pnv_pci_ioda_shutdown, 3725ab7032e7SAlexey Kardashevskiy .disable_device = pnv_npu_disable_device, 37265d2aa710SAlistair Popple }; 37275d2aa710SAlistair Popple 37287f2c39e9SFrederic Barrat static const struct pci_controller_ops pnv_npu_ocapi_ioda_controller_ops = { 3729c1a2feadSFrederic Barrat .enable_device_hook = pnv_ocapi_enable_device_hook, 3730f724385fSFrederic Barrat .release_device = pnv_pci_release_device, 37317f2c39e9SFrederic Barrat .window_alignment = pnv_pci_window_alignment, 37327f2c39e9SFrederic Barrat .reset_secondary_bus = pnv_pci_reset_secondary_bus, 37337f2c39e9SFrederic Barrat .shutdown = pnv_pci_ioda_shutdown, 37347f2c39e9SFrederic Barrat }; 37357f2c39e9SFrederic Barrat 3736e51df2c1SAnton Blanchard static void __init pnv_pci_init_ioda_phb(struct device_node *np, 3737e9cc17d4SGavin Shan u64 hub_id, int ioda_type) 3738184cd4a3SBenjamin Herrenschmidt { 3739184cd4a3SBenjamin Herrenschmidt struct pci_controller *hose; 3740184cd4a3SBenjamin Herrenschmidt struct pnv_phb *phb; 37412b923ed1SGavin Shan unsigned long size, m64map_off, m32map_off, pemap_off; 37422b923ed1SGavin Shan unsigned long iomap_off = 0, dma32map_off = 0; 3743fd141d1aSBenjamin Herrenschmidt struct resource r; 3744c681b93cSAlistair Popple const __be64 *prop64; 37453a1a4661SBenjamin Herrenschmidt const __be32 *prop32; 3746f1b7cc3eSGavin Shan int len; 37473fa23ff8SGavin Shan unsigned int segno; 3748184cd4a3SBenjamin Herrenschmidt u64 phb_id; 3749184cd4a3SBenjamin Herrenschmidt void *aux; 3750184cd4a3SBenjamin Herrenschmidt long rc; 3751184cd4a3SBenjamin Herrenschmidt 375208a45b32SBenjamin Herrenschmidt if (!of_device_is_available(np)) 375308a45b32SBenjamin Herrenschmidt return; 375408a45b32SBenjamin Herrenschmidt 3755b7c670d6SRob Herring pr_info("Initializing %s PHB (%pOF)\n", pnv_phb_names[ioda_type], np); 3756184cd4a3SBenjamin Herrenschmidt 3757184cd4a3SBenjamin Herrenschmidt prop64 = of_get_property(np, "ibm,opal-phbid", NULL); 3758184cd4a3SBenjamin Herrenschmidt if (!prop64) { 3759184cd4a3SBenjamin Herrenschmidt pr_err(" Missing \"ibm,opal-phbid\" property !\n"); 3760184cd4a3SBenjamin Herrenschmidt return; 3761184cd4a3SBenjamin Herrenschmidt } 3762184cd4a3SBenjamin Herrenschmidt phb_id = be64_to_cpup(prop64); 3763184cd4a3SBenjamin Herrenschmidt pr_debug(" PHB-ID : 0x%016llx\n", phb_id); 3764184cd4a3SBenjamin Herrenschmidt 37657e1c4e27SMike Rapoport phb = memblock_alloc(sizeof(*phb), SMP_CACHE_BYTES); 37668a7f97b9SMike Rapoport if (!phb) 37678a7f97b9SMike Rapoport panic("%s: Failed to allocate %zu bytes\n", __func__, 37688a7f97b9SMike Rapoport sizeof(*phb)); 376958d714ecSGavin Shan 377058d714ecSGavin Shan /* Allocate PCI controller */ 3771184cd4a3SBenjamin Herrenschmidt phb->hose = hose = pcibios_alloc_controller(np); 377258d714ecSGavin Shan if (!phb->hose) { 3773b7c670d6SRob Herring pr_err(" Can't allocate PCI controller for %pOF\n", 3774b7c670d6SRob Herring np); 3775e39f223fSMichael Ellerman memblock_free(__pa(phb), sizeof(struct pnv_phb)); 3776184cd4a3SBenjamin Herrenschmidt return; 3777184cd4a3SBenjamin Herrenschmidt } 3778184cd4a3SBenjamin Herrenschmidt 3779184cd4a3SBenjamin Herrenschmidt spin_lock_init(&phb->lock); 3780f1b7cc3eSGavin Shan prop32 = of_get_property(np, "bus-range", &len); 3781f1b7cc3eSGavin Shan if (prop32 && len == 8) { 37823a1a4661SBenjamin Herrenschmidt hose->first_busno = be32_to_cpu(prop32[0]); 37833a1a4661SBenjamin Herrenschmidt hose->last_busno = be32_to_cpu(prop32[1]); 3784f1b7cc3eSGavin Shan } else { 3785b7c670d6SRob Herring pr_warn(" Broken <bus-range> on %pOF\n", np); 3786184cd4a3SBenjamin Herrenschmidt hose->first_busno = 0; 3787184cd4a3SBenjamin Herrenschmidt hose->last_busno = 0xff; 3788f1b7cc3eSGavin Shan } 3789184cd4a3SBenjamin Herrenschmidt hose->private_data = phb; 3790e9cc17d4SGavin Shan phb->hub_id = hub_id; 3791184cd4a3SBenjamin Herrenschmidt phb->opal_id = phb_id; 3792aa0c033fSGavin Shan phb->type = ioda_type; 3793781a868fSWei Yang mutex_init(&phb->ioda.pe_alloc_mutex); 3794184cd4a3SBenjamin Herrenschmidt 3795cee72d5bSBenjamin Herrenschmidt /* Detect specific models for error handling */ 3796cee72d5bSBenjamin Herrenschmidt if (of_device_is_compatible(np, "ibm,p7ioc-pciex")) 3797cee72d5bSBenjamin Herrenschmidt phb->model = PNV_PHB_MODEL_P7IOC; 3798f3d40c25SBenjamin Herrenschmidt else if (of_device_is_compatible(np, "ibm,power8-pciex")) 3799aa0c033fSGavin Shan phb->model = PNV_PHB_MODEL_PHB3; 38005d2aa710SAlistair Popple else if (of_device_is_compatible(np, "ibm,power8-npu-pciex")) 38015d2aa710SAlistair Popple phb->model = PNV_PHB_MODEL_NPU; 3802616badd2SAlistair Popple else if (of_device_is_compatible(np, "ibm,power9-npu-pciex")) 3803616badd2SAlistair Popple phb->model = PNV_PHB_MODEL_NPU2; 3804cee72d5bSBenjamin Herrenschmidt else 3805cee72d5bSBenjamin Herrenschmidt phb->model = PNV_PHB_MODEL_UNKNOWN; 3806cee72d5bSBenjamin Herrenschmidt 38075cb1f8fdSRussell Currey /* Initialize diagnostic data buffer */ 38085cb1f8fdSRussell Currey prop32 = of_get_property(np, "ibm,phb-diag-data-size", NULL); 38095cb1f8fdSRussell Currey if (prop32) 38105cb1f8fdSRussell Currey phb->diag_data_size = be32_to_cpup(prop32); 38115cb1f8fdSRussell Currey else 38125cb1f8fdSRussell Currey phb->diag_data_size = PNV_PCI_DIAG_BUF_SIZE; 38135cb1f8fdSRussell Currey 38147e1c4e27SMike Rapoport phb->diag_data = memblock_alloc(phb->diag_data_size, SMP_CACHE_BYTES); 38158a7f97b9SMike Rapoport if (!phb->diag_data) 38168a7f97b9SMike Rapoport panic("%s: Failed to allocate %u bytes\n", __func__, 38178a7f97b9SMike Rapoport phb->diag_data_size); 38185cb1f8fdSRussell Currey 3819aa0c033fSGavin Shan /* Parse 32-bit and IO ranges (if any) */ 38202f1ec02eSGavin Shan pci_process_bridge_OF_ranges(hose, np, !hose->global_number); 3821184cd4a3SBenjamin Herrenschmidt 3822aa0c033fSGavin Shan /* Get registers */ 3823fd141d1aSBenjamin Herrenschmidt if (!of_address_to_resource(np, 0, &r)) { 3824fd141d1aSBenjamin Herrenschmidt phb->regs_phys = r.start; 3825fd141d1aSBenjamin Herrenschmidt phb->regs = ioremap(r.start, resource_size(&r)); 3826184cd4a3SBenjamin Herrenschmidt if (phb->regs == NULL) 3827184cd4a3SBenjamin Herrenschmidt pr_err(" Failed to map registers !\n"); 3828fd141d1aSBenjamin Herrenschmidt } 3829577c8c88SGavin Shan 3830184cd4a3SBenjamin Herrenschmidt /* Initialize more IODA stuff */ 383192b8f137SGavin Shan phb->ioda.total_pe_num = 1; 383236954dc7SGavin Shan prop32 = of_get_property(np, "ibm,opal-num-pes", NULL); 383336954dc7SGavin Shan if (prop32) 383492b8f137SGavin Shan phb->ioda.total_pe_num = be32_to_cpup(prop32); 383536954dc7SGavin Shan prop32 = of_get_property(np, "ibm,opal-reserved-pe", NULL); 383636954dc7SGavin Shan if (prop32) 383792b8f137SGavin Shan phb->ioda.reserved_pe_idx = be32_to_cpup(prop32); 3838262af557SGuo Chao 3839c127562aSGavin Shan /* Invalidate RID to PE# mapping */ 3840c127562aSGavin Shan for (segno = 0; segno < ARRAY_SIZE(phb->ioda.pe_rmap); segno++) 3841c127562aSGavin Shan phb->ioda.pe_rmap[segno] = IODA_INVALID_PE; 3842c127562aSGavin Shan 3843262af557SGuo Chao /* Parse 64-bit MMIO range */ 3844262af557SGuo Chao pnv_ioda_parse_m64_window(phb); 3845262af557SGuo Chao 3846184cd4a3SBenjamin Herrenschmidt phb->ioda.m32_size = resource_size(&hose->mem_resources[0]); 3847aa0c033fSGavin Shan /* FW Has already off top 64k of M32 space (MSI space) */ 3848184cd4a3SBenjamin Herrenschmidt phb->ioda.m32_size += 0x10000; 3849184cd4a3SBenjamin Herrenschmidt 385092b8f137SGavin Shan phb->ioda.m32_segsize = phb->ioda.m32_size / phb->ioda.total_pe_num; 38513fd47f06SBenjamin Herrenschmidt phb->ioda.m32_pci_base = hose->mem_resources[0].start - hose->mem_offset[0]; 3852184cd4a3SBenjamin Herrenschmidt phb->ioda.io_size = hose->pci_io_size; 385392b8f137SGavin Shan phb->ioda.io_segsize = phb->ioda.io_size / phb->ioda.total_pe_num; 3854184cd4a3SBenjamin Herrenschmidt phb->ioda.io_pci_base = 0; /* XXX calculate this ? */ 3855184cd4a3SBenjamin Herrenschmidt 38562b923ed1SGavin Shan /* Calculate how many 32-bit TCE segments we have */ 38572b923ed1SGavin Shan phb->ioda.dma32_count = phb->ioda.m32_pci_base / 38582b923ed1SGavin Shan PNV_IODA1_DMA32_SEGSIZE; 38592b923ed1SGavin Shan 3860c35d2a8cSGavin Shan /* Allocate aux data & arrays. We don't have IO ports on PHB3 */ 3861b7115316SChristophe Leroy size = ALIGN(max_t(unsigned, phb->ioda.total_pe_num, 8) / 8, 386292a86756SAlexey Kardashevskiy sizeof(unsigned long)); 386393289d8cSGavin Shan m64map_off = size; 386493289d8cSGavin Shan size += phb->ioda.total_pe_num * sizeof(phb->ioda.m64_segmap[0]); 3865184cd4a3SBenjamin Herrenschmidt m32map_off = size; 386692b8f137SGavin Shan size += phb->ioda.total_pe_num * sizeof(phb->ioda.m32_segmap[0]); 3867c35d2a8cSGavin Shan if (phb->type == PNV_PHB_IODA1) { 3868c35d2a8cSGavin Shan iomap_off = size; 386992b8f137SGavin Shan size += phb->ioda.total_pe_num * sizeof(phb->ioda.io_segmap[0]); 38702b923ed1SGavin Shan dma32map_off = size; 38712b923ed1SGavin Shan size += phb->ioda.dma32_count * 38722b923ed1SGavin Shan sizeof(phb->ioda.dma32_segmap[0]); 3873c35d2a8cSGavin Shan } 3874184cd4a3SBenjamin Herrenschmidt pemap_off = size; 387592b8f137SGavin Shan size += phb->ioda.total_pe_num * sizeof(struct pnv_ioda_pe); 38767e1c4e27SMike Rapoport aux = memblock_alloc(size, SMP_CACHE_BYTES); 38778a7f97b9SMike Rapoport if (!aux) 38788a7f97b9SMike Rapoport panic("%s: Failed to allocate %lu bytes\n", __func__, size); 3879184cd4a3SBenjamin Herrenschmidt phb->ioda.pe_alloc = aux; 388093289d8cSGavin Shan phb->ioda.m64_segmap = aux + m64map_off; 3881184cd4a3SBenjamin Herrenschmidt phb->ioda.m32_segmap = aux + m32map_off; 388293289d8cSGavin Shan for (segno = 0; segno < phb->ioda.total_pe_num; segno++) { 388393289d8cSGavin Shan phb->ioda.m64_segmap[segno] = IODA_INVALID_PE; 38843fa23ff8SGavin Shan phb->ioda.m32_segmap[segno] = IODA_INVALID_PE; 388593289d8cSGavin Shan } 38863fa23ff8SGavin Shan if (phb->type == PNV_PHB_IODA1) { 3887184cd4a3SBenjamin Herrenschmidt phb->ioda.io_segmap = aux + iomap_off; 38883fa23ff8SGavin Shan for (segno = 0; segno < phb->ioda.total_pe_num; segno++) 38893fa23ff8SGavin Shan phb->ioda.io_segmap[segno] = IODA_INVALID_PE; 38902b923ed1SGavin Shan 38912b923ed1SGavin Shan phb->ioda.dma32_segmap = aux + dma32map_off; 38922b923ed1SGavin Shan for (segno = 0; segno < phb->ioda.dma32_count; segno++) 38932b923ed1SGavin Shan phb->ioda.dma32_segmap[segno] = IODA_INVALID_PE; 38943fa23ff8SGavin Shan } 3895184cd4a3SBenjamin Herrenschmidt phb->ioda.pe_array = aux + pemap_off; 389663803c39SGavin Shan 389763803c39SGavin Shan /* 389863803c39SGavin Shan * Choose PE number for root bus, which shouldn't have 389963803c39SGavin Shan * M64 resources consumed by its child devices. To pick 390063803c39SGavin Shan * the PE number adjacent to the reserved one if possible. 390163803c39SGavin Shan */ 390263803c39SGavin Shan pnv_ioda_reserve_pe(phb, phb->ioda.reserved_pe_idx); 390363803c39SGavin Shan if (phb->ioda.reserved_pe_idx == 0) { 390463803c39SGavin Shan phb->ioda.root_pe_idx = 1; 390563803c39SGavin Shan pnv_ioda_reserve_pe(phb, phb->ioda.root_pe_idx); 390663803c39SGavin Shan } else if (phb->ioda.reserved_pe_idx == (phb->ioda.total_pe_num - 1)) { 390763803c39SGavin Shan phb->ioda.root_pe_idx = phb->ioda.reserved_pe_idx - 1; 390863803c39SGavin Shan pnv_ioda_reserve_pe(phb, phb->ioda.root_pe_idx); 390963803c39SGavin Shan } else { 391063803c39SGavin Shan phb->ioda.root_pe_idx = IODA_INVALID_PE; 391163803c39SGavin Shan } 3912184cd4a3SBenjamin Herrenschmidt 3913184cd4a3SBenjamin Herrenschmidt INIT_LIST_HEAD(&phb->ioda.pe_list); 3914781a868fSWei Yang mutex_init(&phb->ioda.pe_list_mutex); 3915184cd4a3SBenjamin Herrenschmidt 3916184cd4a3SBenjamin Herrenschmidt /* Calculate how many 32-bit TCE segments we have */ 39172b923ed1SGavin Shan phb->ioda.dma32_count = phb->ioda.m32_pci_base / 3918acce971cSGavin Shan PNV_IODA1_DMA32_SEGSIZE; 3919184cd4a3SBenjamin Herrenschmidt 3920aa0c033fSGavin Shan #if 0 /* We should really do that ... */ 3921184cd4a3SBenjamin Herrenschmidt rc = opal_pci_set_phb_mem_window(opal->phb_id, 3922184cd4a3SBenjamin Herrenschmidt window_type, 3923184cd4a3SBenjamin Herrenschmidt window_num, 3924184cd4a3SBenjamin Herrenschmidt starting_real_address, 3925184cd4a3SBenjamin Herrenschmidt starting_pci_address, 3926184cd4a3SBenjamin Herrenschmidt segment_size); 3927184cd4a3SBenjamin Herrenschmidt #endif 3928184cd4a3SBenjamin Herrenschmidt 3929262af557SGuo Chao pr_info(" %03d (%03d) PE's M32: 0x%x [segment=0x%x]\n", 393092b8f137SGavin Shan phb->ioda.total_pe_num, phb->ioda.reserved_pe_idx, 3931262af557SGuo Chao phb->ioda.m32_size, phb->ioda.m32_segsize); 3932262af557SGuo Chao if (phb->ioda.m64_size) 3933262af557SGuo Chao pr_info(" M64: 0x%lx [segment=0x%lx]\n", 3934262af557SGuo Chao phb->ioda.m64_size, phb->ioda.m64_segsize); 3935262af557SGuo Chao if (phb->ioda.io_size) 3936262af557SGuo Chao pr_info(" IO: 0x%x [segment=0x%x]\n", 3937184cd4a3SBenjamin Herrenschmidt phb->ioda.io_size, phb->ioda.io_segsize); 3938184cd4a3SBenjamin Herrenschmidt 3939262af557SGuo Chao 3940184cd4a3SBenjamin Herrenschmidt phb->hose->ops = &pnv_pci_ops; 394149dec922SGavin Shan phb->get_pe_state = pnv_ioda_get_pe_state; 394249dec922SGavin Shan phb->freeze_pe = pnv_ioda_freeze_pe; 394349dec922SGavin Shan phb->unfreeze_pe = pnv_ioda_unfreeze_pe; 3944184cd4a3SBenjamin Herrenschmidt 3945184cd4a3SBenjamin Herrenschmidt /* Setup MSI support */ 3946184cd4a3SBenjamin Herrenschmidt pnv_pci_init_ioda_msis(phb); 3947184cd4a3SBenjamin Herrenschmidt 3948c40a4210SGavin Shan /* 3949c40a4210SGavin Shan * We pass the PCI probe flag PCI_REASSIGN_ALL_RSRC here 3950c40a4210SGavin Shan * to let the PCI core do resource assignment. It's supposed 3951c40a4210SGavin Shan * that the PCI core will do correct I/O and MMIO alignment 3952c40a4210SGavin Shan * for the P2P bridge bars so that each PCI bus (excluding 3953c40a4210SGavin Shan * the child P2P bridges) can form individual PE. 3954184cd4a3SBenjamin Herrenschmidt */ 3955fb446ad0SGavin Shan ppc_md.pcibios_fixup = pnv_pci_ioda_fixup; 39565d2aa710SAlistair Popple 39577f2c39e9SFrederic Barrat switch (phb->type) { 39587f2c39e9SFrederic Barrat case PNV_PHB_NPU_NVLINK: 39595d2aa710SAlistair Popple hose->controller_ops = pnv_npu_ioda_controller_ops; 39607f2c39e9SFrederic Barrat break; 39617f2c39e9SFrederic Barrat case PNV_PHB_NPU_OCAPI: 39627f2c39e9SFrederic Barrat hose->controller_ops = pnv_npu_ocapi_ioda_controller_ops; 39637f2c39e9SFrederic Barrat break; 39647f2c39e9SFrederic Barrat default: 396592ae0353SDaniel Axtens hose->controller_ops = pnv_pci_ioda_controller_ops; 3966f9f83456SAlexey Kardashevskiy } 3967ad30cb99SMichael Ellerman 396838274637SYongji Xie ppc_md.pcibios_default_alignment = pnv_pci_default_alignment; 396938274637SYongji Xie 39706e628c7dSWei Yang #ifdef CONFIG_PCI_IOV 3971965c94f3SOliver O'Halloran ppc_md.pcibios_fixup_sriov = pnv_pci_ioda_fixup_iov; 39725350ab3fSWei Yang ppc_md.pcibios_iov_resource_alignment = pnv_pci_iov_resource_alignment; 3973988fc3baSBryant G. Ly ppc_md.pcibios_sriov_enable = pnv_pcibios_sriov_enable; 3974988fc3baSBryant G. Ly ppc_md.pcibios_sriov_disable = pnv_pcibios_sriov_disable; 3975ad30cb99SMichael Ellerman #endif 3976ad30cb99SMichael Ellerman 3977c40a4210SGavin Shan pci_add_flags(PCI_REASSIGN_ALL_RSRC); 3978184cd4a3SBenjamin Herrenschmidt 3979184cd4a3SBenjamin Herrenschmidt /* Reset IODA tables to a clean state */ 3980d1a85eeeSGavin Shan rc = opal_pci_reset(phb_id, OPAL_RESET_PCI_IODA_TABLE, OPAL_ASSERT_RESET); 3981184cd4a3SBenjamin Herrenschmidt if (rc) 3982f2c2cbccSJoe Perches pr_warn(" OPAL Error %ld performing IODA table reset !\n", rc); 3983361f2a2aSGavin Shan 39846060e9eaSAndrew Donnellan /* 39856060e9eaSAndrew Donnellan * If we're running in kdump kernel, the previous kernel never 3986361f2a2aSGavin Shan * shutdown PCI devices correctly. We already got IODA table 3987361f2a2aSGavin Shan * cleaned out. So we have to issue PHB reset to stop all PCI 398845baee14SGuilherme G. Piccoli * transactions from previous kernel. The ppc_pci_reset_phbs 3989b174b4fbSOliver O'Halloran * kernel parameter will force this reset too. Additionally, 3990b174b4fbSOliver O'Halloran * if the IODA reset above failed then use a bigger hammer. 3991b174b4fbSOliver O'Halloran * This can happen if we get a PHB fatal error in very early 3992b174b4fbSOliver O'Halloran * boot. 3993361f2a2aSGavin Shan */ 3994b174b4fbSOliver O'Halloran if (is_kdump_kernel() || pci_reset_phbs || rc) { 3995361f2a2aSGavin Shan pr_info(" Issue PHB reset ...\n"); 3996cadf364dSGavin Shan pnv_eeh_phb_reset(hose, EEH_RESET_FUNDAMENTAL); 3997cadf364dSGavin Shan pnv_eeh_phb_reset(hose, EEH_RESET_DEACTIVATE); 3998361f2a2aSGavin Shan } 3999262af557SGuo Chao 40009e9e8935SGavin Shan /* Remove M64 resource if we can't configure it successfully */ 40019e9e8935SGavin Shan if (!phb->init_m64 || phb->init_m64(phb)) 4002262af557SGuo Chao hose->mem_resources[1].flags = 0; 4003184cd4a3SBenjamin Herrenschmidt } 4004184cd4a3SBenjamin Herrenschmidt 400567975005SBjorn Helgaas void __init pnv_pci_init_ioda2_phb(struct device_node *np) 4006aa0c033fSGavin Shan { 4007e9cc17d4SGavin Shan pnv_pci_init_ioda_phb(np, 0, PNV_PHB_IODA2); 4008aa0c033fSGavin Shan } 4009aa0c033fSGavin Shan 40105d2aa710SAlistair Popple void __init pnv_pci_init_npu_phb(struct device_node *np) 40115d2aa710SAlistair Popple { 40127f2c39e9SFrederic Barrat pnv_pci_init_ioda_phb(np, 0, PNV_PHB_NPU_NVLINK); 40135d2aa710SAlistair Popple } 40145d2aa710SAlistair Popple 40157f2c39e9SFrederic Barrat void __init pnv_pci_init_npu2_opencapi_phb(struct device_node *np) 40167f2c39e9SFrederic Barrat { 40177f2c39e9SFrederic Barrat pnv_pci_init_ioda_phb(np, 0, PNV_PHB_NPU_OCAPI); 4018184cd4a3SBenjamin Herrenschmidt } 4019184cd4a3SBenjamin Herrenschmidt 4020228c2f41SAndrew Donnellan static void pnv_npu2_opencapi_cfg_size_fixup(struct pci_dev *dev) 4021228c2f41SAndrew Donnellan { 4022228c2f41SAndrew Donnellan struct pci_controller *hose = pci_bus_to_host(dev->bus); 4023228c2f41SAndrew Donnellan struct pnv_phb *phb = hose->private_data; 4024228c2f41SAndrew Donnellan 4025228c2f41SAndrew Donnellan if (!machine_is(powernv)) 4026228c2f41SAndrew Donnellan return; 4027228c2f41SAndrew Donnellan 4028228c2f41SAndrew Donnellan if (phb->type == PNV_PHB_NPU_OCAPI) 4029228c2f41SAndrew Donnellan dev->cfg_size = PCI_CFG_SPACE_EXP_SIZE; 4030228c2f41SAndrew Donnellan } 4031228c2f41SAndrew Donnellan DECLARE_PCI_FIXUP_EARLY(PCI_ANY_ID, PCI_ANY_ID, pnv_npu2_opencapi_cfg_size_fixup); 4032228c2f41SAndrew Donnellan 4033184cd4a3SBenjamin Herrenschmidt void __init pnv_pci_init_ioda_hub(struct device_node *np) 4034184cd4a3SBenjamin Herrenschmidt { 4035184cd4a3SBenjamin Herrenschmidt struct device_node *phbn; 4036184cd4a3SBenjamin Herrenschmidt const __be64 *prop64; 4037184cd4a3SBenjamin Herrenschmidt u64 hub_id; 4038184cd4a3SBenjamin Herrenschmidt 4039b7c670d6SRob Herring pr_info("Probing IODA IO-Hub %pOF\n", np); 4040184cd4a3SBenjamin Herrenschmidt 4041184cd4a3SBenjamin Herrenschmidt prop64 = of_get_property(np, "ibm,opal-hubid", NULL); 4042184cd4a3SBenjamin Herrenschmidt if (!prop64) { 4043184cd4a3SBenjamin Herrenschmidt pr_err(" Missing \"ibm,opal-hubid\" property !\n"); 4044184cd4a3SBenjamin Herrenschmidt return; 4045184cd4a3SBenjamin Herrenschmidt } 4046184cd4a3SBenjamin Herrenschmidt hub_id = be64_to_cpup(prop64); 4047184cd4a3SBenjamin Herrenschmidt pr_devel(" HUB-ID : 0x%016llx\n", hub_id); 4048184cd4a3SBenjamin Herrenschmidt 4049184cd4a3SBenjamin Herrenschmidt /* Count child PHBs */ 4050184cd4a3SBenjamin Herrenschmidt for_each_child_of_node(np, phbn) { 4051184cd4a3SBenjamin Herrenschmidt /* Look for IODA1 PHBs */ 4052184cd4a3SBenjamin Herrenschmidt if (of_device_is_compatible(phbn, "ibm,ioda-phb")) 4053184cd4a3SBenjamin Herrenschmidt pnv_pci_init_ioda_phb(phbn, hub_id, PNV_PHB_IODA1); 4054184cd4a3SBenjamin Herrenschmidt } 4055184cd4a3SBenjamin Herrenschmidt } 4056