1184cd4a3SBenjamin Herrenschmidt /* 2184cd4a3SBenjamin Herrenschmidt * Support PCI/PCIe on PowerNV platforms 3184cd4a3SBenjamin Herrenschmidt * 4184cd4a3SBenjamin Herrenschmidt * Copyright 2011 Benjamin Herrenschmidt, IBM Corp. 5184cd4a3SBenjamin Herrenschmidt * 6184cd4a3SBenjamin Herrenschmidt * This program is free software; you can redistribute it and/or 7184cd4a3SBenjamin Herrenschmidt * modify it under the terms of the GNU General Public License 8184cd4a3SBenjamin Herrenschmidt * as published by the Free Software Foundation; either version 9184cd4a3SBenjamin Herrenschmidt * 2 of the License, or (at your option) any later version. 10184cd4a3SBenjamin Herrenschmidt */ 11184cd4a3SBenjamin Herrenschmidt 12cee72d5bSBenjamin Herrenschmidt #undef DEBUG 13184cd4a3SBenjamin Herrenschmidt 14184cd4a3SBenjamin Herrenschmidt #include <linux/kernel.h> 15184cd4a3SBenjamin Herrenschmidt #include <linux/pci.h> 16361f2a2aSGavin Shan #include <linux/crash_dump.h> 1737c367f2SGavin Shan #include <linux/debugfs.h> 18184cd4a3SBenjamin Herrenschmidt #include <linux/delay.h> 19184cd4a3SBenjamin Herrenschmidt #include <linux/string.h> 20184cd4a3SBenjamin Herrenschmidt #include <linux/init.h> 21184cd4a3SBenjamin Herrenschmidt #include <linux/bootmem.h> 22184cd4a3SBenjamin Herrenschmidt #include <linux/irq.h> 23184cd4a3SBenjamin Herrenschmidt #include <linux/io.h> 24184cd4a3SBenjamin Herrenschmidt #include <linux/msi.h> 25cd15b048SBenjamin Herrenschmidt #include <linux/memblock.h> 26ac9a5889SAlexey Kardashevskiy #include <linux/iommu.h> 27e57080f1SAlexey Kardashevskiy #include <linux/rculist.h> 284793d65dSAlexey Kardashevskiy #include <linux/sizes.h> 29184cd4a3SBenjamin Herrenschmidt 30184cd4a3SBenjamin Herrenschmidt #include <asm/sections.h> 31184cd4a3SBenjamin Herrenschmidt #include <asm/io.h> 32184cd4a3SBenjamin Herrenschmidt #include <asm/prom.h> 33184cd4a3SBenjamin Herrenschmidt #include <asm/pci-bridge.h> 34184cd4a3SBenjamin Herrenschmidt #include <asm/machdep.h> 35fb1b55d6SGavin Shan #include <asm/msi_bitmap.h> 36184cd4a3SBenjamin Herrenschmidt #include <asm/ppc-pci.h> 37184cd4a3SBenjamin Herrenschmidt #include <asm/opal.h> 38184cd4a3SBenjamin Herrenschmidt #include <asm/iommu.h> 39184cd4a3SBenjamin Herrenschmidt #include <asm/tce.h> 40137436c9SGavin Shan #include <asm/xics.h> 4137c367f2SGavin Shan #include <asm/debug.h> 42262af557SGuo Chao #include <asm/firmware.h> 4380c49c7eSIan Munsie #include <asm/pnv-pci.h> 44aca6913fSAlexey Kardashevskiy #include <asm/mmzone.h> 4580c49c7eSIan Munsie 46ec249dd8SMichael Neuling #include <misc/cxl-base.h> 47184cd4a3SBenjamin Herrenschmidt 48184cd4a3SBenjamin Herrenschmidt #include "powernv.h" 49184cd4a3SBenjamin Herrenschmidt #include "pci.h" 50184cd4a3SBenjamin Herrenschmidt 51781a868fSWei Yang /* 256M DMA window, 4K TCE pages, 8 bytes TCE */ 52781a868fSWei Yang #define TCE32_TABLE_SIZE ((0x10000000 / 0x1000) * 8) 53781a868fSWei Yang 54bbb845c4SAlexey Kardashevskiy #define POWERNV_IOMMU_DEFAULT_LEVELS 1 55bbb845c4SAlexey Kardashevskiy #define POWERNV_IOMMU_MAX_LEVELS 5 56bbb845c4SAlexey Kardashevskiy 57aca6913fSAlexey Kardashevskiy static void pnv_pci_ioda2_table_free_pages(struct iommu_table *tbl); 58aca6913fSAlexey Kardashevskiy 596d31c2faSJoe Perches static void pe_level_printk(const struct pnv_ioda_pe *pe, const char *level, 606d31c2faSJoe Perches const char *fmt, ...) 616d31c2faSJoe Perches { 626d31c2faSJoe Perches struct va_format vaf; 636d31c2faSJoe Perches va_list args; 646d31c2faSJoe Perches char pfix[32]; 65184cd4a3SBenjamin Herrenschmidt 666d31c2faSJoe Perches va_start(args, fmt); 676d31c2faSJoe Perches 686d31c2faSJoe Perches vaf.fmt = fmt; 696d31c2faSJoe Perches vaf.va = &args; 706d31c2faSJoe Perches 71781a868fSWei Yang if (pe->flags & PNV_IODA_PE_DEV) 726d31c2faSJoe Perches strlcpy(pfix, dev_name(&pe->pdev->dev), sizeof(pfix)); 73781a868fSWei Yang else if (pe->flags & (PNV_IODA_PE_BUS | PNV_IODA_PE_BUS_ALL)) 746d31c2faSJoe Perches sprintf(pfix, "%04x:%02x ", 756d31c2faSJoe Perches pci_domain_nr(pe->pbus), pe->pbus->number); 76781a868fSWei Yang #ifdef CONFIG_PCI_IOV 77781a868fSWei Yang else if (pe->flags & PNV_IODA_PE_VF) 78781a868fSWei Yang sprintf(pfix, "%04x:%02x:%2x.%d", 79781a868fSWei Yang pci_domain_nr(pe->parent_dev->bus), 80781a868fSWei Yang (pe->rid & 0xff00) >> 8, 81781a868fSWei Yang PCI_SLOT(pe->rid), PCI_FUNC(pe->rid)); 82781a868fSWei Yang #endif /* CONFIG_PCI_IOV*/ 836d31c2faSJoe Perches 846d31c2faSJoe Perches printk("%spci %s: [PE# %.3d] %pV", 856d31c2faSJoe Perches level, pfix, pe->pe_number, &vaf); 866d31c2faSJoe Perches 876d31c2faSJoe Perches va_end(args); 886d31c2faSJoe Perches } 896d31c2faSJoe Perches 906d31c2faSJoe Perches #define pe_err(pe, fmt, ...) \ 916d31c2faSJoe Perches pe_level_printk(pe, KERN_ERR, fmt, ##__VA_ARGS__) 926d31c2faSJoe Perches #define pe_warn(pe, fmt, ...) \ 936d31c2faSJoe Perches pe_level_printk(pe, KERN_WARNING, fmt, ##__VA_ARGS__) 946d31c2faSJoe Perches #define pe_info(pe, fmt, ...) \ 956d31c2faSJoe Perches pe_level_printk(pe, KERN_INFO, fmt, ##__VA_ARGS__) 96184cd4a3SBenjamin Herrenschmidt 974e287840SThadeu Lima de Souza Cascardo static bool pnv_iommu_bypass_disabled __read_mostly; 984e287840SThadeu Lima de Souza Cascardo 994e287840SThadeu Lima de Souza Cascardo static int __init iommu_setup(char *str) 1004e287840SThadeu Lima de Souza Cascardo { 1014e287840SThadeu Lima de Souza Cascardo if (!str) 1024e287840SThadeu Lima de Souza Cascardo return -EINVAL; 1034e287840SThadeu Lima de Souza Cascardo 1044e287840SThadeu Lima de Souza Cascardo while (*str) { 1054e287840SThadeu Lima de Souza Cascardo if (!strncmp(str, "nobypass", 8)) { 1064e287840SThadeu Lima de Souza Cascardo pnv_iommu_bypass_disabled = true; 1074e287840SThadeu Lima de Souza Cascardo pr_info("PowerNV: IOMMU bypass window disabled.\n"); 1084e287840SThadeu Lima de Souza Cascardo break; 1094e287840SThadeu Lima de Souza Cascardo } 1104e287840SThadeu Lima de Souza Cascardo str += strcspn(str, ","); 1114e287840SThadeu Lima de Souza Cascardo if (*str == ',') 1124e287840SThadeu Lima de Souza Cascardo str++; 1134e287840SThadeu Lima de Souza Cascardo } 1144e287840SThadeu Lima de Souza Cascardo 1154e287840SThadeu Lima de Souza Cascardo return 0; 1164e287840SThadeu Lima de Souza Cascardo } 1174e287840SThadeu Lima de Souza Cascardo early_param("iommu", iommu_setup); 1184e287840SThadeu Lima de Souza Cascardo 1198e0a1611SAlexey Kardashevskiy /* 1208e0a1611SAlexey Kardashevskiy * stdcix is only supposed to be used in hypervisor real mode as per 1218e0a1611SAlexey Kardashevskiy * the architecture spec 1228e0a1611SAlexey Kardashevskiy */ 1238e0a1611SAlexey Kardashevskiy static inline void __raw_rm_writeq(u64 val, volatile void __iomem *paddr) 1248e0a1611SAlexey Kardashevskiy { 1258e0a1611SAlexey Kardashevskiy __asm__ __volatile__("stdcix %0,0,%1" 1268e0a1611SAlexey Kardashevskiy : : "r" (val), "r" (paddr) : "memory"); 1278e0a1611SAlexey Kardashevskiy } 1288e0a1611SAlexey Kardashevskiy 129262af557SGuo Chao static inline bool pnv_pci_is_mem_pref_64(unsigned long flags) 130262af557SGuo Chao { 131262af557SGuo Chao return ((flags & (IORESOURCE_MEM_64 | IORESOURCE_PREFETCH)) == 132262af557SGuo Chao (IORESOURCE_MEM_64 | IORESOURCE_PREFETCH)); 133262af557SGuo Chao } 134262af557SGuo Chao 1354b82ab18SGavin Shan static void pnv_ioda_reserve_pe(struct pnv_phb *phb, int pe_no) 1364b82ab18SGavin Shan { 1374b82ab18SGavin Shan if (!(pe_no >= 0 && pe_no < phb->ioda.total_pe)) { 1384b82ab18SGavin Shan pr_warn("%s: Invalid PE %d on PHB#%x\n", 1394b82ab18SGavin Shan __func__, pe_no, phb->hose->global_number); 1404b82ab18SGavin Shan return; 1414b82ab18SGavin Shan } 1424b82ab18SGavin Shan 143e9dc4d7fSGavin Shan if (test_and_set_bit(pe_no, phb->ioda.pe_alloc)) 144e9dc4d7fSGavin Shan pr_debug("%s: PE %d was reserved on PHB#%x\n", 1454b82ab18SGavin Shan __func__, pe_no, phb->hose->global_number); 1464b82ab18SGavin Shan 1474b82ab18SGavin Shan phb->ioda.pe_array[pe_no].phb = phb; 1484b82ab18SGavin Shan phb->ioda.pe_array[pe_no].pe_number = pe_no; 1494b82ab18SGavin Shan } 1504b82ab18SGavin Shan 151cad5cef6SGreg Kroah-Hartman static int pnv_ioda_alloc_pe(struct pnv_phb *phb) 152184cd4a3SBenjamin Herrenschmidt { 153184cd4a3SBenjamin Herrenschmidt unsigned long pe; 154184cd4a3SBenjamin Herrenschmidt 155184cd4a3SBenjamin Herrenschmidt do { 156184cd4a3SBenjamin Herrenschmidt pe = find_next_zero_bit(phb->ioda.pe_alloc, 157184cd4a3SBenjamin Herrenschmidt phb->ioda.total_pe, 0); 158184cd4a3SBenjamin Herrenschmidt if (pe >= phb->ioda.total_pe) 159184cd4a3SBenjamin Herrenschmidt return IODA_INVALID_PE; 160184cd4a3SBenjamin Herrenschmidt } while(test_and_set_bit(pe, phb->ioda.pe_alloc)); 161184cd4a3SBenjamin Herrenschmidt 1624cce9550SGavin Shan phb->ioda.pe_array[pe].phb = phb; 163184cd4a3SBenjamin Herrenschmidt phb->ioda.pe_array[pe].pe_number = pe; 164184cd4a3SBenjamin Herrenschmidt return pe; 165184cd4a3SBenjamin Herrenschmidt } 166184cd4a3SBenjamin Herrenschmidt 167cad5cef6SGreg Kroah-Hartman static void pnv_ioda_free_pe(struct pnv_phb *phb, int pe) 168184cd4a3SBenjamin Herrenschmidt { 169184cd4a3SBenjamin Herrenschmidt WARN_ON(phb->ioda.pe_array[pe].pdev); 170184cd4a3SBenjamin Herrenschmidt 171184cd4a3SBenjamin Herrenschmidt memset(&phb->ioda.pe_array[pe], 0, sizeof(struct pnv_ioda_pe)); 172184cd4a3SBenjamin Herrenschmidt clear_bit(pe, phb->ioda.pe_alloc); 173184cd4a3SBenjamin Herrenschmidt } 174184cd4a3SBenjamin Herrenschmidt 175262af557SGuo Chao /* The default M64 BAR is shared by all PEs */ 176262af557SGuo Chao static int pnv_ioda2_init_m64(struct pnv_phb *phb) 177262af557SGuo Chao { 178262af557SGuo Chao const char *desc; 179262af557SGuo Chao struct resource *r; 180262af557SGuo Chao s64 rc; 181262af557SGuo Chao 182262af557SGuo Chao /* Configure the default M64 BAR */ 183262af557SGuo Chao rc = opal_pci_set_phb_mem_window(phb->opal_id, 184262af557SGuo Chao OPAL_M64_WINDOW_TYPE, 185262af557SGuo Chao phb->ioda.m64_bar_idx, 186262af557SGuo Chao phb->ioda.m64_base, 187262af557SGuo Chao 0, /* unused */ 188262af557SGuo Chao phb->ioda.m64_size); 189262af557SGuo Chao if (rc != OPAL_SUCCESS) { 190262af557SGuo Chao desc = "configuring"; 191262af557SGuo Chao goto fail; 192262af557SGuo Chao } 193262af557SGuo Chao 194262af557SGuo Chao /* Enable the default M64 BAR */ 195262af557SGuo Chao rc = opal_pci_phb_mmio_enable(phb->opal_id, 196262af557SGuo Chao OPAL_M64_WINDOW_TYPE, 197262af557SGuo Chao phb->ioda.m64_bar_idx, 198262af557SGuo Chao OPAL_ENABLE_M64_SPLIT); 199262af557SGuo Chao if (rc != OPAL_SUCCESS) { 200262af557SGuo Chao desc = "enabling"; 201262af557SGuo Chao goto fail; 202262af557SGuo Chao } 203262af557SGuo Chao 204262af557SGuo Chao /* Mark the M64 BAR assigned */ 205262af557SGuo Chao set_bit(phb->ioda.m64_bar_idx, &phb->ioda.m64_bar_alloc); 206262af557SGuo Chao 207262af557SGuo Chao /* 208262af557SGuo Chao * Strip off the segment used by the reserved PE, which is 209262af557SGuo Chao * expected to be 0 or last one of PE capabicity. 210262af557SGuo Chao */ 211262af557SGuo Chao r = &phb->hose->mem_resources[1]; 212262af557SGuo Chao if (phb->ioda.reserved_pe == 0) 213262af557SGuo Chao r->start += phb->ioda.m64_segsize; 214262af557SGuo Chao else if (phb->ioda.reserved_pe == (phb->ioda.total_pe - 1)) 215262af557SGuo Chao r->end -= phb->ioda.m64_segsize; 216262af557SGuo Chao else 217262af557SGuo Chao pr_warn(" Cannot strip M64 segment for reserved PE#%d\n", 218262af557SGuo Chao phb->ioda.reserved_pe); 219262af557SGuo Chao 220262af557SGuo Chao return 0; 221262af557SGuo Chao 222262af557SGuo Chao fail: 223262af557SGuo Chao pr_warn(" Failure %lld %s M64 BAR#%d\n", 224262af557SGuo Chao rc, desc, phb->ioda.m64_bar_idx); 225262af557SGuo Chao opal_pci_phb_mmio_enable(phb->opal_id, 226262af557SGuo Chao OPAL_M64_WINDOW_TYPE, 227262af557SGuo Chao phb->ioda.m64_bar_idx, 228262af557SGuo Chao OPAL_DISABLE_M64); 229262af557SGuo Chao return -EIO; 230262af557SGuo Chao } 231262af557SGuo Chao 23296a2f92bSGavin Shan static void pnv_ioda2_reserve_dev_m64_pe(struct pci_dev *pdev, 23396a2f92bSGavin Shan unsigned long *pe_bitmap) 234262af557SGuo Chao { 23596a2f92bSGavin Shan struct pci_controller *hose = pci_bus_to_host(pdev->bus); 23696a2f92bSGavin Shan struct pnv_phb *phb = hose->private_data; 237262af557SGuo Chao struct resource *r; 23896a2f92bSGavin Shan resource_size_t base, sgsz, start, end; 23996a2f92bSGavin Shan int segno, i; 240262af557SGuo Chao 24196a2f92bSGavin Shan base = phb->ioda.m64_base; 24296a2f92bSGavin Shan sgsz = phb->ioda.m64_segsize; 24396a2f92bSGavin Shan for (i = 0; i <= PCI_ROM_RESOURCE; i++) { 24496a2f92bSGavin Shan r = &pdev->resource[i]; 24596a2f92bSGavin Shan if (!r->parent || !pnv_pci_is_mem_pref_64(r->flags)) 246262af557SGuo Chao continue; 247262af557SGuo Chao 24896a2f92bSGavin Shan start = _ALIGN_DOWN(r->start - base, sgsz); 24996a2f92bSGavin Shan end = _ALIGN_UP(r->end - base, sgsz); 25096a2f92bSGavin Shan for (segno = start / sgsz; segno < end / sgsz; segno++) { 25196a2f92bSGavin Shan if (pe_bitmap) 25296a2f92bSGavin Shan set_bit(segno, pe_bitmap); 25396a2f92bSGavin Shan else 25496a2f92bSGavin Shan pnv_ioda_reserve_pe(phb, segno); 255262af557SGuo Chao } 256262af557SGuo Chao } 257262af557SGuo Chao } 258262af557SGuo Chao 25996a2f92bSGavin Shan static void pnv_ioda2_reserve_m64_pe(struct pci_bus *bus, 26096a2f92bSGavin Shan unsigned long *pe_bitmap, 26196a2f92bSGavin Shan bool all) 26296a2f92bSGavin Shan { 26396a2f92bSGavin Shan struct pci_dev *pdev; 26496a2f92bSGavin Shan 26596a2f92bSGavin Shan list_for_each_entry(pdev, &bus->devices, bus_list) { 26696a2f92bSGavin Shan pnv_ioda2_reserve_dev_m64_pe(pdev, pe_bitmap); 26796a2f92bSGavin Shan 26896a2f92bSGavin Shan if (all && pdev->subordinate) 26996a2f92bSGavin Shan pnv_ioda2_reserve_m64_pe(pdev->subordinate, 27096a2f92bSGavin Shan pe_bitmap, all); 27196a2f92bSGavin Shan } 27296a2f92bSGavin Shan } 27396a2f92bSGavin Shan 274262af557SGuo Chao static int pnv_ioda2_pick_m64_pe(struct pnv_phb *phb, 275262af557SGuo Chao struct pci_bus *bus, int all) 276262af557SGuo Chao { 277262af557SGuo Chao resource_size_t segsz = phb->ioda.m64_segsize; 278262af557SGuo Chao struct pci_dev *pdev; 279262af557SGuo Chao struct resource *r; 280262af557SGuo Chao struct pnv_ioda_pe *master_pe, *pe; 281262af557SGuo Chao unsigned long size, *pe_alloc; 282262af557SGuo Chao bool found; 283262af557SGuo Chao int start, i, j; 284262af557SGuo Chao 285262af557SGuo Chao /* Root bus shouldn't use M64 */ 286262af557SGuo Chao if (pci_is_root_bus(bus)) 287262af557SGuo Chao return IODA_INVALID_PE; 288262af557SGuo Chao 289262af557SGuo Chao /* We support only one M64 window on each bus */ 290262af557SGuo Chao found = false; 291262af557SGuo Chao pci_bus_for_each_resource(bus, r, i) { 292262af557SGuo Chao if (r && r->parent && 293262af557SGuo Chao pnv_pci_is_mem_pref_64(r->flags)) { 294262af557SGuo Chao found = true; 295262af557SGuo Chao break; 296262af557SGuo Chao } 297262af557SGuo Chao } 298262af557SGuo Chao 299262af557SGuo Chao /* No M64 window found ? */ 300262af557SGuo Chao if (!found) 301262af557SGuo Chao return IODA_INVALID_PE; 302262af557SGuo Chao 303262af557SGuo Chao /* Allocate bitmap */ 304262af557SGuo Chao size = _ALIGN_UP(phb->ioda.total_pe / 8, sizeof(unsigned long)); 305262af557SGuo Chao pe_alloc = kzalloc(size, GFP_KERNEL); 306262af557SGuo Chao if (!pe_alloc) { 307262af557SGuo Chao pr_warn("%s: Out of memory !\n", 308262af557SGuo Chao __func__); 309262af557SGuo Chao return IODA_INVALID_PE; 310262af557SGuo Chao } 311262af557SGuo Chao 312262af557SGuo Chao /* 313262af557SGuo Chao * Figure out reserved PE numbers by the PE 314262af557SGuo Chao * the its child PEs. 315262af557SGuo Chao */ 316262af557SGuo Chao start = (r->start - phb->ioda.m64_base) / segsz; 317262af557SGuo Chao for (i = 0; i < resource_size(r) / segsz; i++) 318262af557SGuo Chao set_bit(start + i, pe_alloc); 319262af557SGuo Chao 320262af557SGuo Chao if (all) 321262af557SGuo Chao goto done; 322262af557SGuo Chao 323262af557SGuo Chao /* 324262af557SGuo Chao * If the PE doesn't cover all subordinate buses, 325262af557SGuo Chao * we need subtract from reserved PEs for children. 326262af557SGuo Chao */ 327262af557SGuo Chao list_for_each_entry(pdev, &bus->devices, bus_list) { 328262af557SGuo Chao if (!pdev->subordinate) 329262af557SGuo Chao continue; 330262af557SGuo Chao 331262af557SGuo Chao pci_bus_for_each_resource(pdev->subordinate, r, i) { 332262af557SGuo Chao if (!r || !r->parent || 333262af557SGuo Chao !pnv_pci_is_mem_pref_64(r->flags)) 334262af557SGuo Chao continue; 335262af557SGuo Chao 336262af557SGuo Chao start = (r->start - phb->ioda.m64_base) / segsz; 337262af557SGuo Chao for (j = 0; j < resource_size(r) / segsz ; j++) 338262af557SGuo Chao clear_bit(start + j, pe_alloc); 339262af557SGuo Chao } 340262af557SGuo Chao } 341262af557SGuo Chao 342262af557SGuo Chao /* 343262af557SGuo Chao * the current bus might not own M64 window and that's all 344262af557SGuo Chao * contributed by its child buses. For the case, we needn't 345262af557SGuo Chao * pick M64 dependent PE#. 346262af557SGuo Chao */ 347262af557SGuo Chao if (bitmap_empty(pe_alloc, phb->ioda.total_pe)) { 348262af557SGuo Chao kfree(pe_alloc); 349262af557SGuo Chao return IODA_INVALID_PE; 350262af557SGuo Chao } 351262af557SGuo Chao 352262af557SGuo Chao /* 353262af557SGuo Chao * Figure out the master PE and put all slave PEs to master 354262af557SGuo Chao * PE's list to form compound PE. 355262af557SGuo Chao */ 356262af557SGuo Chao done: 357262af557SGuo Chao master_pe = NULL; 358262af557SGuo Chao i = -1; 359262af557SGuo Chao while ((i = find_next_bit(pe_alloc, phb->ioda.total_pe, i + 1)) < 360262af557SGuo Chao phb->ioda.total_pe) { 361262af557SGuo Chao pe = &phb->ioda.pe_array[i]; 362262af557SGuo Chao 363262af557SGuo Chao if (!master_pe) { 364262af557SGuo Chao pe->flags |= PNV_IODA_PE_MASTER; 365262af557SGuo Chao INIT_LIST_HEAD(&pe->slaves); 366262af557SGuo Chao master_pe = pe; 367262af557SGuo Chao } else { 368262af557SGuo Chao pe->flags |= PNV_IODA_PE_SLAVE; 369262af557SGuo Chao pe->master = master_pe; 370262af557SGuo Chao list_add_tail(&pe->list, &master_pe->slaves); 371262af557SGuo Chao } 372262af557SGuo Chao } 373262af557SGuo Chao 374262af557SGuo Chao kfree(pe_alloc); 375262af557SGuo Chao return master_pe->pe_number; 376262af557SGuo Chao } 377262af557SGuo Chao 378262af557SGuo Chao static void __init pnv_ioda_parse_m64_window(struct pnv_phb *phb) 379262af557SGuo Chao { 380262af557SGuo Chao struct pci_controller *hose = phb->hose; 381262af557SGuo Chao struct device_node *dn = hose->dn; 382262af557SGuo Chao struct resource *res; 383262af557SGuo Chao const u32 *r; 384262af557SGuo Chao u64 pci_addr; 385262af557SGuo Chao 3861665c4a8SGavin Shan /* FIXME: Support M64 for P7IOC */ 3871665c4a8SGavin Shan if (phb->type != PNV_PHB_IODA2) { 3881665c4a8SGavin Shan pr_info(" Not support M64 window\n"); 3891665c4a8SGavin Shan return; 3901665c4a8SGavin Shan } 3911665c4a8SGavin Shan 392262af557SGuo Chao if (!firmware_has_feature(FW_FEATURE_OPALv3)) { 393262af557SGuo Chao pr_info(" Firmware too old to support M64 window\n"); 394262af557SGuo Chao return; 395262af557SGuo Chao } 396262af557SGuo Chao 397262af557SGuo Chao r = of_get_property(dn, "ibm,opal-m64-window", NULL); 398262af557SGuo Chao if (!r) { 399262af557SGuo Chao pr_info(" No <ibm,opal-m64-window> on %s\n", 400262af557SGuo Chao dn->full_name); 401262af557SGuo Chao return; 402262af557SGuo Chao } 403262af557SGuo Chao 404262af557SGuo Chao res = &hose->mem_resources[1]; 405262af557SGuo Chao res->start = of_translate_address(dn, r + 2); 406262af557SGuo Chao res->end = res->start + of_read_number(r + 4, 2) - 1; 407262af557SGuo Chao res->flags = (IORESOURCE_MEM | IORESOURCE_MEM_64 | IORESOURCE_PREFETCH); 408262af557SGuo Chao pci_addr = of_read_number(r, 2); 409262af557SGuo Chao hose->mem_offset[1] = res->start - pci_addr; 410262af557SGuo Chao 411262af557SGuo Chao phb->ioda.m64_size = resource_size(res); 412262af557SGuo Chao phb->ioda.m64_segsize = phb->ioda.m64_size / phb->ioda.total_pe; 413262af557SGuo Chao phb->ioda.m64_base = pci_addr; 414262af557SGuo Chao 415e9863e68SWei Yang pr_info(" MEM64 0x%016llx..0x%016llx -> 0x%016llx\n", 416e9863e68SWei Yang res->start, res->end, pci_addr); 417e9863e68SWei Yang 418262af557SGuo Chao /* Use last M64 BAR to cover M64 window */ 419262af557SGuo Chao phb->ioda.m64_bar_idx = 15; 420262af557SGuo Chao phb->init_m64 = pnv_ioda2_init_m64; 4215ef73567SGavin Shan phb->reserve_m64_pe = pnv_ioda2_reserve_m64_pe; 422262af557SGuo Chao phb->pick_m64_pe = pnv_ioda2_pick_m64_pe; 423262af557SGuo Chao } 424262af557SGuo Chao 42549dec922SGavin Shan static void pnv_ioda_freeze_pe(struct pnv_phb *phb, int pe_no) 42649dec922SGavin Shan { 42749dec922SGavin Shan struct pnv_ioda_pe *pe = &phb->ioda.pe_array[pe_no]; 42849dec922SGavin Shan struct pnv_ioda_pe *slave; 42949dec922SGavin Shan s64 rc; 43049dec922SGavin Shan 43149dec922SGavin Shan /* Fetch master PE */ 43249dec922SGavin Shan if (pe->flags & PNV_IODA_PE_SLAVE) { 43349dec922SGavin Shan pe = pe->master; 434ec8e4e9dSGavin Shan if (WARN_ON(!pe || !(pe->flags & PNV_IODA_PE_MASTER))) 435ec8e4e9dSGavin Shan return; 436ec8e4e9dSGavin Shan 43749dec922SGavin Shan pe_no = pe->pe_number; 43849dec922SGavin Shan } 43949dec922SGavin Shan 44049dec922SGavin Shan /* Freeze master PE */ 44149dec922SGavin Shan rc = opal_pci_eeh_freeze_set(phb->opal_id, 44249dec922SGavin Shan pe_no, 44349dec922SGavin Shan OPAL_EEH_ACTION_SET_FREEZE_ALL); 44449dec922SGavin Shan if (rc != OPAL_SUCCESS) { 44549dec922SGavin Shan pr_warn("%s: Failure %lld freezing PHB#%x-PE#%x\n", 44649dec922SGavin Shan __func__, rc, phb->hose->global_number, pe_no); 44749dec922SGavin Shan return; 44849dec922SGavin Shan } 44949dec922SGavin Shan 45049dec922SGavin Shan /* Freeze slave PEs */ 45149dec922SGavin Shan if (!(pe->flags & PNV_IODA_PE_MASTER)) 45249dec922SGavin Shan return; 45349dec922SGavin Shan 45449dec922SGavin Shan list_for_each_entry(slave, &pe->slaves, list) { 45549dec922SGavin Shan rc = opal_pci_eeh_freeze_set(phb->opal_id, 45649dec922SGavin Shan slave->pe_number, 45749dec922SGavin Shan OPAL_EEH_ACTION_SET_FREEZE_ALL); 45849dec922SGavin Shan if (rc != OPAL_SUCCESS) 45949dec922SGavin Shan pr_warn("%s: Failure %lld freezing PHB#%x-PE#%x\n", 46049dec922SGavin Shan __func__, rc, phb->hose->global_number, 46149dec922SGavin Shan slave->pe_number); 46249dec922SGavin Shan } 46349dec922SGavin Shan } 46449dec922SGavin Shan 465e51df2c1SAnton Blanchard static int pnv_ioda_unfreeze_pe(struct pnv_phb *phb, int pe_no, int opt) 46649dec922SGavin Shan { 46749dec922SGavin Shan struct pnv_ioda_pe *pe, *slave; 46849dec922SGavin Shan s64 rc; 46949dec922SGavin Shan 47049dec922SGavin Shan /* Find master PE */ 47149dec922SGavin Shan pe = &phb->ioda.pe_array[pe_no]; 47249dec922SGavin Shan if (pe->flags & PNV_IODA_PE_SLAVE) { 47349dec922SGavin Shan pe = pe->master; 47449dec922SGavin Shan WARN_ON(!pe || !(pe->flags & PNV_IODA_PE_MASTER)); 47549dec922SGavin Shan pe_no = pe->pe_number; 47649dec922SGavin Shan } 47749dec922SGavin Shan 47849dec922SGavin Shan /* Clear frozen state for master PE */ 47949dec922SGavin Shan rc = opal_pci_eeh_freeze_clear(phb->opal_id, pe_no, opt); 48049dec922SGavin Shan if (rc != OPAL_SUCCESS) { 48149dec922SGavin Shan pr_warn("%s: Failure %lld clear %d on PHB#%x-PE#%x\n", 48249dec922SGavin Shan __func__, rc, opt, phb->hose->global_number, pe_no); 48349dec922SGavin Shan return -EIO; 48449dec922SGavin Shan } 48549dec922SGavin Shan 48649dec922SGavin Shan if (!(pe->flags & PNV_IODA_PE_MASTER)) 48749dec922SGavin Shan return 0; 48849dec922SGavin Shan 48949dec922SGavin Shan /* Clear frozen state for slave PEs */ 49049dec922SGavin Shan list_for_each_entry(slave, &pe->slaves, list) { 49149dec922SGavin Shan rc = opal_pci_eeh_freeze_clear(phb->opal_id, 49249dec922SGavin Shan slave->pe_number, 49349dec922SGavin Shan opt); 49449dec922SGavin Shan if (rc != OPAL_SUCCESS) { 49549dec922SGavin Shan pr_warn("%s: Failure %lld clear %d on PHB#%x-PE#%x\n", 49649dec922SGavin Shan __func__, rc, opt, phb->hose->global_number, 49749dec922SGavin Shan slave->pe_number); 49849dec922SGavin Shan return -EIO; 49949dec922SGavin Shan } 50049dec922SGavin Shan } 50149dec922SGavin Shan 50249dec922SGavin Shan return 0; 50349dec922SGavin Shan } 50449dec922SGavin Shan 50549dec922SGavin Shan static int pnv_ioda_get_pe_state(struct pnv_phb *phb, int pe_no) 50649dec922SGavin Shan { 50749dec922SGavin Shan struct pnv_ioda_pe *slave, *pe; 50849dec922SGavin Shan u8 fstate, state; 50949dec922SGavin Shan __be16 pcierr; 51049dec922SGavin Shan s64 rc; 51149dec922SGavin Shan 51249dec922SGavin Shan /* Sanity check on PE number */ 51349dec922SGavin Shan if (pe_no < 0 || pe_no >= phb->ioda.total_pe) 51449dec922SGavin Shan return OPAL_EEH_STOPPED_PERM_UNAVAIL; 51549dec922SGavin Shan 51649dec922SGavin Shan /* 51749dec922SGavin Shan * Fetch the master PE and the PE instance might be 51849dec922SGavin Shan * not initialized yet. 51949dec922SGavin Shan */ 52049dec922SGavin Shan pe = &phb->ioda.pe_array[pe_no]; 52149dec922SGavin Shan if (pe->flags & PNV_IODA_PE_SLAVE) { 52249dec922SGavin Shan pe = pe->master; 52349dec922SGavin Shan WARN_ON(!pe || !(pe->flags & PNV_IODA_PE_MASTER)); 52449dec922SGavin Shan pe_no = pe->pe_number; 52549dec922SGavin Shan } 52649dec922SGavin Shan 52749dec922SGavin Shan /* Check the master PE */ 52849dec922SGavin Shan rc = opal_pci_eeh_freeze_status(phb->opal_id, pe_no, 52949dec922SGavin Shan &state, &pcierr, NULL); 53049dec922SGavin Shan if (rc != OPAL_SUCCESS) { 53149dec922SGavin Shan pr_warn("%s: Failure %lld getting " 53249dec922SGavin Shan "PHB#%x-PE#%x state\n", 53349dec922SGavin Shan __func__, rc, 53449dec922SGavin Shan phb->hose->global_number, pe_no); 53549dec922SGavin Shan return OPAL_EEH_STOPPED_TEMP_UNAVAIL; 53649dec922SGavin Shan } 53749dec922SGavin Shan 53849dec922SGavin Shan /* Check the slave PE */ 53949dec922SGavin Shan if (!(pe->flags & PNV_IODA_PE_MASTER)) 54049dec922SGavin Shan return state; 54149dec922SGavin Shan 54249dec922SGavin Shan list_for_each_entry(slave, &pe->slaves, list) { 54349dec922SGavin Shan rc = opal_pci_eeh_freeze_status(phb->opal_id, 54449dec922SGavin Shan slave->pe_number, 54549dec922SGavin Shan &fstate, 54649dec922SGavin Shan &pcierr, 54749dec922SGavin Shan NULL); 54849dec922SGavin Shan if (rc != OPAL_SUCCESS) { 54949dec922SGavin Shan pr_warn("%s: Failure %lld getting " 55049dec922SGavin Shan "PHB#%x-PE#%x state\n", 55149dec922SGavin Shan __func__, rc, 55249dec922SGavin Shan phb->hose->global_number, slave->pe_number); 55349dec922SGavin Shan return OPAL_EEH_STOPPED_TEMP_UNAVAIL; 55449dec922SGavin Shan } 55549dec922SGavin Shan 55649dec922SGavin Shan /* 55749dec922SGavin Shan * Override the result based on the ascending 55849dec922SGavin Shan * priority. 55949dec922SGavin Shan */ 56049dec922SGavin Shan if (fstate > state) 56149dec922SGavin Shan state = fstate; 56249dec922SGavin Shan } 56349dec922SGavin Shan 56449dec922SGavin Shan return state; 56549dec922SGavin Shan } 56649dec922SGavin Shan 567184cd4a3SBenjamin Herrenschmidt /* Currently those 2 are only used when MSIs are enabled, this will change 568184cd4a3SBenjamin Herrenschmidt * but in the meantime, we need to protect them to avoid warnings 569184cd4a3SBenjamin Herrenschmidt */ 570184cd4a3SBenjamin Herrenschmidt #ifdef CONFIG_PCI_MSI 571cad5cef6SGreg Kroah-Hartman static struct pnv_ioda_pe *pnv_ioda_get_pe(struct pci_dev *dev) 572184cd4a3SBenjamin Herrenschmidt { 573184cd4a3SBenjamin Herrenschmidt struct pci_controller *hose = pci_bus_to_host(dev->bus); 574184cd4a3SBenjamin Herrenschmidt struct pnv_phb *phb = hose->private_data; 575b72c1f65SBenjamin Herrenschmidt struct pci_dn *pdn = pci_get_pdn(dev); 576184cd4a3SBenjamin Herrenschmidt 577184cd4a3SBenjamin Herrenschmidt if (!pdn) 578184cd4a3SBenjamin Herrenschmidt return NULL; 579184cd4a3SBenjamin Herrenschmidt if (pdn->pe_number == IODA_INVALID_PE) 580184cd4a3SBenjamin Herrenschmidt return NULL; 581184cd4a3SBenjamin Herrenschmidt return &phb->ioda.pe_array[pdn->pe_number]; 582184cd4a3SBenjamin Herrenschmidt } 583184cd4a3SBenjamin Herrenschmidt #endif /* CONFIG_PCI_MSI */ 584184cd4a3SBenjamin Herrenschmidt 585b131a842SGavin Shan static int pnv_ioda_set_one_peltv(struct pnv_phb *phb, 586b131a842SGavin Shan struct pnv_ioda_pe *parent, 587b131a842SGavin Shan struct pnv_ioda_pe *child, 588b131a842SGavin Shan bool is_add) 589b131a842SGavin Shan { 590b131a842SGavin Shan const char *desc = is_add ? "adding" : "removing"; 591b131a842SGavin Shan uint8_t op = is_add ? OPAL_ADD_PE_TO_DOMAIN : 592b131a842SGavin Shan OPAL_REMOVE_PE_FROM_DOMAIN; 593b131a842SGavin Shan struct pnv_ioda_pe *slave; 594b131a842SGavin Shan long rc; 595b131a842SGavin Shan 596b131a842SGavin Shan /* Parent PE affects child PE */ 597b131a842SGavin Shan rc = opal_pci_set_peltv(phb->opal_id, parent->pe_number, 598b131a842SGavin Shan child->pe_number, op); 599b131a842SGavin Shan if (rc != OPAL_SUCCESS) { 600b131a842SGavin Shan pe_warn(child, "OPAL error %ld %s to parent PELTV\n", 601b131a842SGavin Shan rc, desc); 602b131a842SGavin Shan return -ENXIO; 603b131a842SGavin Shan } 604b131a842SGavin Shan 605b131a842SGavin Shan if (!(child->flags & PNV_IODA_PE_MASTER)) 606b131a842SGavin Shan return 0; 607b131a842SGavin Shan 608b131a842SGavin Shan /* Compound case: parent PE affects slave PEs */ 609b131a842SGavin Shan list_for_each_entry(slave, &child->slaves, list) { 610b131a842SGavin Shan rc = opal_pci_set_peltv(phb->opal_id, parent->pe_number, 611b131a842SGavin Shan slave->pe_number, op); 612b131a842SGavin Shan if (rc != OPAL_SUCCESS) { 613b131a842SGavin Shan pe_warn(slave, "OPAL error %ld %s to parent PELTV\n", 614b131a842SGavin Shan rc, desc); 615b131a842SGavin Shan return -ENXIO; 616b131a842SGavin Shan } 617b131a842SGavin Shan } 618b131a842SGavin Shan 619b131a842SGavin Shan return 0; 620b131a842SGavin Shan } 621b131a842SGavin Shan 622b131a842SGavin Shan static int pnv_ioda_set_peltv(struct pnv_phb *phb, 623b131a842SGavin Shan struct pnv_ioda_pe *pe, 624b131a842SGavin Shan bool is_add) 625b131a842SGavin Shan { 626b131a842SGavin Shan struct pnv_ioda_pe *slave; 627781a868fSWei Yang struct pci_dev *pdev = NULL; 628b131a842SGavin Shan int ret; 629b131a842SGavin Shan 630b131a842SGavin Shan /* 631b131a842SGavin Shan * Clear PE frozen state. If it's master PE, we need 632b131a842SGavin Shan * clear slave PE frozen state as well. 633b131a842SGavin Shan */ 634b131a842SGavin Shan if (is_add) { 635b131a842SGavin Shan opal_pci_eeh_freeze_clear(phb->opal_id, pe->pe_number, 636b131a842SGavin Shan OPAL_EEH_ACTION_CLEAR_FREEZE_ALL); 637b131a842SGavin Shan if (pe->flags & PNV_IODA_PE_MASTER) { 638b131a842SGavin Shan list_for_each_entry(slave, &pe->slaves, list) 639b131a842SGavin Shan opal_pci_eeh_freeze_clear(phb->opal_id, 640b131a842SGavin Shan slave->pe_number, 641b131a842SGavin Shan OPAL_EEH_ACTION_CLEAR_FREEZE_ALL); 642b131a842SGavin Shan } 643b131a842SGavin Shan } 644b131a842SGavin Shan 645b131a842SGavin Shan /* 646b131a842SGavin Shan * Associate PE in PELT. We need add the PE into the 647b131a842SGavin Shan * corresponding PELT-V as well. Otherwise, the error 648b131a842SGavin Shan * originated from the PE might contribute to other 649b131a842SGavin Shan * PEs. 650b131a842SGavin Shan */ 651b131a842SGavin Shan ret = pnv_ioda_set_one_peltv(phb, pe, pe, is_add); 652b131a842SGavin Shan if (ret) 653b131a842SGavin Shan return ret; 654b131a842SGavin Shan 655b131a842SGavin Shan /* For compound PEs, any one affects all of them */ 656b131a842SGavin Shan if (pe->flags & PNV_IODA_PE_MASTER) { 657b131a842SGavin Shan list_for_each_entry(slave, &pe->slaves, list) { 658b131a842SGavin Shan ret = pnv_ioda_set_one_peltv(phb, slave, pe, is_add); 659b131a842SGavin Shan if (ret) 660b131a842SGavin Shan return ret; 661b131a842SGavin Shan } 662b131a842SGavin Shan } 663b131a842SGavin Shan 664b131a842SGavin Shan if (pe->flags & (PNV_IODA_PE_BUS_ALL | PNV_IODA_PE_BUS)) 665b131a842SGavin Shan pdev = pe->pbus->self; 666781a868fSWei Yang else if (pe->flags & PNV_IODA_PE_DEV) 667b131a842SGavin Shan pdev = pe->pdev->bus->self; 668781a868fSWei Yang #ifdef CONFIG_PCI_IOV 669781a868fSWei Yang else if (pe->flags & PNV_IODA_PE_VF) 670781a868fSWei Yang pdev = pe->parent_dev->bus->self; 671781a868fSWei Yang #endif /* CONFIG_PCI_IOV */ 672b131a842SGavin Shan while (pdev) { 673b131a842SGavin Shan struct pci_dn *pdn = pci_get_pdn(pdev); 674b131a842SGavin Shan struct pnv_ioda_pe *parent; 675b131a842SGavin Shan 676b131a842SGavin Shan if (pdn && pdn->pe_number != IODA_INVALID_PE) { 677b131a842SGavin Shan parent = &phb->ioda.pe_array[pdn->pe_number]; 678b131a842SGavin Shan ret = pnv_ioda_set_one_peltv(phb, parent, pe, is_add); 679b131a842SGavin Shan if (ret) 680b131a842SGavin Shan return ret; 681b131a842SGavin Shan } 682b131a842SGavin Shan 683b131a842SGavin Shan pdev = pdev->bus->self; 684b131a842SGavin Shan } 685b131a842SGavin Shan 686b131a842SGavin Shan return 0; 687b131a842SGavin Shan } 688b131a842SGavin Shan 689781a868fSWei Yang #ifdef CONFIG_PCI_IOV 690781a868fSWei Yang static int pnv_ioda_deconfigure_pe(struct pnv_phb *phb, struct pnv_ioda_pe *pe) 691781a868fSWei Yang { 692781a868fSWei Yang struct pci_dev *parent; 693781a868fSWei Yang uint8_t bcomp, dcomp, fcomp; 694781a868fSWei Yang int64_t rc; 695781a868fSWei Yang long rid_end, rid; 696781a868fSWei Yang 697781a868fSWei Yang /* Currently, we just deconfigure VF PE. Bus PE will always there.*/ 698781a868fSWei Yang if (pe->pbus) { 699781a868fSWei Yang int count; 700781a868fSWei Yang 701781a868fSWei Yang dcomp = OPAL_IGNORE_RID_DEVICE_NUMBER; 702781a868fSWei Yang fcomp = OPAL_IGNORE_RID_FUNCTION_NUMBER; 703781a868fSWei Yang parent = pe->pbus->self; 704781a868fSWei Yang if (pe->flags & PNV_IODA_PE_BUS_ALL) 705781a868fSWei Yang count = pe->pbus->busn_res.end - pe->pbus->busn_res.start + 1; 706781a868fSWei Yang else 707781a868fSWei Yang count = 1; 708781a868fSWei Yang 709781a868fSWei Yang switch(count) { 710781a868fSWei Yang case 1: bcomp = OpalPciBusAll; break; 711781a868fSWei Yang case 2: bcomp = OpalPciBus7Bits; break; 712781a868fSWei Yang case 4: bcomp = OpalPciBus6Bits; break; 713781a868fSWei Yang case 8: bcomp = OpalPciBus5Bits; break; 714781a868fSWei Yang case 16: bcomp = OpalPciBus4Bits; break; 715781a868fSWei Yang case 32: bcomp = OpalPciBus3Bits; break; 716781a868fSWei Yang default: 717781a868fSWei Yang dev_err(&pe->pbus->dev, "Number of subordinate buses %d unsupported\n", 718781a868fSWei Yang count); 719781a868fSWei Yang /* Do an exact match only */ 720781a868fSWei Yang bcomp = OpalPciBusAll; 721781a868fSWei Yang } 722781a868fSWei Yang rid_end = pe->rid + (count << 8); 723781a868fSWei Yang } else { 724781a868fSWei Yang if (pe->flags & PNV_IODA_PE_VF) 725781a868fSWei Yang parent = pe->parent_dev; 726781a868fSWei Yang else 727781a868fSWei Yang parent = pe->pdev->bus->self; 728781a868fSWei Yang bcomp = OpalPciBusAll; 729781a868fSWei Yang dcomp = OPAL_COMPARE_RID_DEVICE_NUMBER; 730781a868fSWei Yang fcomp = OPAL_COMPARE_RID_FUNCTION_NUMBER; 731781a868fSWei Yang rid_end = pe->rid + 1; 732781a868fSWei Yang } 733781a868fSWei Yang 734781a868fSWei Yang /* Clear the reverse map */ 735781a868fSWei Yang for (rid = pe->rid; rid < rid_end; rid++) 736781a868fSWei Yang phb->ioda.pe_rmap[rid] = 0; 737781a868fSWei Yang 738781a868fSWei Yang /* Release from all parents PELT-V */ 739781a868fSWei Yang while (parent) { 740781a868fSWei Yang struct pci_dn *pdn = pci_get_pdn(parent); 741781a868fSWei Yang if (pdn && pdn->pe_number != IODA_INVALID_PE) { 742781a868fSWei Yang rc = opal_pci_set_peltv(phb->opal_id, pdn->pe_number, 743781a868fSWei Yang pe->pe_number, OPAL_REMOVE_PE_FROM_DOMAIN); 744781a868fSWei Yang /* XXX What to do in case of error ? */ 745781a868fSWei Yang } 746781a868fSWei Yang parent = parent->bus->self; 747781a868fSWei Yang } 748781a868fSWei Yang 749781a868fSWei Yang opal_pci_eeh_freeze_set(phb->opal_id, pe->pe_number, 750781a868fSWei Yang OPAL_EEH_ACTION_CLEAR_FREEZE_ALL); 751781a868fSWei Yang 752781a868fSWei Yang /* Disassociate PE in PELT */ 753781a868fSWei Yang rc = opal_pci_set_peltv(phb->opal_id, pe->pe_number, 754781a868fSWei Yang pe->pe_number, OPAL_REMOVE_PE_FROM_DOMAIN); 755781a868fSWei Yang if (rc) 756781a868fSWei Yang pe_warn(pe, "OPAL error %ld remove self from PELTV\n", rc); 757781a868fSWei Yang rc = opal_pci_set_pe(phb->opal_id, pe->pe_number, pe->rid, 758781a868fSWei Yang bcomp, dcomp, fcomp, OPAL_UNMAP_PE); 759781a868fSWei Yang if (rc) 760781a868fSWei Yang pe_err(pe, "OPAL error %ld trying to setup PELT table\n", rc); 761781a868fSWei Yang 762781a868fSWei Yang pe->pbus = NULL; 763781a868fSWei Yang pe->pdev = NULL; 764781a868fSWei Yang pe->parent_dev = NULL; 765781a868fSWei Yang 766781a868fSWei Yang return 0; 767781a868fSWei Yang } 768781a868fSWei Yang #endif /* CONFIG_PCI_IOV */ 769781a868fSWei Yang 770cad5cef6SGreg Kroah-Hartman static int pnv_ioda_configure_pe(struct pnv_phb *phb, struct pnv_ioda_pe *pe) 771184cd4a3SBenjamin Herrenschmidt { 772184cd4a3SBenjamin Herrenschmidt struct pci_dev *parent; 773184cd4a3SBenjamin Herrenschmidt uint8_t bcomp, dcomp, fcomp; 774184cd4a3SBenjamin Herrenschmidt long rc, rid_end, rid; 775184cd4a3SBenjamin Herrenschmidt 776184cd4a3SBenjamin Herrenschmidt /* Bus validation ? */ 777184cd4a3SBenjamin Herrenschmidt if (pe->pbus) { 778184cd4a3SBenjamin Herrenschmidt int count; 779184cd4a3SBenjamin Herrenschmidt 780184cd4a3SBenjamin Herrenschmidt dcomp = OPAL_IGNORE_RID_DEVICE_NUMBER; 781184cd4a3SBenjamin Herrenschmidt fcomp = OPAL_IGNORE_RID_FUNCTION_NUMBER; 782184cd4a3SBenjamin Herrenschmidt parent = pe->pbus->self; 783fb446ad0SGavin Shan if (pe->flags & PNV_IODA_PE_BUS_ALL) 784b918c62eSYinghai Lu count = pe->pbus->busn_res.end - pe->pbus->busn_res.start + 1; 785fb446ad0SGavin Shan else 786fb446ad0SGavin Shan count = 1; 787fb446ad0SGavin Shan 788184cd4a3SBenjamin Herrenschmidt switch(count) { 789184cd4a3SBenjamin Herrenschmidt case 1: bcomp = OpalPciBusAll; break; 790184cd4a3SBenjamin Herrenschmidt case 2: bcomp = OpalPciBus7Bits; break; 791184cd4a3SBenjamin Herrenschmidt case 4: bcomp = OpalPciBus6Bits; break; 792184cd4a3SBenjamin Herrenschmidt case 8: bcomp = OpalPciBus5Bits; break; 793184cd4a3SBenjamin Herrenschmidt case 16: bcomp = OpalPciBus4Bits; break; 794184cd4a3SBenjamin Herrenschmidt case 32: bcomp = OpalPciBus3Bits; break; 795184cd4a3SBenjamin Herrenschmidt default: 796781a868fSWei Yang dev_err(&pe->pbus->dev, "Number of subordinate buses %d unsupported\n", 797781a868fSWei Yang count); 798184cd4a3SBenjamin Herrenschmidt /* Do an exact match only */ 799184cd4a3SBenjamin Herrenschmidt bcomp = OpalPciBusAll; 800184cd4a3SBenjamin Herrenschmidt } 801184cd4a3SBenjamin Herrenschmidt rid_end = pe->rid + (count << 8); 802184cd4a3SBenjamin Herrenschmidt } else { 803781a868fSWei Yang #ifdef CONFIG_PCI_IOV 804781a868fSWei Yang if (pe->flags & PNV_IODA_PE_VF) 805781a868fSWei Yang parent = pe->parent_dev; 806781a868fSWei Yang else 807781a868fSWei Yang #endif /* CONFIG_PCI_IOV */ 808184cd4a3SBenjamin Herrenschmidt parent = pe->pdev->bus->self; 809184cd4a3SBenjamin Herrenschmidt bcomp = OpalPciBusAll; 810184cd4a3SBenjamin Herrenschmidt dcomp = OPAL_COMPARE_RID_DEVICE_NUMBER; 811184cd4a3SBenjamin Herrenschmidt fcomp = OPAL_COMPARE_RID_FUNCTION_NUMBER; 812184cd4a3SBenjamin Herrenschmidt rid_end = pe->rid + 1; 813184cd4a3SBenjamin Herrenschmidt } 814184cd4a3SBenjamin Herrenschmidt 815631ad691SGavin Shan /* 816631ad691SGavin Shan * Associate PE in PELT. We need add the PE into the 817631ad691SGavin Shan * corresponding PELT-V as well. Otherwise, the error 818631ad691SGavin Shan * originated from the PE might contribute to other 819631ad691SGavin Shan * PEs. 820631ad691SGavin Shan */ 821184cd4a3SBenjamin Herrenschmidt rc = opal_pci_set_pe(phb->opal_id, pe->pe_number, pe->rid, 822184cd4a3SBenjamin Herrenschmidt bcomp, dcomp, fcomp, OPAL_MAP_PE); 823184cd4a3SBenjamin Herrenschmidt if (rc) { 824184cd4a3SBenjamin Herrenschmidt pe_err(pe, "OPAL error %ld trying to setup PELT table\n", rc); 825184cd4a3SBenjamin Herrenschmidt return -ENXIO; 826184cd4a3SBenjamin Herrenschmidt } 827631ad691SGavin Shan 828b131a842SGavin Shan /* Configure PELTV */ 829b131a842SGavin Shan pnv_ioda_set_peltv(phb, pe, true); 830184cd4a3SBenjamin Herrenschmidt 831184cd4a3SBenjamin Herrenschmidt /* Setup reverse map */ 832184cd4a3SBenjamin Herrenschmidt for (rid = pe->rid; rid < rid_end; rid++) 833184cd4a3SBenjamin Herrenschmidt phb->ioda.pe_rmap[rid] = pe->pe_number; 834184cd4a3SBenjamin Herrenschmidt 835184cd4a3SBenjamin Herrenschmidt /* Setup one MVTs on IODA1 */ 8364773f76bSGavin Shan if (phb->type != PNV_PHB_IODA1) { 8374773f76bSGavin Shan pe->mve_number = 0; 8384773f76bSGavin Shan goto out; 8394773f76bSGavin Shan } 8404773f76bSGavin Shan 841184cd4a3SBenjamin Herrenschmidt pe->mve_number = pe->pe_number; 8424773f76bSGavin Shan rc = opal_pci_set_mve(phb->opal_id, pe->mve_number, pe->pe_number); 8434773f76bSGavin Shan if (rc != OPAL_SUCCESS) { 844184cd4a3SBenjamin Herrenschmidt pe_err(pe, "OPAL error %ld setting up MVE %d\n", 845184cd4a3SBenjamin Herrenschmidt rc, pe->mve_number); 846184cd4a3SBenjamin Herrenschmidt pe->mve_number = -1; 847184cd4a3SBenjamin Herrenschmidt } else { 848184cd4a3SBenjamin Herrenschmidt rc = opal_pci_set_mve_enable(phb->opal_id, 849cee72d5bSBenjamin Herrenschmidt pe->mve_number, OPAL_ENABLE_MVE); 850184cd4a3SBenjamin Herrenschmidt if (rc) { 851184cd4a3SBenjamin Herrenschmidt pe_err(pe, "OPAL error %ld enabling MVE %d\n", 852184cd4a3SBenjamin Herrenschmidt rc, pe->mve_number); 853184cd4a3SBenjamin Herrenschmidt pe->mve_number = -1; 854184cd4a3SBenjamin Herrenschmidt } 855184cd4a3SBenjamin Herrenschmidt } 856184cd4a3SBenjamin Herrenschmidt 8574773f76bSGavin Shan out: 858184cd4a3SBenjamin Herrenschmidt return 0; 859184cd4a3SBenjamin Herrenschmidt } 860184cd4a3SBenjamin Herrenschmidt 861cad5cef6SGreg Kroah-Hartman static void pnv_ioda_link_pe_by_weight(struct pnv_phb *phb, 862184cd4a3SBenjamin Herrenschmidt struct pnv_ioda_pe *pe) 863184cd4a3SBenjamin Herrenschmidt { 864184cd4a3SBenjamin Herrenschmidt struct pnv_ioda_pe *lpe; 865184cd4a3SBenjamin Herrenschmidt 8667ebdf956SGavin Shan list_for_each_entry(lpe, &phb->ioda.pe_dma_list, dma_link) { 867184cd4a3SBenjamin Herrenschmidt if (lpe->dma_weight < pe->dma_weight) { 8687ebdf956SGavin Shan list_add_tail(&pe->dma_link, &lpe->dma_link); 869184cd4a3SBenjamin Herrenschmidt return; 870184cd4a3SBenjamin Herrenschmidt } 871184cd4a3SBenjamin Herrenschmidt } 8727ebdf956SGavin Shan list_add_tail(&pe->dma_link, &phb->ioda.pe_dma_list); 873184cd4a3SBenjamin Herrenschmidt } 874184cd4a3SBenjamin Herrenschmidt 875184cd4a3SBenjamin Herrenschmidt static unsigned int pnv_ioda_dma_weight(struct pci_dev *dev) 876184cd4a3SBenjamin Herrenschmidt { 877184cd4a3SBenjamin Herrenschmidt /* This is quite simplistic. The "base" weight of a device 878184cd4a3SBenjamin Herrenschmidt * is 10. 0 means no DMA is to be accounted for it. 879184cd4a3SBenjamin Herrenschmidt */ 880184cd4a3SBenjamin Herrenschmidt 881184cd4a3SBenjamin Herrenschmidt /* If it's a bridge, no DMA */ 882184cd4a3SBenjamin Herrenschmidt if (dev->hdr_type != PCI_HEADER_TYPE_NORMAL) 883184cd4a3SBenjamin Herrenschmidt return 0; 884184cd4a3SBenjamin Herrenschmidt 885184cd4a3SBenjamin Herrenschmidt /* Reduce the weight of slow USB controllers */ 886184cd4a3SBenjamin Herrenschmidt if (dev->class == PCI_CLASS_SERIAL_USB_UHCI || 887184cd4a3SBenjamin Herrenschmidt dev->class == PCI_CLASS_SERIAL_USB_OHCI || 888184cd4a3SBenjamin Herrenschmidt dev->class == PCI_CLASS_SERIAL_USB_EHCI) 889184cd4a3SBenjamin Herrenschmidt return 3; 890184cd4a3SBenjamin Herrenschmidt 891184cd4a3SBenjamin Herrenschmidt /* Increase the weight of RAID (includes Obsidian) */ 892184cd4a3SBenjamin Herrenschmidt if ((dev->class >> 8) == PCI_CLASS_STORAGE_RAID) 893184cd4a3SBenjamin Herrenschmidt return 15; 894184cd4a3SBenjamin Herrenschmidt 895184cd4a3SBenjamin Herrenschmidt /* Default */ 896184cd4a3SBenjamin Herrenschmidt return 10; 897184cd4a3SBenjamin Herrenschmidt } 898184cd4a3SBenjamin Herrenschmidt 899781a868fSWei Yang #ifdef CONFIG_PCI_IOV 900781a868fSWei Yang static int pnv_pci_vf_resource_shift(struct pci_dev *dev, int offset) 901781a868fSWei Yang { 902781a868fSWei Yang struct pci_dn *pdn = pci_get_pdn(dev); 903781a868fSWei Yang int i; 904781a868fSWei Yang struct resource *res, res2; 905781a868fSWei Yang resource_size_t size; 906781a868fSWei Yang u16 num_vfs; 907781a868fSWei Yang 908781a868fSWei Yang if (!dev->is_physfn) 909781a868fSWei Yang return -EINVAL; 910781a868fSWei Yang 911781a868fSWei Yang /* 912781a868fSWei Yang * "offset" is in VFs. The M64 windows are sized so that when they 913781a868fSWei Yang * are segmented, each segment is the same size as the IOV BAR. 914781a868fSWei Yang * Each segment is in a separate PE, and the high order bits of the 915781a868fSWei Yang * address are the PE number. Therefore, each VF's BAR is in a 916781a868fSWei Yang * separate PE, and changing the IOV BAR start address changes the 917781a868fSWei Yang * range of PEs the VFs are in. 918781a868fSWei Yang */ 919781a868fSWei Yang num_vfs = pdn->num_vfs; 920781a868fSWei Yang for (i = 0; i < PCI_SRIOV_NUM_BARS; i++) { 921781a868fSWei Yang res = &dev->resource[i + PCI_IOV_RESOURCES]; 922781a868fSWei Yang if (!res->flags || !res->parent) 923781a868fSWei Yang continue; 924781a868fSWei Yang 925781a868fSWei Yang if (!pnv_pci_is_mem_pref_64(res->flags)) 926781a868fSWei Yang continue; 927781a868fSWei Yang 928781a868fSWei Yang /* 929781a868fSWei Yang * The actual IOV BAR range is determined by the start address 930781a868fSWei Yang * and the actual size for num_vfs VFs BAR. This check is to 931781a868fSWei Yang * make sure that after shifting, the range will not overlap 932781a868fSWei Yang * with another device. 933781a868fSWei Yang */ 934781a868fSWei Yang size = pci_iov_resource_size(dev, i + PCI_IOV_RESOURCES); 935781a868fSWei Yang res2.flags = res->flags; 936781a868fSWei Yang res2.start = res->start + (size * offset); 937781a868fSWei Yang res2.end = res2.start + (size * num_vfs) - 1; 938781a868fSWei Yang 939781a868fSWei Yang if (res2.end > res->end) { 940781a868fSWei Yang dev_err(&dev->dev, "VF BAR%d: %pR would extend past %pR (trying to enable %d VFs shifted by %d)\n", 941781a868fSWei Yang i, &res2, res, num_vfs, offset); 942781a868fSWei Yang return -EBUSY; 943781a868fSWei Yang } 944781a868fSWei Yang } 945781a868fSWei Yang 946781a868fSWei Yang /* 947781a868fSWei Yang * After doing so, there would be a "hole" in the /proc/iomem when 948781a868fSWei Yang * offset is a positive value. It looks like the device return some 949781a868fSWei Yang * mmio back to the system, which actually no one could use it. 950781a868fSWei Yang */ 951781a868fSWei Yang for (i = 0; i < PCI_SRIOV_NUM_BARS; i++) { 952781a868fSWei Yang res = &dev->resource[i + PCI_IOV_RESOURCES]; 953781a868fSWei Yang if (!res->flags || !res->parent) 954781a868fSWei Yang continue; 955781a868fSWei Yang 956781a868fSWei Yang if (!pnv_pci_is_mem_pref_64(res->flags)) 957781a868fSWei Yang continue; 958781a868fSWei Yang 959781a868fSWei Yang size = pci_iov_resource_size(dev, i + PCI_IOV_RESOURCES); 960781a868fSWei Yang res2 = *res; 961781a868fSWei Yang res->start += size * offset; 962781a868fSWei Yang 963781a868fSWei Yang dev_info(&dev->dev, "VF BAR%d: %pR shifted to %pR (enabling %d VFs shifted by %d)\n", 964781a868fSWei Yang i, &res2, res, num_vfs, offset); 965781a868fSWei Yang pci_update_resource(dev, i + PCI_IOV_RESOURCES); 966781a868fSWei Yang } 967781a868fSWei Yang return 0; 968781a868fSWei Yang } 969781a868fSWei Yang #endif /* CONFIG_PCI_IOV */ 970781a868fSWei Yang 971fb446ad0SGavin Shan #if 0 972cad5cef6SGreg Kroah-Hartman static struct pnv_ioda_pe *pnv_ioda_setup_dev_PE(struct pci_dev *dev) 973184cd4a3SBenjamin Herrenschmidt { 974184cd4a3SBenjamin Herrenschmidt struct pci_controller *hose = pci_bus_to_host(dev->bus); 975184cd4a3SBenjamin Herrenschmidt struct pnv_phb *phb = hose->private_data; 976b72c1f65SBenjamin Herrenschmidt struct pci_dn *pdn = pci_get_pdn(dev); 977184cd4a3SBenjamin Herrenschmidt struct pnv_ioda_pe *pe; 978184cd4a3SBenjamin Herrenschmidt int pe_num; 979184cd4a3SBenjamin Herrenschmidt 980184cd4a3SBenjamin Herrenschmidt if (!pdn) { 981184cd4a3SBenjamin Herrenschmidt pr_err("%s: Device tree node not associated properly\n", 982184cd4a3SBenjamin Herrenschmidt pci_name(dev)); 983184cd4a3SBenjamin Herrenschmidt return NULL; 984184cd4a3SBenjamin Herrenschmidt } 985184cd4a3SBenjamin Herrenschmidt if (pdn->pe_number != IODA_INVALID_PE) 986184cd4a3SBenjamin Herrenschmidt return NULL; 987184cd4a3SBenjamin Herrenschmidt 988184cd4a3SBenjamin Herrenschmidt /* PE#0 has been pre-set */ 989184cd4a3SBenjamin Herrenschmidt if (dev->bus->number == 0) 990184cd4a3SBenjamin Herrenschmidt pe_num = 0; 991184cd4a3SBenjamin Herrenschmidt else 992184cd4a3SBenjamin Herrenschmidt pe_num = pnv_ioda_alloc_pe(phb); 993184cd4a3SBenjamin Herrenschmidt if (pe_num == IODA_INVALID_PE) { 994184cd4a3SBenjamin Herrenschmidt pr_warning("%s: Not enough PE# available, disabling device\n", 995184cd4a3SBenjamin Herrenschmidt pci_name(dev)); 996184cd4a3SBenjamin Herrenschmidt return NULL; 997184cd4a3SBenjamin Herrenschmidt } 998184cd4a3SBenjamin Herrenschmidt 999184cd4a3SBenjamin Herrenschmidt /* NOTE: We get only one ref to the pci_dev for the pdn, not for the 1000184cd4a3SBenjamin Herrenschmidt * pointer in the PE data structure, both should be destroyed at the 1001184cd4a3SBenjamin Herrenschmidt * same time. However, this needs to be looked at more closely again 1002184cd4a3SBenjamin Herrenschmidt * once we actually start removing things (Hotplug, SR-IOV, ...) 1003184cd4a3SBenjamin Herrenschmidt * 1004184cd4a3SBenjamin Herrenschmidt * At some point we want to remove the PDN completely anyways 1005184cd4a3SBenjamin Herrenschmidt */ 1006184cd4a3SBenjamin Herrenschmidt pe = &phb->ioda.pe_array[pe_num]; 1007184cd4a3SBenjamin Herrenschmidt pci_dev_get(dev); 1008184cd4a3SBenjamin Herrenschmidt pdn->pcidev = dev; 1009184cd4a3SBenjamin Herrenschmidt pdn->pe_number = pe_num; 1010184cd4a3SBenjamin Herrenschmidt pe->pdev = dev; 1011184cd4a3SBenjamin Herrenschmidt pe->pbus = NULL; 1012184cd4a3SBenjamin Herrenschmidt pe->tce32_seg = -1; 1013184cd4a3SBenjamin Herrenschmidt pe->mve_number = -1; 1014184cd4a3SBenjamin Herrenschmidt pe->rid = dev->bus->number << 8 | pdn->devfn; 1015184cd4a3SBenjamin Herrenschmidt 1016184cd4a3SBenjamin Herrenschmidt pe_info(pe, "Associated device to PE\n"); 1017184cd4a3SBenjamin Herrenschmidt 1018184cd4a3SBenjamin Herrenschmidt if (pnv_ioda_configure_pe(phb, pe)) { 1019184cd4a3SBenjamin Herrenschmidt /* XXX What do we do here ? */ 1020184cd4a3SBenjamin Herrenschmidt if (pe_num) 1021184cd4a3SBenjamin Herrenschmidt pnv_ioda_free_pe(phb, pe_num); 1022184cd4a3SBenjamin Herrenschmidt pdn->pe_number = IODA_INVALID_PE; 1023184cd4a3SBenjamin Herrenschmidt pe->pdev = NULL; 1024184cd4a3SBenjamin Herrenschmidt pci_dev_put(dev); 1025184cd4a3SBenjamin Herrenschmidt return NULL; 1026184cd4a3SBenjamin Herrenschmidt } 1027184cd4a3SBenjamin Herrenschmidt 1028184cd4a3SBenjamin Herrenschmidt /* Assign a DMA weight to the device */ 1029184cd4a3SBenjamin Herrenschmidt pe->dma_weight = pnv_ioda_dma_weight(dev); 1030184cd4a3SBenjamin Herrenschmidt if (pe->dma_weight != 0) { 1031184cd4a3SBenjamin Herrenschmidt phb->ioda.dma_weight += pe->dma_weight; 1032184cd4a3SBenjamin Herrenschmidt phb->ioda.dma_pe_count++; 1033184cd4a3SBenjamin Herrenschmidt } 1034184cd4a3SBenjamin Herrenschmidt 1035184cd4a3SBenjamin Herrenschmidt /* Link the PE */ 1036184cd4a3SBenjamin Herrenschmidt pnv_ioda_link_pe_by_weight(phb, pe); 1037184cd4a3SBenjamin Herrenschmidt 1038184cd4a3SBenjamin Herrenschmidt return pe; 1039184cd4a3SBenjamin Herrenschmidt } 1040fb446ad0SGavin Shan #endif /* Useful for SRIOV case */ 1041184cd4a3SBenjamin Herrenschmidt 1042184cd4a3SBenjamin Herrenschmidt static void pnv_ioda_setup_same_PE(struct pci_bus *bus, struct pnv_ioda_pe *pe) 1043184cd4a3SBenjamin Herrenschmidt { 1044184cd4a3SBenjamin Herrenschmidt struct pci_dev *dev; 1045184cd4a3SBenjamin Herrenschmidt 1046184cd4a3SBenjamin Herrenschmidt list_for_each_entry(dev, &bus->devices, bus_list) { 1047b72c1f65SBenjamin Herrenschmidt struct pci_dn *pdn = pci_get_pdn(dev); 1048184cd4a3SBenjamin Herrenschmidt 1049184cd4a3SBenjamin Herrenschmidt if (pdn == NULL) { 1050184cd4a3SBenjamin Herrenschmidt pr_warn("%s: No device node associated with device !\n", 1051184cd4a3SBenjamin Herrenschmidt pci_name(dev)); 1052184cd4a3SBenjamin Herrenschmidt continue; 1053184cd4a3SBenjamin Herrenschmidt } 1054184cd4a3SBenjamin Herrenschmidt pdn->pe_number = pe->pe_number; 1055184cd4a3SBenjamin Herrenschmidt pe->dma_weight += pnv_ioda_dma_weight(dev); 1056fb446ad0SGavin Shan if ((pe->flags & PNV_IODA_PE_BUS_ALL) && dev->subordinate) 1057184cd4a3SBenjamin Herrenschmidt pnv_ioda_setup_same_PE(dev->subordinate, pe); 1058184cd4a3SBenjamin Herrenschmidt } 1059184cd4a3SBenjamin Herrenschmidt } 1060184cd4a3SBenjamin Herrenschmidt 1061fb446ad0SGavin Shan /* 1062fb446ad0SGavin Shan * There're 2 types of PCI bus sensitive PEs: One that is compromised of 1063fb446ad0SGavin Shan * single PCI bus. Another one that contains the primary PCI bus and its 1064fb446ad0SGavin Shan * subordinate PCI devices and buses. The second type of PE is normally 1065fb446ad0SGavin Shan * orgiriated by PCIe-to-PCI bridge or PLX switch downstream ports. 1066fb446ad0SGavin Shan */ 1067cad5cef6SGreg Kroah-Hartman static void pnv_ioda_setup_bus_PE(struct pci_bus *bus, int all) 1068184cd4a3SBenjamin Herrenschmidt { 1069fb446ad0SGavin Shan struct pci_controller *hose = pci_bus_to_host(bus); 1070184cd4a3SBenjamin Herrenschmidt struct pnv_phb *phb = hose->private_data; 1071184cd4a3SBenjamin Herrenschmidt struct pnv_ioda_pe *pe; 1072262af557SGuo Chao int pe_num = IODA_INVALID_PE; 1073184cd4a3SBenjamin Herrenschmidt 1074262af557SGuo Chao /* Check if PE is determined by M64 */ 1075262af557SGuo Chao if (phb->pick_m64_pe) 1076262af557SGuo Chao pe_num = phb->pick_m64_pe(phb, bus, all); 1077262af557SGuo Chao 1078262af557SGuo Chao /* The PE number isn't pinned by M64 */ 1079262af557SGuo Chao if (pe_num == IODA_INVALID_PE) 1080184cd4a3SBenjamin Herrenschmidt pe_num = pnv_ioda_alloc_pe(phb); 1081262af557SGuo Chao 1082184cd4a3SBenjamin Herrenschmidt if (pe_num == IODA_INVALID_PE) { 1083fb446ad0SGavin Shan pr_warning("%s: Not enough PE# available for PCI bus %04x:%02x\n", 1084fb446ad0SGavin Shan __func__, pci_domain_nr(bus), bus->number); 1085184cd4a3SBenjamin Herrenschmidt return; 1086184cd4a3SBenjamin Herrenschmidt } 1087184cd4a3SBenjamin Herrenschmidt 1088184cd4a3SBenjamin Herrenschmidt pe = &phb->ioda.pe_array[pe_num]; 1089262af557SGuo Chao pe->flags |= (all ? PNV_IODA_PE_BUS_ALL : PNV_IODA_PE_BUS); 1090184cd4a3SBenjamin Herrenschmidt pe->pbus = bus; 1091184cd4a3SBenjamin Herrenschmidt pe->pdev = NULL; 1092184cd4a3SBenjamin Herrenschmidt pe->tce32_seg = -1; 1093184cd4a3SBenjamin Herrenschmidt pe->mve_number = -1; 1094b918c62eSYinghai Lu pe->rid = bus->busn_res.start << 8; 1095184cd4a3SBenjamin Herrenschmidt pe->dma_weight = 0; 1096184cd4a3SBenjamin Herrenschmidt 1097fb446ad0SGavin Shan if (all) 1098fb446ad0SGavin Shan pe_info(pe, "Secondary bus %d..%d associated with PE#%d\n", 1099fb446ad0SGavin Shan bus->busn_res.start, bus->busn_res.end, pe_num); 1100fb446ad0SGavin Shan else 1101fb446ad0SGavin Shan pe_info(pe, "Secondary bus %d associated with PE#%d\n", 1102fb446ad0SGavin Shan bus->busn_res.start, pe_num); 1103184cd4a3SBenjamin Herrenschmidt 1104184cd4a3SBenjamin Herrenschmidt if (pnv_ioda_configure_pe(phb, pe)) { 1105184cd4a3SBenjamin Herrenschmidt /* XXX What do we do here ? */ 1106184cd4a3SBenjamin Herrenschmidt if (pe_num) 1107184cd4a3SBenjamin Herrenschmidt pnv_ioda_free_pe(phb, pe_num); 1108184cd4a3SBenjamin Herrenschmidt pe->pbus = NULL; 1109184cd4a3SBenjamin Herrenschmidt return; 1110184cd4a3SBenjamin Herrenschmidt } 1111184cd4a3SBenjamin Herrenschmidt 1112184cd4a3SBenjamin Herrenschmidt /* Associate it with all child devices */ 1113184cd4a3SBenjamin Herrenschmidt pnv_ioda_setup_same_PE(bus, pe); 1114184cd4a3SBenjamin Herrenschmidt 11157ebdf956SGavin Shan /* Put PE to the list */ 11167ebdf956SGavin Shan list_add_tail(&pe->list, &phb->ioda.pe_list); 11177ebdf956SGavin Shan 1118184cd4a3SBenjamin Herrenschmidt /* Account for one DMA PE if at least one DMA capable device exist 1119184cd4a3SBenjamin Herrenschmidt * below the bridge 1120184cd4a3SBenjamin Herrenschmidt */ 1121184cd4a3SBenjamin Herrenschmidt if (pe->dma_weight != 0) { 1122184cd4a3SBenjamin Herrenschmidt phb->ioda.dma_weight += pe->dma_weight; 1123184cd4a3SBenjamin Herrenschmidt phb->ioda.dma_pe_count++; 1124184cd4a3SBenjamin Herrenschmidt } 1125184cd4a3SBenjamin Herrenschmidt 1126184cd4a3SBenjamin Herrenschmidt /* Link the PE */ 1127184cd4a3SBenjamin Herrenschmidt pnv_ioda_link_pe_by_weight(phb, pe); 1128184cd4a3SBenjamin Herrenschmidt } 1129184cd4a3SBenjamin Herrenschmidt 1130cad5cef6SGreg Kroah-Hartman static void pnv_ioda_setup_PEs(struct pci_bus *bus) 1131184cd4a3SBenjamin Herrenschmidt { 1132184cd4a3SBenjamin Herrenschmidt struct pci_dev *dev; 1133fb446ad0SGavin Shan 1134fb446ad0SGavin Shan pnv_ioda_setup_bus_PE(bus, 0); 1135184cd4a3SBenjamin Herrenschmidt 1136184cd4a3SBenjamin Herrenschmidt list_for_each_entry(dev, &bus->devices, bus_list) { 1137fb446ad0SGavin Shan if (dev->subordinate) { 113862f87c0eSYijing Wang if (pci_pcie_type(dev) == PCI_EXP_TYPE_PCI_BRIDGE) 1139fb446ad0SGavin Shan pnv_ioda_setup_bus_PE(dev->subordinate, 1); 1140fb446ad0SGavin Shan else 1141184cd4a3SBenjamin Herrenschmidt pnv_ioda_setup_PEs(dev->subordinate); 1142184cd4a3SBenjamin Herrenschmidt } 1143184cd4a3SBenjamin Herrenschmidt } 1144fb446ad0SGavin Shan } 1145fb446ad0SGavin Shan 1146fb446ad0SGavin Shan /* 1147fb446ad0SGavin Shan * Configure PEs so that the downstream PCI buses and devices 1148fb446ad0SGavin Shan * could have their associated PE#. Unfortunately, we didn't 1149fb446ad0SGavin Shan * figure out the way to identify the PLX bridge yet. So we 1150fb446ad0SGavin Shan * simply put the PCI bus and the subordinate behind the root 1151fb446ad0SGavin Shan * port to PE# here. The game rule here is expected to be changed 1152fb446ad0SGavin Shan * as soon as we can detected PLX bridge correctly. 1153fb446ad0SGavin Shan */ 1154cad5cef6SGreg Kroah-Hartman static void pnv_pci_ioda_setup_PEs(void) 1155fb446ad0SGavin Shan { 1156fb446ad0SGavin Shan struct pci_controller *hose, *tmp; 1157262af557SGuo Chao struct pnv_phb *phb; 1158fb446ad0SGavin Shan 1159fb446ad0SGavin Shan list_for_each_entry_safe(hose, tmp, &hose_list, list_node) { 1160262af557SGuo Chao phb = hose->private_data; 1161262af557SGuo Chao 1162262af557SGuo Chao /* M64 layout might affect PE allocation */ 11635ef73567SGavin Shan if (phb->reserve_m64_pe) 116496a2f92bSGavin Shan phb->reserve_m64_pe(hose->bus, NULL, true); 1165262af557SGuo Chao 1166fb446ad0SGavin Shan pnv_ioda_setup_PEs(hose->bus); 1167fb446ad0SGavin Shan } 1168fb446ad0SGavin Shan } 1169184cd4a3SBenjamin Herrenschmidt 1170a8b2f828SGavin Shan #ifdef CONFIG_PCI_IOV 1171781a868fSWei Yang static int pnv_pci_vf_release_m64(struct pci_dev *pdev) 1172781a868fSWei Yang { 1173781a868fSWei Yang struct pci_bus *bus; 1174781a868fSWei Yang struct pci_controller *hose; 1175781a868fSWei Yang struct pnv_phb *phb; 1176781a868fSWei Yang struct pci_dn *pdn; 117702639b0eSWei Yang int i, j; 1178781a868fSWei Yang 1179781a868fSWei Yang bus = pdev->bus; 1180781a868fSWei Yang hose = pci_bus_to_host(bus); 1181781a868fSWei Yang phb = hose->private_data; 1182781a868fSWei Yang pdn = pci_get_pdn(pdev); 1183781a868fSWei Yang 118402639b0eSWei Yang for (i = 0; i < PCI_SRIOV_NUM_BARS; i++) 118502639b0eSWei Yang for (j = 0; j < M64_PER_IOV; j++) { 118602639b0eSWei Yang if (pdn->m64_wins[i][j] == IODA_INVALID_M64) 1187781a868fSWei Yang continue; 1188781a868fSWei Yang opal_pci_phb_mmio_enable(phb->opal_id, 118902639b0eSWei Yang OPAL_M64_WINDOW_TYPE, pdn->m64_wins[i][j], 0); 119002639b0eSWei Yang clear_bit(pdn->m64_wins[i][j], &phb->ioda.m64_bar_alloc); 119102639b0eSWei Yang pdn->m64_wins[i][j] = IODA_INVALID_M64; 1192781a868fSWei Yang } 1193781a868fSWei Yang 1194781a868fSWei Yang return 0; 1195781a868fSWei Yang } 1196781a868fSWei Yang 119702639b0eSWei Yang static int pnv_pci_vf_assign_m64(struct pci_dev *pdev, u16 num_vfs) 1198781a868fSWei Yang { 1199781a868fSWei Yang struct pci_bus *bus; 1200781a868fSWei Yang struct pci_controller *hose; 1201781a868fSWei Yang struct pnv_phb *phb; 1202781a868fSWei Yang struct pci_dn *pdn; 1203781a868fSWei Yang unsigned int win; 1204781a868fSWei Yang struct resource *res; 120502639b0eSWei Yang int i, j; 1206781a868fSWei Yang int64_t rc; 120702639b0eSWei Yang int total_vfs; 120802639b0eSWei Yang resource_size_t size, start; 120902639b0eSWei Yang int pe_num; 121002639b0eSWei Yang int vf_groups; 121102639b0eSWei Yang int vf_per_group; 1212781a868fSWei Yang 1213781a868fSWei Yang bus = pdev->bus; 1214781a868fSWei Yang hose = pci_bus_to_host(bus); 1215781a868fSWei Yang phb = hose->private_data; 1216781a868fSWei Yang pdn = pci_get_pdn(pdev); 121702639b0eSWei Yang total_vfs = pci_sriov_get_totalvfs(pdev); 1218781a868fSWei Yang 1219781a868fSWei Yang /* Initialize the m64_wins to IODA_INVALID_M64 */ 1220781a868fSWei Yang for (i = 0; i < PCI_SRIOV_NUM_BARS; i++) 122102639b0eSWei Yang for (j = 0; j < M64_PER_IOV; j++) 122202639b0eSWei Yang pdn->m64_wins[i][j] = IODA_INVALID_M64; 122302639b0eSWei Yang 122402639b0eSWei Yang if (pdn->m64_per_iov == M64_PER_IOV) { 122502639b0eSWei Yang vf_groups = (num_vfs <= M64_PER_IOV) ? num_vfs: M64_PER_IOV; 122602639b0eSWei Yang vf_per_group = (num_vfs <= M64_PER_IOV)? 1: 122702639b0eSWei Yang roundup_pow_of_two(num_vfs) / pdn->m64_per_iov; 122802639b0eSWei Yang } else { 122902639b0eSWei Yang vf_groups = 1; 123002639b0eSWei Yang vf_per_group = 1; 123102639b0eSWei Yang } 1232781a868fSWei Yang 1233781a868fSWei Yang for (i = 0; i < PCI_SRIOV_NUM_BARS; i++) { 1234781a868fSWei Yang res = &pdev->resource[i + PCI_IOV_RESOURCES]; 1235781a868fSWei Yang if (!res->flags || !res->parent) 1236781a868fSWei Yang continue; 1237781a868fSWei Yang 1238781a868fSWei Yang if (!pnv_pci_is_mem_pref_64(res->flags)) 1239781a868fSWei Yang continue; 1240781a868fSWei Yang 124102639b0eSWei Yang for (j = 0; j < vf_groups; j++) { 1242781a868fSWei Yang do { 1243781a868fSWei Yang win = find_next_zero_bit(&phb->ioda.m64_bar_alloc, 1244781a868fSWei Yang phb->ioda.m64_bar_idx + 1, 0); 1245781a868fSWei Yang 1246781a868fSWei Yang if (win >= phb->ioda.m64_bar_idx + 1) 1247781a868fSWei Yang goto m64_failed; 1248781a868fSWei Yang } while (test_and_set_bit(win, &phb->ioda.m64_bar_alloc)); 1249781a868fSWei Yang 125002639b0eSWei Yang pdn->m64_wins[i][j] = win; 125102639b0eSWei Yang 125202639b0eSWei Yang if (pdn->m64_per_iov == M64_PER_IOV) { 125302639b0eSWei Yang size = pci_iov_resource_size(pdev, 125402639b0eSWei Yang PCI_IOV_RESOURCES + i); 125502639b0eSWei Yang size = size * vf_per_group; 125602639b0eSWei Yang start = res->start + size * j; 125702639b0eSWei Yang } else { 125802639b0eSWei Yang size = resource_size(res); 125902639b0eSWei Yang start = res->start; 126002639b0eSWei Yang } 1261781a868fSWei Yang 1262781a868fSWei Yang /* Map the M64 here */ 126302639b0eSWei Yang if (pdn->m64_per_iov == M64_PER_IOV) { 126402639b0eSWei Yang pe_num = pdn->offset + j; 126502639b0eSWei Yang rc = opal_pci_map_pe_mmio_window(phb->opal_id, 126602639b0eSWei Yang pe_num, OPAL_M64_WINDOW_TYPE, 126702639b0eSWei Yang pdn->m64_wins[i][j], 0); 126802639b0eSWei Yang } 126902639b0eSWei Yang 1270781a868fSWei Yang rc = opal_pci_set_phb_mem_window(phb->opal_id, 1271781a868fSWei Yang OPAL_M64_WINDOW_TYPE, 127202639b0eSWei Yang pdn->m64_wins[i][j], 127302639b0eSWei Yang start, 1274781a868fSWei Yang 0, /* unused */ 127502639b0eSWei Yang size); 127602639b0eSWei Yang 127702639b0eSWei Yang 1278781a868fSWei Yang if (rc != OPAL_SUCCESS) { 1279781a868fSWei Yang dev_err(&pdev->dev, "Failed to map M64 window #%d: %lld\n", 1280781a868fSWei Yang win, rc); 1281781a868fSWei Yang goto m64_failed; 1282781a868fSWei Yang } 1283781a868fSWei Yang 128402639b0eSWei Yang if (pdn->m64_per_iov == M64_PER_IOV) 1285781a868fSWei Yang rc = opal_pci_phb_mmio_enable(phb->opal_id, 128602639b0eSWei Yang OPAL_M64_WINDOW_TYPE, pdn->m64_wins[i][j], 2); 128702639b0eSWei Yang else 128802639b0eSWei Yang rc = opal_pci_phb_mmio_enable(phb->opal_id, 128902639b0eSWei Yang OPAL_M64_WINDOW_TYPE, pdn->m64_wins[i][j], 1); 129002639b0eSWei Yang 1291781a868fSWei Yang if (rc != OPAL_SUCCESS) { 1292781a868fSWei Yang dev_err(&pdev->dev, "Failed to enable M64 window #%d: %llx\n", 1293781a868fSWei Yang win, rc); 1294781a868fSWei Yang goto m64_failed; 1295781a868fSWei Yang } 1296781a868fSWei Yang } 129702639b0eSWei Yang } 1298781a868fSWei Yang return 0; 1299781a868fSWei Yang 1300781a868fSWei Yang m64_failed: 1301781a868fSWei Yang pnv_pci_vf_release_m64(pdev); 1302781a868fSWei Yang return -EBUSY; 1303781a868fSWei Yang } 1304781a868fSWei Yang 1305c035e37bSAlexey Kardashevskiy static long pnv_pci_ioda2_unset_window(struct iommu_table_group *table_group, 1306c035e37bSAlexey Kardashevskiy int num); 1307c035e37bSAlexey Kardashevskiy static void pnv_pci_ioda2_set_bypass(struct pnv_ioda_pe *pe, bool enable); 1308c035e37bSAlexey Kardashevskiy 1309781a868fSWei Yang static void pnv_pci_ioda2_release_dma_pe(struct pci_dev *dev, struct pnv_ioda_pe *pe) 1310781a868fSWei Yang { 1311781a868fSWei Yang struct iommu_table *tbl; 1312781a868fSWei Yang int64_t rc; 1313781a868fSWei Yang 1314b348aa65SAlexey Kardashevskiy tbl = pe->table_group.tables[0]; 1315c035e37bSAlexey Kardashevskiy rc = pnv_pci_ioda2_unset_window(&pe->table_group, 0); 1316781a868fSWei Yang if (rc) 1317781a868fSWei Yang pe_warn(pe, "OPAL error %ld release DMA window\n", rc); 1318781a868fSWei Yang 1319c035e37bSAlexey Kardashevskiy pnv_pci_ioda2_set_bypass(pe, false); 13200eaf4defSAlexey Kardashevskiy if (pe->table_group.group) { 13210eaf4defSAlexey Kardashevskiy iommu_group_put(pe->table_group.group); 13220eaf4defSAlexey Kardashevskiy BUG_ON(pe->table_group.group); 1323ac9a5889SAlexey Kardashevskiy } 1324aca6913fSAlexey Kardashevskiy pnv_pci_ioda2_table_free_pages(tbl); 1325781a868fSWei Yang iommu_free_table(tbl, of_node_full_name(dev->dev.of_node)); 1326781a868fSWei Yang } 1327781a868fSWei Yang 132802639b0eSWei Yang static void pnv_ioda_release_vf_PE(struct pci_dev *pdev, u16 num_vfs) 1329781a868fSWei Yang { 1330781a868fSWei Yang struct pci_bus *bus; 1331781a868fSWei Yang struct pci_controller *hose; 1332781a868fSWei Yang struct pnv_phb *phb; 1333781a868fSWei Yang struct pnv_ioda_pe *pe, *pe_n; 1334781a868fSWei Yang struct pci_dn *pdn; 133502639b0eSWei Yang u16 vf_index; 133602639b0eSWei Yang int64_t rc; 1337781a868fSWei Yang 1338781a868fSWei Yang bus = pdev->bus; 1339781a868fSWei Yang hose = pci_bus_to_host(bus); 1340781a868fSWei Yang phb = hose->private_data; 134102639b0eSWei Yang pdn = pci_get_pdn(pdev); 1342781a868fSWei Yang 1343781a868fSWei Yang if (!pdev->is_physfn) 1344781a868fSWei Yang return; 1345781a868fSWei Yang 134602639b0eSWei Yang if (pdn->m64_per_iov == M64_PER_IOV && num_vfs > M64_PER_IOV) { 134702639b0eSWei Yang int vf_group; 134802639b0eSWei Yang int vf_per_group; 134902639b0eSWei Yang int vf_index1; 135002639b0eSWei Yang 135102639b0eSWei Yang vf_per_group = roundup_pow_of_two(num_vfs) / pdn->m64_per_iov; 135202639b0eSWei Yang 135302639b0eSWei Yang for (vf_group = 0; vf_group < M64_PER_IOV; vf_group++) 135402639b0eSWei Yang for (vf_index = vf_group * vf_per_group; 135502639b0eSWei Yang vf_index < (vf_group + 1) * vf_per_group && 135602639b0eSWei Yang vf_index < num_vfs; 135702639b0eSWei Yang vf_index++) 135802639b0eSWei Yang for (vf_index1 = vf_group * vf_per_group; 135902639b0eSWei Yang vf_index1 < (vf_group + 1) * vf_per_group && 136002639b0eSWei Yang vf_index1 < num_vfs; 136102639b0eSWei Yang vf_index1++){ 136202639b0eSWei Yang 136302639b0eSWei Yang rc = opal_pci_set_peltv(phb->opal_id, 136402639b0eSWei Yang pdn->offset + vf_index, 136502639b0eSWei Yang pdn->offset + vf_index1, 136602639b0eSWei Yang OPAL_REMOVE_PE_FROM_DOMAIN); 136702639b0eSWei Yang 136802639b0eSWei Yang if (rc) 136902639b0eSWei Yang dev_warn(&pdev->dev, "%s: Failed to unlink same group PE#%d(%lld)\n", 137002639b0eSWei Yang __func__, 137102639b0eSWei Yang pdn->offset + vf_index1, rc); 137202639b0eSWei Yang } 137302639b0eSWei Yang } 137402639b0eSWei Yang 1375781a868fSWei Yang list_for_each_entry_safe(pe, pe_n, &phb->ioda.pe_list, list) { 1376781a868fSWei Yang if (pe->parent_dev != pdev) 1377781a868fSWei Yang continue; 1378781a868fSWei Yang 1379781a868fSWei Yang pnv_pci_ioda2_release_dma_pe(pdev, pe); 1380781a868fSWei Yang 1381781a868fSWei Yang /* Remove from list */ 1382781a868fSWei Yang mutex_lock(&phb->ioda.pe_list_mutex); 1383781a868fSWei Yang list_del(&pe->list); 1384781a868fSWei Yang mutex_unlock(&phb->ioda.pe_list_mutex); 1385781a868fSWei Yang 1386781a868fSWei Yang pnv_ioda_deconfigure_pe(phb, pe); 1387781a868fSWei Yang 1388781a868fSWei Yang pnv_ioda_free_pe(phb, pe->pe_number); 1389781a868fSWei Yang } 1390781a868fSWei Yang } 1391781a868fSWei Yang 1392781a868fSWei Yang void pnv_pci_sriov_disable(struct pci_dev *pdev) 1393781a868fSWei Yang { 1394781a868fSWei Yang struct pci_bus *bus; 1395781a868fSWei Yang struct pci_controller *hose; 1396781a868fSWei Yang struct pnv_phb *phb; 1397781a868fSWei Yang struct pci_dn *pdn; 1398781a868fSWei Yang struct pci_sriov *iov; 1399781a868fSWei Yang u16 num_vfs; 1400781a868fSWei Yang 1401781a868fSWei Yang bus = pdev->bus; 1402781a868fSWei Yang hose = pci_bus_to_host(bus); 1403781a868fSWei Yang phb = hose->private_data; 1404781a868fSWei Yang pdn = pci_get_pdn(pdev); 1405781a868fSWei Yang iov = pdev->sriov; 1406781a868fSWei Yang num_vfs = pdn->num_vfs; 1407781a868fSWei Yang 1408781a868fSWei Yang /* Release VF PEs */ 140902639b0eSWei Yang pnv_ioda_release_vf_PE(pdev, num_vfs); 1410781a868fSWei Yang 1411781a868fSWei Yang if (phb->type == PNV_PHB_IODA2) { 141202639b0eSWei Yang if (pdn->m64_per_iov == 1) 1413781a868fSWei Yang pnv_pci_vf_resource_shift(pdev, -pdn->offset); 1414781a868fSWei Yang 1415781a868fSWei Yang /* Release M64 windows */ 1416781a868fSWei Yang pnv_pci_vf_release_m64(pdev); 1417781a868fSWei Yang 1418781a868fSWei Yang /* Release PE numbers */ 1419781a868fSWei Yang bitmap_clear(phb->ioda.pe_alloc, pdn->offset, num_vfs); 1420781a868fSWei Yang pdn->offset = 0; 1421781a868fSWei Yang } 1422781a868fSWei Yang } 1423781a868fSWei Yang 1424781a868fSWei Yang static void pnv_pci_ioda2_setup_dma_pe(struct pnv_phb *phb, 1425781a868fSWei Yang struct pnv_ioda_pe *pe); 1426781a868fSWei Yang static void pnv_ioda_setup_vf_PE(struct pci_dev *pdev, u16 num_vfs) 1427781a868fSWei Yang { 1428781a868fSWei Yang struct pci_bus *bus; 1429781a868fSWei Yang struct pci_controller *hose; 1430781a868fSWei Yang struct pnv_phb *phb; 1431781a868fSWei Yang struct pnv_ioda_pe *pe; 1432781a868fSWei Yang int pe_num; 1433781a868fSWei Yang u16 vf_index; 1434781a868fSWei Yang struct pci_dn *pdn; 143502639b0eSWei Yang int64_t rc; 1436781a868fSWei Yang 1437781a868fSWei Yang bus = pdev->bus; 1438781a868fSWei Yang hose = pci_bus_to_host(bus); 1439781a868fSWei Yang phb = hose->private_data; 1440781a868fSWei Yang pdn = pci_get_pdn(pdev); 1441781a868fSWei Yang 1442781a868fSWei Yang if (!pdev->is_physfn) 1443781a868fSWei Yang return; 1444781a868fSWei Yang 1445781a868fSWei Yang /* Reserve PE for each VF */ 1446781a868fSWei Yang for (vf_index = 0; vf_index < num_vfs; vf_index++) { 1447781a868fSWei Yang pe_num = pdn->offset + vf_index; 1448781a868fSWei Yang 1449781a868fSWei Yang pe = &phb->ioda.pe_array[pe_num]; 1450781a868fSWei Yang pe->pe_number = pe_num; 1451781a868fSWei Yang pe->phb = phb; 1452781a868fSWei Yang pe->flags = PNV_IODA_PE_VF; 1453781a868fSWei Yang pe->pbus = NULL; 1454781a868fSWei Yang pe->parent_dev = pdev; 1455781a868fSWei Yang pe->tce32_seg = -1; 1456781a868fSWei Yang pe->mve_number = -1; 1457781a868fSWei Yang pe->rid = (pci_iov_virtfn_bus(pdev, vf_index) << 8) | 1458781a868fSWei Yang pci_iov_virtfn_devfn(pdev, vf_index); 1459781a868fSWei Yang 1460781a868fSWei Yang pe_info(pe, "VF %04d:%02d:%02d.%d associated with PE#%d\n", 1461781a868fSWei Yang hose->global_number, pdev->bus->number, 1462781a868fSWei Yang PCI_SLOT(pci_iov_virtfn_devfn(pdev, vf_index)), 1463781a868fSWei Yang PCI_FUNC(pci_iov_virtfn_devfn(pdev, vf_index)), pe_num); 1464781a868fSWei Yang 1465781a868fSWei Yang if (pnv_ioda_configure_pe(phb, pe)) { 1466781a868fSWei Yang /* XXX What do we do here ? */ 1467781a868fSWei Yang if (pe_num) 1468781a868fSWei Yang pnv_ioda_free_pe(phb, pe_num); 1469781a868fSWei Yang pe->pdev = NULL; 1470781a868fSWei Yang continue; 1471781a868fSWei Yang } 1472781a868fSWei Yang 1473781a868fSWei Yang /* Put PE to the list */ 1474781a868fSWei Yang mutex_lock(&phb->ioda.pe_list_mutex); 1475781a868fSWei Yang list_add_tail(&pe->list, &phb->ioda.pe_list); 1476781a868fSWei Yang mutex_unlock(&phb->ioda.pe_list_mutex); 1477781a868fSWei Yang 1478781a868fSWei Yang pnv_pci_ioda2_setup_dma_pe(phb, pe); 1479781a868fSWei Yang } 148002639b0eSWei Yang 148102639b0eSWei Yang if (pdn->m64_per_iov == M64_PER_IOV && num_vfs > M64_PER_IOV) { 148202639b0eSWei Yang int vf_group; 148302639b0eSWei Yang int vf_per_group; 148402639b0eSWei Yang int vf_index1; 148502639b0eSWei Yang 148602639b0eSWei Yang vf_per_group = roundup_pow_of_two(num_vfs) / pdn->m64_per_iov; 148702639b0eSWei Yang 148802639b0eSWei Yang for (vf_group = 0; vf_group < M64_PER_IOV; vf_group++) { 148902639b0eSWei Yang for (vf_index = vf_group * vf_per_group; 149002639b0eSWei Yang vf_index < (vf_group + 1) * vf_per_group && 149102639b0eSWei Yang vf_index < num_vfs; 149202639b0eSWei Yang vf_index++) { 149302639b0eSWei Yang for (vf_index1 = vf_group * vf_per_group; 149402639b0eSWei Yang vf_index1 < (vf_group + 1) * vf_per_group && 149502639b0eSWei Yang vf_index1 < num_vfs; 149602639b0eSWei Yang vf_index1++) { 149702639b0eSWei Yang 149802639b0eSWei Yang rc = opal_pci_set_peltv(phb->opal_id, 149902639b0eSWei Yang pdn->offset + vf_index, 150002639b0eSWei Yang pdn->offset + vf_index1, 150102639b0eSWei Yang OPAL_ADD_PE_TO_DOMAIN); 150202639b0eSWei Yang 150302639b0eSWei Yang if (rc) 150402639b0eSWei Yang dev_warn(&pdev->dev, "%s: Failed to link same group PE#%d(%lld)\n", 150502639b0eSWei Yang __func__, 150602639b0eSWei Yang pdn->offset + vf_index1, rc); 150702639b0eSWei Yang } 150802639b0eSWei Yang } 150902639b0eSWei Yang } 151002639b0eSWei Yang } 1511781a868fSWei Yang } 1512781a868fSWei Yang 1513781a868fSWei Yang int pnv_pci_sriov_enable(struct pci_dev *pdev, u16 num_vfs) 1514781a868fSWei Yang { 1515781a868fSWei Yang struct pci_bus *bus; 1516781a868fSWei Yang struct pci_controller *hose; 1517781a868fSWei Yang struct pnv_phb *phb; 1518781a868fSWei Yang struct pci_dn *pdn; 1519781a868fSWei Yang int ret; 1520781a868fSWei Yang 1521781a868fSWei Yang bus = pdev->bus; 1522781a868fSWei Yang hose = pci_bus_to_host(bus); 1523781a868fSWei Yang phb = hose->private_data; 1524781a868fSWei Yang pdn = pci_get_pdn(pdev); 1525781a868fSWei Yang 1526781a868fSWei Yang if (phb->type == PNV_PHB_IODA2) { 1527781a868fSWei Yang /* Calculate available PE for required VFs */ 1528781a868fSWei Yang mutex_lock(&phb->ioda.pe_alloc_mutex); 1529781a868fSWei Yang pdn->offset = bitmap_find_next_zero_area( 1530781a868fSWei Yang phb->ioda.pe_alloc, phb->ioda.total_pe, 1531781a868fSWei Yang 0, num_vfs, 0); 1532781a868fSWei Yang if (pdn->offset >= phb->ioda.total_pe) { 1533781a868fSWei Yang mutex_unlock(&phb->ioda.pe_alloc_mutex); 1534781a868fSWei Yang dev_info(&pdev->dev, "Failed to enable VF%d\n", num_vfs); 1535781a868fSWei Yang pdn->offset = 0; 1536781a868fSWei Yang return -EBUSY; 1537781a868fSWei Yang } 1538781a868fSWei Yang bitmap_set(phb->ioda.pe_alloc, pdn->offset, num_vfs); 1539781a868fSWei Yang pdn->num_vfs = num_vfs; 1540781a868fSWei Yang mutex_unlock(&phb->ioda.pe_alloc_mutex); 1541781a868fSWei Yang 1542781a868fSWei Yang /* Assign M64 window accordingly */ 154302639b0eSWei Yang ret = pnv_pci_vf_assign_m64(pdev, num_vfs); 1544781a868fSWei Yang if (ret) { 1545781a868fSWei Yang dev_info(&pdev->dev, "Not enough M64 window resources\n"); 1546781a868fSWei Yang goto m64_failed; 1547781a868fSWei Yang } 1548781a868fSWei Yang 1549781a868fSWei Yang /* 1550781a868fSWei Yang * When using one M64 BAR to map one IOV BAR, we need to shift 1551781a868fSWei Yang * the IOV BAR according to the PE# allocated to the VFs. 1552781a868fSWei Yang * Otherwise, the PE# for the VF will conflict with others. 1553781a868fSWei Yang */ 155402639b0eSWei Yang if (pdn->m64_per_iov == 1) { 1555781a868fSWei Yang ret = pnv_pci_vf_resource_shift(pdev, pdn->offset); 1556781a868fSWei Yang if (ret) 1557781a868fSWei Yang goto m64_failed; 1558781a868fSWei Yang } 155902639b0eSWei Yang } 1560781a868fSWei Yang 1561781a868fSWei Yang /* Setup VF PEs */ 1562781a868fSWei Yang pnv_ioda_setup_vf_PE(pdev, num_vfs); 1563781a868fSWei Yang 1564781a868fSWei Yang return 0; 1565781a868fSWei Yang 1566781a868fSWei Yang m64_failed: 1567781a868fSWei Yang bitmap_clear(phb->ioda.pe_alloc, pdn->offset, num_vfs); 1568781a868fSWei Yang pdn->offset = 0; 1569781a868fSWei Yang 1570781a868fSWei Yang return ret; 1571781a868fSWei Yang } 1572781a868fSWei Yang 1573a8b2f828SGavin Shan int pcibios_sriov_disable(struct pci_dev *pdev) 1574a8b2f828SGavin Shan { 1575781a868fSWei Yang pnv_pci_sriov_disable(pdev); 1576781a868fSWei Yang 1577a8b2f828SGavin Shan /* Release PCI data */ 1578a8b2f828SGavin Shan remove_dev_pci_data(pdev); 1579a8b2f828SGavin Shan return 0; 1580a8b2f828SGavin Shan } 1581a8b2f828SGavin Shan 1582a8b2f828SGavin Shan int pcibios_sriov_enable(struct pci_dev *pdev, u16 num_vfs) 1583a8b2f828SGavin Shan { 1584a8b2f828SGavin Shan /* Allocate PCI data */ 1585a8b2f828SGavin Shan add_dev_pci_data(pdev); 1586781a868fSWei Yang 1587781a868fSWei Yang pnv_pci_sriov_enable(pdev, num_vfs); 1588a8b2f828SGavin Shan return 0; 1589a8b2f828SGavin Shan } 1590a8b2f828SGavin Shan #endif /* CONFIG_PCI_IOV */ 1591a8b2f828SGavin Shan 1592959c9bddSGavin Shan static void pnv_pci_ioda_dma_dev_setup(struct pnv_phb *phb, struct pci_dev *pdev) 1593184cd4a3SBenjamin Herrenschmidt { 1594b72c1f65SBenjamin Herrenschmidt struct pci_dn *pdn = pci_get_pdn(pdev); 1595959c9bddSGavin Shan struct pnv_ioda_pe *pe; 1596184cd4a3SBenjamin Herrenschmidt 1597959c9bddSGavin Shan /* 1598959c9bddSGavin Shan * The function can be called while the PE# 1599959c9bddSGavin Shan * hasn't been assigned. Do nothing for the 1600959c9bddSGavin Shan * case. 1601959c9bddSGavin Shan */ 1602959c9bddSGavin Shan if (!pdn || pdn->pe_number == IODA_INVALID_PE) 1603959c9bddSGavin Shan return; 1604184cd4a3SBenjamin Herrenschmidt 1605959c9bddSGavin Shan pe = &phb->ioda.pe_array[pdn->pe_number]; 1606cd15b048SBenjamin Herrenschmidt WARN_ON(get_dma_ops(&pdev->dev) != &dma_iommu_ops); 1607b348aa65SAlexey Kardashevskiy set_iommu_table_base(&pdev->dev, pe->table_group.tables[0]); 16084617082eSAlexey Kardashevskiy /* 16094617082eSAlexey Kardashevskiy * Note: iommu_add_device() will fail here as 16104617082eSAlexey Kardashevskiy * for physical PE: the device is already added by now; 16114617082eSAlexey Kardashevskiy * for virtual PE: sysfs entries are not ready yet and 16124617082eSAlexey Kardashevskiy * tce_iommu_bus_notifier will add the device to a group later. 16134617082eSAlexey Kardashevskiy */ 1614184cd4a3SBenjamin Herrenschmidt } 1615184cd4a3SBenjamin Herrenschmidt 1616763d2d8dSDaniel Axtens static int pnv_pci_ioda_dma_set_mask(struct pci_dev *pdev, u64 dma_mask) 1617cd15b048SBenjamin Herrenschmidt { 1618763d2d8dSDaniel Axtens struct pci_controller *hose = pci_bus_to_host(pdev->bus); 1619763d2d8dSDaniel Axtens struct pnv_phb *phb = hose->private_data; 1620cd15b048SBenjamin Herrenschmidt struct pci_dn *pdn = pci_get_pdn(pdev); 1621cd15b048SBenjamin Herrenschmidt struct pnv_ioda_pe *pe; 1622cd15b048SBenjamin Herrenschmidt uint64_t top; 1623cd15b048SBenjamin Herrenschmidt bool bypass = false; 1624cd15b048SBenjamin Herrenschmidt 1625cd15b048SBenjamin Herrenschmidt if (WARN_ON(!pdn || pdn->pe_number == IODA_INVALID_PE)) 1626cd15b048SBenjamin Herrenschmidt return -ENODEV;; 1627cd15b048SBenjamin Herrenschmidt 1628cd15b048SBenjamin Herrenschmidt pe = &phb->ioda.pe_array[pdn->pe_number]; 1629cd15b048SBenjamin Herrenschmidt if (pe->tce_bypass_enabled) { 1630cd15b048SBenjamin Herrenschmidt top = pe->tce_bypass_base + memblock_end_of_DRAM() - 1; 1631cd15b048SBenjamin Herrenschmidt bypass = (dma_mask >= top); 1632cd15b048SBenjamin Herrenschmidt } 1633cd15b048SBenjamin Herrenschmidt 1634cd15b048SBenjamin Herrenschmidt if (bypass) { 1635cd15b048SBenjamin Herrenschmidt dev_info(&pdev->dev, "Using 64-bit DMA iommu bypass\n"); 1636cd15b048SBenjamin Herrenschmidt set_dma_ops(&pdev->dev, &dma_direct_ops); 1637cd15b048SBenjamin Herrenschmidt } else { 1638cd15b048SBenjamin Herrenschmidt dev_info(&pdev->dev, "Using 32-bit DMA via iommu\n"); 1639cd15b048SBenjamin Herrenschmidt set_dma_ops(&pdev->dev, &dma_iommu_ops); 1640cd15b048SBenjamin Herrenschmidt } 1641a32305bfSBrian W Hart *pdev->dev.dma_mask = dma_mask; 1642cd15b048SBenjamin Herrenschmidt return 0; 1643cd15b048SBenjamin Herrenschmidt } 1644cd15b048SBenjamin Herrenschmidt 1645fe7e85c6SGavin Shan static u64 pnv_pci_ioda_dma_get_required_mask(struct pnv_phb *phb, 1646fe7e85c6SGavin Shan struct pci_dev *pdev) 1647fe7e85c6SGavin Shan { 1648fe7e85c6SGavin Shan struct pci_dn *pdn = pci_get_pdn(pdev); 1649fe7e85c6SGavin Shan struct pnv_ioda_pe *pe; 1650fe7e85c6SGavin Shan u64 end, mask; 1651fe7e85c6SGavin Shan 1652fe7e85c6SGavin Shan if (WARN_ON(!pdn || pdn->pe_number == IODA_INVALID_PE)) 1653fe7e85c6SGavin Shan return 0; 1654fe7e85c6SGavin Shan 1655fe7e85c6SGavin Shan pe = &phb->ioda.pe_array[pdn->pe_number]; 1656fe7e85c6SGavin Shan if (!pe->tce_bypass_enabled) 1657fe7e85c6SGavin Shan return __dma_get_required_mask(&pdev->dev); 1658fe7e85c6SGavin Shan 1659fe7e85c6SGavin Shan 1660fe7e85c6SGavin Shan end = pe->tce_bypass_base + memblock_end_of_DRAM(); 1661fe7e85c6SGavin Shan mask = 1ULL << (fls64(end) - 1); 1662fe7e85c6SGavin Shan mask += mask - 1; 1663fe7e85c6SGavin Shan 1664fe7e85c6SGavin Shan return mask; 1665fe7e85c6SGavin Shan } 1666fe7e85c6SGavin Shan 1667dff4a39eSGavin Shan static void pnv_ioda_setup_bus_dma(struct pnv_ioda_pe *pe, 1668ea30e99eSAlexey Kardashevskiy struct pci_bus *bus) 166974251fe2SBenjamin Herrenschmidt { 167074251fe2SBenjamin Herrenschmidt struct pci_dev *dev; 167174251fe2SBenjamin Herrenschmidt 167274251fe2SBenjamin Herrenschmidt list_for_each_entry(dev, &bus->devices, bus_list) { 1673b348aa65SAlexey Kardashevskiy set_iommu_table_base(&dev->dev, pe->table_group.tables[0]); 1674e91c2511SBenjamin Herrenschmidt set_dma_offset(&dev->dev, pe->tce_bypass_base); 16754617082eSAlexey Kardashevskiy iommu_add_device(&dev->dev); 1676dff4a39eSGavin Shan 16775c89a87dSAlexey Kardashevskiy if ((pe->flags & PNV_IODA_PE_BUS_ALL) && dev->subordinate) 1678ea30e99eSAlexey Kardashevskiy pnv_ioda_setup_bus_dma(pe, dev->subordinate); 167974251fe2SBenjamin Herrenschmidt } 168074251fe2SBenjamin Herrenschmidt } 168174251fe2SBenjamin Herrenschmidt 1682decbda25SAlexey Kardashevskiy static void pnv_pci_ioda1_tce_invalidate(struct iommu_table *tbl, 1683decbda25SAlexey Kardashevskiy unsigned long index, unsigned long npages, bool rm) 16844cce9550SGavin Shan { 16850eaf4defSAlexey Kardashevskiy struct iommu_table_group_link *tgl = list_first_entry_or_null( 16860eaf4defSAlexey Kardashevskiy &tbl->it_group_list, struct iommu_table_group_link, 16870eaf4defSAlexey Kardashevskiy next); 16880eaf4defSAlexey Kardashevskiy struct pnv_ioda_pe *pe = container_of(tgl->table_group, 1689b348aa65SAlexey Kardashevskiy struct pnv_ioda_pe, table_group); 16903ad26e5cSBenjamin Herrenschmidt __be64 __iomem *invalidate = rm ? 16915780fb04SAlexey Kardashevskiy (__be64 __iomem *)pe->phb->ioda.tce_inval_reg_phys : 16925780fb04SAlexey Kardashevskiy pe->phb->ioda.tce_inval_reg; 16934cce9550SGavin Shan unsigned long start, end, inc; 1694b0376c9bSAlexey Kardashevskiy const unsigned shift = tbl->it_page_shift; 16954cce9550SGavin Shan 1696decbda25SAlexey Kardashevskiy start = __pa(((__be64 *)tbl->it_base) + index - tbl->it_offset); 1697decbda25SAlexey Kardashevskiy end = __pa(((__be64 *)tbl->it_base) + index - tbl->it_offset + 1698decbda25SAlexey Kardashevskiy npages - 1); 16994cce9550SGavin Shan 17004cce9550SGavin Shan /* BML uses this case for p6/p7/galaxy2: Shift addr and put in node */ 17014cce9550SGavin Shan if (tbl->it_busno) { 1702b0376c9bSAlexey Kardashevskiy start <<= shift; 1703b0376c9bSAlexey Kardashevskiy end <<= shift; 1704b0376c9bSAlexey Kardashevskiy inc = 128ull << shift; 17054cce9550SGavin Shan start |= tbl->it_busno; 17064cce9550SGavin Shan end |= tbl->it_busno; 17074cce9550SGavin Shan } else if (tbl->it_type & TCE_PCI_SWINV_PAIR) { 17084cce9550SGavin Shan /* p7ioc-style invalidation, 2 TCEs per write */ 17094cce9550SGavin Shan start |= (1ull << 63); 17104cce9550SGavin Shan end |= (1ull << 63); 17114cce9550SGavin Shan inc = 16; 17124cce9550SGavin Shan } else { 17134cce9550SGavin Shan /* Default (older HW) */ 17144cce9550SGavin Shan inc = 128; 17154cce9550SGavin Shan } 17164cce9550SGavin Shan 17174cce9550SGavin Shan end |= inc - 1; /* round up end to be different than start */ 17184cce9550SGavin Shan 17194cce9550SGavin Shan mb(); /* Ensure above stores are visible */ 17204cce9550SGavin Shan while (start <= end) { 17218e0a1611SAlexey Kardashevskiy if (rm) 17223ad26e5cSBenjamin Herrenschmidt __raw_rm_writeq(cpu_to_be64(start), invalidate); 17238e0a1611SAlexey Kardashevskiy else 17243a1a4661SBenjamin Herrenschmidt __raw_writeq(cpu_to_be64(start), invalidate); 17254cce9550SGavin Shan start += inc; 17264cce9550SGavin Shan } 17274cce9550SGavin Shan 17284cce9550SGavin Shan /* 17294cce9550SGavin Shan * The iommu layer will do another mb() for us on build() 17304cce9550SGavin Shan * and we don't care on free() 17314cce9550SGavin Shan */ 17324cce9550SGavin Shan } 17334cce9550SGavin Shan 1734decbda25SAlexey Kardashevskiy static int pnv_ioda1_tce_build(struct iommu_table *tbl, long index, 1735decbda25SAlexey Kardashevskiy long npages, unsigned long uaddr, 1736decbda25SAlexey Kardashevskiy enum dma_data_direction direction, 1737decbda25SAlexey Kardashevskiy struct dma_attrs *attrs) 1738decbda25SAlexey Kardashevskiy { 1739decbda25SAlexey Kardashevskiy int ret = pnv_tce_build(tbl, index, npages, uaddr, direction, 1740decbda25SAlexey Kardashevskiy attrs); 1741decbda25SAlexey Kardashevskiy 1742decbda25SAlexey Kardashevskiy if (!ret && (tbl->it_type & TCE_PCI_SWINV_CREATE)) 1743decbda25SAlexey Kardashevskiy pnv_pci_ioda1_tce_invalidate(tbl, index, npages, false); 1744decbda25SAlexey Kardashevskiy 1745decbda25SAlexey Kardashevskiy return ret; 1746decbda25SAlexey Kardashevskiy } 1747decbda25SAlexey Kardashevskiy 174805c6cfb9SAlexey Kardashevskiy #ifdef CONFIG_IOMMU_API 174905c6cfb9SAlexey Kardashevskiy static int pnv_ioda1_tce_xchg(struct iommu_table *tbl, long index, 175005c6cfb9SAlexey Kardashevskiy unsigned long *hpa, enum dma_data_direction *direction) 175105c6cfb9SAlexey Kardashevskiy { 175205c6cfb9SAlexey Kardashevskiy long ret = pnv_tce_xchg(tbl, index, hpa, direction); 175305c6cfb9SAlexey Kardashevskiy 175405c6cfb9SAlexey Kardashevskiy if (!ret && (tbl->it_type & 175505c6cfb9SAlexey Kardashevskiy (TCE_PCI_SWINV_CREATE | TCE_PCI_SWINV_FREE))) 175605c6cfb9SAlexey Kardashevskiy pnv_pci_ioda1_tce_invalidate(tbl, index, 1, false); 175705c6cfb9SAlexey Kardashevskiy 175805c6cfb9SAlexey Kardashevskiy return ret; 175905c6cfb9SAlexey Kardashevskiy } 176005c6cfb9SAlexey Kardashevskiy #endif 176105c6cfb9SAlexey Kardashevskiy 1762decbda25SAlexey Kardashevskiy static void pnv_ioda1_tce_free(struct iommu_table *tbl, long index, 1763decbda25SAlexey Kardashevskiy long npages) 1764decbda25SAlexey Kardashevskiy { 1765decbda25SAlexey Kardashevskiy pnv_tce_free(tbl, index, npages); 1766decbda25SAlexey Kardashevskiy 1767decbda25SAlexey Kardashevskiy if (tbl->it_type & TCE_PCI_SWINV_FREE) 1768decbda25SAlexey Kardashevskiy pnv_pci_ioda1_tce_invalidate(tbl, index, npages, false); 1769decbda25SAlexey Kardashevskiy } 1770decbda25SAlexey Kardashevskiy 1771da004c36SAlexey Kardashevskiy static struct iommu_table_ops pnv_ioda1_iommu_ops = { 1772decbda25SAlexey Kardashevskiy .set = pnv_ioda1_tce_build, 177305c6cfb9SAlexey Kardashevskiy #ifdef CONFIG_IOMMU_API 177405c6cfb9SAlexey Kardashevskiy .exchange = pnv_ioda1_tce_xchg, 177505c6cfb9SAlexey Kardashevskiy #endif 1776decbda25SAlexey Kardashevskiy .clear = pnv_ioda1_tce_free, 1777da004c36SAlexey Kardashevskiy .get = pnv_tce_get, 1778da004c36SAlexey Kardashevskiy }; 1779da004c36SAlexey Kardashevskiy 17805780fb04SAlexey Kardashevskiy static inline void pnv_pci_ioda2_tce_invalidate_entire(struct pnv_ioda_pe *pe) 17815780fb04SAlexey Kardashevskiy { 17825780fb04SAlexey Kardashevskiy /* 01xb - invalidate TCEs that match the specified PE# */ 17835780fb04SAlexey Kardashevskiy unsigned long val = (0x4ull << 60) | (pe->pe_number & 0xFF); 17845780fb04SAlexey Kardashevskiy struct pnv_phb *phb = pe->phb; 17855780fb04SAlexey Kardashevskiy 17865780fb04SAlexey Kardashevskiy if (!phb->ioda.tce_inval_reg) 17875780fb04SAlexey Kardashevskiy return; 17885780fb04SAlexey Kardashevskiy 17895780fb04SAlexey Kardashevskiy mb(); /* Ensure above stores are visible */ 17905780fb04SAlexey Kardashevskiy __raw_writeq(cpu_to_be64(val), phb->ioda.tce_inval_reg); 17915780fb04SAlexey Kardashevskiy } 17925780fb04SAlexey Kardashevskiy 1793e57080f1SAlexey Kardashevskiy static void pnv_pci_ioda2_do_tce_invalidate(unsigned pe_number, bool rm, 1794e57080f1SAlexey Kardashevskiy __be64 __iomem *invalidate, unsigned shift, 1795e57080f1SAlexey Kardashevskiy unsigned long index, unsigned long npages) 17964cce9550SGavin Shan { 17974cce9550SGavin Shan unsigned long start, end, inc; 17984cce9550SGavin Shan 17994cce9550SGavin Shan /* We'll invalidate DMA address in PE scope */ 1800b0376c9bSAlexey Kardashevskiy start = 0x2ull << 60; 1801e57080f1SAlexey Kardashevskiy start |= (pe_number & 0xFF); 18024cce9550SGavin Shan end = start; 18034cce9550SGavin Shan 18044cce9550SGavin Shan /* Figure out the start, end and step */ 1805decbda25SAlexey Kardashevskiy start |= (index << shift); 1806decbda25SAlexey Kardashevskiy end |= ((index + npages - 1) << shift); 1807b0376c9bSAlexey Kardashevskiy inc = (0x1ull << shift); 18084cce9550SGavin Shan mb(); 18094cce9550SGavin Shan 18104cce9550SGavin Shan while (start <= end) { 18118e0a1611SAlexey Kardashevskiy if (rm) 18123ad26e5cSBenjamin Herrenschmidt __raw_rm_writeq(cpu_to_be64(start), invalidate); 18138e0a1611SAlexey Kardashevskiy else 18143a1a4661SBenjamin Herrenschmidt __raw_writeq(cpu_to_be64(start), invalidate); 18154cce9550SGavin Shan start += inc; 18164cce9550SGavin Shan } 18174cce9550SGavin Shan } 18184cce9550SGavin Shan 1819e57080f1SAlexey Kardashevskiy static void pnv_pci_ioda2_tce_invalidate(struct iommu_table *tbl, 1820e57080f1SAlexey Kardashevskiy unsigned long index, unsigned long npages, bool rm) 1821e57080f1SAlexey Kardashevskiy { 1822e57080f1SAlexey Kardashevskiy struct iommu_table_group_link *tgl; 1823e57080f1SAlexey Kardashevskiy 1824e57080f1SAlexey Kardashevskiy list_for_each_entry_rcu(tgl, &tbl->it_group_list, next) { 1825e57080f1SAlexey Kardashevskiy struct pnv_ioda_pe *pe = container_of(tgl->table_group, 1826e57080f1SAlexey Kardashevskiy struct pnv_ioda_pe, table_group); 1827e57080f1SAlexey Kardashevskiy __be64 __iomem *invalidate = rm ? 1828e57080f1SAlexey Kardashevskiy (__be64 __iomem *)pe->phb->ioda.tce_inval_reg_phys : 1829e57080f1SAlexey Kardashevskiy pe->phb->ioda.tce_inval_reg; 1830e57080f1SAlexey Kardashevskiy 1831e57080f1SAlexey Kardashevskiy pnv_pci_ioda2_do_tce_invalidate(pe->pe_number, rm, 1832e57080f1SAlexey Kardashevskiy invalidate, tbl->it_page_shift, 1833e57080f1SAlexey Kardashevskiy index, npages); 1834e57080f1SAlexey Kardashevskiy } 1835e57080f1SAlexey Kardashevskiy } 1836e57080f1SAlexey Kardashevskiy 1837decbda25SAlexey Kardashevskiy static int pnv_ioda2_tce_build(struct iommu_table *tbl, long index, 1838decbda25SAlexey Kardashevskiy long npages, unsigned long uaddr, 1839decbda25SAlexey Kardashevskiy enum dma_data_direction direction, 1840decbda25SAlexey Kardashevskiy struct dma_attrs *attrs) 18414cce9550SGavin Shan { 1842decbda25SAlexey Kardashevskiy int ret = pnv_tce_build(tbl, index, npages, uaddr, direction, 1843decbda25SAlexey Kardashevskiy attrs); 18444cce9550SGavin Shan 1845decbda25SAlexey Kardashevskiy if (!ret && (tbl->it_type & TCE_PCI_SWINV_CREATE)) 1846decbda25SAlexey Kardashevskiy pnv_pci_ioda2_tce_invalidate(tbl, index, npages, false); 1847decbda25SAlexey Kardashevskiy 1848decbda25SAlexey Kardashevskiy return ret; 1849decbda25SAlexey Kardashevskiy } 1850decbda25SAlexey Kardashevskiy 185105c6cfb9SAlexey Kardashevskiy #ifdef CONFIG_IOMMU_API 185205c6cfb9SAlexey Kardashevskiy static int pnv_ioda2_tce_xchg(struct iommu_table *tbl, long index, 185305c6cfb9SAlexey Kardashevskiy unsigned long *hpa, enum dma_data_direction *direction) 185405c6cfb9SAlexey Kardashevskiy { 185505c6cfb9SAlexey Kardashevskiy long ret = pnv_tce_xchg(tbl, index, hpa, direction); 185605c6cfb9SAlexey Kardashevskiy 185705c6cfb9SAlexey Kardashevskiy if (!ret && (tbl->it_type & 185805c6cfb9SAlexey Kardashevskiy (TCE_PCI_SWINV_CREATE | TCE_PCI_SWINV_FREE))) 185905c6cfb9SAlexey Kardashevskiy pnv_pci_ioda2_tce_invalidate(tbl, index, 1, false); 186005c6cfb9SAlexey Kardashevskiy 186105c6cfb9SAlexey Kardashevskiy return ret; 186205c6cfb9SAlexey Kardashevskiy } 186305c6cfb9SAlexey Kardashevskiy #endif 186405c6cfb9SAlexey Kardashevskiy 1865decbda25SAlexey Kardashevskiy static void pnv_ioda2_tce_free(struct iommu_table *tbl, long index, 1866decbda25SAlexey Kardashevskiy long npages) 1867decbda25SAlexey Kardashevskiy { 1868decbda25SAlexey Kardashevskiy pnv_tce_free(tbl, index, npages); 1869decbda25SAlexey Kardashevskiy 1870decbda25SAlexey Kardashevskiy if (tbl->it_type & TCE_PCI_SWINV_FREE) 1871decbda25SAlexey Kardashevskiy pnv_pci_ioda2_tce_invalidate(tbl, index, npages, false); 18724cce9550SGavin Shan } 18734cce9550SGavin Shan 18744793d65dSAlexey Kardashevskiy static void pnv_ioda2_table_free(struct iommu_table *tbl) 18754793d65dSAlexey Kardashevskiy { 18764793d65dSAlexey Kardashevskiy pnv_pci_ioda2_table_free_pages(tbl); 18774793d65dSAlexey Kardashevskiy iommu_free_table(tbl, "pnv"); 18784793d65dSAlexey Kardashevskiy } 18794793d65dSAlexey Kardashevskiy 1880da004c36SAlexey Kardashevskiy static struct iommu_table_ops pnv_ioda2_iommu_ops = { 1881decbda25SAlexey Kardashevskiy .set = pnv_ioda2_tce_build, 188205c6cfb9SAlexey Kardashevskiy #ifdef CONFIG_IOMMU_API 188305c6cfb9SAlexey Kardashevskiy .exchange = pnv_ioda2_tce_xchg, 188405c6cfb9SAlexey Kardashevskiy #endif 1885decbda25SAlexey Kardashevskiy .clear = pnv_ioda2_tce_free, 1886da004c36SAlexey Kardashevskiy .get = pnv_tce_get, 18874793d65dSAlexey Kardashevskiy .free = pnv_ioda2_table_free, 1888da004c36SAlexey Kardashevskiy }; 1889da004c36SAlexey Kardashevskiy 1890cad5cef6SGreg Kroah-Hartman static void pnv_pci_ioda_setup_dma_pe(struct pnv_phb *phb, 1891cad5cef6SGreg Kroah-Hartman struct pnv_ioda_pe *pe, unsigned int base, 1892184cd4a3SBenjamin Herrenschmidt unsigned int segs) 1893184cd4a3SBenjamin Herrenschmidt { 1894184cd4a3SBenjamin Herrenschmidt 1895184cd4a3SBenjamin Herrenschmidt struct page *tce_mem = NULL; 1896184cd4a3SBenjamin Herrenschmidt struct iommu_table *tbl; 1897184cd4a3SBenjamin Herrenschmidt unsigned int i; 1898184cd4a3SBenjamin Herrenschmidt int64_t rc; 1899184cd4a3SBenjamin Herrenschmidt void *addr; 1900184cd4a3SBenjamin Herrenschmidt 1901184cd4a3SBenjamin Herrenschmidt /* XXX FIXME: Handle 64-bit only DMA devices */ 1902184cd4a3SBenjamin Herrenschmidt /* XXX FIXME: Provide 64-bit DMA facilities & non-4K TCE tables etc.. */ 1903184cd4a3SBenjamin Herrenschmidt /* XXX FIXME: Allocate multi-level tables on PHB3 */ 1904184cd4a3SBenjamin Herrenschmidt 1905184cd4a3SBenjamin Herrenschmidt /* We shouldn't already have a 32-bit DMA associated */ 1906184cd4a3SBenjamin Herrenschmidt if (WARN_ON(pe->tce32_seg >= 0)) 1907184cd4a3SBenjamin Herrenschmidt return; 1908184cd4a3SBenjamin Herrenschmidt 19090eaf4defSAlexey Kardashevskiy tbl = pnv_pci_table_alloc(phb->hose->node); 1910b348aa65SAlexey Kardashevskiy iommu_register_group(&pe->table_group, phb->hose->global_number, 1911b348aa65SAlexey Kardashevskiy pe->pe_number); 19120eaf4defSAlexey Kardashevskiy pnv_pci_link_table_and_group(phb->hose->node, 0, tbl, &pe->table_group); 1913c5773822SAlexey Kardashevskiy 1914184cd4a3SBenjamin Herrenschmidt /* Grab a 32-bit TCE table */ 1915184cd4a3SBenjamin Herrenschmidt pe->tce32_seg = base; 1916184cd4a3SBenjamin Herrenschmidt pe_info(pe, " Setting up 32-bit TCE table at %08x..%08x\n", 1917184cd4a3SBenjamin Herrenschmidt (base << 28), ((base + segs) << 28) - 1); 1918184cd4a3SBenjamin Herrenschmidt 1919184cd4a3SBenjamin Herrenschmidt /* XXX Currently, we allocate one big contiguous table for the 1920184cd4a3SBenjamin Herrenschmidt * TCEs. We only really need one chunk per 256M of TCE space 1921184cd4a3SBenjamin Herrenschmidt * (ie per segment) but that's an optimization for later, it 1922184cd4a3SBenjamin Herrenschmidt * requires some added smarts with our get/put_tce implementation 1923184cd4a3SBenjamin Herrenschmidt */ 1924184cd4a3SBenjamin Herrenschmidt tce_mem = alloc_pages_node(phb->hose->node, GFP_KERNEL, 1925184cd4a3SBenjamin Herrenschmidt get_order(TCE32_TABLE_SIZE * segs)); 1926184cd4a3SBenjamin Herrenschmidt if (!tce_mem) { 1927184cd4a3SBenjamin Herrenschmidt pe_err(pe, " Failed to allocate a 32-bit TCE memory\n"); 1928184cd4a3SBenjamin Herrenschmidt goto fail; 1929184cd4a3SBenjamin Herrenschmidt } 1930184cd4a3SBenjamin Herrenschmidt addr = page_address(tce_mem); 1931184cd4a3SBenjamin Herrenschmidt memset(addr, 0, TCE32_TABLE_SIZE * segs); 1932184cd4a3SBenjamin Herrenschmidt 1933184cd4a3SBenjamin Herrenschmidt /* Configure HW */ 1934184cd4a3SBenjamin Herrenschmidt for (i = 0; i < segs; i++) { 1935184cd4a3SBenjamin Herrenschmidt rc = opal_pci_map_pe_dma_window(phb->opal_id, 1936184cd4a3SBenjamin Herrenschmidt pe->pe_number, 1937184cd4a3SBenjamin Herrenschmidt base + i, 1, 1938184cd4a3SBenjamin Herrenschmidt __pa(addr) + TCE32_TABLE_SIZE * i, 1939184cd4a3SBenjamin Herrenschmidt TCE32_TABLE_SIZE, 0x1000); 1940184cd4a3SBenjamin Herrenschmidt if (rc) { 1941184cd4a3SBenjamin Herrenschmidt pe_err(pe, " Failed to configure 32-bit TCE table," 1942184cd4a3SBenjamin Herrenschmidt " err %ld\n", rc); 1943184cd4a3SBenjamin Herrenschmidt goto fail; 1944184cd4a3SBenjamin Herrenschmidt } 1945184cd4a3SBenjamin Herrenschmidt } 1946184cd4a3SBenjamin Herrenschmidt 1947184cd4a3SBenjamin Herrenschmidt /* Setup linux iommu table */ 1948184cd4a3SBenjamin Herrenschmidt pnv_pci_setup_iommu_table(tbl, addr, TCE32_TABLE_SIZE * segs, 19498fa5d454SAlexey Kardashevskiy base << 28, IOMMU_PAGE_SHIFT_4K); 1950184cd4a3SBenjamin Herrenschmidt 1951184cd4a3SBenjamin Herrenschmidt /* OPAL variant of P7IOC SW invalidated TCEs */ 19525780fb04SAlexey Kardashevskiy if (phb->ioda.tce_inval_reg) 195365fd766bSGavin Shan tbl->it_type |= (TCE_PCI_SWINV_CREATE | 195465fd766bSGavin Shan TCE_PCI_SWINV_FREE | 195565fd766bSGavin Shan TCE_PCI_SWINV_PAIR); 19565780fb04SAlexey Kardashevskiy 1957da004c36SAlexey Kardashevskiy tbl->it_ops = &pnv_ioda1_iommu_ops; 19584793d65dSAlexey Kardashevskiy pe->table_group.tce32_start = tbl->it_offset << tbl->it_page_shift; 19594793d65dSAlexey Kardashevskiy pe->table_group.tce32_size = tbl->it_size << tbl->it_page_shift; 1960184cd4a3SBenjamin Herrenschmidt iommu_init_table(tbl, phb->hose->node); 1961184cd4a3SBenjamin Herrenschmidt 1962781a868fSWei Yang if (pe->flags & PNV_IODA_PE_DEV) { 19634617082eSAlexey Kardashevskiy /* 19644617082eSAlexey Kardashevskiy * Setting table base here only for carrying iommu_group 19654617082eSAlexey Kardashevskiy * further down to let iommu_add_device() do the job. 19664617082eSAlexey Kardashevskiy * pnv_pci_ioda_dma_dev_setup will override it later anyway. 19674617082eSAlexey Kardashevskiy */ 19684617082eSAlexey Kardashevskiy set_iommu_table_base(&pe->pdev->dev, tbl); 19694617082eSAlexey Kardashevskiy iommu_add_device(&pe->pdev->dev); 1970c5773822SAlexey Kardashevskiy } else if (pe->flags & (PNV_IODA_PE_BUS | PNV_IODA_PE_BUS_ALL)) 1971ea30e99eSAlexey Kardashevskiy pnv_ioda_setup_bus_dma(pe, pe->pbus); 197274251fe2SBenjamin Herrenschmidt 1973184cd4a3SBenjamin Herrenschmidt return; 1974184cd4a3SBenjamin Herrenschmidt fail: 1975184cd4a3SBenjamin Herrenschmidt /* XXX Failure: Try to fallback to 64-bit only ? */ 1976184cd4a3SBenjamin Herrenschmidt if (pe->tce32_seg >= 0) 1977184cd4a3SBenjamin Herrenschmidt pe->tce32_seg = -1; 1978184cd4a3SBenjamin Herrenschmidt if (tce_mem) 1979184cd4a3SBenjamin Herrenschmidt __free_pages(tce_mem, get_order(TCE32_TABLE_SIZE * segs)); 19800eaf4defSAlexey Kardashevskiy if (tbl) { 19810eaf4defSAlexey Kardashevskiy pnv_pci_unlink_table_and_group(tbl, &pe->table_group); 19820eaf4defSAlexey Kardashevskiy iommu_free_table(tbl, "pnv"); 19830eaf4defSAlexey Kardashevskiy } 1984184cd4a3SBenjamin Herrenschmidt } 1985184cd4a3SBenjamin Herrenschmidt 198643cb60abSAlexey Kardashevskiy static long pnv_pci_ioda2_set_window(struct iommu_table_group *table_group, 198743cb60abSAlexey Kardashevskiy int num, struct iommu_table *tbl) 198843cb60abSAlexey Kardashevskiy { 198943cb60abSAlexey Kardashevskiy struct pnv_ioda_pe *pe = container_of(table_group, struct pnv_ioda_pe, 199043cb60abSAlexey Kardashevskiy table_group); 199143cb60abSAlexey Kardashevskiy struct pnv_phb *phb = pe->phb; 199243cb60abSAlexey Kardashevskiy int64_t rc; 1993bbb845c4SAlexey Kardashevskiy const unsigned long size = tbl->it_indirect_levels ? 1994bbb845c4SAlexey Kardashevskiy tbl->it_level_size : tbl->it_size; 199543cb60abSAlexey Kardashevskiy const __u64 start_addr = tbl->it_offset << tbl->it_page_shift; 199643cb60abSAlexey Kardashevskiy const __u64 win_size = tbl->it_size << tbl->it_page_shift; 199743cb60abSAlexey Kardashevskiy 19984793d65dSAlexey Kardashevskiy pe_info(pe, "Setting up window#%d %llx..%llx pg=%x\n", num, 199943cb60abSAlexey Kardashevskiy start_addr, start_addr + win_size - 1, 200043cb60abSAlexey Kardashevskiy IOMMU_PAGE_SIZE(tbl)); 200143cb60abSAlexey Kardashevskiy 200243cb60abSAlexey Kardashevskiy /* 200343cb60abSAlexey Kardashevskiy * Map TCE table through TVT. The TVE index is the PE number 200443cb60abSAlexey Kardashevskiy * shifted by 1 bit for 32-bits DMA space. 200543cb60abSAlexey Kardashevskiy */ 200643cb60abSAlexey Kardashevskiy rc = opal_pci_map_pe_dma_window(phb->opal_id, 200743cb60abSAlexey Kardashevskiy pe->pe_number, 20084793d65dSAlexey Kardashevskiy (pe->pe_number << 1) + num, 2009bbb845c4SAlexey Kardashevskiy tbl->it_indirect_levels + 1, 201043cb60abSAlexey Kardashevskiy __pa(tbl->it_base), 2011bbb845c4SAlexey Kardashevskiy size << 3, 201243cb60abSAlexey Kardashevskiy IOMMU_PAGE_SIZE(tbl)); 201343cb60abSAlexey Kardashevskiy if (rc) { 201443cb60abSAlexey Kardashevskiy pe_err(pe, "Failed to configure TCE table, err %ld\n", rc); 201543cb60abSAlexey Kardashevskiy return rc; 201643cb60abSAlexey Kardashevskiy } 201743cb60abSAlexey Kardashevskiy 201843cb60abSAlexey Kardashevskiy pnv_pci_link_table_and_group(phb->hose->node, num, 201943cb60abSAlexey Kardashevskiy tbl, &pe->table_group); 202043cb60abSAlexey Kardashevskiy pnv_pci_ioda2_tce_invalidate_entire(pe); 202143cb60abSAlexey Kardashevskiy 202243cb60abSAlexey Kardashevskiy return 0; 202343cb60abSAlexey Kardashevskiy } 202443cb60abSAlexey Kardashevskiy 2025f87a8864SAlexey Kardashevskiy static void pnv_pci_ioda2_set_bypass(struct pnv_ioda_pe *pe, bool enable) 2026cd15b048SBenjamin Herrenschmidt { 2027cd15b048SBenjamin Herrenschmidt uint16_t window_id = (pe->pe_number << 1 ) + 1; 2028cd15b048SBenjamin Herrenschmidt int64_t rc; 2029cd15b048SBenjamin Herrenschmidt 2030cd15b048SBenjamin Herrenschmidt pe_info(pe, "%sabling 64-bit DMA bypass\n", enable ? "En" : "Dis"); 2031cd15b048SBenjamin Herrenschmidt if (enable) { 2032cd15b048SBenjamin Herrenschmidt phys_addr_t top = memblock_end_of_DRAM(); 2033cd15b048SBenjamin Herrenschmidt 2034cd15b048SBenjamin Herrenschmidt top = roundup_pow_of_two(top); 2035cd15b048SBenjamin Herrenschmidt rc = opal_pci_map_pe_dma_window_real(pe->phb->opal_id, 2036cd15b048SBenjamin Herrenschmidt pe->pe_number, 2037cd15b048SBenjamin Herrenschmidt window_id, 2038cd15b048SBenjamin Herrenschmidt pe->tce_bypass_base, 2039cd15b048SBenjamin Herrenschmidt top); 2040cd15b048SBenjamin Herrenschmidt } else { 2041cd15b048SBenjamin Herrenschmidt rc = opal_pci_map_pe_dma_window_real(pe->phb->opal_id, 2042cd15b048SBenjamin Herrenschmidt pe->pe_number, 2043cd15b048SBenjamin Herrenschmidt window_id, 2044cd15b048SBenjamin Herrenschmidt pe->tce_bypass_base, 2045cd15b048SBenjamin Herrenschmidt 0); 2046cd15b048SBenjamin Herrenschmidt } 2047cd15b048SBenjamin Herrenschmidt if (rc) 2048cd15b048SBenjamin Herrenschmidt pe_err(pe, "OPAL error %lld configuring bypass window\n", rc); 2049cd15b048SBenjamin Herrenschmidt else 2050cd15b048SBenjamin Herrenschmidt pe->tce_bypass_enabled = enable; 2051cd15b048SBenjamin Herrenschmidt } 2052cd15b048SBenjamin Herrenschmidt 20534793d65dSAlexey Kardashevskiy static long pnv_pci_ioda2_table_alloc_pages(int nid, __u64 bus_offset, 20544793d65dSAlexey Kardashevskiy __u32 page_shift, __u64 window_size, __u32 levels, 20554793d65dSAlexey Kardashevskiy struct iommu_table *tbl); 20564793d65dSAlexey Kardashevskiy 20574793d65dSAlexey Kardashevskiy static long pnv_pci_ioda2_create_table(struct iommu_table_group *table_group, 20584793d65dSAlexey Kardashevskiy int num, __u32 page_shift, __u64 window_size, __u32 levels, 20594793d65dSAlexey Kardashevskiy struct iommu_table **ptbl) 20604793d65dSAlexey Kardashevskiy { 20614793d65dSAlexey Kardashevskiy struct pnv_ioda_pe *pe = container_of(table_group, struct pnv_ioda_pe, 20624793d65dSAlexey Kardashevskiy table_group); 20634793d65dSAlexey Kardashevskiy int nid = pe->phb->hose->node; 20644793d65dSAlexey Kardashevskiy __u64 bus_offset = num ? pe->tce_bypass_base : table_group->tce32_start; 20654793d65dSAlexey Kardashevskiy long ret; 20664793d65dSAlexey Kardashevskiy struct iommu_table *tbl; 20674793d65dSAlexey Kardashevskiy 20684793d65dSAlexey Kardashevskiy tbl = pnv_pci_table_alloc(nid); 20694793d65dSAlexey Kardashevskiy if (!tbl) 20704793d65dSAlexey Kardashevskiy return -ENOMEM; 20714793d65dSAlexey Kardashevskiy 20724793d65dSAlexey Kardashevskiy ret = pnv_pci_ioda2_table_alloc_pages(nid, 20734793d65dSAlexey Kardashevskiy bus_offset, page_shift, window_size, 20744793d65dSAlexey Kardashevskiy levels, tbl); 20754793d65dSAlexey Kardashevskiy if (ret) { 20764793d65dSAlexey Kardashevskiy iommu_free_table(tbl, "pnv"); 20774793d65dSAlexey Kardashevskiy return ret; 20784793d65dSAlexey Kardashevskiy } 20794793d65dSAlexey Kardashevskiy 20804793d65dSAlexey Kardashevskiy tbl->it_ops = &pnv_ioda2_iommu_ops; 20814793d65dSAlexey Kardashevskiy if (pe->phb->ioda.tce_inval_reg) 20824793d65dSAlexey Kardashevskiy tbl->it_type |= (TCE_PCI_SWINV_CREATE | TCE_PCI_SWINV_FREE); 20834793d65dSAlexey Kardashevskiy 20844793d65dSAlexey Kardashevskiy *ptbl = tbl; 20854793d65dSAlexey Kardashevskiy 20864793d65dSAlexey Kardashevskiy return 0; 20874793d65dSAlexey Kardashevskiy } 20884793d65dSAlexey Kardashevskiy 208946d3e1e1SAlexey Kardashevskiy static long pnv_pci_ioda2_setup_default_config(struct pnv_ioda_pe *pe) 209046d3e1e1SAlexey Kardashevskiy { 209146d3e1e1SAlexey Kardashevskiy struct iommu_table *tbl = NULL; 209246d3e1e1SAlexey Kardashevskiy long rc; 209346d3e1e1SAlexey Kardashevskiy 209446d3e1e1SAlexey Kardashevskiy rc = pnv_pci_ioda2_create_table(&pe->table_group, 0, 209546d3e1e1SAlexey Kardashevskiy IOMMU_PAGE_SHIFT_4K, 209646d3e1e1SAlexey Kardashevskiy pe->table_group.tce32_size, 209746d3e1e1SAlexey Kardashevskiy POWERNV_IOMMU_DEFAULT_LEVELS, &tbl); 209846d3e1e1SAlexey Kardashevskiy if (rc) { 209946d3e1e1SAlexey Kardashevskiy pe_err(pe, "Failed to create 32-bit TCE table, err %ld", 210046d3e1e1SAlexey Kardashevskiy rc); 210146d3e1e1SAlexey Kardashevskiy return rc; 210246d3e1e1SAlexey Kardashevskiy } 210346d3e1e1SAlexey Kardashevskiy 210446d3e1e1SAlexey Kardashevskiy iommu_init_table(tbl, pe->phb->hose->node); 210546d3e1e1SAlexey Kardashevskiy 210646d3e1e1SAlexey Kardashevskiy rc = pnv_pci_ioda2_set_window(&pe->table_group, 0, tbl); 210746d3e1e1SAlexey Kardashevskiy if (rc) { 210846d3e1e1SAlexey Kardashevskiy pe_err(pe, "Failed to configure 32-bit TCE table, err %ld\n", 210946d3e1e1SAlexey Kardashevskiy rc); 211046d3e1e1SAlexey Kardashevskiy pnv_ioda2_table_free(tbl); 211146d3e1e1SAlexey Kardashevskiy return rc; 211246d3e1e1SAlexey Kardashevskiy } 211346d3e1e1SAlexey Kardashevskiy 211446d3e1e1SAlexey Kardashevskiy if (!pnv_iommu_bypass_disabled) 211546d3e1e1SAlexey Kardashevskiy pnv_pci_ioda2_set_bypass(pe, true); 211646d3e1e1SAlexey Kardashevskiy 211746d3e1e1SAlexey Kardashevskiy /* OPAL variant of PHB3 invalidated TCEs */ 211846d3e1e1SAlexey Kardashevskiy if (pe->phb->ioda.tce_inval_reg) 211946d3e1e1SAlexey Kardashevskiy tbl->it_type |= (TCE_PCI_SWINV_CREATE | TCE_PCI_SWINV_FREE); 212046d3e1e1SAlexey Kardashevskiy 212146d3e1e1SAlexey Kardashevskiy /* 212246d3e1e1SAlexey Kardashevskiy * Setting table base here only for carrying iommu_group 212346d3e1e1SAlexey Kardashevskiy * further down to let iommu_add_device() do the job. 212446d3e1e1SAlexey Kardashevskiy * pnv_pci_ioda_dma_dev_setup will override it later anyway. 212546d3e1e1SAlexey Kardashevskiy */ 212646d3e1e1SAlexey Kardashevskiy if (pe->flags & PNV_IODA_PE_DEV) 212746d3e1e1SAlexey Kardashevskiy set_iommu_table_base(&pe->pdev->dev, tbl); 212846d3e1e1SAlexey Kardashevskiy 212946d3e1e1SAlexey Kardashevskiy return 0; 213046d3e1e1SAlexey Kardashevskiy } 213146d3e1e1SAlexey Kardashevskiy 2132b5926430SAlexey Kardashevskiy #if defined(CONFIG_IOMMU_API) || defined(CONFIG_PCI_IOV) 2133b5926430SAlexey Kardashevskiy static long pnv_pci_ioda2_unset_window(struct iommu_table_group *table_group, 2134b5926430SAlexey Kardashevskiy int num) 2135b5926430SAlexey Kardashevskiy { 2136b5926430SAlexey Kardashevskiy struct pnv_ioda_pe *pe = container_of(table_group, struct pnv_ioda_pe, 2137b5926430SAlexey Kardashevskiy table_group); 2138b5926430SAlexey Kardashevskiy struct pnv_phb *phb = pe->phb; 2139b5926430SAlexey Kardashevskiy long ret; 2140b5926430SAlexey Kardashevskiy 2141b5926430SAlexey Kardashevskiy pe_info(pe, "Removing DMA window #%d\n", num); 2142b5926430SAlexey Kardashevskiy 2143b5926430SAlexey Kardashevskiy ret = opal_pci_map_pe_dma_window(phb->opal_id, pe->pe_number, 2144b5926430SAlexey Kardashevskiy (pe->pe_number << 1) + num, 2145b5926430SAlexey Kardashevskiy 0/* levels */, 0/* table address */, 2146b5926430SAlexey Kardashevskiy 0/* table size */, 0/* page size */); 2147b5926430SAlexey Kardashevskiy if (ret) 2148b5926430SAlexey Kardashevskiy pe_warn(pe, "Unmapping failed, ret = %ld\n", ret); 2149b5926430SAlexey Kardashevskiy else 2150b5926430SAlexey Kardashevskiy pnv_pci_ioda2_tce_invalidate_entire(pe); 2151b5926430SAlexey Kardashevskiy 2152b5926430SAlexey Kardashevskiy pnv_pci_unlink_table_and_group(table_group->tables[num], table_group); 2153b5926430SAlexey Kardashevskiy 2154b5926430SAlexey Kardashevskiy return ret; 2155b5926430SAlexey Kardashevskiy } 2156b5926430SAlexey Kardashevskiy #endif 2157b5926430SAlexey Kardashevskiy 2158f87a8864SAlexey Kardashevskiy #ifdef CONFIG_IOMMU_API 215900547193SAlexey Kardashevskiy static unsigned long pnv_pci_ioda2_get_table_size(__u32 page_shift, 216000547193SAlexey Kardashevskiy __u64 window_size, __u32 levels) 216100547193SAlexey Kardashevskiy { 216200547193SAlexey Kardashevskiy unsigned long bytes = 0; 216300547193SAlexey Kardashevskiy const unsigned window_shift = ilog2(window_size); 216400547193SAlexey Kardashevskiy unsigned entries_shift = window_shift - page_shift; 216500547193SAlexey Kardashevskiy unsigned table_shift = entries_shift + 3; 216600547193SAlexey Kardashevskiy unsigned long tce_table_size = max(0x1000UL, 1UL << table_shift); 216700547193SAlexey Kardashevskiy unsigned long direct_table_size; 216800547193SAlexey Kardashevskiy 216900547193SAlexey Kardashevskiy if (!levels || (levels > POWERNV_IOMMU_MAX_LEVELS) || 217000547193SAlexey Kardashevskiy (window_size > memory_hotplug_max()) || 217100547193SAlexey Kardashevskiy !is_power_of_2(window_size)) 217200547193SAlexey Kardashevskiy return 0; 217300547193SAlexey Kardashevskiy 217400547193SAlexey Kardashevskiy /* Calculate a direct table size from window_size and levels */ 217500547193SAlexey Kardashevskiy entries_shift = (entries_shift + levels - 1) / levels; 217600547193SAlexey Kardashevskiy table_shift = entries_shift + 3; 217700547193SAlexey Kardashevskiy table_shift = max_t(unsigned, table_shift, PAGE_SHIFT); 217800547193SAlexey Kardashevskiy direct_table_size = 1UL << table_shift; 217900547193SAlexey Kardashevskiy 218000547193SAlexey Kardashevskiy for ( ; levels; --levels) { 218100547193SAlexey Kardashevskiy bytes += _ALIGN_UP(tce_table_size, direct_table_size); 218200547193SAlexey Kardashevskiy 218300547193SAlexey Kardashevskiy tce_table_size /= direct_table_size; 218400547193SAlexey Kardashevskiy tce_table_size <<= 3; 218500547193SAlexey Kardashevskiy tce_table_size = _ALIGN_UP(tce_table_size, direct_table_size); 218600547193SAlexey Kardashevskiy } 218700547193SAlexey Kardashevskiy 218800547193SAlexey Kardashevskiy return bytes; 218900547193SAlexey Kardashevskiy } 219000547193SAlexey Kardashevskiy 2191f87a8864SAlexey Kardashevskiy static void pnv_ioda2_take_ownership(struct iommu_table_group *table_group) 2192cd15b048SBenjamin Herrenschmidt { 2193f87a8864SAlexey Kardashevskiy struct pnv_ioda_pe *pe = container_of(table_group, struct pnv_ioda_pe, 2194f87a8864SAlexey Kardashevskiy table_group); 219546d3e1e1SAlexey Kardashevskiy /* Store @tbl as pnv_pci_ioda2_unset_window() resets it */ 219646d3e1e1SAlexey Kardashevskiy struct iommu_table *tbl = pe->table_group.tables[0]; 2197cd15b048SBenjamin Herrenschmidt 2198f87a8864SAlexey Kardashevskiy pnv_pci_ioda2_set_bypass(pe, false); 219946d3e1e1SAlexey Kardashevskiy pnv_pci_ioda2_unset_window(&pe->table_group, 0); 220046d3e1e1SAlexey Kardashevskiy pnv_ioda2_table_free(tbl); 2201cd15b048SBenjamin Herrenschmidt } 2202cd15b048SBenjamin Herrenschmidt 2203f87a8864SAlexey Kardashevskiy static void pnv_ioda2_release_ownership(struct iommu_table_group *table_group) 2204f87a8864SAlexey Kardashevskiy { 2205f87a8864SAlexey Kardashevskiy struct pnv_ioda_pe *pe = container_of(table_group, struct pnv_ioda_pe, 2206f87a8864SAlexey Kardashevskiy table_group); 2207f87a8864SAlexey Kardashevskiy 220846d3e1e1SAlexey Kardashevskiy pnv_pci_ioda2_setup_default_config(pe); 2209f87a8864SAlexey Kardashevskiy } 2210f87a8864SAlexey Kardashevskiy 2211f87a8864SAlexey Kardashevskiy static struct iommu_table_group_ops pnv_pci_ioda2_ops = { 221200547193SAlexey Kardashevskiy .get_table_size = pnv_pci_ioda2_get_table_size, 22134793d65dSAlexey Kardashevskiy .create_table = pnv_pci_ioda2_create_table, 22144793d65dSAlexey Kardashevskiy .set_window = pnv_pci_ioda2_set_window, 22154793d65dSAlexey Kardashevskiy .unset_window = pnv_pci_ioda2_unset_window, 2216f87a8864SAlexey Kardashevskiy .take_ownership = pnv_ioda2_take_ownership, 2217f87a8864SAlexey Kardashevskiy .release_ownership = pnv_ioda2_release_ownership, 2218f87a8864SAlexey Kardashevskiy }; 2219f87a8864SAlexey Kardashevskiy #endif 2220f87a8864SAlexey Kardashevskiy 22215780fb04SAlexey Kardashevskiy static void pnv_pci_ioda_setup_opal_tce_kill(struct pnv_phb *phb) 22225780fb04SAlexey Kardashevskiy { 22235780fb04SAlexey Kardashevskiy const __be64 *swinvp; 22245780fb04SAlexey Kardashevskiy 22255780fb04SAlexey Kardashevskiy /* OPAL variant of PHB3 invalidated TCEs */ 22265780fb04SAlexey Kardashevskiy swinvp = of_get_property(phb->hose->dn, "ibm,opal-tce-kill", NULL); 22275780fb04SAlexey Kardashevskiy if (!swinvp) 22285780fb04SAlexey Kardashevskiy return; 22295780fb04SAlexey Kardashevskiy 22305780fb04SAlexey Kardashevskiy phb->ioda.tce_inval_reg_phys = be64_to_cpup(swinvp); 22315780fb04SAlexey Kardashevskiy phb->ioda.tce_inval_reg = ioremap(phb->ioda.tce_inval_reg_phys, 8); 22325780fb04SAlexey Kardashevskiy } 22335780fb04SAlexey Kardashevskiy 2234bbb845c4SAlexey Kardashevskiy static __be64 *pnv_pci_ioda2_table_do_alloc_pages(int nid, unsigned shift, 2235bbb845c4SAlexey Kardashevskiy unsigned levels, unsigned long limit, 2236bbb845c4SAlexey Kardashevskiy unsigned long *current_offset) 2237aca6913fSAlexey Kardashevskiy { 2238aca6913fSAlexey Kardashevskiy struct page *tce_mem = NULL; 2239bbb845c4SAlexey Kardashevskiy __be64 *addr, *tmp; 2240aca6913fSAlexey Kardashevskiy unsigned order = max_t(unsigned, shift, PAGE_SHIFT) - PAGE_SHIFT; 2241bbb845c4SAlexey Kardashevskiy unsigned long allocated = 1UL << (order + PAGE_SHIFT); 2242bbb845c4SAlexey Kardashevskiy unsigned entries = 1UL << (shift - 3); 2243bbb845c4SAlexey Kardashevskiy long i; 2244aca6913fSAlexey Kardashevskiy 2245aca6913fSAlexey Kardashevskiy tce_mem = alloc_pages_node(nid, GFP_KERNEL, order); 2246aca6913fSAlexey Kardashevskiy if (!tce_mem) { 2247aca6913fSAlexey Kardashevskiy pr_err("Failed to allocate a TCE memory, order=%d\n", order); 2248aca6913fSAlexey Kardashevskiy return NULL; 2249aca6913fSAlexey Kardashevskiy } 2250aca6913fSAlexey Kardashevskiy addr = page_address(tce_mem); 2251bbb845c4SAlexey Kardashevskiy memset(addr, 0, allocated); 2252bbb845c4SAlexey Kardashevskiy 2253bbb845c4SAlexey Kardashevskiy --levels; 2254bbb845c4SAlexey Kardashevskiy if (!levels) { 2255bbb845c4SAlexey Kardashevskiy *current_offset += allocated; 2256bbb845c4SAlexey Kardashevskiy return addr; 2257bbb845c4SAlexey Kardashevskiy } 2258bbb845c4SAlexey Kardashevskiy 2259bbb845c4SAlexey Kardashevskiy for (i = 0; i < entries; ++i) { 2260bbb845c4SAlexey Kardashevskiy tmp = pnv_pci_ioda2_table_do_alloc_pages(nid, shift, 2261bbb845c4SAlexey Kardashevskiy levels, limit, current_offset); 2262bbb845c4SAlexey Kardashevskiy if (!tmp) 2263bbb845c4SAlexey Kardashevskiy break; 2264bbb845c4SAlexey Kardashevskiy 2265bbb845c4SAlexey Kardashevskiy addr[i] = cpu_to_be64(__pa(tmp) | 2266bbb845c4SAlexey Kardashevskiy TCE_PCI_READ | TCE_PCI_WRITE); 2267bbb845c4SAlexey Kardashevskiy 2268bbb845c4SAlexey Kardashevskiy if (*current_offset >= limit) 2269bbb845c4SAlexey Kardashevskiy break; 2270bbb845c4SAlexey Kardashevskiy } 2271aca6913fSAlexey Kardashevskiy 2272aca6913fSAlexey Kardashevskiy return addr; 2273aca6913fSAlexey Kardashevskiy } 2274aca6913fSAlexey Kardashevskiy 2275bbb845c4SAlexey Kardashevskiy static void pnv_pci_ioda2_table_do_free_pages(__be64 *addr, 2276bbb845c4SAlexey Kardashevskiy unsigned long size, unsigned level); 2277bbb845c4SAlexey Kardashevskiy 2278aca6913fSAlexey Kardashevskiy static long pnv_pci_ioda2_table_alloc_pages(int nid, __u64 bus_offset, 2279bbb845c4SAlexey Kardashevskiy __u32 page_shift, __u64 window_size, __u32 levels, 2280bbb845c4SAlexey Kardashevskiy struct iommu_table *tbl) 2281aca6913fSAlexey Kardashevskiy { 2282aca6913fSAlexey Kardashevskiy void *addr; 2283bbb845c4SAlexey Kardashevskiy unsigned long offset = 0, level_shift; 2284aca6913fSAlexey Kardashevskiy const unsigned window_shift = ilog2(window_size); 2285aca6913fSAlexey Kardashevskiy unsigned entries_shift = window_shift - page_shift; 2286aca6913fSAlexey Kardashevskiy unsigned table_shift = max_t(unsigned, entries_shift + 3, PAGE_SHIFT); 2287aca6913fSAlexey Kardashevskiy const unsigned long tce_table_size = 1UL << table_shift; 2288aca6913fSAlexey Kardashevskiy 2289bbb845c4SAlexey Kardashevskiy if (!levels || (levels > POWERNV_IOMMU_MAX_LEVELS)) 2290bbb845c4SAlexey Kardashevskiy return -EINVAL; 2291bbb845c4SAlexey Kardashevskiy 2292aca6913fSAlexey Kardashevskiy if ((window_size > memory_hotplug_max()) || !is_power_of_2(window_size)) 2293aca6913fSAlexey Kardashevskiy return -EINVAL; 2294aca6913fSAlexey Kardashevskiy 2295bbb845c4SAlexey Kardashevskiy /* Adjust direct table size from window_size and levels */ 2296bbb845c4SAlexey Kardashevskiy entries_shift = (entries_shift + levels - 1) / levels; 2297bbb845c4SAlexey Kardashevskiy level_shift = entries_shift + 3; 2298bbb845c4SAlexey Kardashevskiy level_shift = max_t(unsigned, level_shift, PAGE_SHIFT); 2299bbb845c4SAlexey Kardashevskiy 2300aca6913fSAlexey Kardashevskiy /* Allocate TCE table */ 2301bbb845c4SAlexey Kardashevskiy addr = pnv_pci_ioda2_table_do_alloc_pages(nid, level_shift, 2302bbb845c4SAlexey Kardashevskiy levels, tce_table_size, &offset); 2303bbb845c4SAlexey Kardashevskiy 2304bbb845c4SAlexey Kardashevskiy /* addr==NULL means that the first level allocation failed */ 2305aca6913fSAlexey Kardashevskiy if (!addr) 2306aca6913fSAlexey Kardashevskiy return -ENOMEM; 2307aca6913fSAlexey Kardashevskiy 2308bbb845c4SAlexey Kardashevskiy /* 2309bbb845c4SAlexey Kardashevskiy * First level was allocated but some lower level failed as 2310bbb845c4SAlexey Kardashevskiy * we did not allocate as much as we wanted, 2311bbb845c4SAlexey Kardashevskiy * release partially allocated table. 2312bbb845c4SAlexey Kardashevskiy */ 2313bbb845c4SAlexey Kardashevskiy if (offset < tce_table_size) { 2314bbb845c4SAlexey Kardashevskiy pnv_pci_ioda2_table_do_free_pages(addr, 2315bbb845c4SAlexey Kardashevskiy 1ULL << (level_shift - 3), levels - 1); 2316bbb845c4SAlexey Kardashevskiy return -ENOMEM; 2317bbb845c4SAlexey Kardashevskiy } 2318bbb845c4SAlexey Kardashevskiy 2319aca6913fSAlexey Kardashevskiy /* Setup linux iommu table */ 2320aca6913fSAlexey Kardashevskiy pnv_pci_setup_iommu_table(tbl, addr, tce_table_size, bus_offset, 2321aca6913fSAlexey Kardashevskiy page_shift); 2322bbb845c4SAlexey Kardashevskiy tbl->it_level_size = 1ULL << (level_shift - 3); 2323bbb845c4SAlexey Kardashevskiy tbl->it_indirect_levels = levels - 1; 232400547193SAlexey Kardashevskiy tbl->it_allocated_size = offset; 2325aca6913fSAlexey Kardashevskiy 2326aca6913fSAlexey Kardashevskiy pr_devel("Created TCE table: ws=%08llx ts=%lx @%08llx\n", 2327aca6913fSAlexey Kardashevskiy window_size, tce_table_size, bus_offset); 2328aca6913fSAlexey Kardashevskiy 2329aca6913fSAlexey Kardashevskiy return 0; 2330aca6913fSAlexey Kardashevskiy } 2331aca6913fSAlexey Kardashevskiy 2332bbb845c4SAlexey Kardashevskiy static void pnv_pci_ioda2_table_do_free_pages(__be64 *addr, 2333bbb845c4SAlexey Kardashevskiy unsigned long size, unsigned level) 2334bbb845c4SAlexey Kardashevskiy { 2335bbb845c4SAlexey Kardashevskiy const unsigned long addr_ul = (unsigned long) addr & 2336bbb845c4SAlexey Kardashevskiy ~(TCE_PCI_READ | TCE_PCI_WRITE); 2337bbb845c4SAlexey Kardashevskiy 2338bbb845c4SAlexey Kardashevskiy if (level) { 2339bbb845c4SAlexey Kardashevskiy long i; 2340bbb845c4SAlexey Kardashevskiy u64 *tmp = (u64 *) addr_ul; 2341bbb845c4SAlexey Kardashevskiy 2342bbb845c4SAlexey Kardashevskiy for (i = 0; i < size; ++i) { 2343bbb845c4SAlexey Kardashevskiy unsigned long hpa = be64_to_cpu(tmp[i]); 2344bbb845c4SAlexey Kardashevskiy 2345bbb845c4SAlexey Kardashevskiy if (!(hpa & (TCE_PCI_READ | TCE_PCI_WRITE))) 2346bbb845c4SAlexey Kardashevskiy continue; 2347bbb845c4SAlexey Kardashevskiy 2348bbb845c4SAlexey Kardashevskiy pnv_pci_ioda2_table_do_free_pages(__va(hpa), size, 2349bbb845c4SAlexey Kardashevskiy level - 1); 2350bbb845c4SAlexey Kardashevskiy } 2351bbb845c4SAlexey Kardashevskiy } 2352bbb845c4SAlexey Kardashevskiy 2353bbb845c4SAlexey Kardashevskiy free_pages(addr_ul, get_order(size << 3)); 2354bbb845c4SAlexey Kardashevskiy } 2355bbb845c4SAlexey Kardashevskiy 2356aca6913fSAlexey Kardashevskiy static void pnv_pci_ioda2_table_free_pages(struct iommu_table *tbl) 2357aca6913fSAlexey Kardashevskiy { 2358bbb845c4SAlexey Kardashevskiy const unsigned long size = tbl->it_indirect_levels ? 2359bbb845c4SAlexey Kardashevskiy tbl->it_level_size : tbl->it_size; 2360bbb845c4SAlexey Kardashevskiy 2361aca6913fSAlexey Kardashevskiy if (!tbl->it_size) 2362aca6913fSAlexey Kardashevskiy return; 2363aca6913fSAlexey Kardashevskiy 2364bbb845c4SAlexey Kardashevskiy pnv_pci_ioda2_table_do_free_pages((__be64 *)tbl->it_base, size, 2365bbb845c4SAlexey Kardashevskiy tbl->it_indirect_levels); 2366aca6913fSAlexey Kardashevskiy } 2367aca6913fSAlexey Kardashevskiy 2368373f5657SGavin Shan static void pnv_pci_ioda2_setup_dma_pe(struct pnv_phb *phb, 2369373f5657SGavin Shan struct pnv_ioda_pe *pe) 2370373f5657SGavin Shan { 2371373f5657SGavin Shan int64_t rc; 2372373f5657SGavin Shan 2373373f5657SGavin Shan /* We shouldn't already have a 32-bit DMA associated */ 2374373f5657SGavin Shan if (WARN_ON(pe->tce32_seg >= 0)) 2375373f5657SGavin Shan return; 2376373f5657SGavin Shan 2377f87a8864SAlexey Kardashevskiy /* TVE #1 is selected by PCI address bit 59 */ 2378f87a8864SAlexey Kardashevskiy pe->tce_bypass_base = 1ull << 59; 2379f87a8864SAlexey Kardashevskiy 2380b348aa65SAlexey Kardashevskiy iommu_register_group(&pe->table_group, phb->hose->global_number, 2381b348aa65SAlexey Kardashevskiy pe->pe_number); 2382c5773822SAlexey Kardashevskiy 2383373f5657SGavin Shan /* The PE will reserve all possible 32-bits space */ 2384373f5657SGavin Shan pe->tce32_seg = 0; 2385373f5657SGavin Shan pe_info(pe, "Setting up 32-bit TCE table at 0..%08x\n", 2386aca6913fSAlexey Kardashevskiy phb->ioda.m32_pci_base); 2387373f5657SGavin Shan 2388e5aad1e6SAlexey Kardashevskiy /* Setup linux iommu table */ 23894793d65dSAlexey Kardashevskiy pe->table_group.tce32_start = 0; 23904793d65dSAlexey Kardashevskiy pe->table_group.tce32_size = phb->ioda.m32_pci_base; 23914793d65dSAlexey Kardashevskiy pe->table_group.max_dynamic_windows_supported = 23924793d65dSAlexey Kardashevskiy IOMMU_TABLE_GROUP_MAX_TABLES; 23934793d65dSAlexey Kardashevskiy pe->table_group.max_levels = POWERNV_IOMMU_MAX_LEVELS; 23944793d65dSAlexey Kardashevskiy pe->table_group.pgsizes = SZ_4K | SZ_64K | SZ_16M; 2395e5aad1e6SAlexey Kardashevskiy #ifdef CONFIG_IOMMU_API 2396e5aad1e6SAlexey Kardashevskiy pe->table_group.ops = &pnv_pci_ioda2_ops; 2397e5aad1e6SAlexey Kardashevskiy #endif 2398e5aad1e6SAlexey Kardashevskiy 239946d3e1e1SAlexey Kardashevskiy rc = pnv_pci_ioda2_setup_default_config(pe); 2400373f5657SGavin Shan if (rc) { 2401373f5657SGavin Shan if (pe->tce32_seg >= 0) 2402373f5657SGavin Shan pe->tce32_seg = -1; 240346d3e1e1SAlexey Kardashevskiy return; 24040eaf4defSAlexey Kardashevskiy } 240546d3e1e1SAlexey Kardashevskiy 240646d3e1e1SAlexey Kardashevskiy if (pe->flags & PNV_IODA_PE_DEV) 240746d3e1e1SAlexey Kardashevskiy iommu_add_device(&pe->pdev->dev); 240846d3e1e1SAlexey Kardashevskiy else if (pe->flags & (PNV_IODA_PE_BUS | PNV_IODA_PE_BUS_ALL)) 240946d3e1e1SAlexey Kardashevskiy pnv_ioda_setup_bus_dma(pe, pe->pbus); 2410373f5657SGavin Shan } 2411373f5657SGavin Shan 2412cad5cef6SGreg Kroah-Hartman static void pnv_ioda_setup_dma(struct pnv_phb *phb) 2413184cd4a3SBenjamin Herrenschmidt { 2414184cd4a3SBenjamin Herrenschmidt struct pci_controller *hose = phb->hose; 2415184cd4a3SBenjamin Herrenschmidt unsigned int residual, remaining, segs, tw, base; 2416184cd4a3SBenjamin Herrenschmidt struct pnv_ioda_pe *pe; 2417184cd4a3SBenjamin Herrenschmidt 2418184cd4a3SBenjamin Herrenschmidt /* If we have more PE# than segments available, hand out one 2419184cd4a3SBenjamin Herrenschmidt * per PE until we run out and let the rest fail. If not, 2420184cd4a3SBenjamin Herrenschmidt * then we assign at least one segment per PE, plus more based 2421184cd4a3SBenjamin Herrenschmidt * on the amount of devices under that PE 2422184cd4a3SBenjamin Herrenschmidt */ 2423184cd4a3SBenjamin Herrenschmidt if (phb->ioda.dma_pe_count > phb->ioda.tce32_count) 2424184cd4a3SBenjamin Herrenschmidt residual = 0; 2425184cd4a3SBenjamin Herrenschmidt else 2426184cd4a3SBenjamin Herrenschmidt residual = phb->ioda.tce32_count - 2427184cd4a3SBenjamin Herrenschmidt phb->ioda.dma_pe_count; 2428184cd4a3SBenjamin Herrenschmidt 2429184cd4a3SBenjamin Herrenschmidt pr_info("PCI: Domain %04x has %ld available 32-bit DMA segments\n", 2430184cd4a3SBenjamin Herrenschmidt hose->global_number, phb->ioda.tce32_count); 2431184cd4a3SBenjamin Herrenschmidt pr_info("PCI: %d PE# for a total weight of %d\n", 2432184cd4a3SBenjamin Herrenschmidt phb->ioda.dma_pe_count, phb->ioda.dma_weight); 2433184cd4a3SBenjamin Herrenschmidt 24345780fb04SAlexey Kardashevskiy pnv_pci_ioda_setup_opal_tce_kill(phb); 24355780fb04SAlexey Kardashevskiy 2436184cd4a3SBenjamin Herrenschmidt /* Walk our PE list and configure their DMA segments, hand them 2437184cd4a3SBenjamin Herrenschmidt * out one base segment plus any residual segments based on 2438184cd4a3SBenjamin Herrenschmidt * weight 2439184cd4a3SBenjamin Herrenschmidt */ 2440184cd4a3SBenjamin Herrenschmidt remaining = phb->ioda.tce32_count; 2441184cd4a3SBenjamin Herrenschmidt tw = phb->ioda.dma_weight; 2442184cd4a3SBenjamin Herrenschmidt base = 0; 24437ebdf956SGavin Shan list_for_each_entry(pe, &phb->ioda.pe_dma_list, dma_link) { 2444184cd4a3SBenjamin Herrenschmidt if (!pe->dma_weight) 2445184cd4a3SBenjamin Herrenschmidt continue; 2446184cd4a3SBenjamin Herrenschmidt if (!remaining) { 2447184cd4a3SBenjamin Herrenschmidt pe_warn(pe, "No DMA32 resources available\n"); 2448184cd4a3SBenjamin Herrenschmidt continue; 2449184cd4a3SBenjamin Herrenschmidt } 2450184cd4a3SBenjamin Herrenschmidt segs = 1; 2451184cd4a3SBenjamin Herrenschmidt if (residual) { 2452184cd4a3SBenjamin Herrenschmidt segs += ((pe->dma_weight * residual) + (tw / 2)) / tw; 2453184cd4a3SBenjamin Herrenschmidt if (segs > remaining) 2454184cd4a3SBenjamin Herrenschmidt segs = remaining; 2455184cd4a3SBenjamin Herrenschmidt } 2456373f5657SGavin Shan 2457373f5657SGavin Shan /* 2458373f5657SGavin Shan * For IODA2 compliant PHB3, we needn't care about the weight. 2459373f5657SGavin Shan * The all available 32-bits DMA space will be assigned to 2460373f5657SGavin Shan * the specific PE. 2461373f5657SGavin Shan */ 2462373f5657SGavin Shan if (phb->type == PNV_PHB_IODA1) { 2463184cd4a3SBenjamin Herrenschmidt pe_info(pe, "DMA weight %d, assigned %d DMA32 segments\n", 2464184cd4a3SBenjamin Herrenschmidt pe->dma_weight, segs); 2465184cd4a3SBenjamin Herrenschmidt pnv_pci_ioda_setup_dma_pe(phb, pe, base, segs); 2466373f5657SGavin Shan } else { 2467373f5657SGavin Shan pe_info(pe, "Assign DMA32 space\n"); 2468373f5657SGavin Shan segs = 0; 2469373f5657SGavin Shan pnv_pci_ioda2_setup_dma_pe(phb, pe); 2470373f5657SGavin Shan } 2471373f5657SGavin Shan 2472184cd4a3SBenjamin Herrenschmidt remaining -= segs; 2473184cd4a3SBenjamin Herrenschmidt base += segs; 2474184cd4a3SBenjamin Herrenschmidt } 2475184cd4a3SBenjamin Herrenschmidt } 2476184cd4a3SBenjamin Herrenschmidt 2477184cd4a3SBenjamin Herrenschmidt #ifdef CONFIG_PCI_MSI 2478137436c9SGavin Shan static void pnv_ioda2_msi_eoi(struct irq_data *d) 2479137436c9SGavin Shan { 2480137436c9SGavin Shan unsigned int hw_irq = (unsigned int)irqd_to_hwirq(d); 2481137436c9SGavin Shan struct irq_chip *chip = irq_data_get_irq_chip(d); 2482137436c9SGavin Shan struct pnv_phb *phb = container_of(chip, struct pnv_phb, 2483137436c9SGavin Shan ioda.irq_chip); 2484137436c9SGavin Shan int64_t rc; 2485137436c9SGavin Shan 2486137436c9SGavin Shan rc = opal_pci_msi_eoi(phb->opal_id, hw_irq); 2487137436c9SGavin Shan WARN_ON_ONCE(rc); 2488137436c9SGavin Shan 2489137436c9SGavin Shan icp_native_eoi(d); 2490137436c9SGavin Shan } 2491137436c9SGavin Shan 2492fd9a1c26SIan Munsie 2493fd9a1c26SIan Munsie static void set_msi_irq_chip(struct pnv_phb *phb, unsigned int virq) 2494fd9a1c26SIan Munsie { 2495fd9a1c26SIan Munsie struct irq_data *idata; 2496fd9a1c26SIan Munsie struct irq_chip *ichip; 2497fd9a1c26SIan Munsie 2498fd9a1c26SIan Munsie if (phb->type != PNV_PHB_IODA2) 2499fd9a1c26SIan Munsie return; 2500fd9a1c26SIan Munsie 2501fd9a1c26SIan Munsie if (!phb->ioda.irq_chip_init) { 2502fd9a1c26SIan Munsie /* 2503fd9a1c26SIan Munsie * First time we setup an MSI IRQ, we need to setup the 2504fd9a1c26SIan Munsie * corresponding IRQ chip to route correctly. 2505fd9a1c26SIan Munsie */ 2506fd9a1c26SIan Munsie idata = irq_get_irq_data(virq); 2507fd9a1c26SIan Munsie ichip = irq_data_get_irq_chip(idata); 2508fd9a1c26SIan Munsie phb->ioda.irq_chip_init = 1; 2509fd9a1c26SIan Munsie phb->ioda.irq_chip = *ichip; 2510fd9a1c26SIan Munsie phb->ioda.irq_chip.irq_eoi = pnv_ioda2_msi_eoi; 2511fd9a1c26SIan Munsie } 2512fd9a1c26SIan Munsie irq_set_chip(virq, &phb->ioda.irq_chip); 2513fd9a1c26SIan Munsie } 2514fd9a1c26SIan Munsie 251580c49c7eSIan Munsie #ifdef CONFIG_CXL_BASE 251680c49c7eSIan Munsie 25176f963ec2SRyan Grimm struct device_node *pnv_pci_get_phb_node(struct pci_dev *dev) 251880c49c7eSIan Munsie { 251980c49c7eSIan Munsie struct pci_controller *hose = pci_bus_to_host(dev->bus); 252080c49c7eSIan Munsie 25216f963ec2SRyan Grimm return of_node_get(hose->dn); 252280c49c7eSIan Munsie } 25236f963ec2SRyan Grimm EXPORT_SYMBOL(pnv_pci_get_phb_node); 252480c49c7eSIan Munsie 25251212aa1cSRyan Grimm int pnv_phb_to_cxl_mode(struct pci_dev *dev, uint64_t mode) 252680c49c7eSIan Munsie { 252780c49c7eSIan Munsie struct pci_controller *hose = pci_bus_to_host(dev->bus); 252880c49c7eSIan Munsie struct pnv_phb *phb = hose->private_data; 252980c49c7eSIan Munsie struct pnv_ioda_pe *pe; 253080c49c7eSIan Munsie int rc; 253180c49c7eSIan Munsie 253280c49c7eSIan Munsie pe = pnv_ioda_get_pe(dev); 253380c49c7eSIan Munsie if (!pe) 253480c49c7eSIan Munsie return -ENODEV; 253580c49c7eSIan Munsie 253680c49c7eSIan Munsie pe_info(pe, "Switching PHB to CXL\n"); 253780c49c7eSIan Munsie 25381212aa1cSRyan Grimm rc = opal_pci_set_phb_cxl_mode(phb->opal_id, mode, pe->pe_number); 253980c49c7eSIan Munsie if (rc) 254080c49c7eSIan Munsie dev_err(&dev->dev, "opal_pci_set_phb_cxl_mode failed: %i\n", rc); 254180c49c7eSIan Munsie 254280c49c7eSIan Munsie return rc; 254380c49c7eSIan Munsie } 25441212aa1cSRyan Grimm EXPORT_SYMBOL(pnv_phb_to_cxl_mode); 254580c49c7eSIan Munsie 254680c49c7eSIan Munsie /* Find PHB for cxl dev and allocate MSI hwirqs? 254780c49c7eSIan Munsie * Returns the absolute hardware IRQ number 254880c49c7eSIan Munsie */ 254980c49c7eSIan Munsie int pnv_cxl_alloc_hwirqs(struct pci_dev *dev, int num) 255080c49c7eSIan Munsie { 255180c49c7eSIan Munsie struct pci_controller *hose = pci_bus_to_host(dev->bus); 255280c49c7eSIan Munsie struct pnv_phb *phb = hose->private_data; 255380c49c7eSIan Munsie int hwirq = msi_bitmap_alloc_hwirqs(&phb->msi_bmp, num); 255480c49c7eSIan Munsie 255580c49c7eSIan Munsie if (hwirq < 0) { 255680c49c7eSIan Munsie dev_warn(&dev->dev, "Failed to find a free MSI\n"); 255780c49c7eSIan Munsie return -ENOSPC; 255880c49c7eSIan Munsie } 255980c49c7eSIan Munsie 256080c49c7eSIan Munsie return phb->msi_base + hwirq; 256180c49c7eSIan Munsie } 256280c49c7eSIan Munsie EXPORT_SYMBOL(pnv_cxl_alloc_hwirqs); 256380c49c7eSIan Munsie 256480c49c7eSIan Munsie void pnv_cxl_release_hwirqs(struct pci_dev *dev, int hwirq, int num) 256580c49c7eSIan Munsie { 256680c49c7eSIan Munsie struct pci_controller *hose = pci_bus_to_host(dev->bus); 256780c49c7eSIan Munsie struct pnv_phb *phb = hose->private_data; 256880c49c7eSIan Munsie 256980c49c7eSIan Munsie msi_bitmap_free_hwirqs(&phb->msi_bmp, hwirq - phb->msi_base, num); 257080c49c7eSIan Munsie } 257180c49c7eSIan Munsie EXPORT_SYMBOL(pnv_cxl_release_hwirqs); 257280c49c7eSIan Munsie 257380c49c7eSIan Munsie void pnv_cxl_release_hwirq_ranges(struct cxl_irq_ranges *irqs, 257480c49c7eSIan Munsie struct pci_dev *dev) 257580c49c7eSIan Munsie { 257680c49c7eSIan Munsie struct pci_controller *hose = pci_bus_to_host(dev->bus); 257780c49c7eSIan Munsie struct pnv_phb *phb = hose->private_data; 257880c49c7eSIan Munsie int i, hwirq; 257980c49c7eSIan Munsie 258080c49c7eSIan Munsie for (i = 1; i < CXL_IRQ_RANGES; i++) { 258180c49c7eSIan Munsie if (!irqs->range[i]) 258280c49c7eSIan Munsie continue; 258380c49c7eSIan Munsie pr_devel("cxl release irq range 0x%x: offset: 0x%lx limit: %ld\n", 258480c49c7eSIan Munsie i, irqs->offset[i], 258580c49c7eSIan Munsie irqs->range[i]); 258680c49c7eSIan Munsie hwirq = irqs->offset[i] - phb->msi_base; 258780c49c7eSIan Munsie msi_bitmap_free_hwirqs(&phb->msi_bmp, hwirq, 258880c49c7eSIan Munsie irqs->range[i]); 258980c49c7eSIan Munsie } 259080c49c7eSIan Munsie } 259180c49c7eSIan Munsie EXPORT_SYMBOL(pnv_cxl_release_hwirq_ranges); 259280c49c7eSIan Munsie 259380c49c7eSIan Munsie int pnv_cxl_alloc_hwirq_ranges(struct cxl_irq_ranges *irqs, 259480c49c7eSIan Munsie struct pci_dev *dev, int num) 259580c49c7eSIan Munsie { 259680c49c7eSIan Munsie struct pci_controller *hose = pci_bus_to_host(dev->bus); 259780c49c7eSIan Munsie struct pnv_phb *phb = hose->private_data; 259880c49c7eSIan Munsie int i, hwirq, try; 259980c49c7eSIan Munsie 260080c49c7eSIan Munsie memset(irqs, 0, sizeof(struct cxl_irq_ranges)); 260180c49c7eSIan Munsie 260280c49c7eSIan Munsie /* 0 is reserved for the multiplexed PSL DSI interrupt */ 260380c49c7eSIan Munsie for (i = 1; i < CXL_IRQ_RANGES && num; i++) { 260480c49c7eSIan Munsie try = num; 260580c49c7eSIan Munsie while (try) { 260680c49c7eSIan Munsie hwirq = msi_bitmap_alloc_hwirqs(&phb->msi_bmp, try); 260780c49c7eSIan Munsie if (hwirq >= 0) 260880c49c7eSIan Munsie break; 260980c49c7eSIan Munsie try /= 2; 261080c49c7eSIan Munsie } 261180c49c7eSIan Munsie if (!try) 261280c49c7eSIan Munsie goto fail; 261380c49c7eSIan Munsie 261480c49c7eSIan Munsie irqs->offset[i] = phb->msi_base + hwirq; 261580c49c7eSIan Munsie irqs->range[i] = try; 261680c49c7eSIan Munsie pr_devel("cxl alloc irq range 0x%x: offset: 0x%lx limit: %li\n", 261780c49c7eSIan Munsie i, irqs->offset[i], irqs->range[i]); 261880c49c7eSIan Munsie num -= try; 261980c49c7eSIan Munsie } 262080c49c7eSIan Munsie if (num) 262180c49c7eSIan Munsie goto fail; 262280c49c7eSIan Munsie 262380c49c7eSIan Munsie return 0; 262480c49c7eSIan Munsie fail: 262580c49c7eSIan Munsie pnv_cxl_release_hwirq_ranges(irqs, dev); 262680c49c7eSIan Munsie return -ENOSPC; 262780c49c7eSIan Munsie } 262880c49c7eSIan Munsie EXPORT_SYMBOL(pnv_cxl_alloc_hwirq_ranges); 262980c49c7eSIan Munsie 263080c49c7eSIan Munsie int pnv_cxl_get_irq_count(struct pci_dev *dev) 263180c49c7eSIan Munsie { 263280c49c7eSIan Munsie struct pci_controller *hose = pci_bus_to_host(dev->bus); 263380c49c7eSIan Munsie struct pnv_phb *phb = hose->private_data; 263480c49c7eSIan Munsie 263580c49c7eSIan Munsie return phb->msi_bmp.irq_count; 263680c49c7eSIan Munsie } 263780c49c7eSIan Munsie EXPORT_SYMBOL(pnv_cxl_get_irq_count); 263880c49c7eSIan Munsie 263980c49c7eSIan Munsie int pnv_cxl_ioda_msi_setup(struct pci_dev *dev, unsigned int hwirq, 264080c49c7eSIan Munsie unsigned int virq) 264180c49c7eSIan Munsie { 264280c49c7eSIan Munsie struct pci_controller *hose = pci_bus_to_host(dev->bus); 264380c49c7eSIan Munsie struct pnv_phb *phb = hose->private_data; 264480c49c7eSIan Munsie unsigned int xive_num = hwirq - phb->msi_base; 264580c49c7eSIan Munsie struct pnv_ioda_pe *pe; 264680c49c7eSIan Munsie int rc; 264780c49c7eSIan Munsie 264880c49c7eSIan Munsie if (!(pe = pnv_ioda_get_pe(dev))) 264980c49c7eSIan Munsie return -ENODEV; 265080c49c7eSIan Munsie 265180c49c7eSIan Munsie /* Assign XIVE to PE */ 265280c49c7eSIan Munsie rc = opal_pci_set_xive_pe(phb->opal_id, pe->pe_number, xive_num); 265380c49c7eSIan Munsie if (rc) { 265480c49c7eSIan Munsie pe_warn(pe, "%s: OPAL error %d setting msi_base 0x%x " 265580c49c7eSIan Munsie "hwirq 0x%x XIVE 0x%x PE\n", 265680c49c7eSIan Munsie pci_name(dev), rc, phb->msi_base, hwirq, xive_num); 265780c49c7eSIan Munsie return -EIO; 265880c49c7eSIan Munsie } 265980c49c7eSIan Munsie set_msi_irq_chip(phb, virq); 266080c49c7eSIan Munsie 266180c49c7eSIan Munsie return 0; 266280c49c7eSIan Munsie } 266380c49c7eSIan Munsie EXPORT_SYMBOL(pnv_cxl_ioda_msi_setup); 266480c49c7eSIan Munsie #endif 266580c49c7eSIan Munsie 2666184cd4a3SBenjamin Herrenschmidt static int pnv_pci_ioda_msi_setup(struct pnv_phb *phb, struct pci_dev *dev, 2667137436c9SGavin Shan unsigned int hwirq, unsigned int virq, 2668137436c9SGavin Shan unsigned int is_64, struct msi_msg *msg) 2669184cd4a3SBenjamin Herrenschmidt { 2670184cd4a3SBenjamin Herrenschmidt struct pnv_ioda_pe *pe = pnv_ioda_get_pe(dev); 2671184cd4a3SBenjamin Herrenschmidt unsigned int xive_num = hwirq - phb->msi_base; 26723a1a4661SBenjamin Herrenschmidt __be32 data; 2673184cd4a3SBenjamin Herrenschmidt int rc; 2674184cd4a3SBenjamin Herrenschmidt 2675184cd4a3SBenjamin Herrenschmidt /* No PE assigned ? bail out ... no MSI for you ! */ 2676184cd4a3SBenjamin Herrenschmidt if (pe == NULL) 2677184cd4a3SBenjamin Herrenschmidt return -ENXIO; 2678184cd4a3SBenjamin Herrenschmidt 2679184cd4a3SBenjamin Herrenschmidt /* Check if we have an MVE */ 2680184cd4a3SBenjamin Herrenschmidt if (pe->mve_number < 0) 2681184cd4a3SBenjamin Herrenschmidt return -ENXIO; 2682184cd4a3SBenjamin Herrenschmidt 2683b72c1f65SBenjamin Herrenschmidt /* Force 32-bit MSI on some broken devices */ 268436074381SBenjamin Herrenschmidt if (dev->no_64bit_msi) 2685b72c1f65SBenjamin Herrenschmidt is_64 = 0; 2686b72c1f65SBenjamin Herrenschmidt 2687184cd4a3SBenjamin Herrenschmidt /* Assign XIVE to PE */ 2688184cd4a3SBenjamin Herrenschmidt rc = opal_pci_set_xive_pe(phb->opal_id, pe->pe_number, xive_num); 2689184cd4a3SBenjamin Herrenschmidt if (rc) { 2690184cd4a3SBenjamin Herrenschmidt pr_warn("%s: OPAL error %d setting XIVE %d PE\n", 2691184cd4a3SBenjamin Herrenschmidt pci_name(dev), rc, xive_num); 2692184cd4a3SBenjamin Herrenschmidt return -EIO; 2693184cd4a3SBenjamin Herrenschmidt } 2694184cd4a3SBenjamin Herrenschmidt 2695184cd4a3SBenjamin Herrenschmidt if (is_64) { 26963a1a4661SBenjamin Herrenschmidt __be64 addr64; 26973a1a4661SBenjamin Herrenschmidt 2698184cd4a3SBenjamin Herrenschmidt rc = opal_get_msi_64(phb->opal_id, pe->mve_number, xive_num, 1, 2699184cd4a3SBenjamin Herrenschmidt &addr64, &data); 2700184cd4a3SBenjamin Herrenschmidt if (rc) { 2701184cd4a3SBenjamin Herrenschmidt pr_warn("%s: OPAL error %d getting 64-bit MSI data\n", 2702184cd4a3SBenjamin Herrenschmidt pci_name(dev), rc); 2703184cd4a3SBenjamin Herrenschmidt return -EIO; 2704184cd4a3SBenjamin Herrenschmidt } 27053a1a4661SBenjamin Herrenschmidt msg->address_hi = be64_to_cpu(addr64) >> 32; 27063a1a4661SBenjamin Herrenschmidt msg->address_lo = be64_to_cpu(addr64) & 0xfffffffful; 2707184cd4a3SBenjamin Herrenschmidt } else { 27083a1a4661SBenjamin Herrenschmidt __be32 addr32; 27093a1a4661SBenjamin Herrenschmidt 2710184cd4a3SBenjamin Herrenschmidt rc = opal_get_msi_32(phb->opal_id, pe->mve_number, xive_num, 1, 2711184cd4a3SBenjamin Herrenschmidt &addr32, &data); 2712184cd4a3SBenjamin Herrenschmidt if (rc) { 2713184cd4a3SBenjamin Herrenschmidt pr_warn("%s: OPAL error %d getting 32-bit MSI data\n", 2714184cd4a3SBenjamin Herrenschmidt pci_name(dev), rc); 2715184cd4a3SBenjamin Herrenschmidt return -EIO; 2716184cd4a3SBenjamin Herrenschmidt } 2717184cd4a3SBenjamin Herrenschmidt msg->address_hi = 0; 27183a1a4661SBenjamin Herrenschmidt msg->address_lo = be32_to_cpu(addr32); 2719184cd4a3SBenjamin Herrenschmidt } 27203a1a4661SBenjamin Herrenschmidt msg->data = be32_to_cpu(data); 2721184cd4a3SBenjamin Herrenschmidt 2722fd9a1c26SIan Munsie set_msi_irq_chip(phb, virq); 2723137436c9SGavin Shan 2724184cd4a3SBenjamin Herrenschmidt pr_devel("%s: %s-bit MSI on hwirq %x (xive #%d)," 2725184cd4a3SBenjamin Herrenschmidt " address=%x_%08x data=%x PE# %d\n", 2726184cd4a3SBenjamin Herrenschmidt pci_name(dev), is_64 ? "64" : "32", hwirq, xive_num, 2727184cd4a3SBenjamin Herrenschmidt msg->address_hi, msg->address_lo, data, pe->pe_number); 2728184cd4a3SBenjamin Herrenschmidt 2729184cd4a3SBenjamin Herrenschmidt return 0; 2730184cd4a3SBenjamin Herrenschmidt } 2731184cd4a3SBenjamin Herrenschmidt 2732184cd4a3SBenjamin Herrenschmidt static void pnv_pci_init_ioda_msis(struct pnv_phb *phb) 2733184cd4a3SBenjamin Herrenschmidt { 2734fb1b55d6SGavin Shan unsigned int count; 2735184cd4a3SBenjamin Herrenschmidt const __be32 *prop = of_get_property(phb->hose->dn, 2736184cd4a3SBenjamin Herrenschmidt "ibm,opal-msi-ranges", NULL); 2737184cd4a3SBenjamin Herrenschmidt if (!prop) { 2738184cd4a3SBenjamin Herrenschmidt /* BML Fallback */ 2739184cd4a3SBenjamin Herrenschmidt prop = of_get_property(phb->hose->dn, "msi-ranges", NULL); 2740184cd4a3SBenjamin Herrenschmidt } 2741184cd4a3SBenjamin Herrenschmidt if (!prop) 2742184cd4a3SBenjamin Herrenschmidt return; 2743184cd4a3SBenjamin Herrenschmidt 2744184cd4a3SBenjamin Herrenschmidt phb->msi_base = be32_to_cpup(prop); 2745fb1b55d6SGavin Shan count = be32_to_cpup(prop + 1); 2746fb1b55d6SGavin Shan if (msi_bitmap_alloc(&phb->msi_bmp, count, phb->hose->dn)) { 2747184cd4a3SBenjamin Herrenschmidt pr_err("PCI %d: Failed to allocate MSI bitmap !\n", 2748184cd4a3SBenjamin Herrenschmidt phb->hose->global_number); 2749184cd4a3SBenjamin Herrenschmidt return; 2750184cd4a3SBenjamin Herrenschmidt } 2751fb1b55d6SGavin Shan 2752184cd4a3SBenjamin Herrenschmidt phb->msi_setup = pnv_pci_ioda_msi_setup; 2753184cd4a3SBenjamin Herrenschmidt phb->msi32_support = 1; 2754184cd4a3SBenjamin Herrenschmidt pr_info(" Allocated bitmap for %d MSIs (base IRQ 0x%x)\n", 2755fb1b55d6SGavin Shan count, phb->msi_base); 2756184cd4a3SBenjamin Herrenschmidt } 2757184cd4a3SBenjamin Herrenschmidt #else 2758184cd4a3SBenjamin Herrenschmidt static void pnv_pci_init_ioda_msis(struct pnv_phb *phb) { } 2759184cd4a3SBenjamin Herrenschmidt #endif /* CONFIG_PCI_MSI */ 2760184cd4a3SBenjamin Herrenschmidt 27616e628c7dSWei Yang #ifdef CONFIG_PCI_IOV 27626e628c7dSWei Yang static void pnv_pci_ioda_fixup_iov_resources(struct pci_dev *pdev) 27636e628c7dSWei Yang { 27646e628c7dSWei Yang struct pci_controller *hose; 27656e628c7dSWei Yang struct pnv_phb *phb; 27666e628c7dSWei Yang struct resource *res; 27676e628c7dSWei Yang int i; 27686e628c7dSWei Yang resource_size_t size; 27696e628c7dSWei Yang struct pci_dn *pdn; 27705b88ec22SWei Yang int mul, total_vfs; 27716e628c7dSWei Yang 27726e628c7dSWei Yang if (!pdev->is_physfn || pdev->is_added) 27736e628c7dSWei Yang return; 27746e628c7dSWei Yang 27756e628c7dSWei Yang hose = pci_bus_to_host(pdev->bus); 27766e628c7dSWei Yang phb = hose->private_data; 27776e628c7dSWei Yang 27786e628c7dSWei Yang pdn = pci_get_pdn(pdev); 27796e628c7dSWei Yang pdn->vfs_expanded = 0; 27806e628c7dSWei Yang 27815b88ec22SWei Yang total_vfs = pci_sriov_get_totalvfs(pdev); 27825b88ec22SWei Yang pdn->m64_per_iov = 1; 27835b88ec22SWei Yang mul = phb->ioda.total_pe; 27845b88ec22SWei Yang 27855b88ec22SWei Yang for (i = 0; i < PCI_SRIOV_NUM_BARS; i++) { 27865b88ec22SWei Yang res = &pdev->resource[i + PCI_IOV_RESOURCES]; 27875b88ec22SWei Yang if (!res->flags || res->parent) 27885b88ec22SWei Yang continue; 27895b88ec22SWei Yang if (!pnv_pci_is_mem_pref_64(res->flags)) { 27905b88ec22SWei Yang dev_warn(&pdev->dev, " non M64 VF BAR%d: %pR\n", 27915b88ec22SWei Yang i, res); 27925b88ec22SWei Yang continue; 27935b88ec22SWei Yang } 27945b88ec22SWei Yang 27955b88ec22SWei Yang size = pci_iov_resource_size(pdev, i + PCI_IOV_RESOURCES); 27965b88ec22SWei Yang 27975b88ec22SWei Yang /* bigger than 64M */ 27985b88ec22SWei Yang if (size > (1 << 26)) { 27995b88ec22SWei Yang dev_info(&pdev->dev, "PowerNV: VF BAR%d: %pR IOV size is bigger than 64M, roundup power2\n", 28005b88ec22SWei Yang i, res); 28015b88ec22SWei Yang pdn->m64_per_iov = M64_PER_IOV; 28025b88ec22SWei Yang mul = roundup_pow_of_two(total_vfs); 28035b88ec22SWei Yang break; 28045b88ec22SWei Yang } 28055b88ec22SWei Yang } 28065b88ec22SWei Yang 28076e628c7dSWei Yang for (i = 0; i < PCI_SRIOV_NUM_BARS; i++) { 28086e628c7dSWei Yang res = &pdev->resource[i + PCI_IOV_RESOURCES]; 28096e628c7dSWei Yang if (!res->flags || res->parent) 28106e628c7dSWei Yang continue; 28116e628c7dSWei Yang if (!pnv_pci_is_mem_pref_64(res->flags)) { 28126e628c7dSWei Yang dev_warn(&pdev->dev, "Skipping expanding VF BAR%d: %pR\n", 28136e628c7dSWei Yang i, res); 28146e628c7dSWei Yang continue; 28156e628c7dSWei Yang } 28166e628c7dSWei Yang 28176e628c7dSWei Yang dev_dbg(&pdev->dev, " Fixing VF BAR%d: %pR to\n", i, res); 28186e628c7dSWei Yang size = pci_iov_resource_size(pdev, i + PCI_IOV_RESOURCES); 28195b88ec22SWei Yang res->end = res->start + size * mul - 1; 28206e628c7dSWei Yang dev_dbg(&pdev->dev, " %pR\n", res); 28216e628c7dSWei Yang dev_info(&pdev->dev, "VF BAR%d: %pR (expanded to %d VFs for PE alignment)", 28225b88ec22SWei Yang i, res, mul); 28236e628c7dSWei Yang } 28245b88ec22SWei Yang pdn->vfs_expanded = mul; 28256e628c7dSWei Yang } 28266e628c7dSWei Yang #endif /* CONFIG_PCI_IOV */ 28276e628c7dSWei Yang 282811685becSGavin Shan /* 282911685becSGavin Shan * This function is supposed to be called on basis of PE from top 283011685becSGavin Shan * to bottom style. So the the I/O or MMIO segment assigned to 283111685becSGavin Shan * parent PE could be overrided by its child PEs if necessary. 283211685becSGavin Shan */ 2833cad5cef6SGreg Kroah-Hartman static void pnv_ioda_setup_pe_seg(struct pci_controller *hose, 283411685becSGavin Shan struct pnv_ioda_pe *pe) 283511685becSGavin Shan { 283611685becSGavin Shan struct pnv_phb *phb = hose->private_data; 283711685becSGavin Shan struct pci_bus_region region; 283811685becSGavin Shan struct resource *res; 283911685becSGavin Shan int i, index; 284011685becSGavin Shan int rc; 284111685becSGavin Shan 284211685becSGavin Shan /* 284311685becSGavin Shan * NOTE: We only care PCI bus based PE for now. For PCI 284411685becSGavin Shan * device based PE, for example SRIOV sensitive VF should 284511685becSGavin Shan * be figured out later. 284611685becSGavin Shan */ 284711685becSGavin Shan BUG_ON(!(pe->flags & (PNV_IODA_PE_BUS | PNV_IODA_PE_BUS_ALL))); 284811685becSGavin Shan 284911685becSGavin Shan pci_bus_for_each_resource(pe->pbus, res, i) { 285011685becSGavin Shan if (!res || !res->flags || 285111685becSGavin Shan res->start > res->end) 285211685becSGavin Shan continue; 285311685becSGavin Shan 285411685becSGavin Shan if (res->flags & IORESOURCE_IO) { 285511685becSGavin Shan region.start = res->start - phb->ioda.io_pci_base; 285611685becSGavin Shan region.end = res->end - phb->ioda.io_pci_base; 285711685becSGavin Shan index = region.start / phb->ioda.io_segsize; 285811685becSGavin Shan 285911685becSGavin Shan while (index < phb->ioda.total_pe && 286011685becSGavin Shan region.start <= region.end) { 286111685becSGavin Shan phb->ioda.io_segmap[index] = pe->pe_number; 286211685becSGavin Shan rc = opal_pci_map_pe_mmio_window(phb->opal_id, 286311685becSGavin Shan pe->pe_number, OPAL_IO_WINDOW_TYPE, 0, index); 286411685becSGavin Shan if (rc != OPAL_SUCCESS) { 286511685becSGavin Shan pr_err("%s: OPAL error %d when mapping IO " 286611685becSGavin Shan "segment #%d to PE#%d\n", 286711685becSGavin Shan __func__, rc, index, pe->pe_number); 286811685becSGavin Shan break; 286911685becSGavin Shan } 287011685becSGavin Shan 287111685becSGavin Shan region.start += phb->ioda.io_segsize; 287211685becSGavin Shan index++; 287311685becSGavin Shan } 2874027fa02fSGavin Shan } else if ((res->flags & IORESOURCE_MEM) && 2875027fa02fSGavin Shan !pnv_pci_is_mem_pref_64(res->flags)) { 287611685becSGavin Shan region.start = res->start - 28773fd47f06SBenjamin Herrenschmidt hose->mem_offset[0] - 287811685becSGavin Shan phb->ioda.m32_pci_base; 287911685becSGavin Shan region.end = res->end - 28803fd47f06SBenjamin Herrenschmidt hose->mem_offset[0] - 288111685becSGavin Shan phb->ioda.m32_pci_base; 288211685becSGavin Shan index = region.start / phb->ioda.m32_segsize; 288311685becSGavin Shan 288411685becSGavin Shan while (index < phb->ioda.total_pe && 288511685becSGavin Shan region.start <= region.end) { 288611685becSGavin Shan phb->ioda.m32_segmap[index] = pe->pe_number; 288711685becSGavin Shan rc = opal_pci_map_pe_mmio_window(phb->opal_id, 288811685becSGavin Shan pe->pe_number, OPAL_M32_WINDOW_TYPE, 0, index); 288911685becSGavin Shan if (rc != OPAL_SUCCESS) { 289011685becSGavin Shan pr_err("%s: OPAL error %d when mapping M32 " 289111685becSGavin Shan "segment#%d to PE#%d", 289211685becSGavin Shan __func__, rc, index, pe->pe_number); 289311685becSGavin Shan break; 289411685becSGavin Shan } 289511685becSGavin Shan 289611685becSGavin Shan region.start += phb->ioda.m32_segsize; 289711685becSGavin Shan index++; 289811685becSGavin Shan } 289911685becSGavin Shan } 290011685becSGavin Shan } 290111685becSGavin Shan } 290211685becSGavin Shan 2903cad5cef6SGreg Kroah-Hartman static void pnv_pci_ioda_setup_seg(void) 290411685becSGavin Shan { 290511685becSGavin Shan struct pci_controller *tmp, *hose; 290611685becSGavin Shan struct pnv_phb *phb; 290711685becSGavin Shan struct pnv_ioda_pe *pe; 290811685becSGavin Shan 290911685becSGavin Shan list_for_each_entry_safe(hose, tmp, &hose_list, list_node) { 291011685becSGavin Shan phb = hose->private_data; 291111685becSGavin Shan list_for_each_entry(pe, &phb->ioda.pe_list, list) { 291211685becSGavin Shan pnv_ioda_setup_pe_seg(hose, pe); 291311685becSGavin Shan } 291411685becSGavin Shan } 291511685becSGavin Shan } 291611685becSGavin Shan 2917cad5cef6SGreg Kroah-Hartman static void pnv_pci_ioda_setup_DMA(void) 291813395c48SGavin Shan { 291913395c48SGavin Shan struct pci_controller *hose, *tmp; 2920db1266c8SGavin Shan struct pnv_phb *phb; 292113395c48SGavin Shan 292213395c48SGavin Shan list_for_each_entry_safe(hose, tmp, &hose_list, list_node) { 292313395c48SGavin Shan pnv_ioda_setup_dma(hose->private_data); 2924db1266c8SGavin Shan 2925db1266c8SGavin Shan /* Mark the PHB initialization done */ 2926db1266c8SGavin Shan phb = hose->private_data; 2927db1266c8SGavin Shan phb->initialized = 1; 292813395c48SGavin Shan } 292913395c48SGavin Shan } 293013395c48SGavin Shan 293137c367f2SGavin Shan static void pnv_pci_ioda_create_dbgfs(void) 293237c367f2SGavin Shan { 293337c367f2SGavin Shan #ifdef CONFIG_DEBUG_FS 293437c367f2SGavin Shan struct pci_controller *hose, *tmp; 293537c367f2SGavin Shan struct pnv_phb *phb; 293637c367f2SGavin Shan char name[16]; 293737c367f2SGavin Shan 293837c367f2SGavin Shan list_for_each_entry_safe(hose, tmp, &hose_list, list_node) { 293937c367f2SGavin Shan phb = hose->private_data; 294037c367f2SGavin Shan 294137c367f2SGavin Shan sprintf(name, "PCI%04x", hose->global_number); 294237c367f2SGavin Shan phb->dbgfs = debugfs_create_dir(name, powerpc_debugfs_root); 294337c367f2SGavin Shan if (!phb->dbgfs) 294437c367f2SGavin Shan pr_warning("%s: Error on creating debugfs on PHB#%x\n", 294537c367f2SGavin Shan __func__, hose->global_number); 294637c367f2SGavin Shan } 294737c367f2SGavin Shan #endif /* CONFIG_DEBUG_FS */ 294837c367f2SGavin Shan } 294937c367f2SGavin Shan 2950cad5cef6SGreg Kroah-Hartman static void pnv_pci_ioda_fixup(void) 2951fb446ad0SGavin Shan { 2952fb446ad0SGavin Shan pnv_pci_ioda_setup_PEs(); 295311685becSGavin Shan pnv_pci_ioda_setup_seg(); 295413395c48SGavin Shan pnv_pci_ioda_setup_DMA(); 2955e9cc17d4SGavin Shan 295637c367f2SGavin Shan pnv_pci_ioda_create_dbgfs(); 295737c367f2SGavin Shan 2958e9cc17d4SGavin Shan #ifdef CONFIG_EEH 2959e9cc17d4SGavin Shan eeh_init(); 2960dadcd6d6SMike Qiu eeh_addr_cache_build(); 2961e9cc17d4SGavin Shan #endif 2962fb446ad0SGavin Shan } 2963fb446ad0SGavin Shan 2964271fd03aSGavin Shan /* 2965271fd03aSGavin Shan * Returns the alignment for I/O or memory windows for P2P 2966271fd03aSGavin Shan * bridges. That actually depends on how PEs are segmented. 2967271fd03aSGavin Shan * For now, we return I/O or M32 segment size for PE sensitive 2968271fd03aSGavin Shan * P2P bridges. Otherwise, the default values (4KiB for I/O, 2969271fd03aSGavin Shan * 1MiB for memory) will be returned. 2970271fd03aSGavin Shan * 2971271fd03aSGavin Shan * The current PCI bus might be put into one PE, which was 2972271fd03aSGavin Shan * create against the parent PCI bridge. For that case, we 2973271fd03aSGavin Shan * needn't enlarge the alignment so that we can save some 2974271fd03aSGavin Shan * resources. 2975271fd03aSGavin Shan */ 2976271fd03aSGavin Shan static resource_size_t pnv_pci_window_alignment(struct pci_bus *bus, 2977271fd03aSGavin Shan unsigned long type) 2978271fd03aSGavin Shan { 2979271fd03aSGavin Shan struct pci_dev *bridge; 2980271fd03aSGavin Shan struct pci_controller *hose = pci_bus_to_host(bus); 2981271fd03aSGavin Shan struct pnv_phb *phb = hose->private_data; 2982271fd03aSGavin Shan int num_pci_bridges = 0; 2983271fd03aSGavin Shan 2984271fd03aSGavin Shan bridge = bus->self; 2985271fd03aSGavin Shan while (bridge) { 2986271fd03aSGavin Shan if (pci_pcie_type(bridge) == PCI_EXP_TYPE_PCI_BRIDGE) { 2987271fd03aSGavin Shan num_pci_bridges++; 2988271fd03aSGavin Shan if (num_pci_bridges >= 2) 2989271fd03aSGavin Shan return 1; 2990271fd03aSGavin Shan } 2991271fd03aSGavin Shan 2992271fd03aSGavin Shan bridge = bridge->bus->self; 2993271fd03aSGavin Shan } 2994271fd03aSGavin Shan 2995262af557SGuo Chao /* We fail back to M32 if M64 isn't supported */ 2996262af557SGuo Chao if (phb->ioda.m64_segsize && 2997262af557SGuo Chao pnv_pci_is_mem_pref_64(type)) 2998262af557SGuo Chao return phb->ioda.m64_segsize; 2999271fd03aSGavin Shan if (type & IORESOURCE_MEM) 3000271fd03aSGavin Shan return phb->ioda.m32_segsize; 3001271fd03aSGavin Shan 3002271fd03aSGavin Shan return phb->ioda.io_segsize; 3003271fd03aSGavin Shan } 3004271fd03aSGavin Shan 30055350ab3fSWei Yang #ifdef CONFIG_PCI_IOV 30065350ab3fSWei Yang static resource_size_t pnv_pci_iov_resource_alignment(struct pci_dev *pdev, 30075350ab3fSWei Yang int resno) 30085350ab3fSWei Yang { 30095350ab3fSWei Yang struct pci_dn *pdn = pci_get_pdn(pdev); 30105350ab3fSWei Yang resource_size_t align, iov_align; 30115350ab3fSWei Yang 30125350ab3fSWei Yang iov_align = resource_size(&pdev->resource[resno]); 30135350ab3fSWei Yang if (iov_align) 30145350ab3fSWei Yang return iov_align; 30155350ab3fSWei Yang 30165350ab3fSWei Yang align = pci_iov_resource_size(pdev, resno); 30175350ab3fSWei Yang if (pdn->vfs_expanded) 30185350ab3fSWei Yang return pdn->vfs_expanded * align; 30195350ab3fSWei Yang 30205350ab3fSWei Yang return align; 30215350ab3fSWei Yang } 30225350ab3fSWei Yang #endif /* CONFIG_PCI_IOV */ 30235350ab3fSWei Yang 3024184cd4a3SBenjamin Herrenschmidt /* Prevent enabling devices for which we couldn't properly 3025184cd4a3SBenjamin Herrenschmidt * assign a PE 3026184cd4a3SBenjamin Herrenschmidt */ 3027c88c2a18SDaniel Axtens static bool pnv_pci_enable_device_hook(struct pci_dev *dev) 3028184cd4a3SBenjamin Herrenschmidt { 3029db1266c8SGavin Shan struct pci_controller *hose = pci_bus_to_host(dev->bus); 3030db1266c8SGavin Shan struct pnv_phb *phb = hose->private_data; 3031db1266c8SGavin Shan struct pci_dn *pdn; 3032184cd4a3SBenjamin Herrenschmidt 3033db1266c8SGavin Shan /* The function is probably called while the PEs have 3034db1266c8SGavin Shan * not be created yet. For example, resource reassignment 3035db1266c8SGavin Shan * during PCI probe period. We just skip the check if 3036db1266c8SGavin Shan * PEs isn't ready. 3037db1266c8SGavin Shan */ 3038db1266c8SGavin Shan if (!phb->initialized) 3039c88c2a18SDaniel Axtens return true; 3040db1266c8SGavin Shan 3041b72c1f65SBenjamin Herrenschmidt pdn = pci_get_pdn(dev); 3042184cd4a3SBenjamin Herrenschmidt if (!pdn || pdn->pe_number == IODA_INVALID_PE) 3043c88c2a18SDaniel Axtens return false; 3044db1266c8SGavin Shan 3045c88c2a18SDaniel Axtens return true; 3046184cd4a3SBenjamin Herrenschmidt } 3047184cd4a3SBenjamin Herrenschmidt 3048184cd4a3SBenjamin Herrenschmidt static u32 pnv_ioda_bdfn_to_pe(struct pnv_phb *phb, struct pci_bus *bus, 3049184cd4a3SBenjamin Herrenschmidt u32 devfn) 3050184cd4a3SBenjamin Herrenschmidt { 3051184cd4a3SBenjamin Herrenschmidt return phb->ioda.pe_rmap[(bus->number << 8) | devfn]; 3052184cd4a3SBenjamin Herrenschmidt } 3053184cd4a3SBenjamin Herrenschmidt 30547a8e6bbfSMichael Neuling static void pnv_pci_ioda_shutdown(struct pci_controller *hose) 305573ed148aSBenjamin Herrenschmidt { 30567a8e6bbfSMichael Neuling struct pnv_phb *phb = hose->private_data; 30577a8e6bbfSMichael Neuling 3058d1a85eeeSGavin Shan opal_pci_reset(phb->opal_id, OPAL_RESET_PCI_IODA_TABLE, 305973ed148aSBenjamin Herrenschmidt OPAL_ASSERT_RESET); 306073ed148aSBenjamin Herrenschmidt } 306173ed148aSBenjamin Herrenschmidt 306292ae0353SDaniel Axtens static const struct pci_controller_ops pnv_pci_ioda_controller_ops = { 306392ae0353SDaniel Axtens .dma_dev_setup = pnv_pci_dma_dev_setup, 306492ae0353SDaniel Axtens #ifdef CONFIG_PCI_MSI 306592ae0353SDaniel Axtens .setup_msi_irqs = pnv_setup_msi_irqs, 306692ae0353SDaniel Axtens .teardown_msi_irqs = pnv_teardown_msi_irqs, 306792ae0353SDaniel Axtens #endif 306892ae0353SDaniel Axtens .enable_device_hook = pnv_pci_enable_device_hook, 306992ae0353SDaniel Axtens .window_alignment = pnv_pci_window_alignment, 307092ae0353SDaniel Axtens .reset_secondary_bus = pnv_pci_reset_secondary_bus, 3071763d2d8dSDaniel Axtens .dma_set_mask = pnv_pci_ioda_dma_set_mask, 30727a8e6bbfSMichael Neuling .shutdown = pnv_pci_ioda_shutdown, 307392ae0353SDaniel Axtens }; 307492ae0353SDaniel Axtens 3075e51df2c1SAnton Blanchard static void __init pnv_pci_init_ioda_phb(struct device_node *np, 3076e9cc17d4SGavin Shan u64 hub_id, int ioda_type) 3077184cd4a3SBenjamin Herrenschmidt { 3078184cd4a3SBenjamin Herrenschmidt struct pci_controller *hose; 3079184cd4a3SBenjamin Herrenschmidt struct pnv_phb *phb; 30808184616fSGavin Shan unsigned long size, m32map_off, pemap_off, iomap_off = 0; 3081c681b93cSAlistair Popple const __be64 *prop64; 30823a1a4661SBenjamin Herrenschmidt const __be32 *prop32; 3083f1b7cc3eSGavin Shan int len; 3084184cd4a3SBenjamin Herrenschmidt u64 phb_id; 3085184cd4a3SBenjamin Herrenschmidt void *aux; 3086184cd4a3SBenjamin Herrenschmidt long rc; 3087184cd4a3SBenjamin Herrenschmidt 3088aa0c033fSGavin Shan pr_info("Initializing IODA%d OPAL PHB %s\n", ioda_type, np->full_name); 3089184cd4a3SBenjamin Herrenschmidt 3090184cd4a3SBenjamin Herrenschmidt prop64 = of_get_property(np, "ibm,opal-phbid", NULL); 3091184cd4a3SBenjamin Herrenschmidt if (!prop64) { 3092184cd4a3SBenjamin Herrenschmidt pr_err(" Missing \"ibm,opal-phbid\" property !\n"); 3093184cd4a3SBenjamin Herrenschmidt return; 3094184cd4a3SBenjamin Herrenschmidt } 3095184cd4a3SBenjamin Herrenschmidt phb_id = be64_to_cpup(prop64); 3096184cd4a3SBenjamin Herrenschmidt pr_debug(" PHB-ID : 0x%016llx\n", phb_id); 3097184cd4a3SBenjamin Herrenschmidt 3098e39f223fSMichael Ellerman phb = memblock_virt_alloc(sizeof(struct pnv_phb), 0); 309958d714ecSGavin Shan 310058d714ecSGavin Shan /* Allocate PCI controller */ 3101184cd4a3SBenjamin Herrenschmidt phb->hose = hose = pcibios_alloc_controller(np); 310258d714ecSGavin Shan if (!phb->hose) { 310358d714ecSGavin Shan pr_err(" Can't allocate PCI controller for %s\n", 3104184cd4a3SBenjamin Herrenschmidt np->full_name); 3105e39f223fSMichael Ellerman memblock_free(__pa(phb), sizeof(struct pnv_phb)); 3106184cd4a3SBenjamin Herrenschmidt return; 3107184cd4a3SBenjamin Herrenschmidt } 3108184cd4a3SBenjamin Herrenschmidt 3109184cd4a3SBenjamin Herrenschmidt spin_lock_init(&phb->lock); 3110f1b7cc3eSGavin Shan prop32 = of_get_property(np, "bus-range", &len); 3111f1b7cc3eSGavin Shan if (prop32 && len == 8) { 31123a1a4661SBenjamin Herrenschmidt hose->first_busno = be32_to_cpu(prop32[0]); 31133a1a4661SBenjamin Herrenschmidt hose->last_busno = be32_to_cpu(prop32[1]); 3114f1b7cc3eSGavin Shan } else { 3115f1b7cc3eSGavin Shan pr_warn(" Broken <bus-range> on %s\n", np->full_name); 3116184cd4a3SBenjamin Herrenschmidt hose->first_busno = 0; 3117184cd4a3SBenjamin Herrenschmidt hose->last_busno = 0xff; 3118f1b7cc3eSGavin Shan } 3119184cd4a3SBenjamin Herrenschmidt hose->private_data = phb; 3120e9cc17d4SGavin Shan phb->hub_id = hub_id; 3121184cd4a3SBenjamin Herrenschmidt phb->opal_id = phb_id; 3122aa0c033fSGavin Shan phb->type = ioda_type; 3123781a868fSWei Yang mutex_init(&phb->ioda.pe_alloc_mutex); 3124184cd4a3SBenjamin Herrenschmidt 3125cee72d5bSBenjamin Herrenschmidt /* Detect specific models for error handling */ 3126cee72d5bSBenjamin Herrenschmidt if (of_device_is_compatible(np, "ibm,p7ioc-pciex")) 3127cee72d5bSBenjamin Herrenschmidt phb->model = PNV_PHB_MODEL_P7IOC; 3128f3d40c25SBenjamin Herrenschmidt else if (of_device_is_compatible(np, "ibm,power8-pciex")) 3129aa0c033fSGavin Shan phb->model = PNV_PHB_MODEL_PHB3; 3130cee72d5bSBenjamin Herrenschmidt else 3131cee72d5bSBenjamin Herrenschmidt phb->model = PNV_PHB_MODEL_UNKNOWN; 3132cee72d5bSBenjamin Herrenschmidt 3133aa0c033fSGavin Shan /* Parse 32-bit and IO ranges (if any) */ 31342f1ec02eSGavin Shan pci_process_bridge_OF_ranges(hose, np, !hose->global_number); 3135184cd4a3SBenjamin Herrenschmidt 3136aa0c033fSGavin Shan /* Get registers */ 3137184cd4a3SBenjamin Herrenschmidt phb->regs = of_iomap(np, 0); 3138184cd4a3SBenjamin Herrenschmidt if (phb->regs == NULL) 3139184cd4a3SBenjamin Herrenschmidt pr_err(" Failed to map registers !\n"); 3140184cd4a3SBenjamin Herrenschmidt 3141184cd4a3SBenjamin Herrenschmidt /* Initialize more IODA stuff */ 3142aa0c033fSGavin Shan phb->ioda.total_pe = 1; 314336954dc7SGavin Shan prop32 = of_get_property(np, "ibm,opal-num-pes", NULL); 314436954dc7SGavin Shan if (prop32) 31453a1a4661SBenjamin Herrenschmidt phb->ioda.total_pe = be32_to_cpup(prop32); 314636954dc7SGavin Shan prop32 = of_get_property(np, "ibm,opal-reserved-pe", NULL); 314736954dc7SGavin Shan if (prop32) 314836954dc7SGavin Shan phb->ioda.reserved_pe = be32_to_cpup(prop32); 3149262af557SGuo Chao 3150262af557SGuo Chao /* Parse 64-bit MMIO range */ 3151262af557SGuo Chao pnv_ioda_parse_m64_window(phb); 3152262af557SGuo Chao 3153184cd4a3SBenjamin Herrenschmidt phb->ioda.m32_size = resource_size(&hose->mem_resources[0]); 3154aa0c033fSGavin Shan /* FW Has already off top 64k of M32 space (MSI space) */ 3155184cd4a3SBenjamin Herrenschmidt phb->ioda.m32_size += 0x10000; 3156184cd4a3SBenjamin Herrenschmidt 3157184cd4a3SBenjamin Herrenschmidt phb->ioda.m32_segsize = phb->ioda.m32_size / phb->ioda.total_pe; 31583fd47f06SBenjamin Herrenschmidt phb->ioda.m32_pci_base = hose->mem_resources[0].start - hose->mem_offset[0]; 3159184cd4a3SBenjamin Herrenschmidt phb->ioda.io_size = hose->pci_io_size; 3160184cd4a3SBenjamin Herrenschmidt phb->ioda.io_segsize = phb->ioda.io_size / phb->ioda.total_pe; 3161184cd4a3SBenjamin Herrenschmidt phb->ioda.io_pci_base = 0; /* XXX calculate this ? */ 3162184cd4a3SBenjamin Herrenschmidt 3163c35d2a8cSGavin Shan /* Allocate aux data & arrays. We don't have IO ports on PHB3 */ 3164184cd4a3SBenjamin Herrenschmidt size = _ALIGN_UP(phb->ioda.total_pe / 8, sizeof(unsigned long)); 3165184cd4a3SBenjamin Herrenschmidt m32map_off = size; 3166e47747f4SGavin Shan size += phb->ioda.total_pe * sizeof(phb->ioda.m32_segmap[0]); 3167c35d2a8cSGavin Shan if (phb->type == PNV_PHB_IODA1) { 3168c35d2a8cSGavin Shan iomap_off = size; 3169e47747f4SGavin Shan size += phb->ioda.total_pe * sizeof(phb->ioda.io_segmap[0]); 3170c35d2a8cSGavin Shan } 3171184cd4a3SBenjamin Herrenschmidt pemap_off = size; 3172184cd4a3SBenjamin Herrenschmidt size += phb->ioda.total_pe * sizeof(struct pnv_ioda_pe); 3173e39f223fSMichael Ellerman aux = memblock_virt_alloc(size, 0); 3174184cd4a3SBenjamin Herrenschmidt phb->ioda.pe_alloc = aux; 3175184cd4a3SBenjamin Herrenschmidt phb->ioda.m32_segmap = aux + m32map_off; 3176c35d2a8cSGavin Shan if (phb->type == PNV_PHB_IODA1) 3177184cd4a3SBenjamin Herrenschmidt phb->ioda.io_segmap = aux + iomap_off; 3178184cd4a3SBenjamin Herrenschmidt phb->ioda.pe_array = aux + pemap_off; 317936954dc7SGavin Shan set_bit(phb->ioda.reserved_pe, phb->ioda.pe_alloc); 3180184cd4a3SBenjamin Herrenschmidt 31817ebdf956SGavin Shan INIT_LIST_HEAD(&phb->ioda.pe_dma_list); 3182184cd4a3SBenjamin Herrenschmidt INIT_LIST_HEAD(&phb->ioda.pe_list); 3183781a868fSWei Yang mutex_init(&phb->ioda.pe_list_mutex); 3184184cd4a3SBenjamin Herrenschmidt 3185184cd4a3SBenjamin Herrenschmidt /* Calculate how many 32-bit TCE segments we have */ 3186184cd4a3SBenjamin Herrenschmidt phb->ioda.tce32_count = phb->ioda.m32_pci_base >> 28; 3187184cd4a3SBenjamin Herrenschmidt 3188aa0c033fSGavin Shan #if 0 /* We should really do that ... */ 3189184cd4a3SBenjamin Herrenschmidt rc = opal_pci_set_phb_mem_window(opal->phb_id, 3190184cd4a3SBenjamin Herrenschmidt window_type, 3191184cd4a3SBenjamin Herrenschmidt window_num, 3192184cd4a3SBenjamin Herrenschmidt starting_real_address, 3193184cd4a3SBenjamin Herrenschmidt starting_pci_address, 3194184cd4a3SBenjamin Herrenschmidt segment_size); 3195184cd4a3SBenjamin Herrenschmidt #endif 3196184cd4a3SBenjamin Herrenschmidt 3197262af557SGuo Chao pr_info(" %03d (%03d) PE's M32: 0x%x [segment=0x%x]\n", 3198262af557SGuo Chao phb->ioda.total_pe, phb->ioda.reserved_pe, 3199262af557SGuo Chao phb->ioda.m32_size, phb->ioda.m32_segsize); 3200262af557SGuo Chao if (phb->ioda.m64_size) 3201262af557SGuo Chao pr_info(" M64: 0x%lx [segment=0x%lx]\n", 3202262af557SGuo Chao phb->ioda.m64_size, phb->ioda.m64_segsize); 3203262af557SGuo Chao if (phb->ioda.io_size) 3204262af557SGuo Chao pr_info(" IO: 0x%x [segment=0x%x]\n", 3205184cd4a3SBenjamin Herrenschmidt phb->ioda.io_size, phb->ioda.io_segsize); 3206184cd4a3SBenjamin Herrenschmidt 3207262af557SGuo Chao 3208184cd4a3SBenjamin Herrenschmidt phb->hose->ops = &pnv_pci_ops; 320949dec922SGavin Shan phb->get_pe_state = pnv_ioda_get_pe_state; 321049dec922SGavin Shan phb->freeze_pe = pnv_ioda_freeze_pe; 321149dec922SGavin Shan phb->unfreeze_pe = pnv_ioda_unfreeze_pe; 3212184cd4a3SBenjamin Herrenschmidt 3213184cd4a3SBenjamin Herrenschmidt /* Setup RID -> PE mapping function */ 3214184cd4a3SBenjamin Herrenschmidt phb->bdfn_to_pe = pnv_ioda_bdfn_to_pe; 3215184cd4a3SBenjamin Herrenschmidt 3216184cd4a3SBenjamin Herrenschmidt /* Setup TCEs */ 3217184cd4a3SBenjamin Herrenschmidt phb->dma_dev_setup = pnv_pci_ioda_dma_dev_setup; 3218fe7e85c6SGavin Shan phb->dma_get_required_mask = pnv_pci_ioda_dma_get_required_mask; 3219184cd4a3SBenjamin Herrenschmidt 3220184cd4a3SBenjamin Herrenschmidt /* Setup MSI support */ 3221184cd4a3SBenjamin Herrenschmidt pnv_pci_init_ioda_msis(phb); 3222184cd4a3SBenjamin Herrenschmidt 3223c40a4210SGavin Shan /* 3224c40a4210SGavin Shan * We pass the PCI probe flag PCI_REASSIGN_ALL_RSRC here 3225c40a4210SGavin Shan * to let the PCI core do resource assignment. It's supposed 3226c40a4210SGavin Shan * that the PCI core will do correct I/O and MMIO alignment 3227c40a4210SGavin Shan * for the P2P bridge bars so that each PCI bus (excluding 3228c40a4210SGavin Shan * the child P2P bridges) can form individual PE. 3229184cd4a3SBenjamin Herrenschmidt */ 3230fb446ad0SGavin Shan ppc_md.pcibios_fixup = pnv_pci_ioda_fixup; 323192ae0353SDaniel Axtens hose->controller_ops = pnv_pci_ioda_controller_ops; 3232ad30cb99SMichael Ellerman 32336e628c7dSWei Yang #ifdef CONFIG_PCI_IOV 32346e628c7dSWei Yang ppc_md.pcibios_fixup_sriov = pnv_pci_ioda_fixup_iov_resources; 32355350ab3fSWei Yang ppc_md.pcibios_iov_resource_alignment = pnv_pci_iov_resource_alignment; 3236ad30cb99SMichael Ellerman #endif 3237ad30cb99SMichael Ellerman 3238c40a4210SGavin Shan pci_add_flags(PCI_REASSIGN_ALL_RSRC); 3239184cd4a3SBenjamin Herrenschmidt 3240184cd4a3SBenjamin Herrenschmidt /* Reset IODA tables to a clean state */ 3241d1a85eeeSGavin Shan rc = opal_pci_reset(phb_id, OPAL_RESET_PCI_IODA_TABLE, OPAL_ASSERT_RESET); 3242184cd4a3SBenjamin Herrenschmidt if (rc) 3243f11fe552SBenjamin Herrenschmidt pr_warning(" OPAL Error %ld performing IODA table reset !\n", rc); 3244361f2a2aSGavin Shan 3245361f2a2aSGavin Shan /* If we're running in kdump kerenl, the previous kerenl never 3246361f2a2aSGavin Shan * shutdown PCI devices correctly. We already got IODA table 3247361f2a2aSGavin Shan * cleaned out. So we have to issue PHB reset to stop all PCI 3248361f2a2aSGavin Shan * transactions from previous kerenl. 3249361f2a2aSGavin Shan */ 3250361f2a2aSGavin Shan if (is_kdump_kernel()) { 3251361f2a2aSGavin Shan pr_info(" Issue PHB reset ...\n"); 3252cadf364dSGavin Shan pnv_eeh_phb_reset(hose, EEH_RESET_FUNDAMENTAL); 3253cadf364dSGavin Shan pnv_eeh_phb_reset(hose, EEH_RESET_DEACTIVATE); 3254361f2a2aSGavin Shan } 3255262af557SGuo Chao 32569e9e8935SGavin Shan /* Remove M64 resource if we can't configure it successfully */ 32579e9e8935SGavin Shan if (!phb->init_m64 || phb->init_m64(phb)) 3258262af557SGuo Chao hose->mem_resources[1].flags = 0; 3259184cd4a3SBenjamin Herrenschmidt } 3260184cd4a3SBenjamin Herrenschmidt 326167975005SBjorn Helgaas void __init pnv_pci_init_ioda2_phb(struct device_node *np) 3262aa0c033fSGavin Shan { 3263e9cc17d4SGavin Shan pnv_pci_init_ioda_phb(np, 0, PNV_PHB_IODA2); 3264aa0c033fSGavin Shan } 3265aa0c033fSGavin Shan 3266184cd4a3SBenjamin Herrenschmidt void __init pnv_pci_init_ioda_hub(struct device_node *np) 3267184cd4a3SBenjamin Herrenschmidt { 3268184cd4a3SBenjamin Herrenschmidt struct device_node *phbn; 3269c681b93cSAlistair Popple const __be64 *prop64; 3270184cd4a3SBenjamin Herrenschmidt u64 hub_id; 3271184cd4a3SBenjamin Herrenschmidt 3272184cd4a3SBenjamin Herrenschmidt pr_info("Probing IODA IO-Hub %s\n", np->full_name); 3273184cd4a3SBenjamin Herrenschmidt 3274184cd4a3SBenjamin Herrenschmidt prop64 = of_get_property(np, "ibm,opal-hubid", NULL); 3275184cd4a3SBenjamin Herrenschmidt if (!prop64) { 3276184cd4a3SBenjamin Herrenschmidt pr_err(" Missing \"ibm,opal-hubid\" property !\n"); 3277184cd4a3SBenjamin Herrenschmidt return; 3278184cd4a3SBenjamin Herrenschmidt } 3279184cd4a3SBenjamin Herrenschmidt hub_id = be64_to_cpup(prop64); 3280184cd4a3SBenjamin Herrenschmidt pr_devel(" HUB-ID : 0x%016llx\n", hub_id); 3281184cd4a3SBenjamin Herrenschmidt 3282184cd4a3SBenjamin Herrenschmidt /* Count child PHBs */ 3283184cd4a3SBenjamin Herrenschmidt for_each_child_of_node(np, phbn) { 3284184cd4a3SBenjamin Herrenschmidt /* Look for IODA1 PHBs */ 3285184cd4a3SBenjamin Herrenschmidt if (of_device_is_compatible(phbn, "ibm,ioda-phb")) 3286e9cc17d4SGavin Shan pnv_pci_init_ioda_phb(phbn, hub_id, PNV_PHB_IODA1); 3287184cd4a3SBenjamin Herrenschmidt } 3288184cd4a3SBenjamin Herrenschmidt } 3289