1184cd4a3SBenjamin Herrenschmidt /* 2184cd4a3SBenjamin Herrenschmidt * Support PCI/PCIe on PowerNV platforms 3184cd4a3SBenjamin Herrenschmidt * 4184cd4a3SBenjamin Herrenschmidt * Copyright 2011 Benjamin Herrenschmidt, IBM Corp. 5184cd4a3SBenjamin Herrenschmidt * 6184cd4a3SBenjamin Herrenschmidt * This program is free software; you can redistribute it and/or 7184cd4a3SBenjamin Herrenschmidt * modify it under the terms of the GNU General Public License 8184cd4a3SBenjamin Herrenschmidt * as published by the Free Software Foundation; either version 9184cd4a3SBenjamin Herrenschmidt * 2 of the License, or (at your option) any later version. 10184cd4a3SBenjamin Herrenschmidt */ 11184cd4a3SBenjamin Herrenschmidt 12cee72d5bSBenjamin Herrenschmidt #undef DEBUG 13184cd4a3SBenjamin Herrenschmidt 14184cd4a3SBenjamin Herrenschmidt #include <linux/kernel.h> 15184cd4a3SBenjamin Herrenschmidt #include <linux/pci.h> 16361f2a2aSGavin Shan #include <linux/crash_dump.h> 1737c367f2SGavin Shan #include <linux/debugfs.h> 18184cd4a3SBenjamin Herrenschmidt #include <linux/delay.h> 19184cd4a3SBenjamin Herrenschmidt #include <linux/string.h> 20184cd4a3SBenjamin Herrenschmidt #include <linux/init.h> 21184cd4a3SBenjamin Herrenschmidt #include <linux/bootmem.h> 22184cd4a3SBenjamin Herrenschmidt #include <linux/irq.h> 23184cd4a3SBenjamin Herrenschmidt #include <linux/io.h> 24184cd4a3SBenjamin Herrenschmidt #include <linux/msi.h> 25cd15b048SBenjamin Herrenschmidt #include <linux/memblock.h> 26ac9a5889SAlexey Kardashevskiy #include <linux/iommu.h> 27e57080f1SAlexey Kardashevskiy #include <linux/rculist.h> 284793d65dSAlexey Kardashevskiy #include <linux/sizes.h> 29184cd4a3SBenjamin Herrenschmidt 30184cd4a3SBenjamin Herrenschmidt #include <asm/sections.h> 31184cd4a3SBenjamin Herrenschmidt #include <asm/io.h> 32184cd4a3SBenjamin Herrenschmidt #include <asm/prom.h> 33184cd4a3SBenjamin Herrenschmidt #include <asm/pci-bridge.h> 34184cd4a3SBenjamin Herrenschmidt #include <asm/machdep.h> 35fb1b55d6SGavin Shan #include <asm/msi_bitmap.h> 36184cd4a3SBenjamin Herrenschmidt #include <asm/ppc-pci.h> 37184cd4a3SBenjamin Herrenschmidt #include <asm/opal.h> 38184cd4a3SBenjamin Herrenschmidt #include <asm/iommu.h> 39184cd4a3SBenjamin Herrenschmidt #include <asm/tce.h> 40137436c9SGavin Shan #include <asm/xics.h> 4137c367f2SGavin Shan #include <asm/debug.h> 42262af557SGuo Chao #include <asm/firmware.h> 4380c49c7eSIan Munsie #include <asm/pnv-pci.h> 44aca6913fSAlexey Kardashevskiy #include <asm/mmzone.h> 4580c49c7eSIan Munsie 46ec249dd8SMichael Neuling #include <misc/cxl-base.h> 47184cd4a3SBenjamin Herrenschmidt 48184cd4a3SBenjamin Herrenschmidt #include "powernv.h" 49184cd4a3SBenjamin Herrenschmidt #include "pci.h" 50184cd4a3SBenjamin Herrenschmidt 5199451551SGavin Shan #define PNV_IODA1_M64_NUM 16 /* Number of M64 BARs */ 5299451551SGavin Shan #define PNV_IODA1_M64_SEGS 8 /* Segments per M64 BAR */ 53acce971cSGavin Shan #define PNV_IODA1_DMA32_SEGSIZE 0x10000000 54781a868fSWei Yang 55bbb845c4SAlexey Kardashevskiy #define POWERNV_IOMMU_DEFAULT_LEVELS 1 56bbb845c4SAlexey Kardashevskiy #define POWERNV_IOMMU_MAX_LEVELS 5 57bbb845c4SAlexey Kardashevskiy 58aca6913fSAlexey Kardashevskiy static void pnv_pci_ioda2_table_free_pages(struct iommu_table *tbl); 59aca6913fSAlexey Kardashevskiy 607d623e42SAlexey Kardashevskiy void pe_level_printk(const struct pnv_ioda_pe *pe, const char *level, 616d31c2faSJoe Perches const char *fmt, ...) 626d31c2faSJoe Perches { 636d31c2faSJoe Perches struct va_format vaf; 646d31c2faSJoe Perches va_list args; 656d31c2faSJoe Perches char pfix[32]; 66184cd4a3SBenjamin Herrenschmidt 676d31c2faSJoe Perches va_start(args, fmt); 686d31c2faSJoe Perches 696d31c2faSJoe Perches vaf.fmt = fmt; 706d31c2faSJoe Perches vaf.va = &args; 716d31c2faSJoe Perches 72781a868fSWei Yang if (pe->flags & PNV_IODA_PE_DEV) 736d31c2faSJoe Perches strlcpy(pfix, dev_name(&pe->pdev->dev), sizeof(pfix)); 74781a868fSWei Yang else if (pe->flags & (PNV_IODA_PE_BUS | PNV_IODA_PE_BUS_ALL)) 756d31c2faSJoe Perches sprintf(pfix, "%04x:%02x ", 766d31c2faSJoe Perches pci_domain_nr(pe->pbus), pe->pbus->number); 77781a868fSWei Yang #ifdef CONFIG_PCI_IOV 78781a868fSWei Yang else if (pe->flags & PNV_IODA_PE_VF) 79781a868fSWei Yang sprintf(pfix, "%04x:%02x:%2x.%d", 80781a868fSWei Yang pci_domain_nr(pe->parent_dev->bus), 81781a868fSWei Yang (pe->rid & 0xff00) >> 8, 82781a868fSWei Yang PCI_SLOT(pe->rid), PCI_FUNC(pe->rid)); 83781a868fSWei Yang #endif /* CONFIG_PCI_IOV*/ 846d31c2faSJoe Perches 856d31c2faSJoe Perches printk("%spci %s: [PE# %.3d] %pV", 866d31c2faSJoe Perches level, pfix, pe->pe_number, &vaf); 876d31c2faSJoe Perches 886d31c2faSJoe Perches va_end(args); 896d31c2faSJoe Perches } 906d31c2faSJoe Perches 914e287840SThadeu Lima de Souza Cascardo static bool pnv_iommu_bypass_disabled __read_mostly; 924e287840SThadeu Lima de Souza Cascardo 934e287840SThadeu Lima de Souza Cascardo static int __init iommu_setup(char *str) 944e287840SThadeu Lima de Souza Cascardo { 954e287840SThadeu Lima de Souza Cascardo if (!str) 964e287840SThadeu Lima de Souza Cascardo return -EINVAL; 974e287840SThadeu Lima de Souza Cascardo 984e287840SThadeu Lima de Souza Cascardo while (*str) { 994e287840SThadeu Lima de Souza Cascardo if (!strncmp(str, "nobypass", 8)) { 1004e287840SThadeu Lima de Souza Cascardo pnv_iommu_bypass_disabled = true; 1014e287840SThadeu Lima de Souza Cascardo pr_info("PowerNV: IOMMU bypass window disabled.\n"); 1024e287840SThadeu Lima de Souza Cascardo break; 1034e287840SThadeu Lima de Souza Cascardo } 1044e287840SThadeu Lima de Souza Cascardo str += strcspn(str, ","); 1054e287840SThadeu Lima de Souza Cascardo if (*str == ',') 1064e287840SThadeu Lima de Souza Cascardo str++; 1074e287840SThadeu Lima de Souza Cascardo } 1084e287840SThadeu Lima de Souza Cascardo 1094e287840SThadeu Lima de Souza Cascardo return 0; 1104e287840SThadeu Lima de Souza Cascardo } 1114e287840SThadeu Lima de Souza Cascardo early_param("iommu", iommu_setup); 1124e287840SThadeu Lima de Souza Cascardo 113262af557SGuo Chao static inline bool pnv_pci_is_mem_pref_64(unsigned long flags) 114262af557SGuo Chao { 115262af557SGuo Chao return ((flags & (IORESOURCE_MEM_64 | IORESOURCE_PREFETCH)) == 116262af557SGuo Chao (IORESOURCE_MEM_64 | IORESOURCE_PREFETCH)); 117262af557SGuo Chao } 118262af557SGuo Chao 1191e916772SGavin Shan static struct pnv_ioda_pe *pnv_ioda_init_pe(struct pnv_phb *phb, int pe_no) 1201e916772SGavin Shan { 1211e916772SGavin Shan phb->ioda.pe_array[pe_no].phb = phb; 1221e916772SGavin Shan phb->ioda.pe_array[pe_no].pe_number = pe_no; 1231e916772SGavin Shan 1241e916772SGavin Shan return &phb->ioda.pe_array[pe_no]; 1251e916772SGavin Shan } 1261e916772SGavin Shan 1274b82ab18SGavin Shan static void pnv_ioda_reserve_pe(struct pnv_phb *phb, int pe_no) 1284b82ab18SGavin Shan { 12992b8f137SGavin Shan if (!(pe_no >= 0 && pe_no < phb->ioda.total_pe_num)) { 1304b82ab18SGavin Shan pr_warn("%s: Invalid PE %d on PHB#%x\n", 1314b82ab18SGavin Shan __func__, pe_no, phb->hose->global_number); 1324b82ab18SGavin Shan return; 1334b82ab18SGavin Shan } 1344b82ab18SGavin Shan 135e9dc4d7fSGavin Shan if (test_and_set_bit(pe_no, phb->ioda.pe_alloc)) 136e9dc4d7fSGavin Shan pr_debug("%s: PE %d was reserved on PHB#%x\n", 1374b82ab18SGavin Shan __func__, pe_no, phb->hose->global_number); 1384b82ab18SGavin Shan 1391e916772SGavin Shan pnv_ioda_init_pe(phb, pe_no); 1404b82ab18SGavin Shan } 1414b82ab18SGavin Shan 1421e916772SGavin Shan static struct pnv_ioda_pe *pnv_ioda_alloc_pe(struct pnv_phb *phb) 143184cd4a3SBenjamin Herrenschmidt { 1449fcd6f4aSGavin Shan unsigned long pe = phb->ioda.total_pe_num - 1; 145184cd4a3SBenjamin Herrenschmidt 1469fcd6f4aSGavin Shan for (pe = phb->ioda.total_pe_num - 1; pe >= 0; pe--) { 1479fcd6f4aSGavin Shan if (!test_and_set_bit(pe, phb->ioda.pe_alloc)) 1481e916772SGavin Shan return pnv_ioda_init_pe(phb, pe); 149184cd4a3SBenjamin Herrenschmidt } 150184cd4a3SBenjamin Herrenschmidt 1519fcd6f4aSGavin Shan return NULL; 1529fcd6f4aSGavin Shan } 1539fcd6f4aSGavin Shan 1541e916772SGavin Shan static void pnv_ioda_free_pe(struct pnv_ioda_pe *pe) 155184cd4a3SBenjamin Herrenschmidt { 1561e916772SGavin Shan struct pnv_phb *phb = pe->phb; 157184cd4a3SBenjamin Herrenschmidt 1581e916772SGavin Shan WARN_ON(pe->pdev); 1591e916772SGavin Shan 1601e916772SGavin Shan memset(pe, 0, sizeof(struct pnv_ioda_pe)); 1611e916772SGavin Shan clear_bit(pe->pe_number, phb->ioda.pe_alloc); 162184cd4a3SBenjamin Herrenschmidt } 163184cd4a3SBenjamin Herrenschmidt 164262af557SGuo Chao /* The default M64 BAR is shared by all PEs */ 165262af557SGuo Chao static int pnv_ioda2_init_m64(struct pnv_phb *phb) 166262af557SGuo Chao { 167262af557SGuo Chao const char *desc; 168262af557SGuo Chao struct resource *r; 169262af557SGuo Chao s64 rc; 170262af557SGuo Chao 171262af557SGuo Chao /* Configure the default M64 BAR */ 172262af557SGuo Chao rc = opal_pci_set_phb_mem_window(phb->opal_id, 173262af557SGuo Chao OPAL_M64_WINDOW_TYPE, 174262af557SGuo Chao phb->ioda.m64_bar_idx, 175262af557SGuo Chao phb->ioda.m64_base, 176262af557SGuo Chao 0, /* unused */ 177262af557SGuo Chao phb->ioda.m64_size); 178262af557SGuo Chao if (rc != OPAL_SUCCESS) { 179262af557SGuo Chao desc = "configuring"; 180262af557SGuo Chao goto fail; 181262af557SGuo Chao } 182262af557SGuo Chao 183262af557SGuo Chao /* Enable the default M64 BAR */ 184262af557SGuo Chao rc = opal_pci_phb_mmio_enable(phb->opal_id, 185262af557SGuo Chao OPAL_M64_WINDOW_TYPE, 186262af557SGuo Chao phb->ioda.m64_bar_idx, 187262af557SGuo Chao OPAL_ENABLE_M64_SPLIT); 188262af557SGuo Chao if (rc != OPAL_SUCCESS) { 189262af557SGuo Chao desc = "enabling"; 190262af557SGuo Chao goto fail; 191262af557SGuo Chao } 192262af557SGuo Chao 193262af557SGuo Chao /* Mark the M64 BAR assigned */ 194262af557SGuo Chao set_bit(phb->ioda.m64_bar_idx, &phb->ioda.m64_bar_alloc); 195262af557SGuo Chao 196262af557SGuo Chao /* 19763803c39SGavin Shan * Exclude the segments for reserved and root bus PE, which 19863803c39SGavin Shan * are first or last two PEs. 199262af557SGuo Chao */ 200262af557SGuo Chao r = &phb->hose->mem_resources[1]; 20192b8f137SGavin Shan if (phb->ioda.reserved_pe_idx == 0) 20263803c39SGavin Shan r->start += (2 * phb->ioda.m64_segsize); 20392b8f137SGavin Shan else if (phb->ioda.reserved_pe_idx == (phb->ioda.total_pe_num - 1)) 20463803c39SGavin Shan r->end -= (2 * phb->ioda.m64_segsize); 205262af557SGuo Chao else 206262af557SGuo Chao pr_warn(" Cannot strip M64 segment for reserved PE#%d\n", 20792b8f137SGavin Shan phb->ioda.reserved_pe_idx); 208262af557SGuo Chao 209262af557SGuo Chao return 0; 210262af557SGuo Chao 211262af557SGuo Chao fail: 212262af557SGuo Chao pr_warn(" Failure %lld %s M64 BAR#%d\n", 213262af557SGuo Chao rc, desc, phb->ioda.m64_bar_idx); 214262af557SGuo Chao opal_pci_phb_mmio_enable(phb->opal_id, 215262af557SGuo Chao OPAL_M64_WINDOW_TYPE, 216262af557SGuo Chao phb->ioda.m64_bar_idx, 217262af557SGuo Chao OPAL_DISABLE_M64); 218262af557SGuo Chao return -EIO; 219262af557SGuo Chao } 220262af557SGuo Chao 221c430670aSGavin Shan static void pnv_ioda_reserve_dev_m64_pe(struct pci_dev *pdev, 22296a2f92bSGavin Shan unsigned long *pe_bitmap) 223262af557SGuo Chao { 22496a2f92bSGavin Shan struct pci_controller *hose = pci_bus_to_host(pdev->bus); 22596a2f92bSGavin Shan struct pnv_phb *phb = hose->private_data; 226262af557SGuo Chao struct resource *r; 22796a2f92bSGavin Shan resource_size_t base, sgsz, start, end; 22896a2f92bSGavin Shan int segno, i; 229262af557SGuo Chao 23096a2f92bSGavin Shan base = phb->ioda.m64_base; 23196a2f92bSGavin Shan sgsz = phb->ioda.m64_segsize; 23296a2f92bSGavin Shan for (i = 0; i <= PCI_ROM_RESOURCE; i++) { 23396a2f92bSGavin Shan r = &pdev->resource[i]; 23496a2f92bSGavin Shan if (!r->parent || !pnv_pci_is_mem_pref_64(r->flags)) 235262af557SGuo Chao continue; 236262af557SGuo Chao 23796a2f92bSGavin Shan start = _ALIGN_DOWN(r->start - base, sgsz); 23896a2f92bSGavin Shan end = _ALIGN_UP(r->end - base, sgsz); 23996a2f92bSGavin Shan for (segno = start / sgsz; segno < end / sgsz; segno++) { 24096a2f92bSGavin Shan if (pe_bitmap) 24196a2f92bSGavin Shan set_bit(segno, pe_bitmap); 24296a2f92bSGavin Shan else 24396a2f92bSGavin Shan pnv_ioda_reserve_pe(phb, segno); 244262af557SGuo Chao } 245262af557SGuo Chao } 246262af557SGuo Chao } 247262af557SGuo Chao 24899451551SGavin Shan static int pnv_ioda1_init_m64(struct pnv_phb *phb) 24999451551SGavin Shan { 25099451551SGavin Shan struct resource *r; 25199451551SGavin Shan int index; 25299451551SGavin Shan 25399451551SGavin Shan /* 25499451551SGavin Shan * There are 16 M64 BARs, each of which has 8 segments. So 25599451551SGavin Shan * there are as many M64 segments as the maximum number of 25699451551SGavin Shan * PEs, which is 128. 25799451551SGavin Shan */ 25899451551SGavin Shan for (index = 0; index < PNV_IODA1_M64_NUM; index++) { 25999451551SGavin Shan unsigned long base, segsz = phb->ioda.m64_segsize; 26099451551SGavin Shan int64_t rc; 26199451551SGavin Shan 26299451551SGavin Shan base = phb->ioda.m64_base + 26399451551SGavin Shan index * PNV_IODA1_M64_SEGS * segsz; 26499451551SGavin Shan rc = opal_pci_set_phb_mem_window(phb->opal_id, 26599451551SGavin Shan OPAL_M64_WINDOW_TYPE, index, base, 0, 26699451551SGavin Shan PNV_IODA1_M64_SEGS * segsz); 26799451551SGavin Shan if (rc != OPAL_SUCCESS) { 26899451551SGavin Shan pr_warn(" Error %lld setting M64 PHB#%d-BAR#%d\n", 26999451551SGavin Shan rc, phb->hose->global_number, index); 27099451551SGavin Shan goto fail; 27199451551SGavin Shan } 27299451551SGavin Shan 27399451551SGavin Shan rc = opal_pci_phb_mmio_enable(phb->opal_id, 27499451551SGavin Shan OPAL_M64_WINDOW_TYPE, index, 27599451551SGavin Shan OPAL_ENABLE_M64_SPLIT); 27699451551SGavin Shan if (rc != OPAL_SUCCESS) { 27799451551SGavin Shan pr_warn(" Error %lld enabling M64 PHB#%d-BAR#%d\n", 27899451551SGavin Shan rc, phb->hose->global_number, index); 27999451551SGavin Shan goto fail; 28099451551SGavin Shan } 28199451551SGavin Shan } 28299451551SGavin Shan 28399451551SGavin Shan /* 28463803c39SGavin Shan * Exclude the segments for reserved and root bus PE, which 28563803c39SGavin Shan * are first or last two PEs. 28699451551SGavin Shan */ 28799451551SGavin Shan r = &phb->hose->mem_resources[1]; 28899451551SGavin Shan if (phb->ioda.reserved_pe_idx == 0) 28963803c39SGavin Shan r->start += (2 * phb->ioda.m64_segsize); 29099451551SGavin Shan else if (phb->ioda.reserved_pe_idx == (phb->ioda.total_pe_num - 1)) 29163803c39SGavin Shan r->end -= (2 * phb->ioda.m64_segsize); 29299451551SGavin Shan else 29399451551SGavin Shan WARN(1, "Wrong reserved PE#%d on PHB#%d\n", 29499451551SGavin Shan phb->ioda.reserved_pe_idx, phb->hose->global_number); 29599451551SGavin Shan 29699451551SGavin Shan return 0; 29799451551SGavin Shan 29899451551SGavin Shan fail: 29999451551SGavin Shan for ( ; index >= 0; index--) 30099451551SGavin Shan opal_pci_phb_mmio_enable(phb->opal_id, 30199451551SGavin Shan OPAL_M64_WINDOW_TYPE, index, OPAL_DISABLE_M64); 30299451551SGavin Shan 30399451551SGavin Shan return -EIO; 30499451551SGavin Shan } 30599451551SGavin Shan 306c430670aSGavin Shan static void pnv_ioda_reserve_m64_pe(struct pci_bus *bus, 30796a2f92bSGavin Shan unsigned long *pe_bitmap, 30896a2f92bSGavin Shan bool all) 309262af557SGuo Chao { 310262af557SGuo Chao struct pci_dev *pdev; 31196a2f92bSGavin Shan 31296a2f92bSGavin Shan list_for_each_entry(pdev, &bus->devices, bus_list) { 313c430670aSGavin Shan pnv_ioda_reserve_dev_m64_pe(pdev, pe_bitmap); 31496a2f92bSGavin Shan 31596a2f92bSGavin Shan if (all && pdev->subordinate) 316c430670aSGavin Shan pnv_ioda_reserve_m64_pe(pdev->subordinate, 31796a2f92bSGavin Shan pe_bitmap, all); 31896a2f92bSGavin Shan } 31996a2f92bSGavin Shan } 32096a2f92bSGavin Shan 3211e916772SGavin Shan static struct pnv_ioda_pe *pnv_ioda_pick_m64_pe(struct pci_bus *bus, bool all) 322262af557SGuo Chao { 32326ba248dSGavin Shan struct pci_controller *hose = pci_bus_to_host(bus); 32426ba248dSGavin Shan struct pnv_phb *phb = hose->private_data; 325262af557SGuo Chao struct pnv_ioda_pe *master_pe, *pe; 326262af557SGuo Chao unsigned long size, *pe_alloc; 32726ba248dSGavin Shan int i; 328262af557SGuo Chao 329262af557SGuo Chao /* Root bus shouldn't use M64 */ 330262af557SGuo Chao if (pci_is_root_bus(bus)) 3311e916772SGavin Shan return NULL; 332262af557SGuo Chao 333262af557SGuo Chao /* Allocate bitmap */ 33492b8f137SGavin Shan size = _ALIGN_UP(phb->ioda.total_pe_num / 8, sizeof(unsigned long)); 335262af557SGuo Chao pe_alloc = kzalloc(size, GFP_KERNEL); 336262af557SGuo Chao if (!pe_alloc) { 337262af557SGuo Chao pr_warn("%s: Out of memory !\n", 338262af557SGuo Chao __func__); 3391e916772SGavin Shan return NULL; 340262af557SGuo Chao } 341262af557SGuo Chao 34226ba248dSGavin Shan /* Figure out reserved PE numbers by the PE */ 343c430670aSGavin Shan pnv_ioda_reserve_m64_pe(bus, pe_alloc, all); 344262af557SGuo Chao 345262af557SGuo Chao /* 346262af557SGuo Chao * the current bus might not own M64 window and that's all 347262af557SGuo Chao * contributed by its child buses. For the case, we needn't 348262af557SGuo Chao * pick M64 dependent PE#. 349262af557SGuo Chao */ 35092b8f137SGavin Shan if (bitmap_empty(pe_alloc, phb->ioda.total_pe_num)) { 351262af557SGuo Chao kfree(pe_alloc); 3521e916772SGavin Shan return NULL; 353262af557SGuo Chao } 354262af557SGuo Chao 355262af557SGuo Chao /* 356262af557SGuo Chao * Figure out the master PE and put all slave PEs to master 357262af557SGuo Chao * PE's list to form compound PE. 358262af557SGuo Chao */ 359262af557SGuo Chao master_pe = NULL; 360262af557SGuo Chao i = -1; 36192b8f137SGavin Shan while ((i = find_next_bit(pe_alloc, phb->ioda.total_pe_num, i + 1)) < 36292b8f137SGavin Shan phb->ioda.total_pe_num) { 363262af557SGuo Chao pe = &phb->ioda.pe_array[i]; 364262af557SGuo Chao 36593289d8cSGavin Shan phb->ioda.m64_segmap[pe->pe_number] = pe->pe_number; 366262af557SGuo Chao if (!master_pe) { 367262af557SGuo Chao pe->flags |= PNV_IODA_PE_MASTER; 368262af557SGuo Chao INIT_LIST_HEAD(&pe->slaves); 369262af557SGuo Chao master_pe = pe; 370262af557SGuo Chao } else { 371262af557SGuo Chao pe->flags |= PNV_IODA_PE_SLAVE; 372262af557SGuo Chao pe->master = master_pe; 373262af557SGuo Chao list_add_tail(&pe->list, &master_pe->slaves); 374262af557SGuo Chao } 37599451551SGavin Shan 37699451551SGavin Shan /* 37799451551SGavin Shan * P7IOC supports M64DT, which helps mapping M64 segment 37899451551SGavin Shan * to one particular PE#. However, PHB3 has fixed mapping 37999451551SGavin Shan * between M64 segment and PE#. In order to have same logic 38099451551SGavin Shan * for P7IOC and PHB3, we enforce fixed mapping between M64 38199451551SGavin Shan * segment and PE# on P7IOC. 38299451551SGavin Shan */ 38399451551SGavin Shan if (phb->type == PNV_PHB_IODA1) { 38499451551SGavin Shan int64_t rc; 38599451551SGavin Shan 38699451551SGavin Shan rc = opal_pci_map_pe_mmio_window(phb->opal_id, 38799451551SGavin Shan pe->pe_number, OPAL_M64_WINDOW_TYPE, 38899451551SGavin Shan pe->pe_number / PNV_IODA1_M64_SEGS, 38999451551SGavin Shan pe->pe_number % PNV_IODA1_M64_SEGS); 39099451551SGavin Shan if (rc != OPAL_SUCCESS) 39199451551SGavin Shan pr_warn("%s: Error %lld mapping M64 for PHB#%d-PE#%d\n", 39299451551SGavin Shan __func__, rc, phb->hose->global_number, 39399451551SGavin Shan pe->pe_number); 39499451551SGavin Shan } 395262af557SGuo Chao } 396262af557SGuo Chao 397262af557SGuo Chao kfree(pe_alloc); 3981e916772SGavin Shan return master_pe; 399262af557SGuo Chao } 400262af557SGuo Chao 401262af557SGuo Chao static void __init pnv_ioda_parse_m64_window(struct pnv_phb *phb) 402262af557SGuo Chao { 403262af557SGuo Chao struct pci_controller *hose = phb->hose; 404262af557SGuo Chao struct device_node *dn = hose->dn; 405262af557SGuo Chao struct resource *res; 406262af557SGuo Chao const u32 *r; 407262af557SGuo Chao u64 pci_addr; 408262af557SGuo Chao 40999451551SGavin Shan if (phb->type != PNV_PHB_IODA1 && phb->type != PNV_PHB_IODA2) { 4101665c4a8SGavin Shan pr_info(" Not support M64 window\n"); 4111665c4a8SGavin Shan return; 4121665c4a8SGavin Shan } 4131665c4a8SGavin Shan 414e4d54f71SStewart Smith if (!firmware_has_feature(FW_FEATURE_OPAL)) { 415262af557SGuo Chao pr_info(" Firmware too old to support M64 window\n"); 416262af557SGuo Chao return; 417262af557SGuo Chao } 418262af557SGuo Chao 419262af557SGuo Chao r = of_get_property(dn, "ibm,opal-m64-window", NULL); 420262af557SGuo Chao if (!r) { 421262af557SGuo Chao pr_info(" No <ibm,opal-m64-window> on %s\n", 422262af557SGuo Chao dn->full_name); 423262af557SGuo Chao return; 424262af557SGuo Chao } 425262af557SGuo Chao 426262af557SGuo Chao res = &hose->mem_resources[1]; 427e80c4e7cSGavin Shan res->name = dn->full_name; 428262af557SGuo Chao res->start = of_translate_address(dn, r + 2); 429262af557SGuo Chao res->end = res->start + of_read_number(r + 4, 2) - 1; 430262af557SGuo Chao res->flags = (IORESOURCE_MEM | IORESOURCE_MEM_64 | IORESOURCE_PREFETCH); 431262af557SGuo Chao pci_addr = of_read_number(r, 2); 432262af557SGuo Chao hose->mem_offset[1] = res->start - pci_addr; 433262af557SGuo Chao 434262af557SGuo Chao phb->ioda.m64_size = resource_size(res); 43592b8f137SGavin Shan phb->ioda.m64_segsize = phb->ioda.m64_size / phb->ioda.total_pe_num; 436262af557SGuo Chao phb->ioda.m64_base = pci_addr; 437262af557SGuo Chao 438e9863e68SWei Yang pr_info(" MEM64 0x%016llx..0x%016llx -> 0x%016llx\n", 439e9863e68SWei Yang res->start, res->end, pci_addr); 440e9863e68SWei Yang 441262af557SGuo Chao /* Use last M64 BAR to cover M64 window */ 442262af557SGuo Chao phb->ioda.m64_bar_idx = 15; 44399451551SGavin Shan if (phb->type == PNV_PHB_IODA1) 44499451551SGavin Shan phb->init_m64 = pnv_ioda1_init_m64; 44599451551SGavin Shan else 446262af557SGuo Chao phb->init_m64 = pnv_ioda2_init_m64; 447c430670aSGavin Shan phb->reserve_m64_pe = pnv_ioda_reserve_m64_pe; 448c430670aSGavin Shan phb->pick_m64_pe = pnv_ioda_pick_m64_pe; 449262af557SGuo Chao } 450262af557SGuo Chao 45149dec922SGavin Shan static void pnv_ioda_freeze_pe(struct pnv_phb *phb, int pe_no) 45249dec922SGavin Shan { 45349dec922SGavin Shan struct pnv_ioda_pe *pe = &phb->ioda.pe_array[pe_no]; 45449dec922SGavin Shan struct pnv_ioda_pe *slave; 45549dec922SGavin Shan s64 rc; 45649dec922SGavin Shan 45749dec922SGavin Shan /* Fetch master PE */ 45849dec922SGavin Shan if (pe->flags & PNV_IODA_PE_SLAVE) { 45949dec922SGavin Shan pe = pe->master; 460ec8e4e9dSGavin Shan if (WARN_ON(!pe || !(pe->flags & PNV_IODA_PE_MASTER))) 461ec8e4e9dSGavin Shan return; 462ec8e4e9dSGavin Shan 46349dec922SGavin Shan pe_no = pe->pe_number; 46449dec922SGavin Shan } 46549dec922SGavin Shan 46649dec922SGavin Shan /* Freeze master PE */ 46749dec922SGavin Shan rc = opal_pci_eeh_freeze_set(phb->opal_id, 46849dec922SGavin Shan pe_no, 46949dec922SGavin Shan OPAL_EEH_ACTION_SET_FREEZE_ALL); 47049dec922SGavin Shan if (rc != OPAL_SUCCESS) { 47149dec922SGavin Shan pr_warn("%s: Failure %lld freezing PHB#%x-PE#%x\n", 47249dec922SGavin Shan __func__, rc, phb->hose->global_number, pe_no); 47349dec922SGavin Shan return; 47449dec922SGavin Shan } 47549dec922SGavin Shan 47649dec922SGavin Shan /* Freeze slave PEs */ 47749dec922SGavin Shan if (!(pe->flags & PNV_IODA_PE_MASTER)) 47849dec922SGavin Shan return; 47949dec922SGavin Shan 48049dec922SGavin Shan list_for_each_entry(slave, &pe->slaves, list) { 48149dec922SGavin Shan rc = opal_pci_eeh_freeze_set(phb->opal_id, 48249dec922SGavin Shan slave->pe_number, 48349dec922SGavin Shan OPAL_EEH_ACTION_SET_FREEZE_ALL); 48449dec922SGavin Shan if (rc != OPAL_SUCCESS) 48549dec922SGavin Shan pr_warn("%s: Failure %lld freezing PHB#%x-PE#%x\n", 48649dec922SGavin Shan __func__, rc, phb->hose->global_number, 48749dec922SGavin Shan slave->pe_number); 48849dec922SGavin Shan } 48949dec922SGavin Shan } 49049dec922SGavin Shan 491e51df2c1SAnton Blanchard static int pnv_ioda_unfreeze_pe(struct pnv_phb *phb, int pe_no, int opt) 49249dec922SGavin Shan { 49349dec922SGavin Shan struct pnv_ioda_pe *pe, *slave; 49449dec922SGavin Shan s64 rc; 49549dec922SGavin Shan 49649dec922SGavin Shan /* Find master PE */ 49749dec922SGavin Shan pe = &phb->ioda.pe_array[pe_no]; 49849dec922SGavin Shan if (pe->flags & PNV_IODA_PE_SLAVE) { 49949dec922SGavin Shan pe = pe->master; 50049dec922SGavin Shan WARN_ON(!pe || !(pe->flags & PNV_IODA_PE_MASTER)); 50149dec922SGavin Shan pe_no = pe->pe_number; 50249dec922SGavin Shan } 50349dec922SGavin Shan 50449dec922SGavin Shan /* Clear frozen state for master PE */ 50549dec922SGavin Shan rc = opal_pci_eeh_freeze_clear(phb->opal_id, pe_no, opt); 50649dec922SGavin Shan if (rc != OPAL_SUCCESS) { 50749dec922SGavin Shan pr_warn("%s: Failure %lld clear %d on PHB#%x-PE#%x\n", 50849dec922SGavin Shan __func__, rc, opt, phb->hose->global_number, pe_no); 50949dec922SGavin Shan return -EIO; 51049dec922SGavin Shan } 51149dec922SGavin Shan 51249dec922SGavin Shan if (!(pe->flags & PNV_IODA_PE_MASTER)) 51349dec922SGavin Shan return 0; 51449dec922SGavin Shan 51549dec922SGavin Shan /* Clear frozen state for slave PEs */ 51649dec922SGavin Shan list_for_each_entry(slave, &pe->slaves, list) { 51749dec922SGavin Shan rc = opal_pci_eeh_freeze_clear(phb->opal_id, 51849dec922SGavin Shan slave->pe_number, 51949dec922SGavin Shan opt); 52049dec922SGavin Shan if (rc != OPAL_SUCCESS) { 52149dec922SGavin Shan pr_warn("%s: Failure %lld clear %d on PHB#%x-PE#%x\n", 52249dec922SGavin Shan __func__, rc, opt, phb->hose->global_number, 52349dec922SGavin Shan slave->pe_number); 52449dec922SGavin Shan return -EIO; 52549dec922SGavin Shan } 52649dec922SGavin Shan } 52749dec922SGavin Shan 52849dec922SGavin Shan return 0; 52949dec922SGavin Shan } 53049dec922SGavin Shan 53149dec922SGavin Shan static int pnv_ioda_get_pe_state(struct pnv_phb *phb, int pe_no) 53249dec922SGavin Shan { 53349dec922SGavin Shan struct pnv_ioda_pe *slave, *pe; 53449dec922SGavin Shan u8 fstate, state; 53549dec922SGavin Shan __be16 pcierr; 53649dec922SGavin Shan s64 rc; 53749dec922SGavin Shan 53849dec922SGavin Shan /* Sanity check on PE number */ 53992b8f137SGavin Shan if (pe_no < 0 || pe_no >= phb->ioda.total_pe_num) 54049dec922SGavin Shan return OPAL_EEH_STOPPED_PERM_UNAVAIL; 54149dec922SGavin Shan 54249dec922SGavin Shan /* 54349dec922SGavin Shan * Fetch the master PE and the PE instance might be 54449dec922SGavin Shan * not initialized yet. 54549dec922SGavin Shan */ 54649dec922SGavin Shan pe = &phb->ioda.pe_array[pe_no]; 54749dec922SGavin Shan if (pe->flags & PNV_IODA_PE_SLAVE) { 54849dec922SGavin Shan pe = pe->master; 54949dec922SGavin Shan WARN_ON(!pe || !(pe->flags & PNV_IODA_PE_MASTER)); 55049dec922SGavin Shan pe_no = pe->pe_number; 55149dec922SGavin Shan } 55249dec922SGavin Shan 55349dec922SGavin Shan /* Check the master PE */ 55449dec922SGavin Shan rc = opal_pci_eeh_freeze_status(phb->opal_id, pe_no, 55549dec922SGavin Shan &state, &pcierr, NULL); 55649dec922SGavin Shan if (rc != OPAL_SUCCESS) { 55749dec922SGavin Shan pr_warn("%s: Failure %lld getting " 55849dec922SGavin Shan "PHB#%x-PE#%x state\n", 55949dec922SGavin Shan __func__, rc, 56049dec922SGavin Shan phb->hose->global_number, pe_no); 56149dec922SGavin Shan return OPAL_EEH_STOPPED_TEMP_UNAVAIL; 56249dec922SGavin Shan } 56349dec922SGavin Shan 56449dec922SGavin Shan /* Check the slave PE */ 56549dec922SGavin Shan if (!(pe->flags & PNV_IODA_PE_MASTER)) 56649dec922SGavin Shan return state; 56749dec922SGavin Shan 56849dec922SGavin Shan list_for_each_entry(slave, &pe->slaves, list) { 56949dec922SGavin Shan rc = opal_pci_eeh_freeze_status(phb->opal_id, 57049dec922SGavin Shan slave->pe_number, 57149dec922SGavin Shan &fstate, 57249dec922SGavin Shan &pcierr, 57349dec922SGavin Shan NULL); 57449dec922SGavin Shan if (rc != OPAL_SUCCESS) { 57549dec922SGavin Shan pr_warn("%s: Failure %lld getting " 57649dec922SGavin Shan "PHB#%x-PE#%x state\n", 57749dec922SGavin Shan __func__, rc, 57849dec922SGavin Shan phb->hose->global_number, slave->pe_number); 57949dec922SGavin Shan return OPAL_EEH_STOPPED_TEMP_UNAVAIL; 58049dec922SGavin Shan } 58149dec922SGavin Shan 58249dec922SGavin Shan /* 58349dec922SGavin Shan * Override the result based on the ascending 58449dec922SGavin Shan * priority. 58549dec922SGavin Shan */ 58649dec922SGavin Shan if (fstate > state) 58749dec922SGavin Shan state = fstate; 58849dec922SGavin Shan } 58949dec922SGavin Shan 59049dec922SGavin Shan return state; 59149dec922SGavin Shan } 59249dec922SGavin Shan 593184cd4a3SBenjamin Herrenschmidt /* Currently those 2 are only used when MSIs are enabled, this will change 594184cd4a3SBenjamin Herrenschmidt * but in the meantime, we need to protect them to avoid warnings 595184cd4a3SBenjamin Herrenschmidt */ 596184cd4a3SBenjamin Herrenschmidt #ifdef CONFIG_PCI_MSI 597cad5cef6SGreg Kroah-Hartman static struct pnv_ioda_pe *pnv_ioda_get_pe(struct pci_dev *dev) 598184cd4a3SBenjamin Herrenschmidt { 599184cd4a3SBenjamin Herrenschmidt struct pci_controller *hose = pci_bus_to_host(dev->bus); 600184cd4a3SBenjamin Herrenschmidt struct pnv_phb *phb = hose->private_data; 601b72c1f65SBenjamin Herrenschmidt struct pci_dn *pdn = pci_get_pdn(dev); 602184cd4a3SBenjamin Herrenschmidt 603184cd4a3SBenjamin Herrenschmidt if (!pdn) 604184cd4a3SBenjamin Herrenschmidt return NULL; 605184cd4a3SBenjamin Herrenschmidt if (pdn->pe_number == IODA_INVALID_PE) 606184cd4a3SBenjamin Herrenschmidt return NULL; 607184cd4a3SBenjamin Herrenschmidt return &phb->ioda.pe_array[pdn->pe_number]; 608184cd4a3SBenjamin Herrenschmidt } 609184cd4a3SBenjamin Herrenschmidt #endif /* CONFIG_PCI_MSI */ 610184cd4a3SBenjamin Herrenschmidt 611b131a842SGavin Shan static int pnv_ioda_set_one_peltv(struct pnv_phb *phb, 612b131a842SGavin Shan struct pnv_ioda_pe *parent, 613b131a842SGavin Shan struct pnv_ioda_pe *child, 614b131a842SGavin Shan bool is_add) 615b131a842SGavin Shan { 616b131a842SGavin Shan const char *desc = is_add ? "adding" : "removing"; 617b131a842SGavin Shan uint8_t op = is_add ? OPAL_ADD_PE_TO_DOMAIN : 618b131a842SGavin Shan OPAL_REMOVE_PE_FROM_DOMAIN; 619b131a842SGavin Shan struct pnv_ioda_pe *slave; 620b131a842SGavin Shan long rc; 621b131a842SGavin Shan 622b131a842SGavin Shan /* Parent PE affects child PE */ 623b131a842SGavin Shan rc = opal_pci_set_peltv(phb->opal_id, parent->pe_number, 624b131a842SGavin Shan child->pe_number, op); 625b131a842SGavin Shan if (rc != OPAL_SUCCESS) { 626b131a842SGavin Shan pe_warn(child, "OPAL error %ld %s to parent PELTV\n", 627b131a842SGavin Shan rc, desc); 628b131a842SGavin Shan return -ENXIO; 629b131a842SGavin Shan } 630b131a842SGavin Shan 631b131a842SGavin Shan if (!(child->flags & PNV_IODA_PE_MASTER)) 632b131a842SGavin Shan return 0; 633b131a842SGavin Shan 634b131a842SGavin Shan /* Compound case: parent PE affects slave PEs */ 635b131a842SGavin Shan list_for_each_entry(slave, &child->slaves, list) { 636b131a842SGavin Shan rc = opal_pci_set_peltv(phb->opal_id, parent->pe_number, 637b131a842SGavin Shan slave->pe_number, op); 638b131a842SGavin Shan if (rc != OPAL_SUCCESS) { 639b131a842SGavin Shan pe_warn(slave, "OPAL error %ld %s to parent PELTV\n", 640b131a842SGavin Shan rc, desc); 641b131a842SGavin Shan return -ENXIO; 642b131a842SGavin Shan } 643b131a842SGavin Shan } 644b131a842SGavin Shan 645b131a842SGavin Shan return 0; 646b131a842SGavin Shan } 647b131a842SGavin Shan 648b131a842SGavin Shan static int pnv_ioda_set_peltv(struct pnv_phb *phb, 649b131a842SGavin Shan struct pnv_ioda_pe *pe, 650b131a842SGavin Shan bool is_add) 651b131a842SGavin Shan { 652b131a842SGavin Shan struct pnv_ioda_pe *slave; 653781a868fSWei Yang struct pci_dev *pdev = NULL; 654b131a842SGavin Shan int ret; 655b131a842SGavin Shan 656b131a842SGavin Shan /* 657b131a842SGavin Shan * Clear PE frozen state. If it's master PE, we need 658b131a842SGavin Shan * clear slave PE frozen state as well. 659b131a842SGavin Shan */ 660b131a842SGavin Shan if (is_add) { 661b131a842SGavin Shan opal_pci_eeh_freeze_clear(phb->opal_id, pe->pe_number, 662b131a842SGavin Shan OPAL_EEH_ACTION_CLEAR_FREEZE_ALL); 663b131a842SGavin Shan if (pe->flags & PNV_IODA_PE_MASTER) { 664b131a842SGavin Shan list_for_each_entry(slave, &pe->slaves, list) 665b131a842SGavin Shan opal_pci_eeh_freeze_clear(phb->opal_id, 666b131a842SGavin Shan slave->pe_number, 667b131a842SGavin Shan OPAL_EEH_ACTION_CLEAR_FREEZE_ALL); 668b131a842SGavin Shan } 669b131a842SGavin Shan } 670b131a842SGavin Shan 671b131a842SGavin Shan /* 672b131a842SGavin Shan * Associate PE in PELT. We need add the PE into the 673b131a842SGavin Shan * corresponding PELT-V as well. Otherwise, the error 674b131a842SGavin Shan * originated from the PE might contribute to other 675b131a842SGavin Shan * PEs. 676b131a842SGavin Shan */ 677b131a842SGavin Shan ret = pnv_ioda_set_one_peltv(phb, pe, pe, is_add); 678b131a842SGavin Shan if (ret) 679b131a842SGavin Shan return ret; 680b131a842SGavin Shan 681b131a842SGavin Shan /* For compound PEs, any one affects all of them */ 682b131a842SGavin Shan if (pe->flags & PNV_IODA_PE_MASTER) { 683b131a842SGavin Shan list_for_each_entry(slave, &pe->slaves, list) { 684b131a842SGavin Shan ret = pnv_ioda_set_one_peltv(phb, slave, pe, is_add); 685b131a842SGavin Shan if (ret) 686b131a842SGavin Shan return ret; 687b131a842SGavin Shan } 688b131a842SGavin Shan } 689b131a842SGavin Shan 690b131a842SGavin Shan if (pe->flags & (PNV_IODA_PE_BUS_ALL | PNV_IODA_PE_BUS)) 691b131a842SGavin Shan pdev = pe->pbus->self; 692781a868fSWei Yang else if (pe->flags & PNV_IODA_PE_DEV) 693b131a842SGavin Shan pdev = pe->pdev->bus->self; 694781a868fSWei Yang #ifdef CONFIG_PCI_IOV 695781a868fSWei Yang else if (pe->flags & PNV_IODA_PE_VF) 696283e2d8aSGavin Shan pdev = pe->parent_dev; 697781a868fSWei Yang #endif /* CONFIG_PCI_IOV */ 698b131a842SGavin Shan while (pdev) { 699b131a842SGavin Shan struct pci_dn *pdn = pci_get_pdn(pdev); 700b131a842SGavin Shan struct pnv_ioda_pe *parent; 701b131a842SGavin Shan 702b131a842SGavin Shan if (pdn && pdn->pe_number != IODA_INVALID_PE) { 703b131a842SGavin Shan parent = &phb->ioda.pe_array[pdn->pe_number]; 704b131a842SGavin Shan ret = pnv_ioda_set_one_peltv(phb, parent, pe, is_add); 705b131a842SGavin Shan if (ret) 706b131a842SGavin Shan return ret; 707b131a842SGavin Shan } 708b131a842SGavin Shan 709b131a842SGavin Shan pdev = pdev->bus->self; 710b131a842SGavin Shan } 711b131a842SGavin Shan 712b131a842SGavin Shan return 0; 713b131a842SGavin Shan } 714b131a842SGavin Shan 715781a868fSWei Yang static int pnv_ioda_deconfigure_pe(struct pnv_phb *phb, struct pnv_ioda_pe *pe) 716781a868fSWei Yang { 717781a868fSWei Yang struct pci_dev *parent; 718781a868fSWei Yang uint8_t bcomp, dcomp, fcomp; 719781a868fSWei Yang int64_t rc; 720781a868fSWei Yang long rid_end, rid; 721781a868fSWei Yang 722781a868fSWei Yang /* Currently, we just deconfigure VF PE. Bus PE will always there.*/ 723781a868fSWei Yang if (pe->pbus) { 724781a868fSWei Yang int count; 725781a868fSWei Yang 726781a868fSWei Yang dcomp = OPAL_IGNORE_RID_DEVICE_NUMBER; 727781a868fSWei Yang fcomp = OPAL_IGNORE_RID_FUNCTION_NUMBER; 728781a868fSWei Yang parent = pe->pbus->self; 729781a868fSWei Yang if (pe->flags & PNV_IODA_PE_BUS_ALL) 730781a868fSWei Yang count = pe->pbus->busn_res.end - pe->pbus->busn_res.start + 1; 731781a868fSWei Yang else 732781a868fSWei Yang count = 1; 733781a868fSWei Yang 734781a868fSWei Yang switch(count) { 735781a868fSWei Yang case 1: bcomp = OpalPciBusAll; break; 736781a868fSWei Yang case 2: bcomp = OpalPciBus7Bits; break; 737781a868fSWei Yang case 4: bcomp = OpalPciBus6Bits; break; 738781a868fSWei Yang case 8: bcomp = OpalPciBus5Bits; break; 739781a868fSWei Yang case 16: bcomp = OpalPciBus4Bits; break; 740781a868fSWei Yang case 32: bcomp = OpalPciBus3Bits; break; 741781a868fSWei Yang default: 742781a868fSWei Yang dev_err(&pe->pbus->dev, "Number of subordinate buses %d unsupported\n", 743781a868fSWei Yang count); 744781a868fSWei Yang /* Do an exact match only */ 745781a868fSWei Yang bcomp = OpalPciBusAll; 746781a868fSWei Yang } 747781a868fSWei Yang rid_end = pe->rid + (count << 8); 748781a868fSWei Yang } else { 74993e01a50SGavin Shan #ifdef CONFIG_PCI_IOV 750781a868fSWei Yang if (pe->flags & PNV_IODA_PE_VF) 751781a868fSWei Yang parent = pe->parent_dev; 752781a868fSWei Yang else 75393e01a50SGavin Shan #endif 754781a868fSWei Yang parent = pe->pdev->bus->self; 755781a868fSWei Yang bcomp = OpalPciBusAll; 756781a868fSWei Yang dcomp = OPAL_COMPARE_RID_DEVICE_NUMBER; 757781a868fSWei Yang fcomp = OPAL_COMPARE_RID_FUNCTION_NUMBER; 758781a868fSWei Yang rid_end = pe->rid + 1; 759781a868fSWei Yang } 760781a868fSWei Yang 761781a868fSWei Yang /* Clear the reverse map */ 762781a868fSWei Yang for (rid = pe->rid; rid < rid_end; rid++) 763c127562aSGavin Shan phb->ioda.pe_rmap[rid] = IODA_INVALID_PE; 764781a868fSWei Yang 765781a868fSWei Yang /* Release from all parents PELT-V */ 766781a868fSWei Yang while (parent) { 767781a868fSWei Yang struct pci_dn *pdn = pci_get_pdn(parent); 768781a868fSWei Yang if (pdn && pdn->pe_number != IODA_INVALID_PE) { 769781a868fSWei Yang rc = opal_pci_set_peltv(phb->opal_id, pdn->pe_number, 770781a868fSWei Yang pe->pe_number, OPAL_REMOVE_PE_FROM_DOMAIN); 771781a868fSWei Yang /* XXX What to do in case of error ? */ 772781a868fSWei Yang } 773781a868fSWei Yang parent = parent->bus->self; 774781a868fSWei Yang } 775781a868fSWei Yang 776f951e510SGavin Shan opal_pci_eeh_freeze_clear(phb->opal_id, pe->pe_number, 777781a868fSWei Yang OPAL_EEH_ACTION_CLEAR_FREEZE_ALL); 778781a868fSWei Yang 779781a868fSWei Yang /* Disassociate PE in PELT */ 780781a868fSWei Yang rc = opal_pci_set_peltv(phb->opal_id, pe->pe_number, 781781a868fSWei Yang pe->pe_number, OPAL_REMOVE_PE_FROM_DOMAIN); 782781a868fSWei Yang if (rc) 783781a868fSWei Yang pe_warn(pe, "OPAL error %ld remove self from PELTV\n", rc); 784781a868fSWei Yang rc = opal_pci_set_pe(phb->opal_id, pe->pe_number, pe->rid, 785781a868fSWei Yang bcomp, dcomp, fcomp, OPAL_UNMAP_PE); 786781a868fSWei Yang if (rc) 787781a868fSWei Yang pe_err(pe, "OPAL error %ld trying to setup PELT table\n", rc); 788781a868fSWei Yang 789781a868fSWei Yang pe->pbus = NULL; 790781a868fSWei Yang pe->pdev = NULL; 79193e01a50SGavin Shan #ifdef CONFIG_PCI_IOV 792781a868fSWei Yang pe->parent_dev = NULL; 79393e01a50SGavin Shan #endif 794781a868fSWei Yang 795781a868fSWei Yang return 0; 796781a868fSWei Yang } 797781a868fSWei Yang 798cad5cef6SGreg Kroah-Hartman static int pnv_ioda_configure_pe(struct pnv_phb *phb, struct pnv_ioda_pe *pe) 799184cd4a3SBenjamin Herrenschmidt { 800184cd4a3SBenjamin Herrenschmidt struct pci_dev *parent; 801184cd4a3SBenjamin Herrenschmidt uint8_t bcomp, dcomp, fcomp; 802184cd4a3SBenjamin Herrenschmidt long rc, rid_end, rid; 803184cd4a3SBenjamin Herrenschmidt 804184cd4a3SBenjamin Herrenschmidt /* Bus validation ? */ 805184cd4a3SBenjamin Herrenschmidt if (pe->pbus) { 806184cd4a3SBenjamin Herrenschmidt int count; 807184cd4a3SBenjamin Herrenschmidt 808184cd4a3SBenjamin Herrenschmidt dcomp = OPAL_IGNORE_RID_DEVICE_NUMBER; 809184cd4a3SBenjamin Herrenschmidt fcomp = OPAL_IGNORE_RID_FUNCTION_NUMBER; 810184cd4a3SBenjamin Herrenschmidt parent = pe->pbus->self; 811fb446ad0SGavin Shan if (pe->flags & PNV_IODA_PE_BUS_ALL) 812b918c62eSYinghai Lu count = pe->pbus->busn_res.end - pe->pbus->busn_res.start + 1; 813fb446ad0SGavin Shan else 814fb446ad0SGavin Shan count = 1; 815fb446ad0SGavin Shan 816184cd4a3SBenjamin Herrenschmidt switch(count) { 817184cd4a3SBenjamin Herrenschmidt case 1: bcomp = OpalPciBusAll; break; 818184cd4a3SBenjamin Herrenschmidt case 2: bcomp = OpalPciBus7Bits; break; 819184cd4a3SBenjamin Herrenschmidt case 4: bcomp = OpalPciBus6Bits; break; 820184cd4a3SBenjamin Herrenschmidt case 8: bcomp = OpalPciBus5Bits; break; 821184cd4a3SBenjamin Herrenschmidt case 16: bcomp = OpalPciBus4Bits; break; 822184cd4a3SBenjamin Herrenschmidt case 32: bcomp = OpalPciBus3Bits; break; 823184cd4a3SBenjamin Herrenschmidt default: 824781a868fSWei Yang dev_err(&pe->pbus->dev, "Number of subordinate buses %d unsupported\n", 825781a868fSWei Yang count); 826184cd4a3SBenjamin Herrenschmidt /* Do an exact match only */ 827184cd4a3SBenjamin Herrenschmidt bcomp = OpalPciBusAll; 828184cd4a3SBenjamin Herrenschmidt } 829184cd4a3SBenjamin Herrenschmidt rid_end = pe->rid + (count << 8); 830184cd4a3SBenjamin Herrenschmidt } else { 831781a868fSWei Yang #ifdef CONFIG_PCI_IOV 832781a868fSWei Yang if (pe->flags & PNV_IODA_PE_VF) 833781a868fSWei Yang parent = pe->parent_dev; 834781a868fSWei Yang else 835781a868fSWei Yang #endif /* CONFIG_PCI_IOV */ 836184cd4a3SBenjamin Herrenschmidt parent = pe->pdev->bus->self; 837184cd4a3SBenjamin Herrenschmidt bcomp = OpalPciBusAll; 838184cd4a3SBenjamin Herrenschmidt dcomp = OPAL_COMPARE_RID_DEVICE_NUMBER; 839184cd4a3SBenjamin Herrenschmidt fcomp = OPAL_COMPARE_RID_FUNCTION_NUMBER; 840184cd4a3SBenjamin Herrenschmidt rid_end = pe->rid + 1; 841184cd4a3SBenjamin Herrenschmidt } 842184cd4a3SBenjamin Herrenschmidt 843631ad691SGavin Shan /* 844631ad691SGavin Shan * Associate PE in PELT. We need add the PE into the 845631ad691SGavin Shan * corresponding PELT-V as well. Otherwise, the error 846631ad691SGavin Shan * originated from the PE might contribute to other 847631ad691SGavin Shan * PEs. 848631ad691SGavin Shan */ 849184cd4a3SBenjamin Herrenschmidt rc = opal_pci_set_pe(phb->opal_id, pe->pe_number, pe->rid, 850184cd4a3SBenjamin Herrenschmidt bcomp, dcomp, fcomp, OPAL_MAP_PE); 851184cd4a3SBenjamin Herrenschmidt if (rc) { 852184cd4a3SBenjamin Herrenschmidt pe_err(pe, "OPAL error %ld trying to setup PELT table\n", rc); 853184cd4a3SBenjamin Herrenschmidt return -ENXIO; 854184cd4a3SBenjamin Herrenschmidt } 855631ad691SGavin Shan 8565d2aa710SAlistair Popple /* 8575d2aa710SAlistair Popple * Configure PELTV. NPUs don't have a PELTV table so skip 8585d2aa710SAlistair Popple * configuration on them. 8595d2aa710SAlistair Popple */ 8605d2aa710SAlistair Popple if (phb->type != PNV_PHB_NPU) 861b131a842SGavin Shan pnv_ioda_set_peltv(phb, pe, true); 862184cd4a3SBenjamin Herrenschmidt 863184cd4a3SBenjamin Herrenschmidt /* Setup reverse map */ 864184cd4a3SBenjamin Herrenschmidt for (rid = pe->rid; rid < rid_end; rid++) 865184cd4a3SBenjamin Herrenschmidt phb->ioda.pe_rmap[rid] = pe->pe_number; 866184cd4a3SBenjamin Herrenschmidt 867184cd4a3SBenjamin Herrenschmidt /* Setup one MVTs on IODA1 */ 8684773f76bSGavin Shan if (phb->type != PNV_PHB_IODA1) { 8694773f76bSGavin Shan pe->mve_number = 0; 8704773f76bSGavin Shan goto out; 8714773f76bSGavin Shan } 8724773f76bSGavin Shan 873184cd4a3SBenjamin Herrenschmidt pe->mve_number = pe->pe_number; 8744773f76bSGavin Shan rc = opal_pci_set_mve(phb->opal_id, pe->mve_number, pe->pe_number); 8754773f76bSGavin Shan if (rc != OPAL_SUCCESS) { 876184cd4a3SBenjamin Herrenschmidt pe_err(pe, "OPAL error %ld setting up MVE %d\n", 877184cd4a3SBenjamin Herrenschmidt rc, pe->mve_number); 878184cd4a3SBenjamin Herrenschmidt pe->mve_number = -1; 879184cd4a3SBenjamin Herrenschmidt } else { 880184cd4a3SBenjamin Herrenschmidt rc = opal_pci_set_mve_enable(phb->opal_id, 881cee72d5bSBenjamin Herrenschmidt pe->mve_number, OPAL_ENABLE_MVE); 882184cd4a3SBenjamin Herrenschmidt if (rc) { 883184cd4a3SBenjamin Herrenschmidt pe_err(pe, "OPAL error %ld enabling MVE %d\n", 884184cd4a3SBenjamin Herrenschmidt rc, pe->mve_number); 885184cd4a3SBenjamin Herrenschmidt pe->mve_number = -1; 886184cd4a3SBenjamin Herrenschmidt } 887184cd4a3SBenjamin Herrenschmidt } 888184cd4a3SBenjamin Herrenschmidt 8894773f76bSGavin Shan out: 890184cd4a3SBenjamin Herrenschmidt return 0; 891184cd4a3SBenjamin Herrenschmidt } 892184cd4a3SBenjamin Herrenschmidt 893781a868fSWei Yang #ifdef CONFIG_PCI_IOV 894781a868fSWei Yang static int pnv_pci_vf_resource_shift(struct pci_dev *dev, int offset) 895781a868fSWei Yang { 896781a868fSWei Yang struct pci_dn *pdn = pci_get_pdn(dev); 897781a868fSWei Yang int i; 898781a868fSWei Yang struct resource *res, res2; 899781a868fSWei Yang resource_size_t size; 900781a868fSWei Yang u16 num_vfs; 901781a868fSWei Yang 902781a868fSWei Yang if (!dev->is_physfn) 903781a868fSWei Yang return -EINVAL; 904781a868fSWei Yang 905781a868fSWei Yang /* 906781a868fSWei Yang * "offset" is in VFs. The M64 windows are sized so that when they 907781a868fSWei Yang * are segmented, each segment is the same size as the IOV BAR. 908781a868fSWei Yang * Each segment is in a separate PE, and the high order bits of the 909781a868fSWei Yang * address are the PE number. Therefore, each VF's BAR is in a 910781a868fSWei Yang * separate PE, and changing the IOV BAR start address changes the 911781a868fSWei Yang * range of PEs the VFs are in. 912781a868fSWei Yang */ 913781a868fSWei Yang num_vfs = pdn->num_vfs; 914781a868fSWei Yang for (i = 0; i < PCI_SRIOV_NUM_BARS; i++) { 915781a868fSWei Yang res = &dev->resource[i + PCI_IOV_RESOURCES]; 916781a868fSWei Yang if (!res->flags || !res->parent) 917781a868fSWei Yang continue; 918781a868fSWei Yang 919781a868fSWei Yang /* 920781a868fSWei Yang * The actual IOV BAR range is determined by the start address 921781a868fSWei Yang * and the actual size for num_vfs VFs BAR. This check is to 922781a868fSWei Yang * make sure that after shifting, the range will not overlap 923781a868fSWei Yang * with another device. 924781a868fSWei Yang */ 925781a868fSWei Yang size = pci_iov_resource_size(dev, i + PCI_IOV_RESOURCES); 926781a868fSWei Yang res2.flags = res->flags; 927781a868fSWei Yang res2.start = res->start + (size * offset); 928781a868fSWei Yang res2.end = res2.start + (size * num_vfs) - 1; 929781a868fSWei Yang 930781a868fSWei Yang if (res2.end > res->end) { 931781a868fSWei Yang dev_err(&dev->dev, "VF BAR%d: %pR would extend past %pR (trying to enable %d VFs shifted by %d)\n", 932781a868fSWei Yang i, &res2, res, num_vfs, offset); 933781a868fSWei Yang return -EBUSY; 934781a868fSWei Yang } 935781a868fSWei Yang } 936781a868fSWei Yang 937781a868fSWei Yang /* 938781a868fSWei Yang * After doing so, there would be a "hole" in the /proc/iomem when 939781a868fSWei Yang * offset is a positive value. It looks like the device return some 940781a868fSWei Yang * mmio back to the system, which actually no one could use it. 941781a868fSWei Yang */ 942781a868fSWei Yang for (i = 0; i < PCI_SRIOV_NUM_BARS; i++) { 943781a868fSWei Yang res = &dev->resource[i + PCI_IOV_RESOURCES]; 944781a868fSWei Yang if (!res->flags || !res->parent) 945781a868fSWei Yang continue; 946781a868fSWei Yang 947781a868fSWei Yang size = pci_iov_resource_size(dev, i + PCI_IOV_RESOURCES); 948781a868fSWei Yang res2 = *res; 949781a868fSWei Yang res->start += size * offset; 950781a868fSWei Yang 95174703cc4SWei Yang dev_info(&dev->dev, "VF BAR%d: %pR shifted to %pR (%sabling %d VFs shifted by %d)\n", 95274703cc4SWei Yang i, &res2, res, (offset > 0) ? "En" : "Dis", 95374703cc4SWei Yang num_vfs, offset); 954781a868fSWei Yang pci_update_resource(dev, i + PCI_IOV_RESOURCES); 955781a868fSWei Yang } 956781a868fSWei Yang return 0; 957781a868fSWei Yang } 958781a868fSWei Yang #endif /* CONFIG_PCI_IOV */ 959781a868fSWei Yang 960cad5cef6SGreg Kroah-Hartman static struct pnv_ioda_pe *pnv_ioda_setup_dev_PE(struct pci_dev *dev) 961184cd4a3SBenjamin Herrenschmidt { 962184cd4a3SBenjamin Herrenschmidt struct pci_controller *hose = pci_bus_to_host(dev->bus); 963184cd4a3SBenjamin Herrenschmidt struct pnv_phb *phb = hose->private_data; 964b72c1f65SBenjamin Herrenschmidt struct pci_dn *pdn = pci_get_pdn(dev); 965184cd4a3SBenjamin Herrenschmidt struct pnv_ioda_pe *pe; 966184cd4a3SBenjamin Herrenschmidt 967184cd4a3SBenjamin Herrenschmidt if (!pdn) { 968184cd4a3SBenjamin Herrenschmidt pr_err("%s: Device tree node not associated properly\n", 969184cd4a3SBenjamin Herrenschmidt pci_name(dev)); 970184cd4a3SBenjamin Herrenschmidt return NULL; 971184cd4a3SBenjamin Herrenschmidt } 972184cd4a3SBenjamin Herrenschmidt if (pdn->pe_number != IODA_INVALID_PE) 973184cd4a3SBenjamin Herrenschmidt return NULL; 974184cd4a3SBenjamin Herrenschmidt 9751e916772SGavin Shan pe = pnv_ioda_alloc_pe(phb); 9761e916772SGavin Shan if (!pe) { 977184cd4a3SBenjamin Herrenschmidt pr_warning("%s: Not enough PE# available, disabling device\n", 978184cd4a3SBenjamin Herrenschmidt pci_name(dev)); 979184cd4a3SBenjamin Herrenschmidt return NULL; 980184cd4a3SBenjamin Herrenschmidt } 981184cd4a3SBenjamin Herrenschmidt 982184cd4a3SBenjamin Herrenschmidt /* NOTE: We get only one ref to the pci_dev for the pdn, not for the 983184cd4a3SBenjamin Herrenschmidt * pointer in the PE data structure, both should be destroyed at the 984184cd4a3SBenjamin Herrenschmidt * same time. However, this needs to be looked at more closely again 985184cd4a3SBenjamin Herrenschmidt * once we actually start removing things (Hotplug, SR-IOV, ...) 986184cd4a3SBenjamin Herrenschmidt * 987184cd4a3SBenjamin Herrenschmidt * At some point we want to remove the PDN completely anyways 988184cd4a3SBenjamin Herrenschmidt */ 989184cd4a3SBenjamin Herrenschmidt pci_dev_get(dev); 990184cd4a3SBenjamin Herrenschmidt pdn->pcidev = dev; 9911e916772SGavin Shan pdn->pe_number = pe->pe_number; 9925d2aa710SAlistair Popple pe->flags = PNV_IODA_PE_DEV; 993184cd4a3SBenjamin Herrenschmidt pe->pdev = dev; 994184cd4a3SBenjamin Herrenschmidt pe->pbus = NULL; 995184cd4a3SBenjamin Herrenschmidt pe->mve_number = -1; 996184cd4a3SBenjamin Herrenschmidt pe->rid = dev->bus->number << 8 | pdn->devfn; 997184cd4a3SBenjamin Herrenschmidt 998184cd4a3SBenjamin Herrenschmidt pe_info(pe, "Associated device to PE\n"); 999184cd4a3SBenjamin Herrenschmidt 1000184cd4a3SBenjamin Herrenschmidt if (pnv_ioda_configure_pe(phb, pe)) { 1001184cd4a3SBenjamin Herrenschmidt /* XXX What do we do here ? */ 10021e916772SGavin Shan pnv_ioda_free_pe(pe); 1003184cd4a3SBenjamin Herrenschmidt pdn->pe_number = IODA_INVALID_PE; 1004184cd4a3SBenjamin Herrenschmidt pe->pdev = NULL; 1005184cd4a3SBenjamin Herrenschmidt pci_dev_put(dev); 1006184cd4a3SBenjamin Herrenschmidt return NULL; 1007184cd4a3SBenjamin Herrenschmidt } 1008184cd4a3SBenjamin Herrenschmidt 10091d4e89cfSAlexey Kardashevskiy /* Put PE to the list */ 10101d4e89cfSAlexey Kardashevskiy list_add_tail(&pe->list, &phb->ioda.pe_list); 10111d4e89cfSAlexey Kardashevskiy 1012184cd4a3SBenjamin Herrenschmidt return pe; 1013184cd4a3SBenjamin Herrenschmidt } 1014184cd4a3SBenjamin Herrenschmidt 1015184cd4a3SBenjamin Herrenschmidt static void pnv_ioda_setup_same_PE(struct pci_bus *bus, struct pnv_ioda_pe *pe) 1016184cd4a3SBenjamin Herrenschmidt { 1017184cd4a3SBenjamin Herrenschmidt struct pci_dev *dev; 1018184cd4a3SBenjamin Herrenschmidt 1019184cd4a3SBenjamin Herrenschmidt list_for_each_entry(dev, &bus->devices, bus_list) { 1020b72c1f65SBenjamin Herrenschmidt struct pci_dn *pdn = pci_get_pdn(dev); 1021184cd4a3SBenjamin Herrenschmidt 1022184cd4a3SBenjamin Herrenschmidt if (pdn == NULL) { 1023184cd4a3SBenjamin Herrenschmidt pr_warn("%s: No device node associated with device !\n", 1024184cd4a3SBenjamin Herrenschmidt pci_name(dev)); 1025184cd4a3SBenjamin Herrenschmidt continue; 1026184cd4a3SBenjamin Herrenschmidt } 1027ccd1c191SGavin Shan 1028ccd1c191SGavin Shan /* 1029ccd1c191SGavin Shan * In partial hotplug case, the PCI device might be still 1030ccd1c191SGavin Shan * associated with the PE and needn't attach it to the PE 1031ccd1c191SGavin Shan * again. 1032ccd1c191SGavin Shan */ 1033ccd1c191SGavin Shan if (pdn->pe_number != IODA_INVALID_PE) 1034ccd1c191SGavin Shan continue; 1035ccd1c191SGavin Shan 103694973b24SAlistair Popple pdn->pcidev = dev; 1037184cd4a3SBenjamin Herrenschmidt pdn->pe_number = pe->pe_number; 1038fb446ad0SGavin Shan if ((pe->flags & PNV_IODA_PE_BUS_ALL) && dev->subordinate) 1039184cd4a3SBenjamin Herrenschmidt pnv_ioda_setup_same_PE(dev->subordinate, pe); 1040184cd4a3SBenjamin Herrenschmidt } 1041184cd4a3SBenjamin Herrenschmidt } 1042184cd4a3SBenjamin Herrenschmidt 1043fb446ad0SGavin Shan /* 1044fb446ad0SGavin Shan * There're 2 types of PCI bus sensitive PEs: One that is compromised of 1045fb446ad0SGavin Shan * single PCI bus. Another one that contains the primary PCI bus and its 1046fb446ad0SGavin Shan * subordinate PCI devices and buses. The second type of PE is normally 1047fb446ad0SGavin Shan * orgiriated by PCIe-to-PCI bridge or PLX switch downstream ports. 1048fb446ad0SGavin Shan */ 10491e916772SGavin Shan static struct pnv_ioda_pe *pnv_ioda_setup_bus_PE(struct pci_bus *bus, bool all) 1050184cd4a3SBenjamin Herrenschmidt { 1051fb446ad0SGavin Shan struct pci_controller *hose = pci_bus_to_host(bus); 1052184cd4a3SBenjamin Herrenschmidt struct pnv_phb *phb = hose->private_data; 10531e916772SGavin Shan struct pnv_ioda_pe *pe = NULL; 1054ccd1c191SGavin Shan unsigned int pe_num; 1055ccd1c191SGavin Shan 1056ccd1c191SGavin Shan /* 1057ccd1c191SGavin Shan * In partial hotplug case, the PE instance might be still alive. 1058ccd1c191SGavin Shan * We should reuse it instead of allocating a new one. 1059ccd1c191SGavin Shan */ 1060ccd1c191SGavin Shan pe_num = phb->ioda.pe_rmap[bus->number << 8]; 1061ccd1c191SGavin Shan if (pe_num != IODA_INVALID_PE) { 1062ccd1c191SGavin Shan pe = &phb->ioda.pe_array[pe_num]; 1063ccd1c191SGavin Shan pnv_ioda_setup_same_PE(bus, pe); 1064ccd1c191SGavin Shan return NULL; 1065ccd1c191SGavin Shan } 1066184cd4a3SBenjamin Herrenschmidt 106763803c39SGavin Shan /* PE number for root bus should have been reserved */ 106863803c39SGavin Shan if (pci_is_root_bus(bus) && 106963803c39SGavin Shan phb->ioda.root_pe_idx != IODA_INVALID_PE) 107063803c39SGavin Shan pe = &phb->ioda.pe_array[phb->ioda.root_pe_idx]; 107163803c39SGavin Shan 1072262af557SGuo Chao /* Check if PE is determined by M64 */ 107363803c39SGavin Shan if (!pe && phb->pick_m64_pe) 10741e916772SGavin Shan pe = phb->pick_m64_pe(bus, all); 1075262af557SGuo Chao 1076262af557SGuo Chao /* The PE number isn't pinned by M64 */ 10771e916772SGavin Shan if (!pe) 10781e916772SGavin Shan pe = pnv_ioda_alloc_pe(phb); 1079262af557SGuo Chao 10801e916772SGavin Shan if (!pe) { 1081fb446ad0SGavin Shan pr_warning("%s: Not enough PE# available for PCI bus %04x:%02x\n", 1082fb446ad0SGavin Shan __func__, pci_domain_nr(bus), bus->number); 10831e916772SGavin Shan return NULL; 1084184cd4a3SBenjamin Herrenschmidt } 1085184cd4a3SBenjamin Herrenschmidt 1086262af557SGuo Chao pe->flags |= (all ? PNV_IODA_PE_BUS_ALL : PNV_IODA_PE_BUS); 1087184cd4a3SBenjamin Herrenschmidt pe->pbus = bus; 1088184cd4a3SBenjamin Herrenschmidt pe->pdev = NULL; 1089184cd4a3SBenjamin Herrenschmidt pe->mve_number = -1; 1090b918c62eSYinghai Lu pe->rid = bus->busn_res.start << 8; 1091184cd4a3SBenjamin Herrenschmidt 1092fb446ad0SGavin Shan if (all) 1093fb446ad0SGavin Shan pe_info(pe, "Secondary bus %d..%d associated with PE#%d\n", 10941e916772SGavin Shan bus->busn_res.start, bus->busn_res.end, pe->pe_number); 1095fb446ad0SGavin Shan else 1096fb446ad0SGavin Shan pe_info(pe, "Secondary bus %d associated with PE#%d\n", 10971e916772SGavin Shan bus->busn_res.start, pe->pe_number); 1098184cd4a3SBenjamin Herrenschmidt 1099184cd4a3SBenjamin Herrenschmidt if (pnv_ioda_configure_pe(phb, pe)) { 1100184cd4a3SBenjamin Herrenschmidt /* XXX What do we do here ? */ 11011e916772SGavin Shan pnv_ioda_free_pe(pe); 1102184cd4a3SBenjamin Herrenschmidt pe->pbus = NULL; 11031e916772SGavin Shan return NULL; 1104184cd4a3SBenjamin Herrenschmidt } 1105184cd4a3SBenjamin Herrenschmidt 1106184cd4a3SBenjamin Herrenschmidt /* Associate it with all child devices */ 1107184cd4a3SBenjamin Herrenschmidt pnv_ioda_setup_same_PE(bus, pe); 1108184cd4a3SBenjamin Herrenschmidt 11097ebdf956SGavin Shan /* Put PE to the list */ 11107ebdf956SGavin Shan list_add_tail(&pe->list, &phb->ioda.pe_list); 11111e916772SGavin Shan 11121e916772SGavin Shan return pe; 1113184cd4a3SBenjamin Herrenschmidt } 1114184cd4a3SBenjamin Herrenschmidt 1115b521549aSAlistair Popple static struct pnv_ioda_pe *pnv_ioda_setup_npu_PE(struct pci_dev *npu_pdev) 11165d2aa710SAlistair Popple { 1117b521549aSAlistair Popple int pe_num, found_pe = false, rc; 1118b521549aSAlistair Popple long rid; 1119b521549aSAlistair Popple struct pnv_ioda_pe *pe; 1120b521549aSAlistair Popple struct pci_dev *gpu_pdev; 1121b521549aSAlistair Popple struct pci_dn *npu_pdn; 1122b521549aSAlistair Popple struct pci_controller *hose = pci_bus_to_host(npu_pdev->bus); 1123b521549aSAlistair Popple struct pnv_phb *phb = hose->private_data; 1124b521549aSAlistair Popple 1125b521549aSAlistair Popple /* 1126b521549aSAlistair Popple * Due to a hardware errata PE#0 on the NPU is reserved for 1127b521549aSAlistair Popple * error handling. This means we only have three PEs remaining 1128b521549aSAlistair Popple * which need to be assigned to four links, implying some 1129b521549aSAlistair Popple * links must share PEs. 1130b521549aSAlistair Popple * 1131b521549aSAlistair Popple * To achieve this we assign PEs such that NPUs linking the 1132b521549aSAlistair Popple * same GPU get assigned the same PE. 1133b521549aSAlistair Popple */ 1134b521549aSAlistair Popple gpu_pdev = pnv_pci_get_gpu_dev(npu_pdev); 113592b8f137SGavin Shan for (pe_num = 0; pe_num < phb->ioda.total_pe_num; pe_num++) { 1136b521549aSAlistair Popple pe = &phb->ioda.pe_array[pe_num]; 1137b521549aSAlistair Popple if (!pe->pdev) 1138b521549aSAlistair Popple continue; 1139b521549aSAlistair Popple 1140b521549aSAlistair Popple if (pnv_pci_get_gpu_dev(pe->pdev) == gpu_pdev) { 1141b521549aSAlistair Popple /* 1142b521549aSAlistair Popple * This device has the same peer GPU so should 1143b521549aSAlistair Popple * be assigned the same PE as the existing 1144b521549aSAlistair Popple * peer NPU. 1145b521549aSAlistair Popple */ 1146b521549aSAlistair Popple dev_info(&npu_pdev->dev, 1147b521549aSAlistair Popple "Associating to existing PE %d\n", pe_num); 1148b521549aSAlistair Popple pci_dev_get(npu_pdev); 1149b521549aSAlistair Popple npu_pdn = pci_get_pdn(npu_pdev); 1150b521549aSAlistair Popple rid = npu_pdev->bus->number << 8 | npu_pdn->devfn; 1151b521549aSAlistair Popple npu_pdn->pcidev = npu_pdev; 1152b521549aSAlistair Popple npu_pdn->pe_number = pe_num; 1153b521549aSAlistair Popple phb->ioda.pe_rmap[rid] = pe->pe_number; 1154b521549aSAlistair Popple 1155b521549aSAlistair Popple /* Map the PE to this link */ 1156b521549aSAlistair Popple rc = opal_pci_set_pe(phb->opal_id, pe_num, rid, 1157b521549aSAlistair Popple OpalPciBusAll, 1158b521549aSAlistair Popple OPAL_COMPARE_RID_DEVICE_NUMBER, 1159b521549aSAlistair Popple OPAL_COMPARE_RID_FUNCTION_NUMBER, 1160b521549aSAlistair Popple OPAL_MAP_PE); 1161b521549aSAlistair Popple WARN_ON(rc != OPAL_SUCCESS); 1162b521549aSAlistair Popple found_pe = true; 1163b521549aSAlistair Popple break; 1164b521549aSAlistair Popple } 1165b521549aSAlistair Popple } 1166b521549aSAlistair Popple 1167b521549aSAlistair Popple if (!found_pe) 1168b521549aSAlistair Popple /* 1169b521549aSAlistair Popple * Could not find an existing PE so allocate a new 1170b521549aSAlistair Popple * one. 1171b521549aSAlistair Popple */ 1172b521549aSAlistair Popple return pnv_ioda_setup_dev_PE(npu_pdev); 1173b521549aSAlistair Popple else 1174b521549aSAlistair Popple return pe; 1175b521549aSAlistair Popple } 1176b521549aSAlistair Popple 1177b521549aSAlistair Popple static void pnv_ioda_setup_npu_PEs(struct pci_bus *bus) 1178b521549aSAlistair Popple { 11795d2aa710SAlistair Popple struct pci_dev *pdev; 11805d2aa710SAlistair Popple 11815d2aa710SAlistair Popple list_for_each_entry(pdev, &bus->devices, bus_list) 1182b521549aSAlistair Popple pnv_ioda_setup_npu_PE(pdev); 11835d2aa710SAlistair Popple } 11845d2aa710SAlistair Popple 1185cad5cef6SGreg Kroah-Hartman static void pnv_pci_ioda_setup_PEs(void) 1186fb446ad0SGavin Shan { 1187fb446ad0SGavin Shan struct pci_controller *hose, *tmp; 1188262af557SGuo Chao struct pnv_phb *phb; 1189fb446ad0SGavin Shan 1190fb446ad0SGavin Shan list_for_each_entry_safe(hose, tmp, &hose_list, list_node) { 1191262af557SGuo Chao phb = hose->private_data; 119208f48f32SAlistair Popple if (phb->type == PNV_PHB_NPU) { 119308f48f32SAlistair Popple /* PE#0 is needed for error reporting */ 119408f48f32SAlistair Popple pnv_ioda_reserve_pe(phb, 0); 1195b521549aSAlistair Popple pnv_ioda_setup_npu_PEs(hose->bus); 1196ccd1c191SGavin Shan } 1197fb446ad0SGavin Shan } 1198fb446ad0SGavin Shan } 1199184cd4a3SBenjamin Herrenschmidt 1200a8b2f828SGavin Shan #ifdef CONFIG_PCI_IOV 1201ee8222feSWei Yang static int pnv_pci_vf_release_m64(struct pci_dev *pdev, u16 num_vfs) 1202781a868fSWei Yang { 1203781a868fSWei Yang struct pci_bus *bus; 1204781a868fSWei Yang struct pci_controller *hose; 1205781a868fSWei Yang struct pnv_phb *phb; 1206781a868fSWei Yang struct pci_dn *pdn; 120702639b0eSWei Yang int i, j; 1208ee8222feSWei Yang int m64_bars; 1209781a868fSWei Yang 1210781a868fSWei Yang bus = pdev->bus; 1211781a868fSWei Yang hose = pci_bus_to_host(bus); 1212781a868fSWei Yang phb = hose->private_data; 1213781a868fSWei Yang pdn = pci_get_pdn(pdev); 1214781a868fSWei Yang 1215ee8222feSWei Yang if (pdn->m64_single_mode) 1216ee8222feSWei Yang m64_bars = num_vfs; 1217ee8222feSWei Yang else 1218ee8222feSWei Yang m64_bars = 1; 1219ee8222feSWei Yang 122002639b0eSWei Yang for (i = 0; i < PCI_SRIOV_NUM_BARS; i++) 1221ee8222feSWei Yang for (j = 0; j < m64_bars; j++) { 1222ee8222feSWei Yang if (pdn->m64_map[j][i] == IODA_INVALID_M64) 1223781a868fSWei Yang continue; 1224781a868fSWei Yang opal_pci_phb_mmio_enable(phb->opal_id, 1225ee8222feSWei Yang OPAL_M64_WINDOW_TYPE, pdn->m64_map[j][i], 0); 1226ee8222feSWei Yang clear_bit(pdn->m64_map[j][i], &phb->ioda.m64_bar_alloc); 1227ee8222feSWei Yang pdn->m64_map[j][i] = IODA_INVALID_M64; 1228781a868fSWei Yang } 1229781a868fSWei Yang 1230ee8222feSWei Yang kfree(pdn->m64_map); 1231781a868fSWei Yang return 0; 1232781a868fSWei Yang } 1233781a868fSWei Yang 123402639b0eSWei Yang static int pnv_pci_vf_assign_m64(struct pci_dev *pdev, u16 num_vfs) 1235781a868fSWei Yang { 1236781a868fSWei Yang struct pci_bus *bus; 1237781a868fSWei Yang struct pci_controller *hose; 1238781a868fSWei Yang struct pnv_phb *phb; 1239781a868fSWei Yang struct pci_dn *pdn; 1240781a868fSWei Yang unsigned int win; 1241781a868fSWei Yang struct resource *res; 124202639b0eSWei Yang int i, j; 1243781a868fSWei Yang int64_t rc; 124402639b0eSWei Yang int total_vfs; 124502639b0eSWei Yang resource_size_t size, start; 124602639b0eSWei Yang int pe_num; 1247ee8222feSWei Yang int m64_bars; 1248781a868fSWei Yang 1249781a868fSWei Yang bus = pdev->bus; 1250781a868fSWei Yang hose = pci_bus_to_host(bus); 1251781a868fSWei Yang phb = hose->private_data; 1252781a868fSWei Yang pdn = pci_get_pdn(pdev); 125302639b0eSWei Yang total_vfs = pci_sriov_get_totalvfs(pdev); 1254781a868fSWei Yang 1255ee8222feSWei Yang if (pdn->m64_single_mode) 1256ee8222feSWei Yang m64_bars = num_vfs; 1257ee8222feSWei Yang else 1258ee8222feSWei Yang m64_bars = 1; 125902639b0eSWei Yang 1260ee8222feSWei Yang pdn->m64_map = kmalloc(sizeof(*pdn->m64_map) * m64_bars, GFP_KERNEL); 1261ee8222feSWei Yang if (!pdn->m64_map) 1262ee8222feSWei Yang return -ENOMEM; 1263ee8222feSWei Yang /* Initialize the m64_map to IODA_INVALID_M64 */ 1264ee8222feSWei Yang for (i = 0; i < m64_bars ; i++) 1265ee8222feSWei Yang for (j = 0; j < PCI_SRIOV_NUM_BARS; j++) 1266ee8222feSWei Yang pdn->m64_map[i][j] = IODA_INVALID_M64; 1267ee8222feSWei Yang 1268781a868fSWei Yang 1269781a868fSWei Yang for (i = 0; i < PCI_SRIOV_NUM_BARS; i++) { 1270781a868fSWei Yang res = &pdev->resource[i + PCI_IOV_RESOURCES]; 1271781a868fSWei Yang if (!res->flags || !res->parent) 1272781a868fSWei Yang continue; 1273781a868fSWei Yang 1274ee8222feSWei Yang for (j = 0; j < m64_bars; j++) { 1275781a868fSWei Yang do { 1276781a868fSWei Yang win = find_next_zero_bit(&phb->ioda.m64_bar_alloc, 1277781a868fSWei Yang phb->ioda.m64_bar_idx + 1, 0); 1278781a868fSWei Yang 1279781a868fSWei Yang if (win >= phb->ioda.m64_bar_idx + 1) 1280781a868fSWei Yang goto m64_failed; 1281781a868fSWei Yang } while (test_and_set_bit(win, &phb->ioda.m64_bar_alloc)); 1282781a868fSWei Yang 1283ee8222feSWei Yang pdn->m64_map[j][i] = win; 128402639b0eSWei Yang 1285ee8222feSWei Yang if (pdn->m64_single_mode) { 128602639b0eSWei Yang size = pci_iov_resource_size(pdev, 128702639b0eSWei Yang PCI_IOV_RESOURCES + i); 128802639b0eSWei Yang start = res->start + size * j; 128902639b0eSWei Yang } else { 129002639b0eSWei Yang size = resource_size(res); 129102639b0eSWei Yang start = res->start; 129202639b0eSWei Yang } 1293781a868fSWei Yang 1294781a868fSWei Yang /* Map the M64 here */ 1295ee8222feSWei Yang if (pdn->m64_single_mode) { 1296be283eebSWei Yang pe_num = pdn->pe_num_map[j]; 129702639b0eSWei Yang rc = opal_pci_map_pe_mmio_window(phb->opal_id, 129802639b0eSWei Yang pe_num, OPAL_M64_WINDOW_TYPE, 1299ee8222feSWei Yang pdn->m64_map[j][i], 0); 130002639b0eSWei Yang } 130102639b0eSWei Yang 1302781a868fSWei Yang rc = opal_pci_set_phb_mem_window(phb->opal_id, 1303781a868fSWei Yang OPAL_M64_WINDOW_TYPE, 1304ee8222feSWei Yang pdn->m64_map[j][i], 130502639b0eSWei Yang start, 1306781a868fSWei Yang 0, /* unused */ 130702639b0eSWei Yang size); 130802639b0eSWei Yang 130902639b0eSWei Yang 1310781a868fSWei Yang if (rc != OPAL_SUCCESS) { 1311781a868fSWei Yang dev_err(&pdev->dev, "Failed to map M64 window #%d: %lld\n", 1312781a868fSWei Yang win, rc); 1313781a868fSWei Yang goto m64_failed; 1314781a868fSWei Yang } 1315781a868fSWei Yang 1316ee8222feSWei Yang if (pdn->m64_single_mode) 1317781a868fSWei Yang rc = opal_pci_phb_mmio_enable(phb->opal_id, 1318ee8222feSWei Yang OPAL_M64_WINDOW_TYPE, pdn->m64_map[j][i], 2); 131902639b0eSWei Yang else 132002639b0eSWei Yang rc = opal_pci_phb_mmio_enable(phb->opal_id, 1321ee8222feSWei Yang OPAL_M64_WINDOW_TYPE, pdn->m64_map[j][i], 1); 132202639b0eSWei Yang 1323781a868fSWei Yang if (rc != OPAL_SUCCESS) { 1324781a868fSWei Yang dev_err(&pdev->dev, "Failed to enable M64 window #%d: %llx\n", 1325781a868fSWei Yang win, rc); 1326781a868fSWei Yang goto m64_failed; 1327781a868fSWei Yang } 1328781a868fSWei Yang } 132902639b0eSWei Yang } 1330781a868fSWei Yang return 0; 1331781a868fSWei Yang 1332781a868fSWei Yang m64_failed: 1333ee8222feSWei Yang pnv_pci_vf_release_m64(pdev, num_vfs); 1334781a868fSWei Yang return -EBUSY; 1335781a868fSWei Yang } 1336781a868fSWei Yang 1337c035e37bSAlexey Kardashevskiy static long pnv_pci_ioda2_unset_window(struct iommu_table_group *table_group, 1338c035e37bSAlexey Kardashevskiy int num); 1339c035e37bSAlexey Kardashevskiy static void pnv_pci_ioda2_set_bypass(struct pnv_ioda_pe *pe, bool enable); 1340c035e37bSAlexey Kardashevskiy 1341781a868fSWei Yang static void pnv_pci_ioda2_release_dma_pe(struct pci_dev *dev, struct pnv_ioda_pe *pe) 1342781a868fSWei Yang { 1343781a868fSWei Yang struct iommu_table *tbl; 1344781a868fSWei Yang int64_t rc; 1345781a868fSWei Yang 1346b348aa65SAlexey Kardashevskiy tbl = pe->table_group.tables[0]; 1347c035e37bSAlexey Kardashevskiy rc = pnv_pci_ioda2_unset_window(&pe->table_group, 0); 1348781a868fSWei Yang if (rc) 1349781a868fSWei Yang pe_warn(pe, "OPAL error %ld release DMA window\n", rc); 1350781a868fSWei Yang 1351c035e37bSAlexey Kardashevskiy pnv_pci_ioda2_set_bypass(pe, false); 13520eaf4defSAlexey Kardashevskiy if (pe->table_group.group) { 13530eaf4defSAlexey Kardashevskiy iommu_group_put(pe->table_group.group); 13540eaf4defSAlexey Kardashevskiy BUG_ON(pe->table_group.group); 1355ac9a5889SAlexey Kardashevskiy } 1356aca6913fSAlexey Kardashevskiy pnv_pci_ioda2_table_free_pages(tbl); 1357781a868fSWei Yang iommu_free_table(tbl, of_node_full_name(dev->dev.of_node)); 1358781a868fSWei Yang } 1359781a868fSWei Yang 1360ee8222feSWei Yang static void pnv_ioda_release_vf_PE(struct pci_dev *pdev) 1361781a868fSWei Yang { 1362781a868fSWei Yang struct pci_bus *bus; 1363781a868fSWei Yang struct pci_controller *hose; 1364781a868fSWei Yang struct pnv_phb *phb; 1365781a868fSWei Yang struct pnv_ioda_pe *pe, *pe_n; 1366781a868fSWei Yang struct pci_dn *pdn; 1367781a868fSWei Yang 1368781a868fSWei Yang bus = pdev->bus; 1369781a868fSWei Yang hose = pci_bus_to_host(bus); 1370781a868fSWei Yang phb = hose->private_data; 137102639b0eSWei Yang pdn = pci_get_pdn(pdev); 1372781a868fSWei Yang 1373781a868fSWei Yang if (!pdev->is_physfn) 1374781a868fSWei Yang return; 1375781a868fSWei Yang 1376781a868fSWei Yang list_for_each_entry_safe(pe, pe_n, &phb->ioda.pe_list, list) { 1377781a868fSWei Yang if (pe->parent_dev != pdev) 1378781a868fSWei Yang continue; 1379781a868fSWei Yang 1380781a868fSWei Yang pnv_pci_ioda2_release_dma_pe(pdev, pe); 1381781a868fSWei Yang 1382781a868fSWei Yang /* Remove from list */ 1383781a868fSWei Yang mutex_lock(&phb->ioda.pe_list_mutex); 1384781a868fSWei Yang list_del(&pe->list); 1385781a868fSWei Yang mutex_unlock(&phb->ioda.pe_list_mutex); 1386781a868fSWei Yang 1387781a868fSWei Yang pnv_ioda_deconfigure_pe(phb, pe); 1388781a868fSWei Yang 13891e916772SGavin Shan pnv_ioda_free_pe(pe); 1390781a868fSWei Yang } 1391781a868fSWei Yang } 1392781a868fSWei Yang 1393781a868fSWei Yang void pnv_pci_sriov_disable(struct pci_dev *pdev) 1394781a868fSWei Yang { 1395781a868fSWei Yang struct pci_bus *bus; 1396781a868fSWei Yang struct pci_controller *hose; 1397781a868fSWei Yang struct pnv_phb *phb; 13981e916772SGavin Shan struct pnv_ioda_pe *pe; 1399781a868fSWei Yang struct pci_dn *pdn; 1400781a868fSWei Yang struct pci_sriov *iov; 1401be283eebSWei Yang u16 num_vfs, i; 1402781a868fSWei Yang 1403781a868fSWei Yang bus = pdev->bus; 1404781a868fSWei Yang hose = pci_bus_to_host(bus); 1405781a868fSWei Yang phb = hose->private_data; 1406781a868fSWei Yang pdn = pci_get_pdn(pdev); 1407781a868fSWei Yang iov = pdev->sriov; 1408781a868fSWei Yang num_vfs = pdn->num_vfs; 1409781a868fSWei Yang 1410781a868fSWei Yang /* Release VF PEs */ 1411ee8222feSWei Yang pnv_ioda_release_vf_PE(pdev); 1412781a868fSWei Yang 1413781a868fSWei Yang if (phb->type == PNV_PHB_IODA2) { 1414ee8222feSWei Yang if (!pdn->m64_single_mode) 1415be283eebSWei Yang pnv_pci_vf_resource_shift(pdev, -*pdn->pe_num_map); 1416781a868fSWei Yang 1417781a868fSWei Yang /* Release M64 windows */ 1418ee8222feSWei Yang pnv_pci_vf_release_m64(pdev, num_vfs); 1419781a868fSWei Yang 1420781a868fSWei Yang /* Release PE numbers */ 1421be283eebSWei Yang if (pdn->m64_single_mode) { 1422be283eebSWei Yang for (i = 0; i < num_vfs; i++) { 14231e916772SGavin Shan if (pdn->pe_num_map[i] == IODA_INVALID_PE) 14241e916772SGavin Shan continue; 14251e916772SGavin Shan 14261e916772SGavin Shan pe = &phb->ioda.pe_array[pdn->pe_num_map[i]]; 14271e916772SGavin Shan pnv_ioda_free_pe(pe); 1428be283eebSWei Yang } 1429be283eebSWei Yang } else 1430be283eebSWei Yang bitmap_clear(phb->ioda.pe_alloc, *pdn->pe_num_map, num_vfs); 1431be283eebSWei Yang /* Releasing pe_num_map */ 1432be283eebSWei Yang kfree(pdn->pe_num_map); 1433781a868fSWei Yang } 1434781a868fSWei Yang } 1435781a868fSWei Yang 1436781a868fSWei Yang static void pnv_pci_ioda2_setup_dma_pe(struct pnv_phb *phb, 1437781a868fSWei Yang struct pnv_ioda_pe *pe); 1438781a868fSWei Yang static void pnv_ioda_setup_vf_PE(struct pci_dev *pdev, u16 num_vfs) 1439781a868fSWei Yang { 1440781a868fSWei Yang struct pci_bus *bus; 1441781a868fSWei Yang struct pci_controller *hose; 1442781a868fSWei Yang struct pnv_phb *phb; 1443781a868fSWei Yang struct pnv_ioda_pe *pe; 1444781a868fSWei Yang int pe_num; 1445781a868fSWei Yang u16 vf_index; 1446781a868fSWei Yang struct pci_dn *pdn; 1447781a868fSWei Yang 1448781a868fSWei Yang bus = pdev->bus; 1449781a868fSWei Yang hose = pci_bus_to_host(bus); 1450781a868fSWei Yang phb = hose->private_data; 1451781a868fSWei Yang pdn = pci_get_pdn(pdev); 1452781a868fSWei Yang 1453781a868fSWei Yang if (!pdev->is_physfn) 1454781a868fSWei Yang return; 1455781a868fSWei Yang 1456781a868fSWei Yang /* Reserve PE for each VF */ 1457781a868fSWei Yang for (vf_index = 0; vf_index < num_vfs; vf_index++) { 1458be283eebSWei Yang if (pdn->m64_single_mode) 1459be283eebSWei Yang pe_num = pdn->pe_num_map[vf_index]; 1460be283eebSWei Yang else 1461be283eebSWei Yang pe_num = *pdn->pe_num_map + vf_index; 1462781a868fSWei Yang 1463781a868fSWei Yang pe = &phb->ioda.pe_array[pe_num]; 1464781a868fSWei Yang pe->pe_number = pe_num; 1465781a868fSWei Yang pe->phb = phb; 1466781a868fSWei Yang pe->flags = PNV_IODA_PE_VF; 1467781a868fSWei Yang pe->pbus = NULL; 1468781a868fSWei Yang pe->parent_dev = pdev; 1469781a868fSWei Yang pe->mve_number = -1; 1470781a868fSWei Yang pe->rid = (pci_iov_virtfn_bus(pdev, vf_index) << 8) | 1471781a868fSWei Yang pci_iov_virtfn_devfn(pdev, vf_index); 1472781a868fSWei Yang 1473781a868fSWei Yang pe_info(pe, "VF %04d:%02d:%02d.%d associated with PE#%d\n", 1474781a868fSWei Yang hose->global_number, pdev->bus->number, 1475781a868fSWei Yang PCI_SLOT(pci_iov_virtfn_devfn(pdev, vf_index)), 1476781a868fSWei Yang PCI_FUNC(pci_iov_virtfn_devfn(pdev, vf_index)), pe_num); 1477781a868fSWei Yang 1478781a868fSWei Yang if (pnv_ioda_configure_pe(phb, pe)) { 1479781a868fSWei Yang /* XXX What do we do here ? */ 14801e916772SGavin Shan pnv_ioda_free_pe(pe); 1481781a868fSWei Yang pe->pdev = NULL; 1482781a868fSWei Yang continue; 1483781a868fSWei Yang } 1484781a868fSWei Yang 1485781a868fSWei Yang /* Put PE to the list */ 1486781a868fSWei Yang mutex_lock(&phb->ioda.pe_list_mutex); 1487781a868fSWei Yang list_add_tail(&pe->list, &phb->ioda.pe_list); 1488781a868fSWei Yang mutex_unlock(&phb->ioda.pe_list_mutex); 1489781a868fSWei Yang 1490781a868fSWei Yang pnv_pci_ioda2_setup_dma_pe(phb, pe); 1491781a868fSWei Yang } 1492781a868fSWei Yang } 1493781a868fSWei Yang 1494781a868fSWei Yang int pnv_pci_sriov_enable(struct pci_dev *pdev, u16 num_vfs) 1495781a868fSWei Yang { 1496781a868fSWei Yang struct pci_bus *bus; 1497781a868fSWei Yang struct pci_controller *hose; 1498781a868fSWei Yang struct pnv_phb *phb; 14991e916772SGavin Shan struct pnv_ioda_pe *pe; 1500781a868fSWei Yang struct pci_dn *pdn; 1501781a868fSWei Yang int ret; 1502be283eebSWei Yang u16 i; 1503781a868fSWei Yang 1504781a868fSWei Yang bus = pdev->bus; 1505781a868fSWei Yang hose = pci_bus_to_host(bus); 1506781a868fSWei Yang phb = hose->private_data; 1507781a868fSWei Yang pdn = pci_get_pdn(pdev); 1508781a868fSWei Yang 1509781a868fSWei Yang if (phb->type == PNV_PHB_IODA2) { 1510b0331854SWei Yang if (!pdn->vfs_expanded) { 1511b0331854SWei Yang dev_info(&pdev->dev, "don't support this SRIOV device" 1512b0331854SWei Yang " with non 64bit-prefetchable IOV BAR\n"); 1513b0331854SWei Yang return -ENOSPC; 1514b0331854SWei Yang } 1515b0331854SWei Yang 1516ee8222feSWei Yang /* 1517ee8222feSWei Yang * When M64 BARs functions in Single PE mode, the number of VFs 1518ee8222feSWei Yang * could be enabled must be less than the number of M64 BARs. 1519ee8222feSWei Yang */ 1520ee8222feSWei Yang if (pdn->m64_single_mode && num_vfs > phb->ioda.m64_bar_idx) { 1521ee8222feSWei Yang dev_info(&pdev->dev, "Not enough M64 BAR for VFs\n"); 1522ee8222feSWei Yang return -EBUSY; 1523ee8222feSWei Yang } 1524ee8222feSWei Yang 1525be283eebSWei Yang /* Allocating pe_num_map */ 1526be283eebSWei Yang if (pdn->m64_single_mode) 1527be283eebSWei Yang pdn->pe_num_map = kmalloc(sizeof(*pdn->pe_num_map) * num_vfs, 1528be283eebSWei Yang GFP_KERNEL); 1529be283eebSWei Yang else 1530be283eebSWei Yang pdn->pe_num_map = kmalloc(sizeof(*pdn->pe_num_map), GFP_KERNEL); 1531be283eebSWei Yang 1532be283eebSWei Yang if (!pdn->pe_num_map) 1533be283eebSWei Yang return -ENOMEM; 1534be283eebSWei Yang 1535be283eebSWei Yang if (pdn->m64_single_mode) 1536be283eebSWei Yang for (i = 0; i < num_vfs; i++) 1537be283eebSWei Yang pdn->pe_num_map[i] = IODA_INVALID_PE; 1538be283eebSWei Yang 1539781a868fSWei Yang /* Calculate available PE for required VFs */ 1540be283eebSWei Yang if (pdn->m64_single_mode) { 1541be283eebSWei Yang for (i = 0; i < num_vfs; i++) { 15421e916772SGavin Shan pe = pnv_ioda_alloc_pe(phb); 15431e916772SGavin Shan if (!pe) { 1544be283eebSWei Yang ret = -EBUSY; 1545be283eebSWei Yang goto m64_failed; 1546be283eebSWei Yang } 15471e916772SGavin Shan 15481e916772SGavin Shan pdn->pe_num_map[i] = pe->pe_number; 1549be283eebSWei Yang } 1550be283eebSWei Yang } else { 1551781a868fSWei Yang mutex_lock(&phb->ioda.pe_alloc_mutex); 1552be283eebSWei Yang *pdn->pe_num_map = bitmap_find_next_zero_area( 155392b8f137SGavin Shan phb->ioda.pe_alloc, phb->ioda.total_pe_num, 1554781a868fSWei Yang 0, num_vfs, 0); 155592b8f137SGavin Shan if (*pdn->pe_num_map >= phb->ioda.total_pe_num) { 1556781a868fSWei Yang mutex_unlock(&phb->ioda.pe_alloc_mutex); 1557781a868fSWei Yang dev_info(&pdev->dev, "Failed to enable VF%d\n", num_vfs); 1558be283eebSWei Yang kfree(pdn->pe_num_map); 1559781a868fSWei Yang return -EBUSY; 1560781a868fSWei Yang } 1561be283eebSWei Yang bitmap_set(phb->ioda.pe_alloc, *pdn->pe_num_map, num_vfs); 1562781a868fSWei Yang mutex_unlock(&phb->ioda.pe_alloc_mutex); 1563be283eebSWei Yang } 1564be283eebSWei Yang pdn->num_vfs = num_vfs; 1565781a868fSWei Yang 1566781a868fSWei Yang /* Assign M64 window accordingly */ 156702639b0eSWei Yang ret = pnv_pci_vf_assign_m64(pdev, num_vfs); 1568781a868fSWei Yang if (ret) { 1569781a868fSWei Yang dev_info(&pdev->dev, "Not enough M64 window resources\n"); 1570781a868fSWei Yang goto m64_failed; 1571781a868fSWei Yang } 1572781a868fSWei Yang 1573781a868fSWei Yang /* 1574781a868fSWei Yang * When using one M64 BAR to map one IOV BAR, we need to shift 1575781a868fSWei Yang * the IOV BAR according to the PE# allocated to the VFs. 1576781a868fSWei Yang * Otherwise, the PE# for the VF will conflict with others. 1577781a868fSWei Yang */ 1578ee8222feSWei Yang if (!pdn->m64_single_mode) { 1579be283eebSWei Yang ret = pnv_pci_vf_resource_shift(pdev, *pdn->pe_num_map); 1580781a868fSWei Yang if (ret) 1581781a868fSWei Yang goto m64_failed; 1582781a868fSWei Yang } 158302639b0eSWei Yang } 1584781a868fSWei Yang 1585781a868fSWei Yang /* Setup VF PEs */ 1586781a868fSWei Yang pnv_ioda_setup_vf_PE(pdev, num_vfs); 1587781a868fSWei Yang 1588781a868fSWei Yang return 0; 1589781a868fSWei Yang 1590781a868fSWei Yang m64_failed: 1591be283eebSWei Yang if (pdn->m64_single_mode) { 1592be283eebSWei Yang for (i = 0; i < num_vfs; i++) { 15931e916772SGavin Shan if (pdn->pe_num_map[i] == IODA_INVALID_PE) 15941e916772SGavin Shan continue; 15951e916772SGavin Shan 15961e916772SGavin Shan pe = &phb->ioda.pe_array[pdn->pe_num_map[i]]; 15971e916772SGavin Shan pnv_ioda_free_pe(pe); 1598be283eebSWei Yang } 1599be283eebSWei Yang } else 1600be283eebSWei Yang bitmap_clear(phb->ioda.pe_alloc, *pdn->pe_num_map, num_vfs); 1601be283eebSWei Yang 1602be283eebSWei Yang /* Releasing pe_num_map */ 1603be283eebSWei Yang kfree(pdn->pe_num_map); 1604781a868fSWei Yang 1605781a868fSWei Yang return ret; 1606781a868fSWei Yang } 1607781a868fSWei Yang 1608a8b2f828SGavin Shan int pcibios_sriov_disable(struct pci_dev *pdev) 1609a8b2f828SGavin Shan { 1610781a868fSWei Yang pnv_pci_sriov_disable(pdev); 1611781a868fSWei Yang 1612a8b2f828SGavin Shan /* Release PCI data */ 1613a8b2f828SGavin Shan remove_dev_pci_data(pdev); 1614a8b2f828SGavin Shan return 0; 1615a8b2f828SGavin Shan } 1616a8b2f828SGavin Shan 1617a8b2f828SGavin Shan int pcibios_sriov_enable(struct pci_dev *pdev, u16 num_vfs) 1618a8b2f828SGavin Shan { 1619a8b2f828SGavin Shan /* Allocate PCI data */ 1620a8b2f828SGavin Shan add_dev_pci_data(pdev); 1621781a868fSWei Yang 1622ee8222feSWei Yang return pnv_pci_sriov_enable(pdev, num_vfs); 1623a8b2f828SGavin Shan } 1624a8b2f828SGavin Shan #endif /* CONFIG_PCI_IOV */ 1625a8b2f828SGavin Shan 1626959c9bddSGavin Shan static void pnv_pci_ioda_dma_dev_setup(struct pnv_phb *phb, struct pci_dev *pdev) 1627184cd4a3SBenjamin Herrenschmidt { 1628b72c1f65SBenjamin Herrenschmidt struct pci_dn *pdn = pci_get_pdn(pdev); 1629959c9bddSGavin Shan struct pnv_ioda_pe *pe; 1630184cd4a3SBenjamin Herrenschmidt 1631959c9bddSGavin Shan /* 1632959c9bddSGavin Shan * The function can be called while the PE# 1633959c9bddSGavin Shan * hasn't been assigned. Do nothing for the 1634959c9bddSGavin Shan * case. 1635959c9bddSGavin Shan */ 1636959c9bddSGavin Shan if (!pdn || pdn->pe_number == IODA_INVALID_PE) 1637959c9bddSGavin Shan return; 1638184cd4a3SBenjamin Herrenschmidt 1639959c9bddSGavin Shan pe = &phb->ioda.pe_array[pdn->pe_number]; 1640cd15b048SBenjamin Herrenschmidt WARN_ON(get_dma_ops(&pdev->dev) != &dma_iommu_ops); 16410e1ffef0SAlexey Kardashevskiy set_dma_offset(&pdev->dev, pe->tce_bypass_base); 1642b348aa65SAlexey Kardashevskiy set_iommu_table_base(&pdev->dev, pe->table_group.tables[0]); 16434617082eSAlexey Kardashevskiy /* 16444617082eSAlexey Kardashevskiy * Note: iommu_add_device() will fail here as 16454617082eSAlexey Kardashevskiy * for physical PE: the device is already added by now; 16464617082eSAlexey Kardashevskiy * for virtual PE: sysfs entries are not ready yet and 16474617082eSAlexey Kardashevskiy * tce_iommu_bus_notifier will add the device to a group later. 16484617082eSAlexey Kardashevskiy */ 1649184cd4a3SBenjamin Herrenschmidt } 1650184cd4a3SBenjamin Herrenschmidt 1651763d2d8dSDaniel Axtens static int pnv_pci_ioda_dma_set_mask(struct pci_dev *pdev, u64 dma_mask) 1652cd15b048SBenjamin Herrenschmidt { 1653763d2d8dSDaniel Axtens struct pci_controller *hose = pci_bus_to_host(pdev->bus); 1654763d2d8dSDaniel Axtens struct pnv_phb *phb = hose->private_data; 1655cd15b048SBenjamin Herrenschmidt struct pci_dn *pdn = pci_get_pdn(pdev); 1656cd15b048SBenjamin Herrenschmidt struct pnv_ioda_pe *pe; 1657cd15b048SBenjamin Herrenschmidt uint64_t top; 1658cd15b048SBenjamin Herrenschmidt bool bypass = false; 1659cd15b048SBenjamin Herrenschmidt 1660cd15b048SBenjamin Herrenschmidt if (WARN_ON(!pdn || pdn->pe_number == IODA_INVALID_PE)) 1661cd15b048SBenjamin Herrenschmidt return -ENODEV;; 1662cd15b048SBenjamin Herrenschmidt 1663cd15b048SBenjamin Herrenschmidt pe = &phb->ioda.pe_array[pdn->pe_number]; 1664cd15b048SBenjamin Herrenschmidt if (pe->tce_bypass_enabled) { 1665cd15b048SBenjamin Herrenschmidt top = pe->tce_bypass_base + memblock_end_of_DRAM() - 1; 1666cd15b048SBenjamin Herrenschmidt bypass = (dma_mask >= top); 1667cd15b048SBenjamin Herrenschmidt } 1668cd15b048SBenjamin Herrenschmidt 1669cd15b048SBenjamin Herrenschmidt if (bypass) { 1670cd15b048SBenjamin Herrenschmidt dev_info(&pdev->dev, "Using 64-bit DMA iommu bypass\n"); 1671cd15b048SBenjamin Herrenschmidt set_dma_ops(&pdev->dev, &dma_direct_ops); 1672cd15b048SBenjamin Herrenschmidt } else { 1673cd15b048SBenjamin Herrenschmidt dev_info(&pdev->dev, "Using 32-bit DMA via iommu\n"); 1674cd15b048SBenjamin Herrenschmidt set_dma_ops(&pdev->dev, &dma_iommu_ops); 1675cd15b048SBenjamin Herrenschmidt } 1676a32305bfSBrian W Hart *pdev->dev.dma_mask = dma_mask; 16775d2aa710SAlistair Popple 16785d2aa710SAlistair Popple /* Update peer npu devices */ 1679f9f83456SAlexey Kardashevskiy pnv_npu_try_dma_set_bypass(pdev, bypass); 16805d2aa710SAlistair Popple 1681cd15b048SBenjamin Herrenschmidt return 0; 1682cd15b048SBenjamin Herrenschmidt } 1683cd15b048SBenjamin Herrenschmidt 168453522982SAndrew Donnellan static u64 pnv_pci_ioda_dma_get_required_mask(struct pci_dev *pdev) 1685fe7e85c6SGavin Shan { 168653522982SAndrew Donnellan struct pci_controller *hose = pci_bus_to_host(pdev->bus); 168753522982SAndrew Donnellan struct pnv_phb *phb = hose->private_data; 1688fe7e85c6SGavin Shan struct pci_dn *pdn = pci_get_pdn(pdev); 1689fe7e85c6SGavin Shan struct pnv_ioda_pe *pe; 1690fe7e85c6SGavin Shan u64 end, mask; 1691fe7e85c6SGavin Shan 1692fe7e85c6SGavin Shan if (WARN_ON(!pdn || pdn->pe_number == IODA_INVALID_PE)) 1693fe7e85c6SGavin Shan return 0; 1694fe7e85c6SGavin Shan 1695fe7e85c6SGavin Shan pe = &phb->ioda.pe_array[pdn->pe_number]; 1696fe7e85c6SGavin Shan if (!pe->tce_bypass_enabled) 1697fe7e85c6SGavin Shan return __dma_get_required_mask(&pdev->dev); 1698fe7e85c6SGavin Shan 1699fe7e85c6SGavin Shan 1700fe7e85c6SGavin Shan end = pe->tce_bypass_base + memblock_end_of_DRAM(); 1701fe7e85c6SGavin Shan mask = 1ULL << (fls64(end) - 1); 1702fe7e85c6SGavin Shan mask += mask - 1; 1703fe7e85c6SGavin Shan 1704fe7e85c6SGavin Shan return mask; 1705fe7e85c6SGavin Shan } 1706fe7e85c6SGavin Shan 1707dff4a39eSGavin Shan static void pnv_ioda_setup_bus_dma(struct pnv_ioda_pe *pe, 1708ea30e99eSAlexey Kardashevskiy struct pci_bus *bus) 170974251fe2SBenjamin Herrenschmidt { 171074251fe2SBenjamin Herrenschmidt struct pci_dev *dev; 171174251fe2SBenjamin Herrenschmidt 171274251fe2SBenjamin Herrenschmidt list_for_each_entry(dev, &bus->devices, bus_list) { 1713b348aa65SAlexey Kardashevskiy set_iommu_table_base(&dev->dev, pe->table_group.tables[0]); 1714e91c2511SBenjamin Herrenschmidt set_dma_offset(&dev->dev, pe->tce_bypass_base); 17154617082eSAlexey Kardashevskiy iommu_add_device(&dev->dev); 1716dff4a39eSGavin Shan 17175c89a87dSAlexey Kardashevskiy if ((pe->flags & PNV_IODA_PE_BUS_ALL) && dev->subordinate) 1718ea30e99eSAlexey Kardashevskiy pnv_ioda_setup_bus_dma(pe, dev->subordinate); 171974251fe2SBenjamin Herrenschmidt } 172074251fe2SBenjamin Herrenschmidt } 172174251fe2SBenjamin Herrenschmidt 1722decbda25SAlexey Kardashevskiy static void pnv_pci_ioda1_tce_invalidate(struct iommu_table *tbl, 1723decbda25SAlexey Kardashevskiy unsigned long index, unsigned long npages, bool rm) 17244cce9550SGavin Shan { 17250eaf4defSAlexey Kardashevskiy struct iommu_table_group_link *tgl = list_first_entry_or_null( 17260eaf4defSAlexey Kardashevskiy &tbl->it_group_list, struct iommu_table_group_link, 17270eaf4defSAlexey Kardashevskiy next); 17280eaf4defSAlexey Kardashevskiy struct pnv_ioda_pe *pe = container_of(tgl->table_group, 1729b348aa65SAlexey Kardashevskiy struct pnv_ioda_pe, table_group); 17303ad26e5cSBenjamin Herrenschmidt __be64 __iomem *invalidate = rm ? 17315780fb04SAlexey Kardashevskiy (__be64 __iomem *)pe->phb->ioda.tce_inval_reg_phys : 17325780fb04SAlexey Kardashevskiy pe->phb->ioda.tce_inval_reg; 17334cce9550SGavin Shan unsigned long start, end, inc; 1734b0376c9bSAlexey Kardashevskiy const unsigned shift = tbl->it_page_shift; 17354cce9550SGavin Shan 1736decbda25SAlexey Kardashevskiy start = __pa(((__be64 *)tbl->it_base) + index - tbl->it_offset); 1737decbda25SAlexey Kardashevskiy end = __pa(((__be64 *)tbl->it_base) + index - tbl->it_offset + 1738decbda25SAlexey Kardashevskiy npages - 1); 17394cce9550SGavin Shan 17404cce9550SGavin Shan /* BML uses this case for p6/p7/galaxy2: Shift addr and put in node */ 17414cce9550SGavin Shan if (tbl->it_busno) { 1742b0376c9bSAlexey Kardashevskiy start <<= shift; 1743b0376c9bSAlexey Kardashevskiy end <<= shift; 1744b0376c9bSAlexey Kardashevskiy inc = 128ull << shift; 17454cce9550SGavin Shan start |= tbl->it_busno; 17464cce9550SGavin Shan end |= tbl->it_busno; 17474cce9550SGavin Shan } else if (tbl->it_type & TCE_PCI_SWINV_PAIR) { 17484cce9550SGavin Shan /* p7ioc-style invalidation, 2 TCEs per write */ 17494cce9550SGavin Shan start |= (1ull << 63); 17504cce9550SGavin Shan end |= (1ull << 63); 17514cce9550SGavin Shan inc = 16; 17524cce9550SGavin Shan } else { 17534cce9550SGavin Shan /* Default (older HW) */ 17544cce9550SGavin Shan inc = 128; 17554cce9550SGavin Shan } 17564cce9550SGavin Shan 17574cce9550SGavin Shan end |= inc - 1; /* round up end to be different than start */ 17584cce9550SGavin Shan 17594cce9550SGavin Shan mb(); /* Ensure above stores are visible */ 17604cce9550SGavin Shan while (start <= end) { 17618e0a1611SAlexey Kardashevskiy if (rm) 17623ad26e5cSBenjamin Herrenschmidt __raw_rm_writeq(cpu_to_be64(start), invalidate); 17638e0a1611SAlexey Kardashevskiy else 17643a1a4661SBenjamin Herrenschmidt __raw_writeq(cpu_to_be64(start), invalidate); 17654cce9550SGavin Shan start += inc; 17664cce9550SGavin Shan } 17674cce9550SGavin Shan 17684cce9550SGavin Shan /* 17694cce9550SGavin Shan * The iommu layer will do another mb() for us on build() 17704cce9550SGavin Shan * and we don't care on free() 17714cce9550SGavin Shan */ 17724cce9550SGavin Shan } 17734cce9550SGavin Shan 1774decbda25SAlexey Kardashevskiy static int pnv_ioda1_tce_build(struct iommu_table *tbl, long index, 1775decbda25SAlexey Kardashevskiy long npages, unsigned long uaddr, 1776decbda25SAlexey Kardashevskiy enum dma_data_direction direction, 1777decbda25SAlexey Kardashevskiy struct dma_attrs *attrs) 1778decbda25SAlexey Kardashevskiy { 1779decbda25SAlexey Kardashevskiy int ret = pnv_tce_build(tbl, index, npages, uaddr, direction, 1780decbda25SAlexey Kardashevskiy attrs); 1781decbda25SAlexey Kardashevskiy 1782decbda25SAlexey Kardashevskiy if (!ret && (tbl->it_type & TCE_PCI_SWINV_CREATE)) 1783decbda25SAlexey Kardashevskiy pnv_pci_ioda1_tce_invalidate(tbl, index, npages, false); 1784decbda25SAlexey Kardashevskiy 1785decbda25SAlexey Kardashevskiy return ret; 1786decbda25SAlexey Kardashevskiy } 1787decbda25SAlexey Kardashevskiy 178805c6cfb9SAlexey Kardashevskiy #ifdef CONFIG_IOMMU_API 178905c6cfb9SAlexey Kardashevskiy static int pnv_ioda1_tce_xchg(struct iommu_table *tbl, long index, 179005c6cfb9SAlexey Kardashevskiy unsigned long *hpa, enum dma_data_direction *direction) 179105c6cfb9SAlexey Kardashevskiy { 179205c6cfb9SAlexey Kardashevskiy long ret = pnv_tce_xchg(tbl, index, hpa, direction); 179305c6cfb9SAlexey Kardashevskiy 179405c6cfb9SAlexey Kardashevskiy if (!ret && (tbl->it_type & 179505c6cfb9SAlexey Kardashevskiy (TCE_PCI_SWINV_CREATE | TCE_PCI_SWINV_FREE))) 179605c6cfb9SAlexey Kardashevskiy pnv_pci_ioda1_tce_invalidate(tbl, index, 1, false); 179705c6cfb9SAlexey Kardashevskiy 179805c6cfb9SAlexey Kardashevskiy return ret; 179905c6cfb9SAlexey Kardashevskiy } 180005c6cfb9SAlexey Kardashevskiy #endif 180105c6cfb9SAlexey Kardashevskiy 1802decbda25SAlexey Kardashevskiy static void pnv_ioda1_tce_free(struct iommu_table *tbl, long index, 1803decbda25SAlexey Kardashevskiy long npages) 1804decbda25SAlexey Kardashevskiy { 1805decbda25SAlexey Kardashevskiy pnv_tce_free(tbl, index, npages); 1806decbda25SAlexey Kardashevskiy 1807decbda25SAlexey Kardashevskiy if (tbl->it_type & TCE_PCI_SWINV_FREE) 1808decbda25SAlexey Kardashevskiy pnv_pci_ioda1_tce_invalidate(tbl, index, npages, false); 1809decbda25SAlexey Kardashevskiy } 1810decbda25SAlexey Kardashevskiy 1811da004c36SAlexey Kardashevskiy static struct iommu_table_ops pnv_ioda1_iommu_ops = { 1812decbda25SAlexey Kardashevskiy .set = pnv_ioda1_tce_build, 181305c6cfb9SAlexey Kardashevskiy #ifdef CONFIG_IOMMU_API 181405c6cfb9SAlexey Kardashevskiy .exchange = pnv_ioda1_tce_xchg, 181505c6cfb9SAlexey Kardashevskiy #endif 1816decbda25SAlexey Kardashevskiy .clear = pnv_ioda1_tce_free, 1817da004c36SAlexey Kardashevskiy .get = pnv_tce_get, 1818da004c36SAlexey Kardashevskiy }; 1819da004c36SAlexey Kardashevskiy 18200bbcdb43SAlexey Kardashevskiy #define TCE_KILL_INVAL_ALL PPC_BIT(0) 1821bef9253fSAlexey Kardashevskiy #define TCE_KILL_INVAL_PE PPC_BIT(1) 1822bef9253fSAlexey Kardashevskiy #define TCE_KILL_INVAL_TCE PPC_BIT(2) 1823bef9253fSAlexey Kardashevskiy 18240bbcdb43SAlexey Kardashevskiy void pnv_pci_ioda2_tce_invalidate_entire(struct pnv_phb *phb, bool rm) 18250bbcdb43SAlexey Kardashevskiy { 18260bbcdb43SAlexey Kardashevskiy const unsigned long val = TCE_KILL_INVAL_ALL; 18270bbcdb43SAlexey Kardashevskiy 18280bbcdb43SAlexey Kardashevskiy mb(); /* Ensure previous TCE table stores are visible */ 18290bbcdb43SAlexey Kardashevskiy if (rm) 18300bbcdb43SAlexey Kardashevskiy __raw_rm_writeq(cpu_to_be64(val), 18310bbcdb43SAlexey Kardashevskiy (__be64 __iomem *) 18320bbcdb43SAlexey Kardashevskiy phb->ioda.tce_inval_reg_phys); 18330bbcdb43SAlexey Kardashevskiy else 18340bbcdb43SAlexey Kardashevskiy __raw_writeq(cpu_to_be64(val), phb->ioda.tce_inval_reg); 18350bbcdb43SAlexey Kardashevskiy } 18360bbcdb43SAlexey Kardashevskiy 1837a7cf13caSAlexey Kardashevskiy static inline void pnv_pci_ioda2_tce_invalidate_pe(struct pnv_ioda_pe *pe) 18385780fb04SAlexey Kardashevskiy { 18395780fb04SAlexey Kardashevskiy /* 01xb - invalidate TCEs that match the specified PE# */ 1840bef9253fSAlexey Kardashevskiy unsigned long val = TCE_KILL_INVAL_PE | (pe->pe_number & 0xFF); 18415780fb04SAlexey Kardashevskiy struct pnv_phb *phb = pe->phb; 18425780fb04SAlexey Kardashevskiy 18435780fb04SAlexey Kardashevskiy if (!phb->ioda.tce_inval_reg) 18445780fb04SAlexey Kardashevskiy return; 18455780fb04SAlexey Kardashevskiy 18465780fb04SAlexey Kardashevskiy mb(); /* Ensure above stores are visible */ 18475780fb04SAlexey Kardashevskiy __raw_writeq(cpu_to_be64(val), phb->ioda.tce_inval_reg); 18485780fb04SAlexey Kardashevskiy } 18495780fb04SAlexey Kardashevskiy 1850e57080f1SAlexey Kardashevskiy static void pnv_pci_ioda2_do_tce_invalidate(unsigned pe_number, bool rm, 1851e57080f1SAlexey Kardashevskiy __be64 __iomem *invalidate, unsigned shift, 1852e57080f1SAlexey Kardashevskiy unsigned long index, unsigned long npages) 18534cce9550SGavin Shan { 18544cce9550SGavin Shan unsigned long start, end, inc; 18554cce9550SGavin Shan 18564cce9550SGavin Shan /* We'll invalidate DMA address in PE scope */ 1857bef9253fSAlexey Kardashevskiy start = TCE_KILL_INVAL_TCE; 1858e57080f1SAlexey Kardashevskiy start |= (pe_number & 0xFF); 18594cce9550SGavin Shan end = start; 18604cce9550SGavin Shan 18614cce9550SGavin Shan /* Figure out the start, end and step */ 1862decbda25SAlexey Kardashevskiy start |= (index << shift); 1863decbda25SAlexey Kardashevskiy end |= ((index + npages - 1) << shift); 1864b0376c9bSAlexey Kardashevskiy inc = (0x1ull << shift); 18654cce9550SGavin Shan mb(); 18664cce9550SGavin Shan 18674cce9550SGavin Shan while (start <= end) { 18688e0a1611SAlexey Kardashevskiy if (rm) 18693ad26e5cSBenjamin Herrenschmidt __raw_rm_writeq(cpu_to_be64(start), invalidate); 18708e0a1611SAlexey Kardashevskiy else 18713a1a4661SBenjamin Herrenschmidt __raw_writeq(cpu_to_be64(start), invalidate); 18724cce9550SGavin Shan start += inc; 18734cce9550SGavin Shan } 18744cce9550SGavin Shan } 18754cce9550SGavin Shan 1876e57080f1SAlexey Kardashevskiy static void pnv_pci_ioda2_tce_invalidate(struct iommu_table *tbl, 1877e57080f1SAlexey Kardashevskiy unsigned long index, unsigned long npages, bool rm) 1878e57080f1SAlexey Kardashevskiy { 1879e57080f1SAlexey Kardashevskiy struct iommu_table_group_link *tgl; 1880e57080f1SAlexey Kardashevskiy 1881e57080f1SAlexey Kardashevskiy list_for_each_entry_rcu(tgl, &tbl->it_group_list, next) { 1882e57080f1SAlexey Kardashevskiy struct pnv_ioda_pe *pe = container_of(tgl->table_group, 1883e57080f1SAlexey Kardashevskiy struct pnv_ioda_pe, table_group); 1884e57080f1SAlexey Kardashevskiy __be64 __iomem *invalidate = rm ? 1885e57080f1SAlexey Kardashevskiy (__be64 __iomem *)pe->phb->ioda.tce_inval_reg_phys : 1886e57080f1SAlexey Kardashevskiy pe->phb->ioda.tce_inval_reg; 1887e57080f1SAlexey Kardashevskiy 188885674868SAlexey Kardashevskiy if (pe->phb->type == PNV_PHB_NPU) { 18890bbcdb43SAlexey Kardashevskiy /* 18900bbcdb43SAlexey Kardashevskiy * The NVLink hardware does not support TCE kill 18910bbcdb43SAlexey Kardashevskiy * per TCE entry so we have to invalidate 18920bbcdb43SAlexey Kardashevskiy * the entire cache for it. 18930bbcdb43SAlexey Kardashevskiy */ 189485674868SAlexey Kardashevskiy pnv_pci_ioda2_tce_invalidate_entire(pe->phb, rm); 18955d2aa710SAlistair Popple continue; 18965d2aa710SAlistair Popple } 189785674868SAlexey Kardashevskiy pnv_pci_ioda2_do_tce_invalidate(pe->pe_number, rm, 189885674868SAlexey Kardashevskiy invalidate, tbl->it_page_shift, 189985674868SAlexey Kardashevskiy index, npages); 1900e57080f1SAlexey Kardashevskiy } 1901e57080f1SAlexey Kardashevskiy } 1902e57080f1SAlexey Kardashevskiy 1903decbda25SAlexey Kardashevskiy static int pnv_ioda2_tce_build(struct iommu_table *tbl, long index, 1904decbda25SAlexey Kardashevskiy long npages, unsigned long uaddr, 1905decbda25SAlexey Kardashevskiy enum dma_data_direction direction, 1906decbda25SAlexey Kardashevskiy struct dma_attrs *attrs) 19074cce9550SGavin Shan { 1908decbda25SAlexey Kardashevskiy int ret = pnv_tce_build(tbl, index, npages, uaddr, direction, 1909decbda25SAlexey Kardashevskiy attrs); 19104cce9550SGavin Shan 1911decbda25SAlexey Kardashevskiy if (!ret && (tbl->it_type & TCE_PCI_SWINV_CREATE)) 1912decbda25SAlexey Kardashevskiy pnv_pci_ioda2_tce_invalidate(tbl, index, npages, false); 1913decbda25SAlexey Kardashevskiy 1914decbda25SAlexey Kardashevskiy return ret; 1915decbda25SAlexey Kardashevskiy } 1916decbda25SAlexey Kardashevskiy 191705c6cfb9SAlexey Kardashevskiy #ifdef CONFIG_IOMMU_API 191805c6cfb9SAlexey Kardashevskiy static int pnv_ioda2_tce_xchg(struct iommu_table *tbl, long index, 191905c6cfb9SAlexey Kardashevskiy unsigned long *hpa, enum dma_data_direction *direction) 192005c6cfb9SAlexey Kardashevskiy { 192105c6cfb9SAlexey Kardashevskiy long ret = pnv_tce_xchg(tbl, index, hpa, direction); 192205c6cfb9SAlexey Kardashevskiy 192305c6cfb9SAlexey Kardashevskiy if (!ret && (tbl->it_type & 192405c6cfb9SAlexey Kardashevskiy (TCE_PCI_SWINV_CREATE | TCE_PCI_SWINV_FREE))) 192505c6cfb9SAlexey Kardashevskiy pnv_pci_ioda2_tce_invalidate(tbl, index, 1, false); 192605c6cfb9SAlexey Kardashevskiy 192705c6cfb9SAlexey Kardashevskiy return ret; 192805c6cfb9SAlexey Kardashevskiy } 192905c6cfb9SAlexey Kardashevskiy #endif 193005c6cfb9SAlexey Kardashevskiy 1931decbda25SAlexey Kardashevskiy static void pnv_ioda2_tce_free(struct iommu_table *tbl, long index, 1932decbda25SAlexey Kardashevskiy long npages) 1933decbda25SAlexey Kardashevskiy { 1934decbda25SAlexey Kardashevskiy pnv_tce_free(tbl, index, npages); 1935decbda25SAlexey Kardashevskiy 1936decbda25SAlexey Kardashevskiy if (tbl->it_type & TCE_PCI_SWINV_FREE) 1937decbda25SAlexey Kardashevskiy pnv_pci_ioda2_tce_invalidate(tbl, index, npages, false); 19384cce9550SGavin Shan } 19394cce9550SGavin Shan 19404793d65dSAlexey Kardashevskiy static void pnv_ioda2_table_free(struct iommu_table *tbl) 19414793d65dSAlexey Kardashevskiy { 19424793d65dSAlexey Kardashevskiy pnv_pci_ioda2_table_free_pages(tbl); 19434793d65dSAlexey Kardashevskiy iommu_free_table(tbl, "pnv"); 19444793d65dSAlexey Kardashevskiy } 19454793d65dSAlexey Kardashevskiy 1946da004c36SAlexey Kardashevskiy static struct iommu_table_ops pnv_ioda2_iommu_ops = { 1947decbda25SAlexey Kardashevskiy .set = pnv_ioda2_tce_build, 194805c6cfb9SAlexey Kardashevskiy #ifdef CONFIG_IOMMU_API 194905c6cfb9SAlexey Kardashevskiy .exchange = pnv_ioda2_tce_xchg, 195005c6cfb9SAlexey Kardashevskiy #endif 1951decbda25SAlexey Kardashevskiy .clear = pnv_ioda2_tce_free, 1952da004c36SAlexey Kardashevskiy .get = pnv_tce_get, 19534793d65dSAlexey Kardashevskiy .free = pnv_ioda2_table_free, 1954da004c36SAlexey Kardashevskiy }; 1955da004c36SAlexey Kardashevskiy 1956801846d1SGavin Shan static int pnv_pci_ioda_dev_dma_weight(struct pci_dev *dev, void *data) 1957801846d1SGavin Shan { 1958801846d1SGavin Shan unsigned int *weight = (unsigned int *)data; 1959801846d1SGavin Shan 1960801846d1SGavin Shan /* This is quite simplistic. The "base" weight of a device 1961801846d1SGavin Shan * is 10. 0 means no DMA is to be accounted for it. 1962801846d1SGavin Shan */ 1963801846d1SGavin Shan if (dev->hdr_type != PCI_HEADER_TYPE_NORMAL) 1964801846d1SGavin Shan return 0; 1965801846d1SGavin Shan 1966801846d1SGavin Shan if (dev->class == PCI_CLASS_SERIAL_USB_UHCI || 1967801846d1SGavin Shan dev->class == PCI_CLASS_SERIAL_USB_OHCI || 1968801846d1SGavin Shan dev->class == PCI_CLASS_SERIAL_USB_EHCI) 1969801846d1SGavin Shan *weight += 3; 1970801846d1SGavin Shan else if ((dev->class >> 8) == PCI_CLASS_STORAGE_RAID) 1971801846d1SGavin Shan *weight += 15; 1972801846d1SGavin Shan else 1973801846d1SGavin Shan *weight += 10; 1974801846d1SGavin Shan 1975801846d1SGavin Shan return 0; 1976801846d1SGavin Shan } 1977801846d1SGavin Shan 1978801846d1SGavin Shan static unsigned int pnv_pci_ioda_pe_dma_weight(struct pnv_ioda_pe *pe) 1979801846d1SGavin Shan { 1980801846d1SGavin Shan unsigned int weight = 0; 1981801846d1SGavin Shan 1982801846d1SGavin Shan /* SRIOV VF has same DMA32 weight as its PF */ 1983801846d1SGavin Shan #ifdef CONFIG_PCI_IOV 1984801846d1SGavin Shan if ((pe->flags & PNV_IODA_PE_VF) && pe->parent_dev) { 1985801846d1SGavin Shan pnv_pci_ioda_dev_dma_weight(pe->parent_dev, &weight); 1986801846d1SGavin Shan return weight; 1987801846d1SGavin Shan } 1988801846d1SGavin Shan #endif 1989801846d1SGavin Shan 1990801846d1SGavin Shan if ((pe->flags & PNV_IODA_PE_DEV) && pe->pdev) { 1991801846d1SGavin Shan pnv_pci_ioda_dev_dma_weight(pe->pdev, &weight); 1992801846d1SGavin Shan } else if ((pe->flags & PNV_IODA_PE_BUS) && pe->pbus) { 1993801846d1SGavin Shan struct pci_dev *pdev; 1994801846d1SGavin Shan 1995801846d1SGavin Shan list_for_each_entry(pdev, &pe->pbus->devices, bus_list) 1996801846d1SGavin Shan pnv_pci_ioda_dev_dma_weight(pdev, &weight); 1997801846d1SGavin Shan } else if ((pe->flags & PNV_IODA_PE_BUS_ALL) && pe->pbus) { 1998801846d1SGavin Shan pci_walk_bus(pe->pbus, pnv_pci_ioda_dev_dma_weight, &weight); 1999801846d1SGavin Shan } 2000801846d1SGavin Shan 2001801846d1SGavin Shan return weight; 2002801846d1SGavin Shan } 2003801846d1SGavin Shan 2004b30d936fSGavin Shan static void pnv_pci_ioda1_setup_dma_pe(struct pnv_phb *phb, 20052b923ed1SGavin Shan struct pnv_ioda_pe *pe) 2006184cd4a3SBenjamin Herrenschmidt { 2007184cd4a3SBenjamin Herrenschmidt 2008184cd4a3SBenjamin Herrenschmidt struct page *tce_mem = NULL; 2009184cd4a3SBenjamin Herrenschmidt struct iommu_table *tbl; 20102b923ed1SGavin Shan unsigned int weight, total_weight = 0; 20112b923ed1SGavin Shan unsigned int tce32_segsz, base, segs, avail, i; 2012184cd4a3SBenjamin Herrenschmidt int64_t rc; 2013184cd4a3SBenjamin Herrenschmidt void *addr; 2014184cd4a3SBenjamin Herrenschmidt 2015184cd4a3SBenjamin Herrenschmidt /* XXX FIXME: Handle 64-bit only DMA devices */ 2016184cd4a3SBenjamin Herrenschmidt /* XXX FIXME: Provide 64-bit DMA facilities & non-4K TCE tables etc.. */ 2017184cd4a3SBenjamin Herrenschmidt /* XXX FIXME: Allocate multi-level tables on PHB3 */ 20182b923ed1SGavin Shan weight = pnv_pci_ioda_pe_dma_weight(pe); 20192b923ed1SGavin Shan if (!weight) 20202b923ed1SGavin Shan return; 2021184cd4a3SBenjamin Herrenschmidt 20222b923ed1SGavin Shan pci_walk_bus(phb->hose->bus, pnv_pci_ioda_dev_dma_weight, 20232b923ed1SGavin Shan &total_weight); 20242b923ed1SGavin Shan segs = (weight * phb->ioda.dma32_count) / total_weight; 20252b923ed1SGavin Shan if (!segs) 20262b923ed1SGavin Shan segs = 1; 20272b923ed1SGavin Shan 20282b923ed1SGavin Shan /* 20292b923ed1SGavin Shan * Allocate contiguous DMA32 segments. We begin with the expected 20302b923ed1SGavin Shan * number of segments. With one more attempt, the number of DMA32 20312b923ed1SGavin Shan * segments to be allocated is decreased by one until one segment 20322b923ed1SGavin Shan * is allocated successfully. 20332b923ed1SGavin Shan */ 20342b923ed1SGavin Shan do { 20352b923ed1SGavin Shan for (base = 0; base <= phb->ioda.dma32_count - segs; base++) { 20362b923ed1SGavin Shan for (avail = 0, i = base; i < base + segs; i++) { 20372b923ed1SGavin Shan if (phb->ioda.dma32_segmap[i] == 20382b923ed1SGavin Shan IODA_INVALID_PE) 20392b923ed1SGavin Shan avail++; 20402b923ed1SGavin Shan } 20412b923ed1SGavin Shan 20422b923ed1SGavin Shan if (avail == segs) 20432b923ed1SGavin Shan goto found; 20442b923ed1SGavin Shan } 20452b923ed1SGavin Shan } while (--segs); 20462b923ed1SGavin Shan 20472b923ed1SGavin Shan if (!segs) { 20482b923ed1SGavin Shan pe_warn(pe, "No available DMA32 segments\n"); 20492b923ed1SGavin Shan return; 20502b923ed1SGavin Shan } 20512b923ed1SGavin Shan 20522b923ed1SGavin Shan found: 20530eaf4defSAlexey Kardashevskiy tbl = pnv_pci_table_alloc(phb->hose->node); 2054b348aa65SAlexey Kardashevskiy iommu_register_group(&pe->table_group, phb->hose->global_number, 2055b348aa65SAlexey Kardashevskiy pe->pe_number); 20560eaf4defSAlexey Kardashevskiy pnv_pci_link_table_and_group(phb->hose->node, 0, tbl, &pe->table_group); 2057c5773822SAlexey Kardashevskiy 2058184cd4a3SBenjamin Herrenschmidt /* Grab a 32-bit TCE table */ 20592b923ed1SGavin Shan pe_info(pe, "DMA weight %d (%d), assigned (%d) %d DMA32 segments\n", 20602b923ed1SGavin Shan weight, total_weight, base, segs); 2061184cd4a3SBenjamin Herrenschmidt pe_info(pe, " Setting up 32-bit TCE table at %08x..%08x\n", 2062acce971cSGavin Shan base * PNV_IODA1_DMA32_SEGSIZE, 2063acce971cSGavin Shan (base + segs) * PNV_IODA1_DMA32_SEGSIZE - 1); 2064184cd4a3SBenjamin Herrenschmidt 2065184cd4a3SBenjamin Herrenschmidt /* XXX Currently, we allocate one big contiguous table for the 2066184cd4a3SBenjamin Herrenschmidt * TCEs. We only really need one chunk per 256M of TCE space 2067184cd4a3SBenjamin Herrenschmidt * (ie per segment) but that's an optimization for later, it 2068184cd4a3SBenjamin Herrenschmidt * requires some added smarts with our get/put_tce implementation 2069acce971cSGavin Shan * 2070acce971cSGavin Shan * Each TCE page is 4KB in size and each TCE entry occupies 8 2071acce971cSGavin Shan * bytes 2072184cd4a3SBenjamin Herrenschmidt */ 2073acce971cSGavin Shan tce32_segsz = PNV_IODA1_DMA32_SEGSIZE >> (IOMMU_PAGE_SHIFT_4K - 3); 2074184cd4a3SBenjamin Herrenschmidt tce_mem = alloc_pages_node(phb->hose->node, GFP_KERNEL, 2075acce971cSGavin Shan get_order(tce32_segsz * segs)); 2076184cd4a3SBenjamin Herrenschmidt if (!tce_mem) { 2077184cd4a3SBenjamin Herrenschmidt pe_err(pe, " Failed to allocate a 32-bit TCE memory\n"); 2078184cd4a3SBenjamin Herrenschmidt goto fail; 2079184cd4a3SBenjamin Herrenschmidt } 2080184cd4a3SBenjamin Herrenschmidt addr = page_address(tce_mem); 2081acce971cSGavin Shan memset(addr, 0, tce32_segsz * segs); 2082184cd4a3SBenjamin Herrenschmidt 2083184cd4a3SBenjamin Herrenschmidt /* Configure HW */ 2084184cd4a3SBenjamin Herrenschmidt for (i = 0; i < segs; i++) { 2085184cd4a3SBenjamin Herrenschmidt rc = opal_pci_map_pe_dma_window(phb->opal_id, 2086184cd4a3SBenjamin Herrenschmidt pe->pe_number, 2087184cd4a3SBenjamin Herrenschmidt base + i, 1, 2088acce971cSGavin Shan __pa(addr) + tce32_segsz * i, 2089acce971cSGavin Shan tce32_segsz, IOMMU_PAGE_SIZE_4K); 2090184cd4a3SBenjamin Herrenschmidt if (rc) { 2091184cd4a3SBenjamin Herrenschmidt pe_err(pe, " Failed to configure 32-bit TCE table," 2092184cd4a3SBenjamin Herrenschmidt " err %ld\n", rc); 2093184cd4a3SBenjamin Herrenschmidt goto fail; 2094184cd4a3SBenjamin Herrenschmidt } 2095184cd4a3SBenjamin Herrenschmidt } 2096184cd4a3SBenjamin Herrenschmidt 20972b923ed1SGavin Shan /* Setup DMA32 segment mapping */ 20982b923ed1SGavin Shan for (i = base; i < base + segs; i++) 20992b923ed1SGavin Shan phb->ioda.dma32_segmap[i] = pe->pe_number; 21002b923ed1SGavin Shan 2101184cd4a3SBenjamin Herrenschmidt /* Setup linux iommu table */ 2102acce971cSGavin Shan pnv_pci_setup_iommu_table(tbl, addr, tce32_segsz * segs, 2103acce971cSGavin Shan base * PNV_IODA1_DMA32_SEGSIZE, 2104acce971cSGavin Shan IOMMU_PAGE_SHIFT_4K); 2105184cd4a3SBenjamin Herrenschmidt 2106184cd4a3SBenjamin Herrenschmidt /* OPAL variant of P7IOC SW invalidated TCEs */ 21075780fb04SAlexey Kardashevskiy if (phb->ioda.tce_inval_reg) 210865fd766bSGavin Shan tbl->it_type |= (TCE_PCI_SWINV_CREATE | 210965fd766bSGavin Shan TCE_PCI_SWINV_FREE | 211065fd766bSGavin Shan TCE_PCI_SWINV_PAIR); 21115780fb04SAlexey Kardashevskiy 2112da004c36SAlexey Kardashevskiy tbl->it_ops = &pnv_ioda1_iommu_ops; 21134793d65dSAlexey Kardashevskiy pe->table_group.tce32_start = tbl->it_offset << tbl->it_page_shift; 21144793d65dSAlexey Kardashevskiy pe->table_group.tce32_size = tbl->it_size << tbl->it_page_shift; 2115184cd4a3SBenjamin Herrenschmidt iommu_init_table(tbl, phb->hose->node); 2116184cd4a3SBenjamin Herrenschmidt 2117781a868fSWei Yang if (pe->flags & PNV_IODA_PE_DEV) { 21184617082eSAlexey Kardashevskiy /* 21194617082eSAlexey Kardashevskiy * Setting table base here only for carrying iommu_group 21204617082eSAlexey Kardashevskiy * further down to let iommu_add_device() do the job. 21214617082eSAlexey Kardashevskiy * pnv_pci_ioda_dma_dev_setup will override it later anyway. 21224617082eSAlexey Kardashevskiy */ 21234617082eSAlexey Kardashevskiy set_iommu_table_base(&pe->pdev->dev, tbl); 21244617082eSAlexey Kardashevskiy iommu_add_device(&pe->pdev->dev); 2125c5773822SAlexey Kardashevskiy } else if (pe->flags & (PNV_IODA_PE_BUS | PNV_IODA_PE_BUS_ALL)) 2126ea30e99eSAlexey Kardashevskiy pnv_ioda_setup_bus_dma(pe, pe->pbus); 212774251fe2SBenjamin Herrenschmidt 2128184cd4a3SBenjamin Herrenschmidt return; 2129184cd4a3SBenjamin Herrenschmidt fail: 2130184cd4a3SBenjamin Herrenschmidt /* XXX Failure: Try to fallback to 64-bit only ? */ 2131184cd4a3SBenjamin Herrenschmidt if (tce_mem) 2132acce971cSGavin Shan __free_pages(tce_mem, get_order(tce32_segsz * segs)); 21330eaf4defSAlexey Kardashevskiy if (tbl) { 21340eaf4defSAlexey Kardashevskiy pnv_pci_unlink_table_and_group(tbl, &pe->table_group); 21350eaf4defSAlexey Kardashevskiy iommu_free_table(tbl, "pnv"); 21360eaf4defSAlexey Kardashevskiy } 2137184cd4a3SBenjamin Herrenschmidt } 2138184cd4a3SBenjamin Herrenschmidt 213943cb60abSAlexey Kardashevskiy static long pnv_pci_ioda2_set_window(struct iommu_table_group *table_group, 214043cb60abSAlexey Kardashevskiy int num, struct iommu_table *tbl) 214143cb60abSAlexey Kardashevskiy { 214243cb60abSAlexey Kardashevskiy struct pnv_ioda_pe *pe = container_of(table_group, struct pnv_ioda_pe, 214343cb60abSAlexey Kardashevskiy table_group); 214443cb60abSAlexey Kardashevskiy struct pnv_phb *phb = pe->phb; 214543cb60abSAlexey Kardashevskiy int64_t rc; 2146bbb845c4SAlexey Kardashevskiy const unsigned long size = tbl->it_indirect_levels ? 2147bbb845c4SAlexey Kardashevskiy tbl->it_level_size : tbl->it_size; 214843cb60abSAlexey Kardashevskiy const __u64 start_addr = tbl->it_offset << tbl->it_page_shift; 214943cb60abSAlexey Kardashevskiy const __u64 win_size = tbl->it_size << tbl->it_page_shift; 215043cb60abSAlexey Kardashevskiy 21514793d65dSAlexey Kardashevskiy pe_info(pe, "Setting up window#%d %llx..%llx pg=%x\n", num, 215243cb60abSAlexey Kardashevskiy start_addr, start_addr + win_size - 1, 215343cb60abSAlexey Kardashevskiy IOMMU_PAGE_SIZE(tbl)); 215443cb60abSAlexey Kardashevskiy 215543cb60abSAlexey Kardashevskiy /* 215643cb60abSAlexey Kardashevskiy * Map TCE table through TVT. The TVE index is the PE number 215743cb60abSAlexey Kardashevskiy * shifted by 1 bit for 32-bits DMA space. 215843cb60abSAlexey Kardashevskiy */ 215943cb60abSAlexey Kardashevskiy rc = opal_pci_map_pe_dma_window(phb->opal_id, 216043cb60abSAlexey Kardashevskiy pe->pe_number, 21614793d65dSAlexey Kardashevskiy (pe->pe_number << 1) + num, 2162bbb845c4SAlexey Kardashevskiy tbl->it_indirect_levels + 1, 216343cb60abSAlexey Kardashevskiy __pa(tbl->it_base), 2164bbb845c4SAlexey Kardashevskiy size << 3, 216543cb60abSAlexey Kardashevskiy IOMMU_PAGE_SIZE(tbl)); 216643cb60abSAlexey Kardashevskiy if (rc) { 216743cb60abSAlexey Kardashevskiy pe_err(pe, "Failed to configure TCE table, err %ld\n", rc); 216843cb60abSAlexey Kardashevskiy return rc; 216943cb60abSAlexey Kardashevskiy } 217043cb60abSAlexey Kardashevskiy 217143cb60abSAlexey Kardashevskiy pnv_pci_link_table_and_group(phb->hose->node, num, 217243cb60abSAlexey Kardashevskiy tbl, &pe->table_group); 2173a7cf13caSAlexey Kardashevskiy pnv_pci_ioda2_tce_invalidate_pe(pe); 217443cb60abSAlexey Kardashevskiy 217543cb60abSAlexey Kardashevskiy return 0; 217643cb60abSAlexey Kardashevskiy } 217743cb60abSAlexey Kardashevskiy 2178f87a8864SAlexey Kardashevskiy static void pnv_pci_ioda2_set_bypass(struct pnv_ioda_pe *pe, bool enable) 2179cd15b048SBenjamin Herrenschmidt { 2180cd15b048SBenjamin Herrenschmidt uint16_t window_id = (pe->pe_number << 1 ) + 1; 2181cd15b048SBenjamin Herrenschmidt int64_t rc; 2182cd15b048SBenjamin Herrenschmidt 2183cd15b048SBenjamin Herrenschmidt pe_info(pe, "%sabling 64-bit DMA bypass\n", enable ? "En" : "Dis"); 2184cd15b048SBenjamin Herrenschmidt if (enable) { 2185cd15b048SBenjamin Herrenschmidt phys_addr_t top = memblock_end_of_DRAM(); 2186cd15b048SBenjamin Herrenschmidt 2187cd15b048SBenjamin Herrenschmidt top = roundup_pow_of_two(top); 2188cd15b048SBenjamin Herrenschmidt rc = opal_pci_map_pe_dma_window_real(pe->phb->opal_id, 2189cd15b048SBenjamin Herrenschmidt pe->pe_number, 2190cd15b048SBenjamin Herrenschmidt window_id, 2191cd15b048SBenjamin Herrenschmidt pe->tce_bypass_base, 2192cd15b048SBenjamin Herrenschmidt top); 2193cd15b048SBenjamin Herrenschmidt } else { 2194cd15b048SBenjamin Herrenschmidt rc = opal_pci_map_pe_dma_window_real(pe->phb->opal_id, 2195cd15b048SBenjamin Herrenschmidt pe->pe_number, 2196cd15b048SBenjamin Herrenschmidt window_id, 2197cd15b048SBenjamin Herrenschmidt pe->tce_bypass_base, 2198cd15b048SBenjamin Herrenschmidt 0); 2199cd15b048SBenjamin Herrenschmidt } 2200cd15b048SBenjamin Herrenschmidt if (rc) 2201cd15b048SBenjamin Herrenschmidt pe_err(pe, "OPAL error %lld configuring bypass window\n", rc); 2202cd15b048SBenjamin Herrenschmidt else 2203cd15b048SBenjamin Herrenschmidt pe->tce_bypass_enabled = enable; 2204cd15b048SBenjamin Herrenschmidt } 2205cd15b048SBenjamin Herrenschmidt 22064793d65dSAlexey Kardashevskiy static long pnv_pci_ioda2_table_alloc_pages(int nid, __u64 bus_offset, 22074793d65dSAlexey Kardashevskiy __u32 page_shift, __u64 window_size, __u32 levels, 22084793d65dSAlexey Kardashevskiy struct iommu_table *tbl); 22094793d65dSAlexey Kardashevskiy 22104793d65dSAlexey Kardashevskiy static long pnv_pci_ioda2_create_table(struct iommu_table_group *table_group, 22114793d65dSAlexey Kardashevskiy int num, __u32 page_shift, __u64 window_size, __u32 levels, 22124793d65dSAlexey Kardashevskiy struct iommu_table **ptbl) 22134793d65dSAlexey Kardashevskiy { 22144793d65dSAlexey Kardashevskiy struct pnv_ioda_pe *pe = container_of(table_group, struct pnv_ioda_pe, 22154793d65dSAlexey Kardashevskiy table_group); 22164793d65dSAlexey Kardashevskiy int nid = pe->phb->hose->node; 22174793d65dSAlexey Kardashevskiy __u64 bus_offset = num ? pe->tce_bypass_base : table_group->tce32_start; 22184793d65dSAlexey Kardashevskiy long ret; 22194793d65dSAlexey Kardashevskiy struct iommu_table *tbl; 22204793d65dSAlexey Kardashevskiy 22214793d65dSAlexey Kardashevskiy tbl = pnv_pci_table_alloc(nid); 22224793d65dSAlexey Kardashevskiy if (!tbl) 22234793d65dSAlexey Kardashevskiy return -ENOMEM; 22244793d65dSAlexey Kardashevskiy 22254793d65dSAlexey Kardashevskiy ret = pnv_pci_ioda2_table_alloc_pages(nid, 22264793d65dSAlexey Kardashevskiy bus_offset, page_shift, window_size, 22274793d65dSAlexey Kardashevskiy levels, tbl); 22284793d65dSAlexey Kardashevskiy if (ret) { 22294793d65dSAlexey Kardashevskiy iommu_free_table(tbl, "pnv"); 22304793d65dSAlexey Kardashevskiy return ret; 22314793d65dSAlexey Kardashevskiy } 22324793d65dSAlexey Kardashevskiy 22334793d65dSAlexey Kardashevskiy tbl->it_ops = &pnv_ioda2_iommu_ops; 22344793d65dSAlexey Kardashevskiy if (pe->phb->ioda.tce_inval_reg) 22354793d65dSAlexey Kardashevskiy tbl->it_type |= (TCE_PCI_SWINV_CREATE | TCE_PCI_SWINV_FREE); 22364793d65dSAlexey Kardashevskiy 22374793d65dSAlexey Kardashevskiy *ptbl = tbl; 22384793d65dSAlexey Kardashevskiy 22394793d65dSAlexey Kardashevskiy return 0; 22404793d65dSAlexey Kardashevskiy } 22414793d65dSAlexey Kardashevskiy 224246d3e1e1SAlexey Kardashevskiy static long pnv_pci_ioda2_setup_default_config(struct pnv_ioda_pe *pe) 224346d3e1e1SAlexey Kardashevskiy { 224446d3e1e1SAlexey Kardashevskiy struct iommu_table *tbl = NULL; 224546d3e1e1SAlexey Kardashevskiy long rc; 224646d3e1e1SAlexey Kardashevskiy 2247bb005455SNishanth Aravamudan /* 2248fa144869SNishanth Aravamudan * crashkernel= specifies the kdump kernel's maximum memory at 2249fa144869SNishanth Aravamudan * some offset and there is no guaranteed the result is a power 2250fa144869SNishanth Aravamudan * of 2, which will cause errors later. 2251fa144869SNishanth Aravamudan */ 2252fa144869SNishanth Aravamudan const u64 max_memory = __rounddown_pow_of_two(memory_hotplug_max()); 2253fa144869SNishanth Aravamudan 2254fa144869SNishanth Aravamudan /* 2255bb005455SNishanth Aravamudan * In memory constrained environments, e.g. kdump kernel, the 2256bb005455SNishanth Aravamudan * DMA window can be larger than available memory, which will 2257bb005455SNishanth Aravamudan * cause errors later. 2258bb005455SNishanth Aravamudan */ 2259fa144869SNishanth Aravamudan const u64 window_size = min((u64)pe->table_group.tce32_size, max_memory); 2260bb005455SNishanth Aravamudan 226146d3e1e1SAlexey Kardashevskiy rc = pnv_pci_ioda2_create_table(&pe->table_group, 0, 226246d3e1e1SAlexey Kardashevskiy IOMMU_PAGE_SHIFT_4K, 2263bb005455SNishanth Aravamudan window_size, 226446d3e1e1SAlexey Kardashevskiy POWERNV_IOMMU_DEFAULT_LEVELS, &tbl); 226546d3e1e1SAlexey Kardashevskiy if (rc) { 226646d3e1e1SAlexey Kardashevskiy pe_err(pe, "Failed to create 32-bit TCE table, err %ld", 226746d3e1e1SAlexey Kardashevskiy rc); 226846d3e1e1SAlexey Kardashevskiy return rc; 226946d3e1e1SAlexey Kardashevskiy } 227046d3e1e1SAlexey Kardashevskiy 227146d3e1e1SAlexey Kardashevskiy iommu_init_table(tbl, pe->phb->hose->node); 227246d3e1e1SAlexey Kardashevskiy 227346d3e1e1SAlexey Kardashevskiy rc = pnv_pci_ioda2_set_window(&pe->table_group, 0, tbl); 227446d3e1e1SAlexey Kardashevskiy if (rc) { 227546d3e1e1SAlexey Kardashevskiy pe_err(pe, "Failed to configure 32-bit TCE table, err %ld\n", 227646d3e1e1SAlexey Kardashevskiy rc); 227746d3e1e1SAlexey Kardashevskiy pnv_ioda2_table_free(tbl); 227846d3e1e1SAlexey Kardashevskiy return rc; 227946d3e1e1SAlexey Kardashevskiy } 228046d3e1e1SAlexey Kardashevskiy 228146d3e1e1SAlexey Kardashevskiy if (!pnv_iommu_bypass_disabled) 228246d3e1e1SAlexey Kardashevskiy pnv_pci_ioda2_set_bypass(pe, true); 228346d3e1e1SAlexey Kardashevskiy 228446d3e1e1SAlexey Kardashevskiy /* OPAL variant of PHB3 invalidated TCEs */ 228546d3e1e1SAlexey Kardashevskiy if (pe->phb->ioda.tce_inval_reg) 228646d3e1e1SAlexey Kardashevskiy tbl->it_type |= (TCE_PCI_SWINV_CREATE | TCE_PCI_SWINV_FREE); 228746d3e1e1SAlexey Kardashevskiy 228846d3e1e1SAlexey Kardashevskiy /* 228946d3e1e1SAlexey Kardashevskiy * Setting table base here only for carrying iommu_group 229046d3e1e1SAlexey Kardashevskiy * further down to let iommu_add_device() do the job. 229146d3e1e1SAlexey Kardashevskiy * pnv_pci_ioda_dma_dev_setup will override it later anyway. 229246d3e1e1SAlexey Kardashevskiy */ 229346d3e1e1SAlexey Kardashevskiy if (pe->flags & PNV_IODA_PE_DEV) 229446d3e1e1SAlexey Kardashevskiy set_iommu_table_base(&pe->pdev->dev, tbl); 229546d3e1e1SAlexey Kardashevskiy 229646d3e1e1SAlexey Kardashevskiy return 0; 229746d3e1e1SAlexey Kardashevskiy } 229846d3e1e1SAlexey Kardashevskiy 2299b5926430SAlexey Kardashevskiy #if defined(CONFIG_IOMMU_API) || defined(CONFIG_PCI_IOV) 2300b5926430SAlexey Kardashevskiy static long pnv_pci_ioda2_unset_window(struct iommu_table_group *table_group, 2301b5926430SAlexey Kardashevskiy int num) 2302b5926430SAlexey Kardashevskiy { 2303b5926430SAlexey Kardashevskiy struct pnv_ioda_pe *pe = container_of(table_group, struct pnv_ioda_pe, 2304b5926430SAlexey Kardashevskiy table_group); 2305b5926430SAlexey Kardashevskiy struct pnv_phb *phb = pe->phb; 2306b5926430SAlexey Kardashevskiy long ret; 2307b5926430SAlexey Kardashevskiy 2308b5926430SAlexey Kardashevskiy pe_info(pe, "Removing DMA window #%d\n", num); 2309b5926430SAlexey Kardashevskiy 2310b5926430SAlexey Kardashevskiy ret = opal_pci_map_pe_dma_window(phb->opal_id, pe->pe_number, 2311b5926430SAlexey Kardashevskiy (pe->pe_number << 1) + num, 2312b5926430SAlexey Kardashevskiy 0/* levels */, 0/* table address */, 2313b5926430SAlexey Kardashevskiy 0/* table size */, 0/* page size */); 2314b5926430SAlexey Kardashevskiy if (ret) 2315b5926430SAlexey Kardashevskiy pe_warn(pe, "Unmapping failed, ret = %ld\n", ret); 2316b5926430SAlexey Kardashevskiy else 2317a7cf13caSAlexey Kardashevskiy pnv_pci_ioda2_tce_invalidate_pe(pe); 2318b5926430SAlexey Kardashevskiy 2319b5926430SAlexey Kardashevskiy pnv_pci_unlink_table_and_group(table_group->tables[num], table_group); 2320b5926430SAlexey Kardashevskiy 2321b5926430SAlexey Kardashevskiy return ret; 2322b5926430SAlexey Kardashevskiy } 2323b5926430SAlexey Kardashevskiy #endif 2324b5926430SAlexey Kardashevskiy 2325f87a8864SAlexey Kardashevskiy #ifdef CONFIG_IOMMU_API 232600547193SAlexey Kardashevskiy static unsigned long pnv_pci_ioda2_get_table_size(__u32 page_shift, 232700547193SAlexey Kardashevskiy __u64 window_size, __u32 levels) 232800547193SAlexey Kardashevskiy { 232900547193SAlexey Kardashevskiy unsigned long bytes = 0; 233000547193SAlexey Kardashevskiy const unsigned window_shift = ilog2(window_size); 233100547193SAlexey Kardashevskiy unsigned entries_shift = window_shift - page_shift; 233200547193SAlexey Kardashevskiy unsigned table_shift = entries_shift + 3; 233300547193SAlexey Kardashevskiy unsigned long tce_table_size = max(0x1000UL, 1UL << table_shift); 233400547193SAlexey Kardashevskiy unsigned long direct_table_size; 233500547193SAlexey Kardashevskiy 233600547193SAlexey Kardashevskiy if (!levels || (levels > POWERNV_IOMMU_MAX_LEVELS) || 233700547193SAlexey Kardashevskiy (window_size > memory_hotplug_max()) || 233800547193SAlexey Kardashevskiy !is_power_of_2(window_size)) 233900547193SAlexey Kardashevskiy return 0; 234000547193SAlexey Kardashevskiy 234100547193SAlexey Kardashevskiy /* Calculate a direct table size from window_size and levels */ 234200547193SAlexey Kardashevskiy entries_shift = (entries_shift + levels - 1) / levels; 234300547193SAlexey Kardashevskiy table_shift = entries_shift + 3; 234400547193SAlexey Kardashevskiy table_shift = max_t(unsigned, table_shift, PAGE_SHIFT); 234500547193SAlexey Kardashevskiy direct_table_size = 1UL << table_shift; 234600547193SAlexey Kardashevskiy 234700547193SAlexey Kardashevskiy for ( ; levels; --levels) { 234800547193SAlexey Kardashevskiy bytes += _ALIGN_UP(tce_table_size, direct_table_size); 234900547193SAlexey Kardashevskiy 235000547193SAlexey Kardashevskiy tce_table_size /= direct_table_size; 235100547193SAlexey Kardashevskiy tce_table_size <<= 3; 235200547193SAlexey Kardashevskiy tce_table_size = _ALIGN_UP(tce_table_size, direct_table_size); 235300547193SAlexey Kardashevskiy } 235400547193SAlexey Kardashevskiy 235500547193SAlexey Kardashevskiy return bytes; 235600547193SAlexey Kardashevskiy } 235700547193SAlexey Kardashevskiy 2358f87a8864SAlexey Kardashevskiy static void pnv_ioda2_take_ownership(struct iommu_table_group *table_group) 2359cd15b048SBenjamin Herrenschmidt { 2360f87a8864SAlexey Kardashevskiy struct pnv_ioda_pe *pe = container_of(table_group, struct pnv_ioda_pe, 2361f87a8864SAlexey Kardashevskiy table_group); 236246d3e1e1SAlexey Kardashevskiy /* Store @tbl as pnv_pci_ioda2_unset_window() resets it */ 236346d3e1e1SAlexey Kardashevskiy struct iommu_table *tbl = pe->table_group.tables[0]; 2364cd15b048SBenjamin Herrenschmidt 2365f87a8864SAlexey Kardashevskiy pnv_pci_ioda2_set_bypass(pe, false); 236646d3e1e1SAlexey Kardashevskiy pnv_pci_ioda2_unset_window(&pe->table_group, 0); 236746d3e1e1SAlexey Kardashevskiy pnv_ioda2_table_free(tbl); 2368cd15b048SBenjamin Herrenschmidt } 2369cd15b048SBenjamin Herrenschmidt 2370f87a8864SAlexey Kardashevskiy static void pnv_ioda2_release_ownership(struct iommu_table_group *table_group) 2371f87a8864SAlexey Kardashevskiy { 2372f87a8864SAlexey Kardashevskiy struct pnv_ioda_pe *pe = container_of(table_group, struct pnv_ioda_pe, 2373f87a8864SAlexey Kardashevskiy table_group); 2374f87a8864SAlexey Kardashevskiy 237546d3e1e1SAlexey Kardashevskiy pnv_pci_ioda2_setup_default_config(pe); 2376f87a8864SAlexey Kardashevskiy } 2377f87a8864SAlexey Kardashevskiy 2378f87a8864SAlexey Kardashevskiy static struct iommu_table_group_ops pnv_pci_ioda2_ops = { 237900547193SAlexey Kardashevskiy .get_table_size = pnv_pci_ioda2_get_table_size, 23804793d65dSAlexey Kardashevskiy .create_table = pnv_pci_ioda2_create_table, 23814793d65dSAlexey Kardashevskiy .set_window = pnv_pci_ioda2_set_window, 23824793d65dSAlexey Kardashevskiy .unset_window = pnv_pci_ioda2_unset_window, 2383f87a8864SAlexey Kardashevskiy .take_ownership = pnv_ioda2_take_ownership, 2384f87a8864SAlexey Kardashevskiy .release_ownership = pnv_ioda2_release_ownership, 2385f87a8864SAlexey Kardashevskiy }; 2386b5cb9ab1SAlexey Kardashevskiy 2387b5cb9ab1SAlexey Kardashevskiy static int gpe_table_group_to_npe_cb(struct device *dev, void *opaque) 2388b5cb9ab1SAlexey Kardashevskiy { 2389b5cb9ab1SAlexey Kardashevskiy struct pci_controller *hose; 2390b5cb9ab1SAlexey Kardashevskiy struct pnv_phb *phb; 2391b5cb9ab1SAlexey Kardashevskiy struct pnv_ioda_pe **ptmppe = opaque; 2392b5cb9ab1SAlexey Kardashevskiy struct pci_dev *pdev = container_of(dev, struct pci_dev, dev); 2393b5cb9ab1SAlexey Kardashevskiy struct pci_dn *pdn = pci_get_pdn(pdev); 2394b5cb9ab1SAlexey Kardashevskiy 2395b5cb9ab1SAlexey Kardashevskiy if (!pdn || pdn->pe_number == IODA_INVALID_PE) 2396b5cb9ab1SAlexey Kardashevskiy return 0; 2397b5cb9ab1SAlexey Kardashevskiy 2398b5cb9ab1SAlexey Kardashevskiy hose = pci_bus_to_host(pdev->bus); 2399b5cb9ab1SAlexey Kardashevskiy phb = hose->private_data; 2400b5cb9ab1SAlexey Kardashevskiy if (phb->type != PNV_PHB_NPU) 2401b5cb9ab1SAlexey Kardashevskiy return 0; 2402b5cb9ab1SAlexey Kardashevskiy 2403b5cb9ab1SAlexey Kardashevskiy *ptmppe = &phb->ioda.pe_array[pdn->pe_number]; 2404b5cb9ab1SAlexey Kardashevskiy 2405b5cb9ab1SAlexey Kardashevskiy return 1; 2406b5cb9ab1SAlexey Kardashevskiy } 2407b5cb9ab1SAlexey Kardashevskiy 2408b5cb9ab1SAlexey Kardashevskiy /* 2409b5cb9ab1SAlexey Kardashevskiy * This returns PE of associated NPU. 2410b5cb9ab1SAlexey Kardashevskiy * This assumes that NPU is in the same IOMMU group with GPU and there is 2411b5cb9ab1SAlexey Kardashevskiy * no other PEs. 2412b5cb9ab1SAlexey Kardashevskiy */ 2413b5cb9ab1SAlexey Kardashevskiy static struct pnv_ioda_pe *gpe_table_group_to_npe( 2414b5cb9ab1SAlexey Kardashevskiy struct iommu_table_group *table_group) 2415b5cb9ab1SAlexey Kardashevskiy { 2416b5cb9ab1SAlexey Kardashevskiy struct pnv_ioda_pe *npe = NULL; 2417b5cb9ab1SAlexey Kardashevskiy int ret = iommu_group_for_each_dev(table_group->group, &npe, 2418b5cb9ab1SAlexey Kardashevskiy gpe_table_group_to_npe_cb); 2419b5cb9ab1SAlexey Kardashevskiy 2420b5cb9ab1SAlexey Kardashevskiy BUG_ON(!ret || !npe); 2421b5cb9ab1SAlexey Kardashevskiy 2422b5cb9ab1SAlexey Kardashevskiy return npe; 2423b5cb9ab1SAlexey Kardashevskiy } 2424b5cb9ab1SAlexey Kardashevskiy 2425b5cb9ab1SAlexey Kardashevskiy static long pnv_pci_ioda2_npu_set_window(struct iommu_table_group *table_group, 2426b5cb9ab1SAlexey Kardashevskiy int num, struct iommu_table *tbl) 2427b5cb9ab1SAlexey Kardashevskiy { 2428b5cb9ab1SAlexey Kardashevskiy long ret = pnv_pci_ioda2_set_window(table_group, num, tbl); 2429b5cb9ab1SAlexey Kardashevskiy 2430b5cb9ab1SAlexey Kardashevskiy if (ret) 2431b5cb9ab1SAlexey Kardashevskiy return ret; 2432b5cb9ab1SAlexey Kardashevskiy 2433b5cb9ab1SAlexey Kardashevskiy ret = pnv_npu_set_window(gpe_table_group_to_npe(table_group), num, tbl); 2434b5cb9ab1SAlexey Kardashevskiy if (ret) 2435b5cb9ab1SAlexey Kardashevskiy pnv_pci_ioda2_unset_window(table_group, num); 2436b5cb9ab1SAlexey Kardashevskiy 2437b5cb9ab1SAlexey Kardashevskiy return ret; 2438b5cb9ab1SAlexey Kardashevskiy } 2439b5cb9ab1SAlexey Kardashevskiy 2440b5cb9ab1SAlexey Kardashevskiy static long pnv_pci_ioda2_npu_unset_window( 2441b5cb9ab1SAlexey Kardashevskiy struct iommu_table_group *table_group, 2442b5cb9ab1SAlexey Kardashevskiy int num) 2443b5cb9ab1SAlexey Kardashevskiy { 2444b5cb9ab1SAlexey Kardashevskiy long ret = pnv_pci_ioda2_unset_window(table_group, num); 2445b5cb9ab1SAlexey Kardashevskiy 2446b5cb9ab1SAlexey Kardashevskiy if (ret) 2447b5cb9ab1SAlexey Kardashevskiy return ret; 2448b5cb9ab1SAlexey Kardashevskiy 2449b5cb9ab1SAlexey Kardashevskiy return pnv_npu_unset_window(gpe_table_group_to_npe(table_group), num); 2450b5cb9ab1SAlexey Kardashevskiy } 2451b5cb9ab1SAlexey Kardashevskiy 2452b5cb9ab1SAlexey Kardashevskiy static void pnv_ioda2_npu_take_ownership(struct iommu_table_group *table_group) 2453b5cb9ab1SAlexey Kardashevskiy { 2454b5cb9ab1SAlexey Kardashevskiy /* 2455b5cb9ab1SAlexey Kardashevskiy * Detach NPU first as pnv_ioda2_take_ownership() will destroy 2456b5cb9ab1SAlexey Kardashevskiy * the iommu_table if 32bit DMA is enabled. 2457b5cb9ab1SAlexey Kardashevskiy */ 2458b5cb9ab1SAlexey Kardashevskiy pnv_npu_take_ownership(gpe_table_group_to_npe(table_group)); 2459b5cb9ab1SAlexey Kardashevskiy pnv_ioda2_take_ownership(table_group); 2460b5cb9ab1SAlexey Kardashevskiy } 2461b5cb9ab1SAlexey Kardashevskiy 2462b5cb9ab1SAlexey Kardashevskiy static struct iommu_table_group_ops pnv_pci_ioda2_npu_ops = { 2463b5cb9ab1SAlexey Kardashevskiy .get_table_size = pnv_pci_ioda2_get_table_size, 2464b5cb9ab1SAlexey Kardashevskiy .create_table = pnv_pci_ioda2_create_table, 2465b5cb9ab1SAlexey Kardashevskiy .set_window = pnv_pci_ioda2_npu_set_window, 2466b5cb9ab1SAlexey Kardashevskiy .unset_window = pnv_pci_ioda2_npu_unset_window, 2467b5cb9ab1SAlexey Kardashevskiy .take_ownership = pnv_ioda2_npu_take_ownership, 2468b5cb9ab1SAlexey Kardashevskiy .release_ownership = pnv_ioda2_release_ownership, 2469b5cb9ab1SAlexey Kardashevskiy }; 2470b5cb9ab1SAlexey Kardashevskiy 2471b5cb9ab1SAlexey Kardashevskiy static void pnv_pci_ioda_setup_iommu_api(void) 2472b5cb9ab1SAlexey Kardashevskiy { 2473b5cb9ab1SAlexey Kardashevskiy struct pci_controller *hose, *tmp; 2474b5cb9ab1SAlexey Kardashevskiy struct pnv_phb *phb; 2475b5cb9ab1SAlexey Kardashevskiy struct pnv_ioda_pe *pe, *gpe; 2476b5cb9ab1SAlexey Kardashevskiy 2477b5cb9ab1SAlexey Kardashevskiy /* 2478b5cb9ab1SAlexey Kardashevskiy * Now we have all PHBs discovered, time to add NPU devices to 2479b5cb9ab1SAlexey Kardashevskiy * the corresponding IOMMU groups. 2480b5cb9ab1SAlexey Kardashevskiy */ 2481b5cb9ab1SAlexey Kardashevskiy list_for_each_entry_safe(hose, tmp, &hose_list, list_node) { 2482b5cb9ab1SAlexey Kardashevskiy phb = hose->private_data; 2483b5cb9ab1SAlexey Kardashevskiy 2484b5cb9ab1SAlexey Kardashevskiy if (phb->type != PNV_PHB_NPU) 2485b5cb9ab1SAlexey Kardashevskiy continue; 2486b5cb9ab1SAlexey Kardashevskiy 2487b5cb9ab1SAlexey Kardashevskiy list_for_each_entry(pe, &phb->ioda.pe_list, list) { 2488b5cb9ab1SAlexey Kardashevskiy gpe = pnv_pci_npu_setup_iommu(pe); 2489b5cb9ab1SAlexey Kardashevskiy if (gpe) 2490b5cb9ab1SAlexey Kardashevskiy gpe->table_group.ops = &pnv_pci_ioda2_npu_ops; 2491b5cb9ab1SAlexey Kardashevskiy } 2492b5cb9ab1SAlexey Kardashevskiy } 2493b5cb9ab1SAlexey Kardashevskiy } 2494b5cb9ab1SAlexey Kardashevskiy #else /* !CONFIG_IOMMU_API */ 2495b5cb9ab1SAlexey Kardashevskiy static void pnv_pci_ioda_setup_iommu_api(void) { }; 2496f87a8864SAlexey Kardashevskiy #endif 2497f87a8864SAlexey Kardashevskiy 24985780fb04SAlexey Kardashevskiy static void pnv_pci_ioda_setup_opal_tce_kill(struct pnv_phb *phb) 24995780fb04SAlexey Kardashevskiy { 25005780fb04SAlexey Kardashevskiy const __be64 *swinvp; 25015780fb04SAlexey Kardashevskiy 25025780fb04SAlexey Kardashevskiy /* OPAL variant of PHB3 invalidated TCEs */ 25035780fb04SAlexey Kardashevskiy swinvp = of_get_property(phb->hose->dn, "ibm,opal-tce-kill", NULL); 25045780fb04SAlexey Kardashevskiy if (!swinvp) 25055780fb04SAlexey Kardashevskiy return; 25065780fb04SAlexey Kardashevskiy 25075780fb04SAlexey Kardashevskiy phb->ioda.tce_inval_reg_phys = be64_to_cpup(swinvp); 25085780fb04SAlexey Kardashevskiy phb->ioda.tce_inval_reg = ioremap(phb->ioda.tce_inval_reg_phys, 8); 25095780fb04SAlexey Kardashevskiy } 25105780fb04SAlexey Kardashevskiy 2511bbb845c4SAlexey Kardashevskiy static __be64 *pnv_pci_ioda2_table_do_alloc_pages(int nid, unsigned shift, 2512bbb845c4SAlexey Kardashevskiy unsigned levels, unsigned long limit, 25133ba3a73eSAlexey Kardashevskiy unsigned long *current_offset, unsigned long *total_allocated) 2514aca6913fSAlexey Kardashevskiy { 2515aca6913fSAlexey Kardashevskiy struct page *tce_mem = NULL; 2516bbb845c4SAlexey Kardashevskiy __be64 *addr, *tmp; 2517aca6913fSAlexey Kardashevskiy unsigned order = max_t(unsigned, shift, PAGE_SHIFT) - PAGE_SHIFT; 2518bbb845c4SAlexey Kardashevskiy unsigned long allocated = 1UL << (order + PAGE_SHIFT); 2519bbb845c4SAlexey Kardashevskiy unsigned entries = 1UL << (shift - 3); 2520bbb845c4SAlexey Kardashevskiy long i; 2521aca6913fSAlexey Kardashevskiy 2522aca6913fSAlexey Kardashevskiy tce_mem = alloc_pages_node(nid, GFP_KERNEL, order); 2523aca6913fSAlexey Kardashevskiy if (!tce_mem) { 2524aca6913fSAlexey Kardashevskiy pr_err("Failed to allocate a TCE memory, order=%d\n", order); 2525aca6913fSAlexey Kardashevskiy return NULL; 2526aca6913fSAlexey Kardashevskiy } 2527aca6913fSAlexey Kardashevskiy addr = page_address(tce_mem); 2528bbb845c4SAlexey Kardashevskiy memset(addr, 0, allocated); 25293ba3a73eSAlexey Kardashevskiy *total_allocated += allocated; 2530bbb845c4SAlexey Kardashevskiy 2531bbb845c4SAlexey Kardashevskiy --levels; 2532bbb845c4SAlexey Kardashevskiy if (!levels) { 2533bbb845c4SAlexey Kardashevskiy *current_offset += allocated; 2534bbb845c4SAlexey Kardashevskiy return addr; 2535bbb845c4SAlexey Kardashevskiy } 2536bbb845c4SAlexey Kardashevskiy 2537bbb845c4SAlexey Kardashevskiy for (i = 0; i < entries; ++i) { 2538bbb845c4SAlexey Kardashevskiy tmp = pnv_pci_ioda2_table_do_alloc_pages(nid, shift, 25393ba3a73eSAlexey Kardashevskiy levels, limit, current_offset, total_allocated); 2540bbb845c4SAlexey Kardashevskiy if (!tmp) 2541bbb845c4SAlexey Kardashevskiy break; 2542bbb845c4SAlexey Kardashevskiy 2543bbb845c4SAlexey Kardashevskiy addr[i] = cpu_to_be64(__pa(tmp) | 2544bbb845c4SAlexey Kardashevskiy TCE_PCI_READ | TCE_PCI_WRITE); 2545bbb845c4SAlexey Kardashevskiy 2546bbb845c4SAlexey Kardashevskiy if (*current_offset >= limit) 2547bbb845c4SAlexey Kardashevskiy break; 2548bbb845c4SAlexey Kardashevskiy } 2549aca6913fSAlexey Kardashevskiy 2550aca6913fSAlexey Kardashevskiy return addr; 2551aca6913fSAlexey Kardashevskiy } 2552aca6913fSAlexey Kardashevskiy 2553bbb845c4SAlexey Kardashevskiy static void pnv_pci_ioda2_table_do_free_pages(__be64 *addr, 2554bbb845c4SAlexey Kardashevskiy unsigned long size, unsigned level); 2555bbb845c4SAlexey Kardashevskiy 2556aca6913fSAlexey Kardashevskiy static long pnv_pci_ioda2_table_alloc_pages(int nid, __u64 bus_offset, 2557bbb845c4SAlexey Kardashevskiy __u32 page_shift, __u64 window_size, __u32 levels, 2558bbb845c4SAlexey Kardashevskiy struct iommu_table *tbl) 2559aca6913fSAlexey Kardashevskiy { 2560aca6913fSAlexey Kardashevskiy void *addr; 25613ba3a73eSAlexey Kardashevskiy unsigned long offset = 0, level_shift, total_allocated = 0; 2562aca6913fSAlexey Kardashevskiy const unsigned window_shift = ilog2(window_size); 2563aca6913fSAlexey Kardashevskiy unsigned entries_shift = window_shift - page_shift; 2564aca6913fSAlexey Kardashevskiy unsigned table_shift = max_t(unsigned, entries_shift + 3, PAGE_SHIFT); 2565aca6913fSAlexey Kardashevskiy const unsigned long tce_table_size = 1UL << table_shift; 2566aca6913fSAlexey Kardashevskiy 2567bbb845c4SAlexey Kardashevskiy if (!levels || (levels > POWERNV_IOMMU_MAX_LEVELS)) 2568bbb845c4SAlexey Kardashevskiy return -EINVAL; 2569bbb845c4SAlexey Kardashevskiy 2570aca6913fSAlexey Kardashevskiy if ((window_size > memory_hotplug_max()) || !is_power_of_2(window_size)) 2571aca6913fSAlexey Kardashevskiy return -EINVAL; 2572aca6913fSAlexey Kardashevskiy 2573bbb845c4SAlexey Kardashevskiy /* Adjust direct table size from window_size and levels */ 2574bbb845c4SAlexey Kardashevskiy entries_shift = (entries_shift + levels - 1) / levels; 2575bbb845c4SAlexey Kardashevskiy level_shift = entries_shift + 3; 2576bbb845c4SAlexey Kardashevskiy level_shift = max_t(unsigned, level_shift, PAGE_SHIFT); 2577bbb845c4SAlexey Kardashevskiy 2578aca6913fSAlexey Kardashevskiy /* Allocate TCE table */ 2579bbb845c4SAlexey Kardashevskiy addr = pnv_pci_ioda2_table_do_alloc_pages(nid, level_shift, 25803ba3a73eSAlexey Kardashevskiy levels, tce_table_size, &offset, &total_allocated); 2581bbb845c4SAlexey Kardashevskiy 2582bbb845c4SAlexey Kardashevskiy /* addr==NULL means that the first level allocation failed */ 2583aca6913fSAlexey Kardashevskiy if (!addr) 2584aca6913fSAlexey Kardashevskiy return -ENOMEM; 2585aca6913fSAlexey Kardashevskiy 2586bbb845c4SAlexey Kardashevskiy /* 2587bbb845c4SAlexey Kardashevskiy * First level was allocated but some lower level failed as 2588bbb845c4SAlexey Kardashevskiy * we did not allocate as much as we wanted, 2589bbb845c4SAlexey Kardashevskiy * release partially allocated table. 2590bbb845c4SAlexey Kardashevskiy */ 2591bbb845c4SAlexey Kardashevskiy if (offset < tce_table_size) { 2592bbb845c4SAlexey Kardashevskiy pnv_pci_ioda2_table_do_free_pages(addr, 2593bbb845c4SAlexey Kardashevskiy 1ULL << (level_shift - 3), levels - 1); 2594bbb845c4SAlexey Kardashevskiy return -ENOMEM; 2595bbb845c4SAlexey Kardashevskiy } 2596bbb845c4SAlexey Kardashevskiy 2597aca6913fSAlexey Kardashevskiy /* Setup linux iommu table */ 2598aca6913fSAlexey Kardashevskiy pnv_pci_setup_iommu_table(tbl, addr, tce_table_size, bus_offset, 2599aca6913fSAlexey Kardashevskiy page_shift); 2600bbb845c4SAlexey Kardashevskiy tbl->it_level_size = 1ULL << (level_shift - 3); 2601bbb845c4SAlexey Kardashevskiy tbl->it_indirect_levels = levels - 1; 26023ba3a73eSAlexey Kardashevskiy tbl->it_allocated_size = total_allocated; 2603aca6913fSAlexey Kardashevskiy 2604aca6913fSAlexey Kardashevskiy pr_devel("Created TCE table: ws=%08llx ts=%lx @%08llx\n", 2605aca6913fSAlexey Kardashevskiy window_size, tce_table_size, bus_offset); 2606aca6913fSAlexey Kardashevskiy 2607aca6913fSAlexey Kardashevskiy return 0; 2608aca6913fSAlexey Kardashevskiy } 2609aca6913fSAlexey Kardashevskiy 2610bbb845c4SAlexey Kardashevskiy static void pnv_pci_ioda2_table_do_free_pages(__be64 *addr, 2611bbb845c4SAlexey Kardashevskiy unsigned long size, unsigned level) 2612bbb845c4SAlexey Kardashevskiy { 2613bbb845c4SAlexey Kardashevskiy const unsigned long addr_ul = (unsigned long) addr & 2614bbb845c4SAlexey Kardashevskiy ~(TCE_PCI_READ | TCE_PCI_WRITE); 2615bbb845c4SAlexey Kardashevskiy 2616bbb845c4SAlexey Kardashevskiy if (level) { 2617bbb845c4SAlexey Kardashevskiy long i; 2618bbb845c4SAlexey Kardashevskiy u64 *tmp = (u64 *) addr_ul; 2619bbb845c4SAlexey Kardashevskiy 2620bbb845c4SAlexey Kardashevskiy for (i = 0; i < size; ++i) { 2621bbb845c4SAlexey Kardashevskiy unsigned long hpa = be64_to_cpu(tmp[i]); 2622bbb845c4SAlexey Kardashevskiy 2623bbb845c4SAlexey Kardashevskiy if (!(hpa & (TCE_PCI_READ | TCE_PCI_WRITE))) 2624bbb845c4SAlexey Kardashevskiy continue; 2625bbb845c4SAlexey Kardashevskiy 2626bbb845c4SAlexey Kardashevskiy pnv_pci_ioda2_table_do_free_pages(__va(hpa), size, 2627bbb845c4SAlexey Kardashevskiy level - 1); 2628bbb845c4SAlexey Kardashevskiy } 2629bbb845c4SAlexey Kardashevskiy } 2630bbb845c4SAlexey Kardashevskiy 2631bbb845c4SAlexey Kardashevskiy free_pages(addr_ul, get_order(size << 3)); 2632bbb845c4SAlexey Kardashevskiy } 2633bbb845c4SAlexey Kardashevskiy 2634aca6913fSAlexey Kardashevskiy static void pnv_pci_ioda2_table_free_pages(struct iommu_table *tbl) 2635aca6913fSAlexey Kardashevskiy { 2636bbb845c4SAlexey Kardashevskiy const unsigned long size = tbl->it_indirect_levels ? 2637bbb845c4SAlexey Kardashevskiy tbl->it_level_size : tbl->it_size; 2638bbb845c4SAlexey Kardashevskiy 2639aca6913fSAlexey Kardashevskiy if (!tbl->it_size) 2640aca6913fSAlexey Kardashevskiy return; 2641aca6913fSAlexey Kardashevskiy 2642bbb845c4SAlexey Kardashevskiy pnv_pci_ioda2_table_do_free_pages((__be64 *)tbl->it_base, size, 2643bbb845c4SAlexey Kardashevskiy tbl->it_indirect_levels); 2644aca6913fSAlexey Kardashevskiy } 2645aca6913fSAlexey Kardashevskiy 2646373f5657SGavin Shan static void pnv_pci_ioda2_setup_dma_pe(struct pnv_phb *phb, 2647373f5657SGavin Shan struct pnv_ioda_pe *pe) 2648373f5657SGavin Shan { 2649373f5657SGavin Shan int64_t rc; 2650373f5657SGavin Shan 2651ccd1c191SGavin Shan if (!pnv_pci_ioda_pe_dma_weight(pe)) 2652ccd1c191SGavin Shan return; 2653ccd1c191SGavin Shan 2654f87a8864SAlexey Kardashevskiy /* TVE #1 is selected by PCI address bit 59 */ 2655f87a8864SAlexey Kardashevskiy pe->tce_bypass_base = 1ull << 59; 2656f87a8864SAlexey Kardashevskiy 2657b348aa65SAlexey Kardashevskiy iommu_register_group(&pe->table_group, phb->hose->global_number, 2658b348aa65SAlexey Kardashevskiy pe->pe_number); 2659c5773822SAlexey Kardashevskiy 2660373f5657SGavin Shan /* The PE will reserve all possible 32-bits space */ 2661373f5657SGavin Shan pe_info(pe, "Setting up 32-bit TCE table at 0..%08x\n", 2662aca6913fSAlexey Kardashevskiy phb->ioda.m32_pci_base); 2663373f5657SGavin Shan 2664e5aad1e6SAlexey Kardashevskiy /* Setup linux iommu table */ 26654793d65dSAlexey Kardashevskiy pe->table_group.tce32_start = 0; 26664793d65dSAlexey Kardashevskiy pe->table_group.tce32_size = phb->ioda.m32_pci_base; 26674793d65dSAlexey Kardashevskiy pe->table_group.max_dynamic_windows_supported = 26684793d65dSAlexey Kardashevskiy IOMMU_TABLE_GROUP_MAX_TABLES; 26694793d65dSAlexey Kardashevskiy pe->table_group.max_levels = POWERNV_IOMMU_MAX_LEVELS; 26704793d65dSAlexey Kardashevskiy pe->table_group.pgsizes = SZ_4K | SZ_64K | SZ_16M; 2671e5aad1e6SAlexey Kardashevskiy #ifdef CONFIG_IOMMU_API 2672e5aad1e6SAlexey Kardashevskiy pe->table_group.ops = &pnv_pci_ioda2_ops; 2673e5aad1e6SAlexey Kardashevskiy #endif 2674e5aad1e6SAlexey Kardashevskiy 267546d3e1e1SAlexey Kardashevskiy rc = pnv_pci_ioda2_setup_default_config(pe); 2676801846d1SGavin Shan if (rc) 267746d3e1e1SAlexey Kardashevskiy return; 267846d3e1e1SAlexey Kardashevskiy 267946d3e1e1SAlexey Kardashevskiy if (pe->flags & PNV_IODA_PE_DEV) 268046d3e1e1SAlexey Kardashevskiy iommu_add_device(&pe->pdev->dev); 268146d3e1e1SAlexey Kardashevskiy else if (pe->flags & (PNV_IODA_PE_BUS | PNV_IODA_PE_BUS_ALL)) 268246d3e1e1SAlexey Kardashevskiy pnv_ioda_setup_bus_dma(pe, pe->pbus); 2683373f5657SGavin Shan } 2684373f5657SGavin Shan 2685184cd4a3SBenjamin Herrenschmidt #ifdef CONFIG_PCI_MSI 2686137436c9SGavin Shan static void pnv_ioda2_msi_eoi(struct irq_data *d) 2687137436c9SGavin Shan { 2688137436c9SGavin Shan unsigned int hw_irq = (unsigned int)irqd_to_hwirq(d); 2689137436c9SGavin Shan struct irq_chip *chip = irq_data_get_irq_chip(d); 2690137436c9SGavin Shan struct pnv_phb *phb = container_of(chip, struct pnv_phb, 2691137436c9SGavin Shan ioda.irq_chip); 2692137436c9SGavin Shan int64_t rc; 2693137436c9SGavin Shan 2694137436c9SGavin Shan rc = opal_pci_msi_eoi(phb->opal_id, hw_irq); 2695137436c9SGavin Shan WARN_ON_ONCE(rc); 2696137436c9SGavin Shan 2697137436c9SGavin Shan icp_native_eoi(d); 2698137436c9SGavin Shan } 2699137436c9SGavin Shan 2700fd9a1c26SIan Munsie 2701fd9a1c26SIan Munsie static void set_msi_irq_chip(struct pnv_phb *phb, unsigned int virq) 2702fd9a1c26SIan Munsie { 2703fd9a1c26SIan Munsie struct irq_data *idata; 2704fd9a1c26SIan Munsie struct irq_chip *ichip; 2705fd9a1c26SIan Munsie 2706fd9a1c26SIan Munsie if (phb->type != PNV_PHB_IODA2) 2707fd9a1c26SIan Munsie return; 2708fd9a1c26SIan Munsie 2709fd9a1c26SIan Munsie if (!phb->ioda.irq_chip_init) { 2710fd9a1c26SIan Munsie /* 2711fd9a1c26SIan Munsie * First time we setup an MSI IRQ, we need to setup the 2712fd9a1c26SIan Munsie * corresponding IRQ chip to route correctly. 2713fd9a1c26SIan Munsie */ 2714fd9a1c26SIan Munsie idata = irq_get_irq_data(virq); 2715fd9a1c26SIan Munsie ichip = irq_data_get_irq_chip(idata); 2716fd9a1c26SIan Munsie phb->ioda.irq_chip_init = 1; 2717fd9a1c26SIan Munsie phb->ioda.irq_chip = *ichip; 2718fd9a1c26SIan Munsie phb->ioda.irq_chip.irq_eoi = pnv_ioda2_msi_eoi; 2719fd9a1c26SIan Munsie } 2720fd9a1c26SIan Munsie irq_set_chip(virq, &phb->ioda.irq_chip); 2721fd9a1c26SIan Munsie } 2722fd9a1c26SIan Munsie 272380c49c7eSIan Munsie #ifdef CONFIG_CXL_BASE 272480c49c7eSIan Munsie 27256f963ec2SRyan Grimm struct device_node *pnv_pci_get_phb_node(struct pci_dev *dev) 272680c49c7eSIan Munsie { 272780c49c7eSIan Munsie struct pci_controller *hose = pci_bus_to_host(dev->bus); 272880c49c7eSIan Munsie 27296f963ec2SRyan Grimm return of_node_get(hose->dn); 273080c49c7eSIan Munsie } 27316f963ec2SRyan Grimm EXPORT_SYMBOL(pnv_pci_get_phb_node); 273280c49c7eSIan Munsie 27331212aa1cSRyan Grimm int pnv_phb_to_cxl_mode(struct pci_dev *dev, uint64_t mode) 273480c49c7eSIan Munsie { 273580c49c7eSIan Munsie struct pci_controller *hose = pci_bus_to_host(dev->bus); 273680c49c7eSIan Munsie struct pnv_phb *phb = hose->private_data; 273780c49c7eSIan Munsie struct pnv_ioda_pe *pe; 273880c49c7eSIan Munsie int rc; 273980c49c7eSIan Munsie 274080c49c7eSIan Munsie pe = pnv_ioda_get_pe(dev); 274180c49c7eSIan Munsie if (!pe) 274280c49c7eSIan Munsie return -ENODEV; 274380c49c7eSIan Munsie 274480c49c7eSIan Munsie pe_info(pe, "Switching PHB to CXL\n"); 274580c49c7eSIan Munsie 27461212aa1cSRyan Grimm rc = opal_pci_set_phb_cxl_mode(phb->opal_id, mode, pe->pe_number); 2747b385c9e9SIan Munsie if (rc == OPAL_UNSUPPORTED) 2748b385c9e9SIan Munsie dev_err(&dev->dev, "Required cxl mode not supported by firmware - update skiboot\n"); 2749b385c9e9SIan Munsie else if (rc) 275080c49c7eSIan Munsie dev_err(&dev->dev, "opal_pci_set_phb_cxl_mode failed: %i\n", rc); 275180c49c7eSIan Munsie 275280c49c7eSIan Munsie return rc; 275380c49c7eSIan Munsie } 27541212aa1cSRyan Grimm EXPORT_SYMBOL(pnv_phb_to_cxl_mode); 275580c49c7eSIan Munsie 275680c49c7eSIan Munsie /* Find PHB for cxl dev and allocate MSI hwirqs? 275780c49c7eSIan Munsie * Returns the absolute hardware IRQ number 275880c49c7eSIan Munsie */ 275980c49c7eSIan Munsie int pnv_cxl_alloc_hwirqs(struct pci_dev *dev, int num) 276080c49c7eSIan Munsie { 276180c49c7eSIan Munsie struct pci_controller *hose = pci_bus_to_host(dev->bus); 276280c49c7eSIan Munsie struct pnv_phb *phb = hose->private_data; 276380c49c7eSIan Munsie int hwirq = msi_bitmap_alloc_hwirqs(&phb->msi_bmp, num); 276480c49c7eSIan Munsie 276580c49c7eSIan Munsie if (hwirq < 0) { 276680c49c7eSIan Munsie dev_warn(&dev->dev, "Failed to find a free MSI\n"); 276780c49c7eSIan Munsie return -ENOSPC; 276880c49c7eSIan Munsie } 276980c49c7eSIan Munsie 277080c49c7eSIan Munsie return phb->msi_base + hwirq; 277180c49c7eSIan Munsie } 277280c49c7eSIan Munsie EXPORT_SYMBOL(pnv_cxl_alloc_hwirqs); 277380c49c7eSIan Munsie 277480c49c7eSIan Munsie void pnv_cxl_release_hwirqs(struct pci_dev *dev, int hwirq, int num) 277580c49c7eSIan Munsie { 277680c49c7eSIan Munsie struct pci_controller *hose = pci_bus_to_host(dev->bus); 277780c49c7eSIan Munsie struct pnv_phb *phb = hose->private_data; 277880c49c7eSIan Munsie 277980c49c7eSIan Munsie msi_bitmap_free_hwirqs(&phb->msi_bmp, hwirq - phb->msi_base, num); 278080c49c7eSIan Munsie } 278180c49c7eSIan Munsie EXPORT_SYMBOL(pnv_cxl_release_hwirqs); 278280c49c7eSIan Munsie 278380c49c7eSIan Munsie void pnv_cxl_release_hwirq_ranges(struct cxl_irq_ranges *irqs, 278480c49c7eSIan Munsie struct pci_dev *dev) 278580c49c7eSIan Munsie { 278680c49c7eSIan Munsie struct pci_controller *hose = pci_bus_to_host(dev->bus); 278780c49c7eSIan Munsie struct pnv_phb *phb = hose->private_data; 278880c49c7eSIan Munsie int i, hwirq; 278980c49c7eSIan Munsie 279080c49c7eSIan Munsie for (i = 1; i < CXL_IRQ_RANGES; i++) { 279180c49c7eSIan Munsie if (!irqs->range[i]) 279280c49c7eSIan Munsie continue; 279380c49c7eSIan Munsie pr_devel("cxl release irq range 0x%x: offset: 0x%lx limit: %ld\n", 279480c49c7eSIan Munsie i, irqs->offset[i], 279580c49c7eSIan Munsie irqs->range[i]); 279680c49c7eSIan Munsie hwirq = irqs->offset[i] - phb->msi_base; 279780c49c7eSIan Munsie msi_bitmap_free_hwirqs(&phb->msi_bmp, hwirq, 279880c49c7eSIan Munsie irqs->range[i]); 279980c49c7eSIan Munsie } 280080c49c7eSIan Munsie } 280180c49c7eSIan Munsie EXPORT_SYMBOL(pnv_cxl_release_hwirq_ranges); 280280c49c7eSIan Munsie 280380c49c7eSIan Munsie int pnv_cxl_alloc_hwirq_ranges(struct cxl_irq_ranges *irqs, 280480c49c7eSIan Munsie struct pci_dev *dev, int num) 280580c49c7eSIan Munsie { 280680c49c7eSIan Munsie struct pci_controller *hose = pci_bus_to_host(dev->bus); 280780c49c7eSIan Munsie struct pnv_phb *phb = hose->private_data; 280880c49c7eSIan Munsie int i, hwirq, try; 280980c49c7eSIan Munsie 281080c49c7eSIan Munsie memset(irqs, 0, sizeof(struct cxl_irq_ranges)); 281180c49c7eSIan Munsie 281280c49c7eSIan Munsie /* 0 is reserved for the multiplexed PSL DSI interrupt */ 281380c49c7eSIan Munsie for (i = 1; i < CXL_IRQ_RANGES && num; i++) { 281480c49c7eSIan Munsie try = num; 281580c49c7eSIan Munsie while (try) { 281680c49c7eSIan Munsie hwirq = msi_bitmap_alloc_hwirqs(&phb->msi_bmp, try); 281780c49c7eSIan Munsie if (hwirq >= 0) 281880c49c7eSIan Munsie break; 281980c49c7eSIan Munsie try /= 2; 282080c49c7eSIan Munsie } 282180c49c7eSIan Munsie if (!try) 282280c49c7eSIan Munsie goto fail; 282380c49c7eSIan Munsie 282480c49c7eSIan Munsie irqs->offset[i] = phb->msi_base + hwirq; 282580c49c7eSIan Munsie irqs->range[i] = try; 282680c49c7eSIan Munsie pr_devel("cxl alloc irq range 0x%x: offset: 0x%lx limit: %li\n", 282780c49c7eSIan Munsie i, irqs->offset[i], irqs->range[i]); 282880c49c7eSIan Munsie num -= try; 282980c49c7eSIan Munsie } 283080c49c7eSIan Munsie if (num) 283180c49c7eSIan Munsie goto fail; 283280c49c7eSIan Munsie 283380c49c7eSIan Munsie return 0; 283480c49c7eSIan Munsie fail: 283580c49c7eSIan Munsie pnv_cxl_release_hwirq_ranges(irqs, dev); 283680c49c7eSIan Munsie return -ENOSPC; 283780c49c7eSIan Munsie } 283880c49c7eSIan Munsie EXPORT_SYMBOL(pnv_cxl_alloc_hwirq_ranges); 283980c49c7eSIan Munsie 284080c49c7eSIan Munsie int pnv_cxl_get_irq_count(struct pci_dev *dev) 284180c49c7eSIan Munsie { 284280c49c7eSIan Munsie struct pci_controller *hose = pci_bus_to_host(dev->bus); 284380c49c7eSIan Munsie struct pnv_phb *phb = hose->private_data; 284480c49c7eSIan Munsie 284580c49c7eSIan Munsie return phb->msi_bmp.irq_count; 284680c49c7eSIan Munsie } 284780c49c7eSIan Munsie EXPORT_SYMBOL(pnv_cxl_get_irq_count); 284880c49c7eSIan Munsie 284980c49c7eSIan Munsie int pnv_cxl_ioda_msi_setup(struct pci_dev *dev, unsigned int hwirq, 285080c49c7eSIan Munsie unsigned int virq) 285180c49c7eSIan Munsie { 285280c49c7eSIan Munsie struct pci_controller *hose = pci_bus_to_host(dev->bus); 285380c49c7eSIan Munsie struct pnv_phb *phb = hose->private_data; 285480c49c7eSIan Munsie unsigned int xive_num = hwirq - phb->msi_base; 285580c49c7eSIan Munsie struct pnv_ioda_pe *pe; 285680c49c7eSIan Munsie int rc; 285780c49c7eSIan Munsie 285880c49c7eSIan Munsie if (!(pe = pnv_ioda_get_pe(dev))) 285980c49c7eSIan Munsie return -ENODEV; 286080c49c7eSIan Munsie 286180c49c7eSIan Munsie /* Assign XIVE to PE */ 286280c49c7eSIan Munsie rc = opal_pci_set_xive_pe(phb->opal_id, pe->pe_number, xive_num); 286380c49c7eSIan Munsie if (rc) { 286480c49c7eSIan Munsie pe_warn(pe, "%s: OPAL error %d setting msi_base 0x%x " 286580c49c7eSIan Munsie "hwirq 0x%x XIVE 0x%x PE\n", 286680c49c7eSIan Munsie pci_name(dev), rc, phb->msi_base, hwirq, xive_num); 286780c49c7eSIan Munsie return -EIO; 286880c49c7eSIan Munsie } 286980c49c7eSIan Munsie set_msi_irq_chip(phb, virq); 287080c49c7eSIan Munsie 287180c49c7eSIan Munsie return 0; 287280c49c7eSIan Munsie } 287380c49c7eSIan Munsie EXPORT_SYMBOL(pnv_cxl_ioda_msi_setup); 287480c49c7eSIan Munsie #endif 287580c49c7eSIan Munsie 2876184cd4a3SBenjamin Herrenschmidt static int pnv_pci_ioda_msi_setup(struct pnv_phb *phb, struct pci_dev *dev, 2877137436c9SGavin Shan unsigned int hwirq, unsigned int virq, 2878137436c9SGavin Shan unsigned int is_64, struct msi_msg *msg) 2879184cd4a3SBenjamin Herrenschmidt { 2880184cd4a3SBenjamin Herrenschmidt struct pnv_ioda_pe *pe = pnv_ioda_get_pe(dev); 2881184cd4a3SBenjamin Herrenschmidt unsigned int xive_num = hwirq - phb->msi_base; 28823a1a4661SBenjamin Herrenschmidt __be32 data; 2883184cd4a3SBenjamin Herrenschmidt int rc; 2884184cd4a3SBenjamin Herrenschmidt 2885184cd4a3SBenjamin Herrenschmidt /* No PE assigned ? bail out ... no MSI for you ! */ 2886184cd4a3SBenjamin Herrenschmidt if (pe == NULL) 2887184cd4a3SBenjamin Herrenschmidt return -ENXIO; 2888184cd4a3SBenjamin Herrenschmidt 2889184cd4a3SBenjamin Herrenschmidt /* Check if we have an MVE */ 2890184cd4a3SBenjamin Herrenschmidt if (pe->mve_number < 0) 2891184cd4a3SBenjamin Herrenschmidt return -ENXIO; 2892184cd4a3SBenjamin Herrenschmidt 2893b72c1f65SBenjamin Herrenschmidt /* Force 32-bit MSI on some broken devices */ 289436074381SBenjamin Herrenschmidt if (dev->no_64bit_msi) 2895b72c1f65SBenjamin Herrenschmidt is_64 = 0; 2896b72c1f65SBenjamin Herrenschmidt 2897184cd4a3SBenjamin Herrenschmidt /* Assign XIVE to PE */ 2898184cd4a3SBenjamin Herrenschmidt rc = opal_pci_set_xive_pe(phb->opal_id, pe->pe_number, xive_num); 2899184cd4a3SBenjamin Herrenschmidt if (rc) { 2900184cd4a3SBenjamin Herrenschmidt pr_warn("%s: OPAL error %d setting XIVE %d PE\n", 2901184cd4a3SBenjamin Herrenschmidt pci_name(dev), rc, xive_num); 2902184cd4a3SBenjamin Herrenschmidt return -EIO; 2903184cd4a3SBenjamin Herrenschmidt } 2904184cd4a3SBenjamin Herrenschmidt 2905184cd4a3SBenjamin Herrenschmidt if (is_64) { 29063a1a4661SBenjamin Herrenschmidt __be64 addr64; 29073a1a4661SBenjamin Herrenschmidt 2908184cd4a3SBenjamin Herrenschmidt rc = opal_get_msi_64(phb->opal_id, pe->mve_number, xive_num, 1, 2909184cd4a3SBenjamin Herrenschmidt &addr64, &data); 2910184cd4a3SBenjamin Herrenschmidt if (rc) { 2911184cd4a3SBenjamin Herrenschmidt pr_warn("%s: OPAL error %d getting 64-bit MSI data\n", 2912184cd4a3SBenjamin Herrenschmidt pci_name(dev), rc); 2913184cd4a3SBenjamin Herrenschmidt return -EIO; 2914184cd4a3SBenjamin Herrenschmidt } 29153a1a4661SBenjamin Herrenschmidt msg->address_hi = be64_to_cpu(addr64) >> 32; 29163a1a4661SBenjamin Herrenschmidt msg->address_lo = be64_to_cpu(addr64) & 0xfffffffful; 2917184cd4a3SBenjamin Herrenschmidt } else { 29183a1a4661SBenjamin Herrenschmidt __be32 addr32; 29193a1a4661SBenjamin Herrenschmidt 2920184cd4a3SBenjamin Herrenschmidt rc = opal_get_msi_32(phb->opal_id, pe->mve_number, xive_num, 1, 2921184cd4a3SBenjamin Herrenschmidt &addr32, &data); 2922184cd4a3SBenjamin Herrenschmidt if (rc) { 2923184cd4a3SBenjamin Herrenschmidt pr_warn("%s: OPAL error %d getting 32-bit MSI data\n", 2924184cd4a3SBenjamin Herrenschmidt pci_name(dev), rc); 2925184cd4a3SBenjamin Herrenschmidt return -EIO; 2926184cd4a3SBenjamin Herrenschmidt } 2927184cd4a3SBenjamin Herrenschmidt msg->address_hi = 0; 29283a1a4661SBenjamin Herrenschmidt msg->address_lo = be32_to_cpu(addr32); 2929184cd4a3SBenjamin Herrenschmidt } 29303a1a4661SBenjamin Herrenschmidt msg->data = be32_to_cpu(data); 2931184cd4a3SBenjamin Herrenschmidt 2932fd9a1c26SIan Munsie set_msi_irq_chip(phb, virq); 2933137436c9SGavin Shan 2934184cd4a3SBenjamin Herrenschmidt pr_devel("%s: %s-bit MSI on hwirq %x (xive #%d)," 2935184cd4a3SBenjamin Herrenschmidt " address=%x_%08x data=%x PE# %d\n", 2936184cd4a3SBenjamin Herrenschmidt pci_name(dev), is_64 ? "64" : "32", hwirq, xive_num, 2937184cd4a3SBenjamin Herrenschmidt msg->address_hi, msg->address_lo, data, pe->pe_number); 2938184cd4a3SBenjamin Herrenschmidt 2939184cd4a3SBenjamin Herrenschmidt return 0; 2940184cd4a3SBenjamin Herrenschmidt } 2941184cd4a3SBenjamin Herrenschmidt 2942184cd4a3SBenjamin Herrenschmidt static void pnv_pci_init_ioda_msis(struct pnv_phb *phb) 2943184cd4a3SBenjamin Herrenschmidt { 2944fb1b55d6SGavin Shan unsigned int count; 2945184cd4a3SBenjamin Herrenschmidt const __be32 *prop = of_get_property(phb->hose->dn, 2946184cd4a3SBenjamin Herrenschmidt "ibm,opal-msi-ranges", NULL); 2947184cd4a3SBenjamin Herrenschmidt if (!prop) { 2948184cd4a3SBenjamin Herrenschmidt /* BML Fallback */ 2949184cd4a3SBenjamin Herrenschmidt prop = of_get_property(phb->hose->dn, "msi-ranges", NULL); 2950184cd4a3SBenjamin Herrenschmidt } 2951184cd4a3SBenjamin Herrenschmidt if (!prop) 2952184cd4a3SBenjamin Herrenschmidt return; 2953184cd4a3SBenjamin Herrenschmidt 2954184cd4a3SBenjamin Herrenschmidt phb->msi_base = be32_to_cpup(prop); 2955fb1b55d6SGavin Shan count = be32_to_cpup(prop + 1); 2956fb1b55d6SGavin Shan if (msi_bitmap_alloc(&phb->msi_bmp, count, phb->hose->dn)) { 2957184cd4a3SBenjamin Herrenschmidt pr_err("PCI %d: Failed to allocate MSI bitmap !\n", 2958184cd4a3SBenjamin Herrenschmidt phb->hose->global_number); 2959184cd4a3SBenjamin Herrenschmidt return; 2960184cd4a3SBenjamin Herrenschmidt } 2961fb1b55d6SGavin Shan 2962184cd4a3SBenjamin Herrenschmidt phb->msi_setup = pnv_pci_ioda_msi_setup; 2963184cd4a3SBenjamin Herrenschmidt phb->msi32_support = 1; 2964184cd4a3SBenjamin Herrenschmidt pr_info(" Allocated bitmap for %d MSIs (base IRQ 0x%x)\n", 2965fb1b55d6SGavin Shan count, phb->msi_base); 2966184cd4a3SBenjamin Herrenschmidt } 2967184cd4a3SBenjamin Herrenschmidt #else 2968184cd4a3SBenjamin Herrenschmidt static void pnv_pci_init_ioda_msis(struct pnv_phb *phb) { } 2969184cd4a3SBenjamin Herrenschmidt #endif /* CONFIG_PCI_MSI */ 2970184cd4a3SBenjamin Herrenschmidt 29716e628c7dSWei Yang #ifdef CONFIG_PCI_IOV 29726e628c7dSWei Yang static void pnv_pci_ioda_fixup_iov_resources(struct pci_dev *pdev) 29736e628c7dSWei Yang { 2974f2dd0afeSWei Yang struct pci_controller *hose = pci_bus_to_host(pdev->bus); 2975f2dd0afeSWei Yang struct pnv_phb *phb = hose->private_data; 2976f2dd0afeSWei Yang const resource_size_t gate = phb->ioda.m64_segsize >> 2; 29776e628c7dSWei Yang struct resource *res; 29786e628c7dSWei Yang int i; 2979dfcc8d45SWei Yang resource_size_t size, total_vf_bar_sz; 29806e628c7dSWei Yang struct pci_dn *pdn; 29815b88ec22SWei Yang int mul, total_vfs; 29826e628c7dSWei Yang 29836e628c7dSWei Yang if (!pdev->is_physfn || pdev->is_added) 29846e628c7dSWei Yang return; 29856e628c7dSWei Yang 29866e628c7dSWei Yang pdn = pci_get_pdn(pdev); 29876e628c7dSWei Yang pdn->vfs_expanded = 0; 2988ee8222feSWei Yang pdn->m64_single_mode = false; 29896e628c7dSWei Yang 29905b88ec22SWei Yang total_vfs = pci_sriov_get_totalvfs(pdev); 299192b8f137SGavin Shan mul = phb->ioda.total_pe_num; 2992dfcc8d45SWei Yang total_vf_bar_sz = 0; 29935b88ec22SWei Yang 29945b88ec22SWei Yang for (i = 0; i < PCI_SRIOV_NUM_BARS; i++) { 29955b88ec22SWei Yang res = &pdev->resource[i + PCI_IOV_RESOURCES]; 29965b88ec22SWei Yang if (!res->flags || res->parent) 29975b88ec22SWei Yang continue; 29985b88ec22SWei Yang if (!pnv_pci_is_mem_pref_64(res->flags)) { 2999b0331854SWei Yang dev_warn(&pdev->dev, "Don't support SR-IOV with" 3000b0331854SWei Yang " non M64 VF BAR%d: %pR. \n", 30015b88ec22SWei Yang i, res); 3002b0331854SWei Yang goto truncate_iov; 30035b88ec22SWei Yang } 30045b88ec22SWei Yang 3005dfcc8d45SWei Yang total_vf_bar_sz += pci_iov_resource_size(pdev, 3006dfcc8d45SWei Yang i + PCI_IOV_RESOURCES); 30075b88ec22SWei Yang 3008f2dd0afeSWei Yang /* 3009f2dd0afeSWei Yang * If bigger than quarter of M64 segment size, just round up 3010f2dd0afeSWei Yang * power of two. 3011f2dd0afeSWei Yang * 3012f2dd0afeSWei Yang * Generally, one M64 BAR maps one IOV BAR. To avoid conflict 3013f2dd0afeSWei Yang * with other devices, IOV BAR size is expanded to be 3014f2dd0afeSWei Yang * (total_pe * VF_BAR_size). When VF_BAR_size is half of M64 3015f2dd0afeSWei Yang * segment size , the expanded size would equal to half of the 3016f2dd0afeSWei Yang * whole M64 space size, which will exhaust the M64 Space and 3017f2dd0afeSWei Yang * limit the system flexibility. This is a design decision to 3018f2dd0afeSWei Yang * set the boundary to quarter of the M64 segment size. 3019f2dd0afeSWei Yang */ 3020dfcc8d45SWei Yang if (total_vf_bar_sz > gate) { 30215b88ec22SWei Yang mul = roundup_pow_of_two(total_vfs); 3022dfcc8d45SWei Yang dev_info(&pdev->dev, 3023dfcc8d45SWei Yang "VF BAR Total IOV size %llx > %llx, roundup to %d VFs\n", 3024dfcc8d45SWei Yang total_vf_bar_sz, gate, mul); 3025ee8222feSWei Yang pdn->m64_single_mode = true; 30265b88ec22SWei Yang break; 30275b88ec22SWei Yang } 30285b88ec22SWei Yang } 30295b88ec22SWei Yang 30306e628c7dSWei Yang for (i = 0; i < PCI_SRIOV_NUM_BARS; i++) { 30316e628c7dSWei Yang res = &pdev->resource[i + PCI_IOV_RESOURCES]; 30326e628c7dSWei Yang if (!res->flags || res->parent) 30336e628c7dSWei Yang continue; 30346e628c7dSWei Yang 30356e628c7dSWei Yang size = pci_iov_resource_size(pdev, i + PCI_IOV_RESOURCES); 3036ee8222feSWei Yang /* 3037ee8222feSWei Yang * On PHB3, the minimum size alignment of M64 BAR in single 3038ee8222feSWei Yang * mode is 32MB. 3039ee8222feSWei Yang */ 3040ee8222feSWei Yang if (pdn->m64_single_mode && (size < SZ_32M)) 3041ee8222feSWei Yang goto truncate_iov; 3042ee8222feSWei Yang dev_dbg(&pdev->dev, " Fixing VF BAR%d: %pR to\n", i, res); 30435b88ec22SWei Yang res->end = res->start + size * mul - 1; 30446e628c7dSWei Yang dev_dbg(&pdev->dev, " %pR\n", res); 30456e628c7dSWei Yang dev_info(&pdev->dev, "VF BAR%d: %pR (expanded to %d VFs for PE alignment)", 30465b88ec22SWei Yang i, res, mul); 30476e628c7dSWei Yang } 30485b88ec22SWei Yang pdn->vfs_expanded = mul; 3049b0331854SWei Yang 3050b0331854SWei Yang return; 3051b0331854SWei Yang 3052b0331854SWei Yang truncate_iov: 3053b0331854SWei Yang /* To save MMIO space, IOV BAR is truncated. */ 3054b0331854SWei Yang for (i = 0; i < PCI_SRIOV_NUM_BARS; i++) { 3055b0331854SWei Yang res = &pdev->resource[i + PCI_IOV_RESOURCES]; 3056b0331854SWei Yang res->flags = 0; 3057b0331854SWei Yang res->end = res->start - 1; 3058b0331854SWei Yang } 30596e628c7dSWei Yang } 30606e628c7dSWei Yang #endif /* CONFIG_PCI_IOV */ 30616e628c7dSWei Yang 306223e79425SGavin Shan static void pnv_ioda_setup_pe_res(struct pnv_ioda_pe *pe, 306323e79425SGavin Shan struct resource *res) 306411685becSGavin Shan { 306523e79425SGavin Shan struct pnv_phb *phb = pe->phb; 306611685becSGavin Shan struct pci_bus_region region; 306723e79425SGavin Shan int index; 306823e79425SGavin Shan int64_t rc; 306911685becSGavin Shan 307023e79425SGavin Shan if (!res || !res->flags || res->start > res->end) 307123e79425SGavin Shan return; 307211685becSGavin Shan 307311685becSGavin Shan if (res->flags & IORESOURCE_IO) { 307411685becSGavin Shan region.start = res->start - phb->ioda.io_pci_base; 307511685becSGavin Shan region.end = res->end - phb->ioda.io_pci_base; 307611685becSGavin Shan index = region.start / phb->ioda.io_segsize; 307711685becSGavin Shan 307892b8f137SGavin Shan while (index < phb->ioda.total_pe_num && 307911685becSGavin Shan region.start <= region.end) { 308011685becSGavin Shan phb->ioda.io_segmap[index] = pe->pe_number; 308111685becSGavin Shan rc = opal_pci_map_pe_mmio_window(phb->opal_id, 308211685becSGavin Shan pe->pe_number, OPAL_IO_WINDOW_TYPE, 0, index); 308311685becSGavin Shan if (rc != OPAL_SUCCESS) { 308423e79425SGavin Shan pr_err("%s: Error %lld mapping IO segment#%d to PE#%d\n", 308511685becSGavin Shan __func__, rc, index, pe->pe_number); 308611685becSGavin Shan break; 308711685becSGavin Shan } 308811685becSGavin Shan 308911685becSGavin Shan region.start += phb->ioda.io_segsize; 309011685becSGavin Shan index++; 309111685becSGavin Shan } 3092027fa02fSGavin Shan } else if ((res->flags & IORESOURCE_MEM) && 3093027fa02fSGavin Shan !pnv_pci_is_mem_pref_64(res->flags)) { 309411685becSGavin Shan region.start = res->start - 309523e79425SGavin Shan phb->hose->mem_offset[0] - 309611685becSGavin Shan phb->ioda.m32_pci_base; 309711685becSGavin Shan region.end = res->end - 309823e79425SGavin Shan phb->hose->mem_offset[0] - 309911685becSGavin Shan phb->ioda.m32_pci_base; 310011685becSGavin Shan index = region.start / phb->ioda.m32_segsize; 310111685becSGavin Shan 310292b8f137SGavin Shan while (index < phb->ioda.total_pe_num && 310311685becSGavin Shan region.start <= region.end) { 310411685becSGavin Shan phb->ioda.m32_segmap[index] = pe->pe_number; 310511685becSGavin Shan rc = opal_pci_map_pe_mmio_window(phb->opal_id, 310611685becSGavin Shan pe->pe_number, OPAL_M32_WINDOW_TYPE, 0, index); 310711685becSGavin Shan if (rc != OPAL_SUCCESS) { 310823e79425SGavin Shan pr_err("%s: Error %lld mapping M32 segment#%d to PE#%d", 310911685becSGavin Shan __func__, rc, index, pe->pe_number); 311011685becSGavin Shan break; 311111685becSGavin Shan } 311211685becSGavin Shan 311311685becSGavin Shan region.start += phb->ioda.m32_segsize; 311411685becSGavin Shan index++; 311511685becSGavin Shan } 311611685becSGavin Shan } 311711685becSGavin Shan } 311823e79425SGavin Shan 311923e79425SGavin Shan /* 312023e79425SGavin Shan * This function is supposed to be called on basis of PE from top 312123e79425SGavin Shan * to bottom style. So the the I/O or MMIO segment assigned to 312223e79425SGavin Shan * parent PE could be overrided by its child PEs if necessary. 312323e79425SGavin Shan */ 312423e79425SGavin Shan static void pnv_ioda_setup_pe_seg(struct pnv_ioda_pe *pe) 312523e79425SGavin Shan { 312669d733e7SGavin Shan struct pci_dev *pdev; 312723e79425SGavin Shan int i; 312823e79425SGavin Shan 312923e79425SGavin Shan /* 313023e79425SGavin Shan * NOTE: We only care PCI bus based PE for now. For PCI 313123e79425SGavin Shan * device based PE, for example SRIOV sensitive VF should 313223e79425SGavin Shan * be figured out later. 313323e79425SGavin Shan */ 313423e79425SGavin Shan BUG_ON(!(pe->flags & (PNV_IODA_PE_BUS | PNV_IODA_PE_BUS_ALL))); 313523e79425SGavin Shan 313669d733e7SGavin Shan list_for_each_entry(pdev, &pe->pbus->devices, bus_list) { 313769d733e7SGavin Shan for (i = 0; i <= PCI_ROM_RESOURCE; i++) 313869d733e7SGavin Shan pnv_ioda_setup_pe_res(pe, &pdev->resource[i]); 313969d733e7SGavin Shan 314069d733e7SGavin Shan /* 314169d733e7SGavin Shan * If the PE contains all subordinate PCI buses, the 314269d733e7SGavin Shan * windows of the child bridges should be mapped to 314369d733e7SGavin Shan * the PE as well. 314469d733e7SGavin Shan */ 314569d733e7SGavin Shan if (!(pe->flags & PNV_IODA_PE_BUS_ALL) || !pci_is_bridge(pdev)) 314669d733e7SGavin Shan continue; 314769d733e7SGavin Shan for (i = 0; i < PCI_BRIDGE_RESOURCE_NUM; i++) 314869d733e7SGavin Shan pnv_ioda_setup_pe_res(pe, 314969d733e7SGavin Shan &pdev->resource[PCI_BRIDGE_RESOURCES + i]); 315069d733e7SGavin Shan } 315111685becSGavin Shan } 315211685becSGavin Shan 315337c367f2SGavin Shan static void pnv_pci_ioda_create_dbgfs(void) 315437c367f2SGavin Shan { 315537c367f2SGavin Shan #ifdef CONFIG_DEBUG_FS 315637c367f2SGavin Shan struct pci_controller *hose, *tmp; 315737c367f2SGavin Shan struct pnv_phb *phb; 315837c367f2SGavin Shan char name[16]; 315937c367f2SGavin Shan 316037c367f2SGavin Shan list_for_each_entry_safe(hose, tmp, &hose_list, list_node) { 316137c367f2SGavin Shan phb = hose->private_data; 316237c367f2SGavin Shan 3163ccd1c191SGavin Shan /* Notify initialization of PHB done */ 3164ccd1c191SGavin Shan phb->initialized = 1; 3165ccd1c191SGavin Shan 316637c367f2SGavin Shan sprintf(name, "PCI%04x", hose->global_number); 316737c367f2SGavin Shan phb->dbgfs = debugfs_create_dir(name, powerpc_debugfs_root); 316837c367f2SGavin Shan if (!phb->dbgfs) 316937c367f2SGavin Shan pr_warning("%s: Error on creating debugfs on PHB#%x\n", 317037c367f2SGavin Shan __func__, hose->global_number); 317137c367f2SGavin Shan } 317237c367f2SGavin Shan #endif /* CONFIG_DEBUG_FS */ 317337c367f2SGavin Shan } 317437c367f2SGavin Shan 3175cad5cef6SGreg Kroah-Hartman static void pnv_pci_ioda_fixup(void) 3176fb446ad0SGavin Shan { 3177fb446ad0SGavin Shan pnv_pci_ioda_setup_PEs(); 3178ccd1c191SGavin Shan pnv_pci_ioda_setup_iommu_api(); 317937c367f2SGavin Shan pnv_pci_ioda_create_dbgfs(); 318037c367f2SGavin Shan 3181e9cc17d4SGavin Shan #ifdef CONFIG_EEH 3182e9cc17d4SGavin Shan eeh_init(); 3183dadcd6d6SMike Qiu eeh_addr_cache_build(); 3184e9cc17d4SGavin Shan #endif 3185fb446ad0SGavin Shan } 3186fb446ad0SGavin Shan 3187271fd03aSGavin Shan /* 3188271fd03aSGavin Shan * Returns the alignment for I/O or memory windows for P2P 3189271fd03aSGavin Shan * bridges. That actually depends on how PEs are segmented. 3190271fd03aSGavin Shan * For now, we return I/O or M32 segment size for PE sensitive 3191271fd03aSGavin Shan * P2P bridges. Otherwise, the default values (4KiB for I/O, 3192271fd03aSGavin Shan * 1MiB for memory) will be returned. 3193271fd03aSGavin Shan * 3194271fd03aSGavin Shan * The current PCI bus might be put into one PE, which was 3195271fd03aSGavin Shan * create against the parent PCI bridge. For that case, we 3196271fd03aSGavin Shan * needn't enlarge the alignment so that we can save some 3197271fd03aSGavin Shan * resources. 3198271fd03aSGavin Shan */ 3199271fd03aSGavin Shan static resource_size_t pnv_pci_window_alignment(struct pci_bus *bus, 3200271fd03aSGavin Shan unsigned long type) 3201271fd03aSGavin Shan { 3202271fd03aSGavin Shan struct pci_dev *bridge; 3203271fd03aSGavin Shan struct pci_controller *hose = pci_bus_to_host(bus); 3204271fd03aSGavin Shan struct pnv_phb *phb = hose->private_data; 3205271fd03aSGavin Shan int num_pci_bridges = 0; 3206271fd03aSGavin Shan 3207271fd03aSGavin Shan bridge = bus->self; 3208271fd03aSGavin Shan while (bridge) { 3209271fd03aSGavin Shan if (pci_pcie_type(bridge) == PCI_EXP_TYPE_PCI_BRIDGE) { 3210271fd03aSGavin Shan num_pci_bridges++; 3211271fd03aSGavin Shan if (num_pci_bridges >= 2) 3212271fd03aSGavin Shan return 1; 3213271fd03aSGavin Shan } 3214271fd03aSGavin Shan 3215271fd03aSGavin Shan bridge = bridge->bus->self; 3216271fd03aSGavin Shan } 3217271fd03aSGavin Shan 3218262af557SGuo Chao /* We fail back to M32 if M64 isn't supported */ 3219262af557SGuo Chao if (phb->ioda.m64_segsize && 3220262af557SGuo Chao pnv_pci_is_mem_pref_64(type)) 3221262af557SGuo Chao return phb->ioda.m64_segsize; 3222271fd03aSGavin Shan if (type & IORESOURCE_MEM) 3223271fd03aSGavin Shan return phb->ioda.m32_segsize; 3224271fd03aSGavin Shan 3225271fd03aSGavin Shan return phb->ioda.io_segsize; 3226271fd03aSGavin Shan } 3227271fd03aSGavin Shan 322840e2a47eSGavin Shan /* 322940e2a47eSGavin Shan * We are updating root port or the upstream port of the 323040e2a47eSGavin Shan * bridge behind the root port with PHB's windows in order 323140e2a47eSGavin Shan * to accommodate the changes on required resources during 323240e2a47eSGavin Shan * PCI (slot) hotplug, which is connected to either root 323340e2a47eSGavin Shan * port or the downstream ports of PCIe switch behind the 323440e2a47eSGavin Shan * root port. 323540e2a47eSGavin Shan */ 323640e2a47eSGavin Shan static void pnv_pci_fixup_bridge_resources(struct pci_bus *bus, 323740e2a47eSGavin Shan unsigned long type) 323840e2a47eSGavin Shan { 323940e2a47eSGavin Shan struct pci_controller *hose = pci_bus_to_host(bus); 324040e2a47eSGavin Shan struct pnv_phb *phb = hose->private_data; 324140e2a47eSGavin Shan struct pci_dev *bridge = bus->self; 324240e2a47eSGavin Shan struct resource *r, *w; 324340e2a47eSGavin Shan bool msi_region = false; 324440e2a47eSGavin Shan int i; 324540e2a47eSGavin Shan 324640e2a47eSGavin Shan /* Check if we need apply fixup to the bridge's windows */ 324740e2a47eSGavin Shan if (!pci_is_root_bus(bridge->bus) && 324840e2a47eSGavin Shan !pci_is_root_bus(bridge->bus->self->bus)) 324940e2a47eSGavin Shan return; 325040e2a47eSGavin Shan 325140e2a47eSGavin Shan /* Fixup the resources */ 325240e2a47eSGavin Shan for (i = 0; i < PCI_BRIDGE_RESOURCE_NUM; i++) { 325340e2a47eSGavin Shan r = &bridge->resource[PCI_BRIDGE_RESOURCES + i]; 325440e2a47eSGavin Shan if (!r->flags || !r->parent) 325540e2a47eSGavin Shan continue; 325640e2a47eSGavin Shan 325740e2a47eSGavin Shan w = NULL; 325840e2a47eSGavin Shan if (r->flags & type & IORESOURCE_IO) 325940e2a47eSGavin Shan w = &hose->io_resource; 326040e2a47eSGavin Shan else if (pnv_pci_is_mem_pref_64(r->flags) && 326140e2a47eSGavin Shan (type & IORESOURCE_PREFETCH) && 326240e2a47eSGavin Shan phb->ioda.m64_segsize) 326340e2a47eSGavin Shan w = &hose->mem_resources[1]; 326440e2a47eSGavin Shan else if (r->flags & type & IORESOURCE_MEM) { 326540e2a47eSGavin Shan w = &hose->mem_resources[0]; 326640e2a47eSGavin Shan msi_region = true; 326740e2a47eSGavin Shan } 326840e2a47eSGavin Shan 326940e2a47eSGavin Shan r->start = w->start; 327040e2a47eSGavin Shan r->end = w->end; 327140e2a47eSGavin Shan 327240e2a47eSGavin Shan /* The 64KB 32-bits MSI region shouldn't be included in 327340e2a47eSGavin Shan * the 32-bits bridge window. Otherwise, we can see strange 327440e2a47eSGavin Shan * issues. One of them is EEH error observed on Garrison. 327540e2a47eSGavin Shan * 327640e2a47eSGavin Shan * Exclude top 1MB region which is the minimal alignment of 327740e2a47eSGavin Shan * 32-bits bridge window. 327840e2a47eSGavin Shan */ 327940e2a47eSGavin Shan if (msi_region) { 328040e2a47eSGavin Shan r->end += 0x10000; 328140e2a47eSGavin Shan r->end -= 0x100000; 328240e2a47eSGavin Shan } 328340e2a47eSGavin Shan } 328440e2a47eSGavin Shan } 328540e2a47eSGavin Shan 3286ccd1c191SGavin Shan static void pnv_pci_setup_bridge(struct pci_bus *bus, unsigned long type) 3287ccd1c191SGavin Shan { 3288ccd1c191SGavin Shan struct pci_controller *hose = pci_bus_to_host(bus); 3289ccd1c191SGavin Shan struct pnv_phb *phb = hose->private_data; 3290ccd1c191SGavin Shan struct pci_dev *bridge = bus->self; 3291ccd1c191SGavin Shan struct pnv_ioda_pe *pe; 3292ccd1c191SGavin Shan bool all = (pci_pcie_type(bridge) == PCI_EXP_TYPE_PCI_BRIDGE); 3293ccd1c191SGavin Shan 329440e2a47eSGavin Shan /* Extend bridge's windows if necessary */ 329540e2a47eSGavin Shan pnv_pci_fixup_bridge_resources(bus, type); 329640e2a47eSGavin Shan 329763803c39SGavin Shan /* The PE for root bus should be realized before any one else */ 329863803c39SGavin Shan if (!phb->ioda.root_pe_populated) { 329963803c39SGavin Shan pe = pnv_ioda_setup_bus_PE(phb->hose->bus, false); 330063803c39SGavin Shan if (pe) { 330163803c39SGavin Shan phb->ioda.root_pe_idx = pe->pe_number; 330263803c39SGavin Shan phb->ioda.root_pe_populated = true; 330363803c39SGavin Shan } 330463803c39SGavin Shan } 330563803c39SGavin Shan 3306ccd1c191SGavin Shan /* Don't assign PE to PCI bus, which doesn't have subordinate devices */ 3307ccd1c191SGavin Shan if (list_empty(&bus->devices)) 3308ccd1c191SGavin Shan return; 3309ccd1c191SGavin Shan 3310ccd1c191SGavin Shan /* Reserve PEs according to used M64 resources */ 3311ccd1c191SGavin Shan if (phb->reserve_m64_pe) 3312ccd1c191SGavin Shan phb->reserve_m64_pe(bus, NULL, all); 3313ccd1c191SGavin Shan 3314ccd1c191SGavin Shan /* 3315ccd1c191SGavin Shan * Assign PE. We might run here because of partial hotplug. 3316ccd1c191SGavin Shan * For the case, we just pick up the existing PE and should 3317ccd1c191SGavin Shan * not allocate resources again. 3318ccd1c191SGavin Shan */ 3319ccd1c191SGavin Shan pe = pnv_ioda_setup_bus_PE(bus, all); 3320ccd1c191SGavin Shan if (!pe) 3321ccd1c191SGavin Shan return; 3322ccd1c191SGavin Shan 3323ccd1c191SGavin Shan pnv_ioda_setup_pe_seg(pe); 3324ccd1c191SGavin Shan switch (phb->type) { 3325ccd1c191SGavin Shan case PNV_PHB_IODA1: 3326ccd1c191SGavin Shan pnv_pci_ioda1_setup_dma_pe(phb, pe); 3327ccd1c191SGavin Shan break; 3328ccd1c191SGavin Shan case PNV_PHB_IODA2: 3329ccd1c191SGavin Shan pnv_pci_ioda2_setup_dma_pe(phb, pe); 3330ccd1c191SGavin Shan break; 3331ccd1c191SGavin Shan default: 3332ccd1c191SGavin Shan pr_warn("%s: No DMA for PHB#%d (type %d)\n", 3333ccd1c191SGavin Shan __func__, phb->hose->global_number, phb->type); 3334ccd1c191SGavin Shan } 3335ccd1c191SGavin Shan } 3336ccd1c191SGavin Shan 33375350ab3fSWei Yang #ifdef CONFIG_PCI_IOV 33385350ab3fSWei Yang static resource_size_t pnv_pci_iov_resource_alignment(struct pci_dev *pdev, 33395350ab3fSWei Yang int resno) 33405350ab3fSWei Yang { 3341ee8222feSWei Yang struct pci_controller *hose = pci_bus_to_host(pdev->bus); 3342ee8222feSWei Yang struct pnv_phb *phb = hose->private_data; 33435350ab3fSWei Yang struct pci_dn *pdn = pci_get_pdn(pdev); 33447fbe7a93SWei Yang resource_size_t align; 33455350ab3fSWei Yang 33467fbe7a93SWei Yang /* 33477fbe7a93SWei Yang * On PowerNV platform, IOV BAR is mapped by M64 BAR to enable the 33487fbe7a93SWei Yang * SR-IOV. While from hardware perspective, the range mapped by M64 33497fbe7a93SWei Yang * BAR should be size aligned. 33507fbe7a93SWei Yang * 3351ee8222feSWei Yang * When IOV BAR is mapped with M64 BAR in Single PE mode, the extra 3352ee8222feSWei Yang * powernv-specific hardware restriction is gone. But if just use the 3353ee8222feSWei Yang * VF BAR size as the alignment, PF BAR / VF BAR may be allocated with 3354ee8222feSWei Yang * in one segment of M64 #15, which introduces the PE conflict between 3355ee8222feSWei Yang * PF and VF. Based on this, the minimum alignment of an IOV BAR is 3356ee8222feSWei Yang * m64_segsize. 3357ee8222feSWei Yang * 33587fbe7a93SWei Yang * This function returns the total IOV BAR size if M64 BAR is in 33597fbe7a93SWei Yang * Shared PE mode or just VF BAR size if not. 3360ee8222feSWei Yang * If the M64 BAR is in Single PE mode, return the VF BAR size or 3361ee8222feSWei Yang * M64 segment size if IOV BAR size is less. 33627fbe7a93SWei Yang */ 33635350ab3fSWei Yang align = pci_iov_resource_size(pdev, resno); 33647fbe7a93SWei Yang if (!pdn->vfs_expanded) 33655350ab3fSWei Yang return align; 3366ee8222feSWei Yang if (pdn->m64_single_mode) 3367ee8222feSWei Yang return max(align, (resource_size_t)phb->ioda.m64_segsize); 33687fbe7a93SWei Yang 33697fbe7a93SWei Yang return pdn->vfs_expanded * align; 33705350ab3fSWei Yang } 33715350ab3fSWei Yang #endif /* CONFIG_PCI_IOV */ 33725350ab3fSWei Yang 3373184cd4a3SBenjamin Herrenschmidt /* Prevent enabling devices for which we couldn't properly 3374184cd4a3SBenjamin Herrenschmidt * assign a PE 3375184cd4a3SBenjamin Herrenschmidt */ 3376c88c2a18SDaniel Axtens static bool pnv_pci_enable_device_hook(struct pci_dev *dev) 3377184cd4a3SBenjamin Herrenschmidt { 3378db1266c8SGavin Shan struct pci_controller *hose = pci_bus_to_host(dev->bus); 3379db1266c8SGavin Shan struct pnv_phb *phb = hose->private_data; 3380db1266c8SGavin Shan struct pci_dn *pdn; 3381184cd4a3SBenjamin Herrenschmidt 3382db1266c8SGavin Shan /* The function is probably called while the PEs have 3383db1266c8SGavin Shan * not be created yet. For example, resource reassignment 3384db1266c8SGavin Shan * during PCI probe period. We just skip the check if 3385db1266c8SGavin Shan * PEs isn't ready. 3386db1266c8SGavin Shan */ 3387db1266c8SGavin Shan if (!phb->initialized) 3388c88c2a18SDaniel Axtens return true; 3389db1266c8SGavin Shan 3390b72c1f65SBenjamin Herrenschmidt pdn = pci_get_pdn(dev); 3391184cd4a3SBenjamin Herrenschmidt if (!pdn || pdn->pe_number == IODA_INVALID_PE) 3392c88c2a18SDaniel Axtens return false; 3393db1266c8SGavin Shan 3394c88c2a18SDaniel Axtens return true; 3395184cd4a3SBenjamin Herrenschmidt } 3396184cd4a3SBenjamin Herrenschmidt 33977a8e6bbfSMichael Neuling static void pnv_pci_ioda_shutdown(struct pci_controller *hose) 339873ed148aSBenjamin Herrenschmidt { 33997a8e6bbfSMichael Neuling struct pnv_phb *phb = hose->private_data; 34007a8e6bbfSMichael Neuling 3401d1a85eeeSGavin Shan opal_pci_reset(phb->opal_id, OPAL_RESET_PCI_IODA_TABLE, 340273ed148aSBenjamin Herrenschmidt OPAL_ASSERT_RESET); 340373ed148aSBenjamin Herrenschmidt } 340473ed148aSBenjamin Herrenschmidt 340592ae0353SDaniel Axtens static const struct pci_controller_ops pnv_pci_ioda_controller_ops = { 340692ae0353SDaniel Axtens .dma_dev_setup = pnv_pci_dma_dev_setup, 34071bc74f1cSGavin Shan .dma_bus_setup = pnv_pci_dma_bus_setup, 340892ae0353SDaniel Axtens #ifdef CONFIG_PCI_MSI 340992ae0353SDaniel Axtens .setup_msi_irqs = pnv_setup_msi_irqs, 341092ae0353SDaniel Axtens .teardown_msi_irqs = pnv_teardown_msi_irqs, 341192ae0353SDaniel Axtens #endif 341292ae0353SDaniel Axtens .enable_device_hook = pnv_pci_enable_device_hook, 341392ae0353SDaniel Axtens .window_alignment = pnv_pci_window_alignment, 3414ccd1c191SGavin Shan .setup_bridge = pnv_pci_setup_bridge, 341592ae0353SDaniel Axtens .reset_secondary_bus = pnv_pci_reset_secondary_bus, 3416763d2d8dSDaniel Axtens .dma_set_mask = pnv_pci_ioda_dma_set_mask, 341753522982SAndrew Donnellan .dma_get_required_mask = pnv_pci_ioda_dma_get_required_mask, 34187a8e6bbfSMichael Neuling .shutdown = pnv_pci_ioda_shutdown, 341992ae0353SDaniel Axtens }; 342092ae0353SDaniel Axtens 3421f9f83456SAlexey Kardashevskiy static int pnv_npu_dma_set_mask(struct pci_dev *npdev, u64 dma_mask) 3422f9f83456SAlexey Kardashevskiy { 3423f9f83456SAlexey Kardashevskiy dev_err_once(&npdev->dev, 3424f9f83456SAlexey Kardashevskiy "%s operation unsupported for NVLink devices\n", 3425f9f83456SAlexey Kardashevskiy __func__); 3426f9f83456SAlexey Kardashevskiy return -EPERM; 3427f9f83456SAlexey Kardashevskiy } 3428f9f83456SAlexey Kardashevskiy 34295d2aa710SAlistair Popple static const struct pci_controller_ops pnv_npu_ioda_controller_ops = { 34305d2aa710SAlistair Popple .dma_dev_setup = pnv_pci_dma_dev_setup, 34315d2aa710SAlistair Popple #ifdef CONFIG_PCI_MSI 34325d2aa710SAlistair Popple .setup_msi_irqs = pnv_setup_msi_irqs, 34335d2aa710SAlistair Popple .teardown_msi_irqs = pnv_teardown_msi_irqs, 34345d2aa710SAlistair Popple #endif 34355d2aa710SAlistair Popple .enable_device_hook = pnv_pci_enable_device_hook, 34365d2aa710SAlistair Popple .window_alignment = pnv_pci_window_alignment, 34375d2aa710SAlistair Popple .reset_secondary_bus = pnv_pci_reset_secondary_bus, 34385d2aa710SAlistair Popple .dma_set_mask = pnv_npu_dma_set_mask, 34395d2aa710SAlistair Popple .shutdown = pnv_pci_ioda_shutdown, 34405d2aa710SAlistair Popple }; 34415d2aa710SAlistair Popple 3442e51df2c1SAnton Blanchard static void __init pnv_pci_init_ioda_phb(struct device_node *np, 3443e9cc17d4SGavin Shan u64 hub_id, int ioda_type) 3444184cd4a3SBenjamin Herrenschmidt { 3445184cd4a3SBenjamin Herrenschmidt struct pci_controller *hose; 3446184cd4a3SBenjamin Herrenschmidt struct pnv_phb *phb; 34472b923ed1SGavin Shan unsigned long size, m64map_off, m32map_off, pemap_off; 34482b923ed1SGavin Shan unsigned long iomap_off = 0, dma32map_off = 0; 3449c681b93cSAlistair Popple const __be64 *prop64; 34503a1a4661SBenjamin Herrenschmidt const __be32 *prop32; 3451f1b7cc3eSGavin Shan int len; 34523fa23ff8SGavin Shan unsigned int segno; 3453184cd4a3SBenjamin Herrenschmidt u64 phb_id; 3454184cd4a3SBenjamin Herrenschmidt void *aux; 3455184cd4a3SBenjamin Herrenschmidt long rc; 3456184cd4a3SBenjamin Herrenschmidt 3457aa0c033fSGavin Shan pr_info("Initializing IODA%d OPAL PHB %s\n", ioda_type, np->full_name); 3458184cd4a3SBenjamin Herrenschmidt 3459184cd4a3SBenjamin Herrenschmidt prop64 = of_get_property(np, "ibm,opal-phbid", NULL); 3460184cd4a3SBenjamin Herrenschmidt if (!prop64) { 3461184cd4a3SBenjamin Herrenschmidt pr_err(" Missing \"ibm,opal-phbid\" property !\n"); 3462184cd4a3SBenjamin Herrenschmidt return; 3463184cd4a3SBenjamin Herrenschmidt } 3464184cd4a3SBenjamin Herrenschmidt phb_id = be64_to_cpup(prop64); 3465184cd4a3SBenjamin Herrenschmidt pr_debug(" PHB-ID : 0x%016llx\n", phb_id); 3466184cd4a3SBenjamin Herrenschmidt 3467e39f223fSMichael Ellerman phb = memblock_virt_alloc(sizeof(struct pnv_phb), 0); 346858d714ecSGavin Shan 346958d714ecSGavin Shan /* Allocate PCI controller */ 3470184cd4a3SBenjamin Herrenschmidt phb->hose = hose = pcibios_alloc_controller(np); 347158d714ecSGavin Shan if (!phb->hose) { 347258d714ecSGavin Shan pr_err(" Can't allocate PCI controller for %s\n", 3473184cd4a3SBenjamin Herrenschmidt np->full_name); 3474e39f223fSMichael Ellerman memblock_free(__pa(phb), sizeof(struct pnv_phb)); 3475184cd4a3SBenjamin Herrenschmidt return; 3476184cd4a3SBenjamin Herrenschmidt } 3477184cd4a3SBenjamin Herrenschmidt 3478184cd4a3SBenjamin Herrenschmidt spin_lock_init(&phb->lock); 3479f1b7cc3eSGavin Shan prop32 = of_get_property(np, "bus-range", &len); 3480f1b7cc3eSGavin Shan if (prop32 && len == 8) { 34813a1a4661SBenjamin Herrenschmidt hose->first_busno = be32_to_cpu(prop32[0]); 34823a1a4661SBenjamin Herrenschmidt hose->last_busno = be32_to_cpu(prop32[1]); 3483f1b7cc3eSGavin Shan } else { 3484f1b7cc3eSGavin Shan pr_warn(" Broken <bus-range> on %s\n", np->full_name); 3485184cd4a3SBenjamin Herrenschmidt hose->first_busno = 0; 3486184cd4a3SBenjamin Herrenschmidt hose->last_busno = 0xff; 3487f1b7cc3eSGavin Shan } 3488184cd4a3SBenjamin Herrenschmidt hose->private_data = phb; 3489e9cc17d4SGavin Shan phb->hub_id = hub_id; 3490184cd4a3SBenjamin Herrenschmidt phb->opal_id = phb_id; 3491aa0c033fSGavin Shan phb->type = ioda_type; 3492781a868fSWei Yang mutex_init(&phb->ioda.pe_alloc_mutex); 3493184cd4a3SBenjamin Herrenschmidt 3494cee72d5bSBenjamin Herrenschmidt /* Detect specific models for error handling */ 3495cee72d5bSBenjamin Herrenschmidt if (of_device_is_compatible(np, "ibm,p7ioc-pciex")) 3496cee72d5bSBenjamin Herrenschmidt phb->model = PNV_PHB_MODEL_P7IOC; 3497f3d40c25SBenjamin Herrenschmidt else if (of_device_is_compatible(np, "ibm,power8-pciex")) 3498aa0c033fSGavin Shan phb->model = PNV_PHB_MODEL_PHB3; 34995d2aa710SAlistair Popple else if (of_device_is_compatible(np, "ibm,power8-npu-pciex")) 35005d2aa710SAlistair Popple phb->model = PNV_PHB_MODEL_NPU; 3501cee72d5bSBenjamin Herrenschmidt else 3502cee72d5bSBenjamin Herrenschmidt phb->model = PNV_PHB_MODEL_UNKNOWN; 3503cee72d5bSBenjamin Herrenschmidt 3504aa0c033fSGavin Shan /* Parse 32-bit and IO ranges (if any) */ 35052f1ec02eSGavin Shan pci_process_bridge_OF_ranges(hose, np, !hose->global_number); 3506184cd4a3SBenjamin Herrenschmidt 3507aa0c033fSGavin Shan /* Get registers */ 3508184cd4a3SBenjamin Herrenschmidt phb->regs = of_iomap(np, 0); 3509184cd4a3SBenjamin Herrenschmidt if (phb->regs == NULL) 3510184cd4a3SBenjamin Herrenschmidt pr_err(" Failed to map registers !\n"); 3511184cd4a3SBenjamin Herrenschmidt 3512577c8c88SGavin Shan /* Initialize TCE kill register */ 3513577c8c88SGavin Shan pnv_pci_ioda_setup_opal_tce_kill(phb); 3514577c8c88SGavin Shan 3515184cd4a3SBenjamin Herrenschmidt /* Initialize more IODA stuff */ 351692b8f137SGavin Shan phb->ioda.total_pe_num = 1; 351736954dc7SGavin Shan prop32 = of_get_property(np, "ibm,opal-num-pes", NULL); 351836954dc7SGavin Shan if (prop32) 351992b8f137SGavin Shan phb->ioda.total_pe_num = be32_to_cpup(prop32); 352036954dc7SGavin Shan prop32 = of_get_property(np, "ibm,opal-reserved-pe", NULL); 352136954dc7SGavin Shan if (prop32) 352292b8f137SGavin Shan phb->ioda.reserved_pe_idx = be32_to_cpup(prop32); 3523262af557SGuo Chao 3524c127562aSGavin Shan /* Invalidate RID to PE# mapping */ 3525c127562aSGavin Shan for (segno = 0; segno < ARRAY_SIZE(phb->ioda.pe_rmap); segno++) 3526c127562aSGavin Shan phb->ioda.pe_rmap[segno] = IODA_INVALID_PE; 3527c127562aSGavin Shan 3528262af557SGuo Chao /* Parse 64-bit MMIO range */ 3529262af557SGuo Chao pnv_ioda_parse_m64_window(phb); 3530262af557SGuo Chao 3531184cd4a3SBenjamin Herrenschmidt phb->ioda.m32_size = resource_size(&hose->mem_resources[0]); 3532aa0c033fSGavin Shan /* FW Has already off top 64k of M32 space (MSI space) */ 3533184cd4a3SBenjamin Herrenschmidt phb->ioda.m32_size += 0x10000; 3534184cd4a3SBenjamin Herrenschmidt 353592b8f137SGavin Shan phb->ioda.m32_segsize = phb->ioda.m32_size / phb->ioda.total_pe_num; 35363fd47f06SBenjamin Herrenschmidt phb->ioda.m32_pci_base = hose->mem_resources[0].start - hose->mem_offset[0]; 3537184cd4a3SBenjamin Herrenschmidt phb->ioda.io_size = hose->pci_io_size; 353892b8f137SGavin Shan phb->ioda.io_segsize = phb->ioda.io_size / phb->ioda.total_pe_num; 3539184cd4a3SBenjamin Herrenschmidt phb->ioda.io_pci_base = 0; /* XXX calculate this ? */ 3540184cd4a3SBenjamin Herrenschmidt 35412b923ed1SGavin Shan /* Calculate how many 32-bit TCE segments we have */ 35422b923ed1SGavin Shan phb->ioda.dma32_count = phb->ioda.m32_pci_base / 35432b923ed1SGavin Shan PNV_IODA1_DMA32_SEGSIZE; 35442b923ed1SGavin Shan 3545c35d2a8cSGavin Shan /* Allocate aux data & arrays. We don't have IO ports on PHB3 */ 354692a86756SAlexey Kardashevskiy size = _ALIGN_UP(max_t(unsigned, phb->ioda.total_pe_num, 8) / 8, 354792a86756SAlexey Kardashevskiy sizeof(unsigned long)); 354893289d8cSGavin Shan m64map_off = size; 354993289d8cSGavin Shan size += phb->ioda.total_pe_num * sizeof(phb->ioda.m64_segmap[0]); 3550184cd4a3SBenjamin Herrenschmidt m32map_off = size; 355192b8f137SGavin Shan size += phb->ioda.total_pe_num * sizeof(phb->ioda.m32_segmap[0]); 3552c35d2a8cSGavin Shan if (phb->type == PNV_PHB_IODA1) { 3553c35d2a8cSGavin Shan iomap_off = size; 355492b8f137SGavin Shan size += phb->ioda.total_pe_num * sizeof(phb->ioda.io_segmap[0]); 35552b923ed1SGavin Shan dma32map_off = size; 35562b923ed1SGavin Shan size += phb->ioda.dma32_count * 35572b923ed1SGavin Shan sizeof(phb->ioda.dma32_segmap[0]); 3558c35d2a8cSGavin Shan } 3559184cd4a3SBenjamin Herrenschmidt pemap_off = size; 356092b8f137SGavin Shan size += phb->ioda.total_pe_num * sizeof(struct pnv_ioda_pe); 3561e39f223fSMichael Ellerman aux = memblock_virt_alloc(size, 0); 3562184cd4a3SBenjamin Herrenschmidt phb->ioda.pe_alloc = aux; 356393289d8cSGavin Shan phb->ioda.m64_segmap = aux + m64map_off; 3564184cd4a3SBenjamin Herrenschmidt phb->ioda.m32_segmap = aux + m32map_off; 356593289d8cSGavin Shan for (segno = 0; segno < phb->ioda.total_pe_num; segno++) { 356693289d8cSGavin Shan phb->ioda.m64_segmap[segno] = IODA_INVALID_PE; 35673fa23ff8SGavin Shan phb->ioda.m32_segmap[segno] = IODA_INVALID_PE; 356893289d8cSGavin Shan } 35693fa23ff8SGavin Shan if (phb->type == PNV_PHB_IODA1) { 3570184cd4a3SBenjamin Herrenschmidt phb->ioda.io_segmap = aux + iomap_off; 35713fa23ff8SGavin Shan for (segno = 0; segno < phb->ioda.total_pe_num; segno++) 35723fa23ff8SGavin Shan phb->ioda.io_segmap[segno] = IODA_INVALID_PE; 35732b923ed1SGavin Shan 35742b923ed1SGavin Shan phb->ioda.dma32_segmap = aux + dma32map_off; 35752b923ed1SGavin Shan for (segno = 0; segno < phb->ioda.dma32_count; segno++) 35762b923ed1SGavin Shan phb->ioda.dma32_segmap[segno] = IODA_INVALID_PE; 35773fa23ff8SGavin Shan } 3578184cd4a3SBenjamin Herrenschmidt phb->ioda.pe_array = aux + pemap_off; 357963803c39SGavin Shan 358063803c39SGavin Shan /* 358163803c39SGavin Shan * Choose PE number for root bus, which shouldn't have 358263803c39SGavin Shan * M64 resources consumed by its child devices. To pick 358363803c39SGavin Shan * the PE number adjacent to the reserved one if possible. 358463803c39SGavin Shan */ 358563803c39SGavin Shan pnv_ioda_reserve_pe(phb, phb->ioda.reserved_pe_idx); 358663803c39SGavin Shan if (phb->ioda.reserved_pe_idx == 0) { 358763803c39SGavin Shan phb->ioda.root_pe_idx = 1; 358863803c39SGavin Shan pnv_ioda_reserve_pe(phb, phb->ioda.root_pe_idx); 358963803c39SGavin Shan } else if (phb->ioda.reserved_pe_idx == (phb->ioda.total_pe_num - 1)) { 359063803c39SGavin Shan phb->ioda.root_pe_idx = phb->ioda.reserved_pe_idx - 1; 359163803c39SGavin Shan pnv_ioda_reserve_pe(phb, phb->ioda.root_pe_idx); 359263803c39SGavin Shan } else { 359363803c39SGavin Shan phb->ioda.root_pe_idx = IODA_INVALID_PE; 359463803c39SGavin Shan } 3595184cd4a3SBenjamin Herrenschmidt 3596184cd4a3SBenjamin Herrenschmidt INIT_LIST_HEAD(&phb->ioda.pe_list); 3597781a868fSWei Yang mutex_init(&phb->ioda.pe_list_mutex); 3598184cd4a3SBenjamin Herrenschmidt 3599184cd4a3SBenjamin Herrenschmidt /* Calculate how many 32-bit TCE segments we have */ 36002b923ed1SGavin Shan phb->ioda.dma32_count = phb->ioda.m32_pci_base / 3601acce971cSGavin Shan PNV_IODA1_DMA32_SEGSIZE; 3602184cd4a3SBenjamin Herrenschmidt 3603aa0c033fSGavin Shan #if 0 /* We should really do that ... */ 3604184cd4a3SBenjamin Herrenschmidt rc = opal_pci_set_phb_mem_window(opal->phb_id, 3605184cd4a3SBenjamin Herrenschmidt window_type, 3606184cd4a3SBenjamin Herrenschmidt window_num, 3607184cd4a3SBenjamin Herrenschmidt starting_real_address, 3608184cd4a3SBenjamin Herrenschmidt starting_pci_address, 3609184cd4a3SBenjamin Herrenschmidt segment_size); 3610184cd4a3SBenjamin Herrenschmidt #endif 3611184cd4a3SBenjamin Herrenschmidt 3612262af557SGuo Chao pr_info(" %03d (%03d) PE's M32: 0x%x [segment=0x%x]\n", 361392b8f137SGavin Shan phb->ioda.total_pe_num, phb->ioda.reserved_pe_idx, 3614262af557SGuo Chao phb->ioda.m32_size, phb->ioda.m32_segsize); 3615262af557SGuo Chao if (phb->ioda.m64_size) 3616262af557SGuo Chao pr_info(" M64: 0x%lx [segment=0x%lx]\n", 3617262af557SGuo Chao phb->ioda.m64_size, phb->ioda.m64_segsize); 3618262af557SGuo Chao if (phb->ioda.io_size) 3619262af557SGuo Chao pr_info(" IO: 0x%x [segment=0x%x]\n", 3620184cd4a3SBenjamin Herrenschmidt phb->ioda.io_size, phb->ioda.io_segsize); 3621184cd4a3SBenjamin Herrenschmidt 3622262af557SGuo Chao 3623184cd4a3SBenjamin Herrenschmidt phb->hose->ops = &pnv_pci_ops; 362449dec922SGavin Shan phb->get_pe_state = pnv_ioda_get_pe_state; 362549dec922SGavin Shan phb->freeze_pe = pnv_ioda_freeze_pe; 362649dec922SGavin Shan phb->unfreeze_pe = pnv_ioda_unfreeze_pe; 3627184cd4a3SBenjamin Herrenschmidt 3628184cd4a3SBenjamin Herrenschmidt /* Setup MSI support */ 3629184cd4a3SBenjamin Herrenschmidt pnv_pci_init_ioda_msis(phb); 3630184cd4a3SBenjamin Herrenschmidt 3631c40a4210SGavin Shan /* 3632c40a4210SGavin Shan * We pass the PCI probe flag PCI_REASSIGN_ALL_RSRC here 3633c40a4210SGavin Shan * to let the PCI core do resource assignment. It's supposed 3634c40a4210SGavin Shan * that the PCI core will do correct I/O and MMIO alignment 3635c40a4210SGavin Shan * for the P2P bridge bars so that each PCI bus (excluding 3636c40a4210SGavin Shan * the child P2P bridges) can form individual PE. 3637184cd4a3SBenjamin Herrenschmidt */ 3638fb446ad0SGavin Shan ppc_md.pcibios_fixup = pnv_pci_ioda_fixup; 36395d2aa710SAlistair Popple 3640f9f83456SAlexey Kardashevskiy if (phb->type == PNV_PHB_NPU) { 36415d2aa710SAlistair Popple hose->controller_ops = pnv_npu_ioda_controller_ops; 3642f9f83456SAlexey Kardashevskiy } else { 3643f9f83456SAlexey Kardashevskiy phb->dma_dev_setup = pnv_pci_ioda_dma_dev_setup; 364492ae0353SDaniel Axtens hose->controller_ops = pnv_pci_ioda_controller_ops; 3645f9f83456SAlexey Kardashevskiy } 3646ad30cb99SMichael Ellerman 36476e628c7dSWei Yang #ifdef CONFIG_PCI_IOV 36486e628c7dSWei Yang ppc_md.pcibios_fixup_sriov = pnv_pci_ioda_fixup_iov_resources; 36495350ab3fSWei Yang ppc_md.pcibios_iov_resource_alignment = pnv_pci_iov_resource_alignment; 3650ad30cb99SMichael Ellerman #endif 3651ad30cb99SMichael Ellerman 3652c40a4210SGavin Shan pci_add_flags(PCI_REASSIGN_ALL_RSRC); 3653184cd4a3SBenjamin Herrenschmidt 3654184cd4a3SBenjamin Herrenschmidt /* Reset IODA tables to a clean state */ 3655d1a85eeeSGavin Shan rc = opal_pci_reset(phb_id, OPAL_RESET_PCI_IODA_TABLE, OPAL_ASSERT_RESET); 3656184cd4a3SBenjamin Herrenschmidt if (rc) 3657f11fe552SBenjamin Herrenschmidt pr_warning(" OPAL Error %ld performing IODA table reset !\n", rc); 3658361f2a2aSGavin Shan 3659361f2a2aSGavin Shan /* If we're running in kdump kerenl, the previous kerenl never 3660361f2a2aSGavin Shan * shutdown PCI devices correctly. We already got IODA table 3661361f2a2aSGavin Shan * cleaned out. So we have to issue PHB reset to stop all PCI 3662361f2a2aSGavin Shan * transactions from previous kerenl. 3663361f2a2aSGavin Shan */ 3664361f2a2aSGavin Shan if (is_kdump_kernel()) { 3665361f2a2aSGavin Shan pr_info(" Issue PHB reset ...\n"); 3666cadf364dSGavin Shan pnv_eeh_phb_reset(hose, EEH_RESET_FUNDAMENTAL); 3667cadf364dSGavin Shan pnv_eeh_phb_reset(hose, EEH_RESET_DEACTIVATE); 3668361f2a2aSGavin Shan } 3669262af557SGuo Chao 36709e9e8935SGavin Shan /* Remove M64 resource if we can't configure it successfully */ 36719e9e8935SGavin Shan if (!phb->init_m64 || phb->init_m64(phb)) 3672262af557SGuo Chao hose->mem_resources[1].flags = 0; 3673184cd4a3SBenjamin Herrenschmidt } 3674184cd4a3SBenjamin Herrenschmidt 367567975005SBjorn Helgaas void __init pnv_pci_init_ioda2_phb(struct device_node *np) 3676aa0c033fSGavin Shan { 3677e9cc17d4SGavin Shan pnv_pci_init_ioda_phb(np, 0, PNV_PHB_IODA2); 3678aa0c033fSGavin Shan } 3679aa0c033fSGavin Shan 36805d2aa710SAlistair Popple void __init pnv_pci_init_npu_phb(struct device_node *np) 36815d2aa710SAlistair Popple { 36825d2aa710SAlistair Popple pnv_pci_init_ioda_phb(np, 0, PNV_PHB_NPU); 36835d2aa710SAlistair Popple } 36845d2aa710SAlistair Popple 3685184cd4a3SBenjamin Herrenschmidt void __init pnv_pci_init_ioda_hub(struct device_node *np) 3686184cd4a3SBenjamin Herrenschmidt { 3687184cd4a3SBenjamin Herrenschmidt struct device_node *phbn; 3688c681b93cSAlistair Popple const __be64 *prop64; 3689184cd4a3SBenjamin Herrenschmidt u64 hub_id; 3690184cd4a3SBenjamin Herrenschmidt 3691184cd4a3SBenjamin Herrenschmidt pr_info("Probing IODA IO-Hub %s\n", np->full_name); 3692184cd4a3SBenjamin Herrenschmidt 3693184cd4a3SBenjamin Herrenschmidt prop64 = of_get_property(np, "ibm,opal-hubid", NULL); 3694184cd4a3SBenjamin Herrenschmidt if (!prop64) { 3695184cd4a3SBenjamin Herrenschmidt pr_err(" Missing \"ibm,opal-hubid\" property !\n"); 3696184cd4a3SBenjamin Herrenschmidt return; 3697184cd4a3SBenjamin Herrenschmidt } 3698184cd4a3SBenjamin Herrenschmidt hub_id = be64_to_cpup(prop64); 3699184cd4a3SBenjamin Herrenschmidt pr_devel(" HUB-ID : 0x%016llx\n", hub_id); 3700184cd4a3SBenjamin Herrenschmidt 3701184cd4a3SBenjamin Herrenschmidt /* Count child PHBs */ 3702184cd4a3SBenjamin Herrenschmidt for_each_child_of_node(np, phbn) { 3703184cd4a3SBenjamin Herrenschmidt /* Look for IODA1 PHBs */ 3704184cd4a3SBenjamin Herrenschmidt if (of_device_is_compatible(phbn, "ibm,ioda-phb")) 3705e9cc17d4SGavin Shan pnv_pci_init_ioda_phb(phbn, hub_id, PNV_PHB_IODA1); 3706184cd4a3SBenjamin Herrenschmidt } 3707184cd4a3SBenjamin Herrenschmidt } 3708