1184cd4a3SBenjamin Herrenschmidt /* 2184cd4a3SBenjamin Herrenschmidt * Support PCI/PCIe on PowerNV platforms 3184cd4a3SBenjamin Herrenschmidt * 4184cd4a3SBenjamin Herrenschmidt * Copyright 2011 Benjamin Herrenschmidt, IBM Corp. 5184cd4a3SBenjamin Herrenschmidt * 6184cd4a3SBenjamin Herrenschmidt * This program is free software; you can redistribute it and/or 7184cd4a3SBenjamin Herrenschmidt * modify it under the terms of the GNU General Public License 8184cd4a3SBenjamin Herrenschmidt * as published by the Free Software Foundation; either version 9184cd4a3SBenjamin Herrenschmidt * 2 of the License, or (at your option) any later version. 10184cd4a3SBenjamin Herrenschmidt */ 11184cd4a3SBenjamin Herrenschmidt 12cee72d5bSBenjamin Herrenschmidt #undef DEBUG 13184cd4a3SBenjamin Herrenschmidt 14184cd4a3SBenjamin Herrenschmidt #include <linux/kernel.h> 15184cd4a3SBenjamin Herrenschmidt #include <linux/pci.h> 16361f2a2aSGavin Shan #include <linux/crash_dump.h> 1737c367f2SGavin Shan #include <linux/debugfs.h> 18184cd4a3SBenjamin Herrenschmidt #include <linux/delay.h> 19184cd4a3SBenjamin Herrenschmidt #include <linux/string.h> 20184cd4a3SBenjamin Herrenschmidt #include <linux/init.h> 21184cd4a3SBenjamin Herrenschmidt #include <linux/bootmem.h> 22184cd4a3SBenjamin Herrenschmidt #include <linux/irq.h> 23184cd4a3SBenjamin Herrenschmidt #include <linux/io.h> 24184cd4a3SBenjamin Herrenschmidt #include <linux/msi.h> 25cd15b048SBenjamin Herrenschmidt #include <linux/memblock.h> 26ac9a5889SAlexey Kardashevskiy #include <linux/iommu.h> 27e57080f1SAlexey Kardashevskiy #include <linux/rculist.h> 284793d65dSAlexey Kardashevskiy #include <linux/sizes.h> 29184cd4a3SBenjamin Herrenschmidt 30184cd4a3SBenjamin Herrenschmidt #include <asm/sections.h> 31184cd4a3SBenjamin Herrenschmidt #include <asm/io.h> 32184cd4a3SBenjamin Herrenschmidt #include <asm/prom.h> 33184cd4a3SBenjamin Herrenschmidt #include <asm/pci-bridge.h> 34184cd4a3SBenjamin Herrenschmidt #include <asm/machdep.h> 35fb1b55d6SGavin Shan #include <asm/msi_bitmap.h> 36184cd4a3SBenjamin Herrenschmidt #include <asm/ppc-pci.h> 37184cd4a3SBenjamin Herrenschmidt #include <asm/opal.h> 38184cd4a3SBenjamin Herrenschmidt #include <asm/iommu.h> 39184cd4a3SBenjamin Herrenschmidt #include <asm/tce.h> 40137436c9SGavin Shan #include <asm/xics.h> 4137c367f2SGavin Shan #include <asm/debug.h> 42262af557SGuo Chao #include <asm/firmware.h> 4380c49c7eSIan Munsie #include <asm/pnv-pci.h> 44aca6913fSAlexey Kardashevskiy #include <asm/mmzone.h> 4580c49c7eSIan Munsie 46ec249dd8SMichael Neuling #include <misc/cxl-base.h> 47184cd4a3SBenjamin Herrenschmidt 48184cd4a3SBenjamin Herrenschmidt #include "powernv.h" 49184cd4a3SBenjamin Herrenschmidt #include "pci.h" 50184cd4a3SBenjamin Herrenschmidt 51781a868fSWei Yang /* 256M DMA window, 4K TCE pages, 8 bytes TCE */ 52781a868fSWei Yang #define TCE32_TABLE_SIZE ((0x10000000 / 0x1000) * 8) 53781a868fSWei Yang 54bbb845c4SAlexey Kardashevskiy #define POWERNV_IOMMU_DEFAULT_LEVELS 1 55bbb845c4SAlexey Kardashevskiy #define POWERNV_IOMMU_MAX_LEVELS 5 56bbb845c4SAlexey Kardashevskiy 57aca6913fSAlexey Kardashevskiy static void pnv_pci_ioda2_table_free_pages(struct iommu_table *tbl); 58aca6913fSAlexey Kardashevskiy 596d31c2faSJoe Perches static void pe_level_printk(const struct pnv_ioda_pe *pe, const char *level, 606d31c2faSJoe Perches const char *fmt, ...) 616d31c2faSJoe Perches { 626d31c2faSJoe Perches struct va_format vaf; 636d31c2faSJoe Perches va_list args; 646d31c2faSJoe Perches char pfix[32]; 65184cd4a3SBenjamin Herrenschmidt 666d31c2faSJoe Perches va_start(args, fmt); 676d31c2faSJoe Perches 686d31c2faSJoe Perches vaf.fmt = fmt; 696d31c2faSJoe Perches vaf.va = &args; 706d31c2faSJoe Perches 71781a868fSWei Yang if (pe->flags & PNV_IODA_PE_DEV) 726d31c2faSJoe Perches strlcpy(pfix, dev_name(&pe->pdev->dev), sizeof(pfix)); 73781a868fSWei Yang else if (pe->flags & (PNV_IODA_PE_BUS | PNV_IODA_PE_BUS_ALL)) 746d31c2faSJoe Perches sprintf(pfix, "%04x:%02x ", 756d31c2faSJoe Perches pci_domain_nr(pe->pbus), pe->pbus->number); 76781a868fSWei Yang #ifdef CONFIG_PCI_IOV 77781a868fSWei Yang else if (pe->flags & PNV_IODA_PE_VF) 78781a868fSWei Yang sprintf(pfix, "%04x:%02x:%2x.%d", 79781a868fSWei Yang pci_domain_nr(pe->parent_dev->bus), 80781a868fSWei Yang (pe->rid & 0xff00) >> 8, 81781a868fSWei Yang PCI_SLOT(pe->rid), PCI_FUNC(pe->rid)); 82781a868fSWei Yang #endif /* CONFIG_PCI_IOV*/ 836d31c2faSJoe Perches 846d31c2faSJoe Perches printk("%spci %s: [PE# %.3d] %pV", 856d31c2faSJoe Perches level, pfix, pe->pe_number, &vaf); 866d31c2faSJoe Perches 876d31c2faSJoe Perches va_end(args); 886d31c2faSJoe Perches } 896d31c2faSJoe Perches 906d31c2faSJoe Perches #define pe_err(pe, fmt, ...) \ 916d31c2faSJoe Perches pe_level_printk(pe, KERN_ERR, fmt, ##__VA_ARGS__) 926d31c2faSJoe Perches #define pe_warn(pe, fmt, ...) \ 936d31c2faSJoe Perches pe_level_printk(pe, KERN_WARNING, fmt, ##__VA_ARGS__) 946d31c2faSJoe Perches #define pe_info(pe, fmt, ...) \ 956d31c2faSJoe Perches pe_level_printk(pe, KERN_INFO, fmt, ##__VA_ARGS__) 96184cd4a3SBenjamin Herrenschmidt 974e287840SThadeu Lima de Souza Cascardo static bool pnv_iommu_bypass_disabled __read_mostly; 984e287840SThadeu Lima de Souza Cascardo 994e287840SThadeu Lima de Souza Cascardo static int __init iommu_setup(char *str) 1004e287840SThadeu Lima de Souza Cascardo { 1014e287840SThadeu Lima de Souza Cascardo if (!str) 1024e287840SThadeu Lima de Souza Cascardo return -EINVAL; 1034e287840SThadeu Lima de Souza Cascardo 1044e287840SThadeu Lima de Souza Cascardo while (*str) { 1054e287840SThadeu Lima de Souza Cascardo if (!strncmp(str, "nobypass", 8)) { 1064e287840SThadeu Lima de Souza Cascardo pnv_iommu_bypass_disabled = true; 1074e287840SThadeu Lima de Souza Cascardo pr_info("PowerNV: IOMMU bypass window disabled.\n"); 1084e287840SThadeu Lima de Souza Cascardo break; 1094e287840SThadeu Lima de Souza Cascardo } 1104e287840SThadeu Lima de Souza Cascardo str += strcspn(str, ","); 1114e287840SThadeu Lima de Souza Cascardo if (*str == ',') 1124e287840SThadeu Lima de Souza Cascardo str++; 1134e287840SThadeu Lima de Souza Cascardo } 1144e287840SThadeu Lima de Souza Cascardo 1154e287840SThadeu Lima de Souza Cascardo return 0; 1164e287840SThadeu Lima de Souza Cascardo } 1174e287840SThadeu Lima de Souza Cascardo early_param("iommu", iommu_setup); 1184e287840SThadeu Lima de Souza Cascardo 119262af557SGuo Chao static inline bool pnv_pci_is_mem_pref_64(unsigned long flags) 120262af557SGuo Chao { 121262af557SGuo Chao return ((flags & (IORESOURCE_MEM_64 | IORESOURCE_PREFETCH)) == 122262af557SGuo Chao (IORESOURCE_MEM_64 | IORESOURCE_PREFETCH)); 123262af557SGuo Chao } 124262af557SGuo Chao 1254b82ab18SGavin Shan static void pnv_ioda_reserve_pe(struct pnv_phb *phb, int pe_no) 1264b82ab18SGavin Shan { 12792b8f137SGavin Shan if (!(pe_no >= 0 && pe_no < phb->ioda.total_pe_num)) { 1284b82ab18SGavin Shan pr_warn("%s: Invalid PE %d on PHB#%x\n", 1294b82ab18SGavin Shan __func__, pe_no, phb->hose->global_number); 1304b82ab18SGavin Shan return; 1314b82ab18SGavin Shan } 1324b82ab18SGavin Shan 133e9dc4d7fSGavin Shan if (test_and_set_bit(pe_no, phb->ioda.pe_alloc)) 134e9dc4d7fSGavin Shan pr_debug("%s: PE %d was reserved on PHB#%x\n", 1354b82ab18SGavin Shan __func__, pe_no, phb->hose->global_number); 1364b82ab18SGavin Shan 1374b82ab18SGavin Shan phb->ioda.pe_array[pe_no].phb = phb; 1384b82ab18SGavin Shan phb->ioda.pe_array[pe_no].pe_number = pe_no; 1394b82ab18SGavin Shan } 1404b82ab18SGavin Shan 141689ee8c9SGavin Shan static unsigned int pnv_ioda_alloc_pe(struct pnv_phb *phb) 142184cd4a3SBenjamin Herrenschmidt { 143184cd4a3SBenjamin Herrenschmidt unsigned long pe; 144184cd4a3SBenjamin Herrenschmidt 145184cd4a3SBenjamin Herrenschmidt do { 146184cd4a3SBenjamin Herrenschmidt pe = find_next_zero_bit(phb->ioda.pe_alloc, 14792b8f137SGavin Shan phb->ioda.total_pe_num, 0); 14892b8f137SGavin Shan if (pe >= phb->ioda.total_pe_num) 149184cd4a3SBenjamin Herrenschmidt return IODA_INVALID_PE; 150184cd4a3SBenjamin Herrenschmidt } while(test_and_set_bit(pe, phb->ioda.pe_alloc)); 151184cd4a3SBenjamin Herrenschmidt 1524cce9550SGavin Shan phb->ioda.pe_array[pe].phb = phb; 153184cd4a3SBenjamin Herrenschmidt phb->ioda.pe_array[pe].pe_number = pe; 154184cd4a3SBenjamin Herrenschmidt return pe; 155184cd4a3SBenjamin Herrenschmidt } 156184cd4a3SBenjamin Herrenschmidt 157cad5cef6SGreg Kroah-Hartman static void pnv_ioda_free_pe(struct pnv_phb *phb, int pe) 158184cd4a3SBenjamin Herrenschmidt { 159184cd4a3SBenjamin Herrenschmidt WARN_ON(phb->ioda.pe_array[pe].pdev); 160184cd4a3SBenjamin Herrenschmidt 161184cd4a3SBenjamin Herrenschmidt memset(&phb->ioda.pe_array[pe], 0, sizeof(struct pnv_ioda_pe)); 162184cd4a3SBenjamin Herrenschmidt clear_bit(pe, phb->ioda.pe_alloc); 163184cd4a3SBenjamin Herrenschmidt } 164184cd4a3SBenjamin Herrenschmidt 165262af557SGuo Chao /* The default M64 BAR is shared by all PEs */ 166262af557SGuo Chao static int pnv_ioda2_init_m64(struct pnv_phb *phb) 167262af557SGuo Chao { 168262af557SGuo Chao const char *desc; 169262af557SGuo Chao struct resource *r; 170262af557SGuo Chao s64 rc; 171262af557SGuo Chao 172262af557SGuo Chao /* Configure the default M64 BAR */ 173262af557SGuo Chao rc = opal_pci_set_phb_mem_window(phb->opal_id, 174262af557SGuo Chao OPAL_M64_WINDOW_TYPE, 175262af557SGuo Chao phb->ioda.m64_bar_idx, 176262af557SGuo Chao phb->ioda.m64_base, 177262af557SGuo Chao 0, /* unused */ 178262af557SGuo Chao phb->ioda.m64_size); 179262af557SGuo Chao if (rc != OPAL_SUCCESS) { 180262af557SGuo Chao desc = "configuring"; 181262af557SGuo Chao goto fail; 182262af557SGuo Chao } 183262af557SGuo Chao 184262af557SGuo Chao /* Enable the default M64 BAR */ 185262af557SGuo Chao rc = opal_pci_phb_mmio_enable(phb->opal_id, 186262af557SGuo Chao OPAL_M64_WINDOW_TYPE, 187262af557SGuo Chao phb->ioda.m64_bar_idx, 188262af557SGuo Chao OPAL_ENABLE_M64_SPLIT); 189262af557SGuo Chao if (rc != OPAL_SUCCESS) { 190262af557SGuo Chao desc = "enabling"; 191262af557SGuo Chao goto fail; 192262af557SGuo Chao } 193262af557SGuo Chao 194262af557SGuo Chao /* Mark the M64 BAR assigned */ 195262af557SGuo Chao set_bit(phb->ioda.m64_bar_idx, &phb->ioda.m64_bar_alloc); 196262af557SGuo Chao 197262af557SGuo Chao /* 198262af557SGuo Chao * Strip off the segment used by the reserved PE, which is 199262af557SGuo Chao * expected to be 0 or last one of PE capabicity. 200262af557SGuo Chao */ 201262af557SGuo Chao r = &phb->hose->mem_resources[1]; 20292b8f137SGavin Shan if (phb->ioda.reserved_pe_idx == 0) 203262af557SGuo Chao r->start += phb->ioda.m64_segsize; 20492b8f137SGavin Shan else if (phb->ioda.reserved_pe_idx == (phb->ioda.total_pe_num - 1)) 205262af557SGuo Chao r->end -= phb->ioda.m64_segsize; 206262af557SGuo Chao else 207262af557SGuo Chao pr_warn(" Cannot strip M64 segment for reserved PE#%d\n", 20892b8f137SGavin Shan phb->ioda.reserved_pe_idx); 209262af557SGuo Chao 210262af557SGuo Chao return 0; 211262af557SGuo Chao 212262af557SGuo Chao fail: 213262af557SGuo Chao pr_warn(" Failure %lld %s M64 BAR#%d\n", 214262af557SGuo Chao rc, desc, phb->ioda.m64_bar_idx); 215262af557SGuo Chao opal_pci_phb_mmio_enable(phb->opal_id, 216262af557SGuo Chao OPAL_M64_WINDOW_TYPE, 217262af557SGuo Chao phb->ioda.m64_bar_idx, 218262af557SGuo Chao OPAL_DISABLE_M64); 219262af557SGuo Chao return -EIO; 220262af557SGuo Chao } 221262af557SGuo Chao 22296a2f92bSGavin Shan static void pnv_ioda2_reserve_dev_m64_pe(struct pci_dev *pdev, 22396a2f92bSGavin Shan unsigned long *pe_bitmap) 224262af557SGuo Chao { 22596a2f92bSGavin Shan struct pci_controller *hose = pci_bus_to_host(pdev->bus); 22696a2f92bSGavin Shan struct pnv_phb *phb = hose->private_data; 227262af557SGuo Chao struct resource *r; 22896a2f92bSGavin Shan resource_size_t base, sgsz, start, end; 22996a2f92bSGavin Shan int segno, i; 230262af557SGuo Chao 23196a2f92bSGavin Shan base = phb->ioda.m64_base; 23296a2f92bSGavin Shan sgsz = phb->ioda.m64_segsize; 23396a2f92bSGavin Shan for (i = 0; i <= PCI_ROM_RESOURCE; i++) { 23496a2f92bSGavin Shan r = &pdev->resource[i]; 23596a2f92bSGavin Shan if (!r->parent || !pnv_pci_is_mem_pref_64(r->flags)) 236262af557SGuo Chao continue; 237262af557SGuo Chao 23896a2f92bSGavin Shan start = _ALIGN_DOWN(r->start - base, sgsz); 23996a2f92bSGavin Shan end = _ALIGN_UP(r->end - base, sgsz); 24096a2f92bSGavin Shan for (segno = start / sgsz; segno < end / sgsz; segno++) { 24196a2f92bSGavin Shan if (pe_bitmap) 24296a2f92bSGavin Shan set_bit(segno, pe_bitmap); 24396a2f92bSGavin Shan else 24496a2f92bSGavin Shan pnv_ioda_reserve_pe(phb, segno); 245262af557SGuo Chao } 246262af557SGuo Chao } 247262af557SGuo Chao } 248262af557SGuo Chao 24996a2f92bSGavin Shan static void pnv_ioda2_reserve_m64_pe(struct pci_bus *bus, 25096a2f92bSGavin Shan unsigned long *pe_bitmap, 25196a2f92bSGavin Shan bool all) 252262af557SGuo Chao { 253262af557SGuo Chao struct pci_dev *pdev; 25496a2f92bSGavin Shan 25596a2f92bSGavin Shan list_for_each_entry(pdev, &bus->devices, bus_list) { 25696a2f92bSGavin Shan pnv_ioda2_reserve_dev_m64_pe(pdev, pe_bitmap); 25796a2f92bSGavin Shan 25896a2f92bSGavin Shan if (all && pdev->subordinate) 25996a2f92bSGavin Shan pnv_ioda2_reserve_m64_pe(pdev->subordinate, 26096a2f92bSGavin Shan pe_bitmap, all); 26196a2f92bSGavin Shan } 26296a2f92bSGavin Shan } 26396a2f92bSGavin Shan 264689ee8c9SGavin Shan static unsigned int pnv_ioda2_pick_m64_pe(struct pci_bus *bus, bool all) 265262af557SGuo Chao { 26626ba248dSGavin Shan struct pci_controller *hose = pci_bus_to_host(bus); 26726ba248dSGavin Shan struct pnv_phb *phb = hose->private_data; 268262af557SGuo Chao struct pnv_ioda_pe *master_pe, *pe; 269262af557SGuo Chao unsigned long size, *pe_alloc; 27026ba248dSGavin Shan int i; 271262af557SGuo Chao 272262af557SGuo Chao /* Root bus shouldn't use M64 */ 273262af557SGuo Chao if (pci_is_root_bus(bus)) 274262af557SGuo Chao return IODA_INVALID_PE; 275262af557SGuo Chao 276262af557SGuo Chao /* Allocate bitmap */ 27792b8f137SGavin Shan size = _ALIGN_UP(phb->ioda.total_pe_num / 8, sizeof(unsigned long)); 278262af557SGuo Chao pe_alloc = kzalloc(size, GFP_KERNEL); 279262af557SGuo Chao if (!pe_alloc) { 280262af557SGuo Chao pr_warn("%s: Out of memory !\n", 281262af557SGuo Chao __func__); 282262af557SGuo Chao return IODA_INVALID_PE; 283262af557SGuo Chao } 284262af557SGuo Chao 28526ba248dSGavin Shan /* Figure out reserved PE numbers by the PE */ 28626ba248dSGavin Shan pnv_ioda2_reserve_m64_pe(bus, pe_alloc, all); 287262af557SGuo Chao 288262af557SGuo Chao /* 289262af557SGuo Chao * the current bus might not own M64 window and that's all 290262af557SGuo Chao * contributed by its child buses. For the case, we needn't 291262af557SGuo Chao * pick M64 dependent PE#. 292262af557SGuo Chao */ 29392b8f137SGavin Shan if (bitmap_empty(pe_alloc, phb->ioda.total_pe_num)) { 294262af557SGuo Chao kfree(pe_alloc); 295262af557SGuo Chao return IODA_INVALID_PE; 296262af557SGuo Chao } 297262af557SGuo Chao 298262af557SGuo Chao /* 299262af557SGuo Chao * Figure out the master PE and put all slave PEs to master 300262af557SGuo Chao * PE's list to form compound PE. 301262af557SGuo Chao */ 302262af557SGuo Chao master_pe = NULL; 303262af557SGuo Chao i = -1; 30492b8f137SGavin Shan while ((i = find_next_bit(pe_alloc, phb->ioda.total_pe_num, i + 1)) < 30592b8f137SGavin Shan phb->ioda.total_pe_num) { 306262af557SGuo Chao pe = &phb->ioda.pe_array[i]; 307262af557SGuo Chao 30893289d8cSGavin Shan phb->ioda.m64_segmap[pe->pe_number] = pe->pe_number; 309262af557SGuo Chao if (!master_pe) { 310262af557SGuo Chao pe->flags |= PNV_IODA_PE_MASTER; 311262af557SGuo Chao INIT_LIST_HEAD(&pe->slaves); 312262af557SGuo Chao master_pe = pe; 313262af557SGuo Chao } else { 314262af557SGuo Chao pe->flags |= PNV_IODA_PE_SLAVE; 315262af557SGuo Chao pe->master = master_pe; 316262af557SGuo Chao list_add_tail(&pe->list, &master_pe->slaves); 317262af557SGuo Chao } 318262af557SGuo Chao } 319262af557SGuo Chao 320262af557SGuo Chao kfree(pe_alloc); 321262af557SGuo Chao return master_pe->pe_number; 322262af557SGuo Chao } 323262af557SGuo Chao 324262af557SGuo Chao static void __init pnv_ioda_parse_m64_window(struct pnv_phb *phb) 325262af557SGuo Chao { 326262af557SGuo Chao struct pci_controller *hose = phb->hose; 327262af557SGuo Chao struct device_node *dn = hose->dn; 328262af557SGuo Chao struct resource *res; 329262af557SGuo Chao const u32 *r; 330262af557SGuo Chao u64 pci_addr; 331262af557SGuo Chao 3321665c4a8SGavin Shan /* FIXME: Support M64 for P7IOC */ 3331665c4a8SGavin Shan if (phb->type != PNV_PHB_IODA2) { 3341665c4a8SGavin Shan pr_info(" Not support M64 window\n"); 3351665c4a8SGavin Shan return; 3361665c4a8SGavin Shan } 3371665c4a8SGavin Shan 338e4d54f71SStewart Smith if (!firmware_has_feature(FW_FEATURE_OPAL)) { 339262af557SGuo Chao pr_info(" Firmware too old to support M64 window\n"); 340262af557SGuo Chao return; 341262af557SGuo Chao } 342262af557SGuo Chao 343262af557SGuo Chao r = of_get_property(dn, "ibm,opal-m64-window", NULL); 344262af557SGuo Chao if (!r) { 345262af557SGuo Chao pr_info(" No <ibm,opal-m64-window> on %s\n", 346262af557SGuo Chao dn->full_name); 347262af557SGuo Chao return; 348262af557SGuo Chao } 349262af557SGuo Chao 350262af557SGuo Chao res = &hose->mem_resources[1]; 351e80c4e7cSGavin Shan res->name = dn->full_name; 352262af557SGuo Chao res->start = of_translate_address(dn, r + 2); 353262af557SGuo Chao res->end = res->start + of_read_number(r + 4, 2) - 1; 354262af557SGuo Chao res->flags = (IORESOURCE_MEM | IORESOURCE_MEM_64 | IORESOURCE_PREFETCH); 355262af557SGuo Chao pci_addr = of_read_number(r, 2); 356262af557SGuo Chao hose->mem_offset[1] = res->start - pci_addr; 357262af557SGuo Chao 358262af557SGuo Chao phb->ioda.m64_size = resource_size(res); 35992b8f137SGavin Shan phb->ioda.m64_segsize = phb->ioda.m64_size / phb->ioda.total_pe_num; 360262af557SGuo Chao phb->ioda.m64_base = pci_addr; 361262af557SGuo Chao 362e9863e68SWei Yang pr_info(" MEM64 0x%016llx..0x%016llx -> 0x%016llx\n", 363e9863e68SWei Yang res->start, res->end, pci_addr); 364e9863e68SWei Yang 365262af557SGuo Chao /* Use last M64 BAR to cover M64 window */ 366262af557SGuo Chao phb->ioda.m64_bar_idx = 15; 367262af557SGuo Chao phb->init_m64 = pnv_ioda2_init_m64; 3685ef73567SGavin Shan phb->reserve_m64_pe = pnv_ioda2_reserve_m64_pe; 369262af557SGuo Chao phb->pick_m64_pe = pnv_ioda2_pick_m64_pe; 370262af557SGuo Chao } 371262af557SGuo Chao 37249dec922SGavin Shan static void pnv_ioda_freeze_pe(struct pnv_phb *phb, int pe_no) 37349dec922SGavin Shan { 37449dec922SGavin Shan struct pnv_ioda_pe *pe = &phb->ioda.pe_array[pe_no]; 37549dec922SGavin Shan struct pnv_ioda_pe *slave; 37649dec922SGavin Shan s64 rc; 37749dec922SGavin Shan 37849dec922SGavin Shan /* Fetch master PE */ 37949dec922SGavin Shan if (pe->flags & PNV_IODA_PE_SLAVE) { 38049dec922SGavin Shan pe = pe->master; 381ec8e4e9dSGavin Shan if (WARN_ON(!pe || !(pe->flags & PNV_IODA_PE_MASTER))) 382ec8e4e9dSGavin Shan return; 383ec8e4e9dSGavin Shan 38449dec922SGavin Shan pe_no = pe->pe_number; 38549dec922SGavin Shan } 38649dec922SGavin Shan 38749dec922SGavin Shan /* Freeze master PE */ 38849dec922SGavin Shan rc = opal_pci_eeh_freeze_set(phb->opal_id, 38949dec922SGavin Shan pe_no, 39049dec922SGavin Shan OPAL_EEH_ACTION_SET_FREEZE_ALL); 39149dec922SGavin Shan if (rc != OPAL_SUCCESS) { 39249dec922SGavin Shan pr_warn("%s: Failure %lld freezing PHB#%x-PE#%x\n", 39349dec922SGavin Shan __func__, rc, phb->hose->global_number, pe_no); 39449dec922SGavin Shan return; 39549dec922SGavin Shan } 39649dec922SGavin Shan 39749dec922SGavin Shan /* Freeze slave PEs */ 39849dec922SGavin Shan if (!(pe->flags & PNV_IODA_PE_MASTER)) 39949dec922SGavin Shan return; 40049dec922SGavin Shan 40149dec922SGavin Shan list_for_each_entry(slave, &pe->slaves, list) { 40249dec922SGavin Shan rc = opal_pci_eeh_freeze_set(phb->opal_id, 40349dec922SGavin Shan slave->pe_number, 40449dec922SGavin Shan OPAL_EEH_ACTION_SET_FREEZE_ALL); 40549dec922SGavin Shan if (rc != OPAL_SUCCESS) 40649dec922SGavin Shan pr_warn("%s: Failure %lld freezing PHB#%x-PE#%x\n", 40749dec922SGavin Shan __func__, rc, phb->hose->global_number, 40849dec922SGavin Shan slave->pe_number); 40949dec922SGavin Shan } 41049dec922SGavin Shan } 41149dec922SGavin Shan 412e51df2c1SAnton Blanchard static int pnv_ioda_unfreeze_pe(struct pnv_phb *phb, int pe_no, int opt) 41349dec922SGavin Shan { 41449dec922SGavin Shan struct pnv_ioda_pe *pe, *slave; 41549dec922SGavin Shan s64 rc; 41649dec922SGavin Shan 41749dec922SGavin Shan /* Find master PE */ 41849dec922SGavin Shan pe = &phb->ioda.pe_array[pe_no]; 41949dec922SGavin Shan if (pe->flags & PNV_IODA_PE_SLAVE) { 42049dec922SGavin Shan pe = pe->master; 42149dec922SGavin Shan WARN_ON(!pe || !(pe->flags & PNV_IODA_PE_MASTER)); 42249dec922SGavin Shan pe_no = pe->pe_number; 42349dec922SGavin Shan } 42449dec922SGavin Shan 42549dec922SGavin Shan /* Clear frozen state for master PE */ 42649dec922SGavin Shan rc = opal_pci_eeh_freeze_clear(phb->opal_id, pe_no, opt); 42749dec922SGavin Shan if (rc != OPAL_SUCCESS) { 42849dec922SGavin Shan pr_warn("%s: Failure %lld clear %d on PHB#%x-PE#%x\n", 42949dec922SGavin Shan __func__, rc, opt, phb->hose->global_number, pe_no); 43049dec922SGavin Shan return -EIO; 43149dec922SGavin Shan } 43249dec922SGavin Shan 43349dec922SGavin Shan if (!(pe->flags & PNV_IODA_PE_MASTER)) 43449dec922SGavin Shan return 0; 43549dec922SGavin Shan 43649dec922SGavin Shan /* Clear frozen state for slave PEs */ 43749dec922SGavin Shan list_for_each_entry(slave, &pe->slaves, list) { 43849dec922SGavin Shan rc = opal_pci_eeh_freeze_clear(phb->opal_id, 43949dec922SGavin Shan slave->pe_number, 44049dec922SGavin Shan opt); 44149dec922SGavin Shan if (rc != OPAL_SUCCESS) { 44249dec922SGavin Shan pr_warn("%s: Failure %lld clear %d on PHB#%x-PE#%x\n", 44349dec922SGavin Shan __func__, rc, opt, phb->hose->global_number, 44449dec922SGavin Shan slave->pe_number); 44549dec922SGavin Shan return -EIO; 44649dec922SGavin Shan } 44749dec922SGavin Shan } 44849dec922SGavin Shan 44949dec922SGavin Shan return 0; 45049dec922SGavin Shan } 45149dec922SGavin Shan 45249dec922SGavin Shan static int pnv_ioda_get_pe_state(struct pnv_phb *phb, int pe_no) 45349dec922SGavin Shan { 45449dec922SGavin Shan struct pnv_ioda_pe *slave, *pe; 45549dec922SGavin Shan u8 fstate, state; 45649dec922SGavin Shan __be16 pcierr; 45749dec922SGavin Shan s64 rc; 45849dec922SGavin Shan 45949dec922SGavin Shan /* Sanity check on PE number */ 46092b8f137SGavin Shan if (pe_no < 0 || pe_no >= phb->ioda.total_pe_num) 46149dec922SGavin Shan return OPAL_EEH_STOPPED_PERM_UNAVAIL; 46249dec922SGavin Shan 46349dec922SGavin Shan /* 46449dec922SGavin Shan * Fetch the master PE and the PE instance might be 46549dec922SGavin Shan * not initialized yet. 46649dec922SGavin Shan */ 46749dec922SGavin Shan pe = &phb->ioda.pe_array[pe_no]; 46849dec922SGavin Shan if (pe->flags & PNV_IODA_PE_SLAVE) { 46949dec922SGavin Shan pe = pe->master; 47049dec922SGavin Shan WARN_ON(!pe || !(pe->flags & PNV_IODA_PE_MASTER)); 47149dec922SGavin Shan pe_no = pe->pe_number; 47249dec922SGavin Shan } 47349dec922SGavin Shan 47449dec922SGavin Shan /* Check the master PE */ 47549dec922SGavin Shan rc = opal_pci_eeh_freeze_status(phb->opal_id, pe_no, 47649dec922SGavin Shan &state, &pcierr, NULL); 47749dec922SGavin Shan if (rc != OPAL_SUCCESS) { 47849dec922SGavin Shan pr_warn("%s: Failure %lld getting " 47949dec922SGavin Shan "PHB#%x-PE#%x state\n", 48049dec922SGavin Shan __func__, rc, 48149dec922SGavin Shan phb->hose->global_number, pe_no); 48249dec922SGavin Shan return OPAL_EEH_STOPPED_TEMP_UNAVAIL; 48349dec922SGavin Shan } 48449dec922SGavin Shan 48549dec922SGavin Shan /* Check the slave PE */ 48649dec922SGavin Shan if (!(pe->flags & PNV_IODA_PE_MASTER)) 48749dec922SGavin Shan return state; 48849dec922SGavin Shan 48949dec922SGavin Shan list_for_each_entry(slave, &pe->slaves, list) { 49049dec922SGavin Shan rc = opal_pci_eeh_freeze_status(phb->opal_id, 49149dec922SGavin Shan slave->pe_number, 49249dec922SGavin Shan &fstate, 49349dec922SGavin Shan &pcierr, 49449dec922SGavin Shan NULL); 49549dec922SGavin Shan if (rc != OPAL_SUCCESS) { 49649dec922SGavin Shan pr_warn("%s: Failure %lld getting " 49749dec922SGavin Shan "PHB#%x-PE#%x state\n", 49849dec922SGavin Shan __func__, rc, 49949dec922SGavin Shan phb->hose->global_number, slave->pe_number); 50049dec922SGavin Shan return OPAL_EEH_STOPPED_TEMP_UNAVAIL; 50149dec922SGavin Shan } 50249dec922SGavin Shan 50349dec922SGavin Shan /* 50449dec922SGavin Shan * Override the result based on the ascending 50549dec922SGavin Shan * priority. 50649dec922SGavin Shan */ 50749dec922SGavin Shan if (fstate > state) 50849dec922SGavin Shan state = fstate; 50949dec922SGavin Shan } 51049dec922SGavin Shan 51149dec922SGavin Shan return state; 51249dec922SGavin Shan } 51349dec922SGavin Shan 514184cd4a3SBenjamin Herrenschmidt /* Currently those 2 are only used when MSIs are enabled, this will change 515184cd4a3SBenjamin Herrenschmidt * but in the meantime, we need to protect them to avoid warnings 516184cd4a3SBenjamin Herrenschmidt */ 517184cd4a3SBenjamin Herrenschmidt #ifdef CONFIG_PCI_MSI 518cad5cef6SGreg Kroah-Hartman static struct pnv_ioda_pe *pnv_ioda_get_pe(struct pci_dev *dev) 519184cd4a3SBenjamin Herrenschmidt { 520184cd4a3SBenjamin Herrenschmidt struct pci_controller *hose = pci_bus_to_host(dev->bus); 521184cd4a3SBenjamin Herrenschmidt struct pnv_phb *phb = hose->private_data; 522b72c1f65SBenjamin Herrenschmidt struct pci_dn *pdn = pci_get_pdn(dev); 523184cd4a3SBenjamin Herrenschmidt 524184cd4a3SBenjamin Herrenschmidt if (!pdn) 525184cd4a3SBenjamin Herrenschmidt return NULL; 526184cd4a3SBenjamin Herrenschmidt if (pdn->pe_number == IODA_INVALID_PE) 527184cd4a3SBenjamin Herrenschmidt return NULL; 528184cd4a3SBenjamin Herrenschmidt return &phb->ioda.pe_array[pdn->pe_number]; 529184cd4a3SBenjamin Herrenschmidt } 530184cd4a3SBenjamin Herrenschmidt #endif /* CONFIG_PCI_MSI */ 531184cd4a3SBenjamin Herrenschmidt 532b131a842SGavin Shan static int pnv_ioda_set_one_peltv(struct pnv_phb *phb, 533b131a842SGavin Shan struct pnv_ioda_pe *parent, 534b131a842SGavin Shan struct pnv_ioda_pe *child, 535b131a842SGavin Shan bool is_add) 536b131a842SGavin Shan { 537b131a842SGavin Shan const char *desc = is_add ? "adding" : "removing"; 538b131a842SGavin Shan uint8_t op = is_add ? OPAL_ADD_PE_TO_DOMAIN : 539b131a842SGavin Shan OPAL_REMOVE_PE_FROM_DOMAIN; 540b131a842SGavin Shan struct pnv_ioda_pe *slave; 541b131a842SGavin Shan long rc; 542b131a842SGavin Shan 543b131a842SGavin Shan /* Parent PE affects child PE */ 544b131a842SGavin Shan rc = opal_pci_set_peltv(phb->opal_id, parent->pe_number, 545b131a842SGavin Shan child->pe_number, op); 546b131a842SGavin Shan if (rc != OPAL_SUCCESS) { 547b131a842SGavin Shan pe_warn(child, "OPAL error %ld %s to parent PELTV\n", 548b131a842SGavin Shan rc, desc); 549b131a842SGavin Shan return -ENXIO; 550b131a842SGavin Shan } 551b131a842SGavin Shan 552b131a842SGavin Shan if (!(child->flags & PNV_IODA_PE_MASTER)) 553b131a842SGavin Shan return 0; 554b131a842SGavin Shan 555b131a842SGavin Shan /* Compound case: parent PE affects slave PEs */ 556b131a842SGavin Shan list_for_each_entry(slave, &child->slaves, list) { 557b131a842SGavin Shan rc = opal_pci_set_peltv(phb->opal_id, parent->pe_number, 558b131a842SGavin Shan slave->pe_number, op); 559b131a842SGavin Shan if (rc != OPAL_SUCCESS) { 560b131a842SGavin Shan pe_warn(slave, "OPAL error %ld %s to parent PELTV\n", 561b131a842SGavin Shan rc, desc); 562b131a842SGavin Shan return -ENXIO; 563b131a842SGavin Shan } 564b131a842SGavin Shan } 565b131a842SGavin Shan 566b131a842SGavin Shan return 0; 567b131a842SGavin Shan } 568b131a842SGavin Shan 569b131a842SGavin Shan static int pnv_ioda_set_peltv(struct pnv_phb *phb, 570b131a842SGavin Shan struct pnv_ioda_pe *pe, 571b131a842SGavin Shan bool is_add) 572b131a842SGavin Shan { 573b131a842SGavin Shan struct pnv_ioda_pe *slave; 574781a868fSWei Yang struct pci_dev *pdev = NULL; 575b131a842SGavin Shan int ret; 576b131a842SGavin Shan 577b131a842SGavin Shan /* 578b131a842SGavin Shan * Clear PE frozen state. If it's master PE, we need 579b131a842SGavin Shan * clear slave PE frozen state as well. 580b131a842SGavin Shan */ 581b131a842SGavin Shan if (is_add) { 582b131a842SGavin Shan opal_pci_eeh_freeze_clear(phb->opal_id, pe->pe_number, 583b131a842SGavin Shan OPAL_EEH_ACTION_CLEAR_FREEZE_ALL); 584b131a842SGavin Shan if (pe->flags & PNV_IODA_PE_MASTER) { 585b131a842SGavin Shan list_for_each_entry(slave, &pe->slaves, list) 586b131a842SGavin Shan opal_pci_eeh_freeze_clear(phb->opal_id, 587b131a842SGavin Shan slave->pe_number, 588b131a842SGavin Shan OPAL_EEH_ACTION_CLEAR_FREEZE_ALL); 589b131a842SGavin Shan } 590b131a842SGavin Shan } 591b131a842SGavin Shan 592b131a842SGavin Shan /* 593b131a842SGavin Shan * Associate PE in PELT. We need add the PE into the 594b131a842SGavin Shan * corresponding PELT-V as well. Otherwise, the error 595b131a842SGavin Shan * originated from the PE might contribute to other 596b131a842SGavin Shan * PEs. 597b131a842SGavin Shan */ 598b131a842SGavin Shan ret = pnv_ioda_set_one_peltv(phb, pe, pe, is_add); 599b131a842SGavin Shan if (ret) 600b131a842SGavin Shan return ret; 601b131a842SGavin Shan 602b131a842SGavin Shan /* For compound PEs, any one affects all of them */ 603b131a842SGavin Shan if (pe->flags & PNV_IODA_PE_MASTER) { 604b131a842SGavin Shan list_for_each_entry(slave, &pe->slaves, list) { 605b131a842SGavin Shan ret = pnv_ioda_set_one_peltv(phb, slave, pe, is_add); 606b131a842SGavin Shan if (ret) 607b131a842SGavin Shan return ret; 608b131a842SGavin Shan } 609b131a842SGavin Shan } 610b131a842SGavin Shan 611b131a842SGavin Shan if (pe->flags & (PNV_IODA_PE_BUS_ALL | PNV_IODA_PE_BUS)) 612b131a842SGavin Shan pdev = pe->pbus->self; 613781a868fSWei Yang else if (pe->flags & PNV_IODA_PE_DEV) 614b131a842SGavin Shan pdev = pe->pdev->bus->self; 615781a868fSWei Yang #ifdef CONFIG_PCI_IOV 616781a868fSWei Yang else if (pe->flags & PNV_IODA_PE_VF) 617283e2d8aSGavin Shan pdev = pe->parent_dev; 618781a868fSWei Yang #endif /* CONFIG_PCI_IOV */ 619b131a842SGavin Shan while (pdev) { 620b131a842SGavin Shan struct pci_dn *pdn = pci_get_pdn(pdev); 621b131a842SGavin Shan struct pnv_ioda_pe *parent; 622b131a842SGavin Shan 623b131a842SGavin Shan if (pdn && pdn->pe_number != IODA_INVALID_PE) { 624b131a842SGavin Shan parent = &phb->ioda.pe_array[pdn->pe_number]; 625b131a842SGavin Shan ret = pnv_ioda_set_one_peltv(phb, parent, pe, is_add); 626b131a842SGavin Shan if (ret) 627b131a842SGavin Shan return ret; 628b131a842SGavin Shan } 629b131a842SGavin Shan 630b131a842SGavin Shan pdev = pdev->bus->self; 631b131a842SGavin Shan } 632b131a842SGavin Shan 633b131a842SGavin Shan return 0; 634b131a842SGavin Shan } 635b131a842SGavin Shan 636781a868fSWei Yang #ifdef CONFIG_PCI_IOV 637781a868fSWei Yang static int pnv_ioda_deconfigure_pe(struct pnv_phb *phb, struct pnv_ioda_pe *pe) 638781a868fSWei Yang { 639781a868fSWei Yang struct pci_dev *parent; 640781a868fSWei Yang uint8_t bcomp, dcomp, fcomp; 641781a868fSWei Yang int64_t rc; 642781a868fSWei Yang long rid_end, rid; 643781a868fSWei Yang 644781a868fSWei Yang /* Currently, we just deconfigure VF PE. Bus PE will always there.*/ 645781a868fSWei Yang if (pe->pbus) { 646781a868fSWei Yang int count; 647781a868fSWei Yang 648781a868fSWei Yang dcomp = OPAL_IGNORE_RID_DEVICE_NUMBER; 649781a868fSWei Yang fcomp = OPAL_IGNORE_RID_FUNCTION_NUMBER; 650781a868fSWei Yang parent = pe->pbus->self; 651781a868fSWei Yang if (pe->flags & PNV_IODA_PE_BUS_ALL) 652781a868fSWei Yang count = pe->pbus->busn_res.end - pe->pbus->busn_res.start + 1; 653781a868fSWei Yang else 654781a868fSWei Yang count = 1; 655781a868fSWei Yang 656781a868fSWei Yang switch(count) { 657781a868fSWei Yang case 1: bcomp = OpalPciBusAll; break; 658781a868fSWei Yang case 2: bcomp = OpalPciBus7Bits; break; 659781a868fSWei Yang case 4: bcomp = OpalPciBus6Bits; break; 660781a868fSWei Yang case 8: bcomp = OpalPciBus5Bits; break; 661781a868fSWei Yang case 16: bcomp = OpalPciBus4Bits; break; 662781a868fSWei Yang case 32: bcomp = OpalPciBus3Bits; break; 663781a868fSWei Yang default: 664781a868fSWei Yang dev_err(&pe->pbus->dev, "Number of subordinate buses %d unsupported\n", 665781a868fSWei Yang count); 666781a868fSWei Yang /* Do an exact match only */ 667781a868fSWei Yang bcomp = OpalPciBusAll; 668781a868fSWei Yang } 669781a868fSWei Yang rid_end = pe->rid + (count << 8); 670781a868fSWei Yang } else { 671781a868fSWei Yang if (pe->flags & PNV_IODA_PE_VF) 672781a868fSWei Yang parent = pe->parent_dev; 673781a868fSWei Yang else 674781a868fSWei Yang parent = pe->pdev->bus->self; 675781a868fSWei Yang bcomp = OpalPciBusAll; 676781a868fSWei Yang dcomp = OPAL_COMPARE_RID_DEVICE_NUMBER; 677781a868fSWei Yang fcomp = OPAL_COMPARE_RID_FUNCTION_NUMBER; 678781a868fSWei Yang rid_end = pe->rid + 1; 679781a868fSWei Yang } 680781a868fSWei Yang 681781a868fSWei Yang /* Clear the reverse map */ 682781a868fSWei Yang for (rid = pe->rid; rid < rid_end; rid++) 683781a868fSWei Yang phb->ioda.pe_rmap[rid] = 0; 684781a868fSWei Yang 685781a868fSWei Yang /* Release from all parents PELT-V */ 686781a868fSWei Yang while (parent) { 687781a868fSWei Yang struct pci_dn *pdn = pci_get_pdn(parent); 688781a868fSWei Yang if (pdn && pdn->pe_number != IODA_INVALID_PE) { 689781a868fSWei Yang rc = opal_pci_set_peltv(phb->opal_id, pdn->pe_number, 690781a868fSWei Yang pe->pe_number, OPAL_REMOVE_PE_FROM_DOMAIN); 691781a868fSWei Yang /* XXX What to do in case of error ? */ 692781a868fSWei Yang } 693781a868fSWei Yang parent = parent->bus->self; 694781a868fSWei Yang } 695781a868fSWei Yang 696f951e510SGavin Shan opal_pci_eeh_freeze_clear(phb->opal_id, pe->pe_number, 697781a868fSWei Yang OPAL_EEH_ACTION_CLEAR_FREEZE_ALL); 698781a868fSWei Yang 699781a868fSWei Yang /* Disassociate PE in PELT */ 700781a868fSWei Yang rc = opal_pci_set_peltv(phb->opal_id, pe->pe_number, 701781a868fSWei Yang pe->pe_number, OPAL_REMOVE_PE_FROM_DOMAIN); 702781a868fSWei Yang if (rc) 703781a868fSWei Yang pe_warn(pe, "OPAL error %ld remove self from PELTV\n", rc); 704781a868fSWei Yang rc = opal_pci_set_pe(phb->opal_id, pe->pe_number, pe->rid, 705781a868fSWei Yang bcomp, dcomp, fcomp, OPAL_UNMAP_PE); 706781a868fSWei Yang if (rc) 707781a868fSWei Yang pe_err(pe, "OPAL error %ld trying to setup PELT table\n", rc); 708781a868fSWei Yang 709781a868fSWei Yang pe->pbus = NULL; 710781a868fSWei Yang pe->pdev = NULL; 711781a868fSWei Yang pe->parent_dev = NULL; 712781a868fSWei Yang 713781a868fSWei Yang return 0; 714781a868fSWei Yang } 715781a868fSWei Yang #endif /* CONFIG_PCI_IOV */ 716781a868fSWei Yang 717cad5cef6SGreg Kroah-Hartman static int pnv_ioda_configure_pe(struct pnv_phb *phb, struct pnv_ioda_pe *pe) 718184cd4a3SBenjamin Herrenschmidt { 719184cd4a3SBenjamin Herrenschmidt struct pci_dev *parent; 720184cd4a3SBenjamin Herrenschmidt uint8_t bcomp, dcomp, fcomp; 721184cd4a3SBenjamin Herrenschmidt long rc, rid_end, rid; 722184cd4a3SBenjamin Herrenschmidt 723184cd4a3SBenjamin Herrenschmidt /* Bus validation ? */ 724184cd4a3SBenjamin Herrenschmidt if (pe->pbus) { 725184cd4a3SBenjamin Herrenschmidt int count; 726184cd4a3SBenjamin Herrenschmidt 727184cd4a3SBenjamin Herrenschmidt dcomp = OPAL_IGNORE_RID_DEVICE_NUMBER; 728184cd4a3SBenjamin Herrenschmidt fcomp = OPAL_IGNORE_RID_FUNCTION_NUMBER; 729184cd4a3SBenjamin Herrenschmidt parent = pe->pbus->self; 730fb446ad0SGavin Shan if (pe->flags & PNV_IODA_PE_BUS_ALL) 731b918c62eSYinghai Lu count = pe->pbus->busn_res.end - pe->pbus->busn_res.start + 1; 732fb446ad0SGavin Shan else 733fb446ad0SGavin Shan count = 1; 734fb446ad0SGavin Shan 735184cd4a3SBenjamin Herrenschmidt switch(count) { 736184cd4a3SBenjamin Herrenschmidt case 1: bcomp = OpalPciBusAll; break; 737184cd4a3SBenjamin Herrenschmidt case 2: bcomp = OpalPciBus7Bits; break; 738184cd4a3SBenjamin Herrenschmidt case 4: bcomp = OpalPciBus6Bits; break; 739184cd4a3SBenjamin Herrenschmidt case 8: bcomp = OpalPciBus5Bits; break; 740184cd4a3SBenjamin Herrenschmidt case 16: bcomp = OpalPciBus4Bits; break; 741184cd4a3SBenjamin Herrenschmidt case 32: bcomp = OpalPciBus3Bits; break; 742184cd4a3SBenjamin Herrenschmidt default: 743781a868fSWei Yang dev_err(&pe->pbus->dev, "Number of subordinate buses %d unsupported\n", 744781a868fSWei Yang count); 745184cd4a3SBenjamin Herrenschmidt /* Do an exact match only */ 746184cd4a3SBenjamin Herrenschmidt bcomp = OpalPciBusAll; 747184cd4a3SBenjamin Herrenschmidt } 748184cd4a3SBenjamin Herrenschmidt rid_end = pe->rid + (count << 8); 749184cd4a3SBenjamin Herrenschmidt } else { 750781a868fSWei Yang #ifdef CONFIG_PCI_IOV 751781a868fSWei Yang if (pe->flags & PNV_IODA_PE_VF) 752781a868fSWei Yang parent = pe->parent_dev; 753781a868fSWei Yang else 754781a868fSWei Yang #endif /* CONFIG_PCI_IOV */ 755184cd4a3SBenjamin Herrenschmidt parent = pe->pdev->bus->self; 756184cd4a3SBenjamin Herrenschmidt bcomp = OpalPciBusAll; 757184cd4a3SBenjamin Herrenschmidt dcomp = OPAL_COMPARE_RID_DEVICE_NUMBER; 758184cd4a3SBenjamin Herrenschmidt fcomp = OPAL_COMPARE_RID_FUNCTION_NUMBER; 759184cd4a3SBenjamin Herrenschmidt rid_end = pe->rid + 1; 760184cd4a3SBenjamin Herrenschmidt } 761184cd4a3SBenjamin Herrenschmidt 762631ad691SGavin Shan /* 763631ad691SGavin Shan * Associate PE in PELT. We need add the PE into the 764631ad691SGavin Shan * corresponding PELT-V as well. Otherwise, the error 765631ad691SGavin Shan * originated from the PE might contribute to other 766631ad691SGavin Shan * PEs. 767631ad691SGavin Shan */ 768184cd4a3SBenjamin Herrenschmidt rc = opal_pci_set_pe(phb->opal_id, pe->pe_number, pe->rid, 769184cd4a3SBenjamin Herrenschmidt bcomp, dcomp, fcomp, OPAL_MAP_PE); 770184cd4a3SBenjamin Herrenschmidt if (rc) { 771184cd4a3SBenjamin Herrenschmidt pe_err(pe, "OPAL error %ld trying to setup PELT table\n", rc); 772184cd4a3SBenjamin Herrenschmidt return -ENXIO; 773184cd4a3SBenjamin Herrenschmidt } 774631ad691SGavin Shan 7755d2aa710SAlistair Popple /* 7765d2aa710SAlistair Popple * Configure PELTV. NPUs don't have a PELTV table so skip 7775d2aa710SAlistair Popple * configuration on them. 7785d2aa710SAlistair Popple */ 7795d2aa710SAlistair Popple if (phb->type != PNV_PHB_NPU) 780b131a842SGavin Shan pnv_ioda_set_peltv(phb, pe, true); 781184cd4a3SBenjamin Herrenschmidt 782184cd4a3SBenjamin Herrenschmidt /* Setup reverse map */ 783184cd4a3SBenjamin Herrenschmidt for (rid = pe->rid; rid < rid_end; rid++) 784184cd4a3SBenjamin Herrenschmidt phb->ioda.pe_rmap[rid] = pe->pe_number; 785184cd4a3SBenjamin Herrenschmidt 786184cd4a3SBenjamin Herrenschmidt /* Setup one MVTs on IODA1 */ 7874773f76bSGavin Shan if (phb->type != PNV_PHB_IODA1) { 7884773f76bSGavin Shan pe->mve_number = 0; 7894773f76bSGavin Shan goto out; 7904773f76bSGavin Shan } 7914773f76bSGavin Shan 792184cd4a3SBenjamin Herrenschmidt pe->mve_number = pe->pe_number; 7934773f76bSGavin Shan rc = opal_pci_set_mve(phb->opal_id, pe->mve_number, pe->pe_number); 7944773f76bSGavin Shan if (rc != OPAL_SUCCESS) { 795184cd4a3SBenjamin Herrenschmidt pe_err(pe, "OPAL error %ld setting up MVE %d\n", 796184cd4a3SBenjamin Herrenschmidt rc, pe->mve_number); 797184cd4a3SBenjamin Herrenschmidt pe->mve_number = -1; 798184cd4a3SBenjamin Herrenschmidt } else { 799184cd4a3SBenjamin Herrenschmidt rc = opal_pci_set_mve_enable(phb->opal_id, 800cee72d5bSBenjamin Herrenschmidt pe->mve_number, OPAL_ENABLE_MVE); 801184cd4a3SBenjamin Herrenschmidt if (rc) { 802184cd4a3SBenjamin Herrenschmidt pe_err(pe, "OPAL error %ld enabling MVE %d\n", 803184cd4a3SBenjamin Herrenschmidt rc, pe->mve_number); 804184cd4a3SBenjamin Herrenschmidt pe->mve_number = -1; 805184cd4a3SBenjamin Herrenschmidt } 806184cd4a3SBenjamin Herrenschmidt } 807184cd4a3SBenjamin Herrenschmidt 8084773f76bSGavin Shan out: 809184cd4a3SBenjamin Herrenschmidt return 0; 810184cd4a3SBenjamin Herrenschmidt } 811184cd4a3SBenjamin Herrenschmidt 812cad5cef6SGreg Kroah-Hartman static void pnv_ioda_link_pe_by_weight(struct pnv_phb *phb, 813184cd4a3SBenjamin Herrenschmidt struct pnv_ioda_pe *pe) 814184cd4a3SBenjamin Herrenschmidt { 815184cd4a3SBenjamin Herrenschmidt struct pnv_ioda_pe *lpe; 816184cd4a3SBenjamin Herrenschmidt 8177ebdf956SGavin Shan list_for_each_entry(lpe, &phb->ioda.pe_dma_list, dma_link) { 818184cd4a3SBenjamin Herrenschmidt if (lpe->dma_weight < pe->dma_weight) { 8197ebdf956SGavin Shan list_add_tail(&pe->dma_link, &lpe->dma_link); 820184cd4a3SBenjamin Herrenschmidt return; 821184cd4a3SBenjamin Herrenschmidt } 822184cd4a3SBenjamin Herrenschmidt } 8237ebdf956SGavin Shan list_add_tail(&pe->dma_link, &phb->ioda.pe_dma_list); 824184cd4a3SBenjamin Herrenschmidt } 825184cd4a3SBenjamin Herrenschmidt 826184cd4a3SBenjamin Herrenschmidt static unsigned int pnv_ioda_dma_weight(struct pci_dev *dev) 827184cd4a3SBenjamin Herrenschmidt { 828184cd4a3SBenjamin Herrenschmidt /* This is quite simplistic. The "base" weight of a device 829184cd4a3SBenjamin Herrenschmidt * is 10. 0 means no DMA is to be accounted for it. 830184cd4a3SBenjamin Herrenschmidt */ 831184cd4a3SBenjamin Herrenschmidt 832184cd4a3SBenjamin Herrenschmidt /* If it's a bridge, no DMA */ 833184cd4a3SBenjamin Herrenschmidt if (dev->hdr_type != PCI_HEADER_TYPE_NORMAL) 834184cd4a3SBenjamin Herrenschmidt return 0; 835184cd4a3SBenjamin Herrenschmidt 836184cd4a3SBenjamin Herrenschmidt /* Reduce the weight of slow USB controllers */ 837184cd4a3SBenjamin Herrenschmidt if (dev->class == PCI_CLASS_SERIAL_USB_UHCI || 838184cd4a3SBenjamin Herrenschmidt dev->class == PCI_CLASS_SERIAL_USB_OHCI || 839184cd4a3SBenjamin Herrenschmidt dev->class == PCI_CLASS_SERIAL_USB_EHCI) 840184cd4a3SBenjamin Herrenschmidt return 3; 841184cd4a3SBenjamin Herrenschmidt 842184cd4a3SBenjamin Herrenschmidt /* Increase the weight of RAID (includes Obsidian) */ 843184cd4a3SBenjamin Herrenschmidt if ((dev->class >> 8) == PCI_CLASS_STORAGE_RAID) 844184cd4a3SBenjamin Herrenschmidt return 15; 845184cd4a3SBenjamin Herrenschmidt 846184cd4a3SBenjamin Herrenschmidt /* Default */ 847184cd4a3SBenjamin Herrenschmidt return 10; 848184cd4a3SBenjamin Herrenschmidt } 849184cd4a3SBenjamin Herrenschmidt 850781a868fSWei Yang #ifdef CONFIG_PCI_IOV 851781a868fSWei Yang static int pnv_pci_vf_resource_shift(struct pci_dev *dev, int offset) 852781a868fSWei Yang { 853781a868fSWei Yang struct pci_dn *pdn = pci_get_pdn(dev); 854781a868fSWei Yang int i; 855781a868fSWei Yang struct resource *res, res2; 856781a868fSWei Yang resource_size_t size; 857781a868fSWei Yang u16 num_vfs; 858781a868fSWei Yang 859781a868fSWei Yang if (!dev->is_physfn) 860781a868fSWei Yang return -EINVAL; 861781a868fSWei Yang 862781a868fSWei Yang /* 863781a868fSWei Yang * "offset" is in VFs. The M64 windows are sized so that when they 864781a868fSWei Yang * are segmented, each segment is the same size as the IOV BAR. 865781a868fSWei Yang * Each segment is in a separate PE, and the high order bits of the 866781a868fSWei Yang * address are the PE number. Therefore, each VF's BAR is in a 867781a868fSWei Yang * separate PE, and changing the IOV BAR start address changes the 868781a868fSWei Yang * range of PEs the VFs are in. 869781a868fSWei Yang */ 870781a868fSWei Yang num_vfs = pdn->num_vfs; 871781a868fSWei Yang for (i = 0; i < PCI_SRIOV_NUM_BARS; i++) { 872781a868fSWei Yang res = &dev->resource[i + PCI_IOV_RESOURCES]; 873781a868fSWei Yang if (!res->flags || !res->parent) 874781a868fSWei Yang continue; 875781a868fSWei Yang 876781a868fSWei Yang /* 877781a868fSWei Yang * The actual IOV BAR range is determined by the start address 878781a868fSWei Yang * and the actual size for num_vfs VFs BAR. This check is to 879781a868fSWei Yang * make sure that after shifting, the range will not overlap 880781a868fSWei Yang * with another device. 881781a868fSWei Yang */ 882781a868fSWei Yang size = pci_iov_resource_size(dev, i + PCI_IOV_RESOURCES); 883781a868fSWei Yang res2.flags = res->flags; 884781a868fSWei Yang res2.start = res->start + (size * offset); 885781a868fSWei Yang res2.end = res2.start + (size * num_vfs) - 1; 886781a868fSWei Yang 887781a868fSWei Yang if (res2.end > res->end) { 888781a868fSWei Yang dev_err(&dev->dev, "VF BAR%d: %pR would extend past %pR (trying to enable %d VFs shifted by %d)\n", 889781a868fSWei Yang i, &res2, res, num_vfs, offset); 890781a868fSWei Yang return -EBUSY; 891781a868fSWei Yang } 892781a868fSWei Yang } 893781a868fSWei Yang 894781a868fSWei Yang /* 895781a868fSWei Yang * After doing so, there would be a "hole" in the /proc/iomem when 896781a868fSWei Yang * offset is a positive value. It looks like the device return some 897781a868fSWei Yang * mmio back to the system, which actually no one could use it. 898781a868fSWei Yang */ 899781a868fSWei Yang for (i = 0; i < PCI_SRIOV_NUM_BARS; i++) { 900781a868fSWei Yang res = &dev->resource[i + PCI_IOV_RESOURCES]; 901781a868fSWei Yang if (!res->flags || !res->parent) 902781a868fSWei Yang continue; 903781a868fSWei Yang 904781a868fSWei Yang size = pci_iov_resource_size(dev, i + PCI_IOV_RESOURCES); 905781a868fSWei Yang res2 = *res; 906781a868fSWei Yang res->start += size * offset; 907781a868fSWei Yang 90874703cc4SWei Yang dev_info(&dev->dev, "VF BAR%d: %pR shifted to %pR (%sabling %d VFs shifted by %d)\n", 90974703cc4SWei Yang i, &res2, res, (offset > 0) ? "En" : "Dis", 91074703cc4SWei Yang num_vfs, offset); 911781a868fSWei Yang pci_update_resource(dev, i + PCI_IOV_RESOURCES); 912781a868fSWei Yang } 913781a868fSWei Yang return 0; 914781a868fSWei Yang } 915781a868fSWei Yang #endif /* CONFIG_PCI_IOV */ 916781a868fSWei Yang 917cad5cef6SGreg Kroah-Hartman static struct pnv_ioda_pe *pnv_ioda_setup_dev_PE(struct pci_dev *dev) 918184cd4a3SBenjamin Herrenschmidt { 919184cd4a3SBenjamin Herrenschmidt struct pci_controller *hose = pci_bus_to_host(dev->bus); 920184cd4a3SBenjamin Herrenschmidt struct pnv_phb *phb = hose->private_data; 921b72c1f65SBenjamin Herrenschmidt struct pci_dn *pdn = pci_get_pdn(dev); 922184cd4a3SBenjamin Herrenschmidt struct pnv_ioda_pe *pe; 923689ee8c9SGavin Shan unsigned int pe_num; 924184cd4a3SBenjamin Herrenschmidt 925184cd4a3SBenjamin Herrenschmidt if (!pdn) { 926184cd4a3SBenjamin Herrenschmidt pr_err("%s: Device tree node not associated properly\n", 927184cd4a3SBenjamin Herrenschmidt pci_name(dev)); 928184cd4a3SBenjamin Herrenschmidt return NULL; 929184cd4a3SBenjamin Herrenschmidt } 930184cd4a3SBenjamin Herrenschmidt if (pdn->pe_number != IODA_INVALID_PE) 931184cd4a3SBenjamin Herrenschmidt return NULL; 932184cd4a3SBenjamin Herrenschmidt 933184cd4a3SBenjamin Herrenschmidt pe_num = pnv_ioda_alloc_pe(phb); 934184cd4a3SBenjamin Herrenschmidt if (pe_num == IODA_INVALID_PE) { 935184cd4a3SBenjamin Herrenschmidt pr_warning("%s: Not enough PE# available, disabling device\n", 936184cd4a3SBenjamin Herrenschmidt pci_name(dev)); 937184cd4a3SBenjamin Herrenschmidt return NULL; 938184cd4a3SBenjamin Herrenschmidt } 939184cd4a3SBenjamin Herrenschmidt 940184cd4a3SBenjamin Herrenschmidt /* NOTE: We get only one ref to the pci_dev for the pdn, not for the 941184cd4a3SBenjamin Herrenschmidt * pointer in the PE data structure, both should be destroyed at the 942184cd4a3SBenjamin Herrenschmidt * same time. However, this needs to be looked at more closely again 943184cd4a3SBenjamin Herrenschmidt * once we actually start removing things (Hotplug, SR-IOV, ...) 944184cd4a3SBenjamin Herrenschmidt * 945184cd4a3SBenjamin Herrenschmidt * At some point we want to remove the PDN completely anyways 946184cd4a3SBenjamin Herrenschmidt */ 947184cd4a3SBenjamin Herrenschmidt pe = &phb->ioda.pe_array[pe_num]; 948184cd4a3SBenjamin Herrenschmidt pci_dev_get(dev); 949184cd4a3SBenjamin Herrenschmidt pdn->pcidev = dev; 950184cd4a3SBenjamin Herrenschmidt pdn->pe_number = pe_num; 9515d2aa710SAlistair Popple pe->flags = PNV_IODA_PE_DEV; 952184cd4a3SBenjamin Herrenschmidt pe->pdev = dev; 953184cd4a3SBenjamin Herrenschmidt pe->pbus = NULL; 954184cd4a3SBenjamin Herrenschmidt pe->tce32_seg = -1; 955184cd4a3SBenjamin Herrenschmidt pe->mve_number = -1; 956184cd4a3SBenjamin Herrenschmidt pe->rid = dev->bus->number << 8 | pdn->devfn; 957184cd4a3SBenjamin Herrenschmidt 958184cd4a3SBenjamin Herrenschmidt pe_info(pe, "Associated device to PE\n"); 959184cd4a3SBenjamin Herrenschmidt 960184cd4a3SBenjamin Herrenschmidt if (pnv_ioda_configure_pe(phb, pe)) { 961184cd4a3SBenjamin Herrenschmidt /* XXX What do we do here ? */ 962184cd4a3SBenjamin Herrenschmidt if (pe_num) 963184cd4a3SBenjamin Herrenschmidt pnv_ioda_free_pe(phb, pe_num); 964184cd4a3SBenjamin Herrenschmidt pdn->pe_number = IODA_INVALID_PE; 965184cd4a3SBenjamin Herrenschmidt pe->pdev = NULL; 966184cd4a3SBenjamin Herrenschmidt pci_dev_put(dev); 967184cd4a3SBenjamin Herrenschmidt return NULL; 968184cd4a3SBenjamin Herrenschmidt } 969184cd4a3SBenjamin Herrenschmidt 970184cd4a3SBenjamin Herrenschmidt /* Assign a DMA weight to the device */ 971184cd4a3SBenjamin Herrenschmidt pe->dma_weight = pnv_ioda_dma_weight(dev); 972184cd4a3SBenjamin Herrenschmidt if (pe->dma_weight != 0) { 973184cd4a3SBenjamin Herrenschmidt phb->ioda.dma_weight += pe->dma_weight; 974184cd4a3SBenjamin Herrenschmidt phb->ioda.dma_pe_count++; 975184cd4a3SBenjamin Herrenschmidt } 976184cd4a3SBenjamin Herrenschmidt 977184cd4a3SBenjamin Herrenschmidt /* Link the PE */ 978184cd4a3SBenjamin Herrenschmidt pnv_ioda_link_pe_by_weight(phb, pe); 979184cd4a3SBenjamin Herrenschmidt 980184cd4a3SBenjamin Herrenschmidt return pe; 981184cd4a3SBenjamin Herrenschmidt } 982184cd4a3SBenjamin Herrenschmidt 983184cd4a3SBenjamin Herrenschmidt static void pnv_ioda_setup_same_PE(struct pci_bus *bus, struct pnv_ioda_pe *pe) 984184cd4a3SBenjamin Herrenschmidt { 985184cd4a3SBenjamin Herrenschmidt struct pci_dev *dev; 986184cd4a3SBenjamin Herrenschmidt 987184cd4a3SBenjamin Herrenschmidt list_for_each_entry(dev, &bus->devices, bus_list) { 988b72c1f65SBenjamin Herrenschmidt struct pci_dn *pdn = pci_get_pdn(dev); 989184cd4a3SBenjamin Herrenschmidt 990184cd4a3SBenjamin Herrenschmidt if (pdn == NULL) { 991184cd4a3SBenjamin Herrenschmidt pr_warn("%s: No device node associated with device !\n", 992184cd4a3SBenjamin Herrenschmidt pci_name(dev)); 993184cd4a3SBenjamin Herrenschmidt continue; 994184cd4a3SBenjamin Herrenschmidt } 99594973b24SAlistair Popple pdn->pcidev = dev; 996184cd4a3SBenjamin Herrenschmidt pdn->pe_number = pe->pe_number; 997184cd4a3SBenjamin Herrenschmidt pe->dma_weight += pnv_ioda_dma_weight(dev); 998fb446ad0SGavin Shan if ((pe->flags & PNV_IODA_PE_BUS_ALL) && dev->subordinate) 999184cd4a3SBenjamin Herrenschmidt pnv_ioda_setup_same_PE(dev->subordinate, pe); 1000184cd4a3SBenjamin Herrenschmidt } 1001184cd4a3SBenjamin Herrenschmidt } 1002184cd4a3SBenjamin Herrenschmidt 1003fb446ad0SGavin Shan /* 1004fb446ad0SGavin Shan * There're 2 types of PCI bus sensitive PEs: One that is compromised of 1005fb446ad0SGavin Shan * single PCI bus. Another one that contains the primary PCI bus and its 1006fb446ad0SGavin Shan * subordinate PCI devices and buses. The second type of PE is normally 1007fb446ad0SGavin Shan * orgiriated by PCIe-to-PCI bridge or PLX switch downstream ports. 1008fb446ad0SGavin Shan */ 1009d1203852SGavin Shan static void pnv_ioda_setup_bus_PE(struct pci_bus *bus, bool all) 1010184cd4a3SBenjamin Herrenschmidt { 1011fb446ad0SGavin Shan struct pci_controller *hose = pci_bus_to_host(bus); 1012184cd4a3SBenjamin Herrenschmidt struct pnv_phb *phb = hose->private_data; 1013184cd4a3SBenjamin Herrenschmidt struct pnv_ioda_pe *pe; 1014689ee8c9SGavin Shan unsigned int pe_num = IODA_INVALID_PE; 1015184cd4a3SBenjamin Herrenschmidt 1016262af557SGuo Chao /* Check if PE is determined by M64 */ 1017262af557SGuo Chao if (phb->pick_m64_pe) 101826ba248dSGavin Shan pe_num = phb->pick_m64_pe(bus, all); 1019262af557SGuo Chao 1020262af557SGuo Chao /* The PE number isn't pinned by M64 */ 1021262af557SGuo Chao if (pe_num == IODA_INVALID_PE) 1022184cd4a3SBenjamin Herrenschmidt pe_num = pnv_ioda_alloc_pe(phb); 1023262af557SGuo Chao 1024184cd4a3SBenjamin Herrenschmidt if (pe_num == IODA_INVALID_PE) { 1025fb446ad0SGavin Shan pr_warning("%s: Not enough PE# available for PCI bus %04x:%02x\n", 1026fb446ad0SGavin Shan __func__, pci_domain_nr(bus), bus->number); 1027184cd4a3SBenjamin Herrenschmidt return; 1028184cd4a3SBenjamin Herrenschmidt } 1029184cd4a3SBenjamin Herrenschmidt 1030184cd4a3SBenjamin Herrenschmidt pe = &phb->ioda.pe_array[pe_num]; 1031262af557SGuo Chao pe->flags |= (all ? PNV_IODA_PE_BUS_ALL : PNV_IODA_PE_BUS); 1032184cd4a3SBenjamin Herrenschmidt pe->pbus = bus; 1033184cd4a3SBenjamin Herrenschmidt pe->pdev = NULL; 1034184cd4a3SBenjamin Herrenschmidt pe->tce32_seg = -1; 1035184cd4a3SBenjamin Herrenschmidt pe->mve_number = -1; 1036b918c62eSYinghai Lu pe->rid = bus->busn_res.start << 8; 1037184cd4a3SBenjamin Herrenschmidt pe->dma_weight = 0; 1038184cd4a3SBenjamin Herrenschmidt 1039fb446ad0SGavin Shan if (all) 1040fb446ad0SGavin Shan pe_info(pe, "Secondary bus %d..%d associated with PE#%d\n", 1041fb446ad0SGavin Shan bus->busn_res.start, bus->busn_res.end, pe_num); 1042fb446ad0SGavin Shan else 1043fb446ad0SGavin Shan pe_info(pe, "Secondary bus %d associated with PE#%d\n", 1044fb446ad0SGavin Shan bus->busn_res.start, pe_num); 1045184cd4a3SBenjamin Herrenschmidt 1046184cd4a3SBenjamin Herrenschmidt if (pnv_ioda_configure_pe(phb, pe)) { 1047184cd4a3SBenjamin Herrenschmidt /* XXX What do we do here ? */ 1048184cd4a3SBenjamin Herrenschmidt if (pe_num) 1049184cd4a3SBenjamin Herrenschmidt pnv_ioda_free_pe(phb, pe_num); 1050184cd4a3SBenjamin Herrenschmidt pe->pbus = NULL; 1051184cd4a3SBenjamin Herrenschmidt return; 1052184cd4a3SBenjamin Herrenschmidt } 1053184cd4a3SBenjamin Herrenschmidt 1054184cd4a3SBenjamin Herrenschmidt /* Associate it with all child devices */ 1055184cd4a3SBenjamin Herrenschmidt pnv_ioda_setup_same_PE(bus, pe); 1056184cd4a3SBenjamin Herrenschmidt 10577ebdf956SGavin Shan /* Put PE to the list */ 10587ebdf956SGavin Shan list_add_tail(&pe->list, &phb->ioda.pe_list); 10597ebdf956SGavin Shan 1060184cd4a3SBenjamin Herrenschmidt /* Account for one DMA PE if at least one DMA capable device exist 1061184cd4a3SBenjamin Herrenschmidt * below the bridge 1062184cd4a3SBenjamin Herrenschmidt */ 1063184cd4a3SBenjamin Herrenschmidt if (pe->dma_weight != 0) { 1064184cd4a3SBenjamin Herrenschmidt phb->ioda.dma_weight += pe->dma_weight; 1065184cd4a3SBenjamin Herrenschmidt phb->ioda.dma_pe_count++; 1066184cd4a3SBenjamin Herrenschmidt } 1067184cd4a3SBenjamin Herrenschmidt 1068184cd4a3SBenjamin Herrenschmidt /* Link the PE */ 1069184cd4a3SBenjamin Herrenschmidt pnv_ioda_link_pe_by_weight(phb, pe); 1070184cd4a3SBenjamin Herrenschmidt } 1071184cd4a3SBenjamin Herrenschmidt 1072b521549aSAlistair Popple static struct pnv_ioda_pe *pnv_ioda_setup_npu_PE(struct pci_dev *npu_pdev) 10735d2aa710SAlistair Popple { 1074b521549aSAlistair Popple int pe_num, found_pe = false, rc; 1075b521549aSAlistair Popple long rid; 1076b521549aSAlistair Popple struct pnv_ioda_pe *pe; 1077b521549aSAlistair Popple struct pci_dev *gpu_pdev; 1078b521549aSAlistair Popple struct pci_dn *npu_pdn; 1079b521549aSAlistair Popple struct pci_controller *hose = pci_bus_to_host(npu_pdev->bus); 1080b521549aSAlistair Popple struct pnv_phb *phb = hose->private_data; 1081b521549aSAlistair Popple 1082b521549aSAlistair Popple /* 1083b521549aSAlistair Popple * Due to a hardware errata PE#0 on the NPU is reserved for 1084b521549aSAlistair Popple * error handling. This means we only have three PEs remaining 1085b521549aSAlistair Popple * which need to be assigned to four links, implying some 1086b521549aSAlistair Popple * links must share PEs. 1087b521549aSAlistair Popple * 1088b521549aSAlistair Popple * To achieve this we assign PEs such that NPUs linking the 1089b521549aSAlistair Popple * same GPU get assigned the same PE. 1090b521549aSAlistair Popple */ 1091b521549aSAlistair Popple gpu_pdev = pnv_pci_get_gpu_dev(npu_pdev); 109292b8f137SGavin Shan for (pe_num = 0; pe_num < phb->ioda.total_pe_num; pe_num++) { 1093b521549aSAlistair Popple pe = &phb->ioda.pe_array[pe_num]; 1094b521549aSAlistair Popple if (!pe->pdev) 1095b521549aSAlistair Popple continue; 1096b521549aSAlistair Popple 1097b521549aSAlistair Popple if (pnv_pci_get_gpu_dev(pe->pdev) == gpu_pdev) { 1098b521549aSAlistair Popple /* 1099b521549aSAlistair Popple * This device has the same peer GPU so should 1100b521549aSAlistair Popple * be assigned the same PE as the existing 1101b521549aSAlistair Popple * peer NPU. 1102b521549aSAlistair Popple */ 1103b521549aSAlistair Popple dev_info(&npu_pdev->dev, 1104b521549aSAlistair Popple "Associating to existing PE %d\n", pe_num); 1105b521549aSAlistair Popple pci_dev_get(npu_pdev); 1106b521549aSAlistair Popple npu_pdn = pci_get_pdn(npu_pdev); 1107b521549aSAlistair Popple rid = npu_pdev->bus->number << 8 | npu_pdn->devfn; 1108b521549aSAlistair Popple npu_pdn->pcidev = npu_pdev; 1109b521549aSAlistair Popple npu_pdn->pe_number = pe_num; 1110b521549aSAlistair Popple pe->dma_weight += pnv_ioda_dma_weight(npu_pdev); 1111b521549aSAlistair Popple phb->ioda.pe_rmap[rid] = pe->pe_number; 1112b521549aSAlistair Popple 1113b521549aSAlistair Popple /* Map the PE to this link */ 1114b521549aSAlistair Popple rc = opal_pci_set_pe(phb->opal_id, pe_num, rid, 1115b521549aSAlistair Popple OpalPciBusAll, 1116b521549aSAlistair Popple OPAL_COMPARE_RID_DEVICE_NUMBER, 1117b521549aSAlistair Popple OPAL_COMPARE_RID_FUNCTION_NUMBER, 1118b521549aSAlistair Popple OPAL_MAP_PE); 1119b521549aSAlistair Popple WARN_ON(rc != OPAL_SUCCESS); 1120b521549aSAlistair Popple found_pe = true; 1121b521549aSAlistair Popple break; 1122b521549aSAlistair Popple } 1123b521549aSAlistair Popple } 1124b521549aSAlistair Popple 1125b521549aSAlistair Popple if (!found_pe) 1126b521549aSAlistair Popple /* 1127b521549aSAlistair Popple * Could not find an existing PE so allocate a new 1128b521549aSAlistair Popple * one. 1129b521549aSAlistair Popple */ 1130b521549aSAlistair Popple return pnv_ioda_setup_dev_PE(npu_pdev); 1131b521549aSAlistair Popple else 1132b521549aSAlistair Popple return pe; 1133b521549aSAlistair Popple } 1134b521549aSAlistair Popple 1135b521549aSAlistair Popple static void pnv_ioda_setup_npu_PEs(struct pci_bus *bus) 1136b521549aSAlistair Popple { 11375d2aa710SAlistair Popple struct pci_dev *pdev; 11385d2aa710SAlistair Popple 11395d2aa710SAlistair Popple list_for_each_entry(pdev, &bus->devices, bus_list) 1140b521549aSAlistair Popple pnv_ioda_setup_npu_PE(pdev); 11415d2aa710SAlistair Popple } 11425d2aa710SAlistair Popple 1143cad5cef6SGreg Kroah-Hartman static void pnv_ioda_setup_PEs(struct pci_bus *bus) 1144184cd4a3SBenjamin Herrenschmidt { 1145184cd4a3SBenjamin Herrenschmidt struct pci_dev *dev; 1146fb446ad0SGavin Shan 1147d1203852SGavin Shan pnv_ioda_setup_bus_PE(bus, false); 1148184cd4a3SBenjamin Herrenschmidt 1149184cd4a3SBenjamin Herrenschmidt list_for_each_entry(dev, &bus->devices, bus_list) { 1150fb446ad0SGavin Shan if (dev->subordinate) { 115162f87c0eSYijing Wang if (pci_pcie_type(dev) == PCI_EXP_TYPE_PCI_BRIDGE) 1152d1203852SGavin Shan pnv_ioda_setup_bus_PE(dev->subordinate, true); 1153fb446ad0SGavin Shan else 1154184cd4a3SBenjamin Herrenschmidt pnv_ioda_setup_PEs(dev->subordinate); 1155184cd4a3SBenjamin Herrenschmidt } 1156184cd4a3SBenjamin Herrenschmidt } 1157fb446ad0SGavin Shan } 1158fb446ad0SGavin Shan 1159fb446ad0SGavin Shan /* 1160fb446ad0SGavin Shan * Configure PEs so that the downstream PCI buses and devices 1161fb446ad0SGavin Shan * could have their associated PE#. Unfortunately, we didn't 1162fb446ad0SGavin Shan * figure out the way to identify the PLX bridge yet. So we 1163fb446ad0SGavin Shan * simply put the PCI bus and the subordinate behind the root 1164fb446ad0SGavin Shan * port to PE# here. The game rule here is expected to be changed 1165fb446ad0SGavin Shan * as soon as we can detected PLX bridge correctly. 1166fb446ad0SGavin Shan */ 1167cad5cef6SGreg Kroah-Hartman static void pnv_pci_ioda_setup_PEs(void) 1168fb446ad0SGavin Shan { 1169fb446ad0SGavin Shan struct pci_controller *hose, *tmp; 1170262af557SGuo Chao struct pnv_phb *phb; 1171fb446ad0SGavin Shan 1172fb446ad0SGavin Shan list_for_each_entry_safe(hose, tmp, &hose_list, list_node) { 1173262af557SGuo Chao phb = hose->private_data; 1174262af557SGuo Chao 1175262af557SGuo Chao /* M64 layout might affect PE allocation */ 11765ef73567SGavin Shan if (phb->reserve_m64_pe) 117796a2f92bSGavin Shan phb->reserve_m64_pe(hose->bus, NULL, true); 1178262af557SGuo Chao 11795d2aa710SAlistair Popple /* 11805d2aa710SAlistair Popple * On NPU PHB, we expect separate PEs for individual PCI 11815d2aa710SAlistair Popple * functions. PCI bus dependent PEs are required for the 11825d2aa710SAlistair Popple * remaining types of PHBs. 11835d2aa710SAlistair Popple */ 118408f48f32SAlistair Popple if (phb->type == PNV_PHB_NPU) { 118508f48f32SAlistair Popple /* PE#0 is needed for error reporting */ 118608f48f32SAlistair Popple pnv_ioda_reserve_pe(phb, 0); 1187b521549aSAlistair Popple pnv_ioda_setup_npu_PEs(hose->bus); 118808f48f32SAlistair Popple } else 1189fb446ad0SGavin Shan pnv_ioda_setup_PEs(hose->bus); 1190fb446ad0SGavin Shan } 1191fb446ad0SGavin Shan } 1192184cd4a3SBenjamin Herrenschmidt 1193a8b2f828SGavin Shan #ifdef CONFIG_PCI_IOV 1194ee8222feSWei Yang static int pnv_pci_vf_release_m64(struct pci_dev *pdev, u16 num_vfs) 1195781a868fSWei Yang { 1196781a868fSWei Yang struct pci_bus *bus; 1197781a868fSWei Yang struct pci_controller *hose; 1198781a868fSWei Yang struct pnv_phb *phb; 1199781a868fSWei Yang struct pci_dn *pdn; 120002639b0eSWei Yang int i, j; 1201ee8222feSWei Yang int m64_bars; 1202781a868fSWei Yang 1203781a868fSWei Yang bus = pdev->bus; 1204781a868fSWei Yang hose = pci_bus_to_host(bus); 1205781a868fSWei Yang phb = hose->private_data; 1206781a868fSWei Yang pdn = pci_get_pdn(pdev); 1207781a868fSWei Yang 1208ee8222feSWei Yang if (pdn->m64_single_mode) 1209ee8222feSWei Yang m64_bars = num_vfs; 1210ee8222feSWei Yang else 1211ee8222feSWei Yang m64_bars = 1; 1212ee8222feSWei Yang 121302639b0eSWei Yang for (i = 0; i < PCI_SRIOV_NUM_BARS; i++) 1214ee8222feSWei Yang for (j = 0; j < m64_bars; j++) { 1215ee8222feSWei Yang if (pdn->m64_map[j][i] == IODA_INVALID_M64) 1216781a868fSWei Yang continue; 1217781a868fSWei Yang opal_pci_phb_mmio_enable(phb->opal_id, 1218ee8222feSWei Yang OPAL_M64_WINDOW_TYPE, pdn->m64_map[j][i], 0); 1219ee8222feSWei Yang clear_bit(pdn->m64_map[j][i], &phb->ioda.m64_bar_alloc); 1220ee8222feSWei Yang pdn->m64_map[j][i] = IODA_INVALID_M64; 1221781a868fSWei Yang } 1222781a868fSWei Yang 1223ee8222feSWei Yang kfree(pdn->m64_map); 1224781a868fSWei Yang return 0; 1225781a868fSWei Yang } 1226781a868fSWei Yang 122702639b0eSWei Yang static int pnv_pci_vf_assign_m64(struct pci_dev *pdev, u16 num_vfs) 1228781a868fSWei Yang { 1229781a868fSWei Yang struct pci_bus *bus; 1230781a868fSWei Yang struct pci_controller *hose; 1231781a868fSWei Yang struct pnv_phb *phb; 1232781a868fSWei Yang struct pci_dn *pdn; 1233781a868fSWei Yang unsigned int win; 1234781a868fSWei Yang struct resource *res; 123502639b0eSWei Yang int i, j; 1236781a868fSWei Yang int64_t rc; 123702639b0eSWei Yang int total_vfs; 123802639b0eSWei Yang resource_size_t size, start; 123902639b0eSWei Yang int pe_num; 1240ee8222feSWei Yang int m64_bars; 1241781a868fSWei Yang 1242781a868fSWei Yang bus = pdev->bus; 1243781a868fSWei Yang hose = pci_bus_to_host(bus); 1244781a868fSWei Yang phb = hose->private_data; 1245781a868fSWei Yang pdn = pci_get_pdn(pdev); 124602639b0eSWei Yang total_vfs = pci_sriov_get_totalvfs(pdev); 1247781a868fSWei Yang 1248ee8222feSWei Yang if (pdn->m64_single_mode) 1249ee8222feSWei Yang m64_bars = num_vfs; 1250ee8222feSWei Yang else 1251ee8222feSWei Yang m64_bars = 1; 125202639b0eSWei Yang 1253ee8222feSWei Yang pdn->m64_map = kmalloc(sizeof(*pdn->m64_map) * m64_bars, GFP_KERNEL); 1254ee8222feSWei Yang if (!pdn->m64_map) 1255ee8222feSWei Yang return -ENOMEM; 1256ee8222feSWei Yang /* Initialize the m64_map to IODA_INVALID_M64 */ 1257ee8222feSWei Yang for (i = 0; i < m64_bars ; i++) 1258ee8222feSWei Yang for (j = 0; j < PCI_SRIOV_NUM_BARS; j++) 1259ee8222feSWei Yang pdn->m64_map[i][j] = IODA_INVALID_M64; 1260ee8222feSWei Yang 1261781a868fSWei Yang 1262781a868fSWei Yang for (i = 0; i < PCI_SRIOV_NUM_BARS; i++) { 1263781a868fSWei Yang res = &pdev->resource[i + PCI_IOV_RESOURCES]; 1264781a868fSWei Yang if (!res->flags || !res->parent) 1265781a868fSWei Yang continue; 1266781a868fSWei Yang 1267ee8222feSWei Yang for (j = 0; j < m64_bars; j++) { 1268781a868fSWei Yang do { 1269781a868fSWei Yang win = find_next_zero_bit(&phb->ioda.m64_bar_alloc, 1270781a868fSWei Yang phb->ioda.m64_bar_idx + 1, 0); 1271781a868fSWei Yang 1272781a868fSWei Yang if (win >= phb->ioda.m64_bar_idx + 1) 1273781a868fSWei Yang goto m64_failed; 1274781a868fSWei Yang } while (test_and_set_bit(win, &phb->ioda.m64_bar_alloc)); 1275781a868fSWei Yang 1276ee8222feSWei Yang pdn->m64_map[j][i] = win; 127702639b0eSWei Yang 1278ee8222feSWei Yang if (pdn->m64_single_mode) { 127902639b0eSWei Yang size = pci_iov_resource_size(pdev, 128002639b0eSWei Yang PCI_IOV_RESOURCES + i); 128102639b0eSWei Yang start = res->start + size * j; 128202639b0eSWei Yang } else { 128302639b0eSWei Yang size = resource_size(res); 128402639b0eSWei Yang start = res->start; 128502639b0eSWei Yang } 1286781a868fSWei Yang 1287781a868fSWei Yang /* Map the M64 here */ 1288ee8222feSWei Yang if (pdn->m64_single_mode) { 1289be283eebSWei Yang pe_num = pdn->pe_num_map[j]; 129002639b0eSWei Yang rc = opal_pci_map_pe_mmio_window(phb->opal_id, 129102639b0eSWei Yang pe_num, OPAL_M64_WINDOW_TYPE, 1292ee8222feSWei Yang pdn->m64_map[j][i], 0); 129302639b0eSWei Yang } 129402639b0eSWei Yang 1295781a868fSWei Yang rc = opal_pci_set_phb_mem_window(phb->opal_id, 1296781a868fSWei Yang OPAL_M64_WINDOW_TYPE, 1297ee8222feSWei Yang pdn->m64_map[j][i], 129802639b0eSWei Yang start, 1299781a868fSWei Yang 0, /* unused */ 130002639b0eSWei Yang size); 130102639b0eSWei Yang 130202639b0eSWei Yang 1303781a868fSWei Yang if (rc != OPAL_SUCCESS) { 1304781a868fSWei Yang dev_err(&pdev->dev, "Failed to map M64 window #%d: %lld\n", 1305781a868fSWei Yang win, rc); 1306781a868fSWei Yang goto m64_failed; 1307781a868fSWei Yang } 1308781a868fSWei Yang 1309ee8222feSWei Yang if (pdn->m64_single_mode) 1310781a868fSWei Yang rc = opal_pci_phb_mmio_enable(phb->opal_id, 1311ee8222feSWei Yang OPAL_M64_WINDOW_TYPE, pdn->m64_map[j][i], 2); 131202639b0eSWei Yang else 131302639b0eSWei Yang rc = opal_pci_phb_mmio_enable(phb->opal_id, 1314ee8222feSWei Yang OPAL_M64_WINDOW_TYPE, pdn->m64_map[j][i], 1); 131502639b0eSWei Yang 1316781a868fSWei Yang if (rc != OPAL_SUCCESS) { 1317781a868fSWei Yang dev_err(&pdev->dev, "Failed to enable M64 window #%d: %llx\n", 1318781a868fSWei Yang win, rc); 1319781a868fSWei Yang goto m64_failed; 1320781a868fSWei Yang } 1321781a868fSWei Yang } 132202639b0eSWei Yang } 1323781a868fSWei Yang return 0; 1324781a868fSWei Yang 1325781a868fSWei Yang m64_failed: 1326ee8222feSWei Yang pnv_pci_vf_release_m64(pdev, num_vfs); 1327781a868fSWei Yang return -EBUSY; 1328781a868fSWei Yang } 1329781a868fSWei Yang 1330c035e37bSAlexey Kardashevskiy static long pnv_pci_ioda2_unset_window(struct iommu_table_group *table_group, 1331c035e37bSAlexey Kardashevskiy int num); 1332c035e37bSAlexey Kardashevskiy static void pnv_pci_ioda2_set_bypass(struct pnv_ioda_pe *pe, bool enable); 1333c035e37bSAlexey Kardashevskiy 1334781a868fSWei Yang static void pnv_pci_ioda2_release_dma_pe(struct pci_dev *dev, struct pnv_ioda_pe *pe) 1335781a868fSWei Yang { 1336781a868fSWei Yang struct iommu_table *tbl; 1337781a868fSWei Yang int64_t rc; 1338781a868fSWei Yang 1339b348aa65SAlexey Kardashevskiy tbl = pe->table_group.tables[0]; 1340c035e37bSAlexey Kardashevskiy rc = pnv_pci_ioda2_unset_window(&pe->table_group, 0); 1341781a868fSWei Yang if (rc) 1342781a868fSWei Yang pe_warn(pe, "OPAL error %ld release DMA window\n", rc); 1343781a868fSWei Yang 1344c035e37bSAlexey Kardashevskiy pnv_pci_ioda2_set_bypass(pe, false); 13450eaf4defSAlexey Kardashevskiy if (pe->table_group.group) { 13460eaf4defSAlexey Kardashevskiy iommu_group_put(pe->table_group.group); 13470eaf4defSAlexey Kardashevskiy BUG_ON(pe->table_group.group); 1348ac9a5889SAlexey Kardashevskiy } 1349aca6913fSAlexey Kardashevskiy pnv_pci_ioda2_table_free_pages(tbl); 1350781a868fSWei Yang iommu_free_table(tbl, of_node_full_name(dev->dev.of_node)); 1351781a868fSWei Yang } 1352781a868fSWei Yang 1353ee8222feSWei Yang static void pnv_ioda_release_vf_PE(struct pci_dev *pdev) 1354781a868fSWei Yang { 1355781a868fSWei Yang struct pci_bus *bus; 1356781a868fSWei Yang struct pci_controller *hose; 1357781a868fSWei Yang struct pnv_phb *phb; 1358781a868fSWei Yang struct pnv_ioda_pe *pe, *pe_n; 1359781a868fSWei Yang struct pci_dn *pdn; 1360781a868fSWei Yang 1361781a868fSWei Yang bus = pdev->bus; 1362781a868fSWei Yang hose = pci_bus_to_host(bus); 1363781a868fSWei Yang phb = hose->private_data; 136402639b0eSWei Yang pdn = pci_get_pdn(pdev); 1365781a868fSWei Yang 1366781a868fSWei Yang if (!pdev->is_physfn) 1367781a868fSWei Yang return; 1368781a868fSWei Yang 1369781a868fSWei Yang list_for_each_entry_safe(pe, pe_n, &phb->ioda.pe_list, list) { 1370781a868fSWei Yang if (pe->parent_dev != pdev) 1371781a868fSWei Yang continue; 1372781a868fSWei Yang 1373781a868fSWei Yang pnv_pci_ioda2_release_dma_pe(pdev, pe); 1374781a868fSWei Yang 1375781a868fSWei Yang /* Remove from list */ 1376781a868fSWei Yang mutex_lock(&phb->ioda.pe_list_mutex); 1377781a868fSWei Yang list_del(&pe->list); 1378781a868fSWei Yang mutex_unlock(&phb->ioda.pe_list_mutex); 1379781a868fSWei Yang 1380781a868fSWei Yang pnv_ioda_deconfigure_pe(phb, pe); 1381781a868fSWei Yang 1382781a868fSWei Yang pnv_ioda_free_pe(phb, pe->pe_number); 1383781a868fSWei Yang } 1384781a868fSWei Yang } 1385781a868fSWei Yang 1386781a868fSWei Yang void pnv_pci_sriov_disable(struct pci_dev *pdev) 1387781a868fSWei Yang { 1388781a868fSWei Yang struct pci_bus *bus; 1389781a868fSWei Yang struct pci_controller *hose; 1390781a868fSWei Yang struct pnv_phb *phb; 1391781a868fSWei Yang struct pci_dn *pdn; 1392781a868fSWei Yang struct pci_sriov *iov; 1393be283eebSWei Yang u16 num_vfs, i; 1394781a868fSWei Yang 1395781a868fSWei Yang bus = pdev->bus; 1396781a868fSWei Yang hose = pci_bus_to_host(bus); 1397781a868fSWei Yang phb = hose->private_data; 1398781a868fSWei Yang pdn = pci_get_pdn(pdev); 1399781a868fSWei Yang iov = pdev->sriov; 1400781a868fSWei Yang num_vfs = pdn->num_vfs; 1401781a868fSWei Yang 1402781a868fSWei Yang /* Release VF PEs */ 1403ee8222feSWei Yang pnv_ioda_release_vf_PE(pdev); 1404781a868fSWei Yang 1405781a868fSWei Yang if (phb->type == PNV_PHB_IODA2) { 1406ee8222feSWei Yang if (!pdn->m64_single_mode) 1407be283eebSWei Yang pnv_pci_vf_resource_shift(pdev, -*pdn->pe_num_map); 1408781a868fSWei Yang 1409781a868fSWei Yang /* Release M64 windows */ 1410ee8222feSWei Yang pnv_pci_vf_release_m64(pdev, num_vfs); 1411781a868fSWei Yang 1412781a868fSWei Yang /* Release PE numbers */ 1413be283eebSWei Yang if (pdn->m64_single_mode) { 1414be283eebSWei Yang for (i = 0; i < num_vfs; i++) { 1415be283eebSWei Yang if (pdn->pe_num_map[i] != IODA_INVALID_PE) 1416be283eebSWei Yang pnv_ioda_free_pe(phb, pdn->pe_num_map[i]); 1417be283eebSWei Yang } 1418be283eebSWei Yang } else 1419be283eebSWei Yang bitmap_clear(phb->ioda.pe_alloc, *pdn->pe_num_map, num_vfs); 1420be283eebSWei Yang /* Releasing pe_num_map */ 1421be283eebSWei Yang kfree(pdn->pe_num_map); 1422781a868fSWei Yang } 1423781a868fSWei Yang } 1424781a868fSWei Yang 1425781a868fSWei Yang static void pnv_pci_ioda2_setup_dma_pe(struct pnv_phb *phb, 1426781a868fSWei Yang struct pnv_ioda_pe *pe); 1427781a868fSWei Yang static void pnv_ioda_setup_vf_PE(struct pci_dev *pdev, u16 num_vfs) 1428781a868fSWei Yang { 1429781a868fSWei Yang struct pci_bus *bus; 1430781a868fSWei Yang struct pci_controller *hose; 1431781a868fSWei Yang struct pnv_phb *phb; 1432781a868fSWei Yang struct pnv_ioda_pe *pe; 1433781a868fSWei Yang int pe_num; 1434781a868fSWei Yang u16 vf_index; 1435781a868fSWei Yang struct pci_dn *pdn; 1436781a868fSWei Yang 1437781a868fSWei Yang bus = pdev->bus; 1438781a868fSWei Yang hose = pci_bus_to_host(bus); 1439781a868fSWei Yang phb = hose->private_data; 1440781a868fSWei Yang pdn = pci_get_pdn(pdev); 1441781a868fSWei Yang 1442781a868fSWei Yang if (!pdev->is_physfn) 1443781a868fSWei Yang return; 1444781a868fSWei Yang 1445781a868fSWei Yang /* Reserve PE for each VF */ 1446781a868fSWei Yang for (vf_index = 0; vf_index < num_vfs; vf_index++) { 1447be283eebSWei Yang if (pdn->m64_single_mode) 1448be283eebSWei Yang pe_num = pdn->pe_num_map[vf_index]; 1449be283eebSWei Yang else 1450be283eebSWei Yang pe_num = *pdn->pe_num_map + vf_index; 1451781a868fSWei Yang 1452781a868fSWei Yang pe = &phb->ioda.pe_array[pe_num]; 1453781a868fSWei Yang pe->pe_number = pe_num; 1454781a868fSWei Yang pe->phb = phb; 1455781a868fSWei Yang pe->flags = PNV_IODA_PE_VF; 1456781a868fSWei Yang pe->pbus = NULL; 1457781a868fSWei Yang pe->parent_dev = pdev; 1458781a868fSWei Yang pe->tce32_seg = -1; 1459781a868fSWei Yang pe->mve_number = -1; 1460781a868fSWei Yang pe->rid = (pci_iov_virtfn_bus(pdev, vf_index) << 8) | 1461781a868fSWei Yang pci_iov_virtfn_devfn(pdev, vf_index); 1462781a868fSWei Yang 1463781a868fSWei Yang pe_info(pe, "VF %04d:%02d:%02d.%d associated with PE#%d\n", 1464781a868fSWei Yang hose->global_number, pdev->bus->number, 1465781a868fSWei Yang PCI_SLOT(pci_iov_virtfn_devfn(pdev, vf_index)), 1466781a868fSWei Yang PCI_FUNC(pci_iov_virtfn_devfn(pdev, vf_index)), pe_num); 1467781a868fSWei Yang 1468781a868fSWei Yang if (pnv_ioda_configure_pe(phb, pe)) { 1469781a868fSWei Yang /* XXX What do we do here ? */ 1470781a868fSWei Yang if (pe_num) 1471781a868fSWei Yang pnv_ioda_free_pe(phb, pe_num); 1472781a868fSWei Yang pe->pdev = NULL; 1473781a868fSWei Yang continue; 1474781a868fSWei Yang } 1475781a868fSWei Yang 1476781a868fSWei Yang /* Put PE to the list */ 1477781a868fSWei Yang mutex_lock(&phb->ioda.pe_list_mutex); 1478781a868fSWei Yang list_add_tail(&pe->list, &phb->ioda.pe_list); 1479781a868fSWei Yang mutex_unlock(&phb->ioda.pe_list_mutex); 1480781a868fSWei Yang 1481781a868fSWei Yang pnv_pci_ioda2_setup_dma_pe(phb, pe); 1482781a868fSWei Yang } 1483781a868fSWei Yang } 1484781a868fSWei Yang 1485781a868fSWei Yang int pnv_pci_sriov_enable(struct pci_dev *pdev, u16 num_vfs) 1486781a868fSWei Yang { 1487781a868fSWei Yang struct pci_bus *bus; 1488781a868fSWei Yang struct pci_controller *hose; 1489781a868fSWei Yang struct pnv_phb *phb; 1490781a868fSWei Yang struct pci_dn *pdn; 1491781a868fSWei Yang int ret; 1492be283eebSWei Yang u16 i; 1493781a868fSWei Yang 1494781a868fSWei Yang bus = pdev->bus; 1495781a868fSWei Yang hose = pci_bus_to_host(bus); 1496781a868fSWei Yang phb = hose->private_data; 1497781a868fSWei Yang pdn = pci_get_pdn(pdev); 1498781a868fSWei Yang 1499781a868fSWei Yang if (phb->type == PNV_PHB_IODA2) { 1500b0331854SWei Yang if (!pdn->vfs_expanded) { 1501b0331854SWei Yang dev_info(&pdev->dev, "don't support this SRIOV device" 1502b0331854SWei Yang " with non 64bit-prefetchable IOV BAR\n"); 1503b0331854SWei Yang return -ENOSPC; 1504b0331854SWei Yang } 1505b0331854SWei Yang 1506ee8222feSWei Yang /* 1507ee8222feSWei Yang * When M64 BARs functions in Single PE mode, the number of VFs 1508ee8222feSWei Yang * could be enabled must be less than the number of M64 BARs. 1509ee8222feSWei Yang */ 1510ee8222feSWei Yang if (pdn->m64_single_mode && num_vfs > phb->ioda.m64_bar_idx) { 1511ee8222feSWei Yang dev_info(&pdev->dev, "Not enough M64 BAR for VFs\n"); 1512ee8222feSWei Yang return -EBUSY; 1513ee8222feSWei Yang } 1514ee8222feSWei Yang 1515be283eebSWei Yang /* Allocating pe_num_map */ 1516be283eebSWei Yang if (pdn->m64_single_mode) 1517be283eebSWei Yang pdn->pe_num_map = kmalloc(sizeof(*pdn->pe_num_map) * num_vfs, 1518be283eebSWei Yang GFP_KERNEL); 1519be283eebSWei Yang else 1520be283eebSWei Yang pdn->pe_num_map = kmalloc(sizeof(*pdn->pe_num_map), GFP_KERNEL); 1521be283eebSWei Yang 1522be283eebSWei Yang if (!pdn->pe_num_map) 1523be283eebSWei Yang return -ENOMEM; 1524be283eebSWei Yang 1525be283eebSWei Yang if (pdn->m64_single_mode) 1526be283eebSWei Yang for (i = 0; i < num_vfs; i++) 1527be283eebSWei Yang pdn->pe_num_map[i] = IODA_INVALID_PE; 1528be283eebSWei Yang 1529781a868fSWei Yang /* Calculate available PE for required VFs */ 1530be283eebSWei Yang if (pdn->m64_single_mode) { 1531be283eebSWei Yang for (i = 0; i < num_vfs; i++) { 1532be283eebSWei Yang pdn->pe_num_map[i] = pnv_ioda_alloc_pe(phb); 1533be283eebSWei Yang if (pdn->pe_num_map[i] == IODA_INVALID_PE) { 1534be283eebSWei Yang ret = -EBUSY; 1535be283eebSWei Yang goto m64_failed; 1536be283eebSWei Yang } 1537be283eebSWei Yang } 1538be283eebSWei Yang } else { 1539781a868fSWei Yang mutex_lock(&phb->ioda.pe_alloc_mutex); 1540be283eebSWei Yang *pdn->pe_num_map = bitmap_find_next_zero_area( 154192b8f137SGavin Shan phb->ioda.pe_alloc, phb->ioda.total_pe_num, 1542781a868fSWei Yang 0, num_vfs, 0); 154392b8f137SGavin Shan if (*pdn->pe_num_map >= phb->ioda.total_pe_num) { 1544781a868fSWei Yang mutex_unlock(&phb->ioda.pe_alloc_mutex); 1545781a868fSWei Yang dev_info(&pdev->dev, "Failed to enable VF%d\n", num_vfs); 1546be283eebSWei Yang kfree(pdn->pe_num_map); 1547781a868fSWei Yang return -EBUSY; 1548781a868fSWei Yang } 1549be283eebSWei Yang bitmap_set(phb->ioda.pe_alloc, *pdn->pe_num_map, num_vfs); 1550781a868fSWei Yang mutex_unlock(&phb->ioda.pe_alloc_mutex); 1551be283eebSWei Yang } 1552be283eebSWei Yang pdn->num_vfs = num_vfs; 1553781a868fSWei Yang 1554781a868fSWei Yang /* Assign M64 window accordingly */ 155502639b0eSWei Yang ret = pnv_pci_vf_assign_m64(pdev, num_vfs); 1556781a868fSWei Yang if (ret) { 1557781a868fSWei Yang dev_info(&pdev->dev, "Not enough M64 window resources\n"); 1558781a868fSWei Yang goto m64_failed; 1559781a868fSWei Yang } 1560781a868fSWei Yang 1561781a868fSWei Yang /* 1562781a868fSWei Yang * When using one M64 BAR to map one IOV BAR, we need to shift 1563781a868fSWei Yang * the IOV BAR according to the PE# allocated to the VFs. 1564781a868fSWei Yang * Otherwise, the PE# for the VF will conflict with others. 1565781a868fSWei Yang */ 1566ee8222feSWei Yang if (!pdn->m64_single_mode) { 1567be283eebSWei Yang ret = pnv_pci_vf_resource_shift(pdev, *pdn->pe_num_map); 1568781a868fSWei Yang if (ret) 1569781a868fSWei Yang goto m64_failed; 1570781a868fSWei Yang } 157102639b0eSWei Yang } 1572781a868fSWei Yang 1573781a868fSWei Yang /* Setup VF PEs */ 1574781a868fSWei Yang pnv_ioda_setup_vf_PE(pdev, num_vfs); 1575781a868fSWei Yang 1576781a868fSWei Yang return 0; 1577781a868fSWei Yang 1578781a868fSWei Yang m64_failed: 1579be283eebSWei Yang if (pdn->m64_single_mode) { 1580be283eebSWei Yang for (i = 0; i < num_vfs; i++) { 1581be283eebSWei Yang if (pdn->pe_num_map[i] != IODA_INVALID_PE) 1582be283eebSWei Yang pnv_ioda_free_pe(phb, pdn->pe_num_map[i]); 1583be283eebSWei Yang } 1584be283eebSWei Yang } else 1585be283eebSWei Yang bitmap_clear(phb->ioda.pe_alloc, *pdn->pe_num_map, num_vfs); 1586be283eebSWei Yang 1587be283eebSWei Yang /* Releasing pe_num_map */ 1588be283eebSWei Yang kfree(pdn->pe_num_map); 1589781a868fSWei Yang 1590781a868fSWei Yang return ret; 1591781a868fSWei Yang } 1592781a868fSWei Yang 1593a8b2f828SGavin Shan int pcibios_sriov_disable(struct pci_dev *pdev) 1594a8b2f828SGavin Shan { 1595781a868fSWei Yang pnv_pci_sriov_disable(pdev); 1596781a868fSWei Yang 1597a8b2f828SGavin Shan /* Release PCI data */ 1598a8b2f828SGavin Shan remove_dev_pci_data(pdev); 1599a8b2f828SGavin Shan return 0; 1600a8b2f828SGavin Shan } 1601a8b2f828SGavin Shan 1602a8b2f828SGavin Shan int pcibios_sriov_enable(struct pci_dev *pdev, u16 num_vfs) 1603a8b2f828SGavin Shan { 1604a8b2f828SGavin Shan /* Allocate PCI data */ 1605a8b2f828SGavin Shan add_dev_pci_data(pdev); 1606781a868fSWei Yang 1607ee8222feSWei Yang return pnv_pci_sriov_enable(pdev, num_vfs); 1608a8b2f828SGavin Shan } 1609a8b2f828SGavin Shan #endif /* CONFIG_PCI_IOV */ 1610a8b2f828SGavin Shan 1611959c9bddSGavin Shan static void pnv_pci_ioda_dma_dev_setup(struct pnv_phb *phb, struct pci_dev *pdev) 1612184cd4a3SBenjamin Herrenschmidt { 1613b72c1f65SBenjamin Herrenschmidt struct pci_dn *pdn = pci_get_pdn(pdev); 1614959c9bddSGavin Shan struct pnv_ioda_pe *pe; 1615184cd4a3SBenjamin Herrenschmidt 1616959c9bddSGavin Shan /* 1617959c9bddSGavin Shan * The function can be called while the PE# 1618959c9bddSGavin Shan * hasn't been assigned. Do nothing for the 1619959c9bddSGavin Shan * case. 1620959c9bddSGavin Shan */ 1621959c9bddSGavin Shan if (!pdn || pdn->pe_number == IODA_INVALID_PE) 1622959c9bddSGavin Shan return; 1623184cd4a3SBenjamin Herrenschmidt 1624959c9bddSGavin Shan pe = &phb->ioda.pe_array[pdn->pe_number]; 1625cd15b048SBenjamin Herrenschmidt WARN_ON(get_dma_ops(&pdev->dev) != &dma_iommu_ops); 16260e1ffef0SAlexey Kardashevskiy set_dma_offset(&pdev->dev, pe->tce_bypass_base); 1627b348aa65SAlexey Kardashevskiy set_iommu_table_base(&pdev->dev, pe->table_group.tables[0]); 16284617082eSAlexey Kardashevskiy /* 16294617082eSAlexey Kardashevskiy * Note: iommu_add_device() will fail here as 16304617082eSAlexey Kardashevskiy * for physical PE: the device is already added by now; 16314617082eSAlexey Kardashevskiy * for virtual PE: sysfs entries are not ready yet and 16324617082eSAlexey Kardashevskiy * tce_iommu_bus_notifier will add the device to a group later. 16334617082eSAlexey Kardashevskiy */ 1634184cd4a3SBenjamin Herrenschmidt } 1635184cd4a3SBenjamin Herrenschmidt 1636763d2d8dSDaniel Axtens static int pnv_pci_ioda_dma_set_mask(struct pci_dev *pdev, u64 dma_mask) 1637cd15b048SBenjamin Herrenschmidt { 1638763d2d8dSDaniel Axtens struct pci_controller *hose = pci_bus_to_host(pdev->bus); 1639763d2d8dSDaniel Axtens struct pnv_phb *phb = hose->private_data; 1640cd15b048SBenjamin Herrenschmidt struct pci_dn *pdn = pci_get_pdn(pdev); 1641cd15b048SBenjamin Herrenschmidt struct pnv_ioda_pe *pe; 1642cd15b048SBenjamin Herrenschmidt uint64_t top; 1643cd15b048SBenjamin Herrenschmidt bool bypass = false; 16445d2aa710SAlistair Popple struct pci_dev *linked_npu_dev; 16455d2aa710SAlistair Popple int i; 1646cd15b048SBenjamin Herrenschmidt 1647cd15b048SBenjamin Herrenschmidt if (WARN_ON(!pdn || pdn->pe_number == IODA_INVALID_PE)) 1648cd15b048SBenjamin Herrenschmidt return -ENODEV;; 1649cd15b048SBenjamin Herrenschmidt 1650cd15b048SBenjamin Herrenschmidt pe = &phb->ioda.pe_array[pdn->pe_number]; 1651cd15b048SBenjamin Herrenschmidt if (pe->tce_bypass_enabled) { 1652cd15b048SBenjamin Herrenschmidt top = pe->tce_bypass_base + memblock_end_of_DRAM() - 1; 1653cd15b048SBenjamin Herrenschmidt bypass = (dma_mask >= top); 1654cd15b048SBenjamin Herrenschmidt } 1655cd15b048SBenjamin Herrenschmidt 1656cd15b048SBenjamin Herrenschmidt if (bypass) { 1657cd15b048SBenjamin Herrenschmidt dev_info(&pdev->dev, "Using 64-bit DMA iommu bypass\n"); 1658cd15b048SBenjamin Herrenschmidt set_dma_ops(&pdev->dev, &dma_direct_ops); 1659cd15b048SBenjamin Herrenschmidt } else { 1660cd15b048SBenjamin Herrenschmidt dev_info(&pdev->dev, "Using 32-bit DMA via iommu\n"); 1661cd15b048SBenjamin Herrenschmidt set_dma_ops(&pdev->dev, &dma_iommu_ops); 1662cd15b048SBenjamin Herrenschmidt } 1663a32305bfSBrian W Hart *pdev->dev.dma_mask = dma_mask; 16645d2aa710SAlistair Popple 16655d2aa710SAlistair Popple /* Update peer npu devices */ 16665d2aa710SAlistair Popple if (pe->flags & PNV_IODA_PE_PEER) 1667419dbd5eSAlistair Popple for (i = 0; i < PNV_IODA_MAX_PEER_PES; i++) { 1668419dbd5eSAlistair Popple if (!pe->peers[i]) 1669419dbd5eSAlistair Popple continue; 1670419dbd5eSAlistair Popple 16715d2aa710SAlistair Popple linked_npu_dev = pe->peers[i]->pdev; 16725d2aa710SAlistair Popple if (dma_get_mask(&linked_npu_dev->dev) != dma_mask) 16735d2aa710SAlistair Popple dma_set_mask(&linked_npu_dev->dev, dma_mask); 16745d2aa710SAlistair Popple } 16755d2aa710SAlistair Popple 1676cd15b048SBenjamin Herrenschmidt return 0; 1677cd15b048SBenjamin Herrenschmidt } 1678cd15b048SBenjamin Herrenschmidt 167953522982SAndrew Donnellan static u64 pnv_pci_ioda_dma_get_required_mask(struct pci_dev *pdev) 1680fe7e85c6SGavin Shan { 168153522982SAndrew Donnellan struct pci_controller *hose = pci_bus_to_host(pdev->bus); 168253522982SAndrew Donnellan struct pnv_phb *phb = hose->private_data; 1683fe7e85c6SGavin Shan struct pci_dn *pdn = pci_get_pdn(pdev); 1684fe7e85c6SGavin Shan struct pnv_ioda_pe *pe; 1685fe7e85c6SGavin Shan u64 end, mask; 1686fe7e85c6SGavin Shan 1687fe7e85c6SGavin Shan if (WARN_ON(!pdn || pdn->pe_number == IODA_INVALID_PE)) 1688fe7e85c6SGavin Shan return 0; 1689fe7e85c6SGavin Shan 1690fe7e85c6SGavin Shan pe = &phb->ioda.pe_array[pdn->pe_number]; 1691fe7e85c6SGavin Shan if (!pe->tce_bypass_enabled) 1692fe7e85c6SGavin Shan return __dma_get_required_mask(&pdev->dev); 1693fe7e85c6SGavin Shan 1694fe7e85c6SGavin Shan 1695fe7e85c6SGavin Shan end = pe->tce_bypass_base + memblock_end_of_DRAM(); 1696fe7e85c6SGavin Shan mask = 1ULL << (fls64(end) - 1); 1697fe7e85c6SGavin Shan mask += mask - 1; 1698fe7e85c6SGavin Shan 1699fe7e85c6SGavin Shan return mask; 1700fe7e85c6SGavin Shan } 1701fe7e85c6SGavin Shan 1702dff4a39eSGavin Shan static void pnv_ioda_setup_bus_dma(struct pnv_ioda_pe *pe, 1703ea30e99eSAlexey Kardashevskiy struct pci_bus *bus) 170474251fe2SBenjamin Herrenschmidt { 170574251fe2SBenjamin Herrenschmidt struct pci_dev *dev; 170674251fe2SBenjamin Herrenschmidt 170774251fe2SBenjamin Herrenschmidt list_for_each_entry(dev, &bus->devices, bus_list) { 1708b348aa65SAlexey Kardashevskiy set_iommu_table_base(&dev->dev, pe->table_group.tables[0]); 1709e91c2511SBenjamin Herrenschmidt set_dma_offset(&dev->dev, pe->tce_bypass_base); 17104617082eSAlexey Kardashevskiy iommu_add_device(&dev->dev); 1711dff4a39eSGavin Shan 17125c89a87dSAlexey Kardashevskiy if ((pe->flags & PNV_IODA_PE_BUS_ALL) && dev->subordinate) 1713ea30e99eSAlexey Kardashevskiy pnv_ioda_setup_bus_dma(pe, dev->subordinate); 171474251fe2SBenjamin Herrenschmidt } 171574251fe2SBenjamin Herrenschmidt } 171674251fe2SBenjamin Herrenschmidt 1717decbda25SAlexey Kardashevskiy static void pnv_pci_ioda1_tce_invalidate(struct iommu_table *tbl, 1718decbda25SAlexey Kardashevskiy unsigned long index, unsigned long npages, bool rm) 17194cce9550SGavin Shan { 17200eaf4defSAlexey Kardashevskiy struct iommu_table_group_link *tgl = list_first_entry_or_null( 17210eaf4defSAlexey Kardashevskiy &tbl->it_group_list, struct iommu_table_group_link, 17220eaf4defSAlexey Kardashevskiy next); 17230eaf4defSAlexey Kardashevskiy struct pnv_ioda_pe *pe = container_of(tgl->table_group, 1724b348aa65SAlexey Kardashevskiy struct pnv_ioda_pe, table_group); 17253ad26e5cSBenjamin Herrenschmidt __be64 __iomem *invalidate = rm ? 17265780fb04SAlexey Kardashevskiy (__be64 __iomem *)pe->phb->ioda.tce_inval_reg_phys : 17275780fb04SAlexey Kardashevskiy pe->phb->ioda.tce_inval_reg; 17284cce9550SGavin Shan unsigned long start, end, inc; 1729b0376c9bSAlexey Kardashevskiy const unsigned shift = tbl->it_page_shift; 17304cce9550SGavin Shan 1731decbda25SAlexey Kardashevskiy start = __pa(((__be64 *)tbl->it_base) + index - tbl->it_offset); 1732decbda25SAlexey Kardashevskiy end = __pa(((__be64 *)tbl->it_base) + index - tbl->it_offset + 1733decbda25SAlexey Kardashevskiy npages - 1); 17344cce9550SGavin Shan 17354cce9550SGavin Shan /* BML uses this case for p6/p7/galaxy2: Shift addr and put in node */ 17364cce9550SGavin Shan if (tbl->it_busno) { 1737b0376c9bSAlexey Kardashevskiy start <<= shift; 1738b0376c9bSAlexey Kardashevskiy end <<= shift; 1739b0376c9bSAlexey Kardashevskiy inc = 128ull << shift; 17404cce9550SGavin Shan start |= tbl->it_busno; 17414cce9550SGavin Shan end |= tbl->it_busno; 17424cce9550SGavin Shan } else if (tbl->it_type & TCE_PCI_SWINV_PAIR) { 17434cce9550SGavin Shan /* p7ioc-style invalidation, 2 TCEs per write */ 17444cce9550SGavin Shan start |= (1ull << 63); 17454cce9550SGavin Shan end |= (1ull << 63); 17464cce9550SGavin Shan inc = 16; 17474cce9550SGavin Shan } else { 17484cce9550SGavin Shan /* Default (older HW) */ 17494cce9550SGavin Shan inc = 128; 17504cce9550SGavin Shan } 17514cce9550SGavin Shan 17524cce9550SGavin Shan end |= inc - 1; /* round up end to be different than start */ 17534cce9550SGavin Shan 17544cce9550SGavin Shan mb(); /* Ensure above stores are visible */ 17554cce9550SGavin Shan while (start <= end) { 17568e0a1611SAlexey Kardashevskiy if (rm) 17573ad26e5cSBenjamin Herrenschmidt __raw_rm_writeq(cpu_to_be64(start), invalidate); 17588e0a1611SAlexey Kardashevskiy else 17593a1a4661SBenjamin Herrenschmidt __raw_writeq(cpu_to_be64(start), invalidate); 17604cce9550SGavin Shan start += inc; 17614cce9550SGavin Shan } 17624cce9550SGavin Shan 17634cce9550SGavin Shan /* 17644cce9550SGavin Shan * The iommu layer will do another mb() for us on build() 17654cce9550SGavin Shan * and we don't care on free() 17664cce9550SGavin Shan */ 17674cce9550SGavin Shan } 17684cce9550SGavin Shan 1769decbda25SAlexey Kardashevskiy static int pnv_ioda1_tce_build(struct iommu_table *tbl, long index, 1770decbda25SAlexey Kardashevskiy long npages, unsigned long uaddr, 1771decbda25SAlexey Kardashevskiy enum dma_data_direction direction, 1772decbda25SAlexey Kardashevskiy struct dma_attrs *attrs) 1773decbda25SAlexey Kardashevskiy { 1774decbda25SAlexey Kardashevskiy int ret = pnv_tce_build(tbl, index, npages, uaddr, direction, 1775decbda25SAlexey Kardashevskiy attrs); 1776decbda25SAlexey Kardashevskiy 1777decbda25SAlexey Kardashevskiy if (!ret && (tbl->it_type & TCE_PCI_SWINV_CREATE)) 1778decbda25SAlexey Kardashevskiy pnv_pci_ioda1_tce_invalidate(tbl, index, npages, false); 1779decbda25SAlexey Kardashevskiy 1780decbda25SAlexey Kardashevskiy return ret; 1781decbda25SAlexey Kardashevskiy } 1782decbda25SAlexey Kardashevskiy 178305c6cfb9SAlexey Kardashevskiy #ifdef CONFIG_IOMMU_API 178405c6cfb9SAlexey Kardashevskiy static int pnv_ioda1_tce_xchg(struct iommu_table *tbl, long index, 178505c6cfb9SAlexey Kardashevskiy unsigned long *hpa, enum dma_data_direction *direction) 178605c6cfb9SAlexey Kardashevskiy { 178705c6cfb9SAlexey Kardashevskiy long ret = pnv_tce_xchg(tbl, index, hpa, direction); 178805c6cfb9SAlexey Kardashevskiy 178905c6cfb9SAlexey Kardashevskiy if (!ret && (tbl->it_type & 179005c6cfb9SAlexey Kardashevskiy (TCE_PCI_SWINV_CREATE | TCE_PCI_SWINV_FREE))) 179105c6cfb9SAlexey Kardashevskiy pnv_pci_ioda1_tce_invalidate(tbl, index, 1, false); 179205c6cfb9SAlexey Kardashevskiy 179305c6cfb9SAlexey Kardashevskiy return ret; 179405c6cfb9SAlexey Kardashevskiy } 179505c6cfb9SAlexey Kardashevskiy #endif 179605c6cfb9SAlexey Kardashevskiy 1797decbda25SAlexey Kardashevskiy static void pnv_ioda1_tce_free(struct iommu_table *tbl, long index, 1798decbda25SAlexey Kardashevskiy long npages) 1799decbda25SAlexey Kardashevskiy { 1800decbda25SAlexey Kardashevskiy pnv_tce_free(tbl, index, npages); 1801decbda25SAlexey Kardashevskiy 1802decbda25SAlexey Kardashevskiy if (tbl->it_type & TCE_PCI_SWINV_FREE) 1803decbda25SAlexey Kardashevskiy pnv_pci_ioda1_tce_invalidate(tbl, index, npages, false); 1804decbda25SAlexey Kardashevskiy } 1805decbda25SAlexey Kardashevskiy 1806da004c36SAlexey Kardashevskiy static struct iommu_table_ops pnv_ioda1_iommu_ops = { 1807decbda25SAlexey Kardashevskiy .set = pnv_ioda1_tce_build, 180805c6cfb9SAlexey Kardashevskiy #ifdef CONFIG_IOMMU_API 180905c6cfb9SAlexey Kardashevskiy .exchange = pnv_ioda1_tce_xchg, 181005c6cfb9SAlexey Kardashevskiy #endif 1811decbda25SAlexey Kardashevskiy .clear = pnv_ioda1_tce_free, 1812da004c36SAlexey Kardashevskiy .get = pnv_tce_get, 1813da004c36SAlexey Kardashevskiy }; 1814da004c36SAlexey Kardashevskiy 18155780fb04SAlexey Kardashevskiy static inline void pnv_pci_ioda2_tce_invalidate_entire(struct pnv_ioda_pe *pe) 18165780fb04SAlexey Kardashevskiy { 18175780fb04SAlexey Kardashevskiy /* 01xb - invalidate TCEs that match the specified PE# */ 18185780fb04SAlexey Kardashevskiy unsigned long val = (0x4ull << 60) | (pe->pe_number & 0xFF); 18195780fb04SAlexey Kardashevskiy struct pnv_phb *phb = pe->phb; 18205d2aa710SAlistair Popple struct pnv_ioda_pe *npe; 18215d2aa710SAlistair Popple int i; 18225780fb04SAlexey Kardashevskiy 18235780fb04SAlexey Kardashevskiy if (!phb->ioda.tce_inval_reg) 18245780fb04SAlexey Kardashevskiy return; 18255780fb04SAlexey Kardashevskiy 18265780fb04SAlexey Kardashevskiy mb(); /* Ensure above stores are visible */ 18275780fb04SAlexey Kardashevskiy __raw_writeq(cpu_to_be64(val), phb->ioda.tce_inval_reg); 18285d2aa710SAlistair Popple 18295d2aa710SAlistair Popple if (pe->flags & PNV_IODA_PE_PEER) 18305d2aa710SAlistair Popple for (i = 0; i < PNV_IODA_MAX_PEER_PES; i++) { 18315d2aa710SAlistair Popple npe = pe->peers[i]; 18325d2aa710SAlistair Popple if (!npe || npe->phb->type != PNV_PHB_NPU) 18335d2aa710SAlistair Popple continue; 18345d2aa710SAlistair Popple 18355d2aa710SAlistair Popple pnv_npu_tce_invalidate_entire(npe); 18365d2aa710SAlistair Popple } 18375780fb04SAlexey Kardashevskiy } 18385780fb04SAlexey Kardashevskiy 1839e57080f1SAlexey Kardashevskiy static void pnv_pci_ioda2_do_tce_invalidate(unsigned pe_number, bool rm, 1840e57080f1SAlexey Kardashevskiy __be64 __iomem *invalidate, unsigned shift, 1841e57080f1SAlexey Kardashevskiy unsigned long index, unsigned long npages) 18424cce9550SGavin Shan { 18434cce9550SGavin Shan unsigned long start, end, inc; 18444cce9550SGavin Shan 18454cce9550SGavin Shan /* We'll invalidate DMA address in PE scope */ 1846b0376c9bSAlexey Kardashevskiy start = 0x2ull << 60; 1847e57080f1SAlexey Kardashevskiy start |= (pe_number & 0xFF); 18484cce9550SGavin Shan end = start; 18494cce9550SGavin Shan 18504cce9550SGavin Shan /* Figure out the start, end and step */ 1851decbda25SAlexey Kardashevskiy start |= (index << shift); 1852decbda25SAlexey Kardashevskiy end |= ((index + npages - 1) << shift); 1853b0376c9bSAlexey Kardashevskiy inc = (0x1ull << shift); 18544cce9550SGavin Shan mb(); 18554cce9550SGavin Shan 18564cce9550SGavin Shan while (start <= end) { 18578e0a1611SAlexey Kardashevskiy if (rm) 18583ad26e5cSBenjamin Herrenschmidt __raw_rm_writeq(cpu_to_be64(start), invalidate); 18598e0a1611SAlexey Kardashevskiy else 18603a1a4661SBenjamin Herrenschmidt __raw_writeq(cpu_to_be64(start), invalidate); 18614cce9550SGavin Shan start += inc; 18624cce9550SGavin Shan } 18634cce9550SGavin Shan } 18644cce9550SGavin Shan 1865e57080f1SAlexey Kardashevskiy static void pnv_pci_ioda2_tce_invalidate(struct iommu_table *tbl, 1866e57080f1SAlexey Kardashevskiy unsigned long index, unsigned long npages, bool rm) 1867e57080f1SAlexey Kardashevskiy { 1868e57080f1SAlexey Kardashevskiy struct iommu_table_group_link *tgl; 1869e57080f1SAlexey Kardashevskiy 1870e57080f1SAlexey Kardashevskiy list_for_each_entry_rcu(tgl, &tbl->it_group_list, next) { 18715d2aa710SAlistair Popple struct pnv_ioda_pe *npe; 1872e57080f1SAlexey Kardashevskiy struct pnv_ioda_pe *pe = container_of(tgl->table_group, 1873e57080f1SAlexey Kardashevskiy struct pnv_ioda_pe, table_group); 1874e57080f1SAlexey Kardashevskiy __be64 __iomem *invalidate = rm ? 1875e57080f1SAlexey Kardashevskiy (__be64 __iomem *)pe->phb->ioda.tce_inval_reg_phys : 1876e57080f1SAlexey Kardashevskiy pe->phb->ioda.tce_inval_reg; 18775d2aa710SAlistair Popple int i; 1878e57080f1SAlexey Kardashevskiy 1879e57080f1SAlexey Kardashevskiy pnv_pci_ioda2_do_tce_invalidate(pe->pe_number, rm, 1880e57080f1SAlexey Kardashevskiy invalidate, tbl->it_page_shift, 1881e57080f1SAlexey Kardashevskiy index, npages); 18825d2aa710SAlistair Popple 18835d2aa710SAlistair Popple if (pe->flags & PNV_IODA_PE_PEER) 18845d2aa710SAlistair Popple /* Invalidate PEs using the same TCE table */ 18855d2aa710SAlistair Popple for (i = 0; i < PNV_IODA_MAX_PEER_PES; i++) { 18865d2aa710SAlistair Popple npe = pe->peers[i]; 18875d2aa710SAlistair Popple if (!npe || npe->phb->type != PNV_PHB_NPU) 18885d2aa710SAlistair Popple continue; 18895d2aa710SAlistair Popple 18905d2aa710SAlistair Popple pnv_npu_tce_invalidate(npe, tbl, index, 18915d2aa710SAlistair Popple npages, rm); 18925d2aa710SAlistair Popple } 1893e57080f1SAlexey Kardashevskiy } 1894e57080f1SAlexey Kardashevskiy } 1895e57080f1SAlexey Kardashevskiy 1896decbda25SAlexey Kardashevskiy static int pnv_ioda2_tce_build(struct iommu_table *tbl, long index, 1897decbda25SAlexey Kardashevskiy long npages, unsigned long uaddr, 1898decbda25SAlexey Kardashevskiy enum dma_data_direction direction, 1899decbda25SAlexey Kardashevskiy struct dma_attrs *attrs) 19004cce9550SGavin Shan { 1901decbda25SAlexey Kardashevskiy int ret = pnv_tce_build(tbl, index, npages, uaddr, direction, 1902decbda25SAlexey Kardashevskiy attrs); 19034cce9550SGavin Shan 1904decbda25SAlexey Kardashevskiy if (!ret && (tbl->it_type & TCE_PCI_SWINV_CREATE)) 1905decbda25SAlexey Kardashevskiy pnv_pci_ioda2_tce_invalidate(tbl, index, npages, false); 1906decbda25SAlexey Kardashevskiy 1907decbda25SAlexey Kardashevskiy return ret; 1908decbda25SAlexey Kardashevskiy } 1909decbda25SAlexey Kardashevskiy 191005c6cfb9SAlexey Kardashevskiy #ifdef CONFIG_IOMMU_API 191105c6cfb9SAlexey Kardashevskiy static int pnv_ioda2_tce_xchg(struct iommu_table *tbl, long index, 191205c6cfb9SAlexey Kardashevskiy unsigned long *hpa, enum dma_data_direction *direction) 191305c6cfb9SAlexey Kardashevskiy { 191405c6cfb9SAlexey Kardashevskiy long ret = pnv_tce_xchg(tbl, index, hpa, direction); 191505c6cfb9SAlexey Kardashevskiy 191605c6cfb9SAlexey Kardashevskiy if (!ret && (tbl->it_type & 191705c6cfb9SAlexey Kardashevskiy (TCE_PCI_SWINV_CREATE | TCE_PCI_SWINV_FREE))) 191805c6cfb9SAlexey Kardashevskiy pnv_pci_ioda2_tce_invalidate(tbl, index, 1, false); 191905c6cfb9SAlexey Kardashevskiy 192005c6cfb9SAlexey Kardashevskiy return ret; 192105c6cfb9SAlexey Kardashevskiy } 192205c6cfb9SAlexey Kardashevskiy #endif 192305c6cfb9SAlexey Kardashevskiy 1924decbda25SAlexey Kardashevskiy static void pnv_ioda2_tce_free(struct iommu_table *tbl, long index, 1925decbda25SAlexey Kardashevskiy long npages) 1926decbda25SAlexey Kardashevskiy { 1927decbda25SAlexey Kardashevskiy pnv_tce_free(tbl, index, npages); 1928decbda25SAlexey Kardashevskiy 1929decbda25SAlexey Kardashevskiy if (tbl->it_type & TCE_PCI_SWINV_FREE) 1930decbda25SAlexey Kardashevskiy pnv_pci_ioda2_tce_invalidate(tbl, index, npages, false); 19314cce9550SGavin Shan } 19324cce9550SGavin Shan 19334793d65dSAlexey Kardashevskiy static void pnv_ioda2_table_free(struct iommu_table *tbl) 19344793d65dSAlexey Kardashevskiy { 19354793d65dSAlexey Kardashevskiy pnv_pci_ioda2_table_free_pages(tbl); 19364793d65dSAlexey Kardashevskiy iommu_free_table(tbl, "pnv"); 19374793d65dSAlexey Kardashevskiy } 19384793d65dSAlexey Kardashevskiy 1939da004c36SAlexey Kardashevskiy static struct iommu_table_ops pnv_ioda2_iommu_ops = { 1940decbda25SAlexey Kardashevskiy .set = pnv_ioda2_tce_build, 194105c6cfb9SAlexey Kardashevskiy #ifdef CONFIG_IOMMU_API 194205c6cfb9SAlexey Kardashevskiy .exchange = pnv_ioda2_tce_xchg, 194305c6cfb9SAlexey Kardashevskiy #endif 1944decbda25SAlexey Kardashevskiy .clear = pnv_ioda2_tce_free, 1945da004c36SAlexey Kardashevskiy .get = pnv_tce_get, 19464793d65dSAlexey Kardashevskiy .free = pnv_ioda2_table_free, 1947da004c36SAlexey Kardashevskiy }; 1948da004c36SAlexey Kardashevskiy 1949cad5cef6SGreg Kroah-Hartman static void pnv_pci_ioda_setup_dma_pe(struct pnv_phb *phb, 1950cad5cef6SGreg Kroah-Hartman struct pnv_ioda_pe *pe, unsigned int base, 1951184cd4a3SBenjamin Herrenschmidt unsigned int segs) 1952184cd4a3SBenjamin Herrenschmidt { 1953184cd4a3SBenjamin Herrenschmidt 1954184cd4a3SBenjamin Herrenschmidt struct page *tce_mem = NULL; 1955184cd4a3SBenjamin Herrenschmidt struct iommu_table *tbl; 1956184cd4a3SBenjamin Herrenschmidt unsigned int i; 1957184cd4a3SBenjamin Herrenschmidt int64_t rc; 1958184cd4a3SBenjamin Herrenschmidt void *addr; 1959184cd4a3SBenjamin Herrenschmidt 1960184cd4a3SBenjamin Herrenschmidt /* XXX FIXME: Handle 64-bit only DMA devices */ 1961184cd4a3SBenjamin Herrenschmidt /* XXX FIXME: Provide 64-bit DMA facilities & non-4K TCE tables etc.. */ 1962184cd4a3SBenjamin Herrenschmidt /* XXX FIXME: Allocate multi-level tables on PHB3 */ 1963184cd4a3SBenjamin Herrenschmidt 1964184cd4a3SBenjamin Herrenschmidt /* We shouldn't already have a 32-bit DMA associated */ 1965184cd4a3SBenjamin Herrenschmidt if (WARN_ON(pe->tce32_seg >= 0)) 1966184cd4a3SBenjamin Herrenschmidt return; 1967184cd4a3SBenjamin Herrenschmidt 19680eaf4defSAlexey Kardashevskiy tbl = pnv_pci_table_alloc(phb->hose->node); 1969b348aa65SAlexey Kardashevskiy iommu_register_group(&pe->table_group, phb->hose->global_number, 1970b348aa65SAlexey Kardashevskiy pe->pe_number); 19710eaf4defSAlexey Kardashevskiy pnv_pci_link_table_and_group(phb->hose->node, 0, tbl, &pe->table_group); 1972c5773822SAlexey Kardashevskiy 1973184cd4a3SBenjamin Herrenschmidt /* Grab a 32-bit TCE table */ 1974184cd4a3SBenjamin Herrenschmidt pe->tce32_seg = base; 1975184cd4a3SBenjamin Herrenschmidt pe_info(pe, " Setting up 32-bit TCE table at %08x..%08x\n", 1976184cd4a3SBenjamin Herrenschmidt (base << 28), ((base + segs) << 28) - 1); 1977184cd4a3SBenjamin Herrenschmidt 1978184cd4a3SBenjamin Herrenschmidt /* XXX Currently, we allocate one big contiguous table for the 1979184cd4a3SBenjamin Herrenschmidt * TCEs. We only really need one chunk per 256M of TCE space 1980184cd4a3SBenjamin Herrenschmidt * (ie per segment) but that's an optimization for later, it 1981184cd4a3SBenjamin Herrenschmidt * requires some added smarts with our get/put_tce implementation 1982184cd4a3SBenjamin Herrenschmidt */ 1983184cd4a3SBenjamin Herrenschmidt tce_mem = alloc_pages_node(phb->hose->node, GFP_KERNEL, 1984184cd4a3SBenjamin Herrenschmidt get_order(TCE32_TABLE_SIZE * segs)); 1985184cd4a3SBenjamin Herrenschmidt if (!tce_mem) { 1986184cd4a3SBenjamin Herrenschmidt pe_err(pe, " Failed to allocate a 32-bit TCE memory\n"); 1987184cd4a3SBenjamin Herrenschmidt goto fail; 1988184cd4a3SBenjamin Herrenschmidt } 1989184cd4a3SBenjamin Herrenschmidt addr = page_address(tce_mem); 1990184cd4a3SBenjamin Herrenschmidt memset(addr, 0, TCE32_TABLE_SIZE * segs); 1991184cd4a3SBenjamin Herrenschmidt 1992184cd4a3SBenjamin Herrenschmidt /* Configure HW */ 1993184cd4a3SBenjamin Herrenschmidt for (i = 0; i < segs; i++) { 1994184cd4a3SBenjamin Herrenschmidt rc = opal_pci_map_pe_dma_window(phb->opal_id, 1995184cd4a3SBenjamin Herrenschmidt pe->pe_number, 1996184cd4a3SBenjamin Herrenschmidt base + i, 1, 1997184cd4a3SBenjamin Herrenschmidt __pa(addr) + TCE32_TABLE_SIZE * i, 1998184cd4a3SBenjamin Herrenschmidt TCE32_TABLE_SIZE, 0x1000); 1999184cd4a3SBenjamin Herrenschmidt if (rc) { 2000184cd4a3SBenjamin Herrenschmidt pe_err(pe, " Failed to configure 32-bit TCE table," 2001184cd4a3SBenjamin Herrenschmidt " err %ld\n", rc); 2002184cd4a3SBenjamin Herrenschmidt goto fail; 2003184cd4a3SBenjamin Herrenschmidt } 2004184cd4a3SBenjamin Herrenschmidt } 2005184cd4a3SBenjamin Herrenschmidt 2006184cd4a3SBenjamin Herrenschmidt /* Setup linux iommu table */ 2007184cd4a3SBenjamin Herrenschmidt pnv_pci_setup_iommu_table(tbl, addr, TCE32_TABLE_SIZE * segs, 20088fa5d454SAlexey Kardashevskiy base << 28, IOMMU_PAGE_SHIFT_4K); 2009184cd4a3SBenjamin Herrenschmidt 2010184cd4a3SBenjamin Herrenschmidt /* OPAL variant of P7IOC SW invalidated TCEs */ 20115780fb04SAlexey Kardashevskiy if (phb->ioda.tce_inval_reg) 201265fd766bSGavin Shan tbl->it_type |= (TCE_PCI_SWINV_CREATE | 201365fd766bSGavin Shan TCE_PCI_SWINV_FREE | 201465fd766bSGavin Shan TCE_PCI_SWINV_PAIR); 20155780fb04SAlexey Kardashevskiy 2016da004c36SAlexey Kardashevskiy tbl->it_ops = &pnv_ioda1_iommu_ops; 20174793d65dSAlexey Kardashevskiy pe->table_group.tce32_start = tbl->it_offset << tbl->it_page_shift; 20184793d65dSAlexey Kardashevskiy pe->table_group.tce32_size = tbl->it_size << tbl->it_page_shift; 2019184cd4a3SBenjamin Herrenschmidt iommu_init_table(tbl, phb->hose->node); 2020184cd4a3SBenjamin Herrenschmidt 2021781a868fSWei Yang if (pe->flags & PNV_IODA_PE_DEV) { 20224617082eSAlexey Kardashevskiy /* 20234617082eSAlexey Kardashevskiy * Setting table base here only for carrying iommu_group 20244617082eSAlexey Kardashevskiy * further down to let iommu_add_device() do the job. 20254617082eSAlexey Kardashevskiy * pnv_pci_ioda_dma_dev_setup will override it later anyway. 20264617082eSAlexey Kardashevskiy */ 20274617082eSAlexey Kardashevskiy set_iommu_table_base(&pe->pdev->dev, tbl); 20284617082eSAlexey Kardashevskiy iommu_add_device(&pe->pdev->dev); 2029c5773822SAlexey Kardashevskiy } else if (pe->flags & (PNV_IODA_PE_BUS | PNV_IODA_PE_BUS_ALL)) 2030ea30e99eSAlexey Kardashevskiy pnv_ioda_setup_bus_dma(pe, pe->pbus); 203174251fe2SBenjamin Herrenschmidt 2032184cd4a3SBenjamin Herrenschmidt return; 2033184cd4a3SBenjamin Herrenschmidt fail: 2034184cd4a3SBenjamin Herrenschmidt /* XXX Failure: Try to fallback to 64-bit only ? */ 2035184cd4a3SBenjamin Herrenschmidt if (pe->tce32_seg >= 0) 2036184cd4a3SBenjamin Herrenschmidt pe->tce32_seg = -1; 2037184cd4a3SBenjamin Herrenschmidt if (tce_mem) 2038184cd4a3SBenjamin Herrenschmidt __free_pages(tce_mem, get_order(TCE32_TABLE_SIZE * segs)); 20390eaf4defSAlexey Kardashevskiy if (tbl) { 20400eaf4defSAlexey Kardashevskiy pnv_pci_unlink_table_and_group(tbl, &pe->table_group); 20410eaf4defSAlexey Kardashevskiy iommu_free_table(tbl, "pnv"); 20420eaf4defSAlexey Kardashevskiy } 2043184cd4a3SBenjamin Herrenschmidt } 2044184cd4a3SBenjamin Herrenschmidt 204543cb60abSAlexey Kardashevskiy static long pnv_pci_ioda2_set_window(struct iommu_table_group *table_group, 204643cb60abSAlexey Kardashevskiy int num, struct iommu_table *tbl) 204743cb60abSAlexey Kardashevskiy { 204843cb60abSAlexey Kardashevskiy struct pnv_ioda_pe *pe = container_of(table_group, struct pnv_ioda_pe, 204943cb60abSAlexey Kardashevskiy table_group); 205043cb60abSAlexey Kardashevskiy struct pnv_phb *phb = pe->phb; 205143cb60abSAlexey Kardashevskiy int64_t rc; 2052bbb845c4SAlexey Kardashevskiy const unsigned long size = tbl->it_indirect_levels ? 2053bbb845c4SAlexey Kardashevskiy tbl->it_level_size : tbl->it_size; 205443cb60abSAlexey Kardashevskiy const __u64 start_addr = tbl->it_offset << tbl->it_page_shift; 205543cb60abSAlexey Kardashevskiy const __u64 win_size = tbl->it_size << tbl->it_page_shift; 205643cb60abSAlexey Kardashevskiy 20574793d65dSAlexey Kardashevskiy pe_info(pe, "Setting up window#%d %llx..%llx pg=%x\n", num, 205843cb60abSAlexey Kardashevskiy start_addr, start_addr + win_size - 1, 205943cb60abSAlexey Kardashevskiy IOMMU_PAGE_SIZE(tbl)); 206043cb60abSAlexey Kardashevskiy 206143cb60abSAlexey Kardashevskiy /* 206243cb60abSAlexey Kardashevskiy * Map TCE table through TVT. The TVE index is the PE number 206343cb60abSAlexey Kardashevskiy * shifted by 1 bit for 32-bits DMA space. 206443cb60abSAlexey Kardashevskiy */ 206543cb60abSAlexey Kardashevskiy rc = opal_pci_map_pe_dma_window(phb->opal_id, 206643cb60abSAlexey Kardashevskiy pe->pe_number, 20674793d65dSAlexey Kardashevskiy (pe->pe_number << 1) + num, 2068bbb845c4SAlexey Kardashevskiy tbl->it_indirect_levels + 1, 206943cb60abSAlexey Kardashevskiy __pa(tbl->it_base), 2070bbb845c4SAlexey Kardashevskiy size << 3, 207143cb60abSAlexey Kardashevskiy IOMMU_PAGE_SIZE(tbl)); 207243cb60abSAlexey Kardashevskiy if (rc) { 207343cb60abSAlexey Kardashevskiy pe_err(pe, "Failed to configure TCE table, err %ld\n", rc); 207443cb60abSAlexey Kardashevskiy return rc; 207543cb60abSAlexey Kardashevskiy } 207643cb60abSAlexey Kardashevskiy 207743cb60abSAlexey Kardashevskiy pnv_pci_link_table_and_group(phb->hose->node, num, 207843cb60abSAlexey Kardashevskiy tbl, &pe->table_group); 207943cb60abSAlexey Kardashevskiy pnv_pci_ioda2_tce_invalidate_entire(pe); 208043cb60abSAlexey Kardashevskiy 208143cb60abSAlexey Kardashevskiy return 0; 208243cb60abSAlexey Kardashevskiy } 208343cb60abSAlexey Kardashevskiy 2084f87a8864SAlexey Kardashevskiy static void pnv_pci_ioda2_set_bypass(struct pnv_ioda_pe *pe, bool enable) 2085cd15b048SBenjamin Herrenschmidt { 2086cd15b048SBenjamin Herrenschmidt uint16_t window_id = (pe->pe_number << 1 ) + 1; 2087cd15b048SBenjamin Herrenschmidt int64_t rc; 2088cd15b048SBenjamin Herrenschmidt 2089cd15b048SBenjamin Herrenschmidt pe_info(pe, "%sabling 64-bit DMA bypass\n", enable ? "En" : "Dis"); 2090cd15b048SBenjamin Herrenschmidt if (enable) { 2091cd15b048SBenjamin Herrenschmidt phys_addr_t top = memblock_end_of_DRAM(); 2092cd15b048SBenjamin Herrenschmidt 2093cd15b048SBenjamin Herrenschmidt top = roundup_pow_of_two(top); 2094cd15b048SBenjamin Herrenschmidt rc = opal_pci_map_pe_dma_window_real(pe->phb->opal_id, 2095cd15b048SBenjamin Herrenschmidt pe->pe_number, 2096cd15b048SBenjamin Herrenschmidt window_id, 2097cd15b048SBenjamin Herrenschmidt pe->tce_bypass_base, 2098cd15b048SBenjamin Herrenschmidt top); 2099cd15b048SBenjamin Herrenschmidt } else { 2100cd15b048SBenjamin Herrenschmidt rc = opal_pci_map_pe_dma_window_real(pe->phb->opal_id, 2101cd15b048SBenjamin Herrenschmidt pe->pe_number, 2102cd15b048SBenjamin Herrenschmidt window_id, 2103cd15b048SBenjamin Herrenschmidt pe->tce_bypass_base, 2104cd15b048SBenjamin Herrenschmidt 0); 2105cd15b048SBenjamin Herrenschmidt } 2106cd15b048SBenjamin Herrenschmidt if (rc) 2107cd15b048SBenjamin Herrenschmidt pe_err(pe, "OPAL error %lld configuring bypass window\n", rc); 2108cd15b048SBenjamin Herrenschmidt else 2109cd15b048SBenjamin Herrenschmidt pe->tce_bypass_enabled = enable; 2110cd15b048SBenjamin Herrenschmidt } 2111cd15b048SBenjamin Herrenschmidt 21124793d65dSAlexey Kardashevskiy static long pnv_pci_ioda2_table_alloc_pages(int nid, __u64 bus_offset, 21134793d65dSAlexey Kardashevskiy __u32 page_shift, __u64 window_size, __u32 levels, 21144793d65dSAlexey Kardashevskiy struct iommu_table *tbl); 21154793d65dSAlexey Kardashevskiy 21164793d65dSAlexey Kardashevskiy static long pnv_pci_ioda2_create_table(struct iommu_table_group *table_group, 21174793d65dSAlexey Kardashevskiy int num, __u32 page_shift, __u64 window_size, __u32 levels, 21184793d65dSAlexey Kardashevskiy struct iommu_table **ptbl) 21194793d65dSAlexey Kardashevskiy { 21204793d65dSAlexey Kardashevskiy struct pnv_ioda_pe *pe = container_of(table_group, struct pnv_ioda_pe, 21214793d65dSAlexey Kardashevskiy table_group); 21224793d65dSAlexey Kardashevskiy int nid = pe->phb->hose->node; 21234793d65dSAlexey Kardashevskiy __u64 bus_offset = num ? pe->tce_bypass_base : table_group->tce32_start; 21244793d65dSAlexey Kardashevskiy long ret; 21254793d65dSAlexey Kardashevskiy struct iommu_table *tbl; 21264793d65dSAlexey Kardashevskiy 21274793d65dSAlexey Kardashevskiy tbl = pnv_pci_table_alloc(nid); 21284793d65dSAlexey Kardashevskiy if (!tbl) 21294793d65dSAlexey Kardashevskiy return -ENOMEM; 21304793d65dSAlexey Kardashevskiy 21314793d65dSAlexey Kardashevskiy ret = pnv_pci_ioda2_table_alloc_pages(nid, 21324793d65dSAlexey Kardashevskiy bus_offset, page_shift, window_size, 21334793d65dSAlexey Kardashevskiy levels, tbl); 21344793d65dSAlexey Kardashevskiy if (ret) { 21354793d65dSAlexey Kardashevskiy iommu_free_table(tbl, "pnv"); 21364793d65dSAlexey Kardashevskiy return ret; 21374793d65dSAlexey Kardashevskiy } 21384793d65dSAlexey Kardashevskiy 21394793d65dSAlexey Kardashevskiy tbl->it_ops = &pnv_ioda2_iommu_ops; 21404793d65dSAlexey Kardashevskiy if (pe->phb->ioda.tce_inval_reg) 21414793d65dSAlexey Kardashevskiy tbl->it_type |= (TCE_PCI_SWINV_CREATE | TCE_PCI_SWINV_FREE); 21424793d65dSAlexey Kardashevskiy 21434793d65dSAlexey Kardashevskiy *ptbl = tbl; 21444793d65dSAlexey Kardashevskiy 21454793d65dSAlexey Kardashevskiy return 0; 21464793d65dSAlexey Kardashevskiy } 21474793d65dSAlexey Kardashevskiy 214846d3e1e1SAlexey Kardashevskiy static long pnv_pci_ioda2_setup_default_config(struct pnv_ioda_pe *pe) 214946d3e1e1SAlexey Kardashevskiy { 215046d3e1e1SAlexey Kardashevskiy struct iommu_table *tbl = NULL; 215146d3e1e1SAlexey Kardashevskiy long rc; 215246d3e1e1SAlexey Kardashevskiy 2153bb005455SNishanth Aravamudan /* 2154fa144869SNishanth Aravamudan * crashkernel= specifies the kdump kernel's maximum memory at 2155fa144869SNishanth Aravamudan * some offset and there is no guaranteed the result is a power 2156fa144869SNishanth Aravamudan * of 2, which will cause errors later. 2157fa144869SNishanth Aravamudan */ 2158fa144869SNishanth Aravamudan const u64 max_memory = __rounddown_pow_of_two(memory_hotplug_max()); 2159fa144869SNishanth Aravamudan 2160fa144869SNishanth Aravamudan /* 2161bb005455SNishanth Aravamudan * In memory constrained environments, e.g. kdump kernel, the 2162bb005455SNishanth Aravamudan * DMA window can be larger than available memory, which will 2163bb005455SNishanth Aravamudan * cause errors later. 2164bb005455SNishanth Aravamudan */ 2165fa144869SNishanth Aravamudan const u64 window_size = min((u64)pe->table_group.tce32_size, max_memory); 2166bb005455SNishanth Aravamudan 216746d3e1e1SAlexey Kardashevskiy rc = pnv_pci_ioda2_create_table(&pe->table_group, 0, 216846d3e1e1SAlexey Kardashevskiy IOMMU_PAGE_SHIFT_4K, 2169bb005455SNishanth Aravamudan window_size, 217046d3e1e1SAlexey Kardashevskiy POWERNV_IOMMU_DEFAULT_LEVELS, &tbl); 217146d3e1e1SAlexey Kardashevskiy if (rc) { 217246d3e1e1SAlexey Kardashevskiy pe_err(pe, "Failed to create 32-bit TCE table, err %ld", 217346d3e1e1SAlexey Kardashevskiy rc); 217446d3e1e1SAlexey Kardashevskiy return rc; 217546d3e1e1SAlexey Kardashevskiy } 217646d3e1e1SAlexey Kardashevskiy 217746d3e1e1SAlexey Kardashevskiy iommu_init_table(tbl, pe->phb->hose->node); 217846d3e1e1SAlexey Kardashevskiy 217946d3e1e1SAlexey Kardashevskiy rc = pnv_pci_ioda2_set_window(&pe->table_group, 0, tbl); 218046d3e1e1SAlexey Kardashevskiy if (rc) { 218146d3e1e1SAlexey Kardashevskiy pe_err(pe, "Failed to configure 32-bit TCE table, err %ld\n", 218246d3e1e1SAlexey Kardashevskiy rc); 218346d3e1e1SAlexey Kardashevskiy pnv_ioda2_table_free(tbl); 218446d3e1e1SAlexey Kardashevskiy return rc; 218546d3e1e1SAlexey Kardashevskiy } 218646d3e1e1SAlexey Kardashevskiy 218746d3e1e1SAlexey Kardashevskiy if (!pnv_iommu_bypass_disabled) 218846d3e1e1SAlexey Kardashevskiy pnv_pci_ioda2_set_bypass(pe, true); 218946d3e1e1SAlexey Kardashevskiy 219046d3e1e1SAlexey Kardashevskiy /* OPAL variant of PHB3 invalidated TCEs */ 219146d3e1e1SAlexey Kardashevskiy if (pe->phb->ioda.tce_inval_reg) 219246d3e1e1SAlexey Kardashevskiy tbl->it_type |= (TCE_PCI_SWINV_CREATE | TCE_PCI_SWINV_FREE); 219346d3e1e1SAlexey Kardashevskiy 219446d3e1e1SAlexey Kardashevskiy /* 219546d3e1e1SAlexey Kardashevskiy * Setting table base here only for carrying iommu_group 219646d3e1e1SAlexey Kardashevskiy * further down to let iommu_add_device() do the job. 219746d3e1e1SAlexey Kardashevskiy * pnv_pci_ioda_dma_dev_setup will override it later anyway. 219846d3e1e1SAlexey Kardashevskiy */ 219946d3e1e1SAlexey Kardashevskiy if (pe->flags & PNV_IODA_PE_DEV) 220046d3e1e1SAlexey Kardashevskiy set_iommu_table_base(&pe->pdev->dev, tbl); 220146d3e1e1SAlexey Kardashevskiy 220246d3e1e1SAlexey Kardashevskiy return 0; 220346d3e1e1SAlexey Kardashevskiy } 220446d3e1e1SAlexey Kardashevskiy 2205b5926430SAlexey Kardashevskiy #if defined(CONFIG_IOMMU_API) || defined(CONFIG_PCI_IOV) 2206b5926430SAlexey Kardashevskiy static long pnv_pci_ioda2_unset_window(struct iommu_table_group *table_group, 2207b5926430SAlexey Kardashevskiy int num) 2208b5926430SAlexey Kardashevskiy { 2209b5926430SAlexey Kardashevskiy struct pnv_ioda_pe *pe = container_of(table_group, struct pnv_ioda_pe, 2210b5926430SAlexey Kardashevskiy table_group); 2211b5926430SAlexey Kardashevskiy struct pnv_phb *phb = pe->phb; 2212b5926430SAlexey Kardashevskiy long ret; 2213b5926430SAlexey Kardashevskiy 2214b5926430SAlexey Kardashevskiy pe_info(pe, "Removing DMA window #%d\n", num); 2215b5926430SAlexey Kardashevskiy 2216b5926430SAlexey Kardashevskiy ret = opal_pci_map_pe_dma_window(phb->opal_id, pe->pe_number, 2217b5926430SAlexey Kardashevskiy (pe->pe_number << 1) + num, 2218b5926430SAlexey Kardashevskiy 0/* levels */, 0/* table address */, 2219b5926430SAlexey Kardashevskiy 0/* table size */, 0/* page size */); 2220b5926430SAlexey Kardashevskiy if (ret) 2221b5926430SAlexey Kardashevskiy pe_warn(pe, "Unmapping failed, ret = %ld\n", ret); 2222b5926430SAlexey Kardashevskiy else 2223b5926430SAlexey Kardashevskiy pnv_pci_ioda2_tce_invalidate_entire(pe); 2224b5926430SAlexey Kardashevskiy 2225b5926430SAlexey Kardashevskiy pnv_pci_unlink_table_and_group(table_group->tables[num], table_group); 2226b5926430SAlexey Kardashevskiy 2227b5926430SAlexey Kardashevskiy return ret; 2228b5926430SAlexey Kardashevskiy } 2229b5926430SAlexey Kardashevskiy #endif 2230b5926430SAlexey Kardashevskiy 2231f87a8864SAlexey Kardashevskiy #ifdef CONFIG_IOMMU_API 223200547193SAlexey Kardashevskiy static unsigned long pnv_pci_ioda2_get_table_size(__u32 page_shift, 223300547193SAlexey Kardashevskiy __u64 window_size, __u32 levels) 223400547193SAlexey Kardashevskiy { 223500547193SAlexey Kardashevskiy unsigned long bytes = 0; 223600547193SAlexey Kardashevskiy const unsigned window_shift = ilog2(window_size); 223700547193SAlexey Kardashevskiy unsigned entries_shift = window_shift - page_shift; 223800547193SAlexey Kardashevskiy unsigned table_shift = entries_shift + 3; 223900547193SAlexey Kardashevskiy unsigned long tce_table_size = max(0x1000UL, 1UL << table_shift); 224000547193SAlexey Kardashevskiy unsigned long direct_table_size; 224100547193SAlexey Kardashevskiy 224200547193SAlexey Kardashevskiy if (!levels || (levels > POWERNV_IOMMU_MAX_LEVELS) || 224300547193SAlexey Kardashevskiy (window_size > memory_hotplug_max()) || 224400547193SAlexey Kardashevskiy !is_power_of_2(window_size)) 224500547193SAlexey Kardashevskiy return 0; 224600547193SAlexey Kardashevskiy 224700547193SAlexey Kardashevskiy /* Calculate a direct table size from window_size and levels */ 224800547193SAlexey Kardashevskiy entries_shift = (entries_shift + levels - 1) / levels; 224900547193SAlexey Kardashevskiy table_shift = entries_shift + 3; 225000547193SAlexey Kardashevskiy table_shift = max_t(unsigned, table_shift, PAGE_SHIFT); 225100547193SAlexey Kardashevskiy direct_table_size = 1UL << table_shift; 225200547193SAlexey Kardashevskiy 225300547193SAlexey Kardashevskiy for ( ; levels; --levels) { 225400547193SAlexey Kardashevskiy bytes += _ALIGN_UP(tce_table_size, direct_table_size); 225500547193SAlexey Kardashevskiy 225600547193SAlexey Kardashevskiy tce_table_size /= direct_table_size; 225700547193SAlexey Kardashevskiy tce_table_size <<= 3; 225800547193SAlexey Kardashevskiy tce_table_size = _ALIGN_UP(tce_table_size, direct_table_size); 225900547193SAlexey Kardashevskiy } 226000547193SAlexey Kardashevskiy 226100547193SAlexey Kardashevskiy return bytes; 226200547193SAlexey Kardashevskiy } 226300547193SAlexey Kardashevskiy 2264f87a8864SAlexey Kardashevskiy static void pnv_ioda2_take_ownership(struct iommu_table_group *table_group) 2265cd15b048SBenjamin Herrenschmidt { 2266f87a8864SAlexey Kardashevskiy struct pnv_ioda_pe *pe = container_of(table_group, struct pnv_ioda_pe, 2267f87a8864SAlexey Kardashevskiy table_group); 226846d3e1e1SAlexey Kardashevskiy /* Store @tbl as pnv_pci_ioda2_unset_window() resets it */ 226946d3e1e1SAlexey Kardashevskiy struct iommu_table *tbl = pe->table_group.tables[0]; 2270cd15b048SBenjamin Herrenschmidt 2271f87a8864SAlexey Kardashevskiy pnv_pci_ioda2_set_bypass(pe, false); 227246d3e1e1SAlexey Kardashevskiy pnv_pci_ioda2_unset_window(&pe->table_group, 0); 227346d3e1e1SAlexey Kardashevskiy pnv_ioda2_table_free(tbl); 2274cd15b048SBenjamin Herrenschmidt } 2275cd15b048SBenjamin Herrenschmidt 2276f87a8864SAlexey Kardashevskiy static void pnv_ioda2_release_ownership(struct iommu_table_group *table_group) 2277f87a8864SAlexey Kardashevskiy { 2278f87a8864SAlexey Kardashevskiy struct pnv_ioda_pe *pe = container_of(table_group, struct pnv_ioda_pe, 2279f87a8864SAlexey Kardashevskiy table_group); 2280f87a8864SAlexey Kardashevskiy 228146d3e1e1SAlexey Kardashevskiy pnv_pci_ioda2_setup_default_config(pe); 2282f87a8864SAlexey Kardashevskiy } 2283f87a8864SAlexey Kardashevskiy 2284f87a8864SAlexey Kardashevskiy static struct iommu_table_group_ops pnv_pci_ioda2_ops = { 228500547193SAlexey Kardashevskiy .get_table_size = pnv_pci_ioda2_get_table_size, 22864793d65dSAlexey Kardashevskiy .create_table = pnv_pci_ioda2_create_table, 22874793d65dSAlexey Kardashevskiy .set_window = pnv_pci_ioda2_set_window, 22884793d65dSAlexey Kardashevskiy .unset_window = pnv_pci_ioda2_unset_window, 2289f87a8864SAlexey Kardashevskiy .take_ownership = pnv_ioda2_take_ownership, 2290f87a8864SAlexey Kardashevskiy .release_ownership = pnv_ioda2_release_ownership, 2291f87a8864SAlexey Kardashevskiy }; 2292f87a8864SAlexey Kardashevskiy #endif 2293f87a8864SAlexey Kardashevskiy 22945780fb04SAlexey Kardashevskiy static void pnv_pci_ioda_setup_opal_tce_kill(struct pnv_phb *phb) 22955780fb04SAlexey Kardashevskiy { 22965780fb04SAlexey Kardashevskiy const __be64 *swinvp; 22975780fb04SAlexey Kardashevskiy 22985780fb04SAlexey Kardashevskiy /* OPAL variant of PHB3 invalidated TCEs */ 22995780fb04SAlexey Kardashevskiy swinvp = of_get_property(phb->hose->dn, "ibm,opal-tce-kill", NULL); 23005780fb04SAlexey Kardashevskiy if (!swinvp) 23015780fb04SAlexey Kardashevskiy return; 23025780fb04SAlexey Kardashevskiy 23035780fb04SAlexey Kardashevskiy phb->ioda.tce_inval_reg_phys = be64_to_cpup(swinvp); 23045780fb04SAlexey Kardashevskiy phb->ioda.tce_inval_reg = ioremap(phb->ioda.tce_inval_reg_phys, 8); 23055780fb04SAlexey Kardashevskiy } 23065780fb04SAlexey Kardashevskiy 2307bbb845c4SAlexey Kardashevskiy static __be64 *pnv_pci_ioda2_table_do_alloc_pages(int nid, unsigned shift, 2308bbb845c4SAlexey Kardashevskiy unsigned levels, unsigned long limit, 23093ba3a73eSAlexey Kardashevskiy unsigned long *current_offset, unsigned long *total_allocated) 2310aca6913fSAlexey Kardashevskiy { 2311aca6913fSAlexey Kardashevskiy struct page *tce_mem = NULL; 2312bbb845c4SAlexey Kardashevskiy __be64 *addr, *tmp; 2313aca6913fSAlexey Kardashevskiy unsigned order = max_t(unsigned, shift, PAGE_SHIFT) - PAGE_SHIFT; 2314bbb845c4SAlexey Kardashevskiy unsigned long allocated = 1UL << (order + PAGE_SHIFT); 2315bbb845c4SAlexey Kardashevskiy unsigned entries = 1UL << (shift - 3); 2316bbb845c4SAlexey Kardashevskiy long i; 2317aca6913fSAlexey Kardashevskiy 2318aca6913fSAlexey Kardashevskiy tce_mem = alloc_pages_node(nid, GFP_KERNEL, order); 2319aca6913fSAlexey Kardashevskiy if (!tce_mem) { 2320aca6913fSAlexey Kardashevskiy pr_err("Failed to allocate a TCE memory, order=%d\n", order); 2321aca6913fSAlexey Kardashevskiy return NULL; 2322aca6913fSAlexey Kardashevskiy } 2323aca6913fSAlexey Kardashevskiy addr = page_address(tce_mem); 2324bbb845c4SAlexey Kardashevskiy memset(addr, 0, allocated); 23253ba3a73eSAlexey Kardashevskiy *total_allocated += allocated; 2326bbb845c4SAlexey Kardashevskiy 2327bbb845c4SAlexey Kardashevskiy --levels; 2328bbb845c4SAlexey Kardashevskiy if (!levels) { 2329bbb845c4SAlexey Kardashevskiy *current_offset += allocated; 2330bbb845c4SAlexey Kardashevskiy return addr; 2331bbb845c4SAlexey Kardashevskiy } 2332bbb845c4SAlexey Kardashevskiy 2333bbb845c4SAlexey Kardashevskiy for (i = 0; i < entries; ++i) { 2334bbb845c4SAlexey Kardashevskiy tmp = pnv_pci_ioda2_table_do_alloc_pages(nid, shift, 23353ba3a73eSAlexey Kardashevskiy levels, limit, current_offset, total_allocated); 2336bbb845c4SAlexey Kardashevskiy if (!tmp) 2337bbb845c4SAlexey Kardashevskiy break; 2338bbb845c4SAlexey Kardashevskiy 2339bbb845c4SAlexey Kardashevskiy addr[i] = cpu_to_be64(__pa(tmp) | 2340bbb845c4SAlexey Kardashevskiy TCE_PCI_READ | TCE_PCI_WRITE); 2341bbb845c4SAlexey Kardashevskiy 2342bbb845c4SAlexey Kardashevskiy if (*current_offset >= limit) 2343bbb845c4SAlexey Kardashevskiy break; 2344bbb845c4SAlexey Kardashevskiy } 2345aca6913fSAlexey Kardashevskiy 2346aca6913fSAlexey Kardashevskiy return addr; 2347aca6913fSAlexey Kardashevskiy } 2348aca6913fSAlexey Kardashevskiy 2349bbb845c4SAlexey Kardashevskiy static void pnv_pci_ioda2_table_do_free_pages(__be64 *addr, 2350bbb845c4SAlexey Kardashevskiy unsigned long size, unsigned level); 2351bbb845c4SAlexey Kardashevskiy 2352aca6913fSAlexey Kardashevskiy static long pnv_pci_ioda2_table_alloc_pages(int nid, __u64 bus_offset, 2353bbb845c4SAlexey Kardashevskiy __u32 page_shift, __u64 window_size, __u32 levels, 2354bbb845c4SAlexey Kardashevskiy struct iommu_table *tbl) 2355aca6913fSAlexey Kardashevskiy { 2356aca6913fSAlexey Kardashevskiy void *addr; 23573ba3a73eSAlexey Kardashevskiy unsigned long offset = 0, level_shift, total_allocated = 0; 2358aca6913fSAlexey Kardashevskiy const unsigned window_shift = ilog2(window_size); 2359aca6913fSAlexey Kardashevskiy unsigned entries_shift = window_shift - page_shift; 2360aca6913fSAlexey Kardashevskiy unsigned table_shift = max_t(unsigned, entries_shift + 3, PAGE_SHIFT); 2361aca6913fSAlexey Kardashevskiy const unsigned long tce_table_size = 1UL << table_shift; 2362aca6913fSAlexey Kardashevskiy 2363bbb845c4SAlexey Kardashevskiy if (!levels || (levels > POWERNV_IOMMU_MAX_LEVELS)) 2364bbb845c4SAlexey Kardashevskiy return -EINVAL; 2365bbb845c4SAlexey Kardashevskiy 2366aca6913fSAlexey Kardashevskiy if ((window_size > memory_hotplug_max()) || !is_power_of_2(window_size)) 2367aca6913fSAlexey Kardashevskiy return -EINVAL; 2368aca6913fSAlexey Kardashevskiy 2369bbb845c4SAlexey Kardashevskiy /* Adjust direct table size from window_size and levels */ 2370bbb845c4SAlexey Kardashevskiy entries_shift = (entries_shift + levels - 1) / levels; 2371bbb845c4SAlexey Kardashevskiy level_shift = entries_shift + 3; 2372bbb845c4SAlexey Kardashevskiy level_shift = max_t(unsigned, level_shift, PAGE_SHIFT); 2373bbb845c4SAlexey Kardashevskiy 2374aca6913fSAlexey Kardashevskiy /* Allocate TCE table */ 2375bbb845c4SAlexey Kardashevskiy addr = pnv_pci_ioda2_table_do_alloc_pages(nid, level_shift, 23763ba3a73eSAlexey Kardashevskiy levels, tce_table_size, &offset, &total_allocated); 2377bbb845c4SAlexey Kardashevskiy 2378bbb845c4SAlexey Kardashevskiy /* addr==NULL means that the first level allocation failed */ 2379aca6913fSAlexey Kardashevskiy if (!addr) 2380aca6913fSAlexey Kardashevskiy return -ENOMEM; 2381aca6913fSAlexey Kardashevskiy 2382bbb845c4SAlexey Kardashevskiy /* 2383bbb845c4SAlexey Kardashevskiy * First level was allocated but some lower level failed as 2384bbb845c4SAlexey Kardashevskiy * we did not allocate as much as we wanted, 2385bbb845c4SAlexey Kardashevskiy * release partially allocated table. 2386bbb845c4SAlexey Kardashevskiy */ 2387bbb845c4SAlexey Kardashevskiy if (offset < tce_table_size) { 2388bbb845c4SAlexey Kardashevskiy pnv_pci_ioda2_table_do_free_pages(addr, 2389bbb845c4SAlexey Kardashevskiy 1ULL << (level_shift - 3), levels - 1); 2390bbb845c4SAlexey Kardashevskiy return -ENOMEM; 2391bbb845c4SAlexey Kardashevskiy } 2392bbb845c4SAlexey Kardashevskiy 2393aca6913fSAlexey Kardashevskiy /* Setup linux iommu table */ 2394aca6913fSAlexey Kardashevskiy pnv_pci_setup_iommu_table(tbl, addr, tce_table_size, bus_offset, 2395aca6913fSAlexey Kardashevskiy page_shift); 2396bbb845c4SAlexey Kardashevskiy tbl->it_level_size = 1ULL << (level_shift - 3); 2397bbb845c4SAlexey Kardashevskiy tbl->it_indirect_levels = levels - 1; 23983ba3a73eSAlexey Kardashevskiy tbl->it_allocated_size = total_allocated; 2399aca6913fSAlexey Kardashevskiy 2400aca6913fSAlexey Kardashevskiy pr_devel("Created TCE table: ws=%08llx ts=%lx @%08llx\n", 2401aca6913fSAlexey Kardashevskiy window_size, tce_table_size, bus_offset); 2402aca6913fSAlexey Kardashevskiy 2403aca6913fSAlexey Kardashevskiy return 0; 2404aca6913fSAlexey Kardashevskiy } 2405aca6913fSAlexey Kardashevskiy 2406bbb845c4SAlexey Kardashevskiy static void pnv_pci_ioda2_table_do_free_pages(__be64 *addr, 2407bbb845c4SAlexey Kardashevskiy unsigned long size, unsigned level) 2408bbb845c4SAlexey Kardashevskiy { 2409bbb845c4SAlexey Kardashevskiy const unsigned long addr_ul = (unsigned long) addr & 2410bbb845c4SAlexey Kardashevskiy ~(TCE_PCI_READ | TCE_PCI_WRITE); 2411bbb845c4SAlexey Kardashevskiy 2412bbb845c4SAlexey Kardashevskiy if (level) { 2413bbb845c4SAlexey Kardashevskiy long i; 2414bbb845c4SAlexey Kardashevskiy u64 *tmp = (u64 *) addr_ul; 2415bbb845c4SAlexey Kardashevskiy 2416bbb845c4SAlexey Kardashevskiy for (i = 0; i < size; ++i) { 2417bbb845c4SAlexey Kardashevskiy unsigned long hpa = be64_to_cpu(tmp[i]); 2418bbb845c4SAlexey Kardashevskiy 2419bbb845c4SAlexey Kardashevskiy if (!(hpa & (TCE_PCI_READ | TCE_PCI_WRITE))) 2420bbb845c4SAlexey Kardashevskiy continue; 2421bbb845c4SAlexey Kardashevskiy 2422bbb845c4SAlexey Kardashevskiy pnv_pci_ioda2_table_do_free_pages(__va(hpa), size, 2423bbb845c4SAlexey Kardashevskiy level - 1); 2424bbb845c4SAlexey Kardashevskiy } 2425bbb845c4SAlexey Kardashevskiy } 2426bbb845c4SAlexey Kardashevskiy 2427bbb845c4SAlexey Kardashevskiy free_pages(addr_ul, get_order(size << 3)); 2428bbb845c4SAlexey Kardashevskiy } 2429bbb845c4SAlexey Kardashevskiy 2430aca6913fSAlexey Kardashevskiy static void pnv_pci_ioda2_table_free_pages(struct iommu_table *tbl) 2431aca6913fSAlexey Kardashevskiy { 2432bbb845c4SAlexey Kardashevskiy const unsigned long size = tbl->it_indirect_levels ? 2433bbb845c4SAlexey Kardashevskiy tbl->it_level_size : tbl->it_size; 2434bbb845c4SAlexey Kardashevskiy 2435aca6913fSAlexey Kardashevskiy if (!tbl->it_size) 2436aca6913fSAlexey Kardashevskiy return; 2437aca6913fSAlexey Kardashevskiy 2438bbb845c4SAlexey Kardashevskiy pnv_pci_ioda2_table_do_free_pages((__be64 *)tbl->it_base, size, 2439bbb845c4SAlexey Kardashevskiy tbl->it_indirect_levels); 2440aca6913fSAlexey Kardashevskiy } 2441aca6913fSAlexey Kardashevskiy 2442373f5657SGavin Shan static void pnv_pci_ioda2_setup_dma_pe(struct pnv_phb *phb, 2443373f5657SGavin Shan struct pnv_ioda_pe *pe) 2444373f5657SGavin Shan { 2445373f5657SGavin Shan int64_t rc; 2446373f5657SGavin Shan 2447373f5657SGavin Shan /* We shouldn't already have a 32-bit DMA associated */ 2448373f5657SGavin Shan if (WARN_ON(pe->tce32_seg >= 0)) 2449373f5657SGavin Shan return; 2450373f5657SGavin Shan 2451f87a8864SAlexey Kardashevskiy /* TVE #1 is selected by PCI address bit 59 */ 2452f87a8864SAlexey Kardashevskiy pe->tce_bypass_base = 1ull << 59; 2453f87a8864SAlexey Kardashevskiy 2454b348aa65SAlexey Kardashevskiy iommu_register_group(&pe->table_group, phb->hose->global_number, 2455b348aa65SAlexey Kardashevskiy pe->pe_number); 2456c5773822SAlexey Kardashevskiy 2457373f5657SGavin Shan /* The PE will reserve all possible 32-bits space */ 2458373f5657SGavin Shan pe->tce32_seg = 0; 2459373f5657SGavin Shan pe_info(pe, "Setting up 32-bit TCE table at 0..%08x\n", 2460aca6913fSAlexey Kardashevskiy phb->ioda.m32_pci_base); 2461373f5657SGavin Shan 2462e5aad1e6SAlexey Kardashevskiy /* Setup linux iommu table */ 24634793d65dSAlexey Kardashevskiy pe->table_group.tce32_start = 0; 24644793d65dSAlexey Kardashevskiy pe->table_group.tce32_size = phb->ioda.m32_pci_base; 24654793d65dSAlexey Kardashevskiy pe->table_group.max_dynamic_windows_supported = 24664793d65dSAlexey Kardashevskiy IOMMU_TABLE_GROUP_MAX_TABLES; 24674793d65dSAlexey Kardashevskiy pe->table_group.max_levels = POWERNV_IOMMU_MAX_LEVELS; 24684793d65dSAlexey Kardashevskiy pe->table_group.pgsizes = SZ_4K | SZ_64K | SZ_16M; 2469e5aad1e6SAlexey Kardashevskiy #ifdef CONFIG_IOMMU_API 2470e5aad1e6SAlexey Kardashevskiy pe->table_group.ops = &pnv_pci_ioda2_ops; 2471e5aad1e6SAlexey Kardashevskiy #endif 2472e5aad1e6SAlexey Kardashevskiy 247346d3e1e1SAlexey Kardashevskiy rc = pnv_pci_ioda2_setup_default_config(pe); 2474373f5657SGavin Shan if (rc) { 2475373f5657SGavin Shan if (pe->tce32_seg >= 0) 2476373f5657SGavin Shan pe->tce32_seg = -1; 247746d3e1e1SAlexey Kardashevskiy return; 24780eaf4defSAlexey Kardashevskiy } 247946d3e1e1SAlexey Kardashevskiy 248046d3e1e1SAlexey Kardashevskiy if (pe->flags & PNV_IODA_PE_DEV) 248146d3e1e1SAlexey Kardashevskiy iommu_add_device(&pe->pdev->dev); 248246d3e1e1SAlexey Kardashevskiy else if (pe->flags & (PNV_IODA_PE_BUS | PNV_IODA_PE_BUS_ALL)) 248346d3e1e1SAlexey Kardashevskiy pnv_ioda_setup_bus_dma(pe, pe->pbus); 2484373f5657SGavin Shan } 2485373f5657SGavin Shan 2486cad5cef6SGreg Kroah-Hartman static void pnv_ioda_setup_dma(struct pnv_phb *phb) 2487184cd4a3SBenjamin Herrenschmidt { 2488184cd4a3SBenjamin Herrenschmidt struct pci_controller *hose = phb->hose; 2489184cd4a3SBenjamin Herrenschmidt unsigned int residual, remaining, segs, tw, base; 2490184cd4a3SBenjamin Herrenschmidt struct pnv_ioda_pe *pe; 2491184cd4a3SBenjamin Herrenschmidt 2492184cd4a3SBenjamin Herrenschmidt /* If we have more PE# than segments available, hand out one 2493184cd4a3SBenjamin Herrenschmidt * per PE until we run out and let the rest fail. If not, 2494184cd4a3SBenjamin Herrenschmidt * then we assign at least one segment per PE, plus more based 2495184cd4a3SBenjamin Herrenschmidt * on the amount of devices under that PE 2496184cd4a3SBenjamin Herrenschmidt */ 2497184cd4a3SBenjamin Herrenschmidt if (phb->ioda.dma_pe_count > phb->ioda.tce32_count) 2498184cd4a3SBenjamin Herrenschmidt residual = 0; 2499184cd4a3SBenjamin Herrenschmidt else 2500184cd4a3SBenjamin Herrenschmidt residual = phb->ioda.tce32_count - 2501184cd4a3SBenjamin Herrenschmidt phb->ioda.dma_pe_count; 2502184cd4a3SBenjamin Herrenschmidt 2503184cd4a3SBenjamin Herrenschmidt pr_info("PCI: Domain %04x has %ld available 32-bit DMA segments\n", 2504184cd4a3SBenjamin Herrenschmidt hose->global_number, phb->ioda.tce32_count); 2505184cd4a3SBenjamin Herrenschmidt pr_info("PCI: %d PE# for a total weight of %d\n", 2506184cd4a3SBenjamin Herrenschmidt phb->ioda.dma_pe_count, phb->ioda.dma_weight); 2507184cd4a3SBenjamin Herrenschmidt 25085780fb04SAlexey Kardashevskiy pnv_pci_ioda_setup_opal_tce_kill(phb); 25095780fb04SAlexey Kardashevskiy 2510184cd4a3SBenjamin Herrenschmidt /* Walk our PE list and configure their DMA segments, hand them 2511184cd4a3SBenjamin Herrenschmidt * out one base segment plus any residual segments based on 2512184cd4a3SBenjamin Herrenschmidt * weight 2513184cd4a3SBenjamin Herrenschmidt */ 2514184cd4a3SBenjamin Herrenschmidt remaining = phb->ioda.tce32_count; 2515184cd4a3SBenjamin Herrenschmidt tw = phb->ioda.dma_weight; 2516184cd4a3SBenjamin Herrenschmidt base = 0; 25177ebdf956SGavin Shan list_for_each_entry(pe, &phb->ioda.pe_dma_list, dma_link) { 2518184cd4a3SBenjamin Herrenschmidt if (!pe->dma_weight) 2519184cd4a3SBenjamin Herrenschmidt continue; 2520184cd4a3SBenjamin Herrenschmidt if (!remaining) { 2521184cd4a3SBenjamin Herrenschmidt pe_warn(pe, "No DMA32 resources available\n"); 2522184cd4a3SBenjamin Herrenschmidt continue; 2523184cd4a3SBenjamin Herrenschmidt } 2524184cd4a3SBenjamin Herrenschmidt segs = 1; 2525184cd4a3SBenjamin Herrenschmidt if (residual) { 2526184cd4a3SBenjamin Herrenschmidt segs += ((pe->dma_weight * residual) + (tw / 2)) / tw; 2527184cd4a3SBenjamin Herrenschmidt if (segs > remaining) 2528184cd4a3SBenjamin Herrenschmidt segs = remaining; 2529184cd4a3SBenjamin Herrenschmidt } 2530373f5657SGavin Shan 2531373f5657SGavin Shan /* 2532373f5657SGavin Shan * For IODA2 compliant PHB3, we needn't care about the weight. 2533373f5657SGavin Shan * The all available 32-bits DMA space will be assigned to 2534373f5657SGavin Shan * the specific PE. 2535373f5657SGavin Shan */ 2536373f5657SGavin Shan if (phb->type == PNV_PHB_IODA1) { 2537184cd4a3SBenjamin Herrenschmidt pe_info(pe, "DMA weight %d, assigned %d DMA32 segments\n", 2538184cd4a3SBenjamin Herrenschmidt pe->dma_weight, segs); 2539184cd4a3SBenjamin Herrenschmidt pnv_pci_ioda_setup_dma_pe(phb, pe, base, segs); 25405d2aa710SAlistair Popple } else if (phb->type == PNV_PHB_IODA2) { 2541373f5657SGavin Shan pe_info(pe, "Assign DMA32 space\n"); 2542373f5657SGavin Shan segs = 0; 2543373f5657SGavin Shan pnv_pci_ioda2_setup_dma_pe(phb, pe); 25445d2aa710SAlistair Popple } else if (phb->type == PNV_PHB_NPU) { 25455d2aa710SAlistair Popple /* 25465d2aa710SAlistair Popple * We initialise the DMA space for an NPU PHB 25475d2aa710SAlistair Popple * after setup of the PHB is complete as we 25485d2aa710SAlistair Popple * point the NPU TVT to the the same location 25495d2aa710SAlistair Popple * as the PHB3 TVT. 25505d2aa710SAlistair Popple */ 2551373f5657SGavin Shan } 2552373f5657SGavin Shan 2553184cd4a3SBenjamin Herrenschmidt remaining -= segs; 2554184cd4a3SBenjamin Herrenschmidt base += segs; 2555184cd4a3SBenjamin Herrenschmidt } 2556184cd4a3SBenjamin Herrenschmidt } 2557184cd4a3SBenjamin Herrenschmidt 2558184cd4a3SBenjamin Herrenschmidt #ifdef CONFIG_PCI_MSI 2559137436c9SGavin Shan static void pnv_ioda2_msi_eoi(struct irq_data *d) 2560137436c9SGavin Shan { 2561137436c9SGavin Shan unsigned int hw_irq = (unsigned int)irqd_to_hwirq(d); 2562137436c9SGavin Shan struct irq_chip *chip = irq_data_get_irq_chip(d); 2563137436c9SGavin Shan struct pnv_phb *phb = container_of(chip, struct pnv_phb, 2564137436c9SGavin Shan ioda.irq_chip); 2565137436c9SGavin Shan int64_t rc; 2566137436c9SGavin Shan 2567137436c9SGavin Shan rc = opal_pci_msi_eoi(phb->opal_id, hw_irq); 2568137436c9SGavin Shan WARN_ON_ONCE(rc); 2569137436c9SGavin Shan 2570137436c9SGavin Shan icp_native_eoi(d); 2571137436c9SGavin Shan } 2572137436c9SGavin Shan 2573fd9a1c26SIan Munsie 2574fd9a1c26SIan Munsie static void set_msi_irq_chip(struct pnv_phb *phb, unsigned int virq) 2575fd9a1c26SIan Munsie { 2576fd9a1c26SIan Munsie struct irq_data *idata; 2577fd9a1c26SIan Munsie struct irq_chip *ichip; 2578fd9a1c26SIan Munsie 2579fd9a1c26SIan Munsie if (phb->type != PNV_PHB_IODA2) 2580fd9a1c26SIan Munsie return; 2581fd9a1c26SIan Munsie 2582fd9a1c26SIan Munsie if (!phb->ioda.irq_chip_init) { 2583fd9a1c26SIan Munsie /* 2584fd9a1c26SIan Munsie * First time we setup an MSI IRQ, we need to setup the 2585fd9a1c26SIan Munsie * corresponding IRQ chip to route correctly. 2586fd9a1c26SIan Munsie */ 2587fd9a1c26SIan Munsie idata = irq_get_irq_data(virq); 2588fd9a1c26SIan Munsie ichip = irq_data_get_irq_chip(idata); 2589fd9a1c26SIan Munsie phb->ioda.irq_chip_init = 1; 2590fd9a1c26SIan Munsie phb->ioda.irq_chip = *ichip; 2591fd9a1c26SIan Munsie phb->ioda.irq_chip.irq_eoi = pnv_ioda2_msi_eoi; 2592fd9a1c26SIan Munsie } 2593fd9a1c26SIan Munsie irq_set_chip(virq, &phb->ioda.irq_chip); 2594fd9a1c26SIan Munsie } 2595fd9a1c26SIan Munsie 259680c49c7eSIan Munsie #ifdef CONFIG_CXL_BASE 259780c49c7eSIan Munsie 25986f963ec2SRyan Grimm struct device_node *pnv_pci_get_phb_node(struct pci_dev *dev) 259980c49c7eSIan Munsie { 260080c49c7eSIan Munsie struct pci_controller *hose = pci_bus_to_host(dev->bus); 260180c49c7eSIan Munsie 26026f963ec2SRyan Grimm return of_node_get(hose->dn); 260380c49c7eSIan Munsie } 26046f963ec2SRyan Grimm EXPORT_SYMBOL(pnv_pci_get_phb_node); 260580c49c7eSIan Munsie 26061212aa1cSRyan Grimm int pnv_phb_to_cxl_mode(struct pci_dev *dev, uint64_t mode) 260780c49c7eSIan Munsie { 260880c49c7eSIan Munsie struct pci_controller *hose = pci_bus_to_host(dev->bus); 260980c49c7eSIan Munsie struct pnv_phb *phb = hose->private_data; 261080c49c7eSIan Munsie struct pnv_ioda_pe *pe; 261180c49c7eSIan Munsie int rc; 261280c49c7eSIan Munsie 261380c49c7eSIan Munsie pe = pnv_ioda_get_pe(dev); 261480c49c7eSIan Munsie if (!pe) 261580c49c7eSIan Munsie return -ENODEV; 261680c49c7eSIan Munsie 261780c49c7eSIan Munsie pe_info(pe, "Switching PHB to CXL\n"); 261880c49c7eSIan Munsie 26191212aa1cSRyan Grimm rc = opal_pci_set_phb_cxl_mode(phb->opal_id, mode, pe->pe_number); 262080c49c7eSIan Munsie if (rc) 262180c49c7eSIan Munsie dev_err(&dev->dev, "opal_pci_set_phb_cxl_mode failed: %i\n", rc); 262280c49c7eSIan Munsie 262380c49c7eSIan Munsie return rc; 262480c49c7eSIan Munsie } 26251212aa1cSRyan Grimm EXPORT_SYMBOL(pnv_phb_to_cxl_mode); 262680c49c7eSIan Munsie 262780c49c7eSIan Munsie /* Find PHB for cxl dev and allocate MSI hwirqs? 262880c49c7eSIan Munsie * Returns the absolute hardware IRQ number 262980c49c7eSIan Munsie */ 263080c49c7eSIan Munsie int pnv_cxl_alloc_hwirqs(struct pci_dev *dev, int num) 263180c49c7eSIan Munsie { 263280c49c7eSIan Munsie struct pci_controller *hose = pci_bus_to_host(dev->bus); 263380c49c7eSIan Munsie struct pnv_phb *phb = hose->private_data; 263480c49c7eSIan Munsie int hwirq = msi_bitmap_alloc_hwirqs(&phb->msi_bmp, num); 263580c49c7eSIan Munsie 263680c49c7eSIan Munsie if (hwirq < 0) { 263780c49c7eSIan Munsie dev_warn(&dev->dev, "Failed to find a free MSI\n"); 263880c49c7eSIan Munsie return -ENOSPC; 263980c49c7eSIan Munsie } 264080c49c7eSIan Munsie 264180c49c7eSIan Munsie return phb->msi_base + hwirq; 264280c49c7eSIan Munsie } 264380c49c7eSIan Munsie EXPORT_SYMBOL(pnv_cxl_alloc_hwirqs); 264480c49c7eSIan Munsie 264580c49c7eSIan Munsie void pnv_cxl_release_hwirqs(struct pci_dev *dev, int hwirq, int num) 264680c49c7eSIan Munsie { 264780c49c7eSIan Munsie struct pci_controller *hose = pci_bus_to_host(dev->bus); 264880c49c7eSIan Munsie struct pnv_phb *phb = hose->private_data; 264980c49c7eSIan Munsie 265080c49c7eSIan Munsie msi_bitmap_free_hwirqs(&phb->msi_bmp, hwirq - phb->msi_base, num); 265180c49c7eSIan Munsie } 265280c49c7eSIan Munsie EXPORT_SYMBOL(pnv_cxl_release_hwirqs); 265380c49c7eSIan Munsie 265480c49c7eSIan Munsie void pnv_cxl_release_hwirq_ranges(struct cxl_irq_ranges *irqs, 265580c49c7eSIan Munsie struct pci_dev *dev) 265680c49c7eSIan Munsie { 265780c49c7eSIan Munsie struct pci_controller *hose = pci_bus_to_host(dev->bus); 265880c49c7eSIan Munsie struct pnv_phb *phb = hose->private_data; 265980c49c7eSIan Munsie int i, hwirq; 266080c49c7eSIan Munsie 266180c49c7eSIan Munsie for (i = 1; i < CXL_IRQ_RANGES; i++) { 266280c49c7eSIan Munsie if (!irqs->range[i]) 266380c49c7eSIan Munsie continue; 266480c49c7eSIan Munsie pr_devel("cxl release irq range 0x%x: offset: 0x%lx limit: %ld\n", 266580c49c7eSIan Munsie i, irqs->offset[i], 266680c49c7eSIan Munsie irqs->range[i]); 266780c49c7eSIan Munsie hwirq = irqs->offset[i] - phb->msi_base; 266880c49c7eSIan Munsie msi_bitmap_free_hwirqs(&phb->msi_bmp, hwirq, 266980c49c7eSIan Munsie irqs->range[i]); 267080c49c7eSIan Munsie } 267180c49c7eSIan Munsie } 267280c49c7eSIan Munsie EXPORT_SYMBOL(pnv_cxl_release_hwirq_ranges); 267380c49c7eSIan Munsie 267480c49c7eSIan Munsie int pnv_cxl_alloc_hwirq_ranges(struct cxl_irq_ranges *irqs, 267580c49c7eSIan Munsie struct pci_dev *dev, int num) 267680c49c7eSIan Munsie { 267780c49c7eSIan Munsie struct pci_controller *hose = pci_bus_to_host(dev->bus); 267880c49c7eSIan Munsie struct pnv_phb *phb = hose->private_data; 267980c49c7eSIan Munsie int i, hwirq, try; 268080c49c7eSIan Munsie 268180c49c7eSIan Munsie memset(irqs, 0, sizeof(struct cxl_irq_ranges)); 268280c49c7eSIan Munsie 268380c49c7eSIan Munsie /* 0 is reserved for the multiplexed PSL DSI interrupt */ 268480c49c7eSIan Munsie for (i = 1; i < CXL_IRQ_RANGES && num; i++) { 268580c49c7eSIan Munsie try = num; 268680c49c7eSIan Munsie while (try) { 268780c49c7eSIan Munsie hwirq = msi_bitmap_alloc_hwirqs(&phb->msi_bmp, try); 268880c49c7eSIan Munsie if (hwirq >= 0) 268980c49c7eSIan Munsie break; 269080c49c7eSIan Munsie try /= 2; 269180c49c7eSIan Munsie } 269280c49c7eSIan Munsie if (!try) 269380c49c7eSIan Munsie goto fail; 269480c49c7eSIan Munsie 269580c49c7eSIan Munsie irqs->offset[i] = phb->msi_base + hwirq; 269680c49c7eSIan Munsie irqs->range[i] = try; 269780c49c7eSIan Munsie pr_devel("cxl alloc irq range 0x%x: offset: 0x%lx limit: %li\n", 269880c49c7eSIan Munsie i, irqs->offset[i], irqs->range[i]); 269980c49c7eSIan Munsie num -= try; 270080c49c7eSIan Munsie } 270180c49c7eSIan Munsie if (num) 270280c49c7eSIan Munsie goto fail; 270380c49c7eSIan Munsie 270480c49c7eSIan Munsie return 0; 270580c49c7eSIan Munsie fail: 270680c49c7eSIan Munsie pnv_cxl_release_hwirq_ranges(irqs, dev); 270780c49c7eSIan Munsie return -ENOSPC; 270880c49c7eSIan Munsie } 270980c49c7eSIan Munsie EXPORT_SYMBOL(pnv_cxl_alloc_hwirq_ranges); 271080c49c7eSIan Munsie 271180c49c7eSIan Munsie int pnv_cxl_get_irq_count(struct pci_dev *dev) 271280c49c7eSIan Munsie { 271380c49c7eSIan Munsie struct pci_controller *hose = pci_bus_to_host(dev->bus); 271480c49c7eSIan Munsie struct pnv_phb *phb = hose->private_data; 271580c49c7eSIan Munsie 271680c49c7eSIan Munsie return phb->msi_bmp.irq_count; 271780c49c7eSIan Munsie } 271880c49c7eSIan Munsie EXPORT_SYMBOL(pnv_cxl_get_irq_count); 271980c49c7eSIan Munsie 272080c49c7eSIan Munsie int pnv_cxl_ioda_msi_setup(struct pci_dev *dev, unsigned int hwirq, 272180c49c7eSIan Munsie unsigned int virq) 272280c49c7eSIan Munsie { 272380c49c7eSIan Munsie struct pci_controller *hose = pci_bus_to_host(dev->bus); 272480c49c7eSIan Munsie struct pnv_phb *phb = hose->private_data; 272580c49c7eSIan Munsie unsigned int xive_num = hwirq - phb->msi_base; 272680c49c7eSIan Munsie struct pnv_ioda_pe *pe; 272780c49c7eSIan Munsie int rc; 272880c49c7eSIan Munsie 272980c49c7eSIan Munsie if (!(pe = pnv_ioda_get_pe(dev))) 273080c49c7eSIan Munsie return -ENODEV; 273180c49c7eSIan Munsie 273280c49c7eSIan Munsie /* Assign XIVE to PE */ 273380c49c7eSIan Munsie rc = opal_pci_set_xive_pe(phb->opal_id, pe->pe_number, xive_num); 273480c49c7eSIan Munsie if (rc) { 273580c49c7eSIan Munsie pe_warn(pe, "%s: OPAL error %d setting msi_base 0x%x " 273680c49c7eSIan Munsie "hwirq 0x%x XIVE 0x%x PE\n", 273780c49c7eSIan Munsie pci_name(dev), rc, phb->msi_base, hwirq, xive_num); 273880c49c7eSIan Munsie return -EIO; 273980c49c7eSIan Munsie } 274080c49c7eSIan Munsie set_msi_irq_chip(phb, virq); 274180c49c7eSIan Munsie 274280c49c7eSIan Munsie return 0; 274380c49c7eSIan Munsie } 274480c49c7eSIan Munsie EXPORT_SYMBOL(pnv_cxl_ioda_msi_setup); 274580c49c7eSIan Munsie #endif 274680c49c7eSIan Munsie 2747184cd4a3SBenjamin Herrenschmidt static int pnv_pci_ioda_msi_setup(struct pnv_phb *phb, struct pci_dev *dev, 2748137436c9SGavin Shan unsigned int hwirq, unsigned int virq, 2749137436c9SGavin Shan unsigned int is_64, struct msi_msg *msg) 2750184cd4a3SBenjamin Herrenschmidt { 2751184cd4a3SBenjamin Herrenschmidt struct pnv_ioda_pe *pe = pnv_ioda_get_pe(dev); 2752184cd4a3SBenjamin Herrenschmidt unsigned int xive_num = hwirq - phb->msi_base; 27533a1a4661SBenjamin Herrenschmidt __be32 data; 2754184cd4a3SBenjamin Herrenschmidt int rc; 2755184cd4a3SBenjamin Herrenschmidt 2756184cd4a3SBenjamin Herrenschmidt /* No PE assigned ? bail out ... no MSI for you ! */ 2757184cd4a3SBenjamin Herrenschmidt if (pe == NULL) 2758184cd4a3SBenjamin Herrenschmidt return -ENXIO; 2759184cd4a3SBenjamin Herrenschmidt 2760184cd4a3SBenjamin Herrenschmidt /* Check if we have an MVE */ 2761184cd4a3SBenjamin Herrenschmidt if (pe->mve_number < 0) 2762184cd4a3SBenjamin Herrenschmidt return -ENXIO; 2763184cd4a3SBenjamin Herrenschmidt 2764b72c1f65SBenjamin Herrenschmidt /* Force 32-bit MSI on some broken devices */ 276536074381SBenjamin Herrenschmidt if (dev->no_64bit_msi) 2766b72c1f65SBenjamin Herrenschmidt is_64 = 0; 2767b72c1f65SBenjamin Herrenschmidt 2768184cd4a3SBenjamin Herrenschmidt /* Assign XIVE to PE */ 2769184cd4a3SBenjamin Herrenschmidt rc = opal_pci_set_xive_pe(phb->opal_id, pe->pe_number, xive_num); 2770184cd4a3SBenjamin Herrenschmidt if (rc) { 2771184cd4a3SBenjamin Herrenschmidt pr_warn("%s: OPAL error %d setting XIVE %d PE\n", 2772184cd4a3SBenjamin Herrenschmidt pci_name(dev), rc, xive_num); 2773184cd4a3SBenjamin Herrenschmidt return -EIO; 2774184cd4a3SBenjamin Herrenschmidt } 2775184cd4a3SBenjamin Herrenschmidt 2776184cd4a3SBenjamin Herrenschmidt if (is_64) { 27773a1a4661SBenjamin Herrenschmidt __be64 addr64; 27783a1a4661SBenjamin Herrenschmidt 2779184cd4a3SBenjamin Herrenschmidt rc = opal_get_msi_64(phb->opal_id, pe->mve_number, xive_num, 1, 2780184cd4a3SBenjamin Herrenschmidt &addr64, &data); 2781184cd4a3SBenjamin Herrenschmidt if (rc) { 2782184cd4a3SBenjamin Herrenschmidt pr_warn("%s: OPAL error %d getting 64-bit MSI data\n", 2783184cd4a3SBenjamin Herrenschmidt pci_name(dev), rc); 2784184cd4a3SBenjamin Herrenschmidt return -EIO; 2785184cd4a3SBenjamin Herrenschmidt } 27863a1a4661SBenjamin Herrenschmidt msg->address_hi = be64_to_cpu(addr64) >> 32; 27873a1a4661SBenjamin Herrenschmidt msg->address_lo = be64_to_cpu(addr64) & 0xfffffffful; 2788184cd4a3SBenjamin Herrenschmidt } else { 27893a1a4661SBenjamin Herrenschmidt __be32 addr32; 27903a1a4661SBenjamin Herrenschmidt 2791184cd4a3SBenjamin Herrenschmidt rc = opal_get_msi_32(phb->opal_id, pe->mve_number, xive_num, 1, 2792184cd4a3SBenjamin Herrenschmidt &addr32, &data); 2793184cd4a3SBenjamin Herrenschmidt if (rc) { 2794184cd4a3SBenjamin Herrenschmidt pr_warn("%s: OPAL error %d getting 32-bit MSI data\n", 2795184cd4a3SBenjamin Herrenschmidt pci_name(dev), rc); 2796184cd4a3SBenjamin Herrenschmidt return -EIO; 2797184cd4a3SBenjamin Herrenschmidt } 2798184cd4a3SBenjamin Herrenschmidt msg->address_hi = 0; 27993a1a4661SBenjamin Herrenschmidt msg->address_lo = be32_to_cpu(addr32); 2800184cd4a3SBenjamin Herrenschmidt } 28013a1a4661SBenjamin Herrenschmidt msg->data = be32_to_cpu(data); 2802184cd4a3SBenjamin Herrenschmidt 2803fd9a1c26SIan Munsie set_msi_irq_chip(phb, virq); 2804137436c9SGavin Shan 2805184cd4a3SBenjamin Herrenschmidt pr_devel("%s: %s-bit MSI on hwirq %x (xive #%d)," 2806184cd4a3SBenjamin Herrenschmidt " address=%x_%08x data=%x PE# %d\n", 2807184cd4a3SBenjamin Herrenschmidt pci_name(dev), is_64 ? "64" : "32", hwirq, xive_num, 2808184cd4a3SBenjamin Herrenschmidt msg->address_hi, msg->address_lo, data, pe->pe_number); 2809184cd4a3SBenjamin Herrenschmidt 2810184cd4a3SBenjamin Herrenschmidt return 0; 2811184cd4a3SBenjamin Herrenschmidt } 2812184cd4a3SBenjamin Herrenschmidt 2813184cd4a3SBenjamin Herrenschmidt static void pnv_pci_init_ioda_msis(struct pnv_phb *phb) 2814184cd4a3SBenjamin Herrenschmidt { 2815fb1b55d6SGavin Shan unsigned int count; 2816184cd4a3SBenjamin Herrenschmidt const __be32 *prop = of_get_property(phb->hose->dn, 2817184cd4a3SBenjamin Herrenschmidt "ibm,opal-msi-ranges", NULL); 2818184cd4a3SBenjamin Herrenschmidt if (!prop) { 2819184cd4a3SBenjamin Herrenschmidt /* BML Fallback */ 2820184cd4a3SBenjamin Herrenschmidt prop = of_get_property(phb->hose->dn, "msi-ranges", NULL); 2821184cd4a3SBenjamin Herrenschmidt } 2822184cd4a3SBenjamin Herrenschmidt if (!prop) 2823184cd4a3SBenjamin Herrenschmidt return; 2824184cd4a3SBenjamin Herrenschmidt 2825184cd4a3SBenjamin Herrenschmidt phb->msi_base = be32_to_cpup(prop); 2826fb1b55d6SGavin Shan count = be32_to_cpup(prop + 1); 2827fb1b55d6SGavin Shan if (msi_bitmap_alloc(&phb->msi_bmp, count, phb->hose->dn)) { 2828184cd4a3SBenjamin Herrenschmidt pr_err("PCI %d: Failed to allocate MSI bitmap !\n", 2829184cd4a3SBenjamin Herrenschmidt phb->hose->global_number); 2830184cd4a3SBenjamin Herrenschmidt return; 2831184cd4a3SBenjamin Herrenschmidt } 2832fb1b55d6SGavin Shan 2833184cd4a3SBenjamin Herrenschmidt phb->msi_setup = pnv_pci_ioda_msi_setup; 2834184cd4a3SBenjamin Herrenschmidt phb->msi32_support = 1; 2835184cd4a3SBenjamin Herrenschmidt pr_info(" Allocated bitmap for %d MSIs (base IRQ 0x%x)\n", 2836fb1b55d6SGavin Shan count, phb->msi_base); 2837184cd4a3SBenjamin Herrenschmidt } 2838184cd4a3SBenjamin Herrenschmidt #else 2839184cd4a3SBenjamin Herrenschmidt static void pnv_pci_init_ioda_msis(struct pnv_phb *phb) { } 2840184cd4a3SBenjamin Herrenschmidt #endif /* CONFIG_PCI_MSI */ 2841184cd4a3SBenjamin Herrenschmidt 28426e628c7dSWei Yang #ifdef CONFIG_PCI_IOV 28436e628c7dSWei Yang static void pnv_pci_ioda_fixup_iov_resources(struct pci_dev *pdev) 28446e628c7dSWei Yang { 2845f2dd0afeSWei Yang struct pci_controller *hose = pci_bus_to_host(pdev->bus); 2846f2dd0afeSWei Yang struct pnv_phb *phb = hose->private_data; 2847f2dd0afeSWei Yang const resource_size_t gate = phb->ioda.m64_segsize >> 2; 28486e628c7dSWei Yang struct resource *res; 28496e628c7dSWei Yang int i; 2850dfcc8d45SWei Yang resource_size_t size, total_vf_bar_sz; 28516e628c7dSWei Yang struct pci_dn *pdn; 28525b88ec22SWei Yang int mul, total_vfs; 28536e628c7dSWei Yang 28546e628c7dSWei Yang if (!pdev->is_physfn || pdev->is_added) 28556e628c7dSWei Yang return; 28566e628c7dSWei Yang 28576e628c7dSWei Yang pdn = pci_get_pdn(pdev); 28586e628c7dSWei Yang pdn->vfs_expanded = 0; 2859ee8222feSWei Yang pdn->m64_single_mode = false; 28606e628c7dSWei Yang 28615b88ec22SWei Yang total_vfs = pci_sriov_get_totalvfs(pdev); 286292b8f137SGavin Shan mul = phb->ioda.total_pe_num; 2863dfcc8d45SWei Yang total_vf_bar_sz = 0; 28645b88ec22SWei Yang 28655b88ec22SWei Yang for (i = 0; i < PCI_SRIOV_NUM_BARS; i++) { 28665b88ec22SWei Yang res = &pdev->resource[i + PCI_IOV_RESOURCES]; 28675b88ec22SWei Yang if (!res->flags || res->parent) 28685b88ec22SWei Yang continue; 28695b88ec22SWei Yang if (!pnv_pci_is_mem_pref_64(res->flags)) { 2870b0331854SWei Yang dev_warn(&pdev->dev, "Don't support SR-IOV with" 2871b0331854SWei Yang " non M64 VF BAR%d: %pR. \n", 28725b88ec22SWei Yang i, res); 2873b0331854SWei Yang goto truncate_iov; 28745b88ec22SWei Yang } 28755b88ec22SWei Yang 2876dfcc8d45SWei Yang total_vf_bar_sz += pci_iov_resource_size(pdev, 2877dfcc8d45SWei Yang i + PCI_IOV_RESOURCES); 28785b88ec22SWei Yang 2879f2dd0afeSWei Yang /* 2880f2dd0afeSWei Yang * If bigger than quarter of M64 segment size, just round up 2881f2dd0afeSWei Yang * power of two. 2882f2dd0afeSWei Yang * 2883f2dd0afeSWei Yang * Generally, one M64 BAR maps one IOV BAR. To avoid conflict 2884f2dd0afeSWei Yang * with other devices, IOV BAR size is expanded to be 2885f2dd0afeSWei Yang * (total_pe * VF_BAR_size). When VF_BAR_size is half of M64 2886f2dd0afeSWei Yang * segment size , the expanded size would equal to half of the 2887f2dd0afeSWei Yang * whole M64 space size, which will exhaust the M64 Space and 2888f2dd0afeSWei Yang * limit the system flexibility. This is a design decision to 2889f2dd0afeSWei Yang * set the boundary to quarter of the M64 segment size. 2890f2dd0afeSWei Yang */ 2891dfcc8d45SWei Yang if (total_vf_bar_sz > gate) { 28925b88ec22SWei Yang mul = roundup_pow_of_two(total_vfs); 2893dfcc8d45SWei Yang dev_info(&pdev->dev, 2894dfcc8d45SWei Yang "VF BAR Total IOV size %llx > %llx, roundup to %d VFs\n", 2895dfcc8d45SWei Yang total_vf_bar_sz, gate, mul); 2896ee8222feSWei Yang pdn->m64_single_mode = true; 28975b88ec22SWei Yang break; 28985b88ec22SWei Yang } 28995b88ec22SWei Yang } 29005b88ec22SWei Yang 29016e628c7dSWei Yang for (i = 0; i < PCI_SRIOV_NUM_BARS; i++) { 29026e628c7dSWei Yang res = &pdev->resource[i + PCI_IOV_RESOURCES]; 29036e628c7dSWei Yang if (!res->flags || res->parent) 29046e628c7dSWei Yang continue; 29056e628c7dSWei Yang 29066e628c7dSWei Yang size = pci_iov_resource_size(pdev, i + PCI_IOV_RESOURCES); 2907ee8222feSWei Yang /* 2908ee8222feSWei Yang * On PHB3, the minimum size alignment of M64 BAR in single 2909ee8222feSWei Yang * mode is 32MB. 2910ee8222feSWei Yang */ 2911ee8222feSWei Yang if (pdn->m64_single_mode && (size < SZ_32M)) 2912ee8222feSWei Yang goto truncate_iov; 2913ee8222feSWei Yang dev_dbg(&pdev->dev, " Fixing VF BAR%d: %pR to\n", i, res); 29145b88ec22SWei Yang res->end = res->start + size * mul - 1; 29156e628c7dSWei Yang dev_dbg(&pdev->dev, " %pR\n", res); 29166e628c7dSWei Yang dev_info(&pdev->dev, "VF BAR%d: %pR (expanded to %d VFs for PE alignment)", 29175b88ec22SWei Yang i, res, mul); 29186e628c7dSWei Yang } 29195b88ec22SWei Yang pdn->vfs_expanded = mul; 2920b0331854SWei Yang 2921b0331854SWei Yang return; 2922b0331854SWei Yang 2923b0331854SWei Yang truncate_iov: 2924b0331854SWei Yang /* To save MMIO space, IOV BAR is truncated. */ 2925b0331854SWei Yang for (i = 0; i < PCI_SRIOV_NUM_BARS; i++) { 2926b0331854SWei Yang res = &pdev->resource[i + PCI_IOV_RESOURCES]; 2927b0331854SWei Yang res->flags = 0; 2928b0331854SWei Yang res->end = res->start - 1; 2929b0331854SWei Yang } 29306e628c7dSWei Yang } 29316e628c7dSWei Yang #endif /* CONFIG_PCI_IOV */ 29326e628c7dSWei Yang 293323e79425SGavin Shan static void pnv_ioda_setup_pe_res(struct pnv_ioda_pe *pe, 293423e79425SGavin Shan struct resource *res) 293511685becSGavin Shan { 293623e79425SGavin Shan struct pnv_phb *phb = pe->phb; 293711685becSGavin Shan struct pci_bus_region region; 293823e79425SGavin Shan int index; 293923e79425SGavin Shan int64_t rc; 294011685becSGavin Shan 294123e79425SGavin Shan if (!res || !res->flags || res->start > res->end) 294223e79425SGavin Shan return; 294311685becSGavin Shan 294411685becSGavin Shan if (res->flags & IORESOURCE_IO) { 294511685becSGavin Shan region.start = res->start - phb->ioda.io_pci_base; 294611685becSGavin Shan region.end = res->end - phb->ioda.io_pci_base; 294711685becSGavin Shan index = region.start / phb->ioda.io_segsize; 294811685becSGavin Shan 294992b8f137SGavin Shan while (index < phb->ioda.total_pe_num && 295011685becSGavin Shan region.start <= region.end) { 295111685becSGavin Shan phb->ioda.io_segmap[index] = pe->pe_number; 295211685becSGavin Shan rc = opal_pci_map_pe_mmio_window(phb->opal_id, 295311685becSGavin Shan pe->pe_number, OPAL_IO_WINDOW_TYPE, 0, index); 295411685becSGavin Shan if (rc != OPAL_SUCCESS) { 295523e79425SGavin Shan pr_err("%s: Error %lld mapping IO segment#%d to PE#%d\n", 295611685becSGavin Shan __func__, rc, index, pe->pe_number); 295711685becSGavin Shan break; 295811685becSGavin Shan } 295911685becSGavin Shan 296011685becSGavin Shan region.start += phb->ioda.io_segsize; 296111685becSGavin Shan index++; 296211685becSGavin Shan } 2963027fa02fSGavin Shan } else if ((res->flags & IORESOURCE_MEM) && 2964027fa02fSGavin Shan !pnv_pci_is_mem_pref_64(res->flags)) { 296511685becSGavin Shan region.start = res->start - 296623e79425SGavin Shan phb->hose->mem_offset[0] - 296711685becSGavin Shan phb->ioda.m32_pci_base; 296811685becSGavin Shan region.end = res->end - 296923e79425SGavin Shan phb->hose->mem_offset[0] - 297011685becSGavin Shan phb->ioda.m32_pci_base; 297111685becSGavin Shan index = region.start / phb->ioda.m32_segsize; 297211685becSGavin Shan 297392b8f137SGavin Shan while (index < phb->ioda.total_pe_num && 297411685becSGavin Shan region.start <= region.end) { 297511685becSGavin Shan phb->ioda.m32_segmap[index] = pe->pe_number; 297611685becSGavin Shan rc = opal_pci_map_pe_mmio_window(phb->opal_id, 297711685becSGavin Shan pe->pe_number, OPAL_M32_WINDOW_TYPE, 0, index); 297811685becSGavin Shan if (rc != OPAL_SUCCESS) { 297923e79425SGavin Shan pr_err("%s: Error %lld mapping M32 segment#%d to PE#%d", 298011685becSGavin Shan __func__, rc, index, pe->pe_number); 298111685becSGavin Shan break; 298211685becSGavin Shan } 298311685becSGavin Shan 298411685becSGavin Shan region.start += phb->ioda.m32_segsize; 298511685becSGavin Shan index++; 298611685becSGavin Shan } 298711685becSGavin Shan } 298811685becSGavin Shan } 298923e79425SGavin Shan 299023e79425SGavin Shan /* 299123e79425SGavin Shan * This function is supposed to be called on basis of PE from top 299223e79425SGavin Shan * to bottom style. So the the I/O or MMIO segment assigned to 299323e79425SGavin Shan * parent PE could be overrided by its child PEs if necessary. 299423e79425SGavin Shan */ 299523e79425SGavin Shan static void pnv_ioda_setup_pe_seg(struct pnv_ioda_pe *pe) 299623e79425SGavin Shan { 299769d733e7SGavin Shan struct pci_dev *pdev; 299823e79425SGavin Shan int i; 299923e79425SGavin Shan 300023e79425SGavin Shan /* 300123e79425SGavin Shan * NOTE: We only care PCI bus based PE for now. For PCI 300223e79425SGavin Shan * device based PE, for example SRIOV sensitive VF should 300323e79425SGavin Shan * be figured out later. 300423e79425SGavin Shan */ 300523e79425SGavin Shan BUG_ON(!(pe->flags & (PNV_IODA_PE_BUS | PNV_IODA_PE_BUS_ALL))); 300623e79425SGavin Shan 300769d733e7SGavin Shan list_for_each_entry(pdev, &pe->pbus->devices, bus_list) { 300869d733e7SGavin Shan for (i = 0; i <= PCI_ROM_RESOURCE; i++) 300969d733e7SGavin Shan pnv_ioda_setup_pe_res(pe, &pdev->resource[i]); 301069d733e7SGavin Shan 301169d733e7SGavin Shan /* 301269d733e7SGavin Shan * If the PE contains all subordinate PCI buses, the 301369d733e7SGavin Shan * windows of the child bridges should be mapped to 301469d733e7SGavin Shan * the PE as well. 301569d733e7SGavin Shan */ 301669d733e7SGavin Shan if (!(pe->flags & PNV_IODA_PE_BUS_ALL) || !pci_is_bridge(pdev)) 301769d733e7SGavin Shan continue; 301869d733e7SGavin Shan for (i = 0; i < PCI_BRIDGE_RESOURCE_NUM; i++) 301969d733e7SGavin Shan pnv_ioda_setup_pe_res(pe, 302069d733e7SGavin Shan &pdev->resource[PCI_BRIDGE_RESOURCES + i]); 302169d733e7SGavin Shan } 302211685becSGavin Shan } 302311685becSGavin Shan 3024cad5cef6SGreg Kroah-Hartman static void pnv_pci_ioda_setup_seg(void) 302511685becSGavin Shan { 302611685becSGavin Shan struct pci_controller *tmp, *hose; 302711685becSGavin Shan struct pnv_phb *phb; 302811685becSGavin Shan struct pnv_ioda_pe *pe; 302911685becSGavin Shan 303011685becSGavin Shan list_for_each_entry_safe(hose, tmp, &hose_list, list_node) { 303111685becSGavin Shan phb = hose->private_data; 30325d2aa710SAlistair Popple 30335d2aa710SAlistair Popple /* NPU PHB does not support IO or MMIO segmentation */ 30345d2aa710SAlistair Popple if (phb->type == PNV_PHB_NPU) 30355d2aa710SAlistair Popple continue; 30365d2aa710SAlistair Popple 303711685becSGavin Shan list_for_each_entry(pe, &phb->ioda.pe_list, list) { 303823e79425SGavin Shan pnv_ioda_setup_pe_seg(pe); 303911685becSGavin Shan } 304011685becSGavin Shan } 304111685becSGavin Shan } 304211685becSGavin Shan 3043cad5cef6SGreg Kroah-Hartman static void pnv_pci_ioda_setup_DMA(void) 304413395c48SGavin Shan { 304513395c48SGavin Shan struct pci_controller *hose, *tmp; 3046db1266c8SGavin Shan struct pnv_phb *phb; 304713395c48SGavin Shan 304813395c48SGavin Shan list_for_each_entry_safe(hose, tmp, &hose_list, list_node) { 304913395c48SGavin Shan pnv_ioda_setup_dma(hose->private_data); 3050db1266c8SGavin Shan 3051db1266c8SGavin Shan /* Mark the PHB initialization done */ 3052db1266c8SGavin Shan phb = hose->private_data; 3053db1266c8SGavin Shan phb->initialized = 1; 305413395c48SGavin Shan } 305513395c48SGavin Shan } 305613395c48SGavin Shan 305737c367f2SGavin Shan static void pnv_pci_ioda_create_dbgfs(void) 305837c367f2SGavin Shan { 305937c367f2SGavin Shan #ifdef CONFIG_DEBUG_FS 306037c367f2SGavin Shan struct pci_controller *hose, *tmp; 306137c367f2SGavin Shan struct pnv_phb *phb; 306237c367f2SGavin Shan char name[16]; 306337c367f2SGavin Shan 306437c367f2SGavin Shan list_for_each_entry_safe(hose, tmp, &hose_list, list_node) { 306537c367f2SGavin Shan phb = hose->private_data; 306637c367f2SGavin Shan 306737c367f2SGavin Shan sprintf(name, "PCI%04x", hose->global_number); 306837c367f2SGavin Shan phb->dbgfs = debugfs_create_dir(name, powerpc_debugfs_root); 306937c367f2SGavin Shan if (!phb->dbgfs) 307037c367f2SGavin Shan pr_warning("%s: Error on creating debugfs on PHB#%x\n", 307137c367f2SGavin Shan __func__, hose->global_number); 307237c367f2SGavin Shan } 307337c367f2SGavin Shan #endif /* CONFIG_DEBUG_FS */ 307437c367f2SGavin Shan } 307537c367f2SGavin Shan 30765d2aa710SAlistair Popple static void pnv_npu_ioda_fixup(void) 30775d2aa710SAlistair Popple { 30785d2aa710SAlistair Popple bool enable_bypass; 30795d2aa710SAlistair Popple struct pci_controller *hose, *tmp; 30805d2aa710SAlistair Popple struct pnv_phb *phb; 30815d2aa710SAlistair Popple struct pnv_ioda_pe *pe; 30825d2aa710SAlistair Popple 30835d2aa710SAlistair Popple list_for_each_entry_safe(hose, tmp, &hose_list, list_node) { 30845d2aa710SAlistair Popple phb = hose->private_data; 30855d2aa710SAlistair Popple if (phb->type != PNV_PHB_NPU) 30865d2aa710SAlistair Popple continue; 30875d2aa710SAlistair Popple 30885d2aa710SAlistair Popple list_for_each_entry(pe, &phb->ioda.pe_dma_list, dma_link) { 30895d2aa710SAlistair Popple enable_bypass = dma_get_mask(&pe->pdev->dev) == 30905d2aa710SAlistair Popple DMA_BIT_MASK(64); 30915d2aa710SAlistair Popple pnv_npu_init_dma_pe(pe); 30925d2aa710SAlistair Popple pnv_npu_dma_set_bypass(pe, enable_bypass); 30935d2aa710SAlistair Popple } 30945d2aa710SAlistair Popple } 30955d2aa710SAlistair Popple } 30965d2aa710SAlistair Popple 3097cad5cef6SGreg Kroah-Hartman static void pnv_pci_ioda_fixup(void) 3098fb446ad0SGavin Shan { 3099fb446ad0SGavin Shan pnv_pci_ioda_setup_PEs(); 310011685becSGavin Shan pnv_pci_ioda_setup_seg(); 310113395c48SGavin Shan pnv_pci_ioda_setup_DMA(); 3102e9cc17d4SGavin Shan 310337c367f2SGavin Shan pnv_pci_ioda_create_dbgfs(); 310437c367f2SGavin Shan 3105e9cc17d4SGavin Shan #ifdef CONFIG_EEH 3106e9cc17d4SGavin Shan eeh_init(); 3107dadcd6d6SMike Qiu eeh_addr_cache_build(); 3108e9cc17d4SGavin Shan #endif 31095d2aa710SAlistair Popple 31105d2aa710SAlistair Popple /* Link NPU IODA tables to their PCI devices. */ 31115d2aa710SAlistair Popple pnv_npu_ioda_fixup(); 3112fb446ad0SGavin Shan } 3113fb446ad0SGavin Shan 3114271fd03aSGavin Shan /* 3115271fd03aSGavin Shan * Returns the alignment for I/O or memory windows for P2P 3116271fd03aSGavin Shan * bridges. That actually depends on how PEs are segmented. 3117271fd03aSGavin Shan * For now, we return I/O or M32 segment size for PE sensitive 3118271fd03aSGavin Shan * P2P bridges. Otherwise, the default values (4KiB for I/O, 3119271fd03aSGavin Shan * 1MiB for memory) will be returned. 3120271fd03aSGavin Shan * 3121271fd03aSGavin Shan * The current PCI bus might be put into one PE, which was 3122271fd03aSGavin Shan * create against the parent PCI bridge. For that case, we 3123271fd03aSGavin Shan * needn't enlarge the alignment so that we can save some 3124271fd03aSGavin Shan * resources. 3125271fd03aSGavin Shan */ 3126271fd03aSGavin Shan static resource_size_t pnv_pci_window_alignment(struct pci_bus *bus, 3127271fd03aSGavin Shan unsigned long type) 3128271fd03aSGavin Shan { 3129271fd03aSGavin Shan struct pci_dev *bridge; 3130271fd03aSGavin Shan struct pci_controller *hose = pci_bus_to_host(bus); 3131271fd03aSGavin Shan struct pnv_phb *phb = hose->private_data; 3132271fd03aSGavin Shan int num_pci_bridges = 0; 3133271fd03aSGavin Shan 3134271fd03aSGavin Shan bridge = bus->self; 3135271fd03aSGavin Shan while (bridge) { 3136271fd03aSGavin Shan if (pci_pcie_type(bridge) == PCI_EXP_TYPE_PCI_BRIDGE) { 3137271fd03aSGavin Shan num_pci_bridges++; 3138271fd03aSGavin Shan if (num_pci_bridges >= 2) 3139271fd03aSGavin Shan return 1; 3140271fd03aSGavin Shan } 3141271fd03aSGavin Shan 3142271fd03aSGavin Shan bridge = bridge->bus->self; 3143271fd03aSGavin Shan } 3144271fd03aSGavin Shan 3145262af557SGuo Chao /* We fail back to M32 if M64 isn't supported */ 3146262af557SGuo Chao if (phb->ioda.m64_segsize && 3147262af557SGuo Chao pnv_pci_is_mem_pref_64(type)) 3148262af557SGuo Chao return phb->ioda.m64_segsize; 3149271fd03aSGavin Shan if (type & IORESOURCE_MEM) 3150271fd03aSGavin Shan return phb->ioda.m32_segsize; 3151271fd03aSGavin Shan 3152271fd03aSGavin Shan return phb->ioda.io_segsize; 3153271fd03aSGavin Shan } 3154271fd03aSGavin Shan 31555350ab3fSWei Yang #ifdef CONFIG_PCI_IOV 31565350ab3fSWei Yang static resource_size_t pnv_pci_iov_resource_alignment(struct pci_dev *pdev, 31575350ab3fSWei Yang int resno) 31585350ab3fSWei Yang { 3159ee8222feSWei Yang struct pci_controller *hose = pci_bus_to_host(pdev->bus); 3160ee8222feSWei Yang struct pnv_phb *phb = hose->private_data; 31615350ab3fSWei Yang struct pci_dn *pdn = pci_get_pdn(pdev); 31627fbe7a93SWei Yang resource_size_t align; 31635350ab3fSWei Yang 31647fbe7a93SWei Yang /* 31657fbe7a93SWei Yang * On PowerNV platform, IOV BAR is mapped by M64 BAR to enable the 31667fbe7a93SWei Yang * SR-IOV. While from hardware perspective, the range mapped by M64 31677fbe7a93SWei Yang * BAR should be size aligned. 31687fbe7a93SWei Yang * 3169ee8222feSWei Yang * When IOV BAR is mapped with M64 BAR in Single PE mode, the extra 3170ee8222feSWei Yang * powernv-specific hardware restriction is gone. But if just use the 3171ee8222feSWei Yang * VF BAR size as the alignment, PF BAR / VF BAR may be allocated with 3172ee8222feSWei Yang * in one segment of M64 #15, which introduces the PE conflict between 3173ee8222feSWei Yang * PF and VF. Based on this, the minimum alignment of an IOV BAR is 3174ee8222feSWei Yang * m64_segsize. 3175ee8222feSWei Yang * 31767fbe7a93SWei Yang * This function returns the total IOV BAR size if M64 BAR is in 31777fbe7a93SWei Yang * Shared PE mode or just VF BAR size if not. 3178ee8222feSWei Yang * If the M64 BAR is in Single PE mode, return the VF BAR size or 3179ee8222feSWei Yang * M64 segment size if IOV BAR size is less. 31807fbe7a93SWei Yang */ 31815350ab3fSWei Yang align = pci_iov_resource_size(pdev, resno); 31827fbe7a93SWei Yang if (!pdn->vfs_expanded) 31835350ab3fSWei Yang return align; 3184ee8222feSWei Yang if (pdn->m64_single_mode) 3185ee8222feSWei Yang return max(align, (resource_size_t)phb->ioda.m64_segsize); 31867fbe7a93SWei Yang 31877fbe7a93SWei Yang return pdn->vfs_expanded * align; 31885350ab3fSWei Yang } 31895350ab3fSWei Yang #endif /* CONFIG_PCI_IOV */ 31905350ab3fSWei Yang 3191184cd4a3SBenjamin Herrenschmidt /* Prevent enabling devices for which we couldn't properly 3192184cd4a3SBenjamin Herrenschmidt * assign a PE 3193184cd4a3SBenjamin Herrenschmidt */ 3194c88c2a18SDaniel Axtens static bool pnv_pci_enable_device_hook(struct pci_dev *dev) 3195184cd4a3SBenjamin Herrenschmidt { 3196db1266c8SGavin Shan struct pci_controller *hose = pci_bus_to_host(dev->bus); 3197db1266c8SGavin Shan struct pnv_phb *phb = hose->private_data; 3198db1266c8SGavin Shan struct pci_dn *pdn; 3199184cd4a3SBenjamin Herrenschmidt 3200db1266c8SGavin Shan /* The function is probably called while the PEs have 3201db1266c8SGavin Shan * not be created yet. For example, resource reassignment 3202db1266c8SGavin Shan * during PCI probe period. We just skip the check if 3203db1266c8SGavin Shan * PEs isn't ready. 3204db1266c8SGavin Shan */ 3205db1266c8SGavin Shan if (!phb->initialized) 3206c88c2a18SDaniel Axtens return true; 3207db1266c8SGavin Shan 3208b72c1f65SBenjamin Herrenschmidt pdn = pci_get_pdn(dev); 3209184cd4a3SBenjamin Herrenschmidt if (!pdn || pdn->pe_number == IODA_INVALID_PE) 3210c88c2a18SDaniel Axtens return false; 3211db1266c8SGavin Shan 3212c88c2a18SDaniel Axtens return true; 3213184cd4a3SBenjamin Herrenschmidt } 3214184cd4a3SBenjamin Herrenschmidt 32157a8e6bbfSMichael Neuling static void pnv_pci_ioda_shutdown(struct pci_controller *hose) 321673ed148aSBenjamin Herrenschmidt { 32177a8e6bbfSMichael Neuling struct pnv_phb *phb = hose->private_data; 32187a8e6bbfSMichael Neuling 3219d1a85eeeSGavin Shan opal_pci_reset(phb->opal_id, OPAL_RESET_PCI_IODA_TABLE, 322073ed148aSBenjamin Herrenschmidt OPAL_ASSERT_RESET); 322173ed148aSBenjamin Herrenschmidt } 322273ed148aSBenjamin Herrenschmidt 322392ae0353SDaniel Axtens static const struct pci_controller_ops pnv_pci_ioda_controller_ops = { 322492ae0353SDaniel Axtens .dma_dev_setup = pnv_pci_dma_dev_setup, 32251bc74f1cSGavin Shan .dma_bus_setup = pnv_pci_dma_bus_setup, 322692ae0353SDaniel Axtens #ifdef CONFIG_PCI_MSI 322792ae0353SDaniel Axtens .setup_msi_irqs = pnv_setup_msi_irqs, 322892ae0353SDaniel Axtens .teardown_msi_irqs = pnv_teardown_msi_irqs, 322992ae0353SDaniel Axtens #endif 323092ae0353SDaniel Axtens .enable_device_hook = pnv_pci_enable_device_hook, 323192ae0353SDaniel Axtens .window_alignment = pnv_pci_window_alignment, 323292ae0353SDaniel Axtens .reset_secondary_bus = pnv_pci_reset_secondary_bus, 3233763d2d8dSDaniel Axtens .dma_set_mask = pnv_pci_ioda_dma_set_mask, 323453522982SAndrew Donnellan .dma_get_required_mask = pnv_pci_ioda_dma_get_required_mask, 32357a8e6bbfSMichael Neuling .shutdown = pnv_pci_ioda_shutdown, 323692ae0353SDaniel Axtens }; 323792ae0353SDaniel Axtens 32385d2aa710SAlistair Popple static const struct pci_controller_ops pnv_npu_ioda_controller_ops = { 32395d2aa710SAlistair Popple .dma_dev_setup = pnv_pci_dma_dev_setup, 32405d2aa710SAlistair Popple #ifdef CONFIG_PCI_MSI 32415d2aa710SAlistair Popple .setup_msi_irqs = pnv_setup_msi_irqs, 32425d2aa710SAlistair Popple .teardown_msi_irqs = pnv_teardown_msi_irqs, 32435d2aa710SAlistair Popple #endif 32445d2aa710SAlistair Popple .enable_device_hook = pnv_pci_enable_device_hook, 32455d2aa710SAlistair Popple .window_alignment = pnv_pci_window_alignment, 32465d2aa710SAlistair Popple .reset_secondary_bus = pnv_pci_reset_secondary_bus, 32475d2aa710SAlistair Popple .dma_set_mask = pnv_npu_dma_set_mask, 32485d2aa710SAlistair Popple .shutdown = pnv_pci_ioda_shutdown, 32495d2aa710SAlistair Popple }; 32505d2aa710SAlistair Popple 3251e51df2c1SAnton Blanchard static void __init pnv_pci_init_ioda_phb(struct device_node *np, 3252e9cc17d4SGavin Shan u64 hub_id, int ioda_type) 3253184cd4a3SBenjamin Herrenschmidt { 3254184cd4a3SBenjamin Herrenschmidt struct pci_controller *hose; 3255184cd4a3SBenjamin Herrenschmidt struct pnv_phb *phb; 325693289d8cSGavin Shan unsigned long size, m64map_off, m32map_off, pemap_off, iomap_off = 0; 3257c681b93cSAlistair Popple const __be64 *prop64; 32583a1a4661SBenjamin Herrenschmidt const __be32 *prop32; 3259f1b7cc3eSGavin Shan int len; 32603fa23ff8SGavin Shan unsigned int segno; 3261184cd4a3SBenjamin Herrenschmidt u64 phb_id; 3262184cd4a3SBenjamin Herrenschmidt void *aux; 3263184cd4a3SBenjamin Herrenschmidt long rc; 3264184cd4a3SBenjamin Herrenschmidt 3265aa0c033fSGavin Shan pr_info("Initializing IODA%d OPAL PHB %s\n", ioda_type, np->full_name); 3266184cd4a3SBenjamin Herrenschmidt 3267184cd4a3SBenjamin Herrenschmidt prop64 = of_get_property(np, "ibm,opal-phbid", NULL); 3268184cd4a3SBenjamin Herrenschmidt if (!prop64) { 3269184cd4a3SBenjamin Herrenschmidt pr_err(" Missing \"ibm,opal-phbid\" property !\n"); 3270184cd4a3SBenjamin Herrenschmidt return; 3271184cd4a3SBenjamin Herrenschmidt } 3272184cd4a3SBenjamin Herrenschmidt phb_id = be64_to_cpup(prop64); 3273184cd4a3SBenjamin Herrenschmidt pr_debug(" PHB-ID : 0x%016llx\n", phb_id); 3274184cd4a3SBenjamin Herrenschmidt 3275e39f223fSMichael Ellerman phb = memblock_virt_alloc(sizeof(struct pnv_phb), 0); 327658d714ecSGavin Shan 327758d714ecSGavin Shan /* Allocate PCI controller */ 3278184cd4a3SBenjamin Herrenschmidt phb->hose = hose = pcibios_alloc_controller(np); 327958d714ecSGavin Shan if (!phb->hose) { 328058d714ecSGavin Shan pr_err(" Can't allocate PCI controller for %s\n", 3281184cd4a3SBenjamin Herrenschmidt np->full_name); 3282e39f223fSMichael Ellerman memblock_free(__pa(phb), sizeof(struct pnv_phb)); 3283184cd4a3SBenjamin Herrenschmidt return; 3284184cd4a3SBenjamin Herrenschmidt } 3285184cd4a3SBenjamin Herrenschmidt 3286184cd4a3SBenjamin Herrenschmidt spin_lock_init(&phb->lock); 3287f1b7cc3eSGavin Shan prop32 = of_get_property(np, "bus-range", &len); 3288f1b7cc3eSGavin Shan if (prop32 && len == 8) { 32893a1a4661SBenjamin Herrenschmidt hose->first_busno = be32_to_cpu(prop32[0]); 32903a1a4661SBenjamin Herrenschmidt hose->last_busno = be32_to_cpu(prop32[1]); 3291f1b7cc3eSGavin Shan } else { 3292f1b7cc3eSGavin Shan pr_warn(" Broken <bus-range> on %s\n", np->full_name); 3293184cd4a3SBenjamin Herrenschmidt hose->first_busno = 0; 3294184cd4a3SBenjamin Herrenschmidt hose->last_busno = 0xff; 3295f1b7cc3eSGavin Shan } 3296184cd4a3SBenjamin Herrenschmidt hose->private_data = phb; 3297e9cc17d4SGavin Shan phb->hub_id = hub_id; 3298184cd4a3SBenjamin Herrenschmidt phb->opal_id = phb_id; 3299aa0c033fSGavin Shan phb->type = ioda_type; 3300781a868fSWei Yang mutex_init(&phb->ioda.pe_alloc_mutex); 3301184cd4a3SBenjamin Herrenschmidt 3302cee72d5bSBenjamin Herrenschmidt /* Detect specific models for error handling */ 3303cee72d5bSBenjamin Herrenschmidt if (of_device_is_compatible(np, "ibm,p7ioc-pciex")) 3304cee72d5bSBenjamin Herrenschmidt phb->model = PNV_PHB_MODEL_P7IOC; 3305f3d40c25SBenjamin Herrenschmidt else if (of_device_is_compatible(np, "ibm,power8-pciex")) 3306aa0c033fSGavin Shan phb->model = PNV_PHB_MODEL_PHB3; 33075d2aa710SAlistair Popple else if (of_device_is_compatible(np, "ibm,power8-npu-pciex")) 33085d2aa710SAlistair Popple phb->model = PNV_PHB_MODEL_NPU; 3309cee72d5bSBenjamin Herrenschmidt else 3310cee72d5bSBenjamin Herrenschmidt phb->model = PNV_PHB_MODEL_UNKNOWN; 3311cee72d5bSBenjamin Herrenschmidt 3312aa0c033fSGavin Shan /* Parse 32-bit and IO ranges (if any) */ 33132f1ec02eSGavin Shan pci_process_bridge_OF_ranges(hose, np, !hose->global_number); 3314184cd4a3SBenjamin Herrenschmidt 3315aa0c033fSGavin Shan /* Get registers */ 3316184cd4a3SBenjamin Herrenschmidt phb->regs = of_iomap(np, 0); 3317184cd4a3SBenjamin Herrenschmidt if (phb->regs == NULL) 3318184cd4a3SBenjamin Herrenschmidt pr_err(" Failed to map registers !\n"); 3319184cd4a3SBenjamin Herrenschmidt 3320184cd4a3SBenjamin Herrenschmidt /* Initialize more IODA stuff */ 332192b8f137SGavin Shan phb->ioda.total_pe_num = 1; 332236954dc7SGavin Shan prop32 = of_get_property(np, "ibm,opal-num-pes", NULL); 332336954dc7SGavin Shan if (prop32) 332492b8f137SGavin Shan phb->ioda.total_pe_num = be32_to_cpup(prop32); 332536954dc7SGavin Shan prop32 = of_get_property(np, "ibm,opal-reserved-pe", NULL); 332636954dc7SGavin Shan if (prop32) 332792b8f137SGavin Shan phb->ioda.reserved_pe_idx = be32_to_cpup(prop32); 3328262af557SGuo Chao 3329262af557SGuo Chao /* Parse 64-bit MMIO range */ 3330262af557SGuo Chao pnv_ioda_parse_m64_window(phb); 3331262af557SGuo Chao 3332184cd4a3SBenjamin Herrenschmidt phb->ioda.m32_size = resource_size(&hose->mem_resources[0]); 3333aa0c033fSGavin Shan /* FW Has already off top 64k of M32 space (MSI space) */ 3334184cd4a3SBenjamin Herrenschmidt phb->ioda.m32_size += 0x10000; 3335184cd4a3SBenjamin Herrenschmidt 333692b8f137SGavin Shan phb->ioda.m32_segsize = phb->ioda.m32_size / phb->ioda.total_pe_num; 33373fd47f06SBenjamin Herrenschmidt phb->ioda.m32_pci_base = hose->mem_resources[0].start - hose->mem_offset[0]; 3338184cd4a3SBenjamin Herrenschmidt phb->ioda.io_size = hose->pci_io_size; 333992b8f137SGavin Shan phb->ioda.io_segsize = phb->ioda.io_size / phb->ioda.total_pe_num; 3340184cd4a3SBenjamin Herrenschmidt phb->ioda.io_pci_base = 0; /* XXX calculate this ? */ 3341184cd4a3SBenjamin Herrenschmidt 3342c35d2a8cSGavin Shan /* Allocate aux data & arrays. We don't have IO ports on PHB3 */ 334392b8f137SGavin Shan size = _ALIGN_UP(phb->ioda.total_pe_num / 8, sizeof(unsigned long)); 334493289d8cSGavin Shan m64map_off = size; 334593289d8cSGavin Shan size += phb->ioda.total_pe_num * sizeof(phb->ioda.m64_segmap[0]); 3346184cd4a3SBenjamin Herrenschmidt m32map_off = size; 334792b8f137SGavin Shan size += phb->ioda.total_pe_num * sizeof(phb->ioda.m32_segmap[0]); 3348c35d2a8cSGavin Shan if (phb->type == PNV_PHB_IODA1) { 3349c35d2a8cSGavin Shan iomap_off = size; 335092b8f137SGavin Shan size += phb->ioda.total_pe_num * sizeof(phb->ioda.io_segmap[0]); 3351c35d2a8cSGavin Shan } 3352184cd4a3SBenjamin Herrenschmidt pemap_off = size; 335392b8f137SGavin Shan size += phb->ioda.total_pe_num * sizeof(struct pnv_ioda_pe); 3354e39f223fSMichael Ellerman aux = memblock_virt_alloc(size, 0); 3355184cd4a3SBenjamin Herrenschmidt phb->ioda.pe_alloc = aux; 335693289d8cSGavin Shan phb->ioda.m64_segmap = aux + m64map_off; 3357184cd4a3SBenjamin Herrenschmidt phb->ioda.m32_segmap = aux + m32map_off; 335893289d8cSGavin Shan for (segno = 0; segno < phb->ioda.total_pe_num; segno++) { 335993289d8cSGavin Shan phb->ioda.m64_segmap[segno] = IODA_INVALID_PE; 33603fa23ff8SGavin Shan phb->ioda.m32_segmap[segno] = IODA_INVALID_PE; 336193289d8cSGavin Shan } 33623fa23ff8SGavin Shan if (phb->type == PNV_PHB_IODA1) { 3363184cd4a3SBenjamin Herrenschmidt phb->ioda.io_segmap = aux + iomap_off; 33643fa23ff8SGavin Shan for (segno = 0; segno < phb->ioda.total_pe_num; segno++) 33653fa23ff8SGavin Shan phb->ioda.io_segmap[segno] = IODA_INVALID_PE; 33663fa23ff8SGavin Shan } 3367184cd4a3SBenjamin Herrenschmidt phb->ioda.pe_array = aux + pemap_off; 336892b8f137SGavin Shan set_bit(phb->ioda.reserved_pe_idx, phb->ioda.pe_alloc); 3369184cd4a3SBenjamin Herrenschmidt 33707ebdf956SGavin Shan INIT_LIST_HEAD(&phb->ioda.pe_dma_list); 3371184cd4a3SBenjamin Herrenschmidt INIT_LIST_HEAD(&phb->ioda.pe_list); 3372781a868fSWei Yang mutex_init(&phb->ioda.pe_list_mutex); 3373184cd4a3SBenjamin Herrenschmidt 3374184cd4a3SBenjamin Herrenschmidt /* Calculate how many 32-bit TCE segments we have */ 3375184cd4a3SBenjamin Herrenschmidt phb->ioda.tce32_count = phb->ioda.m32_pci_base >> 28; 3376184cd4a3SBenjamin Herrenschmidt 3377aa0c033fSGavin Shan #if 0 /* We should really do that ... */ 3378184cd4a3SBenjamin Herrenschmidt rc = opal_pci_set_phb_mem_window(opal->phb_id, 3379184cd4a3SBenjamin Herrenschmidt window_type, 3380184cd4a3SBenjamin Herrenschmidt window_num, 3381184cd4a3SBenjamin Herrenschmidt starting_real_address, 3382184cd4a3SBenjamin Herrenschmidt starting_pci_address, 3383184cd4a3SBenjamin Herrenschmidt segment_size); 3384184cd4a3SBenjamin Herrenschmidt #endif 3385184cd4a3SBenjamin Herrenschmidt 3386262af557SGuo Chao pr_info(" %03d (%03d) PE's M32: 0x%x [segment=0x%x]\n", 338792b8f137SGavin Shan phb->ioda.total_pe_num, phb->ioda.reserved_pe_idx, 3388262af557SGuo Chao phb->ioda.m32_size, phb->ioda.m32_segsize); 3389262af557SGuo Chao if (phb->ioda.m64_size) 3390262af557SGuo Chao pr_info(" M64: 0x%lx [segment=0x%lx]\n", 3391262af557SGuo Chao phb->ioda.m64_size, phb->ioda.m64_segsize); 3392262af557SGuo Chao if (phb->ioda.io_size) 3393262af557SGuo Chao pr_info(" IO: 0x%x [segment=0x%x]\n", 3394184cd4a3SBenjamin Herrenschmidt phb->ioda.io_size, phb->ioda.io_segsize); 3395184cd4a3SBenjamin Herrenschmidt 3396262af557SGuo Chao 3397184cd4a3SBenjamin Herrenschmidt phb->hose->ops = &pnv_pci_ops; 339849dec922SGavin Shan phb->get_pe_state = pnv_ioda_get_pe_state; 339949dec922SGavin Shan phb->freeze_pe = pnv_ioda_freeze_pe; 340049dec922SGavin Shan phb->unfreeze_pe = pnv_ioda_unfreeze_pe; 3401184cd4a3SBenjamin Herrenschmidt 3402184cd4a3SBenjamin Herrenschmidt /* Setup TCEs */ 3403184cd4a3SBenjamin Herrenschmidt phb->dma_dev_setup = pnv_pci_ioda_dma_dev_setup; 3404184cd4a3SBenjamin Herrenschmidt 3405184cd4a3SBenjamin Herrenschmidt /* Setup MSI support */ 3406184cd4a3SBenjamin Herrenschmidt pnv_pci_init_ioda_msis(phb); 3407184cd4a3SBenjamin Herrenschmidt 3408c40a4210SGavin Shan /* 3409c40a4210SGavin Shan * We pass the PCI probe flag PCI_REASSIGN_ALL_RSRC here 3410c40a4210SGavin Shan * to let the PCI core do resource assignment. It's supposed 3411c40a4210SGavin Shan * that the PCI core will do correct I/O and MMIO alignment 3412c40a4210SGavin Shan * for the P2P bridge bars so that each PCI bus (excluding 3413c40a4210SGavin Shan * the child P2P bridges) can form individual PE. 3414184cd4a3SBenjamin Herrenschmidt */ 3415fb446ad0SGavin Shan ppc_md.pcibios_fixup = pnv_pci_ioda_fixup; 34165d2aa710SAlistair Popple 34175d2aa710SAlistair Popple if (phb->type == PNV_PHB_NPU) 34185d2aa710SAlistair Popple hose->controller_ops = pnv_npu_ioda_controller_ops; 34195d2aa710SAlistair Popple else 342092ae0353SDaniel Axtens hose->controller_ops = pnv_pci_ioda_controller_ops; 3421ad30cb99SMichael Ellerman 34226e628c7dSWei Yang #ifdef CONFIG_PCI_IOV 34236e628c7dSWei Yang ppc_md.pcibios_fixup_sriov = pnv_pci_ioda_fixup_iov_resources; 34245350ab3fSWei Yang ppc_md.pcibios_iov_resource_alignment = pnv_pci_iov_resource_alignment; 3425ad30cb99SMichael Ellerman #endif 3426ad30cb99SMichael Ellerman 3427c40a4210SGavin Shan pci_add_flags(PCI_REASSIGN_ALL_RSRC); 3428184cd4a3SBenjamin Herrenschmidt 3429184cd4a3SBenjamin Herrenschmidt /* Reset IODA tables to a clean state */ 3430d1a85eeeSGavin Shan rc = opal_pci_reset(phb_id, OPAL_RESET_PCI_IODA_TABLE, OPAL_ASSERT_RESET); 3431184cd4a3SBenjamin Herrenschmidt if (rc) 3432f11fe552SBenjamin Herrenschmidt pr_warning(" OPAL Error %ld performing IODA table reset !\n", rc); 3433361f2a2aSGavin Shan 3434361f2a2aSGavin Shan /* If we're running in kdump kerenl, the previous kerenl never 3435361f2a2aSGavin Shan * shutdown PCI devices correctly. We already got IODA table 3436361f2a2aSGavin Shan * cleaned out. So we have to issue PHB reset to stop all PCI 3437361f2a2aSGavin Shan * transactions from previous kerenl. 3438361f2a2aSGavin Shan */ 3439361f2a2aSGavin Shan if (is_kdump_kernel()) { 3440361f2a2aSGavin Shan pr_info(" Issue PHB reset ...\n"); 3441cadf364dSGavin Shan pnv_eeh_phb_reset(hose, EEH_RESET_FUNDAMENTAL); 3442cadf364dSGavin Shan pnv_eeh_phb_reset(hose, EEH_RESET_DEACTIVATE); 3443361f2a2aSGavin Shan } 3444262af557SGuo Chao 34459e9e8935SGavin Shan /* Remove M64 resource if we can't configure it successfully */ 34469e9e8935SGavin Shan if (!phb->init_m64 || phb->init_m64(phb)) 3447262af557SGuo Chao hose->mem_resources[1].flags = 0; 3448184cd4a3SBenjamin Herrenschmidt } 3449184cd4a3SBenjamin Herrenschmidt 345067975005SBjorn Helgaas void __init pnv_pci_init_ioda2_phb(struct device_node *np) 3451aa0c033fSGavin Shan { 3452e9cc17d4SGavin Shan pnv_pci_init_ioda_phb(np, 0, PNV_PHB_IODA2); 3453aa0c033fSGavin Shan } 3454aa0c033fSGavin Shan 34555d2aa710SAlistair Popple void __init pnv_pci_init_npu_phb(struct device_node *np) 34565d2aa710SAlistair Popple { 34575d2aa710SAlistair Popple pnv_pci_init_ioda_phb(np, 0, PNV_PHB_NPU); 34585d2aa710SAlistair Popple } 34595d2aa710SAlistair Popple 3460184cd4a3SBenjamin Herrenschmidt void __init pnv_pci_init_ioda_hub(struct device_node *np) 3461184cd4a3SBenjamin Herrenschmidt { 3462184cd4a3SBenjamin Herrenschmidt struct device_node *phbn; 3463c681b93cSAlistair Popple const __be64 *prop64; 3464184cd4a3SBenjamin Herrenschmidt u64 hub_id; 3465184cd4a3SBenjamin Herrenschmidt 3466184cd4a3SBenjamin Herrenschmidt pr_info("Probing IODA IO-Hub %s\n", np->full_name); 3467184cd4a3SBenjamin Herrenschmidt 3468184cd4a3SBenjamin Herrenschmidt prop64 = of_get_property(np, "ibm,opal-hubid", NULL); 3469184cd4a3SBenjamin Herrenschmidt if (!prop64) { 3470184cd4a3SBenjamin Herrenschmidt pr_err(" Missing \"ibm,opal-hubid\" property !\n"); 3471184cd4a3SBenjamin Herrenschmidt return; 3472184cd4a3SBenjamin Herrenschmidt } 3473184cd4a3SBenjamin Herrenschmidt hub_id = be64_to_cpup(prop64); 3474184cd4a3SBenjamin Herrenschmidt pr_devel(" HUB-ID : 0x%016llx\n", hub_id); 3475184cd4a3SBenjamin Herrenschmidt 3476184cd4a3SBenjamin Herrenschmidt /* Count child PHBs */ 3477184cd4a3SBenjamin Herrenschmidt for_each_child_of_node(np, phbn) { 3478184cd4a3SBenjamin Herrenschmidt /* Look for IODA1 PHBs */ 3479184cd4a3SBenjamin Herrenschmidt if (of_device_is_compatible(phbn, "ibm,ioda-phb")) 3480e9cc17d4SGavin Shan pnv_pci_init_ioda_phb(phbn, hub_id, PNV_PHB_IODA1); 3481184cd4a3SBenjamin Herrenschmidt } 3482184cd4a3SBenjamin Herrenschmidt } 3483