1184cd4a3SBenjamin Herrenschmidt /* 2184cd4a3SBenjamin Herrenschmidt * Support PCI/PCIe on PowerNV platforms 3184cd4a3SBenjamin Herrenschmidt * 4184cd4a3SBenjamin Herrenschmidt * Copyright 2011 Benjamin Herrenschmidt, IBM Corp. 5184cd4a3SBenjamin Herrenschmidt * 6184cd4a3SBenjamin Herrenschmidt * This program is free software; you can redistribute it and/or 7184cd4a3SBenjamin Herrenschmidt * modify it under the terms of the GNU General Public License 8184cd4a3SBenjamin Herrenschmidt * as published by the Free Software Foundation; either version 9184cd4a3SBenjamin Herrenschmidt * 2 of the License, or (at your option) any later version. 10184cd4a3SBenjamin Herrenschmidt */ 11184cd4a3SBenjamin Herrenschmidt 12cee72d5bSBenjamin Herrenschmidt #undef DEBUG 13184cd4a3SBenjamin Herrenschmidt 14184cd4a3SBenjamin Herrenschmidt #include <linux/kernel.h> 15184cd4a3SBenjamin Herrenschmidt #include <linux/pci.h> 16361f2a2aSGavin Shan #include <linux/crash_dump.h> 17184cd4a3SBenjamin Herrenschmidt #include <linux/delay.h> 18184cd4a3SBenjamin Herrenschmidt #include <linux/string.h> 19184cd4a3SBenjamin Herrenschmidt #include <linux/init.h> 20184cd4a3SBenjamin Herrenschmidt #include <linux/bootmem.h> 21184cd4a3SBenjamin Herrenschmidt #include <linux/irq.h> 22184cd4a3SBenjamin Herrenschmidt #include <linux/io.h> 23184cd4a3SBenjamin Herrenschmidt #include <linux/msi.h> 24cd15b048SBenjamin Herrenschmidt #include <linux/memblock.h> 25ac9a5889SAlexey Kardashevskiy #include <linux/iommu.h> 26e57080f1SAlexey Kardashevskiy #include <linux/rculist.h> 274793d65dSAlexey Kardashevskiy #include <linux/sizes.h> 28184cd4a3SBenjamin Herrenschmidt 29184cd4a3SBenjamin Herrenschmidt #include <asm/sections.h> 30184cd4a3SBenjamin Herrenschmidt #include <asm/io.h> 31184cd4a3SBenjamin Herrenschmidt #include <asm/prom.h> 32184cd4a3SBenjamin Herrenschmidt #include <asm/pci-bridge.h> 33184cd4a3SBenjamin Herrenschmidt #include <asm/machdep.h> 34fb1b55d6SGavin Shan #include <asm/msi_bitmap.h> 35184cd4a3SBenjamin Herrenschmidt #include <asm/ppc-pci.h> 36184cd4a3SBenjamin Herrenschmidt #include <asm/opal.h> 37184cd4a3SBenjamin Herrenschmidt #include <asm/iommu.h> 38184cd4a3SBenjamin Herrenschmidt #include <asm/tce.h> 39137436c9SGavin Shan #include <asm/xics.h> 407644d581SMichael Ellerman #include <asm/debugfs.h> 41262af557SGuo Chao #include <asm/firmware.h> 4280c49c7eSIan Munsie #include <asm/pnv-pci.h> 43aca6913fSAlexey Kardashevskiy #include <asm/mmzone.h> 4480c49c7eSIan Munsie 45ec249dd8SMichael Neuling #include <misc/cxl-base.h> 46184cd4a3SBenjamin Herrenschmidt 47184cd4a3SBenjamin Herrenschmidt #include "powernv.h" 48184cd4a3SBenjamin Herrenschmidt #include "pci.h" 49184cd4a3SBenjamin Herrenschmidt 5099451551SGavin Shan #define PNV_IODA1_M64_NUM 16 /* Number of M64 BARs */ 5199451551SGavin Shan #define PNV_IODA1_M64_SEGS 8 /* Segments per M64 BAR */ 52acce971cSGavin Shan #define PNV_IODA1_DMA32_SEGSIZE 0x10000000 53781a868fSWei Yang 54bbb845c4SAlexey Kardashevskiy #define POWERNV_IOMMU_DEFAULT_LEVELS 1 55bbb845c4SAlexey Kardashevskiy #define POWERNV_IOMMU_MAX_LEVELS 5 56bbb845c4SAlexey Kardashevskiy 577f2c39e9SFrederic Barrat static const char * const pnv_phb_names[] = { "IODA1", "IODA2", "NPU_NVLINK", 587f2c39e9SFrederic Barrat "NPU_OCAPI" }; 59aca6913fSAlexey Kardashevskiy static void pnv_pci_ioda2_table_free_pages(struct iommu_table *tbl); 60aca6913fSAlexey Kardashevskiy 617d623e42SAlexey Kardashevskiy void pe_level_printk(const struct pnv_ioda_pe *pe, const char *level, 626d31c2faSJoe Perches const char *fmt, ...) 636d31c2faSJoe Perches { 646d31c2faSJoe Perches struct va_format vaf; 656d31c2faSJoe Perches va_list args; 666d31c2faSJoe Perches char pfix[32]; 67184cd4a3SBenjamin Herrenschmidt 686d31c2faSJoe Perches va_start(args, fmt); 696d31c2faSJoe Perches 706d31c2faSJoe Perches vaf.fmt = fmt; 716d31c2faSJoe Perches vaf.va = &args; 726d31c2faSJoe Perches 73781a868fSWei Yang if (pe->flags & PNV_IODA_PE_DEV) 746d31c2faSJoe Perches strlcpy(pfix, dev_name(&pe->pdev->dev), sizeof(pfix)); 75781a868fSWei Yang else if (pe->flags & (PNV_IODA_PE_BUS | PNV_IODA_PE_BUS_ALL)) 766d31c2faSJoe Perches sprintf(pfix, "%04x:%02x ", 776d31c2faSJoe Perches pci_domain_nr(pe->pbus), pe->pbus->number); 78781a868fSWei Yang #ifdef CONFIG_PCI_IOV 79781a868fSWei Yang else if (pe->flags & PNV_IODA_PE_VF) 80781a868fSWei Yang sprintf(pfix, "%04x:%02x:%2x.%d", 81781a868fSWei Yang pci_domain_nr(pe->parent_dev->bus), 82781a868fSWei Yang (pe->rid & 0xff00) >> 8, 83781a868fSWei Yang PCI_SLOT(pe->rid), PCI_FUNC(pe->rid)); 84781a868fSWei Yang #endif /* CONFIG_PCI_IOV*/ 856d31c2faSJoe Perches 861f52f176SRussell Currey printk("%spci %s: [PE# %.2x] %pV", 876d31c2faSJoe Perches level, pfix, pe->pe_number, &vaf); 886d31c2faSJoe Perches 896d31c2faSJoe Perches va_end(args); 906d31c2faSJoe Perches } 916d31c2faSJoe Perches 924e287840SThadeu Lima de Souza Cascardo static bool pnv_iommu_bypass_disabled __read_mostly; 9345baee14SGuilherme G. Piccoli static bool pci_reset_phbs __read_mostly; 944e287840SThadeu Lima de Souza Cascardo 954e287840SThadeu Lima de Souza Cascardo static int __init iommu_setup(char *str) 964e287840SThadeu Lima de Souza Cascardo { 974e287840SThadeu Lima de Souza Cascardo if (!str) 984e287840SThadeu Lima de Souza Cascardo return -EINVAL; 994e287840SThadeu Lima de Souza Cascardo 1004e287840SThadeu Lima de Souza Cascardo while (*str) { 1014e287840SThadeu Lima de Souza Cascardo if (!strncmp(str, "nobypass", 8)) { 1024e287840SThadeu Lima de Souza Cascardo pnv_iommu_bypass_disabled = true; 1034e287840SThadeu Lima de Souza Cascardo pr_info("PowerNV: IOMMU bypass window disabled.\n"); 1044e287840SThadeu Lima de Souza Cascardo break; 1054e287840SThadeu Lima de Souza Cascardo } 1064e287840SThadeu Lima de Souza Cascardo str += strcspn(str, ","); 1074e287840SThadeu Lima de Souza Cascardo if (*str == ',') 1084e287840SThadeu Lima de Souza Cascardo str++; 1094e287840SThadeu Lima de Souza Cascardo } 1104e287840SThadeu Lima de Souza Cascardo 1114e287840SThadeu Lima de Souza Cascardo return 0; 1124e287840SThadeu Lima de Souza Cascardo } 1134e287840SThadeu Lima de Souza Cascardo early_param("iommu", iommu_setup); 1144e287840SThadeu Lima de Souza Cascardo 11545baee14SGuilherme G. Piccoli static int __init pci_reset_phbs_setup(char *str) 11645baee14SGuilherme G. Piccoli { 11745baee14SGuilherme G. Piccoli pci_reset_phbs = true; 11845baee14SGuilherme G. Piccoli return 0; 11945baee14SGuilherme G. Piccoli } 12045baee14SGuilherme G. Piccoli 12145baee14SGuilherme G. Piccoli early_param("ppc_pci_reset_phbs", pci_reset_phbs_setup); 12245baee14SGuilherme G. Piccoli 1235958d19aSBenjamin Herrenschmidt static inline bool pnv_pci_is_m64(struct pnv_phb *phb, struct resource *r) 124262af557SGuo Chao { 1255958d19aSBenjamin Herrenschmidt /* 1265958d19aSBenjamin Herrenschmidt * WARNING: We cannot rely on the resource flags. The Linux PCI 1275958d19aSBenjamin Herrenschmidt * allocation code sometimes decides to put a 64-bit prefetchable 1285958d19aSBenjamin Herrenschmidt * BAR in the 32-bit window, so we have to compare the addresses. 1295958d19aSBenjamin Herrenschmidt * 1305958d19aSBenjamin Herrenschmidt * For simplicity we only test resource start. 1315958d19aSBenjamin Herrenschmidt */ 1325958d19aSBenjamin Herrenschmidt return (r->start >= phb->ioda.m64_base && 1335958d19aSBenjamin Herrenschmidt r->start < (phb->ioda.m64_base + phb->ioda.m64_size)); 134262af557SGuo Chao } 135262af557SGuo Chao 136b79331a5SRussell Currey static inline bool pnv_pci_is_m64_flags(unsigned long resource_flags) 137b79331a5SRussell Currey { 138b79331a5SRussell Currey unsigned long flags = (IORESOURCE_MEM_64 | IORESOURCE_PREFETCH); 139b79331a5SRussell Currey 140b79331a5SRussell Currey return (resource_flags & flags) == flags; 141b79331a5SRussell Currey } 142b79331a5SRussell Currey 1431e916772SGavin Shan static struct pnv_ioda_pe *pnv_ioda_init_pe(struct pnv_phb *phb, int pe_no) 1441e916772SGavin Shan { 145313483ddSGavin Shan s64 rc; 146313483ddSGavin Shan 1471e916772SGavin Shan phb->ioda.pe_array[pe_no].phb = phb; 1481e916772SGavin Shan phb->ioda.pe_array[pe_no].pe_number = pe_no; 1491e916772SGavin Shan 150313483ddSGavin Shan /* 151313483ddSGavin Shan * Clear the PE frozen state as it might be put into frozen state 152313483ddSGavin Shan * in the last PCI remove path. It's not harmful to do so when the 153313483ddSGavin Shan * PE is already in unfrozen state. 154313483ddSGavin Shan */ 155313483ddSGavin Shan rc = opal_pci_eeh_freeze_clear(phb->opal_id, pe_no, 156313483ddSGavin Shan OPAL_EEH_ACTION_CLEAR_FREEZE_ALL); 157d4791db5SRussell Currey if (rc != OPAL_SUCCESS && rc != OPAL_UNSUPPORTED) 1581f52f176SRussell Currey pr_warn("%s: Error %lld unfreezing PHB#%x-PE#%x\n", 159313483ddSGavin Shan __func__, rc, phb->hose->global_number, pe_no); 160313483ddSGavin Shan 1611e916772SGavin Shan return &phb->ioda.pe_array[pe_no]; 1621e916772SGavin Shan } 1631e916772SGavin Shan 1644b82ab18SGavin Shan static void pnv_ioda_reserve_pe(struct pnv_phb *phb, int pe_no) 1654b82ab18SGavin Shan { 16692b8f137SGavin Shan if (!(pe_no >= 0 && pe_no < phb->ioda.total_pe_num)) { 1671f52f176SRussell Currey pr_warn("%s: Invalid PE %x on PHB#%x\n", 1684b82ab18SGavin Shan __func__, pe_no, phb->hose->global_number); 1694b82ab18SGavin Shan return; 1704b82ab18SGavin Shan } 1714b82ab18SGavin Shan 172e9dc4d7fSGavin Shan if (test_and_set_bit(pe_no, phb->ioda.pe_alloc)) 1731f52f176SRussell Currey pr_debug("%s: PE %x was reserved on PHB#%x\n", 1744b82ab18SGavin Shan __func__, pe_no, phb->hose->global_number); 1754b82ab18SGavin Shan 1761e916772SGavin Shan pnv_ioda_init_pe(phb, pe_no); 1774b82ab18SGavin Shan } 1784b82ab18SGavin Shan 1791e916772SGavin Shan static struct pnv_ioda_pe *pnv_ioda_alloc_pe(struct pnv_phb *phb) 180184cd4a3SBenjamin Herrenschmidt { 18160964816SAndrzej Hajda long pe; 182184cd4a3SBenjamin Herrenschmidt 1839fcd6f4aSGavin Shan for (pe = phb->ioda.total_pe_num - 1; pe >= 0; pe--) { 1849fcd6f4aSGavin Shan if (!test_and_set_bit(pe, phb->ioda.pe_alloc)) 1851e916772SGavin Shan return pnv_ioda_init_pe(phb, pe); 186184cd4a3SBenjamin Herrenschmidt } 187184cd4a3SBenjamin Herrenschmidt 1889fcd6f4aSGavin Shan return NULL; 1899fcd6f4aSGavin Shan } 1909fcd6f4aSGavin Shan 1911e916772SGavin Shan static void pnv_ioda_free_pe(struct pnv_ioda_pe *pe) 192184cd4a3SBenjamin Herrenschmidt { 1931e916772SGavin Shan struct pnv_phb *phb = pe->phb; 194caa58f80SGavin Shan unsigned int pe_num = pe->pe_number; 195184cd4a3SBenjamin Herrenschmidt 1961e916772SGavin Shan WARN_ON(pe->pdev); 1971e916772SGavin Shan 1981e916772SGavin Shan memset(pe, 0, sizeof(struct pnv_ioda_pe)); 199caa58f80SGavin Shan clear_bit(pe_num, phb->ioda.pe_alloc); 200184cd4a3SBenjamin Herrenschmidt } 201184cd4a3SBenjamin Herrenschmidt 202262af557SGuo Chao /* The default M64 BAR is shared by all PEs */ 203262af557SGuo Chao static int pnv_ioda2_init_m64(struct pnv_phb *phb) 204262af557SGuo Chao { 205262af557SGuo Chao const char *desc; 206262af557SGuo Chao struct resource *r; 207262af557SGuo Chao s64 rc; 208262af557SGuo Chao 209262af557SGuo Chao /* Configure the default M64 BAR */ 210262af557SGuo Chao rc = opal_pci_set_phb_mem_window(phb->opal_id, 211262af557SGuo Chao OPAL_M64_WINDOW_TYPE, 212262af557SGuo Chao phb->ioda.m64_bar_idx, 213262af557SGuo Chao phb->ioda.m64_base, 214262af557SGuo Chao 0, /* unused */ 215262af557SGuo Chao phb->ioda.m64_size); 216262af557SGuo Chao if (rc != OPAL_SUCCESS) { 217262af557SGuo Chao desc = "configuring"; 218262af557SGuo Chao goto fail; 219262af557SGuo Chao } 220262af557SGuo Chao 221262af557SGuo Chao /* Enable the default M64 BAR */ 222262af557SGuo Chao rc = opal_pci_phb_mmio_enable(phb->opal_id, 223262af557SGuo Chao OPAL_M64_WINDOW_TYPE, 224262af557SGuo Chao phb->ioda.m64_bar_idx, 225262af557SGuo Chao OPAL_ENABLE_M64_SPLIT); 226262af557SGuo Chao if (rc != OPAL_SUCCESS) { 227262af557SGuo Chao desc = "enabling"; 228262af557SGuo Chao goto fail; 229262af557SGuo Chao } 230262af557SGuo Chao 231262af557SGuo Chao /* 23263803c39SGavin Shan * Exclude the segments for reserved and root bus PE, which 23363803c39SGavin Shan * are first or last two PEs. 234262af557SGuo Chao */ 235262af557SGuo Chao r = &phb->hose->mem_resources[1]; 23692b8f137SGavin Shan if (phb->ioda.reserved_pe_idx == 0) 23763803c39SGavin Shan r->start += (2 * phb->ioda.m64_segsize); 23892b8f137SGavin Shan else if (phb->ioda.reserved_pe_idx == (phb->ioda.total_pe_num - 1)) 23963803c39SGavin Shan r->end -= (2 * phb->ioda.m64_segsize); 240262af557SGuo Chao else 2411f52f176SRussell Currey pr_warn(" Cannot strip M64 segment for reserved PE#%x\n", 24292b8f137SGavin Shan phb->ioda.reserved_pe_idx); 243262af557SGuo Chao 244262af557SGuo Chao return 0; 245262af557SGuo Chao 246262af557SGuo Chao fail: 247262af557SGuo Chao pr_warn(" Failure %lld %s M64 BAR#%d\n", 248262af557SGuo Chao rc, desc, phb->ioda.m64_bar_idx); 249262af557SGuo Chao opal_pci_phb_mmio_enable(phb->opal_id, 250262af557SGuo Chao OPAL_M64_WINDOW_TYPE, 251262af557SGuo Chao phb->ioda.m64_bar_idx, 252262af557SGuo Chao OPAL_DISABLE_M64); 253262af557SGuo Chao return -EIO; 254262af557SGuo Chao } 255262af557SGuo Chao 256c430670aSGavin Shan static void pnv_ioda_reserve_dev_m64_pe(struct pci_dev *pdev, 25796a2f92bSGavin Shan unsigned long *pe_bitmap) 258262af557SGuo Chao { 25996a2f92bSGavin Shan struct pci_controller *hose = pci_bus_to_host(pdev->bus); 26096a2f92bSGavin Shan struct pnv_phb *phb = hose->private_data; 261262af557SGuo Chao struct resource *r; 26296a2f92bSGavin Shan resource_size_t base, sgsz, start, end; 26396a2f92bSGavin Shan int segno, i; 264262af557SGuo Chao 26596a2f92bSGavin Shan base = phb->ioda.m64_base; 26696a2f92bSGavin Shan sgsz = phb->ioda.m64_segsize; 26796a2f92bSGavin Shan for (i = 0; i <= PCI_ROM_RESOURCE; i++) { 26896a2f92bSGavin Shan r = &pdev->resource[i]; 2695958d19aSBenjamin Herrenschmidt if (!r->parent || !pnv_pci_is_m64(phb, r)) 270262af557SGuo Chao continue; 271262af557SGuo Chao 27296a2f92bSGavin Shan start = _ALIGN_DOWN(r->start - base, sgsz); 27396a2f92bSGavin Shan end = _ALIGN_UP(r->end - base, sgsz); 27496a2f92bSGavin Shan for (segno = start / sgsz; segno < end / sgsz; segno++) { 27596a2f92bSGavin Shan if (pe_bitmap) 27696a2f92bSGavin Shan set_bit(segno, pe_bitmap); 27796a2f92bSGavin Shan else 27896a2f92bSGavin Shan pnv_ioda_reserve_pe(phb, segno); 279262af557SGuo Chao } 280262af557SGuo Chao } 281262af557SGuo Chao } 282262af557SGuo Chao 28399451551SGavin Shan static int pnv_ioda1_init_m64(struct pnv_phb *phb) 28499451551SGavin Shan { 28599451551SGavin Shan struct resource *r; 28699451551SGavin Shan int index; 28799451551SGavin Shan 28899451551SGavin Shan /* 28999451551SGavin Shan * There are 16 M64 BARs, each of which has 8 segments. So 29099451551SGavin Shan * there are as many M64 segments as the maximum number of 29199451551SGavin Shan * PEs, which is 128. 29299451551SGavin Shan */ 29399451551SGavin Shan for (index = 0; index < PNV_IODA1_M64_NUM; index++) { 29499451551SGavin Shan unsigned long base, segsz = phb->ioda.m64_segsize; 29599451551SGavin Shan int64_t rc; 29699451551SGavin Shan 29799451551SGavin Shan base = phb->ioda.m64_base + 29899451551SGavin Shan index * PNV_IODA1_M64_SEGS * segsz; 29999451551SGavin Shan rc = opal_pci_set_phb_mem_window(phb->opal_id, 30099451551SGavin Shan OPAL_M64_WINDOW_TYPE, index, base, 0, 30199451551SGavin Shan PNV_IODA1_M64_SEGS * segsz); 30299451551SGavin Shan if (rc != OPAL_SUCCESS) { 3031f52f176SRussell Currey pr_warn(" Error %lld setting M64 PHB#%x-BAR#%d\n", 30499451551SGavin Shan rc, phb->hose->global_number, index); 30599451551SGavin Shan goto fail; 30699451551SGavin Shan } 30799451551SGavin Shan 30899451551SGavin Shan rc = opal_pci_phb_mmio_enable(phb->opal_id, 30999451551SGavin Shan OPAL_M64_WINDOW_TYPE, index, 31099451551SGavin Shan OPAL_ENABLE_M64_SPLIT); 31199451551SGavin Shan if (rc != OPAL_SUCCESS) { 3121f52f176SRussell Currey pr_warn(" Error %lld enabling M64 PHB#%x-BAR#%d\n", 31399451551SGavin Shan rc, phb->hose->global_number, index); 31499451551SGavin Shan goto fail; 31599451551SGavin Shan } 31699451551SGavin Shan } 31799451551SGavin Shan 31899451551SGavin Shan /* 31963803c39SGavin Shan * Exclude the segments for reserved and root bus PE, which 32063803c39SGavin Shan * are first or last two PEs. 32199451551SGavin Shan */ 32299451551SGavin Shan r = &phb->hose->mem_resources[1]; 32399451551SGavin Shan if (phb->ioda.reserved_pe_idx == 0) 32463803c39SGavin Shan r->start += (2 * phb->ioda.m64_segsize); 32599451551SGavin Shan else if (phb->ioda.reserved_pe_idx == (phb->ioda.total_pe_num - 1)) 32663803c39SGavin Shan r->end -= (2 * phb->ioda.m64_segsize); 32799451551SGavin Shan else 3281f52f176SRussell Currey WARN(1, "Wrong reserved PE#%x on PHB#%x\n", 32999451551SGavin Shan phb->ioda.reserved_pe_idx, phb->hose->global_number); 33099451551SGavin Shan 33199451551SGavin Shan return 0; 33299451551SGavin Shan 33399451551SGavin Shan fail: 33499451551SGavin Shan for ( ; index >= 0; index--) 33599451551SGavin Shan opal_pci_phb_mmio_enable(phb->opal_id, 33699451551SGavin Shan OPAL_M64_WINDOW_TYPE, index, OPAL_DISABLE_M64); 33799451551SGavin Shan 33899451551SGavin Shan return -EIO; 33999451551SGavin Shan } 34099451551SGavin Shan 341c430670aSGavin Shan static void pnv_ioda_reserve_m64_pe(struct pci_bus *bus, 34296a2f92bSGavin Shan unsigned long *pe_bitmap, 34396a2f92bSGavin Shan bool all) 344262af557SGuo Chao { 345262af557SGuo Chao struct pci_dev *pdev; 34696a2f92bSGavin Shan 34796a2f92bSGavin Shan list_for_each_entry(pdev, &bus->devices, bus_list) { 348c430670aSGavin Shan pnv_ioda_reserve_dev_m64_pe(pdev, pe_bitmap); 34996a2f92bSGavin Shan 35096a2f92bSGavin Shan if (all && pdev->subordinate) 351c430670aSGavin Shan pnv_ioda_reserve_m64_pe(pdev->subordinate, 35296a2f92bSGavin Shan pe_bitmap, all); 35396a2f92bSGavin Shan } 35496a2f92bSGavin Shan } 35596a2f92bSGavin Shan 3561e916772SGavin Shan static struct pnv_ioda_pe *pnv_ioda_pick_m64_pe(struct pci_bus *bus, bool all) 357262af557SGuo Chao { 35826ba248dSGavin Shan struct pci_controller *hose = pci_bus_to_host(bus); 35926ba248dSGavin Shan struct pnv_phb *phb = hose->private_data; 360262af557SGuo Chao struct pnv_ioda_pe *master_pe, *pe; 361262af557SGuo Chao unsigned long size, *pe_alloc; 36226ba248dSGavin Shan int i; 363262af557SGuo Chao 364262af557SGuo Chao /* Root bus shouldn't use M64 */ 365262af557SGuo Chao if (pci_is_root_bus(bus)) 3661e916772SGavin Shan return NULL; 367262af557SGuo Chao 368262af557SGuo Chao /* Allocate bitmap */ 36992b8f137SGavin Shan size = _ALIGN_UP(phb->ioda.total_pe_num / 8, sizeof(unsigned long)); 370262af557SGuo Chao pe_alloc = kzalloc(size, GFP_KERNEL); 371262af557SGuo Chao if (!pe_alloc) { 372262af557SGuo Chao pr_warn("%s: Out of memory !\n", 373262af557SGuo Chao __func__); 3741e916772SGavin Shan return NULL; 375262af557SGuo Chao } 376262af557SGuo Chao 37726ba248dSGavin Shan /* Figure out reserved PE numbers by the PE */ 378c430670aSGavin Shan pnv_ioda_reserve_m64_pe(bus, pe_alloc, all); 379262af557SGuo Chao 380262af557SGuo Chao /* 381262af557SGuo Chao * the current bus might not own M64 window and that's all 382262af557SGuo Chao * contributed by its child buses. For the case, we needn't 383262af557SGuo Chao * pick M64 dependent PE#. 384262af557SGuo Chao */ 38592b8f137SGavin Shan if (bitmap_empty(pe_alloc, phb->ioda.total_pe_num)) { 386262af557SGuo Chao kfree(pe_alloc); 3871e916772SGavin Shan return NULL; 388262af557SGuo Chao } 389262af557SGuo Chao 390262af557SGuo Chao /* 391262af557SGuo Chao * Figure out the master PE and put all slave PEs to master 392262af557SGuo Chao * PE's list to form compound PE. 393262af557SGuo Chao */ 394262af557SGuo Chao master_pe = NULL; 395262af557SGuo Chao i = -1; 39692b8f137SGavin Shan while ((i = find_next_bit(pe_alloc, phb->ioda.total_pe_num, i + 1)) < 39792b8f137SGavin Shan phb->ioda.total_pe_num) { 398262af557SGuo Chao pe = &phb->ioda.pe_array[i]; 399262af557SGuo Chao 40093289d8cSGavin Shan phb->ioda.m64_segmap[pe->pe_number] = pe->pe_number; 401262af557SGuo Chao if (!master_pe) { 402262af557SGuo Chao pe->flags |= PNV_IODA_PE_MASTER; 403262af557SGuo Chao INIT_LIST_HEAD(&pe->slaves); 404262af557SGuo Chao master_pe = pe; 405262af557SGuo Chao } else { 406262af557SGuo Chao pe->flags |= PNV_IODA_PE_SLAVE; 407262af557SGuo Chao pe->master = master_pe; 408262af557SGuo Chao list_add_tail(&pe->list, &master_pe->slaves); 409262af557SGuo Chao } 41099451551SGavin Shan 41199451551SGavin Shan /* 41299451551SGavin Shan * P7IOC supports M64DT, which helps mapping M64 segment 41399451551SGavin Shan * to one particular PE#. However, PHB3 has fixed mapping 41499451551SGavin Shan * between M64 segment and PE#. In order to have same logic 41599451551SGavin Shan * for P7IOC and PHB3, we enforce fixed mapping between M64 41699451551SGavin Shan * segment and PE# on P7IOC. 41799451551SGavin Shan */ 41899451551SGavin Shan if (phb->type == PNV_PHB_IODA1) { 41999451551SGavin Shan int64_t rc; 42099451551SGavin Shan 42199451551SGavin Shan rc = opal_pci_map_pe_mmio_window(phb->opal_id, 42299451551SGavin Shan pe->pe_number, OPAL_M64_WINDOW_TYPE, 42399451551SGavin Shan pe->pe_number / PNV_IODA1_M64_SEGS, 42499451551SGavin Shan pe->pe_number % PNV_IODA1_M64_SEGS); 42599451551SGavin Shan if (rc != OPAL_SUCCESS) 4261f52f176SRussell Currey pr_warn("%s: Error %lld mapping M64 for PHB#%x-PE#%x\n", 42799451551SGavin Shan __func__, rc, phb->hose->global_number, 42899451551SGavin Shan pe->pe_number); 42999451551SGavin Shan } 430262af557SGuo Chao } 431262af557SGuo Chao 432262af557SGuo Chao kfree(pe_alloc); 4331e916772SGavin Shan return master_pe; 434262af557SGuo Chao } 435262af557SGuo Chao 436262af557SGuo Chao static void __init pnv_ioda_parse_m64_window(struct pnv_phb *phb) 437262af557SGuo Chao { 438262af557SGuo Chao struct pci_controller *hose = phb->hose; 439262af557SGuo Chao struct device_node *dn = hose->dn; 440262af557SGuo Chao struct resource *res; 441a1339fafSBenjamin Herrenschmidt u32 m64_range[2], i; 4420e7736c6SGavin Shan const __be32 *r; 443262af557SGuo Chao u64 pci_addr; 444262af557SGuo Chao 44599451551SGavin Shan if (phb->type != PNV_PHB_IODA1 && phb->type != PNV_PHB_IODA2) { 4461665c4a8SGavin Shan pr_info(" Not support M64 window\n"); 4471665c4a8SGavin Shan return; 4481665c4a8SGavin Shan } 4491665c4a8SGavin Shan 450e4d54f71SStewart Smith if (!firmware_has_feature(FW_FEATURE_OPAL)) { 451262af557SGuo Chao pr_info(" Firmware too old to support M64 window\n"); 452262af557SGuo Chao return; 453262af557SGuo Chao } 454262af557SGuo Chao 455262af557SGuo Chao r = of_get_property(dn, "ibm,opal-m64-window", NULL); 456262af557SGuo Chao if (!r) { 457b7c670d6SRob Herring pr_info(" No <ibm,opal-m64-window> on %pOF\n", 458b7c670d6SRob Herring dn); 459262af557SGuo Chao return; 460262af557SGuo Chao } 461262af557SGuo Chao 462a1339fafSBenjamin Herrenschmidt /* 463a1339fafSBenjamin Herrenschmidt * Find the available M64 BAR range and pickup the last one for 464a1339fafSBenjamin Herrenschmidt * covering the whole 64-bits space. We support only one range. 465a1339fafSBenjamin Herrenschmidt */ 466a1339fafSBenjamin Herrenschmidt if (of_property_read_u32_array(dn, "ibm,opal-available-m64-ranges", 467a1339fafSBenjamin Herrenschmidt m64_range, 2)) { 468a1339fafSBenjamin Herrenschmidt /* In absence of the property, assume 0..15 */ 469a1339fafSBenjamin Herrenschmidt m64_range[0] = 0; 470a1339fafSBenjamin Herrenschmidt m64_range[1] = 16; 471a1339fafSBenjamin Herrenschmidt } 472a1339fafSBenjamin Herrenschmidt /* We only support 64 bits in our allocator */ 473a1339fafSBenjamin Herrenschmidt if (m64_range[1] > 63) { 474a1339fafSBenjamin Herrenschmidt pr_warn("%s: Limiting M64 range to 63 (from %d) on PHB#%x\n", 475a1339fafSBenjamin Herrenschmidt __func__, m64_range[1], phb->hose->global_number); 476a1339fafSBenjamin Herrenschmidt m64_range[1] = 63; 477a1339fafSBenjamin Herrenschmidt } 478a1339fafSBenjamin Herrenschmidt /* Empty range, no m64 */ 479a1339fafSBenjamin Herrenschmidt if (m64_range[1] <= m64_range[0]) { 480a1339fafSBenjamin Herrenschmidt pr_warn("%s: M64 empty, disabling M64 usage on PHB#%x\n", 481a1339fafSBenjamin Herrenschmidt __func__, phb->hose->global_number); 482a1339fafSBenjamin Herrenschmidt return; 483a1339fafSBenjamin Herrenschmidt } 484a1339fafSBenjamin Herrenschmidt 485a1339fafSBenjamin Herrenschmidt /* Configure M64 informations */ 486262af557SGuo Chao res = &hose->mem_resources[1]; 487e80c4e7cSGavin Shan res->name = dn->full_name; 488262af557SGuo Chao res->start = of_translate_address(dn, r + 2); 489262af557SGuo Chao res->end = res->start + of_read_number(r + 4, 2) - 1; 490262af557SGuo Chao res->flags = (IORESOURCE_MEM | IORESOURCE_MEM_64 | IORESOURCE_PREFETCH); 491262af557SGuo Chao pci_addr = of_read_number(r, 2); 492262af557SGuo Chao hose->mem_offset[1] = res->start - pci_addr; 493262af557SGuo Chao 494262af557SGuo Chao phb->ioda.m64_size = resource_size(res); 49592b8f137SGavin Shan phb->ioda.m64_segsize = phb->ioda.m64_size / phb->ioda.total_pe_num; 496262af557SGuo Chao phb->ioda.m64_base = pci_addr; 497262af557SGuo Chao 498a1339fafSBenjamin Herrenschmidt /* This lines up nicely with the display from processing OF ranges */ 499a1339fafSBenjamin Herrenschmidt pr_info(" MEM 0x%016llx..0x%016llx -> 0x%016llx (M64 #%d..%d)\n", 500a1339fafSBenjamin Herrenschmidt res->start, res->end, pci_addr, m64_range[0], 501a1339fafSBenjamin Herrenschmidt m64_range[0] + m64_range[1] - 1); 502a1339fafSBenjamin Herrenschmidt 503a1339fafSBenjamin Herrenschmidt /* Mark all M64 used up by default */ 504a1339fafSBenjamin Herrenschmidt phb->ioda.m64_bar_alloc = (unsigned long)-1; 505e9863e68SWei Yang 506262af557SGuo Chao /* Use last M64 BAR to cover M64 window */ 507a1339fafSBenjamin Herrenschmidt m64_range[1]--; 508a1339fafSBenjamin Herrenschmidt phb->ioda.m64_bar_idx = m64_range[0] + m64_range[1]; 509a1339fafSBenjamin Herrenschmidt 510a1339fafSBenjamin Herrenschmidt pr_info(" Using M64 #%d as default window\n", phb->ioda.m64_bar_idx); 511a1339fafSBenjamin Herrenschmidt 512a1339fafSBenjamin Herrenschmidt /* Mark remaining ones free */ 513a1339fafSBenjamin Herrenschmidt for (i = m64_range[0]; i < m64_range[1]; i++) 514a1339fafSBenjamin Herrenschmidt clear_bit(i, &phb->ioda.m64_bar_alloc); 515a1339fafSBenjamin Herrenschmidt 516a1339fafSBenjamin Herrenschmidt /* 517a1339fafSBenjamin Herrenschmidt * Setup init functions for M64 based on IODA version, IODA3 uses 518a1339fafSBenjamin Herrenschmidt * the IODA2 code. 519a1339fafSBenjamin Herrenschmidt */ 52099451551SGavin Shan if (phb->type == PNV_PHB_IODA1) 52199451551SGavin Shan phb->init_m64 = pnv_ioda1_init_m64; 52299451551SGavin Shan else 523262af557SGuo Chao phb->init_m64 = pnv_ioda2_init_m64; 524c430670aSGavin Shan phb->reserve_m64_pe = pnv_ioda_reserve_m64_pe; 525c430670aSGavin Shan phb->pick_m64_pe = pnv_ioda_pick_m64_pe; 526262af557SGuo Chao } 527262af557SGuo Chao 52849dec922SGavin Shan static void pnv_ioda_freeze_pe(struct pnv_phb *phb, int pe_no) 52949dec922SGavin Shan { 53049dec922SGavin Shan struct pnv_ioda_pe *pe = &phb->ioda.pe_array[pe_no]; 53149dec922SGavin Shan struct pnv_ioda_pe *slave; 53249dec922SGavin Shan s64 rc; 53349dec922SGavin Shan 53449dec922SGavin Shan /* Fetch master PE */ 53549dec922SGavin Shan if (pe->flags & PNV_IODA_PE_SLAVE) { 53649dec922SGavin Shan pe = pe->master; 537ec8e4e9dSGavin Shan if (WARN_ON(!pe || !(pe->flags & PNV_IODA_PE_MASTER))) 538ec8e4e9dSGavin Shan return; 539ec8e4e9dSGavin Shan 54049dec922SGavin Shan pe_no = pe->pe_number; 54149dec922SGavin Shan } 54249dec922SGavin Shan 54349dec922SGavin Shan /* Freeze master PE */ 54449dec922SGavin Shan rc = opal_pci_eeh_freeze_set(phb->opal_id, 54549dec922SGavin Shan pe_no, 54649dec922SGavin Shan OPAL_EEH_ACTION_SET_FREEZE_ALL); 54749dec922SGavin Shan if (rc != OPAL_SUCCESS) { 54849dec922SGavin Shan pr_warn("%s: Failure %lld freezing PHB#%x-PE#%x\n", 54949dec922SGavin Shan __func__, rc, phb->hose->global_number, pe_no); 55049dec922SGavin Shan return; 55149dec922SGavin Shan } 55249dec922SGavin Shan 55349dec922SGavin Shan /* Freeze slave PEs */ 55449dec922SGavin Shan if (!(pe->flags & PNV_IODA_PE_MASTER)) 55549dec922SGavin Shan return; 55649dec922SGavin Shan 55749dec922SGavin Shan list_for_each_entry(slave, &pe->slaves, list) { 55849dec922SGavin Shan rc = opal_pci_eeh_freeze_set(phb->opal_id, 55949dec922SGavin Shan slave->pe_number, 56049dec922SGavin Shan OPAL_EEH_ACTION_SET_FREEZE_ALL); 56149dec922SGavin Shan if (rc != OPAL_SUCCESS) 56249dec922SGavin Shan pr_warn("%s: Failure %lld freezing PHB#%x-PE#%x\n", 56349dec922SGavin Shan __func__, rc, phb->hose->global_number, 56449dec922SGavin Shan slave->pe_number); 56549dec922SGavin Shan } 56649dec922SGavin Shan } 56749dec922SGavin Shan 568e51df2c1SAnton Blanchard static int pnv_ioda_unfreeze_pe(struct pnv_phb *phb, int pe_no, int opt) 56949dec922SGavin Shan { 57049dec922SGavin Shan struct pnv_ioda_pe *pe, *slave; 57149dec922SGavin Shan s64 rc; 57249dec922SGavin Shan 57349dec922SGavin Shan /* Find master PE */ 57449dec922SGavin Shan pe = &phb->ioda.pe_array[pe_no]; 57549dec922SGavin Shan if (pe->flags & PNV_IODA_PE_SLAVE) { 57649dec922SGavin Shan pe = pe->master; 57749dec922SGavin Shan WARN_ON(!pe || !(pe->flags & PNV_IODA_PE_MASTER)); 57849dec922SGavin Shan pe_no = pe->pe_number; 57949dec922SGavin Shan } 58049dec922SGavin Shan 58149dec922SGavin Shan /* Clear frozen state for master PE */ 58249dec922SGavin Shan rc = opal_pci_eeh_freeze_clear(phb->opal_id, pe_no, opt); 58349dec922SGavin Shan if (rc != OPAL_SUCCESS) { 58449dec922SGavin Shan pr_warn("%s: Failure %lld clear %d on PHB#%x-PE#%x\n", 58549dec922SGavin Shan __func__, rc, opt, phb->hose->global_number, pe_no); 58649dec922SGavin Shan return -EIO; 58749dec922SGavin Shan } 58849dec922SGavin Shan 58949dec922SGavin Shan if (!(pe->flags & PNV_IODA_PE_MASTER)) 59049dec922SGavin Shan return 0; 59149dec922SGavin Shan 59249dec922SGavin Shan /* Clear frozen state for slave PEs */ 59349dec922SGavin Shan list_for_each_entry(slave, &pe->slaves, list) { 59449dec922SGavin Shan rc = opal_pci_eeh_freeze_clear(phb->opal_id, 59549dec922SGavin Shan slave->pe_number, 59649dec922SGavin Shan opt); 59749dec922SGavin Shan if (rc != OPAL_SUCCESS) { 59849dec922SGavin Shan pr_warn("%s: Failure %lld clear %d on PHB#%x-PE#%x\n", 59949dec922SGavin Shan __func__, rc, opt, phb->hose->global_number, 60049dec922SGavin Shan slave->pe_number); 60149dec922SGavin Shan return -EIO; 60249dec922SGavin Shan } 60349dec922SGavin Shan } 60449dec922SGavin Shan 60549dec922SGavin Shan return 0; 60649dec922SGavin Shan } 60749dec922SGavin Shan 60849dec922SGavin Shan static int pnv_ioda_get_pe_state(struct pnv_phb *phb, int pe_no) 60949dec922SGavin Shan { 61049dec922SGavin Shan struct pnv_ioda_pe *slave, *pe; 61149dec922SGavin Shan u8 fstate, state; 61249dec922SGavin Shan __be16 pcierr; 61349dec922SGavin Shan s64 rc; 61449dec922SGavin Shan 61549dec922SGavin Shan /* Sanity check on PE number */ 61692b8f137SGavin Shan if (pe_no < 0 || pe_no >= phb->ioda.total_pe_num) 61749dec922SGavin Shan return OPAL_EEH_STOPPED_PERM_UNAVAIL; 61849dec922SGavin Shan 61949dec922SGavin Shan /* 62049dec922SGavin Shan * Fetch the master PE and the PE instance might be 62149dec922SGavin Shan * not initialized yet. 62249dec922SGavin Shan */ 62349dec922SGavin Shan pe = &phb->ioda.pe_array[pe_no]; 62449dec922SGavin Shan if (pe->flags & PNV_IODA_PE_SLAVE) { 62549dec922SGavin Shan pe = pe->master; 62649dec922SGavin Shan WARN_ON(!pe || !(pe->flags & PNV_IODA_PE_MASTER)); 62749dec922SGavin Shan pe_no = pe->pe_number; 62849dec922SGavin Shan } 62949dec922SGavin Shan 63049dec922SGavin Shan /* Check the master PE */ 63149dec922SGavin Shan rc = opal_pci_eeh_freeze_status(phb->opal_id, pe_no, 63249dec922SGavin Shan &state, &pcierr, NULL); 63349dec922SGavin Shan if (rc != OPAL_SUCCESS) { 63449dec922SGavin Shan pr_warn("%s: Failure %lld getting " 63549dec922SGavin Shan "PHB#%x-PE#%x state\n", 63649dec922SGavin Shan __func__, rc, 63749dec922SGavin Shan phb->hose->global_number, pe_no); 63849dec922SGavin Shan return OPAL_EEH_STOPPED_TEMP_UNAVAIL; 63949dec922SGavin Shan } 64049dec922SGavin Shan 64149dec922SGavin Shan /* Check the slave PE */ 64249dec922SGavin Shan if (!(pe->flags & PNV_IODA_PE_MASTER)) 64349dec922SGavin Shan return state; 64449dec922SGavin Shan 64549dec922SGavin Shan list_for_each_entry(slave, &pe->slaves, list) { 64649dec922SGavin Shan rc = opal_pci_eeh_freeze_status(phb->opal_id, 64749dec922SGavin Shan slave->pe_number, 64849dec922SGavin Shan &fstate, 64949dec922SGavin Shan &pcierr, 65049dec922SGavin Shan NULL); 65149dec922SGavin Shan if (rc != OPAL_SUCCESS) { 65249dec922SGavin Shan pr_warn("%s: Failure %lld getting " 65349dec922SGavin Shan "PHB#%x-PE#%x state\n", 65449dec922SGavin Shan __func__, rc, 65549dec922SGavin Shan phb->hose->global_number, slave->pe_number); 65649dec922SGavin Shan return OPAL_EEH_STOPPED_TEMP_UNAVAIL; 65749dec922SGavin Shan } 65849dec922SGavin Shan 65949dec922SGavin Shan /* 66049dec922SGavin Shan * Override the result based on the ascending 66149dec922SGavin Shan * priority. 66249dec922SGavin Shan */ 66349dec922SGavin Shan if (fstate > state) 66449dec922SGavin Shan state = fstate; 66549dec922SGavin Shan } 66649dec922SGavin Shan 66749dec922SGavin Shan return state; 66849dec922SGavin Shan } 66949dec922SGavin Shan 670184cd4a3SBenjamin Herrenschmidt /* Currently those 2 are only used when MSIs are enabled, this will change 671184cd4a3SBenjamin Herrenschmidt * but in the meantime, we need to protect them to avoid warnings 672184cd4a3SBenjamin Herrenschmidt */ 673184cd4a3SBenjamin Herrenschmidt #ifdef CONFIG_PCI_MSI 674f456834aSIan Munsie struct pnv_ioda_pe *pnv_ioda_get_pe(struct pci_dev *dev) 675184cd4a3SBenjamin Herrenschmidt { 676184cd4a3SBenjamin Herrenschmidt struct pci_controller *hose = pci_bus_to_host(dev->bus); 677184cd4a3SBenjamin Herrenschmidt struct pnv_phb *phb = hose->private_data; 678b72c1f65SBenjamin Herrenschmidt struct pci_dn *pdn = pci_get_pdn(dev); 679184cd4a3SBenjamin Herrenschmidt 680184cd4a3SBenjamin Herrenschmidt if (!pdn) 681184cd4a3SBenjamin Herrenschmidt return NULL; 682184cd4a3SBenjamin Herrenschmidt if (pdn->pe_number == IODA_INVALID_PE) 683184cd4a3SBenjamin Herrenschmidt return NULL; 684184cd4a3SBenjamin Herrenschmidt return &phb->ioda.pe_array[pdn->pe_number]; 685184cd4a3SBenjamin Herrenschmidt } 686184cd4a3SBenjamin Herrenschmidt #endif /* CONFIG_PCI_MSI */ 687184cd4a3SBenjamin Herrenschmidt 688b131a842SGavin Shan static int pnv_ioda_set_one_peltv(struct pnv_phb *phb, 689b131a842SGavin Shan struct pnv_ioda_pe *parent, 690b131a842SGavin Shan struct pnv_ioda_pe *child, 691b131a842SGavin Shan bool is_add) 692b131a842SGavin Shan { 693b131a842SGavin Shan const char *desc = is_add ? "adding" : "removing"; 694b131a842SGavin Shan uint8_t op = is_add ? OPAL_ADD_PE_TO_DOMAIN : 695b131a842SGavin Shan OPAL_REMOVE_PE_FROM_DOMAIN; 696b131a842SGavin Shan struct pnv_ioda_pe *slave; 697b131a842SGavin Shan long rc; 698b131a842SGavin Shan 699b131a842SGavin Shan /* Parent PE affects child PE */ 700b131a842SGavin Shan rc = opal_pci_set_peltv(phb->opal_id, parent->pe_number, 701b131a842SGavin Shan child->pe_number, op); 702b131a842SGavin Shan if (rc != OPAL_SUCCESS) { 703b131a842SGavin Shan pe_warn(child, "OPAL error %ld %s to parent PELTV\n", 704b131a842SGavin Shan rc, desc); 705b131a842SGavin Shan return -ENXIO; 706b131a842SGavin Shan } 707b131a842SGavin Shan 708b131a842SGavin Shan if (!(child->flags & PNV_IODA_PE_MASTER)) 709b131a842SGavin Shan return 0; 710b131a842SGavin Shan 711b131a842SGavin Shan /* Compound case: parent PE affects slave PEs */ 712b131a842SGavin Shan list_for_each_entry(slave, &child->slaves, list) { 713b131a842SGavin Shan rc = opal_pci_set_peltv(phb->opal_id, parent->pe_number, 714b131a842SGavin Shan slave->pe_number, op); 715b131a842SGavin Shan if (rc != OPAL_SUCCESS) { 716b131a842SGavin Shan pe_warn(slave, "OPAL error %ld %s to parent PELTV\n", 717b131a842SGavin Shan rc, desc); 718b131a842SGavin Shan return -ENXIO; 719b131a842SGavin Shan } 720b131a842SGavin Shan } 721b131a842SGavin Shan 722b131a842SGavin Shan return 0; 723b131a842SGavin Shan } 724b131a842SGavin Shan 725b131a842SGavin Shan static int pnv_ioda_set_peltv(struct pnv_phb *phb, 726b131a842SGavin Shan struct pnv_ioda_pe *pe, 727b131a842SGavin Shan bool is_add) 728b131a842SGavin Shan { 729b131a842SGavin Shan struct pnv_ioda_pe *slave; 730781a868fSWei Yang struct pci_dev *pdev = NULL; 731b131a842SGavin Shan int ret; 732b131a842SGavin Shan 733b131a842SGavin Shan /* 734b131a842SGavin Shan * Clear PE frozen state. If it's master PE, we need 735b131a842SGavin Shan * clear slave PE frozen state as well. 736b131a842SGavin Shan */ 737b131a842SGavin Shan if (is_add) { 738b131a842SGavin Shan opal_pci_eeh_freeze_clear(phb->opal_id, pe->pe_number, 739b131a842SGavin Shan OPAL_EEH_ACTION_CLEAR_FREEZE_ALL); 740b131a842SGavin Shan if (pe->flags & PNV_IODA_PE_MASTER) { 741b131a842SGavin Shan list_for_each_entry(slave, &pe->slaves, list) 742b131a842SGavin Shan opal_pci_eeh_freeze_clear(phb->opal_id, 743b131a842SGavin Shan slave->pe_number, 744b131a842SGavin Shan OPAL_EEH_ACTION_CLEAR_FREEZE_ALL); 745b131a842SGavin Shan } 746b131a842SGavin Shan } 747b131a842SGavin Shan 748b131a842SGavin Shan /* 749b131a842SGavin Shan * Associate PE in PELT. We need add the PE into the 750b131a842SGavin Shan * corresponding PELT-V as well. Otherwise, the error 751b131a842SGavin Shan * originated from the PE might contribute to other 752b131a842SGavin Shan * PEs. 753b131a842SGavin Shan */ 754b131a842SGavin Shan ret = pnv_ioda_set_one_peltv(phb, pe, pe, is_add); 755b131a842SGavin Shan if (ret) 756b131a842SGavin Shan return ret; 757b131a842SGavin Shan 758b131a842SGavin Shan /* For compound PEs, any one affects all of them */ 759b131a842SGavin Shan if (pe->flags & PNV_IODA_PE_MASTER) { 760b131a842SGavin Shan list_for_each_entry(slave, &pe->slaves, list) { 761b131a842SGavin Shan ret = pnv_ioda_set_one_peltv(phb, slave, pe, is_add); 762b131a842SGavin Shan if (ret) 763b131a842SGavin Shan return ret; 764b131a842SGavin Shan } 765b131a842SGavin Shan } 766b131a842SGavin Shan 767b131a842SGavin Shan if (pe->flags & (PNV_IODA_PE_BUS_ALL | PNV_IODA_PE_BUS)) 768b131a842SGavin Shan pdev = pe->pbus->self; 769781a868fSWei Yang else if (pe->flags & PNV_IODA_PE_DEV) 770b131a842SGavin Shan pdev = pe->pdev->bus->self; 771781a868fSWei Yang #ifdef CONFIG_PCI_IOV 772781a868fSWei Yang else if (pe->flags & PNV_IODA_PE_VF) 773283e2d8aSGavin Shan pdev = pe->parent_dev; 774781a868fSWei Yang #endif /* CONFIG_PCI_IOV */ 775b131a842SGavin Shan while (pdev) { 776b131a842SGavin Shan struct pci_dn *pdn = pci_get_pdn(pdev); 777b131a842SGavin Shan struct pnv_ioda_pe *parent; 778b131a842SGavin Shan 779b131a842SGavin Shan if (pdn && pdn->pe_number != IODA_INVALID_PE) { 780b131a842SGavin Shan parent = &phb->ioda.pe_array[pdn->pe_number]; 781b131a842SGavin Shan ret = pnv_ioda_set_one_peltv(phb, parent, pe, is_add); 782b131a842SGavin Shan if (ret) 783b131a842SGavin Shan return ret; 784b131a842SGavin Shan } 785b131a842SGavin Shan 786b131a842SGavin Shan pdev = pdev->bus->self; 787b131a842SGavin Shan } 788b131a842SGavin Shan 789b131a842SGavin Shan return 0; 790b131a842SGavin Shan } 791b131a842SGavin Shan 792781a868fSWei Yang static int pnv_ioda_deconfigure_pe(struct pnv_phb *phb, struct pnv_ioda_pe *pe) 793781a868fSWei Yang { 794781a868fSWei Yang struct pci_dev *parent; 795781a868fSWei Yang uint8_t bcomp, dcomp, fcomp; 796781a868fSWei Yang int64_t rc; 797781a868fSWei Yang long rid_end, rid; 798781a868fSWei Yang 799781a868fSWei Yang /* Currently, we just deconfigure VF PE. Bus PE will always there.*/ 800781a868fSWei Yang if (pe->pbus) { 801781a868fSWei Yang int count; 802781a868fSWei Yang 803781a868fSWei Yang dcomp = OPAL_IGNORE_RID_DEVICE_NUMBER; 804781a868fSWei Yang fcomp = OPAL_IGNORE_RID_FUNCTION_NUMBER; 805781a868fSWei Yang parent = pe->pbus->self; 806781a868fSWei Yang if (pe->flags & PNV_IODA_PE_BUS_ALL) 807781a868fSWei Yang count = pe->pbus->busn_res.end - pe->pbus->busn_res.start + 1; 808781a868fSWei Yang else 809781a868fSWei Yang count = 1; 810781a868fSWei Yang 811781a868fSWei Yang switch(count) { 812781a868fSWei Yang case 1: bcomp = OpalPciBusAll; break; 813781a868fSWei Yang case 2: bcomp = OpalPciBus7Bits; break; 814781a868fSWei Yang case 4: bcomp = OpalPciBus6Bits; break; 815781a868fSWei Yang case 8: bcomp = OpalPciBus5Bits; break; 816781a868fSWei Yang case 16: bcomp = OpalPciBus4Bits; break; 817781a868fSWei Yang case 32: bcomp = OpalPciBus3Bits; break; 818781a868fSWei Yang default: 819781a868fSWei Yang dev_err(&pe->pbus->dev, "Number of subordinate buses %d unsupported\n", 820781a868fSWei Yang count); 821781a868fSWei Yang /* Do an exact match only */ 822781a868fSWei Yang bcomp = OpalPciBusAll; 823781a868fSWei Yang } 824781a868fSWei Yang rid_end = pe->rid + (count << 8); 825781a868fSWei Yang } else { 82693e01a50SGavin Shan #ifdef CONFIG_PCI_IOV 827781a868fSWei Yang if (pe->flags & PNV_IODA_PE_VF) 828781a868fSWei Yang parent = pe->parent_dev; 829781a868fSWei Yang else 83093e01a50SGavin Shan #endif 831781a868fSWei Yang parent = pe->pdev->bus->self; 832781a868fSWei Yang bcomp = OpalPciBusAll; 833781a868fSWei Yang dcomp = OPAL_COMPARE_RID_DEVICE_NUMBER; 834781a868fSWei Yang fcomp = OPAL_COMPARE_RID_FUNCTION_NUMBER; 835781a868fSWei Yang rid_end = pe->rid + 1; 836781a868fSWei Yang } 837781a868fSWei Yang 838781a868fSWei Yang /* Clear the reverse map */ 839781a868fSWei Yang for (rid = pe->rid; rid < rid_end; rid++) 840c127562aSGavin Shan phb->ioda.pe_rmap[rid] = IODA_INVALID_PE; 841781a868fSWei Yang 842781a868fSWei Yang /* Release from all parents PELT-V */ 843781a868fSWei Yang while (parent) { 844781a868fSWei Yang struct pci_dn *pdn = pci_get_pdn(parent); 845781a868fSWei Yang if (pdn && pdn->pe_number != IODA_INVALID_PE) { 846781a868fSWei Yang rc = opal_pci_set_peltv(phb->opal_id, pdn->pe_number, 847781a868fSWei Yang pe->pe_number, OPAL_REMOVE_PE_FROM_DOMAIN); 848781a868fSWei Yang /* XXX What to do in case of error ? */ 849781a868fSWei Yang } 850781a868fSWei Yang parent = parent->bus->self; 851781a868fSWei Yang } 852781a868fSWei Yang 853f951e510SGavin Shan opal_pci_eeh_freeze_clear(phb->opal_id, pe->pe_number, 854781a868fSWei Yang OPAL_EEH_ACTION_CLEAR_FREEZE_ALL); 855781a868fSWei Yang 856781a868fSWei Yang /* Disassociate PE in PELT */ 857781a868fSWei Yang rc = opal_pci_set_peltv(phb->opal_id, pe->pe_number, 858781a868fSWei Yang pe->pe_number, OPAL_REMOVE_PE_FROM_DOMAIN); 859781a868fSWei Yang if (rc) 860781a868fSWei Yang pe_warn(pe, "OPAL error %ld remove self from PELTV\n", rc); 861781a868fSWei Yang rc = opal_pci_set_pe(phb->opal_id, pe->pe_number, pe->rid, 862781a868fSWei Yang bcomp, dcomp, fcomp, OPAL_UNMAP_PE); 863781a868fSWei Yang if (rc) 864781a868fSWei Yang pe_err(pe, "OPAL error %ld trying to setup PELT table\n", rc); 865781a868fSWei Yang 866781a868fSWei Yang pe->pbus = NULL; 867781a868fSWei Yang pe->pdev = NULL; 86893e01a50SGavin Shan #ifdef CONFIG_PCI_IOV 869781a868fSWei Yang pe->parent_dev = NULL; 87093e01a50SGavin Shan #endif 871781a868fSWei Yang 872781a868fSWei Yang return 0; 873781a868fSWei Yang } 874781a868fSWei Yang 875cad5cef6SGreg Kroah-Hartman static int pnv_ioda_configure_pe(struct pnv_phb *phb, struct pnv_ioda_pe *pe) 876184cd4a3SBenjamin Herrenschmidt { 877184cd4a3SBenjamin Herrenschmidt struct pci_dev *parent; 878184cd4a3SBenjamin Herrenschmidt uint8_t bcomp, dcomp, fcomp; 879184cd4a3SBenjamin Herrenschmidt long rc, rid_end, rid; 880184cd4a3SBenjamin Herrenschmidt 881184cd4a3SBenjamin Herrenschmidt /* Bus validation ? */ 882184cd4a3SBenjamin Herrenschmidt if (pe->pbus) { 883184cd4a3SBenjamin Herrenschmidt int count; 884184cd4a3SBenjamin Herrenschmidt 885184cd4a3SBenjamin Herrenschmidt dcomp = OPAL_IGNORE_RID_DEVICE_NUMBER; 886184cd4a3SBenjamin Herrenschmidt fcomp = OPAL_IGNORE_RID_FUNCTION_NUMBER; 887184cd4a3SBenjamin Herrenschmidt parent = pe->pbus->self; 888fb446ad0SGavin Shan if (pe->flags & PNV_IODA_PE_BUS_ALL) 889b918c62eSYinghai Lu count = pe->pbus->busn_res.end - pe->pbus->busn_res.start + 1; 890fb446ad0SGavin Shan else 891fb446ad0SGavin Shan count = 1; 892fb446ad0SGavin Shan 893184cd4a3SBenjamin Herrenschmidt switch(count) { 894184cd4a3SBenjamin Herrenschmidt case 1: bcomp = OpalPciBusAll; break; 895184cd4a3SBenjamin Herrenschmidt case 2: bcomp = OpalPciBus7Bits; break; 896184cd4a3SBenjamin Herrenschmidt case 4: bcomp = OpalPciBus6Bits; break; 897184cd4a3SBenjamin Herrenschmidt case 8: bcomp = OpalPciBus5Bits; break; 898184cd4a3SBenjamin Herrenschmidt case 16: bcomp = OpalPciBus4Bits; break; 899184cd4a3SBenjamin Herrenschmidt case 32: bcomp = OpalPciBus3Bits; break; 900184cd4a3SBenjamin Herrenschmidt default: 901781a868fSWei Yang dev_err(&pe->pbus->dev, "Number of subordinate buses %d unsupported\n", 902781a868fSWei Yang count); 903184cd4a3SBenjamin Herrenschmidt /* Do an exact match only */ 904184cd4a3SBenjamin Herrenschmidt bcomp = OpalPciBusAll; 905184cd4a3SBenjamin Herrenschmidt } 906184cd4a3SBenjamin Herrenschmidt rid_end = pe->rid + (count << 8); 907184cd4a3SBenjamin Herrenschmidt } else { 908781a868fSWei Yang #ifdef CONFIG_PCI_IOV 909781a868fSWei Yang if (pe->flags & PNV_IODA_PE_VF) 910781a868fSWei Yang parent = pe->parent_dev; 911781a868fSWei Yang else 912781a868fSWei Yang #endif /* CONFIG_PCI_IOV */ 913184cd4a3SBenjamin Herrenschmidt parent = pe->pdev->bus->self; 914184cd4a3SBenjamin Herrenschmidt bcomp = OpalPciBusAll; 915184cd4a3SBenjamin Herrenschmidt dcomp = OPAL_COMPARE_RID_DEVICE_NUMBER; 916184cd4a3SBenjamin Herrenschmidt fcomp = OPAL_COMPARE_RID_FUNCTION_NUMBER; 917184cd4a3SBenjamin Herrenschmidt rid_end = pe->rid + 1; 918184cd4a3SBenjamin Herrenschmidt } 919184cd4a3SBenjamin Herrenschmidt 920631ad691SGavin Shan /* 921631ad691SGavin Shan * Associate PE in PELT. We need add the PE into the 922631ad691SGavin Shan * corresponding PELT-V as well. Otherwise, the error 923631ad691SGavin Shan * originated from the PE might contribute to other 924631ad691SGavin Shan * PEs. 925631ad691SGavin Shan */ 926184cd4a3SBenjamin Herrenschmidt rc = opal_pci_set_pe(phb->opal_id, pe->pe_number, pe->rid, 927184cd4a3SBenjamin Herrenschmidt bcomp, dcomp, fcomp, OPAL_MAP_PE); 928184cd4a3SBenjamin Herrenschmidt if (rc) { 929184cd4a3SBenjamin Herrenschmidt pe_err(pe, "OPAL error %ld trying to setup PELT table\n", rc); 930184cd4a3SBenjamin Herrenschmidt return -ENXIO; 931184cd4a3SBenjamin Herrenschmidt } 932631ad691SGavin Shan 9335d2aa710SAlistair Popple /* 9345d2aa710SAlistair Popple * Configure PELTV. NPUs don't have a PELTV table so skip 9355d2aa710SAlistair Popple * configuration on them. 9365d2aa710SAlistair Popple */ 9377f2c39e9SFrederic Barrat if (phb->type != PNV_PHB_NPU_NVLINK && phb->type != PNV_PHB_NPU_OCAPI) 938b131a842SGavin Shan pnv_ioda_set_peltv(phb, pe, true); 939184cd4a3SBenjamin Herrenschmidt 940184cd4a3SBenjamin Herrenschmidt /* Setup reverse map */ 941184cd4a3SBenjamin Herrenschmidt for (rid = pe->rid; rid < rid_end; rid++) 942184cd4a3SBenjamin Herrenschmidt phb->ioda.pe_rmap[rid] = pe->pe_number; 943184cd4a3SBenjamin Herrenschmidt 944184cd4a3SBenjamin Herrenschmidt /* Setup one MVTs on IODA1 */ 9454773f76bSGavin Shan if (phb->type != PNV_PHB_IODA1) { 9464773f76bSGavin Shan pe->mve_number = 0; 9474773f76bSGavin Shan goto out; 9484773f76bSGavin Shan } 9494773f76bSGavin Shan 950184cd4a3SBenjamin Herrenschmidt pe->mve_number = pe->pe_number; 9514773f76bSGavin Shan rc = opal_pci_set_mve(phb->opal_id, pe->mve_number, pe->pe_number); 9524773f76bSGavin Shan if (rc != OPAL_SUCCESS) { 9531f52f176SRussell Currey pe_err(pe, "OPAL error %ld setting up MVE %x\n", 954184cd4a3SBenjamin Herrenschmidt rc, pe->mve_number); 955184cd4a3SBenjamin Herrenschmidt pe->mve_number = -1; 956184cd4a3SBenjamin Herrenschmidt } else { 957184cd4a3SBenjamin Herrenschmidt rc = opal_pci_set_mve_enable(phb->opal_id, 958cee72d5bSBenjamin Herrenschmidt pe->mve_number, OPAL_ENABLE_MVE); 959184cd4a3SBenjamin Herrenschmidt if (rc) { 9601f52f176SRussell Currey pe_err(pe, "OPAL error %ld enabling MVE %x\n", 961184cd4a3SBenjamin Herrenschmidt rc, pe->mve_number); 962184cd4a3SBenjamin Herrenschmidt pe->mve_number = -1; 963184cd4a3SBenjamin Herrenschmidt } 964184cd4a3SBenjamin Herrenschmidt } 965184cd4a3SBenjamin Herrenschmidt 9664773f76bSGavin Shan out: 967184cd4a3SBenjamin Herrenschmidt return 0; 968184cd4a3SBenjamin Herrenschmidt } 969184cd4a3SBenjamin Herrenschmidt 970781a868fSWei Yang #ifdef CONFIG_PCI_IOV 971781a868fSWei Yang static int pnv_pci_vf_resource_shift(struct pci_dev *dev, int offset) 972781a868fSWei Yang { 973781a868fSWei Yang struct pci_dn *pdn = pci_get_pdn(dev); 974781a868fSWei Yang int i; 975781a868fSWei Yang struct resource *res, res2; 976781a868fSWei Yang resource_size_t size; 977781a868fSWei Yang u16 num_vfs; 978781a868fSWei Yang 979781a868fSWei Yang if (!dev->is_physfn) 980781a868fSWei Yang return -EINVAL; 981781a868fSWei Yang 982781a868fSWei Yang /* 983781a868fSWei Yang * "offset" is in VFs. The M64 windows are sized so that when they 984781a868fSWei Yang * are segmented, each segment is the same size as the IOV BAR. 985781a868fSWei Yang * Each segment is in a separate PE, and the high order bits of the 986781a868fSWei Yang * address are the PE number. Therefore, each VF's BAR is in a 987781a868fSWei Yang * separate PE, and changing the IOV BAR start address changes the 988781a868fSWei Yang * range of PEs the VFs are in. 989781a868fSWei Yang */ 990781a868fSWei Yang num_vfs = pdn->num_vfs; 991781a868fSWei Yang for (i = 0; i < PCI_SRIOV_NUM_BARS; i++) { 992781a868fSWei Yang res = &dev->resource[i + PCI_IOV_RESOURCES]; 993781a868fSWei Yang if (!res->flags || !res->parent) 994781a868fSWei Yang continue; 995781a868fSWei Yang 996781a868fSWei Yang /* 997781a868fSWei Yang * The actual IOV BAR range is determined by the start address 998781a868fSWei Yang * and the actual size for num_vfs VFs BAR. This check is to 999781a868fSWei Yang * make sure that after shifting, the range will not overlap 1000781a868fSWei Yang * with another device. 1001781a868fSWei Yang */ 1002781a868fSWei Yang size = pci_iov_resource_size(dev, i + PCI_IOV_RESOURCES); 1003781a868fSWei Yang res2.flags = res->flags; 1004781a868fSWei Yang res2.start = res->start + (size * offset); 1005781a868fSWei Yang res2.end = res2.start + (size * num_vfs) - 1; 1006781a868fSWei Yang 1007781a868fSWei Yang if (res2.end > res->end) { 1008781a868fSWei Yang dev_err(&dev->dev, "VF BAR%d: %pR would extend past %pR (trying to enable %d VFs shifted by %d)\n", 1009781a868fSWei Yang i, &res2, res, num_vfs, offset); 1010781a868fSWei Yang return -EBUSY; 1011781a868fSWei Yang } 1012781a868fSWei Yang } 1013781a868fSWei Yang 1014781a868fSWei Yang /* 1015d6f934fdSAlexey Kardashevskiy * Since M64 BAR shares segments among all possible 256 PEs, 1016d6f934fdSAlexey Kardashevskiy * we have to shift the beginning of PF IOV BAR to make it start from 1017d6f934fdSAlexey Kardashevskiy * the segment which belongs to the PE number assigned to the first VF. 1018d6f934fdSAlexey Kardashevskiy * This creates a "hole" in the /proc/iomem which could be used for 1019d6f934fdSAlexey Kardashevskiy * allocating other resources so we reserve this area below and 1020d6f934fdSAlexey Kardashevskiy * release when IOV is released. 1021781a868fSWei Yang */ 1022781a868fSWei Yang for (i = 0; i < PCI_SRIOV_NUM_BARS; i++) { 1023781a868fSWei Yang res = &dev->resource[i + PCI_IOV_RESOURCES]; 1024781a868fSWei Yang if (!res->flags || !res->parent) 1025781a868fSWei Yang continue; 1026781a868fSWei Yang 1027781a868fSWei Yang size = pci_iov_resource_size(dev, i + PCI_IOV_RESOURCES); 1028781a868fSWei Yang res2 = *res; 1029781a868fSWei Yang res->start += size * offset; 1030781a868fSWei Yang 103174703cc4SWei Yang dev_info(&dev->dev, "VF BAR%d: %pR shifted to %pR (%sabling %d VFs shifted by %d)\n", 103274703cc4SWei Yang i, &res2, res, (offset > 0) ? "En" : "Dis", 103374703cc4SWei Yang num_vfs, offset); 1034d6f934fdSAlexey Kardashevskiy 1035d6f934fdSAlexey Kardashevskiy if (offset < 0) { 1036d6f934fdSAlexey Kardashevskiy devm_release_resource(&dev->dev, &pdn->holes[i]); 1037d6f934fdSAlexey Kardashevskiy memset(&pdn->holes[i], 0, sizeof(pdn->holes[i])); 1038d6f934fdSAlexey Kardashevskiy } 1039d6f934fdSAlexey Kardashevskiy 1040781a868fSWei Yang pci_update_resource(dev, i + PCI_IOV_RESOURCES); 1041d6f934fdSAlexey Kardashevskiy 1042d6f934fdSAlexey Kardashevskiy if (offset > 0) { 1043d6f934fdSAlexey Kardashevskiy pdn->holes[i].start = res2.start; 1044d6f934fdSAlexey Kardashevskiy pdn->holes[i].end = res2.start + size * offset - 1; 1045d6f934fdSAlexey Kardashevskiy pdn->holes[i].flags = IORESOURCE_BUS; 1046d6f934fdSAlexey Kardashevskiy pdn->holes[i].name = "pnv_iov_reserved"; 1047d6f934fdSAlexey Kardashevskiy devm_request_resource(&dev->dev, res->parent, 1048d6f934fdSAlexey Kardashevskiy &pdn->holes[i]); 1049d6f934fdSAlexey Kardashevskiy } 1050781a868fSWei Yang } 1051781a868fSWei Yang return 0; 1052781a868fSWei Yang } 1053781a868fSWei Yang #endif /* CONFIG_PCI_IOV */ 1054781a868fSWei Yang 1055cad5cef6SGreg Kroah-Hartman static struct pnv_ioda_pe *pnv_ioda_setup_dev_PE(struct pci_dev *dev) 1056184cd4a3SBenjamin Herrenschmidt { 1057184cd4a3SBenjamin Herrenschmidt struct pci_controller *hose = pci_bus_to_host(dev->bus); 1058184cd4a3SBenjamin Herrenschmidt struct pnv_phb *phb = hose->private_data; 1059b72c1f65SBenjamin Herrenschmidt struct pci_dn *pdn = pci_get_pdn(dev); 1060184cd4a3SBenjamin Herrenschmidt struct pnv_ioda_pe *pe; 1061184cd4a3SBenjamin Herrenschmidt 1062184cd4a3SBenjamin Herrenschmidt if (!pdn) { 1063184cd4a3SBenjamin Herrenschmidt pr_err("%s: Device tree node not associated properly\n", 1064184cd4a3SBenjamin Herrenschmidt pci_name(dev)); 1065184cd4a3SBenjamin Herrenschmidt return NULL; 1066184cd4a3SBenjamin Herrenschmidt } 1067184cd4a3SBenjamin Herrenschmidt if (pdn->pe_number != IODA_INVALID_PE) 1068184cd4a3SBenjamin Herrenschmidt return NULL; 1069184cd4a3SBenjamin Herrenschmidt 10701e916772SGavin Shan pe = pnv_ioda_alloc_pe(phb); 10711e916772SGavin Shan if (!pe) { 1072f2c2cbccSJoe Perches pr_warn("%s: Not enough PE# available, disabling device\n", 1073184cd4a3SBenjamin Herrenschmidt pci_name(dev)); 1074184cd4a3SBenjamin Herrenschmidt return NULL; 1075184cd4a3SBenjamin Herrenschmidt } 1076184cd4a3SBenjamin Herrenschmidt 1077184cd4a3SBenjamin Herrenschmidt /* NOTE: We get only one ref to the pci_dev for the pdn, not for the 1078184cd4a3SBenjamin Herrenschmidt * pointer in the PE data structure, both should be destroyed at the 1079184cd4a3SBenjamin Herrenschmidt * same time. However, this needs to be looked at more closely again 1080184cd4a3SBenjamin Herrenschmidt * once we actually start removing things (Hotplug, SR-IOV, ...) 1081184cd4a3SBenjamin Herrenschmidt * 1082184cd4a3SBenjamin Herrenschmidt * At some point we want to remove the PDN completely anyways 1083184cd4a3SBenjamin Herrenschmidt */ 1084184cd4a3SBenjamin Herrenschmidt pci_dev_get(dev); 1085184cd4a3SBenjamin Herrenschmidt pdn->pcidev = dev; 10861e916772SGavin Shan pdn->pe_number = pe->pe_number; 10875d2aa710SAlistair Popple pe->flags = PNV_IODA_PE_DEV; 1088184cd4a3SBenjamin Herrenschmidt pe->pdev = dev; 1089184cd4a3SBenjamin Herrenschmidt pe->pbus = NULL; 1090184cd4a3SBenjamin Herrenschmidt pe->mve_number = -1; 1091184cd4a3SBenjamin Herrenschmidt pe->rid = dev->bus->number << 8 | pdn->devfn; 1092184cd4a3SBenjamin Herrenschmidt 1093184cd4a3SBenjamin Herrenschmidt pe_info(pe, "Associated device to PE\n"); 1094184cd4a3SBenjamin Herrenschmidt 1095184cd4a3SBenjamin Herrenschmidt if (pnv_ioda_configure_pe(phb, pe)) { 1096184cd4a3SBenjamin Herrenschmidt /* XXX What do we do here ? */ 10971e916772SGavin Shan pnv_ioda_free_pe(pe); 1098184cd4a3SBenjamin Herrenschmidt pdn->pe_number = IODA_INVALID_PE; 1099184cd4a3SBenjamin Herrenschmidt pe->pdev = NULL; 1100184cd4a3SBenjamin Herrenschmidt pci_dev_put(dev); 1101184cd4a3SBenjamin Herrenschmidt return NULL; 1102184cd4a3SBenjamin Herrenschmidt } 1103184cd4a3SBenjamin Herrenschmidt 11041d4e89cfSAlexey Kardashevskiy /* Put PE to the list */ 11051d4e89cfSAlexey Kardashevskiy list_add_tail(&pe->list, &phb->ioda.pe_list); 11061d4e89cfSAlexey Kardashevskiy 1107184cd4a3SBenjamin Herrenschmidt return pe; 1108184cd4a3SBenjamin Herrenschmidt } 1109184cd4a3SBenjamin Herrenschmidt 1110184cd4a3SBenjamin Herrenschmidt static void pnv_ioda_setup_same_PE(struct pci_bus *bus, struct pnv_ioda_pe *pe) 1111184cd4a3SBenjamin Herrenschmidt { 1112184cd4a3SBenjamin Herrenschmidt struct pci_dev *dev; 1113184cd4a3SBenjamin Herrenschmidt 1114184cd4a3SBenjamin Herrenschmidt list_for_each_entry(dev, &bus->devices, bus_list) { 1115b72c1f65SBenjamin Herrenschmidt struct pci_dn *pdn = pci_get_pdn(dev); 1116184cd4a3SBenjamin Herrenschmidt 1117184cd4a3SBenjamin Herrenschmidt if (pdn == NULL) { 1118184cd4a3SBenjamin Herrenschmidt pr_warn("%s: No device node associated with device !\n", 1119184cd4a3SBenjamin Herrenschmidt pci_name(dev)); 1120184cd4a3SBenjamin Herrenschmidt continue; 1121184cd4a3SBenjamin Herrenschmidt } 1122ccd1c191SGavin Shan 1123ccd1c191SGavin Shan /* 1124ccd1c191SGavin Shan * In partial hotplug case, the PCI device might be still 1125ccd1c191SGavin Shan * associated with the PE and needn't attach it to the PE 1126ccd1c191SGavin Shan * again. 1127ccd1c191SGavin Shan */ 1128ccd1c191SGavin Shan if (pdn->pe_number != IODA_INVALID_PE) 1129ccd1c191SGavin Shan continue; 1130ccd1c191SGavin Shan 1131c5f7700bSGavin Shan pe->device_count++; 113294973b24SAlistair Popple pdn->pcidev = dev; 1133184cd4a3SBenjamin Herrenschmidt pdn->pe_number = pe->pe_number; 1134fb446ad0SGavin Shan if ((pe->flags & PNV_IODA_PE_BUS_ALL) && dev->subordinate) 1135184cd4a3SBenjamin Herrenschmidt pnv_ioda_setup_same_PE(dev->subordinate, pe); 1136184cd4a3SBenjamin Herrenschmidt } 1137184cd4a3SBenjamin Herrenschmidt } 1138184cd4a3SBenjamin Herrenschmidt 1139fb446ad0SGavin Shan /* 1140fb446ad0SGavin Shan * There're 2 types of PCI bus sensitive PEs: One that is compromised of 1141fb446ad0SGavin Shan * single PCI bus. Another one that contains the primary PCI bus and its 1142fb446ad0SGavin Shan * subordinate PCI devices and buses. The second type of PE is normally 1143fb446ad0SGavin Shan * orgiriated by PCIe-to-PCI bridge or PLX switch downstream ports. 1144fb446ad0SGavin Shan */ 11451e916772SGavin Shan static struct pnv_ioda_pe *pnv_ioda_setup_bus_PE(struct pci_bus *bus, bool all) 1146184cd4a3SBenjamin Herrenschmidt { 1147fb446ad0SGavin Shan struct pci_controller *hose = pci_bus_to_host(bus); 1148184cd4a3SBenjamin Herrenschmidt struct pnv_phb *phb = hose->private_data; 11491e916772SGavin Shan struct pnv_ioda_pe *pe = NULL; 1150ccd1c191SGavin Shan unsigned int pe_num; 1151ccd1c191SGavin Shan 1152ccd1c191SGavin Shan /* 1153ccd1c191SGavin Shan * In partial hotplug case, the PE instance might be still alive. 1154ccd1c191SGavin Shan * We should reuse it instead of allocating a new one. 1155ccd1c191SGavin Shan */ 1156ccd1c191SGavin Shan pe_num = phb->ioda.pe_rmap[bus->number << 8]; 1157ccd1c191SGavin Shan if (pe_num != IODA_INVALID_PE) { 1158ccd1c191SGavin Shan pe = &phb->ioda.pe_array[pe_num]; 1159ccd1c191SGavin Shan pnv_ioda_setup_same_PE(bus, pe); 1160ccd1c191SGavin Shan return NULL; 1161ccd1c191SGavin Shan } 1162184cd4a3SBenjamin Herrenschmidt 116363803c39SGavin Shan /* PE number for root bus should have been reserved */ 116463803c39SGavin Shan if (pci_is_root_bus(bus) && 116563803c39SGavin Shan phb->ioda.root_pe_idx != IODA_INVALID_PE) 116663803c39SGavin Shan pe = &phb->ioda.pe_array[phb->ioda.root_pe_idx]; 116763803c39SGavin Shan 1168262af557SGuo Chao /* Check if PE is determined by M64 */ 116963803c39SGavin Shan if (!pe && phb->pick_m64_pe) 11701e916772SGavin Shan pe = phb->pick_m64_pe(bus, all); 1171262af557SGuo Chao 1172262af557SGuo Chao /* The PE number isn't pinned by M64 */ 11731e916772SGavin Shan if (!pe) 11741e916772SGavin Shan pe = pnv_ioda_alloc_pe(phb); 1175262af557SGuo Chao 11761e916772SGavin Shan if (!pe) { 1177f2c2cbccSJoe Perches pr_warn("%s: Not enough PE# available for PCI bus %04x:%02x\n", 1178fb446ad0SGavin Shan __func__, pci_domain_nr(bus), bus->number); 11791e916772SGavin Shan return NULL; 1180184cd4a3SBenjamin Herrenschmidt } 1181184cd4a3SBenjamin Herrenschmidt 1182262af557SGuo Chao pe->flags |= (all ? PNV_IODA_PE_BUS_ALL : PNV_IODA_PE_BUS); 1183184cd4a3SBenjamin Herrenschmidt pe->pbus = bus; 1184184cd4a3SBenjamin Herrenschmidt pe->pdev = NULL; 1185184cd4a3SBenjamin Herrenschmidt pe->mve_number = -1; 1186b918c62eSYinghai Lu pe->rid = bus->busn_res.start << 8; 1187184cd4a3SBenjamin Herrenschmidt 1188fb446ad0SGavin Shan if (all) 11891f52f176SRussell Currey pe_info(pe, "Secondary bus %d..%d associated with PE#%x\n", 11901e916772SGavin Shan bus->busn_res.start, bus->busn_res.end, pe->pe_number); 1191fb446ad0SGavin Shan else 11921f52f176SRussell Currey pe_info(pe, "Secondary bus %d associated with PE#%x\n", 11931e916772SGavin Shan bus->busn_res.start, pe->pe_number); 1194184cd4a3SBenjamin Herrenschmidt 1195184cd4a3SBenjamin Herrenschmidt if (pnv_ioda_configure_pe(phb, pe)) { 1196184cd4a3SBenjamin Herrenschmidt /* XXX What do we do here ? */ 11971e916772SGavin Shan pnv_ioda_free_pe(pe); 1198184cd4a3SBenjamin Herrenschmidt pe->pbus = NULL; 11991e916772SGavin Shan return NULL; 1200184cd4a3SBenjamin Herrenschmidt } 1201184cd4a3SBenjamin Herrenschmidt 1202184cd4a3SBenjamin Herrenschmidt /* Associate it with all child devices */ 1203184cd4a3SBenjamin Herrenschmidt pnv_ioda_setup_same_PE(bus, pe); 1204184cd4a3SBenjamin Herrenschmidt 12057ebdf956SGavin Shan /* Put PE to the list */ 12067ebdf956SGavin Shan list_add_tail(&pe->list, &phb->ioda.pe_list); 12071e916772SGavin Shan 12081e916772SGavin Shan return pe; 1209184cd4a3SBenjamin Herrenschmidt } 1210184cd4a3SBenjamin Herrenschmidt 1211b521549aSAlistair Popple static struct pnv_ioda_pe *pnv_ioda_setup_npu_PE(struct pci_dev *npu_pdev) 12125d2aa710SAlistair Popple { 1213b521549aSAlistair Popple int pe_num, found_pe = false, rc; 1214b521549aSAlistair Popple long rid; 1215b521549aSAlistair Popple struct pnv_ioda_pe *pe; 1216b521549aSAlistair Popple struct pci_dev *gpu_pdev; 1217b521549aSAlistair Popple struct pci_dn *npu_pdn; 1218b521549aSAlistair Popple struct pci_controller *hose = pci_bus_to_host(npu_pdev->bus); 1219b521549aSAlistair Popple struct pnv_phb *phb = hose->private_data; 1220b521549aSAlistair Popple 1221b521549aSAlistair Popple /* 1222b521549aSAlistair Popple * Due to a hardware errata PE#0 on the NPU is reserved for 1223b521549aSAlistair Popple * error handling. This means we only have three PEs remaining 1224b521549aSAlistair Popple * which need to be assigned to four links, implying some 1225b521549aSAlistair Popple * links must share PEs. 1226b521549aSAlistair Popple * 1227b521549aSAlistair Popple * To achieve this we assign PEs such that NPUs linking the 1228b521549aSAlistair Popple * same GPU get assigned the same PE. 1229b521549aSAlistair Popple */ 1230b521549aSAlistair Popple gpu_pdev = pnv_pci_get_gpu_dev(npu_pdev); 123192b8f137SGavin Shan for (pe_num = 0; pe_num < phb->ioda.total_pe_num; pe_num++) { 1232b521549aSAlistair Popple pe = &phb->ioda.pe_array[pe_num]; 1233b521549aSAlistair Popple if (!pe->pdev) 1234b521549aSAlistair Popple continue; 1235b521549aSAlistair Popple 1236b521549aSAlistair Popple if (pnv_pci_get_gpu_dev(pe->pdev) == gpu_pdev) { 1237b521549aSAlistair Popple /* 1238b521549aSAlistair Popple * This device has the same peer GPU so should 1239b521549aSAlistair Popple * be assigned the same PE as the existing 1240b521549aSAlistair Popple * peer NPU. 1241b521549aSAlistair Popple */ 1242b521549aSAlistair Popple dev_info(&npu_pdev->dev, 12431f52f176SRussell Currey "Associating to existing PE %x\n", pe_num); 1244b521549aSAlistair Popple pci_dev_get(npu_pdev); 1245b521549aSAlistair Popple npu_pdn = pci_get_pdn(npu_pdev); 1246b521549aSAlistair Popple rid = npu_pdev->bus->number << 8 | npu_pdn->devfn; 1247b521549aSAlistair Popple npu_pdn->pcidev = npu_pdev; 1248b521549aSAlistair Popple npu_pdn->pe_number = pe_num; 1249b521549aSAlistair Popple phb->ioda.pe_rmap[rid] = pe->pe_number; 1250b521549aSAlistair Popple 1251b521549aSAlistair Popple /* Map the PE to this link */ 1252b521549aSAlistair Popple rc = opal_pci_set_pe(phb->opal_id, pe_num, rid, 1253b521549aSAlistair Popple OpalPciBusAll, 1254b521549aSAlistair Popple OPAL_COMPARE_RID_DEVICE_NUMBER, 1255b521549aSAlistair Popple OPAL_COMPARE_RID_FUNCTION_NUMBER, 1256b521549aSAlistair Popple OPAL_MAP_PE); 1257b521549aSAlistair Popple WARN_ON(rc != OPAL_SUCCESS); 1258b521549aSAlistair Popple found_pe = true; 1259b521549aSAlistair Popple break; 1260b521549aSAlistair Popple } 1261b521549aSAlistair Popple } 1262b521549aSAlistair Popple 1263b521549aSAlistair Popple if (!found_pe) 1264b521549aSAlistair Popple /* 1265b521549aSAlistair Popple * Could not find an existing PE so allocate a new 1266b521549aSAlistair Popple * one. 1267b521549aSAlistair Popple */ 1268b521549aSAlistair Popple return pnv_ioda_setup_dev_PE(npu_pdev); 1269b521549aSAlistair Popple else 1270b521549aSAlistair Popple return pe; 1271b521549aSAlistair Popple } 1272b521549aSAlistair Popple 1273b521549aSAlistair Popple static void pnv_ioda_setup_npu_PEs(struct pci_bus *bus) 1274b521549aSAlistair Popple { 12755d2aa710SAlistair Popple struct pci_dev *pdev; 12765d2aa710SAlistair Popple 12775d2aa710SAlistair Popple list_for_each_entry(pdev, &bus->devices, bus_list) 1278b521549aSAlistair Popple pnv_ioda_setup_npu_PE(pdev); 12795d2aa710SAlistair Popple } 12805d2aa710SAlistair Popple 1281cad5cef6SGreg Kroah-Hartman static void pnv_pci_ioda_setup_PEs(void) 1282fb446ad0SGavin Shan { 1283fb446ad0SGavin Shan struct pci_controller *hose, *tmp; 1284262af557SGuo Chao struct pnv_phb *phb; 12857f2c39e9SFrederic Barrat struct pci_bus *bus; 12867f2c39e9SFrederic Barrat struct pci_dev *pdev; 1287fb446ad0SGavin Shan 1288fb446ad0SGavin Shan list_for_each_entry_safe(hose, tmp, &hose_list, list_node) { 1289262af557SGuo Chao phb = hose->private_data; 12907f2c39e9SFrederic Barrat if (phb->type == PNV_PHB_NPU_NVLINK) { 129108f48f32SAlistair Popple /* PE#0 is needed for error reporting */ 129208f48f32SAlistair Popple pnv_ioda_reserve_pe(phb, 0); 1293b521549aSAlistair Popple pnv_ioda_setup_npu_PEs(hose->bus); 12941ab66d1fSAlistair Popple if (phb->model == PNV_PHB_MODEL_NPU2) 12951ab66d1fSAlistair Popple pnv_npu2_init(phb); 1296ccd1c191SGavin Shan } 12977f2c39e9SFrederic Barrat if (phb->type == PNV_PHB_NPU_OCAPI) { 12987f2c39e9SFrederic Barrat bus = hose->bus; 12997f2c39e9SFrederic Barrat list_for_each_entry(pdev, &bus->devices, bus_list) 13007f2c39e9SFrederic Barrat pnv_ioda_setup_dev_PE(pdev); 13017f2c39e9SFrederic Barrat } 1302fb446ad0SGavin Shan } 1303fb446ad0SGavin Shan } 1304184cd4a3SBenjamin Herrenschmidt 1305a8b2f828SGavin Shan #ifdef CONFIG_PCI_IOV 1306ee8222feSWei Yang static int pnv_pci_vf_release_m64(struct pci_dev *pdev, u16 num_vfs) 1307781a868fSWei Yang { 1308781a868fSWei Yang struct pci_bus *bus; 1309781a868fSWei Yang struct pci_controller *hose; 1310781a868fSWei Yang struct pnv_phb *phb; 1311781a868fSWei Yang struct pci_dn *pdn; 131202639b0eSWei Yang int i, j; 1313ee8222feSWei Yang int m64_bars; 1314781a868fSWei Yang 1315781a868fSWei Yang bus = pdev->bus; 1316781a868fSWei Yang hose = pci_bus_to_host(bus); 1317781a868fSWei Yang phb = hose->private_data; 1318781a868fSWei Yang pdn = pci_get_pdn(pdev); 1319781a868fSWei Yang 1320ee8222feSWei Yang if (pdn->m64_single_mode) 1321ee8222feSWei Yang m64_bars = num_vfs; 1322ee8222feSWei Yang else 1323ee8222feSWei Yang m64_bars = 1; 1324ee8222feSWei Yang 132502639b0eSWei Yang for (i = 0; i < PCI_SRIOV_NUM_BARS; i++) 1326ee8222feSWei Yang for (j = 0; j < m64_bars; j++) { 1327ee8222feSWei Yang if (pdn->m64_map[j][i] == IODA_INVALID_M64) 1328781a868fSWei Yang continue; 1329781a868fSWei Yang opal_pci_phb_mmio_enable(phb->opal_id, 1330ee8222feSWei Yang OPAL_M64_WINDOW_TYPE, pdn->m64_map[j][i], 0); 1331ee8222feSWei Yang clear_bit(pdn->m64_map[j][i], &phb->ioda.m64_bar_alloc); 1332ee8222feSWei Yang pdn->m64_map[j][i] = IODA_INVALID_M64; 1333781a868fSWei Yang } 1334781a868fSWei Yang 1335ee8222feSWei Yang kfree(pdn->m64_map); 1336781a868fSWei Yang return 0; 1337781a868fSWei Yang } 1338781a868fSWei Yang 133902639b0eSWei Yang static int pnv_pci_vf_assign_m64(struct pci_dev *pdev, u16 num_vfs) 1340781a868fSWei Yang { 1341781a868fSWei Yang struct pci_bus *bus; 1342781a868fSWei Yang struct pci_controller *hose; 1343781a868fSWei Yang struct pnv_phb *phb; 1344781a868fSWei Yang struct pci_dn *pdn; 1345781a868fSWei Yang unsigned int win; 1346781a868fSWei Yang struct resource *res; 134702639b0eSWei Yang int i, j; 1348781a868fSWei Yang int64_t rc; 134902639b0eSWei Yang int total_vfs; 135002639b0eSWei Yang resource_size_t size, start; 135102639b0eSWei Yang int pe_num; 1352ee8222feSWei Yang int m64_bars; 1353781a868fSWei Yang 1354781a868fSWei Yang bus = pdev->bus; 1355781a868fSWei Yang hose = pci_bus_to_host(bus); 1356781a868fSWei Yang phb = hose->private_data; 1357781a868fSWei Yang pdn = pci_get_pdn(pdev); 135802639b0eSWei Yang total_vfs = pci_sriov_get_totalvfs(pdev); 1359781a868fSWei Yang 1360ee8222feSWei Yang if (pdn->m64_single_mode) 1361ee8222feSWei Yang m64_bars = num_vfs; 1362ee8222feSWei Yang else 1363ee8222feSWei Yang m64_bars = 1; 136402639b0eSWei Yang 1365fb37e128SMarkus Elfring pdn->m64_map = kmalloc_array(m64_bars, 1366fb37e128SMarkus Elfring sizeof(*pdn->m64_map), 1367fb37e128SMarkus Elfring GFP_KERNEL); 1368ee8222feSWei Yang if (!pdn->m64_map) 1369ee8222feSWei Yang return -ENOMEM; 1370ee8222feSWei Yang /* Initialize the m64_map to IODA_INVALID_M64 */ 1371ee8222feSWei Yang for (i = 0; i < m64_bars ; i++) 1372ee8222feSWei Yang for (j = 0; j < PCI_SRIOV_NUM_BARS; j++) 1373ee8222feSWei Yang pdn->m64_map[i][j] = IODA_INVALID_M64; 1374ee8222feSWei Yang 1375781a868fSWei Yang 1376781a868fSWei Yang for (i = 0; i < PCI_SRIOV_NUM_BARS; i++) { 1377781a868fSWei Yang res = &pdev->resource[i + PCI_IOV_RESOURCES]; 1378781a868fSWei Yang if (!res->flags || !res->parent) 1379781a868fSWei Yang continue; 1380781a868fSWei Yang 1381ee8222feSWei Yang for (j = 0; j < m64_bars; j++) { 1382781a868fSWei Yang do { 1383781a868fSWei Yang win = find_next_zero_bit(&phb->ioda.m64_bar_alloc, 1384781a868fSWei Yang phb->ioda.m64_bar_idx + 1, 0); 1385781a868fSWei Yang 1386781a868fSWei Yang if (win >= phb->ioda.m64_bar_idx + 1) 1387781a868fSWei Yang goto m64_failed; 1388781a868fSWei Yang } while (test_and_set_bit(win, &phb->ioda.m64_bar_alloc)); 1389781a868fSWei Yang 1390ee8222feSWei Yang pdn->m64_map[j][i] = win; 139102639b0eSWei Yang 1392ee8222feSWei Yang if (pdn->m64_single_mode) { 139302639b0eSWei Yang size = pci_iov_resource_size(pdev, 139402639b0eSWei Yang PCI_IOV_RESOURCES + i); 139502639b0eSWei Yang start = res->start + size * j; 139602639b0eSWei Yang } else { 139702639b0eSWei Yang size = resource_size(res); 139802639b0eSWei Yang start = res->start; 139902639b0eSWei Yang } 1400781a868fSWei Yang 1401781a868fSWei Yang /* Map the M64 here */ 1402ee8222feSWei Yang if (pdn->m64_single_mode) { 1403be283eebSWei Yang pe_num = pdn->pe_num_map[j]; 140402639b0eSWei Yang rc = opal_pci_map_pe_mmio_window(phb->opal_id, 140502639b0eSWei Yang pe_num, OPAL_M64_WINDOW_TYPE, 1406ee8222feSWei Yang pdn->m64_map[j][i], 0); 140702639b0eSWei Yang } 140802639b0eSWei Yang 1409781a868fSWei Yang rc = opal_pci_set_phb_mem_window(phb->opal_id, 1410781a868fSWei Yang OPAL_M64_WINDOW_TYPE, 1411ee8222feSWei Yang pdn->m64_map[j][i], 141202639b0eSWei Yang start, 1413781a868fSWei Yang 0, /* unused */ 141402639b0eSWei Yang size); 141502639b0eSWei Yang 141602639b0eSWei Yang 1417781a868fSWei Yang if (rc != OPAL_SUCCESS) { 1418781a868fSWei Yang dev_err(&pdev->dev, "Failed to map M64 window #%d: %lld\n", 1419781a868fSWei Yang win, rc); 1420781a868fSWei Yang goto m64_failed; 1421781a868fSWei Yang } 1422781a868fSWei Yang 1423ee8222feSWei Yang if (pdn->m64_single_mode) 1424781a868fSWei Yang rc = opal_pci_phb_mmio_enable(phb->opal_id, 1425ee8222feSWei Yang OPAL_M64_WINDOW_TYPE, pdn->m64_map[j][i], 2); 142602639b0eSWei Yang else 142702639b0eSWei Yang rc = opal_pci_phb_mmio_enable(phb->opal_id, 1428ee8222feSWei Yang OPAL_M64_WINDOW_TYPE, pdn->m64_map[j][i], 1); 142902639b0eSWei Yang 1430781a868fSWei Yang if (rc != OPAL_SUCCESS) { 1431781a868fSWei Yang dev_err(&pdev->dev, "Failed to enable M64 window #%d: %llx\n", 1432781a868fSWei Yang win, rc); 1433781a868fSWei Yang goto m64_failed; 1434781a868fSWei Yang } 1435781a868fSWei Yang } 143602639b0eSWei Yang } 1437781a868fSWei Yang return 0; 1438781a868fSWei Yang 1439781a868fSWei Yang m64_failed: 1440ee8222feSWei Yang pnv_pci_vf_release_m64(pdev, num_vfs); 1441781a868fSWei Yang return -EBUSY; 1442781a868fSWei Yang } 1443781a868fSWei Yang 1444c035e37bSAlexey Kardashevskiy static long pnv_pci_ioda2_unset_window(struct iommu_table_group *table_group, 1445c035e37bSAlexey Kardashevskiy int num); 1446c035e37bSAlexey Kardashevskiy 1447781a868fSWei Yang static void pnv_pci_ioda2_release_dma_pe(struct pci_dev *dev, struct pnv_ioda_pe *pe) 1448781a868fSWei Yang { 1449781a868fSWei Yang struct iommu_table *tbl; 1450781a868fSWei Yang int64_t rc; 1451781a868fSWei Yang 1452b348aa65SAlexey Kardashevskiy tbl = pe->table_group.tables[0]; 1453c035e37bSAlexey Kardashevskiy rc = pnv_pci_ioda2_unset_window(&pe->table_group, 0); 1454781a868fSWei Yang if (rc) 1455781a868fSWei Yang pe_warn(pe, "OPAL error %ld release DMA window\n", rc); 1456781a868fSWei Yang 1457c035e37bSAlexey Kardashevskiy pnv_pci_ioda2_set_bypass(pe, false); 14580eaf4defSAlexey Kardashevskiy if (pe->table_group.group) { 14590eaf4defSAlexey Kardashevskiy iommu_group_put(pe->table_group.group); 14600eaf4defSAlexey Kardashevskiy BUG_ON(pe->table_group.group); 1461ac9a5889SAlexey Kardashevskiy } 1462e5afdf9dSAlexey Kardashevskiy iommu_tce_table_put(tbl); 1463781a868fSWei Yang } 1464781a868fSWei Yang 1465ee8222feSWei Yang static void pnv_ioda_release_vf_PE(struct pci_dev *pdev) 1466781a868fSWei Yang { 1467781a868fSWei Yang struct pci_bus *bus; 1468781a868fSWei Yang struct pci_controller *hose; 1469781a868fSWei Yang struct pnv_phb *phb; 1470781a868fSWei Yang struct pnv_ioda_pe *pe, *pe_n; 1471781a868fSWei Yang struct pci_dn *pdn; 1472781a868fSWei Yang 1473781a868fSWei Yang bus = pdev->bus; 1474781a868fSWei Yang hose = pci_bus_to_host(bus); 1475781a868fSWei Yang phb = hose->private_data; 147602639b0eSWei Yang pdn = pci_get_pdn(pdev); 1477781a868fSWei Yang 1478781a868fSWei Yang if (!pdev->is_physfn) 1479781a868fSWei Yang return; 1480781a868fSWei Yang 1481781a868fSWei Yang list_for_each_entry_safe(pe, pe_n, &phb->ioda.pe_list, list) { 1482781a868fSWei Yang if (pe->parent_dev != pdev) 1483781a868fSWei Yang continue; 1484781a868fSWei Yang 1485781a868fSWei Yang pnv_pci_ioda2_release_dma_pe(pdev, pe); 1486781a868fSWei Yang 1487781a868fSWei Yang /* Remove from list */ 1488781a868fSWei Yang mutex_lock(&phb->ioda.pe_list_mutex); 1489781a868fSWei Yang list_del(&pe->list); 1490781a868fSWei Yang mutex_unlock(&phb->ioda.pe_list_mutex); 1491781a868fSWei Yang 1492781a868fSWei Yang pnv_ioda_deconfigure_pe(phb, pe); 1493781a868fSWei Yang 14941e916772SGavin Shan pnv_ioda_free_pe(pe); 1495781a868fSWei Yang } 1496781a868fSWei Yang } 1497781a868fSWei Yang 1498781a868fSWei Yang void pnv_pci_sriov_disable(struct pci_dev *pdev) 1499781a868fSWei Yang { 1500781a868fSWei Yang struct pci_bus *bus; 1501781a868fSWei Yang struct pci_controller *hose; 1502781a868fSWei Yang struct pnv_phb *phb; 15031e916772SGavin Shan struct pnv_ioda_pe *pe; 1504781a868fSWei Yang struct pci_dn *pdn; 1505be283eebSWei Yang u16 num_vfs, i; 1506781a868fSWei Yang 1507781a868fSWei Yang bus = pdev->bus; 1508781a868fSWei Yang hose = pci_bus_to_host(bus); 1509781a868fSWei Yang phb = hose->private_data; 1510781a868fSWei Yang pdn = pci_get_pdn(pdev); 1511781a868fSWei Yang num_vfs = pdn->num_vfs; 1512781a868fSWei Yang 1513781a868fSWei Yang /* Release VF PEs */ 1514ee8222feSWei Yang pnv_ioda_release_vf_PE(pdev); 1515781a868fSWei Yang 1516781a868fSWei Yang if (phb->type == PNV_PHB_IODA2) { 1517ee8222feSWei Yang if (!pdn->m64_single_mode) 1518be283eebSWei Yang pnv_pci_vf_resource_shift(pdev, -*pdn->pe_num_map); 1519781a868fSWei Yang 1520781a868fSWei Yang /* Release M64 windows */ 1521ee8222feSWei Yang pnv_pci_vf_release_m64(pdev, num_vfs); 1522781a868fSWei Yang 1523781a868fSWei Yang /* Release PE numbers */ 1524be283eebSWei Yang if (pdn->m64_single_mode) { 1525be283eebSWei Yang for (i = 0; i < num_vfs; i++) { 15261e916772SGavin Shan if (pdn->pe_num_map[i] == IODA_INVALID_PE) 15271e916772SGavin Shan continue; 15281e916772SGavin Shan 15291e916772SGavin Shan pe = &phb->ioda.pe_array[pdn->pe_num_map[i]]; 15301e916772SGavin Shan pnv_ioda_free_pe(pe); 1531be283eebSWei Yang } 1532be283eebSWei Yang } else 1533be283eebSWei Yang bitmap_clear(phb->ioda.pe_alloc, *pdn->pe_num_map, num_vfs); 1534be283eebSWei Yang /* Releasing pe_num_map */ 1535be283eebSWei Yang kfree(pdn->pe_num_map); 1536781a868fSWei Yang } 1537781a868fSWei Yang } 1538781a868fSWei Yang 1539781a868fSWei Yang static void pnv_pci_ioda2_setup_dma_pe(struct pnv_phb *phb, 1540781a868fSWei Yang struct pnv_ioda_pe *pe); 1541781a868fSWei Yang static void pnv_ioda_setup_vf_PE(struct pci_dev *pdev, u16 num_vfs) 1542781a868fSWei Yang { 1543781a868fSWei Yang struct pci_bus *bus; 1544781a868fSWei Yang struct pci_controller *hose; 1545781a868fSWei Yang struct pnv_phb *phb; 1546781a868fSWei Yang struct pnv_ioda_pe *pe; 1547781a868fSWei Yang int pe_num; 1548781a868fSWei Yang u16 vf_index; 1549781a868fSWei Yang struct pci_dn *pdn; 1550781a868fSWei Yang 1551781a868fSWei Yang bus = pdev->bus; 1552781a868fSWei Yang hose = pci_bus_to_host(bus); 1553781a868fSWei Yang phb = hose->private_data; 1554781a868fSWei Yang pdn = pci_get_pdn(pdev); 1555781a868fSWei Yang 1556781a868fSWei Yang if (!pdev->is_physfn) 1557781a868fSWei Yang return; 1558781a868fSWei Yang 1559781a868fSWei Yang /* Reserve PE for each VF */ 1560781a868fSWei Yang for (vf_index = 0; vf_index < num_vfs; vf_index++) { 1561be283eebSWei Yang if (pdn->m64_single_mode) 1562be283eebSWei Yang pe_num = pdn->pe_num_map[vf_index]; 1563be283eebSWei Yang else 1564be283eebSWei Yang pe_num = *pdn->pe_num_map + vf_index; 1565781a868fSWei Yang 1566781a868fSWei Yang pe = &phb->ioda.pe_array[pe_num]; 1567781a868fSWei Yang pe->pe_number = pe_num; 1568781a868fSWei Yang pe->phb = phb; 1569781a868fSWei Yang pe->flags = PNV_IODA_PE_VF; 1570781a868fSWei Yang pe->pbus = NULL; 1571781a868fSWei Yang pe->parent_dev = pdev; 1572781a868fSWei Yang pe->mve_number = -1; 1573781a868fSWei Yang pe->rid = (pci_iov_virtfn_bus(pdev, vf_index) << 8) | 1574781a868fSWei Yang pci_iov_virtfn_devfn(pdev, vf_index); 1575781a868fSWei Yang 15761f52f176SRussell Currey pe_info(pe, "VF %04d:%02d:%02d.%d associated with PE#%x\n", 1577781a868fSWei Yang hose->global_number, pdev->bus->number, 1578781a868fSWei Yang PCI_SLOT(pci_iov_virtfn_devfn(pdev, vf_index)), 1579781a868fSWei Yang PCI_FUNC(pci_iov_virtfn_devfn(pdev, vf_index)), pe_num); 1580781a868fSWei Yang 1581781a868fSWei Yang if (pnv_ioda_configure_pe(phb, pe)) { 1582781a868fSWei Yang /* XXX What do we do here ? */ 15831e916772SGavin Shan pnv_ioda_free_pe(pe); 1584781a868fSWei Yang pe->pdev = NULL; 1585781a868fSWei Yang continue; 1586781a868fSWei Yang } 1587781a868fSWei Yang 1588781a868fSWei Yang /* Put PE to the list */ 1589781a868fSWei Yang mutex_lock(&phb->ioda.pe_list_mutex); 1590781a868fSWei Yang list_add_tail(&pe->list, &phb->ioda.pe_list); 1591781a868fSWei Yang mutex_unlock(&phb->ioda.pe_list_mutex); 1592781a868fSWei Yang 1593781a868fSWei Yang pnv_pci_ioda2_setup_dma_pe(phb, pe); 1594781a868fSWei Yang } 1595781a868fSWei Yang } 1596781a868fSWei Yang 1597781a868fSWei Yang int pnv_pci_sriov_enable(struct pci_dev *pdev, u16 num_vfs) 1598781a868fSWei Yang { 1599781a868fSWei Yang struct pci_bus *bus; 1600781a868fSWei Yang struct pci_controller *hose; 1601781a868fSWei Yang struct pnv_phb *phb; 16021e916772SGavin Shan struct pnv_ioda_pe *pe; 1603781a868fSWei Yang struct pci_dn *pdn; 1604781a868fSWei Yang int ret; 1605be283eebSWei Yang u16 i; 1606781a868fSWei Yang 1607781a868fSWei Yang bus = pdev->bus; 1608781a868fSWei Yang hose = pci_bus_to_host(bus); 1609781a868fSWei Yang phb = hose->private_data; 1610781a868fSWei Yang pdn = pci_get_pdn(pdev); 1611781a868fSWei Yang 1612781a868fSWei Yang if (phb->type == PNV_PHB_IODA2) { 1613b0331854SWei Yang if (!pdn->vfs_expanded) { 1614b0331854SWei Yang dev_info(&pdev->dev, "don't support this SRIOV device" 1615b0331854SWei Yang " with non 64bit-prefetchable IOV BAR\n"); 1616b0331854SWei Yang return -ENOSPC; 1617b0331854SWei Yang } 1618b0331854SWei Yang 1619ee8222feSWei Yang /* 1620ee8222feSWei Yang * When M64 BARs functions in Single PE mode, the number of VFs 1621ee8222feSWei Yang * could be enabled must be less than the number of M64 BARs. 1622ee8222feSWei Yang */ 1623ee8222feSWei Yang if (pdn->m64_single_mode && num_vfs > phb->ioda.m64_bar_idx) { 1624ee8222feSWei Yang dev_info(&pdev->dev, "Not enough M64 BAR for VFs\n"); 1625ee8222feSWei Yang return -EBUSY; 1626ee8222feSWei Yang } 1627ee8222feSWei Yang 1628be283eebSWei Yang /* Allocating pe_num_map */ 1629be283eebSWei Yang if (pdn->m64_single_mode) 1630fb37e128SMarkus Elfring pdn->pe_num_map = kmalloc_array(num_vfs, 1631fb37e128SMarkus Elfring sizeof(*pdn->pe_num_map), 1632be283eebSWei Yang GFP_KERNEL); 1633be283eebSWei Yang else 1634be283eebSWei Yang pdn->pe_num_map = kmalloc(sizeof(*pdn->pe_num_map), GFP_KERNEL); 1635be283eebSWei Yang 1636be283eebSWei Yang if (!pdn->pe_num_map) 1637be283eebSWei Yang return -ENOMEM; 1638be283eebSWei Yang 1639be283eebSWei Yang if (pdn->m64_single_mode) 1640be283eebSWei Yang for (i = 0; i < num_vfs; i++) 1641be283eebSWei Yang pdn->pe_num_map[i] = IODA_INVALID_PE; 1642be283eebSWei Yang 1643781a868fSWei Yang /* Calculate available PE for required VFs */ 1644be283eebSWei Yang if (pdn->m64_single_mode) { 1645be283eebSWei Yang for (i = 0; i < num_vfs; i++) { 16461e916772SGavin Shan pe = pnv_ioda_alloc_pe(phb); 16471e916772SGavin Shan if (!pe) { 1648be283eebSWei Yang ret = -EBUSY; 1649be283eebSWei Yang goto m64_failed; 1650be283eebSWei Yang } 16511e916772SGavin Shan 16521e916772SGavin Shan pdn->pe_num_map[i] = pe->pe_number; 1653be283eebSWei Yang } 1654be283eebSWei Yang } else { 1655781a868fSWei Yang mutex_lock(&phb->ioda.pe_alloc_mutex); 1656be283eebSWei Yang *pdn->pe_num_map = bitmap_find_next_zero_area( 165792b8f137SGavin Shan phb->ioda.pe_alloc, phb->ioda.total_pe_num, 1658781a868fSWei Yang 0, num_vfs, 0); 165992b8f137SGavin Shan if (*pdn->pe_num_map >= phb->ioda.total_pe_num) { 1660781a868fSWei Yang mutex_unlock(&phb->ioda.pe_alloc_mutex); 1661781a868fSWei Yang dev_info(&pdev->dev, "Failed to enable VF%d\n", num_vfs); 1662be283eebSWei Yang kfree(pdn->pe_num_map); 1663781a868fSWei Yang return -EBUSY; 1664781a868fSWei Yang } 1665be283eebSWei Yang bitmap_set(phb->ioda.pe_alloc, *pdn->pe_num_map, num_vfs); 1666781a868fSWei Yang mutex_unlock(&phb->ioda.pe_alloc_mutex); 1667be283eebSWei Yang } 1668be283eebSWei Yang pdn->num_vfs = num_vfs; 1669781a868fSWei Yang 1670781a868fSWei Yang /* Assign M64 window accordingly */ 167102639b0eSWei Yang ret = pnv_pci_vf_assign_m64(pdev, num_vfs); 1672781a868fSWei Yang if (ret) { 1673781a868fSWei Yang dev_info(&pdev->dev, "Not enough M64 window resources\n"); 1674781a868fSWei Yang goto m64_failed; 1675781a868fSWei Yang } 1676781a868fSWei Yang 1677781a868fSWei Yang /* 1678781a868fSWei Yang * When using one M64 BAR to map one IOV BAR, we need to shift 1679781a868fSWei Yang * the IOV BAR according to the PE# allocated to the VFs. 1680781a868fSWei Yang * Otherwise, the PE# for the VF will conflict with others. 1681781a868fSWei Yang */ 1682ee8222feSWei Yang if (!pdn->m64_single_mode) { 1683be283eebSWei Yang ret = pnv_pci_vf_resource_shift(pdev, *pdn->pe_num_map); 1684781a868fSWei Yang if (ret) 1685781a868fSWei Yang goto m64_failed; 1686781a868fSWei Yang } 168702639b0eSWei Yang } 1688781a868fSWei Yang 1689781a868fSWei Yang /* Setup VF PEs */ 1690781a868fSWei Yang pnv_ioda_setup_vf_PE(pdev, num_vfs); 1691781a868fSWei Yang 1692781a868fSWei Yang return 0; 1693781a868fSWei Yang 1694781a868fSWei Yang m64_failed: 1695be283eebSWei Yang if (pdn->m64_single_mode) { 1696be283eebSWei Yang for (i = 0; i < num_vfs; i++) { 16971e916772SGavin Shan if (pdn->pe_num_map[i] == IODA_INVALID_PE) 16981e916772SGavin Shan continue; 16991e916772SGavin Shan 17001e916772SGavin Shan pe = &phb->ioda.pe_array[pdn->pe_num_map[i]]; 17011e916772SGavin Shan pnv_ioda_free_pe(pe); 1702be283eebSWei Yang } 1703be283eebSWei Yang } else 1704be283eebSWei Yang bitmap_clear(phb->ioda.pe_alloc, *pdn->pe_num_map, num_vfs); 1705be283eebSWei Yang 1706be283eebSWei Yang /* Releasing pe_num_map */ 1707be283eebSWei Yang kfree(pdn->pe_num_map); 1708781a868fSWei Yang 1709781a868fSWei Yang return ret; 1710781a868fSWei Yang } 1711781a868fSWei Yang 1712988fc3baSBryant G. Ly int pnv_pcibios_sriov_disable(struct pci_dev *pdev) 1713a8b2f828SGavin Shan { 1714781a868fSWei Yang pnv_pci_sriov_disable(pdev); 1715781a868fSWei Yang 1716a8b2f828SGavin Shan /* Release PCI data */ 1717a8b2f828SGavin Shan remove_dev_pci_data(pdev); 1718a8b2f828SGavin Shan return 0; 1719a8b2f828SGavin Shan } 1720a8b2f828SGavin Shan 1721988fc3baSBryant G. Ly int pnv_pcibios_sriov_enable(struct pci_dev *pdev, u16 num_vfs) 1722a8b2f828SGavin Shan { 1723a8b2f828SGavin Shan /* Allocate PCI data */ 1724a8b2f828SGavin Shan add_dev_pci_data(pdev); 1725781a868fSWei Yang 1726ee8222feSWei Yang return pnv_pci_sriov_enable(pdev, num_vfs); 1727a8b2f828SGavin Shan } 1728a8b2f828SGavin Shan #endif /* CONFIG_PCI_IOV */ 1729a8b2f828SGavin Shan 1730959c9bddSGavin Shan static void pnv_pci_ioda_dma_dev_setup(struct pnv_phb *phb, struct pci_dev *pdev) 1731184cd4a3SBenjamin Herrenschmidt { 1732b72c1f65SBenjamin Herrenschmidt struct pci_dn *pdn = pci_get_pdn(pdev); 1733959c9bddSGavin Shan struct pnv_ioda_pe *pe; 1734184cd4a3SBenjamin Herrenschmidt 1735959c9bddSGavin Shan /* 1736959c9bddSGavin Shan * The function can be called while the PE# 1737959c9bddSGavin Shan * hasn't been assigned. Do nothing for the 1738959c9bddSGavin Shan * case. 1739959c9bddSGavin Shan */ 1740959c9bddSGavin Shan if (!pdn || pdn->pe_number == IODA_INVALID_PE) 1741959c9bddSGavin Shan return; 1742184cd4a3SBenjamin Herrenschmidt 1743959c9bddSGavin Shan pe = &phb->ioda.pe_array[pdn->pe_number]; 1744cd15b048SBenjamin Herrenschmidt WARN_ON(get_dma_ops(&pdev->dev) != &dma_iommu_ops); 17450e1ffef0SAlexey Kardashevskiy set_dma_offset(&pdev->dev, pe->tce_bypass_base); 1746b348aa65SAlexey Kardashevskiy set_iommu_table_base(&pdev->dev, pe->table_group.tables[0]); 17474617082eSAlexey Kardashevskiy /* 17484617082eSAlexey Kardashevskiy * Note: iommu_add_device() will fail here as 17494617082eSAlexey Kardashevskiy * for physical PE: the device is already added by now; 17504617082eSAlexey Kardashevskiy * for virtual PE: sysfs entries are not ready yet and 17514617082eSAlexey Kardashevskiy * tce_iommu_bus_notifier will add the device to a group later. 17524617082eSAlexey Kardashevskiy */ 1753184cd4a3SBenjamin Herrenschmidt } 1754184cd4a3SBenjamin Herrenschmidt 1755a0f98629SRussell Currey static bool pnv_pci_ioda_pe_single_vendor(struct pnv_ioda_pe *pe) 1756a0f98629SRussell Currey { 1757a0f98629SRussell Currey unsigned short vendor = 0; 1758a0f98629SRussell Currey struct pci_dev *pdev; 1759a0f98629SRussell Currey 1760a0f98629SRussell Currey if (pe->device_count == 1) 1761a0f98629SRussell Currey return true; 1762a0f98629SRussell Currey 1763a0f98629SRussell Currey /* pe->pdev should be set if it's a single device, pe->pbus if not */ 1764a0f98629SRussell Currey if (!pe->pbus) 1765a0f98629SRussell Currey return true; 1766a0f98629SRussell Currey 1767a0f98629SRussell Currey list_for_each_entry(pdev, &pe->pbus->devices, bus_list) { 1768a0f98629SRussell Currey if (!vendor) { 1769a0f98629SRussell Currey vendor = pdev->vendor; 1770a0f98629SRussell Currey continue; 1771a0f98629SRussell Currey } 1772a0f98629SRussell Currey 1773a0f98629SRussell Currey if (pdev->vendor != vendor) 1774a0f98629SRussell Currey return false; 1775a0f98629SRussell Currey } 1776a0f98629SRussell Currey 1777a0f98629SRussell Currey return true; 1778a0f98629SRussell Currey } 1779a0f98629SRussell Currey 17808e3f1b1dSRussell Currey /* 17818e3f1b1dSRussell Currey * Reconfigure TVE#0 to be usable as 64-bit DMA space. 17828e3f1b1dSRussell Currey * 17838e3f1b1dSRussell Currey * The first 4GB of virtual memory for a PE is reserved for 32-bit accesses. 17848e3f1b1dSRussell Currey * Devices can only access more than that if bit 59 of the PCI address is set 17858e3f1b1dSRussell Currey * by hardware, which indicates TVE#1 should be used instead of TVE#0. 17868e3f1b1dSRussell Currey * Many PCI devices are not capable of addressing that many bits, and as a 17878e3f1b1dSRussell Currey * result are limited to the 4GB of virtual memory made available to 32-bit 17888e3f1b1dSRussell Currey * devices in TVE#0. 17898e3f1b1dSRussell Currey * 17908e3f1b1dSRussell Currey * In order to work around this, reconfigure TVE#0 to be suitable for 64-bit 17918e3f1b1dSRussell Currey * devices by configuring the virtual memory past the first 4GB inaccessible 17928e3f1b1dSRussell Currey * by 64-bit DMAs. This should only be used by devices that want more than 17938e3f1b1dSRussell Currey * 4GB, and only on PEs that have no 32-bit devices. 17948e3f1b1dSRussell Currey * 17958e3f1b1dSRussell Currey * Currently this will only work on PHB3 (POWER8). 17968e3f1b1dSRussell Currey */ 17978e3f1b1dSRussell Currey static int pnv_pci_ioda_dma_64bit_bypass(struct pnv_ioda_pe *pe) 17988e3f1b1dSRussell Currey { 17998e3f1b1dSRussell Currey u64 window_size, table_size, tce_count, addr; 18008e3f1b1dSRussell Currey struct page *table_pages; 18018e3f1b1dSRussell Currey u64 tce_order = 28; /* 256MB TCEs */ 18028e3f1b1dSRussell Currey __be64 *tces; 18038e3f1b1dSRussell Currey s64 rc; 18048e3f1b1dSRussell Currey 18058e3f1b1dSRussell Currey /* 18068e3f1b1dSRussell Currey * Window size needs to be a power of two, but needs to account for 18078e3f1b1dSRussell Currey * shifting memory by the 4GB offset required to skip 32bit space. 18088e3f1b1dSRussell Currey */ 18098e3f1b1dSRussell Currey window_size = roundup_pow_of_two(memory_hotplug_max() + (1ULL << 32)); 18108e3f1b1dSRussell Currey tce_count = window_size >> tce_order; 18118e3f1b1dSRussell Currey table_size = tce_count << 3; 18128e3f1b1dSRussell Currey 18138e3f1b1dSRussell Currey if (table_size < PAGE_SIZE) 18148e3f1b1dSRussell Currey table_size = PAGE_SIZE; 18158e3f1b1dSRussell Currey 18168e3f1b1dSRussell Currey table_pages = alloc_pages_node(pe->phb->hose->node, GFP_KERNEL, 18178e3f1b1dSRussell Currey get_order(table_size)); 18188e3f1b1dSRussell Currey if (!table_pages) 18198e3f1b1dSRussell Currey goto err; 18208e3f1b1dSRussell Currey 18218e3f1b1dSRussell Currey tces = page_address(table_pages); 18228e3f1b1dSRussell Currey if (!tces) 18238e3f1b1dSRussell Currey goto err; 18248e3f1b1dSRussell Currey 18258e3f1b1dSRussell Currey memset(tces, 0, table_size); 18268e3f1b1dSRussell Currey 18278e3f1b1dSRussell Currey for (addr = 0; addr < memory_hotplug_max(); addr += (1 << tce_order)) { 18288e3f1b1dSRussell Currey tces[(addr + (1ULL << 32)) >> tce_order] = 18298e3f1b1dSRussell Currey cpu_to_be64(addr | TCE_PCI_READ | TCE_PCI_WRITE); 18308e3f1b1dSRussell Currey } 18318e3f1b1dSRussell Currey 18328e3f1b1dSRussell Currey rc = opal_pci_map_pe_dma_window(pe->phb->opal_id, 18338e3f1b1dSRussell Currey pe->pe_number, 18348e3f1b1dSRussell Currey /* reconfigure window 0 */ 18358e3f1b1dSRussell Currey (pe->pe_number << 1) + 0, 18368e3f1b1dSRussell Currey 1, 18378e3f1b1dSRussell Currey __pa(tces), 18388e3f1b1dSRussell Currey table_size, 18398e3f1b1dSRussell Currey 1 << tce_order); 18408e3f1b1dSRussell Currey if (rc == OPAL_SUCCESS) { 18418e3f1b1dSRussell Currey pe_info(pe, "Using 64-bit DMA iommu bypass (through TVE#0)\n"); 18428e3f1b1dSRussell Currey return 0; 18438e3f1b1dSRussell Currey } 18448e3f1b1dSRussell Currey err: 18458e3f1b1dSRussell Currey pe_err(pe, "Error configuring 64-bit DMA bypass\n"); 18468e3f1b1dSRussell Currey return -EIO; 18478e3f1b1dSRussell Currey } 18488e3f1b1dSRussell Currey 1849763d2d8dSDaniel Axtens static int pnv_pci_ioda_dma_set_mask(struct pci_dev *pdev, u64 dma_mask) 1850cd15b048SBenjamin Herrenschmidt { 1851763d2d8dSDaniel Axtens struct pci_controller *hose = pci_bus_to_host(pdev->bus); 1852763d2d8dSDaniel Axtens struct pnv_phb *phb = hose->private_data; 1853cd15b048SBenjamin Herrenschmidt struct pci_dn *pdn = pci_get_pdn(pdev); 1854cd15b048SBenjamin Herrenschmidt struct pnv_ioda_pe *pe; 1855cd15b048SBenjamin Herrenschmidt uint64_t top; 1856cd15b048SBenjamin Herrenschmidt bool bypass = false; 18578e3f1b1dSRussell Currey s64 rc; 1858cd15b048SBenjamin Herrenschmidt 1859cd15b048SBenjamin Herrenschmidt if (WARN_ON(!pdn || pdn->pe_number == IODA_INVALID_PE)) 1860cd15b048SBenjamin Herrenschmidt return -ENODEV;; 1861cd15b048SBenjamin Herrenschmidt 1862cd15b048SBenjamin Herrenschmidt pe = &phb->ioda.pe_array[pdn->pe_number]; 1863cd15b048SBenjamin Herrenschmidt if (pe->tce_bypass_enabled) { 1864cd15b048SBenjamin Herrenschmidt top = pe->tce_bypass_base + memblock_end_of_DRAM() - 1; 1865cd15b048SBenjamin Herrenschmidt bypass = (dma_mask >= top); 1866cd15b048SBenjamin Herrenschmidt } 1867cd15b048SBenjamin Herrenschmidt 1868cd15b048SBenjamin Herrenschmidt if (bypass) { 1869cd15b048SBenjamin Herrenschmidt dev_info(&pdev->dev, "Using 64-bit DMA iommu bypass\n"); 1870cd15b048SBenjamin Herrenschmidt set_dma_ops(&pdev->dev, &dma_direct_ops); 1871cd15b048SBenjamin Herrenschmidt } else { 18728e3f1b1dSRussell Currey /* 18738e3f1b1dSRussell Currey * If the device can't set the TCE bypass bit but still wants 18748e3f1b1dSRussell Currey * to access 4GB or more, on PHB3 we can reconfigure TVE#0 to 18758e3f1b1dSRussell Currey * bypass the 32-bit region and be usable for 64-bit DMAs. 18768e3f1b1dSRussell Currey * The device needs to be able to address all of this space. 18778e3f1b1dSRussell Currey */ 18788e3f1b1dSRussell Currey if (dma_mask >> 32 && 18798e3f1b1dSRussell Currey dma_mask > (memory_hotplug_max() + (1ULL << 32)) && 18808e3f1b1dSRussell Currey pnv_pci_ioda_pe_single_vendor(pe) && 18818e3f1b1dSRussell Currey phb->model == PNV_PHB_MODEL_PHB3) { 18828e3f1b1dSRussell Currey /* Configure the bypass mode */ 18838e3f1b1dSRussell Currey rc = pnv_pci_ioda_dma_64bit_bypass(pe); 18848e3f1b1dSRussell Currey if (rc) 18858e3f1b1dSRussell Currey return rc; 18868e3f1b1dSRussell Currey /* 4GB offset bypasses 32-bit space */ 18878e3f1b1dSRussell Currey set_dma_offset(&pdev->dev, (1ULL << 32)); 18888e3f1b1dSRussell Currey set_dma_ops(&pdev->dev, &dma_direct_ops); 1889253fd51eSAlistair Popple } else if (dma_mask >> 32 && dma_mask != DMA_BIT_MASK(64)) { 1890253fd51eSAlistair Popple /* 1891253fd51eSAlistair Popple * Fail the request if a DMA mask between 32 and 64 bits 1892253fd51eSAlistair Popple * was requested but couldn't be fulfilled. Ideally we 1893253fd51eSAlistair Popple * would do this for 64-bits but historically we have 1894253fd51eSAlistair Popple * always fallen back to 32-bits. 1895253fd51eSAlistair Popple */ 1896253fd51eSAlistair Popple return -ENOMEM; 18978e3f1b1dSRussell Currey } else { 1898cd15b048SBenjamin Herrenschmidt dev_info(&pdev->dev, "Using 32-bit DMA via iommu\n"); 1899cd15b048SBenjamin Herrenschmidt set_dma_ops(&pdev->dev, &dma_iommu_ops); 1900cd15b048SBenjamin Herrenschmidt } 19018e3f1b1dSRussell Currey } 1902a32305bfSBrian W Hart *pdev->dev.dma_mask = dma_mask; 19035d2aa710SAlistair Popple 19045d2aa710SAlistair Popple /* Update peer npu devices */ 1905f9f83456SAlexey Kardashevskiy pnv_npu_try_dma_set_bypass(pdev, bypass); 19065d2aa710SAlistair Popple 1907cd15b048SBenjamin Herrenschmidt return 0; 1908cd15b048SBenjamin Herrenschmidt } 1909cd15b048SBenjamin Herrenschmidt 191053522982SAndrew Donnellan static u64 pnv_pci_ioda_dma_get_required_mask(struct pci_dev *pdev) 1911fe7e85c6SGavin Shan { 191253522982SAndrew Donnellan struct pci_controller *hose = pci_bus_to_host(pdev->bus); 191353522982SAndrew Donnellan struct pnv_phb *phb = hose->private_data; 1914fe7e85c6SGavin Shan struct pci_dn *pdn = pci_get_pdn(pdev); 1915fe7e85c6SGavin Shan struct pnv_ioda_pe *pe; 1916fe7e85c6SGavin Shan u64 end, mask; 1917fe7e85c6SGavin Shan 1918fe7e85c6SGavin Shan if (WARN_ON(!pdn || pdn->pe_number == IODA_INVALID_PE)) 1919fe7e85c6SGavin Shan return 0; 1920fe7e85c6SGavin Shan 1921fe7e85c6SGavin Shan pe = &phb->ioda.pe_array[pdn->pe_number]; 1922fe7e85c6SGavin Shan if (!pe->tce_bypass_enabled) 1923fe7e85c6SGavin Shan return __dma_get_required_mask(&pdev->dev); 1924fe7e85c6SGavin Shan 1925fe7e85c6SGavin Shan 1926fe7e85c6SGavin Shan end = pe->tce_bypass_base + memblock_end_of_DRAM(); 1927fe7e85c6SGavin Shan mask = 1ULL << (fls64(end) - 1); 1928fe7e85c6SGavin Shan mask += mask - 1; 1929fe7e85c6SGavin Shan 1930fe7e85c6SGavin Shan return mask; 1931fe7e85c6SGavin Shan } 1932fe7e85c6SGavin Shan 1933dff4a39eSGavin Shan static void pnv_ioda_setup_bus_dma(struct pnv_ioda_pe *pe, 1934db08e1d5SAlexey Kardashevskiy struct pci_bus *bus, 1935db08e1d5SAlexey Kardashevskiy bool add_to_group) 193674251fe2SBenjamin Herrenschmidt { 193774251fe2SBenjamin Herrenschmidt struct pci_dev *dev; 193874251fe2SBenjamin Herrenschmidt 193974251fe2SBenjamin Herrenschmidt list_for_each_entry(dev, &bus->devices, bus_list) { 1940b348aa65SAlexey Kardashevskiy set_iommu_table_base(&dev->dev, pe->table_group.tables[0]); 1941e91c2511SBenjamin Herrenschmidt set_dma_offset(&dev->dev, pe->tce_bypass_base); 1942db08e1d5SAlexey Kardashevskiy if (add_to_group) 19434617082eSAlexey Kardashevskiy iommu_add_device(&dev->dev); 1944dff4a39eSGavin Shan 19455c89a87dSAlexey Kardashevskiy if ((pe->flags & PNV_IODA_PE_BUS_ALL) && dev->subordinate) 1946db08e1d5SAlexey Kardashevskiy pnv_ioda_setup_bus_dma(pe, dev->subordinate, 1947db08e1d5SAlexey Kardashevskiy add_to_group); 194874251fe2SBenjamin Herrenschmidt } 194974251fe2SBenjamin Herrenschmidt } 195074251fe2SBenjamin Herrenschmidt 1951fd141d1aSBenjamin Herrenschmidt static inline __be64 __iomem *pnv_ioda_get_inval_reg(struct pnv_phb *phb, 1952fd141d1aSBenjamin Herrenschmidt bool real_mode) 1953fd141d1aSBenjamin Herrenschmidt { 1954fd141d1aSBenjamin Herrenschmidt return real_mode ? (__be64 __iomem *)(phb->regs_phys + 0x210) : 1955fd141d1aSBenjamin Herrenschmidt (phb->regs + 0x210); 1956fd141d1aSBenjamin Herrenschmidt } 1957fd141d1aSBenjamin Herrenschmidt 1958a34ab7c3SBenjamin Herrenschmidt static void pnv_pci_p7ioc_tce_invalidate(struct iommu_table *tbl, 1959decbda25SAlexey Kardashevskiy unsigned long index, unsigned long npages, bool rm) 19604cce9550SGavin Shan { 19610eaf4defSAlexey Kardashevskiy struct iommu_table_group_link *tgl = list_first_entry_or_null( 19620eaf4defSAlexey Kardashevskiy &tbl->it_group_list, struct iommu_table_group_link, 19630eaf4defSAlexey Kardashevskiy next); 19640eaf4defSAlexey Kardashevskiy struct pnv_ioda_pe *pe = container_of(tgl->table_group, 1965b348aa65SAlexey Kardashevskiy struct pnv_ioda_pe, table_group); 1966fd141d1aSBenjamin Herrenschmidt __be64 __iomem *invalidate = pnv_ioda_get_inval_reg(pe->phb, rm); 19674cce9550SGavin Shan unsigned long start, end, inc; 19684cce9550SGavin Shan 1969decbda25SAlexey Kardashevskiy start = __pa(((__be64 *)tbl->it_base) + index - tbl->it_offset); 1970decbda25SAlexey Kardashevskiy end = __pa(((__be64 *)tbl->it_base) + index - tbl->it_offset + 1971decbda25SAlexey Kardashevskiy npages - 1); 19724cce9550SGavin Shan 19734cce9550SGavin Shan /* p7ioc-style invalidation, 2 TCEs per write */ 19744cce9550SGavin Shan start |= (1ull << 63); 19754cce9550SGavin Shan end |= (1ull << 63); 19764cce9550SGavin Shan inc = 16; 19774cce9550SGavin Shan end |= inc - 1; /* round up end to be different than start */ 19784cce9550SGavin Shan 19794cce9550SGavin Shan mb(); /* Ensure above stores are visible */ 19804cce9550SGavin Shan while (start <= end) { 19818e0a1611SAlexey Kardashevskiy if (rm) 19823ad26e5cSBenjamin Herrenschmidt __raw_rm_writeq(cpu_to_be64(start), invalidate); 19838e0a1611SAlexey Kardashevskiy else 19843a1a4661SBenjamin Herrenschmidt __raw_writeq(cpu_to_be64(start), invalidate); 19854cce9550SGavin Shan start += inc; 19864cce9550SGavin Shan } 19874cce9550SGavin Shan 19884cce9550SGavin Shan /* 19894cce9550SGavin Shan * The iommu layer will do another mb() for us on build() 19904cce9550SGavin Shan * and we don't care on free() 19914cce9550SGavin Shan */ 19924cce9550SGavin Shan } 19934cce9550SGavin Shan 1994decbda25SAlexey Kardashevskiy static int pnv_ioda1_tce_build(struct iommu_table *tbl, long index, 1995decbda25SAlexey Kardashevskiy long npages, unsigned long uaddr, 1996decbda25SAlexey Kardashevskiy enum dma_data_direction direction, 199700085f1eSKrzysztof Kozlowski unsigned long attrs) 1998decbda25SAlexey Kardashevskiy { 1999decbda25SAlexey Kardashevskiy int ret = pnv_tce_build(tbl, index, npages, uaddr, direction, 2000decbda25SAlexey Kardashevskiy attrs); 2001decbda25SAlexey Kardashevskiy 200208acce1cSBenjamin Herrenschmidt if (!ret) 2003a34ab7c3SBenjamin Herrenschmidt pnv_pci_p7ioc_tce_invalidate(tbl, index, npages, false); 2004decbda25SAlexey Kardashevskiy 2005decbda25SAlexey Kardashevskiy return ret; 2006decbda25SAlexey Kardashevskiy } 2007decbda25SAlexey Kardashevskiy 200805c6cfb9SAlexey Kardashevskiy #ifdef CONFIG_IOMMU_API 200905c6cfb9SAlexey Kardashevskiy static int pnv_ioda1_tce_xchg(struct iommu_table *tbl, long index, 201005c6cfb9SAlexey Kardashevskiy unsigned long *hpa, enum dma_data_direction *direction) 201105c6cfb9SAlexey Kardashevskiy { 201205c6cfb9SAlexey Kardashevskiy long ret = pnv_tce_xchg(tbl, index, hpa, direction); 201305c6cfb9SAlexey Kardashevskiy 201408acce1cSBenjamin Herrenschmidt if (!ret) 2015a34ab7c3SBenjamin Herrenschmidt pnv_pci_p7ioc_tce_invalidate(tbl, index, 1, false); 201605c6cfb9SAlexey Kardashevskiy 201705c6cfb9SAlexey Kardashevskiy return ret; 201805c6cfb9SAlexey Kardashevskiy } 2019a540aa56SAlexey Kardashevskiy 2020a540aa56SAlexey Kardashevskiy static int pnv_ioda1_tce_xchg_rm(struct iommu_table *tbl, long index, 2021a540aa56SAlexey Kardashevskiy unsigned long *hpa, enum dma_data_direction *direction) 2022a540aa56SAlexey Kardashevskiy { 2023a540aa56SAlexey Kardashevskiy long ret = pnv_tce_xchg(tbl, index, hpa, direction); 2024a540aa56SAlexey Kardashevskiy 2025a540aa56SAlexey Kardashevskiy if (!ret) 2026a540aa56SAlexey Kardashevskiy pnv_pci_p7ioc_tce_invalidate(tbl, index, 1, true); 2027a540aa56SAlexey Kardashevskiy 2028a540aa56SAlexey Kardashevskiy return ret; 2029a540aa56SAlexey Kardashevskiy } 203005c6cfb9SAlexey Kardashevskiy #endif 203105c6cfb9SAlexey Kardashevskiy 2032decbda25SAlexey Kardashevskiy static void pnv_ioda1_tce_free(struct iommu_table *tbl, long index, 2033decbda25SAlexey Kardashevskiy long npages) 2034decbda25SAlexey Kardashevskiy { 2035decbda25SAlexey Kardashevskiy pnv_tce_free(tbl, index, npages); 2036decbda25SAlexey Kardashevskiy 2037a34ab7c3SBenjamin Herrenschmidt pnv_pci_p7ioc_tce_invalidate(tbl, index, npages, false); 2038decbda25SAlexey Kardashevskiy } 2039decbda25SAlexey Kardashevskiy 2040da004c36SAlexey Kardashevskiy static struct iommu_table_ops pnv_ioda1_iommu_ops = { 2041decbda25SAlexey Kardashevskiy .set = pnv_ioda1_tce_build, 204205c6cfb9SAlexey Kardashevskiy #ifdef CONFIG_IOMMU_API 204305c6cfb9SAlexey Kardashevskiy .exchange = pnv_ioda1_tce_xchg, 2044a540aa56SAlexey Kardashevskiy .exchange_rm = pnv_ioda1_tce_xchg_rm, 204505c6cfb9SAlexey Kardashevskiy #endif 2046decbda25SAlexey Kardashevskiy .clear = pnv_ioda1_tce_free, 2047da004c36SAlexey Kardashevskiy .get = pnv_tce_get, 2048da004c36SAlexey Kardashevskiy }; 2049da004c36SAlexey Kardashevskiy 2050a34ab7c3SBenjamin Herrenschmidt #define PHB3_TCE_KILL_INVAL_ALL PPC_BIT(0) 2051a34ab7c3SBenjamin Herrenschmidt #define PHB3_TCE_KILL_INVAL_PE PPC_BIT(1) 2052a34ab7c3SBenjamin Herrenschmidt #define PHB3_TCE_KILL_INVAL_ONE PPC_BIT(2) 2053bef9253fSAlexey Kardashevskiy 20546b3d12a9SAlistair Popple static void pnv_pci_phb3_tce_invalidate_entire(struct pnv_phb *phb, bool rm) 20550bbcdb43SAlexey Kardashevskiy { 2056fd141d1aSBenjamin Herrenschmidt __be64 __iomem *invalidate = pnv_ioda_get_inval_reg(phb, rm); 2057a34ab7c3SBenjamin Herrenschmidt const unsigned long val = PHB3_TCE_KILL_INVAL_ALL; 20580bbcdb43SAlexey Kardashevskiy 20590bbcdb43SAlexey Kardashevskiy mb(); /* Ensure previous TCE table stores are visible */ 20600bbcdb43SAlexey Kardashevskiy if (rm) 2061fd141d1aSBenjamin Herrenschmidt __raw_rm_writeq(cpu_to_be64(val), invalidate); 20620bbcdb43SAlexey Kardashevskiy else 2063fd141d1aSBenjamin Herrenschmidt __raw_writeq(cpu_to_be64(val), invalidate); 20640bbcdb43SAlexey Kardashevskiy } 20650bbcdb43SAlexey Kardashevskiy 2066a34ab7c3SBenjamin Herrenschmidt static inline void pnv_pci_phb3_tce_invalidate_pe(struct pnv_ioda_pe *pe) 20675780fb04SAlexey Kardashevskiy { 20685780fb04SAlexey Kardashevskiy /* 01xb - invalidate TCEs that match the specified PE# */ 2069fd141d1aSBenjamin Herrenschmidt __be64 __iomem *invalidate = pnv_ioda_get_inval_reg(pe->phb, false); 2070a34ab7c3SBenjamin Herrenschmidt unsigned long val = PHB3_TCE_KILL_INVAL_PE | (pe->pe_number & 0xFF); 20715780fb04SAlexey Kardashevskiy 20725780fb04SAlexey Kardashevskiy mb(); /* Ensure above stores are visible */ 2073fd141d1aSBenjamin Herrenschmidt __raw_writeq(cpu_to_be64(val), invalidate); 20745780fb04SAlexey Kardashevskiy } 20755780fb04SAlexey Kardashevskiy 2076fd141d1aSBenjamin Herrenschmidt static void pnv_pci_phb3_tce_invalidate(struct pnv_ioda_pe *pe, bool rm, 2077fd141d1aSBenjamin Herrenschmidt unsigned shift, unsigned long index, 2078fd141d1aSBenjamin Herrenschmidt unsigned long npages) 20794cce9550SGavin Shan { 20804d902195SAlexey Kardashevskiy __be64 __iomem *invalidate = pnv_ioda_get_inval_reg(pe->phb, rm); 20814cce9550SGavin Shan unsigned long start, end, inc; 20824cce9550SGavin Shan 20834cce9550SGavin Shan /* We'll invalidate DMA address in PE scope */ 2084a34ab7c3SBenjamin Herrenschmidt start = PHB3_TCE_KILL_INVAL_ONE; 2085fd141d1aSBenjamin Herrenschmidt start |= (pe->pe_number & 0xFF); 20864cce9550SGavin Shan end = start; 20874cce9550SGavin Shan 20884cce9550SGavin Shan /* Figure out the start, end and step */ 2089decbda25SAlexey Kardashevskiy start |= (index << shift); 2090decbda25SAlexey Kardashevskiy end |= ((index + npages - 1) << shift); 2091b0376c9bSAlexey Kardashevskiy inc = (0x1ull << shift); 20924cce9550SGavin Shan mb(); 20934cce9550SGavin Shan 20944cce9550SGavin Shan while (start <= end) { 20958e0a1611SAlexey Kardashevskiy if (rm) 20963ad26e5cSBenjamin Herrenschmidt __raw_rm_writeq(cpu_to_be64(start), invalidate); 20978e0a1611SAlexey Kardashevskiy else 20983a1a4661SBenjamin Herrenschmidt __raw_writeq(cpu_to_be64(start), invalidate); 20994cce9550SGavin Shan start += inc; 21004cce9550SGavin Shan } 21014cce9550SGavin Shan } 21024cce9550SGavin Shan 2103f0228c41SBenjamin Herrenschmidt static inline void pnv_pci_ioda2_tce_invalidate_pe(struct pnv_ioda_pe *pe) 2104f0228c41SBenjamin Herrenschmidt { 2105f0228c41SBenjamin Herrenschmidt struct pnv_phb *phb = pe->phb; 2106f0228c41SBenjamin Herrenschmidt 2107f0228c41SBenjamin Herrenschmidt if (phb->model == PNV_PHB_MODEL_PHB3 && phb->regs) 2108f0228c41SBenjamin Herrenschmidt pnv_pci_phb3_tce_invalidate_pe(pe); 2109f0228c41SBenjamin Herrenschmidt else 2110f0228c41SBenjamin Herrenschmidt opal_pci_tce_kill(phb->opal_id, OPAL_PCI_TCE_KILL_PE, 2111f0228c41SBenjamin Herrenschmidt pe->pe_number, 0, 0, 0); 2112f0228c41SBenjamin Herrenschmidt } 2113f0228c41SBenjamin Herrenschmidt 2114e57080f1SAlexey Kardashevskiy static void pnv_pci_ioda2_tce_invalidate(struct iommu_table *tbl, 2115e57080f1SAlexey Kardashevskiy unsigned long index, unsigned long npages, bool rm) 2116e57080f1SAlexey Kardashevskiy { 2117e57080f1SAlexey Kardashevskiy struct iommu_table_group_link *tgl; 2118e57080f1SAlexey Kardashevskiy 2119a540aa56SAlexey Kardashevskiy list_for_each_entry_lockless(tgl, &tbl->it_group_list, next) { 2120e57080f1SAlexey Kardashevskiy struct pnv_ioda_pe *pe = container_of(tgl->table_group, 2121e57080f1SAlexey Kardashevskiy struct pnv_ioda_pe, table_group); 2122f0228c41SBenjamin Herrenschmidt struct pnv_phb *phb = pe->phb; 2123f0228c41SBenjamin Herrenschmidt unsigned int shift = tbl->it_page_shift; 2124f0228c41SBenjamin Herrenschmidt 2125616badd2SAlistair Popple /* 2126616badd2SAlistair Popple * NVLink1 can use the TCE kill register directly as 2127616badd2SAlistair Popple * it's the same as PHB3. NVLink2 is different and 2128616badd2SAlistair Popple * should go via the OPAL call. 2129616badd2SAlistair Popple */ 2130616badd2SAlistair Popple if (phb->model == PNV_PHB_MODEL_NPU) { 21310bbcdb43SAlexey Kardashevskiy /* 21320bbcdb43SAlexey Kardashevskiy * The NVLink hardware does not support TCE kill 21330bbcdb43SAlexey Kardashevskiy * per TCE entry so we have to invalidate 21340bbcdb43SAlexey Kardashevskiy * the entire cache for it. 21350bbcdb43SAlexey Kardashevskiy */ 2136f0228c41SBenjamin Herrenschmidt pnv_pci_phb3_tce_invalidate_entire(phb, rm); 21375d2aa710SAlistair Popple continue; 21385d2aa710SAlistair Popple } 2139f0228c41SBenjamin Herrenschmidt if (phb->model == PNV_PHB_MODEL_PHB3 && phb->regs) 2140f0228c41SBenjamin Herrenschmidt pnv_pci_phb3_tce_invalidate(pe, rm, shift, 214185674868SAlexey Kardashevskiy index, npages); 2142f0228c41SBenjamin Herrenschmidt else 2143f0228c41SBenjamin Herrenschmidt opal_pci_tce_kill(phb->opal_id, 2144f0228c41SBenjamin Herrenschmidt OPAL_PCI_TCE_KILL_PAGES, 2145f0228c41SBenjamin Herrenschmidt pe->pe_number, 1u << shift, 2146f0228c41SBenjamin Herrenschmidt index << shift, npages); 2147e57080f1SAlexey Kardashevskiy } 2148e57080f1SAlexey Kardashevskiy } 2149e57080f1SAlexey Kardashevskiy 21506b3d12a9SAlistair Popple void pnv_pci_ioda2_tce_invalidate_entire(struct pnv_phb *phb, bool rm) 21516b3d12a9SAlistair Popple { 21526b3d12a9SAlistair Popple if (phb->model == PNV_PHB_MODEL_NPU || phb->model == PNV_PHB_MODEL_PHB3) 21536b3d12a9SAlistair Popple pnv_pci_phb3_tce_invalidate_entire(phb, rm); 21546b3d12a9SAlistair Popple else 21556b3d12a9SAlistair Popple opal_pci_tce_kill(phb->opal_id, OPAL_PCI_TCE_KILL, 0, 0, 0, 0); 21566b3d12a9SAlistair Popple } 21576b3d12a9SAlistair Popple 2158decbda25SAlexey Kardashevskiy static int pnv_ioda2_tce_build(struct iommu_table *tbl, long index, 2159decbda25SAlexey Kardashevskiy long npages, unsigned long uaddr, 2160decbda25SAlexey Kardashevskiy enum dma_data_direction direction, 216100085f1eSKrzysztof Kozlowski unsigned long attrs) 21624cce9550SGavin Shan { 2163decbda25SAlexey Kardashevskiy int ret = pnv_tce_build(tbl, index, npages, uaddr, direction, 2164decbda25SAlexey Kardashevskiy attrs); 21654cce9550SGavin Shan 216608acce1cSBenjamin Herrenschmidt if (!ret) 2167decbda25SAlexey Kardashevskiy pnv_pci_ioda2_tce_invalidate(tbl, index, npages, false); 2168decbda25SAlexey Kardashevskiy 2169decbda25SAlexey Kardashevskiy return ret; 2170decbda25SAlexey Kardashevskiy } 2171decbda25SAlexey Kardashevskiy 217205c6cfb9SAlexey Kardashevskiy #ifdef CONFIG_IOMMU_API 217305c6cfb9SAlexey Kardashevskiy static int pnv_ioda2_tce_xchg(struct iommu_table *tbl, long index, 217405c6cfb9SAlexey Kardashevskiy unsigned long *hpa, enum dma_data_direction *direction) 217505c6cfb9SAlexey Kardashevskiy { 217605c6cfb9SAlexey Kardashevskiy long ret = pnv_tce_xchg(tbl, index, hpa, direction); 217705c6cfb9SAlexey Kardashevskiy 217808acce1cSBenjamin Herrenschmidt if (!ret) 217905c6cfb9SAlexey Kardashevskiy pnv_pci_ioda2_tce_invalidate(tbl, index, 1, false); 218005c6cfb9SAlexey Kardashevskiy 218105c6cfb9SAlexey Kardashevskiy return ret; 218205c6cfb9SAlexey Kardashevskiy } 2183a540aa56SAlexey Kardashevskiy 2184a540aa56SAlexey Kardashevskiy static int pnv_ioda2_tce_xchg_rm(struct iommu_table *tbl, long index, 2185a540aa56SAlexey Kardashevskiy unsigned long *hpa, enum dma_data_direction *direction) 2186a540aa56SAlexey Kardashevskiy { 2187a540aa56SAlexey Kardashevskiy long ret = pnv_tce_xchg(tbl, index, hpa, direction); 2188a540aa56SAlexey Kardashevskiy 2189a540aa56SAlexey Kardashevskiy if (!ret) 2190a540aa56SAlexey Kardashevskiy pnv_pci_ioda2_tce_invalidate(tbl, index, 1, true); 2191a540aa56SAlexey Kardashevskiy 2192a540aa56SAlexey Kardashevskiy return ret; 2193a540aa56SAlexey Kardashevskiy } 219405c6cfb9SAlexey Kardashevskiy #endif 219505c6cfb9SAlexey Kardashevskiy 2196decbda25SAlexey Kardashevskiy static void pnv_ioda2_tce_free(struct iommu_table *tbl, long index, 2197decbda25SAlexey Kardashevskiy long npages) 2198decbda25SAlexey Kardashevskiy { 2199decbda25SAlexey Kardashevskiy pnv_tce_free(tbl, index, npages); 2200decbda25SAlexey Kardashevskiy 2201decbda25SAlexey Kardashevskiy pnv_pci_ioda2_tce_invalidate(tbl, index, npages, false); 22024cce9550SGavin Shan } 22034cce9550SGavin Shan 22044793d65dSAlexey Kardashevskiy static void pnv_ioda2_table_free(struct iommu_table *tbl) 22054793d65dSAlexey Kardashevskiy { 22064793d65dSAlexey Kardashevskiy pnv_pci_ioda2_table_free_pages(tbl); 22074793d65dSAlexey Kardashevskiy } 22084793d65dSAlexey Kardashevskiy 2209da004c36SAlexey Kardashevskiy static struct iommu_table_ops pnv_ioda2_iommu_ops = { 2210decbda25SAlexey Kardashevskiy .set = pnv_ioda2_tce_build, 221105c6cfb9SAlexey Kardashevskiy #ifdef CONFIG_IOMMU_API 221205c6cfb9SAlexey Kardashevskiy .exchange = pnv_ioda2_tce_xchg, 2213a540aa56SAlexey Kardashevskiy .exchange_rm = pnv_ioda2_tce_xchg_rm, 221405c6cfb9SAlexey Kardashevskiy #endif 2215decbda25SAlexey Kardashevskiy .clear = pnv_ioda2_tce_free, 2216da004c36SAlexey Kardashevskiy .get = pnv_tce_get, 22174793d65dSAlexey Kardashevskiy .free = pnv_ioda2_table_free, 2218da004c36SAlexey Kardashevskiy }; 2219da004c36SAlexey Kardashevskiy 2220801846d1SGavin Shan static int pnv_pci_ioda_dev_dma_weight(struct pci_dev *dev, void *data) 2221801846d1SGavin Shan { 2222801846d1SGavin Shan unsigned int *weight = (unsigned int *)data; 2223801846d1SGavin Shan 2224801846d1SGavin Shan /* This is quite simplistic. The "base" weight of a device 2225801846d1SGavin Shan * is 10. 0 means no DMA is to be accounted for it. 2226801846d1SGavin Shan */ 2227801846d1SGavin Shan if (dev->hdr_type != PCI_HEADER_TYPE_NORMAL) 2228801846d1SGavin Shan return 0; 2229801846d1SGavin Shan 2230801846d1SGavin Shan if (dev->class == PCI_CLASS_SERIAL_USB_UHCI || 2231801846d1SGavin Shan dev->class == PCI_CLASS_SERIAL_USB_OHCI || 2232801846d1SGavin Shan dev->class == PCI_CLASS_SERIAL_USB_EHCI) 2233801846d1SGavin Shan *weight += 3; 2234801846d1SGavin Shan else if ((dev->class >> 8) == PCI_CLASS_STORAGE_RAID) 2235801846d1SGavin Shan *weight += 15; 2236801846d1SGavin Shan else 2237801846d1SGavin Shan *weight += 10; 2238801846d1SGavin Shan 2239801846d1SGavin Shan return 0; 2240801846d1SGavin Shan } 2241801846d1SGavin Shan 2242801846d1SGavin Shan static unsigned int pnv_pci_ioda_pe_dma_weight(struct pnv_ioda_pe *pe) 2243801846d1SGavin Shan { 2244801846d1SGavin Shan unsigned int weight = 0; 2245801846d1SGavin Shan 2246801846d1SGavin Shan /* SRIOV VF has same DMA32 weight as its PF */ 2247801846d1SGavin Shan #ifdef CONFIG_PCI_IOV 2248801846d1SGavin Shan if ((pe->flags & PNV_IODA_PE_VF) && pe->parent_dev) { 2249801846d1SGavin Shan pnv_pci_ioda_dev_dma_weight(pe->parent_dev, &weight); 2250801846d1SGavin Shan return weight; 2251801846d1SGavin Shan } 2252801846d1SGavin Shan #endif 2253801846d1SGavin Shan 2254801846d1SGavin Shan if ((pe->flags & PNV_IODA_PE_DEV) && pe->pdev) { 2255801846d1SGavin Shan pnv_pci_ioda_dev_dma_weight(pe->pdev, &weight); 2256801846d1SGavin Shan } else if ((pe->flags & PNV_IODA_PE_BUS) && pe->pbus) { 2257801846d1SGavin Shan struct pci_dev *pdev; 2258801846d1SGavin Shan 2259801846d1SGavin Shan list_for_each_entry(pdev, &pe->pbus->devices, bus_list) 2260801846d1SGavin Shan pnv_pci_ioda_dev_dma_weight(pdev, &weight); 2261801846d1SGavin Shan } else if ((pe->flags & PNV_IODA_PE_BUS_ALL) && pe->pbus) { 2262801846d1SGavin Shan pci_walk_bus(pe->pbus, pnv_pci_ioda_dev_dma_weight, &weight); 2263801846d1SGavin Shan } 2264801846d1SGavin Shan 2265801846d1SGavin Shan return weight; 2266801846d1SGavin Shan } 2267801846d1SGavin Shan 2268b30d936fSGavin Shan static void pnv_pci_ioda1_setup_dma_pe(struct pnv_phb *phb, 22692b923ed1SGavin Shan struct pnv_ioda_pe *pe) 2270184cd4a3SBenjamin Herrenschmidt { 2271184cd4a3SBenjamin Herrenschmidt 2272184cd4a3SBenjamin Herrenschmidt struct page *tce_mem = NULL; 2273184cd4a3SBenjamin Herrenschmidt struct iommu_table *tbl; 22742b923ed1SGavin Shan unsigned int weight, total_weight = 0; 22752b923ed1SGavin Shan unsigned int tce32_segsz, base, segs, avail, i; 2276184cd4a3SBenjamin Herrenschmidt int64_t rc; 2277184cd4a3SBenjamin Herrenschmidt void *addr; 2278184cd4a3SBenjamin Herrenschmidt 2279184cd4a3SBenjamin Herrenschmidt /* XXX FIXME: Handle 64-bit only DMA devices */ 2280184cd4a3SBenjamin Herrenschmidt /* XXX FIXME: Provide 64-bit DMA facilities & non-4K TCE tables etc.. */ 2281184cd4a3SBenjamin Herrenschmidt /* XXX FIXME: Allocate multi-level tables on PHB3 */ 22822b923ed1SGavin Shan weight = pnv_pci_ioda_pe_dma_weight(pe); 22832b923ed1SGavin Shan if (!weight) 22842b923ed1SGavin Shan return; 2285184cd4a3SBenjamin Herrenschmidt 22862b923ed1SGavin Shan pci_walk_bus(phb->hose->bus, pnv_pci_ioda_dev_dma_weight, 22872b923ed1SGavin Shan &total_weight); 22882b923ed1SGavin Shan segs = (weight * phb->ioda.dma32_count) / total_weight; 22892b923ed1SGavin Shan if (!segs) 22902b923ed1SGavin Shan segs = 1; 22912b923ed1SGavin Shan 22922b923ed1SGavin Shan /* 22932b923ed1SGavin Shan * Allocate contiguous DMA32 segments. We begin with the expected 22942b923ed1SGavin Shan * number of segments. With one more attempt, the number of DMA32 22952b923ed1SGavin Shan * segments to be allocated is decreased by one until one segment 22962b923ed1SGavin Shan * is allocated successfully. 22972b923ed1SGavin Shan */ 22982b923ed1SGavin Shan do { 22992b923ed1SGavin Shan for (base = 0; base <= phb->ioda.dma32_count - segs; base++) { 23002b923ed1SGavin Shan for (avail = 0, i = base; i < base + segs; i++) { 23012b923ed1SGavin Shan if (phb->ioda.dma32_segmap[i] == 23022b923ed1SGavin Shan IODA_INVALID_PE) 23032b923ed1SGavin Shan avail++; 23042b923ed1SGavin Shan } 23052b923ed1SGavin Shan 23062b923ed1SGavin Shan if (avail == segs) 23072b923ed1SGavin Shan goto found; 23082b923ed1SGavin Shan } 23092b923ed1SGavin Shan } while (--segs); 23102b923ed1SGavin Shan 23112b923ed1SGavin Shan if (!segs) { 23122b923ed1SGavin Shan pe_warn(pe, "No available DMA32 segments\n"); 23132b923ed1SGavin Shan return; 23142b923ed1SGavin Shan } 23152b923ed1SGavin Shan 23162b923ed1SGavin Shan found: 23170eaf4defSAlexey Kardashevskiy tbl = pnv_pci_table_alloc(phb->hose->node); 231882eae1afSAlexey Kardashevskiy if (WARN_ON(!tbl)) 231982eae1afSAlexey Kardashevskiy return; 232082eae1afSAlexey Kardashevskiy 2321b348aa65SAlexey Kardashevskiy iommu_register_group(&pe->table_group, phb->hose->global_number, 2322b348aa65SAlexey Kardashevskiy pe->pe_number); 23230eaf4defSAlexey Kardashevskiy pnv_pci_link_table_and_group(phb->hose->node, 0, tbl, &pe->table_group); 2324c5773822SAlexey Kardashevskiy 2325184cd4a3SBenjamin Herrenschmidt /* Grab a 32-bit TCE table */ 23262b923ed1SGavin Shan pe_info(pe, "DMA weight %d (%d), assigned (%d) %d DMA32 segments\n", 23272b923ed1SGavin Shan weight, total_weight, base, segs); 2328184cd4a3SBenjamin Herrenschmidt pe_info(pe, " Setting up 32-bit TCE table at %08x..%08x\n", 2329acce971cSGavin Shan base * PNV_IODA1_DMA32_SEGSIZE, 2330acce971cSGavin Shan (base + segs) * PNV_IODA1_DMA32_SEGSIZE - 1); 2331184cd4a3SBenjamin Herrenschmidt 2332184cd4a3SBenjamin Herrenschmidt /* XXX Currently, we allocate one big contiguous table for the 2333184cd4a3SBenjamin Herrenschmidt * TCEs. We only really need one chunk per 256M of TCE space 2334184cd4a3SBenjamin Herrenschmidt * (ie per segment) but that's an optimization for later, it 2335184cd4a3SBenjamin Herrenschmidt * requires some added smarts with our get/put_tce implementation 2336acce971cSGavin Shan * 2337acce971cSGavin Shan * Each TCE page is 4KB in size and each TCE entry occupies 8 2338acce971cSGavin Shan * bytes 2339184cd4a3SBenjamin Herrenschmidt */ 2340acce971cSGavin Shan tce32_segsz = PNV_IODA1_DMA32_SEGSIZE >> (IOMMU_PAGE_SHIFT_4K - 3); 2341184cd4a3SBenjamin Herrenschmidt tce_mem = alloc_pages_node(phb->hose->node, GFP_KERNEL, 2342acce971cSGavin Shan get_order(tce32_segsz * segs)); 2343184cd4a3SBenjamin Herrenschmidt if (!tce_mem) { 2344184cd4a3SBenjamin Herrenschmidt pe_err(pe, " Failed to allocate a 32-bit TCE memory\n"); 2345184cd4a3SBenjamin Herrenschmidt goto fail; 2346184cd4a3SBenjamin Herrenschmidt } 2347184cd4a3SBenjamin Herrenschmidt addr = page_address(tce_mem); 2348acce971cSGavin Shan memset(addr, 0, tce32_segsz * segs); 2349184cd4a3SBenjamin Herrenschmidt 2350184cd4a3SBenjamin Herrenschmidt /* Configure HW */ 2351184cd4a3SBenjamin Herrenschmidt for (i = 0; i < segs; i++) { 2352184cd4a3SBenjamin Herrenschmidt rc = opal_pci_map_pe_dma_window(phb->opal_id, 2353184cd4a3SBenjamin Herrenschmidt pe->pe_number, 2354184cd4a3SBenjamin Herrenschmidt base + i, 1, 2355acce971cSGavin Shan __pa(addr) + tce32_segsz * i, 2356acce971cSGavin Shan tce32_segsz, IOMMU_PAGE_SIZE_4K); 2357184cd4a3SBenjamin Herrenschmidt if (rc) { 2358184cd4a3SBenjamin Herrenschmidt pe_err(pe, " Failed to configure 32-bit TCE table," 2359184cd4a3SBenjamin Herrenschmidt " err %ld\n", rc); 2360184cd4a3SBenjamin Herrenschmidt goto fail; 2361184cd4a3SBenjamin Herrenschmidt } 2362184cd4a3SBenjamin Herrenschmidt } 2363184cd4a3SBenjamin Herrenschmidt 23642b923ed1SGavin Shan /* Setup DMA32 segment mapping */ 23652b923ed1SGavin Shan for (i = base; i < base + segs; i++) 23662b923ed1SGavin Shan phb->ioda.dma32_segmap[i] = pe->pe_number; 23672b923ed1SGavin Shan 2368184cd4a3SBenjamin Herrenschmidt /* Setup linux iommu table */ 2369acce971cSGavin Shan pnv_pci_setup_iommu_table(tbl, addr, tce32_segsz * segs, 2370acce971cSGavin Shan base * PNV_IODA1_DMA32_SEGSIZE, 2371acce971cSGavin Shan IOMMU_PAGE_SHIFT_4K); 2372184cd4a3SBenjamin Herrenschmidt 2373da004c36SAlexey Kardashevskiy tbl->it_ops = &pnv_ioda1_iommu_ops; 23744793d65dSAlexey Kardashevskiy pe->table_group.tce32_start = tbl->it_offset << tbl->it_page_shift; 23754793d65dSAlexey Kardashevskiy pe->table_group.tce32_size = tbl->it_size << tbl->it_page_shift; 2376184cd4a3SBenjamin Herrenschmidt iommu_init_table(tbl, phb->hose->node); 2377184cd4a3SBenjamin Herrenschmidt 2378781a868fSWei Yang if (pe->flags & PNV_IODA_PE_DEV) { 23794617082eSAlexey Kardashevskiy /* 23804617082eSAlexey Kardashevskiy * Setting table base here only for carrying iommu_group 23814617082eSAlexey Kardashevskiy * further down to let iommu_add_device() do the job. 23824617082eSAlexey Kardashevskiy * pnv_pci_ioda_dma_dev_setup will override it later anyway. 23834617082eSAlexey Kardashevskiy */ 23844617082eSAlexey Kardashevskiy set_iommu_table_base(&pe->pdev->dev, tbl); 23854617082eSAlexey Kardashevskiy iommu_add_device(&pe->pdev->dev); 2386c5773822SAlexey Kardashevskiy } else if (pe->flags & (PNV_IODA_PE_BUS | PNV_IODA_PE_BUS_ALL)) 2387db08e1d5SAlexey Kardashevskiy pnv_ioda_setup_bus_dma(pe, pe->pbus, true); 238874251fe2SBenjamin Herrenschmidt 2389184cd4a3SBenjamin Herrenschmidt return; 2390184cd4a3SBenjamin Herrenschmidt fail: 2391184cd4a3SBenjamin Herrenschmidt /* XXX Failure: Try to fallback to 64-bit only ? */ 2392184cd4a3SBenjamin Herrenschmidt if (tce_mem) 2393acce971cSGavin Shan __free_pages(tce_mem, get_order(tce32_segsz * segs)); 23940eaf4defSAlexey Kardashevskiy if (tbl) { 23950eaf4defSAlexey Kardashevskiy pnv_pci_unlink_table_and_group(tbl, &pe->table_group); 2396e5afdf9dSAlexey Kardashevskiy iommu_tce_table_put(tbl); 23970eaf4defSAlexey Kardashevskiy } 2398184cd4a3SBenjamin Herrenschmidt } 2399184cd4a3SBenjamin Herrenschmidt 240043cb60abSAlexey Kardashevskiy static long pnv_pci_ioda2_set_window(struct iommu_table_group *table_group, 240143cb60abSAlexey Kardashevskiy int num, struct iommu_table *tbl) 240243cb60abSAlexey Kardashevskiy { 240343cb60abSAlexey Kardashevskiy struct pnv_ioda_pe *pe = container_of(table_group, struct pnv_ioda_pe, 240443cb60abSAlexey Kardashevskiy table_group); 240543cb60abSAlexey Kardashevskiy struct pnv_phb *phb = pe->phb; 240643cb60abSAlexey Kardashevskiy int64_t rc; 2407bbb845c4SAlexey Kardashevskiy const unsigned long size = tbl->it_indirect_levels ? 2408bbb845c4SAlexey Kardashevskiy tbl->it_level_size : tbl->it_size; 240943cb60abSAlexey Kardashevskiy const __u64 start_addr = tbl->it_offset << tbl->it_page_shift; 241043cb60abSAlexey Kardashevskiy const __u64 win_size = tbl->it_size << tbl->it_page_shift; 241143cb60abSAlexey Kardashevskiy 24124793d65dSAlexey Kardashevskiy pe_info(pe, "Setting up window#%d %llx..%llx pg=%x\n", num, 241343cb60abSAlexey Kardashevskiy start_addr, start_addr + win_size - 1, 241443cb60abSAlexey Kardashevskiy IOMMU_PAGE_SIZE(tbl)); 241543cb60abSAlexey Kardashevskiy 241643cb60abSAlexey Kardashevskiy /* 241743cb60abSAlexey Kardashevskiy * Map TCE table through TVT. The TVE index is the PE number 241843cb60abSAlexey Kardashevskiy * shifted by 1 bit for 32-bits DMA space. 241943cb60abSAlexey Kardashevskiy */ 242043cb60abSAlexey Kardashevskiy rc = opal_pci_map_pe_dma_window(phb->opal_id, 242143cb60abSAlexey Kardashevskiy pe->pe_number, 24224793d65dSAlexey Kardashevskiy (pe->pe_number << 1) + num, 2423bbb845c4SAlexey Kardashevskiy tbl->it_indirect_levels + 1, 242443cb60abSAlexey Kardashevskiy __pa(tbl->it_base), 2425bbb845c4SAlexey Kardashevskiy size << 3, 242643cb60abSAlexey Kardashevskiy IOMMU_PAGE_SIZE(tbl)); 242743cb60abSAlexey Kardashevskiy if (rc) { 242843cb60abSAlexey Kardashevskiy pe_err(pe, "Failed to configure TCE table, err %ld\n", rc); 242943cb60abSAlexey Kardashevskiy return rc; 243043cb60abSAlexey Kardashevskiy } 243143cb60abSAlexey Kardashevskiy 243243cb60abSAlexey Kardashevskiy pnv_pci_link_table_and_group(phb->hose->node, num, 243343cb60abSAlexey Kardashevskiy tbl, &pe->table_group); 2434ed7d9a1dSMichael Ellerman pnv_pci_ioda2_tce_invalidate_pe(pe); 243543cb60abSAlexey Kardashevskiy 243643cb60abSAlexey Kardashevskiy return 0; 243743cb60abSAlexey Kardashevskiy } 243843cb60abSAlexey Kardashevskiy 243925529100SFrederic Barrat void pnv_pci_ioda2_set_bypass(struct pnv_ioda_pe *pe, bool enable) 2440cd15b048SBenjamin Herrenschmidt { 2441cd15b048SBenjamin Herrenschmidt uint16_t window_id = (pe->pe_number << 1 ) + 1; 2442cd15b048SBenjamin Herrenschmidt int64_t rc; 2443cd15b048SBenjamin Herrenschmidt 2444cd15b048SBenjamin Herrenschmidt pe_info(pe, "%sabling 64-bit DMA bypass\n", enable ? "En" : "Dis"); 2445cd15b048SBenjamin Herrenschmidt if (enable) { 2446cd15b048SBenjamin Herrenschmidt phys_addr_t top = memblock_end_of_DRAM(); 2447cd15b048SBenjamin Herrenschmidt 2448cd15b048SBenjamin Herrenschmidt top = roundup_pow_of_two(top); 2449cd15b048SBenjamin Herrenschmidt rc = opal_pci_map_pe_dma_window_real(pe->phb->opal_id, 2450cd15b048SBenjamin Herrenschmidt pe->pe_number, 2451cd15b048SBenjamin Herrenschmidt window_id, 2452cd15b048SBenjamin Herrenschmidt pe->tce_bypass_base, 2453cd15b048SBenjamin Herrenschmidt top); 2454cd15b048SBenjamin Herrenschmidt } else { 2455cd15b048SBenjamin Herrenschmidt rc = opal_pci_map_pe_dma_window_real(pe->phb->opal_id, 2456cd15b048SBenjamin Herrenschmidt pe->pe_number, 2457cd15b048SBenjamin Herrenschmidt window_id, 2458cd15b048SBenjamin Herrenschmidt pe->tce_bypass_base, 2459cd15b048SBenjamin Herrenschmidt 0); 2460cd15b048SBenjamin Herrenschmidt } 2461cd15b048SBenjamin Herrenschmidt if (rc) 2462cd15b048SBenjamin Herrenschmidt pe_err(pe, "OPAL error %lld configuring bypass window\n", rc); 2463cd15b048SBenjamin Herrenschmidt else 2464cd15b048SBenjamin Herrenschmidt pe->tce_bypass_enabled = enable; 2465cd15b048SBenjamin Herrenschmidt } 2466cd15b048SBenjamin Herrenschmidt 24674793d65dSAlexey Kardashevskiy static long pnv_pci_ioda2_table_alloc_pages(int nid, __u64 bus_offset, 24684793d65dSAlexey Kardashevskiy __u32 page_shift, __u64 window_size, __u32 levels, 24694793d65dSAlexey Kardashevskiy struct iommu_table *tbl); 24704793d65dSAlexey Kardashevskiy 24714793d65dSAlexey Kardashevskiy static long pnv_pci_ioda2_create_table(struct iommu_table_group *table_group, 24724793d65dSAlexey Kardashevskiy int num, __u32 page_shift, __u64 window_size, __u32 levels, 24734793d65dSAlexey Kardashevskiy struct iommu_table **ptbl) 24744793d65dSAlexey Kardashevskiy { 24754793d65dSAlexey Kardashevskiy struct pnv_ioda_pe *pe = container_of(table_group, struct pnv_ioda_pe, 24764793d65dSAlexey Kardashevskiy table_group); 24774793d65dSAlexey Kardashevskiy int nid = pe->phb->hose->node; 24784793d65dSAlexey Kardashevskiy __u64 bus_offset = num ? pe->tce_bypass_base : table_group->tce32_start; 24794793d65dSAlexey Kardashevskiy long ret; 24804793d65dSAlexey Kardashevskiy struct iommu_table *tbl; 24814793d65dSAlexey Kardashevskiy 24824793d65dSAlexey Kardashevskiy tbl = pnv_pci_table_alloc(nid); 24834793d65dSAlexey Kardashevskiy if (!tbl) 24844793d65dSAlexey Kardashevskiy return -ENOMEM; 24854793d65dSAlexey Kardashevskiy 248611edf116SAlexey Kardashevskiy tbl->it_ops = &pnv_ioda2_iommu_ops; 248711edf116SAlexey Kardashevskiy 24884793d65dSAlexey Kardashevskiy ret = pnv_pci_ioda2_table_alloc_pages(nid, 24894793d65dSAlexey Kardashevskiy bus_offset, page_shift, window_size, 24904793d65dSAlexey Kardashevskiy levels, tbl); 24914793d65dSAlexey Kardashevskiy if (ret) { 2492e5afdf9dSAlexey Kardashevskiy iommu_tce_table_put(tbl); 24934793d65dSAlexey Kardashevskiy return ret; 24944793d65dSAlexey Kardashevskiy } 24954793d65dSAlexey Kardashevskiy 24964793d65dSAlexey Kardashevskiy *ptbl = tbl; 24974793d65dSAlexey Kardashevskiy 24984793d65dSAlexey Kardashevskiy return 0; 24994793d65dSAlexey Kardashevskiy } 25004793d65dSAlexey Kardashevskiy 250146d3e1e1SAlexey Kardashevskiy static long pnv_pci_ioda2_setup_default_config(struct pnv_ioda_pe *pe) 250246d3e1e1SAlexey Kardashevskiy { 250346d3e1e1SAlexey Kardashevskiy struct iommu_table *tbl = NULL; 250446d3e1e1SAlexey Kardashevskiy long rc; 250546d3e1e1SAlexey Kardashevskiy 2506bb005455SNishanth Aravamudan /* 2507fa144869SNishanth Aravamudan * crashkernel= specifies the kdump kernel's maximum memory at 2508fa144869SNishanth Aravamudan * some offset and there is no guaranteed the result is a power 2509fa144869SNishanth Aravamudan * of 2, which will cause errors later. 2510fa144869SNishanth Aravamudan */ 2511fa144869SNishanth Aravamudan const u64 max_memory = __rounddown_pow_of_two(memory_hotplug_max()); 2512fa144869SNishanth Aravamudan 2513fa144869SNishanth Aravamudan /* 2514bb005455SNishanth Aravamudan * In memory constrained environments, e.g. kdump kernel, the 2515bb005455SNishanth Aravamudan * DMA window can be larger than available memory, which will 2516bb005455SNishanth Aravamudan * cause errors later. 2517bb005455SNishanth Aravamudan */ 2518fa144869SNishanth Aravamudan const u64 window_size = min((u64)pe->table_group.tce32_size, max_memory); 2519bb005455SNishanth Aravamudan 252046d3e1e1SAlexey Kardashevskiy rc = pnv_pci_ioda2_create_table(&pe->table_group, 0, 252146d3e1e1SAlexey Kardashevskiy IOMMU_PAGE_SHIFT_4K, 2522bb005455SNishanth Aravamudan window_size, 252346d3e1e1SAlexey Kardashevskiy POWERNV_IOMMU_DEFAULT_LEVELS, &tbl); 252446d3e1e1SAlexey Kardashevskiy if (rc) { 252546d3e1e1SAlexey Kardashevskiy pe_err(pe, "Failed to create 32-bit TCE table, err %ld", 252646d3e1e1SAlexey Kardashevskiy rc); 252746d3e1e1SAlexey Kardashevskiy return rc; 252846d3e1e1SAlexey Kardashevskiy } 252946d3e1e1SAlexey Kardashevskiy 253046d3e1e1SAlexey Kardashevskiy iommu_init_table(tbl, pe->phb->hose->node); 253146d3e1e1SAlexey Kardashevskiy 253246d3e1e1SAlexey Kardashevskiy rc = pnv_pci_ioda2_set_window(&pe->table_group, 0, tbl); 253346d3e1e1SAlexey Kardashevskiy if (rc) { 253446d3e1e1SAlexey Kardashevskiy pe_err(pe, "Failed to configure 32-bit TCE table, err %ld\n", 253546d3e1e1SAlexey Kardashevskiy rc); 2536e5afdf9dSAlexey Kardashevskiy iommu_tce_table_put(tbl); 253746d3e1e1SAlexey Kardashevskiy return rc; 253846d3e1e1SAlexey Kardashevskiy } 253946d3e1e1SAlexey Kardashevskiy 254046d3e1e1SAlexey Kardashevskiy if (!pnv_iommu_bypass_disabled) 254146d3e1e1SAlexey Kardashevskiy pnv_pci_ioda2_set_bypass(pe, true); 254246d3e1e1SAlexey Kardashevskiy 254346d3e1e1SAlexey Kardashevskiy /* 254446d3e1e1SAlexey Kardashevskiy * Setting table base here only for carrying iommu_group 254546d3e1e1SAlexey Kardashevskiy * further down to let iommu_add_device() do the job. 254646d3e1e1SAlexey Kardashevskiy * pnv_pci_ioda_dma_dev_setup will override it later anyway. 254746d3e1e1SAlexey Kardashevskiy */ 254846d3e1e1SAlexey Kardashevskiy if (pe->flags & PNV_IODA_PE_DEV) 254946d3e1e1SAlexey Kardashevskiy set_iommu_table_base(&pe->pdev->dev, tbl); 255046d3e1e1SAlexey Kardashevskiy 255146d3e1e1SAlexey Kardashevskiy return 0; 255246d3e1e1SAlexey Kardashevskiy } 255346d3e1e1SAlexey Kardashevskiy 2554b5926430SAlexey Kardashevskiy #if defined(CONFIG_IOMMU_API) || defined(CONFIG_PCI_IOV) 2555b5926430SAlexey Kardashevskiy static long pnv_pci_ioda2_unset_window(struct iommu_table_group *table_group, 2556b5926430SAlexey Kardashevskiy int num) 2557b5926430SAlexey Kardashevskiy { 2558b5926430SAlexey Kardashevskiy struct pnv_ioda_pe *pe = container_of(table_group, struct pnv_ioda_pe, 2559b5926430SAlexey Kardashevskiy table_group); 2560b5926430SAlexey Kardashevskiy struct pnv_phb *phb = pe->phb; 2561b5926430SAlexey Kardashevskiy long ret; 2562b5926430SAlexey Kardashevskiy 2563b5926430SAlexey Kardashevskiy pe_info(pe, "Removing DMA window #%d\n", num); 2564b5926430SAlexey Kardashevskiy 2565b5926430SAlexey Kardashevskiy ret = opal_pci_map_pe_dma_window(phb->opal_id, pe->pe_number, 2566b5926430SAlexey Kardashevskiy (pe->pe_number << 1) + num, 2567b5926430SAlexey Kardashevskiy 0/* levels */, 0/* table address */, 2568b5926430SAlexey Kardashevskiy 0/* table size */, 0/* page size */); 2569b5926430SAlexey Kardashevskiy if (ret) 2570b5926430SAlexey Kardashevskiy pe_warn(pe, "Unmapping failed, ret = %ld\n", ret); 2571b5926430SAlexey Kardashevskiy else 2572ed7d9a1dSMichael Ellerman pnv_pci_ioda2_tce_invalidate_pe(pe); 2573b5926430SAlexey Kardashevskiy 2574b5926430SAlexey Kardashevskiy pnv_pci_unlink_table_and_group(table_group->tables[num], table_group); 2575b5926430SAlexey Kardashevskiy 2576b5926430SAlexey Kardashevskiy return ret; 2577b5926430SAlexey Kardashevskiy } 2578b5926430SAlexey Kardashevskiy #endif 2579b5926430SAlexey Kardashevskiy 2580f87a8864SAlexey Kardashevskiy #ifdef CONFIG_IOMMU_API 258100547193SAlexey Kardashevskiy static unsigned long pnv_pci_ioda2_get_table_size(__u32 page_shift, 258200547193SAlexey Kardashevskiy __u64 window_size, __u32 levels) 258300547193SAlexey Kardashevskiy { 258400547193SAlexey Kardashevskiy unsigned long bytes = 0; 258500547193SAlexey Kardashevskiy const unsigned window_shift = ilog2(window_size); 258600547193SAlexey Kardashevskiy unsigned entries_shift = window_shift - page_shift; 258700547193SAlexey Kardashevskiy unsigned table_shift = entries_shift + 3; 258800547193SAlexey Kardashevskiy unsigned long tce_table_size = max(0x1000UL, 1UL << table_shift); 258900547193SAlexey Kardashevskiy unsigned long direct_table_size; 259000547193SAlexey Kardashevskiy 259100547193SAlexey Kardashevskiy if (!levels || (levels > POWERNV_IOMMU_MAX_LEVELS) || 259200547193SAlexey Kardashevskiy !is_power_of_2(window_size)) 259300547193SAlexey Kardashevskiy return 0; 259400547193SAlexey Kardashevskiy 259500547193SAlexey Kardashevskiy /* Calculate a direct table size from window_size and levels */ 259600547193SAlexey Kardashevskiy entries_shift = (entries_shift + levels - 1) / levels; 259700547193SAlexey Kardashevskiy table_shift = entries_shift + 3; 259800547193SAlexey Kardashevskiy table_shift = max_t(unsigned, table_shift, PAGE_SHIFT); 259900547193SAlexey Kardashevskiy direct_table_size = 1UL << table_shift; 260000547193SAlexey Kardashevskiy 260100547193SAlexey Kardashevskiy for ( ; levels; --levels) { 260200547193SAlexey Kardashevskiy bytes += _ALIGN_UP(tce_table_size, direct_table_size); 260300547193SAlexey Kardashevskiy 260400547193SAlexey Kardashevskiy tce_table_size /= direct_table_size; 260500547193SAlexey Kardashevskiy tce_table_size <<= 3; 2606e49a6a21SAlexey Kardashevskiy tce_table_size = max_t(unsigned long, 2607e49a6a21SAlexey Kardashevskiy tce_table_size, direct_table_size); 260800547193SAlexey Kardashevskiy } 260900547193SAlexey Kardashevskiy 261000547193SAlexey Kardashevskiy return bytes; 261100547193SAlexey Kardashevskiy } 261200547193SAlexey Kardashevskiy 2613f87a8864SAlexey Kardashevskiy static void pnv_ioda2_take_ownership(struct iommu_table_group *table_group) 2614cd15b048SBenjamin Herrenschmidt { 2615f87a8864SAlexey Kardashevskiy struct pnv_ioda_pe *pe = container_of(table_group, struct pnv_ioda_pe, 2616f87a8864SAlexey Kardashevskiy table_group); 261746d3e1e1SAlexey Kardashevskiy /* Store @tbl as pnv_pci_ioda2_unset_window() resets it */ 261846d3e1e1SAlexey Kardashevskiy struct iommu_table *tbl = pe->table_group.tables[0]; 2619cd15b048SBenjamin Herrenschmidt 2620f87a8864SAlexey Kardashevskiy pnv_pci_ioda2_set_bypass(pe, false); 262146d3e1e1SAlexey Kardashevskiy pnv_pci_ioda2_unset_window(&pe->table_group, 0); 2622db08e1d5SAlexey Kardashevskiy if (pe->pbus) 2623db08e1d5SAlexey Kardashevskiy pnv_ioda_setup_bus_dma(pe, pe->pbus, false); 2624e5afdf9dSAlexey Kardashevskiy iommu_tce_table_put(tbl); 2625cd15b048SBenjamin Herrenschmidt } 2626cd15b048SBenjamin Herrenschmidt 2627f87a8864SAlexey Kardashevskiy static void pnv_ioda2_release_ownership(struct iommu_table_group *table_group) 2628f87a8864SAlexey Kardashevskiy { 2629f87a8864SAlexey Kardashevskiy struct pnv_ioda_pe *pe = container_of(table_group, struct pnv_ioda_pe, 2630f87a8864SAlexey Kardashevskiy table_group); 2631f87a8864SAlexey Kardashevskiy 263246d3e1e1SAlexey Kardashevskiy pnv_pci_ioda2_setup_default_config(pe); 2633db08e1d5SAlexey Kardashevskiy if (pe->pbus) 2634db08e1d5SAlexey Kardashevskiy pnv_ioda_setup_bus_dma(pe, pe->pbus, false); 2635f87a8864SAlexey Kardashevskiy } 2636f87a8864SAlexey Kardashevskiy 2637f87a8864SAlexey Kardashevskiy static struct iommu_table_group_ops pnv_pci_ioda2_ops = { 263800547193SAlexey Kardashevskiy .get_table_size = pnv_pci_ioda2_get_table_size, 26394793d65dSAlexey Kardashevskiy .create_table = pnv_pci_ioda2_create_table, 26404793d65dSAlexey Kardashevskiy .set_window = pnv_pci_ioda2_set_window, 26414793d65dSAlexey Kardashevskiy .unset_window = pnv_pci_ioda2_unset_window, 2642f87a8864SAlexey Kardashevskiy .take_ownership = pnv_ioda2_take_ownership, 2643f87a8864SAlexey Kardashevskiy .release_ownership = pnv_ioda2_release_ownership, 2644f87a8864SAlexey Kardashevskiy }; 2645b5cb9ab1SAlexey Kardashevskiy 2646b5cb9ab1SAlexey Kardashevskiy static int gpe_table_group_to_npe_cb(struct device *dev, void *opaque) 2647b5cb9ab1SAlexey Kardashevskiy { 2648b5cb9ab1SAlexey Kardashevskiy struct pci_controller *hose; 2649b5cb9ab1SAlexey Kardashevskiy struct pnv_phb *phb; 2650b5cb9ab1SAlexey Kardashevskiy struct pnv_ioda_pe **ptmppe = opaque; 2651b5cb9ab1SAlexey Kardashevskiy struct pci_dev *pdev = container_of(dev, struct pci_dev, dev); 2652b5cb9ab1SAlexey Kardashevskiy struct pci_dn *pdn = pci_get_pdn(pdev); 2653b5cb9ab1SAlexey Kardashevskiy 2654b5cb9ab1SAlexey Kardashevskiy if (!pdn || pdn->pe_number == IODA_INVALID_PE) 2655b5cb9ab1SAlexey Kardashevskiy return 0; 2656b5cb9ab1SAlexey Kardashevskiy 2657b5cb9ab1SAlexey Kardashevskiy hose = pci_bus_to_host(pdev->bus); 2658b5cb9ab1SAlexey Kardashevskiy phb = hose->private_data; 26597f2c39e9SFrederic Barrat if (phb->type != PNV_PHB_NPU_NVLINK) 2660b5cb9ab1SAlexey Kardashevskiy return 0; 2661b5cb9ab1SAlexey Kardashevskiy 2662b5cb9ab1SAlexey Kardashevskiy *ptmppe = &phb->ioda.pe_array[pdn->pe_number]; 2663b5cb9ab1SAlexey Kardashevskiy 2664b5cb9ab1SAlexey Kardashevskiy return 1; 2665b5cb9ab1SAlexey Kardashevskiy } 2666b5cb9ab1SAlexey Kardashevskiy 2667b5cb9ab1SAlexey Kardashevskiy /* 2668b5cb9ab1SAlexey Kardashevskiy * This returns PE of associated NPU. 2669b5cb9ab1SAlexey Kardashevskiy * This assumes that NPU is in the same IOMMU group with GPU and there is 2670b5cb9ab1SAlexey Kardashevskiy * no other PEs. 2671b5cb9ab1SAlexey Kardashevskiy */ 2672b5cb9ab1SAlexey Kardashevskiy static struct pnv_ioda_pe *gpe_table_group_to_npe( 2673b5cb9ab1SAlexey Kardashevskiy struct iommu_table_group *table_group) 2674b5cb9ab1SAlexey Kardashevskiy { 2675b5cb9ab1SAlexey Kardashevskiy struct pnv_ioda_pe *npe = NULL; 2676b5cb9ab1SAlexey Kardashevskiy int ret = iommu_group_for_each_dev(table_group->group, &npe, 2677b5cb9ab1SAlexey Kardashevskiy gpe_table_group_to_npe_cb); 2678b5cb9ab1SAlexey Kardashevskiy 2679b5cb9ab1SAlexey Kardashevskiy BUG_ON(!ret || !npe); 2680b5cb9ab1SAlexey Kardashevskiy 2681b5cb9ab1SAlexey Kardashevskiy return npe; 2682b5cb9ab1SAlexey Kardashevskiy } 2683b5cb9ab1SAlexey Kardashevskiy 2684b5cb9ab1SAlexey Kardashevskiy static long pnv_pci_ioda2_npu_set_window(struct iommu_table_group *table_group, 2685b5cb9ab1SAlexey Kardashevskiy int num, struct iommu_table *tbl) 2686b5cb9ab1SAlexey Kardashevskiy { 2687b5cb9ab1SAlexey Kardashevskiy long ret = pnv_pci_ioda2_set_window(table_group, num, tbl); 2688b5cb9ab1SAlexey Kardashevskiy 2689b5cb9ab1SAlexey Kardashevskiy if (ret) 2690b5cb9ab1SAlexey Kardashevskiy return ret; 2691b5cb9ab1SAlexey Kardashevskiy 2692b5cb9ab1SAlexey Kardashevskiy ret = pnv_npu_set_window(gpe_table_group_to_npe(table_group), num, tbl); 2693b5cb9ab1SAlexey Kardashevskiy if (ret) 2694b5cb9ab1SAlexey Kardashevskiy pnv_pci_ioda2_unset_window(table_group, num); 2695b5cb9ab1SAlexey Kardashevskiy 2696b5cb9ab1SAlexey Kardashevskiy return ret; 2697b5cb9ab1SAlexey Kardashevskiy } 2698b5cb9ab1SAlexey Kardashevskiy 2699b5cb9ab1SAlexey Kardashevskiy static long pnv_pci_ioda2_npu_unset_window( 2700b5cb9ab1SAlexey Kardashevskiy struct iommu_table_group *table_group, 2701b5cb9ab1SAlexey Kardashevskiy int num) 2702b5cb9ab1SAlexey Kardashevskiy { 2703b5cb9ab1SAlexey Kardashevskiy long ret = pnv_pci_ioda2_unset_window(table_group, num); 2704b5cb9ab1SAlexey Kardashevskiy 2705b5cb9ab1SAlexey Kardashevskiy if (ret) 2706b5cb9ab1SAlexey Kardashevskiy return ret; 2707b5cb9ab1SAlexey Kardashevskiy 2708b5cb9ab1SAlexey Kardashevskiy return pnv_npu_unset_window(gpe_table_group_to_npe(table_group), num); 2709b5cb9ab1SAlexey Kardashevskiy } 2710b5cb9ab1SAlexey Kardashevskiy 2711b5cb9ab1SAlexey Kardashevskiy static void pnv_ioda2_npu_take_ownership(struct iommu_table_group *table_group) 2712b5cb9ab1SAlexey Kardashevskiy { 2713b5cb9ab1SAlexey Kardashevskiy /* 2714b5cb9ab1SAlexey Kardashevskiy * Detach NPU first as pnv_ioda2_take_ownership() will destroy 2715b5cb9ab1SAlexey Kardashevskiy * the iommu_table if 32bit DMA is enabled. 2716b5cb9ab1SAlexey Kardashevskiy */ 2717b5cb9ab1SAlexey Kardashevskiy pnv_npu_take_ownership(gpe_table_group_to_npe(table_group)); 2718b5cb9ab1SAlexey Kardashevskiy pnv_ioda2_take_ownership(table_group); 2719b5cb9ab1SAlexey Kardashevskiy } 2720b5cb9ab1SAlexey Kardashevskiy 2721b5cb9ab1SAlexey Kardashevskiy static struct iommu_table_group_ops pnv_pci_ioda2_npu_ops = { 2722b5cb9ab1SAlexey Kardashevskiy .get_table_size = pnv_pci_ioda2_get_table_size, 2723b5cb9ab1SAlexey Kardashevskiy .create_table = pnv_pci_ioda2_create_table, 2724b5cb9ab1SAlexey Kardashevskiy .set_window = pnv_pci_ioda2_npu_set_window, 2725b5cb9ab1SAlexey Kardashevskiy .unset_window = pnv_pci_ioda2_npu_unset_window, 2726b5cb9ab1SAlexey Kardashevskiy .take_ownership = pnv_ioda2_npu_take_ownership, 2727b5cb9ab1SAlexey Kardashevskiy .release_ownership = pnv_ioda2_release_ownership, 2728b5cb9ab1SAlexey Kardashevskiy }; 2729b5cb9ab1SAlexey Kardashevskiy 2730b5cb9ab1SAlexey Kardashevskiy static void pnv_pci_ioda_setup_iommu_api(void) 2731b5cb9ab1SAlexey Kardashevskiy { 2732b5cb9ab1SAlexey Kardashevskiy struct pci_controller *hose, *tmp; 2733b5cb9ab1SAlexey Kardashevskiy struct pnv_phb *phb; 2734b5cb9ab1SAlexey Kardashevskiy struct pnv_ioda_pe *pe, *gpe; 2735b5cb9ab1SAlexey Kardashevskiy 2736b5cb9ab1SAlexey Kardashevskiy /* 2737b5cb9ab1SAlexey Kardashevskiy * Now we have all PHBs discovered, time to add NPU devices to 2738b5cb9ab1SAlexey Kardashevskiy * the corresponding IOMMU groups. 2739b5cb9ab1SAlexey Kardashevskiy */ 2740b5cb9ab1SAlexey Kardashevskiy list_for_each_entry_safe(hose, tmp, &hose_list, list_node) { 2741b5cb9ab1SAlexey Kardashevskiy phb = hose->private_data; 2742b5cb9ab1SAlexey Kardashevskiy 27437f2c39e9SFrederic Barrat if (phb->type != PNV_PHB_NPU_NVLINK) 2744b5cb9ab1SAlexey Kardashevskiy continue; 2745b5cb9ab1SAlexey Kardashevskiy 2746b5cb9ab1SAlexey Kardashevskiy list_for_each_entry(pe, &phb->ioda.pe_list, list) { 2747b5cb9ab1SAlexey Kardashevskiy gpe = pnv_pci_npu_setup_iommu(pe); 2748b5cb9ab1SAlexey Kardashevskiy if (gpe) 2749b5cb9ab1SAlexey Kardashevskiy gpe->table_group.ops = &pnv_pci_ioda2_npu_ops; 2750b5cb9ab1SAlexey Kardashevskiy } 2751b5cb9ab1SAlexey Kardashevskiy } 2752b5cb9ab1SAlexey Kardashevskiy } 2753b5cb9ab1SAlexey Kardashevskiy #else /* !CONFIG_IOMMU_API */ 2754b5cb9ab1SAlexey Kardashevskiy static void pnv_pci_ioda_setup_iommu_api(void) { }; 2755f87a8864SAlexey Kardashevskiy #endif 2756f87a8864SAlexey Kardashevskiy 2757bbb845c4SAlexey Kardashevskiy static __be64 *pnv_pci_ioda2_table_do_alloc_pages(int nid, unsigned shift, 2758bbb845c4SAlexey Kardashevskiy unsigned levels, unsigned long limit, 27593ba3a73eSAlexey Kardashevskiy unsigned long *current_offset, unsigned long *total_allocated) 2760aca6913fSAlexey Kardashevskiy { 2761aca6913fSAlexey Kardashevskiy struct page *tce_mem = NULL; 2762bbb845c4SAlexey Kardashevskiy __be64 *addr, *tmp; 2763aca6913fSAlexey Kardashevskiy unsigned order = max_t(unsigned, shift, PAGE_SHIFT) - PAGE_SHIFT; 2764bbb845c4SAlexey Kardashevskiy unsigned long allocated = 1UL << (order + PAGE_SHIFT); 2765bbb845c4SAlexey Kardashevskiy unsigned entries = 1UL << (shift - 3); 2766bbb845c4SAlexey Kardashevskiy long i; 2767aca6913fSAlexey Kardashevskiy 2768aca6913fSAlexey Kardashevskiy tce_mem = alloc_pages_node(nid, GFP_KERNEL, order); 2769aca6913fSAlexey Kardashevskiy if (!tce_mem) { 2770aca6913fSAlexey Kardashevskiy pr_err("Failed to allocate a TCE memory, order=%d\n", order); 2771aca6913fSAlexey Kardashevskiy return NULL; 2772aca6913fSAlexey Kardashevskiy } 2773aca6913fSAlexey Kardashevskiy addr = page_address(tce_mem); 2774bbb845c4SAlexey Kardashevskiy memset(addr, 0, allocated); 27753ba3a73eSAlexey Kardashevskiy *total_allocated += allocated; 2776bbb845c4SAlexey Kardashevskiy 2777bbb845c4SAlexey Kardashevskiy --levels; 2778bbb845c4SAlexey Kardashevskiy if (!levels) { 2779bbb845c4SAlexey Kardashevskiy *current_offset += allocated; 2780bbb845c4SAlexey Kardashevskiy return addr; 2781bbb845c4SAlexey Kardashevskiy } 2782bbb845c4SAlexey Kardashevskiy 2783bbb845c4SAlexey Kardashevskiy for (i = 0; i < entries; ++i) { 2784bbb845c4SAlexey Kardashevskiy tmp = pnv_pci_ioda2_table_do_alloc_pages(nid, shift, 27853ba3a73eSAlexey Kardashevskiy levels, limit, current_offset, total_allocated); 2786bbb845c4SAlexey Kardashevskiy if (!tmp) 2787bbb845c4SAlexey Kardashevskiy break; 2788bbb845c4SAlexey Kardashevskiy 2789bbb845c4SAlexey Kardashevskiy addr[i] = cpu_to_be64(__pa(tmp) | 2790bbb845c4SAlexey Kardashevskiy TCE_PCI_READ | TCE_PCI_WRITE); 2791bbb845c4SAlexey Kardashevskiy 2792bbb845c4SAlexey Kardashevskiy if (*current_offset >= limit) 2793bbb845c4SAlexey Kardashevskiy break; 2794bbb845c4SAlexey Kardashevskiy } 2795aca6913fSAlexey Kardashevskiy 2796aca6913fSAlexey Kardashevskiy return addr; 2797aca6913fSAlexey Kardashevskiy } 2798aca6913fSAlexey Kardashevskiy 2799bbb845c4SAlexey Kardashevskiy static void pnv_pci_ioda2_table_do_free_pages(__be64 *addr, 2800bbb845c4SAlexey Kardashevskiy unsigned long size, unsigned level); 2801bbb845c4SAlexey Kardashevskiy 2802aca6913fSAlexey Kardashevskiy static long pnv_pci_ioda2_table_alloc_pages(int nid, __u64 bus_offset, 2803bbb845c4SAlexey Kardashevskiy __u32 page_shift, __u64 window_size, __u32 levels, 2804bbb845c4SAlexey Kardashevskiy struct iommu_table *tbl) 2805aca6913fSAlexey Kardashevskiy { 2806aca6913fSAlexey Kardashevskiy void *addr; 28073ba3a73eSAlexey Kardashevskiy unsigned long offset = 0, level_shift, total_allocated = 0; 2808aca6913fSAlexey Kardashevskiy const unsigned window_shift = ilog2(window_size); 2809aca6913fSAlexey Kardashevskiy unsigned entries_shift = window_shift - page_shift; 2810aca6913fSAlexey Kardashevskiy unsigned table_shift = max_t(unsigned, entries_shift + 3, PAGE_SHIFT); 2811aca6913fSAlexey Kardashevskiy const unsigned long tce_table_size = 1UL << table_shift; 2812aca6913fSAlexey Kardashevskiy 2813bbb845c4SAlexey Kardashevskiy if (!levels || (levels > POWERNV_IOMMU_MAX_LEVELS)) 2814bbb845c4SAlexey Kardashevskiy return -EINVAL; 2815bbb845c4SAlexey Kardashevskiy 28169003a249SAlexey Kardashevskiy if (!is_power_of_2(window_size)) 2817aca6913fSAlexey Kardashevskiy return -EINVAL; 2818aca6913fSAlexey Kardashevskiy 2819bbb845c4SAlexey Kardashevskiy /* Adjust direct table size from window_size and levels */ 2820bbb845c4SAlexey Kardashevskiy entries_shift = (entries_shift + levels - 1) / levels; 2821bbb845c4SAlexey Kardashevskiy level_shift = entries_shift + 3; 2822bbb845c4SAlexey Kardashevskiy level_shift = max_t(unsigned, level_shift, PAGE_SHIFT); 2823bbb845c4SAlexey Kardashevskiy 28247aafac11SAlexey Kardashevskiy if ((level_shift - 3) * levels + page_shift >= 60) 28257aafac11SAlexey Kardashevskiy return -EINVAL; 28267aafac11SAlexey Kardashevskiy 2827aca6913fSAlexey Kardashevskiy /* Allocate TCE table */ 2828bbb845c4SAlexey Kardashevskiy addr = pnv_pci_ioda2_table_do_alloc_pages(nid, level_shift, 28293ba3a73eSAlexey Kardashevskiy levels, tce_table_size, &offset, &total_allocated); 2830bbb845c4SAlexey Kardashevskiy 2831bbb845c4SAlexey Kardashevskiy /* addr==NULL means that the first level allocation failed */ 2832aca6913fSAlexey Kardashevskiy if (!addr) 2833aca6913fSAlexey Kardashevskiy return -ENOMEM; 2834aca6913fSAlexey Kardashevskiy 2835bbb845c4SAlexey Kardashevskiy /* 2836bbb845c4SAlexey Kardashevskiy * First level was allocated but some lower level failed as 2837bbb845c4SAlexey Kardashevskiy * we did not allocate as much as we wanted, 2838bbb845c4SAlexey Kardashevskiy * release partially allocated table. 2839bbb845c4SAlexey Kardashevskiy */ 2840bbb845c4SAlexey Kardashevskiy if (offset < tce_table_size) { 2841bbb845c4SAlexey Kardashevskiy pnv_pci_ioda2_table_do_free_pages(addr, 2842bbb845c4SAlexey Kardashevskiy 1ULL << (level_shift - 3), levels - 1); 2843bbb845c4SAlexey Kardashevskiy return -ENOMEM; 2844bbb845c4SAlexey Kardashevskiy } 2845bbb845c4SAlexey Kardashevskiy 2846aca6913fSAlexey Kardashevskiy /* Setup linux iommu table */ 2847aca6913fSAlexey Kardashevskiy pnv_pci_setup_iommu_table(tbl, addr, tce_table_size, bus_offset, 2848aca6913fSAlexey Kardashevskiy page_shift); 2849bbb845c4SAlexey Kardashevskiy tbl->it_level_size = 1ULL << (level_shift - 3); 2850bbb845c4SAlexey Kardashevskiy tbl->it_indirect_levels = levels - 1; 28513ba3a73eSAlexey Kardashevskiy tbl->it_allocated_size = total_allocated; 2852aca6913fSAlexey Kardashevskiy 2853aca6913fSAlexey Kardashevskiy pr_devel("Created TCE table: ws=%08llx ts=%lx @%08llx\n", 2854aca6913fSAlexey Kardashevskiy window_size, tce_table_size, bus_offset); 2855aca6913fSAlexey Kardashevskiy 2856aca6913fSAlexey Kardashevskiy return 0; 2857aca6913fSAlexey Kardashevskiy } 2858aca6913fSAlexey Kardashevskiy 2859bbb845c4SAlexey Kardashevskiy static void pnv_pci_ioda2_table_do_free_pages(__be64 *addr, 2860bbb845c4SAlexey Kardashevskiy unsigned long size, unsigned level) 2861bbb845c4SAlexey Kardashevskiy { 2862bbb845c4SAlexey Kardashevskiy const unsigned long addr_ul = (unsigned long) addr & 2863bbb845c4SAlexey Kardashevskiy ~(TCE_PCI_READ | TCE_PCI_WRITE); 2864bbb845c4SAlexey Kardashevskiy 2865bbb845c4SAlexey Kardashevskiy if (level) { 2866bbb845c4SAlexey Kardashevskiy long i; 2867bbb845c4SAlexey Kardashevskiy u64 *tmp = (u64 *) addr_ul; 2868bbb845c4SAlexey Kardashevskiy 2869bbb845c4SAlexey Kardashevskiy for (i = 0; i < size; ++i) { 2870bbb845c4SAlexey Kardashevskiy unsigned long hpa = be64_to_cpu(tmp[i]); 2871bbb845c4SAlexey Kardashevskiy 2872bbb845c4SAlexey Kardashevskiy if (!(hpa & (TCE_PCI_READ | TCE_PCI_WRITE))) 2873bbb845c4SAlexey Kardashevskiy continue; 2874bbb845c4SAlexey Kardashevskiy 2875bbb845c4SAlexey Kardashevskiy pnv_pci_ioda2_table_do_free_pages(__va(hpa), size, 2876bbb845c4SAlexey Kardashevskiy level - 1); 2877bbb845c4SAlexey Kardashevskiy } 2878bbb845c4SAlexey Kardashevskiy } 2879bbb845c4SAlexey Kardashevskiy 2880bbb845c4SAlexey Kardashevskiy free_pages(addr_ul, get_order(size << 3)); 2881bbb845c4SAlexey Kardashevskiy } 2882bbb845c4SAlexey Kardashevskiy 2883aca6913fSAlexey Kardashevskiy static void pnv_pci_ioda2_table_free_pages(struct iommu_table *tbl) 2884aca6913fSAlexey Kardashevskiy { 2885bbb845c4SAlexey Kardashevskiy const unsigned long size = tbl->it_indirect_levels ? 2886bbb845c4SAlexey Kardashevskiy tbl->it_level_size : tbl->it_size; 2887bbb845c4SAlexey Kardashevskiy 2888aca6913fSAlexey Kardashevskiy if (!tbl->it_size) 2889aca6913fSAlexey Kardashevskiy return; 2890aca6913fSAlexey Kardashevskiy 2891bbb845c4SAlexey Kardashevskiy pnv_pci_ioda2_table_do_free_pages((__be64 *)tbl->it_base, size, 2892bbb845c4SAlexey Kardashevskiy tbl->it_indirect_levels); 2893aca6913fSAlexey Kardashevskiy } 2894aca6913fSAlexey Kardashevskiy 2895373f5657SGavin Shan static void pnv_pci_ioda2_setup_dma_pe(struct pnv_phb *phb, 2896373f5657SGavin Shan struct pnv_ioda_pe *pe) 2897373f5657SGavin Shan { 2898373f5657SGavin Shan int64_t rc; 2899373f5657SGavin Shan 2900ccd1c191SGavin Shan if (!pnv_pci_ioda_pe_dma_weight(pe)) 2901ccd1c191SGavin Shan return; 2902ccd1c191SGavin Shan 2903f87a8864SAlexey Kardashevskiy /* TVE #1 is selected by PCI address bit 59 */ 2904f87a8864SAlexey Kardashevskiy pe->tce_bypass_base = 1ull << 59; 2905f87a8864SAlexey Kardashevskiy 2906b348aa65SAlexey Kardashevskiy iommu_register_group(&pe->table_group, phb->hose->global_number, 2907b348aa65SAlexey Kardashevskiy pe->pe_number); 2908c5773822SAlexey Kardashevskiy 2909373f5657SGavin Shan /* The PE will reserve all possible 32-bits space */ 2910373f5657SGavin Shan pe_info(pe, "Setting up 32-bit TCE table at 0..%08x\n", 2911aca6913fSAlexey Kardashevskiy phb->ioda.m32_pci_base); 2912373f5657SGavin Shan 2913e5aad1e6SAlexey Kardashevskiy /* Setup linux iommu table */ 29144793d65dSAlexey Kardashevskiy pe->table_group.tce32_start = 0; 29154793d65dSAlexey Kardashevskiy pe->table_group.tce32_size = phb->ioda.m32_pci_base; 29164793d65dSAlexey Kardashevskiy pe->table_group.max_dynamic_windows_supported = 29174793d65dSAlexey Kardashevskiy IOMMU_TABLE_GROUP_MAX_TABLES; 29184793d65dSAlexey Kardashevskiy pe->table_group.max_levels = POWERNV_IOMMU_MAX_LEVELS; 29194793d65dSAlexey Kardashevskiy pe->table_group.pgsizes = SZ_4K | SZ_64K | SZ_16M; 2920e5aad1e6SAlexey Kardashevskiy #ifdef CONFIG_IOMMU_API 2921e5aad1e6SAlexey Kardashevskiy pe->table_group.ops = &pnv_pci_ioda2_ops; 2922e5aad1e6SAlexey Kardashevskiy #endif 2923e5aad1e6SAlexey Kardashevskiy 292446d3e1e1SAlexey Kardashevskiy rc = pnv_pci_ioda2_setup_default_config(pe); 2925801846d1SGavin Shan if (rc) 292646d3e1e1SAlexey Kardashevskiy return; 292746d3e1e1SAlexey Kardashevskiy 292820f13b95SAlexey Kardashevskiy if (pe->flags & (PNV_IODA_PE_BUS | PNV_IODA_PE_BUS_ALL)) 2929db08e1d5SAlexey Kardashevskiy pnv_ioda_setup_bus_dma(pe, pe->pbus, true); 2930373f5657SGavin Shan } 2931373f5657SGavin Shan 2932184cd4a3SBenjamin Herrenschmidt #ifdef CONFIG_PCI_MSI 29334ee11c1aSSuresh Warrier int64_t pnv_opal_pci_msi_eoi(struct irq_chip *chip, unsigned int hw_irq) 2934137436c9SGavin Shan { 2935137436c9SGavin Shan struct pnv_phb *phb = container_of(chip, struct pnv_phb, 2936137436c9SGavin Shan ioda.irq_chip); 2937137436c9SGavin Shan 29384ee11c1aSSuresh Warrier return opal_pci_msi_eoi(phb->opal_id, hw_irq); 29394ee11c1aSSuresh Warrier } 29404ee11c1aSSuresh Warrier 29414ee11c1aSSuresh Warrier static void pnv_ioda2_msi_eoi(struct irq_data *d) 29424ee11c1aSSuresh Warrier { 29434ee11c1aSSuresh Warrier int64_t rc; 29444ee11c1aSSuresh Warrier unsigned int hw_irq = (unsigned int)irqd_to_hwirq(d); 29454ee11c1aSSuresh Warrier struct irq_chip *chip = irq_data_get_irq_chip(d); 29464ee11c1aSSuresh Warrier 29474ee11c1aSSuresh Warrier rc = pnv_opal_pci_msi_eoi(chip, hw_irq); 2948137436c9SGavin Shan WARN_ON_ONCE(rc); 2949137436c9SGavin Shan 2950137436c9SGavin Shan icp_native_eoi(d); 2951137436c9SGavin Shan } 2952137436c9SGavin Shan 2953fd9a1c26SIan Munsie 2954f456834aSIan Munsie void pnv_set_msi_irq_chip(struct pnv_phb *phb, unsigned int virq) 2955fd9a1c26SIan Munsie { 2956fd9a1c26SIan Munsie struct irq_data *idata; 2957fd9a1c26SIan Munsie struct irq_chip *ichip; 2958fd9a1c26SIan Munsie 2959fb111334SBenjamin Herrenschmidt /* The MSI EOI OPAL call is only needed on PHB3 */ 2960fb111334SBenjamin Herrenschmidt if (phb->model != PNV_PHB_MODEL_PHB3) 2961fd9a1c26SIan Munsie return; 2962fd9a1c26SIan Munsie 2963fd9a1c26SIan Munsie if (!phb->ioda.irq_chip_init) { 2964fd9a1c26SIan Munsie /* 2965fd9a1c26SIan Munsie * First time we setup an MSI IRQ, we need to setup the 2966fd9a1c26SIan Munsie * corresponding IRQ chip to route correctly. 2967fd9a1c26SIan Munsie */ 2968fd9a1c26SIan Munsie idata = irq_get_irq_data(virq); 2969fd9a1c26SIan Munsie ichip = irq_data_get_irq_chip(idata); 2970fd9a1c26SIan Munsie phb->ioda.irq_chip_init = 1; 2971fd9a1c26SIan Munsie phb->ioda.irq_chip = *ichip; 2972fd9a1c26SIan Munsie phb->ioda.irq_chip.irq_eoi = pnv_ioda2_msi_eoi; 2973fd9a1c26SIan Munsie } 2974fd9a1c26SIan Munsie irq_set_chip(virq, &phb->ioda.irq_chip); 2975fd9a1c26SIan Munsie } 2976fd9a1c26SIan Munsie 29774ee11c1aSSuresh Warrier /* 29784ee11c1aSSuresh Warrier * Returns true iff chip is something that we could call 29794ee11c1aSSuresh Warrier * pnv_opal_pci_msi_eoi for. 29804ee11c1aSSuresh Warrier */ 29814ee11c1aSSuresh Warrier bool is_pnv_opal_msi(struct irq_chip *chip) 29824ee11c1aSSuresh Warrier { 29834ee11c1aSSuresh Warrier return chip->irq_eoi == pnv_ioda2_msi_eoi; 29844ee11c1aSSuresh Warrier } 29854ee11c1aSSuresh Warrier EXPORT_SYMBOL_GPL(is_pnv_opal_msi); 29864ee11c1aSSuresh Warrier 2987184cd4a3SBenjamin Herrenschmidt static int pnv_pci_ioda_msi_setup(struct pnv_phb *phb, struct pci_dev *dev, 2988137436c9SGavin Shan unsigned int hwirq, unsigned int virq, 2989137436c9SGavin Shan unsigned int is_64, struct msi_msg *msg) 2990184cd4a3SBenjamin Herrenschmidt { 2991184cd4a3SBenjamin Herrenschmidt struct pnv_ioda_pe *pe = pnv_ioda_get_pe(dev); 2992184cd4a3SBenjamin Herrenschmidt unsigned int xive_num = hwirq - phb->msi_base; 29933a1a4661SBenjamin Herrenschmidt __be32 data; 2994184cd4a3SBenjamin Herrenschmidt int rc; 2995184cd4a3SBenjamin Herrenschmidt 2996184cd4a3SBenjamin Herrenschmidt /* No PE assigned ? bail out ... no MSI for you ! */ 2997184cd4a3SBenjamin Herrenschmidt if (pe == NULL) 2998184cd4a3SBenjamin Herrenschmidt return -ENXIO; 2999184cd4a3SBenjamin Herrenschmidt 3000184cd4a3SBenjamin Herrenschmidt /* Check if we have an MVE */ 3001184cd4a3SBenjamin Herrenschmidt if (pe->mve_number < 0) 3002184cd4a3SBenjamin Herrenschmidt return -ENXIO; 3003184cd4a3SBenjamin Herrenschmidt 3004b72c1f65SBenjamin Herrenschmidt /* Force 32-bit MSI on some broken devices */ 300536074381SBenjamin Herrenschmidt if (dev->no_64bit_msi) 3006b72c1f65SBenjamin Herrenschmidt is_64 = 0; 3007b72c1f65SBenjamin Herrenschmidt 3008184cd4a3SBenjamin Herrenschmidt /* Assign XIVE to PE */ 3009184cd4a3SBenjamin Herrenschmidt rc = opal_pci_set_xive_pe(phb->opal_id, pe->pe_number, xive_num); 3010184cd4a3SBenjamin Herrenschmidt if (rc) { 3011184cd4a3SBenjamin Herrenschmidt pr_warn("%s: OPAL error %d setting XIVE %d PE\n", 3012184cd4a3SBenjamin Herrenschmidt pci_name(dev), rc, xive_num); 3013184cd4a3SBenjamin Herrenschmidt return -EIO; 3014184cd4a3SBenjamin Herrenschmidt } 3015184cd4a3SBenjamin Herrenschmidt 3016184cd4a3SBenjamin Herrenschmidt if (is_64) { 30173a1a4661SBenjamin Herrenschmidt __be64 addr64; 30183a1a4661SBenjamin Herrenschmidt 3019184cd4a3SBenjamin Herrenschmidt rc = opal_get_msi_64(phb->opal_id, pe->mve_number, xive_num, 1, 3020184cd4a3SBenjamin Herrenschmidt &addr64, &data); 3021184cd4a3SBenjamin Herrenschmidt if (rc) { 3022184cd4a3SBenjamin Herrenschmidt pr_warn("%s: OPAL error %d getting 64-bit MSI data\n", 3023184cd4a3SBenjamin Herrenschmidt pci_name(dev), rc); 3024184cd4a3SBenjamin Herrenschmidt return -EIO; 3025184cd4a3SBenjamin Herrenschmidt } 30263a1a4661SBenjamin Herrenschmidt msg->address_hi = be64_to_cpu(addr64) >> 32; 30273a1a4661SBenjamin Herrenschmidt msg->address_lo = be64_to_cpu(addr64) & 0xfffffffful; 3028184cd4a3SBenjamin Herrenschmidt } else { 30293a1a4661SBenjamin Herrenschmidt __be32 addr32; 30303a1a4661SBenjamin Herrenschmidt 3031184cd4a3SBenjamin Herrenschmidt rc = opal_get_msi_32(phb->opal_id, pe->mve_number, xive_num, 1, 3032184cd4a3SBenjamin Herrenschmidt &addr32, &data); 3033184cd4a3SBenjamin Herrenschmidt if (rc) { 3034184cd4a3SBenjamin Herrenschmidt pr_warn("%s: OPAL error %d getting 32-bit MSI data\n", 3035184cd4a3SBenjamin Herrenschmidt pci_name(dev), rc); 3036184cd4a3SBenjamin Herrenschmidt return -EIO; 3037184cd4a3SBenjamin Herrenschmidt } 3038184cd4a3SBenjamin Herrenschmidt msg->address_hi = 0; 30393a1a4661SBenjamin Herrenschmidt msg->address_lo = be32_to_cpu(addr32); 3040184cd4a3SBenjamin Herrenschmidt } 30413a1a4661SBenjamin Herrenschmidt msg->data = be32_to_cpu(data); 3042184cd4a3SBenjamin Herrenschmidt 3043f456834aSIan Munsie pnv_set_msi_irq_chip(phb, virq); 3044137436c9SGavin Shan 3045184cd4a3SBenjamin Herrenschmidt pr_devel("%s: %s-bit MSI on hwirq %x (xive #%d)," 30461f52f176SRussell Currey " address=%x_%08x data=%x PE# %x\n", 3047184cd4a3SBenjamin Herrenschmidt pci_name(dev), is_64 ? "64" : "32", hwirq, xive_num, 3048184cd4a3SBenjamin Herrenschmidt msg->address_hi, msg->address_lo, data, pe->pe_number); 3049184cd4a3SBenjamin Herrenschmidt 3050184cd4a3SBenjamin Herrenschmidt return 0; 3051184cd4a3SBenjamin Herrenschmidt } 3052184cd4a3SBenjamin Herrenschmidt 3053184cd4a3SBenjamin Herrenschmidt static void pnv_pci_init_ioda_msis(struct pnv_phb *phb) 3054184cd4a3SBenjamin Herrenschmidt { 3055fb1b55d6SGavin Shan unsigned int count; 3056184cd4a3SBenjamin Herrenschmidt const __be32 *prop = of_get_property(phb->hose->dn, 3057184cd4a3SBenjamin Herrenschmidt "ibm,opal-msi-ranges", NULL); 3058184cd4a3SBenjamin Herrenschmidt if (!prop) { 3059184cd4a3SBenjamin Herrenschmidt /* BML Fallback */ 3060184cd4a3SBenjamin Herrenschmidt prop = of_get_property(phb->hose->dn, "msi-ranges", NULL); 3061184cd4a3SBenjamin Herrenschmidt } 3062184cd4a3SBenjamin Herrenschmidt if (!prop) 3063184cd4a3SBenjamin Herrenschmidt return; 3064184cd4a3SBenjamin Herrenschmidt 3065184cd4a3SBenjamin Herrenschmidt phb->msi_base = be32_to_cpup(prop); 3066fb1b55d6SGavin Shan count = be32_to_cpup(prop + 1); 3067fb1b55d6SGavin Shan if (msi_bitmap_alloc(&phb->msi_bmp, count, phb->hose->dn)) { 3068184cd4a3SBenjamin Herrenschmidt pr_err("PCI %d: Failed to allocate MSI bitmap !\n", 3069184cd4a3SBenjamin Herrenschmidt phb->hose->global_number); 3070184cd4a3SBenjamin Herrenschmidt return; 3071184cd4a3SBenjamin Herrenschmidt } 3072fb1b55d6SGavin Shan 3073184cd4a3SBenjamin Herrenschmidt phb->msi_setup = pnv_pci_ioda_msi_setup; 3074184cd4a3SBenjamin Herrenschmidt phb->msi32_support = 1; 3075184cd4a3SBenjamin Herrenschmidt pr_info(" Allocated bitmap for %d MSIs (base IRQ 0x%x)\n", 3076fb1b55d6SGavin Shan count, phb->msi_base); 3077184cd4a3SBenjamin Herrenschmidt } 3078184cd4a3SBenjamin Herrenschmidt #else 3079184cd4a3SBenjamin Herrenschmidt static void pnv_pci_init_ioda_msis(struct pnv_phb *phb) { } 3080184cd4a3SBenjamin Herrenschmidt #endif /* CONFIG_PCI_MSI */ 3081184cd4a3SBenjamin Herrenschmidt 30826e628c7dSWei Yang #ifdef CONFIG_PCI_IOV 30836e628c7dSWei Yang static void pnv_pci_ioda_fixup_iov_resources(struct pci_dev *pdev) 30846e628c7dSWei Yang { 3085f2dd0afeSWei Yang struct pci_controller *hose = pci_bus_to_host(pdev->bus); 3086f2dd0afeSWei Yang struct pnv_phb *phb = hose->private_data; 3087f2dd0afeSWei Yang const resource_size_t gate = phb->ioda.m64_segsize >> 2; 30886e628c7dSWei Yang struct resource *res; 30896e628c7dSWei Yang int i; 3090dfcc8d45SWei Yang resource_size_t size, total_vf_bar_sz; 30916e628c7dSWei Yang struct pci_dn *pdn; 30925b88ec22SWei Yang int mul, total_vfs; 30936e628c7dSWei Yang 30946e628c7dSWei Yang if (!pdev->is_physfn || pdev->is_added) 30956e628c7dSWei Yang return; 30966e628c7dSWei Yang 30976e628c7dSWei Yang pdn = pci_get_pdn(pdev); 30986e628c7dSWei Yang pdn->vfs_expanded = 0; 3099ee8222feSWei Yang pdn->m64_single_mode = false; 31006e628c7dSWei Yang 31015b88ec22SWei Yang total_vfs = pci_sriov_get_totalvfs(pdev); 310292b8f137SGavin Shan mul = phb->ioda.total_pe_num; 3103dfcc8d45SWei Yang total_vf_bar_sz = 0; 31045b88ec22SWei Yang 31055b88ec22SWei Yang for (i = 0; i < PCI_SRIOV_NUM_BARS; i++) { 31065b88ec22SWei Yang res = &pdev->resource[i + PCI_IOV_RESOURCES]; 31075b88ec22SWei Yang if (!res->flags || res->parent) 31085b88ec22SWei Yang continue; 3109b79331a5SRussell Currey if (!pnv_pci_is_m64_flags(res->flags)) { 3110b0331854SWei Yang dev_warn(&pdev->dev, "Don't support SR-IOV with" 3111b0331854SWei Yang " non M64 VF BAR%d: %pR. \n", 31125b88ec22SWei Yang i, res); 3113b0331854SWei Yang goto truncate_iov; 31145b88ec22SWei Yang } 31155b88ec22SWei Yang 3116dfcc8d45SWei Yang total_vf_bar_sz += pci_iov_resource_size(pdev, 3117dfcc8d45SWei Yang i + PCI_IOV_RESOURCES); 31185b88ec22SWei Yang 3119f2dd0afeSWei Yang /* 3120f2dd0afeSWei Yang * If bigger than quarter of M64 segment size, just round up 3121f2dd0afeSWei Yang * power of two. 3122f2dd0afeSWei Yang * 3123f2dd0afeSWei Yang * Generally, one M64 BAR maps one IOV BAR. To avoid conflict 3124f2dd0afeSWei Yang * with other devices, IOV BAR size is expanded to be 3125f2dd0afeSWei Yang * (total_pe * VF_BAR_size). When VF_BAR_size is half of M64 3126f2dd0afeSWei Yang * segment size , the expanded size would equal to half of the 3127f2dd0afeSWei Yang * whole M64 space size, which will exhaust the M64 Space and 3128f2dd0afeSWei Yang * limit the system flexibility. This is a design decision to 3129f2dd0afeSWei Yang * set the boundary to quarter of the M64 segment size. 3130f2dd0afeSWei Yang */ 3131dfcc8d45SWei Yang if (total_vf_bar_sz > gate) { 31325b88ec22SWei Yang mul = roundup_pow_of_two(total_vfs); 3133dfcc8d45SWei Yang dev_info(&pdev->dev, 3134dfcc8d45SWei Yang "VF BAR Total IOV size %llx > %llx, roundup to %d VFs\n", 3135dfcc8d45SWei Yang total_vf_bar_sz, gate, mul); 3136ee8222feSWei Yang pdn->m64_single_mode = true; 31375b88ec22SWei Yang break; 31385b88ec22SWei Yang } 31395b88ec22SWei Yang } 31405b88ec22SWei Yang 31416e628c7dSWei Yang for (i = 0; i < PCI_SRIOV_NUM_BARS; i++) { 31426e628c7dSWei Yang res = &pdev->resource[i + PCI_IOV_RESOURCES]; 31436e628c7dSWei Yang if (!res->flags || res->parent) 31446e628c7dSWei Yang continue; 31456e628c7dSWei Yang 31466e628c7dSWei Yang size = pci_iov_resource_size(pdev, i + PCI_IOV_RESOURCES); 3147ee8222feSWei Yang /* 3148ee8222feSWei Yang * On PHB3, the minimum size alignment of M64 BAR in single 3149ee8222feSWei Yang * mode is 32MB. 3150ee8222feSWei Yang */ 3151ee8222feSWei Yang if (pdn->m64_single_mode && (size < SZ_32M)) 3152ee8222feSWei Yang goto truncate_iov; 3153ee8222feSWei Yang dev_dbg(&pdev->dev, " Fixing VF BAR%d: %pR to\n", i, res); 31545b88ec22SWei Yang res->end = res->start + size * mul - 1; 31556e628c7dSWei Yang dev_dbg(&pdev->dev, " %pR\n", res); 31566e628c7dSWei Yang dev_info(&pdev->dev, "VF BAR%d: %pR (expanded to %d VFs for PE alignment)", 31575b88ec22SWei Yang i, res, mul); 31586e628c7dSWei Yang } 31595b88ec22SWei Yang pdn->vfs_expanded = mul; 3160b0331854SWei Yang 3161b0331854SWei Yang return; 3162b0331854SWei Yang 3163b0331854SWei Yang truncate_iov: 3164b0331854SWei Yang /* To save MMIO space, IOV BAR is truncated. */ 3165b0331854SWei Yang for (i = 0; i < PCI_SRIOV_NUM_BARS; i++) { 3166b0331854SWei Yang res = &pdev->resource[i + PCI_IOV_RESOURCES]; 3167b0331854SWei Yang res->flags = 0; 3168b0331854SWei Yang res->end = res->start - 1; 3169b0331854SWei Yang } 31706e628c7dSWei Yang } 31716e628c7dSWei Yang #endif /* CONFIG_PCI_IOV */ 31726e628c7dSWei Yang 317323e79425SGavin Shan static void pnv_ioda_setup_pe_res(struct pnv_ioda_pe *pe, 317423e79425SGavin Shan struct resource *res) 317511685becSGavin Shan { 317623e79425SGavin Shan struct pnv_phb *phb = pe->phb; 317711685becSGavin Shan struct pci_bus_region region; 317823e79425SGavin Shan int index; 317923e79425SGavin Shan int64_t rc; 318011685becSGavin Shan 318123e79425SGavin Shan if (!res || !res->flags || res->start > res->end) 318223e79425SGavin Shan return; 318311685becSGavin Shan 318411685becSGavin Shan if (res->flags & IORESOURCE_IO) { 318511685becSGavin Shan region.start = res->start - phb->ioda.io_pci_base; 318611685becSGavin Shan region.end = res->end - phb->ioda.io_pci_base; 318711685becSGavin Shan index = region.start / phb->ioda.io_segsize; 318811685becSGavin Shan 318992b8f137SGavin Shan while (index < phb->ioda.total_pe_num && 319011685becSGavin Shan region.start <= region.end) { 319111685becSGavin Shan phb->ioda.io_segmap[index] = pe->pe_number; 319211685becSGavin Shan rc = opal_pci_map_pe_mmio_window(phb->opal_id, 319311685becSGavin Shan pe->pe_number, OPAL_IO_WINDOW_TYPE, 0, index); 319411685becSGavin Shan if (rc != OPAL_SUCCESS) { 31951f52f176SRussell Currey pr_err("%s: Error %lld mapping IO segment#%d to PE#%x\n", 319611685becSGavin Shan __func__, rc, index, pe->pe_number); 319711685becSGavin Shan break; 319811685becSGavin Shan } 319911685becSGavin Shan 320011685becSGavin Shan region.start += phb->ioda.io_segsize; 320111685becSGavin Shan index++; 320211685becSGavin Shan } 3203027fa02fSGavin Shan } else if ((res->flags & IORESOURCE_MEM) && 32045958d19aSBenjamin Herrenschmidt !pnv_pci_is_m64(phb, res)) { 320511685becSGavin Shan region.start = res->start - 320623e79425SGavin Shan phb->hose->mem_offset[0] - 320711685becSGavin Shan phb->ioda.m32_pci_base; 320811685becSGavin Shan region.end = res->end - 320923e79425SGavin Shan phb->hose->mem_offset[0] - 321011685becSGavin Shan phb->ioda.m32_pci_base; 321111685becSGavin Shan index = region.start / phb->ioda.m32_segsize; 321211685becSGavin Shan 321392b8f137SGavin Shan while (index < phb->ioda.total_pe_num && 321411685becSGavin Shan region.start <= region.end) { 321511685becSGavin Shan phb->ioda.m32_segmap[index] = pe->pe_number; 321611685becSGavin Shan rc = opal_pci_map_pe_mmio_window(phb->opal_id, 321711685becSGavin Shan pe->pe_number, OPAL_M32_WINDOW_TYPE, 0, index); 321811685becSGavin Shan if (rc != OPAL_SUCCESS) { 32191f52f176SRussell Currey pr_err("%s: Error %lld mapping M32 segment#%d to PE#%x", 322011685becSGavin Shan __func__, rc, index, pe->pe_number); 322111685becSGavin Shan break; 322211685becSGavin Shan } 322311685becSGavin Shan 322411685becSGavin Shan region.start += phb->ioda.m32_segsize; 322511685becSGavin Shan index++; 322611685becSGavin Shan } 322711685becSGavin Shan } 322811685becSGavin Shan } 322923e79425SGavin Shan 323023e79425SGavin Shan /* 323123e79425SGavin Shan * This function is supposed to be called on basis of PE from top 323223e79425SGavin Shan * to bottom style. So the the I/O or MMIO segment assigned to 323303671057SMasahiro Yamada * parent PE could be overridden by its child PEs if necessary. 323423e79425SGavin Shan */ 323523e79425SGavin Shan static void pnv_ioda_setup_pe_seg(struct pnv_ioda_pe *pe) 323623e79425SGavin Shan { 323769d733e7SGavin Shan struct pci_dev *pdev; 323823e79425SGavin Shan int i; 323923e79425SGavin Shan 324023e79425SGavin Shan /* 324123e79425SGavin Shan * NOTE: We only care PCI bus based PE for now. For PCI 324223e79425SGavin Shan * device based PE, for example SRIOV sensitive VF should 324323e79425SGavin Shan * be figured out later. 324423e79425SGavin Shan */ 324523e79425SGavin Shan BUG_ON(!(pe->flags & (PNV_IODA_PE_BUS | PNV_IODA_PE_BUS_ALL))); 324623e79425SGavin Shan 324769d733e7SGavin Shan list_for_each_entry(pdev, &pe->pbus->devices, bus_list) { 324869d733e7SGavin Shan for (i = 0; i <= PCI_ROM_RESOURCE; i++) 324969d733e7SGavin Shan pnv_ioda_setup_pe_res(pe, &pdev->resource[i]); 325069d733e7SGavin Shan 325169d733e7SGavin Shan /* 325269d733e7SGavin Shan * If the PE contains all subordinate PCI buses, the 325369d733e7SGavin Shan * windows of the child bridges should be mapped to 325469d733e7SGavin Shan * the PE as well. 325569d733e7SGavin Shan */ 325669d733e7SGavin Shan if (!(pe->flags & PNV_IODA_PE_BUS_ALL) || !pci_is_bridge(pdev)) 325769d733e7SGavin Shan continue; 325869d733e7SGavin Shan for (i = 0; i < PCI_BRIDGE_RESOURCE_NUM; i++) 325969d733e7SGavin Shan pnv_ioda_setup_pe_res(pe, 326069d733e7SGavin Shan &pdev->resource[PCI_BRIDGE_RESOURCES + i]); 326169d733e7SGavin Shan } 326211685becSGavin Shan } 326311685becSGavin Shan 326498b665daSRussell Currey #ifdef CONFIG_DEBUG_FS 326598b665daSRussell Currey static int pnv_pci_diag_data_set(void *data, u64 val) 326698b665daSRussell Currey { 326798b665daSRussell Currey struct pci_controller *hose; 326898b665daSRussell Currey struct pnv_phb *phb; 326998b665daSRussell Currey s64 ret; 327098b665daSRussell Currey 327198b665daSRussell Currey if (val != 1ULL) 327298b665daSRussell Currey return -EINVAL; 327398b665daSRussell Currey 327498b665daSRussell Currey hose = (struct pci_controller *)data; 327598b665daSRussell Currey if (!hose || !hose->private_data) 327698b665daSRussell Currey return -ENODEV; 327798b665daSRussell Currey 327898b665daSRussell Currey phb = hose->private_data; 327998b665daSRussell Currey 328098b665daSRussell Currey /* Retrieve the diag data from firmware */ 32815cb1f8fdSRussell Currey ret = opal_pci_get_phb_diag_data2(phb->opal_id, phb->diag_data, 32825cb1f8fdSRussell Currey phb->diag_data_size); 328398b665daSRussell Currey if (ret != OPAL_SUCCESS) 328498b665daSRussell Currey return -EIO; 328598b665daSRussell Currey 328698b665daSRussell Currey /* Print the diag data to the kernel log */ 32875cb1f8fdSRussell Currey pnv_pci_dump_phb_diag_data(phb->hose, phb->diag_data); 328898b665daSRussell Currey return 0; 328998b665daSRussell Currey } 329098b665daSRussell Currey 329198b665daSRussell Currey DEFINE_SIMPLE_ATTRIBUTE(pnv_pci_diag_data_fops, NULL, 329298b665daSRussell Currey pnv_pci_diag_data_set, "%llu\n"); 329398b665daSRussell Currey 329498b665daSRussell Currey #endif /* CONFIG_DEBUG_FS */ 329598b665daSRussell Currey 329637c367f2SGavin Shan static void pnv_pci_ioda_create_dbgfs(void) 329737c367f2SGavin Shan { 329837c367f2SGavin Shan #ifdef CONFIG_DEBUG_FS 329937c367f2SGavin Shan struct pci_controller *hose, *tmp; 330037c367f2SGavin Shan struct pnv_phb *phb; 330137c367f2SGavin Shan char name[16]; 330237c367f2SGavin Shan 330337c367f2SGavin Shan list_for_each_entry_safe(hose, tmp, &hose_list, list_node) { 330437c367f2SGavin Shan phb = hose->private_data; 330537c367f2SGavin Shan 3306ccd1c191SGavin Shan /* Notify initialization of PHB done */ 3307ccd1c191SGavin Shan phb->initialized = 1; 3308ccd1c191SGavin Shan 330937c367f2SGavin Shan sprintf(name, "PCI%04x", hose->global_number); 331037c367f2SGavin Shan phb->dbgfs = debugfs_create_dir(name, powerpc_debugfs_root); 331198b665daSRussell Currey if (!phb->dbgfs) { 3312f2c2cbccSJoe Perches pr_warn("%s: Error on creating debugfs on PHB#%x\n", 331337c367f2SGavin Shan __func__, hose->global_number); 331498b665daSRussell Currey continue; 331598b665daSRussell Currey } 331698b665daSRussell Currey 331798b665daSRussell Currey debugfs_create_file("dump_diag_regs", 0200, phb->dbgfs, hose, 331898b665daSRussell Currey &pnv_pci_diag_data_fops); 331937c367f2SGavin Shan } 332037c367f2SGavin Shan #endif /* CONFIG_DEBUG_FS */ 332137c367f2SGavin Shan } 332237c367f2SGavin Shan 3323cad5cef6SGreg Kroah-Hartman static void pnv_pci_ioda_fixup(void) 3324fb446ad0SGavin Shan { 3325fb446ad0SGavin Shan pnv_pci_ioda_setup_PEs(); 3326ccd1c191SGavin Shan pnv_pci_ioda_setup_iommu_api(); 332737c367f2SGavin Shan pnv_pci_ioda_create_dbgfs(); 332837c367f2SGavin Shan 3329e9cc17d4SGavin Shan #ifdef CONFIG_EEH 3330b9fde58dSBenjamin Herrenschmidt pnv_eeh_post_init(); 3331e9cc17d4SGavin Shan #endif 3332fb446ad0SGavin Shan } 3333fb446ad0SGavin Shan 3334271fd03aSGavin Shan /* 3335271fd03aSGavin Shan * Returns the alignment for I/O or memory windows for P2P 3336271fd03aSGavin Shan * bridges. That actually depends on how PEs are segmented. 3337271fd03aSGavin Shan * For now, we return I/O or M32 segment size for PE sensitive 3338271fd03aSGavin Shan * P2P bridges. Otherwise, the default values (4KiB for I/O, 3339271fd03aSGavin Shan * 1MiB for memory) will be returned. 3340271fd03aSGavin Shan * 3341271fd03aSGavin Shan * The current PCI bus might be put into one PE, which was 3342271fd03aSGavin Shan * create against the parent PCI bridge. For that case, we 3343271fd03aSGavin Shan * needn't enlarge the alignment so that we can save some 3344271fd03aSGavin Shan * resources. 3345271fd03aSGavin Shan */ 3346271fd03aSGavin Shan static resource_size_t pnv_pci_window_alignment(struct pci_bus *bus, 3347271fd03aSGavin Shan unsigned long type) 3348271fd03aSGavin Shan { 3349271fd03aSGavin Shan struct pci_dev *bridge; 3350271fd03aSGavin Shan struct pci_controller *hose = pci_bus_to_host(bus); 3351271fd03aSGavin Shan struct pnv_phb *phb = hose->private_data; 3352271fd03aSGavin Shan int num_pci_bridges = 0; 3353271fd03aSGavin Shan 3354271fd03aSGavin Shan bridge = bus->self; 3355271fd03aSGavin Shan while (bridge) { 3356271fd03aSGavin Shan if (pci_pcie_type(bridge) == PCI_EXP_TYPE_PCI_BRIDGE) { 3357271fd03aSGavin Shan num_pci_bridges++; 3358271fd03aSGavin Shan if (num_pci_bridges >= 2) 3359271fd03aSGavin Shan return 1; 3360271fd03aSGavin Shan } 3361271fd03aSGavin Shan 3362271fd03aSGavin Shan bridge = bridge->bus->self; 3363271fd03aSGavin Shan } 3364271fd03aSGavin Shan 33655958d19aSBenjamin Herrenschmidt /* 33665958d19aSBenjamin Herrenschmidt * We fall back to M32 if M64 isn't supported. We enforce the M64 33675958d19aSBenjamin Herrenschmidt * alignment for any 64-bit resource, PCIe doesn't care and 33685958d19aSBenjamin Herrenschmidt * bridges only do 64-bit prefetchable anyway. 33695958d19aSBenjamin Herrenschmidt */ 3370b79331a5SRussell Currey if (phb->ioda.m64_segsize && pnv_pci_is_m64_flags(type)) 3371262af557SGuo Chao return phb->ioda.m64_segsize; 3372271fd03aSGavin Shan if (type & IORESOURCE_MEM) 3373271fd03aSGavin Shan return phb->ioda.m32_segsize; 3374271fd03aSGavin Shan 3375271fd03aSGavin Shan return phb->ioda.io_segsize; 3376271fd03aSGavin Shan } 3377271fd03aSGavin Shan 337840e2a47eSGavin Shan /* 337940e2a47eSGavin Shan * We are updating root port or the upstream port of the 338040e2a47eSGavin Shan * bridge behind the root port with PHB's windows in order 338140e2a47eSGavin Shan * to accommodate the changes on required resources during 338240e2a47eSGavin Shan * PCI (slot) hotplug, which is connected to either root 338340e2a47eSGavin Shan * port or the downstream ports of PCIe switch behind the 338440e2a47eSGavin Shan * root port. 338540e2a47eSGavin Shan */ 338640e2a47eSGavin Shan static void pnv_pci_fixup_bridge_resources(struct pci_bus *bus, 338740e2a47eSGavin Shan unsigned long type) 338840e2a47eSGavin Shan { 338940e2a47eSGavin Shan struct pci_controller *hose = pci_bus_to_host(bus); 339040e2a47eSGavin Shan struct pnv_phb *phb = hose->private_data; 339140e2a47eSGavin Shan struct pci_dev *bridge = bus->self; 339240e2a47eSGavin Shan struct resource *r, *w; 339340e2a47eSGavin Shan bool msi_region = false; 339440e2a47eSGavin Shan int i; 339540e2a47eSGavin Shan 339640e2a47eSGavin Shan /* Check if we need apply fixup to the bridge's windows */ 339740e2a47eSGavin Shan if (!pci_is_root_bus(bridge->bus) && 339840e2a47eSGavin Shan !pci_is_root_bus(bridge->bus->self->bus)) 339940e2a47eSGavin Shan return; 340040e2a47eSGavin Shan 340140e2a47eSGavin Shan /* Fixup the resources */ 340240e2a47eSGavin Shan for (i = 0; i < PCI_BRIDGE_RESOURCE_NUM; i++) { 340340e2a47eSGavin Shan r = &bridge->resource[PCI_BRIDGE_RESOURCES + i]; 340440e2a47eSGavin Shan if (!r->flags || !r->parent) 340540e2a47eSGavin Shan continue; 340640e2a47eSGavin Shan 340740e2a47eSGavin Shan w = NULL; 340840e2a47eSGavin Shan if (r->flags & type & IORESOURCE_IO) 340940e2a47eSGavin Shan w = &hose->io_resource; 34105958d19aSBenjamin Herrenschmidt else if (pnv_pci_is_m64(phb, r) && 341140e2a47eSGavin Shan (type & IORESOURCE_PREFETCH) && 341240e2a47eSGavin Shan phb->ioda.m64_segsize) 341340e2a47eSGavin Shan w = &hose->mem_resources[1]; 341440e2a47eSGavin Shan else if (r->flags & type & IORESOURCE_MEM) { 341540e2a47eSGavin Shan w = &hose->mem_resources[0]; 341640e2a47eSGavin Shan msi_region = true; 341740e2a47eSGavin Shan } 341840e2a47eSGavin Shan 341940e2a47eSGavin Shan r->start = w->start; 342040e2a47eSGavin Shan r->end = w->end; 342140e2a47eSGavin Shan 342240e2a47eSGavin Shan /* The 64KB 32-bits MSI region shouldn't be included in 342340e2a47eSGavin Shan * the 32-bits bridge window. Otherwise, we can see strange 342440e2a47eSGavin Shan * issues. One of them is EEH error observed on Garrison. 342540e2a47eSGavin Shan * 342640e2a47eSGavin Shan * Exclude top 1MB region which is the minimal alignment of 342740e2a47eSGavin Shan * 32-bits bridge window. 342840e2a47eSGavin Shan */ 342940e2a47eSGavin Shan if (msi_region) { 343040e2a47eSGavin Shan r->end += 0x10000; 343140e2a47eSGavin Shan r->end -= 0x100000; 343240e2a47eSGavin Shan } 343340e2a47eSGavin Shan } 343440e2a47eSGavin Shan } 343540e2a47eSGavin Shan 3436ccd1c191SGavin Shan static void pnv_pci_setup_bridge(struct pci_bus *bus, unsigned long type) 3437ccd1c191SGavin Shan { 3438ccd1c191SGavin Shan struct pci_controller *hose = pci_bus_to_host(bus); 3439ccd1c191SGavin Shan struct pnv_phb *phb = hose->private_data; 3440ccd1c191SGavin Shan struct pci_dev *bridge = bus->self; 3441ccd1c191SGavin Shan struct pnv_ioda_pe *pe; 3442ccd1c191SGavin Shan bool all = (pci_pcie_type(bridge) == PCI_EXP_TYPE_PCI_BRIDGE); 3443ccd1c191SGavin Shan 344440e2a47eSGavin Shan /* Extend bridge's windows if necessary */ 344540e2a47eSGavin Shan pnv_pci_fixup_bridge_resources(bus, type); 344640e2a47eSGavin Shan 344763803c39SGavin Shan /* The PE for root bus should be realized before any one else */ 344863803c39SGavin Shan if (!phb->ioda.root_pe_populated) { 344963803c39SGavin Shan pe = pnv_ioda_setup_bus_PE(phb->hose->bus, false); 345063803c39SGavin Shan if (pe) { 345163803c39SGavin Shan phb->ioda.root_pe_idx = pe->pe_number; 345263803c39SGavin Shan phb->ioda.root_pe_populated = true; 345363803c39SGavin Shan } 345463803c39SGavin Shan } 345563803c39SGavin Shan 3456ccd1c191SGavin Shan /* Don't assign PE to PCI bus, which doesn't have subordinate devices */ 3457ccd1c191SGavin Shan if (list_empty(&bus->devices)) 3458ccd1c191SGavin Shan return; 3459ccd1c191SGavin Shan 3460ccd1c191SGavin Shan /* Reserve PEs according to used M64 resources */ 3461ccd1c191SGavin Shan if (phb->reserve_m64_pe) 3462ccd1c191SGavin Shan phb->reserve_m64_pe(bus, NULL, all); 3463ccd1c191SGavin Shan 3464ccd1c191SGavin Shan /* 3465ccd1c191SGavin Shan * Assign PE. We might run here because of partial hotplug. 3466ccd1c191SGavin Shan * For the case, we just pick up the existing PE and should 3467ccd1c191SGavin Shan * not allocate resources again. 3468ccd1c191SGavin Shan */ 3469ccd1c191SGavin Shan pe = pnv_ioda_setup_bus_PE(bus, all); 3470ccd1c191SGavin Shan if (!pe) 3471ccd1c191SGavin Shan return; 3472ccd1c191SGavin Shan 3473ccd1c191SGavin Shan pnv_ioda_setup_pe_seg(pe); 3474ccd1c191SGavin Shan switch (phb->type) { 3475ccd1c191SGavin Shan case PNV_PHB_IODA1: 3476ccd1c191SGavin Shan pnv_pci_ioda1_setup_dma_pe(phb, pe); 3477ccd1c191SGavin Shan break; 3478ccd1c191SGavin Shan case PNV_PHB_IODA2: 3479ccd1c191SGavin Shan pnv_pci_ioda2_setup_dma_pe(phb, pe); 3480ccd1c191SGavin Shan break; 3481ccd1c191SGavin Shan default: 34821f52f176SRussell Currey pr_warn("%s: No DMA for PHB#%x (type %d)\n", 3483ccd1c191SGavin Shan __func__, phb->hose->global_number, phb->type); 3484ccd1c191SGavin Shan } 3485ccd1c191SGavin Shan } 3486ccd1c191SGavin Shan 348738274637SYongji Xie static resource_size_t pnv_pci_default_alignment(void) 348838274637SYongji Xie { 348938274637SYongji Xie return PAGE_SIZE; 349038274637SYongji Xie } 349138274637SYongji Xie 34925350ab3fSWei Yang #ifdef CONFIG_PCI_IOV 34935350ab3fSWei Yang static resource_size_t pnv_pci_iov_resource_alignment(struct pci_dev *pdev, 34945350ab3fSWei Yang int resno) 34955350ab3fSWei Yang { 3496ee8222feSWei Yang struct pci_controller *hose = pci_bus_to_host(pdev->bus); 3497ee8222feSWei Yang struct pnv_phb *phb = hose->private_data; 34985350ab3fSWei Yang struct pci_dn *pdn = pci_get_pdn(pdev); 34997fbe7a93SWei Yang resource_size_t align; 35005350ab3fSWei Yang 35017fbe7a93SWei Yang /* 35027fbe7a93SWei Yang * On PowerNV platform, IOV BAR is mapped by M64 BAR to enable the 35037fbe7a93SWei Yang * SR-IOV. While from hardware perspective, the range mapped by M64 35047fbe7a93SWei Yang * BAR should be size aligned. 35057fbe7a93SWei Yang * 3506ee8222feSWei Yang * When IOV BAR is mapped with M64 BAR in Single PE mode, the extra 3507ee8222feSWei Yang * powernv-specific hardware restriction is gone. But if just use the 3508ee8222feSWei Yang * VF BAR size as the alignment, PF BAR / VF BAR may be allocated with 3509ee8222feSWei Yang * in one segment of M64 #15, which introduces the PE conflict between 3510ee8222feSWei Yang * PF and VF. Based on this, the minimum alignment of an IOV BAR is 3511ee8222feSWei Yang * m64_segsize. 3512ee8222feSWei Yang * 35137fbe7a93SWei Yang * This function returns the total IOV BAR size if M64 BAR is in 35147fbe7a93SWei Yang * Shared PE mode or just VF BAR size if not. 3515ee8222feSWei Yang * If the M64 BAR is in Single PE mode, return the VF BAR size or 3516ee8222feSWei Yang * M64 segment size if IOV BAR size is less. 35177fbe7a93SWei Yang */ 35185350ab3fSWei Yang align = pci_iov_resource_size(pdev, resno); 35197fbe7a93SWei Yang if (!pdn->vfs_expanded) 35205350ab3fSWei Yang return align; 3521ee8222feSWei Yang if (pdn->m64_single_mode) 3522ee8222feSWei Yang return max(align, (resource_size_t)phb->ioda.m64_segsize); 35237fbe7a93SWei Yang 35247fbe7a93SWei Yang return pdn->vfs_expanded * align; 35255350ab3fSWei Yang } 35265350ab3fSWei Yang #endif /* CONFIG_PCI_IOV */ 35275350ab3fSWei Yang 3528184cd4a3SBenjamin Herrenschmidt /* Prevent enabling devices for which we couldn't properly 3529184cd4a3SBenjamin Herrenschmidt * assign a PE 3530184cd4a3SBenjamin Herrenschmidt */ 35314361b034SIan Munsie bool pnv_pci_enable_device_hook(struct pci_dev *dev) 3532184cd4a3SBenjamin Herrenschmidt { 3533db1266c8SGavin Shan struct pci_controller *hose = pci_bus_to_host(dev->bus); 3534db1266c8SGavin Shan struct pnv_phb *phb = hose->private_data; 3535db1266c8SGavin Shan struct pci_dn *pdn; 3536184cd4a3SBenjamin Herrenschmidt 3537db1266c8SGavin Shan /* The function is probably called while the PEs have 3538db1266c8SGavin Shan * not be created yet. For example, resource reassignment 3539db1266c8SGavin Shan * during PCI probe period. We just skip the check if 3540db1266c8SGavin Shan * PEs isn't ready. 3541db1266c8SGavin Shan */ 3542db1266c8SGavin Shan if (!phb->initialized) 3543c88c2a18SDaniel Axtens return true; 3544db1266c8SGavin Shan 3545b72c1f65SBenjamin Herrenschmidt pdn = pci_get_pdn(dev); 3546184cd4a3SBenjamin Herrenschmidt if (!pdn || pdn->pe_number == IODA_INVALID_PE) 3547c88c2a18SDaniel Axtens return false; 3548db1266c8SGavin Shan 3549c88c2a18SDaniel Axtens return true; 3550184cd4a3SBenjamin Herrenschmidt } 3551184cd4a3SBenjamin Herrenschmidt 3552c5f7700bSGavin Shan static long pnv_pci_ioda1_unset_window(struct iommu_table_group *table_group, 3553c5f7700bSGavin Shan int num) 3554c5f7700bSGavin Shan { 3555c5f7700bSGavin Shan struct pnv_ioda_pe *pe = container_of(table_group, 3556c5f7700bSGavin Shan struct pnv_ioda_pe, table_group); 3557c5f7700bSGavin Shan struct pnv_phb *phb = pe->phb; 3558c5f7700bSGavin Shan unsigned int idx; 3559c5f7700bSGavin Shan long rc; 3560c5f7700bSGavin Shan 3561c5f7700bSGavin Shan pe_info(pe, "Removing DMA window #%d\n", num); 3562c5f7700bSGavin Shan for (idx = 0; idx < phb->ioda.dma32_count; idx++) { 3563c5f7700bSGavin Shan if (phb->ioda.dma32_segmap[idx] != pe->pe_number) 3564c5f7700bSGavin Shan continue; 3565c5f7700bSGavin Shan 3566c5f7700bSGavin Shan rc = opal_pci_map_pe_dma_window(phb->opal_id, pe->pe_number, 3567c5f7700bSGavin Shan idx, 0, 0ul, 0ul, 0ul); 3568c5f7700bSGavin Shan if (rc != OPAL_SUCCESS) { 3569c5f7700bSGavin Shan pe_warn(pe, "Failure %ld unmapping DMA32 segment#%d\n", 3570c5f7700bSGavin Shan rc, idx); 3571c5f7700bSGavin Shan return rc; 3572c5f7700bSGavin Shan } 3573c5f7700bSGavin Shan 3574c5f7700bSGavin Shan phb->ioda.dma32_segmap[idx] = IODA_INVALID_PE; 3575c5f7700bSGavin Shan } 3576c5f7700bSGavin Shan 3577c5f7700bSGavin Shan pnv_pci_unlink_table_and_group(table_group->tables[num], table_group); 3578c5f7700bSGavin Shan return OPAL_SUCCESS; 3579c5f7700bSGavin Shan } 3580c5f7700bSGavin Shan 3581c5f7700bSGavin Shan static void pnv_pci_ioda1_release_pe_dma(struct pnv_ioda_pe *pe) 3582c5f7700bSGavin Shan { 3583c5f7700bSGavin Shan unsigned int weight = pnv_pci_ioda_pe_dma_weight(pe); 3584c5f7700bSGavin Shan struct iommu_table *tbl = pe->table_group.tables[0]; 3585c5f7700bSGavin Shan int64_t rc; 3586c5f7700bSGavin Shan 3587c5f7700bSGavin Shan if (!weight) 3588c5f7700bSGavin Shan return; 3589c5f7700bSGavin Shan 3590c5f7700bSGavin Shan rc = pnv_pci_ioda1_unset_window(&pe->table_group, 0); 3591c5f7700bSGavin Shan if (rc != OPAL_SUCCESS) 3592c5f7700bSGavin Shan return; 3593c5f7700bSGavin Shan 3594a34ab7c3SBenjamin Herrenschmidt pnv_pci_p7ioc_tce_invalidate(tbl, tbl->it_offset, tbl->it_size, false); 3595c5f7700bSGavin Shan if (pe->table_group.group) { 3596c5f7700bSGavin Shan iommu_group_put(pe->table_group.group); 3597c5f7700bSGavin Shan WARN_ON(pe->table_group.group); 3598c5f7700bSGavin Shan } 3599c5f7700bSGavin Shan 3600c5f7700bSGavin Shan free_pages(tbl->it_base, get_order(tbl->it_size << 3)); 3601e5afdf9dSAlexey Kardashevskiy iommu_tce_table_put(tbl); 3602c5f7700bSGavin Shan } 3603c5f7700bSGavin Shan 3604c5f7700bSGavin Shan static void pnv_pci_ioda2_release_pe_dma(struct pnv_ioda_pe *pe) 3605c5f7700bSGavin Shan { 3606c5f7700bSGavin Shan struct iommu_table *tbl = pe->table_group.tables[0]; 3607c5f7700bSGavin Shan unsigned int weight = pnv_pci_ioda_pe_dma_weight(pe); 3608c5f7700bSGavin Shan #ifdef CONFIG_IOMMU_API 3609c5f7700bSGavin Shan int64_t rc; 3610c5f7700bSGavin Shan #endif 3611c5f7700bSGavin Shan 3612c5f7700bSGavin Shan if (!weight) 3613c5f7700bSGavin Shan return; 3614c5f7700bSGavin Shan 3615c5f7700bSGavin Shan #ifdef CONFIG_IOMMU_API 3616c5f7700bSGavin Shan rc = pnv_pci_ioda2_unset_window(&pe->table_group, 0); 3617c5f7700bSGavin Shan if (rc) 3618c5f7700bSGavin Shan pe_warn(pe, "OPAL error %ld release DMA window\n", rc); 3619c5f7700bSGavin Shan #endif 3620c5f7700bSGavin Shan 3621c5f7700bSGavin Shan pnv_pci_ioda2_set_bypass(pe, false); 3622c5f7700bSGavin Shan if (pe->table_group.group) { 3623c5f7700bSGavin Shan iommu_group_put(pe->table_group.group); 3624c5f7700bSGavin Shan WARN_ON(pe->table_group.group); 3625c5f7700bSGavin Shan } 3626c5f7700bSGavin Shan 3627c5f7700bSGavin Shan pnv_pci_ioda2_table_free_pages(tbl); 3628e5afdf9dSAlexey Kardashevskiy iommu_tce_table_put(tbl); 3629c5f7700bSGavin Shan } 3630c5f7700bSGavin Shan 3631c5f7700bSGavin Shan static void pnv_ioda_free_pe_seg(struct pnv_ioda_pe *pe, 3632c5f7700bSGavin Shan unsigned short win, 3633c5f7700bSGavin Shan unsigned int *map) 3634c5f7700bSGavin Shan { 3635c5f7700bSGavin Shan struct pnv_phb *phb = pe->phb; 3636c5f7700bSGavin Shan int idx; 3637c5f7700bSGavin Shan int64_t rc; 3638c5f7700bSGavin Shan 3639c5f7700bSGavin Shan for (idx = 0; idx < phb->ioda.total_pe_num; idx++) { 3640c5f7700bSGavin Shan if (map[idx] != pe->pe_number) 3641c5f7700bSGavin Shan continue; 3642c5f7700bSGavin Shan 3643c5f7700bSGavin Shan if (win == OPAL_M64_WINDOW_TYPE) 3644c5f7700bSGavin Shan rc = opal_pci_map_pe_mmio_window(phb->opal_id, 3645c5f7700bSGavin Shan phb->ioda.reserved_pe_idx, win, 3646c5f7700bSGavin Shan idx / PNV_IODA1_M64_SEGS, 3647c5f7700bSGavin Shan idx % PNV_IODA1_M64_SEGS); 3648c5f7700bSGavin Shan else 3649c5f7700bSGavin Shan rc = opal_pci_map_pe_mmio_window(phb->opal_id, 3650c5f7700bSGavin Shan phb->ioda.reserved_pe_idx, win, 0, idx); 3651c5f7700bSGavin Shan 3652c5f7700bSGavin Shan if (rc != OPAL_SUCCESS) 3653c5f7700bSGavin Shan pe_warn(pe, "Error %ld unmapping (%d) segment#%d\n", 3654c5f7700bSGavin Shan rc, win, idx); 3655c5f7700bSGavin Shan 3656c5f7700bSGavin Shan map[idx] = IODA_INVALID_PE; 3657c5f7700bSGavin Shan } 3658c5f7700bSGavin Shan } 3659c5f7700bSGavin Shan 3660c5f7700bSGavin Shan static void pnv_ioda_release_pe_seg(struct pnv_ioda_pe *pe) 3661c5f7700bSGavin Shan { 3662c5f7700bSGavin Shan struct pnv_phb *phb = pe->phb; 3663c5f7700bSGavin Shan 3664c5f7700bSGavin Shan if (phb->type == PNV_PHB_IODA1) { 3665c5f7700bSGavin Shan pnv_ioda_free_pe_seg(pe, OPAL_IO_WINDOW_TYPE, 3666c5f7700bSGavin Shan phb->ioda.io_segmap); 3667c5f7700bSGavin Shan pnv_ioda_free_pe_seg(pe, OPAL_M32_WINDOW_TYPE, 3668c5f7700bSGavin Shan phb->ioda.m32_segmap); 3669c5f7700bSGavin Shan pnv_ioda_free_pe_seg(pe, OPAL_M64_WINDOW_TYPE, 3670c5f7700bSGavin Shan phb->ioda.m64_segmap); 3671c5f7700bSGavin Shan } else if (phb->type == PNV_PHB_IODA2) { 3672c5f7700bSGavin Shan pnv_ioda_free_pe_seg(pe, OPAL_M32_WINDOW_TYPE, 3673c5f7700bSGavin Shan phb->ioda.m32_segmap); 3674c5f7700bSGavin Shan } 3675c5f7700bSGavin Shan } 3676c5f7700bSGavin Shan 3677c5f7700bSGavin Shan static void pnv_ioda_release_pe(struct pnv_ioda_pe *pe) 3678c5f7700bSGavin Shan { 3679c5f7700bSGavin Shan struct pnv_phb *phb = pe->phb; 3680c5f7700bSGavin Shan struct pnv_ioda_pe *slave, *tmp; 3681c5f7700bSGavin Shan 3682c5f7700bSGavin Shan list_del(&pe->list); 3683c5f7700bSGavin Shan switch (phb->type) { 3684c5f7700bSGavin Shan case PNV_PHB_IODA1: 3685c5f7700bSGavin Shan pnv_pci_ioda1_release_pe_dma(pe); 3686c5f7700bSGavin Shan break; 3687c5f7700bSGavin Shan case PNV_PHB_IODA2: 3688c5f7700bSGavin Shan pnv_pci_ioda2_release_pe_dma(pe); 3689c5f7700bSGavin Shan break; 3690c5f7700bSGavin Shan default: 3691c5f7700bSGavin Shan WARN_ON(1); 3692c5f7700bSGavin Shan } 3693c5f7700bSGavin Shan 3694c5f7700bSGavin Shan pnv_ioda_release_pe_seg(pe); 3695c5f7700bSGavin Shan pnv_ioda_deconfigure_pe(pe->phb, pe); 3696b314427aSGavin Shan 3697b314427aSGavin Shan /* Release slave PEs in the compound PE */ 3698b314427aSGavin Shan if (pe->flags & PNV_IODA_PE_MASTER) { 3699b314427aSGavin Shan list_for_each_entry_safe(slave, tmp, &pe->slaves, list) { 3700b314427aSGavin Shan list_del(&slave->list); 3701b314427aSGavin Shan pnv_ioda_free_pe(slave); 3702b314427aSGavin Shan } 3703b314427aSGavin Shan } 3704b314427aSGavin Shan 37056eaed166SGavin Shan /* 37066eaed166SGavin Shan * The PE for root bus can be removed because of hotplug in EEH 37076eaed166SGavin Shan * recovery for fenced PHB error. We need to mark the PE dead so 37086eaed166SGavin Shan * that it can be populated again in PCI hot add path. The PE 37096eaed166SGavin Shan * shouldn't be destroyed as it's the global reserved resource. 37106eaed166SGavin Shan */ 37116eaed166SGavin Shan if (phb->ioda.root_pe_populated && 37126eaed166SGavin Shan phb->ioda.root_pe_idx == pe->pe_number) 37136eaed166SGavin Shan phb->ioda.root_pe_populated = false; 37146eaed166SGavin Shan else 3715c5f7700bSGavin Shan pnv_ioda_free_pe(pe); 3716c5f7700bSGavin Shan } 3717c5f7700bSGavin Shan 3718c5f7700bSGavin Shan static void pnv_pci_release_device(struct pci_dev *pdev) 3719c5f7700bSGavin Shan { 3720c5f7700bSGavin Shan struct pci_controller *hose = pci_bus_to_host(pdev->bus); 3721c5f7700bSGavin Shan struct pnv_phb *phb = hose->private_data; 3722c5f7700bSGavin Shan struct pci_dn *pdn = pci_get_pdn(pdev); 3723c5f7700bSGavin Shan struct pnv_ioda_pe *pe; 3724c5f7700bSGavin Shan 3725c5f7700bSGavin Shan if (pdev->is_virtfn) 3726c5f7700bSGavin Shan return; 3727c5f7700bSGavin Shan 3728c5f7700bSGavin Shan if (!pdn || pdn->pe_number == IODA_INVALID_PE) 3729c5f7700bSGavin Shan return; 3730c5f7700bSGavin Shan 373129bf282dSGavin Shan /* 373229bf282dSGavin Shan * PCI hotplug can happen as part of EEH error recovery. The @pdn 373329bf282dSGavin Shan * isn't removed and added afterwards in this scenario. We should 373429bf282dSGavin Shan * set the PE number in @pdn to an invalid one. Otherwise, the PE's 373529bf282dSGavin Shan * device count is decreased on removing devices while failing to 373629bf282dSGavin Shan * be increased on adding devices. It leads to unbalanced PE's device 373729bf282dSGavin Shan * count and eventually make normal PCI hotplug path broken. 373829bf282dSGavin Shan */ 3739c5f7700bSGavin Shan pe = &phb->ioda.pe_array[pdn->pe_number]; 374029bf282dSGavin Shan pdn->pe_number = IODA_INVALID_PE; 374129bf282dSGavin Shan 3742c5f7700bSGavin Shan WARN_ON(--pe->device_count < 0); 3743c5f7700bSGavin Shan if (pe->device_count == 0) 3744c5f7700bSGavin Shan pnv_ioda_release_pe(pe); 3745c5f7700bSGavin Shan } 3746c5f7700bSGavin Shan 37477a8e6bbfSMichael Neuling static void pnv_pci_ioda_shutdown(struct pci_controller *hose) 374873ed148aSBenjamin Herrenschmidt { 37497a8e6bbfSMichael Neuling struct pnv_phb *phb = hose->private_data; 37507a8e6bbfSMichael Neuling 3751d1a85eeeSGavin Shan opal_pci_reset(phb->opal_id, OPAL_RESET_PCI_IODA_TABLE, 375273ed148aSBenjamin Herrenschmidt OPAL_ASSERT_RESET); 375373ed148aSBenjamin Herrenschmidt } 375473ed148aSBenjamin Herrenschmidt 375592ae0353SDaniel Axtens static const struct pci_controller_ops pnv_pci_ioda_controller_ops = { 375692ae0353SDaniel Axtens .dma_dev_setup = pnv_pci_dma_dev_setup, 37571bc74f1cSGavin Shan .dma_bus_setup = pnv_pci_dma_bus_setup, 375892ae0353SDaniel Axtens #ifdef CONFIG_PCI_MSI 375992ae0353SDaniel Axtens .setup_msi_irqs = pnv_setup_msi_irqs, 376092ae0353SDaniel Axtens .teardown_msi_irqs = pnv_teardown_msi_irqs, 376192ae0353SDaniel Axtens #endif 376292ae0353SDaniel Axtens .enable_device_hook = pnv_pci_enable_device_hook, 3763c5f7700bSGavin Shan .release_device = pnv_pci_release_device, 376492ae0353SDaniel Axtens .window_alignment = pnv_pci_window_alignment, 3765ccd1c191SGavin Shan .setup_bridge = pnv_pci_setup_bridge, 376692ae0353SDaniel Axtens .reset_secondary_bus = pnv_pci_reset_secondary_bus, 3767763d2d8dSDaniel Axtens .dma_set_mask = pnv_pci_ioda_dma_set_mask, 376853522982SAndrew Donnellan .dma_get_required_mask = pnv_pci_ioda_dma_get_required_mask, 37697a8e6bbfSMichael Neuling .shutdown = pnv_pci_ioda_shutdown, 377092ae0353SDaniel Axtens }; 377192ae0353SDaniel Axtens 3772f9f83456SAlexey Kardashevskiy static int pnv_npu_dma_set_mask(struct pci_dev *npdev, u64 dma_mask) 3773f9f83456SAlexey Kardashevskiy { 3774f9f83456SAlexey Kardashevskiy dev_err_once(&npdev->dev, 3775f9f83456SAlexey Kardashevskiy "%s operation unsupported for NVLink devices\n", 3776f9f83456SAlexey Kardashevskiy __func__); 3777f9f83456SAlexey Kardashevskiy return -EPERM; 3778f9f83456SAlexey Kardashevskiy } 3779f9f83456SAlexey Kardashevskiy 37805d2aa710SAlistair Popple static const struct pci_controller_ops pnv_npu_ioda_controller_ops = { 37815d2aa710SAlistair Popple .dma_dev_setup = pnv_pci_dma_dev_setup, 37825d2aa710SAlistair Popple #ifdef CONFIG_PCI_MSI 37835d2aa710SAlistair Popple .setup_msi_irqs = pnv_setup_msi_irqs, 37845d2aa710SAlistair Popple .teardown_msi_irqs = pnv_teardown_msi_irqs, 37855d2aa710SAlistair Popple #endif 37865d2aa710SAlistair Popple .enable_device_hook = pnv_pci_enable_device_hook, 37875d2aa710SAlistair Popple .window_alignment = pnv_pci_window_alignment, 37885d2aa710SAlistair Popple .reset_secondary_bus = pnv_pci_reset_secondary_bus, 37895d2aa710SAlistair Popple .dma_set_mask = pnv_npu_dma_set_mask, 37905d2aa710SAlistair Popple .shutdown = pnv_pci_ioda_shutdown, 37915d2aa710SAlistair Popple }; 37925d2aa710SAlistair Popple 37937f2c39e9SFrederic Barrat static const struct pci_controller_ops pnv_npu_ocapi_ioda_controller_ops = { 37947f2c39e9SFrederic Barrat .enable_device_hook = pnv_pci_enable_device_hook, 37957f2c39e9SFrederic Barrat .window_alignment = pnv_pci_window_alignment, 37967f2c39e9SFrederic Barrat .reset_secondary_bus = pnv_pci_reset_secondary_bus, 37977f2c39e9SFrederic Barrat .shutdown = pnv_pci_ioda_shutdown, 37987f2c39e9SFrederic Barrat }; 37997f2c39e9SFrederic Barrat 38004361b034SIan Munsie #ifdef CONFIG_CXL_BASE 38014361b034SIan Munsie const struct pci_controller_ops pnv_cxl_cx4_ioda_controller_ops = { 38024361b034SIan Munsie .dma_dev_setup = pnv_pci_dma_dev_setup, 38034361b034SIan Munsie .dma_bus_setup = pnv_pci_dma_bus_setup, 3804a2f67d5eSIan Munsie #ifdef CONFIG_PCI_MSI 3805a2f67d5eSIan Munsie .setup_msi_irqs = pnv_cxl_cx4_setup_msi_irqs, 3806a2f67d5eSIan Munsie .teardown_msi_irqs = pnv_cxl_cx4_teardown_msi_irqs, 3807a2f67d5eSIan Munsie #endif 38084361b034SIan Munsie .enable_device_hook = pnv_cxl_enable_device_hook, 38094361b034SIan Munsie .disable_device = pnv_cxl_disable_device, 38104361b034SIan Munsie .release_device = pnv_pci_release_device, 38114361b034SIan Munsie .window_alignment = pnv_pci_window_alignment, 38124361b034SIan Munsie .setup_bridge = pnv_pci_setup_bridge, 38134361b034SIan Munsie .reset_secondary_bus = pnv_pci_reset_secondary_bus, 38144361b034SIan Munsie .dma_set_mask = pnv_pci_ioda_dma_set_mask, 38154361b034SIan Munsie .dma_get_required_mask = pnv_pci_ioda_dma_get_required_mask, 38164361b034SIan Munsie .shutdown = pnv_pci_ioda_shutdown, 38174361b034SIan Munsie }; 38184361b034SIan Munsie #endif 38194361b034SIan Munsie 3820e51df2c1SAnton Blanchard static void __init pnv_pci_init_ioda_phb(struct device_node *np, 3821e9cc17d4SGavin Shan u64 hub_id, int ioda_type) 3822184cd4a3SBenjamin Herrenschmidt { 3823184cd4a3SBenjamin Herrenschmidt struct pci_controller *hose; 3824184cd4a3SBenjamin Herrenschmidt struct pnv_phb *phb; 38252b923ed1SGavin Shan unsigned long size, m64map_off, m32map_off, pemap_off; 38262b923ed1SGavin Shan unsigned long iomap_off = 0, dma32map_off = 0; 3827fd141d1aSBenjamin Herrenschmidt struct resource r; 3828c681b93cSAlistair Popple const __be64 *prop64; 38293a1a4661SBenjamin Herrenschmidt const __be32 *prop32; 3830f1b7cc3eSGavin Shan int len; 38313fa23ff8SGavin Shan unsigned int segno; 3832184cd4a3SBenjamin Herrenschmidt u64 phb_id; 3833184cd4a3SBenjamin Herrenschmidt void *aux; 3834184cd4a3SBenjamin Herrenschmidt long rc; 3835184cd4a3SBenjamin Herrenschmidt 383608a45b32SBenjamin Herrenschmidt if (!of_device_is_available(np)) 383708a45b32SBenjamin Herrenschmidt return; 383808a45b32SBenjamin Herrenschmidt 3839b7c670d6SRob Herring pr_info("Initializing %s PHB (%pOF)\n", pnv_phb_names[ioda_type], np); 3840184cd4a3SBenjamin Herrenschmidt 3841184cd4a3SBenjamin Herrenschmidt prop64 = of_get_property(np, "ibm,opal-phbid", NULL); 3842184cd4a3SBenjamin Herrenschmidt if (!prop64) { 3843184cd4a3SBenjamin Herrenschmidt pr_err(" Missing \"ibm,opal-phbid\" property !\n"); 3844184cd4a3SBenjamin Herrenschmidt return; 3845184cd4a3SBenjamin Herrenschmidt } 3846184cd4a3SBenjamin Herrenschmidt phb_id = be64_to_cpup(prop64); 3847184cd4a3SBenjamin Herrenschmidt pr_debug(" PHB-ID : 0x%016llx\n", phb_id); 3848184cd4a3SBenjamin Herrenschmidt 3849e39f223fSMichael Ellerman phb = memblock_virt_alloc(sizeof(struct pnv_phb), 0); 385058d714ecSGavin Shan 385158d714ecSGavin Shan /* Allocate PCI controller */ 3852184cd4a3SBenjamin Herrenschmidt phb->hose = hose = pcibios_alloc_controller(np); 385358d714ecSGavin Shan if (!phb->hose) { 3854b7c670d6SRob Herring pr_err(" Can't allocate PCI controller for %pOF\n", 3855b7c670d6SRob Herring np); 3856e39f223fSMichael Ellerman memblock_free(__pa(phb), sizeof(struct pnv_phb)); 3857184cd4a3SBenjamin Herrenschmidt return; 3858184cd4a3SBenjamin Herrenschmidt } 3859184cd4a3SBenjamin Herrenschmidt 3860184cd4a3SBenjamin Herrenschmidt spin_lock_init(&phb->lock); 3861f1b7cc3eSGavin Shan prop32 = of_get_property(np, "bus-range", &len); 3862f1b7cc3eSGavin Shan if (prop32 && len == 8) { 38633a1a4661SBenjamin Herrenschmidt hose->first_busno = be32_to_cpu(prop32[0]); 38643a1a4661SBenjamin Herrenschmidt hose->last_busno = be32_to_cpu(prop32[1]); 3865f1b7cc3eSGavin Shan } else { 3866b7c670d6SRob Herring pr_warn(" Broken <bus-range> on %pOF\n", np); 3867184cd4a3SBenjamin Herrenschmidt hose->first_busno = 0; 3868184cd4a3SBenjamin Herrenschmidt hose->last_busno = 0xff; 3869f1b7cc3eSGavin Shan } 3870184cd4a3SBenjamin Herrenschmidt hose->private_data = phb; 3871e9cc17d4SGavin Shan phb->hub_id = hub_id; 3872184cd4a3SBenjamin Herrenschmidt phb->opal_id = phb_id; 3873aa0c033fSGavin Shan phb->type = ioda_type; 3874781a868fSWei Yang mutex_init(&phb->ioda.pe_alloc_mutex); 3875184cd4a3SBenjamin Herrenschmidt 3876cee72d5bSBenjamin Herrenschmidt /* Detect specific models for error handling */ 3877cee72d5bSBenjamin Herrenschmidt if (of_device_is_compatible(np, "ibm,p7ioc-pciex")) 3878cee72d5bSBenjamin Herrenschmidt phb->model = PNV_PHB_MODEL_P7IOC; 3879f3d40c25SBenjamin Herrenschmidt else if (of_device_is_compatible(np, "ibm,power8-pciex")) 3880aa0c033fSGavin Shan phb->model = PNV_PHB_MODEL_PHB3; 38815d2aa710SAlistair Popple else if (of_device_is_compatible(np, "ibm,power8-npu-pciex")) 38825d2aa710SAlistair Popple phb->model = PNV_PHB_MODEL_NPU; 3883616badd2SAlistair Popple else if (of_device_is_compatible(np, "ibm,power9-npu-pciex")) 3884616badd2SAlistair Popple phb->model = PNV_PHB_MODEL_NPU2; 3885cee72d5bSBenjamin Herrenschmidt else 3886cee72d5bSBenjamin Herrenschmidt phb->model = PNV_PHB_MODEL_UNKNOWN; 3887cee72d5bSBenjamin Herrenschmidt 38885cb1f8fdSRussell Currey /* Initialize diagnostic data buffer */ 38895cb1f8fdSRussell Currey prop32 = of_get_property(np, "ibm,phb-diag-data-size", NULL); 38905cb1f8fdSRussell Currey if (prop32) 38915cb1f8fdSRussell Currey phb->diag_data_size = be32_to_cpup(prop32); 38925cb1f8fdSRussell Currey else 38935cb1f8fdSRussell Currey phb->diag_data_size = PNV_PCI_DIAG_BUF_SIZE; 38945cb1f8fdSRussell Currey 38955cb1f8fdSRussell Currey phb->diag_data = memblock_virt_alloc(phb->diag_data_size, 0); 38965cb1f8fdSRussell Currey 3897aa0c033fSGavin Shan /* Parse 32-bit and IO ranges (if any) */ 38982f1ec02eSGavin Shan pci_process_bridge_OF_ranges(hose, np, !hose->global_number); 3899184cd4a3SBenjamin Herrenschmidt 3900aa0c033fSGavin Shan /* Get registers */ 3901fd141d1aSBenjamin Herrenschmidt if (!of_address_to_resource(np, 0, &r)) { 3902fd141d1aSBenjamin Herrenschmidt phb->regs_phys = r.start; 3903fd141d1aSBenjamin Herrenschmidt phb->regs = ioremap(r.start, resource_size(&r)); 3904184cd4a3SBenjamin Herrenschmidt if (phb->regs == NULL) 3905184cd4a3SBenjamin Herrenschmidt pr_err(" Failed to map registers !\n"); 3906fd141d1aSBenjamin Herrenschmidt } 3907577c8c88SGavin Shan 3908184cd4a3SBenjamin Herrenschmidt /* Initialize more IODA stuff */ 390992b8f137SGavin Shan phb->ioda.total_pe_num = 1; 391036954dc7SGavin Shan prop32 = of_get_property(np, "ibm,opal-num-pes", NULL); 391136954dc7SGavin Shan if (prop32) 391292b8f137SGavin Shan phb->ioda.total_pe_num = be32_to_cpup(prop32); 391336954dc7SGavin Shan prop32 = of_get_property(np, "ibm,opal-reserved-pe", NULL); 391436954dc7SGavin Shan if (prop32) 391592b8f137SGavin Shan phb->ioda.reserved_pe_idx = be32_to_cpup(prop32); 3916262af557SGuo Chao 3917c127562aSGavin Shan /* Invalidate RID to PE# mapping */ 3918c127562aSGavin Shan for (segno = 0; segno < ARRAY_SIZE(phb->ioda.pe_rmap); segno++) 3919c127562aSGavin Shan phb->ioda.pe_rmap[segno] = IODA_INVALID_PE; 3920c127562aSGavin Shan 3921262af557SGuo Chao /* Parse 64-bit MMIO range */ 3922262af557SGuo Chao pnv_ioda_parse_m64_window(phb); 3923262af557SGuo Chao 3924184cd4a3SBenjamin Herrenschmidt phb->ioda.m32_size = resource_size(&hose->mem_resources[0]); 3925aa0c033fSGavin Shan /* FW Has already off top 64k of M32 space (MSI space) */ 3926184cd4a3SBenjamin Herrenschmidt phb->ioda.m32_size += 0x10000; 3927184cd4a3SBenjamin Herrenschmidt 392892b8f137SGavin Shan phb->ioda.m32_segsize = phb->ioda.m32_size / phb->ioda.total_pe_num; 39293fd47f06SBenjamin Herrenschmidt phb->ioda.m32_pci_base = hose->mem_resources[0].start - hose->mem_offset[0]; 3930184cd4a3SBenjamin Herrenschmidt phb->ioda.io_size = hose->pci_io_size; 393192b8f137SGavin Shan phb->ioda.io_segsize = phb->ioda.io_size / phb->ioda.total_pe_num; 3932184cd4a3SBenjamin Herrenschmidt phb->ioda.io_pci_base = 0; /* XXX calculate this ? */ 3933184cd4a3SBenjamin Herrenschmidt 39342b923ed1SGavin Shan /* Calculate how many 32-bit TCE segments we have */ 39352b923ed1SGavin Shan phb->ioda.dma32_count = phb->ioda.m32_pci_base / 39362b923ed1SGavin Shan PNV_IODA1_DMA32_SEGSIZE; 39372b923ed1SGavin Shan 3938c35d2a8cSGavin Shan /* Allocate aux data & arrays. We don't have IO ports on PHB3 */ 393992a86756SAlexey Kardashevskiy size = _ALIGN_UP(max_t(unsigned, phb->ioda.total_pe_num, 8) / 8, 394092a86756SAlexey Kardashevskiy sizeof(unsigned long)); 394193289d8cSGavin Shan m64map_off = size; 394293289d8cSGavin Shan size += phb->ioda.total_pe_num * sizeof(phb->ioda.m64_segmap[0]); 3943184cd4a3SBenjamin Herrenschmidt m32map_off = size; 394492b8f137SGavin Shan size += phb->ioda.total_pe_num * sizeof(phb->ioda.m32_segmap[0]); 3945c35d2a8cSGavin Shan if (phb->type == PNV_PHB_IODA1) { 3946c35d2a8cSGavin Shan iomap_off = size; 394792b8f137SGavin Shan size += phb->ioda.total_pe_num * sizeof(phb->ioda.io_segmap[0]); 39482b923ed1SGavin Shan dma32map_off = size; 39492b923ed1SGavin Shan size += phb->ioda.dma32_count * 39502b923ed1SGavin Shan sizeof(phb->ioda.dma32_segmap[0]); 3951c35d2a8cSGavin Shan } 3952184cd4a3SBenjamin Herrenschmidt pemap_off = size; 395392b8f137SGavin Shan size += phb->ioda.total_pe_num * sizeof(struct pnv_ioda_pe); 3954e39f223fSMichael Ellerman aux = memblock_virt_alloc(size, 0); 3955184cd4a3SBenjamin Herrenschmidt phb->ioda.pe_alloc = aux; 395693289d8cSGavin Shan phb->ioda.m64_segmap = aux + m64map_off; 3957184cd4a3SBenjamin Herrenschmidt phb->ioda.m32_segmap = aux + m32map_off; 395893289d8cSGavin Shan for (segno = 0; segno < phb->ioda.total_pe_num; segno++) { 395993289d8cSGavin Shan phb->ioda.m64_segmap[segno] = IODA_INVALID_PE; 39603fa23ff8SGavin Shan phb->ioda.m32_segmap[segno] = IODA_INVALID_PE; 396193289d8cSGavin Shan } 39623fa23ff8SGavin Shan if (phb->type == PNV_PHB_IODA1) { 3963184cd4a3SBenjamin Herrenschmidt phb->ioda.io_segmap = aux + iomap_off; 39643fa23ff8SGavin Shan for (segno = 0; segno < phb->ioda.total_pe_num; segno++) 39653fa23ff8SGavin Shan phb->ioda.io_segmap[segno] = IODA_INVALID_PE; 39662b923ed1SGavin Shan 39672b923ed1SGavin Shan phb->ioda.dma32_segmap = aux + dma32map_off; 39682b923ed1SGavin Shan for (segno = 0; segno < phb->ioda.dma32_count; segno++) 39692b923ed1SGavin Shan phb->ioda.dma32_segmap[segno] = IODA_INVALID_PE; 39703fa23ff8SGavin Shan } 3971184cd4a3SBenjamin Herrenschmidt phb->ioda.pe_array = aux + pemap_off; 397263803c39SGavin Shan 397363803c39SGavin Shan /* 397463803c39SGavin Shan * Choose PE number for root bus, which shouldn't have 397563803c39SGavin Shan * M64 resources consumed by its child devices. To pick 397663803c39SGavin Shan * the PE number adjacent to the reserved one if possible. 397763803c39SGavin Shan */ 397863803c39SGavin Shan pnv_ioda_reserve_pe(phb, phb->ioda.reserved_pe_idx); 397963803c39SGavin Shan if (phb->ioda.reserved_pe_idx == 0) { 398063803c39SGavin Shan phb->ioda.root_pe_idx = 1; 398163803c39SGavin Shan pnv_ioda_reserve_pe(phb, phb->ioda.root_pe_idx); 398263803c39SGavin Shan } else if (phb->ioda.reserved_pe_idx == (phb->ioda.total_pe_num - 1)) { 398363803c39SGavin Shan phb->ioda.root_pe_idx = phb->ioda.reserved_pe_idx - 1; 398463803c39SGavin Shan pnv_ioda_reserve_pe(phb, phb->ioda.root_pe_idx); 398563803c39SGavin Shan } else { 398663803c39SGavin Shan phb->ioda.root_pe_idx = IODA_INVALID_PE; 398763803c39SGavin Shan } 3988184cd4a3SBenjamin Herrenschmidt 3989184cd4a3SBenjamin Herrenschmidt INIT_LIST_HEAD(&phb->ioda.pe_list); 3990781a868fSWei Yang mutex_init(&phb->ioda.pe_list_mutex); 3991184cd4a3SBenjamin Herrenschmidt 3992184cd4a3SBenjamin Herrenschmidt /* Calculate how many 32-bit TCE segments we have */ 39932b923ed1SGavin Shan phb->ioda.dma32_count = phb->ioda.m32_pci_base / 3994acce971cSGavin Shan PNV_IODA1_DMA32_SEGSIZE; 3995184cd4a3SBenjamin Herrenschmidt 3996aa0c033fSGavin Shan #if 0 /* We should really do that ... */ 3997184cd4a3SBenjamin Herrenschmidt rc = opal_pci_set_phb_mem_window(opal->phb_id, 3998184cd4a3SBenjamin Herrenschmidt window_type, 3999184cd4a3SBenjamin Herrenschmidt window_num, 4000184cd4a3SBenjamin Herrenschmidt starting_real_address, 4001184cd4a3SBenjamin Herrenschmidt starting_pci_address, 4002184cd4a3SBenjamin Herrenschmidt segment_size); 4003184cd4a3SBenjamin Herrenschmidt #endif 4004184cd4a3SBenjamin Herrenschmidt 4005262af557SGuo Chao pr_info(" %03d (%03d) PE's M32: 0x%x [segment=0x%x]\n", 400692b8f137SGavin Shan phb->ioda.total_pe_num, phb->ioda.reserved_pe_idx, 4007262af557SGuo Chao phb->ioda.m32_size, phb->ioda.m32_segsize); 4008262af557SGuo Chao if (phb->ioda.m64_size) 4009262af557SGuo Chao pr_info(" M64: 0x%lx [segment=0x%lx]\n", 4010262af557SGuo Chao phb->ioda.m64_size, phb->ioda.m64_segsize); 4011262af557SGuo Chao if (phb->ioda.io_size) 4012262af557SGuo Chao pr_info(" IO: 0x%x [segment=0x%x]\n", 4013184cd4a3SBenjamin Herrenschmidt phb->ioda.io_size, phb->ioda.io_segsize); 4014184cd4a3SBenjamin Herrenschmidt 4015262af557SGuo Chao 4016184cd4a3SBenjamin Herrenschmidt phb->hose->ops = &pnv_pci_ops; 401749dec922SGavin Shan phb->get_pe_state = pnv_ioda_get_pe_state; 401849dec922SGavin Shan phb->freeze_pe = pnv_ioda_freeze_pe; 401949dec922SGavin Shan phb->unfreeze_pe = pnv_ioda_unfreeze_pe; 4020184cd4a3SBenjamin Herrenschmidt 4021184cd4a3SBenjamin Herrenschmidt /* Setup MSI support */ 4022184cd4a3SBenjamin Herrenschmidt pnv_pci_init_ioda_msis(phb); 4023184cd4a3SBenjamin Herrenschmidt 4024c40a4210SGavin Shan /* 4025c40a4210SGavin Shan * We pass the PCI probe flag PCI_REASSIGN_ALL_RSRC here 4026c40a4210SGavin Shan * to let the PCI core do resource assignment. It's supposed 4027c40a4210SGavin Shan * that the PCI core will do correct I/O and MMIO alignment 4028c40a4210SGavin Shan * for the P2P bridge bars so that each PCI bus (excluding 4029c40a4210SGavin Shan * the child P2P bridges) can form individual PE. 4030184cd4a3SBenjamin Herrenschmidt */ 4031fb446ad0SGavin Shan ppc_md.pcibios_fixup = pnv_pci_ioda_fixup; 40325d2aa710SAlistair Popple 40337f2c39e9SFrederic Barrat switch (phb->type) { 40347f2c39e9SFrederic Barrat case PNV_PHB_NPU_NVLINK: 40355d2aa710SAlistair Popple hose->controller_ops = pnv_npu_ioda_controller_ops; 40367f2c39e9SFrederic Barrat break; 40377f2c39e9SFrederic Barrat case PNV_PHB_NPU_OCAPI: 40387f2c39e9SFrederic Barrat hose->controller_ops = pnv_npu_ocapi_ioda_controller_ops; 40397f2c39e9SFrederic Barrat break; 40407f2c39e9SFrederic Barrat default: 4041f9f83456SAlexey Kardashevskiy phb->dma_dev_setup = pnv_pci_ioda_dma_dev_setup; 404292ae0353SDaniel Axtens hose->controller_ops = pnv_pci_ioda_controller_ops; 4043f9f83456SAlexey Kardashevskiy } 4044ad30cb99SMichael Ellerman 404538274637SYongji Xie ppc_md.pcibios_default_alignment = pnv_pci_default_alignment; 404638274637SYongji Xie 40476e628c7dSWei Yang #ifdef CONFIG_PCI_IOV 40486e628c7dSWei Yang ppc_md.pcibios_fixup_sriov = pnv_pci_ioda_fixup_iov_resources; 40495350ab3fSWei Yang ppc_md.pcibios_iov_resource_alignment = pnv_pci_iov_resource_alignment; 4050988fc3baSBryant G. Ly ppc_md.pcibios_sriov_enable = pnv_pcibios_sriov_enable; 4051988fc3baSBryant G. Ly ppc_md.pcibios_sriov_disable = pnv_pcibios_sriov_disable; 4052ad30cb99SMichael Ellerman #endif 4053ad30cb99SMichael Ellerman 4054c40a4210SGavin Shan pci_add_flags(PCI_REASSIGN_ALL_RSRC); 4055184cd4a3SBenjamin Herrenschmidt 4056184cd4a3SBenjamin Herrenschmidt /* Reset IODA tables to a clean state */ 4057d1a85eeeSGavin Shan rc = opal_pci_reset(phb_id, OPAL_RESET_PCI_IODA_TABLE, OPAL_ASSERT_RESET); 4058184cd4a3SBenjamin Herrenschmidt if (rc) 4059f2c2cbccSJoe Perches pr_warn(" OPAL Error %ld performing IODA table reset !\n", rc); 4060361f2a2aSGavin Shan 40616060e9eaSAndrew Donnellan /* 40626060e9eaSAndrew Donnellan * If we're running in kdump kernel, the previous kernel never 4063361f2a2aSGavin Shan * shutdown PCI devices correctly. We already got IODA table 4064361f2a2aSGavin Shan * cleaned out. So we have to issue PHB reset to stop all PCI 406545baee14SGuilherme G. Piccoli * transactions from previous kernel. The ppc_pci_reset_phbs 406645baee14SGuilherme G. Piccoli * kernel parameter will force this reset too. 4067361f2a2aSGavin Shan */ 406845baee14SGuilherme G. Piccoli if (is_kdump_kernel() || pci_reset_phbs) { 4069361f2a2aSGavin Shan pr_info(" Issue PHB reset ...\n"); 4070cadf364dSGavin Shan pnv_eeh_phb_reset(hose, EEH_RESET_FUNDAMENTAL); 4071cadf364dSGavin Shan pnv_eeh_phb_reset(hose, EEH_RESET_DEACTIVATE); 4072361f2a2aSGavin Shan } 4073262af557SGuo Chao 40749e9e8935SGavin Shan /* Remove M64 resource if we can't configure it successfully */ 40759e9e8935SGavin Shan if (!phb->init_m64 || phb->init_m64(phb)) 4076262af557SGuo Chao hose->mem_resources[1].flags = 0; 4077184cd4a3SBenjamin Herrenschmidt } 4078184cd4a3SBenjamin Herrenschmidt 407967975005SBjorn Helgaas void __init pnv_pci_init_ioda2_phb(struct device_node *np) 4080aa0c033fSGavin Shan { 4081e9cc17d4SGavin Shan pnv_pci_init_ioda_phb(np, 0, PNV_PHB_IODA2); 4082aa0c033fSGavin Shan } 4083aa0c033fSGavin Shan 40845d2aa710SAlistair Popple void __init pnv_pci_init_npu_phb(struct device_node *np) 40855d2aa710SAlistair Popple { 40867f2c39e9SFrederic Barrat pnv_pci_init_ioda_phb(np, 0, PNV_PHB_NPU_NVLINK); 40877f2c39e9SFrederic Barrat } 40887f2c39e9SFrederic Barrat 40897f2c39e9SFrederic Barrat void __init pnv_pci_init_npu2_opencapi_phb(struct device_node *np) 40907f2c39e9SFrederic Barrat { 40917f2c39e9SFrederic Barrat pnv_pci_init_ioda_phb(np, 0, PNV_PHB_NPU_OCAPI); 40925d2aa710SAlistair Popple } 40935d2aa710SAlistair Popple 4094184cd4a3SBenjamin Herrenschmidt void __init pnv_pci_init_ioda_hub(struct device_node *np) 4095184cd4a3SBenjamin Herrenschmidt { 4096184cd4a3SBenjamin Herrenschmidt struct device_node *phbn; 4097c681b93cSAlistair Popple const __be64 *prop64; 4098184cd4a3SBenjamin Herrenschmidt u64 hub_id; 4099184cd4a3SBenjamin Herrenschmidt 4100b7c670d6SRob Herring pr_info("Probing IODA IO-Hub %pOF\n", np); 4101184cd4a3SBenjamin Herrenschmidt 4102184cd4a3SBenjamin Herrenschmidt prop64 = of_get_property(np, "ibm,opal-hubid", NULL); 4103184cd4a3SBenjamin Herrenschmidt if (!prop64) { 4104184cd4a3SBenjamin Herrenschmidt pr_err(" Missing \"ibm,opal-hubid\" property !\n"); 4105184cd4a3SBenjamin Herrenschmidt return; 4106184cd4a3SBenjamin Herrenschmidt } 4107184cd4a3SBenjamin Herrenschmidt hub_id = be64_to_cpup(prop64); 4108184cd4a3SBenjamin Herrenschmidt pr_devel(" HUB-ID : 0x%016llx\n", hub_id); 4109184cd4a3SBenjamin Herrenschmidt 4110184cd4a3SBenjamin Herrenschmidt /* Count child PHBs */ 4111184cd4a3SBenjamin Herrenschmidt for_each_child_of_node(np, phbn) { 4112184cd4a3SBenjamin Herrenschmidt /* Look for IODA1 PHBs */ 4113184cd4a3SBenjamin Herrenschmidt if (of_device_is_compatible(phbn, "ibm,ioda-phb")) 4114e9cc17d4SGavin Shan pnv_pci_init_ioda_phb(phbn, hub_id, PNV_PHB_IODA1); 4115184cd4a3SBenjamin Herrenschmidt } 4116184cd4a3SBenjamin Herrenschmidt } 4117